Intel® 64 And IA 32 Architectures Software Developer’s Manual, Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C 3D ASM Bible Developer Manual
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Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Combined Volumes:
1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
NOTE: This document contains all three volumes of the Intel 64 and IA-32 Architectures Software
Developer's Manual: Basic Architecture, Order Number 253665; Instruction Set Reference A-Z, Order
Number 325383; System Programming Guide, Order Number 325384. Refer to all three volumes
when evaluating your design needs
Order Number: 325462-060US
September 2016
Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn
more at intel.com, or from the OEM or retailer.
No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting
from such losses.
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products
described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject
matter disclosed herein.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
This document contains information on products, services and/or processes in development. All information provided here is subject to change
without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1800-548-4725, or by visiting http://www.intel.com/design/literature.htm.
Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S.
and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 1997-2016, Intel Corporation. All Rights Reserved.
Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 1:
Basic Architecture
NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of nine volumes:
Basic Architecture, Order Number 253665; Instruction Set Reference A-L, Order Number 253666;
Instruction Set Reference M-U, Order Number 253667; Instruction Set Reference V-Z, Order Number
326018; Instruction Set Reference, Order Number 334569; System Programming Guide, Part 1, Order
Number 253668; System Programming Guide, Part 2, Order Number 253669; System Programming
Guide, Part 3, Order Number 326019; System Programming Guide, Part 4, Order Number 332831. Refer
to all nine volumes when evaluating your design needs.
Order Number: 253665-060US
September 2016
Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn
more at intel.com, or from the OEM or retailer.
No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting
from such losses.
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products
described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject
matter disclosed herein.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
This document contains information on products, services and/or processes in development. All information provided here is subject to change
without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1800-548-4725, or by visiting http://www.intel.com/design/literature.htm.
Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S.
and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 1997-2016, Intel Corporation. All Rights Reserved.
CONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3
NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.1
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.2
Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.2.1
Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.3
Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.4
Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.5
A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.3.6
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.4
RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
CHAPTER 2
INTEL® 64 AND IA-32 ARCHITECTURES
2.1
BRIEF HISTORY OF INTEL® 64 AND IA-32 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
16-bit Processors and Segmentation (1978) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.2
The Intel® 286 Processor (1982) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.3
The Intel386™ Processor (1985) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.4
The Intel486™ Processor (1989) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.1.5
The Intel® Pentium® Processor (1993). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.1.6
The P6 Family of Processors (1995-1999) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.1.7
The Intel® Pentium® 4 Processor Family (2000-2006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.8
The Intel® Xeon® Processor (2001- 2007) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.9
The Intel® Pentium® M Processor (2003-2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.10
The Intel® Pentium® Processor Extreme Edition (2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.1.11
The Intel® Core™ Duo and Intel® Core™ Solo Processors (2006-2007) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.1.12
The Intel® Xeon® Processor 5100, 5300 Series and Intel® Core™2 Processor Family (2006) . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.1.13
The Intel® Xeon® Processor 5200, 5400, 7400 Series and Intel® Core™2 Processor Family (2007) . . . . . . . . . . . . . . . . . .2-5
2.1.14
The Intel® Atom™ Processor Family (2008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.1.15
The Intel® Atom™ Processor Family Based on Silvermont Microarchitecture (2013) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.1.16
The Intel® Core™i7 Processor Family (2008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.1.17
The Intel® Xeon® Processor 7500 Series (2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.18
2010 Intel® Core™ Processor Family (2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.19
The Intel® Xeon® Processor 5600 Series (2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.20
The Second Generation Intel® Core™ Processor Family (2011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.21
The Third Generation Intel® Core™ Processor Family (2012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
2.1.22
The Fourth Generation Intel® Core™ Processor Family (2013) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
2.2
MORE ON SPECIFIC ADVANCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1
P6 Family Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
2.2.2
Intel NetBurst® Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.2.1
The Front End Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.2.2
Out-Of-Order Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.2.3
Retirement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.3
Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.3.1
The Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.3.2
Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.2.4
Intel® Atom™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.2.5
Intel® Microarchitecture Code Name Nehalem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.2.6
Intel® Microarchitecture Code Name Sandy Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.2.7
SIMD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.2.8
Intel® Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Vol. 1 iii
CONTENTS
PAGE
2.2.8.1
2.2.9
2.2.10
2.2.11
2.3
Some Implementation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Core Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Virtualization Technology (Intel® VT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® 64 AND IA-32 PROCESSOR GENERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-18
2-19
2-21
2-21
2-21
CHAPTER 3
BASIC EXECUTION ENVIRONMENT
3.1
MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1
Intel® 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.2
OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.1
64-Bit Mode Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.3
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3.1
IA-32 Memory Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3.2
Paging and Virtual Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.3.3
Memory Organization in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.3.4
Modes of Operation vs. Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.3.5
32-Bit and 16-Bit Address and Operand Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.3.6
Extended Physical Addressing in Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.3.7
Address Calculations in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.3.7.1
Canonical Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4
BASIC PROGRAM EXECUTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.1
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.1.1
General-Purpose Registers in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.2
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.4.2.1
Segment Registers in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.3
EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.3.1
Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4.3.2
DF Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4.3.3
System Flags and IOPL Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4.3.4
RFLAGS Register in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.5
INSTRUCTION POINTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.5.1
Instruction Pointer in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.6
OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.6.1
Operand Size and Address Size in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.7
OPERAND ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.7.1
Immediate Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.7.2
Register Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.7.2.1
Register Operands in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.3
Memory Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.3.1
Memory Operands in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.4
Specifying a Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.4.1
Segmentation in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.7.5
Specifying an Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.7.5.1
Specifying an Offset in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.7.6
Assembler and Compiler Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.7.7
I/O Port Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
CHAPTER 4
DATA TYPES
4.1
FUNDAMENTAL DATA TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1
Alignment of Words, Doublewords, Quadwords, and Double Quadwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.2
NUMERIC DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.1
Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2.1.1
Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2.1.2
Signed Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.2.2
Floating-Point Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3
POINTER DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.1
Pointer Data Types in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
iv Vol. 1
CONTENTS
PAGE
4.4
4.5
4.6
4.6.1
4.6.2
4.7
4.8
4.8.1
4.8.2
4.8.2.1
4.8.2.2
4.8.3
4.8.3.1
4.8.3.2
4.8.3.3
4.8.3.4
4.8.3.5
4.8.3.6
4.8.3.7
4.8.3.8
4.8.4
4.8.4.1
4.8.4.2
4.9
4.9.1
4.9.1.1
4.9.1.2
4.9.1.3
4.9.1.4
4.9.1.5
4.9.1.6
4.9.2
4.9.3
BIT FIELD DATA TYPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
STRING DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
PACKED SIMD DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
64-Bit SIMD Packed Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
128-Bit Packed SIMD Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
BCD AND PACKED BCD INTEGERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
REAL NUMBERS AND FLOATING-POINT FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Real Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Normalized Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Biased Exponent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Real Number and Non-number Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Signed Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Normalized and Denormalized Finite Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Signed Infinities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
NaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Operating on SNaNs and QNaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Using SNaNs and QNaNs in Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
QNaN Floating-Point Indefinite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Half-Precision Floating-Point Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Rounding Control (RC) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Truncation with SSE and SSE2 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
OVERVIEW OF FLOATING-POINT EXCEPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Floating-Point Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Invalid Operation Exception (#I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Denormal Operand Exception (#D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Divide-By-Zero Exception (#Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Inexact-Result (Precision) Exception (#P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Floating-Point Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Typical Actions of a Floating-Point Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
CHAPTER 5
INSTRUCTION SET SUMMARY
5.1
GENERAL-PURPOSE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.1
Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.2
Binary Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.3
Decimal Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.4
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.5
Shift and Rotate Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.6
Bit and Byte Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.1.7
Control Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.1.8
String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.1.9
I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.10
Enter and Leave Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.11
Flag Control (EFLAG) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.12
Segment Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.13
Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.1.14
User Mode Extended Sate Save/Restore Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.1.15
Random Number Generator Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.1.16
BMI1, BMI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.1.16.1
Detection of VEX-encoded GPR Instructions, LZCNT and TZCNT, PREFETCHW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.2
X87 FPU INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.2.1
x87 FPU Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.2.2
x87 FPU Basic Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.2.3
x87 FPU Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.2.4
x87 FPU Transcendental Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Vol. 1 v
CONTENTS
PAGE
5.2.5
5.2.6
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.1.5
5.5.1.6
5.5.2
5.5.3
5.5.4
5.6
5.6.1
5.6.1.1
5.6.1.2
5.6.1.3
5.6.1.4
5.6.1.5
5.6.1.6
5.6.2
5.6.3
5.6.4
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.8.6
5.8.7
5.9
5.10
5.10.1
5.10.2
5.10.3
5.10.4
5.10.5
5.10.6
5.10.7
5.10.8
5.10.9
vi Vol. 1
x87 FPU Load Constants Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x87 FPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX™ INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX Packed Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX State Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE SIMD Single-Precision Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE Packed Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE Shuffle and Unpack Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE MXCSR State Management Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE 64-Bit SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Packed and Scalar Double-Precision Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Packed Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Logical Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Compare Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Shuffle and Unpack Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Packed Single-Precision Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 128-Bit SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE2 Cacheability Control and Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE3 x87-FP Integer Conversion Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE3 Specialized 128-bit Unaligned Data Load Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE3 SIMD Floating-Point Packed ADD/SUB Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE3 Agent Synchronization Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SUPPLEMENTAL STREAMING SIMD EXTENSIONS 3 (SSSE3) INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Horizontal Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Absolute Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply and Add Packed Signed and Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Multiply High with Round and Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE4 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE4.1 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dword Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-Point Dot Product Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Streaming Load Hint Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Blending Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Integer MIN/MAX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-Point Round Instructions with Selectable Rounding Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Insertion and Extractions from XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Integer Format Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11
5-11
5-12
5-12
5-12
5-12
5-13
5-13
5-13
5-13
5-14
5-14
5-14
5-14
5-15
5-15
5-15
5-15
5-16
5-16
5-16
5-16
5-17
5-17
5-17
5-18
5-18
5-18
5-18
5-19
5-19
5-19
5-20
5-20
5-20
5-20
5-21
5-21
5-21
5-21
5-21
5-22
5-22
5-22
5-22
5-23
5-23
5-23
5-23
5-24
5-24
5-24
5-24
5-24
5-24
5-25
5-25
5-25
5-26
CONTENTS
PAGE
5.10.10
5.10.11
5.10.12
5.10.13
5.11
5.11.1
5.11.2
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
Horizontal Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Qword Equality Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dword Packing With Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE4.2 INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
String and Text Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packed Comparison SIMD integer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AESNI AND PCLMULQDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-BIT FLOATING-POINT CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FUSED-MULTIPLY-ADD (FMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® ADVANCED VECTOR EXTENSIONS 2 (INTEL® AVX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS (INTEL® TSX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® SHA EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® ADVANCED VECTOR EXTENSIONS 512 (INTEL® AVX-512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-BIT MODE INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIRTUAL-MACHINE EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAFER MODE EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® MEMORY PROTECTION EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® SECURITY GUARD EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26
5-26
5-26
5-26
5-26
5-26
5-27
5-27
5-27
5-27
5-28
5-28
5-28
5-28
5-28
5-32
5-33
5-34
5-34
5-35
5-35
CHAPTER 6
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6.1
PROCEDURE CALL TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2
STACKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.1
Setting Up a Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2
Stack Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.3
Address-Size Attributes for Stack Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4
Procedure Linking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4.1
Stack-Frame Base Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4.2
Return Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.5
Stack Behavior in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3
CALLING PROCEDURES USING CALL AND RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3.1
Near CALL and RET Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3.2
Far CALL and RET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3.3
Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3.3.1
Passing Parameters Through the General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3.3.2
Passing Parameters on the Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3.3.3
Passing Parameters in an Argument List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.3.4
Saving Procedure State Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.3.5
Calls to Other Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.3.6
CALL and RET Operation Between Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.3.7
Branch Functions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4
INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4.1
Call and Return Operation for Interrupt or Exception Handling Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.4.2
Calls to Interrupt or Exception Handler Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.4.3
Interrupt and Exception Handling in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.4.4
INT n, INTO, INT 3, and BOUND Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.4.5
Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.4.6
Interrupt and Exception Behavior in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.5
PROCEDURE CALLS FOR BLOCK-STRUCTURED LANGUAGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.5.1
ENTER Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.5.2
LEAVE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
CHAPTER 7
PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7.1
PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2
PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS IN 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Vol. 1 vii
CONTENTS
PAGE
7.3
SUMMARY OF GP INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3.1
Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2
7.3.1.1
General Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.3.1.2
Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.3.1.3
Exchange Instructions in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
7.3.1.4
Stack Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
7.3.1.5
Stack Manipulation Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
7.3.1.6
Type Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
7.3.1.7
Type Conversion Instructions in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2
Binary Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.1
Addition and Subtraction Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.2
Increment and Decrement Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.3
Increment and Decrement Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.4
Comparison and Sign Change Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.5
Multiplication and Division Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.3
Decimal Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.3.1
Packed BCD Adjustment Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.3.2
Unpacked BCD Adjustment Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.4
Decimal Arithmetic Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.5
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.6
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.6.1
Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.6.2
Double-Shift Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.3.6.3
Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.3.7
Bit and Byte Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.3.7.1
Bit Test and Modify Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.7.2
Bit Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.7.3
Byte Set on Condition Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.7.4
Test Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.8
Control Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.8.1
Unconditional Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.8.2
Conditional Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.3.8.3
Control Transfer Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.3.8.4
Software Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.3.8.5
Software Interrupt Instructions in 64-bit Mode and Compatibility Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.3.9
String Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.3.9.1
String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.3.9.2
Repeated String Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.3.9.3
Fast-String Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.3.9.4
String Operations in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.3.10
I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.3.11
I/O Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.3.12
Enter and Leave Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13
Flag Control (EFLAG) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13.1
Carry and Direction Flag Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13.2
EFLAGS Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13.3
Interrupt Flag Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.14
Flag Control (RFLAG) Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.15
Segment Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.15.1
Segment-Register Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.15.2
Far Control Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.15.3
Software Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.15.4
Load Far Pointer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16
Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.1
Address Computation Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.2
Table Lookup Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.3
Processor Identification Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.4
No-Operation and Undefined Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.17
Random Number Generator Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
viii Vol. 1
CONTENTS
PAGE
7.3.17.1
7.3.17.2
RDRAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
RDSEED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
CHAPTER 8
PROGRAMMING WITH THE X87 FPU
8.1
X87 FPU EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1
x87 FPU in 64-Bit Mode and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2
x87 FPU Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2.1
Parameter Passing With the x87 FPU Register Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.3
x87 FPU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.3.1
Top of Stack (TOP) Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.3.2
Condition Code Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.3.3
x87 FPU Floating-Point Exception Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.3.4
Stack Fault Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.4
Branching and Conditional Moves on Condition Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.5
x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.5.1
x87 FPU Floating-Point Exception Mask Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.5.2
Precision Control Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.5.3
Rounding Control Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.6
Infinity Control Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.7
x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.8
x87 FPU Instruction and Data (Operand) Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.1.9
Last Instruction Opcode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.1.9.1
Fopcode Compatibility Sub-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.1.10
Saving the x87 FPU’s State with FSTENV/FNSTENV and FSAVE/FNSAVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.1.11
Saving the x87 FPU’s State with FXSAVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.2
X87 FPU DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.2.1
Indefinites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.2.2
Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.3
X87 FPU INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.3.1
Escape (ESC) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.3.2
x87 FPU Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.3.3
Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.3.4
Load Constant Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.3.5
Basic Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.3.6
Comparison and Classification Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.3.6.1
Branching on the x87 FPU Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.3.7
Trigonometric Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.3.8
Approximation of Pi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.3.9
Logarithmic, Exponential, and Scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.3.10
Transcendental Instruction Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.3.11
x87 FPU Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.3.12
Waiting vs. Non-waiting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.3.13
Unsupported x87 FPU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.4
X87 FPU FLOATING-POINT EXCEPTION HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.4.1
Arithmetic vs. Non-arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.5
X87 FPU FLOATING-POINT EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
8.5.1
Invalid Operation Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8.5.1.1
Stack Overflow or Underflow Exception (#IS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8.5.1.2
Invalid Arithmetic Operand Exception (#IA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8.5.2
Denormal Operand Exception (#D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.5.3
Divide-By-Zero Exception (#Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
8.5.4
Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
8.5.5
Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
8.5.6
Inexact-Result (Precision) Exception (#P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
8.6
X87 FPU EXCEPTION SYNCHRONIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
8.7
HANDLING X87 FPU EXCEPTIONS IN SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
8.7.1
Native Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
8.7.2
MS-DOS* Compatibility Sub-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
Vol. 1 ix
CONTENTS
PAGE
8.7.3
Handling x87 FPU Exceptions in Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
CHAPTER 9
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
9.1
OVERVIEW OF MMX TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2
THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.1
MMX Technology in 64-Bit Mode and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
9.2.2
MMX Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
9.2.3
MMX Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.2.4
Memory Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.2.5
Single Instruction, Multiple Data (SIMD) Execution Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
9.3
SATURATION AND WRAPAROUND MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.4
MMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.4.1
Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.4.2
Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.4.3
Comparison Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.4
Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.5
Unpack Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.6
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.7
Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.4.8
EMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.5
COMPATIBILITY WITH X87 FPU ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.5.1
MMX Instructions and the x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.6
WRITING APPLICATIONS WITH MMX CODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.6.1
Checking for MMX Technology Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.6.2
Transitions Between x87 FPU and MMX Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
9.6.3
Using the EMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
9.6.4
Mixing MMX and x87 FPU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.6.5
Interfacing with MMX Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.6.6
Using MMX Code in a Multitasking Operating System Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.6.7
Exception Handling in MMX Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6.8
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6.9
Effect of Instruction Prefixes on MMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
CHAPTER 10
PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
10.1
OVERVIEW OF SSE EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2
SSE PROGRAMMING ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2.1
SSE in 64-Bit Mode and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.2
XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.3
MXCSR Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.3.1
SIMD Floating-Point Mask and Flag Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3.2
SIMD Floating-Point Rounding Control Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3.3
Flush-To-Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3.4
Denormals-Are-Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.4
Compatibility of SSE Extensions with SSE2/SSE3/MMX and the x87 FPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3
SSE DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.4
SSE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.1
SSE Packed and Scalar Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.1.1
SSE Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4.1.2
SSE Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.2
SSE Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.2.1
SSE Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.2.2
SSE Shuffle and Unpack Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.3
SSE Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.4
SSE 64-Bit SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.5
MXCSR State Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6
Cacheability Control, Prefetch, and Memory Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6.1
Cacheability Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
x Vol. 1
CONTENTS
PAGE
10.4.6.2
Caching of Temporal vs. Non-Temporal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6.3
PREFETCHh Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.4.6.4
SFENCE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5
FXSAVE AND FXRSTOR INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5.1
FXSAVE Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5.1.1
x87 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5.1.2
SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.2
Operation of FXSAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.3
Operation of FXRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.6
HANDLING SSE INSTRUCTION EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.7
WRITING APPLICATIONS WITH THE SSE EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
CHAPTER 11
PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
11.1
OVERVIEW OF SSE2 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2
SSE2 PROGRAMMING ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1
SSE2 in 64-Bit Mode and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.2
Compatibility of SSE2 Extensions with SSE, MMX Technology and x87 FPU Programming Environment . . . . . . . . . . . . 11-3
11.2.3
Denormals-Are-Zeros Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3
SSE2 DATA TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4
SSE2 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.4.1
Packed and Scalar Double-Precision Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.4.1.1
Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.4.1.2
SSE2 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.1.3
SSE2 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.1.4
SSE2 Comparison Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.1.5
SSE2 Shuffle and Unpack Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.1.6
SSE2 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.4.2
SSE2 64-Bit and 128-Bit SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.4.3
128-Bit SIMD Integer Instruction Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.4.4
Cacheability Control and Memory Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.1
FLUSH Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.2
Cacheability Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.3
Memory Ordering Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.4
Pause. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.5
Branch Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.5
SSE, SSE2, AND SSE3 EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.5.1
SIMD Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.5.2
SIMD Floating-Point Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.5.2.1
Invalid Operation Exception (#I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.5.2.2
Denormal-Operand Exception (#D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.5.2.3
Divide-By-Zero Exception (#Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.5.2.4
Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.5.2.5
Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.2.6
Inexact-Result (Precision) Exception (#P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.3
Generating SIMD Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.3.1
Handling Masked Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.3.2
Handling Unmasked Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.5.3.3
Handling Combinations of Masked and Unmasked Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.5.4
Handling SIMD Floating-Point Exceptions in Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.5.5
Interaction of SIMD and x87 FPU Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.6
WRITING APPLICATIONS WITH SSE/SSE2 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.6.1
General Guidelines for Using SSE/SSE2 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.6.2
Checking for SSE/SSE2 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.6.3
Checking for the DAZ Flag in the MXCSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.6.4
Initialization of SSE/SSE2 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.6.5
Saving and Restoring the SSE/SSE2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.6.6
Guidelines for Writing to the MXCSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
11.6.7
Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Vol. 1 xi
CONTENTS
PAGE
11.6.8
11.6.9
11.6.10
11.6.10.1
11.6.10.2
11.6.10.3
11.6.11
11.6.12
11.6.13
11.6.14
Compatibility of SIMD and x87 FPU Floating-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
Mixing Packed and Scalar Floating-Point and 128-Bit SIMD Integer Instructions and Data . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
Interfacing with SSE/SSE2 Procedures and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Passing Parameters in XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Saving XMM Register State on a Procedure or Function Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Caller-Save Recommendation for Procedure and Function Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
Updating Existing MMX Technology Routines Using 128-Bit SIMD Integer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
Branching on Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
Cacheability Hint Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
Effect of Instruction Prefixes on the SSE/SSE2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
CHAPTER 12
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
12.1
PROGRAMMING ENVIRONMENT AND DATA TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1
SSE3, SSSE3, SSE4 in 64-Bit Mode and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.2
Compatibility of SSE3/SSSE3 with MMX Technology, the x87 FPU Environment, and SSE/SSE2 Extensions . . . . . . . . . 12-1
12.1.3
Horizontal and Asymmetric Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2
OVERVIEW OF SSE3 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3
SSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3.1
x87 FPU Instruction for Integer Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.2
SIMD Integer Instruction for Specialized 128-bit Unaligned Data Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.3
SIMD Floating-Point Instructions That Enhance LOAD/MOVE/DUPLICATE Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.4
SIMD Floating-Point Instructions Provide Packed Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.3.5
SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.3.6
Two Thread Synchronization Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4
WRITING APPLICATIONS WITH SSE3 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.1
Guidelines for Using SSE3 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.2
Checking for SSE3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.3
Enable FTZ and DAZ for SIMD Floating-Point Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.4.4
Programming SSE3 with SSE/SSE2 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5
OVERVIEW OF SSSE3 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.6
SSSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.6.1
Horizontal Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.6.2
Packed Absolute Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.6.3
Multiply and Add Packed Signed and Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.4
Packed Multiply High with Round and Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.5
Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.6
Packed Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.7
Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.7
WRITING APPLICATIONS WITH SSSE3 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.7.1
Guidelines for Using SSSE3 Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.7.2
Checking for SSSE3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8
SSE3/SSSE3 AND SSE4 EXCEPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8.1
Device Not Available (DNA) Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8.2
Numeric Error flag and IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8.3
Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.8.4
IEEE 754 Compliance of SSE4.1 Floating-Point Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.9
SSE4 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.10 SSE4.1 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.10.1
Dword Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.10.2
Floating-Point Dot Product Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.10.3
Streaming Load Hint Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.10.4
Packed Blending Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.10.5
Packed Integer MIN/MAX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.10.6
Floating-Point Round Instructions with Selectable Rounding Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.10.7
Insertion and Extractions from XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.10.8
Packed Integer Format Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.10.9
Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
12.10.10 Horizontal Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
xii Vol. 1
CONTENTS
PAGE
12.10.11 Packed Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.10.12 Packed Qword Equality Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.10.13 Dword Packing With Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.11 SSE4.2 INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.11.1
String and Text Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.11.1.1
Memory Operand Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.11.2
Packed Comparison SIMD Integer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.12 WRITING APPLICATIONS WITH SSE4 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.12.1
Guidelines for Using SSE4 Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.12.2
Checking for SSE4.1 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.12.3
Checking for SSE4.2 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.13 AESNI OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.13.1
Little-Endian Architecture and Big-Endian Specification (FIPS 197) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.13.1.1
AES Data Structure in Intel 64 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.13.2
AES Transformations and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12.13.3
PCLMULQDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12.13.4
Checking for AESNI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
CHAPTER 13
MANAGING STATE USING THE XSAVE FEATURE SET
13.1
XSAVE-SUPPORTED FEATURES AND STATE-COMPONENT BITMAPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2
ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVE-SUPPORTED FEATURES . . . . . . . . . . . . . . . . . . 13-2
13.3
ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4
XSAVE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.4.1
Legacy Region of an XSAVE Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.4.2
XSAVE Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.4.3
Extended Region of an XSAVE Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.5
XSAVE-MANAGED STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.5.1
x87 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.5.2
SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.5.3
AVX State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.5.4
MPX State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.5.5
AVX-512 State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.5.6
PT State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.5.7
PKRU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.6
PROCESSOR TRACKING OF XSAVE-MANAGED STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.7
OPERATION OF XSAVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.8
OPERATION OF XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.8.1
Standard Form of XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.8.2
Compacted Form of XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.8.3
XRSTOR and the Init and Modified Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.9
OPERATION OF XSAVEOPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.10 OPERATION OF XSAVEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.11 OPERATION OF XSAVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.12 OPERATION OF XRSTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
13.13 MEMORY ACCESSES BY THE XSAVE FEATURE SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
CHAPTER 14
PROGRAMMING WITH AVX, FMA AND AVX2
14.1
INTEL AVX OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.1
256-Bit Wide SIMD Register Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.2
Instruction Syntax Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.3
VEX Prefix Instruction Encoding Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2
FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.2.1
256-bit Floating-Point Arithmetic Processing Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.2
256-bit Non-Arithmetic Instruction Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.3
Arithmetic Primitives for 128-bit Vector and Scalar processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.2.4
Non-Arithmetic Primitives for 128-bit Vector and Scalar Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.3
DETECTION OF AVX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Vol. 1 xiii
CONTENTS
PAGE
14.3.1
14.4
14.4.1
14.5
14.5.1
14.5.2
14.5.3
14.6
14.6.1
14.7
14.7.1
14.8
14.9
14.10
14.11
14.12
14.13
Detection of VEX-Encoded AES and VPCLMULQDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
HALF-PRECISION FLOATING-POINT CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Detection of F16C Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20
FUSED-MULTIPLY-ADD (FMA) EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
FMA Instruction Operand Order and Arithmetic Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Fused-Multiply-ADD (FMA) Numeric Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Detection of FMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
OVERVIEW OF INTEL® ADVANCED VECTOR EXTENSIONS 2 (INTEL® AVX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
AVX2 and 256-bit Vector Integer Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
PROMOTED VECTOR INTEGER INSTRUCTIONS IN AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Detection of AVX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
ACCESSING YMM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
MEMORY ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
SIMD FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
WRITING AVX FLOATING-POINT EXCEPTION HANDLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
GENERAL PURPOSE INSTRUCTION SET ENHANCEMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
CHAPTER 15
PROGRAMMING WITH INTEL® AVX-512
15.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.1
512-Bit Wide SIMD Register Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.2
32 SIMD Register Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.3
Eight Opmask Register Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.4
Instruction Syntax Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.5
EVEX Instruction Encoding Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.2
DETECTION OF AVX-512 FOUNDATION INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.2.1
Additional 512-bit Instruction Extensions of the Intel AVX-512 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3
DETECTION OF 512-BIT INSTRUCTION GROUPS OF INTEL® AVX-512 FAMILY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.4
DETECTION OF INTEL AVX-512 INSTRUCTION GROUPS OPERATING AT 256 AND 128-BIT VECTOR LENGTHS . . . . . . . . . 15-6
15.5
ACCESSING XMM, YMM AND ZMM REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.6
ENHANCED VECTOR PROGRAMMING ENVIRONMENT USING EVEX ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.6.1
OPMASK Register to Predicate Vector Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.6.1.1
Opmask Register K0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.6.1.2
Example of Opmask Usages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.6.2
OpMask Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.6.3
Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.6.4
STATIC ROUNDING MODE AND SUPPRESS ALL EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.6.5
Compressed Disp8*N Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.7
MEMORY ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.8
SIMD FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.9
INSTRUCTION EXCEPTION SPECIFICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.10 EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.11 WRITING FLOATING-POINT EXCEPTION HANDLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
CHAPTER 16
PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS
16.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2
INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2.1
HLE Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2.2
RTM Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3
INTEL® TSX APPLICATION PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.1
Detection of Transactional Synchronization Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.1.1
Detection of HLE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.1.2
Detection of RTM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.1.3
Detection of XTEST Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.2
Querying Transactional Execution Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.3
Requirements for HLE Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.4
Transactional Nesting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiv Vol. 1
16-1
16-1
16-2
16-3
16-3
16-3
16-3
16-3
16-3
16-4
16-4
16-4
CONTENTS
PAGE
16.3.4.1
16.3.4.2
16.3.4.3
16.3.5
16.3.6
16.3.7
16.3.8
16.3.8.1
16.3.8.2
HLE Nesting and Elision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTM Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nesting HLE and RTM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTM Abort Status Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTM Memory Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTM-Enabled Debugger Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Based Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Runtime Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-4
16-5
16-5
16-5
16-5
16-6
16-6
16-6
16-7
CHAPTER 17
INTEL® MEMORY PROTECTION EXTENSIONS
17.1
INTEL® MEMORY PROTECTION EXTENSIONS (INTEL® MPX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.2
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.3
INTEL MPX PROGRAMMING ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.3.1
Detection and Enumeration of Intel MPX Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.3.2
Bounds Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.3.3
Configuration and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.4
Read and Write of IA32_BNDCFGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4
INTEL MPX INSTRUCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4.1
Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.4.2
Usage and Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.4.3
Loading and Storing Bounds in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.4.3.1
BNDLDX and BNDSTX in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.4.3.2
BNDLDX and BNDSTX Outside 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.5
INTERACTIONS WITH INTEL MPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.5.1
Intel MPX and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.5.2
Intel MPX Support for Pointer Operations with Branching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.5.3
CALL, RET, JMP and All Jcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.5.4
BOUND Instruction and Intel MPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.5.5
Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.5.6
Intel MPX and System Manage Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.5.7
Support of Intel MPX in VMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.5.8
Support of Intel MPX in Intel TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
CHAPTER 18
INPUT/OUTPUT
18.1
I/O PORT ADDRESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2
I/O PORT HARDWARE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3
I/O ADDRESS SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1
Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4
I/O INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5
PROTECTED-MODE I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5.1
I/O Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5.2
I/O Permission Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.6
ORDERING I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-1
18-1
18-1
18-2
18-3
18-3
18-3
18-4
18-5
CHAPTER 19
PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
19.1
USING THE CPUID INSTRUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.1
Notes on Where to Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.2
Identification of Earlier IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
APPENDIX A
EFLAGS CROSS-REFERENCE
A.1
EFLAGS AND INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Vol. 1 xv
CONTENTS
PAGE
APPENDIX B
EFLAGS CONDITION CODES
B.1
CONDITION CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
APPENDIX C
FLOATING-POINT EXCEPTIONS SUMMARY
C.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2
X87 FPU INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.3
SSE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.4
SSE2 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.5
SSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.6
SSSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.7
SSE4 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-1
C-1
C-3
C-5
C-7
C-7
C-7
APPENDIX D
GUIDELINES FOR WRITING X87 FPU
EXCEPTION HANDLERS
D.1
MS-DOS COMPATIBILITY SUB-MODE FOR HANDLING X87 FPU EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
D.2
IMPLEMENTATION OF THE MS-DOS* COMPATIBILITY SUB-MODE IN THE INTEL486™, PENTIUM®, AND P6 PROCESSOR FAMILY,
AND PENTIUM® 4 PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
D.2.1
MS-DOS* Compatibility Sub-mode in the Intel486™ and Pentium® Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-2
D.2.1.1
Basic Rules: When FERR# Is Generated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-3
D.2.1.2
Recommended External Hardware to Support the MS-DOS* Compatibility Sub-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-4
D.2.1.3
No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-5
D.2.2
MS-DOS* Compatibility Sub-mode in the P6 Family and Pentium® 4 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-7
D.3
RECOMMENDED PROTOCOL FOR MS-DOS* COMPATIBILITY HANDLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
D.3.1
Floating-Point Exceptions and Their Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-8
D.3.2
Two Options for Handling Numeric Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-8
D.3.2.1
Automatic Exception Handling: Using Masked Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-8
D.3.2.2
Software Exception Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-9
D.3.3
Synchronization Required for Use of x87 FPU Exception Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10
D.3.3.1
Exception Synchronization: What, Why, and When . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10
D.3.3.2
Exception Synchronization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
D.3.3.3
Proper Exception Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
D.3.4
x87 FPU Exception Handling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12
D.3.5
Need for Storing State of IGNNE# Circuit If Using x87 FPU and SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15
D.3.6
Considerations When x87 FPU Shared Between Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15
D.3.6.1
Speculatively Deferring x87 FPU Saves, General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-16
D.3.6.2
Tracking x87 FPU Ownership. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-16
D.3.6.3
Interaction of x87 FPU State Saves and Floating-Point Exception Association . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-17
D.3.6.4
Interrupt Routing From the Kernel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-18
D.3.6.5
Special Considerations for Operating Systems that Support Streaming SIMD Extensions . . . . . . . . . . . . . . . . . . . . . . . . D-19
D.4
DIFFERENCES FOR HANDLERS USING NATIVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19
D.4.1
Origin with the Intel 286 and Intel 287, and Intel386 and Intel 387 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19
D.4.2
Changes with Intel486, Pentium and Pentium Pro Processors with CR0.NE[bit 5] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-20
D.4.3
Considerations When x87 FPU Shared Between Tasks Using Native Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-20
APPENDIX E
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
E.1
TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.2
SOFTWARE EXCEPTION HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.3
EXCEPTION SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
E.4
SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
E.4.1
Floating-Point Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
E.4.2
SSE/SSE2/SSE3 Response To Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4
E.4.2.1
Numeric Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-5
E.4.2.2
Results of Operations with NaN Operands or a NaN Result for SSE/SSE2/SSE3 Numeric Instructions . . . . . . . . . . . . . .E-5
E.4.2.3
Condition Codes, Exception Flags, and Response for Masked and Unmasked Numeric Exceptions . . . . . . . . . . . . . . . . . . E-9
E.4.3
Example SIMD Floating-Point Emulation Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-15
xvi Vol. 1
CONTENTS
PAGE
FIGURES
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 6-6.
Figure 6-7.
Figure 6-8.
Figure 6-9.
Figure 6-10.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 7-5.
Figure 7-6.
Figure 7-7.
Figure 7-8.
Figure 7-9.
Figure 7-10.
Figure 7-11.
Figure 8-1.
Figure 8-2.
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
The P6 Processor Microarchitecture with Advanced Transfer Cache Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
The Intel NetBurst Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
The Intel Core Microarchitecture Pipeline Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
SIMD Extensions, Register Layouts, and Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Comparison of an IA-32 Processor Supporting Hyper-Threading Technology and a Traditional Dual Processor
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Intel 64 and IA-32 Processors that Support Dual-Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Intel 64 Processors that Support Quad-Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Intel Core i7 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
IA-32 Basic Execution Environment for Non-64-bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
64-Bit Mode Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Three Memory Management Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
General System and Application Programming Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Alternate General-Purpose Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Use of Segment Registers for Flat Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Use of Segment Registers in Segmented Memory Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Memory Operand Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Memory Operand Address in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Offset (or Effective Address) Computation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Fundamental Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Bytes, Words, Doublewords, Quadwords, and Double Quadwords in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Numeric Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Pointer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Pointers in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Bit Field Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
64-Bit Packed SIMD Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
128-Bit Packed SIMD Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
BCD Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Binary Real Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Binary Floating-Point Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Real Numbers and NaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Stack Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Stack on Near and Far Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Protection Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Stack Switch on a Call to a Different Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Stack Usage on Transfers to Interrupt and Exception Handling Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Nested Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Stack Frame After Entering the MAIN Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Stack Frame After Entering Procedure A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Stack Frame After Entering Procedure B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Stack Frame After Entering Procedure C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Operation of the PUSH Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Operation of the PUSHA Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Operation of the POP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Operation of the POPA Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Sign Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
SHL/SAL Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
SHR Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
SAR Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
SHLD and SHRD Instruction Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
ROL, ROR, RCL, and RCR Instruction Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
x87 FPU Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
x87 FPU Data Register Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Vol. 1 xvii
CONTENTS
PAGE
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 8-7.
Figure 8-8.
Figure 8-9.
Figure 8-10.
Figure 8-11.
Figure 8-12.
Figure 8-13.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 11-6.
Figure 11-7.
Figure 11-8.
Figure 11-9.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 18-1.
Figure 18-2.
Figure D-1.
Figure D-2.
Figure D-3.
Figure D-4.
Figure D-5.
xviii Vol. 1
Example x87 FPU Dot Product Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
x87 FPU Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Moving the Condition Codes to the EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Contents of x87 FPU Opcode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Protected Mode x87 FPU State Image in Memory, 32-Bit Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Real Mode x87 FPU State Image in Memory, 32-Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Protected Mode x87 FPU State Image in Memory, 16-Bit Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Real Mode x87 FPU State Image in Memory, 16-Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
x87 FPU Data Type Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
MMX Technology Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
MMX Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Data Types Introduced with the MMX Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
SIMD Execution Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
SSE Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
MXCSR Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
128-Bit Packed Single-Precision Floating-Point Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Packed Single-Precision Floating-Point Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Scalar Single-Precision Floating-Point Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
SHUFPS Instruction, Packed Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10
UNPCKHPS Instruction, High Unpack and Interleave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10
UNPCKLPS Instruction, Low Unpack and Interleave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10
Steaming SIMD Extensions 2 Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Data Types Introduced with the SSE2 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Packed Double-Precision Floating-Point Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Scalar Double-Precision Floating-Point Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
SHUFPD Instruction, Packed Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
UNPCKHPD Instruction, High Unpack and Interleave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
UNPCKLPD Instruction, Low Unpack and Interleave Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
SSE and SSE2 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Example Masked Response for Packed Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17
Asymmetric Processing in ADDSUBPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Horizontal Data Movement in HADDPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Horizontal Data Movement in PHADDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
MPSADBW Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16
AES State Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-19
256-Bit Wide SIMD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
General Procedural Flow of Application Detection of AVX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-15
General Procedural Flow of Application Detection of Float-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-20
Immediate Byte for FMA instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-23
512-Bit Wide Vectors and SIMD Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
Procedural Flow for Application Detection of AVX-512 Foundation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Procedural Flow for Application Detection of 512-bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Procedural Flow for Application Detection of 512-bit Instruction Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
Procedural Flow for Detection of Intel AVX-512 Instructions Operating at Vector Lengths < 512 . . . . . . . . . . . . . . . 15-7
Layout of the Bounds Registers BND0-BND3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Common Layout of the Bound Configuration Registers BNDCFGU and BNDCFGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Layout of the Bound Status Registers BNDSTATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Bound Paging Structure and Address Translation in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
Bound Paging Structure and Address Translation Outside 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
I/O Permission Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Recommended Circuit for MS-DOS Compatibility x87 FPU Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4
Behavior of Signals During x87 FPU Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5
Timing of Receipt of External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6
Arithmetic Example Using Infinity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9
General Program Flow for DNA Exception Handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-17
CONTENTS
PAGE
Figure D-6.
Figure E-1.
Program Flow for a Numeric Exception Dispatch Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-18
Control Flow for Handling Unmasked Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-4
Vol. 1 xix
CONTENTS
PAGE
TABLES
Table 2-1.
Table 2-2.
Table 2-3.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
Table 4-10.
Table 4-11.
Table 4-9.
Table 5-1.
Table 5-2.
Table 5-3.
Table 6-1.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-5.
Table 8-4.
Table 8-6.
Table 8-7.
Table 8-8.
Table 8-9.
Table 8-10.
Table 8-11.
Table 9-1.
Table 9-2.
Table 9-3.
Table 10-1.
Table 10-2.
Table 11-1.
Table 11-2.
Table 11-3.
Table 12-1.
Table 12-2.
Table 12-3.
Table 12-4.
Table 12-5.
Table 12-6.
Table 12-7.
Table 12-8.
Table 12-9.
Table 12-10.
Table 12-11.
xx Vol. 1
Key Features of Most Recent IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Key Features of Most Recent Intel 64 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Key Features of Previous Generations of IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Instruction Pointer Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Addressable General Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Effective Operand- and Address-Size Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Effective Operand- and Address-Size Attributes in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Default Segment Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Signed Integer Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Length, Precision, and Range of Floating-Point Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Floating-Point Number and NaN Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Packed Decimal Integer Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Real and Floating-Point Number Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Denormalization Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Rules for Handling NaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Rounding Modes and Encoding of Rounding Control (RC) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Masked Responses to Numeric Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Numeric Underflow (Normalized) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Numeric Overflow Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Instruction Groups in Intel 64 and IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Recent Instruction Set Extensions Introduction in Intel 64 and IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Move Instruction Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
Conditional Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
Bit Test and Modify Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Conditional Jump Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Condition Code Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5
Precision Control Field (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals . . . . . . . . . . . . . . . . . . . . . 8-14
Floating-Point Conditional Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Setting of x87 FPU Condition Code Flags for Floating-Point Number Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Setting of EFLAGS Status Flags for Floating-Point Number Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
TEST Instruction Constants for Conditional Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Arithmetic and Non-arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Invalid Arithmetic Operations and the Masked Responses to Them . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Divide-By-Zero Conditions and the Masked Responses to Them . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Data Range Limits for Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
MMX Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
Effect of Prefixes on MMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
PREFETCHh Instructions Caching Hints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Format of an FXSAVE Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
SSE and SSE2 State Following a Power-up/Reset or INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Effect of Prefixes on SSE, SSE2, and SSE3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
SIMD numeric exceptions signaled by SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Enhanced 32-bit SIMD Multiply Supported by SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Blend Field Size and Control Modes Supported by SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Enhanced SIMD Integer MIN/MAX Instructions Supported by SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
New SIMD Integer conversions supported by SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
New SIMD Integer Conversions Supported by SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
Enhanced SIMD Pack support by SSE4.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
Byte and 32-bit Word Representation of a 128-bit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
Matrix Representation of a 128-bit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
Little Endian Representation of a 128-bit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
Little Endian Representation of a 4x4 Byte Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
CONTENTS
PAGE
Table 12-12.
Table 12-13.
Table 12-15.
Table 12-14.
Table 13-1.
Table 14-1.
Table 14-2.
Table 14-3.
Table 14-4.
Table 14-5.
Table 14-6.
Table 14-7.
Table 14-8.
Table 14-9.
Table 14-10.
Table 14-12.
Table 14-13.
Table 14-14.
Table 14-11.
Table 14-15.
Table 14-16.
Table 14-17.
Table 14-18.
Table 14-19.
Table 14-20.
Table 14-21.
Table 14-22.
Table 14-23.
Table 15-1.
Table 15-2.
Table 15-3.
Table 15-4.
Table 15-5.
Table 15-6.
Table 15-7.
Table 16-1.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 18-1.
Table A-1.
Table A-2.
Table B-1.
Table C-1.
Table C-2.
Table C-3.
Table C-4.
Table C-5.
Table C-6.
Table E-1.
Table E-2.
Table E-3.
Table E-4.
Table E-5.
Table E-6.
Table E-7.
Table E-8.
The ShiftRows Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
Look-up Table Associated with S-Box Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
Look-up Table Associated with InvS-Box Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
The InvShiftRows Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
Format of the Legacy Region of an XSAVE Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Promoted SSE/SSE2/SSE3/SSSE3/SSE4 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Promoted 256-Bit and 128-bit Arithmetic AVX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Promoted 256-bit and 128-bit Data Movement AVX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
256-bit AVX Instruction Enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Promotion of Legacy SIMD ISA to 128-bit Arithmetic AVX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
128-bit AVX Instruction Enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Promotion of Legacy SIMD ISA to 128-bit Non-Arithmetic AVX instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Non-Numerical Behavior for VCVTPH2PS, VCVTPS2PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Invalid Operation for VCVTPH2PS, VCVTPS2PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Underflow Condition for VCVTPS2PH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Overflow Condition for VCVTPS2PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Inexact Condition for VCVTPS2PH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Denormal Condition Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
FMA Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Rounding Behavior of Zero Result in FMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
FMA Numeric Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
Promoted Vector Integer SIMD Instructions in AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
VEX-Only SIMD Instructions in AVX and AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
New Primitive in AVX2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
Alignment Faulting Conditions when Memory Access is Not Aligned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
Instructions Requiring Explicitly Aligned Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
Instructions Not Requiring Explicit Memory Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
512-bit Instruction Groups in the Intel AVX-512 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
Feature flag Collection Required of 256/128 Bit Vector Lengths for Each Instruction Group . . . . . . . . . . . . . . . . . . . . 15-7
Instruction Mnemonics That Do Not Support EVEX.128 Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Characteristics of Three Rounding Control Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Static Rounding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
SIMD Instructions Requiring Explicitly Aligned Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Instructions Not Requiring Explicit Memory Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
RTM Abort Status Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Error Code Definition of BNDSTATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Intel MPX Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
Effective Address Size of Intel MPX Instructions with 67H Prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
Bounds Register INIT Behavior Due to BND Prefix with Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
I/O Instruction Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
Codes Describing Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
EFLAGS Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
EFLAGS Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
x87 FPU and SIMD Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Exceptions Generated with x87 FPU Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Exceptions Generated with SSE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Exceptions Generated with SSE2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5
Exceptions Generated with SSE3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
Exceptions Generated with SSE4 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8
ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIVSS, ADDPD, ADDSD, SUBPD, SUBSD, MULPD, MULSD,
DIVPD, DIVSD, ADDSUBPS, ADDSUBPD, HADDPS, HADDPD, HSUBPS, HSUBPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD, CMPPD.EQ, CMPSD.EQ, CMPPD.ORD, CMPSD.ORD . . . . . . . . . . . . . . . . . E-6
CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD, CMPPD.NEQ, CMPSD.NEQ, CMPPD.UNORD, CMPSD.UNORDE-6
CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE, CMPPD.LT, CMPSD.LT, CMPPD.LE, CMPSD.LE. . . . . . . . . . . . . . . . . . . . . . . . . . E-6
CMPPS.NLT, CMPSS.NLT, CMPPS.NLE, CMPSS.NLE, CMPPD.NLT, CMPSD.NLT, CMPPD.NLE, CMPSD.NLE . . . . . . . . . . . . . . E-7
COMISS, COMISD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7
UCOMISS, UCOMISD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7
CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI, CVTSD2SI, CVTTPD2PI, CVTTSD2SI, CVTPS2DQ,
Vol. 1 xxi
CONTENTS
PAGE
Table E-9.
Table E-10.
Table E-11.
Table E-12.
Table E-13.
Table E-14.
Table E-15.
Table E-16.
Table E-17.
Table E-18.
xxii Vol. 1
CVTTPS2DQ, CVTPD2DQ, CVTTPD2DQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7
MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, MINSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8
SQRTPS, SQRTSS, SQRTPD, SQRTSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8
CVTPS2PD, CVTSS2SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8
CVTPD2PS, CVTSD2SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8
#I - Invalid Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9
#Z - Divide-by-Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11
#D - Denormal Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12
#O - Numeric Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13
#U - Numeric Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-14
#P - Inexact Result (Precision). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-15
CHAPTER 1
ABOUT THIS MANUAL
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number
253665) is part of a set that describes the architecture and programming environment of Intel® 64 and IA-32
architecture processors. Other volumes in this set are:
•
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set
Reference (order numbers 253666, 253667, 326018 and 334569).
•
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D: System
Programming Guide (order numbers 253668, 253669, 326019 and 332831).
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture
and programming environment of Intel 64 and IA-32 processors. The Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volumes 2A, 2B, 2C & 2D, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers who write operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D, describe
the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operatingsystem and BIOS designers. In addition, the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B, addresses the programming environment for classes of software that host operating systems.
1.1
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL
This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which
include:
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Pentium® processors
P6 family processors
Pentium® 4 processors
Pentium® M processors
Intel® Xeon® processors
Pentium® D processors
Pentium® processor Extreme Editions
64-bit Intel® Xeon® processors
Intel® Core™ Duo processor
Intel® Core™ Solo processor
Dual-Core Intel® Xeon® processor LV
Intel® Core™2 Duo processor
Intel® Core™2 Quad processor Q6000 series
Intel® Xeon® processor 3000, 3200 series
Intel® Xeon® processor 5000 series
Intel® Xeon® processor 5100, 5300 series
Intel® Core™2 Extreme processor X7000 and X6800 series
Intel® Core™2 Extreme processor QX6000 series
Intel® Xeon® processor 7100 series
Intel® Pentium® Dual-Core processor
Intel® Xeon® processor 7200, 7300 series
Intel® Xeon® processor 5200, 5400, 7400 series
Vol. 1 1-1
ABOUT THIS MANUAL
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Intel® Core™2 Extreme processor QX9000 and X9000 series
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Intel® Core™ i7 processor
Intel® Core™2 Quad processor Q9000 series
Intel® Core™2 Duo processor E8000, T9000 series
Intel® Atom™ processor family
Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are built from 45 nm and 32 nm processes
Intel® Core™ i5 processor
Intel® Xeon® processor E7-8800/4800/2800 product families
Intel® Core™ i7-3930K processor
2nd generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series
Intel® Xeon® processor E3-1200 product family
Intel® Xeon® processor E5-2400/1400 product family
Intel® Xeon® processor E5-4600/2600/1600 product family
3rd generation Intel® Core™ processors
Intel® Xeon® processor E3-1200 v2 product family
Intel® Xeon® processor E5-2400/1400 v2 product families
Intel® Xeon® processor E5-4600/2600/1600 v2 product families
Intel® Xeon® processor E7-8800/4800/2800 v2 product families
4th generation Intel® Core™ processors
The Intel® Core™ M processor family
Intel® Core™ i7-59xx Processor Extreme Edition
Intel® Core™ i7-49xx Processor Extreme Edition
Intel® Xeon® processor E3-1200 v3 product family
Intel® Xeon® processor E5-2600/1600 v3 product families
5th generation Intel® Core™ processors
Intel® Xeon® processor D-1500 product family
Intel® Xeon® processor E5 v4 family
Intel® Atom™ processor X7-Z8000 and X5-Z8000 series
Intel® Atom™ processor Z3400 series
Intel® Atom™ processor Z3500 series
6th generation Intel® Core™ processors
Intel® Xeon® processor E3-1500m v5 product family
P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium®
Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors.
The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microarchitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture. Intel Xeon
processor 5000, 7100 series are based on the Intel NetBurst® microarchitecture.
The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LV are based on an improved
Pentium® M processor microarchitecture.
The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200 and 7300 series, Intel® Pentium® dual-core, Intel®
Core™2 Duo, Intel® Core™2 Quad, and Intel® Core™2 Extreme processors are based on Intel® Core™ microarchitecture.
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The Intel® Xeon® processor 5200, 5400, 7400 series, Intel® Core™2 Quad processor Q9000 series, and Intel®
Core™2 Extreme processor QX9000, X9000 series, Intel® Core™2 processor E8000 series are based on Enhanced
Intel® Core™ microarchitecture.
The Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are based on the Intel® Atom™ microarchitecture and supports Intel 64 architecture.
The Intel® Core™ i7 processor and Intel® Xeon® processor 3400, 5500, 7500 series are based on 45 nm Intel®
microarchitecture code name Nehalem. Intel® microarchitecture code name Westmere is a 32 nm version of Intel®
microarchitecture code name Nehalem. Intel® Xeon® processor 5600 series, Intel Xeon processor E7 and various
Intel Core i7, i5, i3 processors are based on Intel® microarchitecture code name Westmere. These processors
support Intel 64 architecture.
The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor E78800/4800/2800 product families, Intel® CoreTM i7-3930K processor, and 2nd generation Intel® Core™ i7-2xxx,
Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series are based on the Intel® microarchitecture code
name Sandy Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E7-8800/4800/2800 v2 product families, Intel® Xeon® processor E3-1200 v2 product
family and the 3rd generation Intel® Core™ processors are based on the Intel® microarchitecture code name Ivy
Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E5-4600/2600/1600 v2 product families, Intel® Xeon® processor E5-2400/1400 v2
product families and Intel® Core™ i7-49xx Processor Extreme Edition are based on the Intel® microarchitecture
code name Ivy Bridge-E and support Intel 64 architecture.
The Intel® Xeon® processor E3-1200 v3 product family and 4th Generation Intel® Core™ processors are based on
the Intel® microarchitecture code name Haswell and support Intel 64 architecture.
The Intel® Core™ M processor family, 5th generation Intel® Core™ processors, Intel® Xeon® processor D-1500
product family and the Intel® Xeon® processor E5 v4 family are based on the Intel® microarchitecture code name
Broadwell and support Intel 64 architecture.
The Intel® Xeon® processor E3-1500m v5 product family and 6th generation Intel® Core™ processors are based
on the Intel® microarchitecture code name Skylake and support Intel 64 architecture.
The Intel® Xeon® processor E5-2600/1600 v3 product families and the Intel® Core™ i7-59xx Processor Extreme
Edition are based on the Intel® microarchitecture code name Haswell-E and support Intel 64 architecture.
The Intel® Atom™ processor Z8000 series is based on the Intel microarchitecture code name Airmont.
The Intel® Atom™ processor Z3400 series and the Intel® Atom™ processor Z3500 series are based on the Intel
microarchitecture code name Silvermont.
P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-core Intel® Xeon® processor LV,
and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel® Atom™
processor Z5xx series support IA-32 architecture.
The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel®
Core™2 Duo, Intel® Core™2 Extreme processors, Intel Core 2 Quad processors, Pentium® D processors, Pentium®
Dual-Core processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel® 64 architecture.
IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microprocessors. Intel® 64 architecture is the instruction set architecture and programming environment which is the superset
of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.
1.2
OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE
A description of this manual’s content follows:
Chapter 1 — About This Manual. Gives an overview of all five volumes of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel
manuals and documentation of interest to programmers and hardware designers.
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Chapter 2 — Intel® 64 and IA-32 Architectures. Introduces the Intel 64 and IA-32 architectures along with the
families of Intel processors that are based on these architectures. It also gives an overview of the common features
found in these processors and brief history of the Intel 64 and IA-32 architectures.
Chapter 3 — Basic Execution Environment. Introduces the models of memory organization and describes the
register set used by applications.
Chapter 4 — Data Types. Describes the data types and addressing modes recognized by the processor; provides
an overview of real numbers and floating-point formats and of floating-point exceptions.
Chapter 5 — Instruction Set Summary. Lists all Intel 64 and IA-32 instructions, divided into technology groups.
Chapter 6 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stack and mechanisms
provided for making procedure calls and for servicing interrupts and exceptions.
Chapter 7 — Programming with General-Purpose Instructions. Describes basic load and store, program
control, arithmetic, and string instructions that operate on basic data types, general-purpose and segment registers; also describes system instructions that are executed in protected mode.
Chapter 8 — Programming with the x87 FPU. Describes the x87 floating-point unit (FPU), including floatingpoint registers and data types; gives an overview of the floating-point instruction set and describes the processor's
floating-point exception conditions.
Chapter 9 — Programming with Intel® MMX™ Technology. Describes Intel MMX technology, including MMX
registers and data types; also provides an overview of the MMX instruction set.
Chapter 10 — Programming with Intel® Streaming SIMD Extensions (Intel® SSE). Describes SSE extensions, including XMM registers, the MXCSR register, and packed single-precision floating-point data types; provides
an overview of the SSE instruction set and gives guidelines for writing code that accesses the SSE extensions.
Chapter 11 — Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2). Describes SSE2
extensions, including XMM registers and packed double-precision floating-point data types; provides an overview
of the SSE2 instruction set and gives guidelines for writing code that accesses SSE2 extensions. This chapter also
describes SIMD floating-point exceptions that can be generated with SSE and SSE2 instructions. It also provides
general guidelines for incorporating support for SSE and SSE2 extensions into operating system and applications
code.
Chapter 12 — Programming with Intel® Streaming SIMD Extensions 3 (Intel® SSE3), Supplemental
Streaming SIMD Extensions 3 (SSSE3), Intel® Streaming SIMD Extensions 4 (Intel® SSE4) and Intel®
AES New Instructions (Intel® AESNI). Provides an overview of the SSE3 instruction set, Supplemental SSE3,
SSE4, AESNI instructions, and guidelines for writing code that accesses these extensions.
Chapter 13 — Managing State Using the XSAVE Feature Set. Describes the XSAVE feature set instructions
and explains how software can enable the XSAVE feature set and XSAVE-enabled features.
Chapter 14 — Programming with AVX, FMA and AVX2. Provides an overview of the Intel® AVX instruction set,
FMA and Intel AVX2 extensions and gives guidelines for writing code that accesses these extensions.
Chapter 15 — Programming with Intel Transactional Synchronization Extensions. Describes the instruction extensions that support lock elision techniques to improve the performance of multi-threaded software with
contended locks.
Chapter 16 — Input/Output. Describes the processor’s I/O mechanism, including I/O port addressing, I/O
instructions, and I/O protection mechanisms.
Chapter 17 — Processor Identification and Feature Determination. Describes how to determine the CPU
type and features available in the processor.
Appendix A — EFLAGS Cross-Reference. Summarizes how the IA-32 instructions affect the flags in the EFLAGS
register.
Appendix B — EFLAGS Condition Codes. Summarizes how conditional jump, move, and ‘byte set on condition
code’ instructions use condition code flags (OF, CF, ZF, SF, and PF) in the EFLAGS register.
Appendix C — Floating-Point Exceptions Summary. Summarizes exceptions raised by the x87 FPU floatingpoint and SSE/SSE2/SSE3 floating-point instructions.
Appendix D — Guidelines for Writing x87 FPU Exception Handlers. Describes how to design and write MSDOS* compatible exception handling facilities for FPU exceptions (includes software and hardware requirements
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ABOUT THIS MANUAL
and assembly-language code examples). This appendix also describes general techniques for writing robust FPU
exception handlers.
Appendix E — Guidelines for Writing SIMD Floating-Point Exception Handlers. Gives guidelines for writing
exception handlers for exceptions generated by SSE/SSE2/SSE3 floating-point instructions.
1.3
NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for
hexadecimal and binary numbers. This notation is described below.
1.3.1
Bit and Byte Order
In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses
increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to
two raised to the power of the bit position. Intel 64 and IA-32 processors are “little endian” machines; this means
the bytes of a word are numbered starting from the least significant byte. See Figure 1-1.
Highest
Address
Data Structure
32
24 23
Byte 3
16 15
Byte 2
8 7
Byte 1
0
Byte 0
Bit offset
28
24
20
16
12
8
4
0
Lowest
Address
Byte Offset
Figure 1-1. Bit and Byte Order
1.3.2
Reserved Bits and Software Compatibility
In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as
reserved, it is essential for compatibility with future processors that software treat these bits as having a future,
though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable.
Software should follow these guidelines in dealing with reserved bits:
•
Do not depend on the states of any reserved bits when testing the values of registers that contain such bits.
Mask out the reserved bits before testing.
•
•
•
Do not depend on the states of any reserved bits when storing to memory or to a register.
Do not depend on the ability to retain information written into any reserved bits.
When loading a register, always load the reserved bits with the values indicated in the documentation, if any,
or reload them with values previously read from the same register.
NOTE
Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers.
Depending upon the values of reserved register bits will make software dependent upon the
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unspecified manner in which the processor handles these bits. Programs that depend upon
reserved values risk incompatibility with future processors.
1.3.2.1
Instruction Operands
When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset,
an instruction has the following format:
label: mnemonic argument1, argument2, argument3
where:
•
•
•
A label is an identifier which is followed by a colon.
A mnemonic is a reserved name for a class of instruction opcodes which have the same function.
The operands argument1, argument2, and argument3 are optional. There may be from zero to three
operands, depending on the opcode. When present, they take the form of either literals or identifiers for data
items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items
declared in another part of the program (which may not be shown in the example).
When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left
operand is the destination.
For example:
LOADREG: MOV EAX, SUBTOTAL
In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,
and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.
1.3.3
Hexadecimal and Binary Numbers
Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for
example, 0F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, and F.
Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for
example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might
arise.
1.3.4
Segmented Addressing
The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes.
Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The
range of memory that can be addressed is called an address space.
The processor also supports segmented addressing. This is a form of addressing where a program may have many
independent address spaces, called segments. For example, a program can keep its code (instructions) and stack
in separate segments. Code addresses would always refer to the code space, and stack addresses would always
refer to the stack space. The following notation is used to specify a byte address within a segment:
Segment-register:Byte-address
For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS
register:
DS:FF79H
The following segment address identifies an instruction address in the code segment. The CS register points to the
code segment and the EIP register contains the address of the instruction.
CS:EIP
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1.3.5
A New Syntax for CPUID, CR, and MSR Values
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information.
See Figure 1-2.
CPUID Input and Output
CPUID.01H:ECX.SSE[bit 25] = 1
Input value for EAX register
Output register and feature flag or field
name with bit position(s)
Value (or range) of output
Control Register Values
CR4.OSFXSR[bit 9] = 1
Example CR name
Feature flag or field name
with bit position(s)
Value (or range) of output
Model-Specific Register Values
IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1
Example MSR name
Feature flag or field name with bit position(s)
Value (or range) of output
SDM20002
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation
1.3.6
Exceptions
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the
error. An example of the notation used to show an exception and error code is shown below:
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is
reported. Under some conditions, exceptions that produce error codes may not be able to report an accurate code.
In this case, the error code is zero, as shown below for a general-protection exception:
#GP(0)
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1.4
RELATED LITERATURE
Literature related to Intel 64 and IA-32 processors is listed and viewable on-line at:
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
See also:
•
•
•
The data sheet for a particular Intel 64 or IA-32 processor
•
Intel® Fortran Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
•
Intel® Software Development Tools:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual (in three or seven volumes):
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
•
Intel® 64 and IA-32 Architectures Optimization Reference Manual:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimizationmanual.html
•
Intel 64 Architecture x2APIC Specification:
The specification update for a particular Intel 64 or IA-32 processor
Intel® C++ Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
http://www.intel.com/content/www/us/en/architecture-and-technology/64-architecture-x2apic-specification.html
•
Intel® Trusted Execution Technology Measured Launched Environment Programming Guide:
http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html
•
Developing Multi-threaded Applications: A Platform Consistent Approach:
https://software.intel.com/sites/default/files/article/147714/51534-developing-multithreaded-applications.pdf
•
Using Spin-Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor:
http://software.intel.com/en-us/articles/ap949-using-spin-loops-on-intel-pentiumr-4-processor-and-intelxeonr-processor/
•
Performance Monitoring Unit Sharing Guide
http://software.intel.com/file/30388
Literature related to selected features in future Intel processors are available at:
•
Intel® Architecture Instruction Set Extensions Programming Reference
https://software.intel.com/en-us/isa-extensions
•
Intel® Software Guard Extensions (Intel® SGX) Programming Reference
https://software.intel.com/en-us/isa-extensions/intel-sgx
More relevant links are:
•
Intel® Developer Zone:
https://software.intel.com/en-us
•
Developer centers:
http://www.intel.com/content/www/us/en/hardware-developers/developer-centers.html
•
Processor support general link:
http://www.intel.com/support/processors/
•
Software products and packages:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® Hyper-Threading Technology (Intel® HT Technology):
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm
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CHAPTER 2
INTEL 64 AND IA-32 ARCHITECTURES
®
The exponential growth of computing power and ownership has made the computer one of the most important
forces shaping business and society. Intel 64 and IA-32 architectures have been at the forefront of the computer
revolution and is today the preferred computer architecture, as measured by computers in use and the total
computing power available in the world.
2.1
BRIEF HISTORY OF INTEL® 64 AND IA-32 ARCHITECTURE
The following sections provide a summary of the major technical evolutions from IA-32 to Intel 64 architecture:
starting from the Intel 8086 processor to the latest Intel® Core® 2 Duo, Core 2 Quad and Intel Xeon processor
5300 and 7300 series. Object code created for processors released as early as 1978 still executes on the latest
processors in the Intel 64 and IA-32 architecture families.
2.1.1
16-bit Processors and Segmentation (1978)
The IA-32 architecture family was preceded by 16-bit processors, the 8086 and 8088. The 8086 has 16-bit registers and a 16-bit external data bus, with 20-bit addressing giving a 1-MByte address space. The 8088 is similar to
the 8086 except it has an 8-bit external data bus.
The 8086/8088 introduced segmentation to the IA-32 architecture. With segmentation, a 16-bit segment register
contains a pointer to a memory segment of up to 64 KBytes. Using four segment registers at a time, 8086/8088
processors are able to address up to 256 KBytes without switching between segments. The 20-bit addresses that
can be formed using a segment register and an additional 16-bit pointer provide a total address range of 1 MByte.
2.1.2
The Intel® 286 Processor (1982)
The Intel 286 processor introduced protected mode operation into the IA-32 architecture. Protected mode uses the
segment register content as selectors or pointers into descriptor tables. Descriptors provide 24-bit base addresses
with a physical memory size of up to 16 MBytes, support for virtual memory management on a segment swapping
basis, and a number of protection mechanisms. These mechanisms include:
•
•
•
Segment limit checking
Read-only and execute-only segment options
Four privilege levels
2.1.3
The Intel386™ Processor (1985)
The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers
for use both to hold operands and for addressing. The lower half of each 32-bit Intel386 register retains the properties of the 16-bit registers of earlier generations, permitting backward compatibility. The processor also provides
a virtual-8086 mode that allows for even greater efficiency when executing programs created for 8086/8088
processors.
In addition, the Intel386 processor has support for:
•
•
•
•
A 32-bit address bus that supports up to 4-GBytes of physical memory
A segmented-memory model and a flat memory model
Paging, with a fixed 4-KByte page size providing a method for virtual memory management
Support for parallel stages
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2.1.4
The Intel486™ Processor (1989)
The Intel486™ processor added more parallel execution capability by expanding the Intel386 processor’s instruction decode and execution units into five pipelined stages. Each stage operates in parallel with the others on up to
five instructions in different stages of execution.
In addition, the processor added:
•
An 8-KByte on-chip first-level cache that increased the percent of instructions that could execute at the scalar
rate of one per clock
•
•
An integrated x87 FPU
Power saving and system management capabilities
2.1.5
The Intel® Pentium® Processor (1993)
The introduction of the Intel Pentium processor added a second execution pipeline to achieve superscalar performance (two pipelines, known as u and v, together can execute two instructions per clock). The on-chip first-level
cache doubled, with 8 KBytes devoted to code and another 8 KBytes devoted to data. The data cache uses the MESI
protocol to support more efficient write-back cache in addition to the write-through cache previously used by the
Intel486 processor. Branch prediction with an on-chip branch table was added to increase performance in looping
constructs.
In addition, the processor added:
•
•
•
•
•
Extensions to make the virtual-8086 mode more efficient and allow for 4-MByte as well as 4-KByte pages
Internal data paths of 128 and 256 bits add speed to internal data transfers
Burstable external data bus was increased to 64 bits
An APIC to support systems with multiple processors
A dual processor mode to support glueless two processor systems
A subsequent stepping of the Pentium family introduced Intel MMX technology (the Pentium Processor with MMX
technology). Intel MMX technology uses the single-instruction, multiple-data (SIMD) execution model to perform
parallel computations on packed integer data contained in 64-bit registers.
See Section 2.2.7, “SIMD Instructions.”
2.1.6
The P6 Family of Processors (1995-1999)
The P6 family of processors was based on a superscalar microarchitecture that set new performance standards; see
also Section 2.2.1, “P6 Family Microarchitecture.” One of the goals in the design of the P6 family microarchitecture
was to exceed the performance of the Pentium processor significantly while using the same 0.6-micrometer, fourlayer, metal BICMOS manufacturing process. Members of this family include the following:
•
The Intel Pentium Pro processor is three-way superscalar. Using parallel processing techniques, the
processor is able on average to decode, dispatch, and complete execution of (retire) three instructions per
clock cycle. The Pentium Pro introduced the dynamic execution (micro-data flow analysis, out-of-order
execution, superior branch prediction, and speculative execution) in a superscalar implementation. The
processor was further enhanced by its caches. It has the same two on-chip 8-KByte 1st-Level caches as the
Pentium processor and an additional 256-KByte Level 2 cache in the same package as the processor.
•
The Intel Pentium II processor added Intel MMX technology to the P6 family processors along with new
packaging and several hardware enhancements. The processor core is packaged in the single edge contact
cartridge (SECC). The Level l data and instruction caches were enlarged to 16 KBytes each, and Level 2 cache
sizes of 256 KBytes, 512 KBytes, and 1 MByte are supported. A half-frequency backside bus connects the Level
2 cache to the processor. Multiple low-power states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep are
supported to conserve power when idling.
•
The Pentium II Xeon processor combined the premium characteristics of previous generations of Intel
processors. This includes: 4-way, 8-way (and up) scalability and a 2 MByte 2nd-Level cache running on a fullfrequency backside bus.
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•
The Intel Celeron processor family focused on the value PC market segment. Its introduction offers an
integrated 128 KBytes of Level 2 cache and a plastic pin grid array (P.P.G.A.) form factor to lower system design
cost.
•
The Intel Pentium III processor introduced the Streaming SIMD Extensions (SSE) to the IA-32 architecture.
SSE extensions expand the SIMD execution model introduced with the Intel MMX technology by providing a
new set of 128-bit registers and the ability to perform SIMD operations on packed single-precision floatingpoint values. See Section 2.2.7, “SIMD Instructions.”
•
The Pentium III Xeon processor extended the performance levels of the IA-32 processors with the
enhancement of a full-speed, on-die, and Advanced Transfer Cache.
2.1.7
The Intel® Pentium® 4 Processor Family (2000-2006)
The Intel Pentium 4 processor family is based on Intel NetBurst microarchitecture; see Section 2.2.2, “Intel
NetBurst® Microarchitecture.”
The Intel Pentium 4 processor introduced Streaming SIMD Extensions 2 (SSE2); see Section 2.2.7, “SIMD Instructions.” The Intel Pentium 4 processor 3.40 GHz, supporting Hyper-Threading Technology introduced Streaming
SIMD Extensions 3 (SSE3); see Section 2.2.7, “SIMD Instructions.”
Intel 64 architecture was introduced in the Intel Pentium 4 Processor Extreme Edition supporting Hyper-Threading
Technology and in the Intel Pentium 4 Processor 6xx and 5xx sequences.
Intel® Virtualization Technology (Intel® VT) was introduced in the Intel Pentium 4 processor 672 and 662.
2.1.8
The Intel® Xeon® Processor (2001- 2007)
Intel Xeon processors (with exception for dual-core Intel Xeon processor LV, Intel Xeon processor 5100 series) are
based on the Intel NetBurst microarchitecture; see Section 2.2.2, “Intel NetBurst® Microarchitecture.” As a family,
this group of IA-32 processors (more recently Intel 64 processors) is designed for use in multi-processor server
systems and high-performance workstations.
The Intel Xeon processor MP introduced support for Intel® Hyper-Threading Technology; see Section 2.2.8, “Intel®
Hyper-Threading Technology.”
The 64-bit Intel Xeon processor 3.60 GHz (with an 800 MHz System Bus) was used to introduce Intel 64 architecture. The Dual-Core Intel Xeon processor includes dual core technology. The Intel Xeon processor 70xx series
includes Intel Virtualization Technology.
The Intel Xeon processor 5100 series introduces power-efficient, high performance Intel Core microarchitecture.
This processor is based on Intel 64 architecture; it includes Intel Virtualization Technology and dual-core technology. The Intel Xeon processor 3000 series are also based on Intel Core microarchitecture. The Intel Xeon
processor 5300 series introduces four processor cores in a physical package, they are also based on Intel Core
microarchitecture.
2.1.9
The Intel® Pentium® M Processor (2003-2006)
The Intel Pentium M processor family is a high performance, low power mobile processor family with microarchitectural enhancements over previous generations of IA-32 Intel mobile processors. This family is designed for
extending battery life and seamless integration with platform innovations that enable new usage models (such as
extended mobility, ultra thin form-factors, and integrated wireless networking).
Its enhanced microarchitecture includes:
•
•
Support for Intel Architecture with Dynamic Execution
•
•
On-die, primary 32-KByte instruction cache and 32-KByte write-back data cache
A high performance, low-power core manufactured using Intel’s advanced process technology with copper
interconnect
On-die, second-level cache (up to 2 MByte) with Advanced Transfer Cache Architecture
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INTEL® 64 AND IA-32 ARCHITECTURES
•
•
•
•
Advanced Branch Prediction and Data Prefetch Logic
Support for MMX technology, Streaming SIMD instructions, and the SSE2 instruction set
A 400 or 533 MHz, Source-Synchronous Processor System Bus
Advanced power management using Enhanced Intel SpeedStep® technology
2.1.10
The Intel® Pentium® Processor Extreme Edition (2005)
The Intel Pentium processor Extreme Edition introduced dual-core technology. This technology provides advanced
hardware multi-threading support. The processor is based on Intel NetBurst microarchitecture and supports SSE,
SSE2, SSE3, Hyper-Threading Technology, and Intel 64 architecture.
See also:
•
•
•
•
•
•
Section 2.2.2, “Intel NetBurst® Microarchitecture”
Section 2.2.3, “Intel® Core™ Microarchitecture”
Section 2.2.7, “SIMD Instructions”
Section 2.2.8, “Intel® Hyper-Threading Technology”
Section 2.2.9, “Multi-Core Technology”
Section 2.2.10, “Intel® 64 Architecture”
2.1.11
The Intel® Core™ Duo and Intel® Core™ Solo Processors (2006-2007)
The Intel Core Duo processor offers power-efficient, dual-core performance with a low-power design that extends
battery life. This family and the single-core Intel Core Solo processor offer microarchitectural enhancements over
Pentium M processor family.
Its enhanced microarchitecture includes:
•
•
•
•
•
Intel® Smart Cache which allows for efficient data sharing between two processor cores
Improved decoding and SIMD execution
Intel® Dynamic Power Coordination and Enhanced Intel® Deeper Sleep to reduce power consumption
Intel® Advanced Thermal Manager which features digital thermal sensor interfaces
Support for power-optimized 667 MHz bus
The dual-core Intel Xeon processor LV is based on the same microarchitecture as Intel Core Duo processor, and
supports IA-32 architecture.
2.1.12
The Intel® Xeon® Processor 5100, 5300 Series and Intel® Core™2 Processor Family
(2006)
The Intel Xeon processor 3000, 3200, 5100, 5300, and 7300 series, Intel Pentium Dual-Core, Intel Core 2 Extreme,
Intel Core 2 Quad processors, and Intel Core 2 Duo processor family support Intel 64 architecture; they are based
on the high-performance, power-efficient Intel® Core microarchitecture built on 65 nm process technology. The
Intel Core microarchitecture includes the following innovative features:
•
•
•
•
•
Intel® Wide Dynamic Execution to increase performance and execution throughput
Intel® Intelligent Power Capability to reduce power consumption
Intel® Advanced Smart Cache which allows for efficient data sharing between two processor cores
Intel® Smart Memory Access to increase data bandwidth and hide latency of memory accesses
Intel® Advanced Digital Media Boost which improves application performance using multiple generations of
Streaming SIMD extensions
The Intel Xeon processor 5300 series, Intel Core 2 Extreme processor QX6800 series, and Intel Core 2 Quad
processors support Intel quad-core technology.
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2.1.13
The Intel® Xeon® Processor 5200, 5400, 7400 Series and Intel® Core™2 Processor
Family (2007)
The Intel Xeon processor 5200, 5400, and 7400 series, Intel Core 2 Quad processor Q9000 Series, Intel Core 2 Duo
processor E8000 series support Intel 64 architecture; they are based on the Enhanced Intel® Core microarchitecture using 45 nm process technology. The Enhanced Intel Core microarchitecture provides the following improved
features:
•
•
A radix-16 divider, faster OS primitives further increases the performance of Intel® Wide Dynamic Execution.
•
A 128-bit shuffler engine significantly improves the performance of Intel® Advanced Digital Media Boost and
SSE4.
Improves Intel® Advanced Smart Cache with Up to 50% larger level-two cache and up to 50% increase in wayset associativity.
Intel Xeon processor 5400 series and Intel Core 2 Quad processor Q9000 Series support Intel quad-core technology. Intel Xeon processor 7400 series offers up to six processor cores and an L3 cache up to 16 MBytes.
2.1.14
The Intel® Atom™ Processor Family (2008)
The first generation of Intel® AtomTM processors are built on 45 nm process technology. They are based on a new
microarchitecture, Intel® AtomTM microarchitecture, which is optimized for ultra low power devices. The Intel®
AtomTM microarchitecture features two in-order execution pipelines that minimize power consumption, increase
battery life, and enable ultra-small form factors. The initial Intel Atom Processor family and subsequent generations including
Intel Atom processor D2000, N2000, E2000, Z2000, C1000 series provide the following features:
•
•
•
•
•
•
Enhanced Intel® SpeedStep® Technology
Intel® Hyper-Threading Technology
Deep Power Down Technology with Dynamic Cache Sizing
Support for instruction set extensions up to and including Supplemental Streaming SIMD Extensions 3
(SSSE3).
Support for Intel® Virtualization Technology
Support for Intel® 64 Architecture (excluding Intel Atom processor Z5xx Series)
2.1.15
The Intel® Atom™ Processor Family Based on Silvermont Microarchitecture (2013)
Intel Atom Processor C2xxx, E3xxx, S1xxx series are based on the Silvermont microarchitecture. Processors based on the Silvermont
microarchitecture supports instruction set extensions up to and including SSE4.2, AESNI, and PCLMULQDQ.
2.1.16
The Intel® Core™i7 Processor Family (2008)
The Intel Core i7 processor 900 series support Intel 64 architecture; they are based on Intel® microarchitecture
code name Nehalem using 45 nm process technology. The Intel Core i7 processor and Intel Xeon processor 5500
series include the following innovative features:
•
•
•
•
•
•
•
•
Intel® Turbo Boost Technology converts thermal headroom into higher performance.
Intel® HyperThreading Technology in conjunction with Quadcore to provide four cores and eight threads.
Dedicated power control unit to reduce active and idle power consumption.
Integrated memory controller on the processor supporting three channel of DDR3 memory.
8 MB inclusive Intel® Smart Cache.
Intel® QuickPath interconnect (QPI) providing point-to-point link to chipset.
Support for SSE4.2 and SSE4.1 instruction sets.
Second generation Intel Virtualization Technology.
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2.1.17
The Intel® Xeon® Processor 7500 Series (2010)
The Intel Xeon processor 7500 and 6500 series are based on Intel microarchitecture code name Nehalem using 45
nm process technology. They support the same features described in Section 2.1.16, plus the following innovative
features:
•
•
•
•
Up to eight cores per physical processor package.
Up to 24 MB inclusive Intel® Smart Cache.
Provides Intel® Scalable Memory Interconnect (Intel® SMI) channels with Intel® 7500 Scalable Memory Buffer
to connect to system memory.
Advanced RAS supporting software recoverable machine check architecture.
2.1.18
2010 Intel® Core™ Processor Family (2010)
2010 Intel Core processor family spans Intel Core i7, i5 and i3 processors. They are based on Intel® microarchitecture code name Westmere using 32 nm process technology. The innovative features can include:
•
•
•
•
•
Deliver smart performance using Intel Hyper-Threading Technology plus Intel Turbo Boost Technology.
Enhanced Intel Smart Cache and integrated memory controller.
Intelligent power gating.
Repartitioned platform with on-die integration of 45 nm integrated graphics.
Range of instruction set support up to AESNI, PCLMULQDQ, SSE4.2 and SSE4.1.
2.1.19
The Intel® Xeon® Processor 5600 Series (2010)
The Intel Xeon processor 5600 series are based on Intel microarchitecture code name Westmere using 32 nm
process technology. They support the same features described in Section 2.1.16, plus the following innovative
features:
•
•
•
•
Up to six cores per physical processor package.
Up to 12 MB enhanced Intel® Smart Cache.
Support for AESNI, PCLMULQDQ, SSE4.2 and SSE4.1 instruction sets.
Flexible Intel Virtualization Technologies across processor and I/O.
2.1.20
The Second Generation Intel® Core™ Processor Family (2011)
The Second Generation Intel Core processor family spans Intel Core i7, i5 and i3 processors based on the Sandy
Bridge microarchitecture. They are built from 32 nm process technology and have innovative features including:
•
•
•
•
•
Intel Turbo Boost Technology for Intel Core i5 and i7 processors
Intel Hyper-Threading Technology.
Enhanced Intel Smart Cache and integrated memory controller.
Processor graphics and built-in visual features like Intel® Quick Sync Video, Intel® InsiderTM etc.
Range of instruction set support up to AVX, AESNI, PCLMULQDQ, SSE4.2 and SSE4.1.
Intel Xeon processor E3-1200 product family is also based on the Sandy Bridge microarchitecture.
Intel Xeon processor E5-2400/1400 product families are based on the Sandy Bridge-EP microarchitecture.
Intel Xeon processor E5-4600/2600/1600 product families are based on the Sandy Bridge-EP microarchitecture
and provide support for multiple sockets.
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2.1.21
The Third Generation Intel® Core™ Processor Family (2012)
The Third Generation Intel Core processor family spans Intel Core i7, i5 and i3 processors based on the Ivy Bridge
microarchitecture. The Intel Xeon processor E7-8800/4800/2800 v2 product families and Intel Xeon processor E31200 v2 product family are also based on the Ivy Bridge microarchitecture.
The Intel Xeon processor E5-2400/1400 v2 product families are based on the Ivy Bridge-EP microarchitecture.
The Intel Xeon processor E5-4600/2600/1600 v2 product families are based on the Ivy Bridge-EP microarchitecture and provide support for multiple sockets.
2.1.22
The Fourth Generation Intel® Core™ Processor Family (2013)
The Fourth Generation Intel Core processor family spans Intel Core i7, i5 and i3 processors based on the Haswell
microarchitecture. Intel Xeon processor E3-1200 v3 product family is also based on the Haswell microarchitecture.
2.2
MORE ON SPECIFIC ADVANCES
The following sections provide more information on major innovations.
2.2.1
P6 Family Microarchitecture
The Pentium Pro processor introduced a new microarchitecture commonly referred to as P6 processor microarchitecture. The P6 processor microarchitecture was later enhanced with an on-die, Level 2 cache, called Advanced
Transfer Cache.
The microarchitecture is a three-way superscalar, pipelined architecture. Three-way superscalar means that by
using parallel processing techniques, the processor is able on average to decode, dispatch, and complete execution
of (retire) three instructions per clock cycle. To handle this level of instruction throughput, the P6 processor family
uses a decoupled, 12-stage superpipeline that supports out-of-order instruction execution.
Figure 2-1 shows a conceptual view of the P6 processor microarchitecture pipeline with the Advanced Transfer
Cache enhancement.
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System Bus
Frequently used
Bus Unit
2nd Level Cache
On-die, 8-way
Less frequently used
1st Level Cache
4-way, low latency
Front End
Fetch/
Decode
Execution
Instruction
Cache
Microcode
ROM
Execution
Out-of-Order
Core
Retirement
Branch History Update
BTSs/Branch Prediction
OM16520
Figure 2-1. The P6 Processor Microarchitecture with Advanced Transfer Cache Enhancement
To ensure a steady supply of instructions and data for the instruction execution pipeline, the P6 processor microarchitecture incorporates two cache levels. The Level 1 cache provides an 8-KByte instruction cache and an 8-KByte
data cache, both closely coupled to the pipeline. The Level 2 cache provides 256-KByte, 512-KByte, or 1-MByte
static RAM that is coupled to the core processor through a full clock-speed 64-bit cache bus.
The centerpiece of the P6 processor microarchitecture is an out-of-order execution mechanism called dynamic
execution. Dynamic execution incorporates three data-processing concepts:
•
Deep branch prediction allows the processor to decode instructions beyond branches to keep the instruction
pipeline full. The P6 processor family implements highly optimized branch prediction algorithms to predict the
direction of the instruction.
•
Dynamic data flow analysis requires real-time analysis of the flow of data through the processor to
determine dependencies and to detect opportunities for out-of-order instruction execution. The out-of-order
execution core can monitor many instructions and execute these instructions in the order that best optimizes
the use of the processor’s multiple execution units, while maintaining the data integrity.
•
Speculative execution refers to the processor’s ability to execute instructions that lie beyond a conditional
branch that has not yet been resolved, and ultimately to commit the results in the order of the original
instruction stream. To make speculative execution possible, the P6 processor microarchitecture decouples the
dispatch and execution of instructions from the commitment of results. The processor’s out-of-order execution
core uses data-flow analysis to execute all available instructions in the instruction pool and store the results in
temporary registers. The retirement unit then linearly searches the instruction pool for completed instructions
that no longer have data dependencies with other instructions or unresolved branch predictions. When
completed instructions are found, the retirement unit commits the results of these instructions to memory
and/or the IA-32 registers (the processor’s eight general-purpose registers and eight x87 FPU data registers)
in the order they were originally issued and retires the instructions from the instruction pool.
2.2.2
Intel NetBurst® Microarchitecture
The Intel NetBurst microarchitecture provides:
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•
The Rapid Execution Engine
— Arithmetic Logic Units (ALUs) run at twice the processor frequency
— Basic integer operations can dispatch in 1/2 processor clock tick
•
Hyper-Pipelined Technology
— Deep pipeline to enable industry-leading clock rates for desktop PCs and servers
— Frequency headroom and scalability to continue leadership into the future
•
Advanced Dynamic Execution
— Deep, out-of-order, speculative execution engine
•
•
Up to 126 instructions in flight
Up to 48 loads and 24 stores in pipeline1
— Enhanced branch prediction capability
•
•
•
•
Reduces the misprediction penalty associated with deeper pipelines
Advanced branch prediction algorithm
4K-entry branch target array
New cache subsystem
— First level caches
•
•
•
•
Advanced Execution Trace Cache stores decoded instructions
Execution Trace Cache removes decoder latency from main execution loops
Execution Trace Cache integrates path of program execution flow into a single line
Low latency data cache
— Second level cache
•
•
•
Full-speed, unified 8-way Level 2 on-die Advance Transfer Cache
Bandwidth and performance increases with processor frequency
High-performance, quad-pumped bus interface to the Intel NetBurst microarchitecture system bus
— Supports quad-pumped, scalable bus clock to achieve up to 4X effective speed
— Capable of delivering up to 8.5 GBytes of bandwidth per second
•
•
•
Superscalar issue to enable parallelism
Expanded hardware registers with renaming to avoid register name space limitations
64-byte cache line size (transfers data up to two lines per sector)
Figure 2-2 is an overview of the Intel NetBurst microarchitecture. This microarchitecture pipeline is made up of
three sections: (1) the front end pipeline, (2) the out-of-order execution core, and (3) the retirement unit.
1. Intel 64 and IA-32 processors based on the Intel NetBurst microarchitecture at 90 nm process can handle more than 24 stores in
flight.
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INTEL® 64 AND IA-32 ARCHITECTURES
System Bus
Frequently used paths
Less frequently used
paths
Bus Unit
3rd Level Cache
Optional
2nd Level Cache
8-Way
1st Level Cache
4-way
Front End
Fetch/Decode
Trace Cache
Microcode ROM
BTBs/Branch Prediction
Execution
Out-Of-Order
Core
Retirement
Branch History Update
OM16521
Figure 2-2. The Intel NetBurst Microarchitecture
2.2.2.1
The Front End Pipeline
The front end supplies instructions in program order to the out-of-order execution core. It performs a number of
functions:
•
•
•
•
•
•
Prefetches instructions that are likely to be executed
Fetches instructions that have not already been prefetched
Decodes instructions into micro-operations
Generates microcode for complex instructions and special-purpose code
Delivers decoded instructions from the execution trace cache
Predicts branches using highly advanced algorithm
The pipeline is designed to address common problems in high-speed, pipelined microprocessors. Two of these
problems contribute to major sources of delays:
•
•
time to decode instructions fetched from the target
wasted decode bandwidth due to branches or branch target in the middle of cache lines
The operation of the pipeline’s trace cache addresses these issues. Instructions are constantly being fetched and
decoded by the translation engine (part of the fetch/decode logic) and built into sequences of micro-ops called
traces. At any time, multiple traces (representing prefetched branches) are being stored in the trace cache. The
trace cache is searched for the instruction that follows the active branch. If the instruction also appears as the first
instruction in a pre-fetched branch, the fetch and decode of instructions from the memory hierarchy ceases and the
pre-fetched branch becomes the new source of instructions (see Figure 2-2).
The trace cache and the translation engine have cooperating branch prediction hardware. Branch targets are
predicted based on their linear addresses using branch target buffers (BTBs) and fetched as soon as possible.
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2.2.2.2
Out-Of-Order Execution Core
The out-of-order execution core’s ability to execute instructions out of order is a key factor in enabling parallelism.
This feature enables the processor to reorder instructions so that if one micro-op is delayed, other micro-ops may
proceed around it. The processor employs several buffers to smooth the flow of micro-ops.
The core is designed to facilitate parallel execution. It can dispatch up to six micro-ops per cycle (this exceeds trace
cache and retirement micro-op bandwidth). Most pipelines can start executing a new micro-op every cycle, so
several instructions can be in flight at a time for each pipeline. A number of arithmetic logical unit (ALU) instructions can start at two per cycle; many floating-point instructions can start once every two cycles.
2.2.2.3
Retirement Unit
The retirement unit receives the results of the executed micro-ops from the out-of-order execution core and
processes the results so that the architectural state updates according to the original program order.
When a micro-op completes and writes its result, it is retired. Up to three micro-ops may be retired per cycle. The
Reorder Buffer (ROB) is the unit in the processor which buffers completed micro-ops, updates the architectural
state in order, and manages the ordering of exceptions. The retirement section also keeps track of branches and
sends updated branch target information to the BTB. The BTB then purges pre-fetched traces that are no longer
needed.
2.2.3
Intel® Core™ Microarchitecture
Intel Core microarchitecture introduces the following features that enable high performance and power-efficient
performance for single-threaded as well as multi-threaded workloads:
•
Intel® Wide Dynamic Execution enable each processor core to fetch, dispatch, execute in high bandwidths
to support retirement of up to four instructions per cycle.
— Fourteen-stage efficient pipeline
— Three arithmetic logical units
— Four decoders to decode up to five instruction per cycle
— Macro-fusion and micro-fusion to improve front-end throughput
— Peak issue rate of dispatching up to six micro-ops per cycle
— Peak retirement bandwidth of up to 4 micro-ops per cycle
— Advanced branch prediction
— Stack pointer tracker to improve efficiency of executing function/procedure entries and exits
•
Intel® Advanced Smart Cache delivers higher bandwidth from the second level cache to the core, and
optimal performance and flexibility for single-threaded and multi-threaded applications.
— Large second level cache up to 4 MB and 16-way associativity
— Optimized for multicore and single-threaded execution environments
— 256 bit internal data path to improve bandwidth from L2 to first-level data cache
•
Intel® Smart Memory Access prefetches data from memory in response to data access patterns and reduces
cache-miss exposure of out-of-order execution.
— Hardware prefetchers to reduce effective latency of second-level cache misses
— Hardware prefetchers to reduce effective latency of first-level data cache misses
— Memory disambiguation to improve efficiency of speculative execution execution engine
•
Intel® Advanced Digital Media Boost improves most 128-bit SIMD instruction with single-cycle throughput
and floating-point operations.
— Single-cycle throughput of most 128-bit SIMD instructions
— Up to eight floating-point operation per cycle
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— Three issue ports available to dispatching SIMD instructions for execution
Intel Core 2 Extreme, Intel Core 2 Duo processors and Intel Xeon processor 5100 series implement two processor
cores based on the Intel Core microarchitecture, the functionality of the subsystems in each core are depicted in
Figure 2-3.
Instruction Fetch and P reD ecode
Instruction Q ueue
M icrocode
ROM
D ecode
S hared L2 C ache
U p to 10.7 G B /s
FS B
R enam e/A lloc
R etirem ent U nit
(R e-O rder B uffer)
S cheduler
A LU
B ranch
M M X /S S E /FP
M ove
A LU
FA dd
M M X /S S E
A LU
FM ul
M M X/S S E
Load
S tore
L1D C ache and D T LB
Figure 2-3. The Intel Core Microarchitecture Pipeline Functionality
2.2.3.1
The Front End
The front end of Intel Core microarchitecture provides several enhancements to feed the Intel Wide Dynamic
Execution engine:
•
Instruction fetch unit prefetches instructions into an instruction queue to maintain steady supply of instruction
to the decode units.
•
•
Four-wide decode unit can decode 4 instructions per cycle or 5 instructions per cycle with Macrofusion.
•
•
•
•
Microfusion fuses common sequence of two micro-ops as one micro-ops to improve retirement throughput.
•
Advanced branch prediction algorithm directs instruction fetch unit to fetch instructions likely in the architectural code path for decoding.
Macrofusion fuses common sequence of two instructions as one decoded instruction (micro-ops) to increase
decoding throughput.
Instruction queue provides caching of short loops to improve efficiency.
Stack pointer tracker improves efficiency of executing procedure/function entries and exits.
Branch prediction unit employs dedicated hardware to handle different types of branches for improved branch
prediction.
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2.2.3.2
Execution Core
The execution core of the Intel Core microarchitecture is superscalar and can process instructions out of order to
increase the overall rate of instructions executed per cycle (IPC). The execution core employs the following feature
to improve execution throughput and efficiency:
•
•
•
•
•
•
•
•
Up to six micro-ops can be dispatched to execute per cycle
Up to four instructions can be retired per cycle
Three full arithmetic logical units
SIMD instructions can be dispatched through three issue ports
Most SIMD instructions have 1-cycle throughput (including 128-bit SIMD instructions)
Up to eight floating-point operation per cycle
Many long-latency computation operation are pipelined in hardware to increase overall throughput
Reduced exposure to data access delays using Intel Smart Memory Access
2.2.4
Intel® Atom™ Microarchitecture
Intel Atom microarchitecture maximizes power-efficient performance for single-threaded and multi-threaded
workloads by providing:
•
Advanced Micro-Ops Execution
— Single-micro-op instruction execution from decode to retirement, including instructions with register-only,
load, and store semantics.
— Sixteen-stage, in-order pipeline optimized for throughput and reduced power consumption.
— Dual pipelines to enable decode, issue, execution and retirement of two instructions per cycle.
— Advanced stack pointer to improve efficiency of executing function entry/returns.
•
Intel® Smart Cache
— Second level cache is 512 KB and 8-way associativity.
— Optimized for multi-threaded and single-threaded execution environments
— 256 bit internal data path between L2 and L1 data cache improves high bandwidth.
•
Efficient Memory Access
— Efficient hardware prefetchers to L1 and L2, speculatively loading data likely to be requested by processor
to reduce cache miss impact.
•
Intel® Digital Media Boost
— Two issue ports for dispatching SIMD instructions to execution units.
— Single-cycle throughput for most 128-bit integer SIMD instructions
— Up to six floating-point operations per cycle
— Up to two 128-bit SIMD integer operations per cycle
— Safe Instruction Recognition (SIR) to allow long-latency floating-point operations to retire out of order with
respect to integer instructions.
2.2.5
Intel® Microarchitecture Code Name Nehalem
Intel microarchitecture code name Nehalem provides the foundation for many innovative features of Intel Core i7
processors. It builds on the success of 45 nm Intel Core microarchitecture and provides the following feature
enhancements:
•
Enhanced processor core
— Improved branch prediction and recovery from misprediction.
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— Enhanced loop streaming to improve front end performance and reduce power consumption.
— Deeper buffering in out-of-order engine to extract parallelism.
— Enhanced execution units to provide acceleration in CRC, string/text processing and data shuffling.
•
Smart Memory Access
— Integrated memory controller provides low-latency access to system memory and scalable memory
bandwidth
— New cache hierarchy organization with shared, inclusive L3 to reduce snoop traffic
— Two level TLBs and increased TLB size.
— Fast unaligned memory access.
•
HyperThreading Technology
— Provides two hardware threads (logical processors) per core.
— Takes advantage of 4-wide execution engine, large L3, and massive memory bandwidth.
•
Dedicated Power management Innovations
— Integrated microcontroller with optimized embedded firmware to manage power consumption.
— Embedded real-time sensors for temperature, current, and power.
— Integrated power gate to turn off/on per-core power consumption
— Versatility to reduce power consumption of memory, link subsystems.
2.2.6
Intel® Microarchitecture Code Name Sandy Bridge
Intel® microarchitecture code name Sandy Bridge builds on the successes of Intel® Core™ microarchitecture and
Intel microarchitecture code name Nehalem. It offers the following innovative features:
•
Intel Advanced Vector Extensions (Intel AVX)
— 256-bit floating-point instruction set extensions to the 128-bit Intel Streaming SIMD Extensions, providing
up to 2X performance benefits relative to 128-bit code.
— Non-destructive destination encoding offers more flexible coding techniques.
— Supports flexible migration and co-existence between 256-bit AVX code, 128-bit AVX code and legacy 128bit SSE code.
•
Enhanced front-end and execution engine
— New decoded Icache component that improves front-end bandwidth and reduces branch misprediction
penalty.
— Advanced branch prediction.
— Additional macro-fusion support.
— Larger dynamic execution window.
— Multi-precision integer arithmetic enhancements (ADC/SBB, MUL/IMUL).
— LEA bandwidth improvement.
— Reduction of general execution stalls (read ports, writeback conflicts, bypass latency, partial stalls).
— Fast floating-point exception handling.
— XSAVE/XRSTORE performance improvements and XSAVEOPT new instruction.
•
Cache hierarchy improvements for wider data path
— Doubling of bandwidth enabled by two symmetric ports for memory operation.
— Simultaneous handling of more in-flight loads and stores enabled by increased buffers.
— Internal bandwidth of two loads and one store each cycle.
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— Improved prefetching.
— High bandwidth low latency LLC architecture.
— High bandwidth ring architecture of on-die interconnect.
For additional information on Intel® Advanced Vector Extensions (AVX), see Section 5.13, “Intel® Advanced Vector
Extensions (Intel® AVX)” and Chapter 14, “Programming with AVX, FMA and AVX2” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
2.2.7
SIMD Instructions
Beginning with the Pentium II and Pentium with Intel MMX technology processor families, six extensions have been
introduced into the Intel 64 and IA-32 architectures to perform single-instruction multiple-data (SIMD) operations.
These extensions include the MMX technology, SSE extensions, SSE2 extensions, SSE3 extensions, Supplemental
Streaming SIMD Extensions 3, and SSE4. Each of these extensions provides a group of instructions that perform
SIMD operations on packed integer and/or packed floating-point data elements.
SIMD integer operations can use the 64-bit MMX or the 128-bit XMM registers. SIMD floating-point operations use
128-bit XMM registers. Figure 2-4 shows a summary of the various SIMD extensions (MMX technology, SSE, SSE2,
SSE3, SSSE3, and SSE4), the data types they operate on, and how the data types are packed into MMX and XMM
registers.
The Intel MMX technology was introduced in the Pentium II and Pentium with MMX technology processor families.
MMX instructions perform SIMD operations on packed byte, word, or doubleword integers located in MMX registers.
These instructions are useful in applications that operate on integer arrays and streams of integer data that lend
themselves to SIMD processing.
SSE extensions were introduced in the Pentium III processor family. SSE instructions operate on packed singleprecision floating-point values contained in XMM registers and on packed integers contained in MMX registers.
Several SSE instructions provide state management, cache control, and memory ordering operations. Other SSE
instructions are targeted at applications that operate on arrays of single-precision floating-point data elements (3D geometry, 3-D rendering, and video encoding and decoding applications).
SSE2 extensions were introduced in Pentium 4 and Intel Xeon processors. SSE2 instructions operate on packed
double-precision floating-point values contained in XMM registers and on packed integers contained in MMX and
XMM registers. SSE2 integer instructions extend IA-32 SIMD operations by adding new 128-bit SIMD integer operations and by expanding existing 64-bit SIMD integer operations to 128-bit XMM capability. SSE2 instructions also
provide new cache control and memory ordering operations.
SSE3 extensions were introduced with the Pentium 4 processor supporting Hyper-Threading Technology (built on
90 nm process technology). SSE3 offers 13 instructions that accelerate performance of Streaming SIMD Extensions technology, Streaming SIMD Extensions 2 technology, and x87-FP math capabilities.
SSSE3 extensions were introduced with the Intel Xeon processor 5100 series and Intel Core 2 processor family.
SSSE3 offer 32 instructions to accelerate processing of SIMD integer data.
SSE4 extensions offer 54 instructions. 47 of them are referred to as SSE4.1 instructions. SSE4.1 are introduced
with Intel Xeon processor 5400 series and Intel Core 2 Extreme processor QX9650. The other 7 SSE4 instructions
are referred to as SSE4.2 instructions.
AESNI and PCLMULQDQ introduce 7 new instructions. Six of them are primitives for accelerating algorithms based
on AES encryption/decryption standard, referred to as AESNI.
The PCLMULQDQ instruction accelerates general-purpose block encryption, which can perform carry-less multiplication for two binary numbers up to 64-bit wide.
Intel 64 architecture allows four generations of 128-bit SIMD extensions to access up to 16 XMM registers. IA-32
architecture provides 8 XMM registers.
Intel® Advanced Vector Extensions offers comprehensive architectural enhancements over previous generations of
Streaming SIMD Extensions. Intel AVX introduces the following architectural enhancements:
•
•
Support for 256-bit wide vectors and SIMD register set.
256-bit floating-point instruction set enhancement with up to 2X performance gain relative to 128-bit
Streaming SIMD extensions.
Vol. 1 2-15
INTEL® 64 AND IA-32 ARCHITECTURES
•
Instruction syntax support for generalized three-operand syntax to improve instruction programming flexibility
and efficient encoding of new instruction extensions.
•
Enhancement of legacy 128-bit SIMD instruction extensions to support three operand syntax and to simplify
compiler vectorization of high-level language expressions.
•
Support flexible deployment of 256-bit AVX code, 128-bit AVX code, legacy 128-bit code and scalar code.
In addition to performance considerations, programmers should also be cognizant of the implications of VEXencoded AVX instructions with the expectations of system software components that manage the processor state
components enabled by XCR0. For additional information see Section 2.3.10.1, “Vector Length Transition and
Programming Considerations” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
See also:
•
•
Section 5.4, “MMX™ Instructions,” and Chapter 9, “Programming with Intel® MMX™ Technology”
•
Section 5.6, “SSE2 Instructions,” and Chapter 11, “Programming with Intel® Streaming SIMD Extensions 2
(Intel® SSE2)”
•
Section 5.7, “SSE3 Instructions”, Section 5.8, “Supplemental Streaming SIMD Extensions 3 (SSSE3) Instructions”, Section 5.9, “SSE4 Instructions”, and Chapter 12, “Programming with Intel® SSE3, SSSE3, Intel®
SSE4 and Intel® AESNI”
Section 5.5, “SSE Instructions,” and Chapter 10, “Programming with Intel® Streaming SIMD Extensions
(Intel® SSE)”
2-16 Vol. 1
INTEL® 64 AND IA-32 ARCHITECTURES
SIMD Extension
Register Layout
Data Type
MMX Registers
8 Packed Byte Integers
MMX Technology - SSSE3
4 Packed Word Integers
2 Packed Doubleword Integers
Quadword
SSE - AVX
XMM Registers
4 Packed Single-Precision
Floating-Point Values
2 Packed Double-Precision
Floating-Point Values
16 Packed Byte Integers
8 Packed Word Integers
4 Packed Doubleword
Integers
2 Quadword Integers
Double Quadword
AVX
YMM Registers
8 Packed SP FP Values
4 Packed DP FP Values
2 128-bit Data
Figure 2-4. SIMD Extensions, Register Layouts, and Data Types
2.2.8
Intel® Hyper-Threading Technology
Intel Hyper-Threading Technology (Intel HT Technology) was developed to improve the performance of IA-32
processors when executing multi-threaded operating system and application code or single-threaded applications
under multi-tasking environments. The technology enables a single physical processor to execute two or more
separate code streams (threads) concurrently using shared execution resources.
Intel HT Technology is one form of hardware multi-threading capability in IA-32 processor families. It differs from
multi-processor capability using separate physically distinct packages with each physical processor package mated
with a physical socket. Intel HT Technology provides hardware multi-threading capability with a single physical
package by using shared execution resources in a processor core.
Architecturally, an IA-32 processor that supports Intel HT Technology consists of two or more logical processors,
each of which has its own IA-32 architectural state. Each logical processor consists of a full set of IA-32 data registers, segment registers, control registers, debug registers, and most of the MSRs. Each also has its own advanced
programmable interrupt controller (APIC).
Figure 2-5 shows a comparison of a processor that supports Intel HT Technology (implemented with two logical
processors) and a traditional dual processor system.
Vol. 1 2-17
INTEL® 64 AND IA-32 ARCHITECTURES
IA-32 Processor Supporting
Hyper-Threading Technology
AS
Traditional Multiple Processor (MP) System
AS
AS
AS
Processor Core
Processor Core
Processor Core
IA-32 processor
IA-32 processor
IA-32 processor
Two logical
processors that share
a single core
Each processor is a
separate physical
package
AS = IA-32 Architectural State
OM16522
Figure 2-5. Comparison of an IA-32 Processor Supporting Hyper-Threading Technology and a Traditional Dual
Processor System
Unlike a traditional MP system configuration that uses two or more separate physical IA-32 processors, the logical
processors in an IA-32 processor supporting Intel HT Technology share the core resources of the physical
processor. This includes the execution engine and the system bus interface. After power up and initialization, each
logical processor can be independently directed to execute a specified thread, interrupted, or halted.
Intel HT Technology leverages the process and thread-level parallelism found in contemporary operating systems
and high-performance applications by providing two or more logical processors on a single chip. This configuration
allows two or more threads1 to be executed simultaneously on each a physical processor. Each logical processor
executes instructions from an application thread using the resources in the processor core. The core executes these
threads concurrently, using out-of-order instruction scheduling to maximize the use of execution units during each
clock cycle.
2.2.8.1
Some Implementation Notes
All Intel HT Technology configurations require:
•
•
•
A processor that supports Intel HT Technology
A chipset and BIOS that utilize the technology
Operating system optimizations
See http://www.intel.com/products/ht/hyperthreading_more.htm for information.
At the firmware (BIOS) level, the basic procedures to initialize the logical processors in a processor supporting Intel
HT Technology are the same as those for a traditional DP or MP platform. The mechanisms that are described in the
Multiprocessor Specification, Version 1.4 to power-up and initialize physical processors in an MP system also apply
to logical processors in a processor that supports Intel HT Technology.
An operating system designed to run on a traditional DP or MP platform may use CPUID to determine the presence
of hardware multi-threading support feature and the number of logical processors they provide.
Although existing operating system and application code should run correctly on a processor that supports Intel HT
Technology, some code modifications are recommended to get the optimum benefit. These modifications are
discussed in Chapter 7, “Multiple-Processor Management,” Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
1. In the remainder of this document, the term “thread” will be used as a general term for the terms “process” and “thread.”
2-18 Vol. 1
INTEL® 64 AND IA-32 ARCHITECTURES
2.2.9
Multi-Core Technology
Multi-core technology is another form of hardware multi-threading capability in IA-32 processor families. Multicore technology enhances hardware multi-threading capability by providing two or more execution cores in a physical package.
The Intel Pentium processor Extreme Edition is the first member in the IA-32 processor family to introduce multicore technology. The processor provides hardware multi-threading support with both two processor cores and Intel
Hyper-Threading Technology. This means that the Intel Pentium processor Extreme Edition provides four logical
processors in a physical package (two logical processors for each processor core). The Dual-Core Intel Xeon
processor features multi-core, Intel Hyper-Threading Technology and supports multi-processor platforms.
The Intel Pentium D processor also features multi-core technology. This processor provides hardware multithreading support with two processor cores but does not offer Intel Hyper-Threading Technology. This means that
the Intel Pentium D processor provides two logical processors in a physical package, with each logical processor
owning the complete execution resources of a processor core.
The Intel Core 2 processor family, Intel Xeon processor 3000 series, Intel Xeon processor 5100 series, and Intel
Core Duo processor offer power-efficient multi-core technology. The processor contains two cores that share a
smart second level cache. The Level 2 cache enables efficient data sharing between two cores to reduce memory
traffic to the system bus.
Intel Core Duo Processor
Intel Core 2 Duo Processor
Intel Pentium dual-core Processor
Pentium D Processor
Architectual State
Architectual State
Execution Engine
Execution Engine
Local APIC
Local APIC
Architectual State
Architectual State
Execution Engine
Execution Engine
Local APIC
Local APIC
Bus Interface
Bus Interface
Second Level Cache
Bus Interface
System Bus
System Bus
Pentium Processor Extreme Edition
Architectual
State
Architectual
State
Architectual
State
Execution Engine
Local APIC
Architectual
State
Execution Engine
Local APIC
Local APIC
Bus Interface
Local APIC
Bus Interface
System Bus
OM19809
Figure 2-6. Intel 64 and IA-32 Processors that Support Dual-Core
The Pentium® dual-core processor is based on the same technology as the Intel Core 2 Duo processor family.
The Intel Xeon processor 7300, 5300 and 3200 series, Intel Core 2 Extreme Quad-Core processor, and Intel Core
2 Quad processors support Intel quad-core technology. The Quad-core Intel Xeon processors and the Quad-Core
Intel Core 2 processor family are also in Figure 2-7.
Vol. 1 2-19
INTEL® 64 AND IA-32 ARCHITECTURES
Intel Core 2 Extreme Quad-core Processor
Intel Core 2 Quad Processor
Intel Xeon Processor 3200 Series
Intel Xeon Processor 5300 Series
Architectual State
Architectual State
Architectual State
Architectual State
Execution Engine
Execution Engine
Execution Engine
Execution Engine
Local APIC
Local APIC
Local APIC
Local APIC
Second Level Cache
Second Level Cache
Bus Interface
Bus Interface
System Bus
OM19810
Figure 2-7. Intel 64 Processors that Support Quad-Core
Intel Core i7 processors support Intel quad-core technology, Intel HyperThreading Technology, provides Intel
QuickPath interconnect link to the chipset and have integrated memory controller supporting three channel to
DDR3 memory.
Intel Core i7 Processor
Logical
Proces
sor
Logical
Proces
sor
Logical
Proces
sor
Logical
Proces
sor
Logical
Proces
sor
Logical
Proces
sor
Logical
Proces
sor
Logical
Proces
sor
L1 and L2
L1 and L2
L1 and L2
L1 and L2
Execution Engine
Execution Engine
Execution Engine
Execution Engine
Third Level Cache
QuickPath Interconnect (QPI) Interface, Integrated Memory Controller
QPI
IMC
DDR3
Chipset
OM19810b
Figure 2-8. Intel Core i7 Processor
2-20 Vol. 1
INTEL® 64 AND IA-32 ARCHITECTURES
2.2.10
Intel® 64 Architecture
Intel 64 architecture increases the linear address space for software to 64 bits and supports physical address space
up to 46 bits. The technology also introduces a new operating mode referred to as IA-32e mode.
IA-32e mode operates in one of two sub-modes: (1) compatibility mode enables a 64-bit operating system to run
most legacy 32-bit software unmodified, (2) 64-bit mode enables a 64-bit operating system to run applications
written to access 64-bit address space.
In the 64-bit mode, applications may access:
•
•
•
•
•
•
•
64-bit flat linear addressing
8 additional general-purpose registers (GPRs)
8 additional registers for streaming SIMD extensions (SSE, SSE2, SSE3 and SSSE3)
64-bit-wide GPRs and instruction pointers
uniform byte-register addressing
fast interrupt-prioritization mechanism
a new instruction-pointer relative-addressing mode
An Intel 64 architecture processor supports existing IA-32 software because it is able to run all non-64-bit legacy
modes supported by IA-32 architecture. Most existing IA-32 applications also run in compatibility mode.
2.2.11
Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology for Intel 64 and IA-32 architectures provide extensions that support virtualization.
The extensions are referred to as Virtual Machine Extensions (VMX). An Intel 64 or IA-32 platform with VMX can
function as multiple virtual systems (or virtual machines). Each virtual machine can run operating systems and
applications in separate partitions.
VMX also provides programming interface for a new layer of system software (called the Virtual Machine Monitor
(VMM)) used to manage the operation of virtual machines. Information on VMX and on the programming of VMMs
is in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C.
Intel Core i7 processor provides the following enhancements to Intel Virtualization Technology:
•
•
•
Virtual processor ID (VPID) to reduce the cost of VMM managing transitions.
Extended page table (EPT) to reduce the number of transitions for VMM to manage memory virtualization.
Reduced latency of VM transitions.
2.3
INTEL® 64 AND IA-32 PROCESSOR GENERATIONS
In the mid-1960s, Intel cofounder and Chairman Emeritus Gordon Moore had this observation: “... the number of
transistors that would be incorporated on a silicon die would double every 18 months for the next several years.”
Over the past three and half decades, this prediction known as “Moore's Law” has continued to hold true.
The computing power and the complexity (or roughly, the number of transistors per processor) of Intel architecture
processors has grown in close relation to Moore's law. By taking advantage of new process technology and new
microarchitecture designs, each new generation of IA-32 processors has demonstrated frequency-scaling headroom and new performance levels over the previous generation processors.
Vol. 1 2-21
INTEL® 64 AND IA-32 ARCHITECTURES
The key features of the Intel Pentium 4 processor, Intel Xeon processor, Intel Xeon processor MP, Pentium III
processor, and Pentium III Xeon processor with advanced transfer cache are shown in Table 2-1. Older generation
IA-32 processors, which do not employ on-die Level 2 cache, are shown in Table 2-2.
Table 2-1. Key Features of Most Recent IA-32 Processors
Intel
Processor
Date
Introduced
Micro-architecture
Top-Bin Clock
Fre-quency at
Introduction
Transistors
Register
Sizes1
System
Max.
Bus Band- Extern.
width
Addr.
Space
On-Die
Caches2
Intel Pentium
M
Processor
7553
2004
Intel Pentium M
Processor
2.00 GHz
140 M
GP: 32
FPU: 80
MMX: 64
XMM: 128
3.2 GB/s
4 GB
L1: 64 KB
L2: 2 MB
Intel Core Duo
Processor
T26003
2006
Improved Intel
Pentium M
Processor
Microarchitecture;
Dual Core;
2.16 GHz
152M
GP: 32
FPU: 80
MMX: 64
XMM: 128
5.3 GB/s
4 GB
L1: 64 KB
L2: 2 MB
(2MB Total)
1.86 GHz 800 MHz
47M
GP: 32
FPU: 80
MMX: 64
XMM: 128
Up to 4.2
GB/s
4 GB
L1: 56 KB4
L2: 512KB
Intel Smart Cache,
Advanced Thermal
Manager
Intel Atom
Processor
Z5xx series
2008
Intel Atom
Microarchitecture;
Intel Virtualization
Technology.
NOTES:
1. The register size and external data bus size are given in bits.
2. First level cache is denoted using the abbreviation L1, 2nd level cache is denoted as L2. The size
of L1 includes the first-level data cache and the instruction cache where applicable, but
does not include the trace cache.
3. Intel processor numbers are not a measure of performance. Processor numbers differentiate
features within each processor family, not across different processor families.
See http://www.intel.com/products/processor_number for details.
4. In Intel Atom Processor, the size of L1 instruction cache is 32 KBytes, L1 data cache is 24 KBytes.
Table 2-2. Key Features of Most Recent Intel 64 Processors
Intel
Processor
Date
Introduced
Micro-architecture
Highest
Processor
Base Frequency at
Introduction
Transistors
Register
Sizes
System
Bus/QPI
Link
Speed
Max.
Extern.
Addr.
Space
On-Die
Caches
64-bit Intel
Xeon
Processor
with 800 MHz
System Bus
2004
Intel NetBurst
Microarchitecture;
Intel HyperThreading
Technology; Intel
64 Architecture
3.60 GHz
125 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
6.4 GB/s
64 GB
12K µop
Execution
Trace Cache;
16 KB L1;
1 MB L2
64-bit Intel
Xeon
Processor MP
with 8MB L3
2005
Intel NetBurst
Microarchitecture;
Intel HyperThreading
Technology; Intel
64 Architecture
3.33 GHz
675M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
5.3 GB/s 1
1024 GB
(1 TB)
12K µop
Execution
Trace Cache;
16 KB L1;
1 MB L2,
8 MB L3
2-22 Vol. 1
INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-2. Key Features of Most Recent Intel 64 Processors (Contd.)
Intel
Processor
Date
Introduced
Micro-architecture
Highest
Processor
Base Frequency at
Introduction
Transistors
Register
Sizes
System
Bus/QPI
Link
Speed
Max.
Extern.
Addr.
Space
On-Die
Caches
Intel Pentium
4
Processor
Extreme
Edition
Supporting
HyperThreading
Technology
2005
Intel NetBurst
Microarchitecture;
Intel HyperThreading
Technology; Intel
64 Architecture
3.73 GHz
164 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s
64 GB
12K µop
Execution
Trace Cache;
16 KB L1;
2 MB L2
Intel Pentium
Processor
Extreme
Edition 840
2005
Intel NetBurst
Microarchitecture;
Intel HyperThreading
Technology; Intel
64 Architecture;
3.20 GHz
230 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
6.4 GB/s
64 GB
12K µop
Execution
Trace Cache;
16 KB L1;
1MB L2
(2MB Total)
3.00 GHz
321M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
6.4 GB/s
64 GB
12K µop
Execution
Trace Cache;
16 KB L1;
2MB L2
(4MB Total)
3.80 GHz
164 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
6.4 GB/s
64 GB
12K µop
Execution
Trace Cache;
16 KB L1;
2MB L2
3.46 GHz
376M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s
64 GB
12K µop
Execution
Trace Cache;
16 KB L1;
2MB L2
Dual-core 2
Dual-Core Intel
Xeon
Processor
7041
2005
Intel NetBurst
Microarchitecture;
Intel HyperThreading
Technology; Intel
64 Architecture;
Dual-core 3
Intel Pentium
2005
4
Processor 672
Intel NetBurst
Microarchitecture;
Intel HyperThreading
Technology; Intel
64 Architecture;
Intel Virtualization
Technology.
Intel Pentium
Processor
Extreme
Edition 955
2006
Intel NetBurst
Microarchitecture;
Intel 64
Architecture; Dual
Core;
Intel Virtualization
Technology.
Intel Core 2
Extreme
Processor
X6800
2006
Intel Core
Microarchitecture;
Dual Core;
Intel 64
Architecture;
(4MB Total)
2.93 GHz
291M
GP: 32,64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s
64 GB
L1: 64 KB
L2: 4MB
(4MB Total)
Intel Virtualization
Technology.
Vol. 1 2-23
INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-2. Key Features of Most Recent Intel 64 Processors (Contd.)
Intel
Processor
Date
Introduced
Micro-architecture
Highest
Processor
Base Frequency at
Introduction
Transistors
Register
Sizes
System
Bus/QPI
Link
Speed
Max.
Extern.
Addr.
Space
On-Die
Caches
Intel Xeon
Processor
5160
2006
Intel Core
Microarchitecture;
Dual Core;
3.00 GHz
291M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
10.6 GB/s
64 GB
L1: 64 KB
L2: 4MB
(4MB Total)
3.40 GHz
1.3 B
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
12.8 GB/s
64 GB
L1: 64 KB
L2: 1MB
(2MB Total)
Intel 64
Architecture;
Intel Virtualization
Technology.
Intel Xeon
Processor
7140
2006
Intel NetBurst
Microarchitecture;
Dual Core;
Intel 64
Architecture;
L3: 16 MB
(16MB Total)
Intel Virtualization
Technology.
Intel Core 2
Extreme
Processor
QX6700
2006
Intel Core
Microarchitecture;
Quad Core;
2.66 GHz
582M
GP: 32,64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s
64 GB
L1: 64 KB
L2: 4MB
(4MB Total)
2.66 GHz
582 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
10.6 GB/s
256 GB
L1: 64 KB
L2: 4MB (8
MB Total)
3.00 GHz
291 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
10.6 GB/s
64 GB
L1: 64 KB
L2: 4MB
(4MB Total)
2.93 GHz
582 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s
1024 GB
L1: 64 KB
L2: 4MB
(8MB Total)
Intel 64
Architecture;
Intel Virtualization
Technology.
Quad-core
Intel Xeon
Processor
5355
2006
Intel Core
Microarchitecture;
Quad Core;
Intel 64
Architecture;
Intel Virtualization
Technology.
Intel Core 2
Duo Processor
E6850
2007
Intel Core
Microarchitecture;
Dual Core;
Intel 64
Architecture;
Intel Virtualization
Technology;
Intel Trusted
Execution
Technology
Intel Xeon
Processor
7350
2007
Intel Core
Microarchitecture;
Quad Core;
Intel 64
Architecture;
Intel Virtualization
Technology.
2-24 Vol. 1
INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-2. Key Features of Most Recent Intel 64 Processors (Contd.)
Intel
Processor
Date
Introduced
Micro-architecture
Highest
Processor
Base Frequency at
Introduction
Transistors
Register
Sizes
System
Bus/QPI
Link
Speed
Max.
Extern.
Addr.
Space
On-Die
Caches
Intel Xeon
Processor
5472
2007
Enhanced Intel
Core
Microarchitecture;
Quad Core;
3.00 GHz
820 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
12.8 GB/s
256 GB
L1: 64 KB
L2: 6MB
(12MB Total)
2.0 - 1.60
GHz
47 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
Up to 4.2
GB/s
Up to
64GB
L1: 56 KB4
L2: 512KB
2.67 GHz
1.9 B
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s
1024 GB
L1: 64 KB
L2: 3MB
(9MB Total)
Intel 64
Architecture;
Intel Virtualization
Technology.
Intel Atom
Processor
2008
Intel Atom
Microarchitecture;
Intel 64
Architecture;
Intel Virtualization
Technology.
Intel Xeon
Processor
7460
2008
Enhanced Intel
Core
Microarchitecture;
Six Cores;
L3: 16MB
Intel 64
Architecture;
Intel Virtualization
Technology.
Intel Atom
2008
Processor 330
Intel Atom
Microarchitecture;
Intel 64
Architecture;
1.60 GHz
94 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
Up to 4.2
GB/s
Up to
64GB
L1: 56 KB5
L2: 512KB
(1MB Total)
3.20 GHz
731 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
QPI: 6.4
GT/s;
Memory:
25 GB/s
64 GB
L1: 64 KB
L2: 256KB
Dual core;
Intel Virtualization
Technology.
Intel Core i7965
Processor
Extreme
Edition
2008
Intel
microarchitecture
code name
Nehalem;
Quadcore;
HyperThreading
Technology; Intel
QPI; Intel 64
Architecture;
L3: 8MB
Intel Virtualization
Technology.
Vol. 1 2-25
INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-2. Key Features of Most Recent Intel 64 Processors (Contd.)
Intel
Processor
Date
Introduced
Micro-architecture
Highest
Processor
Base Frequency at
Introduction
Transistors
Register
Sizes
Intel Core i7620M
Processor
2010
Intel Turbo Boost
Technology, Intel
microarchitecture
code name
Westmere;
Dualcore;
HyperThreading
Technology; Intel
64 Architecture;
2.66 GHz
383 M
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
System
Bus/QPI
Link
Speed
Max.
Extern.
Addr.
Space
On-Die
Caches
64 GB
L1: 64 KB
L2: 256KB
L3: 4MB
Intel Virtualization
Technology.,
Integrated graphics
Intel XeonProcessor
5680
2010
Intel Turbo Boost
Technology, Intel
microarchitecture
code name
Westmere; Six core;
HyperThreading
Technology; Intel
64 Architecture;
3.33 GHz
1.1B
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
QPI: 6.4
GT/s; 32
GB/s
1 TB
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
QPI: 6.4
GT/s;
Memory:
76 GB/s
16 TB
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
DMI: 5
GT/s;
Memory:
21 GB/s
64 GB
L1: 64 KB
L2: 256KB
L3: 12MB
Intel Virtualization
Technology.
Intel XeonProcessor
7560
2010
Intel Turbo Boost
Technology, Intel
microarchitecture
code name
Nehalem; Eight
core;
HyperThreading
Technology; Intel
64 Architecture;
2.26 GHz
2.3B
L1: 64 KB
L2: 256KB
L3: 24MB
Intel Virtualization
Technology.
Intel Core i72600K
Processor
2011
Intel Turbo Boost
Technology, Intel
microarchitecture
code name Sandy
Bridge; Four core;
HyperThreading
Technology; Intel
64 Architecture;
Intel Virtualization
Technology.,
Processor graphics,
Quicksync Video
2-26 Vol. 1
3.40 GHz
995M
YMM: 256
L1: 64 KB
L2: 256KB
L3: 8MB
INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-2. Key Features of Most Recent Intel 64 Processors (Contd.)
Intel
Processor
Date
Introduced
Micro-architecture
Highest
Processor
Base Frequency at
Introduction
Intel XeonProcessor E31280
2011
Intel Turbo Boost
Technology, Intel
microarchitecture
code name Sandy
Bridge; Four core;
HyperThreading
Technology; Intel
64 Architecture;
3.50 GHz
Transistors
Register
Sizes
System
Bus/QPI
Link
Speed
Max.
Extern.
Addr.
Space
On-Die
Caches
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
DMI: 5
GT/s;
Memory:
21 GB/s
1 TB
L1: 64 KB
L2: 256KB
QPI: 6.4
GT/s;
Memory:
102 GB/s
16 TB
L3: 8MB
YMM: 256
Intel Virtualization
Technology.
Intel XeonProcessor E78870
2011
Intel Turbo Boost
Technology, Intel
microarchitecture
code name
Westmere; Ten
core;
HyperThreading
Technology; Intel
64 Architecture;
2.40 GHz
2.2B
GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
L1: 64 KB
L2: 256KB
L3: 30MB
Intel Virtualization
Technology.
NOTES:
1. The 64-bit Intel Xeon Processor MP with an 8-MByte L3 supports a multi-processor platform with a dual system bus; this creates a
platform bandwidth with 10.6 GBytes.
2. In Intel Pentium Processor Extreme Edition 840, the size of on-die cache is listed for each core. The total size of L2 in the physical
package in 2 MBytes.
3. In Dual-Core Intel Xeon Processor 7041, the size of on-die cache is listed for each core. The total size of L2 in the physical package in
4 MBytes.
4. In Intel Atom Processor, the size of L1 instruction cache is 32 KBytes, L1 data cache is 24 KBytes.
5. In Intel Atom Processor, the size of L1 instruction cache is 32 KBytes, L1 data cache is 24 KBytes.
Vol. 1 2-27
INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-3. Key Features of Previous Generations of IA-32 Processors
Intel
Processor
Date
Introduced
Max. Clock
Frequency/
Technology at
Introduction
Transistors
Register
Sizes1
Ext. Data
Bus Size2
Max.
Extern.
Addr.
Space
Caches
8086
1978
8 MHz
29 K
16 GP
16
1 MB
None
Intel 286
1982
12.5 MHz
134 K
16 GP
16
16 MB
Note 3
Intel386 DX
Processor
1985
20 MHz
275 K
32 GP
32
4 GB
Note 3
Intel486 DX
Processor
1989
25 MHz
1.2 M
32 GP
80 FPU
32
4 GB
L1: 8 KB
Pentium Processor
1993
60 MHz
3.1 M
32 GP
80 FPU
64
4 GB
L1:16 KB
Pentium Pro
Processor
1995
200 MHz
5.5 M
32 GP
80 FPU
64
64 GB
L1: 16 KB
L2: 256 KB or
512 KB
Pentium II Processor
1997
266 MHz
7M
32 GP
80 FPU
64 MMX
64
64 GB
L1: 32 KB
L2: 256 KB or
512 KB
Pentium III Processor
1999
500 MHz
8.2 M
32 GP
80 FPU
64 MMX
128 XMM
64
64 GB
L1: 32 KB
L2: 512 KB
Pentium III and
Pentium III Xeon
Processors
1999
700 MHz
28 M
32 GP
80 FPU
64 MMX
128 XMM
64
64 GB
L1: 32 KB
L2: 256 KB
Pentium 4 Processor
2000
1.50 GHz, Intel
NetBurst
Microarchitecture
42 M
32 GP
80 FPU
64 MMX
128 XMM
64
64 GB
12K µop
Execution
Trace Cache;
L1: 8KB
L2: 256 KB
Intel Xeon Processor
2001
1.70 GHz, Intel
NetBurst
Microarchitecture
42 M
32 GP
80 FPU
64 MMX
128 XMM
64
64 GB
12K µop
Execution
Trace Cache;
L1: 8KB
L2: 512KB
Intel Xeon Processor
2002
2.20 GHz, Intel
NetBurst
Microarchitecture,
HyperThreading
Technology
55 M
32 GP
80 FPU
64 MMX
128 XMM
64
64 GB
12K µop
Execution
Trace Cache;
L1: 8KB
L2: 512KB
Pentium M Processor
2003
1.60 GHz, Intel
NetBurst
Microarchitecture
77 M
32 GP
80 FPU
64 MMX
128 XMM
64
4 GB
L1: 64KB
L2: 1 MB
2-28 Vol. 1
INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-3. Key Features of Previous Generations of IA-32 Processors (Contd.)
Intel Pentium 4
Processor
Supporting HyperThreading
Technology at 90 nm
process
2004
3.40 GHz, Intel
NetBurst
Microarchitecture,
HyperThreading
Technology
125 M
32 GP
80 FPU
64 MMX
128 XMM
64
64 GB
12K µop
Execution
Trace Cache;
L1: 16KB
L2: 1 MB
NOTE:
1. The register size and external data bus size are given in bits. Note also that each 32-bit general-purpose (GP) registers can be
addressed as an 8- or a 16-bit data registers in all of the processors.
2. Internal data paths are 2 to 4 times wider than the external data bus for each processor.
Vol. 1 2-29
INTEL® 64 AND IA-32 ARCHITECTURES
2-30 Vol. 1
CHAPTER 3
BASIC EXECUTION ENVIRONMENT
This chapter describes the basic execution environment of an Intel 64 or IA-32 processor as seen by assemblylanguage programmers. It describes how the processor executes instructions and how it stores and manipulates
data. The execution environment described here includes memory (the address space), general-purpose data
registers, segment registers, the flag register, and the instruction pointer register.
3.1
MODES OF OPERATION
The IA-32 architecture supports three basic operating modes: protected mode, real-address mode, and system
management mode. The operating mode determines which instructions and architectural features are accessible:
•
Protected mode — This mode is the native state of the processor. Among the capabilities of protected mode
is the ability to directly execute “real-address mode” 8086 software in a protected, multi-tasking environment.
This feature is called virtual-8086 mode, although it is not actually a processor mode. Virtual-8086 mode is
actually a protected mode attribute that can be enabled for any task.
•
Real-address mode — This mode implements the programming environment of the Intel 8086 processor with
extensions (such as the ability to switch to protected or system management mode). The processor is placed in
real-address mode following power-up or a reset.
•
System management mode (SMM) — This mode provides an operating system or executive with a
transparent mechanism for implementing platform-specific functions such as power management and system
security. The processor enters SMM when the external SMM interrupt pin (SMI#) is activated or an SMI is
received from the advanced programmable interrupt controller (APIC).
In SMM, the processor switches to a separate address space while saving the basic context of the currently
running program or task. SMM-specific code may then be executed transparently. Upon returning from SMM,
the processor is placed back into its state prior to the system management interrupt. SMM was introduced with
the Intel386™ SL and Intel486™ SL processors and became a standard IA-32 feature with the Pentium
processor family.
3.1.1
Intel® 64 Architecture
Intel 64 architecture adds IA-32e mode. IA-32e mode has two sub-modes.
These are:
•
Compatibility mode (sub-mode of IA-32e mode) — Compatibility mode permits most legacy 16-bit and
32-bit applications to run without re-compilation under a 64-bit operating system. For brevity, the compatibility
sub-mode is referred to as compatibility mode in IA-32 architecture. The execution environment of compatibility mode is the same as described in Section 3.2. Compatibility mode also supports all of the privilege levels
that are supported in 64-bit and protected modes. Legacy applications that run in Virtual 8086 mode or use
hardware task management will not work in this mode.
Compatibility mode is enabled by the operating system (OS) on a code segment basis. This means that a single
64-bit OS can support 64-bit applications running in 64-bit mode and support legacy 32-bit applications (not
recompiled for 64-bits) running in compatibility mode.
Compatibility mode is similar to 32-bit protected mode. Applications access only the first 4 GByte of linearaddress space. Compatibility mode uses 16-bit and 32-bit address and operand sizes. Like protected mode, this
mode allows applications to access physical memory greater than 4 GByte using PAE (Physical Address Extensions).
•
64-bit mode (sub-mode of IA-32e mode) — This mode enables a 64-bit operating system to run applications written to access 64-bit linear address space. For brevity, the 64-bit sub-mode is referred to as 64-bit
mode in IA-32 architecture.
Vol. 1 3-1
BASIC EXECUTION ENVIRONMENT
64-bit mode extends the number of general purpose registers and SIMD extension registers from 8 to 16.
General purpose registers are widened to 64 bits. The mode also introduces a new opcode prefix (REX) to
access the register extensions. See Section 3.2.1 for a detailed description.
64-bit mode is enabled by the operating system on a code-segment basis. Its default address size is 64 bits and
its default operand size is 32 bits. The default operand size can be overridden on an instruction-by-instruction
basis using a REX opcode prefix in conjunction with an operand size override prefix.
REX prefixes allow a 64-bit operand to be specified when operating in 64-bit mode. By using this mechanism,
many existing instructions have been promoted to allow the use of 64-bit registers and 64-bit addresses.
3.2
OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT
Any program or task running on an IA-32 processor is given a set of resources for executing instructions and for
storing code, data, and state information. These resources (described briefly in the following paragraphs and
shown in Figure 3-1) make up the basic execution environment for an IA-32 processor.
An Intel 64 processor supports the basic execution environment of an IA-32 processor, and a similar environment
under IA-32e mode that can execute 64-bit programs (64-bit sub-mode) and 32-bit programs (compatibility submode).
The basic execution environment is used jointly by the application programs and the operating system or executive
running on the processor.
•
Address space — Any task or program running on an IA-32 processor can address a linear address space of
up to 4 GBytes (232 bytes) and a physical address space of up to 64 GBytes (236 bytes). See Section 3.3.6,
“Extended Physical Addressing in Protected Mode,” for more information about addressing an address space
greater than 4 GBytes.
•
Basic program execution registers — The eight general-purpose registers, the six segment registers, the
EFLAGS register, and the EIP (instruction pointer) register comprise a basic execution environment in which to
execute a set of general-purpose instructions. These instructions perform basic integer arithmetic on byte,
word, and doubleword integers, handle program flow control, operate on bit and byte strings, and address
memory. See Section 3.4, “Basic Program Execution Registers,” for more information about these registers.
•
x87 FPU registers — The eight x87 FPU data registers, the x87 FPU control register, the status register, the
x87 FPU instruction pointer register, the x87 FPU operand (data) pointer register, the x87 FPU tag register, and
the x87 FPU opcode register provide an execution environment for operating on single-precision, doubleprecision, and double extended-precision floating-point values, word integers, doubleword integers, quadword
integers, and binary coded decimal (BCD) values. See Section 8.1, “x87 FPU Execution Environment,” for more
information about these registers.
•
MMX registers — The eight MMX registers support execution of single-instruction, multiple-data (SIMD)
operations on 64-bit packed byte, word, and doubleword integers. See Section 9.2, “The MMX Technology
Programming Environment,” for more information about these registers.
•
XMM registers — The eight XMM data registers and the MXCSR register support execution of SIMD operations
on 128-bit packed single-precision and double-precision floating-point values and on 128-bit packed byte,
word, doubleword, and quadword integers. See Section 10.2, “SSE Programming Environment,” for more
information about these registers.
•
YMM registers — The YMM data registers support execution of 256-bit SIMD operations on 256-bit packed
single-precision and double-precision floating-point values and on 256-bit packed byte, word, doubleword, and
quadword integers.
•
Bounds registers — Each of the BND0-BND3 register stores the lower and upper bounds (64 bits each)
associated with the pointer to a memory buffer. They support execution of the Intel MPX instructions.
•
BNDCFGU and BNDSTATUS— BNDCFGU configures user mode MPX operations on bounds checking.
BNDSTATUS provides additional information on the #BR caused by an MPX operation.
3-2 Vol. 1
BASIC EXECUTION ENVIRONMENT
Basic Program Execution Registers
Address Space*
2^32 -1
Eight 32-bit
Registers
General-Purpose Registers
Six 16-bit
Registers
Segment Registers
32-bits
EFLAGS Register
32-bits
EIP (Instruction Pointer Register)
FPU Registers
Eight 80-bit
Registers
Floating-Point
Data Registers
16 bits
Control Register
16 bits
Status Register
16 bits
Tag Register
0
*The address space can be
flat or segmented. Using
the physical address
extension mechanism, a
physical address space of
2^36 - 1 can be addressed.
Opcode Register (11-bits)
48 bits
FPU Instruction Pointer Register
48 bits
FPU Data (Operand) Pointer Register
Bounds Registers
MMX Registers
Eight 64-bit
Registers
MMX Registers
Four 128-bit Registers
BNDCFGU
BNDSTATUS
XMM Registers
Eight 128-bit
Registers
XMM Registers
32-bits
MXCSR Register
YMM Registers
Eight 256-bit
Registers
YMM Registers
Figure 3-1. IA-32 Basic Execution Environment for Non-64-bit Modes
Vol. 1 3-3
BASIC EXECUTION ENVIRONMENT
•
Stack — To support procedure or subroutine calls and the passing of parameters between procedures or
subroutines, a stack and stack management resources are included in the execution environment. The stack
(not shown in Figure 3-1) is located in memory. See Section 6.2, “Stacks,” for more information about stack
structure.
In addition to the resources provided in the basic execution environment, the IA-32 architecture provides the
following resources as part of its system-level architecture. They provide extensive support for operating-system
and system-development software. Except for the I/O ports, the system resources are described in detail in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A & 3B.
•
I/O ports — The IA-32 architecture supports a transfers of data to and from input/output (I/O) ports. See
Chapter 18, “Input/Output,” in this volume.
•
Control registers — The five control registers (CR0 through CR4) determine the operating mode of the
processor and the characteristics of the currently executing task. See Chapter 2, “System Architecture
Overview,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
•
Memory management registers — The GDTR, IDTR, task register, and LDTR specify the locations of data
structures used in protected mode memory management. See Chapter 2, “System Architecture Overview,” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
•
Debug registers — The debug registers (DR0 through DR7) control and allow monitoring of the processor’s
debugging operations. See in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
•
Memory type range registers (MTRRs) — The MTRRs are used to assign memory types to regions of
memory. See the sections on MTRRs in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volumes 3A & 3B.
•
Machine specific registers (MSRs) — The processor provides a variety of machine specific registers that are
used to control and report on processor performance. Virtually all MSRs handle system related functions and
are not accessible to an application program. One exception to this rule is the time-stamp counter. The MSRs
are described in Chapter 35, “Model-Specific Registers (MSRs),” of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3C.
•
Machine check registers — The machine check registers consist of a set of control, status, and errorreporting MSRs that are used to detect and report on hardware (machine) errors. See Chapter 15, “MachineCheck Architecture,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
•
Performance monitoring counters — The performance monitoring counters allow processor performance
events to be monitored. See Chapter 18, “Performance Monitoring,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3B.
The remainder of this chapter describes the organization of memory and the address space, the basic program
execution registers, and addressing modes. Refer to the following chapters in this volume for descriptions of the
other program execution resources shown in Figure 3-1:
•
•
•
x87 FPU registers — See Chapter 8, “Programming with the x87 FPU.”
•
•
YMM registers — See Chapter 14, “Programming with AVX, FMA and AVX2”.
•
Stack implementation and procedure calls — See Chapter 6, “Procedure Calls, Interrupts, and Exceptions.”
MMX Registers — See Chapter 9, “Programming with Intel® MMX™ Technology.”
XMM registers — See Chapter 10, “Programming with Intel® Streaming SIMD Extensions (Intel® SSE),”
Chapter 11, “Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2),” and Chapter 12,
“Programming with Intel® SSE3, SSSE3, Intel® SSE4 and Intel® AESNI.”
BND registers, BNDCFGU, BNDSTATUS — See Chapter 13, “Managing State Using the XSAVE Feature Set,”
and Chapter 17, “Intel® MPX”.
3-4 Vol. 1
BASIC EXECUTION ENVIRONMENT
3.2.1
64-Bit Mode Execution Environment
The execution environment for 64-bit mode is similar to that described in Section 3.2. The following paragraphs
describe the differences that apply.
•
Address space — A task or program running in 64-bit mode on an IA-32 processor can address linear address
space of up to 264 bytes (subject to the canonical addressing requirement described in Section 3.3.7.1) and
physical address space of up to 246 bytes. Software can query CPUID for the physical address size supported
by a processor.
•
Basic program execution registers — The number of general-purpose registers (GPRs) available is 16.
GPRs are 64-bits wide and they support operations on byte, word, doubleword and quadword integers.
Accessing byte registers is done uniformly to the lowest 8 bits. The instruction pointer register becomes 64 bits.
The EFLAGS register is extended to 64 bits wide, and is referred to as the RFLAGS register. The upper 32 bits
of RFLAGS is reserved. The lower 32 bits of RFLAGS is the same as EFLAGS. See Figure 3-2.
•
XMM registers — There are 16 XMM data registers for SIMD operations. See Section 10.2, “SSE Programming
Environment,” for more information about these registers.
•
YMM registers — There are 16 YMM data registers for SIMD operations. See Chapter 14, “Programming with
AVX, FMA and AVX2” for more information about these registers.
•
BND registers, BNDCFGU, BNDSTATUS — See Chapter 13, “Managing State Using the XSAVE Feature Set,”
and Chapter 17, “Intel® MPX”.
•
Stack — The stack pointer size is 64 bits. Stack size is not controlled by a bit in the SS descriptor (as it is in
non-64-bit modes) nor can the pointer size be overridden by an instruction prefix.
•
Control registers — Control registers expand to 64 bits. A new control register (the task priority register: CR8
or TPR) has been added. See Chapter 2, “Intel® 64 and IA-32 Architectures,” in this volume.
•
Debug registers — Debug registers expand to 64 bits. See Chapter 17, “Debug, Branch Profile, TSC, and
Quality of Service,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Vol. 1 3-5
BASIC EXECUTION ENVIRONMENT
•
Descriptor table registers — The global descriptor table register (GDTR) and interrupt descriptor table
register (IDTR) expand to 10 bytes so that they can hold a full 64-bit base address. The local descriptor table
register (LDTR) and the task register (TR) also expand to hold a full 64-bit base address.
Basic Program Execution Registers
Sixteen 64-bit
Registers
Six 16-bit
Registers
Address Space
2^64 -1
General-Purpose Registers
Segment Registers
64-bits
RFLAGS Register
64-bits
RIP (Instruction Pointer Register)
FPU Registers
Eight 80-bit
Registers
Floating-Point
Data Registers
16 bits
Control Register
16 bits
Status Register
16 bits
Tag Register
0
Opcode Register (11-bits)
64 bits
FPU Instruction Pointer Register
64 bits
FPU Data (Operand) Pointer Register
Bounds Registers
MMX Registers
Eight 64-bit
Registers
MMX Registers
Four 128-bit Registers
BNDCFGU
BNDSTATUS
XMM Registers
Sixteen 128-bit
Registers
XMM Registers
32-bits
MXCSR Register
YMM Registers
Sixteen 256-bit
Registers
YMM Registers
Figure 3-2. 64-Bit Mode Execution Environment
3.3
MEMORY ORGANIZATION
The memory that the processor addresses on its bus is called physical memory. Physical memory is organized as
a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address. The physical
address space ranges from zero to a maximum of 236 − 1 (64 GBytes) if the processor does not support Intel
64 architecture. Intel 64 architecture introduces a changes in physical and linear address space; these are
described in Section 3.3.3, Section 3.3.4, and Section 3.3.7.
3-6 Vol. 1
BASIC EXECUTION ENVIRONMENT
Virtually any operating system or executive designed to work with an IA-32 or Intel 64 processor will use the
processor’s memory management facilities to access memory. These facilities provide features such as segmentation and paging, which allow memory to be managed efficiently and reliably. Memory management is described in
detail in Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A. The following paragraphs describe the basic methods of addressing memory when
memory management is used.
3.3.1
IA-32 Memory Models
When employing the processor’s memory management facilities, programs do not directly address physical
memory. Instead, they access memory using one of three memory models: flat, segmented, or real address mode:
•
Flat memory model — Memory appears to a program as a single, continuous address space (Figure 3-3). This
space is called a linear address space. Code, data, and stacks are all contained in this address space. Linear
address space is byte addressable, with addresses running contiguously from 0 to 232 - 1 (if not in 64-bit
mode). An address for any byte in linear address space is called a linear address.
•
Segmented memory model — Memory appears to a program as a group of independent address spaces
called segments. Code, data, and stacks are typically contained in separate segments. To address a byte in a
segment, a program issues a logical address. This consists of a segment selector and an offset (logical
addresses are often referred to as far pointers). The segment selector identifies the segment to be accessed
and the offset identifies a byte in the address space of the segment. Programs running on an IA-32 processor
can address up to 16,383 segments of different sizes and types, and each segment can be as large as 232
bytes.
Internally, all the segments that are defined for a system are mapped into the processor’s linear address space.
To access a memory location, the processor thus translates each logical address into a linear address. This
translation is transparent to the application program.
The primary reason for using segmented memory is to increase the reliability of programs and systems. For
example, placing a program’s stack in a separate segment prevents the stack from growing into the code or
data space and overwriting instructions or data, respectively.
•
Real-address mode memory model — This is the memory model for the Intel 8086 processor. It is
supported to provide compatibility with existing programs written to run on the Intel 8086 processor. The realaddress mode uses a specific implementation of segmented memory in which the linear address space for the
program and the operating system/executive consists of an array of segments of up to 64 KBytes in size each.
The maximum size of the linear address space in real-address mode is 220 bytes.
See also: Chapter 20, “8086 Emulation,” Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B.
Vol. 1 3-7
BASIC EXECUTION ENVIRONMENT
Flat Model
Linear Address
Linear
Address
Space*
Segmented Model
Segments
Linear
Address
Space*
Offset (effective address)
Logical
Address Segment Selector
Real-Address Mode Model
Offset
Logical
Address Segment Selector
Linear Address
Space Divided
Into Equal
Sized Segments
* The linear address space
can be paged when using the
flat or segmented model.
Figure 3-3. Three Memory Management Models
3.3.2
Paging and Virtual Memory
With the flat or the segmented memory model, linear address space is mapped into the processor’s physical
address space either directly or through paging. When using direct mapping (paging disabled), each linear address
has a one-to-one correspondence with a physical address. Linear addresses are sent out on the processor’s address
lines without translation.
When using the IA-32 architecture’s paging mechanism (paging enabled), linear address space is divided into
pages which are mapped to virtual memory. The pages of virtual memory are then mapped as needed into physical
memory. When an operating system or executive uses paging, the paging mechanism is transparent to an application program. All that the application sees is linear address space.
In addition, IA-32 architecture’s paging mechanism includes extensions that support:
•
•
Physical Address Extensions (PAE) to address physical address space greater than 4 GBytes.
Page Size Extensions (PSE) to map linear address to physical address in 4-MBytes pages.
See also: Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A.
3.3.3
Memory Organization in 64-Bit Mode
Intel 64 architecture supports physical address space greater than 64 GBytes; the actual physical address size of
IA-32 processors is implementation specific. In 64-bit mode, there is architectural support for 64-bit linear address
space. However, processors supporting Intel 64 architecture may implement less than 64-bits (see Section
3.3.7.1). The linear address space is mapped into the processor physical address space through the PAE paging
mechanism.
3-8 Vol. 1
BASIC EXECUTION ENVIRONMENT
3.3.4
Modes of Operation vs. Memory Model
When writing code for an IA-32 or Intel 64 processor, a programmer needs to know the operating mode the
processor is going to be in when executing the code and the memory model being used. The relationship between
operating modes and memory models is as follows:
•
Protected mode — When in protected mode, the processor can use any of the memory models described in
this section. (The real-addressing mode memory model is ordinarily used only when the processor is in the
virtual-8086 mode.) The memory model used depends on the design of the operating system or executive.
When multitasking is implemented, individual tasks can use different memory models.
•
Real-address mode — When in real-address mode, the processor only supports the real-address mode
memory model.
•
System management mode — When in SMM, the processor switches to a separate address space, called the
system management RAM (SMRAM). The memory model used to address bytes in this address space is similar
to the real-address mode model. See Chapter 34, “System Management Mode,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3C, for more information on the memory model used in
SMM.
•
Compatibility mode — Software that needs to run in compatibility mode should observe the same memory
model as those targeted to run in 32-bit protected mode. The effect of segmentation is the same as it is in 32bit protected mode semantics.
•
64-bit mode — Segmentation is generally (but not completely) disabled, creating a flat 64-bit linear-address
space. Specifically, the processor treats the segment base of CS, DS, ES, and SS as zero in 64-bit mode (this
makes a linear address equal an effective address). Segmented and real address modes are not available in 64bit mode.
3.3.5
32-Bit and 16-Bit Address and Operand Sizes
IA-32 processors in protected mode can be configured for 32-bit or 16-bit address and operand sizes. With 32-bit
address and operand sizes, the maximum linear address or segment offset is FFFFFFFFH (232-1); operand sizes are
typically 8 bits or 32 bits. With 16-bit address and operand sizes, the maximum linear address or segment offset is
FFFFH (216-1); operand sizes are typically 8 bits or 16 bits.
When using 32-bit addressing, a logical address (or far pointer) consists of a 16-bit segment selector and a 32-bit
offset; when using 16-bit addressing, an address consists of a 16-bit segment selector and a 16-bit offset.
Instruction prefixes allow temporary overrides of the default address and/or operand sizes from within a program.
When operating in protected mode, the segment descriptor for the currently executing code segment defines the
default address and operand size. A segment descriptor is a system data structure not normally visible to application code. Assembler directives allow the default addressing and operand size to be chosen for a program. The
assembler and other tools then set up the segment descriptor for the code segment appropriately.
When operating in real-address mode, the default addressing and operand size is 16 bits. An address-size override
can be used in real-address mode to enable 32-bit addressing. However, the maximum allowable 32-bit linear
address is still 000FFFFFH (220-1).
3.3.6
Extended Physical Addressing in Protected Mode
Beginning with P6 family processors, the IA-32 architecture supports addressing of up to 64 GBytes (236 bytes) of
physical memory. A program or task could not address locations in this address space directly. Instead, it
addresses individual linear address spaces of up to 4 GBytes that mapped to 64-GByte physical address space
through a virtual memory management mechanism. Using this mechanism, an operating system can enable a
program to switch 4-GByte linear address spaces within 64-GByte physical address space.
The use of extended physical addressing requires the processor to operate in protected mode and the operating
system to provide a virtual memory management system. See “36-Bit Physical Addressing Using the PAE Paging
Mechanism” in Chapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
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3.3.7
Address Calculations in 64-Bit Mode
In most cases, 64-bit mode uses flat address space for code, data, and stacks. In 64-bit mode (if there is no
address-size override), the size of effective address calculations is 64 bits. An effective-address calculation uses a
64-bit base and index registers and sign-extend displacements to 64 bits.
In the flat address space of 64-bit mode, linear addresses are equal to effective addresses because the base
address is zero. In the event that FS or GS segments are used with a non-zero base, this rule does not hold. In 64bit mode, the effective address components are added and the effective address is truncated (See for example the
instruction LEA) before adding the full 64-bit segment base. The base is never truncated, regardless of addressing
mode in 64-bit mode.
The instruction pointer is extended to 64 bits to support 64-bit code offsets. The 64-bit instruction pointer is called
the RIP. Table 3-1 shows the relationship between RIP, EIP, and IP.
Table 3-1. Instruction Pointer Sizes
Bits 63:32
16-bit instruction pointer
Not Modified
32-bit instruction pointer
Zero Extension
64-bit instruction pointer
RIP
Bits 31:16
Bits 15:0
IP
EIP
Generally, displacements and immediates in 64-bit mode are not extended to 64 bits. They are still limited to 32
bits and sign-extended during effective-address calculations. In 64-bit mode, however, support is provided for 64bit displacement and immediate forms of the MOV instruction.
All 16-bit and 32-bit address calculations are zero-extended in IA-32e mode to form 64-bit addresses. Address
calculations are first truncated to the effective address size of the current mode (64-bit mode or compatibility
mode), as overridden by any address-size prefix. The result is then zero-extended to the full 64-bit address width.
Because of this, 16-bit and 32-bit applications running in compatibility mode can access only the low 4 GBytes of
the 64-bit mode effective addresses. Likewise, a 32-bit address generated in 64-bit mode can access only the low
4 GBytes of the 64-bit mode effective addresses.
3.3.7.1
Canonical Addressing
In 64-bit mode, an address is considered to be in canonical form if address bits 63 through to the most-significant
implemented bit by the microarchitecture are set to either all ones or all zeros.
Intel 64 architecture defines a 64-bit linear address. Implementations can support less. The first implementation of
IA-32 processors with Intel 64 architecture supports a 48-bit linear address. This means a canonical address must
have bits 63 through 48 set to zeros or ones (depending on whether bit 47 is a zero or one).
Although implementations may not use all 64 bits of the linear address, they should check bits 63 through the
most-significant implemented bit to see if the address is in canonical form. If a linear-memory reference is not in
canonical form, the implementation should generate an exception. In most cases, a general-protection exception
(#GP) is generated. However, in the case of explicit or implied stack references, a stack fault (#SS) is generated.
Instructions that have implied stack references, by default, use the SS segment register. These include PUSH/POPrelated instructions and instructions using RSP/RBP as base registers. In these cases, the canonical fault is #SS.
If an instruction uses base registers RSP/RBP and uses a segment override prefix to specify a non-SS segment, a
canonical fault generates a #GP (instead of an #SS). In 64-bit mode, only FS and GS segment-overrides are applicable in this situation. Other segment override prefixes (CS, DS, ES and SS) are ignored. Note that this also means
that an SS segment-override applied to a “non-stack” register reference is ignored. Such a sequence still produces
a #GP for a canonical fault (and not an #SS).
3.4
BASIC PROGRAM EXECUTION REGISTERS
IA-32 architecture provides 16 basic program execution registers for use in general system and application
programing (see Figure 3-4). These registers can be grouped as follows:
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•
•
•
General-purpose registers. These eight registers are available for storing operands and pointers.
•
EIP (instruction pointer) register. The EIP register contains a 32-bit pointer to the next instruction to be
executed.
Segment registers. These registers hold up to six segment selectors.
EFLAGS (program status and control) register. The EFLAGS register report on the status of the program
being executed and allows limited (application-program level) control of the processor.
3.4.1
General-Purpose Registers
The 32-bit general-purpose registers EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP are provided for holding the
following items:
•
•
•
Operands for logical and arithmetic operations
Operands for address calculations
Memory pointers
Although all of these registers are available for general storage of operands, results, and pointers, caution should
be used when referencing the ESP register. The ESP register holds the stack pointer and as a general rule should
not be used for another purpose.
Many instructions assign specific registers to hold operands. For example, string instructions use the contents of
the ECX, ESI, and EDI registers as operands. When using a segmented memory model, some instructions assume
that pointers in certain registers are relative to specific segments. For instance, some instructions assume that a
pointer in the EBX register points to a memory location in the DS segment.
31
General-Purpose Registers
0
EAX
EBX
ECX
EDX
ESI
EDI
EBP
ESP
Segment Registers
0
15
CS
DS
SS
ES
FS
GS
Program Status and Control Register
0
31
EFLAGS
31
Instruction Pointer
0
EIP
Figure 3-4. General System and Application Programming Registers
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The special uses of general-purpose registers by instructions are described in Chapter 5, “Instruction Set
Summary,” in this volume. See also: Chapter 3, Chapter 4 and Chapter 5 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B & 2C. The following is a summary of special uses:
•
•
•
•
•
•
EAX — Accumulator for operands and results data
•
•
ESP — Stack pointer (in the SS segment)
EBX — Pointer to data in the DS segment
ECX — Counter for string and loop operations
EDX — I/O pointer
ESI — Pointer to data in the segment pointed to by the DS register; source pointer for string operations
EDI — Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for
string operations
EBP — Pointer to data on the stack (in the SS segment)
As shown in Figure 3-5, the lower 16 bits of the general-purpose registers map directly to the register set found in
the 8086 and Intel 286 processors and can be referenced with the names AX, BX, CX, DX, BP, SI, DI, and SP. Each
of the lower two bytes of the EAX, EBX, ECX, and EDX registers can be referenced by the names AH, BH, CH, and
DH (high bytes) and AL, BL, CL, and DL (low bytes).
31
General-Purpose Registers
8 7
16 15
0 16-bit 32-bit
AH
AL
AX
EAX
BH
BL
BX
EBX
CH
CL
CX
ECX
DH
DL
DX
BP
EDX
EBP
SI
ESI
DI
EDI
SP
ESP
Figure 3-5. Alternate General-Purpose Register Names
3.4.1.1
General-Purpose Registers in 64-Bit Mode
In 64-bit mode, there are 16 general purpose registers and the default operand size is 32 bits. However, generalpurpose registers are able to work with either 32-bit or 64-bit operands. If a 32-bit operand size is specified: EAX,
EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D - R15D are available. If a 64-bit operand size is specified: RAX, RBX, RCX,
RDX, RDI, RSI, RBP, RSP, R8-R15 are available. R8D-R15D/R8-R15 represent eight new general-purpose registers.
All of these registers can be accessed at the byte, word, dword, and qword level. REX prefixes are used to generate
64-bit operand sizes or to reference registers R8-R15.
Registers only available in 64-bit mode (R8-R15 and XMM8-XMM15) are preserved across transitions from 64-bit
mode into compatibility mode then back into 64-bit mode. However, values of R8-R15 and XMM8-XMM15 are undefined after transitions from 64-bit mode through compatibility mode to legacy or real mode and then back through
compatibility mode to 64-bit mode.
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Table 3-2. Addressable General Purpose Registers
Register Type
Without REX
With REX
Byte Registers
AL, BL, CL, DL, AH, BH, CH, DH
AL, BL, CL, DL, DIL, SIL, BPL, SPL, R8L - R15L
Word Registers
AX, BX, CX, DX, DI, SI, BP, SP
AX, BX, CX, DX, DI, SI, BP, SP, R8W - R15W
Doubleword Registers
EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP
EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D - R15D
Quadword Registers
N.A.
RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8 - R15
In 64-bit mode, there are limitations on accessing byte registers. An instruction cannot reference legacy highbytes (for example: AH, BH, CH, DH) and one of the new byte registers at the same time (for example: the low
byte of the RAX register). However, instructions may reference legacy low-bytes (for example: AL, BL, CL or DL)
and new byte registers at the same time (for example: the low byte of the R8 register, or RBP). The architecture
enforces this limitation by changing high-byte references (AH, BH, CH, DH) to low byte references (BPL, SPL, DIL,
SIL: the low 8 bits for RBP, RSP, RDI and RSI) for instructions using a REX prefix.
When in 64-bit mode, operand size determines the number of valid bits in the destination general-purpose
register:
•
•
64-bit operands generate a 64-bit result in the destination general-purpose register.
•
8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the
destination general-purpose register are not modified by the operation. If the result of an 8-bit or 16-bit
operation is intended for 64-bit address calculation, explicitly sign-extend the register to the full 64-bits.
32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose
register.
Because the upper 32 bits of 64-bit general-purpose registers are undefined in 32-bit modes, the upper 32 bits of
any general-purpose register are not preserved when switching from 64-bit mode to a 32-bit mode (to protected
mode or compatibility mode). Software must not depend on these bits to maintain a value after a 64-bit to 32-bit
mode switch.
3.4.2
Segment Registers
The segment registers (CS, DS, SS, ES, FS, and GS) hold 16-bit segment selectors. A segment selector is a special
pointer that identifies a segment in memory. To access a particular segment in memory, the segment selector for
that segment must be present in the appropriate segment register.
When writing application code, programmers generally create segment selectors with assembler directives and
symbols. The assembler and other tools then create the actual segment selector values associated with these
directives and symbols. If writing system code, programmers may need to create segment selectors directly. See
Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
How segment registers are used depends on the type of memory management model that the operating system or
executive is using. When using the flat (unsegmented) memory model, segment registers are loaded with segment
selectors that point to overlapping segments, each of which begins at address 0 of the linear address space (see
Figure 3-6). These overlapping segments then comprise the linear address space for the program. Typically, two
overlapping segments are defined: one for code and another for data and stacks. The CS segment register points
to the code segment and all the other segment registers point to the data and stack segment.
When using the segmented memory model, each segment register is ordinarily loaded with a different segment
selector so that each segment register points to a different segment within the linear address space (see
Figure 3-7). At any time, a program can thus access up to six segments in the linear address space. To access a
segment not pointed to by one of the segment registers, a program must first load the segment selector for the
segment to be accessed into a segment register.
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Linear Address
Space for Program
Segment Registers
CS
DS
SS
ES
FS
GS
The segment selector in
each segment register
points to an overlapping
segment in the linear
address space.
Overlapping
Segments
of up to
4 GBytes
Beginning at
Address 0
Figure 3-6. Use of Segment Registers for Flat Memory Model
Code
Segment
Segment Registers
CS
DS
SS
ES
FS
GS
Data
Segment
Stack
Segment
All segments
are mapped
to the same
linear-address
space
Data
Segment
Data
Segment
Data
Segment
Figure 3-7. Use of Segment Registers in Segmented Memory Model
Each of the segment registers is associated with one of three types of storage: code, data, or stack. For example,
the CS register contains the segment selector for the code segment, where the instructions being executed are
stored. The processor fetches instructions from the code segment, using a logical address that consists of the
segment selector in the CS register and the contents of the EIP register. The EIP register contains the offset within
the code segment of the next instruction to be executed. The CS register cannot be loaded explicitly by an application program. Instead, it is loaded implicitly by instructions or internal processor operations that change program
control (such as, procedure calls, interrupt handling, or task switching).
The DS, ES, FS, and GS registers point to four data segments. The availability of four data segments permits efficient and secure access to different types of data structures. For example, four separate data segments might be
created: one for the data structures of the current module, another for the data exported from a higher-level
module, a third for a dynamically created data structure, and a fourth for data shared with another program. To
access additional data segments, the application program must load segment selectors for these segments into the
DS, ES, FS, and GS registers, as needed.
The SS register contains the segment selector for the stack segment, where the procedure stack is stored for the
program, task, or handler currently being executed. All stack operations use the SS register to find the stack
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segment. Unlike the CS register, the SS register can be loaded explicitly, which permits application programs to set
up multiple stacks and switch among them.
See Section 3.3, “Memory Organization,” for an overview of how the segment registers are used in real-address
mode.
The four segment registers CS, DS, SS, and ES are the same as the segment registers found in the Intel 8086 and
Intel 286 processors and the FS and GS registers were introduced into the IA-32 Architecture with the Intel386™
family of processors.
3.4.2.1
Segment Registers in 64-Bit Mode
In 64-bit mode: CS, DS, ES, SS are treated as if each segment base is 0, regardless of the value of the associated
segment descriptor base. This creates a flat address space for code, data, and stack. FS and GS are exceptions.
Both segment registers may be used as additional base registers in linear address calculations (in the addressing
of local data and certain operating system data structures).
Even though segmentation is generally disabled, segment register loads may cause the processor to perform
segment access assists. During these activities, enabled processors will still perform most of the legacy checks on
loaded values (even if the checks are not applicable in 64-bit mode). Such checks are needed because a segment
register loaded in 64-bit mode may be used by an application running in compatibility mode.
Limit checks for CS, DS, ES, SS, FS, and GS are disabled in 64-bit mode.
3.4.3
EFLAGS Register
The 32-bit EFLAGS register contains a group of status flags, a control flag, and a group of system flags. Figure 3-8
defines the flags within this register. Following initialization of the processor (either by asserting the RESET pin or
the INIT pin), the state of the EFLAGS register is 00000002H. Bits 1, 3, 5, 15, and 22 through 31 of this register
are reserved. Software should not use or depend on the states of any of these bits.
Some of the flags in the EFLAGS register can be modified directly, using special-purpose instructions (described in
the following sections). There are no instructions that allow the whole register to be examined or modified directly.
The following instructions can be used to move groups of flags to and from the procedure stack or the EAX register:
LAHF, SAHF, PUSHF, PUSHFD, POPF, and POPFD. After the contents of the EFLAGS register have been transferred to
the procedure stack or EAX register, the flags can be examined and modified using the processor’s bit manipulation
instructions (BT, BTS, BTR, and BTC).
When suspending a task (using the processor’s multitasking facilities), the processor automatically saves the state
of the EFLAGS register in the task state segment (TSS) for the task being suspended. When binding itself to a new
task, the processor loads the EFLAGS register with data from the new task’s TSS.
When a call is made to an interrupt or exception handler procedure, the processor automatically saves the state of
the EFLAGS registers on the procedure stack. When an interrupt or exception is handled with a task switch, the
state of the EFLAGS register is saved in the TSS for the task being suspended.
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V V
I I I A V R 0 N
0 0 0 0 0 0 0 0 0 0
T
C M F
D
P F
X
X
X
X
X
X
X
X
S
C
X
X
S
S
S
S
S
I
O
P
L
O D I T S Z
P
C
A
F F F F F F 0 F 0 F 1 F
ID Flag (ID)
Virtual Interrupt Pending (VIP)
Virtual Interrupt Flag (VIF)
Alignment Check / Access Control (AC)
Virtual-8086 Mode (VM)
Resume Flag (RF)
Nested Task (NT)
I/O Privilege Level (IOPL)
Overflow Flag (OF)
Direction Flag (DF)
Interrupt Enable Flag (IF)
Trap Flag (TF)
Sign Flag (SF)
Zero Flag (ZF)
Auxiliary Carry Flag (AF)
Parity Flag (PF)
Carry Flag (CF)
S Indicates a Status Flag
C Indicates a Control Flag
X Indicates a System Flag
Reserved bit positions. DO NOT USE.
Always set to values previously read.
Figure 3-8. EFLAGS Register
As the IA-32 Architecture has evolved, flags have been added to the EFLAGS register, but the function and placement of existing flags have remained the same from one family of the IA-32 processors to the next. As a result,
code that accesses or modifies these flags for one family of IA-32 processors works as expected when run on later
families of processors.
3.4.3.1
Status Flags
The status flags (bits 0, 2, 4, 6, 7, and 11) of the EFLAGS register indicate the results of arithmetic instructions,
such as the ADD, SUB, MUL, and DIV instructions. The status flag functions are:
CF (bit 0)
Carry flag — Set if an arithmetic operation generates a carry or a borrow out of the mostsignificant bit of the result; cleared otherwise. This flag indicates an overflow condition for
unsigned-integer arithmetic. It is also used in multiple-precision arithmetic.
PF (bit 2)
Parity flag — Set if the least-significant byte of the result contains an even number of 1 bits;
cleared otherwise.
AF (bit 4)
Auxiliary Carry flag — Set if an arithmetic operation generates a carry or a borrow out of bit
3 of the result; cleared otherwise. This flag is used in binary-coded decimal (BCD) arithmetic.
ZF (bit 6)
Zero flag — Set if the result is zero; cleared otherwise.
SF (bit 7)
Sign flag — Set equal to the most-significant bit of the result, which is the sign bit of a signed
integer. (0 indicates a positive value and 1 indicates a negative value.)
OF (bit 11)
Overflow flag — Set if the integer result is too large a positive number or too small a negative
number (excluding the sign-bit) to fit in the destination operand; cleared otherwise. This flag
indicates an overflow condition for signed-integer (two’s complement) arithmetic.
Of these status flags, only the CF flag can be modified directly, using the STC, CLC, and CMC instructions. Also the
bit instructions (BT, BTS, BTR, and BTC) copy a specified bit into the CF flag.
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The status flags allow a single arithmetic operation to produce results for three different data types: unsigned integers, signed integers, and BCD integers. If the result of an arithmetic operation is treated as an unsigned integer,
the CF flag indicates an out-of-range condition (carry or a borrow); if treated as a signed integer (two’s complement number), the OF flag indicates a carry or borrow; and if treated as a BCD digit, the AF flag indicates a carry
or borrow. The SF flag indicates the sign of a signed integer. The ZF flag indicates either a signed- or an unsignedinteger zero.
When performing multiple-precision arithmetic on integers, the CF flag is used in conjunction with the add with
carry (ADC) and subtract with borrow (SBB) instructions to propagate a carry or borrow from one computation to
the next.
The condition instructions Jcc (jump on condition code cc), SETcc (byte set on condition code cc), LOOPcc, and
CMOVcc (conditional move) use one or more of the status flags as condition codes and test them for branch, setbyte, or end-loop conditions.
3.4.3.2
DF Flag
The direction flag (DF, located in bit 10 of the EFLAGS register) controls string instructions (MOVS, CMPS, SCAS,
LODS, and STOS). Setting the DF flag causes the string instructions to auto-decrement (to process strings from
high addresses to low addresses). Clearing the DF flag causes the string instructions to auto-increment
(process strings from low addresses to high addresses).
The STD and CLD instructions set and clear the DF flag, respectively.
3.4.3.3
System Flags and IOPL Field
The system flags and IOPL field in the EFLAGS register control operating-system or executive operations. They
should not be modified by application programs. The functions of the system flags are as follows:
TF (bit 8)
Trap flag — Set to enable single-step mode for debugging; clear to disable single-step mode.
IF (bit 9)
Interrupt enable flag — Controls the response of the processor to maskable interrupt
requests. Set to respond to maskable interrupts; cleared to inhibit maskable interrupts.
IOPL (bits 12 and 13)
I/O privilege level field — Indicates the I/O privilege level of the currently running program
or task. The current privilege level (CPL) of the currently running program or task must be less
than or equal to the I/O privilege level to access the I/O address space. The POPF and IRET
instructions can modify this field only when operating at a CPL of 0.
NT (bit 14)
Nested task flag — Controls the chaining of interrupted and called tasks. Set when the
current task is linked to the previously executed task; cleared when the current task is not
linked to another task.
RF (bit 16)
Resume flag — Controls the processor’s response to debug exceptions.
VM (bit 17)
Virtual-8086 mode flag — Set to enable virtual-8086 mode; clear to return to protected
mode without virtual-8086 mode semantics.
AC (bit 18)
Alignment check (or access control) flag — If the AM bit is set in the CR0 register, alignment checking of user-mode data accesses is enabled if and only if this flag is 1.
If the SMAP bit is set in the CR4 register, explicit supervisor-mode data accesses to user-mode
pages are allowed if and only if this bit is 1. See Section 4.6, “Access Rights,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3A.
VIF (bit 19)
Virtual interrupt flag — Virtual image of the IF flag. Used in conjunction with the VIP flag.
(To use this flag and the VIP flag the virtual mode extensions are enabled by setting the VME
flag in control register CR4.)
VIP (bit 20)
Virtual interrupt pending flag — Set to indicate that an interrupt is pending; clear when no
interrupt is pending. (Software sets and clears this flag; the processor only reads it.) Used in
conjunction with the VIF flag.
ID (bit 21)
Identification flag — The ability of a program to set or clear this flag indicates support for
the CPUID instruction.
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For a detailed description of these flags: see Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3A.
3.4.3.4
RFLAGS Register in 64-Bit Mode
In 64-bit mode, EFLAGS is extended to 64 bits and called RFLAGS. The upper 32 bits of RFLAGS register is
reserved. The lower 32 bits of RFLAGS is the same as EFLAGS.
3.5
INSTRUCTION POINTER
The instruction pointer (EIP) register contains the offset in the current code segment for the next instruction to be
executed. It is advanced from one instruction boundary to the next in straight-line code or it is moved ahead or
backwards by a number of instructions when executing JMP, Jcc, CALL, RET, and IRET instructions.
The EIP register cannot be accessed directly by software; it is controlled implicitly by control-transfer instructions
(such as JMP, Jcc, CALL, and RET), interrupts, and exceptions. The only way to read the EIP register is to execute a
CALL instruction and then read the value of the return instruction pointer from the procedure stack. The EIP
register can be loaded indirectly by modifying the value of a return instruction pointer on the procedure stack and
executing a return instruction (RET or IRET). See Section 6.2.4.2, “Return Instruction Pointer.”
All IA-32 processors prefetch instructions. Because of instruction prefetching, an instruction address read from the
bus during an instruction load does not match the value in the EIP register. Even though different processor generations use different prefetching mechanisms, the function of the EIP register to direct program flow remains fully
compatible with all software written to run on IA-32 processors.
3.5.1
Instruction Pointer in 64-Bit Mode
In 64-bit mode, the RIP register becomes the instruction pointer. This register holds the 64-bit offset of the next
instruction to be executed. 64-bit mode also supports a technique called RIP-relative addressing. Using this technique, the effective address is determined by adding a displacement to the RIP of the next instruction.
3.6
OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES
When the processor is executing in protected mode, every code segment has a default operand-size attribute and
address-size attribute. These attributes are selected with the D (default size) flag in the segment descriptor for the
code segment (see Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A). When the D flag is set, the 32-bit operand-size and address-size attributes are selected; when the flag is clear, the 16-bit size attributes are selected. When the processor is executing
in real-address mode, virtual-8086 mode, or SMM, the default operand-size and address-size attributes are always
16 bits.
The operand-size attribute selects the size of operands. When the 16-bit operand-size attribute is in force, operands can generally be either 8 bits or 16 bits, and when the 32-bit operand-size attribute is in force, operands can
generally be 8 bits or 32 bits.
The address-size attribute selects the sizes of addresses used to address memory: 16 bits or 32 bits. When the 16bit address-size attribute is in force, segment offsets and displacements are 16 bits. This restriction limits the size
of a segment to 64 KBytes. When the 32-bit address-size attribute is in force, segment offsets and displacements
are 32 bits, allowing up to 4 GBytes to be addressed.
The default operand-size attribute and/or address-size attribute can be overridden for a particular instruction by
adding an operand-size and/or address-size prefix to an instruction. See Chapter 2, “Instruction Format,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. The effect of this prefix applies only
to the targeted instruction.
Table 3-4 shows effective operand size and address size (when executing in protected mode or compatibility mode)
depending on the settings of the D flag and the operand-size and address-size prefixes.
3-18 Vol. 1
BASIC EXECUTION ENVIRONMENT
Table 3-3. Effective Operand- and Address-Size Attributes
D Flag in Code Segment Descriptor
0
0
0
0
1
1
1
1
Operand-Size Prefix 66H
N
N
Y
Y
N
N
Y
Y
Address-Size Prefix 67H
N
Y
N
Y
N
Y
N
Y
Effective Operand Size
16
16
32
32
32
32
16
16
Effective Address Size
16
32
16
32
32
16
32
16
NOTES:
Y: Yes - this instruction prefix is present.
N: No - this instruction prefix is not present.
3.6.1
Operand Size and Address Size in 64-Bit Mode
In 64-bit mode, the default address size is 64 bits and the default operand size is 32 bits. Defaults can be overridden using prefixes. Address-size and operand-size prefixes allow mixing of 32/64-bit data and 32/64-bit
addresses on an instruction-by-instruction basis. Table 3-4 shows valid combinations of the 66H instruction prefix
and the REX.W prefix that may be used to specify operand-size overrides in 64-bit mode. Note that 16-bit
addresses are not supported in 64-bit mode.
REX prefixes consist of 4-bit fields that form 16 different values. The W-bit field in the REX prefixes is referred to as
REX.W. If the REX.W field is properly set, the prefix specifies an operand size override to 64 bits. Note that software
can still use the operand-size 66H prefix to toggle to a 16-bit operand size. However, setting REX.W takes precedence over the operand-size prefix (66H) when both are used.
In the case of SSE/SSE2/SSE3/SSSE3 SIMD instructions: the 66H, F2H, and F3H prefixes are mandatory for
opcode extensions. In such a case, there is no interaction between a valid REX.W prefix and a 66H opcode extension prefix.
See Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
Table 3-4. Effective Operand- and Address-Size Attributes in 64-Bit Mode
L Flag in Code Segment Descriptor
1
1
1
1
1
1
1
1
REX.W Prefix
0
0
0
0
1
1
1
1
Operand-Size Prefix 66H
N
N
Y
Y
N
N
Y
Y
Address-Size Prefix 67H
N
Y
N
Y
N
Y
N
Y
Effective Operand Size
32
32
16
16
64
64
64
64
Effective Address Size
64
32
64
32
64
32
64
32
NOTES:
Y: Yes - this instruction prefix is present.
N: No - this instruction prefix is not present.
3.7
OPERAND ADDRESSING
IA-32 machine-instructions act on zero or more operands. Some operands are specified explicitly and others are
implicit. The data for a source operand can be located in:
•
•
•
•
the instruction itself (an immediate operand)
a register
a memory location
an I/O port
Vol. 1 3-19
BASIC EXECUTION ENVIRONMENT
When an instruction returns data to a destination operand, it can be returned to:
•
•
•
a register
a memory location
an I/O port
3.7.1
Immediate Operands
Some instructions use data encoded in the instruction itself as a source operand. These operands are called immediate operands (or simply immediates). For example, the following ADD instruction adds an immediate value of 14
to the contents of the EAX register:
ADD EAX, 14
All arithmetic instructions (except the DIV and IDIV instructions) allow the source operand to be an immediate
value. The maximum value allowed for an immediate operand varies among instructions, but can never be greater
than the maximum value of an unsigned doubleword integer (232).
3.7.2
Register Operands
Source and destination operands can be any of the following registers, depending on the instruction being
executed:
•
•
•
•
•
•
32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP)
•
•
•
MMX registers (MM0 through MM7)
•
•
debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)
16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP)
8-bit general-purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL)
segment registers (CS, DS, SS, ES, FS, and GS)
EFLAGS register
x87 FPU registers (ST0 through ST7, status word, control word, tag word, data operand pointer, and instruction
pointer)
XMM registers (XMM0 through XMM7) and the MXCSR register
control registers (CR0, CR2, CR3, and CR4) and system table pointer registers (GDTR, LDTR, IDTR, and task
register)
MSR registers
Some instructions (such as the DIV and MUL instructions) use quadword operands contained in a pair of 32-bit
registers. Register pairs are represented with a colon separating them. For example, in the register pair EDX:EAX,
EDX contains the high order bits and EAX contains the low order bits of a quadword operand.
Several instructions (such as the PUSHFD and POPFD instructions) are provided to load and store the contents of
the EFLAGS register or to set or clear individual flags in this register. Other instructions (such as the Jcc instructions) use the state of the status flags in the EFLAGS register as condition codes for branching or other decision
making operations.
The processor contains a selection of system registers that are used to control memory management, interrupt and
exception handling, task management, processor management, and debugging activities. Some of these system
registers are accessible by an application program, the operating system, or the executive through a set of system
instructions. When accessing a system register with a system instruction, the register is generally an implied
operand of the instruction.
3-20 Vol. 1
BASIC EXECUTION ENVIRONMENT
3.7.2.1
Register Operands in 64-Bit Mode
Register operands in 64-bit mode can be any of the following:
•
•
•
•
64-bit general-purpose registers (RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, or R8-R15)
•
•
•
Segment registers (CS, DS, SS, ES, FS, and GS)
•
•
•
MMX registers (MM0 through MM7)
•
•
•
Debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)
32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP, or R8D-R15D)
16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, BP, or R8W-R15W)
8-bit general-purpose registers: AL, BL, CL, DL, SIL, DIL, SPL, BPL, and R8L-R15L are available using REX
prefixes; AL, BL, CL, DL, AH, BH, CH, DH are available without using REX prefixes.
RFLAGS register
x87 FPU registers (ST0 through ST7, status word, control word, tag word, data operand pointer, and instruction
pointer)
XMM registers (XMM0 through XMM15) and the MXCSR register
Control registers (CR0, CR2, CR3, CR4, and CR8) and system table pointer registers (GDTR, LDTR, IDTR, and
task register)
MSR registers
RDX:RAX register pair representing a 128-bit operand
3.7.3
Memory Operands
Source and destination operands in memory are referenced by means of a segment selector and an offset (see
Figure 3-9). Segment selectors specify the segment containing the operand. Offsets specify the linear or effective
address of the operand. Offsets can be 32 bits (represented by the notation m16:32) or 16 bits (represented by the
notation m16:16).
15
Segment
Selector
0
31
0
Offset (or Linear Address)
Figure 3-9. Memory Operand Address
3.7.3.1
Memory Operands in 64-Bit Mode
In 64-bit mode, a memory operand can be referenced by a segment selector and an offset. The offset can be 16
bits, 32 bits or 64 bits (see Figure 3-10).
15
Segment
Selector
0
63
0
Offset (or Linear Address)
Figure 3-10. Memory Operand Address in 64-Bit Mode
3.7.4
Specifying a Segment Selector
The segment selector can be specified either implicitly or explicitly. The most common method of specifying a
segment selector is to load it in a segment register and then allow the processor to select the register implicitly,
depending on the type of operation being performed. The processor automatically chooses a segment according to
the rules given in Table 3-5.
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BASIC EXECUTION ENVIRONMENT
When storing data in memory or loading data from memory, the DS segment default can be overridden to allow
other segments to be accessed. Within an assembler, the segment override is generally handled with a colon “:”
operator. For example, the following MOV instruction moves a value from register EAX into the segment pointed to
by the ES register. The offset into the segment is contained in the EBX register:
MOV ES:[EBX], EAX;
Table 3-5. Default Segment Selection Rules
Reference Type
Register Used Segment Used
Default Selection Rule
Instructions
CS
Code Segment
All instruction fetches.
Stack
SS
Stack Segment
All stack pushes and pops.
Any memory reference which uses the ESP or EBP register as a base
register.
Local Data
DS
Data Segment
All data references, except when relative to stack or string destination.
Data Segment
pointed to with the
ES register
Destination of string instructions.
Destination Strings ES
At the machine level, a segment override is specified with a segment-override prefix, which is a byte placed at the
beginning of an instruction. The following default segment selections cannot be overridden:
•
•
•
Instruction fetches must be made from the code segment.
Destination strings in string instructions must be stored in the data segment pointed to by the ES register.
Push and pop operations must always reference the SS segment.
Some instructions require a segment selector to be specified explicitly. In these cases, the 16-bit segment selector
can be located in a memory location or in a 16-bit register. For example, the following MOV instruction moves a
segment selector located in register BX into segment register DS:
MOV DS, BX
Segment selectors can also be specified explicitly as part of a 48-bit far pointer in memory. Here, the first doubleword in memory contains the offset and the next word contains the segment selector.
3.7.4.1
Segmentation in 64-Bit Mode
In IA-32e mode, the effects of segmentation depend on whether the processor is running in compatibility mode or
64-bit mode. In compatibility mode, segmentation functions just as it does in legacy IA-32 mode, using the 16-bit
or 32-bit protected mode semantics described above.
In 64-bit mode, segmentation is generally (but not completely) disabled, creating a flat 64-bit linear-address
space. The processor treats the segment base of CS, DS, ES, SS as zero, creating a linear address that is equal to
the effective address. The exceptions are the FS and GS segments, whose segment registers (which hold the
segment base) can be used as additional base registers in some linear address calculations.
3.7.5
Specifying an Offset
The offset part of a memory address can be specified directly as a static value (called a displacement) or through
an address computation made up of one or more of the following components:
•
•
•
•
Displacement — An 8-, 16-, or 32-bit value.
Base — The value in a general-purpose register.
Index — The value in a general-purpose register.
Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.
3-22 Vol. 1
BASIC EXECUTION ENVIRONMENT
The offset which results from adding these components is called an effective address. Each of these components
can have either a positive or negative (2s complement) value, with the exception of the scaling factor. Figure 3-11
shows all the possible ways that these components can be combined to create an effective address in the selected
segment.
Base
Index
EAX
EBX
ECX
EDX
ESP
EBP
ESI
EDI
EAX
EBX
ECX
EDX
EBP
ESI
EDI
+
Scale
Displacement
1
None
2
*
4
8
+
8-bit
16-bit
32-bit
Offset = Base + (Index * Scale) + Displacement
Figure 3-11. Offset (or Effective Address) Computation
The uses of general-purpose registers as base or index components are restricted in the following manner:
•
•
The ESP register cannot be used as an index register.
When the ESP or EBP register is used as the base, the SS segment is the default segment. In all other cases,
the DS segment is the default segment.
The base, index, and displacement components can be used in any combination, and any of these components can
be NULL. A scale factor may be used only when an index also is used. Each possible combination is useful for data
structures commonly used by programmers in high-level languages and assembly language.
The following addressing modes suggest uses for common combinations of address components.
•
Displacement ⎯ A displacement alone represents a direct (uncomputed) offset to the operand. Because the
displacement is encoded in the instruction, this form of an address is sometimes called an absolute or static
address. It is commonly used to access a statically allocated scalar operand.
•
Base ⎯ A base alone represents an indirect offset to the operand. Since the value in the base register can
change, it can be used for dynamic storage of variables and data structures.
•
Base + Displacement ⎯ A base register and a displacement can be used together for two distinct purposes:
— As an index into an array when the element size is not 2, 4, or 8 bytes—The displacement component
encodes the static offset to the beginning of the array. The base register holds the results of a calculation
to determine the offset to a specific element within the array.
— To access a field of a record: the base register holds the address of the beginning of the record, while the
displacement is a static offset to the field.
An important special case of this combination is access to parameters in a procedure activation record. A
procedure activation record is the stack frame created when a procedure is entered. Here, the EBP register is
the best choice for the base register, because it automatically selects the stack segment. This is a compact
encoding for this common function.
•
(Index ∗ Scale) + Displacement ⎯ This address mode offers an efficient way to index into a static array
when the element size is 2, 4, or 8 bytes. The displacement locates the beginning of the array, the index
register holds the subscript of the desired array element, and the processor automatically converts the
subscript into an index by applying the scaling factor.
•
Base + Index + Displacement ⎯ Using two registers together supports either a two-dimensional array (the
displacement holds the address of the beginning of the array) or one of several instances of an array of records
(the displacement is an offset to a field within the record).
•
Base + (Index ∗ Scale) + Displacement ⎯ Using all the addressing components together allows efficient
indexing of a two-dimensional array when the elements of the array are 2, 4, or 8 bytes in size.
Vol. 1 3-23
BASIC EXECUTION ENVIRONMENT
3.7.5.1
Specifying an Offset in 64-Bit Mode
The offset part of a memory address in 64-bit mode can be specified directly as a static value or through an address
computation made up of one or more of the following components:
•
•
•
•
Displacement — An 8-bit, 16-bit, or 32-bit value.
Base — The value in a 64-bit general-purpose register.
Index — The value in a 64-bit general-purpose register.
Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.
The base and index value can be specified in one of sixteen available general-purpose registers in most cases. See
Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
The following unique combination of address components is also available.
•
RIP + Displacement ⎯ In 64-bit mode, RIP-relative addressing uses a signed 32-bit displacement to
calculate the effective address of the next instruction by sign-extend the 32-bit value and add to the 64-bit
value in RIP.
3.7.6
Assembler and Compiler Addressing Modes
At the machine-code level, the selected combination of displacement, base register, index register, and scale factor
is encoded in an instruction. All assemblers permit a programmer to use any of the allowable combinations of these
addressing components to address operands. High-level language compilers will select an appropriate combination
of these components based on the language construct a programmer defines.
3.7.7
I/O Port Addressing
The processor supports an I/O address space that contains up to 65,536 8-bit I/O ports. Ports that are 16-bit and
32-bit may also be defined in the I/O address space. An I/O port can be addressed with either an immediate
operand or a value in the DX register. See Chapter 18, “Input/Output,” for more information about I/O port
addressing.
3-24 Vol. 1
CHAPTER 4
DATA TYPES
This chapter introduces data types defined for the Intel 64 and IA-32 architectures. A section at the end of this
chapter describes the real-number and floating-point concepts used in x87 FPU, SSE, SSE2, SSE3, SSSE3, SSE4
and Intel AVX extensions.
4.1
FUNDAMENTAL DATA TYPES
The fundamental data types are bytes, words, doublewords, quadwords, and double quadwords (see Figure 4-1).
A byte is eight bits, a word is 2 bytes (16 bits), a doubleword is 4 bytes (32 bits), a quadword is 8 bytes (64 bits),
and a double quadword is 16 bytes (128 bits). A subset of the IA-32 architecture instructions operates on these
fundamental data types without any additional operand typing.
7
0
Byte
N
15 8 7 0
High Low
Byte Byte Word
N+1 N
31
0
16 15
High Word Low Word Doubleword
N+2
63
High Doubleword
0
Low Doubleword
N+4
127
N
32 31
Quadword
N
64 63
High Quadword
0
Low Quadword
N+8
Double
Quadword
N
Figure 4-1. Fundamental Data Types
The quadword data type was introduced into the IA-32 architecture in the Intel486 processor; the double quadword
data type was introduced in the Pentium III processor with the SSE extensions.
Figure 4-2 shows the byte order of each of the fundamental data types when referenced as operands in memory.
The low byte (bits 0 through 7) of each data type occupies the lowest address in memory and that address is also
the address of the operand.
Vol. 1 4-1
DATA TYPES
Word at Address BH
Contains FE06H
Byte at Address 9H
Contains 1FH
Word at Address 6H
Contains 230BH
Word at Address 2H
Contains 74CBH
Word at Address 1H
Contains CB31H
4EH
FH
12H
EH
7AH
DH
FEH
CH
06H
BH
36H
AH
1FH
9H
A4H
8H
23H
7H
0BH
6H
45H
5H
67H
4H
74H
3H
CBH
2H
31H
1H
12H
0H
Doubleword at Address AH
Contains 7AFE0636H
Quadword at Address 6H
Contains
7AFE06361FA4230BH
Double quadword at Address 0H
Contains
4E127AFE06361FA4230B456774CB3112
Figure 4-2. Bytes, Words, Doublewords, Quadwords, and Double Quadwords in Memory
4.1.1
Alignment of Words, Doublewords, Quadwords, and Double Quadwords
Words, doublewords, and quadwords do not need to be aligned in memory on natural boundaries. The natural
boundaries for words, double words, and quadwords are even-numbered addresses, addresses evenly divisible by
four, and addresses evenly divisible by eight, respectively. However, to improve the performance of programs, data
structures (especially stacks) should be aligned on natural boundaries whenever possible. The reason for this is
that the processor requires two memory accesses to make an unaligned memory access; aligned accesses require
only one memory access. A word or doubleword operand that crosses a 4-byte boundary or a quadword operand
that crosses an 8-byte boundary is considered unaligned and requires two separate memory bus cycles for access.
Some instructions that operate on double quadwords require memory operands to be aligned on a natural
boundary. These instructions generate a general-protection exception (#GP) if an unaligned operand is specified. A
natural boundary for a double quadword is any address evenly divisible by 16. Other instructions that operate on
double quadwords permit unaligned access (without generating a general-protection exception). However, additional memory bus cycles are required to access unaligned data from memory.
4.2
NUMERIC DATA TYPES
Although bytes, words, and doublewords are fundamental data types, some instructions support additional interpretations of these data types to allow operations to be performed on numeric data types (signed and unsigned
integers, and floating-point numbers). Single-precision (32-bit) floating-point and double-precision (64-bit)
floating-point data types are supported across all generations of SSE extensions and Intel AVX extensions. Halfprecision (16-bit) floating-point data type is supported only with F16C extensions (VCVTPH2PS, VCVTPS2PH). See
Figure 4-3.
4-2 Vol. 1
DATA TYPES
Byte Unsigned Integer
7
0
Word Unsigned Integer
15
0
Doubleword Unsigned Integer
31
0
Quadword Unsigned Integer
63
0
Sign
Byte Signed Integer
76
0
Sign
Word Signed Integer
0
15 14
Sign
Doubleword Signed Integer
0
31 30
Sign
Quadword Signed Integer
63 62
0
Sign
15 14
Sign
31 30
9
23 22
0
0
Sign
Sign
79 78
63 62
52 51
Integer Bit
0
0
64 63 62
Half Precision
Floating Point
Single Precision
Floating Point
Double Precision
Floating Point
Double Extended Precision
Floating Point
Figure 4-3. Numeric Data Types
4.2.1
Integers
The Intel 64 and IA-32 architectures define two types of integers: unsigned and signed. Unsigned integers are ordinary binary values ranging from 0 to the maximum positive number that can be encoded in the selected operand
size. Signed integers are two’s complement binary values that can be used to represent both positive and negative
integer values.
Some integer instructions (such as the ADD, SUB, PADDB, and PSUBB instructions) operate on either unsigned or
signed integer operands. Other integer instructions (such as IMUL, MUL, IDIV, DIV, FIADD, and FISUB) operate on
only one integer type.
The following sections describe the encodings and ranges of the two types of integers.
4.2.1.1
Unsigned Integers
Unsigned integers are unsigned binary numbers contained in a byte, word, doubleword, and quadword. Their
values range from 0 to 255 for an unsigned byte integer, from 0 to 65,535 for an unsigned word integer, from 0
Vol. 1 4-3
DATA TYPES
to 232 – 1 for an unsigned doubleword integer, and from 0 to 264 – 1 for an unsigned quadword integer. Unsigned
integers are sometimes referred to as ordinals.
4.2.1.2
Signed Integers
Signed integers are signed binary numbers held in a byte, word, doubleword, or quadword. All operations on signed
integers assume a two's complement representation. The sign bit is located in bit 7 in a byte integer, bit 15 in a
word integer, bit 31 in a doubleword integer, and bit 63 in a quadword integer (see the signed integer encodings in
Table 4-1).
Table 4-1. Signed Integer Encodings
Class
Two’s Complement Encoding
Sign
Positive
Largest
Smallest
Zero
Negative
Smallest
Largest
Integer indefinite
0
11..11
.
.
.
.
0
00..01
0
00..00
1
11..11
.
.
.
.
1
00..00
1
00..00
Signed Byte Integer:
Signed Word Integer:
Signed Doubleword Integer:
Signed Quadword Integer:
← 7 bits →
← 15 bits →
← 31 bits →
← 63 bits →
The sign bit is set for negative integers and cleared for positive integers and zero. Integer values range from –128
to +127 for a byte integer, from –32,768 to +32,767 for a word integer, from –231 to +231 – 1 for a doubleword
integer, and from –263 to +263 – 1 for a quadword integer.
When storing integer values in memory, word integers are stored in 2 consecutive bytes; doubleword integers are
stored in 4 consecutive bytes; and quadword integers are stored in 8 consecutive bytes.
The integer indefinite is a special value that is sometimes returned by the x87 FPU when operating on integer
values. For more information, see Section 8.2.1, “Indefinites.”
4.2.2
Floating-Point Data Types
The IA-32 architecture defines and operates on three floating-point data types: single-precision floating-point,
double-precision floating-point, and double-extended precision floating-point (see Figure 4-3). The data formats
for these data types correspond directly to formats specified in the IEEE Standard 754 for Binary Floating-Point
Arithmetic.
Half-precision (16-bit) floating-point data type is supported only for conversion operation with single-precision
floating data using F16C extensions (VCVTPH2PS, VCVTPS2PH).
Table 4-2 gives the length, precision, and approximate normalized range that can be represented by each of these
data types. Denormal values are also supported in each of these types.
4-4 Vol. 1
DATA TYPES
Table 4-2. Length, Precision, and Range of Floating-Point Data Types
Data Type
Half Precision
Length
Precision
(Bits)
16
11
Approximate Normalized Range
Binary
–14
2
15
to 2
–126
127
to 2
Decimal
–5
3.1 × 10
1.18 × 10
to 6.50 × 104
–38
to 3.40 × 1038
Single Precision
32
24
2
Double Precision
64
53
2–1022 to 21023
2.23 × 10–308 to 1.79 × 10308
Double Extended
Precision
80
64
2–16382 to 216383
3.37 × 10–4932 to 1.18 × 104932
NOTE
Section 4.8, “Real Numbers and Floating-Point Formats,” gives an overview of the IEEE Standard
754 floating-point formats and defines the terms integer bit, QNaN, SNaN, and denormal value.
Table 4-3 shows the floating-point encodings for zeros, denormalized finite numbers, normalized finite numbers,
infinites, and NaNs for each of the three floating-point data types. It also gives the format for the QNaN floatingpoint indefinite value. (See Section 4.8.3.7, “QNaN Floating-Point Indefinite,” for a discussion of the use of the
QNaN floating-point indefinite value.)
For the single-precision and double-precision formats, only the fraction part of the significand is encoded. The
integer is assumed to be 1 for all numbers except 0 and denormalized finite numbers. For the double extendedprecision format, the integer is contained in bit 63, and the most-significant fraction bit is bit 62. Here, the integer
is explicitly set to 1 for normalized numbers, infinities, and NaNs, and to 0 for zero and denormalized numbers.
Table 4-3. Floating-Point Number and NaN Encodings
Class
Positive
Negative
Sign
Biased Exponent
Significand
Integer1
Fraction
+∞
0
11..11
1
00..00
+Normals
0
.
.
0
11..10
.
.
00..01
1
.
.
1
11..11
.
.
00..00
+Denormals
0
.
.
0
00..00
.
.
00..00
0
.
.
0
11.11
.
.
00..01
+Zero
0
00..00
0
00..00
−Zero
1
00..00
0
00..00
−Denormals
1
.
.
1
00..00
.
.
00..00
0
.
.
0
00..01
.
.
11..11
−Normals
1
.
.
1
00..01
.
.
11..10
1
.
.
1
00..00
.
.
11..11
-∞
1
11..11
1
00..00
Vol. 1 4-5
DATA TYPES
Table 4-3. Floating-Point Number and NaN Encodings (Contd.)
NaNs
SNaN
X
11..11
1
0X..XX2
QNaN
X
11..11
1
1X..XX
QNaN FloatingPoint Indefinite
1
11..11
1
10..00
← 5Bits →
← 8 Bits →
← 11 Bits →
← 15 Bits →
Half-Precision
Single-Precision:
Double-Precision:
Double Extended-Precision:
← 10 Bits →
← 23 Bits →
← 52 Bits →
← 63 Bits →
NOTES:
1. Integer bit is implied and not stored for single-precision and double-precision formats.
2. The fraction for SNaN encodings must be non-zero with the most-significant bit 0.
The exponent of each floating-point data type is encoded in biased format; see Section 4.8.2.2, “Biased Exponent.”
The biasing constant is 15 for the half-precision format, 127 for the single-precision format, 1023 for the doubleprecision format, and 16,383 for the double extended-precision format.
When storing floating-point values in memory, half-precision values are stored in 2 consecutive bytes in memory;
single-precision values are stored in 4 consecutive bytes in memory; double-precision values are stored in 8
consecutive bytes; and double extended-precision values are stored in 10 consecutive bytes.
The single-precision and double-precision floating-point data types are operated on by x87 FPU, and
SSE/SSE2/SSE3/SSE4.1 and Intel AVX instructions. The double-extended-precision floating-point format is only
operated on by the x87 FPU. See Section 11.6.8, “Compatibility of SIMD and x87 FPU Floating-Point Data Types,”
for a discussion of the compatibility of single-precision and double-precision floating-point data types between the
x87 FPU and SSE/SSE2/SSE3 extensions.
4.3
POINTER DATA TYPES
Pointers are addresses of locations in memory.
In non-64-bit modes, the architecture defines two types of pointers: a near pointer and a far pointer. A near
pointer is a 32-bit (or 16-bit) offset (also called an effective address) within a segment. Near pointers are used
for all memory references in a flat memory model or for references in a segmented model where the identity of the
segment being accessed is implied.
A far pointer is a logical address, consisting of a 16-bit segment selector and a 32-bit (or 16-bit) offset. Far pointers
are used for memory references in a segmented memory model where the identity of a segment being accessed
must be specified explicitly. Near and far pointers with 32-bit offsets are shown in Figure 4-4.
Near Pointer
Offset
31
0
Far Pointer or Logical Address
Segment Selector
47
Offset
32 31
Figure 4-4. Pointer Data Types
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DATA TYPES
4.3.1
Pointer Data Types in 64-Bit Mode
In 64-bit mode (a sub-mode of IA-32e mode), a near pointer is 64 bits. This equates to an effective address. Far
pointers in 64-bit mode can be one of three forms:
•
•
•
16-bit segment selector, 16-bit offset if the operand size is 32 bits
16-bit segment selector, 32-bit offset if the operand size is 32 bits
16-bit segment selector, 64-bit offset if the operand size is 64 bits
See Figure 4-5.
Near Pointer
64-bit Offset
63
0
Far Pointer with 64-bit Operand Size
16-bit Segment Selector
79
64-bit Offset
0
64 63
Far Pointer with 32-bit Operand Size
16-bit Segment Selector
32-bit Offset
0
32 31
47
Far Pointer with 32-bit Operand Size
16-bit Segment Selector
31
16 15
16-bit Offset
0
Figure 4-5. Pointers in 64-Bit Mode
4.4
BIT FIELD DATA TYPE
A bit field (see Figure 4-6) is a contiguous sequence of bits. It can begin at any bit position of any byte in memory
and can contain up to 32 bits.
Bit Field
Field Length
Least
Significant
Bit
Figure 4-6. Bit Field Data Type
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DATA TYPES
4.5
STRING DATA TYPES
Strings are continuous sequences of bits, bytes, words, or doublewords. A bit string can begin at any bit position
of any byte and can contain up to 232 – 1 bits. A byte string can contain bytes, words, or doublewords and can
range from zero to 232 – 1 bytes (4 GBytes).
4.6
PACKED SIMD DATA TYPES
Intel 64 and IA-32 architectures define and operate on a set of 64-bit and 128-bit packed data type for use in SIMD
operations. These data types consist of fundamental data types (packed bytes, words, doublewords, and quadwords) and numeric interpretations of fundamental types for use in packed integer and packed floating-point operations.
4.6.1
64-Bit SIMD Packed Data Types
The 64-bit packed SIMD data types were introduced into the IA-32 architecture in the Intel MMX technology. They
are operated on in MMX registers. The fundamental 64-bit packed data types are packed bytes, packed words, and
packed doublewords (see Figure 4-7). When performing numeric SIMD operations on these data types, these data
types are interpreted as containing byte, word, or doubleword integer values.
Fundamental 64-Bit Packed SIMD Data Types
Packed Bytes
0
63
Packed Words
0
63
Packed Doublewords
0
63
64-Bit Packed Integer Data Types
Packed Byte Integers
0
63
Packed Word Integers
0
63
Packed Doubleword Integers
0
63
Figure 4-7. 64-Bit Packed SIMD Data Types
4.6.2
128-Bit Packed SIMD Data Types
The 128-bit packed SIMD data types were introduced into the IA-32 architecture in the SSE extensions and used
with SSE2, SSE3 and SSSE3 extensions. They are operated on primarily in the 128-bit XMM registers and memory.
The fundamental 128-bit packed data types are packed bytes, packed words, packed doublewords, and packed
quadwords (see Figure 4-8). When performing SIMD operations on these fundamental data types in XMM registers,
these data types are interpreted as containing packed or scalar single-precision floating-point or double-precision
floating-point values, or as containing packed byte, word, doubleword, or quadword integer values.
4-8 Vol. 1
DATA TYPES
Fundamental 128-Bit Packed SIMD Data Types
Packed Bytes
127
0
Packed Words
127
0
Packed Doublewords
127
0
Packed Quadwords
127
0
128-Bit Packed Floating-Point and Integer Data Types
Packed Single Precision
Floating Point
127
0
Packed Double Precision
Floating Point
127
0
Packed Byte Integers
127
0
Packed Word Integers
127
0
Packed Doubleword Integers
127
0
Packed Quadword Integers
127
0
Figure 4-8. 128-Bit Packed SIMD Data Types
4.7
BCD AND PACKED BCD INTEGERS
Binary-coded decimal integers (BCD integers) are unsigned 4-bit integers with valid values ranging from 0 to 9. IA32 architecture defines operations on BCD integers located in one or more general-purpose registers or in one or
more x87 FPU registers (see Figure 4-9).
Vol. 1 4-9
DATA TYPES
BCD Integers
X
7
BCD
43
0
Packed BCD Integers
BCD BCD
7
43
0
80-Bit Packed BCD Decimal Integers
Sign
X
79 78
D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
72 71
0
4 Bits = 1 BCD Digit
Figure 4-9. BCD Data Types
When operating on BCD integers in general-purpose registers, the BCD values can be unpacked (one BCD digit per
byte) or packed (two BCD digits per byte). The value of an unpacked BCD integer is the binary value of the low halfbyte (bits 0 through 3). The high half-byte (bits 4 through 7) can be any value during addition and subtraction, but
must be zero during multiplication and division. Packed BCD integers allow two BCD digits to be contained in one
byte. Here, the digit in the high half-byte is more significant than the digit in the low half-byte.
When operating on BCD integers in x87 FPU data registers, BCD values are packed in an 80-bit format and referred
to as decimal integers. In this format, the first 9 bytes hold 18 BCD digits, 2 digits per byte. The least-significant
digit is contained in the lower half-byte of byte 0 and the most-significant digit is contained in the upper half-byte
of byte 9. The most significant bit of byte 10 contains the sign bit (0 = positive and 1 = negative; bits 0 through 6
of byte 10 are don’t care bits). Negative decimal integers are not stored in two's complement form; they are distinguished from positive decimal integers only by the sign bit. The range of decimal integers that can be encoded in
this format is –1018 + 1 to 1018 – 1.
The decimal integer format exists in memory only. When a decimal integer is loaded in an x87 FPU data register, it
is automatically converted to the double-extended-precision floating-point format. All decimal integers are exactly
representable in double extended-precision format.
Table 4-4 gives the possible encodings of value in the decimal integer data type.
Table 4-4. Packed Decimal Integer Encodings
Magnitude
Class
Positive
Sign
digit
digit
digit
digit
...
digit
1001
1001
1001
1001
...
1001
0
0000000
.
.
.
.
.
.
Smallest
0
0000000
0000
0000
0000
0000
...
0001
Zero
0
0000000
0000
0000
0000
0000
...
0000
Zero
1
0000000
0000
0000
0000
0000
...
0000
Smallest
1
0000000
0000
0000
0000
0000
...
0001
.
.
.
.
.
.
1
0000000
1001
...
1001
Largest
Negative
Largest
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1001
1001
1001
DATA TYPES
Table 4-4. Packed Decimal Integer Encodings (Contd.)
Packed BCD
Integer
Indefinite
1
1111111
← 1 byte →
1111
1111
1100
0000
...
0000
← 9 bytes →
The packed BCD integer indefinite encoding (FFFFC000000000000000H) is stored by the FBSTP instruction in
response to a masked floating-point invalid-operation exception. Attempting to load this value with the FBLD
instruction produces an undefined result.
4.8
REAL NUMBERS AND FLOATING-POINT FORMATS
This section describes how real numbers are represented in floating-point format in x87 FPU and
SSE/SSE2/SSE3/SSE4.1 and Intel AVX floating-point instructions. It also introduces terms such as normalized
numbers, denormalized numbers, biased exponents, signed zeros, and NaNs. Readers who are already familiar
with floating-point processing techniques and the IEEE Standard 754 for Binary Floating-Point Arithmetic may wish
to skip this section.
4.8.1
Real Number System
As shown in Figure 4-10, the real-number system comprises the continuum of real numbers from minus infinity (−
∞) to plus infinity (+ ∞).
Because the size and number of registers that any computer can have is limited, only a subset of the real-number
continuum can be used in real-number (floating-point) calculations. As shown at the bottom of Figure 4-10, the
subset of real numbers that the IA-32 architecture supports represents an approximation of the real number
system. The range and precision of this real-number subset is determined by the IEEE Standard 754 floating-point
formats.
4.8.2
Floating-Point Format
To increase the speed and efficiency of real-number computations, computers and microprocessors typically represent real numbers in a binary floating-point format. In this format, a real number has three parts: a sign, a significand, and an exponent (see Figure 4-11).
The sign is a binary value that indicates whether the number is positive (0) or negative (1). The significand has
two parts: a 1-bit binary integer (also referred to as the J-bit) and a binary fraction. The integer-bit is often not
represented, but instead is an implied value. The exponent is a binary integer that represents the base-2 power by
which the significand is multiplied.
Table 4-5 shows how the real number 178.125 (in ordinary decimal format) is stored in IEEE Standard 754 floatingpoint format. The table lists a progression of real number notations that leads to the single-precision, 32-bit
floating-point format. In this format, the significand is normalized (see Section 4.8.2.1, “Normalized Numbers”)
and the exponent is biased (see Section 4.8.2.2, “Biased Exponent”). For the single-precision floating-point
format, the biasing constant is +127.
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DATA TYPES
Binary Real Number System
10
-1 0
-10
1
-100
100
ςς
ςς
Subset of binary real numbers that can be represented with
IEEE single-precision (32-bit) floating-point format
10
-1 0
100
-100
-10
1
ςς
ςς
+10
10.0000000000000000000000
Precision
1.11111111111111111111111
24 Binary Digits
Numbers within this range
cannot be represented.
Figure 4-10. Binary Real Number System
Sign
Exponent
Significand
Fraction
Integer or J-Bit
Figure 4-11. Binary Floating-Point Format
Table 4-5. Real and Floating-Point Number Notation
Notation
Value
Ordinary Decimal
178.125
Scientific Decimal
1.78125E10 2
Scientific Binary
1.0110010001E2111
Scientific Binary
(Biased Exponent)
1.0110010001E210000110
IEEE Single-Precision Format
Sign
Biased Exponent
Normalized Significand
0
10000110
01100100010000000000000
1. (Implied)
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DATA TYPES
4.8.2.1
Normalized Numbers
In most cases, floating-point numbers are encoded in normalized form. This means that except for zero, the significand is always made up of an integer of 1 and the following fraction:
1.fff...ff
For values less than 1, leading zeros are eliminated. (For each leading zero eliminated, the exponent is decremented by one.)
Representing numbers in normalized form maximizes the number of significant digits that can be accommodated
in a significand of a given width. To summarize, a normalized real number consists of a normalized significand that
represents a real number between 1 and 2 and an exponent that specifies the number’s binary point.
4.8.2.2
Biased Exponent
In the IA-32 architecture, the exponents of floating-point numbers are encoded in a biased form. This means that
a constant is added to the actual exponent so that the biased exponent is always a positive number. The value of
the biasing constant depends on the number of bits available for representing exponents in the floating-point
format being used. The biasing constant is chosen so that the smallest normalized number can be reciprocated
without overflow.
See Section 4.2.2, “Floating-Point Data Types,” for a list of the biasing constants that the IA-32 architecture uses
for the various sizes of floating-point data-types.
4.8.3
Real Number and Non-number Encodings
A variety of real numbers and special values can be encoded in the IEEE Standard 754 floating-point format. These
numbers and values are generally divided into the following classes:
•
•
•
•
•
•
Signed zeros
Denormalized finite numbers
Normalized finite numbers
Signed infinities
NaNs
Indefinite numbers
(The term NaN stands for “Not a Number.”)
Figure 4-12 shows how the encodings for these numbers and non-numbers fit into the real number continuum. The
encodings shown here are for the IEEE single-precision floating-point format. The term “S” indicates the sign bit,
“E” the biased exponent, and “Sig” the significand. The exponent values are given in decimal. The integer bit is
shown for the significands, even though the integer bit is implied in single-precision floating-point format.
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DATA TYPES
NaN
NaN
− Denormalized Finite + Denormalized Finite
−∞
S
1
E
0
1
0
− Normalized Finite
+ Normalized Finite + ∞
− 0+ 0
Real Number and NaN Encodings For 32-Bit Floating-Point Format
E
Sig1
Sig1
S
0.000...
0.000
...
−0
0
0
+0
0.XXX...2
− Denormalized
Finite
1 1...254
1.XXX...
− Normalized
Finite
1
1.000...
−∞
+∞
X3 255
1.0XX...2
SNaN
SNaN X3 255
1.0XX...2
X3 255
1.1XX...
QNaN
QNaN X3 255
1.1XX...
255
+Denormalized
Finite 0
0
0.XXX...2
+Normalized 0 1...254 1.XXX...
Finite
0
255
1.000...
NOTES:
1. Integer bit of fraction implied for
single-precision floating-point format.
2. Fraction must be non-zero.
3. Sign bit ignored.
Figure 4-12. Real Numbers and NaNs
An IA-32 processor can operate on and/or return any of these values, depending on the type of computation being
performed. The following sections describe these number and non-number classes.
4.8.3.1
Signed Zeros
Zero can be represented as a +0 or a −0 depending on the sign bit. Both encodings are equal in value. The sign of
a zero result depends on the operation being performed and the rounding mode being used. Signed zeros have
been provided to aid in implementing interval arithmetic. The sign of a zero may indicate the direction from which
underflow occurred, or it may indicate the sign of an ∞ that has been reciprocated.
4.8.3.2
Normalized and Denormalized Finite Numbers
Non-zero, finite numbers are divided into two classes: normalized and denormalized. The normalized finite
numbers comprise all the non-zero finite values that can be encoded in a normalized real number format between
zero and ∞. In the single-precision floating-point format shown in Figure 4-12, this group of numbers includes all
the numbers with biased exponents ranging from 1 to 25410 (unbiased, the exponent range is from −12610 to
+12710).
When floating-point numbers become very close to zero, the normalized-number format can no longer be used to
represent the numbers. This is because the range of the exponent is not large enough to compensate for shifting
the binary point to the right to eliminate leading zeros.
When the biased exponent is zero, smaller numbers can only be represented by making the integer bit (and
perhaps other leading bits) of the significand zero. The numbers in this range are called denormalized numbers.
The use of leading zeros with denormalized numbers allows smaller numbers to be represented. However, this
denormalization may cause a loss of precision (the number of significant bits is reduced by the leading zeros).
When performing normalized floating-point computations, an IA-32 processor normally operates on normalized
numbers and produces normalized numbers as results. Denormalized numbers represent an underflow condition.
The exact conditions are specified in Section 4.9.1.5, “Numeric Underflow Exception (#U).”
A denormalized number is computed through a technique called gradual underflow. Table 4-6 gives an example of
gradual underflow in the denormalization process. Here the single-precision format is being used, so the minimum
exponent (unbiased) is −12610. The true result in this example requires an exponent of −12910 in order to have a
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DATA TYPES
normalized number. Since −12910 is beyond the allowable exponent range, the result is denormalized by inserting
leading zeros until the minimum exponent of −12610 is reached.
Table 4-6. Denormalization Process
Operation
Sign
Exponent*
Significand
True Result
0
−129
1.01011100000...00
Denormalize
0
−128
0.10101110000...00
Denormalize
0
−127
0.01010111000...00
Denormalize
0
−126
0.00101011100...00
Denormal Result
0
−126
0.00101011100...00
* Expressed as an unbiased, decimal number.
In the extreme case, all the significant bits are shifted out to the right by leading zeros, creating a zero result.
The Intel 64 and IA-32 architectures deal with denormal values in the following ways:
•
•
It avoids creating denormals by normalizing numbers whenever possible.
•
It provides the floating-point denormal-operand exception to permit procedures or programs to detect when
denormals are being used as source operands for computations.
It provides the floating-point underflow exception to permit programmers to detect cases when denormals are
created.
4.8.3.3
Signed Infinities
The two infinities, + ∞ and − ∞, represent the maximum positive and negative real numbers, respectively, that can
be represented in the floating-point format. Infinity is always represented by a significand of 1.00...00 (the integer
bit may be implied) and the maximum biased exponent allowed in the specified format (for example, 25510 for the
single-precision format).
The signs of infinities are observed, and comparisons are possible. Infinities are always interpreted in the affine
sense; that is, –∞ is less than any finite number and +∞ is greater than any finite number. Arithmetic on infinities
is always exact. Exceptions are generated only when the use of an infinity as a source operand constitutes an
invalid operation.
Whereas denormalized numbers may represent an underflow condition, the two ∞ numbers may represent the
result of an overflow condition. Here, the normalized result of a computation has a biased exponent greater than
the largest allowable exponent for the selected result format.
4.8.3.4
NaNs
Since NaNs are non-numbers, they are not part of the real number line. In Figure 4-12, the encoding space for
NaNs in the floating-point formats is shown above the ends of the real number line. This space includes any value
with the maximum allowable biased exponent and a non-zero fraction (the sign bit is ignored for NaNs).
The IA-32 architecture defines two classes of NaNs: quiet NaNs (QNaNs) and signaling NaNs (SNaNs). A QNaN is a
NaN with the most significant fraction bit set; an SNaN is a NaN with the most significant fraction bit clear. QNaNs
are allowed to propagate through most arithmetic operations without signaling an exception. SNaNs generally
signal a floating-point invalid-operation exception whenever they appear as operands in arithmetic operations.
SNaNs are typically used to trap or invoke an exception handler. They must be inserted by software; that is, the
processor never generates an SNaN as a result of a floating-point operation.
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DATA TYPES
4.8.3.5
Operating on SNaNs and QNaNs
When a floating-point operation is performed on an SNaN and/or a QNaN, the result of the operation is either a
QNaN delivered to the destination operand or the generation of a floating-point invalid operation exception,
depending on the following rules:
•
If one of the source operands is an SNaN and the floating-point invalid-operation exception is not masked (see
Section 4.9.1.1, “Invalid Operation Exception (#I)”), then a floating-point invalid-operation exception is
signaled and no result is stored in the destination operand.
•
If either or both of the source operands are NaNs and floating-point invalid-operation exception is masked, the
result is as shown in Table 4-7. When an SNaN is converted to a QNaN, the conversion is handled by setting the
most-significant fraction bit of the SNaN to 1. Also, when one of the source operands is an SNaN, the floatingpoint invalid-operation exception flag is set. Note that for some combinations of source operands, the result is
different for x87 FPU operations and for SSE/SSE2/SSE3/SSE4.1 operations. Intel AVX follows the same
behavior as SSE/SSE2/SSE3/SSE4.1 in this respect.
•
When neither of the source operands is a NaN, but the operation generates a floating-point invalid-operation
exception (see Tables 8-10 and 11-1), the result is commonly a QNaN FP Indefinite (Section 4.8.3.7).
Any exceptions to the behavior described in Table 4-7 are described in Section 8.5.1.2, “Invalid Arithmetic Operand
Exception (#IA),” and Section 11.5.2.1, “Invalid Operation Exception (#I).”
Table 4-7. Rules for Handling NaNs
Source Operands
Result1
SNaN and QNaN
x87 FPU — QNaN source operand.
SSE/SSE2/SSE3/SSE4.1/AVX — First source operand (if this operand is an
SNaN, it is converted to a QNaN)
Two SNaNs
x87 FPU—SNaN source operand with the larger significand, converted into a
QNaN
SSE/SSE2/SSE3/SSE4.1/AVX — First source operand converted to a QNaN
Two QNaNs
x87 FPU — QNaN source operand with the larger
significand
SSE/SSE2/SSE3/SSE4.1/AVX — First source operand
SNaN and a floating-point value
SNaN source operand, converted into a QNaN
QNaN and a floating-point value
QNaN source operand
SNaN (for instructions that take only one operand)
SNaN source operand, converted into a QNaN
QNaN (for instructions that take only one operand)
QNaN source operand
NOTE:
1. For SSE/SSE2/SSE3/SSE4.1 instructions, the first operand is generally a source operand that becomes the destination operand. For
AVX instructions, the first source operand is usually the 2nd operand in a non-destructive source syntax. Within the Result column,
the x87 FPU notation also applies to the FISTTP instruction in SSE3; the SSE3 notation applies to the SIMD floating-point instructions.
4.8.3.6
Using SNaNs and QNaNs in Applications
Except for the rules given at the beginning of Section 4.8.3.4, “NaNs,” for encoding SNaNs and QNaNs, software is
free to use the bits in the significand of a NaN for any purpose. Both SNaNs and QNaNs can be encoded to carry and
store data, such as diagnostic information.
By unmasking the invalid operation exception, the programmer can use signaling NaNs to trap to the exception
handler. The generality of this approach and the large number of NaN values that are available provide the sophisticated programmer with a tool that can be applied to a variety of special situations.
For example, a compiler can use signaling NaNs as references to uninitialized (real) array elements. The compiler
can preinitialize each array element with a signaling NaN whose significand contains the index (relative position) of
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DATA TYPES
the element. Then, if an application program attempts to access an element that it has not initialized, it can use the
NaN placed there by the compiler. If the invalid operation exception is unmasked, an interrupt will occur, and the
exception handler will be invoked. The exception handler can determine which element has been accessed, since
the operand address field of the exception pointer will point to the NaN, and the NaN will contain the index number
of the array element.
Quiet NaNs are often used to speed up debugging. In its early testing phase, a program often contains multiple
errors. An exception handler can be written to save diagnostic information in memory whenever it is invoked. After
storing the diagnostic data, it can supply a quiet NaN as the result of the erroneous instruction, and that NaN can
point to its associated diagnostic area in memory. The program will then continue, creating a different NaN for each
error. When the program ends, the NaN results can be used to access the diagnostic data saved at the time the
errors occurred. Many errors can thus be diagnosed and corrected in one test run.
In embedded applications that use computed results in further computations, an undetected QNaN can invalidate
all subsequent results. Such applications should therefore periodically check for QNaNs and provide a recovery
mechanism to be used if a QNaN result is detected.
4.8.3.7
QNaN Floating-Point Indefinite
For the floating-point data type encodings (single-precision, double-precision, and double-extended-precision),
one unique encoding (a QNaN) is reserved for representing the special value QNaN floating-point indefinite. The
x87 FPU and the SSE/SSE2/SSE3/SSE4.1/AVX extensions return these indefinite values as responses to some
masked floating-point exceptions. Table 4-3 shows the encoding used for the QNaN floating-point indefinite.
4.8.3.8
Half-Precision Floating-Point Operation
Half-precision floating-point values are not used by the processor directly for arithmetic operations. Two instructions, VCVTPH2PS, VCVTPS2PH, provide conversion only between half-precision and single-precision floating-point
values.
The SIMD floating-point exception behavior of VCVTPH2PS and VCVTPS2PH are described in Section 14.4.1.
4.8.4
Rounding
When performing floating-point operations, the processor produces an infinitely precise floating-point result in the
destination format (single-precision, double-precision, or double extended-precision floating-point) whenever
possible. However, because only a subset of the numbers in the real number continuum can be represented in IEEE
Standard 754 floating-point formats, it is often the case that an infinitely precise result cannot be encoded exactly
in the format of the destination operand.
For example, the following value (a) has a 24-bit fraction. The least-significant bit of this fraction (the underlined
bit) cannot be encoded exactly in the single-precision format (which has only a 23-bit fraction):
(a) 1.0001 0000 1000 0011 1001 0111E2 101
To round this result (a), the processor first selects two representable fractions b and c that most closely bracket a
in value (b < a < c).
(b) 1.0001 0000 1000 0011 1001 011E2 101
(c) 1.0001 0000 1000 0011 1001 100E2 101
The processor then sets the result to b or to c according to the selected rounding mode. Rounding introduces an
error in a result that is less than one unit in the last place (the least significant bit position of the floating-point
value) to which the result is rounded.
The IEEE Standard 754 defines four rounding modes (see Table 4-8): round to nearest, round up, round down, and
round toward zero. The default rounding mode (for the Intel 64 and IA-32 architectures) is round to nearest. This
mode provides the most accurate and statistically unbiased estimate of the true result and is suitable for most
applications.
Vol. 1 4-17
DATA TYPES
Table 4-8. Rounding Modes and Encoding of Rounding Control (RC) Field
Rounding Mode
RC Field
Setting
Description
Round to
nearest (even)
00B
Rounded result is the closest to the infinitely precise result. If two values are equally close, the
result is the even value (that is, the one with the least-significant bit of zero). Default
Round down
(toward −∞)
01B
Rounded result is closest to but no greater than the infinitely precise result.
Round up
(toward +∞)
10B
Rounded result is closest to but no less than the infinitely precise result.
Round toward
zero (Truncate)
11B
Rounded result is closest to but no greater in absolute value than the infinitely precise result.
The round up and round down modes are termed directed rounding and can be used to implement interval arithmetic. Interval arithmetic is used to determine upper and lower bounds for the true result of a multistep computation, when the intermediate results of the computation are subject to rounding.
The round toward zero mode (sometimes called the “chop” mode) is commonly used when performing integer
arithmetic with the x87 FPU.
The rounded result is called the inexact result. When the processor produces an inexact result, the floating-point
precision (inexact) flag (PE) is set (see Section 4.9.1.6, “Inexact-Result (Precision) Exception (#P)”).
The rounding modes have no effect on comparison operations, operations that produce exact results, or operations
that produce NaN results.
4.8.4.1
Rounding Control (RC) Fields
In the Intel 64 and IA-32 architectures, the rounding mode is controlled by a 2-bit rounding-control (RC) field
(Table 4-8 shows the encoding of this field). The RC field is implemented in two different locations:
•
•
x87 FPU control register (bits 10 and 11)
The MXCSR register (bits 13 and 14)
Although these two RC fields perform the same function, they control rounding for different execution environments within the processor. The RC field in the x87 FPU control register controls rounding for computations
performed with the x87 FPU instructions; the RC field in the MXCSR register controls rounding for SIMD floatingpoint computations performed with the SSE/SSE2 instructions.
4.8.4.2
Truncation with SSE and SSE2 Conversion Instructions
The following SSE/SSE2 instructions automatically truncate the results of conversions from floating-point values to
integers when the result it inexact: CVTTPD2DQ, CVTTPS2DQ, CVTTPD2PI, CVTTPS2PI, CVTTSD2SI, CVTTSS2SI.
Here, truncation means the round toward zero mode described in Table 4-8.
4.9
OVERVIEW OF FLOATING-POINT EXCEPTIONS
The following section provides an overview of floating-point exceptions and their handling in the IA-32 architecture.
For information specific to the x87 FPU and to the SSE/SSE2/SSE3/SSE4.1 extensions, refer to the following
sections:
•
•
Section 8.4, “x87 FPU Floating-Point Exception Handling”
Section 11.5, “SSE, SSE2, and SSE3 Exceptions”
When operating on floating-point operands, the IA-32 architecture recognizes and detects six classes of exception
conditions:
•
Invalid operation (#I)
4-18 Vol. 1
DATA TYPES
•
•
•
•
•
Divide-by-zero (#Z)
Denormalized operand (#D)
Numeric overflow (#O)
Numeric underflow (#U)
Inexact result (precision) (#P)
The nomenclature of “#” symbol followed by one or two letters (for example, #P) is used in this manual to indicate
exception conditions. It is merely a short-hand form and is not related to assembler mnemonics.
NOTE
All of the exceptions listed above except the denormal-operand exception (#D) are defined in IEEE
Standard 754.
The invalid-operation, divide-by-zero and denormal-operand exceptions are pre-computation exceptions (that is,
they are detected before any arithmetic operation occurs). The numeric-underflow, numeric-overflow and precision
exceptions are post-computation exceptions.
Each of the six exception classes has a corresponding flag bit (IE, ZE, OE, UE, DE, or PE) and mask bit (IM, ZM, OM,
UM, DM, or PM). When one or more floating-point exception conditions are detected, the processor sets the appropriate flag bits, then takes one of two possible courses of action, depending on the settings of the corresponding
mask bits:
•
Mask bit set. Handles the exception automatically, producing a predefined (and often times usable) result,
while allowing program execution to continue undisturbed.
•
Mask bit clear. Invokes a software exception handler to handle the exception.
The masked (default) responses to exceptions have been chosen to deliver a reasonable result for each exception
condition and are generally satisfactory for most floating-point applications. By masking or unmasking specific
floating-point exceptions, programmers can delegate responsibility for most exceptions to the processor and
reserve the most severe exception conditions for software exception handlers.
Because the exception flags are “sticky,” they provide a cumulative record of the exceptions that have occurred
since they were last cleared. A programmer can thus mask all exceptions, run a calculation, and then inspect the
exception flags to see if any exceptions were detected during the calculation.
In the IA-32 architecture, floating-point exception flag and mask bits are implemented in two different locations:
•
x87 FPU status word and control word. The flag bits are located at bits 0 through 5 of the x87 FPU status word
and the mask bits are located at bits 0 through 5 of the x87 FPU control word (see Figures 8-4 and 8-6).
•
MXCSR register. The flag bits are located at bits 0 through 5 of the MXCSR register and the mask bits are
located at bits 7 through 12 of the register (see Figure 10-3).
Although these two sets of flag and mask bits perform the same function, they report on and control exceptions for
different execution environments within the processor. The flag and mask bits in the x87 FPU status and control
words control exception reporting and masking for computations performed with the x87 FPU instructions; the
companion bits in the MXCSR register control exception reporting and masking for SIMD floating-point computations performed with the SSE/SSE2/SSE3 instructions.
Note that when exceptions are masked, the processor may detect multiple exceptions in a single instruction,
because it continues executing the instruction after performing its masked response. For example, the processor
can detect a denormalized operand, perform its masked response to this exception, and then detect numeric
underflow.
See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules for exception precedence when
more than one floating-point exception condition is detected for an instruction.
4.9.1
Floating-Point Exception Conditions
The following sections describe the various conditions that cause a floating-point exception to be generated and the
masked response of the processor when these conditions are detected. The Intel® 64 and IA-32 Architectures
Vol. 1 4-19
DATA TYPES
Software Developer’s Manual, Volumes 3A & 3B, list the floating-point exceptions that can be signaled for each
floating-point instruction.
4.9.1.1
Invalid Operation Exception (#I)
The processor reports an invalid operation exception in response to one or more invalid arithmetic operands. If the
invalid operation exception is masked, the processor sets the IE flag and returns an indefinite value or a QNaN. This
value overwrites the destination register specified by the instruction. If the invalid operation exception is not
masked, the IE flag is set, a software exception handler is invoked, and the operands remain unaltered.
See Section 4.8.3.6, “Using SNaNs and QNaNs in Applications,” for information about the result returned when an
exception is caused by an SNaN.
The processor can detect a variety of invalid arithmetic operations that can be coded in a program. These operations generally indicate a programming error, such as dividing ∞ by ∞ . See the following sections for information
regarding the invalid-operation exception when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions:
•
•
x87 FPU; Section 8.5.1, “Invalid Operation Exception”
SIMD floating-point exceptions; Section 11.5.2.1, “Invalid Operation Exception (#I)”
4.9.1.2
Denormal Operand Exception (#D)
The processor reports the denormal-operand exception if an arithmetic instruction attempts to operate on a
denormal operand (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”). When the exception is
masked, the processor sets the DE flag and proceeds with the instruction. Operating on denormal numbers will
produce results at least as good as, and often better than, what can be obtained when denormal numbers are
flushed to zero. Programmers can mask this exception so that a computation may proceed, then analyze any loss
of accuracy when the final result is delivered.
When a denormal-operand exception is not masked, the DE flag is set, a software exception handler is invoked, and
the operands remain unaltered. When denormal operands have reduced significance due to loss of low-order bits,
it may be advisable to not operate on them. Precluding denormal operands from computations can be accomplished by an exception handler that responds to unmasked denormal-operand exceptions.
See the following sections for information regarding the denormal-operand exception when detected while
executing x87 FPU or SSE/SSE2/SSE3 instructions:
•
•
x87 FPU; Section 8.5.2, “Denormal Operand Exception (#D)”
SIMD floating-point exceptions; Section 11.5.2.2, “Denormal-Operand Exception (#D)”
4.9.1.3
Divide-By-Zero Exception (#Z)
The processor reports the floating-point divide-by-zero exception whenever an instruction attempts to divide a
finite non-zero operand by 0. The masked response for the divide-by-zero exception is to set the ZE flag and return
an infinity signed with the exclusive OR of the sign of the operands. If the divide-by-zero exception is not masked,
the ZE flag is set, a software exception handler is invoked, and the operands remain unaltered.
See the following sections for information regarding the divide-by-zero exception when detected while executing
x87 FPU or SSE/SSE2 instructions:
•
•
x87 FPU; Section 8.5.3, “Divide-By-Zero Exception (#Z)”
SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception (#Z)”
4.9.1.4
Numeric Overflow Exception (#O)
The processor reports a floating-point numeric overflow exception whenever the rounded result of an instruction
exceeds the largest allowable finite value that will fit into the destination operand. Table 4-9 shows the threshold
range for numeric overflow for each of the floating-point formats; overflow occurs when a rounded result falls at or
outside this threshold range.
4-20 Vol. 1
DATA TYPES
Table 4-9. Numeric Overflow Thresholds
Floating-Point Format
Overflow Thresholds
Single Precision
| x | ≥ 1.0 ∗ 2128
Double Precision
| x | ≥ 1.0 ∗ 21024
Double Extended Precision
| x | ≥ 1.0 ∗ 216384
When a numeric-overflow exception occurs and the exception is masked, the processor sets the OE flag and
returns one of the values shown in Table 4-10, according to the current rounding mode. See Section 4.8.4,
“Rounding.”
When numeric overflow occurs and the numeric-overflow exception is not masked, the OE flag is set, a software
exception handler is invoked, and the source and destination operands either remain unchanged or a biased result
is stored in the destination operand (depending whether the overflow exception was generated during an
SSE/SSE2/SSE3 floating-point operation or an x87 FPU operation).
Table 4-10. Masked Responses to Numeric Overflow
Rounding Mode
Sign of True Result
Result
To nearest
+
+∞
–
–∞
+
Largest finite positive number
–
–∞
+
+∞
–
Largest finite negative number
+
Largest finite positive number
–
Largest finite negative number
Toward –∞
Toward +∞
Toward zero
See the following sections for information regarding the numeric overflow exception when detected while executing
x87 FPU instructions or while executing SSE/SSE2/SSE3 instructions:
•
•
x87 FPU; Section 8.5.4, “Numeric Overflow Exception (#O)”
SIMD floating-point exceptions; Section 11.5.2.4, “Numeric Overflow Exception (#O)”
4.9.1.5
Numeric Underflow Exception (#U)
The processor detects a potential floating-point numeric underflow condition whenever the result of rounding with
unbounded exponent (taking into account precision control for x87) is non-zero and tiny; that is, non-zero and less
than the smallest possible normalized, finite value that will fit into the destination operand. Table 4-11 shows the
threshold range for numeric underflow for each of the floating-point formats (assuming normalized results);
underflow occurs when a rounded result falls strictly within the threshold range. The ability to detect and handle
underflow is provided to prevent a very small result from propagating through a computation and causing another
exception (such as overflow during division) to be generated at a later time. Results which trigger underflow are
also potentially less accurate.
Table 4-11. Numeric Underflow (Normalized) Thresholds
Floating-Point Format
Underflow Thresholds*
Single Precision
| x | < 1.0 ∗ 2−126
Double Precision
| x | < 1.0 ∗ 2−1022
Double Extended Precision
| x | < 1.0 ∗ 2−16382
* Where ‘x’ is the result rounded to destination precision with an unbounded exponent range.
Vol. 1 4-21
DATA TYPES
How the processor handles an underflow condition, depends on two related conditions:
•
•
creation of a tiny, non-zero result
creation of an inexact result; that is, a result that cannot be represented exactly in the destination format
Which of these events causes an underflow exception to be reported and how the processor responds to the exception condition depends on whether the underflow exception is masked:
•
Underflow exception masked — The underflow exception is reported (the UE flag is set) only when the result
is both tiny and inexact. The processor returns a correctly signed result whose magnitude is less than or equal
to the smallest positive normal floating-point number to the destination operand, regardless of inexactness.
•
Underflow exception not masked — The underflow exception is reported when the result is non-zero tiny,
regardless of inexactness. The processor leaves the source and destination operands unaltered or stores a
biased result in the destination operand (depending whether the underflow exception was generated during an
SSE/SSE2/SSE3 floating-point operation or an x87 FPU operation) and invokes a software exception handler.
See the following sections for information regarding the numeric underflow exception when detected while
executing x87 FPU instructions or while executing SSE/SSE2/SSE3 instructions:
•
•
x87 FPU; Section 8.5.5, “Numeric Underflow Exception (#U)”
SIMD floating-point exceptions; Section 11.5.2.5, “Numeric Underflow Exception (#U)”
4.9.1.6
Inexact-Result (Precision) Exception (#P)
The inexact-result exception (also called the precision exception) occurs if the result of an operation is not exactly
representable in the destination format. For example, the fraction 1/3 cannot be precisely represented in binary
floating-point form. This exception occurs frequently and indicates that some (normally acceptable) accuracy will
be lost due to rounding. The exception is supported for applications that need to perform exact arithmetic only.
Because the rounded result is generally satisfactory for most applications, this exception is commonly masked.
If the inexact-result exception is masked when an inexact-result condition occurs and a numeric overflow or underflow condition has not occurred, the processor sets the PE flag and stores the rounded result in the destination
operand. The current rounding mode determines the method used to round the result. See Section 4.8.4,
“Rounding.”
If the inexact-result exception is not masked when an inexact result occurs and numeric overflow or underflow has
not occurred, the PE flag is set, the rounded result is stored in the destination operand, and a software exception
handler is invoked.
If an inexact result occurs in conjunction with numeric overflow or underflow, one of the following operations is
carried out:
•
If an inexact result occurs along with masked overflow or underflow, the OE flag or UE flag and the PE flag are
set and the result is stored as described for the overflow or underflow exceptions; see Section 4.9.1.4,
“Numeric Overflow Exception (#O),” or Section 4.9.1.5, “Numeric Underflow Exception (#U).” If the inexact
result exception is unmasked, the processor also invokes a software exception handler.
•
If an inexact result occurs along with unmasked overflow or underflow and the destination operand is a register,
the OE or UE flag and the PE flag are set, the result is stored as described for the overflow or underflow
exceptions, and a software exception handler is invoked.
If an unmasked numeric overflow or underflow exception occurs and the destination operand is a memory location
(which can happen only for a floating-point store), the inexact-result condition is not reported and the C1 flag is
cleared.
See the following sections for information regarding the inexact-result exception when detected while executing
x87 FPU or SSE/SSE2/SSE3 instructions:
•
•
x87 FPU; Section 8.5.6, “Inexact-Result (Precision) Exception (#P)”
SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception (#Z)”
4-22 Vol. 1
DATA TYPES
4.9.2
Floating-Point Exception Priority
The processor handles exceptions according to a predetermined precedence. When an instruction generates two or
more exception conditions, the exception precedence sometimes results in the higher-priority exception being
handled and the lower-priority exceptions being ignored. For example, dividing an SNaN by zero can potentially
signal an invalid-operation exception (due to the SNaN operand) and a divide-by-zero exception. Here, if both
exceptions are masked, the processor handles the higher-priority exception only (the invalid-operation exception),
returning a QNaN to the destination. Alternately, a denormal-operand or inexact-result exception can accompany
a numeric underflow or overflow exception with both exceptions being handled.
The precedence for floating-point exceptions is as follows:
1. Invalid-operation exception, subdivided as follows:
a. stack underflow (occurs with x87 FPU only)
b. stack overflow (occurs with x87 FPU only)
c.
operand of unsupported format (occurs with x87 FPU only when using the double extended-precision
floating-point format)
d. SNaN operand
2. QNaN operand. Though this is not an exception, the handling of a QNaN operand has precedence over lowerpriority exceptions. For example, a QNaN divided by zero results in a QNaN, not a zero-divide exception.
3. Any other invalid-operation exception not mentioned above or a divide-by-zero exception.
4. Denormal-operand exception. If masked, then instruction execution continues and a lower-priority exception
can occur as well.
5. Numeric overflow and underflow exceptions; possibly in conjunction with the inexact-result exception.
6. Inexact-result exception.
Invalid operation, zero divide, and denormal operand exceptions are detected before a floating-point operation
begins. Overflow, underflow, and precision exceptions are not detected until a true result has been computed.
When an unmasked pre-operation exception is detected, the destination operand has not yet been updated, and
appears as if the offending instruction has not been executed. When an unmasked post-operation exception is
detected, the destination operand may be updated with a result, depending on the nature of the exception (except
for SSE/SSE2/SSE3 instructions, which do not update their destination operands in such cases).
4.9.3
Typical Actions of a Floating-Point Exception Handler
After the floating-point exception handler is invoked, the processor handles the exception in the same manner that
it handles non-floating-point exceptions. The floating-point exception handler is normally part of the operating
system or executive software, and it usually invokes a user-registered floating-point exception handle.
A typical action of the exception handler is to store state information in memory. Other typical exception handler
actions include:
•
•
•
•
Examining the stored state information to determine the nature of the error
Taking actions to correct the condition that caused the error
Clearing the exception flags
Returning to the interrupted program and resuming normal execution
In lieu of writing recovery procedures, the exception handler can do the following:
•
•
•
Increment in software an exception counter for later display or printing
Print or display diagnostic information (such as the state information)
Halt further program execution
Vol. 1 4-23
DATA TYPES
4-24 Vol. 1
CHAPTER 5
INSTRUCTION SET SUMMARY
This chapter provides an abridged overview of Intel 64 and IA-32 instructions. Instructions are divided into the
following groups:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
General purpose
x87 FPU
x87 FPU and SIMD state management
Intel® MMX technology
SSE extensions
SSE2 extensions
SSE3 extensions
SSSE3 extensions
SSE4 extensions
AESNI and PCLMULQDQ
Intel® AVX extensions
F16C, RDRAND, RDSEED, FS/GS base access
FMA extensions
Intel® AVX2 extensions
Intel® Transactional Synchronization extensions
System instructions
IA-32e mode: 64-bit mode instructions
VMX instructions
SMX instructions
ADCX and ADOX
Intel® Memory Protection Extensions
Intel® Security Guard Extensions
Table 5-1 lists the groups and IA-32 processors that support each group. More recent instruction set extensions are
listed in Table 5-2. Within these groups, most instructions are collected into functional subgroups.
Table 5-1. Instruction Groups in Intel 64 and IA-32 Processors
Instruction Set
Architecture
Intel 64 and IA-32 Processor Support
General Purpose
All Intel 64 and IA-32 processors.
x87 FPU
Intel486, Pentium, Pentium with MMX Technology, Celeron, Pentium Pro, Pentium II, Pentium II Xeon,
Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo,
Intel Core 2 Duo processors, Intel Atom processors.
x87 FPU and SIMD State
Management
Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors, Pentium M,
Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors, Intel Atom processors.
MMX Technology
Pentium with MMX Technology, Celeron, Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium
4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors, Intel Atom
processors.
SSE Extensions
Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo,
Intel Core 2 Duo processors, Intel Atom processors.
Vol. 1 5-1
INSTRUCTION SET SUMMARY
Table 5-1. Instruction Groups in Intel 64 and IA-32 Processors (Contd.)
Instruction Set
Architecture
Intel 64 and IA-32 Processor Support
SSE2 Extensions
Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors,
Intel Atom processors.
SSE3 Extensions
Pentium 4 supporting HT Technology (built on 90nm process technology), Intel Core Solo, Intel Core Duo,
Intel Core 2 Duo processors, Intel Xeon processor 3xxxx, 5xxx, 7xxx Series, Intel Atom processors.
SSSE3 Extensions
Intel Xeon processor 3xxx, 5100, 5200, 5300, 5400, 5500, 5600, 7300, 7400, 7500 series, Intel Core 2
Extreme processors QX6000 series, Intel Core 2 Duo, Intel Core 2 Quad processors, Intel Pentium Dual-Core
processors, Intel Atom processors.
IA-32e mode: 64-bit
mode instructions
Intel 64 processors.
System Instructions
Intel 64 and IA-32 processors.
VMX Instructions
Intel 64 and IA-32 processors supporting Intel Virtualization Technology.
SMX Instructions
Intel Core 2 Duo processor E6x50, E8xxx; Intel Core 2 Quad processor Q9xxx.
Table 5-2. Recent Instruction Set Extensions Introduction in Intel 64 and IA-32 Processors
Instruction Set
Architecture
Processor Generation Introduction
SSE4.1 Extensions
Intel Xeon processor 3100, 3300, 5200, 5400, 7400, 7500 series, Intel Core 2 Extreme processors
QX9000 series, Intel Core 2 Quad processor Q9000 series, Intel Core 2 Duo processors 8000 series, T9000
series.
SSE4.2 Extensions,
CRC32, POPCNT
Intel Core i7 965 processor, Intel Xeon processors X3400, X3500, X5500, X6500, X7500 series.
AESNI, PCLMULQDQ
InteL Xeon processor E7 series, Intel Xeon processors X3600, X5600, Intel Core i7 980X processor; Use
CPUID to verify presence of AESNI and PCLMULQDQ across Intel Core processor families.
Intel AVX
Intel Xeon processor E3 and E5 families; 2nd Generation Intel Core i7, i5, i3 processor 2xxx families.
F16C, RDRAND, FS/GS
base access
3rd Generation Intel Core processors, Intel Xeon processor E3-1200 v2 product family, Next Generation
Intel Xeon processors, Intel Xeon processor E5 v2 and E7 v2 families.
FMA, AVX2, BMI1, BMI2,
INVPCID
Intel Xeon processor E3-1200 v3 product family; 4th Generation Intel Core processor family.
TSX
Intel Xeon processor E7 v3 product family.
ADX, RDSEED, CLAC,
STAC
Intel Core M processor family; 5th Generation Intel Core processor family.
CLFLUSHOPT, XSAVEC,
XSAVES, MPX, SGX1
6th Generation Intel Core processor family.
The following sections list instructions in each major group and subgroup. Given for each instruction is its
mnemonic and descriptive names. When two or more mnemonics are given (for example, CMOVA/CMOVNBE), they
represent different mnemonics for the same instruction opcode. Assemblers support redundant mnemonics for
some instructions to make it easier to read code listings. For instance, CMOVA (Conditional move if above) and
CMOVNBE (Conditional move if not below or equal) represent the same condition. For detailed information about
specific instructions, see the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C
& 2D.
5-2 Vol. 1
INSTRUCTION SET SUMMARY
5.1
GENERAL-PURPOSE INSTRUCTIONS
The general-purpose instructions preform basic data movement, arithmetic, logic, program flow, and string operations that programmers commonly use to write application and system software to run on Intel 64 and IA-32
processors. They operate on data contained in memory, in the general-purpose registers (EAX, EBX, ECX, EDX,
EDI, ESI, EBP, and ESP) and in the EFLAGS register. They also operate on address information contained in
memory, the general-purpose registers, and the segment registers (CS, DS, SS, ES, FS, and GS).
This group of instructions includes the data transfer, binary integer arithmetic, decimal arithmetic, logic operations,
shift and rotate, bit and byte operations, program control, string, flag control, segment register operations, and
miscellaneous subgroups. The sections that following introduce each subgroup.
For more detailed information on general purpose-instructions, see Chapter 7, “Programming With GeneralPurpose Instructions.”
5.1.1
Data Transfer Instructions
The data transfer instructions move data between memory and the general-purpose and segment registers. They
also perform specific operations such as conditional moves, stack access, and data conversion.
MOV
Move data between general-purpose registers; move data between memory and generalpurpose or segment registers; move immediates to general-purpose registers.
CMOVE/CMOVZ
Conditional move if equal/Conditional move if zero.
CMOVNE/CMOVNZ
Conditional move if not equal/Conditional move if not zero.
CMOVA/CMOVNBE
Conditional move if above/Conditional move if not below or equal.
CMOVAE/CMOVNB
Conditional move if above or equal/Conditional move if not below.
CMOVB/CMOVNAE
Conditional move if below/Conditional move if not above or equal.
CMOVBE/CMOVNA
Conditional move if below or equal/Conditional move if not above.
CMOVG/CMOVNLE
Conditional move if greater/Conditional move if not less or equal.
CMOVGE/CMOVNL
Conditional move if greater or equal/Conditional move if not less.
CMOVL/CMOVNGE
Conditional move if less/Conditional move if not greater or equal.
CMOVLE/CMOVNG
Conditional move if less or equal/Conditional move if not greater.
CMOVC
Conditional move if carry.
CMOVNC
Conditional move if not carry.
CMOVO
Conditional move if overflow.
CMOVNO
Conditional move if not overflow.
CMOVS
Conditional move if sign (negative).
CMOVNS
Conditional move if not sign (non-negative).
CMOVP/CMOVPE
Conditional move if parity/Conditional move if parity even.
CMOVNP/CMOVPO
Conditional move if not parity/Conditional move if parity odd.
XCHG
Exchange.
BSWAP
Byte swap.
XADD
Exchange and add.
CMPXCHG
Compare and exchange.
CMPXCHG8B
Compare and exchange 8 bytes.
PUSH
Push onto stack.
POP
Pop off of stack.
PUSHA/PUSHAD
Push general-purpose registers onto stack.
POPA/POPAD
Pop general-purpose registers from stack.
CWD/CDQ
Convert word to doubleword/Convert doubleword to quadword.
CBW/CWDE
Convert byte to word/Convert word to doubleword in EAX register.
MOVSX
Move and sign extend.
Vol. 1 5-3
INSTRUCTION SET SUMMARY
MOVZX
5.1.2
Move and zero extend.
Binary Arithmetic Instructions
The binary arithmetic instructions perform basic binary integer computations on byte, word, and doubleword integers located in memory and/or the general purpose registers.
ADCX
Unsigned integer add with carry.
ADOX
Unsigned integer add with overflow.
ADD
Integer add.
ADC
Add with carry.
SUB
Subtract.
SBB
Subtract with borrow.
IMUL
Signed multiply.
MUL
Unsigned multiply.
IDIV
Signed divide.
DIV
Unsigned divide.
INC
Increment.
DEC
Decrement.
NEG
Negate.
CMP
Compare.
5.1.3
Decimal Arithmetic Instructions
The decimal arithmetic instructions perform decimal arithmetic on binary coded decimal (BCD) data.
DAA
Decimal adjust after addition.
DAS
Decimal adjust after subtraction.
AAA
ASCII adjust after addition.
AAS
ASCII adjust after subtraction.
AAM
ASCII adjust after multiplication.
AAD
ASCII adjust before division.
5.1.4
Logical Instructions
The logical instructions perform basic AND, OR, XOR, and NOT logical operations on byte, word, and doubleword
values.
AND
Perform bitwise logical AND.
OR
Perform bitwise logical OR.
XOR
Perform bitwise logical exclusive OR.
NOT
Perform bitwise logical NOT.
5.1.5
Shift and Rotate Instructions
The shift and rotate instructions shift and rotate the bits in word and doubleword operands.
SAR
Shift arithmetic right.
SHR
Shift logical right.
SAL/SHL
Shift arithmetic left/Shift logical left.
SHRD
Shift right double.
5-4 Vol. 1
INSTRUCTION SET SUMMARY
SHLD
Shift left double.
ROR
Rotate right.
ROL
Rotate left.
RCR
Rotate through carry right.
RCL
Rotate through carry left.
5.1.6
Bit and Byte Instructions
Bit instructions test and modify individual bits in word and doubleword operands. Byte instructions set the value of
a byte operand to indicate the status of flags in the EFLAGS register.
BT
Bit test.
BTS
Bit test and set.
BTR
Bit test and reset.
BTC
Bit test and complement.
BSF
Bit scan forward.
BSR
Bit scan reverse.
SETE/SETZ
Set byte if equal/Set byte if zero.
SETNE/SETNZ
Set byte if not equal/Set byte if not zero.
SETA/SETNBE
Set byte if above/Set byte if not below or equal.
SETAE/SETNB/SETNC Set byte if above or equal/Set byte if not below/Set byte if not carry.
SETB/SETNAE/SETC
Set byte if below/Set byte if not above or equal/Set byte if carry.
SETBE/SETNA
Set byte if below or equal/Set byte if not above.
SETG/SETNLE
Set byte if greater/Set byte if not less or equal.
SETGE/SETNL
Set byte if greater or equal/Set byte if not less.
SETL/SETNGE
Set byte if less/Set byte if not greater or equal.
SETLE/SETNG
Set byte if less or equal/Set byte if not greater.
SETS
Set byte if sign (negative).
SETNS
Set byte if not sign (non-negative).
SETO
Set byte if overflow.
SETNO
Set byte if not overflow.
SETPE/SETP
Set byte if parity even/Set byte if parity.
SETPO/SETNP
Set byte if parity odd/Set byte if not parity.
TEST
Logical compare.
CRC321
Provides hardware acceleration to calculate cyclic redundancy checks for fast and efficient
implementation of data integrity protocols.
POPCNT2
This instruction calculates of number of bits set to 1 in the second operand (source) and
returns the count in the first operand (a destination register).
5.1.7
Control Transfer Instructions
The control transfer instructions provide jump, conditional jump, loop, and call and return operations to control
program flow.
JMP
Jump.
JE/JZ
Jump if equal/Jump if zero.
JNE/JNZ
Jump if not equal/Jump if not zero.
1. Processor support of CRC32 is enumerated by CPUID.01:ECX[SSE4.2] = 1
2. Processor support of POPCNT is enumerated by CPUID.01:ECX[POPCNT] = 1
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INSTRUCTION SET SUMMARY
JA/JNBE
Jump if above/Jump if not below or equal.
JAE/JNB
Jump if above or equal/Jump if not below.
JB/JNAE
Jump if below/Jump if not above or equal.
JBE/JNA
Jump if below or equal/Jump if not above.
JG/JNLE
Jump if greater/Jump if not less or equal.
JGE/JNL
Jump if greater or equal/Jump if not less.
JL/JNGE
Jump if less/Jump if not greater or equal.
JLE/JNG
Jump if less or equal/Jump if not greater.
JC
Jump if carry.
JNC
Jump if not carry.
JO
Jump if overflow.
JNO
Jump if not overflow.
JS
Jump if sign (negative).
JNS
Jump if not sign (non-negative).
JPO/JNP
Jump if parity odd/Jump if not parity.
JPE/JP
Jump if parity even/Jump if parity.
JCXZ/JECXZ
Jump register CX zero/Jump register ECX zero.
LOOP
Loop with ECX counter.
LOOPZ/LOOPE
Loop with ECX and zero/Loop with ECX and equal.
LOOPNZ/LOOPNE
Loop with ECX and not zero/Loop with ECX and not equal.
CALL
Call procedure.
RET
Return.
IRET
Return from interrupt.
INT
Software interrupt.
INTO
Interrupt on overflow.
BOUND
Detect value out of range.
ENTER
High-level procedure entry.
LEAVE
High-level procedure exit.
5.1.8
String Instructions
The string instructions operate on strings of bytes, allowing them to be moved to and from memory.
MOVS/MOVSB
Move string/Move byte string.
MOVS/MOVSW
Move string/Move word string.
MOVS/MOVSD
Move string/Move doubleword string.
CMPS/CMPSB
Compare string/Compare byte string.
CMPS/CMPSW
Compare string/Compare word string.
CMPS/CMPSD
Compare string/Compare doubleword string.
SCAS/SCASB
Scan string/Scan byte string.
SCAS/SCASW
Scan string/Scan word string.
SCAS/SCASD
Scan string/Scan doubleword string.
LODS/LODSB
Load string/Load byte string.
LODS/LODSW
Load string/Load word string.
LODS/LODSD
Load string/Load doubleword string.
STOS/STOSB
Store string/Store byte string.
STOS/STOSW
Store string/Store word string.
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INSTRUCTION SET SUMMARY
STOS/STOSD
Store string/Store doubleword string.
REP
Repeat while ECX not zero.
REPE/REPZ
Repeat while equal/Repeat while zero.
REPNE/REPNZ
Repeat while not equal/Repeat while not zero.
5.1.9
I/O Instructions
These instructions move data between the processor’s I/O ports and a register or memory.
IN
Read from a port.
OUT
Write to a port.
INS/INSB
Input string from port/Input byte string from port.
INS/INSW
Input string from port/Input word string from port.
INS/INSD
Input string from port/Input doubleword string from port.
OUTS/OUTSB
Output string to port/Output byte string to port.
OUTS/OUTSW
Output string to port/Output word string to port.
OUTS/OUTSD
Output string to port/Output doubleword string to port.
5.1.10
Enter and Leave Instructions
These instructions provide machine-language support for procedure calls in block-structured languages.
ENTER
High-level procedure entry.
LEAVE
High-level procedure exit.
5.1.11
Flag Control (EFLAG) Instructions
The flag control instructions operate on the flags in the EFLAGS register.
STC
Set carry flag.
CLC
Clear the carry flag.
CMC
Complement the carry flag.
CLD
Clear the direction flag.
STD
Set direction flag.
LAHF
Load flags into AH register.
SAHF
Store AH register into flags.
PUSHF/PUSHFD
Push EFLAGS onto stack.
POPF/POPFD
Pop EFLAGS from stack.
STI
Set interrupt flag.
CLI
Clear the interrupt flag.
5.1.12
Segment Register Instructions
The segment register instructions allow far pointers (segment addresses) to be loaded into the segment registers.
LDS
Load far pointer using DS.
LES
Load far pointer using ES.
LFS
Load far pointer using FS.
LGS
Load far pointer using GS.
LSS
Load far pointer using SS.
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INSTRUCTION SET SUMMARY
5.1.13
Miscellaneous Instructions
The miscellaneous instructions provide such functions as loading an effective address, executing a “no-operation,”
and retrieving processor identification information.
LEA
Load effective address.
NOP
No operation.
UD2
Undefined instruction.
XLAT/XLATB
Table lookup translation.
CPUID
Processor identification.
MOVBE1
Move data after swapping data bytes.
PREFETCHW
Prefetch data into cache in anticipation of write.
PREFETCHWT1
Prefetch hint T1 with intent to write.
CLFLUSH
Flushes and invalidates a memory operand and its associated cache line from all levels of
the processor’s cache hierarchy.
CLFLUSHOPT
Flushes and invalidates a memory operand and its associated cache line from all levels of
the processor’s cache hierarchy with optimized memory system throughput.
5.1.14
User Mode Extended Sate Save/Restore Instructions
XSAVE
Save processor extended states to memory.
XSAVEC
Save processor extended states with compaction to memory.
XSAVEOPT
Save processor extended states to memory, optimized.
XRSTOR
Restore processor extended states from memory.
XGETBV
Reads the state of an extended control register.
5.1.15
Random Number Generator Instructions
RDRAND
Retrieves a random number generated from hardware.
RDSEED
Retrieves a random number generated from hardware.
5.1.16
ANDN
BMI1, BMI2
Bitwise AND of first source with inverted 2nd source operands.
BEXTR
Contiguous bitwise extract.
BLSI
Extract lowest set bit.
BLSMSK
Set all lower bits below first set bit to 1.
BLSR
Reset lowest set bit.
BZHI
Zero high bits starting from specified bit position.
LZCNT
Count the number leading zero bits.
MULX
Unsigned multiply without affecting arithmetic flags.
PDEP
Parallel deposit of bits using a mask.
PEXT
Parallel extraction of bits using a mask.
RORX
Rotate right without affecting arithmetic flags.
SARX
Shift arithmetic right.
SHLX
Shift logic left.
SHRX
Shift logic right.
TZCNT
Count the number trailing zero bits.
1. Processor support of MOVBE is enumerated by CPUID.01:ECX.MOVBE[bit 22] = 1.
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INSTRUCTION SET SUMMARY
5.1.16.1
Detection of VEX-encoded GPR Instructions, LZCNT and TZCNT, PREFETCHW
VEX-encoded general-purpose instructions do not operate on any vector registers.
There are separate feature flags for the following subsets of instructions that operate on general purpose registers,
and the detection requirements for hardware support are:
CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]: if 1 indicates the processor supports the first group of advanced bit
manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT);
CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]: if 1 indicates the processor supports the second group of advanced
bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX);
CPUID.EAX=80000001H:ECX.LZCNT[bit 5]: if 1 indicates the processor supports the LZCNT instruction.
CPUID.EAX=80000001H:ECX.PREFTEHCHW[bit 8]: if 1 indicates the processor supports the PREFTEHCHW instruction. CPUID.(EAX=07H, ECX=0H):ECX.PREFTEHCHWT1[bit 0]: if 1 indicates the processor supports the
PREFTEHCHWT1 instruction.
5.2
X87 FPU INSTRUCTIONS
The x87 FPU instructions are executed by the processor’s x87 FPU. These instructions operate on floating-point,
integer, and binary-coded decimal (BCD) operands. For more detail on x87 FPU instructions, see Chapter 8,
“Programming with the x87 FPU.”
These instructions are divided into the following subgroups: data transfer, load constants, and FPU control instructions. The sections that follow introduce each subgroup.
5.2.1
x87 FPU Data Transfer Instructions
The data transfer instructions move floating-point, integer, and BCD values between memory and the x87 FPU
registers. They also perform conditional move operations on floating-point operands.
FLD
Load floating-point value.
FST
Store floating-point value.
FSTP
Store floating-point value and pop.
FILD
Load integer.
FIST
Store integer.
FISTP1
Store integer and pop.
FBLD
Load BCD.
FBSTP
Store BCD and pop.
FXCH
Exchange registers.
FCMOVE
Floating-point conditional move if equal.
FCMOVNE
Floating-point conditional move if not equal.
FCMOVB
Floating-point conditional move if below.
FCMOVBE
Floating-point conditional move if below or equal.
FCMOVNB
Floating-point conditional move if not below.
FCMOVNBE
Floating-point conditional move if not below or equal.
FCMOVU
Floating-point conditional move if unordered.
FCMOVNU
Floating-point conditional move if not unordered.
5.2.2
x87 FPU Basic Arithmetic Instructions
The basic arithmetic instructions perform basic arithmetic operations on floating-point and integer operands.
1. SSE3 provides an instruction FISTTP for integer conversion.
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INSTRUCTION SET SUMMARY
FADD
Add floating-point
FADDP
Add floating-point and pop
FIADD
Add integer
FSUB
Subtract floating-point
FSUBP
Subtract floating-point and pop
FISUB
Subtract integer
FSUBR
Subtract floating-point reverse
FSUBRP
Subtract floating-point reverse and pop
FISUBR
Subtract integer reverse
FMUL
Multiply floating-point
FMULP
Multiply floating-point and pop
FIMUL
Multiply integer
FDIV
Divide floating-point
FDIVP
Divide floating-point and pop
FIDIV
Divide integer
FDIVR
Divide floating-point reverse
FDIVRP
Divide floating-point reverse and pop
FIDIVR
Divide integer reverse
FPREM
Partial remainder
FPREM1
IEEE Partial remainder
FABS
Absolute value
FCHS
Change sign
FRNDINT
Round to integer
FSCALE
Scale by power of two
FSQRT
Square root
FXTRACT
Extract exponent and significand
5.2.3
x87 FPU Comparison Instructions
The compare instructions examine or compare floating-point or integer operands.
FCOM
Compare floating-point.
FCOMP
Compare floating-point and pop.
FCOMPP
Compare floating-point and pop twice.
FUCOM
Unordered compare floating-point.
FUCOMP
Unordered compare floating-point and pop.
FUCOMPP
Unordered compare floating-point and pop twice.
FICOM
Compare integer.
FICOMP
Compare integer and pop.
FCOMI
Compare floating-point and set EFLAGS.
FUCOMI
Unordered compare floating-point and set EFLAGS.
FCOMIP
Compare floating-point, set EFLAGS, and pop.
FUCOMIP
Unordered compare floating-point, set EFLAGS, and pop.
FTST
Test floating-point (compare with 0.0).
FXAM
Examine floating-point.
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INSTRUCTION SET SUMMARY
5.2.4
x87 FPU Transcendental Instructions
The transcendental instructions perform basic trigonometric and logarithmic operations on floating-point operands.
FSIN
Sine
FCOS
Cosine
FSINCOS
Sine and cosine
FPTAN
Partial tangent
FPATAN
Partial arctangent
F2XM1
2x − 1
FYL2X
y∗log2x
FYL2XP1
y∗log2(x+1)
5.2.5
x87 FPU Load Constants Instructions
The load constants instructions load common constants, such as π, into the x87 floating-point registers.
FLD1
Load +1.0
FLDZ
Load +0.0
FLDPI
Load π
FLDL2E
Load log2e
FLDLN2
Load loge2
FLDL2T
Load log210
FLDLG2
Load log102
5.2.6
x87 FPU Control Instructions
The x87 FPU control instructions operate on the x87 FPU register stack and save and restore the x87 FPU state.
FINCSTP
FDECSTP
FFREE
FINIT
FNINIT
FCLEX
FNCLEX
FSTCW
FNSTCW
FLDCW
FSTENV
FNSTENV
FLDENV
FSAVE
FNSAVE
FRSTOR
FSTSW
FNSTSW
WAIT/FWAIT
FNOP
Increment FPU register stack pointer.
Decrement FPU register stack pointer.
Free floating-point register.
Initialize FPU after checking error conditions.
Initialize FPU without checking error conditions.
Clear floating-point exception flags after checking for error conditions.
Clear floating-point exception flags without checking for error conditions.
Store FPU control word after checking error conditions.
Store FPU control word without checking error conditions.
Load FPU control word.
Store FPU environment after checking error conditions.
Store FPU environment without checking error conditions.
Load FPU environment.
Save FPU state after checking error conditions.
Save FPU state without checking error conditions.
Restore FPU state.
Store FPU status word after checking error conditions.
Store FPU status word without checking error conditions.
Wait for FPU.
FPU no operation.
Vol. 1 5-11
INSTRUCTION SET SUMMARY
5.3
X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS
Two state management instructions were introduced into the IA-32 architecture with the Pentium II processor
family:
FXSAVE
FXRSTOR
Save x87 FPU and SIMD state.
Restore x87 FPU and SIMD state.
Initially, these instructions operated only on the x87 FPU (and MMX) registers to perform a fast save and restore,
respectively, of the x87 FPU and MMX state. With the introduction of SSE extensions in the Pentium III processor
family, these instructions were expanded to also save and restore the state of the XMM and MXCSR registers. Intel
64 architecture also supports these instructions.
See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for more detail.
5.4
MMX™ INSTRUCTIONS
Four extensions have been introduced into the IA-32 architecture to permit IA-32 processors to perform singleinstruction multiple-data (SIMD) operations. These extensions include the MMX technology, SSE extensions, SSE2
extensions, and SSE3 extensions. For a discussion that puts SIMD instructions in their historical context, see
Section 2.2.7, “SIMD Instructions.”
MMX instructions operate on packed byte, word, doubleword, or quadword integer operands contained in memory,
in MMX registers, and/or in general-purpose registers. For more detail on these instructions, see Chapter 9,
“Programming with Intel® MMX™ Technology.”
MMX instructions can only be executed on Intel 64 and IA-32 processors that support the MMX technology. Support
for these instructions can be detected with the CPUID instruction. See the description of the CPUID instruction in
Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
MMX instructions are divided into the following subgroups: data transfer, conversion, packed arithmetic, comparison, logical, shift and rotate, and state management instructions. The sections that follow introduce each
subgroup.
5.4.1
MMX Data Transfer Instructions
The data transfer instructions move doubleword and quadword operands between MMX registers and between MMX
registers and memory.
MOVD
MOVQ
5.4.2
Move doubleword.
Move quadword.
MMX Conversion Instructions
The conversion instructions pack and unpack bytes, words, and doublewords
PACKSSWB
Pack words into bytes with signed saturation.
PACKSSDW
Pack doublewords into words with signed saturation.
PACKUSWB
Pack words into bytes with unsigned saturation.
PUNPCKHBW
Unpack high-order bytes.
PUNPCKHWD
Unpack high-order words.
PUNPCKHDQ
Unpack high-order doublewords.
PUNPCKLBW
Unpack low-order bytes.
PUNPCKLWD
Unpack low-order words.
PUNPCKLDQ
Unpack low-order doublewords.
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INSTRUCTION SET SUMMARY
5.4.3
MMX Packed Arithmetic Instructions
The packed arithmetic instructions perform packed integer arithmetic on packed byte, word, and doubleword integers.
PADDB
PADDW
PADDD
PADDSB
PADDSW
PADDUSB
PADDUSW
PSUBB
PSUBW
PSUBD
PSUBSB
PSUBSW
PSUBUSB
PSUBUSW
PMULHW
PMULLW
PMADDWD
5.4.4
Add packed byte integers.
Add packed word integers.
Add packed doubleword integers.
Add packed signed byte integers with signed saturation.
Add packed signed word integers with signed saturation.
Add packed unsigned byte integers with unsigned saturation.
Add packed unsigned word integers with unsigned saturation.
Subtract packed byte integers.
Subtract packed word integers.
Subtract packed doubleword integers.
Subtract packed signed byte integers with signed saturation.
Subtract packed signed word integers with signed saturation.
Subtract packed unsigned byte integers with unsigned saturation.
Subtract packed unsigned word integers with unsigned saturation.
Multiply packed signed word integers and store high result.
Multiply packed signed word integers and store low result.
Multiply and add packed word integers.
MMX Comparison Instructions
The compare instructions compare packed bytes, words, or doublewords.
PCMPEQB
PCMPEQW
PCMPEQD
PCMPGTB
PCMPGTW
PCMPGTD
5.4.5
Compare
Compare
Compare
Compare
Compare
Compare
packed
packed
packed
packed
packed
packed
bytes for equal.
words for equal.
doublewords for equal.
signed byte integers for greater than.
signed word integers for greater than.
signed doubleword integers for greater than.
MMX Logical Instructions
The logical instructions perform AND, AND NOT, OR, and XOR operations on quadword operands.
PAND
PANDN
POR
PXOR
5.4.6
Bitwise
Bitwise
Bitwise
Bitwise
logical
logical
logical
logical
AND.
AND NOT.
OR.
exclusive OR.
MMX Shift and Rotate Instructions
The shift and rotate instructions shift and rotate packed bytes, words, or doublewords, or quadwords in 64-bit
operands.
PSLLW
Shift packed words left logical.
PSLLD
Shift packed doublewords left logical.
PSLLQ
Shift packed quadword left logical.
PSRLW
Shift packed words right logical.
PSRLD
Shift packed doublewords right logical.
PSRLQ
Shift packed quadword right logical.
Vol. 1 5-13
INSTRUCTION SET SUMMARY
PSRAW
Shift packed words right arithmetic.
PSRAD
Shift packed doublewords right arithmetic.
5.4.7
MMX State Management Instructions
The EMMS instruction clears the MMX state from the MMX registers.
EMMS
5.5
Empty MMX state.
SSE INSTRUCTIONS
SSE instructions represent an extension of the SIMD execution model introduced with the MMX technology. For
more detail on these instructions, see Chapter 10, “Programming with Intel® Streaming SIMD Extensions (Intel®
SSE).”
SSE instructions can only be executed on Intel 64 and IA-32 processors that support SSE extensions. Support for
these instructions can be detected with the CPUID instruction. See the description of the CPUID instruction in
Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
SSE instructions are divided into four subgroups (note that the first subgroup has subordinate subgroups of its
own):
•
•
•
•
SIMD single-precision floating-point instructions that operate on the XMM registers.
MXCSR state management instructions.
64-bit SIMD integer instructions that operate on the MMX registers.
Cacheability control, prefetch, and instruction ordering instructions.
The following sections provide an overview of these groups.
5.5.1
SSE SIMD Single-Precision Floating-Point Instructions
These instructions operate on packed and scalar single-precision floating-point values located in XMM registers
and/or memory. This subgroup is further divided into the following subordinate subgroups: data transfer, packed
arithmetic, comparison, logical, shuffle and unpack, and conversion instructions.
5.5.1.1
SSE Data Transfer Instructions
SSE data transfer instructions move packed and scalar single-precision floating-point operands between XMM
registers and between XMM registers and memory.
MOVAPS
Move four aligned packed single-precision floating-point values between XMM registers or
between and XMM register and memory.
MOVUPS
Move four unaligned packed single-precision floating-point values between XMM registers
or between and XMM register and memory.
MOVHPS
Move two packed single-precision floating-point values to an from the high quadword of an
XMM register and memory.
MOVHLPS
Move two packed single-precision floating-point values from the high quadword of an XMM
register to the low quadword of another XMM register.
MOVLPS
Move two packed single-precision floating-point values to an from the low quadword of an
XMM register and memory.
MOVLHPS
Move two packed single-precision floating-point values from the low quadword of an XMM
register to the high quadword of another XMM register.
MOVMSKPS
Extract sign mask from four packed single-precision floating-point values.
5-14 Vol. 1
INSTRUCTION SET SUMMARY
MOVSS
5.5.1.2
Move scalar single-precision floating-point value between XMM registers or between an
XMM register and memory.
SSE Packed Arithmetic Instructions
SSE packed arithmetic instructions perform packed and scalar arithmetic operations on packed and scalar singleprecision floating-point operands.
ADDPS
Add packed single-precision floating-point values.
ADDSS
Add scalar single-precision floating-point values.
SUBPS
Subtract packed single-precision floating-point values.
SUBSS
Subtract scalar single-precision floating-point values.
MULPS
Multiply packed single-precision floating-point values.
MULSS
Multiply scalar single-precision floating-point values.
DIVPS
Divide packed single-precision floating-point values.
DIVSS
Divide scalar single-precision floating-point values.
RCPPS
Compute reciprocals of packed single-precision floating-point values.
RCPSS
Compute reciprocal of scalar single-precision floating-point values.
SQRTPS
Compute square roots of packed single-precision floating-point values.
SQRTSS
Compute square root of scalar single-precision floating-point values.
RSQRTPS
Compute reciprocals of square roots of packed single-precision floating-point values.
RSQRTSS
Compute reciprocal of square root of scalar single-precision floating-point values.
MAXPS
Return maximum packed single-precision floating-point values.
MAXSS
Return maximum scalar single-precision floating-point values.
MINPS
Return minimum packed single-precision floating-point values.
MINSS
Return minimum scalar single-precision floating-point values.
5.5.1.3
SSE Comparison Instructions
SSE compare instructions compare packed and scalar single-precision floating-point operands.
CMPPS
Compare packed single-precision floating-point values.
CMPSS
Compare scalar single-precision floating-point values.
COMISS
Perform ordered comparison of scalar single-precision floating-point values and set flags in
EFLAGS register.
UCOMISS
Perform unordered comparison of scalar single-precision floating-point values and set flags
in EFLAGS register.
5.5.1.4
SSE Logical Instructions
SSE logical instructions perform bitwise AND, AND NOT, OR, and XOR operations on packed single-precision
floating-point operands.
ANDPS
Perform bitwise logical AND of packed single-precision floating-point values.
ANDNPS
Perform bitwise logical AND NOT of packed single-precision floating-point values.
ORPS
Perform bitwise logical OR of packed single-precision floating-point values.
XORPS
Perform bitwise logical XOR of packed single-precision floating-point values.
5.5.1.5
SSE Shuffle and Unpack Instructions
SSE shuffle and unpack instructions shuffle or interleave single-precision floating-point values in packed singleprecision floating-point operands.
SHUFPS
Shuffles values in packed single-precision floating-point operands.
Vol. 1 5-15
INSTRUCTION SET SUMMARY
UNPCKHPS
Unpacks and interleaves the two high-order values from two single-precision floating-point
operands.
UNPCKLPS
Unpacks and interleaves the two low-order values from two single-precision floating-point
operands.
5.5.1.6
SSE Conversion Instructions
SSE conversion instructions convert packed and individual doubleword integers into packed and scalar single-precision floating-point values and vice versa.
CVTPI2PS
Convert packed doubleword integers to packed single-precision floating-point values.
CVTSI2SS
Convert doubleword integer to scalar single-precision floating-point value.
CVTPS2PI
Convert packed single-precision floating-point values to packed doubleword integers.
CVTTPS2PI
Convert with truncation packed single-precision floating-point values to packed doubleword integers.
CVTSS2SI
Convert a scalar single-precision floating-point value to a doubleword integer.
CVTTSS2SI
Convert with truncation a scalar single-precision floating-point value to a scalar doubleword integer.
5.5.2
SSE MXCSR State Management Instructions
MXCSR state management instructions allow saving and restoring the state of the MXCSR control and status
register.
LDMXCSR
Load MXCSR register.
STMXCSR
Save MXCSR register state.
5.5.3
SSE 64-Bit SIMD Integer Instructions
These SSE 64-bit SIMD integer instructions perform additional operations on packed bytes, words, or doublewords
contained in MMX registers. They represent enhancements to the MMX instruction set described in Section 5.4,
“MMX™ Instructions.”
PAVGB
Compute average of packed unsigned byte integers.
PAVGW
Compute average of packed unsigned word integers.
PEXTRW
Extract word.
PINSRW
Insert word.
PMAXUB
Maximum of packed unsigned byte integers.
PMAXSW
Maximum of packed signed word integers.
PMINUB
Minimum of packed unsigned byte integers.
PMINSW
Minimum of packed signed word integers.
PMOVMSKB
Move byte mask.
PMULHUW
Multiply packed unsigned integers and store high result.
PSADBW
Compute sum of absolute differences.
PSHUFW
Shuffle packed integer word in MMX register.
5.5.4
SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions
The cacheability control instructions provide control over the caching of non-temporal data when storing data from
the MMX and XMM registers to memory. The PREFETCHh allows data to be prefetched to a selected cache level. The
SFENCE instruction controls instruction ordering on store operations.
MASKMOVQ
5-16 Vol. 1
Non-temporal store of selected bytes from an MMX register into memory.
INSTRUCTION SET SUMMARY
MOVNTQ
Non-temporal store of quadword from an MMX register into memory.
MOVNTPS
Non-temporal store of four packed single-precision floating-point values from an XMM
register into memory.
PREFETCHh
Load 32 or more of bytes from memory to a selected level of the processor’s cache hierarchy
SFENCE
Serializes store operations.
5.6
SSE2 INSTRUCTIONS
SSE2 extensions represent an extension of the SIMD execution model introduced with MMX technology and the
SSE extensions. SSE2 instructions operate on packed double-precision floating-point operands and on packed
byte, word, doubleword, and quadword operands located in the XMM registers. For more detail on these instructions, see Chapter 11, “Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2).”
SSE2 instructions can only be executed on Intel 64 and IA-32 processors that support the SSE2 extensions.
Support for these instructions can be detected with the CPUID instruction. See the description of the CPUID
instruction in Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A.
These instructions are divided into four subgroups (note that the first subgroup is further divided into subordinate
subgroups):
•
•
•
•
Packed and scalar double-precision floating-point instructions.
Packed single-precision floating-point conversion instructions.
128-bit SIMD integer instructions.
Cacheability-control and instruction ordering instructions.
The following sections give an overview of each subgroup.
5.6.1
SSE2 Packed and Scalar Double-Precision Floating-Point Instructions
SSE2 packed and scalar double-precision floating-point instructions are divided into the following subordinate
subgroups: data movement, arithmetic, comparison, conversion, logical, and shuffle operations on double-precision floating-point operands. These are introduced in the sections that follow.
5.6.1.1
SSE2 Data Movement Instructions
SSE2 data movement instructions move double-precision floating-point data between XMM registers and between
XMM registers and memory.
MOVAPD
Move two aligned packed double-precision floating-point values between XMM registers or
between and XMM register and memory.
MOVUPD
Move two unaligned packed double-precision floating-point values between XMM registers
or between and XMM register and memory.
MOVHPD
Move high packed double-precision floating-point value to an from the high quadword of
an XMM register and memory.
MOVLPD
Move low packed single-precision floating-point value to an from the low quadword of an
XMM register and memory.
MOVMSKPD
Extract sign mask from two packed double-precision floating-point values.
MOVSD
Move scalar double-precision floating-point value between XMM registers or between an
XMM register and memory.
Vol. 1 5-17
INSTRUCTION SET SUMMARY
5.6.1.2
SSE2 Packed Arithmetic Instructions
The arithmetic instructions perform addition, subtraction, multiply, divide, square root, and maximum/minimum
operations on packed and scalar double-precision floating-point operands.
ADDPD
Add packed double-precision floating-point values.
ADDSD
Add scalar double precision floating-point values.
SUBPD
Subtract scalar double-precision floating-point values.
SUBSD
Subtract scalar double-precision floating-point values.
MULPD
Multiply packed double-precision floating-point values.
MULSD
Multiply scalar double-precision floating-point values.
DIVPD
Divide packed double-precision floating-point values.
DIVSD
Divide scalar double-precision floating-point values.
SQRTPD
Compute packed square roots of packed double-precision floating-point values.
SQRTSD
Compute scalar square root of scalar double-precision floating-point values.
MAXPD
Return maximum packed double-precision floating-point values.
MAXSD
Return maximum scalar double-precision floating-point values.
MINPD
Return minimum packed double-precision floating-point values.
MINSD
Return minimum scalar double-precision floating-point values.
5.6.1.3
SSE2 Logical Instructions
SSE2 logical instructions preform AND, AND NOT, OR, and XOR operations on packed double-precision floatingpoint values.
ANDPD
Perform bitwise logical AND of packed double-precision floating-point values.
ANDNPD
Perform bitwise logical AND NOT of packed double-precision floating-point values.
ORPD
Perform bitwise logical OR of packed double-precision floating-point values.
XORPD
Perform bitwise logical XOR of packed double-precision floating-point values.
5.6.1.4
SSE2 Compare Instructions
SSE2 compare instructions compare packed and scalar double-precision floating-point values and return the
results of the comparison either to the destination operand or to the EFLAGS register.
CMPPD
Compare packed double-precision floating-point values.
CMPSD
Compare scalar double-precision floating-point values.
COMISD
Perform ordered comparison of scalar double-precision floating-point values and set flags
in EFLAGS register.
UCOMISD
Perform unordered comparison of scalar double-precision floating-point values and set
flags in EFLAGS register.
5.6.1.5
SSE2 Shuffle and Unpack Instructions
SSE2 shuffle and unpack instructions shuffle or interleave double-precision floating-point values in packed doubleprecision floating-point operands.
SHUFPD
Shuffles values in packed double-precision floating-point operands.
UNPCKHPD
Unpacks and interleaves the high values from two packed double-precision floating-point
operands.
UNPCKLPD
Unpacks and interleaves the low values from two packed double-precision floating-point
operands.
5-18 Vol. 1
INSTRUCTION SET SUMMARY
5.6.1.6
SSE2 Conversion Instructions
SSE2 conversion instructions convert packed and individual doubleword integers into packed and scalar doubleprecision floating-point values and vice versa. They also convert between packed and scalar single-precision and
double-precision floating-point values.
CVTPD2PI
Convert packed double-precision floating-point values to packed doubleword integers.
CVTTPD2PI
Convert with truncation packed double-precision floating-point values to packed doubleword integers.
CVTPI2PD
Convert packed doubleword integers to packed double-precision floating-point values.
CVTPD2DQ
Convert packed double-precision floating-point values to packed doubleword integers.
CVTTPD2DQ
Convert with truncation packed double-precision floating-point values to packed doubleword integers.
CVTDQ2PD
Convert packed doubleword integers to packed double-precision floating-point values.
CVTPS2PD
Convert packed single-precision floating-point values to packed double-precision floatingpoint values.
CVTPD2PS
Convert packed double-precision floating-point values to packed single-precision floatingpoint values.
CVTSS2SD
Convert scalar single-precision floating-point values to scalar double-precision floatingpoint values.
CVTSD2SS
Convert scalar double-precision floating-point values to scalar single-precision floatingpoint values.
CVTSD2SI
Convert scalar double-precision floating-point values to a doubleword integer.
CVTTSD2SI
Convert with truncation scalar double-precision floating-point values to scalar doubleword
integers.
CVTSI2SD
Convert doubleword integer to scalar double-precision floating-point value.
5.6.2
SSE2 Packed Single-Precision Floating-Point Instructions
SSE2 packed single-precision floating-point instructions perform conversion operations on single-precision
floating-point and integer operands. These instructions represent enhancements to the SSE single-precision
floating-point instructions.
CVTDQ2PS
Convert packed doubleword integers to packed single-precision floating-point values.
CVTPS2DQ
Convert packed single-precision floating-point values to packed doubleword integers.
CVTTPS2DQ
Convert with truncation packed single-precision floating-point values to packed doubleword integers.
5.6.3
SSE2 128-Bit SIMD Integer Instructions
SSE2 SIMD integer instructions perform additional operations on packed words, doublewords, and quadwords
contained in XMM and MMX registers.
MOVDQA
Move aligned double quadword.
MOVDQU
Move unaligned double quadword.
MOVQ2DQ
Move quadword integer from MMX to XMM registers.
MOVDQ2Q
Move quadword integer from XMM to MMX registers.
PMULUDQ
Multiply packed unsigned doubleword integers.
PADDQ
Add packed quadword integers.
PSUBQ
Subtract packed quadword integers.
PSHUFLW
Shuffle packed low words.
PSHUFHW
Shuffle packed high words.
PSHUFD
Shuffle packed doublewords.
Vol. 1 5-19
INSTRUCTION SET SUMMARY
PSLLDQ
Shift double quadword left logical.
PSRLDQ
Shift double quadword right logical.
PUNPCKHQDQ
Unpack high quadwords.
PUNPCKLQDQ
Unpack low quadwords.
5.6.4
SSE2 Cacheability Control and Ordering Instructions
SSE2 cacheability control instructions provide additional operations for caching of non-temporal data when storing
data from XMM registers to memory. LFENCE and MFENCE provide additional control of instruction ordering on
store operations.
CLFLUSH
See Section 5.1.13.
LFENCE
Serializes load operations.
MFENCE
Serializes load and store operations.
PAUSE
Improves the performance of “spin-wait loops”.
MASKMOVDQU
Non-temporal store of selected bytes from an XMM register into memory.
MOVNTPD
Non-temporal store of two packed double-precision floating-point values from an XMM
register into memory.
MOVNTDQ
Non-temporal store of double quadword from an XMM register into memory.
MOVNTI
Non-temporal store of a doubleword from a general-purpose register into memory.
5.7
SSE3 INSTRUCTIONS
The SSE3 extensions offers 13 instructions that accelerate performance of Streaming SIMD Extensions technology,
Streaming SIMD Extensions 2 technology, and x87-FP math capabilities. These instructions can be grouped into the
following categories:
•
•
•
•
•
•
One x87FPU instruction used in integer conversion.
One SIMD integer instruction that addresses unaligned data loads.
Two SIMD floating-point packed ADD/SUB instructions.
Four SIMD floating-point horizontal ADD/SUB instructions.
Three SIMD floating-point LOAD/MOVE/DUPLICATE instructions.
Two thread synchronization instructions.
SSE3 instructions can only be executed on Intel 64 and IA-32 processors that support SSE3 extensions. Support
for these instructions can be detected with the CPUID instruction. See the description of the CPUID instruction in
Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
The sections that follow describe each subgroup.
5.7.1
FISTTP
5.7.2
LDDQU
5-20 Vol. 1
SSE3 x87-FP Integer Conversion Instruction
Behaves like the FISTP instruction but uses truncation, irrespective of the rounding mode
specified in the floating-point control word (FCW).
SSE3 Specialized 128-bit Unaligned Data Load Instruction
Special 128-bit unaligned load designed to avoid cache line splits.
INSTRUCTION SET SUMMARY
5.7.3
SSE3 SIMD Floating-Point Packed ADD/SUB Instructions
ADDSUBPS
Performs single-precision addition on the second and fourth pairs of 32-bit data elements
within the operands; single-precision subtraction on the first and third pairs.
ADDSUBPD
Performs double-precision addition on the second pair of quadwords, and double-precision
subtraction on the first pair.
5.7.4
SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions
HADDPS
Performs a single-precision addition on contiguous data elements. The first data element
of the result is obtained by adding the first and second elements of the first operand; the
second element by adding the third and fourth elements of the first operand; the third by
adding the first and second elements of the second operand; and the fourth by adding the
third and fourth elements of the second operand.
HSUBPS
Performs a single-precision subtraction on contiguous data elements. The first data
element of the result is obtained by subtracting the second element of the first operand
from the first element of the first operand; the second element by subtracting the fourth
element of the first operand from the third element of the first operand; the third by
subtracting the second element of the second operand from the first element of the second
operand; and the fourth by subtracting the fourth element of the second operand from the
third element of the second operand.
HADDPD
Performs a double-precision addition on contiguous data elements. The first data element
of the result is obtained by adding the first and second elements of the first operand; the
second element by adding the first and second elements of the second operand.
HSUBPD
Performs a double-precision subtraction on contiguous data elements. The first data
element of the result is obtained by subtracting the second element of the first operand
from the first element of the first operand; the second element by subtracting the second
element of the second operand from the first element of the second operand.
5.7.5
MOVSHDUP
SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions
Loads/moves 128 bits; duplicating the second and fourth 32-bit data elements.
MOVSLDUP
Loads/moves 128 bits; duplicating the first and third 32-bit data elements.
MOVDDUP
Loads/moves 64 bits (bits[63:0] if the source is a register) and returns the same 64 bits in
both the lower and upper halves of the 128-bit result register; duplicates the 64 bits from
the source.
5.7.6
SSE3 Agent Synchronization Instructions
MONITOR
Sets up an address range used to monitor write-back stores.
MWAIT
Enables a logical processor to enter into an optimized state while waiting for a write-back
store to the address range set up by the MONITOR instruction.
5.8
SUPPLEMENTAL STREAMING SIMD EXTENSIONS 3 (SSSE3) INSTRUCTIONS
SSSE3 provide 32 instructions (represented by 14 mnemonics) to accelerate computations on packed integers.
These include:
•
•
•
•
•
Twelve instructions that perform horizontal addition or subtraction operations.
Six instructions that evaluate absolute values.
Two instructions that perform multiply and add operations and speed up the evaluation of dot products.
Two instructions that accelerate packed-integer multiply operations and produce integer values with scaling.
Two instructions that perform a byte-wise, in-place shuffle according to the second shuffle control operand.
Vol. 1 5-21
INSTRUCTION SET SUMMARY
•
Six instructions that negate packed integers in the destination operand if the signs of the corresponding
element in the source operand is less than zero.
•
Two instructions that align data from the composite of two operands.
SSSE3 instructions can only be executed on Intel 64 and IA-32 processors that support SSSE3 extensions. Support
for these instructions can be detected with the CPUID instruction. See the description of the CPUID instruction in
Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
The sections that follow describe each subgroup.
5.8.1
Horizontal Addition/Subtraction
PHADDW
Adds two adjacent, signed 16-bit integers horizontally from the source and destination
operands and packs the signed 16-bit results to the destination operand.
PHADDSW
Adds two adjacent, signed 16-bit integers horizontally from the source and destination
operands and packs the signed, saturated 16-bit results to the destination operand.
PHADDD
Adds two adjacent, signed 32-bit integers horizontally from the source and destination
operands and packs the signed 32-bit results to the destination operand.
PHSUBW
Performs horizontal subtraction on each adjacent pair of 16-bit signed integers by
subtracting the most significant word from the least significant word of each pair in the
source and destination operands. The signed 16-bit results are packed and written to the
destination operand.
PHSUBSW
Performs horizontal subtraction on each adjacent pair of 16-bit signed integers by
subtracting the most significant word from the least significant word of each pair in the
source and destination operands. The signed, saturated 16-bit results are packed and
written to the destination operand.
PHSUBD
Performs horizontal subtraction on each adjacent pair of 32-bit signed integers by
subtracting the most significant doubleword from the least significant double word of each
pair in the source and destination operands. The signed 32-bit results are packed and
written to the destination operand.
5.8.2
Packed Absolute Values
PABSB
Computes the absolute value of each signed byte data element.
PABSW
Computes the absolute value of each signed 16-bit data element.
PABSD
Computes the absolute value of each signed 32-bit data element.
5.8.3
Multiply and Add Packed Signed and Unsigned Bytes
PMADDUBSW
5.8.4
PMULHRSW
5-22 Vol. 1
Multiplies each unsigned byte value with the corresponding signed byte value to produce
an intermediate, 16-bit signed integer. Each adjacent pair of 16-bit signed values are
added horizontally. The signed, saturated 16-bit results are packed to the destination
operand.
Packed Multiply High with Round and Scale
Multiplies vertically each signed 16-bit integer from the destination operand with the corresponding signed 16-bit integer of the source operand, producing intermediate, signed 32bit integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits.
Rounding is always performed by adding 1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by selecting the 16 bits immediately to the right of
the most significant bit of each 18-bit intermediate result and packed to the destination
operand.
INSTRUCTION SET SUMMARY
5.8.5
Packed Shuffle Bytes
PSHUFB
5.8.6
Permutes each byte in place, according to a shuffle control mask. The least significant
three or four bits of each shuffle control byte of the control mask form the shuffle index.
The shuffle mask is unaffected. If the most significant bit (bit 7) of a shuffle control byte is
set, the constant zero is written in the result byte.
Packed Sign
PSIGNB/W/D
5.8.7
PALIGNR
5.9
Negates each signed integer element of the destination operand if the sign of the corresponding data element in the source operand is less than zero.
Packed Align Right
Source operand is appended after the destination operand forming an intermediate value
of twice the width of an operand. The result is extracted from the intermediate value into
the destination operand by selecting the 128 bit or 64 bit value that are right-aligned to the
byte offset specified by the immediate value.
SSE4 INSTRUCTIONS
Intel® Streaming SIMD Extensions 4 (SSE4) introduces 54 new instructions. 47 of the SSE4 instructions are
referred to as SSE4.1 in this document, 7 new SSE4 instructions are referred to as SSE4.2.
SSE4.1 is targeted to improve the performance of media, imaging, and 3D workloads. SSE4.1 adds instructions
that improve compiler vectorization and significantly increase support for packed dword computation. The technology also provides a hint that can improve memory throughput when reading from uncacheable WC memory
type.
The 47 SSE4.1 instructions include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Two instructions perform packed dword multiplies.
Two instructions perform floating-point dot products with input/output selects.
One instruction performs a load with a streaming hint.
Six instructions simplify packed blending.
Eight instructions expand support for packed integer MIN/MAX.
Four instructions support floating-point round with selectable rounding mode and precision exception override.
Seven instructions improve data insertion and extractions from XMM registers
Twelve instructions improve packed integer format conversions (sign and zero extensions).
One instruction improves SAD (sum absolute difference) generation for small block sizes.
One instruction aids horizontal searching operations.
One instruction improves masked comparisons.
One instruction adds qword packed equality comparisons.
One instruction adds dword packing with unsigned saturation.
The SSE4.2 instructions operating on XMM registers include:
•
String and text processing that can take advantage of single-instruction multiple-data programming
techniques.
•
A SIMD integer instruction that enhances the capability of the 128-bit integer SIMD capability in SSE4.1.
Vol. 1 5-23
INSTRUCTION SET SUMMARY
5.10
SSE4.1 INSTRUCTIONS
SSE4.1 instructions can use an XMM register as a source or destination. Programming SSE4.1 is similar to
programming 128-bit Integer SIMD and floating-point SIMD instructions in SSE/SSE2/SSE3/SSSE3. SSE4.1 does
not provide any 64-bit integer SIMD instructions operating on MMX registers. The sections that follow describe each
subgroup.
5.10.1
Dword Multiply Instructions
PMULLD
Returns four lower 32-bits of the 64-bit results of signed 32-bit integer multiplies.
PMULDQ
Returns two 64-bit signed result of signed 32-bit integer multiplies.
5.10.2
Floating-Point Dot Product Instructions
DPPD
Perform double-precision dot product for up to 2 elements and broadcast.
DPPS
Perform single-precision dot products for up to 4 elements and broadcast.
5.10.3
MOVNTDQA
5.10.4
Streaming Load Hint Instruction
Provides a non-temporal hint that can cause adjacent 16-byte items within an aligned 64byte region (a streaming line) to be fetched and held in a small set of temporary buffers
(“streaming load buffers”). Subsequent streaming loads to other aligned 16-byte items in
the same streaming line may be supplied from the streaming load buffer and can improve
throughput.
Packed Blending Instructions
BLENDPD
Conditionally copies specified double-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an immediate byte
control.
BLENDPS
Conditionally copies specified single-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an immediate byte
control.
BLENDVPD
Conditionally copies specified double-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an implied mask.
BLENDVPS
Conditionally copies specified single-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an implied mask.
PBLENDVB
Conditionally copies specified byte elements in the source operand to the corresponding
elements in the destination, using an implied mask.
PBLENDW
Conditionally copies specified word elements in the source operand to the corresponding
elements in the destination, using an immediate byte control.
5.10.5
PMINUW
Packed Integer MIN/MAX Instructions
Compare packed unsigned word integers.
PMINUD
Compare packed unsigned dword integers.
PMINSB
Compare packed signed byte integers.
PMINSD
Compare packed signed dword integers.
PMAXUW
Compare packed unsigned word integers.
PMAXUD
Compare packed unsigned dword integers.
PMAXSB
Compare packed signed byte integers.
5-24 Vol. 1
INSTRUCTION SET SUMMARY
PMAXSD
Compare packed signed dword integers.
5.10.6
Floating-Point Round Instructions with Selectable Rounding Mode
ROUNDPS
Round packed single precision floating-point values into integer values and return rounded
floating-point values.
ROUNDPD
Round packed double precision floating-point values into integer values and return
rounded floating-point values.
ROUNDSS
Round the low packed single precision floating-point value into an integer value and return
a rounded floating-point value.
ROUNDSD
Round the low packed double precision floating-point value into an integer value and
return a rounded floating-point value.
5.10.7
Insertion and Extractions from XMM Registers
EXTRACTPS
Extracts a single-precision floating-point value from a specified offset in an XMM register
and stores the result to memory or a general-purpose register.
INSERTPS
Inserts a single-precision floating-point value from either a 32-bit memory location or
selected from a specified offset in an XMM register to a specified offset in the destination
XMM register. In addition, INSERTPS allows zeroing out selected data elements in the
destination, using a mask.
PINSRB
Insert a byte value from a register or memory into an XMM register.
PINSRD
Insert a dword value from 32-bit register or memory into an XMM register.
PINSRQ
Insert a qword value from 64-bit register or memory into an XMM register.
PEXTRB
Extract a byte from an XMM register and insert the value into a general-purpose register or
memory.
PEXTRW
Extract a word from an XMM register and insert the value into a general-purpose register
or memory.
PEXTRD
Extract a dword from an XMM register and insert the value into a general-purpose register
or memory.
PEXTRQ
Extract a qword from an XMM register and insert the value into a general-purpose register
or memory.
5.10.8
Packed Integer Format Conversions
PMOVSXBW
Sign extend the lower 8-bit integer of each packed word element into packed signed word
integers.
PMOVZXBW
Zero extend the lower 8-bit integer of each packed word element into packed signed word
integers.
PMOVSXBD
Sign extend the lower 8-bit integer of each packed dword element into packed signed
dword integers.
PMOVZXBD
Zero extend the lower 8-bit integer of each packed dword element into packed signed
dword integers.
PMOVSXWD
Sign extend the lower 16-bit integer of each packed dword element into packed signed
dword integers.
PMOVZXWD
Zero extend the lower 16-bit integer of each packed dword element into packed signed
dword integers..
PMOVSXBQ
Sign extend the lower 8-bit integer of each packed qword element into packed signed
qword integers.
PMOVZXBQ
Zero extend the lower 8-bit integer of each packed qword element into packed signed
qword integers.
Vol. 1 5-25
INSTRUCTION SET SUMMARY
PMOVSXWQ
Sign extend the lower 16-bit integer of each packed qword element into packed signed
qword integers.
PMOVZXWQ
Zero extend the lower 16-bit integer of each packed qword element into packed signed
qword integers.
PMOVSXDQ
Sign extend the lower 32-bit integer of each packed qword element into packed signed
qword integers.
PMOVZXDQ
Zero extend the lower 32-bit integer of each packed qword element into packed signed
qword integers.
5.10.9
Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks
MPSADBW
Performs eight 4-byte wide Sum of Absolute Differences operations to produce eight word
integers.
5.10.10 Horizontal Search
PHMINPOSUW
Finds the value and location of the minimum unsigned word from one of 8 horizontally
packed unsigned words. The resulting value and location (offset within the source) are
packed into the low dword of the destination XMM register.
5.10.11 Packed Test
PTEST
Performs a logical AND between the destination with this mask and sets the ZF flag if the
result is zero. The CF flag (zero for TEST) is set if the inverted mask AND’d with the destination is all zeroes.
5.10.12 Packed Qword Equality Comparisons
PCMPEQQ
128-bit packed qword equality test.
5.10.13 Dword Packing With Unsigned Saturation
PACKUSDW
5.11
PACKUSDW packs dword to word with unsigned saturation.
SSE4.2 INSTRUCTION SET
Five of the SSE4.2 instructions operate on XMM register as a source or destination. These include four text/string
processing instructions and one packed quadword compare SIMD instruction. Programming these five SSE4.2
instructions is similar to programming 128-bit Integer SIMD in SSE2/SSSE3. SSE4.2 does not provide any 64-bit
integer SIMD instructions.
CRC32 operates on general-purpose registers and is summarized in Section 5.1.6. The sections that follow summarize each subgroup.
5.11.1
String and Text Processing Instructions
PCMPESTRI
Packed compare explicit-length strings, return index in ECX/RCX.
PCMPESTRM
Packed compare explicit-length strings, return mask in XMM0.
PCMPISTRI
Packed compare implicit-length strings, return index in ECX/RCX.
PCMPISTRM
Packed compare implicit-length strings, return mask in XMM0.
5-26 Vol. 1
INSTRUCTION SET SUMMARY
5.11.2
Packed Comparison SIMD integer Instruction
PCMPGTQ
5.12
Performs logical compare of greater-than on packed integer quadwords.
AESNI AND PCLMULQDQ
Six AESNI instructions operate on XMM registers to provide accelerated primitives for block encryption/decryption
using Advanced Encryption Standard (FIPS-197). The PCLMULQDQ instruction performs carry-less multiplication
for two binary numbers up to 64-bit wide.
AESDEC
Perform an AES decryption round using an 128-bit state and a round key.
AESDECLAST
Perform the last AES decryption round using an 128-bit state and a round key.
AESENC
Perform an AES encryption round using an 128-bit state and a round key.
AESENCLAST
Perform the last AES encryption round using an 128-bit state and a round key.
AESIMC
Perform an inverse mix column transformation primitive.
AESKEYGENASSIST
Assist the creation of round keys with a key expansion schedule.
PCLMULQDQ
Perform carryless multiplication of two 64-bit numbers.
5.13
INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)
Intel® Advanced Vector Extensions (AVX) promotes legacy 128-bit SIMD instruction sets that operate on XMM
register set to use a “vector extension“ (VEX) prefix and operates on 256-bit vector registers (YMM). Almost all
prior generations of 128-bit SIMD instructions that operates on XMM (but not on MMX registers) are promoted to
support three-operand syntax with VEX-128 encoding.
VEX-prefix encoded AVX instructions support 256-bit and 128-bit floating-point operations by extending the legacy
128-bit SIMD floating-point instructions to support three-operand syntax.
Additional functional enhancements are also provided with VEX-encoded AVX instructions.
The list of AVX instructions are listed in the following tables:
•
Table 14-2 lists 256-bit and 128-bit floating-point arithmetic instructions promoted from legacy 128-bit SIMD
instruction sets.
•
Table 14-3 lists 256-bit and 128-bit data movement and processing instructions promoted from legacy 128-bit
SIMD instruction sets.
•
Table 14-4 lists functional enhancements of 256-bit AVX instructions not available from legacy 128-bit SIMD
instruction sets.
•
Table 14-5 lists 128-bit integer and floating-point instructions promoted from legacy 128-bit SIMD instruction
sets.
•
Table 14-6 lists functional enhancements of 128-bit AVX instructions not available from legacy 128-bit SIMD
instruction sets.
•
Table 14-7 lists 128-bit data movement and processing instructions promoted from legacy instruction sets.
5.14
16-BIT FLOATING-POINT CONVERSION
Conversion between single-precision floating-point (32-bit) and half-precision FP (16-bit) data are provided by
VCVTPS2PH, VCVTPH2PS:
VCVTPH2PS
Convert eight/four data element containing 16-bit floating-point data into eight/four
single-precision floating-point data.
VCVTPS2PH
Convert eight/four data element containing single-precision floating-point data into
eight/four 16-bit floating-point data.
Vol. 1 5-27
INSTRUCTION SET SUMMARY
5.15
FUSED-MULTIPLY-ADD (FMA)
FMA extensions enhances Intel AVX with high-throughput, arithmetic capabilities covering fused multiply-add,
fused multiply-subtract, fused multiply add/subtract interleave, signed-reversed multiply on fused multiply-add
and multiply-subtract. FMA extensions provide 36 256-bit floating-point instructions to perform computation on
256-bit vectors and additional 128-bit and scalar FMA instructions.
•
Table 14-15 lists FMA instruction sets.
5.16
INTEL® ADVANCED VECTOR EXTENSIONS 2 (INTEL® AVX2)
Intel® AVX2 extends Intel AVX by promoting most of the 128-bit SIMD integer instructions with 256-bit numeric
processing capabilities. Intel AVX2 instructions follow the same programming model as AVX instructions.
In addition, AVX2 provide enhanced functionalities for broadcast/permute operations on data elements, vector
shift instructions with variable-shift count per data element, and instructions to fetch non-contiguous data
elements from memory.
•
•
Table 14-18 lists promoted vector integer instructions in AVX2.
Table 14-19 lists new instructions in AVX2 that complements AVX.
5.17
INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS (INTEL® TSX)
XABORT
Abort an RTM transaction execution.
XACQUIRE
Prefix hint to the beginning of an HLE transaction region.
XRELEASE
Prefix hint to the end of an HLE transaction region.
XBEGIN
Transaction begin of an RTM transaction region.
XEND
Transaction end of an RTM transaction region.
XTEST
Test if executing in a transactional region.
5.18
INTEL® SHA EXTENSIONS
Intel® SHA extensions provide a set of instructions that target the acceleration of the Secure Hash Algorithm
(SHA), specifically the SHA-1 and SHA-256 variants.
SHA1MSG1
Perform an intermediate calculation for the next four SHA1 message dwords from the
previous message dwords.
SHA1MSG2
Perform the final calculation for the next four SHA1 message dwords from the intermediate
message dwords.
SHA1NEXTE
Calculate SHA1 state E after four rounds.
SHA1RNDS4
Perform four rounds of SHA1 operations.
SHA256MSG1
Perform an intermediate calculation for the next four SHA256 message dwords.
SHA256MSG2
Perform the final calculation for the next four SHA256 message dwords.
SHA256RNDS2
Perform two rounds of SHA256 operations.
5.19
INTEL® ADVANCED VECTOR EXTENSIONS 512 (INTEL® AVX-512)
The Intel® AVX-512 family comprises a collection of 512-bit SIMD instruction sets to accelerate a diverse range of
applications. Intel AVX-512 instructions provide a wide range of functionality that support programming in 512-bit,
256 and 128-bit vector register, plus support for opmask registers and instructions operating on opmask registers.
The collection of 512-bit SIMD instruction sets in Intel AVX-512 include new functionality not available in Intel AVX
and Intel AVX2, and promoted instructions similar to equivalent ones in Intel AVX / Intel AVX2 but with enhance5-28 Vol. 1
INSTRUCTION SET SUMMARY
ment provided by opmask registers not available to VEX-encoded Intel AVX / Intel AVX2. Some instruction
mnemonics in AVX / AVX2 that are promoted into AVX-512 can be replaced by new instruction mnemonics that are
available only with EVEX encoding, e.g., VBROADCASTF128 into VBROADCASTF32X4. Details of EVEX instruction
encoding are discussed in Section 2.6, “Intel® AVX-512 Encoding” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
512-bit instruction mnemonics in AVX-512F that are not AVX/AVX2 promotions include:
VALIGND/Q
Perform dword/qword alignment of two concatenated source vectors.
VBLENDMPD/PS
Replace the VBLENDVPD/PS instructions (using opmask as select control).
VCOMPRESSPD/PS
Compress packed DP or SP elements of a vector.
VCVT(T)PD2UDQ
Convert packed DP FP elements of a vector to packed unsigned 32-bit integers.
VCVT(T)PS2UDQ
Convert packed SP FP elements of a vector to packed unsigned 32-bit integers.
VCVTQQ2PD/PS
Convert packed signed 64-bit integers to packed DP/SP FP elements.
VCVT(T)SD2USI
Convert the low DP FP element of a vector to an unsigned integer.
VCVT(T)SS2USI
Convert the low SP FP element of a vector to an unsigned integer.
VCVTUDQ2PD/PS
Convert packed unsigned 32-bit integers to packed DP/SP FP elements.
VCVTUSI2USD/S
Convert an unsigned integer to the low DP/SP FP element and merge to a vector.
VEXPANDPD/PS
Expand packed DP or SP elements of a vector.
VEXTRACTF32X4/64X4 Extract a vector from a full-length vector with 32/64-bit granular update.
VEXTRACTI32X4/64X4 Extract a vector from a full-length vector with 32/64-bit granular update.
VFIXUPIMMPD/PS
Perform fix-up to special values in DP/SP FP vectors.
VFIXUPIMMSD/SS
Perform fix-up to special values of the low DP/SP FP element.
VGETEXPPD/PS
Convert the exponent of DP/SP FP elements of a vector into FP values.
VGETEXPSD/SS
Convert the exponent of the low DP/SP FP element in a vector into FP value.
VGETMANTPD/PS
Convert the mantissa of DP/SP FP elements of a vector into FP values.
VGETMANTSD/SS
Convert the mantissa of the low DP/SP FP element of a vector into FP value.
VINSERTF32X4/64X4
Insert a 128/256-bit vector into a full-length vector with 32/64-bit granular update.
VMOVDQA32/64
VMOVDQA with 32/64-bit granular conditional update.
VMOVDQU32/64
VMOVDQU with 32/64-bit granular conditional update.
VPBLENDMD/Q
Blend dword/qword elements using opmask as select control.
VPBROADCASTD/Q
Broadcast from general-purpose register to vector register.
VPCMPD/UD
Compare packed signed/unsigned dwords using specified primitive.
VPCMPQ/UQ
Compare packed signed/unsigned quadwords using specified primitive.
VPCOMPRESSQ/D
Compress packed 64/32-bit elements of a vector.
VPERMI2D/Q
Full permute of two tables of dword/qword elements overwriting the index vector.
VPERMI2PD/PS
Full permute of two tables of DP/SP elements overwriting the index vector.
VPERMT2D/Q
Full permute of two tables of dword/qword elements overwriting one source table.
VPERMT2PD/PS
Full permute of two tables of DP/SP elements overwriting one source table.
VPEXPANDD/Q
Expand packed dword/qword elements of a vector.
VPMAXSQ
Compute maximum of packed signed 64-bit integer elements.
VPMAXUD/UQ
Compute maximum of packed unsigned 32/64-bit integer elements.
VPMINSQ
Compute minimum of packed signed 64-bit integer elements.
VPMINUD/UQ
Compute minimum of packed unsigned 32/64-bit integer elements.
VPMOV(S|US)QB
Down convert qword elements in a vector to byte elements using truncation (saturation |
unsigned saturation).
VPMOV(S|US)QW
Down convert qword elements in a vector to word elements using truncation (saturation |
unsigned saturation).
VPMOV(S|US)QD
Down convert qword elements in a vector to dword elements using truncation (saturation
| unsigned saturation).
Vol. 1 5-29
INSTRUCTION SET SUMMARY
VPMOV(S|US)DB
Down convert dword elements in a vector to byte elements using truncation (saturation |
unsigned saturation).
VPMOV(S|US)DW
Down convert dword elements in a vector to word elements using truncation (saturation |
unsigned saturation).
VPROLD/Q
Rotate dword/qword element left by a constant shift count with conditional update.
VPROLVD/Q
Rotate dword/qword element left by shift counts specified in a vector with conditional
update.
VPRORD/Q
Rotate dword/qword element right by a constant shift count with conditional update.
VPRORRD/Q
Rotate dword/qword element right by shift counts specified in a vector with conditional
update.
VPSCATTERDD/DQ
Scatter dword/qword elements in a vector to memory using dword indices.
VPSCATTERQD/QQ
Scatter dword/qword elements in a vector to memory using qword indices.
VPSRAQ
Shift qwords right by a constant shift count and shifting in sign bits.
VPSRAVQ
Shift qwords right by shift counts in a vector and shifting in sign bits.
VPTESTNMD/Q
Perform bitwise NAND of dword/qword elements of two vectors and write results to
opmask.
VPTERLOGD/Q
Perform bitwise ternary logic operation of three vectors with 32/64 bit granular conditional
update.
VPTESTMD/Q
Perform bitwise AND of dword/qword elements of two vectors and write results to opmask.
VRCP14PD/PS
Compute approximate reciprocals of packed DP/SP FP elements of a vector.
VRCP14SD/SS
Compute the approximate reciprocal of the low DP/SP FP element of a vector.
VRNDSCALEPD/PS
Round packed DP/SP FP elements of a vector to specified number of fraction bits.
VRNDSCALESD/SS
Round the low DP/SP FP element of a vector to specified number of fraction bits.
VRSQRT14PD/PS
Compute approximate reciprocals of square roots of packed DP/SP FP elements of a vector.
VRSQRT14SD/SS
Compute the approximate reciprocal of square root of the low DP/SP FP element of a
vector.
VSCALEPD/PS
Multiply packed DP/SP FP elements of a vector by powers of two with exponents specified
in a second vector.
VSCALESD/SS
Multiply the low DP/SP FP element of a vector by powers of two with exponent specified in
the corresponding element of a second vector.
VSCATTERDD/DQ
Scatter SP/DP FP elements in a vector to memory using dword indices.
VSCATTERQD/QQ
Scatter SP/DP FP elements in a vector to memory using qword indices.
VSHUFF32X4/64X2
Shuffle 128-bit lanes of a vector with 32/64 bit granular conditional update.
VSHUFI32X4/64X2
Shuffle 128-bit lanes of a vector with 32/64 bit granular conditional update.
512-bit instruction mnemonics in AVX-512DQ that are not AVX/AVX2 promotions include:
VCVT(T)PD2QQ
Convert packed DP FP elements of a vector to packed signed 64-bit integers.
VCVT(T)PD2UQQ
Convert packed DP FP elements of a vector to packed unsigned 64-bit integers.
VCVT(T)PS2QQ
Convert packed SP FP elements of a vector to packed signed 64-bit integers.
VCVT(T)PS2UQQ
Convert packed SP FP elements of a vector to packed unsigned 64-bit integers.
VCVTUQQ2PD/PS
Convert packed unsigned 64-bit integers to packed DP/SP FP elements.
VEXTRACTF64X2
Extract a vector from a full-length vector with 64-bit granular update.
VEXTRACTI64X2
Extract a vector from a full-length vector with 64-bit granular update.
VFPCLASSPD/PS
Test packed DP/SP FP elements in a vector by numeric/special-value category.
VFPCLASSSD/SS
Test the low DP/SP FP element by numeric/special-value category.
VINSERTF64X2
Insert a 128-bit vector into a full-length vector with 64-bit granular update.
VINSERTI64X2
Insert a 128-bit vector into a full-length vector with 64-bit granular update.
VPMOVM2D/Q
Convert opmask register to vector register in 32/64-bit granularity.
5-30 Vol. 1
INSTRUCTION SET SUMMARY
VPMOVB2D/Q2M
Convert a vector register in 32/64-bit granularity to an opmask register.
VPMULLQ
Multiply packed signed 64-bit integer elements of two vectors and store low 64-bit signed
result.
VRANGEPD/PS
Perform RANGE operation on each pair of DP/SP FP elements of two vectors using specified
range primitive in imm8.
VRANGESD/SS
Perform RANGE operation on the pair of low DP/SP FP element of two vectors using specified range primitive in imm8.
VREDUCEPD/PS
Perform Reduction operation on packed DP/SP FP elements of a vector using specified
reduction primitive in imm8.
VREDUCESD/SS
Perform Reduction operation on the low DP/SP FP element of a vector using specified
reduction primitive in imm8.
512-bit instruction mnemonics in AVX-512BW that are not AVX/AVX2 promotions include:
VDBPSADBW
Double block packed Sum-Absolute-Differences on unsigned bytes.
VMOVDQU8/16
VMOVDQU with 8/16-bit granular conditional update.
VPBLENDMB
Replaces the VPBLENDVB instruction (using opmask as select control).
VPBLENDMW
Blend word elements using opmask as select control.
VPBROADCASTB/W
Broadcast from general-purpose register to vector register.
VPCMPB/UB
Compare packed signed/unsigned bytes using specified primitive.
VPCMPW/UW
Compare packed signed/unsigned words using specified primitive.
VPERMW
Permute packed word elements.
VPERMI2B/W
Full permute from two tables of byte/word elements overwriting the index vector.
VPMOVM2B/W
Convert opmask register to vector register in 8/16-bit granularity.
VPMOVB2M/W2M
Convert a vector register in 8/16-bit granularity to an opmask register.
VPMOV(S|US)WB
Down convert word elements in a vector to byte elements using truncation (saturation |
unsigned saturation).
VPSLLVW
Shift word elements in a vector left by shift counts in a vector.
VPSRAVW
Shift words right by shift counts in a vector and shifting in sign bits.
VPSRLVW
Shift word elements in a vector right by shift counts in a vector.
VPTESTNMB/W
Perform bitwise NAND of byte/word elements of two vectors and write results to opmask.
VPTESTMB/W
Perform bitwise AND of byte/word elements of two vectors and write results to opmask.
512-bit instruction mnemonics in AVX-512CD that are not AVX/AVX2 promotions include:
VPBROADCASTM
Broadcast from opmask register to vector register.
VPCONFLICTD/Q
Detect conflicts within a vector of packed 32/64-bit integers.
VPLZCNTD/Q
Count the number of leading zero bits of packed dword/qword elements.
Opmask instructions include:
KADDB/W/D/Q
Add two 8/16/32/64-bit opmasks.
KANDB/W/D/Q
Logical AND two 8/16/32/64-bit opmasks.
KANDNB/W/D/Q
Logical AND NOT two 8/16/32/64-bit opmasks.
KMOVB/W/D/Q
Move from or move to opmask register of 8/16/32/64-bit data.
KNOTB/W/D/Q
Bitwise NOT of two 8/16/32/64-bit opmasks.
KORB/W/D/Q
Logical OR two 8/16/32/64-bit opmasks.
KORTESTB/W/D/Q
Update EFLAGS according to the result of bitwise OR of two 8/16/32/64-bit opmasks.
KSHIFTLB/W/D/Q
Shift left 8/16/32/64-bit opmask by specified count.
KSHIFTRB/W/D/Q
Shift right 8/16/32/64-bit opmask by specified count.
Vol. 1 5-31
INSTRUCTION SET SUMMARY
KTESTB/W/D/Q
Update EFLAGS according to the result of bitwise TEST of two 8/16/32/64-bit opmasks.
KUNPCKBW/WD/DQ
Unpack and interleave two 8/16/32-bit opmasks into 16/32/64-bit mask.
KXNORB/W/D/Q
Bitwise logical XNOR of two 8/16/32/64-bit opmasks.
KXORB/W/D/Q
Logical XOR of two 8/16/32/64-bit opmasks.
512-bit instruction mnemonics in AVX-512ER include:
VEXP2PD/PS
Compute approximate base-2 exponential of packed DP/SP FP elements of a vector.
VEXP2SD/SS
Compute approximate base-2 exponential of the low DP/SP FP element of a vector.
VRCP28PD/PS
Compute approximate reciprocals to 28 bits of packed DP/SP FP elements of a vector.
VRCP28SD/SS
Compute the approximate reciprocal to 28 bits of the low DP/SP FP element of a vector.
VRSQRT28PD/PS
Compute approximate reciprocals of square roots to 28 bits of packed DP/SP FP elements
of a vector.
VRSQRT28SD/SS
Compute the approximate reciprocal of square root to 28 bits of the low DP/SP FP element
of a vector.
512-bit instruction mnemonics in AVX-512PF include:
VGATHERPF0DPD/PS
Sparse prefetch of packed DP/SP FP vector with T0 hint using dword indices.
VGATHERPF0QPD/PS
Sparse prefetch of packed DP/SP FP vector with T0 hint using qword indices.
VGATHERPF1DPD/PS
Sparse prefetch of packed DP/SP FP vector with T1 hint using dword indices.
VGATHERPF1QPD/PS
Sparse prefetch of packed DP/SP FP vector with T1 hint using qword indices.
VSCATTERPF0DPD/PS
Sparse prefetch of packed DP/SP FP vector with T0 hint to write using dword indices.
VSCATTERPF0QPD/PS
Sparse prefetch of packed DP/SP FP vector with T0 hint to write using qword indices.
VSCATTERPF1DPD/PS
Sparse prefetch of packed DP/SP FP vector with T1 hint to write using dword indices.
VSCATTERPF1QPD/PS
Sparse prefetch of packed DP/SP FP vector with T1 hint to write using qword indices.
5.20
SYSTEM INSTRUCTIONS
The following system instructions are used to control those functions of the processor that are provided to support
for operating systems and executives.
CLAC
Clear AC Flag in EFLAGS register.
STAC
Set AC Flag in EFLAGS register.
LGDT
Load global descriptor table (GDT) register.
SGDT
Store global descriptor table (GDT) register.
LLDT
Load local descriptor table (LDT) register.
SLDT
Store local descriptor table (LDT) register.
LTR
Load task register.
STR
Store task register.
LIDT
Load interrupt descriptor table (IDT) register.
SIDT
Store interrupt descriptor table (IDT) register.
MOV
Load and store control registers.
LMSW
Load machine status word.
SMSW
Store machine status word.
CLTS
Clear the task-switched flag.
ARPL
Adjust requested privilege level.
LAR
Load access rights.
LSL
Load segment limit.
5-32 Vol. 1
INSTRUCTION SET SUMMARY
VERR
Verify segment for reading
VERW
Verify segment for writing.
MOV
Load and store debug registers.
INVD
Invalidate cache, no writeback.
WBINVD
Invalidate cache, with writeback.
INVLPG
Invalidate TLB Entry.
INVPCID
Invalidate Process-Context Identifier.
LOCK (prefix)
Lock Bus.
HLT
Halt processor.
RSM
Return from system management mode (SMM).
RDMSR
Read model-specific register.
WRMSR
Write model-specific register.
RDPMC
Read performance monitoring counters.
RDTSC
Read time stamp counter.
RDTSCP
Read time stamp counter and processor ID.
SYSENTER
Fast System Call, transfers to a flat protected mode kernel at CPL = 0.
SYSEXIT
Fast System Call, transfers to a flat protected mode kernel at CPL = 3.
XSAVE
Save processor extended states to memory.
XSAVEC
Save processor extended states with compaction to memory.
XSAVEOPT
Save processor extended states to memory, optimized.
XSAVES
Save processor supervisor-mode extended states to memory.
XRSTOR
Restore processor extended states from memory.
XRSTORS
Restore processor supervisor-mode extended states from memory.
XGETBV
Reads the state of an extended control register.
XSETBV
Writes the state of an extended control register.
RDFSBASE
Reads from FS base address at any privilege level.
RDGSBASE
Reads from GS base address at any privilege level.
WRFSBASE
Writes to FS base address at any privilege level.
WRGSBASE
Writes to GS base address at any privilege level.
5.21
64-BIT MODE INSTRUCTIONS
The following instructions are introduced in 64-bit mode. This mode is a sub-mode of IA-32e mode.
CDQE
Convert doubleword to quadword.
CMPSQ
Compare string operands.
CMPXCHG16B
Compare RDX:RAX with m128.
LODSQ
Load qword at address (R)SI into RAX.
MOVSQ
Move qword from address (R)SI to (R)DI.
MOVZX (64-bits)
Move bytes/words to doublewords/quadwords, zero-extension.
STOSQ
Store RAX at address RDI.
SWAPGS
Exchanges current GS base register value with value in MSR address C0000102H.
SYSCALL
Fast call to privilege level 0 system procedures.
SYSRET
Return from fast systemcall.
Vol. 1 5-33
INSTRUCTION SET SUMMARY
5.22
VIRTUAL-MACHINE EXTENSIONS
The behavior of the VMCS-maintenance instructions is summarized below:
VMPTRLD
Takes a single 64-bit source operand in memory. It makes the referenced VMCS active and
current.
VMPTRST
Takes a single 64-bit destination operand that is in memory. Current-VMCS pointer is
stored into the destination operand.
VMCLEAR
Takes a single 64-bit operand in memory. The instruction sets the launch state of the VMCS
referenced by the operand to “clear”, renders that VMCS inactive, and ensures that data
for the VMCS have been written to the VMCS-data area in the referenced VMCS region.
VMREAD
Reads a component from the VMCS (the encoding of that field is given in a register
operand) and stores it into a destination operand.
VMWRITE
Writes a component to the VMCS (the encoding of that field is given in a register operand)
from a source operand.
The behavior of the VMX management instructions is summarized below:
VMLAUNCH
Launches a virtual machine managed by the VMCS. A VM entry occurs, transferring control
to the VM.
VMRESUME
Resumes a virtual machine managed by the VMCS. A VM entry occurs, transferring control
to the VM.
VMXOFF
Causes the processor to leave VMX operation.
VMXON
Takes a single 64-bit source operand in memory. It causes a logical processor to enter VMX
root operation and to use the memory referenced by the operand to support VMX operation.
The behavior of the VMX-specific TLB-management instructions is summarized below:
INVEPT
Invalidate cached Extended Page Table (EPT) mappings in the processor to synchronize
address translation in virtual machines with memory-resident EPT pages.
INVVPID
Invalidate cached mappings of address translation based on the Virtual Processor ID
(VPID).
None of the instructions above can be executed in compatibility mode; they generate invalid-opcode exceptions if
executed in compatibility mode.
The behavior of the guest-available instructions is summarized below:
VMCALL
Allows a guest in VMX non-root operation to call the VMM for service. A VM exit occurs,
transferring control to the VMM.
VMFUNC
This instruction allows software in VMX non-root operation to invoke a VM function, which
is processor functionality enabled and configured by software in VMX root operation. No
VM exit occurs.
5.23
SAFER MODE EXTENSIONS
The behavior of the GETSEC instruction leaves of the Safer Mode Extensions (SMX) are summarized below:
GETSEC[CAPABILITIES]Returns the available leaf functions of the GETSEC instruction.
GETSEC[ENTERACCS]
Loads an authenticated code chipset module and enters authenticated code execution
mode.
GETSEC[EXITAC]
Exits authenticated code execution mode.
GETSEC[SENTER]
Establishes a Measured Launched Environment (MLE) which has its dynamic root of trust
anchored to a chipset supporting Intel Trusted Execution Technology.
GETSEC[SEXIT]
Exits the MLE.
GETSEC[PARAMETERS] Returns SMX related parameter information.
GETSEC[SMCRTL]
SMX mode control.
GETSEC[WAKEUP]
Wakes up sleeping logical processors inside an MLE.
5-34 Vol. 1
INSTRUCTION SET SUMMARY
5.24
INTEL® MEMORY PROTECTION EXTENSIONS
Intel Memory Protection Extensions (MPX) provides a set of instructions to enable software to add robust bounds
checking capability to memory references. Details of Intel MPX are described in Chapter 17, “Intel® MPX”.
BNDMK
Create a LowerBound and a UpperBound in a register.
BNDCL
Check the address of a memory reference against a LowerBound.
BNDCU
Check the address of a memory reference against an UpperBound in 1’s compliment form.
BNDCN
Check the address of a memory reference against an UpperBound not in 1’s compliment
form.
BNDMOV
Copy or load from memory of the LowerBound and UpperBound to a register.
BNDMOV
Store to memory of the LowerBound and UpperBound from a register.
BNDLDX
Load bounds using address translation.
BNDSTX
Store bounds using address translation.
5.25
INTEL® SECURITY GUARD EXTENSIONS
Intel Security Guard Extensions (SGX) provide two sets of instruction leaf functions to enable application
software to instantiate a protected container, referred to as an enclave. The enclave instructions are organized as
leaf functions under two instruction mnemonics: ENCLS (ring 0) and ENCLU (ring 3). Details of Intel SGX are
described in CHAPTER 37 through CHAPTER 43 of Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3D.
The first implementation of Intel SGX is also referred to as SGX1, it is introduced with the 6th Generation Intel
Core Processors. The leaf functions supported in SGX1 is shown in Table 5-3.
Table 5-3. Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1
Supervisor Instruction
Description
User Instruction
Description
ENCLS[EADD]
Add a page
ENCLU[EENTER]
Enter an Enclave
ENCLS[EBLOCK]
Block an EPC page
ENCLU[EEXIT]
Exit an Enclave
ENCLS[ECREATE]
Create an enclave
ENCLU[EGETKEY]
Create a cryptographic key
ENCLS[EDBGRD]
Read data by debugger
ENCLU[EREPORT]
Create a cryptographic report
ENCLS[EDBGWR]
Write data by debugger
ENCLU[ERESUME]
Re-enter an Enclave
ENCLS[EEXTEND]
Extend EPC page measurement
ENCLS[EINIT]
Initialize an enclave
ENCLS[ELDB]
Load an EPC page as blocked
ENCLS[ELDU]
Load an EPC page as unblocked
ENCLS[EPA]
Add version array
ENCLS[EREMOVE]
Remove a page from EPC
ENCLS[ETRACK]
Activate EBLOCK checks
ENCLS[EWB]
Write back/invalidate an EPC page
Vol. 1 5-35
INSTRUCTION SET SUMMARY
5-36 Vol. 1
CHAPTER 6
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
This chapter describes the facilities in the Intel 64 and IA-32 architectures for executing calls to procedures or
subroutines. It also describes how interrupts and exceptions are handled from the perspective of an application
programmer.
6.1
PROCEDURE CALL TYPES
The processor supports procedure calls in the following two different ways:
•
•
CALL and RET instructions.
ENTER and LEAVE instructions, in conjunction with the CALL and RET
instructions.
Both of these procedure call mechanisms use the procedure stack, commonly referred to simply as “the stack,” to
save the state of the calling procedure, pass parameters to the called procedure, and store local variables for the
currently executing procedure.
The processor’s facilities for handling interrupts and exceptions are similar to those used by the CALL and RET
instructions.
6.2
STACKS
The stack (see Figure 6-1) is a contiguous array of memory locations. It is contained in a segment and identified by
the segment selector in the SS register. When using the flat memory model, the stack can be located anywhere in
the linear address space for the program. A stack can be up to 4 GBytes long, the maximum size of a segment.
Items are placed on the stack using the PUSH instruction and removed from the stack using the POP instruction.
When an item is pushed onto the stack, the processor decrements the ESP register, then writes the item at the new
top of stack. When an item is popped off the stack, the processor reads the item from the top of stack, then increments the ESP register. In this manner, the stack grows down in memory (towards lesser addresses) when items
are pushed on the stack and shrinks up (towards greater addresses) when the items are popped from the stack.
A program or operating system/executive can set up many stacks. For example, in multitasking systems, each task
can be given its own stack. The number of stacks in a system is limited by the maximum number of segments and
the available physical memory.
When a system sets up many stacks, only one stack—the current stack—is available at a time. The current stack
is the one contained in the segment referenced by the SS register.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Stack Segment
Bottom of Stack
(Initial ESP Value)
Local Variables
for Calling
Procedure
The Stack Can Be
16 or 32 Bits Wide
Parameters
Passed to
Called
Procedure
Frame Boundary
The EBP register is
typically set to point
to the return
instruction pointer.
Return Instruction
Pointer
EBP Register
ESP Register
Top of Stack
Pushes Move the
Top Of Stack to
Lower Addresses
Pops Move the
Top Of Stack to
Higher Addresses
Figure 6-1. Stack Structure
The processor references the SS register automatically for all stack operations. For example, when the ESP register
is used as a memory address, it automatically points to an address in the current stack. Also, the CALL, RET, PUSH,
POP, ENTER, and LEAVE instructions all perform operations on the current stack.
6.2.1
Setting Up a Stack
To set a stack and establish it as the current stack, the program or operating system/executive must do the
following:
1. Establish a stack segment.
2. Load the segment selector for the stack segment into the SS register using a MOV, POP, or LSS instruction.
3. Load the stack pointer for the stack into the ESP register using a MOV, POP, or LSS instruction. The LSS
instruction can be used to load the SS and ESP registers in one operation.
See “Segment Descriptors” in Chapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A, for information on how to set up a segment descriptor and
segment limits for a stack segment.
6.2.2
Stack Alignment
The stack pointer for a stack segment should be aligned on 16-bit (word) or 32-bit (double-word) boundaries,
depending on the width of the stack segment. The D flag in the segment descriptor for the current code segment
sets the stack-segment width (see “Segment Descriptors” in Chapter 3, “Protected-Mode Memory Management,” of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). The PUSH and POP instructions
use the D flag to determine how much to decrement or increment the stack pointer on a push or pop operation,
respectively. When the stack width is 16 bits, the stack pointer is incremented or decremented in 16-bit increments;
when the width is 32 bits, the stack pointer is incremented or decremented in 32-bit increments. Pushing a 16-bit
value onto a 32-bit wide stack can result in stack misaligned (that is, the stack pointer is not aligned on a double6-2 Vol. 1
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
word boundary). One exception to this rule is when the contents of a segment register (a 16-bit segment selector)
are pushed onto a 32-bit wide stack. Here, the processor automatically aligns the stack pointer to the next 32-bit
boundary.
The processor does not check stack pointer alignment. It is the responsibility of the programs, tasks, and system
procedures running on the processor to maintain proper alignment of stack pointers. Misaligning a stack pointer
can cause serious performance degradation and in some instances program failures.
6.2.3
Address-Size Attributes for Stack Accesses
Instructions that use the stack implicitly (such as the PUSH and POP instructions) have two address-size attributes
each of either 16 or 32 bits. This is because they always have the implicit address of the top of the stack, and they
may also have an explicit memory address (for example, PUSH Array1[EBX]). The attribute of the explicit address
is determined by the D flag of the current code segment and the presence or absence of the 67H address-size
prefix.
The address-size attribute of the top of the stack determines whether SP or ESP is used for the stack access. Stack
operations with an address-size attribute of 16 use the 16-bit SP stack pointer register and can use a maximum
stack address of FFFFH; stack operations with an address-size attribute of 32 bits use the 32-bit ESP register and
can use a maximum address of FFFFFFFFH. The default address-size attribute for data segments used as stacks is
controlled by the B flag of the segment’s descriptor. When this flag is clear, the default address-size attribute is 16;
when the flag is set, the address-size attribute is 32.
6.2.4
Procedure Linking Information
The processor provides two pointers for linking of procedures: the stack-frame base pointer and the return instruction pointer. When used in conjunction with a standard software procedure-call technique, these pointers permit
reliable and coherent linking of procedures.
6.2.4.1
Stack-Frame Base Pointer
The stack is typically divided into frames. Each stack frame can then contain local variables, parameters to be
passed to another procedure, and procedure linking information. The stack-frame base pointer (contained in the
EBP register) identifies a fixed reference point within the stack frame for the called procedure. To use the stackframe base pointer, the called procedure typically copies the contents of the ESP register into the EBP register prior
to pushing any local variables on the stack. The stack-frame base pointer then permits easy access to data structures passed on the stack, to the return instruction pointer, and to local variables added to the stack by the called
procedure.
Like the ESP register, the EBP register automatically points to an address in the current stack segment (that is, the
segment specified by the current contents of the SS register).
6.2.4.2
Return Instruction Pointer
Prior to branching to the first instruction of the called procedure, the CALL instruction pushes the address in the EIP
register onto the current stack. This address is then called the return-instruction pointer and it points to the
instruction where execution of the calling procedure should resume following a return from the called procedure.
Upon returning from a called procedure, the RET instruction pops the return-instruction pointer from the stack back
into the EIP register. Execution of the calling procedure then resumes.
The processor does not keep track of the location of the return-instruction pointer. It is thus up to the programmer
to insure that stack pointer is pointing to the return-instruction pointer on the stack, prior to issuing a RET instruction. A common way to reset the stack pointer to the point to the return-instruction pointer is to move the contents
of the EBP register into the ESP register. If the EBP register is loaded with the stack pointer immediately following
a procedure call, it should point to the return instruction pointer on the stack.
The processor does not require that the return instruction pointer point back to the calling procedure. Prior to
executing the RET instruction, the return instruction pointer can be manipulated in software to point to any address
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
in the current code segment (near return) or another code segment (far return). Performing such an operation,
however, should be undertaken very cautiously, using only well defined code entry points.
6.2.5
Stack Behavior in 64-Bit Mode
In 64-bit mode, address calculations that reference SS segments are treated as if the segment base is zero. Fields
(base, limit, and attribute) in segment descriptor registers are ignored. SS DPL is modified such that it is always
equal to CPL. This will be true even if it is the only field in the SS descriptor that is modified.
Registers E(SP), E(IP) and E(BP) are promoted to 64-bits and are re-named RSP, RIP, and RBP respectively. Some
forms of segment load instructions are invalid (for example, LDS, POP ES).
PUSH/POP instructions increment/decrement the stack using a 64-bit width. When the contents of a segment
register is pushed onto 64-bit stack, the pointer is automatically aligned to 64 bits (as with a stack that has a 32bit width).
6.3
CALLING PROCEDURES USING CALL AND RET
The CALL instruction allows control transfers to procedures within the current code segment (near call) and in a
different code segment (far call). Near calls usually provide access to local procedures within the currently running
program or task. Far calls are usually used to access operating system procedures or procedures in a different task.
See “CALL—Call Procedure” in Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 2A, for a detailed description of the CALL instruction.
The RET instruction also allows near and far returns to match the near and far versions of the CALL instruction. In
addition, the RET instruction allows a program to increment the stack pointer on a return to release parameters
from the stack. The number of bytes released from the stack is determined by an optional argument (n) to the RET
instruction. See “RET—Return from Procedure” in Chapter 4, “Instruction Set Reference, M-U,” of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2B, for a detailed description of the RET instruction.
6.3.1
Near CALL and RET Operation
When executing a near call, the processor does the following (see Figure 6-2):
1. Pushes the current value of the EIP register on the stack.
2. Loads the offset of the called procedure in the EIP register.
3. Begins execution of the called procedure.
When executing a near return, the processor performs these actions:
1. Pops the top-of-stack value (the return instruction pointer) into the EIP register.
2. If the RET instruction has an optional n argument, increments the stack pointer by the number of bytes
specified with the n operand to release parameters from the stack.
3. Resumes execution of the calling procedure.
6.3.2
Far CALL and RET Operation
When executing a far call, the processor performs these actions (see Figure 6-2):
1. Pushes the current value of the CS register on the stack.
2. Pushes the current value of the EIP register on the stack.
3. Loads the segment selector of the segment that contains the called procedure in the CS register.
4. Loads the offset of the called procedure in the EIP register.
5. Begins execution of the called procedure.
When executing a far return, the processor does the following:
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
1. Pops the top-of-stack value (the return instruction pointer) into the EIP register.
2. Pops the top-of-stack value (the segment selector for the code segment being returned to) into the CS register.
3. If the RET instruction has an optional n argument, increments the stack pointer by the number of bytes
specified with the n operand to release parameters from the stack.
4. Resumes execution of the calling procedure.
Stack
Frame
Before
Call
Stack
Frame
After
Call
Stack During
Near Call
Param 1
Param 2
Param 3
Calling EIP
Stack During
Near Return
Stack
Frame
Before
Call
ESP Before Call
ESP After Call
Stack
Frame
After
Call
Stack During
Far Call
Param 1
Param 2
Param 3
Calling CS
Calling EIP
ESP After Call
Stack During
Far Return
ESP After Return
ESP After Return
Param 1
Param 2
Param 3
Calling EIP
ESP Before Call
ESP Before Return
Param 1
Param 2
Param 3
Calling CS
Calling EIP
ESP Before Return
Note: On a near or far return, parameters are
released from the stack based on the
optional n operand in the RET n instruction.
Figure 6-2. Stack on Near and Far Calls
6.3.3
Parameter Passing
Parameters can be passed between procedures in any of three ways: through general-purpose registers, in an
argument list, or on the stack.
6.3.3.1
Passing Parameters Through the General-Purpose Registers
The processor does not save the state of the general-purpose registers on procedure calls. A calling procedure can
thus pass up to six parameters to the called procedure by copying the parameters into any of these registers
(except the ESP and EBP registers) prior to executing the CALL instruction. The called procedure can likewise pass
parameters back to the calling procedure through general-purpose registers.
6.3.3.2
Passing Parameters on the Stack
To pass a large number of parameters to the called procedure, the parameters can be placed on the stack, in the
stack frame for the calling procedure. Here, it is useful to use the stack-frame base pointer (in the EBP register) to
make a frame boundary for easy access to the parameters.
The stack can also be used to pass parameters back from the called procedure to the calling procedure.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6.3.3.3
Passing Parameters in an Argument List
An alternate method of passing a larger number of parameters (or a data structure) to the called procedure is to
place the parameters in an argument list in one of the data segments in memory. A pointer to the argument list can
then be passed to the called procedure through a general-purpose register or the stack. Parameters can also be
passed back to the calling procedure in this same manner.
6.3.4
Saving Procedure State Information
The processor does not save the contents of the general-purpose registers, segment registers, or the EFLAGS
register on a procedure call. A calling procedure should explicitly save the values in any of the general-purpose
registers that it will need when it resumes execution after a return. These values can be saved on the stack or in
memory in one of the data segments.
The PUSHA and POPA instructions facilitate saving and restoring the contents of the general-purpose registers.
PUSHA pushes the values in all the general-purpose registers on the stack in the following order: EAX, ECX, EDX,
EBX, ESP (the value prior to executing the PUSHA instruction), EBP, ESI, and EDI. The POPA instruction pops all the
register values saved with a PUSHA instruction (except the ESP value) from the stack to their respective registers.
If a called procedure changes the state of any of the segment registers explicitly, it should restore them to their
former values before executing a return to the calling procedure.
If a calling procedure needs to maintain the state of the EFLAGS register, it can save and restore all or part of the
register using the PUSHF/PUSHFD and POPF/POPFD instructions. The PUSHF instruction pushes the lower word of
the EFLAGS register on the stack, while the PUSHFD instruction pushes the entire register. The POPF instruction
pops a word from the stack into the lower word of the EFLAGS register, while the POPFD instruction pops a double
word from the stack into the register.
6.3.5
Calls to Other Privilege Levels
The IA-32 architecture’s protection mechanism recognizes four privilege levels, numbered from 0 to 3, where a
greater number mean less privilege. The reason to use privilege levels is to improve the reliability of operating
systems. For example, Figure 6-3 shows how privilege levels can be interpreted as rings of protection.
Protection Rings
Operating
System
Kernel
Level 0
Operating System
Services (Device
Drivers, Etc.)
Level 1
Applications
Level 2
Level 3
Highest
0
1
2
Lowest
3
Privilege Levels
Figure 6-3. Protection Rings
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
In this example, the highest privilege level 0 (at the center of the diagram) is used for segments that contain the
most critical code modules in the system, usually the kernel of an operating system. The outer rings (with progressively lower privileges) are used for segments that contain code modules for less critical software.
Code modules in lower privilege segments can only access modules operating at higher privilege segments by
means of a tightly controlled and protected interface called a gate. Attempts to access higher privilege segments
without going through a protection gate and without having sufficient access rights causes a general-protection
exception (#GP) to be generated.
If an operating system or executive uses this multilevel protection mechanism, a call to a procedure that is in a
more privileged protection level than the calling procedure is handled in a similar manner as a far call (see Section
6.3.2, “Far CALL and RET Operation”). The differences are as follows:
•
The segment selector provided in the CALL instruction references a special data structure called a call gate
descriptor. Among other things, the call gate descriptor provides the following:
— access rights information
— the segment selector for the code segment of the called procedure
— an offset into the code segment (that is, the instruction pointer for the called procedure)
•
The processor switches to a new stack to execute the called procedure. Each privilege level has its own stack.
The segment selector and stack pointer for the privilege level 3 stack are stored in the SS and ESP registers,
respectively, and are automatically saved when a call to a more privileged level occurs. The segment selectors
and stack pointers for the privilege level 2, 1, and 0 stacks are stored in a system segment called the task state
segment (TSS).
The use of a call gate and the TSS during a stack switch are transparent to the calling procedure, except when a
general-protection exception is raised.
6.3.6
CALL and RET Operation Between Privilege Levels
When making a call to a more privileged protection level, the processor does the following (see Figure 6-4):
1. Performs an access rights check (privilege check).
2. Temporarily saves (internally) the current contents of the SS, ESP, CS, and EIP registers.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Stack for
Calling Procedure
Stack for
Called Procedure
Param 1
Param 2
Param 3
Calling SS
Calling ESP
Param 1
Param 2
Param 3
Calling CS
Calling EIP
Stack Frame
Before Call
ESP Before Call
ESP After Call
ESP After Return
Param 1
Param 2
Param 3
ESP Before Return
Stack Frame
After Call
Calling SS
Calling ESP
Param 1
Param 2
Param 3
Calling CS
Calling EIP
Note: On a return, parameters are
released on both stacks based on the
optional n operand in the RET n instruction.
Figure 6-4. Stack Switch on a Call to a Different Privilege Level
3. Loads the segment selector and stack pointer for the new stack (that is, the stack for the privilege level being
called) from the TSS into the SS and ESP registers and switches to the new stack.
4. Pushes the temporarily saved SS and ESP values for the calling procedure’s stack onto the new stack.
5. Copies the parameters from the calling procedure’s stack to the new stack. A value in the call gate descriptor
determines how many parameters to copy to the new stack.
6. Pushes the temporarily saved CS and EIP values for the calling procedure to the new stack.
7. Loads the segment selector for the new code segment and the new instruction pointer from the call gate into
the CS and EIP registers, respectively.
8. Begins execution of the called procedure at the new privilege level.
When executing a return from the privileged procedure, the processor performs these actions:
1. Performs a privilege check.
2. Restores the CS and EIP registers to their values prior to the call.
3. If the RET instruction has an optional n argument, increments the stack pointer by the number of bytes
specified with the n operand to release parameters from the stack. If the call gate descriptor specifies that one
or more parameters be copied from one stack to the other, a RET n instruction must be used to release the
parameters from both stacks. Here, the n operand specifies the number of bytes occupied on each stack by the
parameters. On a return, the processor increments ESP by n for each stack to step over (effectively remove)
these parameters from the stacks.
4. Restores the SS and ESP registers to their values prior to the call, which causes a switch back to the stack of
the calling procedure.
5. If the RET instruction has an optional n argument, increments the stack pointer by the number of bytes
specified with the n operand to release parameters from the stack (see explanation in step 3).
6. Resumes execution of the calling procedure.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
See Chapter 5, “Protection,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for
detailed information on calls to privileged levels and the call gate descriptor.
6.3.7
Branch Functions in 64-Bit Mode
The 64-bit extensions expand branching mechanisms to accommodate branches in 64-bit linear-address space.
These are:
•
•
Near-branch semantics are redefined in 64-bit mode
In 64-bit mode and compatibility mode, 64-bit call-gate descriptors for far calls are available
In 64-bit mode, the operand size for all near branches (CALL, RET, JCC, JCXZ, JMP, and LOOP) is forced to 64 bits.
These instructions update the 64-bit RIP without the need for a REX operand-size prefix.
The following aspects of near branches are controlled by the effective operand size:
•
•
•
•
Truncation of the size of the instruction pointer
Size of a stack pop or push, due to a CALL or RET
Size of a stack-pointer increment or decrement, due to a CALL or RET
Indirect-branch operand size
In 64-bit mode, all of the above actions are forced to 64 bits regardless of operand size prefixes (operand size
prefixes are silently ignored). However, the displacement field for relative branches is still limited to 32 bits and the
address size for near branches is not forced in 64-bit mode.
Address sizes affect the size of RCX used for JCXZ and LOOP; they also impact the address calculation for memory
indirect branches. Such addresses are 64 bits by default; but they can be overridden to 32 bits by an address size
prefix.
Software typically uses far branches to change privilege levels. The legacy IA-32 architecture provides the call-gate
mechanism to allow software to branch from one privilege level to another, although call gates can also be used for
branches that do not change privilege levels. When call gates are used, the selector portion of the direct or indirect
pointer references a gate descriptor (the offset in the instruction is ignored). The offset to the destination’s code
segment is taken from the call-gate descriptor.
64-bit mode redefines the type value of a 32-bit call-gate descriptor type to a 64-bit call gate descriptor and
expands the size of the 64-bit descriptor to hold a 64-bit offset. The 64-bit mode call-gate descriptor allows far
branches that reference any location in the supported linear-address space. These call gates also hold the target
code selector (CS), allowing changes to privilege level and default size as a result of the gate transition.
Because immediates are generally specified up to 32 bits, the only way to specify a full 64-bit absolute RIP in 64bit mode is with an indirect branch. For this reason, direct far branches are eliminated from the instruction set in
64-bit mode.
64-bit mode also expands the semantics of the SYSENTER and SYSEXIT instructions so that the instructions
operate within a 64-bit memory space. The mode also introduces two new instructions: SYSCALL and SYSRET
(which are valid only in 64-bit mode). For details, see “SYSENTER—Fast System Call,” “SYSEXIT—Fast Return from
Fast System Call,” “SYSCALL—Fast System Call,” and “SYSRET—Return From Fast System Call” in Chapter 4,
“Instruction Set Reference, M-U,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2B.
6.4
INTERRUPTS AND EXCEPTIONS
The processor provides two mechanisms for interrupting program execution, interrupts and exceptions:
•
•
An interrupt is an asynchronous event that is typically triggered by an I/O device.
An exception is a synchronous event that is generated when the processor detects one or more predefined
conditions while executing an instruction. The IA-32 architecture specifies three classes of exceptions: faults,
traps, and aborts.
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The processor responds to interrupts and exceptions in essentially the same way. When an interrupt or exception
is signaled, the processor halts execution of the current program or task and switches to a handler procedure that
has been written specifically to handle the interrupt or exception condition. The processor accesses the handler
procedure through an entry in the interrupt descriptor table (IDT). When the handler has completed handling the
interrupt or exception, program control is returned to the interrupted program or task.
The operating system, executive, and/or device drivers normally handle interrupts and exceptions independently
from application programs or tasks. Application programs can, however, access the interrupt and exception
handlers incorporated in an operating system or executive through assembly-language calls. The remainder of this
section gives a brief overview of the processor’s interrupt and exception handling mechanism. See Chapter 6,
“Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
3A, for a description of this mechanism.
The IA-32 Architecture defines 18 predefined interrupts and exceptions and 224 user defined interrupts, which are
associated with entries in the IDT. Each interrupt and exception in the IDT is identified with a number, called a
vector. Table 6-1 lists the interrupts and exceptions with entries in the IDT and their respective vectors. Vectors 0
through 8, 10 through 14, and 16 through 19 are the predefined interrupts and exceptions; vectors 32 through 255
are for software-defined interrupts, which are for either software interrupts or maskable hardware interrupts.
Note that the processor defines several additional interrupts that do not point to entries in the IDT; the most
notable of these interrupts is the SMI interrupt. See Chapter 6, “Interrupt and Exception Handling,” in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about the interrupts
and exceptions.
When the processor detects an interrupt or exception, it does one of the following things:
•
•
Executes an implicit call to a handler procedure.
Executes an implicit call to a handler task.
6.4.1
Call and Return Operation for Interrupt or Exception Handling Procedures
A call to an interrupt or exception handler procedure is similar to a procedure call to another protection level (see
Section 6.3.6, “CALL and RET Operation Between Privilege Levels”). Here, the vector references one of two kinds
of gates in the IDT: an interrupt gate or a trap gate. Interrupt and trap gates are similar to call gates in that they
provide the following information:
•
•
•
Access rights information
The segment selector for the code segment that contains the handler procedure
An offset into the code segment to the first instruction of the handler procedure
The difference between an interrupt gate and a trap gate is as follows. If an interrupt or exception handler is called
through an interrupt gate, the processor clears the interrupt enable (IF) flag in the EFLAGS register to prevent
subsequent interrupts from interfering with the execution of the handler. When a handler is called through a trap
gate, the state of the IF flag is not changed.
Table 6-1. Exceptions and Interrupts
Vector
Mnemonic
Description
Source
0
#DE
Divide Error
DIV and IDIV instructions.
1
#DB
Debug
Any code or data reference.
NMI Interrupt
Non-maskable external interrupt.
2
3
#BP
Breakpoint
INT 3 instruction.
4
#OF
Overflow
INTO instruction.
5
#BR
BOUND Range Exceeded
BOUND instruction.
6
#UD
Invalid Opcode (UnDefined Opcode)
UD2 instruction or reserved opcode.1
7
#NM
Device Not Available (No Math Coprocessor)
Floating-point or WAIT/FWAIT instruction.
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Table 6-1. Exceptions and Interrupts (Contd.)
Vector
Mnemonic
Description
Source
8
#DF
Double Fault
Any instruction that can generate an exception, an NMI, or
an INTR.
9
#MF
CoProcessor Segment Overrun (reserved)
Floating-point instruction.2
10
#TS
Invalid TSS
Task switch or TSS access.
11
#NP
Segment Not Present
Loading segment registers or accessing system segments.
12
#SS
Stack Segment Fault
Stack operations and SS register loads.
13
#GP
General Protection
Any memory reference and other protection checks.
14
#PF
Page Fault
Any memory reference.
15
Reserved
16
#MF
Floating-Point Error (Math Fault)
Floating-point or WAIT/FWAIT instruction.
17
#AC
Alignment Check
Any data reference in memory.3
18
#MC
Machine Check
Error codes (if any) and source are model dependent.4
19
#XM
SIMD Floating-Point Exception
SIMD Floating-Point Instruction5
20
#VE
Virtualization Exception
EPT violations6
21-31
Reserved
32-255
Maskable Interrupts
External interrupt from INTR pin or INT n instruction.
NOTES:
1. The UD2 instruction was introduced in the Pentium Pro processor.
2. IA-32 processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.
5. This exception was introduced in the Pentium III processor.
6. This exception can occur only on processors that support the 1-setting of the “EPT-violation #VE” VM-execution control.
If the code segment for the handler procedure has the same privilege level as the currently executing program or
task, the handler procedure uses the current stack; if the handler executes at a more privileged level, the
processor switches to the stack for the handler’s privilege level.
If no stack switch occurs, the processor does the following when calling an interrupt or exception handler (see
Figure 6-5):
1. Pushes the current contents of the EFLAGS, CS, and EIP registers (in that order) on the stack.
2. Pushes an error code (if appropriate) on the stack.
3. Loads the segment selector for the new code segment and the new instruction pointer (from the interrupt gate
or trap gate) into the CS and EIP registers, respectively.
4. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.
5. Begins execution of the handler procedure.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Interrupted Procedure’s
and Handler’s Stack
EFLAGS
CS
EIP
Error Code
Stack Usage with No
Privilege-Level Change
ESP Before
Transfer to Handler
ESP After
Transfer to Handler
Stack Usage with
Privilege-Level Change
Interrupted Procedure’s
Stack
Handler’s Stack
ESP Before
Transfer to Handler
ESP After
Transfer to Handler
SS
ESP
EFLAGS
CS
EIP
Error Code
Figure 6-5. Stack Usage on Transfers to Interrupt and Exception Handling Routines
If a stack switch does occur, the processor does the following:
1. Temporarily saves (internally) the current contents of the SS, ESP, EFLAGS, CS, and EIP registers.
2. Loads the segment selector and stack pointer for the new stack (that is, the stack for the privilege level being
called) from the TSS into the SS and ESP registers and switches to the new stack.
3. Pushes the temporarily saved SS, ESP, EFLAGS, CS, and EIP values for the interrupted procedure’s stack onto
the new stack.
4. Pushes an error code on the new stack (if appropriate).
5. Loads the segment selector for the new code segment and the new instruction pointer (from the interrupt gate
or trap gate) into the CS and EIP registers, respectively.
6. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.
7. Begins execution of the handler procedure at the new privilege level.
A return from an interrupt or exception handler is initiated with the IRET instruction. The IRET instruction is similar
to the far RET instruction, except that it also restores the contents of the EFLAGS register for the interrupted procedure. When executing a return from an interrupt or exception handler from the same privilege level as the interrupted procedure, the processor performs these actions:
1. Restores the CS and EIP registers to their values prior to the interrupt or exception.
2. Restores the EFLAGS register.
3. Increments the stack pointer appropriately.
4. Resumes execution of the interrupted procedure.
When executing a return from an interrupt or exception handler from a different privilege level than the interrupted
procedure, the processor performs these actions:
1. Performs a privilege check.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
2. Restores the CS and EIP registers to their values prior to the interrupt or exception.
3. Restores the EFLAGS register.
4. Restores the SS and ESP registers to their values prior to the interrupt or exception, resulting in a stack switch
back to the stack of the interrupted procedure.
5. Resumes execution of the interrupted procedure.
6.4.2
Calls to Interrupt or Exception Handler Tasks
Interrupt and exception handler routines can also be executed in a separate task. Here, an interrupt or exception
causes a task switch to a handler task. The handler task is given its own address space and (optionally) can
execute at a higher protection level than application programs or tasks.
The switch to the handler task is accomplished with an implicit task call that references a task gate descriptor.
The task gate provides access to the address space for the handler task. As part of the task switch, the processor
saves complete state information for the interrupted program or task. Upon returning from the handler task, the
state of the interrupted program or task is restored and execution continues. See Chapter 6, “Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on handling interrupts and exceptions through handler tasks.
6.4.3
Interrupt and Exception Handling in Real-Address Mode
When operating in real-address mode, the processor responds to an interrupt or exception with an implicit far call
to an interrupt or exception handler. The processor uses the interrupt or exception vector as an index into an interrupt table. The interrupt table contains instruction pointers to the interrupt and exception handler procedures.
The processor saves the state of the EFLAGS register, the EIP register, the CS register, and an optional error code
on the stack before switching to the handler procedure.
A return from the interrupt or exception handler is carried out with the IRET
instruction.
See Chapter 20, “8086 Emulation,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
3B, for more information on handling interrupts and exceptions in real-address mode.
6.4.4
INT n, INTO, INT 3, and BOUND Instructions
The INT n, INTO, INT 3, and BOUND instructions allow a program or task to explicitly call an interrupt or exception
handler. The INT n instruction uses a vector as an argument, which allows a program to call any interrupt handler.
The INTO instruction explicitly calls the overflow exception (#OF) handler if the overflow flag (OF) in the EFLAGS
register is set. The OF flag indicates overflow on arithmetic instructions, but it does not automatically raise an overflow exception. An overflow exception can only be raised explicitly in either of the following ways:
•
•
Execute the INTO instruction.
Test the OF flag and execute the INT n instruction with an argument of 4 (the vector of the overflow exception)
if the flag is set.
Both the methods of dealing with overflow conditions allow a program to test for overflow at specific places in the
instruction stream.
The INT 3 instruction explicitly calls the breakpoint exception (#BP) handler.
The BOUND instruction explicitly calls the BOUND-range exceeded exception (#BR) handler if an operand is found
to be not within predefined boundaries in memory. This instruction is provided for checking references to arrays
and other data structures. Like the overflow exception, the BOUND-range exceeded exception can only be raised
explicitly with the BOUND instruction or the INT n instruction with an argument of 5 (the vector of the boundscheck exception). The processor does not implicitly perform bounds checks and raise the BOUND-range exceeded
exception.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6.4.5
Handling Floating-Point Exceptions
When operating on individual or packed floating-point values, the IA-32 architecture supports a set of six floatingpoint exceptions. These exceptions can be generated during operations performed by the x87 FPU instructions or
by SSE/SSE2/SSE3 instructions. When an x87 FPU instruction (including the FISTTP instruction in SSE3) generates
one or more of these exceptions, it in turn generates floating-point error exception (#MF); when an
SSE/SSE2/SSE3 instruction generates a floating-point exception, it in turn generates SIMD floating-point exception
(#XM).
See the following sections for further descriptions of the floating-point exceptions, how they are generated, and
how they are handled:
•
Section 4.9.1, “Floating-Point Exception Conditions,” and Section 4.9.3, “Typical Actions of a Floating-Point
Exception Handler”
•
Section 8.4, “x87 FPU Floating-Point Exception Handling,” and Section 8.5, “x87 FPU Floating-Point Exception
Conditions”
•
•
Section 11.5.1, “SIMD Floating-Point Exceptions”
Interrupt Behavior
6.4.6
Interrupt and Exception Behavior in 64-Bit Mode
64-bit extensions expand the legacy IA-32 interrupt-processing and exception-processing mechanism to allow
support for 64-bit operating systems and applications. Changes include:
•
•
•
•
•
•
•
All interrupt handlers pointed to by the IDT are 64-bit code (does not apply to the SMI handler).
The size of interrupt-stack pushes is fixed at 64 bits. The processor uses 8-byte, zero extended stores.
The stack pointer (SS:RSP) is pushed unconditionally on interrupts. In legacy environments, this push is
conditional and based on a change in current privilege level (CPL).
The new SS is set to NULL if there is a change in CPL.
IRET behavior changes.
There is a new interrupt stack-switch mechanism.
The alignment of interrupt stack frame is different.
6.5
PROCEDURE CALLS FOR BLOCK-STRUCTURED LANGUAGES
The IA-32 architecture supports an alternate method of performing procedure calls with the ENTER (enter procedure) and LEAVE (leave procedure) instructions. These instructions automatically create and release, respectively,
stack frames for called procedures. The stack frames have predefined spaces for local variables and the necessary
pointers to allow coherent returns from called procedures. They also allow scope rules to be implemented so that
procedures can access their own local variables and some number of other variables located in other stack frames.
ENTER and LEAVE offer two benefits:
•
•
They provide machine-language support for implementing block-structured languages, such as C and Pascal.
They simplify procedure entry and exit in compiler-generated code.
6.5.1
ENTER Instruction
The ENTER instruction creates a stack frame compatible with the scope rules typically used in block-structured
languages. In block-structured languages, the scope of a procedure is the set of variables to which it has access.
The rules for scope vary among languages. They may be based on the nesting of procedures, the division of the
program into separately compiled files, or some other modularization scheme.
ENTER has two operands. The first specifies the number of bytes to be reserved on the stack for dynamic storage
for the procedure being called. Dynamic storage is the memory allocated for variables created when the procedure
is called, also known as automatic variables. The second parameter is the lexical nesting level (from 0 to 31) of the
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
procedure. The nesting level is the depth of a procedure in a hierarchy of procedure calls. The lexical level is unrelated to either the protection privilege level or to the I/O privilege level of the currently running program or task.
ENTER, in the following example, allocates 2 Kbytes of dynamic storage on the stack and sets up pointers to two
previous stack frames in the stack frame for this procedure:
ENTER 2048,3
The lexical nesting level determines the number of stack frame pointers to copy into the new stack frame from the
preceding frame. A stack frame pointer is a doubleword used to access the variables of a procedure. The set of
stack frame pointers used by a procedure to access the variables of other procedures is called the display. The first
doubleword in the display is a pointer to the previous stack frame. This pointer is used by a LEAVE instruction to
undo the effect of an ENTER instruction by discarding the current stack frame.
After the ENTER instruction creates the display for a procedure, it allocates the dynamic local variables for the
procedure by decrementing the contents of the ESP register by the number of bytes specified in the first parameter.
This new value in the ESP register serves as the initial top-of-stack for all PUSH and POP operations within the
procedure.
To allow a procedure to address its display, the ENTER instruction leaves the EBP register pointing to the first
doubleword in the display. Because stacks grow down, this is actually the doubleword with the highest address in
the display. Data manipulation instructions that specify the EBP register as a base register automatically address
locations within the stack segment instead of the data segment.
The ENTER instruction can be used in two ways: nested and non-nested. If the lexical level is 0, the non-nested
form is used. The non-nested form pushes the contents of the EBP register on the stack, copies the contents of the
ESP register into the EBP register, and subtracts the first operand from the contents of the ESP register to allocate
dynamic storage. The non-nested form differs from the nested form in that no stack frame pointers are copied. The
nested form of the ENTER instruction occurs when the second parameter (lexical level) is not zero.
The following pseudo code shows the formal definition of the ENTER instruction. STORAGE is the number of bytes
of dynamic storage to allocate for local variables, and LEVEL is the lexical nesting level.
PUSH EBP;
FRAME_PTR ← ESP;
IF LEVEL > 0
THEN
DO (LEVEL − 1) times
EBP ← EBP − 4;
PUSH Pointer(EBP); (* doubleword pointed to by EBP *)
OD;
PUSH FRAME_PTR;
FI;
EBP ← FRAME_PTR;
ESP ← ESP − STORAGE;
The main procedure (in which all other procedures are nested) operates at the highest lexical level, level 1. The
first procedure it calls operates at the next deeper lexical level, level 2. A level 2 procedure can access the variables
of the main program, which are at fixed locations specified by the compiler. In the case of level 1, the ENTER
instruction allocates only the requested dynamic storage on the stack because there is no previous display to copy.
A procedure that calls another procedure at a lower lexical level gives the called procedure access to the variables
of the caller. The ENTER instruction provides this access by placing a pointer to the calling procedure's stack frame
in the display.
A procedure that calls another procedure at the same lexical level should not give access to its variables. In this
case, the ENTER instruction copies only that part of the display from the calling procedure which refers to previously nested procedures operating at higher lexical levels. The new stack frame does not include the pointer for
addressing the calling procedure’s stack frame.
The ENTER instruction treats a re-entrant procedure as a call to a procedure at the same lexical level. In this case,
each succeeding iteration of the re-entrant procedure can address only its own variables and the variables of the
procedures within which it is nested. A re-entrant procedure always can address its own variables; it does not
require pointers to the stack frames of previous iterations.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
By copying only the stack frame pointers of procedures at higher lexical levels, the ENTER instruction makes certain
that procedures access only those variables of higher lexical levels, not those at parallel lexical levels (see
Figure 6-6).
Main (Lexical Level 1)
Procedure A (Lexical Level 2)
Procedure B (Lexical Level 3)
Procedure C (Lexical Level 3)
Procedure D (Lexical Level 4)
Figure 6-6. Nested Procedures
Block-structured languages can use the lexical levels defined by ENTER to control access to the variables of nested
procedures. In Figure 6-6, for example, if procedure A calls procedure B which, in turn, calls procedure C, then
procedure C will have access to the variables of the MAIN procedure and procedure A, but not those of procedure
B because they are at the same lexical level. The following definition describes the access to variables for the
nested procedures in Figure 6-6.
1. MAIN has variables at fixed locations.
2. Procedure A can access only the variables of MAIN.
3. Procedure B can access only the variables of procedure A and MAIN. Procedure B cannot access the variables of
procedure C or procedure D.
4. Procedure C can access only the variables of procedure A and MAIN. Procedure C cannot access the variables of
procedure B or procedure D.
5. Procedure D can access the variables of procedure C, procedure A, and MAIN. Procedure D cannot access the
variables of procedure B.
In Figure 6-7, an ENTER instruction at the beginning of the MAIN procedure creates three doublewords of dynamic
storage for MAIN, but copies no pointers from other stack frames. The first doubleword in the display holds a copy
of the last value in the EBP register before the ENTER instruction was executed. The second doubleword holds a
copy of the contents of the EBP register following the ENTER instruction. After the instruction is executed, the EBP
register points to the first doubleword pushed on the stack, and the ESP register points to the last doubleword in
the stack frame.
When MAIN calls procedure A, the ENTER instruction creates a new display (see Figure 6-8). The first doubleword
is the last value held in MAIN's EBP register. The second doubleword is a pointer to MAIN's stack frame which is
copied from the second doubleword in MAIN's display. This happens to be another copy of the last value held in
MAIN’s EBP register. Procedure A can access variables in MAIN because MAIN is at level 1.
Therefore the base address for the dynamic storage used in MAIN is the current address in the EBP register, plus
four bytes to account for the saved contents of MAIN’s EBP register. All dynamic variables for MAIN are at fixed,
positive offsets from this value.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Display
Old EBP
EBP
Main’s EBP
Dynamic
Storage
ESP
Figure 6-7. Stack Frame After Entering the MAIN Procedure
Old EBP
Main’s EBP
Display
Main’s EBP
Main’s EBP
Procedure A’s EBP
EBP
Dynamic
Storage
ESP
Figure 6-8. Stack Frame After Entering Procedure A
When procedure A calls procedure B, the ENTER instruction creates a new display (see Figure 6-9). The first
doubleword holds a copy of the last value in procedure A’s EBP register. The second and third doublewords are
copies of the two stack frame pointers in procedure A’s display. Procedure B can access variables in procedure A
and MAIN by using the stack frame pointers in its display.
When procedure B calls procedure C, the ENTER instruction creates a new display for procedure C (see
Figure 6-10). The first doubleword holds a copy of the last value in procedure B’s EBP register. This is used by the
LEAVE instruction to restore procedure B’s stack frame. The second and third doublewords are copies of the two
stack frame pointers in procedure A’s display. If procedure C were at the next deeper lexical level from procedure
B, a fourth doubleword would be copied, which would be the stack frame pointer to procedure B’s local variables.
Note that procedure B and procedure C are at the same level, so procedure C is not intended to access procedure
B’s variables. This does not mean that procedure C is completely isolated from procedure B; procedure C is called
by procedure B, so the pointer to the returning stack frame is a pointer to procedure B’s stack frame. In addition,
procedure B can pass parameters to procedure C either on the stack or through variables global to both procedures
(that is, variables in the scope of both procedures).
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Old EBP
Main’s EBP
Main’s EBP
Main’s EBP
Procedure A’s EBP
Procedure A’s EBP
Display
EBP
Main’s EBP
Procedure A’s EBP
Procedure B’s EBP
Dynamic
Storage
ESP
Figure 6-9. Stack Frame After Entering Procedure B
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Old EBP
Main’s EBP
Main’s EBP
Main’s EBP
Procedure A’s EBP
Procedure A’s EBP
Main’s EBP
Procedure A’s EBP
Procedure B’s EBP
Procedure B’s EBP
Display
EBP
Main’s EBP
Procedure A’s EBP
Procedure C’s EBP
Dynamic
Storage
ESP
Figure 6-10. Stack Frame After Entering Procedure C
6.5.2
LEAVE Instruction
The LEAVE instruction, which does not have any operands, reverses the action of the previous ENTER instruction.
The LEAVE instruction copies the contents of the EBP register into the ESP register to release all stack space allocated to the procedure. Then it restores the old value of the EBP register from the stack. This simultaneously
restores the ESP register to its original value. A subsequent RET instruction then can remove any arguments and
the return address pushed on the stack by the calling program for use by the procedure.
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PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6-20 Vol. 1
CHAPTER 7
PROGRAMMING WITH
GENERAL-PURPOSE INSTRUCTIONS
General-purpose (GP) instructions are a subset of the IA-32 instructions that represent the fundamental instruction
set for the Intel IA-32 processors. These instructions were introduced into the IA-32 architecture with the first IA32 processors (the Intel 8086 and 8088). Additional instructions were added to the general-purpose instruction set
in subsequent families of IA-32 processors (the Intel 286, Intel386, Intel486, Pentium, Pentium Pro, and Pentium
II processors).
Intel 64 architecture further extends the capability of most general-purpose instructions so that they are able to
handle 64-bit data in 64-bit mode. A small number of general-purpose instructions (still supported in non-64-bit
modes) are not supported in 64-bit mode.
General-purpose instructions perform basic data movement, memory addressing, arithmetic and logical, program
flow control, input/output, and string operations on a set of integer, pointer, and BCD data types. This chapter
provides an overview of the general-purpose instructions. See Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D, for detailed descriptions of individual instructions.
7.1
PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS
The programming environment for the general-purpose instructions consists of the set of registers and address
space. The environment includes the following items:
•
General-purpose registers — Eight 32-bit general-purpose registers (see Section 3.4.1, “General-Purpose
Registers”) are used in non-64-bit modes to address operands in memory. These registers are referenced by
the names EAX, EBX, ECX, EDX, EBP, ESI EDI, and ESP.
•
Segment registers — The six 16-bit segment registers contain segment pointers for use in accessing memory
(see Section 3.4.2, “Segment Registers”). These registers are referenced by the names CS, DS, SS, ES, FS, and
GS.
•
EFLAGS register — This 32-bit register (see Section 3.4.3, “EFLAGS Register”) is used to provide status and
control for basic arithmetic, compare, and system operations.
•
EIP register — This 32-bit register contains the current instruction pointer (see Section 3.5, “Instruction
Pointer”).
General-purpose instructions operate on the following data types. The width of valid data types is dependent on
processor mode (see Chapter 4):
•
•
•
•
•
Bytes, words, doublewords
Signed and unsigned byte, word, doubleword integers
Near and far pointers
Bit fields
BCD integers
7.2
PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS IN 64-BIT MODE
The programming environment for the general-purpose instructions in 64-bit mode is similar to that described in
Section 7.1.
•
General-purpose registers — In 64-bit mode, sixteen general-purpose registers available. These include the
eight GPRs described in Section 7.1 and eight new GPRs (R8D-R15D). R8D-R15D are available by using a REX
prefix. All sixteen GPRs can be promoted to 64 bits. The 64-bit registers are referenced as RAX, RBX, RCX, RDX,
RBP, RSI, RDI, RSP and R8-R15 (see Section 3.4.1.1, “General-Purpose Registers in 64-Bit Mode”). Promotion
to 64-bit operand requires REX prefix encodings.
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PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
•
Segment registers — In 64-bit mode, segmentation is available but it is set up uniquely (see Section 3.4.2.1,
“Segment Registers in 64-Bit Mode”).
•
Flags and Status register — When the processor is running in 64-bit mode, EFLAGS becomes the 64-bit
RFLAGS register (see Section 3.4.3, “EFLAGS Register”).
•
Instruction Pointer register — In 64-bit mode, the EIP register becomes the 64-bit RIP register (see Section
3.5.1, “Instruction Pointer in 64-Bit Mode”).
General-purpose instructions operate on the following data types in 64-bit mode. The width of valid data types is
dependent on default operand size, address size, or a prefix that overrides the default size:
•
•
•
•
Bytes, words, doublewords, quadwords
Signed and unsigned byte, word, doubleword, quadword integers
Near and far pointers
Bit fields
See also:
•
•
Chapter 3, “Basic Execution Environment,” for more information about IA-32e modes.
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B for a complete listing of all
instructions. This information documents the behavior of individual instructions in the 64-bit mode context.
Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A, for more detailed information about REX prefixes.
7.3
SUMMARY OF GP INSTRUCTIONS
General purpose instructions are divided into the following subgroups:
•
•
•
•
•
•
•
•
•
•
•
•
•
Data transfer
Binary arithmetic
Decimal arithmetic
Logical
Shift and rotate
Bit and byte
Control transfer
String
I/O
Enter and Leave
Flag control
Segment register
Miscellaneous
Each sub-group of general-purpose instructions is discussed in the context of non-64-bit mode operation first.
Changes in 64-bit mode beyond those affected by the use of the REX prefixes are discussed in separate subsections within each subgroup. For a simple list of general-purpose instructions by subgroup, see Chapter 5.
7.3.1
Data Transfer Instructions
The data transfer instructions move bytes, words, doublewords, or quadwords both between memory and the
processor’s registers and between registers. For the purpose of this discussion, these instructions are divided into
subordinate subgroups that provide for:
•
•
General data movement
Exchange
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PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
•
•
Stack manipulation
Type conversion
7.3.1.1
General Data Movement Instructions
Move instructions — The MOV (move) and CMOVcc (conditional move) instructions transfer data between
memory and registers or between registers.
The MOV instruction performs basic load data and store data operations between memory and the processor’s
registers and data movement operations between registers. It handles data transfers along the paths listed in
Table 7-1. (See “MOV—Move to/from Control Registers” and “MOV—Move to/from Debug Registers” in Chapter 4,
“Instruction Set Reference, M-U,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A, for information on moving data to and from the control and debug registers.)
The MOV instruction cannot move data from one memory location to another or from one segment register to
another segment register. Memory-to-memory moves are performed with the MOVS (string move) instruction (see
Section 7.3.9, “String Operations”).
Conditional move instructions — The CMOVcc instructions are a group of instructions that check the state of the
status flags in the EFLAGS register and perform a move operation if the flags are in a specified state. These instructions can be used to move a 16-bit or 32-bit value from memory to a general-purpose register or from one generalpurpose register to another. The flag state being tested is specified with a condition code (cc) associated with the
instruction. If the condition is not satisfied, a move is not performed and execution continues with the instruction
following the CMOVcc instruction.
Table 7-1. Move Instruction Operations
Type of Data Movement
From memory to a register
Source → Destination
Memory location → General-purpose register
Memory location → Segment register
From a register to memory
General-purpose register → Memory location
Segment register → Memory location
Between registers
General-purpose register → General-purpose register
General-purpose register → Segment register
Segment register → General-purpose register
General-purpose register → Control register
Control register → General-purpose register
General-purpose register → Debug register
Debug register → General-purpose register
Immediate data to a register
Immediate → General-purpose register
Immediate data to memory
Immediate → Memory location
Table 7-2 shows mnemonics for CMOVcc instructions and the conditions being tested for each instruction. The
condition code mnemonics are appended to the letters “CMOV” to form the mnemonics for CMOVcc instructions.
The instructions listed in Table 7-2 as pairs (for example, CMOVA/CMOVNBE) are alternate names for the same
instruction. The assembler provides these alternate names to make it easier to read program listings.
CMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching overhead
for IF statements and the possibility of branch mispredictions by the processor.
These conditional move instructions are supported in the P6 family, Pentium 4, and Intel Xeon processors. Software
can check if CMOVcc instructions are supported by checking the processor’s feature information with the CPUID
instruction.
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PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7.3.1.2
Exchange Instructions
The exchange instructions swap the contents of one or more operands and, in some cases, perform additional operations such as asserting the LOCK signal or modifying flags in the EFLAGS register.
The XCHG (exchange) instruction swaps the contents of two operands. This instruction takes the place of three
MOV instructions and does not require a temporary location to save the contents of one operand location while the
other is being loaded. When a memory operand is used with the XCHG instruction, the processor’s LOCK signal is
automatically asserted. This instruction is thus useful for implementing semaphores or similar data structures for
process synchronization. See “Bus Locking” in Chapter 8, “Multiple-Processor Management,”of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on bus locking.
The BSWAP (byte swap) instruction reverses the byte order in a 32-bit register operand. Bit positions 0 through 7
are exchanged with 24 through 31, and bit positions 8 through 15 are exchanged with 16 through 23. Executing
this instruction twice in a row leaves the register with the same value as before. The BSWAP instruction is useful for
converting between “big-endian” and “little-endian” data formats. This instruction also speeds execution of decimal
arithmetic. (The XCHG instruction can be used to swap the bytes in a word.)
Table 7-2. Conditional Move Instructions
Instruction Mnemonic
Status Flag States
Condition Description
CMOVA/CMOVNBE
(CF or ZF) = 0
Above/not below or equal
CMOVAE/CMOVNB
CF = 0
Above or equal/not below
CMOVNC
CF = 0
Not carry
CMOVB/CMOVNAE
CF = 1
Below/not above or equal
CMOVC
CF = 1
Carry
CMOVBE/CMOVNA
(CF or ZF) = 1
Below or equal/not above
CMOVE/CMOVZ
ZF = 1
Equal/zero
CMOVNE/CMOVNZ
ZF = 0
Not equal/not zero
CMOVP/CMOVPE
PF = 1
Parity/parity even
CMOVNP/CMOVPO
PF = 0
Not parity/parity odd
CMOVGE/CMOVNL
(SF xor OF) = 0
Greater or equal/not less
CMOVL/CMOVNGE
(SF xor OF) = 1
Less/not greater or equal
CMOVLE/CMOVNG
((SF xor OF) or ZF) = 1
Less or equal/not greater
CMOVO
OF = 1
Overflow
CMOVNO
OF = 0
Not overflow
CMOVS
SF = 1
Sign (negative)
CMOVNS
SF = 0
Not sign (non-negative)
Unsigned Conditional Moves
Signed Conditional Moves
The XADD (exchange and add) instruction swaps two operands and then stores the sum of the two operands in the
destination operand. The status flags in the EFLAGS register indicate the result of the addition. This instruction can
be combined with the LOCK prefix (see “LOCK—Assert LOCK# Signal Prefix” in Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A) in a multiprocessing
system to allow multiple processors to execute one DO loop.
The CMPXCHG (compare and exchange) and CMPXCHG8B (compare and exchange 8 bytes) instructions are used
to synchronize operations in systems that use multiple processors. The CMPXCHG instruction requires three operands: a source operand in a register, another source operand in the EAX register, and a destination operand. If
the values contained in the destination operand and the EAX register are equal, the destination operand is
replaced with the value of the other source operand (the value not in the EAX register). Otherwise, the original
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PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
value of the destination operand is loaded in the EAX register. The status flags in the EFLAGS register reflect the
result that would have been obtained by subtracting the destination operand from the value in the EAX register.
The CMPXCHG instruction is commonly used for testing and modifying semaphores. It checks to see if a semaphore
is free. If the semaphore is free, it is marked allocated; otherwise it gets the ID of the current owner. This is all done
in one uninterruptible operation. In a single-processor system, the CMPXCHG instruction eliminates the need to
switch to protection level 0 (to disable interrupts) before executing multiple instructions to test and modify a semaphore.
For multiple processor systems, CMPXCHG can be combined with the LOCK prefix to perform the compare and
exchange operation atomically. (See “Locked Atomic Operations” in Chapter 8, “Multiple-Processor Management,”
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on atomic
operations.)
The CMPXCHG8B instruction also requires three operands: a 64-bit value in EDX:EAX, a 64-bit value in ECX:EBX,
and a destination operand in memory. The instruction compares the 64-bit value in the EDX:EAX registers with the
destination operand. If they are equal, the 64-bit value in the ECX:EBX registers is stored in the destination
operand. If the EDX:EAX registers and the destination are not equal, the destination is loaded in the EDX:EAX
registers. The CMPXCHG8B instruction can be combined with the LOCK prefix to perform the operation atomically.
7.3.1.3
Exchange Instructions in 64-Bit Mode
The CMPXCHG16B instruction is available in 64-bit mode only. It is an extension of the functionality provided by
CMPXCHG8B that operates on 128-bits of data.
7.3.1.4
Stack Manipulation Instructions
The PUSH, POP, PUSHA (push all registers), and POPA (pop all registers) instructions move data to and from the
stack. The PUSH instruction decrements the stack pointer (contained in the ESP register), then copies the source
operand to the top of stack (see Figure 7-1). It operates on memory operands, immediate operands, and register
operands (including segment registers). The PUSH instruction is commonly used to place parameters on the stack
before calling a procedure. It can also be used to reserve space on the stack for temporary variables.
Stack
Stack
Growth
Before Pushing Doubleword
31
n
n−4
n−8
After Pushing Doubleword
31
0
0
ESP
Doubleword Value
ESP
Figure 7-1. Operation of the PUSH Instruction
The PUSHA instruction saves the contents of the eight general-purpose registers on the stack (see Figure 7-2).
This instruction simplifies procedure calls by reducing the number of instructions required to save the contents of
the general-purpose registers. The registers are pushed on the stack in the following order: EAX, ECX, EDX, EBX,
the initial value of ESP before EAX was pushed, EBP, ESI, and EDI.
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Stack
Before Pushing Registers
31
0
Stack
Growth
n
n-4
n-8
n - 12
n - 16
n - 20
n - 24
n - 28
n - 32
n - 36
After Pushing Registers
31
0
ESP
EAX
ECX
EDX
EBX
Old ESP
EBP
ESI
EDI
ESP
Figure 7-2. Operation of the PUSHA Instruction
The POP instruction copies the word or doubleword at the current top of stack (indicated by the ESP register) to the
location specified with the destination operand. It then increments the ESP register to point to the new top of stack
(see Figure 7-3). The destination operand may specify a general-purpose register, a segment register, or a memory
location.
Stack
Before Popping Doubleword
Stack
Growth
31
n
n-4
n-8
After Popping Doubleword
0
31
0
ESP
Doubleword Value
ESP
Figure 7-3. Operation of the POP Instruction
The POPA instruction reverses the effect of the PUSHA instruction. It pops the top eight words or doublewords from
the top of the stack into the general-purpose registers, except for the ESP register (see Figure 7-4). If the operandsize attribute is 32, the doublewords on the stack are transferred to the registers in the following order: EDI, ESI,
EBP, ignore doubleword, EBX, EDX, ECX, and EAX. The ESP register is restored by the action of popping the stack.
If the operand-size attribute is 16, the words on the stack are transferred to the registers in the following order: DI,
SI, BP, ignore word, BX, DX, CX, and AX.
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Stack
Stack
Growth
n
n-4
n-8
n - 12
n - 16
n - 20
n - 24
n - 28
n - 32
n - 36
Before Popping Registers
0
31
After Popping Registers
0
31
ESP
EAX
ECX
EDX
EBX
Ignored
EBP
ESI
EDI
ESP
Figure 7-4. Operation of the POPA Instruction
7.3.1.5
Stack Manipulation Instructions in 64-Bit Mode
In 64-bit mode, the stack pointer size is 64 bits and cannot be overridden by an instruction prefix. In implicit stack
references, address-size overrides are ignored. Pushes and pops of 32-bit values on the stack are not possible in
64-bit mode. 16-bit pushes and pops are supported by using the 66H operand-size prefix. PUSHA, PUSHAD, POPA,
and POPAD are not supported.
7.3.1.6
Type Conversion Instructions
The type conversion instructions convert bytes into words, words into doublewords, and doublewords into quadwords. These instructions are especially useful for converting integers to larger integer formats, because they
perform sign extension (see Figure 7-5).
Two kinds of type conversion instructions are provided: simple conversion and move and convert.
15
0
S N N N N N N N N N N N N N N N
31
15
Before Sign
Extension
0
S S S S S S S S S S S S S S S S S N N N N N N N N N N N N N N N
After Sign
Extension
Figure 7-5. Sign Extension
Simple conversion — The CBW (convert byte to word), CWDE (convert word to doubleword extended), CWD
(convert word to doubleword), and CDQ (convert doubleword to quadword) instructions perform sign extension to
double the size of the source operand.
The CBW instruction copies the sign (bit 7) of the byte in the AL register into every bit position of the upper byte of
the AX register. The CWDE instruction copies the sign (bit 15) of the word in the AX register into every bit position
of the high word of the EAX register.
The CWD instruction copies the sign (bit 15) of the word in the AX register into every bit position in the DX register.
The CDQ instruction copies the sign (bit 31) of the doubleword in the EAX register into every bit position in the EDX
register. The CWD instruction can be used to produce a doubleword dividend from a word before a word division,
and the CDQ instruction can be used to produce a quadword dividend from a doubleword before doubleword division.
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Move with sign or zero extension — The MOVSX (move with sign extension) and MOVZX (move with zero
extension) instructions move the source operand into a register then perform the sign extension.
The MOVSX instruction extends an 8-bit value to a 16-bit value or an 8-bit or 16-bit value to a 32-bit value by sign
extending the source operand, as shown in Figure 7-5. The MOVZX instruction extends an 8-bit value to a 16-bit
value or an 8-bit or 16-bit value to a 32-bit value by zero extending the source operand.
7.3.1.7
Type Conversion Instructions in 64-Bit Mode
The MOVSXD instruction operates on 64-bit data. It sign-extends a 32-bit value to 64 bits. This instruction is not
encodable in non-64-bit modes.
7.3.2
Binary Arithmetic Instructions
Binary arithmetic instructions operate on 8-, 16-, and 32-bit numeric data encoded as signed or unsigned binary
integers. The binary arithmetic instructions may also be used in algorithms that operate on decimal (BCD) values.
For the purpose of this discussion, these instructions are divided into subordinate subgroups of instructions that:
•
•
•
•
Add and subtract
Increment and decrement
Compare and change signs
Multiply and divide
7.3.2.1
Addition and Subtraction Instructions
The ADD (add integers), ADC (add integers with carry), SUB (subtract integers), and SBB (subtract integers with
borrow) instructions perform addition and subtraction operations on signed or unsigned integer operands.
The ADD instruction computes the sum of two integer operands.
The ADC instruction computes the sum of two integer operands, plus 1 if the CF flag is set. This instruction is used
to propagate a carry when adding numbers in stages.
The SUB instruction computes the difference of two integer operands.
The SBB instruction computes the difference of two integer operands, minus 1 if the CF flag is set. This instruction
is used to propagate a borrow when subtracting numbers in stages.
7.3.2.2
Increment and Decrement Instructions
The INC (increment) and DEC (decrement) instructions add 1 to or subtract 1 from an unsigned integer operand,
respectively. A primary use of these instructions is for implementing counters.
7.3.2.3
Increment and Decrement Instructions in 64-Bit Mode
The INC and DEC instructions are supported in 64-bit mode. However, some forms of INC and DEC (the register
operand being encoded using register extension field in the MOD R/M byte) are not encodable in 64-bit mode
because the opcodes are treated as REX prefixes.
7.3.2.4
Comparison and Sign Change Instructions
The CMP (compare) instruction computes the difference between two integer operands and updates the OF, SF, ZF,
AF, PF, and CF flags according to the result. The source operands are not modified, nor is the result saved. The CMP
instruction is commonly used in conjunction with a Jcc (jump) or SETcc (byte set on condition) instruction, with the
latter instructions performing an action based on the result of a CMP instruction.
The NEG (negate) instruction subtracts a signed integer operand from zero. The effect of the NEG instruction is to
change the sign of a two's complement operand while keeping its magnitude.
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7.3.2.5
Multiplication and Division Instructions
The processor provides two multiply instructions, MUL (unsigned multiply) and IMUL (signed multiply), and two
divide instructions, DIV (unsigned divide) and IDIV (signed divide).
The MUL instruction multiplies two unsigned integer operands. The result is computed to twice the size of the
source operands (for example, if word operands are being multiplied, the result is a doubleword).
The IMUL instruction multiplies two signed integer operands. The result is computed to twice the size of the source
operands; however, in some cases the result is truncated to the size of the source operands (see “IMUL—Signed
Multiply” in Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).
The DIV instruction divides one unsigned operand by another unsigned operand and returns a quotient and a
remainder.
The IDIV instruction is identical to the DIV instruction, except that IDIV performs a signed division.
7.3.3
Decimal Arithmetic Instructions
Decimal arithmetic can be performed by combining the binary arithmetic instructions ADD, SUB, MUL, and DIV
(discussed in Section 7.3.2, “Binary Arithmetic Instructions”) with the decimal arithmetic instructions. The decimal
arithmetic instructions are provided to carry out the following operations:
•
•
To adjust the results of a previous binary arithmetic operation to produce a valid BCD result.
To adjust the operands of a subsequent binary arithmetic operation so that the operation will produce a valid
BCD result.
These instructions operate on both packed and unpacked BCD values. For the purpose of this discussion, the
decimal arithmetic instructions are divided into subordinate subgroups of instructions that provide:
•
•
Packed BCD adjustments
Unpacked BCD adjustments
7.3.3.1
Packed BCD Adjustment Instructions
The DAA (decimal adjust after addition) and DAS (decimal adjust after subtraction) instructions adjust the results
of operations performed on packed BCD integers (see Section 4.7, “BCD and Packed BCD Integers”). Adding two
packed BCD values requires two instructions: an ADD instruction followed by a DAA instruction. The ADD instruction adds (binary addition) the two values and stores the result in the AL register. The DAA instruction then adjusts
the value in the AL register to obtain a valid, 2-digit, packed BCD value and sets the CF flag if a decimal carry
occurred as the result of the addition.
Likewise, subtracting one packed BCD value from another requires a SUB instruction followed by a DAS instruction.
The SUB instruction subtracts (binary subtraction) one BCD value from another and stores the result in the AL
register. The DAS instruction then adjusts the value in the AL register to obtain a valid, 2-digit, packed BCD value
and sets the CF flag if a decimal borrow occurred as the result of the subtraction.
7.3.3.2
Unpacked BCD Adjustment Instructions
The AAA (ASCII adjust after addition), AAS (ASCII adjust after subtraction), AAM (ASCII adjust after multiplication), and AAD (ASCII adjust before division) instructions adjust the results of arithmetic operations performed
on unpacked BCD values (see Section 4.7, “BCD and Packed BCD Integers”). All these instructions assume that
the value to be adjusted is stored in the AL register or, in one instance, the AL and AH registers.
The AAA instruction adjusts the contents of the AL register following the addition of two unpacked BCD values. It
converts the binary value in the AL register into a decimal value and stores the result in the AL register in unpacked
BCD format (the decimal number is stored in the lower 4 bits of the register and the upper 4 bits are cleared). If a
decimal carry occurred as a result of the addition, the CF flag is set and the contents of the AH register are incremented by 1.
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The AAS instruction adjusts the contents of the AL register following the subtraction of two unpacked BCD values.
Here again, a binary value is converted into an unpacked BCD value. If a borrow was required to complete the
decimal subtract, the CF flag is set and the contents of the AH register are decremented by 1.
The AAM instruction adjusts the contents of the AL register following a multiplication of two unpacked BCD values.
It converts the binary value in the AL register into a decimal value and stores the least significant digit of the result
in the AL register (in unpacked BCD format) and the most significant digit, if there is one, in the AH register (also
in unpacked BCD format).
The AAD instruction adjusts a two-digit BCD value so that when the value is divided with the DIV instruction, a valid
unpacked BCD result is obtained. The instruction converts the BCD value in registers AH (most significant digit) and
AL (least significant digit) into a binary value and stores the result in register AL. When the value in AL is divided by
an unpacked BCD value, the quotient and remainder will be automatically encoded in unpacked BCD format.
7.3.4
Decimal Arithmetic Instructions in 64-Bit Mode
Decimal arithmetic instructions are not supported in 64-bit mode, they are either invalid or not encodable.
7.3.5
Logical Instructions
The logical instructions AND, OR, XOR (exclusive or), and NOT perform the standard Boolean operations for which
they are named. The AND, OR, and XOR instructions require two operands; the NOT instruction operates on a
single operand.
7.3.6
Shift and Rotate Instructions
The shift and rotate instructions rearrange the bits within an operand. For the purpose of this discussion, these
instructions are further divided into subordinate subgroups of instructions that:
•
•
•
Shift bits
Double-shift bits (move them between operands)
Rotate bits
7.3.6.1
Shift Instructions
The SAL (shift arithmetic left), SHL (shift logical left), SAR (shift arithmetic right), SHR (shift logical right) instructions perform an arithmetic or logical shift of the bits in a byte, word, or doubleword.
The SAL and SHL instructions perform the same operation (see Figure 7-6). They shift the source operand left by
from 1 to 31 bit positions. Empty bit positions are cleared. The CF flag is loaded with the last bit shifted out of the
operand.
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Initial State
Operand
CF
X
1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1
After 1-bit SHL/SAL Instruction
0
1
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 0
After 10-bit SHL/SAL Instruction
0
0
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Figure 7-6. SHL/SAL Instruction Operation
The SHR instruction shifts the source operand right by from 1 to 31 bit positions (see Figure 7-7). As with the
SHL/SAL instruction, the empty bit positions are cleared and the CF flag is loaded with the last bit shifted out of the
operand.
Initial State
Operand
1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1
CF
X
After 1-bit SHR Instruction
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1
1
0
After 10-bit SHR Instruction
0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
0
0
Figure 7-7. SHR Instruction Operation
The SAR instruction shifts the source operand right by from 1 to 31 bit positions (see Figure 7-8). This instruction
differs from the SHR instruction in that it preserves the sign of the source operand by clearing empty bit positions
if the operand is positive or setting the empty bits if the operand is negative. Again, the CF flag is loaded with the
last bit shifted out of the operand.
The SAR and SHR instructions can also be used to perform division by powers of 2 (see “SAL/SAR/SHL/SHR—Shift
Instructions” in Chapter 4, “Instruction Set Reference, M-U,” of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B).
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Initial State (Positive Operand)
Operand
CF
X
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1
After 1-bit SAR Instruction
1
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1
Initial State (Negative Operand)
CF
X
1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1
After 1-bit SAR Instruction
1
1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1
Figure 7-8. SAR Instruction Operation
7.3.6.2
Double-Shift Instructions
The SHLD (shift left double) and SHRD (shift right double) instructions shift a specified number of bits from one
operand to another (see Figure 7-9). They are provided to facilitate operations on unaligned bit strings. They can
also be used to implement a variety of bit string move operations.
31
CF
SHLD Instruction
0
Destination (Memory or Register)
31
0
Source (Register)
31
SHRD Instruction
0
Source (Register)
31
0
Destination (Memory or Register)
CF
Figure 7-9. SHLD and SHRD Instruction Operations
The SHLD instruction shifts the bits in the destination operand to the left and fills the empty bit positions (in the
destination operand) with bits shifted out of the source operand. The destination and source operands must be the
same length (either words or doublewords). The shift count can range from 0 to 31 bits. The result of this shift
operation is stored in the destination operand, and the source operand is not modified. The CF flag is loaded with
the last bit shifted out of the destination operand.
The SHRD instruction operates the same as the SHLD instruction except bits are shifted to the right in the destination operand, with the empty bit positions filled with bits shifted out of the source operand.
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7.3.6.3
Rotate Instructions
The ROL (rotate left), ROR (rotate right), RCL (rotate through carry left) and RCR (rotate through carry right)
instructions rotate the bits in the destination operand out of one end and back through the other end (see
Figure 7-10). Unlike a shift, no bits are lost during a rotation. The rotate count can range from 0 to 31.
31
CF
ROL Instruction
0
Destination (Memory or Register)
31
ROR Instruction
0
Destination (Memory or Register)
31
CF
CF
RCL Instruction
0
Destination (Memory or Register)
31
RCR Instruction
0
Destination (Memory or Register)
CF
Figure 7-10. ROL, ROR, RCL, and RCR Instruction Operations
The ROL instruction rotates the bits in the operand to the left (toward more significant bit locations). The ROR
instruction rotates the operand right (toward less significant bit locations).
The RCL instruction rotates the bits in the operand to the left, through the CF flag. This instruction treats the CF flag
as a one-bit extension on the upper end of the operand. Each bit that exits from the most significant bit location of
the operand moves into the CF flag. At the same time, the bit in the CF flag enters the least significant bit location
of the operand.
The RCR instruction rotates the bits in the operand to the right through the CF flag.
For all the rotate instructions, the CF flag always contains the value of the last bit rotated out of the operand, even
if the instruction does not use the CF flag as an extension of the operand. The value of this flag can then be tested
by a conditional jump instruction (JC or JNC).
7.3.7
Bit and Byte Instructions
These instructions operate on bit or byte strings. For the purpose of this discussion, they are further divided into
subordinate subgroups that:
•
•
•
•
Test and modify a single bit
Scan a bit string
Set a byte given conditions
Test operands and report results
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7.3.7.1
Bit Test and Modify Instructions
The bit test and modify instructions (see Table 7-3) operate on a single bit, which can be in an operand. The location of the bit is specified as an offset from the least significant bit of the operand. When the processor identifies
the bit to be tested and modified, it first loads the CF flag with the current value of the bit. Then it assigns a new
value to the selected bit, as determined by the modify operation for the instruction.
Table 7-3. Bit Test and Modify Instructions
Instruction
Effect on CF Flag
Effect on Selected Bit
BT (Bit Test)
CF flag ← Selected Bit
No effect
BTS (Bit Test and Set)
CF flag ← Selected Bit
Selected Bit ← 1
BTR (Bit Test and Reset)
CF flag ← Selected Bit
Selected Bit ← 0
BTC (Bit Test and Complement)
CF flag ← Selected Bit
Selected Bit ← NOT (Selected Bit)
7.3.7.2
Bit Scan Instructions
The BSF (bit scan forward) and BSR (bit scan reverse) instructions scan a bit string in a source operand for a set bit
and store the bit index of the first set bit found in a destination register. The bit index is the offset from the least
significant bit (bit 0) in the bit string to the first set bit. The BSF instruction scans the source operand low-to-high
(from bit 0 of the source operand toward the most significant bit); the BSR instruction scans high-to-low (from the
most significant bit toward the least significant bit).
7.3.7.3
Byte Set on Condition Instructions
The SETcc (set byte on condition) instructions set a destination-operand byte to 0 or 1, depending on the state of
selected status flags (CF, OF, SF, ZF, and PF) in the EFLAGS register. The suffix (cc) added to the SET mnemonic
determines the condition being tested for.
For example, the SETO instruction tests for overflow. If the OF flag is set, the destination byte is set to 1; if OF is
clear, the destination byte is cleared to 0. Appendix B, “EFLAGS Condition Codes,” lists the conditions it is possible
to test for with this instruction.
7.3.7.4
Test Instruction
The TEST instruction performs a logical AND of two operands and sets the SF, ZF, and PF flags according to the
results. The flags can then be tested by the conditional jump or loop instructions or the SETcc instructions. The
TEST instruction differs from the AND instruction in that it does not alter either of the operands.
7.3.8
Control Transfer Instructions
The processor provides both conditional and unconditional control transfer instructions to direct the flow of
program execution. Conditional transfers are taken only for specified states of the status flags in the EFLAGS
register. Unconditional control transfers are always executed.
For the purpose of this discussion, these instructions are further divided into subordinate subgroups that process:
•
•
•
Unconditional transfers
Conditional transfers
Software interrupts
7.3.8.1
Unconditional Transfer Instructions
The JMP, CALL, RET, INT, and IRET instructions transfer program control to another location (destination address)
in the instruction stream. The destination can be within the same code segment (near transfer) or in a different
code segment (far transfer).
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Jump instruction — The JMP (jump) instruction unconditionally transfers program control to a destination
instruction. The transfer is one-way; that is, a return address is not saved. A destination operand specifies the
address (the instruction pointer) of the destination instruction. The address can be a relative address or an
absolute address.
A relative address is a displacement (offset) with respect to the address in the EIP register. The destination
address (a near pointer) is formed by adding the displacement to the address in the EIP register. The displacement
is specified with a signed integer, allowing jumps either forward or backward in the instruction stream.
An absolute address is a offset from address 0 of a segment. It can be specified in either of the following ways:
•
An address in a general-purpose register — This address is treated as a near pointer, which is copied into
the EIP register. Program execution then continues at the new address within the current code segment.
•
An address specified using the standard addressing modes of the processor — Here, the address can
be a near pointer or a far pointer. If the address is for a near pointer, the address is translated into an offset and
copied into the EIP register. If the address is for a far pointer, the address is translated into a segment selector
(which is copied into the CS register) and an offset (which is copied into the EIP register).
In protected mode, the JMP instruction also allows jumps to a call gate, a task gate, and a task-state segment.
Call and return instructions — The CALL (call procedure) and RET (return from procedure) instructions allow a
jump from one procedure (or subroutine) to another and a subsequent jump back (return) to the calling procedure.
The CALL instruction transfers program control from the current (or calling) procedure to another procedure (the
called procedure). To allow a subsequent return to the calling procedure, the CALL instruction saves the current
contents of the EIP register on the stack before jumping to the called procedure. The EIP register (prior to transferring program control) contains the address of the instruction following the CALL instruction. When this address
is pushed on the stack, it is referred to as the return instruction pointer or return address.
The address of the called procedure (the address of the first instruction in the procedure being jumped to) is specified in a CALL instruction the same way as it is in a JMP instruction (see “Jump instruction” on page 7-15). The
address can be specified as a relative address or an absolute address. If an absolute address is specified, it can be
either a near or a far pointer.
The RET instruction transfers program control from the procedure currently being executed (the called procedure)
back to the procedure that called it (the calling procedure). Transfer of control is accomplished by copying the
return instruction pointer from the stack into the EIP register. Program execution then continues with the instruction pointed to by the EIP register.
The RET instruction has an optional operand, the value of which is added to the contents of the ESP register as part
of the return operation. This operand allows the stack pointer to be incremented to remove parameters from the
stack that were pushed on the stack by the calling procedure.
See Section 6.3, “Calling Procedures Using CALL and RET,” for more information on the mechanics of making procedure calls with the CALL and RET instructions.
Return from interrupt instruction — When the processor services an interrupt, it performs an implicit call to an
interrupt-handling procedure. The IRET (return from interrupt) instruction returns program control from an interrupt handler to the interrupted procedure (that is, the procedure that was executing when the interrupt occurred).
The IRET instruction performs a similar operation to the RET instruction (see “Call and return instructions” on page
7-15) except that it also restores the EFLAGS register from the stack. The contents of the EFLAGS register are
automatically stored on the stack along with the return instruction pointer when the processor services an interrupt.
7.3.8.2
Conditional Transfer Instructions
The conditional transfer instructions execute jumps or loops that transfer program control to another instruction in
the instruction stream if specified conditions are met. The conditions for control transfer are specified with a set of
condition codes that define various states of the status flags (CF, ZF, OF, PF, and SF) in the EFLAGS register.
Conditional jump instructions — The Jcc (conditional) jump instructions transfer program control to a destination instruction if the conditions specified with the condition code (cc) associated with the instruction are satisfied
(see Table 7-4). If the condition is not satisfied, execution continues with the instruction following the Jcc instruction. As with the JMP instruction, the transfer is one-way; that is, a return address is not saved.
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Table 7-4. Conditional Jump Instructions
Instruction Mnemonic
Condition (Flag States)
Description
(CF or ZF) = 0
Above/not below or equal
Unsigned Conditional Jumps
JA/JNBE
JAE/JNB
CF = 0
Above or equal/not below
JB/JNAE
CF = 1
Below/not above or equal
JBE/JNA
(CF or ZF) = 1
Below or equal/not above
JC
CF = 1
Carry
JE/JZ
ZF = 1
Equal/zero
JNC
CF = 0
Not carry
JNE/JNZ
ZF = 0
Not equal/not zero
JNP/JPO
PF = 0
Not parity/parity odd
JP/JPE
PF = 1
Parity/parity even
JCXZ
CX = 0
Register CX is zero
JECXZ
ECX = 0
Register ECX is zero
JG/JNLE
((SF xor OF) or ZF) = 0
Greater/not less or equal
JGE/JNL
(SF xor OF) = 0
Greater or equal/not less
JL/JNGE
(SF xor OF) = 1
Less/not greater or equal
JLE/JNG
((SF xor OF) or ZF) = 1
Less or equal/not greater
JNO
OF = 0
Not overflow
JNS
SF = 0
Not sign (non-negative)
JO
OF = 1
Overflow
JS
SF = 1
Sign (negative)
Signed Conditional Jumps
The destination operand specifies a relative address (a signed offset with respect to the address in the EIP register)
that points to an instruction in the current code segment. The Jcc instructions do not support far transfers;
however, far transfers can be accomplished with a combination of a Jcc and a JMP instruction (see “Jcc—Jump if
Condition Is Met” in Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A).
Table 7-4 shows the mnemonics for the Jcc instructions and the conditions being tested for each instruction. The
condition code mnemonics are appended to the letter “J” to form the mnemonic for a Jcc instruction. The instructions are divided into two groups: unsigned and signed conditional jumps. These groups correspond to the results
of operations performed on unsigned and signed integers respectively. Those instructions listed as pairs (for
example, JA/JNBE) are alternate names for the same instruction. Assemblers provide alternate names to make it
easier to read program listings.
The JCXZ and JECXZ instructions test the CX and ECX registers, respectively, instead of one or more status flags.
See “Jump if zero instructions” on page 7-17 for more information about these instructions.
Loop instructions — The LOOP, LOOPE (loop while equal), LOOPZ (loop while zero), LOOPNE (loop while not
equal), and LOOPNZ (loop while not zero) instructions are conditional jump instructions that use the value of the
ECX register as a count for the number of times to execute a loop. All the loop instructions decrement the count in
the ECX register each time they are executed and terminate a loop when zero is reached. The LOOPE, LOOPZ,
LOOPNE, and LOOPNZ instructions also accept the ZF flag as a condition for terminating the loop before the count
reaches zero.
The LOOP instruction decrements the contents of the ECX register (or the CX register, if the address-size attribute
is 16), then tests the register for the loop-termination condition. If the count in the ECX register is non-zero,
program control is transferred to the instruction address specified by the destination operand. The destination
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operand is a relative address (that is, an offset relative to the contents of the EIP register), and it generally points
to the first instruction in the block of code that is to be executed in the loop. When the count in the ECX register
reaches zero, program control is transferred to the instruction immediately following the LOOP instruction,
which terminates the loop. If the count in the ECX register is zero when the LOOP instruction is first executed, the
register is pre-decremented to FFFFFFFFH, causing the loop to be executed 232 times.
The LOOPE and LOOPZ instructions perform the same operation (they are mnemonics for the same instruction).
These instructions operate the same as the LOOP instruction, except that they also test the ZF flag.
If the count in the ECX register is not zero and the ZF flag is set, program control is transferred to the destination
operand. When the count reaches zero or the ZF flag is clear, the loop is terminated by transferring program control
to the instruction immediately following the LOOPE/LOOPZ instruction.
The LOOPNE and LOOPNZ instructions (mnemonics for the same instruction) operate the same as the
LOOPE/LOOPZ instructions, except that they terminate the loop if the ZF flag is set.
Jump if zero instructions — The JECXZ (jump if ECX zero) instruction jumps to the location specified in the destination operand if the ECX register contains the value zero. This instruction can be used in combination with a loop
instruction (LOOP, LOOPE, LOOPZ, LOOPNE, or LOOPNZ) to test the ECX register prior to beginning a loop. As
described in “Loop instructions” on page 7-16, the loop instructions decrement the contents of the ECX register
before testing for zero. If the value in the ECX register is zero initially, it will be decremented to FFFFFFFFH on the
first loop instruction, causing the loop to be executed 232 times. To prevent this problem, a JECXZ instruction can
be inserted at the beginning of the code block for the loop, causing a jump out of the loop if the ECX register count
is initially zero. When used with repeated string scan and compare instructions, the JECXZ instruction can determine whether the loop terminated because the count reached zero or because the scan or compare conditions were
satisfied.
The JCXZ (jump if CX is zero) instruction operates the same as the JECXZ instruction when the 16-bit address-size
attribute is used. Here, the CX register is tested for zero.
7.3.8.3
Control Transfer Instructions in 64-Bit Mode
In 64-bit mode, the operand size for all near branches (CALL, RET, JCC, JCXZ, JMP, and LOOP) is forced to 64 bits.
The listed instructions update the 64-bit RIP without need for a REX operand-size prefix.
Near branches in the following operations are forced to 64-bits (regardless of operand size prefixes):
•
•
•
•
Truncation of the size of the instruction pointer
Size of a stack pop or push, due to CALL or RET
Size of a stack-pointer increment or decrement, due to CALL or RET
Indirect-branch operand size
Note that the displacement field for relative branches is still limited to 32 bits and the address size for near
branches is not forced.
Address size determines the register size (CX/ECX/RCX) used for JCXZ and LOOP. It also impacts the address
calculation for memory indirect branches. Addresses size is 64 bits by default, although it can be over-ridden to 32
bits (using a prefix).
7.3.8.4
Software Interrupt Instructions
The INT n (software interrupt), INTO (interrupt on overflow), and BOUND (detect value out of range) instructions
allow a program to explicitly raise a specified interrupt or exception, which in turn causes the handler routine for
the interrupt or exception to be called.
The INT n instruction can raise any of the processor’s interrupts or exceptions by encoding the vector of the interrupt or exception in the instruction. This instruction can be used to support software generated interrupts or to test
the operation of interrupt and exception handlers.
The IRET (return from interrupt) instruction returns program control from an interrupt handler to the interrupted
procedure. The IRET instruction performs a similar operation to the RET instruction.
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The CALL (call procedure) and RET (return from procedure) instructions allow a jump from one procedure to
another and a subsequent return to the calling procedure. EFLAGS register contents are automatically stored on
the stack along with the return instruction pointer when the processor services an interrupt.
The INTO instruction raises the overflow exception if the OF flag is set. If the flag is clear, execution continues
without raising the exception. This instruction allows software to access the overflow exception handler explicitly to
check for overflow conditions.
The BOUND instruction compares a signed value against upper and lower bounds, and raises the “BOUND range
exceeded” exception if the value is less than the lower bound or greater than the upper bound. This instruction is
useful for operations such as checking an array index to make sure it falls within the range defined for the array.
7.3.8.5
Software Interrupt Instructions in 64-bit Mode and Compatibility Mode
In 64-bit mode, the stack size is 8 bytes wide. IRET must pop 8-byte items off the stack. SS:RSP pops unconditionally. BOUND is not supported.
In compatibility mode, SS:RSP is popped only if the CPL changes.
7.3.9
String Operations
The GP instructions includes a set of string instructions that are designed to access large data structures; these
are introduced in Section 7.3.9.1. Section 7.3.9.2 describes how REP prefixes can be used with these instructions
to perform more complex repeated string operations. Certain processors optimize repeated string operations
with fast-string operation, as described in Section 7.3.9.3. Section 7.3.9.4 explains how string operations can be
used in 64-bit mode.
7.3.9.1
String Instructions
The MOVS (Move String), CMPS (Compare string), SCAS (Scan string), LODS (Load string), and STOS (Store
string) instructions permit large data structures, such as alphanumeric character strings, to be moved and examined in memory. These instructions operate on individual elements in a string, which can be a byte, word, or
doubleword. The string elements to be operated on are identified with the ESI (source string element) and EDI
(destination string element) registers. Both of these registers contain absolute addresses (offsets into a segment)
that point to a string element.
By default, the ESI register addresses the segment identified with the DS segment register. A segment-override
prefix allows the ESI register to be associated with the CS, SS, ES, FS, or GS segment register. The EDI register
addresses the segment identified with the ES segment register; no segment override is allowed for the EDI register.
The use of two different segment registers in the string instructions permits operations to be performed on strings
located in different segments. Or by associating the ESI register with the ES segment register, both the source and
destination strings can be located in the same segment. (This latter condition can also be achieved by loading the
DS and ES segment registers with the same segment selector and allowing the ESI register to default to the DS
register.)
The MOVS instruction moves the string element addressed by the ESI register to the location addressed by the EDI
register. The assembler recognizes three “short forms” of this instruction, which specify the size of the string to be
moved: MOVSB (move byte string), MOVSW (move word string), and MOVSD (move doubleword string).
The CMPS instruction subtracts the destination string element from the source string element and updates the
status flags (CF, ZF, OF, SF, PF, and AF) in the EFLAGS register according to the results. Neither string element is
written back to memory. The assembler recognizes three “short forms” of the CMPS instruction: CMPSB (compare
byte strings), CMPSW (compare word strings), and CMPSD (compare doubleword strings).
The SCAS instruction subtracts the destination string element from the contents of the EAX, AX, or AL register
(depending on operand length) and updates the status flags according to the results. The string element and
register contents are not modified. The following “short forms” of the SCAS instruction specify the operand length:
SCASB (scan byte string), SCASW (scan word string), and SCASD (scan doubleword string).
The LODS instruction loads the source string element identified by the ESI register into the EAX register (for a
doubleword string), the AX register (for a word string), or the AL register (for a byte string). The “short forms” for
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this instruction are LODSB (load byte string), LODSW (load word string), and LODSD (load doubleword string). This
instruction is usually used in a loop, where other instructions process each element of the string after they are
loaded into the target register.
The STOS instruction stores the source string element from the EAX (doubleword string), AX (word string), or AL
(byte string) register into the memory location identified with the EDI register. The “short forms” for this instruction
are STOSB (store byte string), STOSW (store word string), and STOSD (store doubleword string). This instruction
is also normally used in a loop. Here a string is commonly loaded into the register with a LODS instruction, operated on by other instructions, and then stored again in memory with a STOS instruction.
The I/O instructions (see Section 7.3.10, “I/O Instructions”) also perform operations on strings in memory.
7.3.9.2
Repeated String Operations
Each of the string instructions described in Section 7.3.9.1 perform one iteration of a string operation. To operate
on strings longer than a doubleword, the string instructions can be combined with a repeat prefix (REP) to create a
repeating instruction or be placed in a loop.
When used in string instructions, the ESI and EDI registers are automatically incremented or decremented after
each iteration of an instruction to point to the next element (byte, word, or doubleword) in the string. String operations can thus begin at higher addresses and work toward lower ones, or they can begin at lower addresses and
work toward higher ones. The DF flag in the EFLAGS register controls whether the registers are incremented (DF =
0) or decremented (DF = 1). The STD and CLD instructions set and clear this flag, respectively.
The following repeat prefixes can be used in conjunction with a count in the ECX register to cause a string instruction to repeat:
•
•
•
REP — Repeat while the ECX register not zero.
REPE/REPZ — Repeat while the ECX register not zero and the ZF flag is set.
REPNE/REPNZ — Repeat while the ECX register not zero and the ZF flag is clear.
When a string instruction has a repeat prefix, the operation executes until one of the termination conditions specified by the prefix is satisfied. The REPE/REPZ and REPNE/REPNZ prefixes are used only with the CMPS and SCAS
instructions. Also, note that a REP STOS instruction is the fastest way to initialize a large block of memory.
7.3.9.3
Fast-String Operation
To improve performance, more recent processors support modifications to the processor’s operation during the
string store operations initiated with the MOVS, MOVSB, STOS, and STOSB instructions. This optimized operation,
called fast-string operation, is used when the execution of one of those instructions meets certain initial conditions (see below). Instructions using fast-string operation effectively operate on the string in groups that may
include multiple elements of the native data size (byte, word, doubleword, or quadword). With fast-string operation, the processor recognizes interrupts and data breakpoints only on boundaries between these groups. Faststring operation is used only if the source and destination addresses both use either the WB or WC memory types.
The initial conditions for fast-string operation are implementation-specific and may vary with the native string size.
Examples of parameters that may impact the use of fast-string operation include the following:
•
•
•
•
the alignment indicated in the EDI and ESI alignment registers;
the address order of the string operation;
the value of the initial operation counter (ECX); and
the difference between the source and destination addresses.
NOTE
Initial conditions for fast-string operation in future Intel 64 or IA-32 processor families may differ
from above. The Intel® 64 and IA-32 Architectures Optimization Reference Manual may contain
model-specific information.
Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE
MSR. However, Intel recommends that system software always enable fast-string operation.
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When fast-string operation is enabled (because IA32_MISC_ENABLE[0] = 1), some processors may further
enhance the operation of the REP MOVSB and REP STOSB instructions. A processor supports these enhancements
if CPUID.(EAX=07H, ECX=0H):EBX[bit 9] is 1. The Intel® 64 and IA-32 Architectures Optimization Reference
Manual may include model-specific recommendations for use of these enhancements.
The stores produced by fast-string operation may appear to execute out of order. Software dependent upon
sequential store ordering should not use string operations for the entire data structure to be stored. Data and
semaphores should be separated. Order-dependent code should write to a discrete semaphore variable after any
string operations to allow correctly ordered data to be seen by all processors. Atomicity of load and store operations
is guaranteed only for native data elements of the string with native data size, and only if they are included in a
single cache line. See Section 8.2.4, “Fast-String Operation and Out-of-Order Stores” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
7.3.9.4
String Operations in 64-Bit Mode
The behavior of MOVS (Move String), CMPS (Compare string), SCAS (Scan string), LODS (Load string), and STOS
(Store string) instructions in 64-bit mode is similar to their behavior in non-64-bit modes, with the following differences:
•
•
The source operand is specified by RSI or DS:ESI, depending on the address size attribute of the operation.
•
Operation on 64-bit data is supported by using the REX.W prefix.
The destination operand is specified by RDI or DS:EDI, depending on the address size attribute of the
operation.
When using REP prefixes for string operations in 64-bit mode, the repeat count is specified by RCX or ECX
(depending on the address size attribute of the operation). The default address size is 64 bits.
7.3.10
I/O Instructions
The IN (input from port to register), INS (input from port to string), OUT (output from register to port), and OUTS
(output string to port) instructions move data between the processor’s I/O ports and either a register or memory.
The register I/O instructions (IN and OUT) move data between an I/O port and the EAX register (32-bit I/O), the
AX register (16-bit I/O), or the AL (8-bit I/O) register. The I/O port being read or written to is specified with an
immediate operand or an address in the DX register.
The block I/O instructions (INS and OUTS) instructions move blocks of data (strings) between an I/O port and
memory. These instructions operate similar to the string instructions (see Section 7.3.9, “String Operations”). The
ESI and EDI registers are used to specify string elements in memory and the repeat prefix (REP) is used to repeat
the instructions to implement block moves. The assembler recognizes the following alternate mnemonics for these
instructions: INSB (input byte), INSW (input word), and INSD (input doubleword), and OUTSB (output byte),
OUTSW (output word), and OUTSD (output doubleword).
The INS and OUTS instructions use an address in the DX register to specify the I/O port to be read or written to.
7.3.11
I/O Instructions in 64-Bit Mode
For I/O instructions to and from memory, the differences in 64-bit mode are:
•
•
The source operand is specified by RSI or DS:ESI, depending on the address size attribute of the operation.
•
Operation on 64-bit data is not encodable and REX prefixes are silently ignored.
The destination operand is specified by RDI or DS:EDI, depending on the address size attribute of the
operation.
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7.3.12
Enter and Leave Instructions
The ENTER and LEAVE instructions provide machine-language support for procedure calls in block-structured
languages, such as C and Pascal. These instructions and the call and return mechanism that they support are
described in detail in Section 6.5, “Procedure Calls for Block-Structured Languages”.
7.3.13
Flag Control (EFLAG) Instructions
The Flag Control (EFLAG) instructions allow the state of selected flags in the EFLAGS register to be read or modified. For the purpose of this discussion, these instructions are further divided into subordinate subgroups of
instructions that manipulate:
•
•
•
Carry and direction flags
The EFLAGS register
Interrupt flags
7.3.13.1
Carry and Direction Flag Instructions
The STC (set carry flag), CLC (clear carry flag), and CMC (complement carry flag) instructions allow the CF flag in
the EFLAGS register to be modified directly. They are typically used to initialize the CF flag to a known state before
an instruction that uses the flag in an operation is executed. They are also used in conjunction with the rotate-withcarry instructions (RCL and RCR).
The STD (set direction flag) and CLD (clear direction flag) instructions allow the DF flag in the EFLAGS register to
be modified directly. The DF flag determines the direction in which index registers ESI and EDI are stepped when
executing string processing instructions. If the DF flag is clear, the index registers are incremented after each iteration of a string instruction; if the DF flag is set, the registers are decremented.
7.3.13.2
EFLAGS Transfer Instructions
The EFLAGS transfer instructions allow groups of flags in the EFLAGS register to be copied to a register or memory
or be loaded from a register or memory.
The LAHF (load AH from flags) and SAHF (store AH into flags) instructions operate on five of the EFLAGS status
flags (SF, ZF, AF, PF, and CF). The LAHF instruction copies the status flags to bits 7, 6, 4, 2, and 0 of the AH register,
respectively. The contents of the remaining bits in the register (bits 5, 3, and 1) are unaffected, and the contents
of the EFLAGS register remain unchanged. The SAHF instruction copies bits 7, 6, 4, 2, and 0 from the AH register
into the SF, ZF, AF, PF, and CF flags, respectively in the EFLAGS register.
The PUSHF (push flags), PUSHFD (push flags double), POPF (pop flags), and POPFD (pop flags double) instructions
copy the flags in the EFLAGS register to and from the stack. The PUSHF instruction pushes the lower word of the
EFLAGS register onto the stack (see Figure 7-11). The PUSHFD instruction pushes the entire EFLAGS register onto
the stack (with the RF and VM flags read as clear).
PUSHFD/POPFD
PUSHF/POPF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V V
I I I A V R 0 N
0 0 0 0 0 0 0 0 0 0
T
C M F
D
P F
I
O
P
L
O D I T S Z
P
C
A
F F F F F F 0 F 0 F 1 F
Figure 7-11. Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD Instructions
The POPF instruction pops a word from the stack into the EFLAGS register. Only bits 11, 10, 8, 7, 6, 4, 2, and 0 of
the EFLAGS register are affected with all uses of this instruction. If the current privilege level (CPL) of the current
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code segment is 0 (most privileged), the IOPL bits (bits 13 and 12) also are affected. If the I/O privilege level
(IOPL) is greater than or equal to the CPL, numerically, the IF flag (bit 9) also is affected.
The POPFD instruction pops a doubleword into the EFLAGS register. This instruction can change the state of the AC
bit (bit 18) and the ID bit (bit 21), as well as the bits affected by a POPF instruction. The restrictions for changing
the IOPL bits and the IF flag that were given for the POPF instruction also apply to the POPFD instruction.
7.3.13.3
Interrupt Flag Instructions
The STI (set interrupt flag) and CLI (clear interrupt flag) instructions allow the interrupt IF flag in the EFLAGS
register to be modified directly. The IF flag controls the servicing of hardware-generated interrupts (those received
at the processor’s INTR pin). If the IF flag is set, the processor services hardware interrupts; if the IF flag is clear,
hardware interrupts are masked.
The ability to execute these instructions depends on the operating mode of the processor and the current privilege
level (CPL) of the program or task attempting to execute these instructions.
7.3.14
Flag Control (RFLAG) Instructions in 64-Bit Mode
In 64-bit mode, the LAHF and SAHF instructions are supported if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.
PUSHF and POPF behave the same in 64-bit mode as in non-64-bit mode. PUSHFD always pushes 64-bit RFLAGS
onto the stack (with the RF and VM flags read as clear). POPFD always pops a 64-bit value from the top of the stack
and loads the lower 32 bits into RFLAGS. It then zero extends the upper bits of RFLAGS.
7.3.15
Segment Register Instructions
The processor provides a variety of instructions that address the segment registers of the processor directly. These
instructions are only used when an operating system or executive is using the segmented or the real-address mode
memory model.
For the purpose of this discussion, these instructions are divided into subordinate subgroups of instructions that
allow:
•
•
•
•
Segment-register load and store
Far control transfers
Software interrupt calls
Handling of far pointers
7.3.15.1
Segment-Register Load and Store Instructions
The MOV instruction (introduced in Section 7.3.1.1, “General Data Movement Instructions”) and the PUSH and POP
instructions (introduced in Section 7.3.1.4, “Stack Manipulation Instructions”) can transfer 16-bit segment selectors to and from segment registers (DS, ES, FS, GS, and SS). The transfers are always made to or from a segment
register and a general-purpose register or memory. Transfers between segment registers are not supported.
The POP and MOV instructions cannot place a value in the CS register. Only the far control-transfer versions of the
JMP, CALL, and RET instructions (see Section 7.3.15.2, “Far Control Transfer Instructions”) affect the CS register
directly.
7.3.15.2
Far Control Transfer Instructions
The JMP and CALL instructions (see Section 7.3.8, “Control Transfer Instructions”) both accept a far pointer as a
destination to transfer program control to a segment other than the segment currently being pointed to by the CS
register. When a far call is made with the CALL instruction, the current values of the EIP and CS registers are both
pushed on the stack.
The RET instruction (see “Call and return instructions” on page 7-15) can be used to execute a far return. Here,
program control is transferred from a code segment that contains a called procedure back to the code segment that
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contained the calling procedure. The RET instruction restores the values of the CS and EIP registers for the calling
procedure from the stack.
7.3.15.3
Software Interrupt Instructions
The software interrupt instructions INT, INTO, and IRET (see Section 7.3.8.4, “Software Interrupt Instructions”)
can also call and return from interrupt and exception handler procedures that are located in a code segment other
than the current code segment. With these instructions, however, the switching of code segments is handled transparently from the application program.
7.3.15.4
Load Far Pointer Instructions
The load far pointer instructions LDS (load far pointer using DS), LES (load far pointer using ES), LFS (load far
pointer using FS), LGS (load far pointer using GS), and LSS (load far pointer using SS) load a far pointer from
memory into a segment register and a general-purpose general register. The segment selector part of the far
pointer is loaded into the selected segment register and the offset is loaded into the selected general-purpose
register.
7.3.16
Miscellaneous Instructions
The following instructions perform operations that are of interest to applications programmers. For the purpose of
this discussion, these instructions are further divided into subordinate subgroups of instructions that provide for:
•
•
•
•
Address computations
Table lookup
Processor identification
NOP and undefined instruction entry
7.3.16.1
Address Computation Instruction
The LEA (load effective address) instruction computes the effective address in memory (offset within a segment)
of a source operand and places it in a general-purpose register. This instruction can interpret any of the processor’s
addressing modes and can perform any indexing or scaling that may be needed. It is especially useful for initializing the ESI or EDI registers before the execution of string instructions or for initializing the EBX register before an
XLAT instruction.
7.3.16.2
Table Lookup Instructions
The XLAT and XLATB (table lookup) instructions replace the contents of the AL register with a byte read from a
translation table in memory. The initial value in the AL register is interpreted as an unsigned index into the translation table. This index is added to the contents of the EBX register (which contains the base address of the table)
to calculate the address of the table entry. These instructions are used for applications such as converting character
codes from one alphabet into another (for example, an ASCII code could be used to look up its EBCDIC equivalent
in a table).
7.3.16.3
Processor Identification Instruction
The CPUID (processor identification) instruction returns information about the processor on which the instruction
is executed.
7.3.16.4
No-Operation and Undefined Instructions
The NOP (no operation) instruction increments the EIP register to point at the next instruction, but affects nothing
else.
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The UD2 (undefined) instruction generates an invalid opcode exception. Intel reserves the opcode for this instruction for this function. The instruction is provided to allow software to test an invalid opcode exception handler.
7.3.17
Random Number Generator Instructions
The instructions for generating random numbers to comply with NIST SP800-90A, SP800-90B, and SP800-90C
standards are described in this section.
7.3.17.1
RDRAND
The RDRAND instruction returns a random number. All Intel processors that support the RDRAND instruction indicate the availability of the RDRAND instruction via reporting CPUID.01H:ECX.RDRAND[bit 30] = 1.
RDRAND returns random numbers that are supplied by a cryptographically secure, deterministic random bit generator DRBG. The DRBG is designed to meet the NIST SP 800-90A standard. The DRBG is re-seeded frequently from
an on-chip non-deterministic entropy source to guarantee data returned by RDRAND is statistically uniform, nonperiodic and non-deterministic.
In order for the hardware design to meet its security goals, the random number generator continuously tests itself
and the random data it is generating. Runtime failures in the random number generator circuitry or statistically
anomalous data occurring by chance will be detected by the self test hardware and flag the resulting data as being
bad. In such extremely rare cases, the RDRAND instruction will return no data instead of bad data.
Under heavy load, with multiple cores executing RDRAND in parallel, it is possible, though unlikely, for the demand
of random numbers by software processes/threads to exceed the rate at which the random number generator
hardware can supply them. This will lead to the RDRAND instruction returning no data transitorily. The RDRAND
instruction indicates the occurrence of this rare situation by clearing the CF flag.
The RDRAND instruction returns with the carry flag set (CF = 1) to indicate valid data is returned. It is recommended that software using the RDRAND instruction to get random numbers retry for a limited number of iterations while RDRAND returns CF=0 and complete when valid data is returned, indicated with CF=1. This will deal
with transitory underflows. A retry limit should be employed to prevent a hard failure in the RNG (expected to be
extremely rare) leading to a busy loop in software.
The intrinsic primitive for RDRAND is defined to address software’s need for the common cases (CF = 1) and the
rare situations (CF = 0). The intrinsic primitive returns a value that reflects the value of the carry flag returned by
the underlying RDRAND instruction. The example below illustrates the recommended usage of an RDRAND intrinsic
in a utility function, a loop to fetch a 64 bit random value with a retry count limit of 10. A C implementation might
be written as follows:
---------------------------------------------------------------------------------------#define SUCCESS 1
#define RETRY_LIMIT_EXCEEDED 0
#define RETRY_LIMIT 10
int get_random_64( unsigned __int 64 * arand)
{int i ;
for ( i = 0; i < RETRY_LIMIT; i ++) {
if(_rdrand64_step(arand) ) return SUCCESS;
}
return RETRY_LIMIT_EXCEEDED;
}
-------------------------------------------------------------------------------
7.3.17.2
RDSEED
The RDSEED instruction returns a random number. All Intel processors that support the RDSEED instruction indicate the availability of the RDSEED instruction via reporting CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 1.
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PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
RDSEED returns random numbers that are supplied by a cryptographically secure, enhanced non-deterministic
random bit generator (Enhanced NRBG). The NRBG is designed to meet the NIST SP 800-90B and NIST SP800-90C
standards.
In order for the hardware design to meet its security goals, the random number generator continuously tests itself
and the random data it is generating. Runtime failures in the random number generator circuitry or statistically
anomalous data occurring by chance will be detected by the self test hardware and flag the resulting data as being
bad. In such extremely rare cases, the RDSEED instruction will return no data instead of bad data.
Under heavy load, with multiple cores executing RDSEED in parallel, it is possible for the demand of random
numbers by software processes/threads to exceed the rate at which the random number generator hardware can
supply them. This will lead to the RDSEED instruction returning no data transitorily. The RDSEED instruction indicates the occurrence of this situation by clearing the CF flag.
The RDSEED instruction returns with the carry flag set (CF = 1) to indicate valid data is returned. It is recommended that software using the RDSEED instruction to get random numbers retry for a limited number of iterations
while RDSEED returns CF=0 and complete when valid data is returned, indicated with CF=1. This will deal with
transitory underflows. A retry limit should be employed to prevent a hard failure in the NRBG (expected to be
extremely rare) leading to a busy loop in software.
The intrinsic primitive for RDSEED is defined to address software’s need for the common cases (CF = 1) and the
rare situations (CF = 0). The intrinsic primitive returns a value that reflects the value of the carry flag returned by
the underlying RDSEED instruction.
Vol. 1 7-25
PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7-26 Vol. 1
CHAPTER 8
PROGRAMMING WITH THE X87 FPU
The x87 Floating-Point Unit (FPU) provides high-performance floating-point processing capabilities for use in
graphics processing, scientific, engineering, and business applications. It supports the floating-point, integer, and
packed BCD integer data types and the floating-point processing algorithms and exception handling architecture
defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic.
This chapter describes the x87 FPU’s execution environment and instruction set. It also provides exception
handling information that is specific to the x87 FPU. Refer to the following chapters or sections of chapters for additional information about x87 FPU instructions and floating-point operations:
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, provide detailed descriptions of x87 FPU instructions.
•
Section 4.2.2, “Floating-Point Data Types,” Section 4.2.1.2, “Signed Integers,” and Section 4.7, “BCD and
Packed BCD Integers,” describe the floating-point, integer, and BCD data types.
•
Section 4.9, “Overview of Floating-Point Exceptions,” Section 4.9.1, “Floating-Point Exception Conditions,” and
Section 4.9.2, “Floating-Point Exception Priority,” give an overview of the floating-point exceptions that the x87
FPU can detect and report.
8.1
X87 FPU EXECUTION ENVIRONMENT
The x87 FPU represents a separate execution environment within the IA-32 architecture (see Figure 8-1). This
execution environment consists of eight data registers (called the x87 FPU data registers) and the following
special-purpose registers:
•
•
•
•
•
•
Status register
Control register
Tag word register
Last instruction pointer register
Last data (operand) pointer register
Opcode register
These registers are described in the following sections.
The x87 FPU executes instructions from the processor’s normal instruction stream. The state of the x87 FPU is independent from the state of the basic execution environment and from the state of SSE/SSE2/SSE3 extensions.
However, the x87 FPU and Intel MMX technology share state because the MMX registers are aliased to the x87 FPU
data registers. Therefore, when writing code that uses x87 FPU and MMX instructions, the programmer must
explicitly manage the x87 FPU and MMX state (see Section 9.5, “Compatibility with x87 FPU Architecture”).
8.1.1
x87 FPU in 64-Bit Mode and Compatibility Mode
In compatibility mode and 64-bit mode, x87 FPU instructions function like they do in protected mode. Memory
operands are specified using the ModR/M, SIB encoding that is described in Section 3.7.5, “Specifying an Offset.”
8.1.2
x87 FPU Data Registers
The x87 FPU data registers (shown in Figure 8-1) consist of eight 80-bit registers. Values are stored in these registers in the double extended-precision floating-point format shown in Figure 4-3. When floating-point, integer, or
packed BCD integer values are loaded from memory into any of the x87 FPU data registers, the values are automatically converted into double extended-precision floating-point format (if they are not already in that format).
When computation results are subsequently transferred back into memory from any of the x87 FPU registers, the
Vol. 1 8-1
PROGRAMMING WITH THE X87 FPU
results can be left in the double extended-precision floating-point format or converted back into a shorter floatingpoint format, an integer format, or the packed BCD integer format. (See Section 8.2, “x87 FPU Data Types,” for a
description of the data types operated on by the x87 FPU.)
Data Registers
Sign
79 78
0
64 63
Exponent
R7
Significand
R6
R5
R4
R3
R2
R1
R0
0
15
Control
Register
Status
Register
47
0
Last Instruction Pointer (FCS:FIP)
Last Data (Operand) Pointer (FDS:FDP)
10
Tag
Register
0
Opcode
Figure 8-1. x87 FPU Execution Environment
The x87 FPU instructions treat the eight x87 FPU data registers as a register stack (see Figure 8-2). All addressing of
the data registers is relative to the register on the top of the stack. The register number of the current top-of-stack
register is stored in the TOP (stack TOP) field in the x87 FPU status word. Load operations decrement TOP by one
and load a value into the new top-of-stack register, and store operations store the value from the current TOP
register in memory and then increment TOP by one. (For the x87 FPU, a load operation is equivalent to a push and
a store operation is equivalent to a pop.) Note that load and store operations are also available that do not push and
pop the stack.
FPU Data Register Stack
7
6
Growth
Stack 5
4
ST(1)
Top
3
ST(0)
011B
ST(2)
2
1
0
Figure 8-2. x87 FPU Data Register Stack
If a load operation is performed when TOP is at 0, register wraparound occurs and the new value of TOP is set to 7.
The floating-point stack-overflow exception indicates when wraparound might cause an unsaved value to be overwritten (see Section 8.5.1.1, “Stack Overflow or Underflow Exception (#IS)”).
Many floating-point instructions have several addressing modes that permit the programmer to implicitly operate
on the top of the stack, or to explicitly operate on specific registers relative to the TOP. Assemblers support these
8-2 Vol. 1
PROGRAMMING WITH THE X87 FPU
register addressing modes, using the expression ST(0), or simply ST, to represent the current stack top and ST(i)
to specify the ith register from TOP in the stack (0 ≤ i ≤ 7). For example, if TOP contains 011B (register 3 is the top
of the stack), the following instruction would add the contents of two registers in the stack (registers 3 and 5):
FADD ST, ST(2);
Figure 8-3 shows an example of how the stack structure of the x87 FPU registers and instructions are typically used
to perform a series of computations. Here, a two-dimensional dot product is computed, as follows:
1. The first instruction (FLD value1) decrements the stack register pointer (TOP) and loads the value 5.6 from
memory into ST(0). The result of this operation is shown in snap-shot (a).
2. The second instruction multiplies the value in ST(0) by the value 2.4 from memory and stores the result in
ST(0), shown in snap-shot (b).
3. The third instruction decrements TOP and loads the value 3.8 in ST(0).
4. The fourth instruction multiplies the value in ST(0) by the value 10.3 from memory and stores the result in
ST(0), shown in snap-shot (c).
5. The fifth instruction adds the value and the value in ST(1) and stores the result in ST(0), shown in snap-shot
(d).
Computation
Dot Product = (5.6 x 2.4) + (3.8 x 10.3)
Code:
FLD value1
FMUL value2
FLD value3
FMUL value4
FADD ST(1)
(a)
;(a) value1 = 5.6
;(b) value2 = 2.4
; value3 = 3.8
;(c)value4 = 10.3
;(d)
(c)
(b)
(d)
R7
R7
R7
R7
R6
R6
R6
R6
R5
R5
R5
R5
R4
5.6
ST(0)
R4
13.44
ST(0) R4
13.44
ST(1)
R4
13.44
ST(1)
39.14
ST(0)
R3
52.58
ST(0)
R3
R3
R3
R2
R2
R2
R2
R1
R1
R1
R1
R0
R0
R0
R0
Figure 8-3. Example x87 FPU Dot Product Computation
The style of programming demonstrated in this example is supported by the floating-point instruction set. In cases
where the stack structure causes computation bottlenecks, the FXCH (exchange x87 FPU register contents)
instruction can be used to streamline a computation.
8.1.2.1
Parameter Passing With the x87 FPU Register Stack
Like the general-purpose registers, the contents of the x87 FPU data registers are unaffected by procedure calls, or
in other words, the values are maintained across procedure boundaries. A calling procedure can thus use the x87
FPU data registers (as well as the procedure stack) for passing parameter between procedures. The called procedure can reference parameters passed through the register stack using the current stack register pointer (TOP)
and the ST(0) and ST(i) nomenclature. It is also common practice for a called procedure to leave a return value or
result in register ST(0) when returning execution to the calling procedure or program.
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PROGRAMMING WITH THE X87 FPU
When mixing MMX and x87 FPU instructions in the procedures or code sequences, the programmer is responsible
for maintaining the integrity of parameters being passed in the x87 FPU data registers. If an MMX instruction is
executed before the parameters in the x87 FPU data registers have been passed to another procedure, the parameters may be lost (see Section 9.5, “Compatibility with x87 FPU Architecture”).
8.1.3
x87 FPU Status Register
The 16-bit x87 FPU status register (see Figure 8-4) indicates the current state of the x87 FPU. The flags in the x87
FPU status register include the FPU busy flag, top-of-stack (TOP) pointer, condition code flags, error summary
status flag, stack fault flag, and exception flags. The x87 FPU sets the flags in this register to show the results of
operations.
FPU Busy
Top of Stack Pointer
15 14 13
C
B
3
11 10 9 8 7 6 5 4 3 2 1 0
TOP
C C C E S P U O Z D I
2 1 0 S F E E E E E E
Condition
Code
Error Summary Status
Stack Fault
Exception Flags
Precision
Underflow
Overflow
Zero Divide
Denormalized Operand
Invalid Operation
Figure 8-4. x87 FPU Status Word
The contents of the x87 FPU status register (referred to as the x87 FPU status word) can be stored in memory using
the FSTSW/FNSTSW, FSTENV/FNSTENV, FSAVE/FNSAVE, and FXSAVE instructions. It can also be stored in the AX
register of the integer unit, using the FSTSW/FNSTSW instructions.
8.1.3.1
Top of Stack (TOP) Pointer
A pointer to the x87 FPU data register that is currently at the top of the x87 FPU register stack is contained in bits
11 through 13 of the x87 FPU status word. This pointer, which is commonly referred to as TOP (for top-of-stack),
is a binary value from 0 to 7. See Section 8.1.2, “x87 FPU Data Registers,” for more information about the TOP
pointer.
8.1.3.2
Condition Code Flags
The four condition code flags (C0 through C3) indicate the results of floating-point comparison and arithmetic operations. Table 8-1 summarizes the manner in which the floating-point instructions set the condition code flags.
These condition code bits are used principally for conditional branching and for storage of information used in
exception handling (see Section 8.1.4, “Branching and Conditional Moves on Condition Codes”).
As shown in Table 8-1, the C1 condition code flag is used for a variety of functions. When both the IE and SF flags
in the x87 FPU status word are set, indicating a stack overflow or underflow exception (#IS), the C1 flag distinguishes between overflow (C1 = 1) and underflow (C1 = 0). When the PE flag in the status word is set, indicating
an inexact (rounded) result, the C1 flag is set to 1 if the last rounding by the instruction was upward. The FXAM
instruction sets C1 to the sign of the value being examined.
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PROGRAMMING WITH THE X87 FPU
The C2 condition code flag is used by the FPREM and FPREM1 instructions to indicate an incomplete reduction (or
partial remainder). When a successful reduction has been completed, the C0, C3, and C1 condition code flags are
set to the three least-significant bits of the quotient (Q2, Q1, and Q0, respectively). See “FPREM1—Partial
Remainder” in Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A, for more information on how these instructions use the condition code flags.
The FPTAN, FSIN, FCOS, and FSINCOS instructions set the C2 flag to 1 to indicate that the source operand is
beyond the allowable range of ±263 and clear the C2 flag if the source operand is within the allowable range.
Where the state of the condition code flags are listed as undefined in Table 8-1, do not rely on any specific value in
these flags.
8.1.3.3
x87 FPU Floating-Point Exception Flags
The six x87 FPU floating-point exception flags (bits 0 through 5) of the x87 FPU status word indicate that one or
more floating-point exceptions have been detected since the bits were last cleared. The individual exception flags
(IE, DE, ZE, OE, UE, and PE) are described in detail in Section 8.4, “x87 FPU Floating-Point Exception Handling.”
Each of the exception flags can be masked by an exception mask bit in the x87 FPU control word (see Section 8.1.5,
“x87 FPU Control Word”). The exception summary status flag (ES, bit 7) is set when any of the unmasked exception
flags are set. When the ES flag is set, the x87 FPU exception handler is invoked, using one of the techniques
described in Section 8.7, “Handling x87 FPU Exceptions in Software.” (Note that if an exception flag is masked, the
x87 FPU will still set the appropriate flag if the associated exception occurs, but it will not set the ES flag.)
The exception flags are “sticky” bits (once set, they remain set until explicitly cleared). They can be cleared by
executing the FCLEX/FNCLEX (clear exceptions) instructions, by reinitializing the x87 FPU with the FINIT/FNINIT or
FSAVE/FNSAVE instructions, or by overwriting the flags with an FRSTOR or FLDENV instruction.
The B-bit (bit 15) is included for 8087 compatibility only. It reflects the contents of the ES flag.
Table 8-1. Condition Code Interpretation
Instruction
FCOM, FCOMP, FCOMPP, FICOM, FICOMP, FTST,
FUCOM, FUCOMP, FUCOMPP
C0
Result of Comparison
FCOMI, FCOMIP, FUCOMI, FUCOMIP
FXAM
FPREM, FPREM1
C3
C2
Operands
are not
Comparable
C1
0 or #IS
Undefined. (These instructions set the
status flags in the EFLAGS register.)
#IS
Operand class
Sign
Q2
Q1
0 = reduction
complete
Q0 or #IS
1 = reduction
incomplete
F2XM1, FADD, FADDP, FBSTP, FCMOVcc,
FIADD, FDIV, FDIVP, FDIVR, FDIVRP, FIDIV,
FIDIVR, FIMUL, FIST, FISTP, FISUB,
FISUBR,FMUL, FMULP, FPATAN, FRNDINT,
FSCALE, FST, FSTP, FSUB, FSUBP, FSUBR,
FSUBRP,FSQRT, FYL2X, FYL2XP1
FCOS, FSIN, FSINCOS, FPTAN
FABS, FBLD, FCHS, FDECSTP, FILD, FINCSTP,
FLD, Load Constants, FSTP (ext. prec.), FXCH,
FXTRACT
Undefined
Undefined
Undefined
Roundup or #IS
0 = source
operand within
range
1 = source
operand out of
range
Roundup or #IS
(Undefined if C2 =
1)
0 or #IS
Vol. 1 8-5
PROGRAMMING WITH THE X87 FPU
Table 8-1. Condition Code Interpretation (Contd.)
FLDENV, FRSTOR
Each bit loaded from memory
FFREE, FLDCW, FCLEX/FNCLEX, FNOP,
FSTCW/FNSTCW, FSTENV/FNSTENV,
FSTSW/FNSTSW,
Undefined
FINIT/FNINIT, FSAVE/FNSAVE
8.1.3.4
0
0
0
0
Stack Fault Flag
The stack fault flag (bit 6 of the x87 FPU status word) indicates that stack overflow or stack underflow has occurred
with data in the x87 FPU data register stack. The x87 FPU explicitly sets the SF flag when it detects a stack overflow
or underflow condition, but it does not explicitly clear the flag when it detects an invalid-arithmetic-operand condition.
When this flag is set, the condition code flag C1 indicates the nature of the fault: overflow (C1 = 1) and underflow (C1 = 0). The SF flag is a “sticky” flag, meaning that after it is set, the processor does not clear it until it is
explicitly instructed to do so (for example, by an FINIT/FNINIT, FCLEX/FNCLEX, or FSAVE/FNSAVE instruction).
See Section 8.1.7, “x87 FPU Tag Word,” for more information on x87 FPU stack faults.
8.1.4
Branching and Conditional Moves on Condition Codes
The x87 FPU (beginning with the P6 family processors) supports two mechanisms for branching and performing
conditional moves according to comparisons of two floating-point values. These mechanism are referred to here as
the “old mechanism” and the “new mechanism.”
The old mechanism is available in x87 FPU’s prior to the P6 family processors and in P6 family processors. This
mechanism uses the floating-point compare instructions (FCOM, FCOMP, FCOMPP, FTST, FUCOMPP, FICOM, and
FICOMP) to compare two floating-point values and set the condition code flags (C0 through C3) according to the
results. The contents of the condition code flags are then copied into the status flags of the EFLAGS register using
a two step process (see Figure 8-5):
1. The FSTSW AX instruction moves the x87 FPU status word into the AX register.
2. The SAHF instruction copies the upper 8 bits of the AX register, which includes the condition code flags, into the
lower 8 bits of the EFLAGS register.
When the condition code flags have been loaded into the EFLAGS register, conditional jumps or conditional moves
can be performed based on the new settings of the status flags in the EFLAGS register.
Condition Status
Flag
Code
C0
C1
C2
C3
CF
(none)
PF
ZF
15
x87 FPU Status Word
C
3
0
C C C
2 1 0
FSTSW AX Instruction
15
AX Register
C
3
0
C C C
2 1 0
SAHF Instruction
31
EFLAGS Register
7
0
Z
F
P
C
F 1 F
Figure 8-5. Moving the Condition Codes to the EFLAGS Register
8-6 Vol. 1
PROGRAMMING WITH THE X87 FPU
The new mechanism is available beginning with the P6 family processors. Using this mechanism, the new floatingpoint compare and set EFLAGS instructions (FCOMI, FCOMIP, FUCOMI, and FUCOMIP) compare two floating-point
values and set the ZF, PF, and CF flags in the EFLAGS register directly. A single instruction thus replaces the three
instructions required by the old mechanism.
Note also that the FCMOVcc instructions (also new in the P6 family processors) allow conditional moves of floatingpoint values (values in the x87 FPU data registers) based on the setting of the status flags (ZF, PF, and CF) in the
EFLAGS register. These instructions eliminate the need for an IF statement to perform conditional moves of
floating-point values.
8.1.5
x87 FPU Control Word
The 16-bit x87 FPU control word (see Figure 8-6) controls the precision of the x87 FPU and rounding method used.
It also contains the x87 FPU floating-point exception mask bits. The control word is cached in the x87 FPU control
register. The contents of this register can be loaded with the FLDCW instruction and stored in memory with the
FSTCW/FNSTCW instructions.
Infinity Control
Rounding Control
Precision Control
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X
RC
PC
P U O Z D I
M M M M M M
Exception Masks
Precision
Underflow
Overflow
Zero Divide
Denormal Operand
Invalid Operation
Reserved
Figure 8-6. x87 FPU Control Word
When the x87 FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87 FPU control
word is set to 037FH, which masks all floating-point exceptions, sets rounding to nearest, and sets the x87 FPU
precision to 64 bits.
8.1.5.1
x87 FPU Floating-Point Exception Mask Bits
The exception-flag mask bits (bits 0 through 5 of the x87 FPU control word) mask the 6 floating-point exception
flags in the x87 FPU status word. When one of these mask bits is set, its corresponding x87 FPU floating-point
exception is blocked from being generated.
8.1.5.2
Precision Control Field
The precision-control (PC) field (bits 8 and 9 of the x87 FPU control word) determines the precision (64, 53, or 24
bits) of floating-point calculations made by the x87 FPU (see Table 8-2). The default precision is double extended
precision, which uses the full 64-bit significand available with the double extended-precision floating-point format
of the x87 FPU data registers. This setting is best suited for most applications, because it allows applications to take
full advantage of the maximum precision available with the x87 FPU data registers.
Vol. 1 8-7
PROGRAMMING WITH THE X87 FPU
Table 8-2. Precision Control Field (PC)
Precision
PC Field
Single Precision (24 bits)
00B
Reserved
01B
Double Precision (53 bits)
10B
Double Extended Precision (64 bits)
11B
The double precision and single precision settings reduce the size of the significand to 53 bits and 24 bits, respectively. These settings are provided to support IEEE Standard 754 and to provide compatibility with the specifications of certain existing programming languages. Using these settings nullifies the advantages of the double
extended-precision floating-point format's 64-bit significand length. When reduced precision is specified, the
rounding of the significand value clears the unused bits on the right to zeros.
The precision-control bits only affect the results of the following floating-point instructions: FADD, FADDP, FIADD,
FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR, FMUL, FMULP, FIMUL, FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR,
and FSQRT.
8.1.5.3
Rounding Control Field
The rounding-control (RC) field of the x87 FPU control register (bits 10 and 11) controls how the results of x87 FPU
floating-point instructions are rounded. See Section 4.8.4, “Rounding,” for a discussion of rounding of floatingpoint values; See Section 4.8.4.1, “Rounding Control (RC) Fields”, for the encodings of the RC field.
8.1.6
Infinity Control Flag
The infinity control flag (bit 12 of the x87 FPU control word) is provided for compatibility with the Intel 287 Math
Coprocessor; it is not meaningful for later version x87 FPU coprocessors or IA-32 processors. See Section 4.8.3.3,
“Signed Infinities,” for information on how the x87 FPUs handle infinity values.
8.1.7
x87 FPU Tag Word
The 16-bit tag word (see Figure 8-7) indicates the contents of each the 8 registers in the x87 FPU data-register
stack (one 2-bit tag per register). The tag codes indicate whether a register contains a valid number, zero, or a
special floating-point number (NaN, infinity, denormal, or unsupported format), or whether it is empty. The x87
FPU tag word is cached in the x87 FPU in the x87 FPU tag word register. When the x87 FPU is initialized with either
an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87 FPU tag word is set to FFFFH, which marks all the x87 FPU
data registers as empty.
.
15
0
TAG(7)
TAG(6)
TAG(5)
TAG(4)
TAG(3)
TAG(2)
TAG(1)
TAG(0)
TAG Values
00 — Valid
01 — Zero
10 — Special: invalid (NaN, unsupported), infinity, or denormal
11 — Empty
Figure 8-7. x87 FPU Tag Word
Each tag in the x87 FPU tag word corresponds to a physical register (numbers 0 through 7). The current top-ofstack (TOP) pointer stored in the x87 FPU status word can be used to associate tags with registers relative to ST(0).
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PROGRAMMING WITH THE X87 FPU
The x87 FPU uses the tag values to detect stack overflow and underflow conditions (see Section 8.5.1.1, “Stack
Overflow or Underflow Exception (#IS)”).
Application programs and exception handlers can use this tag information to check the contents of an x87 FPU data
register without performing complex decoding of the actual data in the register. To read the tag register, it must be
stored in memory using either the FSTENV/FNSTENV or FSAVE/FNSAVE instructions. The location of the tag word
in memory after being saved with one of these instructions is shown in Figures 8-9 through 8-12.
Software cannot directly load or modify the tags in the tag register. The FLDENV and FRSTOR instructions load an
image of the tag register into the x87 FPU; however, the x87 FPU uses those tag values only to determine if the
data registers are empty (11B) or non-empty (00B, 01B, or 10B).
If the tag register image indicates that a data register is empty, the tag in the tag register for that data register is
marked empty (11B); if the tag register image indicates that the data register is non-empty, the x87 FPU reads the
actual value in the data register and sets the tag for the register accordingly. This action prevents a program from
setting the values in the tag register to incorrectly represent the actual contents of non-empty data registers.
8.1.8
x87 FPU Instruction and Data (Operand) Pointers
The x87 FPU stores pointers to the instruction and data (operand) for the last non-control instruction executed.
These are the x87 FPU instruction pointer and x87 FPU data (operand) pointers; software can save these pointers
to provide state information for exception handlers. The pointers are illustrated in Figure 8-1 (the figure illustrates
the pointers as used outside 64-bit mode; see below).
Note that the value in the x87 FPU data pointer is always a pointer to a memory operand. If the last non-control
instruction that was executed did not have a memory operand, the value in the data pointer is undefined
(reserved). If CPUID.(EAX=07H,ECX=0H):EBX[bit 6] = 1, the data pointer is updated only for x87 non-control
instructions that incur unmasked x87 exceptions.
The contents of the x87 FPU instruction and data pointers remain unchanged when any of the following instructions
are executed: FCLEX/FNCLEX, FLDCW, FSTCW/FNSTCW, FSTSW/FNSTSW, FSTENV/FNSTENV, FLDENV, and
WAIT/FWAIT.
For all the x87 FPUs and NPXs except the 8087, the x87 FPU instruction pointer points to any prefixes that preceded
the instruction. For the 8087, the x87 FPU instruction pointer points only to the actual opcode.
The x87 FPU instruction and data pointers each consists of an offset and a segment selector:
•
The x87 FPU Instruction Pointer Offset (FIP) comprises 64 bits on processors that support IA-32e mode; on
other processors, it offset comprises 32 bits.
•
•
The x87 FPU Instruction Pointer Selector (FCS) comprises 16 bits.
•
The x87 FPU Data Pointer Selector (FDS) comprises 16 bits.
The x87 FPU Data Pointer Offset (FDP) comprises 64 bits on processors that support IA-32e mode; on other
processors, it offset comprises 32 bits.
The pointers are accessed by the FINIT/FNINIT, FLDENV, FRSTOR, FSAVE/FNSAVE, FSTENV/FNSTENV, FXRSTOR,
FXSAVE, XRSTOR, XSAVE, and XSAVEOPT instructions as follows:
•
•
FINIT/FNINIT. Each instruction clears FIP, FCS, FDP, and FDS.
FLDENV, FRSTOR. These instructions use the memory formats given in Figures 8-9 through 8-12:
— For each of FIP and FDP, each instruction loads the lower 32 bits from memory and clears the upper 32 bits.
— If CR0.PE = 1, each instruction loads FCS and FDS from memory; otherwise, it clears them.
•
FSAVE/FNSAVE, FSTENV/FNSTENV. These instructions use the memory formats given in Figures 8-9 through
8-12.
— Each instruction saves the lower 32 bits of each FIP and FDP into memory. the upper 32 bits are not saved.
— If CR0.PE = 1, each instruction saves FCS and FDS into memory. If
CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the processor deprecates FCS and FDS; it saves each as
0000H.
— After saving these data into memory, FSAVE/FNSAVE clears FIP, FCS, FDP, and FDS.
Vol. 1 8-9
PROGRAMMING WITH THE X87 FPU
•
FXRSTOR, XRSTOR. These instructions load data from a memory image whose format depend on operating
mode and the REX prefix. The memory formats are given in Tables 3-43, 3-46, and 3-47 in Chapter 3,
“Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
— Outside of 64-bit mode or if REX.W = 0, the instructions operate as follows:
•
For each of FIP and FDP, each instruction loads the lower 32 bits from memory and clears the upper 32
bits.
•
Each instruction loads FCS and FDS from memory.
— In 64-bit mode with REX.W = 1, the instructions operate as follows:
•
•
•
Each instruction loads FIP and FDP from memory.
Each instruction clears FCS and FDS.
FXSAVE, XSAVE, and XSAVEOPT. These instructions store data into a memory image whose format depend on
operating mode and the REX prefix. The memory formats are given in Tables 3-43, 3-46, and 3-47 in Chapter
3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
— Outside of 64-bit mode or if REX.W = 0, the instructions operate as follows:
•
Each instruction saves the lower 32 bits of each of FIP and FDP into memory. The upper 32 bits are not
saved.
•
Each instruction saves FCS and FDS into memory. If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the
processor deprecates FCS and FDS; it saves each as 0000H.
— In 64-bit mode with REX.W = 1, each instruction saves FIP and FDP into memory. FCS and FDS are not
saved.
8.1.9
Last Instruction Opcode
The x87 FPU stores in the 11-bit x87 FPU opcode register (FOP) the opcode of the last x87 non-control instruction
executed that incurred an unmasked x87 exception. (This information provides state information for exception
handlers.) Only the first and second opcode bytes (after all prefixes) are stored in the x87 FPU opcode register.
Figure 8-8 shows the encoding of these two bytes. Since the upper 5 bits of the first opcode byte are the same for
all floating-point opcodes (11011B), only the lower 3 bits of this byte are stored in the opcode register.
8.1.9.1
Fopcode Compatibility Sub-mode
Some Pentium 4 and Intel Xeon processors provide program control over the value stored into FOP. Here, bit 2 of
the IA32_MISC_ENABLE MSR enables (set) or disables (clear) the fopcode compatibility mode.
If fopcode compatibility mode is enabled, FOP is defined as it had been in previous IA-32 implementations, as the
opcode of the last x87 non-control instruction executed (even if that instruction did not incur an unmasked x87
exception).
7
1st Instruction Byte
2
10
2nd Instruction Byte
0
7
0
8 7
0
x87 FPU Opcode Register
Figure 8-8. Contents of x87 FPU Opcode Registers
8-10 Vol. 1
PROGRAMMING WITH THE X87 FPU
The fopcode compatibility mode should be enabled only when x87 FPU floating-point exception handlers are
designed to use the fopcode to analyze program performance or restart a program after an exception has been
handled.
More recent Intel 64 processors do not support fopcode compatibility mode and do not allow software to set bit 2
of the IA32_MISC_ENABLE MSR.
8.1.10
Saving the x87 FPU’s State with FSTENV/FNSTENV and FSAVE/FNSAVE
The FSTENV/FNSTENV and FSAVE/FNSAVE instructions store x87 FPU state information in memory for use by
exception handlers and other system and application software. The FSTENV/FNSTENV instruction saves the
contents of the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer, and opcode registers. The
FSAVE/FNSAVE instruction stores that information plus the contents of the x87 FPU data registers. Note that the
FSAVE/FNSAVE instruction also initializes the x87 FPU to default values (just as the FINIT/FNINIT instruction does)
after it has saved the original state of the x87 FPU.
The manner in which this information is stored in memory depends on the operating mode of the processor
(protected mode or real-address mode) and on the operand-size attribute in effect (32-bit or 16-bit). See Figures
8-9 through 8-12. In virtual-8086 mode or SMM, the real-address mode formats shown in Figure 8-12 is used. See
Chapter 34, “System Management Mode,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3C, for information on using the x87 FPU while in SMM.
The FLDENV and FRSTOR instructions allow x87 FPU state information to be loaded from memory into the x87 FPU.
Here, the FLDENV instruction loads only the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer,
and opcode registers, and the FRSTOR instruction loads all the x87 FPU registers, including the x87 FPU stack
registers.
31
32-Bit Protected Mode Format
16 15
0
Control Word
0
Status Word
4
Tag Word
8
FPU Instruction Pointer Offset (FIP)
00000
Bits 10:0 of opcode
FPU Instruction Pointer Selector
FPU Data Pointer Offset (FDP)
12
16
20
FPU Data Pointer Selector (FDS) 24
For instructions that also store x87 FPU data registers, the eight
80-bit registers (R0-R7) follow the above structure in sequence.
Figure 8-9. Protected Mode x87 FPU State Image in Memory, 32-Bit Format
Vol. 1 8-11
PROGRAMMING WITH THE X87 FPU
31
32-Bit Real-Address Mode Format
16 15
0000
FIP[31:16]
0000
FDP[31:16]
0
Control Word
0
Status Word
4
Tag Word
8
FIP[15:0]
12
FOP[10:0]
16
FDP[15:0]
20
000000000000
24
For instructions that also store x87 FPU data registers, the eight
80-bit registers (R0-R7) follow the above structure in sequence.
Figure 8-10. Real Mode x87 FPU State Image in Memory, 32-Bit Format
16-Bit Protected Mode Format
0
15
Control Word
0
Status Word
2
Tag Word
4
FIP
6
FCS
8
FDP
10
FDS
12
Figure 8-11. Protected Mode x87 FPU State Image in Memory, 16-Bit Format
15
16-Bit Real-Address Mode and
Virtual-8086 Mode Format
0
Control Word
0
Status Word
2
Tag Word
FIP[15:0]
FIP[19:16] 0 Bits 10:0 of opcode
FDP[15:0]
4
6
8
10
FDP[19:16] 0 0 0 0 0 0 0 0 0 0 0 0 12
Figure 8-12. Real Mode x87 FPU State Image in Memory, 16-Bit Format
8.1.11
Saving the x87 FPU’s State with FXSAVE
The FXSAVE and FXRSTOR instructions save and restore, respectively, the x87 FPU state along with the state of the
XMM registers and the MXCSR register. Using the FXSAVE instruction to save the x87 FPU state has two benefits:
(1) FXSAVE executes faster than FSAVE, and (2) FXSAVE saves the entire x87 FPU, MMX, and XMM state in one
operation. See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for additional information about these instructions.
8-12 Vol. 1
PROGRAMMING WITH THE X87 FPU
8.2
X87 FPU DATA TYPES
The x87 FPU recognizes and operates on the following seven data types (see Figures 8-13): single-precision
floating point, double-precision floating point, double extended-precision floating point, signed word integer,
signed doubleword integer, signed quadword integer, and packed BCD decimal integers.
For detailed information about these data types, see Section 4.2.2, “Floating-Point Data Types,” Section 4.2.1.2,
“Signed Integers,” and Section 4.7, “BCD and Packed BCD Integers.”
With the exception of the 80-bit double extended-precision floating-point format, all of these data types exist in
memory only. When they are loaded into x87 FPU data registers, they are converted into double extended-precision floating-point format and operated on in that format.
Denormal values are also supported in each of the floating-point types, as required by IEEE Standard 754. When a
denormal number in single-precision or double-precision floating-point format is used as a source operand and the
denormal exception is masked, the x87 FPU automatically normalizes the number when it is converted to double
extended-precision format.
When stored in memory, the least significant byte of an x87 FPU data-type value is stored at the initial address
specified for the value. Successive bytes from the value are then stored in successively higher addresses in
memory. The floating-point instructions load and store memory operands using only the initial address of the
operand.
Single-Precision Floating-Point
Sign
Exp.
23 22
3130
Fraction
0
Implied Integer
Double-Precision Floating-Point
Sign
Exponent
63 62
52 51
Sign
Fraction
0
Implied Integer
Double Extended-Precision Floating-Point
Exponent
6463 62
79 78
Fraction
0
Integer
Word Integer
Sign
15 14
0
Doubleword Integer
Sign
31 30
0
Quadword Integer
Sign
Sign
63 62
0
Packed BCD Integers
X
79 78
D17 D16 D15 D14 D13 D12 D11 D10
72 71
D9
D8
D7
D6
D5
4 Bits = 1 BCD Digit
D4
D3
D2
D1
D0
0
Figure 8-13. x87 FPU Data Type Formats
As a general rule, values should be stored in memory in double-precision format. This format provides sufficient
range and precision to return correct results with a minimum of programmer attention. The single-precision format
is useful for debugging algorithms, because rounding problems will manifest themselves more quickly in this
format. The double extended-precision format is normally reserved for holding intermediate results in the x87 FPU
registers and constants. Its extra length is designed to shield final results from the effects of rounding and overflow/underflow in intermediate calculations. However, when an application requires the maximum range and precision of the x87 FPU (for data storage, computations, and results), values can be stored in memory in double
extended-precision format.
Vol. 1 8-13
PROGRAMMING WITH THE X87 FPU
8.2.1
Indefinites
For each x87 FPU data type, one unique encoding is reserved for representing the special value indefinite. The x87
FPU produces indefinite values as responses to some masked floating-point invalid-operation exceptions. See
Tables 4-1, 4-3, and 4-4 for the encoding of the integer indefinite, QNaN floating-point indefinite, and packed BCD
integer indefinite, respectively.
The binary integer encoding 100..00B represents either of two things, depending on the circumstances of its use:
•
•
The largest negative number supported by the format (–215, –231, or –263)
The integer indefinite value
If this encoding is used as a source operand (as in an integer load or integer arithmetic instruction), the x87 FPU
interprets it as the largest negative number representable in the format being used. If the x87 FPU detects an
invalid operation when storing an integer value in memory with an FIST/FISTP instruction and the invalid-operation
exception is masked, the x87 FPU stores the integer indefinite encoding in the destination operand as a masked
response to the exception. In situations where the origin of a value with this encoding may be ambiguous, the
invalid-operation exception flag can be examined to see if the value was produced as a response to an exception.
8.2.2
Unsupported Double Extended-Precision
Floating-Point Encodings and Pseudo-Denormals
The double extended-precision floating-point format permits many encodings that do not fall into any of the categories shown in Table 4-3. Table 8-3 shows these unsupported encodings. Some of these encodings were supported
by the Intel 287 math coprocessor; however, most of them are not supported by the Intel 387 math coprocessor
and later IA-32 processors. These encodings are no longer supported due to changes made in the final version of
IEEE Standard 754 that eliminated these encodings.
Specifically, the categories of encodings formerly known as pseudo-NaNs, pseudo-infinities, and un-normal
numbers are not supported and should not be used as operand values. The Intel 387 math coprocessor and later
IA-32 processors generate an invalid-operation exception when these encodings are encountered as operands.
Beginning with the Intel 387 math coprocessor, the encodings formerly known as pseudo-denormal numbers are
not generated by IA-32 processors. When encountered as operands, however, they are handled correctly; that is,
they are treated as denormals and a denormal exception is generated. Pseudo-denormal numbers should not be
used as operand values. They are supported by current IA-32 processors (as described here) to support legacy
code.
Table 8-3. Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals
Class
Positive
Pseudo-NaNs
Positive Floating Point
Biased Exponent
Integer
Fraction
0
.
0
11..11
.
11..11
0
Quiet
11..11
.
10..00
0
.
0
11..11
.
11..11
0
Signaling
01..11
.
00..01
Pseudo-infinity
0
11..11
0
00..00
0
.
0
11..10
.
00..01
0
Unnormals
11..11
.
00..00
0
.
0
00..00
.
00..00
1
11..11
.
00..00
Pseudo-denormals
8-14 Vol. 1
Significand
Sign
PROGRAMMING WITH THE X87 FPU
Table 8-3. Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals (Contd.)
Negative Floating Point Pseudo-denormals
1
.
1
00..00
.
00..00
1
11..11
.
00..00
11..10
.
00..01
0
Unnormals
1
.
1
11..01
.
00..00
Pseudo-infinity
1
11..11
0
00..00
11..11
.
11..11
0
Signaling
1
.
1
01..11
.
00..01
1
.
1
11..11
.
11..11
0
Quiet
11..11
.
10..00
Negative Pseudo-NaNs
← 15 bits →
8.3
← 63 bits →
X87 FPU INSTRUCTION SET
The floating-point instructions that the x87 FPU supports can be grouped into six functional categories:
•
•
•
•
•
•
Data transfer instructions
Basic arithmetic instructions
Comparison instructions
Transcendental instructions
Load constant instructions
x87 FPU control instructions
See Section , “CPUID.EAX=80000001H:ECX.PREFTEHCHW[bit 8]: if 1 indicates the processor supports the PREFTEHCHW instruction. CPUID.(EAX=07H, ECX=0H):ECX.PREFTEHCHWT1[bit 0]: if 1 indicates the processor supports
the PREFTEHCHWT1 instruction.,” for a list of the floating-point instructions by category.
The following section briefly describes the instructions in each category. Detailed descriptions of the floating-point
instructions are given in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C
& 2D.
8.3.1
Escape (ESC) Instructions
All of the instructions in the x87 FPU instruction set fall into a class of instructions known as escape (ESC) instructions. All of these instructions have a common opcode format, where the first byte of the opcode is one of the
numbers from D8H through DFH.
8.3.2
x87 FPU Instruction Operands
Most floating-point instructions require one or two operands, located on the x87 FPU data-register stack or in
memory. (None of the floating-point instructions accept immediate operands.)
When an operand is located in a data register, it is referenced relative to the ST(0) register (the register at the top
of the register stack), rather than by a physical register number. Often the ST(0) register is an implied operand.
Operands in memory can be referenced using the same operand addressing methods described in Section 3.7,
“Operand Addressing.”
Vol. 1 8-15
PROGRAMMING WITH THE X87 FPU
8.3.3
Data Transfer Instructions
The data transfer instructions (see Table 8-4) perform the following operations:
•
•
•
Load a floating-point, integer, or packed BCD operand from memory into the ST(0) register.
Store the value in an ST(0) register to memory in floating-point, integer, or packed BCD format.
Move values between registers in the x87 FPU register stack.
The FLD (load floating point) instruction pushes a floating-point operand from memory onto the top of the x87 FPU
data-register stack. If the operand is in single-precision or double-precision floating-point format, it is automatically converted to double extended-precision floating-point format. This instruction can also be used to push the
value in a selected x87 FPU data register onto the top of the register stack.
The FILD (load integer) instruction converts an integer operand in memory into double extended-precision floatingpoint format and pushes the value onto the top of the register stack. The FBLD (load packed decimal) instruction
performs the same load operation for a packed BCD operand in memory.
8-16 Vol. 1
PROGRAMMING WITH THE X87 FPU
Table 8-4. Data Transfer Instructions
Floating Point
Integer
Packed Decimal
FLD
Load Floating Point
FILD
Load Integer
FST
Store Floating Point
FIST
Store Integer
FSTP
Store Floating Point and
Pop
FISTP
Store Integer
and Pop
FXCH
Exchange Register
Contents
FCMOVcc
Conditional Move
FBLD
Load Packed
Decimal
FBSTP
Store Packed
Decimal and Pop
The FST (store floating point) and FIST (store integer) instructions store the value in register ST(0) in memory in
the destination format (floating point or integer, respectively). Again, the format conversion is carried out automatically.
The FSTP (store floating point and pop), FISTP (store integer and pop), and FBSTP (store packed decimal and pop)
instructions store the value in the ST(0) registers into memory in the destination format (floating point, integer, or
packed BCD), then performs a pop operation on the register stack. A pop operation causes the ST(0) register to be
marked empty and the stack pointer (TOP) in the x87 FPU control work to be incremented by 1. The FSTP instruction can also be used to copy the value in the ST(0) register to another x87 FPU register [ST(i)].
The FXCH (exchange register contents) instruction exchanges the value in a selected register in the stack [ST(i)]
with the value in ST(0).
The FCMOVcc (conditional move) instructions move the value in a selected register in the stack [ST(i)] to register
ST(0) if a condition specified with a condition code (cc) is satisfied (see Table 8-5). The condition being tested for
is represented by the status flags in the EFLAGS register. The condition code mnemonics are appended to the
letters “FCMOV” to form the mnemonic for a FCMOVcc instruction.
Table 8-5. Floating-Point Conditional Move Instructions
Instruction Mnemonic
Status Flag States
Condition Description
FCMOVB
CF=1
Below
FCMOVNB
CF=0
Not below
FCMOVE
ZF=1
Equal
FCMOVNE
ZF=0
Not equal
Instruction Mnemonic
Status Flag States
Condition Description
FCMOVBE
CF=1 or ZF=1
Below or equal
FCMOVNBE
CF=0 or ZF=0
Not below nor equal
FCMOVU
PF=1
Unordered
FCMOVNU
PF=0
Not unordered
Like the CMOVcc instructions, the FCMOVcc instructions are useful for optimizing small IF constructions. They also
help eliminate branching overhead for IF operations and the possibility of branch mispredictions by the processor.
Software can check if the FCMOVcc instructions are supported by checking the processor’s feature information with
the CPUID instruction.
Vol. 1 8-17
PROGRAMMING WITH THE X87 FPU
8.3.4
Load Constant Instructions
The following instructions push commonly used constants onto the top [ST(0)] of the x87 FPU register stack:
FLDZ
Load +0.0
FLD1
Load +1.0
FLDPI
Load π
FLDL2T
Load log2 10
FLDL2E
Load log2e
FLDLG2
Load log102
FLDLN2
Load loge2
The constant values have full double extended-precision floating-point precision (64 bits) and are accurate to
approximately 19 decimal digits. They are stored internally in a format more precise than double extended-precision floating point. When loading the constant, the x87 FPU rounds the more precise internal constant according
to the RC (rounding control) field of the x87 FPU control word. The inexact-result exception (#P) is not generated
as a result of this rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up. See
Section 8.3.8, “Approximation of Pi,” for information on the π constant.
8.3.5
Basic Arithmetic Instructions
The following floating-point instructions perform basic arithmetic operations on floating-point numbers. Where
applicable, these instructions match IEEE Standard 754:
FADD/FADDP
FIADD
FSUB/FSUBP
FISUB
FSUBR/FSUBRP
FISUBR
FMUL/FMULP
FIMUL
FDIV/FDIVP
FIDIV
FDIVR/FDIVRP
FIDIVR
FABS
FCHS
FSQRT
FPREM
FPREM1
FRNDINT
FXTRACT
Add floating point
Add integer to floating point
Subtract floating point
Subtract integer from floating point
Reverse subtract floating point
Reverse subtract floating point from integer
Multiply floating point
Multiply integer by floating point
Divide floating point
Divide floating point by integer
Reverse divide
Reverse divide integer by floating point
Absolute value
Change sign
Square root
Partial remainder
IEEE partial remainder
Round to integral value
Extract exponent and significand
The add, subtract, multiply and divide instructions operate on the following types of operands:
•
•
Two x87 FPU data registers
An x87 FPU data register and a floating-point or integer value in memory
See Section 8.1.2, “x87 FPU Data Registers,” for a description of how operands are referenced on the data register
stack.
Operands in memory can be in single-precision floating-point, double-precision floating-point, word-integer, or
doubleword-integer format. They are converted to double extended-precision floating-point format automatically.
8-18 Vol. 1
PROGRAMMING WITH THE X87 FPU
Reverse versions of the subtract (FSUBR) and divide (FDIVR) instructions enable efficient coding. For example, the
following options are available with the FSUB and FSUBR instructions for operating on values in a specified x87 FPU
data register ST(i) and the ST(0) register:
FSUB:
ST(0) ← ST(0) − ST(i)
ST(i) ← ST(i) − ST(0)
FSUBR:
ST(0) ← ST(i) − ST(0)
ST(i) ← ST(0) − ST(i)
These instructions eliminate the need to exchange values between the ST(0) register and another x87 FPU register
to perform a subtraction or division.
The pop versions of the add, subtract, multiply, and divide instructions offer the option of popping the x87 FPU
register stack following the arithmetic operation. These instructions operate on values in the ST(i) and ST(0) registers, store the result in the ST(i) register, and pop the ST(0) register.
The FPREM instruction computes the remainder from the division of two operands in the manner used by the Intel
8087 and Intel 287 math coprocessors; the FPREM1 instruction computes the remainder in the manner specified in
IEEE Standard 754.
The FSQRT instruction computes the square root of the source operand.
The FRNDINT instruction returns a floating-point value that is the integral value closest to the source value in the
direction of the rounding mode specified in the RC field of the x87 FPU control word.
The FABS, FCHS, and FXTRACT instructions perform convenient arithmetic operations. The FABS instruction
produces the absolute value of the source operand. The FCHS instruction changes the sign of the source operand.
The FXTRACT instruction separates the source operand into its exponent and fraction and stores each value in a
register in floating-point format.
8.3.6
Comparison and Classification Instructions
The following instructions compare or classify floating-point values:
FCOM/FCOMP/FCOMPPCompare floating point and set x87 FPU
condition code flags.
FUCOM/FUCOMP/FUCOMPPUnordered compare floating point and set
x87 FPU condition code flags.
FICOM/FICOMPCompare integer and set x87 FPU
condition code flags.
FCOMI/FCOMIPCompare floating point and set EFLAGS
status flags.
FUCOMI/FUCOMIPUnordered compare floating point and
set EFLAGS status flags.
FTST
Test (compare floating point with 0.0).
FXAMExamine.
Comparison of floating-point values differ from comparison of integers because floating-point values have four
(rather than three) mutually exclusive relationships: less than, equal, greater than, and unordered.
The unordered relationship is true when at least one of the two values being compared is a NaN or in an unsupported format. This additional relationship is required because, by definition, NaNs are not numbers, so they
cannot have less than, equal, or greater than relationships with other floating-point values.
The FCOM, FCOMP, and FCOMPP instructions compare the value in register ST(0) with a floating-point source
operand and set the condition code flags (C0, C2, and C3) in the x87 FPU status word according to the results (see
Table 8-6).
Vol. 1 8-19
PROGRAMMING WITH THE X87 FPU
If an unordered condition is detected (one or both of the values are NaNs or in an undefined format), a floatingpoint invalid-operation exception is generated.
The pop versions of the instruction pop the x87 FPU register stack once or twice after the comparison operation is
complete.
The FUCOM, FUCOMP, and FUCOMPP instructions operate the same as the FCOM, FCOMP, and FCOMPP instructions.
The only difference is that with the FUCOM, FUCOMP, and FUCOMPP instructions, if an unordered condition is
detected because one or both of the operands are QNaNs, the floating-point invalid-operation exception is not
generated.
Table 8-6. Setting of x87 FPU Condition Code Flags for Floating-Point Number Comparisons
Condition
C3
C2
C0
ST(0) > Source Operand
0
0
0
ST(0) < Source Operand
0
0
1
ST(0) = Source Operand
1
0
0
Unordered
1
1
1
The FICOM and FICOMP instructions also operate the same as the FCOM and FCOMP instructions, except that the
source operand is an integer value in memory. The integer value is automatically converted into an double
extended-precision floating-point value prior to making the comparison. The FICOMP instruction pops the x87 FPU
register stack following the comparison operation.
The FTST instruction performs the same operation as the FCOM instruction, except that the value in register ST(0)
is always compared with the value 0.0.
The FCOMI and FCOMIP instructions were introduced into the IA-32 architecture in the P6 family processors. They
perform the same comparison as the FCOM and FCOMP instructions, except that they set the status flags (ZF, PF,
and CF) in the EFLAGS register to indicate the results of the comparison (see Table 8-7) instead of the x87 FPU
condition code flags. The FCOMI and FCOMIP instructions allow condition branch instructions (Jcc) to be executed
directly from the results of their comparison.
Table 8-7. Setting of EFLAGS Status Flags for Floating-Point Number Comparisons
Comparison Results
ZF
PF
CF
ST0 > ST(i)
0
0
0
ST0 < ST(i)
0
0
1
ST0 = ST(i)
1
0
0
Unordered
1
1
1
Software can check if the FCOMI and FCOMIP instructions are supported by checking the processor’s feature information with the CPUID instruction.
The FUCOMI and FUCOMIP instructions operate the same as the FCOMI and FCOMIP instructions, except that they
do not generate a floating-point invalid-operation exception if the unordered condition is the result of one or both
of the operands being a QNaN. The FCOMIP and FUCOMIP instructions pop the x87 FPU register stack following the
comparison operation.
The FXAM instruction determines the classification of the floating-point value in the ST(0) register (that is, whether
the value is zero, a denormal number, a normal finite number, ∞, a NaN, or an unsupported format) or that the
register is empty. It sets the x87 FPU condition code flags to indicate the classification (see “FXAM—Examine” in
Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A). It also sets the C1 flag to indicate the sign of the value.
8.3.6.1
Branching on the x87 FPU Condition Codes
The processor does not offer any control-flow instructions that branch on the setting of the condition code flags
(C0, C2, and C3) in the x87 FPU status word. To branch on the state of these flags, the x87 FPU status word must
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PROGRAMMING WITH THE X87 FPU
first be moved to the AX register in the integer unit. The FSTSW AX (store status word) instruction can be used for
this purpose. When these flags are in the AX register, the TEST instruction can be used to control conditional
branching as follows:
1. Check for an unordered result. Use the TEST instruction to compare the contents of the AX register with the
constant 0400H (see Table 8-8). This operation will clear the ZF flag in the EFLAGS register if the condition code
flags indicate an unordered result; otherwise, the ZF flag will be set. The JNZ instruction can then be used to
transfer control (if necessary) to a procedure for handling unordered operands.
Table 8-8. TEST Instruction Constants for Conditional Branching
Order
Constant
Branch
ST(0) > Source Operand
4500H
JZ
ST(0) < Source Operand
0100H
JNZ
ST(0) = Source Operand
4000H
JNZ
Unordered
0400H
JNZ
2. Check ordered comparison result. Use the constants given in Table 8-8 in the TEST instruction to test for a less
than, equal to, or greater than result, then use the corresponding conditional branch instruction to transfer
program control to the appropriate procedure or section of code.
If a program or procedure has been thoroughly tested and it incorporates periodic checks for QNaN results, then it
is not necessary to check for the unordered result every time a comparison is made.
See Section 8.1.4, “Branching and Conditional Moves on Condition Codes,” for another technique for branching on
x87 FPU condition codes.
Some non-comparison x87 FPU instructions update the condition code flags in the x87 FPU status word. To ensure
that the status word is not altered inadvertently, store it immediately following a comparison operation.
8.3.7
Trigonometric Instructions
The following instructions perform four common trigonometric functions:
FSIN
Sine
FCOS
Cosine
FSINCOS
Sine and cosine
FPTAN
Tangent
FPATAN
Arctangent
These instructions operate on the top one or two registers of the x87 FPU register stack and they return their
results to the stack. The source operands for the FSIN, FCOS, FSINCOS, and FPTAN instructions must be given in
radians; the source operand for the FPATAN instruction is given in rectangular coordinate units.
The FSINCOS instruction returns both the sine and the cosine of a source operand value. It operates faster than
executing the FSIN and FCOS instructions in succession.
The FPATAN instruction computes the arctangent of ST(1) divided by ST(0), returning a result in radians. It is
useful for converting rectangular coordinates to polar coordinates.
See Section 8.3.8, “Approximation of Pi” and Section 8.3.10, “Transcendental Instruction Accuracy” for information
regarding the accuracy of these instructions.
8.3.8
Approximation of Pi
When the argument (source operand) of a trigonometric function is within the domain of the function, the argument is automatically reduced by the appropriate multiple of 2π through the same reduction mechanism used by
the FPREM and FPREM1 instructions. The internal value of π (3.1415926…) that the x87 FPU uses for argument
Vol. 1 8-21
PROGRAMMING WITH THE X87 FPU
reduction and other computations, denoted as Pi in the expression below. The numerical value of Pi can be written
as:
Pi = 0.f ∗ 22
where the fraction f is expressed in binary form as:
f = C90FDAA2 2168C234 C
(The spaces in the fraction above indicate 32-bit boundaries.)
The internal approximation Pi of the value π has a 66 significant bits. Since the exact value of π represented in
binary has the next 3 bits equal to 0, it means that Pi is the value of π rounded to nearest-even to 68 bits, and also
the value of π rounded toward zero (truncated) to 69 bits.
However, accuracy problems may arise because this relatively short finite approximation Pi of the number π is used
for calculating the reduced argument of the trigonometric function approximations in the implementations of FSIN,
FCOS, FSINCOS, and FPTAN. Alternately, this means that FSIN (x), FCOS (x), and FPTAN (x) are really approximating the mathematical functions sin (x * π /Pi), cos (x * π / Pi), and tan (x * π / Pi), and not exactly sin (x), cos
(x), and tan (x). (Note that FSINCOS is the equivalent of FSIN and FCOS combined together). The period of sin (x
* π /Pi) for example is 2* Pi, and not 2π.
See also Section 8.3.10, “Transcendental Instruction Accuracy” for more information on the accuracy of these functions.
8.3.9
Logarithmic, Exponential, and Scale
The following instructions provide two different logarithmic functions, an exponential function and a scale function:
FYL2X
Logarithm
FYL2XP1
Logarithm epsilon
F2XM1
Exponential
FSCALE
Scale
The FYL2X and FYL2XP1 instructions perform two different base 2 logarithmic operations. The FYL2X instruction
computes (y ∗ log2x). This operation permits the calculation of the log of any base using the following equation:
logb x = (1/log2 b) ∗ log2 x
The FYL2XP1 instruction computes (y ∗ log2(x + 1)). This operation provides optimum accuracy for values of x that
are close to 0.
The F2XM1 instruction computes (2x − 1). This instruction only operates on source values in the range −1.0 to +1.0.
The FSCALE instruction multiplies the source operand by a power of 2.
8.3.10
Transcendental Instruction Accuracy
New transcendental instruction algorithms were incorporated into the IA-32 architecture beginning with the
Pentium processors. These new algorithms (used in transcendental instructions FSIN, FCOS, FSINCOS, FPTAN,
FPATAN, F2XM1, FYL2X, and FYL2XP1) allow a higher level of accuracy than was possible in earlier IA-32 processors
and x87 math coprocessors. The accuracy of these instructions is measured in terms of units in the last place
(ulp). For a given argument x, let f(x) and F(x) be the correct and computed (approximate) function values,
respectively. The error in ulps is defined to be:
( x ) – F ( x )error = f-------------------------k – 63
2
where k is an integer such that:
1≤2
–k
f ( x ) < 2.
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PROGRAMMING WITH THE X87 FPU
With the Pentium processor and later IA-32 processors, the worst case error on transcendental functions is less
than 1 ulp when rounding to the nearest (even) and less than 1.5 ulps when rounding in other modes. The functions are guaranteed to be monotonic, with respect to the input operands, throughout the domain supported by the
instruction.
However, for FSIN, FCOS, FSINCOS, and FPTAN which approximate periodic trigonometric functions, the previous
statement about maximum ulp errors is true only when these instructions are applied to reduced argument (see
Section 8.3.8, “Approximation of Pi”). This is due to the fact that only 66 significant bits are retained in the finite
approximation Pi of the number π (3.1415926…), used internally for calculating the reduced argument in FSIN,
FCOS, FSINCOS, and FPTAN. This approximation of π is not always sufficiently accurate for good argument reduction.
For single precision, the argument of FSIN, FCOS, FSINCOS, and FPTAN must exceed 200,000 radians in order for
the error of the result to exceed 1 ulp when rounding to the nearest (even), or 1.5 ulps when rounding in other
(directed) rounding modes.
For double and double-extended precision, the ulp errors will grow above these thresholds for arguments much
smaller in magnitude. The ulp errors increase significantly when the argument approaches the value of π (or Pi) for
FSIN, and when it approaches π/2(or Pi/2) for FCOS, FSINCOS, and FPTAN.
For all three IEEE precisions supported (32-bit single precision, 64-bit double precision, and 80-bit doubleextended precision), applying FSIN, FCOS, FSINCOS, or FPTAN to arguments larger than a certain value can lead
to reduced arguments (calculated internally) that are inaccurate or even very inaccurate in some cases. This leads
to equally inaccurate approximations of the corresponding mathematical functions. In particular, arguments that
are close to certain values will lose significance when reduced, leading to increased relative (and ulp) errors in the
results of FSIN, FCOS, FSINCOS, and FPTAN. These values are:
•
•
•
any non-zero multiple of π for FSIN,
any multiple of π, plus π/2 for FCOS, and
any non-zero multiple of π/2 for FSINCOS and FPTAN.
If the arguments passed to FSIN, FCOS, FSINCOS, and FPTAN are not close to these values then even the finite
approximation Pi of π used internally for argument reduction will allow for results that have good accuracy.
Therefore, in order to avoid such errors it is recommended to perform accurate argument reduction in software,
and to apply FSIN, FCOS, FSINCOS, and FPTAN to reduced arguments only. Regardless of the target precision
(single, double, or double-extended), it is safe to reduce the argument to a value smaller in absolute value than
about 3π/4 for FSIN, and smaller than about 3π/8 for FCOS, FSINCOS, and FPTAN.
The thresholds shown above are not exact. For example, accuracy measurements show that the double-extended
precision result of FSIN will not have errors larger than 0.72 ulp for |x| < 2.82 (so |x| < 3π/4 will ensure good accuracy, as 3π/4 < 2.82). On the same interval, double precision results from FSIN will have errors at most slightly
larger than 0.5 ulp, and single precision results will be correctly rounded in the vast majority of cases.
Likewise, the double-extended precision result of FCOS will not have errors larger than 0.82 ulp for |x| < 1.31 (so
|x| < 3π/8 will ensure good accuracy, as 3π/8 < 1.31). On the same interval, double precision results from FCOS
will have errors at most slightly larger than 0.5 ulp, and single precision results will be correctly rounded in the vast
majority of cases.
FSINCOS behaves similarly to FSIN and FCOS, combined as a pair.
Finally, the double-extended precision result of FPTAN will not have errors larger than 0.78 ulp for |x| < 1.25 (so
|x| < 3π/8 will ensure good accuracy, as 3π/8 < 1.25). On the same interval, double precision results from FPTAN
will have errors at most slightly larger than 0.5 ulp, and single precision results will be correctly rounded in the vast
majority of cases.
A recommended alternative in order to avoid the accuracy issues that might be caused by FSIN, FCOS, FSINCOS,
and FPTAN, is to use good quality mathematical library implementations of the sin, cos, sincos, and tan functions,
for example those from the Intel® Math Library available in the Intel® Compiler.
The instructions FYL2X and FYL2XP1 are two operand instructions and are guaranteed to be within 1 ulp only when
y equals 1. When y is not equal to 1, the maximum ulp error is always within 1.35 ulps in round to nearest mode.
(For the two operand functions, monotonicity was proved by holding one of the operands constant.)
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PROGRAMMING WITH THE X87 FPU
8.3.11
x87 FPU Control Instructions
The following instructions control the state and modes of operation of the x87 FPU. They also allow the status of the
x87 FPU to be examined:
FINIT/FNINIT
Initialize x87 FPU
FLDCW
Load x87 FPU control word
FSTCW/FNSTCW
Store x87 FPU control word
FSTSW/FNSTSW
Store x87 FPU status word
FCLEX/FNCLEX
Clear x87 FPU exception flags
FLDENV
Load x87 FPU environment
FSTENV/FNSTENV
Store x87 FPU environment
FRSTOR
Restore x87 FPU state
FSAVE/FNSAVE
Save x87 FPU state
FINCSTP
Increment x87 FPU register stack pointer
FDECSTP
Decrement x87 FPU register stack pointer
FFREE
Free x87 FPU register
FNOP
No operation
WAIT/FWAIT
Check for and handle pending unmasked x87 FPU exceptions
The FINIT/FNINIT instructions initialize the x87 FPU and its internal registers to default values.
The FLDCW instructions loads the x87 FPU control word register with a value from memory. The FSTCW/FNSTCW
and FSTSW/FNSTSW instructions store the x87 FPU control and status words, respectively, in memory (or for an
FSTSW/FNSTSW instruction in a general-purpose register).
The FSTENV/FNSTENV and FSAVE/FNSAVE instructions save the x87 FPU environment and state, respectively, in
memory. The x87 FPU environment includes all the x87 FPU’s control and status registers; the x87 FPU state
includes the x87 FPU environment and the data registers in the x87 FPU register stack. (The FSAVE/FNSAVE
instruction also initializes the x87 FPU to default values, like the FINIT/FNINIT instruction, after it saves the original
state of the x87 FPU.)
The FLDENV and FRSTOR instructions load the x87 FPU environment and state, respectively, from memory into the
x87 FPU. These instructions are commonly used when switching tasks or contexts.
The WAIT/FWAIT instructions are synchronization instructions. (They are actually mnemonics for the same
opcode.) These instructions check the x87 FPU status word for pending unmasked x87 FPU exceptions. If any
pending unmasked x87 FPU exceptions are found, they are handled before the processor resumes execution of the
instructions (integer, floating-point, or system instruction) in the instruction stream. The WAIT/FWAIT instructions
are provided to allow synchronization of instruction execution between the x87 FPU and the processor’s integer
unit. See Section 8.6, “x87 FPU Exception Synchronization,” for more information on the use of the WAIT/FWAIT
instructions.
8.3.12
Waiting vs. Non-waiting Instructions
All of the x87 FPU instructions except a few special control instructions perform a wait operation (similar to the
WAIT/FWAIT instructions), to check for and handle pending unmasked x87 FPU floating-point exceptions, before
they perform their primary operation (such as adding two floating-point numbers). These instructions are called
waiting instructions. Some of the x87 FPU control instructions, such as FSTSW/FNSTSW, have both a waiting and
a non-waiting version. The waiting version (with the “F” prefix) executes a wait operation before it performs its
primary operation; whereas, the non-waiting version (with the “FN” prefix) ignores pending unmasked exceptions.
Non-waiting instructions allow software to save the current x87 FPU state without first handling pending exceptions
or to reset or reinitialize the x87 FPU without regard for pending exceptions.
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PROGRAMMING WITH THE X87 FPU
NOTES
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible
(under unusual circumstances) for a non-waiting instruction to be interrupted prior to being
executed to handle a pending x87 FPU exception. The circumstances where this can happen and
the resulting action of the processor are described in Section D.2.1.3, “No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window.”
When operating a P6 family, Pentium 4, or Intel Xeon processor in MS-DOS compatibility mode,
non-waiting instructions can not be interrupted in this way (see Section D.2.2, “MS-DOS* Compatibility Sub-mode in the P6 Family and Pentium® 4 Processors”).
8.3.13
Unsupported x87 FPU Instructions
The Intel 8087 instructions FENI and FDISI and the Intel 287 math coprocessor instruction FSETPM perform no
function in the Intel 387 math coprocessor and later IA-32 processors. If these opcodes are detected in the instruction stream, the x87 FPU performs no specific operation and no internal x87 FPU states are affected.
8.4
X87 FPU FLOATING-POINT EXCEPTION HANDLING
The x87 FPU detects the six classes of exception conditions described in Section 4.9, “Overview of Floating-Point
Exceptions”:
•
Invalid operation (#I), with two subclasses:
— Stack overflow or underflow (#IS)
— Invalid arithmetic operation (#IA)
•
•
•
•
•
Denormalized operand (#D)
Divide-by-zero (#Z)
Numeric overflow (#O)
Numeric underflow (#U)
Inexact result (precision) (#P)
Each of the six exception classes has a corresponding flag bit in the x87 FPU status word and a mask bit in the x87
FPU control word (see Section 8.1.3, “x87 FPU Status Register,” and Section 8.1.5, “x87 FPU Control Word,” respectively). In addition, the exception summary (ES) flag in the status word indicates when one or more unmasked
exceptions has been detected. The stack fault (SF) flag (also in the status word) distinguishes between the two
types of invalid-operation exceptions.
The mask bits can be set with FLDCW, FRSTOR, or FXRSTOR; they can be read with either FSTCW/FNSTCW,
FSAVE/FNSAVE, or FXSAVE. The flag bits can be read with the FSTSW/FNSTSW, FSAVE/FNSAVE, or FXSAVE
instruction.
NOTE
Section 4.9.1, “Floating-Point Exception Conditions,” provides a general overview of how the IA-32
processor detects and handles the various classes of floating-point exceptions. This information
pertains to x87 FPU as well as SSE/SSE2/SSE3 extensions.
The following sections give specific information about how the x87 FPU handles floating-point exceptions that are
unique to the x87 FPU.
8.4.1
Arithmetic vs. Non-arithmetic Instructions
When dealing with floating-point exceptions, it is useful to distinguish between arithmetic instructions and nonarithmetic instructions. Non-arithmetic instructions have no operands or do not make substantial changes to
their operands. Arithmetic instructions do make significant changes to their operands; in particular, they make
changes that could result in floating-point exceptions being signaled. Table 8-9 lists the non-arithmetic and arithVol. 1 8-25
PROGRAMMING WITH THE X87 FPU
metic instructions. It should be noted that some non-arithmetic instructions can signal a floating-point stack (fault)
exception, but this exception is not the result of an operation on an operand.
Table 8-9. Arithmetic and Non-arithmetic Instructions
Non-arithmetic Instructions
Arithmetic Instructions
FABS
F2XM1
FCHS
FADD/FADDP
FCLEX
FBLD
FDECSTP
FBSTP
FFREE
FCOM/FCOMP/FCOMPP
FINCSTP
FCOS
FINIT/FNINIT
FDIV/FDIVP/FDIVR/FDIVRP
FLD (register-to-register)
FIADD
FLD (extended format from memory)
FICOM/FICOMP
FLD constant
FIDIV/FIDIVR
FLDCW
FILD
FLDENV
FIMUL
FNOP
FIST/FISTP1
FRSTOR
FISUB/FISUBR
FSAVE/FNSAVE
FLD (single and double)
FST/FSTP (register-to-register)
FMUL/FMULP
FSTP (extended format to memory)
FPATAN
FSTCW/FNSTCW
FPREM/FPREM1
FSTENV/FNSTENV
FPTAN
FSTSW/FNSTSW
FRNDINT
WAIT/FWAIT
FSCALE
FXAM
FSIN
FXCH
FSINCOS
FSQRT
FST/FSTP (single and double)
FSUB/FSUBP/FSUBR/FSUBRP
FTST
FUCOM/FUCOMP/FUCOMPP
FXTRACT
FYL2X/FYL2XP1
NOTE:
1. The FISTTP instruction in SSE3 is an arithmetic x87 FPU instruction.
8.5
X87 FPU FLOATING-POINT EXCEPTION CONDITIONS
The following sections describe the various conditions that cause a floating-point exception to be generated by the
x87 FPU and the masked response of the x87 FPU when these conditions are detected. Intel® 64 and IA-32 Archi-
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PROGRAMMING WITH THE X87 FPU
tectures Software Developer’s Manual, Volumes 2A & 2B, list the floating-point exceptions that can be signaled for
each floating-point instruction.
See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules for exception precedence when
more than one floating-point exception condition is detected for an instruction.
8.5.1
Invalid Operation Exception
The floating-point invalid-operation exception occurs in response to two sub-classes of operations:
•
•
Stack overflow or underflow (#IS)
Invalid arithmetic operand (#IA)
The flag for this exception (IE) is bit 0 of the x87 FPU status word, and the mask bit (IM) is bit 0 of the x87 FPU
control word. The stack fault flag (SF) of the x87 FPU status word indicates the type of operation that caused the
exception. When the SF flag is set to 1, a stack operation has resulted in stack overflow or underflow; when the flag
is cleared to 0, an arithmetic instruction has encountered an invalid operand. Note that the x87 FPU explicitly sets
the SF flag when it detects a stack overflow or underflow condition, but it does not explicitly clear the flag when it
detects an invalid-arithmetic-operand condition. As a result, the state of the SF flag can be 1 following an invalidarithmetic-operation exception, if it was not cleared from the last time a stack overflow or underflow condition
occurred. See Section 8.1.3.4, “Stack Fault Flag,” for more information about the SF flag.
8.5.1.1
Stack Overflow or Underflow Exception (#IS)
The x87 FPU tag word keeps track of the contents of the registers in the x87 FPU register stack (see Section 8.1.7,
“x87 FPU Tag Word”). It then uses this information to detect two different types of stack faults:
•
Stack overflow — An instruction attempts to load a non-empty x87 FPU register from memory. A non-empty
register is defined as a register containing a zero (tag value of 01), a valid value (tag value of 00), or a special
value (tag value of 10).
•
Stack underflow — An instruction references an empty x87 FPU register as a source operand, including
attempting to write the contents of an empty register to memory. An empty register has a tag value of 11.
NOTES
The term stack overflow originates from the situation where the program has loaded (pushed) eight
values from memory onto the x87 FPU register stack and the next value pushed on the stack
causes a stack wraparound to a register that already contains a value.
The term stack underflow originates from the opposite situation. Here, a program has stored
(popped) eight values from the x87 FPU register stack to memory and the next value popped from
the stack causes stack wraparound to an empty register.
When the x87 FPU detects stack overflow or underflow, it sets the IE flag (bit 0) and the SF flag (bit 6) in the x87
FPU status word to 1. It then sets condition-code flag C1 (bit 9) in the x87 FPU status word to 1 if stack overflow
occurred or to 0 if stack underflow occurred.
If the invalid-operation exception is masked, the x87 FPU returns the floating point, integer, or packed decimal
integer indefinite value to the destination operand, depending on the instruction being executed. This value overwrites the destination register or memory location specified by the instruction.
If the invalid-operation exception is not masked, a software exception handler is invoked (see Section 8.7,
“Handling x87 FPU Exceptions in Software”) and the top-of-stack pointer (TOP) and source operands remain
unchanged.
8.5.1.2
Invalid Arithmetic Operand Exception (#IA)
The x87 FPU is able to detect a variety of invalid arithmetic operations that can be coded in a program. These operations are listed in Table 8-10. (This list includes the invalid operations defined in IEEE Standard 754.)
When the x87 FPU detects an invalid arithmetic operand, it sets the IE flag (bit 0) in the x87 FPU status word to 1.
If the invalid-operation exception is masked, the x87 FPU then returns an indefinite value or QNaN to the destinaVol. 1 8-27
PROGRAMMING WITH THE X87 FPU
tion operand and/or sets the floating-point condition codes as shown in Table 8-10. If the invalid-operation exception is not masked, a software exception handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in
Software”) and the top-of-stack pointer (TOP) and source operands remain unchanged.
Table 8-10. Invalid Arithmetic Operations and the
Masked Responses to Them
Condition
Masked Response
Any arithmetic operation on an operand that is in an unsupported
format.
Return the QNaN floating-point indefinite value to the
destination operand.
Any arithmetic operation on a SNaN.
Return a QNaN to the destination operand (see Table 4-7).
Ordered compare and test operations: one or both operands are
NaNs.
Set the condition code flags (C0, C2, and C3) in the x87 FPU
status word or the CF, PF, and ZF flags in the EFLAGS register to
111B (not comparable).
Addition: operands are opposite-signed infinities.
Subtraction: operands are like-signed infinities.
Return the QNaN floating-point indefinite value to the
destination operand.
Multiplication: ∞ by 0; 0 by ∞ .
Return the QNaN floating-point indefinite value to the
destination operand.
Division: ∞ by ∞ ; 0 by 0.
Return the QNaN floating-point indefinite value to the
destination operand.
Remainder instructions FPREM, FPREM1: modulus (divisor) is 0 or
dividend is ∞ .
Return the QNaN floating-point indefinite; clear condition code
flag C2 to 0.
Trigonometric instructions FCOS, FPTAN, FSIN, FSINCOS: source
operand is ∞ .
Return the QNaN floating-point indefinite; clear condition code
flag C2 to 0.
FSQRT: negative operand (except FSQRT (–0) = –0); FYL2X: negative
operand (except FYL2X (–0) = –∞); FYL2XP1: operand more
negative than –1.
Return the QNaN floating-point indefinite value to the
destination operand.
FBSTP: Converted value cannot be represented in 18 decimal digits,
or source value is an SNaN, QNaN, ± ∞ , or in an unsupported
format.
Store packed BCD integer indefinite value in the destination
operand.
FIST/FISTP: Converted value exceeds representable integer range
of the destination operand, or source value is an SNaN, QNaN, ±∞,
or in an unsupported format.
Store integer indefinite value in the destination operand.
FXCH: one or both registers are tagged empty.
Load empty registers with the QNaN floating-point indefinite
value, then perform the exchange.
Normally, when one or both of the source operands is a QNaN (and neither is an SNaN or in an unsupported
format), an invalid-operand exception is not generated. An exception to this rule is most of the compare instructions (such as the FCOM and FCOMI instructions) and the floating-point to integer conversion instructions
(FIST/FISTP and FBSTP). With these instructions, a QNaN source operand will generate an invalid-operand exception.
8.5.2
Denormal Operand Exception (#D)
The x87 FPU signals the denormal-operand exception under the following conditions:
•
If an arithmetic instruction attempts to operate on a denormal operand (see Section 4.8.3.2, “Normalized and
Denormalized Finite Numbers”).
•
If an attempt is made to load a denormal single-precision or double-precision floating-point value into an x87
FPU register. (If the denormal value being loaded is a double extended-precision floating-point value, the
denormal-operand exception is not reported.)
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PROGRAMMING WITH THE X87 FPU
The flag (DE) for this exception is bit 1 of the x87 FPU status word, and the mask bit (DM) is bit 1 of the x87 FPU
control word.
When a denormal-operand exception occurs and the exception is masked, the x87 FPU sets the DE flag, then
proceeds with the instruction. The denormal operand in single- or double-precision floating-point format is automatically normalized when converted to the double extended-precision floating-point format. Subsequent operations will benefit from the additional precision of the internal double extended-precision floating-point format.
When a denormal-operand exception occurs and the exception is not masked, the DE flag is set and a software
exception handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in Software”). The top-of-stack
pointer (TOP) and source operands remain unchanged.
For additional information about the denormal-operation exception, see Section 4.9.1.2, “Denormal Operand
Exception (#D).”
8.5.3
Divide-By-Zero Exception (#Z)
The x87 FPU reports a floating-point divide-by-zero exception whenever an instruction attempts to divide a finite
non-zero operand by 0. The flag (ZE) for this exception is bit 2 of the x87 FPU status word, and the mask bit (ZM)
is bit 2 of the x87 FPU control word. The FDIV, FDIVP, FDIVR, FDIVRP, FIDIV, and FIDIVR instructions and the other
instructions that perform division internally (FYL2X and FXTRACT) can report the divide-by-zero exception.
When a divide-by-zero exception occurs and the exception is masked, the x87 FPU sets the ZE flag and returns the
values shown in Table 8-10. If the divide-by-zero exception is not masked, the ZE flag is set, a software exception
handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in Software”), and the top-of-stack pointer
(TOP) and source operands remain unchanged.
Table 8-11. Divide-By-Zero Conditions and the Masked Responses to Them
Condition
Masked Response
Divide or reverse divide operation with a
0 divisor.
Returns an ∞ signed with the exclusive OR of the sign of the two operands to the
destination operand.
FYL2X instruction.
Returns an ∞ signed with the opposite sign of the non-zero operand to the destination
operand.
FXTRACT instruction.
ST(1) is set to –∞; ST(0) is set to 0 with the same sign as the source operand.
8.5.4
Numeric Overflow Exception (#O)
The x87 FPU reports a floating-point numeric overflow exception (#O) whenever the rounded result of an arithmetic instruction exceeds the largest allowable finite value that will fit into the floating-point format of the destination operand. (See Section 4.9.1.4, “Numeric Overflow Exception (#O),” for additional information about the
numeric overflow exception.)
When using the x87 FPU, numeric overflow can occur on arithmetic operations where the result is stored in an x87
FPU data register. It can also occur on store floating-point operations (using the FST and FSTP instructions), where
a within-range value in a data register is stored in memory in a single-precision or double-precision floating-point
format. The numeric overflow exception cannot occur when storing values in an integer or BCD integer format.
Instead, the invalid-arithmetic-operand exception is signaled.
The flag (OE) for the numeric-overflow exception is bit 3 of the x87 FPU status word, and the mask bit (OM) is bit
3 of the x87 FPU control word.
When a numeric-overflow exception occurs and the exception is masked, the x87 FPU sets the OE flag and returns
one of the values shown in Table 4-10. The value returned depends on the current rounding mode of the x87 FPU
(see Section 8.1.5.3, “Rounding Control Field”).
The action that the x87 FPU takes when numeric overflow occurs and the numeric-overflow exception is not
masked, depends on whether the instruction is supposed to store the result in memory or on the register stack.
•
Destination is a memory location — The OE flag is set and a software exception handler is invoked (see
Section 8.7, “Handling x87 FPU Exceptions in Software”). The top-of-stack pointer (TOP) and source and
destination operands remain unchanged. Because the data in the stack is in double extended-precision format,
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the exception handler has the option either of re-executing the store instruction after proper adjustment of the
operand or of rounding the significand on the stack to the destination's precision as the standard requires. The
exception handler should ultimately store a value into the destination location in memory if the program is to
continue.
•
Destination is the register stack — The significand of the result is rounded according to current settings of
the precision and rounding control bits in the x87 FPU control word and the exponent of the result is adjusted
by dividing it by 224576. (For instructions not affected by the precision field, the significand is rounded to
double-extended precision.) The resulting value is stored in the destination operand. Condition code bit C1 in
the x87 FPU status word (called in this situation the “round-up bit”) is set if the significand was rounded upward
and cleared if the result was rounded toward 0. After the result is stored, the OE flag is set and a software
exception handler is invoked. The scaling bias value 24,576 is equal to 3 ∗ 213. Biasing the exponent by 24,576
normally translates the number as nearly as possible to the middle of the double extended-precision floatingpoint exponent range so that, if desired, it can be used in subsequent scaled operations with less risk of causing
further exceptions.
When using the FSCALE instruction, massive overflow can occur, where the result is too large to be represented, even with a bias-adjusted exponent. Here, if overflow occurs again, after the result has been biased, a
properly signed ∞ is stored in the destination operand.
8.5.5
Numeric Underflow Exception (#U)
The x87 FPU detects a potential floating-point numeric underflow condition whenever the result of an arithmetic
instruction is non-zero and tiny; that is, the magnitude of the rounded result with unbounded exponent is non-zero
and less than the smallest possible normalized, finite value that will fit into the floating-point format of the destination operand. (See Section 4.9.1.5, “Numeric Underflow Exception (#U),” for additional information about the
numeric underflow exception.)
Like numeric overflow, numeric underflow can occur on arithmetic operations where the result is stored in an x87
FPU data register. It can also occur on store floating-point operations (with the FST and FSTP instructions), where
a within-range value in a data register is stored in memory in the smaller single-precision or double-precision
floating-point formats. A numeric underflow exception cannot occur when storing values in an integer or BCD
integer format, because a value with magnitude less than 1 is always rounded to an integral value of 0 or 1,
depending on the rounding mode in effect.
The flag (UE) for the numeric-underflow exception is bit 4 of the x87 FPU status word, and the mask bit (UM) is bit
4 of the x87 FPU control word.
When a numeric-underflow condition occurs and the exception is masked, the x87 FPU performs the operation
described in Section 4.9.1.5, “Numeric Underflow Exception (#U).”
When the exception is not masked, the action of the x87 FPU depends on whether the instruction is supposed to
store the result in a memory location or on the x87 FPU resister stack.
•
Destination is a memory location — (Can occur only with a store instruction.) The UE flag is set and a
software exception handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in Software”). The topof-stack pointer (TOP) and source and destination operands remain unchanged, and no result is stored in
memory.
Because the data in the stack is in double extended-precision format, the exception handler has the option
either of re-exchanges the store instruction after proper adjustment of the operand or of rounding the
significand on the stack to the destination's precision as the standard requires. The exception handler should
ultimately store a value into the destination location in memory if the program is to continue.
•
Destination is the register stack — The significand of the result is rounded according to current settings of
the precision and rounding control bits in the x87 FPU control word and the exponent of the result is adjusted
by multiplying it by 224576. (For instructions not affected by the precision field, the significand is rounded to
double extended precision.) The resulting value is stored in the destination operand. Condition code bit C1 in
the x87 FPU status register (acting here as a “round-up bit”) is set if the significand was rounded upward and
cleared if the result was rounded toward 0. After the result is stored, the UE flag is set and a software exception
handler is invoked. The scaling bias value 24,576 is the same as is used for the overflow exception and has the
same effect, which is to translate the result as nearly as possible to the middle of the double extended-precision
floating-point exponent range.
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When using the FSCALE instruction, massive underflow can occur, where the magnitude of the result is too
small to be represented, even with a bias-adjusted exponent. Here, if underflow occurs again after the result
has been biased, a properly signed 0 is stored in the destination operand.
8.5.6
Inexact-Result (Precision) Exception (#P)
The inexact-result exception (also called the precision exception) occurs if the result of an operation is not exactly
representable in the destination format. (See Section 4.9.1.6, “Inexact-Result (Precision) Exception (#P),” for
additional information about the numeric overflow exception.) Note that the transcendental instructions (FSIN,
FCOS, FSINCOS, FPTAN, FPATAN, F2XM1, FYL2X, and FYL2XP1) by nature produce inexact results.
The inexact-result exception flag (PE) is bit 5 of the x87 FPU status word, and the mask bit (PM) is bit 5 of the x87
FPU control word.
If the inexact-result exception is masked when an inexact-result condition occurs and a numeric overflow or underflow condition has not occurred, the x87 FPU handles the exception as describe in Section 4.9.1.6, “Inexact-Result
(Precision) Exception (#P),” with one additional action. The C1 (round-up) bit in the x87 FPU status word is set to
indicate whether the inexact result was rounded up (C1 is set) or “not rounded up” (C1 is cleared). In the “not
rounded up” case, the least-significant bits of the inexact result are truncated so that the result fits in the destination format.
If the inexact-result exception is not masked when an inexact result occurs and numeric overflow or underflow has
not occurred, the x87 FPU handles the exception as described in the previous paragraph and, in addition, invokes
a software exception handler.
If an inexact result occurs in conjunction with numeric overflow or underflow, the x87 FPU carries out one of the
following operations:
•
If an inexact result occurs in conjunction with masked overflow or underflow, the OE or UE flag and the PE flag
are set and the result is stored as described for the overflow or underflow exceptions (see Section 8.5.4,
“Numeric Overflow Exception (#O),” or Section 8.5.5, “Numeric Underflow Exception (#U)”). If the inexact
result exception is unmasked, the x87 FPU also invokes a software exception handler.
•
If an inexact result occurs in conjunction with unmasked overflow or underflow and the destination operand is
a register, the OE or UE flag and the PE flag are set, the result is stored as described for the overflow or
underflow exceptions (see Section 8.5.4, “Numeric Overflow Exception (#O),” or Section 8.5.5, “Numeric
Underflow Exception (#U)”) and a software exception handler is invoked.
If an unmasked numeric overflow or underflow exception occurs and the destination operand is a memory location
(which can happen only for a floating-point store), the inexact-result condition is not reported and the C1 flag is
cleared.
8.6
X87 FPU EXCEPTION SYNCHRONIZATION
Because the integer unit and x87 FPU are separate execution units, it is possible for the processor to execute
floating-point, integer, and system instructions concurrently. No special programming techniques are required to
gain the advantages of concurrent execution. (Floating-point instructions are placed in the instruction stream along
with the integer and system instructions.) However, concurrent execution can cause problems for floating-point
exception handlers.
This problem is related to the way the x87 FPU signals the existence of unmasked floating-point exceptions.
(Special exception synchronization is not required for masked floating-point exceptions, because the x87 FPU
always returns a masked result to the destination operand.)
When a floating-point exception is unmasked and the exception condition occurs, the x87 FPU stops further execution of the floating-point instruction and signals the exception event. On the next occurrence of a floating-point
instruction or a WAIT/FWAIT instruction in the instruction stream, the processor checks the ES flag in the x87 FPU
status word for pending floating-point exceptions. If floating-point exceptions are pending, the x87 FPU makes an
implicit call (traps) to the floating-point software exception handler. The exception handler can then execute
recovery procedures for selected or all floating-point exceptions.
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Synchronization problems occur in the time between the moment when the exception is signaled and when it is
actually handled. Because of concurrent execution, integer or system instructions can be executed during this time.
It is thus possible for the source or destination operands for a floating-point instruction that faulted to be overwritten in memory, making it impossible for the exception handler to analyze or recover from the exception.
To solve this problem, an exception synchronizing instruction (either a floating-point instruction or a WAIT/FWAIT
instruction) can be placed immediately after any floating-point instruction that might present a situation where
state information pertaining to a floating-point exception might be lost or corrupted. Floating-point instructions
that store data in memory are prime candidates for synchronization. For example, the following three lines of code
have the potential for exception synchronization problems:
FILD COUNT
INC COUNT
FSQRT
;Floating-point instruction
;Integer instruction
;Subsequent floating-point instruction
In this example, the INC instruction modifies the source operand of the floating-point instruction, FILD. If an
exception is signaled during the execution of the FILD instruction, the INC instruction would be allowed to overwrite
the value stored in the COUNT memory location before the floating-point exception handler is called. With the
COUNT variable modified, the floating-point exception handler would not be able to recover from the error.
Rearranging the instructions, as follows, so that the FSQRT instruction follows the FILD instruction, synchronizes
floating-point exception handling and eliminates the possibility of the COUNT variable being overwritten before the
floating-point exception handler is invoked.
FILD COUNT
FSQRT
INC COUNT
;Floating-point instruction
;Subsequent floating-point instruction synchronizes
;any exceptions generated by the FILD instruction.
;Integer instruction
The FSQRT instruction does not require any synchronization, because the results of this instruction are stored in
the x87 FPU data registers and will remain there, undisturbed, until the next floating-point or WAIT/FWAIT instruction is executed. To absolutely insure that any exceptions emanating from the FSQRT instruction are handled (for
example, prior to a procedure call), a WAIT instruction can be placed directly after the FSQRT instruction.
Note that some floating-point instructions (non-waiting instructions) do not check for pending unmasked exceptions (see Section 8.3.11, “x87 FPU Control Instructions”). They include the FNINIT, FNSTENV, FNSAVE, FNSTSW,
FNSTCW, and FNCLEX instructions. When an FNINIT, FNSTENV, FNSAVE, or FNCLEX instruction is executed, all
pending exceptions are essentially lost (either the x87 FPU status register is cleared or all exceptions are masked).
The FNSTSW and FNSTCW instructions do not check for pending interrupts, but they do not modify the x87 FPU
status and control registers. A subsequent “waiting” floating-point instruction can then handle any pending exceptions.
8.7
HANDLING X87 FPU EXCEPTIONS IN SOFTWARE
The x87 FPU in Pentium and later IA-32 processors provides two different modes of operation for invoking a software exception handler for floating-point exceptions: native mode and MS-DOS compatibility mode. The mode of
operation is selected by CR0.NE[bit 5]. (See Chapter 2, “System Architecture Overview,” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about the NE flag.)
8.7.1
Native Mode
The native mode for handling floating-point exceptions is selected by setting CR0.NE[bit 5] to 1. In this mode, if the
x87 FPU detects an exception condition while executing a floating-point instruction and the exception is unmasked
(the mask bit for the exception is cleared), the x87 FPU sets the flag for the exception and the ES flag in the x87
FPU status word. It then invokes the software exception handler through the floating-point-error exception (#MF,
exception vector 16), immediately before execution of any of the following instructions in the processor’s instruction stream:
•
The next floating-point instruction, unless it is one of the non-waiting instructions (FNINIT, FNCLEX, FNSTSW,
FNSTCW, FNSTENV, and FNSAVE).
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•
•
The next WAIT/FWAIT instruction.
The next MMX instruction.
If the next floating-point instruction in the instruction stream is a non-waiting instruction, the x87 FPU executes the
instruction without invoking the software exception handler.
8.7.2
MS-DOS* Compatibility Sub-mode
If CR0.NE[bit 5] is 0, the MS-DOS compatibility mode for handling floating-point exceptions is selected. In this
mode, the software exception handler for floating-point exceptions is invoked externally using the processor’s
FERR#, INTR, and IGNNE# pins. This method of reporting floating-point errors and invoking an exception handler
is provided to support the floating-point exception handling mechanism used in PC systems that are running the
MS-DOS or Windows* 95 operating system.
Using FERR# and IGNNE# to handle floating-point exception is deprecated by modern operating systems, this
approach also limits newer processors to operate with one logical processor active.
The MS-DOS compatibility mode is typically used as follows to invoke the floating-point exception handler:
1. If the x87 FPU detects an unmasked floating-point exception, it sets the flag for the exception and the ES flag
in the x87 FPU status word.
2. If the IGNNE# pin is deasserted, the x87 FPU then asserts the FERR# pin either immediately, or else delayed
(deferred) until just before the execution of the next waiting floating-point instruction or MMX instruction.
Whether the FERR# pin is asserted immediately or delayed depends on the type of processor, the instruction,
and the type of exception.
3. If a preceding floating-point instruction has set the exception flag for an unmasked x87 FPU exception, the
processor freezes just before executing the next WAIT instruction, waiting floating-point instruction, or MMX
instruction. Whether the FERR# pin was asserted at the preceding floating-point instruction or is just now being
asserted, the freezing of the processor assures that the x87 FPU exception handler will be invoked before the
new floating-point (or MMX) instruction gets executed.
4. The FERR# pin is connected through external hardware to IRQ13 of a cascaded, programmable interrupt
controller (PIC). When the FERR# pin is asserted, the PIC is programmed to generate an interrupt 75H.
5. The PIC asserts the INTR pin on the processor to signal the interrupt 75H.
6. The BIOS for the PC system handles the interrupt 75H by branching to the interrupt 02H (NMI) interrupt
handler.
7. The interrupt 02H handler determines if the interrupt is the result of an NMI interrupt or a floating-point
exception.
8. If a floating-point exception is detected, the interrupt 02H handler branches to the floating-point exception
handler.
If the IGNNE# pin is asserted, the processor ignores floating-point error conditions. This pin is provided to inhibit
floating-point exceptions from being generated while the floating-point exception handler is servicing a previously
signaled floating-point exception.
Appendix D, “Guidelines for Writing x87 FPU Exception Handlers,” describes the MS-DOS compatibility mode in
much greater detail. This mode is somewhat more complicated in the Intel486 and Pentium processor implementations, as described in Appendix D.
8.7.3
Handling x87 FPU Exceptions in Software
Section 4.9.3, “Typical Actions of a Floating-Point Exception Handler,” shows actions that may be carried out by a
floating-point exception handler. The state of the x87 FPU can be saved with the FSTENV/FNSTENV or
FSAVE/FNSAVE instructions (see Section 8.1.10, “Saving the x87 FPU’s State with FSTENV/FNSTENV and
FSAVE/FNSAVE”).
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If the faulting floating-point instruction is followed by one or more non-floating-point instructions, it may not be
useful to re-execute the faulting instruction. See Section 8.6, “x87 FPU Exception Synchronization,” for more information on synchronizing floating-point exceptions.
In cases where the handler needs to restart program execution with the faulting instruction, the IRET instruction
cannot be used directly. The reason for this is that because the exception is not generated until the next floatingpoint or WAIT/FWAIT instruction following the faulting floating-point instruction, the return instruction pointer on
the stack may not point to the faulting instruction. To restart program execution at the faulting instruction, the
exception handler must obtain a pointer to the instruction from the saved x87 FPU state information, load it into the
return instruction pointer location on the stack, and then execute the IRET instruction.
See Section D.3.4, “x87 FPU Exception Handling Examples,” for general examples of floating-point exception
handlers and for specific examples of how to write a floating-point exception handler when using the MS-DOS
compatibility mode.
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CHAPTER 9
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
The Intel MMX technology was introduced into the IA-32 architecture in the Pentium II processor family and
Pentium processor with MMX technology. The extensions introduced in MMX technology support a single-instruction, multiple-data (SIMD) execution model that is designed to accelerate the performance of advanced media and
communications applications.
This chapter describes MMX technology.
9.1
OVERVIEW OF MMX TECHNOLOGY
MMX technology defines a simple and flexible SIMD execution model to handle 64-bit packed integer data. This
model adds the following features to the IA-32 architecture, while maintaining backwards compatibility with all IA32 applications and operating-system code:
•
•
Eight new 64-bit data registers, called MMX registers
Three new packed data types:
— 64-bit packed byte integers (signed and unsigned)
— 64-bit packed word integers (signed and unsigned)
— 64-bit packed doubleword integers (signed and unsigned)
•
•
Instructions that support the new data types and to handle MMX state management
Extensions to the CPUID instruction
MMX technology is accessible from all the IA32-architecture execution modes (protected mode, real address mode,
and virtual 8086 mode). It does not add any new modes to the architecture.
The following sections of this chapter describe MMX technology’s programming environment, including MMX
register set, data types, and instruction set. Additional instructions that operate on MMX registers have been added
to the IA-32 architecture by the SSE/SSE2 extensions.
For more information, see:
•
Section 10.4.4, “SSE 64-Bit SIMD Integer Instructions,” describes MMX instructions added to the IA-32 architecture with the SSE extensions.
•
Section 11.4.2, “SSE2 64-Bit and 128-Bit SIMD Integer Instructions,” describes MMX instructions added to the
IA-32 architecture with SSE2 extensions.
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, give detailed descriptions
of MMX instructions.
•
Chapter 12, “Intel® MMX™ Technology System Programming,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3B, describes the manner in which MMX technology is integrated into the
IA-32 system programming model.
9.2
THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT
Figure 9-1 shows the execution environment for MMX technology. All MMX instructions operate on MMX registers,
the general-purpose registers, and/or memory as follows:
•
MMX registers — These eight registers (see Figure 9-1) are used to perform operations on 64-bit packed
integer data. They are named MM0 through MM7.
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Address Space
232
-1
MMX Registers
Eight 64-Bit
General-Purpose
Registers
Eight 32-Bit
0
Figure 9-1. MMX Technology Execution Environment
•
General-purpose registers — The eight general-purpose registers (see Figure 3-5) are used with existing
IA-32 addressing modes to address operands in memory. (MMX registers cannot be used to address memory).
General-purpose registers are also used to hold operands for some MMX technology operations. They are EAX,
EBX, ECX, EDX, EBP, ESI, EDI, and ESP.
9.2.1
MMX Technology in 64-Bit Mode and Compatibility Mode
In compatibility mode and 64-bit mode, MMX instructions function like they do in protected mode. Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5.
9.2.2
MMX Registers
The MMX register set consists of eight 64-bit registers (see Figure 9-2), that are used to perform calculations on
the MMX packed integer data types. Values in MMX registers have the same format as a 64-bit quantity in memory.
The MMX registers have two data access modes: 64-bit access mode and 32-bit access mode. The 64-bit access
mode is used for:
•
•
•
•
64-bit memory accesses
64-bit transfers between MMX registers
All pack, logical, and arithmetic instructions
Some unpack instructions
The 32-bit access mode is used for:
•
•
•
32-bit memory accesses
32-bit transfer between general-purpose registers and MMX registers
Some unpack instructions
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63
0
MM7
MM6
MM5
MM4
MM3
MM2
MM1
MM0
Figure 9-2. MMX Register Set
Although MMX registers are defined in the IA-32 architecture as separate registers, they are aliased to the registers
in the FPU data register stack (R0 through R7).
See also Section 9.5, “Compatibility with x87 FPU Architecture.”
9.2.3
MMX Data Types
MMX technology introduced the following 64-bit data types to the IA-32 architecture (see Figure 9-3):
•
•
•
64-bit packed byte integers — eight packed bytes
64-bit packed word integers — four packed words
64-bit packed doubleword integers — two packed doublewords
MMX instructions move 64-bit packed data types (packed bytes, packed words, or packed doublewords) and the
quadword data type between MMX registers and memory or between MMX registers in 64-bit blocks. However,
when performing arithmetic or logical operations on the packed data types, MMX instructions operate in parallel on
the individual bytes, words, or doublewords contained in MMX registers (see Section 9.2.5, “Single Instruction,
Multiple Data (SIMD) Execution Model”).
Packed Byte Integers
63
0
Packed Word Integers
63
0
Packed Doubleword Integers
63
0
Figure 9-3. Data Types Introduced with the MMX Technology
9.2.4
Memory Data Formats
When stored in memory: bytes, words and doublewords in the packed data types are stored in consecutive
addresses. The least significant byte, word, or doubleword is stored at the lowest address and the most significant
byte, word, or doubleword is stored at the high address. The ordering of bytes, words, or doublewords in memory
is always little endian. That is, the bytes with the low addresses are less significant than the bytes with high
addresses.
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9.2.5
Single Instruction, Multiple Data (SIMD) Execution Model
MMX technology uses the single instruction, multiple data (SIMD) technique for performing arithmetic and logical
operations on bytes, words, or doublewords packed into MMX registers (see Figure 9-4). For example, the PADDSW
instruction adds 4 signed word integers from one source operand to 4 signed word integers in a second source
operand and stores 4 word integer results in a destination operand. This SIMD technique speeds up software
performance by allowing the same operation to be carried out on multiple data elements in parallel. MMX technology supports parallel operations on byte, word, and doubleword data elements when contained in MMX registers.
The SIMD execution model supported in the MMX technology directly addresses the needs of modern media,
communications, and graphics applications, which often use sophisticated algorithms that perform the same operations on a large number of small data types (bytes, words, and doublewords). For example, most audio data is
represented in 16-bit (word) quantities. The MMX instructions can operate on 4 words simultaneously with one
instruction. Video and graphics information is commonly represented as palletized 8-bit (byte) quantities. In
Figure 9-4, one MMX instruction operates on 8 bytes simultaneously.
Source 1
Source 2
Destination
X3
X2
Y3
Y2
X1
Y1
OP
OP
OP
X3 OP Y3
X2 OP Y2
X1 OP Y1
X0
Y0
OP
X0 OP Y0
Figure 9-4. SIMD Execution Model
9.3
SATURATION AND WRAPAROUND MODES
When performing integer arithmetic, an operation may result in an out-of-range condition, where the true result
cannot be represented in the destination format. For example, when performing arithmetic on signed word integers, positive overflow can occur when the true signed result is larger than 16 bits.
The MMX technology provides three ways of handling out-of-range conditions:
•
Wraparound arithmetic — With wraparound arithmetic, a true out-of-range result is truncated (that is, the
carry or overflow bit is ignored and only the least significant bits of the result are returned to the destination).
Wraparound arithmetic is suitable for applications that control the range of operands to prevent out-of-range
results. If the range of operands is not controlled, however, wraparound arithmetic can lead to large errors. For
example, adding two large signed numbers can cause positive overflow and produce a negative result.
•
Signed saturation arithmetic — With signed saturation arithmetic, out-of-range results are limited to the
representable range of signed integers for the integer size being operated on (see Table 9-1). For example, if
positive overflow occurs when operating on signed word integers, the result is “saturated” to 7FFFH, which is
the largest positive integer that can be represented in 16 bits; if negative overflow occurs, the result is
saturated to 8000H.
•
Unsigned saturation arithmetic — With unsigned saturation arithmetic, out-of-range results are limited to
the representable range of unsigned integers for the integer size. So, positive overflow when operating on
unsigned byte integers results in FFH being returned and negative overflow results in 00H being returned.
.
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Table 9-1. Data Range Limits for Saturation
Data Type
Lower Limit
Hexadecimal
Upper Limit
Decimal
Hexadecimal
Decimal
Signed Byte
80H
-128
7FH
127
Signed Word
8000H
-32,768
7FFFH
32,767
Unsigned Byte
00H
0
FFH
255
Unsigned Word
0000H
0
FFFFH
65,535
Saturation arithmetic provides an answer for many overflow situations. For example, in color calculations, saturation causes a color to remain pure black or pure white without allowing inversion. It also prevents wraparound artifacts from entering into computations when range checking of source operands it not used.
MMX instructions do not indicate overflow or underflow occurrence by generating exceptions or setting flags in the
EFLAGS register.
9.4
MMX INSTRUCTIONS
The MMX instruction set consists of 47 instructions, grouped into the following categories:
•
•
•
•
•
•
•
•
Data transfer
Arithmetic
Comparison
Conversion
Unpacking
Logical
Shift
Empty MMX state instruction (EMMS)
Table 9-2 gives a summary of the instructions in the MMX instruction set. The following sections give a brief overview of the instructions within each group.
NOTES
The MMX instructions described in this chapter are those instructions that are available in an IA-32
processor when CPUID.01H:EDX.MMX[bit 23] = 1.
Section 10.4.4, “SSE 64-Bit SIMD Integer Instructions,” and Section 11.4.2, “SSE2 64-Bit and 128Bit SIMD Integer Instructions,” list additional instructions included with SSE/SSE2 extensions that
operate on the MMX registers but are not considered part of the MMX instruction set.
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Table 9-2. MMX Instruction Set Summary
Category
Arithmetic
Addition
Subtraction
Multiplication
Wraparound
Signed Saturation
Unsigned Saturation
PADDB, PADDW, PADDD
PADDSB, PADDSW
PADDUSB, PADDUSW
PSUBB, PSUBW, PSUBD
PSUBSB, PSUBSW
PSUBUSB, PSUBUSW
PACKSSWB,
PACKSSDW
PACKUSWB
PMULL, PMULH
PMADD
Multiply and Add
Comparison
Compare for Equal
Compare for Greater
Than
PCMPEQB, PCMPEQW,
PCMPEQD
PCMPGTPB, PCMPGTPW,
PCMPGTPD
Conversion
Pack
Unpack
Unpack High
PUNPCKHBW,
PUNPCKHWD,
PUNPCKHDQ
Unpack Low
PUNPCKLBW,
PUNPCKLWD,
PUNPCKLDQ
Packed
Logical
Shift
And
PAND
And Not
PANDN
Or
POR
Exclusive OR
PXOR
Shift Left Logical
PSLLW, PSLLD
PSLLQ
Shift Right Logical
PSRLW, PSRLD
PSRLQ
Shift Right Arithmetic
PSRAW, PSRAD
Doubleword Transfers
Data Transfer
Quadword Transfers
Register to Register
MOVD
MOVQ
Load from Memory
MOVD
MOVQ
Store to Memory
MOVD
MOVQ
Empty MMX State
9.4.1
Full Quadword
EMMS
Data Transfer Instructions
The MOVD (Move 32 Bits) instruction transfers 32 bits of packed data from memory to an MMX register and vice
versa; or from a general-purpose register to an MMX register and vice versa.
The MOVQ (Move 64 Bits) instruction transfers 64 bits of packed data from memory to an MMX register and vice
versa; or transfers data between MMX registers.
9.4.2
Arithmetic Instructions
The arithmetic instructions perform addition, subtraction, multiplication, and multiply/add operations on packed
data types.
The PADDB/PADDW/PADDD (add packed integers) instructions and the PSUBB/PSUBW/ PSUBD (subtract packed
integers) instructions add or subtract the corresponding signed or unsigned data elements of the source and desti9-6 Vol. 1
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
nation operands in wraparound mode. These instructions operate on packed byte, word, and doubleword data
types.
The PADDSB/PADDSW (add packed signed integers with signed saturation) instructions and the PSUBSB/PSUBSW
(subtract packed signed integers with signed saturation) instructions add or subtract the corresponding signed
data elements of the source and destination operands and saturate the result to the limits of the signed data-type
range. These instructions operate on packed byte and word data types.
The PADDUSB/PADDUSW (add packed unsigned integers with unsigned saturation) instructions and the
PSUBUSB/PSUBUSW (subtract packed unsigned integers with unsigned saturation) instructions add or subtract the
corresponding unsigned data elements of the source and destination operands and saturate the result to the limits
of the unsigned data-type range. These instructions operate on packed byte and word data types.
The PMULHW (multiply packed signed integers and store high result) and PMULLW (multiply packed signed integers
and store low result) instructions perform a signed multiply of the corresponding words of the source and destination operands and write the high-order or low-order 16 bits of each of the results, respectively, to the destination
operand.
The PMADDWD (multiply and add packed integers) instruction computes the products of the corresponding signed
words of the source and destination operands. The four intermediate 32-bit doubleword products are summed in
pairs (high-order pair and low-order pair) to produce two 32-bit doubleword results.
9.4.3
Comparison Instructions
The PCMPEQB/PCMPEQW/PCMPEQD (compare packed data for equal) instructions and the
PCMPGTB/PCMPGTW/PCMPGTD (compare packed signed integers for greater than) instructions compare the corresponding signed data elements (bytes, words, or doublewords) in the source and destination operands for equal to
or greater than, respectively.
These instructions generate a mask of ones or zeros which are written to the destination operand. Logical operations can use the mask to select packed elements. This can be used to implement a packed conditional move operation without a branch or a set of branch instructions. No flags in the EFLAGS register are affected.
9.4.4
Conversion Instructions
The PACKSSWB (pack words into bytes with signed saturation) and PACKSSDW (pack doublewords into words with
signed saturation) instructions convert signed words into signed bytes and signed doublewords into signed words,
respectively, using signed saturation.
PACKUSWB (pack words into bytes with unsigned saturation) converts signed words into unsigned bytes, using
unsigned saturation.
9.4.5
Unpack Instructions
The PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ (unpack high-order data elements) instructions and the
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ (unpack low-order data elements) instructions unpack bytes, words, or
doublewords from the high- or low-order data elements of the source and destination operands and interleave
them in the destination operand. By placing all 0s in the source operand, these instructions can be used to convert
byte integers to word integers, word integers to doubleword integers, or doubleword integers to quadword integers.
9.4.6
Logical Instructions
PAND (bitwise logical AND), PANDN (bitwise logical AND NOT), POR (bitwise logical OR), and PXOR (bitwise logical
exclusive OR) perform bitwise logical operations on the quadword source and destination operands.
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9.4.7
Shift Instructions
The logical shift left, logical shift right and arithmetic shift right instructions shift each element by a specified
number of bit positions.
The PSLLW/PSLLD/PSLLQ (shift packed data left logical) instructions and the PSRLW/PSRLD/PSRLQ (shift packed
data right logical) instructions perform a logical left or right shift of the data elements and fill the empty high or low
order bit positions with zeros. These instructions operate on packed words, doublewords, and quadwords.
The PSRAW/PSRAD (shift packed data right arithmetic) instructions perform an arithmetic right shift, copying the
sign bit for each data element into empty bit positions on the upper end of each data element. This instruction
operates on packed words and doublewords.
9.4.8
EMMS Instruction
The EMMS instruction empties the MMX state by setting the tags in x87 FPU tag word to 11B, indicating empty
registers. This instruction must be executed at the end of an MMX routine before calling other routines that can
execute floating-point instructions. See Section 9.6.3, “Using the EMMS Instruction,” for more information on the
use of this instruction.
9.5
COMPATIBILITY WITH X87 FPU ARCHITECTURE
The MMX state is aliased to the x87 FPU state. No new states or modes have been added to IA-32 architecture to
support the MMX technology. The same floating-point instructions that save and restore the x87 FPU state also
handle the MMX state (for example, during context switching).
MMX technology uses the same interface techniques between the x87 FPU and the operating system (primarily for
task switching purposes). For more details, see Chapter 12, “Intel® MMX™ Technology System Programming,” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
9.5.1
MMX Instructions and the x87 FPU Tag Word
After each MMX instruction, the entire x87 FPU tag word is set to valid (00B). The EMMS instruction (empty MMX
state) sets the entire x87 FPU tag word to empty (11B).
Chapter 12, “Intel® MMX™ Technology System Programming,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A, provides additional information about the effects of x87 FPU and MMX instructions
on the x87 FPU tag word. For a description of the tag word, see Section 8.1.7, “x87 FPU Tag Word.”
9.6
WRITING APPLICATIONS WITH MMX CODE
The following sections give guidelines for writing application code that uses MMX technology.
9.6.1
Checking for MMX Technology Support
Before an application attempts to use the MMX technology, it should check that it is present on the processor. Check
by following these steps:
1. Check that the processor supports the CPUID instruction by attempting to execute the CPUID instruction. If the
processor does not support the CPUID instruction, this will generate an invalid-opcode exception (#UD).
2. Check that the processor supports the MMX technology
(if CPUID.01H:EDX.MMX[bit 23] = 1).
3. Check that emulation of the x87 FPU is disabled (if CR0.EM[bit 2] = 0).
If the processor attempts to execute an unsupported MMX instruction or attempts to execute an MMX instruction
with CR0.EM[bit 2] set, this generates an invalid-opcode exception (#UD).
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Example 9-1 illustrates how to use the CPUID instruction to detect the MMX technology. This example does not
represent the entire CPUID sequence, but shows the portion used for detection of MMX technology.
Example 9-1. Partial Routine for Detecting MMX Technology with the CPUID Instruction
...
; identify existence of CPUID instruction
...
; identify Intel processor
mov
EAX, 1
; request for feature flags
CPUID
; 0FH, 0A2H CPUID instruction
test
EDX, 00800000H
; Is IA MMX technology bit (Bit 23 of EDX) set?
jnz
; MMX_Technology_Found
9.6.2
Transitions Between x87 FPU and MMX Code
Applications can contain both x87 FPU floating-point and MMX instructions. However, because the MMX registers
are aliased to the x87 FPU register stack, care must be taken when making transitions between x87 FPU instructions and MMX instructions to prevent incoherent or unexpected results.
When an MMX instruction (other than the EMMS instruction) is executed, the processor changes the x87 FPU state
as follows:
•
•
•
The TOS (top of stack) value of the x87 FPU status word is set to 0.
The entire x87 FPU tag word is set to the valid state (00B in all tag fields).
When an MMX instruction writes to an MMX register, it writes ones (11B) to the exponent part of the corresponding floating-point register (bits 64 through 79).
The net result of these actions is that any x87 FPU state prior to the execution of the MMX instruction is essentially
lost.
When an x87 FPU instruction is executed, the processor assumes that the current state of the x87 FPU register
stack and control registers is valid and executes the instruction without any preparatory modifications to the x87
FPU state.
If the application contains both x87 FPU floating-point and MMX instructions, the following guidelines are recommended:
•
When transitioning between x87 FPU and MMX code, save the state of any x87 FPU data or control registers
that need to be preserved for future use. The FSAVE and FXSAVE instructions save the entire x87 FPU state.
•
When transitioning between MMX and x87 FPU code, do the following:
— Save any data in the MMX registers that needs to be preserved for future use. FSAVE and FXSAVE also save
the state of MMX registers.
— Execute the EMMS instruction to clear the MMX state from the x87 data and control registers.
The following sections describe the use of the EMMS instruction and give additional guidelines for mixing x87 FPU
and MMX code.
9.6.3
Using the EMMS Instruction
As described in Section 9.6.2, “Transitions Between x87 FPU and MMX Code,” when an MMX instruction executes,
the x87 FPU tag word is marked valid (00B). In this state, the execution of subsequent x87 FPU instructions may
produce unexpected x87 FPU floating-point exceptions and/or incorrect results because the x87 FPU register stack
appears to contain valid data. The EMMS instruction is provided to prevent this problem by marking the x87 FPU
tag word as empty.
The EMMS instruction should be used in each of the following cases:
•
When an application using the x87 FPU instructions calls an MMX technology library/DLL (use the EMMS
instruction at the end of the MMX code).
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•
When an application using MMX instructions calls a x87 FPU floating-point library/DLL (use the EMMS
instruction before calling the x87 FPU code).
•
When a switch is made between MMX code in a task or thread and other tasks or threads in cooperative
operating systems, unless it is certain that more MMX instructions will be executed before any x87 FPU code.
EMMS is not required when mixing MMX technology instructions with SSE/SSE2/SSE3 instructions (see Section
11.6.7, “Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions”).
9.6.4
Mixing MMX and x87 FPU Instructions
An application can contain both x87 FPU floating-point and MMX instructions. However, frequent transitions
between MMX and x87 FPU instructions are not recommended, because they can degrade performance in some
processor implementations. When mixing MMX code with x87 FPU code, follow these guidelines:
•
•
•
Keep the code in separate modules, procedures, or routines.
•
When transitioning between x87 FPU code and MMX code, save the x87 FPU state if it will be needed in the
future.
Do not rely on register contents across transitions between x87 FPU and MMX code modules.
When transitioning between MMX code and x87 FPU code, save the MMX register state (if it will be needed in
the future) and execute an EMMS instruction to empty the MMX state.
9.6.5
Interfacing with MMX Code
MMX technology enables direct access to all the MMX registers. This means that all existing interface conventions
that apply to the use of the processor’s general-purpose registers (EAX, EBX, etc.) also apply to the use of MMX
registers.
An efficient interface to MMX routines might pass parameters and return values through the MMX registers or
through a combination of memory locations (via the stack) and MMX registers. Do not use the EMMS instruction or
mix MMX and x87 FPU code when using to the MMX registers to pass parameters.
If a high-level language that does not support the MMX data types directly is used, the MMX data types can be
defined as a 64-bit structure containing packed data types.
When implementing MMX instructions in high-level languages, other approaches can be taken, such as:
•
•
Passing parameters to an MMX routine by passing a pointer to a structure via the stack.
Returning a value from a function by returning a pointer to a structure.
9.6.6
Using MMX Code in a Multitasking Operating System Environment
An application needs to identify the nature of the multitasking operating system on which it runs. Each task retains
its own state which must be saved when a task switch occurs. The processor state (context) consists of the
general-purpose registers and the floating-point and MMX registers.
Operating systems can be classified into two types:
•
•
Cooperative multitasking operating system
Preemptive multitasking operating system
Cooperative multitasking operating systems do not save the FPU or MMX state when performing a context switch.
Therefore, the application needs to save the relevant state before relinquishing direct or indirect control to the
operating system.
Preemptive multitasking operating systems are responsible for saving and restoring the FPU and MMX state when
performing a context switch. Therefore, the application does not have to save or restore the FPU and MMX state.
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9.6.7
Exception Handling in MMX Code
MMX instructions generate the same type of memory-access exceptions as other IA-32 instructions (page fault,
segment not present, and limit violations). Existing exception handlers do not have to be modified to handle these
types of exceptions for MMX code.
Unless there is a pending floating-point exception, MMX instructions do not generate numeric exceptions. Therefore, there is no need to modify existing exception handlers or add new ones to handle numeric exceptions.
If a floating-point exception is pending, the subsequent MMX instruction generates a numeric error exception
(interrupt 16 and/or assertion of the FERR# pin). The MMX instruction resumes execution upon return from the
exception handler.
9.6.8
Register Mapping
MMX registers and their tags are mapped to physical locations of the floating-point registers and their tags.
Register aliasing and mapping is described in more detail in Chapter 12, “Intel® MMX™ Technology System
Programming,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
9.6.9
Effect of Instruction Prefixes on MMX Instructions
Table 9-3 describes the effect of instruction prefixes on MMX instructions. Unpredictable behavior can range from
being treated as a reserved operation on one generation of IA-32 processors to generating an invalid opcode
exception on another generation of processors.
Table 9-3. Effect of Prefixes on MMX Instructions
Prefix Type
Effect on MMX Instructions
Address Size Prefix (67H)
Affects instructions with a memory operand.
Reserved for instructions without a memory operand and may result in
unpredictable behavior.
Operand Size (66H)
Reserved and may result in unpredictable behavior.
Segment Override (2EH, 36H, 3EH, 26H, 64H,
65H)
Affects instructions with a memory operand.
Repeat Prefix (F3H)
Reserved and may result in unpredictable behavior.
Repeat NE Prefix(F2H)
Reserved and may result in unpredictable behavior.
Lock Prefix (F0H)
Reserved; generates invalid opcode exception (#UD).
Branch Hint Prefixes (2EH and 3EH)
Reserved and may result in unpredictable behavior.
Reserved for instructions without a memory operand and may result in
unpredictable behavior.
See “Instruction Prefixes” in Chapter 2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A, for a description of the instruction prefixes.
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9-12 Vol. 1
CHAPTER 10
PROGRAMMING WITH INTEL®
STREAMING SIMD EXTENSIONS (INTEL® SSE)
The streaming SIMD extensions (SSE) were introduced into the IA-32 architecture in the Pentium III processor
family. These extensions enhance the performance of IA-32 processors for advanced 2-D and 3-D graphics, motion
video, image processing, speech recognition, audio synthesis, telephony, and video conferencing.
This chapter describes SSE. Chapter 11, “Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2),”
provides information to assist in writing application programs that use SSE2 extensions. Chapter 12, “Programming with Intel® SSE3, SSSE3, Intel® SSE4 and Intel® AESNI,” provides this information for SSE3 extensions.
10.1
OVERVIEW OF SSE EXTENSIONS
Intel MMX technology introduced single-instruction multiple-data (SIMD) capability into the IA-32 architecture,
with the 64-bit MMX registers, 64-bit packed integer data types, and instructions that allowed SIMD operations to
be performed on packed integers. SSE extensions expand the SIMD execution model by adding facilities for
handling packed and scalar single-precision floating-point values contained in 128-bit registers.
If CPUID.01H:EDX.SSE[bit 25] = 1, SSE extensions are present.
SSE extensions add the following features to the IA-32 architecture, while maintaining backward compatibility with
all existing IA-32 processors, applications and operating systems.
•
Eight 128-bit data registers (called XMM registers) in non-64-bit modes; sixteen XMM registers are available in
64-bit mode.
•
•
The 32-bit MXCSR register, which provides control and status bits for operations performed on XMM registers.
•
Instructions that perform SIMD operations on single-precision floating-point values and that extend SIMD
operations that can be performed on integers:
The 128-bit packed single-precision floating-point data type (four IEEE single-precision floating-point values
packed into a double quadword).
— 128-bit Packed and scalar single-precision floating-point instructions that operate on data located in MMX
registers
— 64-bit SIMD integer instructions that support additional operations on packed integer operands located in
MMX registers
•
•
Instructions that save and restore the state of the MXCSR register.
•
Extensions to the CPUID instruction.
Instructions that support explicit prefetching of data, control of the cacheability of data, and control the
ordering of store operations.
These features extend the IA-32 architecture’s SIMD programming model in four important ways:
•
The ability to perform SIMD operations on four packed single-precision floating-point values enhances the
performance of IA-32 processors for advanced media and communications applications that use computationintensive algorithms to perform repetitive operations on large arrays of simple, native data elements.
•
The ability to perform SIMD single-precision floating-point operations in XMM registers and SIMD integer
operations in MMX registers provides greater flexibility and throughput for executing applications that operate
on large arrays of floating-point and integer data.
•
Cache control instructions provide the ability to stream data in and out of XMM registers without polluting the
caches and the ability to prefetch data to selected cache levels before it is actually used. Applications that
require regular access to large amounts of data benefit from these prefetching and streaming store capabilities.
•
The SFENCE (store fence) instruction provides greater control over the ordering of store operations when using
weakly-ordered memory types.
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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
SSE extensions are fully compatible with all software written for IA-32 processors. All existing software continues
to run correctly, without modification, on processors that incorporate SSE extensions. Enhancements to CPUID
permit detection of SSE extensions. SSE extensions are accessible from all IA-32 execution modes: protected
mode, real address mode, and virtual-8086 mode.
The following sections of this chapter describe the programming environment for SSE extensions, including: XMM
registers, the packed single-precision floating-point data type, and SSE instructions. For additional information,
see:
•
•
Section 11.6, “Writing Applications with SSE/SSE2 Extensions”.
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, provide a detailed
description of these instructions.
•
Chapter 13, “System Programming for Instruction Set Extensions and Processor Extended States,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating
these extensions into an operating-system environment.
Section 11.5, “SSE, SSE2, and SSE3 Exceptions,” describes the exceptions that can be generated with
SSE/SSE2/SSE3 instructions.
10.2
SSE PROGRAMMING ENVIRONMENT
Figure 10-1 shows the execution environment for the SSE extensions. All SSE instructions operate on the XMM
registers, MMX registers, and/or memory as follows:
•
XMM registers — These eight registers (see Figure 10-2 and Section 10.2.2, “XMM Registers”) are used to
operate on packed or scalar single-precision floating-point data. Scalar operations are operations performed on
individual (unpacked) single-precision floating-point values stored in the low doubleword of an XMM register.
XMM registers are referenced by the names XMM0 through XMM7.
Address Space
2
XMM Registers
Eight 128-Bit
MXCSR Register
32
-1
32 Bits
MMX Registers
Eight 64-Bit
General-Purpose
Registers
Eight 32-Bit
0
EFLAGS Register
32 Bits
Figure 10-1. SSE Execution Environment
•
MXCSR register — This 32-bit register (see Figure 10-3 and Section 10.2.3, “MXCSR Control and Status
Register”) provides status and control bits used in SIMD floating-point operations.
•
MMX registers — These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed
integer data. They are also used to hold operands for some operations performed between the MMX and XMM
registers. MMX registers are referenced by the names MM0 through MM7.
•
General-purpose registers — The eight general-purpose registers (see Figure 3-5) are used along with the
existing IA-32 addressing modes to address operands in memory. (MMX and XMM registers cannot be used to
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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
address memory). The general-purpose registers are also used to hold operands for some SSE instructions and
are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.
•
EFLAGS register — This 32-bit register (see Figure 3-8) is used to record result of some compare operations.
10.2.1
SSE in 64-Bit Mode and Compatibility Mode
In compatibility mode, SSE extensions function like they do in protected mode. In 64-bit mode, eight additional
XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are
specified using the ModR/M, SIB encoding described in Section 3.7.5.
Some SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access 64bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.
10.2.2
XMM Registers
Eight 128-bit XMM data registers were introduced into the IA-32 architecture with SSE extensions (see
Figure 10-2). These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed
independently from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased
to any other of the processor’s registers).
127
0
XMM7
XMM6
XMM5
XMM4
XMM3
XMM2
XMM1
XMM0
Figure 10-2. XMM Registers
SSE instructions use the XMM registers only to operate on packed single-precision floating-point operands. SSE2
extensions expand the functions of the XMM registers to operand on packed or scalar double-precision floatingpoint operands and packed integer operands (see Section 11.2, “SSE2 Programming Environment,” and Section
12.1, “Programming Environment and Data types”).
XMM registers can only be used to perform calculations on data; they cannot be used to address memory.
Addressing memory is accomplished by using the general-purpose registers.
Data can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit increments. When storing the entire contents of an XMM register in memory (128-bit store), the data is stored in 16
consecutive bytes, with the low-order byte of the register being stored in the first byte in memory.
10.2.3
MXCSR Control and Status Register
The 32-bit MXCSR register (see Figure 10-3) contains control and status information for SSE, SSE2, and SSE3
SIMD floating-point operations. This register contains:
•
•
flag and mask bits for SIMD floating-point exceptions
rounding control field for SIMD floating-point operations
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•
•
flush-to-zero flag that provides a means of controlling underflow conditions on SIMD floating-point operations
denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands
The contents of this register can be loaded from memory with the LDMXCSR and FXRSTOR instructions and stored
in memory with STMXCSR and FXSAVE.
Bits 16 through 31 of the MXCSR register are reserved and are cleared on a power-up or reset of the processor;
attempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result
in a general-protection exception (#GP) being generated.
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
F
Z
R
C
P U O Z D I D P U O Z D I
A
M M M M M M
E E E E E E
Z
Flush to Zero
Rounding Control
Precision Mask
Underflow Mask
Overflow Mask
Divide-by-Zero Mask
Denormal Operation Mask
Invalid Operation Mask
Denormals Are Zeros*
Precision Flag
Underflow Flag
Overflow Flag
Divide-by-Zero Flag
Denormal Flag
Invalid Operation Flag
* The denormals-are-zeros flag was introduced in the Pentium 4 and Intel Xeon processor.
Figure 10-3. MXCSR Control/Status Register
10.2.3.1
SIMD Floating-Point Mask and Flag Bits
Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They
are “sticky” flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the
LDMXCSR or the FXRSTOR instruction to write zeroes to them.
Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked
if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up
or reset. This causes all SIMD floating-point exceptions to be initially masked.
If LDMXCSR or FXRSTOR clears a mask bit and sets the corresponding exception flag bit, a SIMD floating-point
exception will not be generated as a result of this change. The unmasked exception will be generated only upon the
execution of the next SSE/SSE2/SSE3 instruction that detects the unmasked exception condition.
For more information about the use of the SIMD floating-point exception mask and flag bits, see Section 11.5,
“SSE, SSE2, and SSE3 Exceptions,” and Section 12.8, “SSE3/SSSE3 And SSE4 Exceptions.”
10.2.3.2
SIMD Floating-Point Rounding Control Field
Bits 13 and 14 of the MXCSR register (the rounding control [RC] field) control how the results of SIMD floating-point
instructions are rounded. See Section 4.8.4, “Rounding,” for a description of the function and encoding of the
rounding control bits.
10.2.3.3
Flush-To-Zero
Bit 15 (FZ) of the MXCSR register enables the flush-to-zero mode, which controls the masked response to a SIMD
floating-point underflow condition. When the underflow exception is masked and the flush-to-zero mode is
enabled, the processor performs the following operations when it detects a floating-point underflow condition:
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•
•
Returns a zero result with the sign of the true result
Sets the precision and underflow exception flags
If the underflow exception is not masked, the flush-to-zero bit is ignored.
The flush-to-zero mode is not compatible with IEEE Standard 754. The IEEE-mandated masked response to underflow is to deliver the denormalized result (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”).
The flush-to-zero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster
execution can be achieved for applications where underflows are common and rounding the underflow result to
zero can be tolerated.
The flush-to-zero bit is cleared upon a power-up or reset of the processor, disabling the flush-to-zero mode.
10.2.3.4
Denormals-Are-Zeros
Bit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor’s response
to a SIMD floating-point denormal operand condition. When the denormals-are-zeros flag is set, the processor
converts all denormal source operands to a zero with the sign of the original operand before performing any
computations on them. The processor does not set the denormal-operand exception flag (DE), regardless of the
setting of the denormal-operand exception mask bit (DM); and it does not generate a denormal-operand exception
if the exception is unmasked.
The denormals-are-zeros mode is not compatible with IEEE Standard 754 (see Section 4.8.3.2, “Normalized and
Denormalized Finite Numbers”). The denormals-are-zeros mode is provided to improve processor performance for
applications such as streaming media processing, where rounding a denormal operand to zero does not appreciably affect the quality of the processed data.
The denormals-are-zeros flag is cleared upon a power-up or reset of the processor, disabling the denormals-arezeros mode.
The denormals-are-zeros mode was introduced in the Pentium 4 and Intel Xeon processor with the SSE2 extensions; however, it is fully compatible with the SSE SIMD floating-point instructions (that is, the denormals-arezeros flag affects the operation of the SSE SIMD floating-point instructions). In earlier IA-32 processors and in
some models of the Pentium 4 processor, this flag (bit 6) is reserved. See Section 11.6.3, “Checking for the DAZ
Flag in the MXCSR Register,” for instructions for detecting the availability of this feature.
Attempting to set bit 6 of the MXCSR register on processors that do not support the DAZ flag will cause a generalprotection exception (#GP). See Section 11.6.6, “Guidelines for Writing to the MXCSR Register,” for instructions for
preventing such general-protection exceptions by using the MXCSR_MASK value returned by the FXSAVE instruction.
10.2.4
Compatibility of SSE Extensions with SSE2/SSE3/MMX and the x87 FPU
The state (XMM registers and MXCSR register) introduced into the IA-32 execution environment with the SSE
extensions is shared with SSE2 and SSE3 extensions. SSE/SSE2/SSE3 instructions are fully compatible; they can
be executed together in the same instruction stream with no need to save state when switching between instruction sets.
XMM registers are independent of the x87 FPU and MMX registers, so SSE/SSE2/SSE3 operations performed on the
XMM registers can be performed in parallel with operations on the x87 FPU and MMX registers (see Section 11.6.7,
“Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions”).
The FXSAVE and FXRSTOR instructions save and restore the SSE/SSE2/SSE3 states along with the x87 FPU and
MMX state.
10.3
SSE DATA TYPES
SSE extensions introduced one data type, the 128-bit packed single-precision floating-point data type, to the IA32 architecture (see Figure 10-4). This data type consists of four IEEE 32-bit single-precision floating-point values
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packed into a double quadword. (See Figure 4-3 for the layout of a single-precision floating-point value; refer to
Section 4.2.2, “Floating-Point Data Types,” for a detailed description of the single-precision floating-point format.)
Contains 4 Single-Precision
Floating-Point Values
127
96 95
64 63
32 31
0
Figure 10-4. 128-Bit Packed Single-Precision Floating-Point Data Type
This 128-bit packed single-precision floating-point data type is operated on in the XMM registers or in memory.
Conversion instructions are provided to convert two packed single-precision floating-point values into two packed
doubleword integers or a scalar single-precision floating-point value into a doubleword integer (see Figure 11-8).
SSE extensions provide conversion instructions between XMM registers and MMX registers, and between XMM
registers and general-purpose bit registers. See Figure 11-8.
The address of a 128-bit packed memory operand must be aligned on a 16-byte boundary, except in the following
cases:
•
•
The MOVUPS instruction supports unaligned accesses.
Scalar instructions that use a 4-byte memory operand that is not subject to alignment requirements.
Figure 4-2 shows the byte order of 128-bit (double quadword) data types in memory.
10.4
SSE INSTRUCTION SET
SSE instructions are divided into four functional groups
•
•
•
•
Packed and scalar single-precision floating-point instructions
64-bit SIMD integer instructions
State management instructions
Cacheability control, prefetch, and memory ordering instructions
The following sections give an overview of each of the instructions in these groups.
10.4.1
SSE Packed and Scalar Floating-Point Instructions
The packed and scalar single-precision floating-point instructions are divided into the following subgroups:
•
•
•
•
•
•
Data movement instructions
Arithmetic instructions
Logical instructions
Comparison instructions
Shuffle instructions
Conversion instructions
The packed single-precision floating-point instructions perform SIMD operations on packed single-precision
floating-point operands (see Figure 10-5). Each source operand contains four single-precision floating-point
values, and the destination operand contains the results of the operation (OP) performed in parallel on the corresponding values (X0 and Y0, X1 and Y1, X2 and Y2, and X3 and Y3) in each operand.
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X3
X2
Y3
X1
Y2
X0
Y1
OP
OP
OP
X3 OP Y3
X2 OP Y2
X1 OP Y1
Y0
OP
X0 OP Y0
Figure 10-5. Packed Single-Precision Floating-Point Operation
The scalar single-precision floating-point instructions operate on the low (least significant) doublewords of the two
source operands (X0 and Y0); see Figure 10-6. The three most significant doublewords (X1, X2, and X3) of the first
source operand are passed through to the destination. The scalar operations are similar to the floating-point operations performed in the x87 FPU data registers with the precision control field in the x87 FPU control word set for
single precision (24-bit significand), except that x87 stack operations use a 15-bit exponent range for the result,
while SSE operations use an 8-bit exponent range.
X3
X2
Y3
Y2
X1
Y1
X0
Y0
OP
X3
X2
X1
X0 OP Y0
Figure 10-6. Scalar Single-Precision Floating-Point Operation
10.4.1.1
SSE Data Movement Instructions
SSE data movement instructions move single-precision floating-point data between XMM registers and between an
XMM register and memory.
The MOVAPS (move aligned packed single-precision floating-point values) instruction transfers a double quadword
operand containing four packed single-precision floating-point values from memory to an XMM register and vice
versa, or between XMM registers. The memory address must be aligned to a 16-byte boundary; otherwise, a
general-protection exception (#GP) is generated.
The MOVUPS (move unaligned packed single-precision, floating-point) instruction performs the same operations as
the MOVAPS instruction, except that 16-byte alignment of a memory address is not required.
The MOVSS (move scalar single-precision floating-point) instruction transfers a 32-bit single-precision floatingpoint operand from memory to the low doubleword of an XMM register and vice versa, or between XMM registers.
The MOVLPS (move low packed single-precision floating-point) instruction moves two packed single-precision
floating-point values from memory to the low quadword of an XMM register and vice versa. The high quadword of
the register is left unchanged.
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The MOVHPS (move high packed single-precision floating-point) instruction moves two packed single-precision
floating-point values from memory to the high quadword of an XMM register and vice versa. The low quadword of
the register is left unchanged.
The MOVLHPS (move packed single-precision floating-point low to high) instruction moves two packed single-precision floating-point values from the low quadword of the source XMM register into the high quadword of the destination XMM register. The low quadword of the destination register is left unchanged.
The MOVHLPS (move packed single-precision floating-point high to low) instruction moves two packed single-precision floating-point values from the high quadword of the source XMM register into the low quadword of the destination XMM register. The high quadword of the destination register is left unchanged.
The MOVMSKPS (move packed single-precision floating-point mask) instruction transfers the most significant bit of
each of the four packed single-precision floating-point numbers in an XMM register to a general-purpose register.
This 4-bit value can then be used as a condition to perform branching.
10.4.1.2
SSE Arithmetic Instructions
SSE arithmetic instructions perform addition, subtraction, multiply, divide, reciprocal, square root, reciprocal of
square root, and maximum/minimum operations on packed and scalar single-precision floating-point values.
The ADDPS (add packed single-precision floating-point values) and SUBPS (subtract packed single-precision
floating-point values) instructions add and subtract, respectively, two packed single-precision floating-point operands.
The ADDSS (add scalar single-precision floating-point values) and SUBSS (subtract scalar single-precision floatingpoint values) instructions add and subtract, respectively, the low single-precision floating-point values of two operands and store the result in the low doubleword of the destination operand.
The MULPS (multiply packed single-precision floating-point values) instruction multiplies two packed single-precision floating-point operands.
The MULSS (multiply scalar single-precision floating-point values) instruction multiplies the low single-precision
floating-point values of two operands and stores the result in the low doubleword of the destination operand.
The DIVPS (divide packed, single-precision floating-point values) instruction divides two packed single-precision
floating-point operands.
The DIVSS (divide scalar single-precision floating-point values) instruction divides the low single-precision floatingpoint values of two operands and stores the result in the low doubleword of the destination operand.
The RCPPS (compute reciprocals of packed single-precision floating-point values) instruction computes the approximate reciprocals of values in a packed single-precision floating-point operand.
The RCPSS (compute reciprocal of scalar single-precision floating-point values) instruction computes the approximate reciprocal of the low single-precision floating-point value in the source operand and stores the result in the
low doubleword of the destination operand.
The SQRTPS (compute square roots of packed single-precision floating-point values) instruction computes the
square roots of the values in a packed single-precision floating-point operand.
The SQRTSS (compute square root of scalar single-precision floating-point values) instruction computes the square
root of the low single-precision floating-point value in the source operand and stores the result in the low doubleword of the destination operand.
The RSQRTPS (compute reciprocals of square roots of packed single-precision floating-point values) instruction
computes the approximate reciprocals of the square roots of the values in a packed single-precision floating-point
operand.
The RSQRTSS (reciprocal of square root of scalar single-precision floating-point value) instruction computes the
approximate reciprocal of the square root of the low single-precision floating-point value in the source operand and
stores the result in the low doubleword of the destination operand.
The MAXPS (return maximum of packed single-precision floating-point values) instruction compares the corresponding values from two packed single-precision floating-point operands and returns the numerically greater
value from each comparison to the destination operand.
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The MAXSS (return maximum of scalar single-precision floating-point values) instruction compares the low values
from two packed single-precision floating-point operands and returns the numerically greater value from the
comparison to the low doubleword of the destination operand.
The MINPS (return minimum of packed single-precision floating-point values) instruction compares the corresponding values from two packed single-precision floating-point operands and returns the numerically lesser value
from each comparison to the destination operand.
The MINSS (return minimum of scalar single-precision floating-point values) instruction compares the low values
from two packed single-precision floating-point operands and returns the numerically lesser value from the
comparison to the low doubleword of the destination operand.
10.4.2
SSE Logical Instructions
SSE logical instructions perform AND, AND NOT, OR, and XOR operations on packed single-precision floating-point
values.
The ANDPS (bitwise logical AND of packed single-precision floating-point values) instruction returns the logical
AND of two packed single-precision floating-point operands.
The ANDNPS (bitwise logical AND NOT of packed single-precision, floating-point values) instruction returns the
logical AND NOT of two packed single-precision floating-point operands.
The ORPS (bitwise logical OR of packed single-precision, floating-point values) instruction returns the logical OR of
two packed single-precision floating-point operands.
The XORPS (bitwise logical XOR of packed single-precision, floating-point values) instruction returns the logical
XOR of two packed single-precision floating-point operands.
10.4.2.1
SSE Comparison Instructions
The compare instructions compare packed and scalar single-precision floating-point values and return the results
of the comparison either to the destination operand or to the EFLAGS register.
The CMPPS (compare packed single-precision floating-point values) instruction compares the corresponding values
from two packed single-precision floating-point operands, using an immediate operand as a predicate, and returns
a 32-bit mask result of all 1s or all 0s for each comparison to the destination operand. The value of the immediate
operand allows the selection of any of 8 compare conditions: equal, less than, less than equal, unordered, not
equal, not less than, not less than or equal, or ordered.
The CMPSS (compare scalar single-precision, floating-point values) instruction compares the low values from two
packed single-precision floating-point operands, using an immediate operand as a predicate, and returns a 32-bit
mask result of all 1s or all 0s for the comparison to the low doubleword of the destination operand. The immediate
operand selects the compare conditions as with the CMPPS instruction.
The COMISS (compare scalar single-precision floating-point values and set EFLAGS) and UCOMISS (unordered
compare scalar single-precision floating-point values and set EFLAGS) instructions compare the low values of two
packed single-precision floating-point operands and set the ZF, PF, and CF flags in the EFLAGS register to show the
result (greater than, less than, equal, or unordered). These two instructions differ as follows: the COMISS instruction signals a floating-point invalid-operation (#I) exception when a source operand is either a QNaN or an SNaN;
the UCOMISS instruction only signals an invalid-operation exception when a source operand is an SNaN.
10.4.2.2
SSE Shuffle and Unpack Instructions
SSE shuffle and unpack instructions shuffle or interleave the contents of two packed single-precision floating-point
values and store the results in the destination operand.
The SHUFPS (shuffle packed single-precision floating-point values) instruction places any two of the four packed
single-precision floating-point values from the destination operand into the two low-order doublewords of the
destination operand, and places any two of the four packed single-precision floating-point values from the source
operand in the two high-order doublewords of the destination operand (see Figure 10-7). By using the same
register for the source and destination operands, the SHUFPS instruction can shuffle four single-precision floatingpoint values into any order.
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DEST
X3
SRC
Y3
DEST
Y3 ... Y0
X2
Y2
Y3 ... Y0
X1
Y1
X0
Y0
X3 ... X0
X3 ... X0
Figure 10-7. SHUFPS Instruction, Packed Shuffle Operation
The UNPCKHPS (unpack and interleave high packed single-precision floating-point values) instruction performs an
interleaved unpack of the high-order single-precision floating-point values from the source and destination operands and stores the result in the destination operand (see Figure 10-8).
DEST
X3
X2
X1
X0
SRC
Y3
Y2
Y1
Y0
DEST
Y3
X3
Y2
X2
Figure 10-8. UNPCKHPS Instruction, High Unpack and Interleave Operation
The UNPCKLPS (unpack and interleave low packed single-precision floating-point values) instruction performs an
interleaved unpack of the low-order single-precision floating-point values from the source and destination operands and stores the result in the destination operand (see Figure 10-9).
DEST
X3
X2
X1
SRC
Y3
Y2
Y1
DEST
Y1
X1
Y0
X0
Y0
X0
Figure 10-9. UNPCKLPS Instruction, Low Unpack and Interleave Operation
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10.4.3
SSE Conversion Instructions
SSE conversion instructions (see Figure 11-8) support packed and scalar conversions between single-precision
floating-point and doubleword integer formats.
The CVTPI2PS (convert packed doubleword integers to packed single-precision floating-point values) instruction
converts two packed signed doubleword integers into two packed single-precision floating-point values. When the
conversion is inexact, the result is rounded according to the rounding mode selected in the MXCSR register.
The CVTSI2SS (convert doubleword integer to scalar single-precision floating-point value) instruction converts a
signed doubleword integer into a single-precision floating-point value. When the conversion is inexact, the result is
rounded according to the rounding mode selected in the MXCSR register.
The CVTPS2PI (convert packed single-precision floating-point values to packed doubleword integers) instruction
converts two packed single-precision floating-point values into two packed signed doubleword integers. When the
conversion is inexact, the result is rounded according to the rounding mode selected in the MXCSR register. The
CVTTPS2PI (convert with truncation packed single-precision floating-point values to packed doubleword integers)
instruction is similar to the CVTPS2PI instruction, except that truncation is used to round a source value to an
integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2 Conversion Instructions”).
The CVTSS2SI (convert scalar single-precision floating-point value to doubleword integer) instruction converts a
single-precision floating-point value into a signed doubleword integer. When the conversion is inexact, the result is
rounded according to the rounding mode selected in the MXCSR register. The CVTTSS2SI (convert with truncation
scalar single-precision floating-point value to doubleword integer) instruction is similar to the CVTSS2SI instruction, except that truncation is used to round the source value to an integer value (see Section 4.8.4.2, “Truncation
with SSE and SSE2 Conversion Instructions”).
10.4.4
SSE 64-Bit SIMD Integer Instructions
SSE extensions add the following 64-bit packed integer instructions to the IA-32 architecture. These instructions
operate on data in MMX registers and 64-bit memory locations.
NOTE
When SSE2 extensions are present in an IA-32 processor, these instructions are extended to
operate on 128-bit operands in XMM registers and 128-bit memory locations.
The PAVGB (compute average of packed unsigned byte integers) and PAVGW (compute average of packed
unsigned word integers) instructions compute a SIMD average of two packed unsigned byte or word integer operands, respectively. For each corresponding pair of data elements in the packed source operands, the elements are
added together, a 1 is added to the temporary sum, and that result is shifted right one bit position.
The PEXTRW (extract word) instruction copies a selected word from an MMX register into a general-purpose
register.
The PINSRW (insert word) instruction copies a word from a general-purpose register or from memory into a
selected word location in an MMX register.
The PMAXUB (maximum of packed unsigned byte integers) instruction compares the corresponding unsigned byte
integers in two packed operands and returns the greater of each comparison to the destination operand.
The PMINUB (minimum of packed unsigned byte integers) instruction compares the corresponding unsigned byte
integers in two packed operands and returns the lesser of each comparison to the destination operand.
The PMAXSW (maximum of packed signed word integers) instruction compares the corresponding signed word
integers in two packed operands and returns the greater of each comparison to the destination operand.
The PMINSW (minimum of packed signed word integers) instruction compares the corresponding signed word integers in two packed operands and returns the lesser of each comparison to the destination operand.
The PMOVMSKB (move byte mask) instruction creates an 8-bit mask from the packed byte integers in an MMX
register and stores the result in the low byte of a general-purpose register. The mask contains the most significant
bit of each byte in the MMX register. (When operating on 128-bit operands, a 16-bit mask is created.)
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The PMULHUW (multiply packed unsigned word integers and store high result) instruction performs a SIMD
unsigned multiply of the words in the two source operands and returns the high word of each result to an MMX
register.
The PSADBW (compute sum of absolute differences) instruction computes the SIMD absolute differences of the
corresponding unsigned byte integers in two source operands, sums the differences, and stores the sum in the low
word of the destination operand.
The PSHUFW (shuffle packed word integers) instruction shuffles the words in the source operand according to the
order specified by an 8-bit immediate operand and returns the result to the destination operand.
10.4.5
MXCSR State Management Instructions
The MXCSR state management instructions (LDMXCSR and STMXCSR) load and save the state of the MXCSR
register, respectively. The LDMXCSR instruction loads the MXCSR register from memory, while the STMXCSR
instruction stores the contents of the register to memory.
10.4.6
Cacheability Control, Prefetch, and Memory Ordering Instructions
SSE extensions introduce several new instructions to give programs more control over the caching of data. They
also introduces the PREFETCHh instructions, which provide the ability to prefetch data to a specified cache level,
and the SFENCE instruction, which enforces program ordering on stores. These instructions are described in the
following sections.
10.4.6.1
Cacheability Control Instructions
The following three instructions enable data from the MMX and XMM registers to be stored to memory using a nontemporal hint. The non-temporal hint directs the processor to store the data to memory without writing the data
into the cache hierarchy. See Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data,” for information
about non-temporal stores and hints.
The MOVNTQ (store quadword using non-temporal hint) instruction stores packed integer data from an MMX
register to memory, using a non-temporal hint.
The MOVNTPS (store packed single-precision floating-point values using non-temporal hint) instruction stores
packed floating-point data from an XMM register to memory, using a non-temporal hint.
The MASKMOVQ (store selected bytes of quadword) instruction stores selected byte integers from an MMX register
to memory, using a byte mask to selectively write the individual bytes. This instruction also uses a non-temporal
hint.
10.4.6.2
Caching of Temporal vs. Non-Temporal Data
Data referenced by a program can be temporal (data will be used again) or non-temporal (data will be referenced
once and not reused in the immediate future). For example, program code is generally temporal, whereas, multimedia data, such as the display list in a 3-D graphics application, is often non-temporal. To make efficient use of
the processor’s caches, it is generally desirable to cache temporal data and not cache non-temporal data. Overloading the processor’s caches with non-temporal data is sometimes referred to as “polluting the caches.” The SSE
and SSE2 cacheability control instructions enable a program to write non-temporal data to memory in a manner
that minimizes pollution of caches.
These SSE and SSE2 non-temporal store instructions minimize cache pollutions by treating the memory being
accessed as the write combining (WC) type. If a program specifies a non-temporal store with one of these instructions and the memory type of the destination region is write back (WB), write through (WT), or write combining
(WC), the processor will do the following:
•
If the memory location being written to is present in the cache hierarchy, the data in the caches is evicted.1
1. Some older CPU implementations (e.g., Pentium M) allowed addresses being written with a non-temporal store instruction to be
updated in-place if the memory type was not WC and line was already in the cache.
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•
The non-temporal data is written to memory with WC semantics.
See also: Chapter 11, “Memory Cache Control,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
Using the WC semantics, the store transaction will be weakly ordered, meaning that the data may not be written to
memory in program order, and the store will not write allocate (that is, the processor will not fetch the corresponding cache line into the cache hierarchy, prior to performing the store). Also, different processor implementations may choose to collapse and combine these stores.
The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in uncacheable memory. Uncacheable as referred to here means that the region
being written to has been mapped with either an uncacheable (UC) or write protected (WP) memory type.
In general, WC semantics require software to ensure coherence, with respect to other processors and other system
agents (such as graphics cards). Appropriate use of synchronization and fencing must be performed for producerconsumer usage models. Fencing ensures that all system agents have global visibility of the stored data; for
instance, failure to fence may result in a written cache line staying within a processor and not being visible to other
agents.
The memory type visible on the bus in the presence of memory type aliasing is implementation specific. As one
possible example, the memory type written to the bus may reflect the memory type for the first store to this line,
as seen in program order; other alternatives are possible. This behavior should be considered reserved, and
dependence on the behavior of any particular implementation risks future incompatibility.
NOTE
Some older CPU implementations (e.g., Pentium M) may implement non-temporal stores by
updating in place data that already reside in the cache hierarchy. For such processors, the
destination region should also be mapped as WC. If mapped as WB or WT, there is the potential for
speculative processor reads to bring the data into the caches; in this case, non-temporal stores
would then update in place, and data would not be flushed from the processor by a subsequent
fencing operation.
10.4.6.3
PREFETCHh Instructions
The PREFETCHh instructions permit programs to load data into the processor at a suggested cache level, so that
the data is closer to the processor’s load and store unit when it is needed. These instructions fetch 32 aligned bytes
(or more, depending on the implementation) containing the addressed byte to a location in the cache hierarchy
specified by the temporal locality hint (see Table 10-1). In this table, the first-level cache is closest to the processor
and second-level cache is farther away from the processor than the first-level cache. The hints specify a prefetch
of either temporal or non-temporal data (see Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data”).
Subsequent accesses to temporal data are treated like normal accesses, while those to non-temporal data will
continue to minimize cache pollution. If the data is already present at a level of the cache hierarchy that is closer
to the processor, the PREFETCHh instruction will not result in any data movement. The PREFETCHh instructions do
not affect functional behavior of the program.
See Section 11.6.13, “Cacheability Hint Instructions,” for additional information about the PREFETCHh instructions.
Table 10-1. PREFETCHh Instructions Caching Hints
PREFETCHh Instruction
Mnemonic
PREFETCHT0
Actions
Temporal data—fetch data into all levels of cache hierarchy:
• Pentium III processor—1st-level cache or 2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
PREFETCHT1
Temporal data—fetch data into level 2 cache and higher
• Pentium III processor—2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
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Table 10-1. PREFETCHh Instructions Caching Hints (Contd.)
PREFETCHh Instruction
Mnemonic
PREFETCHT2
Actions
Temporal data—fetch data into level 2 cache and higher
• Pentium III processor—2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
PREFETCHNTA
Non-temporal data—fetch data into location close to the processor, minimizing cache pollution
• Pentium III processor—1st-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
10.4.6.4
SFENCE Instruction
The SFENCE (Store Fence) instruction controls write ordering by creating a fence for memory store operations. This
instruction guarantees that the result of every store instruction that precedes the store fence in program order is
globally visible before any store instruction that follows the fence. The SFENCE instruction provides an efficient way
of ensuring ordering between procedures that produce weakly-ordered data and procedures that consume that
data.
10.5
FXSAVE AND FXRSTOR INSTRUCTIONS
The FXSAVE and FXRSTOR instructions were introduced into the IA-32 architecture in the Pentium II processor
family (prior to the introduction of the SSE extensions). The original versions of these instructions performed a fast
save and restore, respectively, of the x87 execution environment (x87 state). (By saving the state of the x87 FPU
data registers, the FXSAVE and FXRSTOR instructions implicitly save and restore the state of the MMX registers.)
The SSE extensions expanded the scope of these instructions to save and restore the states of the XMM registers
and the MXCSR register (SSE state), along with x87 state.
The FXSAVE and FXRSTOR instructions can be used in place of the FSAVE/FNSAVE and FRSTOR instructions;
however, the operation of the FXSAVE and FXRSTOR instructions are not identical to the operation of
FSAVE/FNSAVE and FRSTOR.
NOTE
The FXSAVE and FXRSTOR instructions are not considered part of the SSE instruction group. They
have a separate CPUID feature bit to indicate whether they are present (if
CPUID.01H:EDX.FXSR[bit 24] = 1).
The CPUID feature bit for SSE extensions does not indicate the presence of FXSAVE and FXRSTOR.
The FXSAVE and FXRSTOR instructions organize x87 state and SSE state in a region of memory called the FXSAVE
area. Section 10.5.1 provides details of the FXSAVE area and its format. Section 10.5.2 describes operation of
FXSAVE, and Section 10.5.3 describes the operation of FXRSTOR.
10.5.1
FXSAVE Area
The FXSAVE and FXRSTOR instructions organize x87 state and SSE state in a region of memory called the FXSAVE
area. Each of the instructions takes a memory operand that specifies the 16-byte aligned base address of the
FXSAVE area on which it operates.
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Every FXSAVE area comprises the 512 bytes starting at the area’s base address. Table 10-2 illustrates the format
of the first 416 bytes of the legacy region of an FXSAVE area.
Table 10-2. Format of an FXSAVE Area
15
14
Reserved
13
12
CS or FPU
IP bits 63:32
MXCSR_MASK
11
10
9
8
7
6
FPU IP bits 31:0
FOP
MXCSR
Reserved
5
4
Rsvd.
FTW
DS or
FPU DP
bits 63:32
3
2
FSW
1
0
FCW
FPU DP bits 31:0
0
16
Reserved
ST0/MM0
32
Reserved
ST1/MM1
48
Reserved
ST2/MM2
64
Reserved
ST3/MM3
80
Reserved
ST4/MM4
96
Reserved
ST5/MM5
112
Reserved
ST6/MM6
128
Reserved
ST7/MM7
144
XMM0
160
XMM1
176
XMM2
192
XMM3
208
XMM4
224
XMM5
240
XMM6
256
XMM7
272
XMM8
288
XMM9
304
XMM10
320
XMM11
336
XMM12
352
XMM13
368
XMM14
384
XMM15
400
The x87 state component comprises bytes 23:0 and bytes 159:32. The SSE state component comprises
bytes 31:24 and bytes 415:160. FXSAVE and FXRSTOR do not use bytes 511:416; bytes 463:416 are reserved.
Section 10.5.2 and Section 10.5.3 provide details of how FXSAVE and FXRSTOR use an FXSAVE area.
10.5.1.1
x87 State
Table 10-2 illustrates how FXSAVE and FXRSTOR organize x87 state and SSE state; the x87 state is listed below,
along with details of its interactions with FXSAVE and FXRSTOR:
•
Bytes 1:0, 3:2, and 7:6 are used for x87 FPU Control Word (FCW), x87 FPU Status Word (FSW), and x87 FPU
Opcode (FOP), respectively.
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•
Byte 4 is used for an abridged version of the x87 FPU Tag Word (FTW). The following items describe its usage:
— For each j, 0 ≤ j ≤ 7, FXSAVE saves a 0 into bit j of byte 4 if x87 FPU data register STj has a empty tag;
otherwise, FXSAVE saves a 1 into bit j of byte 4.
— For each j, 0 ≤ j ≤ 7, FXRSTOR establishes the tag value for x87 FPU data register STj as follows. If bit j of
byte 4 is 0, the tag for STj in the tag register for that data register is marked empty (11B); otherwise, the
x87 FPU sets the tag for STj based on the value being loaded into that register (see below).
•
Bytes 15:8 are used as follows:
— If the instruction has no REX prefix, or if REX.W = 0:
•
•
•
Bytes 11:8 are used for bits 31:0 of the x87 FPU Instruction Pointer Offset (FIP).
If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0, bytes 13:12 are used for x87 FPU Instruction Pointer
Selector (FPU CS). Otherwise, the processor deprecates the FPU CS value: FXSAVE saves it as 0000H.
Bytes 15:14 are not used.
— If the instruction has a REX prefix with REX.W = 1, bytes 15:8 are used for the full 64 bits of FIP.
•
Bytes 23:16 are used as follows:
— If the instruction has no REX prefix, or if REX.W = 0:
•
•
•
Bytes 19:16 are used for bits 31:0 of the x87 FPU Data Pointer Offset (FDP).
If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0, bytes 21:20 are used for x87 FPU Data Pointer Selector
(FPU DS). Otherwise, the processor deprecates the FPU DS value: FXSAVE saves it as 0000H.
Bytes 23:22 are not used.
— If the instruction has a REX prefix with REX.W = 1, bytes 23:16 are used for the full 64 bits of FDP.
•
•
Bytes 31:24 are used for SSE state (see Section 10.5.1.2).
Bytes 159:32 are used for the registers ST0–ST7 (MM0–MM7). Each of the 8 registers is allocated a 128-bit
region, with the low 80 bits used for the register and the upper 48 bits unused.
10.5.1.2
SSE State
Table 10-2 illustrates how FXSAVE and FXRSTOR organize x87 state and SSE state; the SSE state is listed below,
along with details of its interactions with FXSAVE and FXRSTOR:
•
•
Bytes 23:0 are used for x87 state (see Section 10.5.1.1).
•
•
•
•
Bytes 31:28 are used for the MXCSR_MASK value. FXRSTOR ignores this field.
Bytes 27:24 are used for the MXCSR register. FXRSTOR generates a general-protection fault (#GP) in response
to an attempt to set any of the reserved bits in the MXCSR register.
Bytes 159:32 are used for x87 state.
Bytes 287:160 are used for the registers XMM0–XMM7.
Bytes 415:288 are used for the registers XMM8–XMM15. These fields are used only in 64-bit mode. Executions
of FXSAVE outside 64-bit mode do not write to these bytes; executions of FXRSTOR outside 64-bit mode do not
read these bytes and do not update XMM8–XMM15.
If CR4.OSFXSR = 0, FXSAVE and FXRSTOR may or may not operate on SSE state; this behavior is implementation
dependent. Moreover, SSE instructions cannot be used unless CR4.OSFXSR = 1.
10.5.2
Operation of FXSAVE
The FXSAVE instruction takes a single memory operand, which is an FXSAVE area. The instruction stores x87 state
and SSE state to the FXSAVE area. See Section 10.5.1.1 and Section 10.5.1.2 for details regarding mode-specific
operation and operation determined by instruction prefixes.
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10.5.3
Operation of FXRSTOR
The FXRSTOR instruction takes a single memory operand, which is an FXSAVE area. If the value at bytes 27:24 of
the FXSAVE area is not a legal value for the MXCSR register (e.g., the value sets reserved bits). Otherwise, the
instruction loads x87 state and SSE state rom the FXSAVE area. See Section 10.5.1.1 and Section 10.5.1.2 for
details regarding mode-specific operation and operation determined by instruction prefixes.
10.6
HANDLING SSE INSTRUCTION EXCEPTIONS
See Section 11.5, “SSE, SSE2, and SSE3 Exceptions,” for a detailed discussion of the general and SIMD floatingpoint exceptions that can be generated with the SSE instructions and for guidelines for handling these exceptions
when they occur.
10.7
WRITING APPLICATIONS WITH THE SSE EXTENSIONS
See Section 11.6, “Writing Applications with SSE/SSE2 Extensions,” for additional information about writing applications and operating-system code using the SSE extensions.
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CHAPTER 11
PROGRAMMING WITH INTEL®
STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
The streaming SIMD extensions 2 (SSE2) were introduced into the IA-32 architecture in the Pentium 4 and Intel
Xeon processors. These extensions enhance the performance of IA-32 processors for advanced 3-D graphics, video
decoding/encoding, speech recognition, E-commerce, Internet, scientific, and engineering applications.
This chapter describes the SSE2 extensions and provides information to assist in writing application programs that
use these and the SSE extensions.
11.1
OVERVIEW OF SSE2 EXTENSIONS
SSE2 extensions use the single instruction multiple data (SIMD) execution model that is used with MMX technology
and SSE extensions. They extend this model with support for packed double-precision floating-point values and for
128-bit packed integers.
If CPUID.01H:EDX.SSE2[bit 26] = 1, SSE2 extensions are present.
SSE2 extensions add the following features to the IA-32 architecture, while maintaining backward compatibility
with all existing IA-32 processors, applications and operating systems.
•
Six data types:
— 128-bit packed double-precision floating-point (two IEEE Standard 754 double-precision floating-point
values packed into a double quadword)
— 128-bit packed byte integers
— 128-bit packed word integers
— 128-bit packed doubleword integers
— 128-bit packed quadword integers
•
Instructions to support the additional data types and extend existing SIMD integer operations:
— Packed and scalar double-precision floating-point instructions
— Additional 64-bit and 128-bit SIMD integer instructions
— 128-bit versions of SIMD integer instructions introduced with the MMX technology and the SSE extensions
— Additional cacheability-control and instruction-ordering instructions
•
Modifications to existing IA-32 instructions to support SSE2 features:
— Extensions and modifications to the CPUID instruction
— Modifications to the RDPMC instruction
These new features extend the IA-32 architecture’s SIMD programming model in three important ways:
•
They provide the ability to perform SIMD operations on pairs of packed double-precision floating-point values.
This permits higher precision computations to be carried out in XMM registers, which enhances processor
performance in scientific and engineering applications and in applications that use advanced 3-D geometry
techniques (such as ray tracing). Additional flexibility is provided with instructions that operate on single
(scalar) double-precision floating-point values located in the low quadword of an XMM register.
•
They provide the ability to operate on 128-bit packed integers (bytes, words, doublewords, and quadwords) in
XMM registers. This provides greater flexibility and greater throughput when performing SIMD operations on
packed integers. The capability is particularly useful for applications such as RSA authentication and RC5
encryption. Using the full set of SIMD registers, data types, and instructions provided with the MMX technology
and SSE/SSE2 extensions, programmers can develop algorithms that finely mix packed single- and doubleprecision floating-point data and 64- and 128-bit packed integer data.
•
SSE2 extensions enhance the support introduced with SSE extensions for controlling the cacheability of SIMD
data. SSE2 cache control instructions provide the ability to stream data in and out of the XMM registers without
polluting the caches and the ability to prefetch data before it is actually used.
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SSE2 extensions are fully compatible with all software written for IA-32 processors. All existing software continues
to run correctly, without modification, on processors that incorporate SSE2 extensions, as well as in the presence
of applications that incorporate these extensions. Enhancements to the CPUID instruction permit detection of the
SSE2 extensions. Also, because the SSE2 extensions use the same registers as the SSE extensions, no new operating-system support is required for saving and restoring program state during a context switch beyond that
provided for the SSE extensions.
SSE2 extensions are accessible from all IA-32 execution modes: protected mode, real address mode, virtual 8086
mode.
The following sections in this chapter describe the programming environment for SSE2 extensions including: the
128-bit XMM floating-point register set, data types, and SSE2 instructions. It also describes exceptions that can be
generated with the SSE and SSE2 instructions and gives guidelines for writing applications with SSE and SSE2
extensions.
For additional information about SSE2 extensions, see:
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, provide a detailed
description of individual SSE3 instructions.
•
Chapter 13, “System Programming for Instruction Set Extensions and Processor Extended States,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating
the SSE and SSE2 extensions into an operating-system environment.
11.2
SSE2 PROGRAMMING ENVIRONMENT
Figure 11-1 shows the programming environment for SSE2 extensions. No new registers or other instruction
execution state are defined with SSE2 extensions. SSE2 instructions use the XMM registers, the MMX registers,
and/or IA-32 general-purpose registers, as follows:
•
XMM registers — These eight registers (see Figure 10-2) are used to operate on packed or scalar doubleprecision floating-point data. Scalar operations are operations performed on individual (unpacked) doubleprecision floating-point values stored in the low quadword of an XMM register. XMM registers are also used to
perform operations on 128-bit packed integer data. They are referenced by the names XMM0 through XMM7.
Address Space
2
XMM Registers
Eight 128-Bit
MXCSR Register
32
-1
32 Bits
MMX Registers
Eight 64-Bit
General-Purpose
Registers
Eight 32-Bit
0
EFLAGS Register
32 Bits
Figure 11-1. Steaming SIMD Extensions 2 Execution Environment
•
MXCSR register — This 32-bit register (see Figure 10-3) provides status and control bits used in floating-point
operations. The denormals-are-zeros and flush-to-zero flags in this register provide a higher performance
alternative for the handling of denormal source operands and denormal (underflow) results. For more
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information on the functions of these flags see Section 10.2.3.4, “Denormals-Are-Zeros,” and Section 10.2.3.3,
“Flush-To-Zero.”
•
MMX registers — These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed
integer data. They are also used to hold operands for some operations performed between MMX and XMM
registers. MMX registers are referenced by the names MM0 through MM7.
•
General-purpose registers — The eight general-purpose registers (see Figure 3-5) are used along with the
existing IA-32 addressing modes to address operands in memory. MMX and XMM registers cannot be used to
address memory. The general-purpose registers are also used to hold operands for some SSE2 instructions.
These registers are referenced by the names EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.
•
EFLAGS register — This 32-bit register (see Figure 3-8) is used to record the results of some compare
operations.
11.2.1
SSE2 in 64-Bit Mode and Compatibility Mode
In compatibility mode, SSE2 extensions function like they do in protected mode. In 64-bit mode, eight additional
XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes.
Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5.
Some SSE2 instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access 64bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.
11.2.2
Compatibility of SSE2 Extensions with SSE, MMX
Technology and x87 FPU Programming Environment
SSE2 extensions do not introduce any new state to the IA-32 execution environment beyond that of SSE. SSE2
extensions represent an enhancement of SSE extensions; they are fully compatible and share the same state information. SSE and SSE2 instructions can be executed together in the same instruction stream without the need to
save state when switching between instruction sets.
XMM registers are independent of the x87 FPU and MMX registers; so SSE and SSE2 operations performed on XMM
registers can be performed in parallel with x87 FPU or MMX technology operations (see Section 11.6.7, “Interaction
of SSE/SSE2 Instructions with x87 FPU and MMX Instructions”).
The FXSAVE and FXRSTOR instructions save and restore the SSE and SSE2 states along with the x87 FPU and MMX
states.
11.2.3
Denormals-Are-Zeros Flag
The denormals-are-zeros flag (bit 6 in the MXCSR register) was introduced into the IA-32 architecture with the
SSE2 extensions. See Section 10.2.3.4, “Denormals-Are-Zeros,” for a description of this flag.
11.3
SSE2 DATA TYPES
SSE2 extensions introduced one 128-bit packed floating-point data type and four 128-bit SIMD integer data types
to the IA-32 architecture (see Figure 11-2).
•
Packed double-precision floating-point — This 128-bit data type consists of two IEEE 64-bit doubleprecision floating-point values packed into a double quadword. (See Figure 4-3 for the layout of a 64-bit
double-precision floating-point value; refer to Section 4.2.2, “Floating-Point Data Types,” for a detailed
description of double-precision floating-point values.)
•
128-bit packed integers — The four 128-bit packed integer data types can contain 16 byte integers, 8 word
integers, 4 doubleword integers, or 2 quadword integers. (Refer to Section 4.6.2, “128-Bit Packed SIMD Data
Types,” for a detailed description of the 128-bit packed integers.)
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128-Bit Packed DoublePrecision Floating-Point
127
64 63
0
128-Bit Packed Byte Integers
127
0
128-Bit Packed Word Integers
127
0
128-Bit Packed Doubleword
Integers
127
0
128-Bit Packed Quadword
Integers
127
0
Figure 11-2. Data Types Introduced with the SSE2 Extensions
All of these data types are operated on in XMM registers or memory. Instructions are provided to convert between
these 128-bit data types and the 64-bit and 32-bit data types.
The address of a 128-bit packed memory operand must be aligned on a 16-byte boundary, except in the following
cases:
•
•
a MOVUPD instruction which supports unaligned accesses
scalar instructions that use an 8-byte memory operand that is not subject to alignment requirements
Figure 4-2 shows the byte order of 128-bit (double quadword) and 64-bit (quadword) data types in memory.
11.4
SSE2 INSTRUCTIONS
The SSE2 instructions are divided into four functional groups:
•
•
•
•
Packed and scalar double-precision floating-point instructions
64-bit and 128-bit SIMD integer instructions
128-bit extensions of SIMD integer instructions introduced with the MMX technology and the SSE extensions
Cacheability-control and instruction-ordering instructions
The following sections provide more information about each group.
11.4.1
Packed and Scalar Double-Precision Floating-Point Instructions
The packed and scalar double-precision floating-point instructions are divided into the following sub-groups:
•
•
•
•
•
•
Data movement instructions
Arithmetic instructions
Comparison instructions
Conversion instructions
Logical instructions
Shuffle instructions
The packed double-precision floating-point instructions perform SIMD operations similarly to the packed singleprecision floating-point instructions (see Figure 11-3). Each source operand contains two double-precision
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floating-point values, and the destination operand contains the results of the operation (OP) performed in parallel
on the corresponding values (X0 and Y0, and X1 and Y1) in each operand.
X1
Y1
X0
Y0
OP
OP
X1 OP Y1
X0 OP Y0
Figure 11-3. Packed Double-Precision Floating-Point Operations
The scalar double-precision floating-point instructions operate on the low (least significant) quadwords of two
source operands (X0 and Y0), as shown in Figure 11-4. The high quadword (X1) of the first source operand is
passed through to the destination. The scalar operations are similar to the floating-point operations performed in
x87 FPU data registers with the precision control field in the x87 FPU control word set for double precision (53-bit
significand), except that x87 stack operations use a 15-bit exponent range for the result while SSE2 operations use
an 11-bit exponent range.
See Section 11.6.8, “Compatibility of SIMD and x87 FPU Floating-Point Data Types,” for more information about
obtaining compatible results when performing both scalar double-precision floating-point operations in XMM registers and in x87 FPU data registers.
X1
Y1
X0
Y0
OP
X1
X0 OP Y0
Figure 11-4. Scalar Double-Precision Floating-Point Operations
11.4.1.1
Data Movement Instructions
Data movement instructions move double-precision floating-point data between XMM registers and between XMM
registers and memory.
The MOVAPD (move aligned packed double-precision floating-point) instruction transfers a 128-bit packed doubleprecision floating-point operand from memory to an XMM register or vice versa, or between XMM registers. The
memory address must be aligned to a 16-byte boundary; if not, a general-protection exception (GP#) is generated.
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The MOVUPD (move unaligned packed double-precision floating-point) instruction transfers a 128-bit packed
double-precision floating-point operand from memory to an XMM register or vice versa, or between XMM registers.
Alignment of the memory address is not required.
The MOVSD (move scalar double-precision floating-point) instruction transfers a 64-bit double-precision floatingpoint operand from memory to the low quadword of an XMM register or vice versa, or between XMM registers.
Alignment of the memory address is not required, unless alignment checking is enabled.
The MOVHPD (move high packed double-precision floating-point) instruction transfers a 64-bit double-precision
floating-point operand from memory to the high quadword of an XMM register or vice versa. The low quadword of
the register is left unchanged. Alignment of the memory address is not required, unless alignment checking is
enabled.
The MOVLPD (move low packed double-precision floating-point) instruction transfers a 64-bit double-precision
floating-point operand from memory to the low quadword of an XMM register or vice versa. The high quadword of
the register is left unchanged. Alignment of the memory address is not required, unless alignment checking is
enabled.
The MOVMSKPD (move packed double-precision floating-point mask) instruction extracts the sign bit of each of the
two packed double-precision floating-point numbers in an XMM register and saves them in a general-purpose
register. This 2-bit value can then be used as a condition to perform branching.
11.4.1.2
SSE2 Arithmetic Instructions
SSE2 arithmetic instructions perform addition, subtraction, multiply, divide, square root, and maximum/minimum
operations on packed and scalar double-precision floating-point values.
The ADDPD (add packed double-precision floating-point values) and SUBPD (subtract packed double-precision
floating-point values) instructions add and subtract, respectively, two packed double-precision floating-point operands.
The ADDSD (add scalar double-precision floating-point values) and SUBSD (subtract scalar double-precision
floating-point values) instructions add and subtract, respectively, the low double-precision floating-point values of
two operands and stores the result in the low quadword of the destination operand.
The MULPD (multiply packed double-precision floating-point values) instruction multiplies two packed doubleprecision floating-point operands.
The MULSD (multiply scalar double-precision floating-point values) instruction multiplies the low double-precision
floating-point values of two operands and stores the result in the low quadword of the destination operand.
The DIVPD (divide packed double-precision floating-point values) instruction divides two packed double-precision
floating-point operands.
The DIVSD (divide scalar double-precision floating-point values) instruction divides the low double-precision
floating-point values of two operands and stores the result in the low quadword of the destination operand.
The SQRTPD (compute square roots of packed double-precision floating-point values) instruction computes the
square roots of the values in a packed double-precision floating-point operand.
The SQRTSD (compute square root of scalar double-precision floating-point values) instruction computes the
square root of the low double-precision floating-point value in the source operand and stores the result in the low
quadword of the destination operand.
The MAXPD (return maximum of packed double-precision floating-point values) instruction compares the corresponding values in two packed double-precision floating-point operands and returns the numerically greater value
from each comparison to the destination operand.
The MAXSD (return maximum of scalar double-precision floating-point values) instruction compares the low
double-precision floating-point values from two packed double-precision floating-point operands and returns the
numerically higher value from the comparison to the low quadword of the destination operand.
The MINPD (return minimum of packed double-precision floating-point values) instruction compares the corresponding values from two packed double-precision floating-point operands and returns the numerically lesser value
from each comparison to the destination operand.
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The MINSD (return minimum of scalar double-precision floating-point values) instruction compares the low values
from two packed double-precision floating-point operands and returns the numerically lesser value from the
comparison to the low quadword of the destination operand.
11.4.1.3
SSE2 Logical Instructions
SSE2 logical instructions perform AND, AND NOT, OR, and XOR operations on packed double-precision floatingpoint values.
The ANDPD (bitwise logical AND of packed double-precision floating-point values) instruction returns the logical
AND of two packed double-precision floating-point operands.
The ANDNPD (bitwise logical AND NOT of packed double-precision floating-point values) instruction returns the
logical AND NOT of two packed double-precision floating-point operands.
The ORPD (bitwise logical OR of packed double-precision floating-point values) instruction returns the logical OR of
two packed double-precision floating-point operands.
The XORPD (bitwise logical XOR of packed double-precision floating-point values) instruction returns the logical
XOR of two packed double-precision floating-point operands.
11.4.1.4
SSE2 Comparison Instructions
SSE2 compare instructions compare packed and scalar double-precision floating-point values and return the
results of the comparison either to the destination operand or to the EFLAGS register.
The CMPPD (compare packed double-precision floating-point values) instruction compares the corresponding
values from two packed double-precision floating-point operands, using an immediate operand as a predicate, and
returns a 64-bit mask result of all 1s or all 0s for each comparison to the destination operand. The value of the
immediate operand allows the selection of any of eight compare conditions: equal, less than, less than equal, unordered, not equal, not less than, not less than or equal, or ordered.
The CMPSD (compare scalar double-precision floating-point values) instruction compares the low values from two
packed double-precision floating-point operands, using an immediate operand as a predicate, and returns a 64-bit
mask result of all 1s or all 0s for the comparison to the low quadword of the destination operand. The immediate
operand selects the compare condition as with the CMPPD instruction.
The COMISD (compare scalar double-precision floating-point values and set EFLAGS) and UCOMISD (unordered
compare scalar double-precision floating-point values and set EFLAGS) instructions compare the low values of two
packed double-precision floating-point operands and set the ZF, PF, and CF flags in the EFLAGS register to show the
result (greater than, less than, equal, or unordered). These two instructions differ as follows: the COMISD instruction signals a floating-point invalid-operation (#I) exception when a source operand is either a QNaN or an SNaN;
the UCOMISD instruction only signals an invalid-operation exception when a source operand is an SNaN.
11.4.1.5
SSE2 Shuffle and Unpack Instructions
SSE2 shuffle instructions shuffle the contents of two packed double-precision floating-point values and store the
results in the destination operand.
The SHUFPD (shuffle packed double-precision floating-point values) instruction places either of the two packed
double-precision floating-point values from the destination operand in the low quadword of the destination
operand, and places either of the two packed double-precision floating-point values from source operand in the
high quadword of the destination operand (see Figure 11-5). By using the same register for the source and destination operands, the SHUFPD instruction can swap two packed double-precision floating-point values.
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DEST
X1
SRC
Y1
DEST
Y1 or Y0
X0
Y0
X1 or X0
Figure 11-5. SHUFPD Instruction, Packed Shuffle Operation
The UNPCKHPD (unpack and interleave high packed double-precision floating-point values) instruction performs an
interleaved unpack of the high values from the source and destination operands and stores the result in the destination operand (see Figure 11-6).
The UNPCKLPD (unpack and interleave low packed double-precision floating-point values) instruction performs an
interleaved unpack of the low values from the source and destination operands and stores the result in the destination operand (see Figure 11-7).
DEST
X1
X0
SRC
Y1
Y0
DEST
Y1
X1
Figure 11-6. UNPCKHPD Instruction, High Unpack and Interleave Operation
DEST
X1
X0
SRC
Y1
Y0
DEST
Y0
X0
Figure 11-7. UNPCKLPD Instruction, Low Unpack and Interleave Operation
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11.4.1.6
SSE2 Conversion Instructions
SSE2 conversion instructions (see Figure 11-8) support packed and scalar conversions between:
•
•
•
Double-precision and single-precision floating-point formats
Double-precision floating-point and doubleword integer formats
Single-precision floating-point and doubleword integer formats
Conversion between double-precision and single-precision floating-points values — The following
instructions convert operands between double-precision and single-precision floating-point formats. The operands
being operated on are contained in XMM registers or memory (at most, one operand can reside in memory; the
destination is always an MMX register).
The CVTPS2PD (convert packed single-precision floating-point values to packed double-precision floating-point
values) instruction converts two packed singleprecision floating-point values to two double-precision floating-point values.
The CVTPD2PS (convert packed double-precision floating-point values to packed single-precision floating-point
values) instruction converts two packed doubleprecision floating-point values to two single-precision floating-point values. When a conversion is inexact, the
result is rounded according to the rounding mode selected in the MXCSR register.
The CVTSS2SD (convert scalar single-precision floating-point value to scalar double-precision floating-point value)
instruction converts a single-precision floating-point value to a double-precision floating-point value.
The CVTSD2SS (convert scalar double-precision floating-point value to scalar single-precision floating-point value)
instruction converts a double-precision floating-point value to a single-precision floating-point value. When the
conversion is inexact, the result is rounded according to the rounding mode selected in the MXCSR register.
CV
CV TPS
TT 2D
PS Q
2D
Q
2 Doubleword
Integer
(XMM/mem)
C
C VT
VT P
TP D2
D DQ
2D
Q
C
VT
D
Q
2P
D
D
2P
PI
VT
C
I
2S SI
SD D2
VT S
C TT
V
C
D
2S
SI
VT
C
C
CV VT
TT PD
PD 2P
2P I
I
CVTSD2SS
CVTPD2PS
2 Doubleword
Integer
(MMX/mem)
Doubleword
Integer
(r32/mem)
4 Doubleword
Integer
(XMM/mem)
CVTSS2SD
CVTPS2PD
C
VT
PI
2P
S
I
2P I
S
P
TP S2
CV TTP
CV
S
2P
Q
D
VT
C
I
2S SI
S
2
TS SS
CV TT
CV
SS
I2
S
T
CV
Single-Precision
Floating Point
(XMM/mem)
Double-Precision
Floating-Point
(XMM/mem)
Figure 11-8. SSE and SSE2 Conversion Instructions
Conversion between double-precision floating-point values and doubleword integers — The following
instructions convert operands between double-precision floating-point and doubleword integer formats. Operands
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are housed in XMM registers, MMX registers, general registers or memory (at most one operand can reside in
memory; the destination is always an XMM, MMX, or general register).
The CVTPD2PI (convert packed double-precision floating-point values to packed doubleword integers) instruction
converts two packed double-precision floating-point numbers to two packed signed doubleword integers, with the
result stored in an MMX register. When rounding to an integer value, the source value is rounded according to the
rounding mode in the MXCSR register. The CVTTPD2PI (convert with truncation packed double-precision floatingpoint values to packed doubleword integers) instruction is similar to the CVTPD2PI instruction except that truncation is used to round a source value to an integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2
Conversion Instructions”).
The CVTPI2PD (convert packed doubleword integers to packed double-precision floating-point values) instruction
converts two packed signed doubleword integers to two double-precision floating-point values.
The CVTPD2DQ (convert packed double-precision floating-point values to packed doubleword integers) instruction
converts two packed double-precision floating-point numbers to two packed signed doubleword integers, with the
result stored in the low quadword of an XMM register. When rounding an integer value, the source value is rounded
according to the rounding mode selected in the MXCSR register. The CVTTPD2DQ (convert with truncation packed
double-precision floating-point values to packed doubleword integers) instruction is similar to the CVTPD2DQ
instruction except that truncation is used to round a source value to an integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2 Conversion Instructions”).
The CVTDQ2PD (convert packed doubleword integers to packed double-precision floating-point values) instruction
converts two packed signed doubleword integers located in the low-order doublewords of an XMM register to two
double-precision floating-point values.
The CVTSD2SI (convert scalar double-precision floating-point value to doubleword integer) instruction converts a
double-precision floating-point value to a doubleword integer, and stores the result in a general-purpose register.
When rounding an integer value, the source value is rounded according to the rounding mode selected in the
MXCSR register. The CVTTSD2SI (convert with truncation scalar double-precision floating-point value to doubleword integer) instruction is similar to the CVTSD2SI instruction except that truncation is used to round the source
value to an integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2 Conversion Instructions”).
The CVTSI2SD (convert doubleword integer to scalar double-precision floating-point value) instruction converts a
signed doubleword integer in a general-purpose register to a double-precision floating-point number, and stores
the result in an XMM register.
Conversion between single-precision floating-point and doubleword integer formats — These instructions convert between packed single-precision floating-point and packed doubleword integer formats. Operands
are housed in XMM registers, MMX registers, general registers, or memory (the latter for at most one source
operand). The destination is always an XMM, MMX, or general register. These SSE2 instructions supplement
conversion instructions (CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSI2SS, CVTSS2SI, and CVTTSS2SI) introduced
with SSE extensions.
The CVTPS2DQ (convert packed single-precision floating-point values to packed doubleword integers) instruction
converts four packed single-precision floating-point values to four packed signed doubleword integers, with the
source and destination operands in XMM registers or memory (the latter for at most one source operand). When
the conversion is inexact, the rounded value according to the rounding mode selected in the MXCSR register is
returned. The CVTTPS2DQ (convert with truncation packed single-precision floating-point values to packed doubleword integers) instruction is similar to the CVTPS2DQ instruction except that truncation is used to round a source
value to an integer value (see Section 4.8.4.2, “Truncation with SSE and SSE2 Conversion Instructions”).
The CVTDQ2PS (convert packed doubleword integers to packed single-precision floating-point values) instruction
converts four packed signed doubleword integers to four packed single-precision floating-point numbers, with the
source and destination operands in XMM registers or memory (the latter for at most one source operand). When
the conversion is inexact, the rounded value according to the rounding mode selected in the MXCSR register is
returned.
11.4.2
SSE2 64-Bit and 128-Bit SIMD Integer Instructions
SSE2 extensions add several 128-bit packed integer instructions to the IA-32 architecture. Where appropriate, a
64-bit version of each of these instructions is also provided. The 128-bit versions of instructions operate on data in
XMM registers; 64-bit versions operate on data in MMX registers. The instructions follow.
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The MOVDQA (move aligned double quadword) instruction transfers a double quadword operand from memory to
an XMM register or vice versa; or between XMM registers. The memory address must be aligned to a 16-byte
boundary; otherwise, a general-protection exception (#GP) is generated.
The MOVDQU (move unaligned double quadword) instruction performs the same operations as the MOVDQA
instruction, except that 16-byte alignment of a memory address is not required.
The PADDQ (packed quadword add) instruction adds two packed quadword integer operands or two single quadword integer operands, and stores the results in an XMM or MMX register, respectively. This instruction can operate
on either unsigned or signed (two’s complement notation) integer operands.
The PSUBQ (packed quadword subtract) instruction subtracts two packed quadword integer operands or two single
quadword integer operands, and stores the results in an XMM or MMX register, respectively. Like the PADDQ
instruction, PSUBQ can operate on either unsigned or signed (two’s complement notation) integer operands.
The PMULUDQ (multiply packed unsigned doubleword integers) instruction performs an unsigned multiply of
unsigned doubleword integers and returns a quadword result. Both 64-bit and 128-bit versions of this instruction
are available. The 64-bit version operates on two doubleword integers stored in the low doubleword of each source
operand, and the quadword result is returned to an MMX register. The 128-bit version performs a packed multiply
of two pairs of doubleword integers. Here, the doublewords are packed in the first and third doublewords of the
source operands, and the quadword results are stored in the low and high quadwords of an XMM register.
The PSHUFLW (shuffle packed low words) instruction shuffles the word integers packed into the low quadword of
the source operand and stores the shuffled result in the low quadword of the destination operand. An 8-bit immediate operand specifies the shuffle order.
The PSHUFHW (shuffle packed high words) instruction shuffles the word integers packed into the high quadword of
the source operand and stores the shuffled result in the high quadword of the destination operand. An 8-bit immediate operand specifies the shuffle order.
The PSHUFD (shuffle packed doubleword integers) instruction shuffles the doubleword integers packed into the
source operand and stores the shuffled result in the destination operand. An 8-bit immediate operand specifies the
shuffle order.
The PSLLDQ (shift double quadword left logical) instruction shifts the contents of the source operand to the left by
the amount of bytes specified by an immediate operand. The empty low-order bytes are cleared (set to 0).
The PSRLDQ (shift double quadword right logical) instruction shifts the contents of the source operand to the right
by the amount of bytes specified by an immediate operand. The empty high-order bytes are cleared (set to 0).
The PUNPCKHQDQ (Unpack high quadwords) instruction interleaves the high quadword of the source operand and
the high quadword of the destination operand and writes them to the destination register.
The PUNPCKLQDQ (Unpack low quadwords) instruction interleaves the low quadwords of the source operand and
the low quadwords of the destination operand and writes them to the destination register.
Two additional SSE instructions enable data movement from the MMX registers to the XMM registers.
The MOVQ2DQ (move quadword integer from MMX to XMM registers) instruction moves the quadword integer from
an MMX source register to an XMM destination register.
The MOVDQ2Q (move quadword integer from XMM to MMX registers) instruction moves the low quadword integer
from an XMM source register to an MMX destination register.
11.4.3
128-Bit SIMD Integer Instruction Extensions
All of 64-bit SIMD integer instructions introduced with MMX technology and SSE extensions (with the exception of
the PSHUFW instruction) have been extended by SSE2 extensions to operate on 128-bit packed integer operands
located in XMM registers. The 128-bit versions of these instructions follow the same SIMD conventions regarding
packed operands as the 64-bit versions. For example, where the 64-bit version of the PADDB instruction operates
on 8 packed bytes, the 128-bit version operates on 16 packed bytes.
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11.4.4
Cacheability Control and Memory Ordering Instructions
SSE2 extensions that give programs more control over the caching, loading, and storing of data. are described
below.
11.4.4.1
FLUSH Cache Line
The CLFLUSH (flush cache line) instruction writes and invalidates the cache line associated with a specified linear
address. The invalidation is for all levels of the processor’s cache hierarchy, and it is broadcast throughout the
cache coherency domain.
NOTE
CLFLUSH was introduced with the SSE2 extensions. However, the instruction can be implemented
in IA-32 processors that do not implement the SSE2 extensions. Detect CLFLUSH using the feature
bit (if CPUID.01H:EDX.CLFSH[bit 19] = 1).
11.4.4.2
Cacheability Control Instructions
The following four instructions enable data from XMM and general-purpose registers to be stored to memory using
a non-temporal hint. The non-temporal hint directs the processor to store data to memory without writing the data
into the cache hierarchy. See Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data,” for more information
about non-temporal stores and hints.
The MOVNTDQ (store double quadword using non-temporal hint) instruction stores packed integer data from an
XMM register to memory, using a non-temporal hint.
The MOVNTPD (store packed double-precision floating-point values using non-temporal hint) instruction stores
packed double-precision floating-point data from an XMM register to memory, using a non-temporal hint.
The MOVNTI (store doubleword using non-temporal hint) instruction stores integer data from a general-purpose
register to memory, using a non-temporal hint.
The MASKMOVDQU (store selected bytes of double quadword) instruction stores selected byte integers from an
XMM register to memory, using a byte mask to selectively write the individual bytes. The memory location does not
need to be aligned on a natural boundary. This instruction also uses a non-temporal hint.
11.4.4.3
Memory Ordering Instructions
SSE2 extensions introduce two new fence instructions (LFENCE and MFENCE) as companions to the SFENCE
instruction introduced with SSE extensions.
The LFENCE instruction establishes a memory fence for loads. It guarantees ordering between two loads and
prevents speculative loads from passing the load fence (that is, no speculative loads are allowed until all loads
specified before the load fence have been carried out).
The MFENCE instruction combines the functions of LFENCE and SFENCE by establishing a memory fence for both
loads and stores. It guarantees that all loads and stores specified before the fence are globally observable prior to
any loads or stores being carried out after the fence.
11.4.4.4
Pause
The PAUSE instruction is provided to improve the performance of “spin-wait loops” executed on a Pentium 4 or Intel
Xeon processor. On a Pentium 4 processor, it also provides the added benefit of reducing processor power
consumption while executing a spin-wait loop. It is recommended that a PAUSE instruction always be included in
the code sequence for a spin-wait loop.
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11.4.5
Branch Hints
SSE2 extensions designate two instruction prefixes (2EH and 3EH) to provide branch hints to the processor (see
“Instruction Prefixes” in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A). These prefixes can only be used with the Jcc instruction and only at the machine code level (that is, there are
no mnemonics for the branch hints).
11.5
SSE, SSE2, AND SSE3 EXCEPTIONS
SSE/SSE2/SSE3 extensions generate two general types of exceptions:
•
•
Non-numeric exceptions
SIMD floating-point exceptions1
SSE/SSE2/SSE3 instructions can generate the same type of memory-access and non-numeric exceptions as other
IA-32 architecture instructions. Existing exception handlers can generally handle these exceptions without any
code modification. See “Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE, SSE2
and SSE3 Instructions” in Chapter 13 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A, for a list of the non-numeric exceptions that can be generated by SSE/SSE2/SSE3 instructions and for
guidelines for handling these exceptions.
SSE/SSE2/SSE3 instructions do not generate numeric exceptions on packed integer operations; however, they can
generate numeric (SIMD floating-point) exceptions on packed single-precision and double-precision floating-point
operations. These SIMD floating-point exceptions are defined in the IEEE Standard 754 for Binary Floating-Point
Arithmetic and are the same exceptions that are generated for x87 FPU instructions. See Section 11.5.1, “SIMD
Floating-Point Exceptions,” for a description of these exceptions.
11.5.1
SIMD Floating-Point Exceptions
SIMD floating-point exceptions are those exceptions that can be generated by SSE/SSE2/SSE3 instructions that
operate on packed or scalar floating-point operands.
Six classes of SIMD floating-point exceptions can be generated:
•
•
•
•
•
•
Invalid operation (#I)
Divide-by-zero (#Z)
Denormal operand (#D)
Numeric overflow (#O)
Numeric underflow (#U)
Inexact result (Precision) (#P)
All of these exceptions (except the denormal operand exception) are defined in IEEE Standard 754, and they are
the same exceptions that are generated with the x87 floating-point instructions. Section 4.9, “Overview of
Floating-Point Exceptions,” gives a detailed description of these exceptions and of how and when they are generated. The following sections discuss the implementation of these exceptions in SSE/SSE2/SSE3 extensions.
All SIMD floating-point exceptions are precise and occur as soon as the instruction completes execution.
Each of the six exception conditions has a corresponding flag (IE, DE, ZE, OE, UE, and PE) and mask bit (IM, DM,
ZM, OM, UM, and PM) in the MXCSR register (see Figure 10-3). The mask bits can be set with the LDMXCSR or
FXRSTOR instruction; the mask and flag bits can be read with the STMXCSR or FXSAVE instruction.
The OSXMMEXCEPT flag (bit 10) of control register CR4 provides additional control over generation of SIMD
floating-point exceptions by allowing the operating system to indicate whether or not it supports software exception handlers for SIMD floating-point exceptions. If an unmasked SIMD floating-point exception is generated and
the OSXMMEXCEPT flag is set, the processor invokes a software exception handler by generating a SIMD floating1. The FISTTP instruction in SSE3 does not generate SIMD floating-point exceptions, but it can generate x87 FPU floating-point exceptions.
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point exception (#XM). If the OSXMMEXCEPT bit is clear, the processor generates an invalid-opcode exception
(#UD) on the first SSE or SSE2 instruction that detects a SIMD floating-point exception condition. See Section
11.6.2, “Checking for SSE/SSE2 Support.”
11.5.2
SIMD Floating-Point Exception Conditions
The following sections describe the conditions that cause a SIMD floating-point exception to be generated and the
masked response of the processor when these conditions are detected.
See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules for exception precedence when
more than one floating-point exception condition is detected for an instruction.
11.5.2.1
Invalid Operation Exception (#I)
The floating-point invalid-operation exception (#I) occurs in response to an invalid arithmetic operand. The flag
(IE) and mask (IM) bits for the invalid operation exception are bits 0 and 7, respectively, in the MXCSR register.
If the invalid-operation exception is masked, the processor returns a QNaN, QNaN floating-point indefinite, integer
indefinite, one of the source operands to the destination operand, or it sets the EFLAGS, depending on the operation
being performed. When a value is returned to the destination operand, it overwrites the destination register specified
by the instruction. Table 11-1 lists the invalid-arithmetic operations that the processor detects for instructions and
the masked responses to these operations.
Table 11-1. Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid Arithmetic Operations
Condition
Masked Response
ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD,
MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD, DIVSD,
ADDSUBPD, ADDSUBPD, HADDPD, HADDPS, HSUBPD or HSUBPS
instruction with an SNaN operand
Return the SNaN converted to a QNaN; Refer to Table 4-7 for
more details
SQRTPS, SQRTSS, SQRTPD, or SQRTSD with SNaN operands
Return the SNaN converted to a QNaN
SQRTPS, SQRTSS, SQRTPD, or SQRTSD with negative operands
(except zero)
Return the QNaN floating-point Indefinite
MAXPS, MAXSS, MAXPD, MAXSD, MINPS, MINSS, MINPD, or
MINSD instruction with QNaN or SNaN operands
Return the source 2 operand value
CMPPS, CMPSS, CMPPD or CMPSD instruction with QNaN or SNaN
operands
Return a mask of all 0s (except for the predicates “not-equal,”
“unordered,” “not-less-than,” or “not-less-than-or-equal,” which
returns a mask of all 1s)
CVTPD2PS, CVTSD2SS, CVTPS2PD, CVTSS2SD with SNaN
operands
Return the SNaN converted to a QNaN
COMISS or COMISD with QNaN or SNaN operand(s)
Set EFLAGS values to “not comparable”
Addition of opposite signed infinities or subtraction of like-signed
infinities
Return the QNaN floating-point Indefinite
Multiplication of infinity by zero
Return the QNaN floating-point Indefinite
Divide of (0/0) or ( ∞ / ∞ )
Return the QNaN floating-point Indefinite
Conversion to integer when the value in the source register is a
NaN, ∞, or exceeds the representable range for CVTPS2PI,
CVTTPS2PI, CVTSS2SI, CVTTSS2SI, CVTPD2PI, CVTSD2SI,
CVTPD2DQ, CVTTPD2PI, CVTTSD2SI, CVTTPD2DQ, CVTPS2DQ,
or CVTTPS2DQ
Return the integer Indefinite
If the invalid operation exception is not masked, a software exception handler is invoked and the operands remain
unchanged. See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software.”
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Normally, when one or more of the source operands are QNaNs (and neither is an SNaN or in an unsupported
format), an invalid-operation exception is not generated. The following instructions are exceptions to this rule: the
COMISS and COMISD instructions; and the CMPPS, CMPSS, CMPPD, and CMPSD instructions (when the predicate
is less than, less-than or equal, not less-than, or not less-than or equal). With these instructions, a QNaN source
operand will generate an invalid-operation exception.
The invalid-operation exception is not affected by the flush-to-zero mode or by the denormals-are-zeros mode.
11.5.2.2
Denormal-Operand Exception (#D)
The processor signals the denormal-operand exception if an arithmetic instruction attempts to operate on a
denormal operand. The flag (DE) and mask (DM) bits for the denormal-operand exception are bits 1 and 8, respectively, in the MXCSR register.
The CVTPI2PD, CVTPD2PI, CVTTPD2PI, CVTDQ2PD, CVTPD2DQ, CVTTPD2DQ, CVTSI2SD, CVTSD2SI, CVTTSD2SI,
CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSS2SI, CVTTSS2SI, CVTSI2SS, CVTDQ2PS, CVTPS2DQ, and CVTTPS2DQ
conversion instructions do not signal denormal exceptions. The RCPSS, RCPPS, RSQRTSS, and RSQRTPS instructions do not signal any kind of floating-point exception.
The denormals-are-zero flag (bit 6) of the MXCSR register provides an additional option for handling denormaloperand exceptions. When this flag is set, denormal source operands are automatically converted to zeros with the
sign of the source operand (see Section 10.2.3.4, “Denormals-Are-Zeros”). The denormal operand exception is not
affected by the flush-to-zero mode.
See Section 4.9.1.2, “Denormal Operand Exception (#D),” for more information about the denormal exception.
See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling unmasked
exceptions.
11.5.2.3
Divide-By-Zero Exception (#Z)
The processor reports a divide-by-zero exception when a DIVPS, DIVSS, DIVPD or DIVSD instruction attempts to
divide a finite non-zero operand by 0. The flag (ZE) and mask (ZM) bits for the divide-by-zero exception are bits 2
and 9, respectively, in the MXCSR register.
See Section 4.9.1.3, “Divide-By-Zero Exception (#Z),” for more information about the divide-by-zero exception.
See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling unmasked
exceptions.
The divide-by-zero exception is not affected by the flush-to-zero mode at a single-instruction boundary.
While DAZ does not affect the rules for signaling IEEE exceptions, operations on denormal inputs might have
different results when DAZ=1. As a consequence, DAZ can have an effect on the floating-point exceptions including the divide-by-zero exception - when observed for a given operation involving denormal inputs.
11.5.2.4
Numeric Overflow Exception (#O)
The processor reports a numeric overflow exception whenever the rounded result of an arithmetic instruction
exceeds the largest allowable finite value that fits in the destination operand. This exception can be generated with
the ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD, DIVPS,
DIVSS, DIVPD, DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS, HADDPD, HADDPS, HSUBPD and HSUBPS
instructions. The flag (OE) and mask (OM) bits for the numeric overflow exception are bits 3 and 10, respectively,
in the MXCSR register.
See Section 4.9.1.4, “Numeric Overflow Exception (#O),” for more information about the numeric-overflow exception. See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling
unmasked exceptions.
The numeric overflow exception is not affected by the flush-to-zero mode or by the denormals-are-zeros mode.
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11.5.2.5
Numeric Underflow Exception (#U)
The processor reports a numeric underflow exception whenever the magnitude of the rounded result of an arithmetic instruction, with unbounded exponent, is less than the smallest possible normalized, finite value that will fit
in the destination operand and the numeric-underflow exception is not masked. If the numeric underflow exception
is masked, both underflow and the inexact-result condition must be detected before numeric underflow is reported.
This exception can be generated with the ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD,
MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD, DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS,
HADDPD, HADDPS, HSUBPD, and HSUBPS instructions. The flag (UE) and mask (UM) bits for the numeric underflow exception are bits 4 and 11, respectively, in the MXCSR register.
The flush-to-zero flag (bit 15) of the MXCSR register provides an additional option for handling numeric underflow
exceptions. When this flag is set and the numeric underflow exception is masked, tiny results are returned as a zero
with the sign of the true result (see Section 10.2.3.3, “Flush-To-Zero”).
Underflow will occur when a tiny non-zero result is detected (the result has to be also inexact if underflow exceptions are masked), as described in the IEEE Standard 754-2008. While DAZ does not affect the rules for signaling
IEEE exceptions, operations on denormal inputs might have different results when DAZ=1. As a consequence, DAZ
can have an effect on the floating-point exceptions - including the underflow exception - when observed for a given
operation involving denormal inputs.
See Section 4.9.1.5, “Numeric Underflow Exception (#U),” for more information about the numeric underflow
exception. See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling
unmasked exceptions.
11.5.2.6
Inexact-Result (Precision) Exception (#P)
The inexact-result exception (also called the precision exception) occurs if the result of an operation is not exactly
representable in the destination format. For example, the fraction 1/3 cannot be precisely represented in binary
form. This exception occurs frequently and indicates that some (normally acceptable) accuracy has been lost. The
exception is supported for applications that need to perform exact arithmetic only. Because the rounded result is
generally satisfactory for most applications, this exception is commonly masked.
The flag (PE) and mask (PM) bits for the inexact-result exception are bits 2 and 12, respectively, in the MXCSR
register.
See Section 4.9.1.6, “Inexact-Result (Precision) Exception (#P),” for more information about the inexact-result
exception. See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling
unmasked exceptions.
In flush-to-zero mode, the inexact result exception is reported.
11.5.3
Generating SIMD Floating-Point Exceptions
When the processor executes a packed or scalar floating-point instruction, it looks for and reports on SIMD
floating-point exception conditions using two sequential steps:
1. Looks for, reports on, and handles pre-computation exception conditions (invalid-operand, divide-by-zero, and
denormal operand)
2. Looks for, reports on, and handles post-computation exception conditions (numeric overflow, numeric
underflow, and inexact result)
If both pre- and post-computational exceptions are unmasked, it is possible for the processor to generate a SIMD
floating-point exception (#XM) twice during the execution of an SSE, SSE2 or SSE3 instruction: once when it
detects and handles a pre-computational exception and when it detects a post-computational exception.
11.5.3.1
Handling Masked Exceptions
If all exceptions are masked, the processor handles the exceptions it detects by placing the masked result (or
results for packed operands) in a destination operand and continuing program execution. The masked result may
be a rounded normalized value, signed infinity, a denormal finite number, zero, a QNaN floating-point indefinite, or
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a QNaN depending on the exception condition detected. In most cases, the corresponding exception flag bit in
MXCSR is also set. The one situation where an exception flag is not set is when an underflow condition is detected
and it is not accompanied by an inexact result.
When operating on packed floating-point operands, the processor returns a masked result for each of the suboperand computations and sets a separate set of internal exception flags for each computation. It then performs a
logical-OR on the internal exception flag settings and sets the exception flags in the MXCSR register according to
the results of OR operations.
For example, Figure 11-9 shows the results of an MULPS instruction. In the example, all SIMD floating-point exceptions are masked. Assume that a denormal exception condition is detected prior to the multiplication of sub-operands X0 and Y0, no exception condition is detected for the multiplication of X1 and Y1, a numeric overflow
exception condition is detected for the multiplication of X2 and Y2, and another denormal exception is detected
prior to the multiplication of sub-operands X3 and Y3. Because denormal exceptions are masked, the processor
uses the denormal source values in the multiplications of (X0 and Y0) and of (X3 and Y3) passing the results of the
multiplications through to the destination operand. With the denormal operand, the result of the X0 and Y0 computation is a normalized finite value, with no exceptions detected. However, the X3 and Y3 computation produces a
tiny and inexact result. This causes the corresponding internal numeric underflow and inexact-result exception
flags to be set.
X3
X2
Y3 (Denormal)
MULPS
X1
Y2
MULPS
Tiny, Inexact, Finite
∞
X0 (Denormal)
Y1
MULPS
Y0
MULPS
Normalized Finite Normalized Finite
Figure 11-9. Example Masked Response for Packed Operations
For the multiplication of X2 and Y2, the processor stores the floating-point ∞ in the destination operand, and sets
the corresponding internal sub-operand numeric overflow flag. The result of the X1 and Y1 multiplication is passed
through to the destination operand, with no internal sub-operand exception flags being set. Following the computations, the individual sub-operand exceptions flags for denormal operand, numeric underflow, inexact result, and
numeric overflow are OR’d and the corresponding flags are set in the MXCSR register.
The net result of this computation is that:
•
•
•
•
•
Multiplication of X0 and Y0 produces a normalized finite result
Multiplication of X1 and Y1 produces a normalized finite result
Multiplication of X2 and Y2 produces a floating-point ∞ result
Multiplication of X3 and Y3 produces a tiny, inexact, finite result
Denormal operand, numeric underflow, numeric underflow, and inexact result flags are set in the MXCSR
register
11.5.3.2
Handling Unmasked Exceptions
If all exceptions are unmasked, the processor:
1. First detects any pre-computation exceptions: it ORs those exceptions, sets the appropriate exception flags,
leaves the source and destination operands unaltered, and goes to step 2. If it does not detect any precomputation exceptions, it goes to step 5.
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2. Checks CR4.OSXMMEXCPT[bit 10]. If this flag is set, the processor goes to step 3; if the flag is clear, it
generates an invalid-opcode exception (#UD) and makes an implicit call to the invalid-opcode exception
handler.
3. Generates a SIMD floating-point exception (#XM) and makes an implicit call to the SIMD floating-point
exception handler.
4. If the exception handler is able to fix the source operands that generated the pre-computation exceptions or
mask the condition in such a way as to allow the processor to continue executing the instruction, the processor
resumes instruction execution as described in step 5.
5. Upon returning from the exception handler (or if no pre-computation exceptions were detected), the processor
checks for post-computation exceptions. If the processor detects any post-computation exceptions: it ORs
those exceptions, sets the appropriate exception flags, leaves the source and destination operands unaltered,
and repeats steps 2, 3, and 4.
6. Upon returning from the exceptions handler in step 4 (or if no post-computation exceptions were detected), the
processor completes the execution of the instruction.
The implication of this procedure is that for unmasked exceptions, the processor can generate a SIMD floatingpoint exception (#XM) twice: once if it detects pre-computation exception conditions and a second time if it detects
post-computation exception conditions. For example, if SIMD floating-point exceptions are unmasked for the
computation shown in Figure 11-9, the processor would generate one SIMD floating-point exception for denormal
operand conditions and a second SIMD floating-point exception for overflow and underflow (no inexact result
exception would be generated because the multiplications of X0 and Y0 and of X1 and Y1 are exact).
11.5.3.3
Handling Combinations of Masked and Unmasked Exceptions
In situations where both masked and unmasked exceptions are detected, the processor will set exception flags for
the masked and the unmasked exceptions. However, it will not return masked results until after the processor has
detected and handled unmasked post-computation exceptions and returned from the exception handler (as in step
6 above) to finish executing the instruction.
11.5.4
Handling SIMD Floating-Point Exceptions in Software
Section 4.9.3, “Typical Actions of a Floating-Point Exception Handler,” shows actions that may be carried out by a
SIMD floating-point exception handler. The SSE/SSE2/SSE3 state is saved with the FXSAVE instruction (see Section
11.6.5, “Saving and Restoring the SSE/SSE2 State”).
11.5.5
Interaction of SIMD and x87 FPU Floating-Point Exceptions
SIMD floating-point exceptions are generated independently from x87 FPU floating-point exceptions. SIMD
floating-point exceptions do not cause assertion of the FERR# pin (independent of the value of CR0.NE[bit 5]).
They ignore the assertion and deassertion of the IGNNE# pin.
If applications use SSE/SSE2/SSE3 instructions along with x87 FPU instructions (in the same task or program),
consider the following:
•
SIMD floating-point exceptions are reported independently from the x87 FPU floating-point exceptions. SIMD
and x87 FPU floating-point exceptions can be unmasked independently. Separate x87 FPU and SIMD floatingpoint exception handlers must be provided if the same exception is unmasked for x87 FPU and for
SSE/SSE2/SSE3 operations.
•
The rounding mode specified in the MXCSR register does not affect x87 FPU instructions. Likewise, the rounding
mode specified in the x87 FPU control word does not affect the SSE/SSE2/SSE3 instructions. To use the same
rounding mode, the rounding control bits in the MXCSR register and in the x87 FPU control word must be set
explicitly to the same value.
•
The flush-to-zero mode set in the MXCSR register for SSE/SSE2/SSE3 instructions has no counterpart in the
x87 FPU. For compatibility with the x87 FPU, set the flush-to-zero bit to 0.
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•
The denormals-are-zeros mode set in the MXCSR register for SSE/SSE2/SSE3 instructions has no counterpart
in the x87 FPU. For compatibility with the x87 FPU, set the denormals-are-zeros bit to 0.
•
An application that expects to detect x87 FPU exceptions that occur during the execution of x87 FPU instructions will not be notified if exceptions occurs during the execution of corresponding SSE/SSE2/SSE31 instructions, unless the exception masks that are enabled in the x87 FPU control word have also been enabled in the
MXCSR register and the application is capable of handling SIMD floating-point exceptions (#XM).
— Masked exceptions that occur during an SSE/SSE2/SSE3 library call cannot be detected by unmasking the
exceptions after the call (in an attempt to generate the fault based on the fact that an exception flag is set).
A SIMD floating-point exception flag that is set when the corresponding exception is unmasked will not
generate a fault; only the next occurrence of that unmasked exception will generate a fault.
— An application which checks the x87 FPU status word to determine if any masked exception flags were set
during an x87 FPU library call will also need to check the MXCSR register to detect a similar occurrence of a
masked exception flag being set during an SSE/SSE2/SSE3 library call.
11.6
WRITING APPLICATIONS WITH SSE/SSE2 EXTENSIONS
The following sections give some guidelines for writing application programs and operating-system code that uses
the SSE and SSE2 extensions. Because SSE and SSE2 extensions share the same state and perform companion
operations, these guidelines apply to both sets of extensions.
Chapter 13 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, discusses the interface to the processor for context switching as well as other operating system considerations when writing code that
uses SSE/SSE2/SSE3 extensions.
11.6.1
General Guidelines for Using SSE/SSE2 Extensions
The following guidelines describe how to take full advantage of the performance gains available with the SSE and
SSE2 extensions:
•
•
Ensure that the processor supports the SSE and SSE2 extensions.
•
•
•
Use stack and data alignment techniques to keep data properly aligned for efficient memory use.
Ensure that your operating system supports the SSE and SSE2 extensions. (Operating system support for the
SSE extensions implies support for SSE2 extension and vice versa.)
Use the non-temporal store instructions offered with the SSE and SSE2 extensions.
Employ the optimization and scheduling techniques described in the Intel Pentium 4 Optimization Reference
Manual (see Section 1.4, “Related Literature,” for the order number for this manual).
11.6.2
Checking for SSE/SSE2 Support
Before an application attempts to use the SSE and/or SSE2 extensions, it should check that they are present on the
processor:
1. Check that the processor supports the CPUID instruction. Bit 21 of the EFLAGS register can be used to check
processor’s support the CPUID instruction.
2. Check that the processor supports the SSE and/or SSE2 extensions (true if CPUID.01H:EDX.SSE[bit 25] = 1
and/or CPUID.01H:EDX.SSE2[bit 26] = 1).
Operating system must provide system level support for handling SSE state, exceptions before an application can
use the SSE and/or SSE2 extensions (see Chapter 13 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
1. SSE3 refers to ADDSUBPD, ADDSUBPS, HADDPD, HADDPS, HSUBPD and HSUBPS; the only other SSE3 instruction that can raise
floating-point exceptions is FISTTP: it can generate x87 FPU invalid operation and inexact result exceptions.
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If the processor attempts to execute an unsupported SSE or SSE2 instruction, the processor will generate an
invalid-opcode exception (#UD). If an operating system did not provide adequate system level support for SSE,
executing an SSE or SSE2 instructions can also generate #UD.
11.6.3
Checking for the DAZ Flag in the MXCSR Register
The denormals-are-zero flag in the MXCSR register is available in most of the Pentium 4 processors and in the Intel
Xeon processor, with the exception of some early steppings. To check for the presence of the DAZ flag in the MXCSR
register, do the following:
1. Establish a 512-byte FXSAVE area in memory.
2. Clear the FXSAVE area to all 0s.
3. Execute the FXSAVE instruction, using the address of the first byte of the cleared FXSAVE area as a source
operand. See “FXSAVE—Save x87 FPU, MMX, SSE, and SSE2 State” in Chapter 3 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2A, for a description of the FXSAVE instruction and the
layout of the FXSAVE image.
4. Check the value in the MXCSR_MASK field in the FXSAVE image (bytes 28 through 31).
— If the value of the MXCSR_MASK field is 00000000H, the DAZ flag and denormals-are-zero mode are not
supported.
— If the value of the MXCSR_MASK field is non-zero and bit 6 is set, the DAZ flag and denormals-are-zero
mode are supported.
If the DAZ flag is not supported, then it is a reserved bit and attempting to write a 1 to it will cause a generalprotection exception (#GP). See Section 11.6.6, “Guidelines for Writing to the MXCSR Register,” for general guidelines for preventing general-protection exceptions when writing to the MXCSR register.
11.6.4
Initialization of SSE/SSE2 Extensions
The SSE and SSE2 state is contained in the XMM and MXCSR registers. Upon a hardware reset of the processor, this
state is initialized as follows (see Table 11-2):
•
•
•
•
•
All SIMD floating-point exceptions are masked (bits 7 through 12 of the MXCSR register is set to 1).
•
Each of the XMM registers is cleared (set to all zeros).
All SIMD floating-point exception flags are cleared (bits 0 through 5 of the MXCSR register is set to 0).
The rounding control is set to round-nearest (bits 13 and 14 of the MXCSR register are set to 00B).
The flush-to-zero mode is disabled (bit 15 of the MXCSR register is set to 0).
The denormals-are-zeros mode is disabled (bit 6 of the MXCSR register is set to 0). If the denormals-are-zeros
mode is not supported, this bit is reserved and will be set to 0 on initialization.
Table 11-2. SSE and SSE2 State Following a Power-up/Reset or INIT
Registers
XMM0 through XMM7
MXCSR
Power-Up or Reset
INIT
+0.0
Unchanged
1F80H
Unchanged
If the processor is reset by asserting the INIT# pin, the SSE and SSE2 state is not changed.
11.6.5
Saving and Restoring the SSE/SSE2 State
The FXSAVE instruction saves the x87 FPU, MMX, SSE and SSE2 states (which includes the contents of eight XMM
registers and the MXCSR registers) in a 512-byte block of memory. The FXRSTOR instruction restores the saved
SSE and SSE2 state from memory. See the FXSAVE instruction in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for the layout of the 512-byte state block.
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In addition to saving and restoring the SSE and SSE2 state, FXSAVE and FXRSTOR also save and restore the x87
FPU state (because MMX registers are aliased to the x87 FPU data registers this includes saving and restoring the
MMX state). For greater code efficiency, it is suggested that FXSAVE and FXRSTOR be substituted for the FSAVE,
FNSAVE and FRSTOR instructions in the following situations:
•
•
When a context switch is being made in a multitasking environment
During calls and returns from interrupt and exception handlers
In situations where the code is switching between x87 FPU and MMX technology computations (without a context
switch or a call to an interrupt or exception), the FSAVE/FNSAVE and FRSTOR instructions are more efficient than
the FXSAVE and FXRSTOR instructions.
11.6.6
Guidelines for Writing to the MXCSR Register
The MXCSR has several reserved bits, and attempting to write a 1 to any of these bits will cause a general-protection exception (#GP) to be generated. To allow software to identify these reserved bits, the MXCSR_MASK value is
provided. Software can determine this mask value as follows:
1. Establish a 512-byte FXSAVE area in memory.
2. Clear the FXSAVE area to all 0s.
3. Execute the FXSAVE instruction, using the address of the first byte of the cleared FXSAVE area as a source
operand. See “FXSAVE—Save x87 FPU, MMX, SSE, and SSE2 State” in Chapter 3 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2A, for a description of FXSAVE and the layout of the
FXSAVE image.
4. Check the value in the MXCSR_MASK field in the FXSAVE image (bytes 28 through 31).
— If the value of the MXCSR_MASK field is 00000000H, then the MXCSR_MASK value is the default value of
0000FFBFH. Note that this value indicates that bit 6 of the MXCSR register is reserved; this setting indicates
that the denormals-are-zero mode is not supported on the processor.
— If the value of the MXCSR_MASK field is non-zero, the MXCSR_MASK value should be used as the
MXCSR_MASK.
All bits set to 0 in the MXCSR_MASK value indicate reserved bits in the MXCSR register. Thus, if the MXCSR_MASK
value is AND’d with a value to be written into the MXCSR register, the resulting value will be assured of having all
its reserved bits set to 0, preventing the possibility of a general-protection exception being generated when the
value is written to the MXCSR register.
For example, the default MXCSR_MASK value when 00000000H is returned in the FXSAVE image is 0000FFBFH. If
software AND’s a value to be written to MXCSR register with 0000FFBFH, bit 6 of the result (the DAZ flag) will be
ensured of being set to 0, which is the required setting to prevent general-protection exceptions on processors that
do not support the denormals-are-zero mode.
To prevent general-protection exceptions, the MXCSR_MASK value should be AND’d with the value to be written
into the MXCSR register in the following situations:
•
Operating system routines that receive a parameter from an application program and then write that value to
the MXCSR register (either with an FXRSTOR or LDMXCSR instruction)
•
Any application program that writes to the MXCSR register and that needs to run robustly on several different
IA-32 processors
Note that all bits in the MXCSR_MASK value that are set to 1 indicate features that are supported by the MXCSR
register; they can be treated as feature flags for identifying processor capabilities.
11.6.7
Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions
The XMM registers and the x87 FPU and MMX registers represent separate execution environments, which has
certain ramifications when executing SSE, SSE2, MMX, and x87 FPU instructions in the same code module or when
mixing code modules that contain these instructions:
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•
Those SSE and SSE2 instructions that operate only on XMM registers (such as the packed and scalar floatingpoint instructions and the 128-bit SIMD integer instructions) in the same instruction stream with 64-bit SIMD
integer or x87 FPU instructions without any restrictions. For example, an application can perform the majority
of its floating-point computations in the XMM registers, using the packed and scalar floating-point instructions,
and at the same time use the x87 FPU to perform trigonometric and other transcendental computations.
Likewise, an application can perform packed 64-bit and 128-bit SIMD integer operations together without
restrictions.
•
Those SSE and SSE2 instructions that operate on MMX registers (such as the CVTPS2PI, CVTTPS2PI, CVTPI2PS,
CVTPD2PI, CVTTPD2PI, CVTPI2PD, MOVDQ2Q, MOVQ2DQ, PADDQ, and PSUBQ instructions) can also be
executed in the same instruction stream as 64-bit SIMD integer or x87 FPU instructions, however, here they are
subject to the restrictions on the simultaneous use of MMX technology and x87 FPU instructions, which include:
— Transition from x87 FPU to MMX technology instructions or to SSE or SSE2 instructions that operate on MMX
registers should be preceded by saving the state of the x87 FPU.
— Transition from MMX technology instructions or from SSE or SSE2 instructions that operate on MMX
registers to x87 FPU instructions should be preceded by execution of the EMMS instruction.
11.6.8
Compatibility of SIMD and x87 FPU Floating-Point Data Types
SSE and SSE2 extensions operate on the same single-precision and double-precision floating-point data types that
the x87 FPU operates on. However, when operating on these data types, the SSE and SSE2 extensions operate on
them in their native format (single-precision or double-precision), in contrast to the x87 FPU which extends them
to double extended-precision floating-point format to perform computations and then rounds the result back to a
single-precision or double-precision format before writing results to memory. Because the x87 FPU operates on a
higher precision format and then rounds the result to a lower precision format, it may return a slightly different
result when performing the same operation on the same single-precision or double-precision floating-point values
than is returned by the SSE and SSE2 extensions. The difference occurs only in the least-significant bits of the
significand.
11.6.9
Mixing Packed and Scalar Floating-Point and 128-Bit SIMD Integer Instructions and
Data
SSE and SSE2 extensions define typed operations on packed and scalar floating-point data types and on 128-bit
SIMD integer data types, but IA-32 processors do not enforce this typing at the architectural level. They only
enforce it at the microarchitectural level. Therefore, when a Pentium 4 or Intel Xeon processor loads a packed or
scalar floating-point operand or a 128-bit packed integer operand from memory into an XMM register, it does not
check that the actual data being loaded matches the data type specified in the instruction. Likewise, when the
processor performs an arithmetic operation on the data in an XMM register, it does not check that the data being
operated on matches the data type specified in the instruction.
As a general rule, because data typing of SIMD floating-point and integer data types is not enforced at the architectural level, it is the responsibility of the programmer, assembler, or compiler to insure that code enforces data
typing. Failure to enforce correct data typing can lead to computations that return unexpected results.
For example, in the following code sample, two packed single-precision floating-point operands are moved from
memory into XMM registers (using MOVAPS instructions); then a double-precision packed add operation (using the
ADDPD instruction) is performed on the operands:
movaps
xmm0, [eax]
; EAX register contains pointer to packed
; single-precision floating-point operand
movaps
xmm1, [ebx]
addpd
xmm0, xmm1
Pentium 4 and Intel Xeon processors execute these instructions without generating an invalid-operand exception
(#UD) and will produce the expected results in register XMM0 (that is, the high and low 64-bits of each register will
be treated as a double-precision floating-point value and the processor will operate on them accordingly). Because
the data types operated on and the data type expected by the ADDPD instruction were inconsistent, the instruction
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may result in a SIMD floating-point exception (such as numeric overflow [#O] or invalid operation [#I]) being
generated, but the actual source of the problem (inconsistent data types) is not detected.
The ability to operate on an operand that contains a data type that is inconsistent with the typing of the instruction
being executed, permits some valid operations to be performed. For example, the following instructions load a
packed double-precision floating-point operand from memory to register XMM0, and a mask to register XMM1;
then they use XORPD to toggle the sign bits of the two packed values in register XMM0.
movapd
xmm0, [eax]
; EAX register contains pointer to packed
; double-precision floating-point operand
movaps
xmm1, [ebx]
; EBX register contains pointer to packed
; double-precision floating-point mask
xorpd
xmm0, xmm1 ; XOR operation toggles sign bits using
; the mask in xmm1
In this example: XORPS or PXOR can be used in place of XORPD and yield the same correct result. However,
because of the type mismatch between the operand data type and the instruction data type, a latency penalty will
be incurred due to implementations of the instructions at the microarchitecture level.
Latency penalties can also be incurred by using move instructions of the wrong type. For example, MOVAPS and
MOVAPD can both be used to move a packed single-precision operand from memory to an XMM register. However,
if MOVAPD is used, a latency penalty will be incurred when a correctly typed instruction attempts to use the data in
the register.
Note that these latency penalties are not incurred when moving data from XMM registers to memory.
11.6.10 Interfacing with SSE/SSE2 Procedures and Functions
SSE and SSE2 extensions allow direct access to XMM registers. This means that all existing interface conventions
between procedures and functions that apply to the use of the general-purpose registers (EAX, EBX, etc.) also
apply to XMM register usage.
11.6.10.1 Passing Parameters in XMM Registers
The state of XMM registers is preserved across procedure (or function) boundaries. Parameters can be passed from
one procedure to another using XMM registers.
11.6.10.2 Saving XMM Register State on a Procedure or Function Call
The state of XMM registers can be saved in two ways: using an FXSAVE instruction or a move instruction. FXSAVE
saves the state of all XMM registers (along with the state of MXCSR and the x87 FPU registers). This instruction is
typically used for major changes in the context of the execution environment, such as a task switch. FXRSTOR
restores the XMM, MXCSR, and x87 FPU registers stored with FXSAVE.
In cases where only XMM registers must be saved, or where selected XMM registers need to be saved, move
instructions (MOVAPS, MOVUPS, MOVSS, MOVAPD, MOVUPD, MOVSD, MOVDQA, and MOVDQU) can be used.
These instructions can also be used to restore the contents of XMM registers. To avoid performance degradation
when saving XMM registers to memory or when loading XMM registers from memory, be sure to use the appropriately typed move instructions.
The move instructions can also be used to save the contents of XMM registers on the stack. Here, the stack pointer
(in the ESP register) can be used as the memory address to the next available byte in the stack. Note that the stack
pointer is not automatically incremented when using a move instruction (as it is with PUSH).
A move-instruction procedure that saves the contents of an XMM register to the stack is responsible for decrementing the value in the ESP register by 16. Likewise, a move-instruction procedure that loads an XMM register
from the stack needs also to increment the ESP register by 16. To avoid performance degradation when moving the
contents of XMM registers, use the appropriately typed move instructions.
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Use the LDMXCSR and STMXCSR instructions to save and restore, respectively, the contents of the MXCSR register
on a procedure call and return.
11.6.10.3 Caller-Save Recommendation for Procedure and Function Calls
When making procedure (or function) calls from SSE or SSE2 code, a caller-save convention is recommended for
saving the state of the calling procedure. Using this convention, any register whose content must survive intact
across a procedure call must be stored in memory by the calling procedure prior to executing the call.
The primary reason for using the caller-save convention is to prevent performance degradation. XMM registers can
contain packed or scalar double-precision floating-point, packed single-precision floating-point, and 128-bit packed
integer data types. The called procedure has no way of knowing the data types in XMM registers following a call; so
it is unlikely to use the correctly typed move instruction to store the contents of XMM registers in memory or to
restore the contents of XMM registers from memory.
As described in Section 11.6.9, “Mixing Packed and Scalar Floating-Point and 128-Bit SIMD Integer Instructions
and Data,” executing a move instruction that does not match the type for the data being moved to/from XMM registers will be carried out correctly, but can lead to a greater instruction latency.
11.6.11 Updating Existing MMX Technology Routines Using 128-Bit SIMD Integer Instructions
SSE2 extensions extend all 64-bit MMX SIMD integer instructions to operate on 128-bit SIMD integers using XMM
registers. The extended 128-bit SIMD integer instructions operate like the 64-bit SIMD integer instructions; this
simplifies the porting of MMX technology applications. However, there are considerations:
•
To take advantage of wider 128-bit SIMD integer instructions, MMX technology code must be recompiled to
reference the XMM registers instead of MMX registers.
•
Computation instructions that reference memory operands that are not aligned on 16-byte boundaries should
be replaced with an unaligned 128-bit load (MOVUDQ instruction) followed by a version of the same
computation operation that uses register instead of memory operands. Use of 128-bit packed integer
computation instructions with memory operands that are not 16-byte aligned results in a general protection
exception (#GP).
•
Extension of the PSHUFW instruction (shuffle word across 64-bit integer operand) across a full 128-bit operand
is emulated by a combination of the following instructions: PSHUFHW, PSHUFLW, and PSHUFD.
•
Use of the 64-bit shift by bit instructions (PSRLQ, PSLLQ) can be extended to 128 bits in either of two ways:
— Use of PSRLQ and PSLLQ, along with masking logic operations.
— Rewriting the code sequence to use PSRLDQ and PSLLDQ (shift double quadword operand by bytes)
•
Loop counters need to be updated, since each 128-bit SIMD integer instruction operates on twice the amount
of data as its 64-bit SIMD integer counterpart.
11.6.12 Branching on Arithmetic Operations
There are no condition codes in SSE or SSE2 states. A packed-data comparison instruction generates a mask which
can then be transferred to an integer register. The following code sequence provides an example of how to perform
a conditional branch, based on the result of an SSE2 arithmetic operation.
cmppd
movmskpd
test
jne
XMM0, XMM1
EAX, XMM0
EAX, 0
BRANCH TARGET
; generates a mask in XMM0
; moves a 2 bit mask to eax
; compare with desired result
The COMISD and UCOMISD instructions update the EFLAGS as the result of a scalar comparison. A conditional
branch can then be scheduled immediately following COMISD/UCOMISD.
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11.6.13 Cacheability Hint Instructions
SSE and SSE2 cacheability control instructions enable the programmer to control prefetching, caching, loading and
storing of data. When correctly used, these instructions improve application performance.
To make efficient use of the processor’s super-scalar microarchitecture, a program needs to provide a steady
stream of data to the executing program to avoid stalling the processor. PREFETCHh instructions minimize the
latency of data accesses in performance-critical sections of application code by allowing data to be fetched into the
processor cache hierarchy in advance of actual usage.
PREFETCHh instructions do not change the user-visible semantics of a program, although they may affect performance. The operation of these instructions is implementation-dependent. Programmers may need to tune code for
each IA-32 processor implementation. Excessive usage of PREFETCHh instructions may waste memory bandwidth
and reduce performance. For more detailed information on the use of prefetch hints, refer to Chapter 7, “Optimizing Cache Usage,”, in the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
The non-temporal store instructions (MOVNTI, MOVNTPD, MOVNTPS, MOVNTDQ, MOVNTQ, MASKMOVQ, and
MASKMOVDQU) minimize cache pollution when writing non-temporal data to memory (see Section 10.4.6.1,
“Cacheability Control Instructions” and Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data”). They
prevent non-temporal data from being written into processor caches on a store operation.
Besides reducing cache pollution, the use of weakly-ordered memory types can be important under certain data
sharing relationships, such as a producer-consumer relationship. The use of weakly ordered memory can make the
assembling of data more efficient; but care must be taken to ensure that the consumer obtains the data that the
producer intended. Some common usage models that may be affected in this way by weakly-ordered stores are:
•
•
•
Library functions that use weakly ordered memory to write results
Compiler-generated code that writes weakly-ordered results
Hand-crafted code
The degree to which a consumer of data knows that the data is weakly ordered can vary for these cases. As a
result, the SFENCE or MFENCE instruction should be used to ensure ordering between routines that produce
weakly-ordered data and routines that consume the data. SFENCE and MFENCE provide a performance-efficient
way to ensure ordering by guaranteeing that every store instruction that precedes SFENCE/MFENCE in program
order is globally visible before a store instruction that follows the fence.
11.6.14 Effect of Instruction Prefixes on the SSE/SSE2 Instructions
Table 11-3 describes the effects of instruction prefixes on SSE and SSE2 instructions. (Table 11-3 also applies to
SIMD integer and SIMD floating-point instructions in SSE3.) Unpredictable behavior can range from prefixes being
treated as a reserved operation on one generation of IA-32 processors to generating an invalid opcode exception
on another generation of processors.
See also “Instruction Prefixes” in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A, for complete description of instruction prefixes.
NOTE
Some SSE/SSE2/SSE3 instructions have two-byte opcodes that are either 2 bytes or 3 bytes in
length. Two-byte opcodes that are 3 bytes in length consist of: a mandatory prefix (F2H, F3H, or
66H), 0FH, and an opcode byte. See Table 11-3.
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Table 11-3. Effect of Prefixes on SSE, SSE2, and SSE3 Instructions
Prefix Type
Address Size Prefix (67H)
Effect on SSE, SSE2 and SSE3 Instructions
Affects instructions with a memory operand.
Reserved for instructions without a memory operand and may result in unpredictable
behavior.
Operand Size (66H)
Reserved and may result in unpredictable behavior.
Segment Override
(2EH,36H,3EH,26H,64H,65H)
Affects instructions with a memory operand.
Repeat Prefixes (F2H and F3H)
Reserved and may result in unpredictable behavior.
Lock Prefix (F0H)
Reserved; generates invalid opcode exception (#UD).
Branch Hint Prefixes(E2H and E3H)
Reserved and may result in unpredictable behavior.
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Reserved for instructions without a memory operand and may result in unpredictable
behavior.
CHAPTER 12
PROGRAMMING WITH INTEL® SSE3, SSSE3,
INTEL® SSE4 AND INTEL® AESNI
This chapter describes SSE3, SSSE3, SSE4 and provides information to assist in writing application programs that
use these extensions.
AESNI and PCLMLQDQ are instruction extensions targeted to accelerate high-speed block encryption and cryptographic processing. Section 12.13 covers these instructions and their relationship to the Advanced Encryption
Standard (AES).
12.1
PROGRAMMING ENVIRONMENT AND DATA TYPES
The programming environment for using SSE3, SSSE3, and SSE4 is unchanged from those shown in Figure 3-1 and
Figure 3-2. SSE3, SSSE3, and SSE4 do not introduce new data types. XMM registers are used to operate on packed
integer data, single-precision floating-point data, or double-precision floating-point data.
One SSE3 instruction uses the x87 FPU for x87-style programming. There are two SSE3 instructions that use the
general registers for thread synchronization. The MXCSR register governs SIMD floating-point operations. Note,
however, that the x87FPU control word does not affect the SSE3 instruction that is executed by the x87 FPU
(FISTTP), other than by unmasking an invalid operand or inexact result exception.
SSE4 instructions do not use MMX registers. The majority of SSE4.21 instructions and SSE4.1 instructions operate
on XMM registers.
12.1.1
SSE3, SSSE3, SSE4 in 64-Bit Mode and Compatibility Mode
In compatibility mode, SSE3, SSSE3, and SSE4 function like they do in protected mode. In 64-bit mode, eight additional XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes.
Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5.
Some SSE3, SSSE3, and SSE4 instructions may be used to operate on general-purpose registers. Use the REX.W
prefix to access 64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the
prefix is ignored.
12.1.2
Compatibility of SSE3/SSSE3 with MMX Technology, the x87 FPU Environment, and
SSE/SSE2 Extensions
SSE3, SSSE3, and SSE4 do not introduce any new state to the Intel 64 and IA-32 execution environments.
For SIMD and x87 programming, the FXSAVE and FXRSTOR instructions save and restore the architectural states
of XMM, MXCSR, x87 FPU, and MMX registers. The MONITOR and MWAIT instructions use general purpose registers
on input, they do not modify the content of those registers.
12.1.3
Horizontal and Asymmetric Processing
Many SSE/SSE2/SSE3/SSSE3 instructions accelerate SIMD data processing using a model referred to as vertical
computation. Using this model, data flow is vertical between the data elements of the inputs and the output.
Figure 12-1 illustrates the asymmetric processing of the SSE3 instruction ADDSUBPD. Figure 12-2 illustrates the
horizontal data movement of the SSE3 instruction HADDPD.
1. Although the presence of CRC32 support is enumerated by CPUID.01:ECX[SSE4.2] = 1, CRC32 operates on general purpose registers.
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X1
X0
Y1
Y0
ADD
SUB
X1 + Y1
X0 -Y0
Figure 12-1. Asymmetric Processing in ADDSUBPD
X1
X0
Y1
Y0
ADD
ADD
Y0 + Y1
X0 + X1
Figure 12-2. Horizontal Data Movement in HADDPD
12.2
OVERVIEW OF SSE3 INSTRUCTIONS
SSE3 extensions include 13 instructions. See:
•
•
Section 12.3, “SSE3 Instructions,” provides an introduction to individual SSE3 instructions.
•
Chapter 13, “System Programming for Instruction Set Extensions and Processor Extended States,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating
SSE/SSE2/SSE3 extensions into an operating-system environment.
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, provide detailed
information on individual instructions.
12.3
SSE3 INSTRUCTIONS
SSE3 instructions are grouped as follows:
•
x87 FPU instruction
— One instruction that improves x87 FPU floating-point to integer conversion
•
SIMD integer instruction
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— One instruction that provides a specialized 128-bit unaligned data load
•
SIMD floating-point instructions
— Three instructions that enhance LOAD/MOVE/DUPLICATE performance
— Two instructions that provide packed addition/subtraction
— Four instructions that provide horizontal addition/subtraction
•
Thread synchronization instructions
— Two instructions that improve synchronization between multi-threaded agents
The instructions are discussed in more detail in the following paragraphs.
12.3.1
x87 FPU Instruction for Integer Conversion
The FISTTP instruction (x87 FPU Store Integer and Pop with Truncation) behaves like FISTP, but uses truncation
regardless of what rounding mode is specified in the x87 FPU control word. The instruction converts the top of stack
(ST0) to integer with rounding to and pops the stack.
The FISTTP instruction is available in three precisions: short integer (word or 16-bit), integer (double word or 32bit), and long integer (64-bit). With FISTTP, applications no longer need to change the FCW when truncation is
required.
12.3.2
SIMD Integer Instruction for Specialized 128-bit Unaligned Data Load
The LDDQU instruction is a special 128-bit unaligned load designed to avoid cache line splits. If the address of a 16byte load is on a 16-byte boundary, LDQQU loads the bytes requested. If the address of the load is not aligned on
a 16-byte boundary, LDDQU loads a 32-byte block starting at the 16-byte aligned address immediately below the
load request. It then extracts the requested 16 bytes.
The instruction provides significant performance improvement on 128-bit unaligned memory accesses at the cost
of some usage model restrictions.
12.3.3
SIMD Floating-Point Instructions That Enhance LOAD/MOVE/DUPLICATE Performance
The MOVSHDUP instruction loads/moves 128-bits, duplicating the second and fourth 32-bit data elements.
•
MOVSHDUP OperandA, OperandB
— OperandA (128 bits, four data elements): 3a, 2a, 1a, 0a
— OperandB (128 bits, four data elements): 3b, 2b, 1b, 0b
— Result (stored in OperandA): 3b, 3b, 1b, 1b
The MOVSLDUP instruction loads/moves 128-bits, duplicating the first and third 32-bit data elements.
•
MOVSLDUP OperandA, OperandB
— OperandA (128 bits, four data elements): 3a, 2a, 1a, 0a
— OperandB (128 bits, four data elements): 3b, 2b, 1b, 0b
— Result (stored in OperandA): 2b, 2b, 0b, 0b
The MOVDDUP instruction loads/moves 64-bits; duplicating the 64 bits from the source.
•
MOVDDUP OperandA, OperandB
— OperandA (128 bits, two data elements): 1a, 0a
— OperandB (64 bits, one data element): 0b
— Result (stored in OperandA): 0b, 0b
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12.3.4
SIMD Floating-Point Instructions Provide Packed Addition/Subtraction
The ADDSUBPS instruction has two 128-bit operands. The instruction performs single-precision addition on the
second and fourth pairs of 32-bit data elements within the operands; and single-precision subtraction on the first
and third pairs.
•
ADDSUBPS OperandA, OperandB
— OperandA (128 bits, four data elements): 3a, 2a, 1a, 0a
— OperandB (128 bits, four data elements): 3b, 2b, 1b, 0b
— Result (stored in OperandA): 3a+3b, 2a-2b, 1a+1b, 0a-0b
The ADDSUBPD instruction has two 128-bit operands. The instruction performs double-precision addition on the
second pair of quadwords, and double-precision subtraction on the first pair.
•
ADDSUBPD OperandA, OperandB
— OperandA (128 bits, two data elements): 1a, 0a
— OperandB (128 bits, two data elements): 1b, 0b
— Result (stored in OperandA): 1a+1b, 0a-0b
12.3.5
SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction
Most SIMD instructions operate vertically. This means that the result in position i is a function of the elements in
position i of both operands. Horizontal addition/subtraction operates horizontally. This means that contiguous data
elements in the same source operand are used to produce a result.
The HADDPS instruction performs a single-precision addition on contiguous data elements. The first data element
of the result is obtained by adding the first and second elements of the first operand; the second element by adding
the third and fourth elements of the first operand; the third by adding the first and second elements of the second
operand; and the fourth by adding the third and fourth elements of the second operand.
•
HADDPS OperandA, OperandB
— OperandA (128 bits, four data elements): 3a, 2a, 1a, 0a
— OperandB (128 bits, four data elements): 3b, 2b, 1b, 0b
— Result (Stored in OperandA): 3b+2b, 1b+0b, 3a+2a, 1a+0a
The HSUBPS instruction performs a single-precision subtraction on contiguous data elements. The first data
element of the result is obtained by subtracting the second element of the first operand from the first element of
the first operand; the second element by subtracting the fourth element of the first operand from the third element
of the first operand; the third by subtracting the second element of the second operand from the first element of
the second operand; and the fourth by subtracting the fourth element of the second operand from the third
element of the second operand.
•
HSUBPS OperandA, OperandB
— OperandA (128 bits, four data elements): 3a, 2a, 1a, 0a
— OperandB (128 bits, four data elements): 3b, 2b, 1b, 0b
— Result (Stored in OperandA): 2b-3b, 0b-1b, 2a-3a, 0a-1a
The HADDPD instruction performs a double-precision addition on contiguous data elements. The first data element
of the result is obtained by adding the first and second elements of the first operand; the second element by adding
the first and second elements of the second operand.
•
HADDPD OperandA, OperandB
— OperandA (128 bits, two data elements): 1a, 0a
— OperandB (128 bits, two data elements): 1b, 0b
— Result (Stored in OperandA): 1b+0b, 1a+0a
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The HSUBPD instruction performs a double-precision subtraction on contiguous data elements. The first data
element of the result is obtained by subtracting the second element of the first operand from the first element of
the first operand; the second element by subtracting the second element of the second operand from the first
element of the second operand.
•
HSUBPD OperandA OperandB
— OperandA (128 bits, two data elements): 1a, 0a
— OperandB (128 bits, two data elements): 1b, 0b
— Result (Stored in OperandA): 0b-1b, 0a-1a
12.3.6
Two Thread Synchronization Instructions
The MONITOR instruction sets up an address range that is used to monitor write-back-stores.
MWAIT enables a logical processor to enter into an optimized state while waiting for a write-back-store to the
address range set up by MONITOR. MONITOR and MWAIT require the use of general purpose registers for its input.
The registers used by MONITOR and MWAIT must be initialized properly; register content is not modified by these
instructions.
12.4
WRITING APPLICATIONS WITH SSE3 EXTENSIONS
The following sections give guidelines for writing application programs and operating-system code that use SSE3
instructions.
12.4.1
Guidelines for Using SSE3 Extensions
The following guidelines describe how to maximize the benefits of using SSE3 extensions:
•
Check that the processor supports SSE3 extensions.
— Application may need to ensure that the target operating system supports SSE3. (Operating system
support for the SSE extensions implies sufficient support for SSE2 extensions and SSE3 extensions.)
•
•
Ensure your operating system supports MONITOR and MWAIT.
Employ the optimization and scheduling techniques described in the Intel® 64 and IA-32 Architectures Optimization Reference Manual (see Section 1.4, “Related Literature”).
12.4.2
Checking for SSE3 Support
Before an application attempts to use the SIMD subset of SSE3 extensions, the application should follow the steps
illustrated in Section 11.6.2, “Checking for SSE/SSE2 Support.” Next, use the additional step provided below:
•
Check that the processor supports the SIMD and x87 SSE3 extensions (if CPUID.01H:ECX.SSE3[bit 0] = 1).
An operating systems that provides application support for SSE, SSE2 also provides sufficient application support
for SSE3. To use FISTTP, software only needs to check support for SSE3.
In the initial implementation of MONITOR and MWAIT, these two instructions are available to ring 0 and conditionally available at ring level greater than 0. Before an application attempts to use the MONITOR and MWAIT instructions, the application should use the following steps:
1. Check that the processor supports MONITOR and MWAIT. If CPUID.01H:ECX.MONITOR[bit 3] = 1, MONITOR
and MWAIT are available at ring 0.
2. Query the smallest and largest line size that MONITOR uses. Use CPUID.05H:EAX.smallest[bits
15:0];EBX.largest[bits15:0]. Values are returned in bytes in EAX and EBX.
3. Ensure the memory address range(s) that will be supplied to MONITOR meets memory type requirements.
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MONITOR and MWAIT are targeted for system software that supports efficient thread synchronization, See Chapter
13 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A for details.
12.4.3
Enable FTZ and DAZ for SIMD Floating-Point Computation
Enabling the FTZ and DAZ flags in the MXCSR register is likely to accelerate SIMD floating-point computation where
strict compliance to the IEEE standard 754-1985 is not required. The FTZ flag is available to Intel 64 and IA-32
processors that support the SSE; DAZ is available to Intel 64 processors and to most IA-32 processors that support
SSE/SSE2/SSE3.
Software can detect the presence of DAZ, modify the MXCSR register, and save and restore state information by
following the techniques discussed in Section 11.6.3 through Section 11.6.6.
12.4.4
Programming SSE3 with SSE/SSE2 Extensions
SIMD instructions in SSE3 extensions are intended to complement the use of SSE/SSE2 in programming SIMD
applications. Application software that intends to use SSE3 instructions should also check for the availability of
SSE/SSE2 instructions.
The FISTTP instruction in SSE3 is intended to accelerate x87 style programming where performance is limited by
frequent floating-point conversion to integers; this happens when the x87 FPU control word is modified frequently.
Use of FISTTP can eliminate the need to access the x87 FPU control word.
12.5
OVERVIEW OF SSSE3 INSTRUCTIONS
SSSE3 provides 32 instructions to accelerate a variety of multimedia and signal processing applications employing
SIMD integer data. See:
•
•
Section 12.6, “SSSE3 Instructions,” provides an introduction to individual SSSE3 instructions.
•
Chapter 13, “System Programming for Instruction Set Extensions and Processor Extended States,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating
SSE/SSE2/SSE3/SSSE3 extensions into an operating-system environment.
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, provide detailed
information on individual instructions.
12.6
SSSE3 INSTRUCTIONS
SSSE3 instructions include:
•
•
•
•
•
•
Twelve instructions that perform horizontal addition or subtraction operations.
•
Two instructions that align data from the composite of two operands.
Six instructions that evaluate the absolute values.
Two instructions that perform multiply and add operations and speed up the evaluation of dot products.
Two instructions that accelerate packed-integer multiply operations and produce integer values with scaling.
Two instructions that perform a byte-wise, in-place shuffle according to the second shuffle control operand.
Six instructions that negate packed integers in the destination operand if the signs of the corresponding
element in the source operand is less than zero.
The operands of these instructions are packed integers of byte, word, or double word sizes. The operands are
stored as 64 or 128 bit data in MMX registers, XMM registers, or memory.
The instructions are discussed in more detail in the following paragraphs.
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12.6.1
Horizontal Addition/Subtraction
In analogy to the packed, floating-point horizontal add and subtract instructions in SSE3, SSSE3 offers similar
capabilities on packed integer data. Data elements of signed words, doublewords are supported. Saturated version
for horizontal add and subtract on signed words are also supported. The horizontal data movement of PHADD is
shown in Figure 12-3.
X3
X2
X1
X0
Y3
Y2
Y1
Y0
ADD
ADD
Y2 + Y3
Y0 + Y1
ADD
ADD
X2 + X3
X0 + X1
Figure 12-3. Horizontal Data Movement in PHADDD
There are six horizontal add instructions (represented by three mnemonics); three operate on 128-bit operands
and three operate on 64-bit operands. The width of each data element is either 16 bits or 32 bits. The mnemonics
are listed below.
•
PHADDW adds two adjacent, signed 16-bit integers horizontally from the source and destination operands and
packs the signed 16-bit results to the destination operand.
•
PHADDSW adds two adjacent, signed 16-bit integers horizontally from the source and destination operands
and packs the signed, saturated 16-bit results to the destination operand.
•
PHADDD adds two adjacent, signed 32-bit integers horizontally from the source and destination operands and
packs the signed 32-bit results to the destination operand.
There are six horizontal subtract instructions (represented by three mnemonics); three operate on 128-bit operands and three operate on 64-bit operands. The width of each data element is either 16 bits or 32 bits. These are
listed below.
•
PHSUBW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the
most significant word from the least significant word of each pair in the source and destination operands. The
signed 16-bit results are packed and written to the destination operand.
•
PHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the
most significant word from the least significant word of each pair in the source and destination operands. The
signed, saturated 16-bit results are packed and written to the destination operand.
•
PHSUBD performs horizontal subtraction on each adjacent pair of 32-bit signed integers by subtracting the
most significant doubleword from the least significant double word of each pair in the source and destination
operands. The signed 32-bit results are packed and written to the destination operand.
12.6.2
Packed Absolute Values
There are six packed-absolute-value instructions (represented by three mnemonics). Three operate on 128-bit
operands and three operate on 64-bit operands. The widths of data elements are 8 bits, 16 bits or 32 bits. The
absolute value of each data element of the source operand is stored as an UNSIGNED result in the destination
operand.
•
PABSB computes the absolute value of each signed byte data element.
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•
•
PABSW computes the absolute value of each signed 16-bit data element.
PABSD computes the absolute value of each signed 32-bit data element.
12.6.3
Multiply and Add Packed Signed and Unsigned Bytes
There are two multiply-and-add-packed-signed-unsigned-byte instructions (represented by one mnemonic). One
operates on 128-bit operands and the other operates on 64-bit operands. Multiplications are performed on each
vertical pair of data elements. The data elements in the source operand are signed byte values, the input data
elements of the destination operand are unsigned byte values.
•
PMADDUBSW multiplies each unsigned byte value with the corresponding signed byte value to produce an
intermediate, 16-bit signed integer. Each adjacent pair of 16-bit signed values are added horizontally. The
signed, saturated 16-bit results are packed to the destination operand.
12.6.4
Packed Multiply High with Round and Scale
There are two packed-multiply-high-with-round-and-scale instructions (represented by one mnemonic). One operates on 128-bit operands and the other operates on 64-bit operands.
•
PMULHRSW multiplies vertically each signed 16-bit integer from the destination operand with the corresponding signed 16-bit integer of the source operand, producing intermediate, signed 32-bit integers. Each
intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always performed by adding
1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by selecting the 16 bits
immediately to the right of the most significant bit of each 18-bit intermediate result and packed to the
destination operand.
12.6.5
Packed Shuffle Bytes
There are two packed-shuffle-bytes instructions (represented by one mnemonic). One operates on 128-bit operands and the other operates on 64-bit operands. The shuffle operations are performed bytewise on the destination
operand using the source operand as a control mask.
•
PSHUFB permutes each byte in place, according to a shuffle control mask. The least significant three or four bits
of each shuffle control byte of the control mask form the shuffle index. The shuffle mask is unaffected. If the
most significant bit (bit 7) of a shuffle control byte is set, the constant zero is written in the result byte.
12.6.6
Packed Sign
There are six packed-sign instructions (represented by three mnemonics). Three operate on 128-bit operands and
three operate on 64-bit operands. The widths of each data element for these instructions are 8 bit, 16 bit or 32 bit
signed integers.
•
PSIGNB/W/D negates each signed integer element of the destination operand if the sign of the corresponding
data element in the source operand is less than zero.
12.6.7
Packed Align Right
There are two packed-align-right instructions (represented by one mnemonic). One operates on 128-bit operands
and the other operates on 64-bit operands. These instructions concatenate the destination and source operand into
a composite, and extract the result from the composite according to an immediate constant.
•
PALIGNR’s source operand is appended after the destination operand forming an intermediate value of twice
the width of an operand. The result is extracted from the intermediate value into the destination operand by
selecting the 128-bit or 64-bit value that are right-aligned to the byte offset specified by the immediate value.
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12.7
WRITING APPLICATIONS WITH SSSE3 EXTENSIONS
The following sections give guidelines for writing application programs and operating-system code that use SSSE3
instructions.
12.7.1
Guidelines for Using SSSE3 Extensions
The following guidelines describe how to maximize the benefits of using SSSE3 extensions:
•
•
Check that the processor supports SSSE3 extensions.
•
Employ the optimization and scheduling techniques described in the Intel® 64 and IA-32 Architectures Optimization Reference Manual (see Section 1.4, “Related Literature”).
Ensure that your operating system supports SSE/SSE2/SSE3/SSSE3 extensions. (Operating system support
for the SSE extensions implies sufficient support for SSE2, SSE3, and SSSE3.)
12.7.2
Checking for SSSE3 Support
Before an application attempts to use the SSSE3 extensions, the application should follow the steps illustrated in
Section 11.6.2, “Checking for SSE/SSE2 Support.” Next, use the additional step provided below:
•
Check that the processor supports SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1).
12.8
SSE3/SSSE3 AND SSE4 EXCEPTIONS
SSE3, SSSE3, and SSE4 instructions can generate the same type of memory-access and non-numeric exceptions
as other Intel 64 or IA-32 instructions. Existing exception handlers generally handle these exceptions without code
modification.
FISTTP can generate floating-point exceptions. Some SSE3 instructions can also generate SIMD floating-point
exceptions.
SSE3 additions and changes are noted in the following sections. See also: Section 11.5, “SSE, SSE2, and SSE3
Exceptions”.
12.8.1
Device Not Available (DNA) Exceptions
SSE3, SSSE3, and SSE4 will cause a DNA Exception (#NM) if the processor attempts to execute an SSE3 instruction while CR0.TS[bit 3] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0, execution of an SSE3 extension will cause an
invalid opcode fault regardless of the state of CR0.TS[bit 3].
Similarly, an attempt to execute an SSSE3 instruction on a processor that reports CPUID.01H:ECX.SSSE3[bit 9] =
0 will cause an invalid opcode fault regardless of the state of CR0.TS[bit 3]. An attempt to execute an SSE4.1
instruction on a processor that reports CPUID.01H:ECX.SSE4_1[bit 19] = 0 will cause an invalid opcode fault
regardless of the state of CR0.TS[bit 3].
An attempt to execute PCMPGTQ or any one of the four string processing instructions in SSE4.2 on a processor that
reports CPUID.01H:ECX.SSSE3[bit 20] = 0 will cause an invalid opcode fault regardless of the state of
CR0.TS[bit 3]. CRC32 and POPCNT do not cause #NM.
12.8.2
Numeric Error flag and IGNNE#
Most SSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the IGNNE# pin. With one
exception, all use the exception 19 (#XM) software exception for error reporting. The exception is FISTTP; it
behaves like other x87-FP instructions.
SSSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the IGNNE# pin.
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SSSE3 instructions do not cause floating-point errors. Floating-point numeric errors for SSE4.1 are described in
Section 12.8.4. SSE4.2 instructions do not cause floating-point errors.
12.8.3
Emulation
CR0.EM is used by some software to emulate x87 floating-point instructions, CR0.EM[bit 2] cannot be used for
emulation of SSE, SSE2, SSE3, SSSE3, and SSE4. If an SSE3, SSSE3, and SSE4 instruction executes with
CR0.EM[bit 2] set, an invalid opcode exception (INT 6) is generated instead of a device not available exception (INT
7).
12.8.4
IEEE 754 Compliance of SSE4.1 Floating-Point Instructions
The six SSE4.1 instructions that perform floating-point arithmetic are:
•
•
•
•
•
•
DPPS
DPPD
ROUNDPS
ROUNDPD
ROUNDSS
ROUNDSD
Dot Product operations are not specified in IEEE-754. When neither FTZ nor DAZ are enabled, the dot product
instructions resemble sequences of IEEE-754 multiplies and adds (with rounding at each stage), except that the
treatment of input NaN’s is implementation specific (there will be at least one NaN in the output). The input select
fields (bits imm8[4:7]) force input elements to +0.0f prior to the first multiply and will suppress input exceptions
that would otherwise have been be generated.
As a convenience to the exception handler, any exceptions signaled from DPPS or DPPD leave the destination
unmodified.
Round operations signal invalid and precision only.
Table 12-1. SIMD numeric exceptions signaled by SSE4.1
DPPS
DPPD
ROUNDPS
ROUNDSS
ROUNDPD
ROUNDSD
Overflow
X
X
Underflow
X
X
Invalid
X
X
X (1)
X (1)
Inexact Precision
X
X
X (2)
X (2)
Denormal
X
X
NOTE:
1. Invalid is signaled only if Src = SNaN.
2. Precision is ignored (regardless of the MXCSR precision mask) if if imm8[3] = ‘1’.
The other SSE4.1 instructions with floating-point arguments (BLENDPS, BLENDPD, BLENDVPS, BLENDVPD,
INSERTPS, EXTRACTPS) do not signal any SIMD numeric exceptions.
12.9
SSE4 OVERVIEW
SSE4 comprises of two sets of extensions: SSE4.1 and SSE4.2. SSE4.1 is targeted to improve the performance of
media, imaging, and 3D workloads. SSE4.1 adds instructions that improve compiler vectorization and significantly
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increase support for packed dword computation. The technology also provides a hint that can improve memory
throughput when reading from uncacheable WC memory type.
The 47 SSE4.1 instructions include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Two instructions perform packed dword multiplies.
Two instructions perform floating-point dot products with input/output selects.
One instruction performs a load with a streaming hint.
Six instructions simplify packed blending.
Eight instructions expand support for packed integer MIN/MAX.
Four instructions support floating-point round with selectable rounding mode and precision exception override.
Seven instructions improve data insertion and extractions from XMM registers
Twelve instructions improve packed integer format conversions (sign and zero extensions).
One instruction improves SAD (sum absolute difference) generation for small block sizes.
One instruction aids horizontal searching operations.
One instruction improves masked comparisons.
One instruction adds qword packed equality comparisons.
One instruction adds dword packing with unsigned saturation.
The SSE4.2 instructions operating on XMM registers improve performance in the following areas:
•
String and text processing that can take advantage of single-instruction multiple-data programming
techniques.
•
A SIMD integer instruction that enhances the capability of the 128-bit integer SIMD capability in SSE4.1.
12.10
SSE4.1 INSTRUCTION SET
12.10.1 Dword Multiply Instructions
SSE4.1 adds two dword multiply instructions that aid vectorization. They allow four simultaneous 32 bit by 32 bit
multiplies. PMULLD returns a low 32-bits of the result and PMULDQ returns a 64-bit signed result. These represent
the most common integer multiply operation. See Table 12-2.
Table 12-2. Enhanced 32-bit SIMD Multiply Supported by SSE4.1
Result
32 bit Integer Operation
unsigned x unsigned
signed x signed
Low 32-bit
(not available)
PMULLD
High 32-bit
(not available)
(not available)
64-bit
PMULUDQ*
PMULDQ
NOTE:
* Available prior to SSE4.1.
12.10.2 Floating-Point Dot Product Instructions
SSE4.1 adds two instructions for double-precision (for up to 2 elements; DPPD) and single-precision dot products
(for up to 4 elements; DPPS).
These dot-product instructions include source select and destination broadcast which generally improves the flexibility. For example, a single DPPS instruction can be used for a 2, 3, or 4 element dot product.
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12.10.3 Streaming Load Hint Instruction
Historically, CPU read accesses of WC memory type regions have significantly lower throughput than accesses to
cacheable memory.
The streaming load instruction in SSE4.1, MOVNTDQA, provides a non-temporal hint that can cause adjacent 16byte items within an aligned 64-byte region of WC memory type (a streaming line) to be fetched and held in a small
set of temporary buffers (“streaming load buffers”). Subsequent streaming loads to other aligned 16-byte items in
the same streaming line may be satisfied from the streaming load buffer and can improve throughput.
Programmers are advised to use the following practices to improve the efficiency of MOVNTDQA streaming loads
from WC memory:
•
•
Streaming loads must be 16-byte aligned.
•
Temporally group streaming loads from at most a few streaming lines together. The number of streaming load
buffers is small; grouping a modest number of streams will avoid running out of streaming load buffers and the
resultant re-fetching of streaming lines from memory.
•
Avoid writing to a streaming line until all 16-byte-aligned reads from the streaming line have occurred. Reading
a 16-byte item from a streaming line that has been written, may cause the streaming line to be re-fetched.
•
Avoid reading a given 16-byte item within a streaming line more than once; repeated loads of a particular 16byte item are likely to cause the streaming line to be re-fetched.
•
The streaming load buffers, reflecting the WC memory type characteristics, are not required to be snooped by
operations from other agents. Software should not rely upon such coherency actions to provide any data
coherency with respect to other logical processors or bus agents. Rather, software must insure the consistency
of WC memory accesses between producers and consumers.
•
Streaming loads may be weakly ordered and may appear to software to execute out of order with respect to
other memory operations. Software must explicitly use MFENCE if it needs to preserve order among streaming
loads or between streaming loads and other memory operations.
•
Streaming loads must not be used to reference memory addresses that are mapped to I/O devices having side
effects or when reads to these devices are destructive. This is because MOVNTDQA is speculative in nature.
Temporally group streaming loads of the same streaming cache line for effective use of the small number of
streaming load buffers. If loads to the same streaming line are excessively spaced apart, it may cause the
streaming line to be re-fetched from memory.
Example 12-1 provides a sketch of the basic assembly sequences that illustrate the principles of using MOVNTDQA
in a situation with a producer-consumer accessing a WC memory region.
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Example 12-1. Sketch of MOVNTDQA Usage of a Consumer and a PCI Producer
// P0: producer is a PCI device writing into the WC space
# the PCI device updates status through a UC flag, "u_dev_status" .
# the protocol for "u_dev_status" : 0: produce; 1: consume; 2: all done
mov eax, $0
mov [u_dev_status], eax
producerStart:
mov eax, [u_dev_status] # poll status flag to see if consumer is requestion data
cmp eax, $0
#
jne done
# I no longer need to produce
commence PCI writes to WC region..
mov eax, $1 # producer ready to notify the consumer via status flag
mov [u_dev_status], eax
# now wait for consumer to signal its status
spinloop:
cmp [u_dev_status], $1 # did I get a signal from the consumer ?
jne producerStart
# yes I did
jmp spinloop
# check again
done:
// producer is finished at this point
// P1: consumer check PCI status flag to consume WC data
mov eax, $0 # request to the producer
mov [u_dev_status], eax
consumerStart:
mov; eax, [u_dev_status] # reads the value of the PCI status
cmp eax, $1
# has producer written
jne consumerStart
# tight loop; make it more efficient with pause, etc.
mfence # producer finished device writes to WC, ensure WC region is coherent
ntread:
movntdqa xmm0, [addr]
movntdqa xmm1, [addr + 16]
movntdqa xmm2, [addr + 32]
movntdqa xmm3, [addr + 48]
… # do any more NT reads as needed
mfence # ensure PCI device reads the correct value of [u_dev_status]
# now decide whether we are done or we need the producer to produce more data
# if we are done write a 2 into the variable, otherwise write a 0 into the variable
mov eax, $0/$2
# end or continue producing
mov [u_dev_status], eax
# if I want to consume again I will jump back to consumerStart after storing a 0 into eax
# otherwise I am done
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12.10.4 Packed Blending Instructions
SSE4.1 adds 6 instructions used for blending (BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB,
PBLENDW).
Blending conditionally copies a data element in a source operand to the same element in the destination. SSE4.1
instructions improve blending operations for most field sizes. A single new SSE4.1 instruction can generally replace
a sequence of 2 to 4 operations using previous architectures.
The variable blend instructions (BLENDVPS, BLENDVPD, PBLENDW) introduce the use of control bits stored in an
implicit XMM register (XMM0). The most significant bit in each field (the sign bit, for 2’s complement integer or
floating-point) is used as a selector. See Table 12-3.
Table 12-3. Blend Field Size and Control Modes Supported by SSE4.1
Instructions
Packed
Double FP
BLENDPS
BLENDPD
Packed
QWord
Packed
DWord
Packed
Word
Packed Byte
X
Blend Control
Imm8
X
BLENDVPS
BLENDVPD
Packed
Single FP
Imm8
X
X
X(1)
XMM0
X(1)
XMM0
PBLENDVB
(2)
(2)
(2)
PBLENDW
X
X
X
X
XMM0
Imm8
NOTE:
1. Use of floating-point SIMD instructions on integer data types may incur performance penalties.
2. Byte variable blend can be used for larger sized fields by reformatting (or shuffling) the blend control.
12.10.5 Packed Integer MIN/MAX Instructions
SSE4.1 adds 8 packed integer MIN and MAX instructions (PMINUW, PMINUD, PMINSB, PMINSD; PMAXUW,
PMAXUD, PMAXSB, PMAXSD).
Four 32-bit integer packed MIN and MAX instructions operate on unsigned and signed dwords. Two instructions
operate on signed bytes. Two instructions operate on unsigned words. See Table 12-4.
Table 12-4. Enhanced SIMD Integer MIN/MAX Instructions Supported by SSE4.1
Integer Width
Integer
Format
Byte
Word
DWord
Unsigned
PMINUB*
PMAXUB*
PMINUW
PMAXUW
PMINUD
PMAXUD
Signed
PMINSB
PMAXSB
PMINSW*
PMAXSW*
PMINSD
PMAXSD
NOTE:
* Available prior to SSE4.1.
12.10.6 Floating-Point Round Instructions with Selectable Rounding Mode
High level languages and libraries often expose rounding operations having a variety of numeric rounding and
exception behaviors. Using SSE/SSE2/SSE3 instructions to mitigate the rounding-mode-related problem is sometimes not straight forward.
SSE4.1 introduces four rounding instructions (ROUNDPS, ROUNDPD, ROUNDSS, ROUNDSD) that cover scalar and
packed single- and double-precision floating-point operands. The rounding mode can be selected using an immediate from one of the IEEE-754 modes (Nearest, -Inf, +Inf, and Truncate) without changing the current rounding
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mode; or the instruction can be forced to use the current rounding mode. Another bit in the immediate is used to
suppress inexact precision exceptions.
Rounding instructions in SSE4.1 generally permit single-instruction solutions to C99 functions ceil(), floor(),
trunc(), rint(), nearbyint(). These instructions simplify the implementations of half-way-away-from-zero rounding
modes as used by C99 round() and F90’s nint().
12.10.7 Insertion and Extractions from XMM Registers
SSE4.1 adds 7 instructions (corresponding to 9 assembly instruction mnemonics) that simplify data insertion and
extraction between general-purpose register (GPR) and XMM registers (EXTRACTPS, INSERTPS, PINSRB, PINSRD,
PINSRQ, PEXTRB, PEXTRW, PEXTRD, and PEXTRQ). When accessing memory, no alignment is required for any of
these instructions (unless alignment checking is enabled).
EXTRACTPS extracts a single-precision floating-point value from any dword offset in an XMM register and stores
the result to memory or a general-purpose register. INSERTPS inserts a single floating-point value from either a
32-bit memory location or from specified element in an XMM register to a selected element in the destination XMM
register. In addition, INSERTPS allows the insertion of +0.0f into any destination elements using a mask.
PINSRB, PINSRD, and PINSRQ insert byte, dword, or qword integer values from a register or memory into an XMM
register. Insertion of integer word values were already supported by SSE2 (PINSRW).
PEXTRB, PEXTRW, PEXTRD, and PEXTRQ extract byte, word, dword, and qword from an XMM register and insert the
values into a general-purpose register or memory.
12.10.8 Packed Integer Format Conversions
A common type of operation on packed integers is the conversion by zero- or sign-extension of packed integers
into wider data types. SSE4.1 adds 12 instructions that convert from a smaller packed integer type to a larger
integer type (PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXWD, PMOVZXWD, PMOVSXBQ,
PMOVZXBQ, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, PMOVZXDQ).
The source operand is from either an XMM register or memory; the destination is an XMM register. See Table 12-5.
When accessing memory, no alignment is required for any of the instructions unless alignment checking is enabled.
In which case, all conversions must be aligned to the width of the memory reference. The number of elements
converted (and width of memory reference) is illustrated in Table 12-6. The alignment requirement is shown in
parenthesis.
Table 12-5. New SIMD Integer conversions supported by SSE4.1
Source Type
Destination
Type
Byte
Word
Signed Word
Unsigned Word
PMOVSXBW
PMOVZXBW
Signed Dword
Unsigned Dword
PMOVSXBD
PMOVZXBD
PMOVSXWD
PMOVZXWD
Signed Qword
Unsigned Qword
PMOVSXBQ
PMOVZXBQ
PMOVSXWQ
PMOVZXWQ
Dword
PMOVSXDQ
PMOVZXDQ
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Table 12-6. New SIMD Integer Conversions Supported by SSE4.1
Source Type
Destination
Type
Byte
Word
Word
Dword
8 (64 bits)
Dword
4 (32 bits)
4 (64 bits)
Qword
2 (16 bits)
2 (32 bits)
2 (64 bits)
12.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks
SSE4.1 adds an instruction (MPSADBW) that performs eight 4-byte wide SAD operations per instruction to produce
eight results. Compared to PSADBW, MPSADBW operates on smaller chunks (4-byte instead of 8-byte chunks); this
makes the instruction better suited to video coding standards such as VC.1 and H.264. MPSADBW performs four
times the number of absolute difference operations than that of PSADBW (per instruction). This can improve
performance for dense motion searches.
MPSADBW uses a 4-byte wide field from a source operand; the offset of the 4-byte field within the 128-bit source
operand is specified by two immediate control bits. MPSADBW produces eight 16-bit SAD results. Each 16-bit SAD
result is formed from overlapping pairs of 4 bytes in the destination with the 4-byte field from the source operand.
MPSADBW uses eleven consecutive bytes in the destination operand, its offset is specified by a control bit in the
immediate byte (i.e. the offset can be from byte 0 or from byte 4). Figure 12-4 illustrates the operation of
MPSADBW. MPSADBW can simplify coding of dense motion estimation by providing source and destination offset
control, higher throughput of SAD operations, and the smaller chunk size.
Imm[1:0]*32
127
96
Source
64
Abs. Diff.
Destination
0
Imm[2]*32
Sum
16
127
0
Figure 12-4. MPSADBW Operation
12.10.10 Horizontal Search
SSE4.1 adds a search instruction (PHMINPOSUW) that finds the value and location of the minimum unsigned word
from one of 8 horizontally packed unsigned words. The resulting value and location (offset within the source) are
packed into the low dword of the destination XMM register.
Rapid search is often a significant component of motion estimation. MPSADBW and PHMINPOSUW can be used
together to improve video encode.
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12.10.11 Packed Test
The packed test instruction PTEST is similar to a 128-bit equivalent to the legacy instruction TEST. With PTEST, the
source argument is typically used like a bit mask.
PTEST performs a logical AND between the destination with this mask and sets the ZF flag if the result is zero. The
CF flag (zero for TEST) is set if the inverted mask AND’d with the destination is all zero. Because the destination is
not modified, PTEST simplifies branching operations (such as branching on signs of packed floating-point numbers,
or branching on zero fields).
12.10.12 Packed Qword Equality Comparisons
SSE4.1 adds a 128-bit packed qword equality test. The new instruction (PCMPEQQ) is identical to PCMPEQD, but
has qword granularity.
12.10.13 Dword Packing With Unsigned Saturation
SSE4.1 adds a new instruction PACKUSDW to complete the set of small integer pack instructions in the family of
SIMD instruction extensions. PACKUSDW packs dword to word with unsigned saturation. See Table 12-7 for the
complete set of packing instructions for small integers.
Table 12-7. Enhanced SIMD Pack support by SSE4.1
Saturation
Type
Pack Type
12.11
DWord -> word
Word -> Byte
Unsigned
PACKUSDW (new!)
PACKUSWB
Signed
PACKSSDW
PACKSSWB
SSE4.2 INSTRUCTION SET
Five of the seven SSE4.2 instructions can use an XMM register as a source or destination. These include four
text/string processing instructions and one packed quadword compare SIMD instruction. Programming these five
SSE4.2 instructions is similar to programming 128-bit Integer SIMD in SSE2/SSSE3. SSE4.2 does not provide any
64-bit integer SIMD instructions.
12.11.1 String and Text Processing Instructions
String and text processing instructions in SSE4.2 allocates 4 opcodes to provide a rich set of string and text
processing capabilities that traditionally required many more opcodes. These 4 instructions use XMM registers to
process string or text elements of up to 128-bits (16 bytes or 8 words). Each instruction uses an immediate byte
to support a rich set of programmable controls. A string-processing SSE4.2 instruction returns the result of
processing each pair of string elements using either an index or a mask.
The capabilities of the string/text processing instructions include:
•
•
•
•
•
Handling string/text fragments consisting of bytes or words, either signed or unsigned
Support for partial string or fragments less than 16 bytes in length, using either explicit length or implicit nulltermination
Four types of string compare operations on word/byte elements
Up to 256 compare operations performed in a single instruction on all string/text element pairs
Built-in aggregation of intermediate results from comparisons
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•
•
•
•
•
Programmable control of processing on intermediate results
Programmable control of output formats in terms of an index or mask
Bi-directional support for the index format
Support for two mask formats: bit or natural element width
Not requiring 16-byte alignment for memory operand
The four SSE4.2 instructions that process text/string fragments are:
•
•
•
•
PCMPESTRI — Packed compare explicit-length strings, return index in ECX/RCX
PCMPESTRM — Packed compare explicit-length strings, return mask in XMM0
PCMPISTRI — Packed compare implicit-length strings, return index in ECX/RCX
PCMPISTRM — Packed compare implicit-length strings, return mask in XMM0
All four require the use of an immediate byte to control operation. The two source operands can be XMM registers
or a combination of XMM register and memory address. The immediate byte provides programmable control with
the following attributes:
•
•
•
•
Input data format
Compare operation mode
Intermediate result processing
Output selection
Depending on the output format associated with the instruction, the text/string processing instructions implicitly
uses either a general-purpose register (ECX/RCX) or an XMM register (XMM0) to return the final result.
Two of the four text-string processing instructions specify string length explicitly. They use two general-purpose
registers (EDX, EAX) to specify the number of valid data elements (either word or byte) in the source operands. The
other two instructions specify valid string elements using null termination. A data element is considered valid only
if it has a lower index than the least significant null data element.
12.11.1.1 Memory Operand Alignment
The text and string processing instructions in SSE4.2 do not perform alignment checking on memory operands.
This is different from most other 128-bit SIMD instructions accessing the XMM registers. The absence of an alignment check for these four instructions does not imply any modification to the existing definitions of other instructions.
12.11.2 Packed Comparison SIMD Integer Instruction
SSE4.2 also provides a 128-bit integer SIMD instruction PCMPGTQ that performs logical compare of greater-than
on packed integer quadwords.
12.12
WRITING APPLICATIONS WITH SSE4 EXTENSIONS
12.12.1 Guidelines for Using SSE4 Extensions
The following guidelines describe how to maximize the benefits of using SSE4 extensions:
•
•
Check that the processor supports SSE4 extensions.
•
Employ the optimization and scheduling techniques described in the Intel® 64 and IA-32 Architectures Optimization Reference Manual (see Section 1.4, “Related Literature”).
Ensure that your operating system supports SSE/SSE2/SSE3/SSSE3 extensions. (Operating system support
for the SSE extensions implies sufficient support for SSE2, SSE3, SSSE3, and SSE4.)
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12.12.2 Checking for SSE4.1 Support
Before an application attempts to use SSE4.1 instructions, the application should follow the steps illustrated in
Section 11.6.2, “Checking for SSE/SSE2 Support.” Next, use the additional step provided below:
Check that the processor supports SSE4.1 (if CPUID.01H:ECX.SSE4_1[bit 19] = 1), SSE3 (if
CPUID.01H:ECX.SSE3[bit 0] = 1), and SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1).
12.12.3 Checking for SSE4.2 Support
Before an application attempts to use the following SSE4.2 instructions: PCMPESTRI/PCMPESTRM/PCMPISTRI/PCMPISTRM, PCMPGTQ;the application should follow the steps illustrated in Section 11.6.2, “Checking for
SSE/SSE2 Support.” Next, use the additional step provided below:
Check that the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1), SSE4.1 (if
CPUID.01H:ECX.SSE4_1[bit 19] = 1), and SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1).
Before an application attempts to use the CRC32 instruction, it must check that the processor supports SSE4.2 (if
CPUID.01H:ECX.SSE4_2[bit 20] = 1).
Before an application attempts to use the POPCNT instruction, it must check that the processor supports SSE4.2 (if
CPUID.01H:ECX.SSE4_2[bit 20] = 1) and POPCNT (if CPUID.01H:ECX.POPCNT[bit 23] = 1).
12.13
AESNI OVERVIEW
The AESNI extension provides six instructions to accelerate symmetric block encryption/decryption of 128-bit data
blocks using the Advanced Encryption Standard (AES) specified by the NIST publication FIPS 197. Specifically, two
instructions (AESENC, AESENCLAST) target the AES encryption rounds, two instructions (AESDEC, AESDECLAST)
target AES decryption rounds using the Equivalent Inverse Cipher. One instruction (AESIMC) targets the Inverse
MixColumn transformation primitive and one instruction (AESKEYGEN) targets generation of round keys from the
cipher key for the AES encryption/decryption rounds.
AES supports encryption/decryption using cipher key lengths of 128, 192, and 256 bits by processing the data
block in 10, 12, 14 rounds of predefined transformations. Figure 12-5 depicts the cryptographic processing of a
block of 128-bit plain text into cipher text.
RK(0)
RK(n-1)
RK(1)
Rounds 2.. n-2
XOR
Round 1
Plain text
AES State
AES State
AES State
Last
Round
Cipher text
n-1
AES-128: n = 10
AES-192: n = 12
AES-256: n = 14
Figure 12-5. AES State Flow
The predefined AES transformation primitives are described in the next few sections, they are also referenced in
the operation flow of instruction reference page of these instructions.
12.13.1 Little-Endian Architecture and Big-Endian Specification (FIPS 197)
FIPS 197 document defines the Advanced Encryption Standard (AES) and includes a set of test vectors for testing
all of the steps in the algorithm, and can be used for testing and debugging.
Vol. 1 12-19
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
The following observation is important for using the AES instructions offered in Intel 64 Architecture: FIPS 197 text
convention is to write hex strings with the low-memory byte on the left and the high-memory byte on the right.
Intel’s convention is the reverse. It is similar to the difference between Big Endian and Little Endian notations.
In other words, a 128 bits vector in the FIPS document, when read from left to right, is encoded as [7:0, 15:8,
23:16, 31:24, …127:120]. Note that inside the byte, the encoding is [7:0], so the first bit from the left is the most
significant bit. In practice, the test vectors are written in hexadecimal notation, where pairs of hexadecimal digits
define the different bytes. To translate the FIPS 197 notation to an Intel 64 architecture compatible (“Little
Endian”) format, each test vector needs to be byte-reflected to [127:120,… 31:24, 23:16, 15:8, 7:0].
Example A:
FIPS Test vector: 000102030405060708090a0b0c0d0e0fH
Intel AES Hardware: 0f0e0d0c0b0a09080706050403020100H
It should be pointed out that the only thing at issue is a textual convention, and programmers do not need to
perform byte-reversal in their code, when using the AES instructions.
12.13.1.1 AES Data Structure in Intel 64 Architecture
The AES instructions that are defined in this document operate on one or on two 128 bits source operands: State
and Round Key. From the architectural point of view, the state is input in an xmm register and the Round key is
input either in an xmm register or a 128-bit memory location.
In AES algorithm, the state (128 bits) can be viewed as 4 32-bit doublewords (“Word”s in AES terminology): X3,
X2, X1, X0.
The state may also be viewed as a set of 16 bytes. The 16 bytes can also be viewed as a 4x4 matrix of bytes where
S(i, j) with i, j = 0, 1, 2, 3 compose the 32-bit “word”s as follows:
X0 = S (3, 0) S (2, 0) S (1, 0) S (0, 0)
X1 = S (3, 1) S (2, 1) S (1, 1) S (0, 1)
X2 = S (3, 2) S (2, 2) S (1, 2) S (0, 2)
X3 = S (3, 3) S (2, 3) S (1, 3) S (0, 3)
The following tables, Table 12-8 through Table 12-11, illustrate various representations of a 128-bit state.
Table 12-8. Byte and 32-bit Word Representation of a 128-bit State
Byte #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit Position
127120
119112
111103
10396
9588
8780
7972
7164
6356
5548
4740
3932
3124
2316
158
127 - 96
95 - 64
64 - 32
31 - 0
X3
X2
X1
X0
State Word
State Byte
P
O
N
M
L
K
J
I
H
G
F
E
D
C
0
70
B
Table 12-9. Matrix Representation of a 128-bit State
A
E
I
M
S(0, 0)
S(0, 1)
S(0, 2)
S(0, 3)
B
F
J
N
S(1, 0)
S(1, 1)
S(1, 2)
S(1, 3)
C
G
K
O
S(2, 0)
S(2, 1)
S(2, 2)
S(2, 3)
D
H
L
P
S(3, 0)
S(3, 1)
S(3, 2)
S(3, 3)
Example:
FIPS vector: d4 bf 5d 30 e0 b4 52 ae b8 41 11 f1 1e 27 98 e5
12-20 Vol. 1
A
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
This vector has the “least significant” byte d4 and the significant byte e5 (written in Big Endian format in the FIPS
document). When it is translated to IA notations, the encoding is:
Table 12-10. Little Endian Representation of a 128-bit State
Byte #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
State Byte
P
O
N
M
L
K
J
I
H
G
F
E
D
C
B
A
State Value
e5
98
27
1e
f1
11
41
b8
ae
52
b4
e0
30
5d
bf
d4
Table 12-11. Little Endian Representation of a 4x4 Byte Matrix
A
E
I
M
d4
e0
b8
1e
B
F
J
N
bf
b4
41
27
C
G
K
O
5d
52
11
98
D
H
L
P
30
ae
f1
e5
12.13.2 AES Transformations and Functions
The following functions and transformations are used in the algorithmic descriptions of AES instruction extensions
AESDEC, AESDECLAST, AESENC, AESENCLAST, AESIMC, AESKEYGENASSIST.
Note that these transformations are expressed here in a Little Endian format (and not as in the FIPS 197 document).
•
MixColumns(): A byte-oriented 4x4 matrix transformation on the matrix representation of a 128-bit AES state.
A FIPS-197 defined 4x4 matrix is multiplied to each 4x1 column vector of the AES state. The columns are
considered polynomials with coefficients in the Finite Field that is used in the definition of FIPS 197, the
operations (“multiplication” and “addition”) are in that Finite Field, and the polynomials are reduced modulo
x4+1.
The MixColumns() transformation defines the relationship between each byte of the result state, represented
as S’(i, j) of a 4x4 matrix (see Section 12.13.1), as a function of input state bytes, S(i, j), as follows
S’(0, j) FF_MUL( 02H, S(0, j) ) XOR FF_MUL(03H, S(1, j) ) XOR S(2, j) XOR S(3, j)
S’(1, j) S(0, j) XOR FF_MUL( 02H, S(1, j) ) XOR FF_MUL(03H, S(2, j) ) XOR S(3, j)
S’(2, j) S(0, j) XOR S(1, j) XOR FF_MUL( 02H, S(2, j) ) XOR FF_MUL(03H, S(3, j) )
S’(3, j) FF_MUL(03H, S(0, j) ) XOR S(1, j) XOR S(2, j) XOR FF_MUL( 02H, S(3, j) )
where j = 0, 1, 2, 3. FF_MUL(Byte1, Byte2) denotes the result of multiplying two elements (represented by
Byte1 and byte2) in the Finite Field representation that defines AES. The result of produced bye
FF_MUL(Byte1, Byte2) is an element in the Finite Field (represented as a byte). A Finite Field is a field with a
finite number of elements, and when this number can be represented as a power of 2 (2n), its elements can
be represented as the set of 2n binary strings of length n. AES uses a finite field with n=8 (having 256
elements). With this representation, “addition” of two elements in that field is a bit-wise XOR of their binarystring representation, producing another element in the field. Multiplication of two elements in that field is
defined using an irreducible polynomial (for AES, this polynomial is m(x) = x8 + x4 + x3 + x + 1). In this
Finite Field representation, the bit value of bit position k of a byte represents the coefficient of a polynomial of
order k, e.g., 1010_1101B (ADH) is represented by the polynomial (x7 + x5 + x3 + x2 + 1). The byte value
result of multiplication of two elements is obtained by a carry-less multiplication of the two corresponding
polynomials, followed by reduction modulo the polynomial, where the remainder is calculated using
operations defined in the field. For example, FF_MUL(57H, 83H) = C1H, because the carry-less polynomial
multiplication of the polynomials represented by 57H and 83H produces (x13 + x11 + x9 + x8 + x6 + x5 + x4
+ x3 + 1), and the remainder modulo m(x) is (x7 + x6 + 1).
•
RotWord(): performs a byte-wise cyclic permutation (rotate right in little-endian byte order) on a 32-bit AES
word.
Vol. 1 12-21
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
The output word X’[j] of RotWord(X[j]) where X[j] represent the four bytes of column j, S(i, j), in descending
order X[j] = ( S(3, j), S(2, j), S(1, j), S(0, j) ); X’[j] = ( S’(3, j), S’(2, j), S’(1, j), S’(0, j) ) ( S(0, j), S(3,
j), S(2, j), S(1, j) )
•
ShiftRows(): A byte-oriented matrix transformation that processes the matrix representation of a 16-byte AES
state by cyclically shifting the last three rows of the state by different offset to the left, see Table 12-12.
Table 12-12. The ShiftRows Transformation
Matrix Representation of Input State
A
•
E
Output of ShiftRows
I
M
A
E
I
M
B
F
J
N
F
J
N
B
C
G
K
O
K
O
C
G
D
H
L
P
P
D
H
L
SubBytes(): A byte-oriented transformation that processes the 128-bit AES state by applying a non-linear
substitution table (S-BOX) on each byte of the state.
The SubBytes() function defines the relationship between each byte of the result state S’(i, j) as a function of
input state byte S(i, j), by
S’(i, j) S-Box (S(i, j)[7:4], S(i, j)[3:0])
where S-BOX (S[7:4], S[3:0]) represents a look-up operation on a 16x16 table to return a byte value, see
Table 12-13.
Table 12-13. Look-up Table Associated with S-Box Transformation
S[3:0]
S[7:4]
•
0
1
2
3
4
5
0
63
7c
77
7b
f2
6b
1
ca
82
c9
7d
fa
2
b7
fd
93
26
3
04
c7
23
4
09
83
5
53
6
6
7
8
9
a
b
6f
c5
30
01
67
2b
59
47
f0
ad
d4
a2
36
3f
f7
cc
34
a5
c3
18
96
05
9a
07
2c
1a
1b
6e
5a
a0
d1
00
ed
20
fc
b1
d0
ef
aa
fb
43
4d
7
51
a3
40
8f
92
8
cd
0c
13
ec
9
60
81
4f
a
e0
32
b
e7
c
c
d
e
f
fe
d7
ab
76
af
9c
a4
72
c0
e5
f1
71
d8
31
15
12
80
e2
eb
27
b2
75
52
3b
d6
b3
29
e3
2f
84
5b
6a
cb
be
39
4a
4c
58
cf
33
85
45
f9
02
7f
50
3c
9f
a8
9d
38
f5
bc
b6
da
21
10
ff
f3
d2
5f
97
44
17
c4
a7
7e
3d
64
5d
19
73
dc
22
2a
90
88
46
ee
b8
14
de
5e
0b
db
3a
0a
49
06
24
5c
c2
d3
ac
62
91
95
e4
79
c8
37
6d
8d
d5
4e
a9
6c
56
f4
ea
65
7a
ae
08
ba
78
25
2e
1c
a6
b4
c6
e8
dd
74
1f
4b
bd
8b
8a
d
70
3e
b5
66
48
03
f6
0e
61
35
57
b9
86
c1
1d
9e
e
e1
f8
98
11
69
d9
8e
94
9b
1e
87
e9
ce
55
28
df
f
8c
a1
89
0d
bf
e6
42
68
41
99
2d
0f
b0
54
bb
16
SubWord(): produces an output AES word (four bytes) from the four bytes of an input word using a non-linear
substitution table (S-BOX).
12-22 Vol. 1
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
X’[j] = ( S’(3, j), S’(2, j), S’(1, j), S’(0, j) ) ( S-Box (S(3, j)), S-Box( S(2, j) ), S-Box( S(1, j) ), S-Box( S(0,
j) ))
•
InvMixColumns(): The inverse transformation of MixColumns().
The InvMixColumns() transformation defines the relationship between each byte of the result state S’(i, j) as
a function of input state bytes, S(i, j), by
S’(0, j) FF_MUL( 0eH, S(0, j) ) XOR FF_MUL(0bH, S(1, j) ) XOR FF_MUL(0dH, S(2, j) ) XOR FF_MUL( 09H,
S(3, j) )
S’(1, j) FF_MUL(09H, S(0, j) ) XOR FF_MUL( 0eH, S(1, j) ) XOR FF_MUL(0bH, S(2, j) ) XOR FF_MUL( 0dH,
S(3, j) )
S’(2, j) FF_MUL(0dH, S(0, j) ) XOR FF_MUL( 09H, S(1, j) ) XOR FF_MUL( 0eH, S(2, j) ) XOR FF_MUL(0bH,
S(3, j) )
S’(3, j) FF_MUL(0bH, S(0, j) ) XOR FF_MUL(0dH, S(1, j) ) XOR FF_MUL( 09H, S(2, j) ) XOR FF_MUL( 0eH,
S(3, j) ), where j = 0, 1, 2, 3.
•
InvShiftRows(): The inverse transformation of InvShiftRows(). The InvShiftRows() transforms the matrix
representation of a 16-byte AES state by cyclically shifting the last three rows of the state by different offset to
the right, see Table 12-14.
Vol. 1 12-23
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
Table 12-14. The InvShiftRows Transformation
Matrix Representation of Input State
A
•
E
Output of ShiftRows
I
M
A
E
I
M
B
F
J
N
N
B
F
J
C
G
K
O
K
O
C
G
D
H
L
P
H
L
P
D
InvSubBytes(): The inverse transformation of SubBytes().
The InvSubBytes() transformation defines the relationship between each byte of the result state S’(i, j) as a
function of input state byte S(i, j), by
S’(i, j) InvS-Box (S(i, j)[7:4], S(i, j)[3:0])
where InvS-BOX (S[7:4], S[3:0]) represents a look-up operation on a 16x16 table to return a byte value, see
Table 12-15.
Table 12-15. Look-up Table Associated with InvS-Box Transformation
S[3:0]
S[7:4]
0
1
2
3
4
5
6
7
0
52
09
6a
d5
30
36
a5
38
1
7c
e3
39
82
9b
2f
ff
2
54
7b
94
32
a6
c2
3
08
2e
a1
66
28
4
72
f8
f6
64
5
6c
70
48
6
90
d8
7
d0
8
8
9
a
b
c
bf
40
a3
9e
81
87
34
8e
43
44
23
3d
ee
4c
95
d9
24
b2
76
5b
86
68
98
16
d4
50
fd
ed
b9
da
ab
00
8c
bc
d3
2c
1e
8f
ca
3f
3a
91
11
41
4f
9
96
ac
74
22
a
47
f1
1a
b
fc
56
c
1f
d
d
e
f
f3
d7
fb
c4
de
e9
cb
0b
42
fa
c3
4e
a2
49
6d
8b
d1
25
a4
5c
cc
5d
65
b6
92
5e
15
46
57
a7
8d
9d
84
0a
f7
e4
58
05
b8
b3
45
06
0f
02
c1
af
bd
03
01
13
8a
6b
67
dc
ea
97
f2
cf
ce
f0
b4
e6
73
e7
ad
35
85
e2
f9
37
e8
1c
75
df
6e
71
1d
29
c5
89
6f
b7
62
0e
aa
18
be
1b
3e
4b
c6
d2
79
20
9a
db
c0
fe
78
cd
5a
f4
dd
a8
33
88
07
c7
31
b1
12
10
59
27
80
ec
5f
60
51
7f
a9
19
b5
4a
0d
2d
e5
7a
9f
93
c9
9c
ef
e
a0
e0
3b
4d
ae
2a
f5
b0
c8
eb
bb
3c
83
53
99
61
f
17
2b
04
7e
ba
77
d6
26
e1
69
14
63
55
21
0c
7d
12.13.3 PCLMULQDQ
The PCLMULQDQ instruction performs carry-less multiplication of two 64-bit data into a 128-bit result. Carry-less
multiplication of two 128-bit data into a 256-bit result can use PCLMULQDQ as building blocks.
Carry-less multiplication is a component of many cryptographic systems. It is an important piece of implementing
Galois Counter Mode (GCM) operation of block ciphers. GCM operation can be used in conjunction with AES algorithms to add authentication capability. GCM usage models also include IPsec, storage standard, and security
protocols over fiber channel. Additionally, PCLMULQDQ can be used in calculations of hash functions and CRC using
arbitrary polynomials.
12-24 Vol. 1
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
12.13.4 Checking for AESNI Support
Before an application attempts to use AESNI instructions or PCLMULQDQ, the application should follow the steps
illustrated in Section 11.6.2, “Checking for SSE/SSE2 Support.” Next, use the additional step provided below:
Check that the processor supports AESNI (if CPUID.01H:ECX.AESNI[bit 25] = 1); check that the processor
supports PCLMULQDQ (if CPUID.01H:ECX.PCLMULQDQ[bit 1] = 1).
Vol. 1 12-25
PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4 AND INTEL® AESNI
12-26 Vol. 1
CHAPTER 13
MANAGING STATE USING THE XSAVE FEATURE SET
The XSAVE feature set extends the functionality of the FXSAVE and FXRSTOR instructions (see Section 10.5,
“FXSAVE and FXRSTOR Instructions”) by supporting the saving and restoring of processor state in addition to the
x87 execution environment (x87 state) and the registers used by the streaming SIMD extensions (SSE state).
The XSAVE feature set comprises eight instructions. XGETBV and XSETBV allow software to read and write the
extended control register XCR0, which controls the operation of the XSAVE feature set. XSAVE, XSAVEOPT,
XSAVEC, and XSAVES are four instructions that save processor state to memory; XRSTOR and XRSTORS are corresponding instructions that load processor state from memory. XGETBV, XSAVE, XSAVEOPT, XSAVEC, and XRSTOR
can be executed at any privilege level; XSETBV, XSAVES, and XRSTORS can be executed only if CPL = 0. In addition
to XCR0, the XSAVES and XRSTORS instructions are controlled also by the IA32_XSS MSR (index DA0H).
The XSAVE feature set organizes the state that manages into state components. Operation of the instructions is
based on state-component bitmaps that have the same format as XCR0 and as the IA32_XSS MSR: each bit
corresponds to a state component. Section 13.1 discusses these state components and bitmaps in more detail.
Section 13.2 describes how the processor enumerates support for the XSAVE feature set and for XSAVE-enabled
features (those features that require use of the XSAVE feature set for their enabling). Section 13.3 explains how
software can enable the XSAVE feature set and XSAVE-enabled features.
The XSAVE feature set allows saving and loading processor state from a region of memory called an XSAVE area.
Section 13.4 presents details of the XSAVE area and its organization. Each XSAVE-managed state component is
associated with a section of the XSAVE area. Section 13.5 describes in detail each of the XSAVE-managed state
components.
Section 13.7 through Section 13.12 describe the operation of XSAVE, XRSTOR, XSAVEOPT, XSAVEC, XSAVES, and
XRSTORS, respectively.
13.1
XSAVE-SUPPORTED FEATURES AND STATE-COMPONENT BITMAPS
The XSAVE feature set supports the saving and restoring of state components, each of which is a discrete set of
processor registers (or parts of registers). In general, each such state component corresponds to a particular CPU
feature. Such a feature is XSAVE-supported. Some XSAVE-supported features use registers in multiple XSAVEmanaged state components.
The XSAVE feature set organizes the state components of the XSAVE-supported features using state-component
bitmaps. A state-component bitmap comprises 64 bits; each bit in such a bitmap corresponds to a single state
component. The following bits are defined in state-component bitmaps:
•
Bit 0 corresponds to the state component used for the x87 FPU execution environment (x87 state). See
Section 13.5.1.
•
Bit 1 corresponds to the state component used for registers used by the streaming SIMD extensions (SSE
state). See Section 13.5.2.
•
Bit 2 corresponds to the state component used for the additional register state used by the Intel® Advanced
Vector Extensions (AVX state). See Section 13.5.3.
•
Bits 4:3 correspond to the two state components used for the additional register state used by Intel® Memory
Protection Extensions (MPX state):
— State component 3 is used for the 4 128-bit bounds registers BND0–BND3 (BNDREGS state).
— State component 4 is used for the 64-bit user-mode MPX configuration register BNDCFGU and the 64-bit
MPX status register BNDSTATUS (BNDCSR state).
•
Bits 7:5 correspond to the three state components used for the additional register state used by Intel®
Advanced Vector Extensions 512 (AVX-512 state):
— State component 5 is used for the 8 64-bit opmask registers k0–k7 (opmask state).
Vol. 1 13-1
MANAGING STATE USING THE XSAVE FEATURE SET
— State component 6 is used for the upper 256 bits of the registers ZMM0–ZMM15. These 16 256-bit values
are denoted ZMM0_H–ZMM15_H (ZMM_Hi256 state).
— State component 7 is used for the 16 512-bit registers ZMM16–ZMM31 (Hi16_ZMM state).
•
•
Bit 8 corresponds to the state component used for the Intel Processor Trace MSRs (PT state).
Bit 9 corresponds to the state component used for the protection-key feature’s register PKRU (PKRU state).
See Section 13.5.7.
Bits in the range 62:10 are not currently defined in state-component bitmaps and are reserved for future expansion. As individual state component is defined within bits 62:10, additional sub-sections are updated within Section
13.5 over time. Bit 63 is used for special functionality in some bitmaps and does not correspond to any state
component.
The state component corresponding to bit i of state-component bitmaps is called state component i. Thus, x87
state is state component 0; SSE state is state component 1; AVX state is state component 2; MPX state comprises
state components 3–4; AVX-512 state comprises state components 5–7; PT state is state component 8; and PKRU
state is state component 9.
The XSAVE feature set uses state-component bitmaps in multiple ways. Most of the instructions use an implicit
operand (in EDX:EAX), called the instruction mask, which is the state-component bitmap that specifies the state
components on which the instruction operates.
Some state components are user state components, and they can be managed by the entire XSAVE feature set.
Other state components are supervisor state components, and they can be managed only by XSAVES and
XRSTORS. All the state components corresponding to bits in the range 9:0 are user state components, except PT
state (corresponding to bit 8), which is a supervisor state component.
Extended control register XCR0 contains a state-component bitmap that specifies the user state components that
software has enabled the XSAVE feature set to manage. If the bit corresponding to a state component is clear in
XCR0, instructions in the XSAVE feature set will not operate on that state component, regardless of the value of the
instruction mask.
The IA32_XSS MSR (index DA0H) contains a state-component bitmap that specifies the supervisor state components that software has enabled XSAVES and XRSTORS to manage (XSAVE, XSAVEC, XSAVEOPT, and XRSTOR
cannot manage supervisor state components). If the bit corresponding to a state component is clear in the
IA32_XSS MSR, XSAVES and XRSTORS will not operate on that state component, regardless of the value of the
instruction mask.
Some XSAVE-supported features can be used only if XCR0 has been configured so that the features’ state components can be managed by the XSAVE feature set. (This applies only to features with user state components.) Such
state components and features are XSAVE-enabled. In general, the processor will not modify (or allow modification of) the registers of a state component of an XSAVE-enabled feature if the bit corresponding to that state
component is clear in XCR0. (If software clears such a bit in XCR0, the processor preserves the corresponding state
component.) If an XSAVE-enabled feature has not been fully enabled in XCR0, execution of any instruction defined
for that feature causes an invalid-opcode exception (#UD).
As will be explained in Section 13.3, the XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] = 1. If
CR4.OSXSAVE = 0, the processor treats XSAVE-enabled state features and their state components as if all bits in
XCR0 were clear; the state components cannot be modified and the features’ instructions cannot be executed.
The state components for x87 state, for SSE state, for PT state, and for PKRU state are XSAVE-managed but the
corresponding features are not XSAVE-enabled. Processors allow modification of this state, as well as execution of
x87 FPU instructions and SSE instructions and use of Intel Processor Trace and protection keys, regardless of the
value of CR4.OSXSAVE and XCR0.
13.2
ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVESUPPORTED FEATURES
A processor enumerates support for the XSAVE feature set and for features supported by that feature set using the
CPUID instruction. The following items provide specific details:
•
CPUID.1:ECX.XSAVE[bit 26] enumerates general support for the XSAVE feature set:
13-2 Vol. 1
MANAGING STATE USING THE XSAVE FEATURE SET
— If this bit is 0, the processor does not support any of the following instructions: XGETBV, XRSTOR,
XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and XSETBV; the processor provides no further
enumeration through CPUID function 0DH (see below).
— If this bit is 1, the processor supports the following instructions: XGETBV, XRSTOR, XSAVE, and XSETBV.1
Further enumeration is provided through CPUID function 0DH.
CR4.OSXSAVE can be set to 1 if and only if CPUID.1:ECX.XSAVE[bit 26] is enumerated as 1.
•
CPUID function 0DH enumerates details of CPU support through a set of sub-functions. Software selects a
specific sub-function by the value placed in the ECX register. The following items provide specific details:
— CPUID function 0DH, sub-function 0.
•
EDX:EAX is a bitmap of all the user state components that can be managed using the XSAVE feature
set. A bit can be set in XCR0 if and only if the corresponding bit is set in this bitmap. Every processor
that supports the XSAVE feature set will set EAX[0] (x87 state) and EAX[1] (SSE state).
If EAX[i] = 1 (for 1 < i < 32) or EDX[i–32] = 1 (for 32 ≤ i < 63), sub-function i enumerates details for
state component i (see below).
•
ECX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all
the user state components supported by this processor.
•
EBX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all
the user state components corresponding to bits currently set in XCR0.
— CPUID function 0DH, sub-function 1.
•
EAX[0] enumerates support for the XSAVEOPT instruction. The instruction is supported if and only if
this bit is 1. If EAX[0] = 0, execution of XSAVEOPT causes an invalid-opcode exception (#UD).
•
EAX[1] enumerates support for compaction extensions to the XSAVE feature set. The following are
supported if this bit is 1:
—
—
—
The compacted format of the extended region of XSAVE areas (see Section 13.4.3).
The XSAVEC instruction. If EAX[1] = 0, execution of XSAVEC causes a #UD.
Execution of the compacted form of XRSTOR (see Section 13.8).
•
EAX[2] enumerates support for execution of XGETBV with ECX = 1. This allows software to determine
the state of the init optimization. See Section 13.6.
•
EAX[3] enumerates support for XSAVES, XRSTORS, and the IA32_XSS MSR. If EAX[3] = 0, execution
of XSAVES or XRSTORS causes a #UD; an attempt to access the IA32_XSS MSR using RDMSR or
WRMSR causes a general-protection exception (#GP). Every processor that supports a supervisor state
component sets EAX[3]. Every processor that sets EAX[3] (XSAVES, XRSTORS, IA32_XSS) will also set
EAX[1] (the compaction extensions).
•
•
EAX[31:4] are reserved.
•
EBX enumerates the size (in bytes) required by the XSAVES instruction for an XSAVE area containing all
the state components corresponding to bits currently set in XCR0 | IA32_XSS.
EDX:ECX is a bitmap of all the supervisor state components that can be managed by XSAVES and
XRSTORS. A bit can be set in the IA32_XSS MSR if and only if the corresponding bit is set in this bitmap.
NOTE
In summary, the XSAVE feature set supports state component i (0 ≤ i < 63) if one of the following
is true: (1) i < 32 and CPUID.(EAX=0DH,ECX=0):EAX[i] = 1; (2) i ≥ 32 and
CPUID.(EAX=0DH,ECX=0):EAX[i–32] = 1; (3) i < 32 and CPUID.(EAX=0DH,ECX=1):ECX[i] = 1;
or (4) i ≥ 32 and CPUID.(EAX=0DH,ECX=1):EDX[i–32] = 1. The XSAVE feature set supports user
state component i if (1) or (2) holds; if (3) or (4) holds, state component i is a supervisor state
component and support is limited to XSAVES and XRSTORS.
1. If CPUID.1:ECX.XSAVE[bit 26] = 1, XGETBV and XSETBV may be executed with ECX = 0 (to read and write XCR0). Any support for
execution of these instructions with other values of ECX is enumerated separately.
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MANAGING STATE USING THE XSAVE FEATURE SET
— CPUID function 0DH, sub-function i (i > 1). This sub-function enumerates details for state component i. If
the XSAVE feature set supports state component i (see note above), the following items provide specific
details:
•
•
EAX enumerates the size (in bytes) required for state component i.
If state component i is a user state component, EBX enumerates the offset (in bytes, from the base of
the XSAVE area) of the section used for state component i. (This offset applies only when the standard
format for the extended region of the XSAVE area is being used; see Section 13.4.3.)
•
•
If state component i is a supervisor state component, EBX returns 0.
•
The value returned by ECX[1] indicates the alignment of state component i when the compacted format
of the extended region of an XSAVE area is used (see Section 13.4.3). If ECX[1] returns 0, state
component i is located immediately following the preceding state component; if ECX[1] returns 1, state
component i is located on the next 64-byte boundary following the preceding state component.
•
ECX[31:2] and EDX return 0.
If state component i is a user state component, ECX[0] return 0; if state component i is a supervisor
state component, ECX[0] returns 1.
If the XSAVE feature set does not support state component i, sub-function i returns 0 in EAX, EBX, ECX, and
EDX.
13.3
ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED FEATURES
Software enables the XSAVE feature set by setting CR4.OSXSAVE[bit 18] to 1 (e.g., with the MOV to CR4 instruction). If this bit is 0, execution of any of XGETBV, XRSTOR, XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and
XSETBV causes an invalid-opcode exception (#UD).
When CR4.OSXSAVE = 1 and CPL = 0, executing the XSETBV instruction with ECX = 0 writes the 64-bit value in
EDX:EAX to XCR0 (EAX is written to XCR0[31:0] and EDX to XCR0[63:32]). (Execution of the XSETBV instruction
causes a general-protection fault — #GP — if CPL > 0.) The following items provide details regarding individual bits
in XCR0:
•
XCR0[0] is associated with x87 state (see Section 13.5.1). XCR0[0] is always 1. It has that value coming out of
RESET. Executing the XSETBV instruction causes a general-protection fault (#GP) if ECX = 0 and EAX[0] is 0.
•
XCR0[1] is associated with SSE state (see Section 13.5.2). Software can use the XSAVE feature set to manage
SSE state only if XCR0[1] = 1. The value of XCR0[1] in no way determines whether software can execute SSE
instructions (these instructions can be executed even if XCR0[1] = 0).
XCR0[1] is 0 coming out of RESET. As noted in Section 13.2, every processor that supports the XSAVE feature
set allows software to set XCR0[1].
•
XCR0[2] is associated with AVX state (see Section 13.5.3). Software can use the XSAVE feature set to manage
AVX state only if XCR0[2] = 1. In addition, software can execute AVX instructions only if CR4.OSXSAVE =
XCR0[2] = 1. Otherwise, any execution of an AVX instruction causes an invalid-opcode exception (#UD).
XCR0[2] is 0 coming out of RESET. As noted in Section 13.2, a processor allows software to set XCR0[2] if and
only if CPUID.(EAX=0DH,ECX=0):EAX[2] = 1. In addition, executing the XSETBV instruction causes a generalprotection fault (#GP) if ECX = 0 and EAX[2:1] has the value 10b; that is, software cannot enable the XSAVE
feature set for AVX state but not for SSE state.
As noted in Section 13.1, the processor will preserve AVX state unmodified if software clears XCR0[2].
However, clearing XCR0[2] while AVX state is not in its initial configuration may cause SSE instructions to incur
a power and performance penalty. See Section 13.5.3, “Enable the Use Of XSAVE Feature Set And XSAVE State
Components” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for how system
software can avoid this penalty.
•
XCR0[4:3] are associated with MPX state (see Section 13.5.4). Software can use the XSAVE feature set to
manage MPX state only if XCR0[4:3] = 11b. In addition, software can execute MPX instructions only if
CR4.OSXSAVE = 1 and XCR0[4:3] = 11b. Otherwise, any execution of an MPX instruction causes an invalidopcode exception (#UD).1
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MANAGING STATE USING THE XSAVE FEATURE SET
XCR0[4:3] have value 00b coming out of RESET. As noted in Section 13.2, a processor allows software to set
XCR0[4:3] to 11b if and only if CPUID.(EAX=0DH,ECX=0):EAX[4:3] = 11b. In addition, executing the XSETBV
instruction causes a general-protection fault (#GP) if ECX = 0, EAX[4:3] is neither 00b nor 11b; that is,
software can enable the XSAVE feature set for MPX state only if it does so for both state components.
As noted in Section 13.1, the processor will preserve MPX state unmodified if software clears XCR0[4:3].
•
XCR0[7:5] are associated with AVX-512 state (see Section 13.5.5). Software can use the XSAVE feature set to
manage AVX-512 state only if XCR0[7:5] = 111b. In addition, software can execute AVX-512 instructions only
if CR4.OSXSAVE = 1 and XCR0[7:5] = 111b. Otherwise, any execution of an AVX-512 instruction causes an
invalid-opcode exception (#UD).
XCR0[7:5] have value 000b coming out of RESET. As noted in Section 13.2, a processor allows software to set
XCR0[7:5] to 111b if and only if CPUID.(EAX=0DH,ECX=0):EAX[7:5] = 111b. In addition, executing the
XSETBV instruction causes a general-protection fault (#GP) if ECX = 0, EAX[7:5] is not 000b, and any bit is
clear in EAX[2:1] or EAX[7:5]; that is, software can enable the XSAVE feature set for AVX-512 state only if it
does so for all three state components, and only if it also does so for AVX state and SSE state. This implies that
the value of XCR0[7:5] is always either 000b or 111b.
As noted in Section 13.1, the processor will preserve AVX-512 state unmodified if software clears XCR0[7:5].
However, clearing XCR0[7:5] while AVX-512 state is not in its initial configuration may cause SSE and AVX
instructions to incur a power and performance penalty. See Section 13.5.3, “Enable the Use Of XSAVE Feature
Set And XSAVE State Components” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
3A, for how system software can avoid this penalty.
•
XCR0[9] is associated with PKRU state (see Section 13.5.7). Software can use the XSAVE feature set to
manage PKRU state only if XCR0[9] = 1. The value of XCR0[9] in no way determines whether software can use
protection keys or execute other instructions that access PKRU state (these instructions can be executed even
if XCR0[9] = 0).
XCR0[9] is 0 coming out of RESET. As noted in Section 13.2, a processor allows software to set XCR0[9] if and
only if CPUID.(EAX=0DH,ECX=0):EAX[9] = 1.
•
XCR0[63:10] and XCR0[8] are reserved.1 Executing the XSETBV instruction causes a general-protection fault
(#GP) if ECX = 0 and any corresponding bit in EDX:EAX is not 0. These bits in XCR0 are all 0 coming out of
RESET.
Software operating with CPL > 0 may need to determine whether the XSAVE feature set and certain XSAVEenabled features have been enabled. If CPL > 0, execution of the MOV from CR4 instruction causes a generalprotection fault (#GP). The following alternative mechanisms allow software to discover the enabling of the XSAVE
feature set regardless of CPL:
•
The value of CR4.OSXSAVE is returned in CPUID.1:ECX.OSXSAVE[bit 27]. If software determines that
CPUID.1:ECX.OSXSAVE = 1, the processor supports the XSAVE feature set and the feature set has been
enabled in CR4.
•
Executing the XGETBV instruction with ECX = 0 returns the value of XCR0 in EDX:EAX. XGETBV can be
executed if CR4.OSXSAVE = 1 (if CPUID.1:ECX.OSXSAVE = 1), regardless of CPL.
Thus, software can use the following algorithm to determine the support and enabling for the XSAVE feature set:
1. Use CPUID to discover the value of CPUID.1:ECX.OSXSAVE.
— If the bit is 0, either the XSAVE feature set is not supported by the processor or has not been enabled by
software. Either way, the XSAVE feature set is not available, nor are XSAVE-enabled features such as AVX.
— If the bit is 1, the processor supports the XSAVE feature set — including the XGETBV instruction — and it
has been enabled by software. The XSAVE feature set can be used to manage x87 state (because XCR0[0]
is always 1). Software requiring more detailed information can go on to the next step.
2. Execute XGETBV with ECX = 0 to discover the value of XCR0. If XCR0[1] = 1, the XSAVE feature set can be
used to manage SSE state. If XCR0[2] = 1, the XSAVE feature set can be used to manage AVX state and
software can execute AVX instructions. If XCR0[4:3] is 11b, the XSAVE feature set can be used to manage MPX
1. If XCR0[3] = 0, executions of CALL, RET, JMP, and Jcc do not initialize the bounds registers.
1. Bit 8 corresponds to a supervisor state component. Since bits can be set in XCR0 only for user state components, that bit of XCR0
must be 0.
Vol. 1 13-5
MANAGING STATE USING THE XSAVE FEATURE SET
state and software can execute MPX instructions. If XCR0[7:5] is 111b, the XSAVE feature set can be used to
manage AVX-512 state and software can execute AVX-512 instructions. If XCR0[9] = 1, the XSAVE feature set
can be used to manage PKRU state.
The IA32_XSS MSR (with MSR index DA0H) is zero coming out of RESET. If CR4.OSXSAVE = 1,
CPUID.(EAX=0DH,ECX=1):EAX[3] = 1, and CPL = 0, executing the WRMSR instruction with ECX = DA0H writes
the 64-bit value in EDX:EAX to the IA32_XSS MSR (EAX is written to IA32_XSS[31:0] and EDX to
IA32_XSS[63:32]). The following items provide details regarding individual bits in the IA32_XSS MSR:
•
IA32_XSS[8] is associated with PT state (see Section 13.5.6). Software can use XSAVES and XRSTORS to
manage PT state only if IA32_XSS[8] = 1. The value of IA32_XSS[8] does not determine whether software can
use Intel Processor Trace (the feature can be used even if IA32_XSS[8] = 0).
•
IA32_XSS[63:9] and IA32_XSS[7:0] are reserved.1 Executing the WRMSR instruction causes a generalprotection fault (#GP) if ECX = DA0H and any corresponding bit in EDX:EAX is not 0. These bits in XCR0 are all
0 coming out of RESET.
The IA32_XSS MSR is 0 coming out of RESET.
There is no mechanism by which software operating with CPL > 0 can discover the value of the IA32_XSS MSR.
13.4
XSAVE AREA
The XSAVE feature set includes instructions that save and restore the XSAVE-managed state components to and
from memory: XSAVE, XSAVEOPT, XSAVEC, and XSAVES (for saving); and XRSTOR and XRSTORS (for restoring).
The processor organizes the state components in a region of memory called an XSAVE area. Each of the save and
restore instructions takes a memory operand that specifies the 64-byte aligned base address of the XSAVE area on
which it operates.
Every XSAVE area has the following format:
•
The legacy region. The legacy region of an XSAVE area comprises the 512 bytes starting at the area’s base
address. It is used to manage the state components for x87 state and SSE state. The legacy region is described
in more detail in Section 13.4.1.
•
The XSAVE header. The XSAVE header of an XSAVE area comprises the 64 bytes starting at an offset of 512
bytes from the area’s base address. The XSAVE header is described in more detail in Section 13.4.2.
•
The extended region. The extended region of an XSAVE area starts at an offset of 576 bytes from the area’s
base address. It is used to manage the state components other than those for x87 state and SSE state. The
extended region is described in more detail in Section 13.4.3. The size of the extended region is determined by
which state components the processor supports and which bits have been set in XCR0 and IA32_XSS (see
Section 13.3).
13.4.1
Legacy Region of an XSAVE Area
The legacy region of an XSAVE area comprises the 512 bytes starting at the area’s base address. It has the same
format as the FXSAVE area (see Section 10.5.1). The XSAVE feature set uses the legacy area for x87 state (state
component 0) and SSE state (state component 1). Table 13-1 illustrates the format of the first 416 bytes of the
legacy region of an XSAVE area.
Table 13-1. Format of the Legacy Region of an XSAVE Area
15
14
FIP[63:48] or
reserved
13
12
FCS or
FIP[47:32]
MXCSR_MASK
11
10
9
8
7
6
FIP[31:0]
FOP
MXCSR
FDP[63:48]
or reserved
5
4
Rsvd.
FTW
FDS or
FDP[47:32]
3
2
FSW
1
0
FCW
FDP[31:0]
0
16
1. Bit 9 and bits 7:0 correspond to user state components. Since bits can be set in the IA32_XSS MSR only for supervisor state components, those bits of the MSR must be 0.
13-6 Vol. 1
MANAGING STATE USING THE XSAVE FEATURE SET
Table 13-1. Format of the Legacy Region of an XSAVE Area (Contd.) (Contd.)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ST0/MM0
32
Reserved
ST1/MM1
48
Reserved
ST2/MM2
64
Reserved
ST3/MM3
80
Reserved
ST4/MM4
96
Reserved
ST5/MM5
112
Reserved
ST6/MM6
128
Reserved
ST7/MM7
144
XMM0
160
XMM1
176
XMM2
192
XMM3
208
XMM4
224
XMM5
240
XMM6
256
XMM7
272
XMM8
288
XMM9
304
XMM10
320
XMM11
336
XMM12
352
XMM13
368
XMM14
384
XMM15
400
The x87 state component comprises bytes 23:0 and bytes 159:32. The SSE state component comprises
bytes 31:24 and bytes 415:160. The XSAVE feature set does not use bytes 511:416; bytes 463:416 are reserved.
Section 13.7 through Section 13.9 provide details of how instructions in the XSAVE feature set use the legacy
region of an XSAVE area.
13.4.2
XSAVE Header
The XSAVE header of an XSAVE area comprises the 64 bytes starting at offset 512 from the area’s base address:
•
Bytes 7:0 of the XSAVE header is a state-component bitmap (see Section 13.1) called XSTATE_BV. It
identifies the state components in the XSAVE area.
•
Bytes 15:8 of the XSAVE header is a state-component bitmap called XCOMP_BV. It is used as follows:
— XCOMP_BV[63] indicates the format of the extended region of the XSAVE area (see Section 13.4.3). If it is
clear, the standard format is used. If it is set, the compacted format is used; XCOMP_BV[62:0] provide
format specifics as specified in Section 13.4.3.
— XCOMP_BV[63] determines which form of the XRSTOR instruction is used. If the bit is set, the compacted
form is used; otherwise, the standard form is used. See Section 13.8.
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MANAGING STATE USING THE XSAVE FEATURE SET
— All bits in XCOMP_BV should be 0 if the processor does not support the compaction extensions to the XSAVE
feature set.
•
Bytes 63:16 of the XSAVE header are reserved.
Section 13.7 through Section 13.9 provide details of how instructions in the XSAVE feature set use the XSAVE
header of an XSAVE area.
13.4.3
Extended Region of an XSAVE Area
The extended region of an XSAVE area starts at byte offset 576 from the area’s base address. The size of the
extended region is determined by which state components the processor supports and which bits have been set in
XCR0 | IA32_XSS (see Section 13.3).
The XSAVE feature set uses the extended area for each state component i, where i ≥ 2. The following state components are currently supported in the extended area: state component 2 contains AVX state; state components 5–7
contain AVX-512 state; and state component 9 contains PKRU state.
The extended region of the an XSAVE area may have one of two formats. The standard format is supported by all
processors that support the XSAVE feature set; the compacted format is supported by those processors that
support the compaction extensions to the XSAVE feature set (see Section 13.2). Bit 63 of the XCOMP_BV field in
the XSAVE header (see Section 13.4.2) indicates which format is used.
The following items describe the two possible formats of the extended region:
•
Standard format. Each state component i (i ≥ 2) is located at the byte offset from the base address of the
XSAVE area enumerated in CPUID.(EAX=0DH,ECX=i):EBX. (CPUID.(EAX=0DH,ECX=i):EAX enumerates the
number of bytes required for state component i.
•
Compacted format. Each state component i (i ≥ 2) is located at a byte offset from the base address of the
XSAVE area based on the XCOMP_BV field in the XSAVE header:
— If XCOMP_BV[i] = 0, state component i is not in the XSAVE area.
— If XCOMP_BV[i] = 1, state component i is located at a byte offset locationI from the base address of the
XSAVE area, where locationI is determined by the following items:
•
If XCOMP_BV[j] = 0 for every j, 2 ≤ j < i, locationI is 576. (This item applies if i is the first bit set in
bits 62:2 of the XCOMP_BV; it implies that state component i is located at the beginning of the
extended region.)
•
Otherwise, let j, 2 ≤ j < i, be the greatest value such that XCOMP_BV[j] = 1. Then locationI is
determined by the following values: locationJ; sizeJ, as enumerated in CPUID.(EAX=0DH,ECX=j):EAX;
and the value of alignI, as enumerated in CPUID.(EAX=0DH,ECX=i):ECX[1]:
13.5
—
If alignI = 0, locationI = locationJ + sizeJ. (This item implies that state component i is located
immediately following the preceding state component whose bit is set in XCOMP_BV.)
—
If alignI = 1, locationI = ceiling(locationJ + sizeJ, 64). (This item implies that state component i is
located on the next 64-byte boundary following the preceding state component whose bit is set in
XCOMP_BV.)
XSAVE-MANAGED STATE
The section provides details regarding how the XSAVE feature set interacts with the various XSAVE-managed state
components.
Unless otherwise state, the state pertaining to a particular state component is saved beginning at byte 0 of the
section of the XSAVE are corresponding to that state component.
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MANAGING STATE USING THE XSAVE FEATURE SET
13.5.1
x87 State
Instructions in the XSAVE feature set can manage the same state of the x87 FPU execution environment (x87
state) that can be managed using the FXSAVE and FXRSTOR instructions. They organize all x87 state as a user
state component in the legacy region of the XSAVE area (see Section 13.4.1). This region is illustrated in
Table 13-1; the x87 state is listed below, along with details of its interactions with the XSAVE feature set:
•
Bytes 1:0, 3:2, 7:6. These are used for the x87 FPU Control Word (FCW), the x87 FPU Status Word (FSW), and
the x87 FPU Opcode (FOP), respectively.
•
Byte 4 is used for an abridged version of the x87 FPU Tag Word (FTW). The following items describe its usage:
— For each j, 0 ≤ j ≤ 7, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save a 0 into bit j of byte 4 if x87 FPU data
register STj has a empty tag; otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save a 1 into bit j of
byte 4.
— For each j, 0 ≤ j ≤ 7, XRSTOR and XRSTORS establish the tag value for x87 FPU data register STj as follows.
If bit j of byte 4 is 0, the tag for STj in the tag register for that data register is marked empty (11B);
otherwise, the x87 FPU sets the tag for STj based on the value being loaded into that register (see below).
•
Bytes 15:8 are used as follows:
— If the instruction has no REX prefix, or if REX.W = 0:
•
•
•
Bytes 11:8 are used for bits 31:0 of the x87 FPU Instruction Pointer Offset (FIP).
If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0, bytes 13:12 are used for x87 FPU Instruction Pointer
Selector (FCS). Otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save these bytes as 0000H, and
XRSTOR and XRSTORS ignore them.
Bytes 15:14 are not used.
— If the instruction has a REX prefix with REX.W = 1, bytes 15:8 are used for the full 64 bits of FIP.
•
Bytes 23:16 are used as follows:
— If the instruction has no REX prefix, or if REX.W = 0:
•
•
•
Bytes 19:16 are used for bits 31:0 of the x87 FPU Data Pointer Offset (FDP).
If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0, bytes 21:20 are used for x87 FPU Data Pointer Selector
(FDS). Otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save these bytes as 0000H; and XRSTOR
and XRSTORS ignore them.
Bytes 23:22 are not used.
— If the instruction has a REX prefix with REX.W = 1, bytes 23:16 are used for the full 64 bits of FDP.
•
•
Bytes 31:24 are used for SSE state (see Section 13.5.2).
Bytes 159:32 are used for the registers ST0–ST7 (MM0–MM7). Each of the 8 register is allocated a 128-bit
region, with the low 80 bits used for the register and the upper 48 bits unused.
x87 state is XSAVE-managed but the x87 FPU feature is not XSAVE-enabled. The XSAVE feature set can operate on
x87 state only if the feature set is enabled (CR4.OSXSAVE = 1).1 Software can otherwise use x87 state even if the
XSAVE feature set is not enabled.
13.5.2
SSE State
Instructions in the XSAVE feature set can manage the registers used by the streaming SIMD extensions (SSE
state) just as the FXSAVE and FXRSTOR instructions do. They organize all SSE state as a user state component in
the legacy region of the XSAVE area (see Section 13.4.1). This region is illustrated in Table 13-1; the SSE state is
listed below, along with details of its interactions with the XSAVE feature set:
•
•
Bytes 23:0 are used for x87 state (see Section 13.5.1).
Bytes 27:24 are used for the MXCSR register. XRSTOR and XRSTORS generate general-protection faults (#GP)
in response to attempts to set any of the reserved bits of the MXCSR register.2
1. The processor ensures that XCR0[0] is always 1.
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MANAGING STATE USING THE XSAVE FEATURE SET
•
•
•
•
Bytes 31:28 are used for the MXCSR_MASK value. XRSTOR and XRSTORS ignore this field.
Bytes 159:32 are used for x87 state.
Bytes 287:160 are used for the registers XMM0–XMM7.
Bytes 415:288 are used for the registers XMM8–XMM15. These fields are used only in 64-bit mode. Executions
of XSAVE, XSAVEOPT, XSAVEC, and XSAVES outside 64-bit mode do not modify these bytes; executions of
XRSTOR and XRSTORS outside 64-bit mode do not update XMM8–XMM15. See Section 13.13.
SSE state is XSAVE-managed but the SSE feature is not XSAVE-enabled. The XSAVE feature set can operate on SSE
state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage SSE state
(XCR0[1] = 1). Software can otherwise use SSE state even if the XSAVE feature set is not enabled or has not been
configured to manage SSE state.
13.5.3
AVX State
The register state used by the Intel® Advanced Vector Extensions (AVX) comprises the MXCSR register and 16 256bit vector registers called YMM0–YMM15. The low 128 bits of each register YMMi is identical to the SSE register
XMMi. Thus, the new state register state added by AVX comprises the upper 128 bits of the registers YMM0–
YMM15. These 16 128-bit values are denoted YMM0_H–YMM15_H and are collectively called AVX state.
As noted in Section 13.1, the XSAVE feature set manages AVX state as user state component 2. Thus, AVX state is
located in the extended region of the XSAVE area (see Section 13.4.3).
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=2):EBX enumerates the offset (in bytes, from the base of the
XSAVE area) of the section of the extended region of the XSAVE area used for AVX state (when the standard format
of the extended region is used). CPUID.(EAX=0DH,ECX=2):EAX enumerates the size (in bytes) required for AVX
state.
The XSAVE feature set partitions YMM0_H–YMM15_H in a manner similar to that used for the XMM registers (see
Section 13.5.2). Bytes 127:0 of the AVX-state section are used for YMM0_H–YMM7_H. Bytes 255:128 are used for
YMM8_H–YMM15_H, but they are used only in 64-bit mode. Executions of XSAVE, XSAVEOPT, XSAVEC, and
XSAVES outside 64-bit mode do not modify bytes 255:128; executions of XRSTOR and XRSTORS outside 64-bit
mode do not update YMM8_H–YMM15_H. See Section 13.13. In general, bytes 16i+15:16i are used for YMMi_H
(for 0 ≤ i ≤ 15).
AVX state is XSAVE-managed and the AVX feature is XSAVE-enabled. The XSAVE feature set can operate on AVX
state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage AVX state
(XCR0[2] = 1). AVX instructions cannot be used unless the XSAVE feature set is enabled and has been configured
to manage AVX state.
13.5.4
MPX State
The register state used by the Intel® Memory Protection Extensions (MPX) comprises the 4 128-bit bounds registers BND0–BND3 (BNDREG state); and the 64-bit user-mode configuration register BNDCFGU and the 64-bit MPX
status register BNDSTATUS (collectively, BNDCSR state). Together, these two user state components compose
MPX state.
As noted in Section 13.1, the XSAVE feature set manages MPX state as state components 3–4. Thus, MPX state is
located in the extended region of the XSAVE area (see Section 13.4.3). The following items detail how these state
components are organized in this region:
•
BNDREG state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=3):EBX enumerates the offset (in bytes, from the base of the
XSAVE area) of the section of the extended region of the XSAVE area used for BNDREG state (when the
standard format of the extended region is used). CPUID.(EAX=0DH,ECX=5):EAX enumerates the size (in
bytes) required for BNDREG state. The BNDREG section is used for the 4 128-bit bound registers BND0–BND3,
with bytes 16i+15:16i being used for BNDi.
2. While MXCSR and MXCSR_MASK are part of SSE state, their treatment by the XSAVE feature set is not the same as that of the XMM
registers. See Section 13.7 through Section 13.11 for details.
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MANAGING STATE USING THE XSAVE FEATURE SET
•
BNDCSR state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=4):EBX enumerates the offset of the section of the extended
region of the XSAVE area used for BNDCSR state (when the standard format of the extended region is used).
CPUID.(EAX=0DH,ECX=6):EAX enumerates the size (in bytes) required for BNDCSR state. In the BNDSCR
section, bytes 7:0 are used for BNDCFGU and bytes 15:8 are used for BNDSTATUS.
Both components of MPX state are XSAVE-managed and the MPX feature is XSAVE-enabled. The XSAVE feature set
can operate on MPX state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage
MPX state (XCR0[4:3] = 11b). MPX instructions cannot be used unless the XSAVE feature set is enabled and has
been configured to manage MPX state.
13.5.5
AVX-512 State
The register state used by the Intel® Advanced Vector Extensions 512 (AVX-512) comprises the MXCSR register,
the 8 64-bit opmask registers k0–k7, and 32 512-bit vector registers called ZMM0–ZMM31. For each i, 0 <= i <=
15, the low 256 bits of register ZMMi is identical to the AVX register YMMi. Thus, the new state register state added
by AVX comprises the following user state components:
•
•
The opmask registers, collectively called opmask state.
•
The 16 512-bit registers ZMM16–ZMM31, collectively called Hi16_ZMM state.
The upper 256 bits of the registers ZMM0–ZMM15. These 16 256-bit values are denoted ZMM0_H–ZMM15_H
and are collectively called ZMM_Hi256 state.
Together, these three state components compose AVX-512 state.
As noted in Section 13.1, the XSAVE feature set manages AVX-512 state as state components 5–7. Thus, AVX-512
state is located in the extended region of the XSAVE area (see Section 13.4.3). The following items detail how
these state components are organized in this region:
•
Opmask state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=5):EBX enumerates the offset (in bytes, from the base of the
XSAVE area) of the section of the extended region of the XSAVE area used for opmask state (when the standard
format of the extended region is used). CPUID.(EAX=0DH,ECX=5):EAX enumerates the size (in bytes)
required for opmask state. The opmask section is used for the 8 64-bit bound registers k0–k7, with
bytes 8i+7:8i being used for ki.
•
ZMM_Hi256 state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=6):EBX enumerates the offset of the section of the extended
region of the XSAVE area used for ZMM_Hi256 state (when the standard format of the extended region is
used). CPUID.(EAX=0DH,ECX=6):EAX enumerates the size (in bytes) required for ZMM_Hi256 state.
The XSAVE feature set partitions ZMM0_H–ZMM15_H in a manner similar to that used for the XMM registers
(see Section 13.5.2). Bytes 255:0 of the ZMM_Hi256-state section are used for ZMM0_H–ZMM7_H.
Bytes 511:256 are used for ZMM8_H–ZMM15_H, but they are used only in 64-bit mode. Executions of XSAVE,
XSAVEOPT, XSAVEC, and XSAVES outside 64-bit mode do not modify bytes 511:256; executions of XRSTOR
and XRSTORS outside 64-bit mode do not update ZMM8_H–ZMM15_H. See Section 13.13. In general,
bytes 32i+31:32i are used for ZMMi_H (for 0 ≤ i ≤ 15).
•
Hi16_ZMM state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=7):EBX enumerates the offset of the section of the extended
region of the XSAVE area used for Hi16_ZMM state (when the standard format of the extended region is used).
CPUID.(EAX=0DH,ECX=7):EAX enumerates the size (in bytes) required for Hi16_ZMM state.
The XSAVE feature set accesses Hi16_ZMM state only in 64-bit mode. Executions of XSAVE, XSAVEOPT,
XSAVEC, and XSAVES outside 64-bit mode do not modify the Hi16_ZMM section; executions of XRSTOR and
XRSTORS outside 64-bit mode do not update ZMM16–ZMM31. See Section 13.13. In general,
bytes 64(i-16)+63:64(i-16) are used for ZMMi (for 16 ≤ i ≤ 31).
All three components of AVX-512 state are XSAVE-managed and the AVX-512 feature is XSAVE-enabled. The
XSAVE feature set can operate on AVX-512 state only if the feature set is enabled (CR4.OSXSAVE = 1) and has
been configured to manage AVX-512 state (XCR0[7:5] = 111b). AVX-512 instructions cannot be used unless the
XSAVE feature set is enabled and has been configured to manage AVX-512 state.
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MANAGING STATE USING THE XSAVE FEATURE SET
13.5.6
PT State
The register state used by Intel Processor Trace (PT state) comprises the following 9 MSRs: IA32_RTIT_CTL,
IA32_RTIT_OUTPUT_BASE, IA32_RTIT_OUTPUT_MASK_PTRS, IA32_RTIT_STATUS, IA32_RTIT_CR3_MATCH,
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B, IA32_RTIT_ADDR1_A, and IA32_RTIT_ADDR1_B.1
As noted in Section 13.1, the XSAVE feature set manages PT state as supervisor state component 8. Thus, PT state
is located in the extended region of the XSAVE area (see Section 13.4.3). As noted in Section 13.2,
CPUID.(EAX=0DH,ECX=8):EAX enumerates the size (in bytes) required for PT state. The MSRs are each allocated
8 bytes in the state component in the order given above. Thus, IA32_RTIT_CTL is at byte offset 0,
IA32_RTIT_OUTPUT_BASE at byte offset 8, etc. Any locations in the state component at or beyond byte offset 72
are reserved.
PT state is XSAVE-managed but Intel Processor Trace is not XSAVE-enabled. The XSAVE feature set can operate on
PT state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage PT state
(IA32_XSS[8] = 1). Software can otherwise use Intel Processor Trace and access its MSRs (using RDMSR and
WRMSR) even if the XSAVE feature set is not enabled or has not been configured to manage PT state.
The following items describe special treatment of PT state by the XSAVES and XRSTORS instructions:
•
If XSAVES saves PT state, the instruction clears IA32_RTIT_CTL.TraceEn (bit 0) after saving the value of the
IA32_RTIT_CTL MSR and before saving any other PT state. If XSAVES causes a fault or a VM exit, it restores
IA32_RTIT_CTL.TraceEn to its original value.
•
•
If XSAVES saves PT state, the instruction saves zeroes in the reserved portions of the state component.
•
If XRSTORS causes an exception or a VM exit, it does so before any modification to IA32_RTIT_CTL.TraceEn
(even if it has loaded other PT state).
If XRSTORS would restore (or initialize) PT state and IA32_RTIT_CTL.TraceEn = 1, the instruction causes a
general-protection exception (#GP) before modifying PT state.
13.5.7
PKRU State
The register state used by the protection-key feature (PKRU state) is the 32-bit PKRU register. As noted in Section
13.1, the XSAVE feature set manages PKRU state as user state component 9. Thus, PKRU state is located in the
extended region of the XSAVE area (see Section 13.4.3).
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=9):EBX enumerates the offset (in bytes, from the base of the
XSAVE area) of the section of the extended region of the XSAVE area used for PKRU state (when the standard
format of the extended region is used). CPUID.(EAX=0DH,ECX=9):EAX enumerates the size (in bytes) required for
PKRU state. The XSAVE feature set uses bytes 3:0 of the PK-state section for the PKRU register.
PKRU state is XSAVE-managed but the protection-key feature is not XSAVE-enabled. The XSAVE feature set can
operate on PKRU state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage
PKRU state (XCR0[9] = 1). Software can otherwise use protection keys and access PKRU state even if the XSAVE
feature set is not enabled or has not been configured to manage PKRU state.
The value of the PKRU register determines the access rights for user-mode linear addresses. (See Section 4.6,
“Access Rights,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.) The access rights
that pertain to an execution of the XRSTOR and XRSTORS instructions are determined by the value of the register
before the execution and not by any value that the execution might load into the PKRU register.
13.6
PROCESSOR TRACKING OF XSAVE-MANAGED STATE
The XSAVEOPT, XSAVEC, and XSAVES instructions use two optimization to reduce the amount of data that they
write to memory. They avoid writing data for any state component known to be in its initial configuration (the init
optimization). In addition, if either XSAVEOPT or XSAVES is using the same XSAVE area as that used by the most
1. These MSRs might not be supported by every processor that supports Intel Processor Trace. Software can use the CPUID instruction
to discover which are supported; see Section 36.3.1, “Detection of Intel Processor Trace and Capability Enumeration,” of Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3C.
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MANAGING STATE USING THE XSAVE FEATURE SET
recent execution of XRSTOR or XRSTORS, it may avoid writing data for any state component whose configuration
is known not to have been modified since then (the modified optimization). (XSAVE does not use these optimizations, and XSAVEC does not use the modified optimization.) The operation of XSAVEOPT, XSAVEC, and XSAVES
are described in more detail in Section 13.9 through Section 13.11.
A processor can support the init and modified optimizations with special hardware that tracks the state components
that might benefit from those optimizations. Other implementations might not include such hardware; such a
processor would always consider each such state component as not in its initial configuration and as modified since
the last execution of XRSTOR or XRSTORS.
The following notation describes the state of the init and modified optimizations:
•
XINUSE denotes the state-component bitmap corresponding to the init optimization. If XINUSE[i] = 0, state
component i is known to be in its initial configuration; otherwise XINUSE[i] = 1. It is possible for XINUSE[i] to
be 1 even when state component i is in its initial configuration. On a processor that does not support the init
optimization, XINUSE[i] is always 1 for every value of i.
Executing XGETBV with ECX = 1 returns in EDX:EAX the logical-AND of XCR0 and the current value of the
XINUSE state-component bitmap. Such an execution of XGETBV always sets EAX[1] to 1 if XCR0[1] = 1 and
MXCSR does not have its RESET value of 1F80H. Section 13.2 explains how software can determine whether a
processor supports this use of XGETBV.
•
XMODIFIED denotes the state-component bitmap corresponding to the modified optimization. If
XMODIFIED[i] = 0, state component i is known not to have been modified since the most recent execution of
XRSTOR or XRSTORS; otherwise XMODIFIED[i] = 1. It is possible for XMODIFIED[i] to be 1 even when state
component i has not been modified since the most recent execution of XRSTOR or XRSTORS. On a processor
that does not support the modified optimization, XMODIFIED[i] is always 1 for every value of i.
A processor that implements the modified optimization saves information about the most recent execution of
XRSTOR or XRSTORS in a quantity called XRSTOR_INFO, a 4-tuple containing the following: (1) the CPL;
(2) whether the logical processor was in VMX non-root operation; (3) the linear address of the XSAVE area; and
(4) the XCOMP_BV field in the XSAVE area. An execution of XSAVEOPT or XSAVES uses the modified optimization
only if that execution corresponds to XRSTOR_INFO on these four parameters.
This mechanism implies that, depending on details of the operating system, the processor might determine that an
execution of XSAVEOPT by one user application corresponds to an earlier execution of XRSTOR by a different application. For this reason, Intel recommends the application software not use the XSAVEOPT instruction.
The following items specify the initial configuration each state component (for the purposes of defining the XINUSE
bitmap):
•
x87 state. x87 state is in its initial configuration if the following all hold: FCW is 037FH; FSW is 0000H; FTW is
FFFFH; FCS and FDS are each 0000H; FIP and FDP are each 00000000_00000000H; each of ST0–ST7 is
0000_00000000_00000000H.
•
SSE state. In 64-bit mode, SSE state is in its initial configuration if each of XMM0–XMM15 is 0. Outside 64-bit
mode, SSE state is in its initial configuration if each of XMM0–XMM7 is 0. XINUSE[1] pertains only to the state
of the XMM registers and not to MXCSR. An execution of XRSTOR or XRSTORS outside 64-bit mode does not
update XMM8–XMM15. (See Section 13.13.)
•
AVX state. In 64-bit mode, AVX state is in its initial configuration if each of YMM0_H–YMM15_H is 0. Outside
64-bit mode, AVX state is in its initial configuration if each of YMM0_H–YMM7_H is 0. An execution of XRSTOR
or XRSTORS outside 64-bit mode does not update YMM8_H–YMM15_H. (See Section 13.13.)
•
•
•
•
BNDREG state. BNDREG state is in its initial configuration if the value of each of BND0–BND3 is 0.
•
BNDCSR state. BNDCSR state is in its initial configuration if BNDCFGU and BNDCSR each has value 0.
Opmask state. Opmask state is in its initial configuration if each of the opmask registers k0–k7 is 0.
ZMM_Hi256 state. In 64-bit mode, ZMM_Hi256 state is in its initial configuration if each of ZMM0_H–
ZMM15_H is 0. Outside 64-bit mode, ZMM_Hi256 state is in its initial configuration if each of ZMM0_H–ZMM7_H
is 0. An execution of XRSTOR or XRSTORS outside 64-bit mode does not update ZMM8_H–ZMM15_H. (See
Section 13.13.)
Hi16_ZMM state. In 64-bit mode, Hi16_ZMM state is in its initial configuration if each of ZMM16–ZMM31 is 0.
Outside 64-bit mode, Hi16_ZMM state is always in its initial configuration. An execution of XRSTOR or
XRSTORS outside 64-bit mode does not update ZMM31–ZMM31. (See Section 13.13.)
Vol. 1 13-13
MANAGING STATE USING THE XSAVE FEATURE SET
•
•
PT state. PT state is in its initial configuration if each of the 9 MSRs is 0.
PKRU state. PKRU state is in its initial configuration if the value of the PKRU is 0.
13.7
OPERATION OF XSAVE
The XSAVE instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction
mask. The logical-AND of XCR0 and the instruction mask is the requested-feature bitmap (RFBM) of the user
state components to be saved.
The following conditions cause execution of the XSAVE instruction to generate a fault:
•
•
•
If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.
If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.
If the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP) occurs.1
If none of these conditions cause a fault, execution of XSAVE reads the XSTATE_BV field of the XSAVE header (see
Section 13.4.2) and writes it back to memory, setting XSTATE_BV[i] (0 ≤ i ≤ 63) as follows:
•
•
If RFBM[i] = 0, XSTATE_BV[i] is not changed.
If RFBM[i] = 1, XSTATE_BV[i] is set to the value of XINUSE[i]. Section 13.6 defines XINUSE to describe the
processor init optimization and specifies the initial configuration of each state component. The nature of that
optimization implies the following:
— If state component i is in its initial configuration, XINUSE[i] may be either 0 or 1, and XSTATE_BV[i] may be
written with either 0 or 1.
XINUSE[1] pertains only to the state of the XMM registers and not to MXCSR. Thus, XSTATE_BV[1] may be
written with 0 even if MXCSR does not have its RESET value of 1F80H.
— If state component i is not in its initial configuration, XINUSE[i] = 1 and XSTATE_BV[i] is written with 1.
(As explained in Section 13.6, the initial configurations of some state components may depend on whether the
processor is in 64-bit mode.)
The XSAVE instruction does not write any part of the XSAVE header other than the XSTATE_BV field; in particular,
it does not write to the XCOMP_BV field.
Execution of XSAVE saves into the XSAVE area those state components corresponding to bits that are set in RFBM.
State components 0 and 1 are located in the legacy region of the XSAVE area (see Section 13.4.1). Each state
component i, 2 ≤ i ≤ 62, is located in the extended region; the XSAVE instruction always uses the standard format
for the extended region (see Section 13.4.3).
The MXCSR register and MXCSR_MASK are part of SSE state (see Section 13.5.2) and are thus associated with
RFBM[1]. However, the XSAVE instruction also saves these values when RFBM[2] = 1 (even if RFBM[1] = 0).
See Section 13.5 for specifics for each state component and for details regarding mode-specific operation and
operation determined by instruction prefixes. See Section 13.13 for details regarding faults caused by memory
accesses.
13.8
OPERATION OF XRSTOR
The XRSTOR instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction
mask. The logical-AND of XCR0 and the instruction mask is the requested-feature bitmap (RFBM) of the user
state components to be restored.
The following conditions cause execution of the XRSTOR instruction to generate a fault:
•
If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
13-14 Vol. 1
MANAGING STATE USING THE XSAVE FEATURE SET
•
•
If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.
If the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP) occurs.1
After checking for these faults, the XRSTOR instruction reads the XCOMP_BV field in the XSAVE area’s XSAVE
header (see Section 13.4.2). If XCOMP_BV[63] = 0, the standard form of XRSTOR is executed (see Section
13.8.1); otherwise, the compacted form of XRSTOR is executed (see Section 13.8.2).2
See Section 13.2 for details of how to determine whether the compacted form of XRSTOR is supported.
13.8.1
Standard Form of XRSTOR
The standard from of XRSTOR performs additional fault checking. Either of the following conditions causes a
general-protection exception (#GP):
•
•
The XSTATE_BV field of the XSAVE header sets a bit that is not set in XCR0.
Bytes 23:8 of the XSAVE header are not all 0 (this implies that all bits in XCOMP_BV are 0).3
If none of these conditions cause a fault, the processor updates each state component i for which RFBM[i] = 1.
XRSTOR updates state component i based on the value of bit i in the XSTATE_BV field of the XSAVE header:
•
If XSTATE_BV[i] = 0, the state component is set to its initial configuration. Section 13.6 specifies the initial
configuration of each state component.
The initial configuration of state component 1 pertains only to the XMM registers and not to MXCSR. See below
for the treatment of MXCSR
•
If XSTATE_BV[i] = 1, the state component is loaded with data from the XSAVE area. See Section 13.5 for
specifics for each state component and for details regarding mode-specific operation and operation determined
by instruction prefixes. See Section 13.13 for details regarding faults caused by memory accesses.
State components 0 and 1 are located in the legacy region of the XSAVE area (see Section 13.4.1). Each state
component i, 2 ≤ i ≤ 62, is located in the extended region; the standard form of XRSTOR uses the standard
format for the extended region (see Section 13.4.3).
The MXCSR register is part of state component 1, SSE state (see Section 13.5.2). However, the standard form of
XRSTOR loads the MXCSR register from memory whenever the RFBM[1] (SSE) or RFBM[2] (AVX) is set, regardless
of the values of XSTATE_BV[1] and XSTATE_BV[2]. The standard form of XRSTOR causes a general-protection
exception (#GP) if it would load MXCSR with an illegal value.
13.8.2
Compacted Form of XRSTOR
The compacted from of XRSTOR performs additional fault checking. Any of the following conditions causes a #GP:
•
•
•
The XCOMP_BV field of the XSAVE header sets a bit in the range 62:0 that is not set in XCR0.
The XSTATE_BV field of the XSAVE header sets a bit (including bit 63) that is not set in XCOMP_BV.
Bytes 63:16 of the XSAVE header are not all 0.
If none of these conditions cause a fault, the processor updates each state component i for which RFBM[i] = 1.
XRSTOR updates state component i based on the value of bit i in the XSTATE_BV field of the XSAVE header:
•
If XSTATE_BV[i] = 0, the state component is set to its initial configuration. Section 13.6 specifies the initial
configuration of each state component.
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
2. If the processor does not support the compacted form of XRSTOR, it may execute the standard form of XRSTOR without first reading the XCOMP_BV field. A processor supports the compacted form of XRSTOR only if it enumerates
CPUID.(EAX=0DH,ECX=1):EAX[1] as 1.
3. Bytes 63:24 of the XSAVE header are also reserved. Software should ensure that bytes 63:16 of the XSAVE header are all 0 in any
XSAVE area. (Bytes 15:8 should also be 0 if the XSAVE area is to be used on a processor that does not support the compaction
extensions to the XSAVE feature set.)
Vol. 1 13-15
MANAGING STATE USING THE XSAVE FEATURE SET
If XSTATE_BV[1] = 0, the compacted form XRSTOR initializes MXCSR to 1F80H. (This differs from the standard
from of XRSTOR, which loads MXCSR from the XSAVE area whenever either RFBM[1] or RFBM[2] is set.)
State component i is set to its initial configuration as indicated above if RFBM[i] = 1 and XSTATE_BV[i] = 0 —
even if XCOMP_BV[i] = 0. This is true for all values of i, including 0 (x87 state) and 1 (SSE state).
•
If XSTATE_BV[i] = 1, the state component is loaded with data from the XSAVE area.1 See Section 13.5 for
specifics for each state component and for details regarding mode-specific operation and operation determined
by instruction prefixes. See Section 13.13 for details regarding faults caused by memory accesses.
State components 0 and 1 are located in the legacy region of the XSAVE area (see Section 13.4.1). Each state
component i, 2 ≤ i ≤ 62, is located in the extended region; the compacted form of the XRSTOR instruction uses
the compacted format for the extended region (see Section 13.4.3).
The MXCSR register is part of SSE state (see Section 13.5.2) and is thus loaded from memory if RFBM[1] =
XSTATE_BV[i] = 1. The compacted form of XRSTOR does not consider RFBM[2] (AVX) when determining whether
to update MXCSR. (This is a difference from the standard form of XRSTOR.) The compacted form of XRSTOR causes
a general-protection exception (#GP) if it would load MXCSR with an illegal value.
13.8.3
XRSTOR and the Init and Modified Optimizations
Execution of the XRSTOR instruction causes the processor to update is tracking for the init and modified optimizations (see Section 13.6). The following items provide details:
•
The processor updates its tracking for the init optimization as follows:
— If RFBM[i] = 0, XINUSE[i] is not changed.
— If RFBM[i] = 1 and XSTATE_BV[i] = 0, state component i may be tracked as init; XINUSE[i] may be set to
0 or 1. (As noted in Section 13.6, a processor need not implement the init optimization for state component
i; a processor that does not do so implicitly maintains XINUSE[i] = 1 at all times.)
— If RFBM[i] = 1 and XSTATE_BV[i] = 1, state component i is tracked as not init; XINUSE[i] is set to 1.
•
The processor updates its tracking for the modified optimization and records information about the XRSTOR
execution for future interaction with the XSAVEOPT and XSAVES instructions (see Section 13.9 and Section
13.11) as follows:
— If RFBM[i] = 0, state component i is tracked as modified; XMODIFIED[i] is set to 1.
— If RFBM[i] = 1, state component i may be tracked as unmodified; XMODIFIED[i] may be set to 0 or 1. (As
noted in Section 13.6, a processor need not implement the modified optimization for state component i; a
processor that does not do so implicitly maintains XMODIFIED[i] = 1 at all times.)
— XRSTOR_INFO is set to the 4-tuple w,x,y,z, where w is the CPL (0); x is 1 if the logical processor is in VMX
non-root operation and 0 otherwise; y is the linear address of the XSAVE area; and z is XCOMP_BV. In
particular, the standard form of XRSTOR always sets z to all zeroes, while the compacted form of XRSTORS
never does so (because it sets at least bit 63 to 1).
13.9
OPERATION OF XSAVEOPT
The operation of XSAVEOPT is similar to that of XSAVE. Unlike XSAVE, XSAVEOPT uses the init optimization (by
which it may omit saving state components that are in their initial configuration) and the modified optimization (by
which it may omit saving state components that have not been modified since the last execution of XRSTOR); see
Section 13.6. See Section 13.2 for details of how to determine whether XSAVEOPT is supported.
The XSAVEOPT instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction
mask. The logical (bitwise) AND of XCR0 and the instruction mask is the requested-feature bitmap (RFBM) of
the user state components to be saved.
1. Earlier fault checking ensured that, if the instruction has reached this point in execution and XSTATE_BV[i] is 1, then XCOMP_BV[i] is
also 1.
13-16 Vol. 1
MANAGING STATE USING THE XSAVE FEATURE SET
The following conditions cause execution of the XSAVEOPT instruction to generate a fault:
•
•
•
If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.
If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.
If the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP) occurs.1
If none of these conditions cause a fault, execution of XSAVEOPT reads the XSTATE_BV field of the XSAVE header
(see Section 13.4.2) and writes it back to memory, setting XSTATE_BV[i] (0 ≤ i ≤ 63) as follows:
•
•
If RFBM[i] = 0, XSTATE_BV[i] is not changed.
If RFBM[i] = 1, XSTATE_BV[i] is set to the value of XINUSE[i]. Section 13.6 defines XINUSE to describe the
processor init optimization and specifies the initial configuration of each state component. The nature of that
optimization implies the following:
— If the state component is in its initial configuration, XINUSE[i] may be either 0 or 1, and XSTATE_BV[i] may
be written with either 0 or 1.
XINUSE[1] pertains only to the state of the XMM registers and not to MXCSR. Thus, XSTATE_BV[1] may be
written with 0 even if MXCSR does not have its RESET value of 1F80H.
— If the state component is not in its initial configuration, XSTATE_BV[i] is written with 1.
(As explained in Section 13.6, the initial configurations of some state components may depend on whether the
processor is in 64-bit mode.)
The XSAVEOPT instruction does not write any part of the XSAVE header other than the XSTATE_BV field; in particular, it does not write to the XCOMP_BV field.
Execution of XSAVEOPT saves into the XSAVE area those state components corresponding to bits that are set in
RFBM (subject to the optimizations described below). State components 0 and 1 are located in the legacy region of
the XSAVE area (see Section 13.4.1). Each state component i, 2 ≤ i ≤ 62, is located in the extended region; the
XSAVEOPT instruction always uses the standard format for the extended region (see Section 13.4.3).
See Section 13.5 for specifics for each state component and for details regarding mode-specific operation and
operation determined by instruction prefixes. See Section 13.13 for details regarding faults caused by memory
accesses.
Execution of XSAVEOPT performs two optimizations that reduce the amount of data written to memory:
•
Init optimization.
If XINUSE[i] = 0, state component i is not saved to the XSAVE area (even if RFBM[i] = 1). (See below for
exceptions made for MXCSR.)
•
Modified optimization.
Each execution of XRSTOR and XRSTORS establishes XRSTOR_INFO as a 4-tuple w,x,y,z (see Section 13.8.3
and Section 13.12). Execution of XSAVEOPT uses the modified optimization only if the following all hold for the
current value of XRSTOR_INFO:
— w = CPL;
— x = 1 if and only if the logical processor is in VMX non-root operation;
— y is the linear address of the XSAVE area being used by XSAVEOPT; and
— z is 00000000_00000000H. (This last item implies that XSAVEOPT does not use the modified optimization
if the last execution of XRSTOR used the compacted form, or if an execution of XRSTORS followed the last
execution of XRSTOR.)
If XSAVEOPT uses the modified optimization and XMODIFIED[i] = 0 (see Section 13.6), state component i is
not saved to the XSAVE area.
(In practice, the benefit of the modified optimization for state component i depends on how the processor is
tracking state component i; see Section 13.6. Limitations on the tracking ability may result in state component
i being saved even though is in the same configuration that was loaded by the previous execution of XRSTOR.)
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
Vol. 1 13-17
MANAGING STATE USING THE XSAVE FEATURE SET
Depending on details of the operating system, an execution of XSAVEOPT by a user application might use the
modified optimization when the most recent execution of XRSTOR was by a different application. Because of
this, Intel recommends the application software not use the XSAVEOPT instruction.
The MXCSR register and MXCSR_MASK are part of SSE state (see Section 13.5.2) and are thus associated with
bit 1 of RFBM. However, the XSAVEOPT instruction also saves these values when RFBM[2] = 1 (even if RFBM[1] =
0). The init and modified optimizations do not apply to the MXCSR register and MXCSR_MASK.
13.10
OPERATION OF XSAVEC
The operation of XSAVEC is similar to that of XSAVE. Two main differences are (1) XSAVEC uses the compacted
format for the extended region of the XSAVE area; and (2) XSAVEC uses the init optimization (see Section 13.6).
Unlike XSAVEOPT, XSAVEC does not use the modified optimization. See Section 13.2 for details of how to determine
whether XSAVEC is supported.
The XSAVEC instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction
mask. The logical (bitwise) AND of XCR0 and the instruction mask is the requested-feature bitmap (RFBM) of
the user state components to be saved.
The following conditions cause execution of the XSAVEC instruction to generate a fault:
•
•
•
If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.
If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.
If the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP) occurs.1
If none of these conditions cause a fault, execution of XSAVEC writes the XSTATE_BV field of the XSAVE header
(see Section 13.4.2), setting XSTATE_BV[i] (0 ≤ i ≤ 63) as follows:2
•
•
If RFBM[i] = 0, XSTATE_BV[i] is written as 0.
If RFBM[i] = 1, XSTATE_BV[i] is set to the value of XINUSE[i] (see below for an exception made for
XSTATE_BV[1]). Section 13.6 defines XINUSE to describe the processor init optimization and specifies the
initial configuration of each state component. The nature of that optimization implies the following:
— If state component i is in its initial configuration, XSTATE_BV[i] may be written with either 0 or 1.
— If state component i is not in its initial configuration, XSTATE_BV[i] is written with 1.
XINUSE[1] pertains only to the state of the XMM registers and not to MXCSR. However, if RFBM[1] = 1 and
MXCSR does not have the value 1F80H, XSAVEC writes XSTATE_BV[1] as 1 even if XINUSE[1] = 0.
(As explained in Section 13.6, the initial configurations of some state components may depend on whether the
processor is in 64-bit mode.)
The XSAVEC instructions sets bit 63 of the XCOMP_BV field of the XSAVE header while writing RFBM[62:0] to
XCOMP_BV[62:0]. The XSAVEC instruction does not write any part of the XSAVE header other than the XSTATE_BV
and XCOMP_BV fields.
Execution of XSAVEC saves into the XSAVE area those state components corresponding to bits that are set in RFBM
(subject to the init optimization described below). State components 0 and 1 are located in the legacy region of the
XSAVE area (see Section 13.4.1). Each state component i, 2 ≤ i ≤ 62, is located in the extended region; the XSAVEC
instruction always uses the compacted format for the extended region (see Section 13.4.3).
See Section 13.5 for specifics for each state component and for details regarding mode-specific operation and
operation determined by instruction prefixes. See Section 13.13 for details regarding faults caused by memory
accesses.
Execution of XSAVEC performs the init optimization to reduce the amount of data written to memory. If
XINUSE[i] = 0, state component i is not saved to the XSAVE area (even if RFBM[i] = 1). However, if RFBM[1] = 1
and MXCSR does not have the value 1F80H, XSAVEC writes saves all of state component 1 (SSE — including the
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
2. Unlike the XSAVE and XSAVEOPT instructions, the XSAVEC instruction does not read the XSTATE_BV field of the XSAVE header.
13-18 Vol. 1
MANAGING STATE USING THE XSAVE FEATURE SET
XMM registers) even if XINUSE[1] = 0. Unlike the XSAVE instruction, RFBM[2] does not determine whether
XSAVEC saves MXCSR and MXCSR_MASK.
13.11
OPERATION OF XSAVES
The operation of XSAVES is similar to that of XSAVEC. The main differences are (1) XSAVES can be executed only
if CPL = 0; (2) XSAVES can operate on the state components whose bits are set in XCR0 | IA32_XSS and can thus
operate on supervisor state components; and (3) XSAVES uses the modified optimization (see Section 13.6). See
Section 13.2 for details of how to determine whether XSAVES is supported.
The XSAVES instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction
mask. EDX:EAX & (XCR0 | IA32_XSS) (the logical AND the instruction mask with the logical OR of XCR0 and
IA32_XSS) is the requested-feature bitmap (RFBM) of the state components to be saved.
The following conditions cause execution of the XSAVES instruction to generate a fault:
•
•
•
If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.
If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.
If CPL > 0 or if the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP)
occurs.1
If none of these conditions cause a fault, execution of XSAVES writes the XSTATE_BV field of the XSAVE header
(see Section 13.4.2), setting XSTATE_BV[i] (0 ≤ i ≤ 63) as follows:
•
•
If RFBM[i] = 0, XSTATE_BV[i] is written as 0.
If RFBM[i] = 1, XSTATE_BV[i] is set to the value of XINUSE[i] (see below for an exception made for
XSTATE_BV[1]). Section 13.6 defines XINUSE to describe the processor init optimization and specifies the
initial configuration of each state component. The nature of that optimization implies the following:
— If state component i is in its initial configuration, XSTATE_BV[i] may be written with either 0 or 1.
— If state component i is not in its initial configuration, XSTATE_BV[i] is written with 1.
XINUSE[1] pertains only to the state of the XMM registers and not to MXCSR. However, if RFBM[1] = 1 and
MXCSR does not have the value 1F80H, XSAVES writes XSTATE_BV[1] as 1 even if XINUSE[1] = 0.
(As explained in Section 13.6, the initial configurations of some state components may depend on whether the
processor is in 64-bit mode.)
The XSAVES instructions sets bit 63 of the XCOMP_BV field of the XSAVE header while writing RFBM[62:0] to
XCOMP_BV[62:0]. The XSAVES instruction does not write any part of the XSAVE header other than the XSTATE_BV
and XCOMP_BV fields.
Execution of XSAVES saves into the XSAVE area those state components corresponding to bits that are set in RFBM
(subject to the optimizations described below). State components 0 and 1 are located in the legacy region of the
XSAVE area (see Section 13.4.1). Each state component i, 2 ≤ i ≤ 62, is located in the extended region; the XSAVES
instruction always uses the compacted format for the extended region (see Section 13.4.3).
See Section 13.5 for specifics for each state component and for details regarding mode-specific operation and
operation determined by instruction prefixes; in particular, see Section 13.5.6 for some special treatment of PT
state by XSAVES. See Section 13.13 for details regarding faults caused by memory accesses.
Execution of XSAVES performs the init optimization to reduce the amount of data written to memory. If
XINUSE[i] = 0, state component i is not saved to the XSAVE area (even if RFBM[i] = 1). However, if RFBM[1] = 1
and MXCSR does not have the value 1F80H, XSAVES writes saves all of state component 1 (SSE — including the
XMM registers) even if XINUSE[1] = 0.
Like XSAVEOPT, XSAVES may perform the modified optimization. Each execution of XRSTOR and XRSTORS establishes XRSTOR_INFO as a 4-tuple w,x,y,z (see Section 13.8.3 and Section 13.12). Execution of XSAVES uses the
modified optimization only if the following all hold:
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
Vol. 1 13-19
MANAGING STATE USING THE XSAVE FEATURE SET
•
•
•
•
w = CPL;
x = 1 if and only if the logical processor is in VMX non-root operation;
y is the linear address of the XSAVE area being used by XSAVEOPT; and
z[63] is 1 and z[62:0] = RFBM[62:0]. (This last item implies that XSAVES does not use the modified optimization if the last execution of XRSTOR used the standard form and followed the last execution of XRSTORS.)
If XSAVES uses the modified optimization and XMODIFIED[i] = 0 (see Section 13.6), state component i is not
saved to the XSAVE area.
13.12
OPERATION OF XRSTORS
The operation of XRSTORS is similar to that of XRSTOR. Three main differences are (1) XRSTORS can be executed
only if CPL = 0; (2) XRSTORS can operate on the state components whose bits are set in XCR0 | IA32_XSS and can
thus operate on supervisor state components; and (3) XRSTORS has only a compacted form (no standard form;
see Section 13.8). See Section 13.2 for details of how to determine whether XRSTORS is supported.
The XRSTORS instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction
mask. EDX:EAX & (XCR0 | IA32_XSS) (the logical AND the instruction mask with the logical OR of XCR0 and
IA32_XSS) is the requested-feature bitmap (RFBM) of the state components to be restored.
The following conditions cause execution of the XRSTOR instruction to generate a fault:
•
•
•
If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.
If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.
If CPL > 0 or if the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP)
occurs.1
After checking for these faults, the XRSTORS instruction reads the first 64 bytes of the XSAVE header, including the
XSTATE_BV and XCOMP_BV fields (see Section 13.4.2). A #GP occurs if any of the following conditions hold for the
values read:
•
•
•
•
XCOMP_BV[63] = 0.
XCOMP_BV sets a bit in the range 62:0 that is not set in XCR0 | IA32_XSS.
XSTATE_BV sets a bit (including bit 63) that is not set in XCOMP_BV.
Bytes 63:16 of the XSAVE header are not all 0.
If none of these conditions cause a fault, the processor updates each state component i for which RFBM[i] = 1.
XRSTORS updates state component i based on the value of bit i in the XSTATE_BV field of the XSAVE header:
•
If XSTATE_BV[i] = 0, the state component is set to its initial configuration. Section 13.6 specifies the initial
configuration of each state component. If XSTATE_BV[1] = 0, XRSTORS initializes MXCSR to 1F80H.
State component i is set to its initial configuration as indicated above if RFBM[i] = 1 and XSTATE_BV[i] = 0 —
even if XCOMP_BV[i] = 0. This is true for all values of i, including 0 (x87 state) and 1 (SSE state).
•
If XSTATE_BV[i] = 1, the state component is loaded with data from the XSAVE area.2 See Section 13.5 for
specifics for each state component and for details regarding mode-specific operation and operation determined
by instruction prefixes; in particular, see Section 13.5.6 for some special treatment of PT state by XRSTORS.
See Section 13.13 for details regarding faults caused by memory accesses.
If XRSTORS is restoring a supervisor state component, the instruction causes a general-protection exception
(#GP) if it would load any element of that component with an unsupported value (e.g., by setting a reserved bit
in an MSR) or if a bit is set in any reserved portion of the state component in the XSAVE area.
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
2. Earlier fault checking ensured that, if the instruction has reached this point in execution and XSTATE_BV[i] is 1, then XCOMP_BV[i] is
also 1.
13-20 Vol. 1
MANAGING STATE USING THE XSAVE FEATURE SET
State components 0 and 1 are located in the legacy region of the XSAVE area (see Section 13.4.1). Each state
component i, 2 ≤ i ≤ 62, is located in the extended region; XRSTORS uses the compacted format for the
extended region (see Section 13.4.3).
The MXCSR register is part of SSE state (see Section 13.5.2) and is thus loaded from memory if RFBM[1] =
XSTATE_BV[i] = 1. XRSTORS causes a general-protection exception (#GP) if it would load MXCSR with an
illegal value.
If an execution of XRSTORS causes an exception or a VM exit during or after restoring a supervisor state component, each element of that state component may have the value it held before the XRSTORS execution, the value
loaded from the XSAVE area, or the element’s initial value (as defined in Section 13.6). See Section 13.5.6 for
some special treatment of PT state for the case in which XRSTORS causes an exception or a VM exit.
Like XRSTOR, execution of XRSTORS causes the processor to update is tracking for the init and modified optimizations (see Section 13.6 and Section 13.8.3). The following items provide details:
•
The processor updates its tracking for the init optimization as follows:
— If RFBM[i] = 0, XINUSE[i] is not changed.
— If RFBM[i] = 1 and XSTATE_BV[i] = 0, state component i may be tracked as init; XINUSE[i] may be set to
0 or 1.
— If RFBM[i] = 1 and XSTATE_BV[i] = 1, state component i is tracked as not init; XINUSE[i] is set to 1.
•
The processor updates its tracking for the modified optimization and records information about the XRSTORS
execution for future interaction with the XSAVEOPT and XSAVES instructions as follows:
— If RFBM[i] = 0, state component i is tracked as modified; XMODIFIED[i] is set to 1.
— If RFBM[i] = 1, state component i may be tracked as unmodified; XMODIFIED[i] may be set to 0 or 1.
— XRSTOR_INFO is set to the 4-tuple w,x,y,z, where w is the CPL; x is 1 if the logical processor is in VMX
non-root operation and 0 otherwise; y is the linear address of the XSAVE area; and z is XCOMP_BV (this
implies that z[63] = 1).
13.13
MEMORY ACCESSES BY THE XSAVE FEATURE SET
Each instruction in the XSAVE feature set operates on a set of XSAVE-managed state components. The specific set
of components on which an instruction operates is determined by the values of XCR0, the IA32_XSS MSR,
EDX:EAX, and (for XRSTOR and XRSTORS) the XSAVE header.
Section 13.4 provides the details necessary to determine the location of each state component for any execution of
an instruction in the XSAVE feature set. An execution of an instruction in the XSAVE feature set may access any
byte of any state component on which that execution operates.
Section 13.5 provides details of the different XSAVE-managed state components. Some portions of some of these
components are accessible only in 64-bit mode. Executions of XRSTOR and XRSTORS outside 64-bit mode will not
update those portions; executions of XSAVE, XSAVEC, XSAVEOPT, and XSAVES will not modify the corresponding
locations in memory.
Despite this fact, any execution of these instructions outside 64-bit mode may access any byte in any state component on which that execution operates — even those at addresses corresponding to registers that are accessible
only in 64-bit mode. As result, such an execution may incur a fault due to an attempt to access such an address.
For example, an execution of XSAVE outside 64-bit mode may incur a page fault if paging does not map as
read/write the section of the XSAVE area containing state component 7 (Hi16_ZMM state) — despite the fact that
state component 7 can be accessed only in 64-bit mode.
Vol. 1 13-21
MANAGING STATE USING THE XSAVE FEATURE SET
13-22 Vol. 1
CHAPTER 14
PROGRAMMING WITH AVX, FMA AND AVX2
Intel® Advanced Vector Extensions (Intel® AVX) introduces 256-bit vector processing capability. The Intel AVX
instruction set extends 128-bit SIMD instruction sets by employing a new instruction encoding scheme via a vector
extension prefix (VEX). Intel AVX also offers several enhanced features beyond those available in prior generations
of 128-bit SIMD extensions.
FMA (Fused Multiply Add) extensions enhances Intel AVX further in floating-point numeric computations. FMA
provides high-throughput, arithmetic operations cover fused multiply-add, fused multiply-subtract, fused multiply
add/subtract interleave, signed-reversed multiply on fused multiply-add and multiply-subtract.
Intel AVX2 provides 256-bit integer SIMD extensions that accelerate computation across integer and floating-point
domains using 256-bit vector registers.
This chapter summarizes the key features of Intel AVX, FMA and AVX2.
14.1
INTEL AVX OVERVIEW
Intel AVX introduces the following architectural enhancements:
•
•
Support for 256-bit wide vectors with the YMM vector register set.
•
Enhancement of legacy 128-bit SIMD instruction extensions to support three-operand syntax and to simplify
compiler vectorization of high-level language expressions.
•
VEX prefix-encoded instruction syntax support for generalized three-operand syntax to improve instruction
programming flexibility and efficient encoding of new instruction extensions.
•
Most VEX-encoded 128-bit and 256-bit AVX instructions (with both load and computational operation
semantics) are not restricted to 16-byte or 32-byte memory alignment.
•
Support flexible deployment of 256-bit AVX code, 128-bit AVX code, legacy 128-bit code and scalar code.
256-bit floating-point instruction set enhancement with up to 2X performance gain relative to 128-bit
Streaming SIMD extensions.
With the exception of SIMD instructions operating on MMX registers, almost all legacy 128-bit SIMD instructions
have AVX equivalents that support three operand syntax. 256-bit AVX instructions employ three-operand syntax
and some with 4-operand syntax.
14.1.1
256-Bit Wide SIMD Register Support
Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7 in operating modes that are 32-bit or
less, YMM0-YMM15 in 64-bit mode). The lower 128-bits of the YMM registers are aliased to the respective 128-bit
XMM registers.
Legacy SSE instructions (i.e. SIMD instructions operating on XMM state but not using the VEX prefix, also referred
to non-VEX encoded SIMD instructions) will not access the upper bits beyond bit 128 of the YMM registers. AVX
instructions with a VEX prefix and vector length of 128-bits zeroes the upper bits (above bit 128) of the YMM
register.
Vol. 1 14-1
PROGRAMMING WITH AVX, FMA AND AVX2
Bit#
0
128 127
255
YMM0
XMM0
YMM1
XMM1
...
YMM15
XMM15
Figure 14-1. 256-Bit Wide SIMD Register
14.1.2
Instruction Syntax Enhancements
Intel AVX employs an instruction encoding scheme using a new prefix (known as “VEX” prefix). Instruction
encoding using the VEX prefix can directly encode a register operand within the VEX prefix. This support two new
instruction syntax in Intel 64 architecture:
•
A non-destructive operand (in a three-operand instruction syntax): The non-destructive source reduces the
number of registers, register-register copies and explicit load operations required in typical SSE loops, reduces
code size, and improves micro-fusion opportunities.
•
A third source operand (in a four-operand instruction syntax) via the upper 4 bits in an 8-bit immediate field.
Support for the third source operand is defined for selected instructions (e.g. VBLENDVPD, VBLENDVPS,
PBLENDVB).
Two-operand instruction syntax previously expressed in legacy SSE instruction as
ADDPS xmm1, xmm2/m128
128-bit AVX equivalent can be expressed in three-operand syntax as
VADDPS xmm1, xmm2, xmm3/m128
In four-operand syntax, the extra register operand is encoded in the immediate byte.
Note SIMD instructions supporting three-operand syntax but processing only 128-bits of data are considered part
of the 256-bit SIMD instruction set extensions of AVX, because bits 255:128 of the destination register are zeroed
by the processor.
14.1.3
VEX Prefix Instruction Encoding Support
Intel AVX introduces a new prefix, referred to as VEX, in the Intel 64 and IA-32 instruction encoding format.
Instruction encoding using the VEX prefix provides the following capabilities:
•
Direct encoding of a register operand within VEX. This provides instruction syntax support for non-destructive
source operand.
•
Efficient encoding of instruction syntax operating on 128-bit and 256-bit register sets.
14-2 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
•
•
Compaction of REX prefix functionality: The equivalent functionality of the REX prefix is encoded within VEX.
•
Most VEX-encoded SIMD numeric and data processing instruction semantics with memory operand have
relaxed memory alignment requirements than instructions encoded using SIMD prefixes (see Section 14.9).
Compaction of SIMD prefix functionality and escape byte encoding: The functionality of SIMD prefix (66H, F2H,
F3H) on opcode is equivalent to an opcode extension field to introduce new processing primitives. This
functionality is replaced by a more compact representation of opcode extension within the VEX prefix. Similarly,
the functionality of the escape opcode byte (0FH) and two-byte escape (0F38H, 0F3AH) are also compacted
within the VEX prefix encoding.
VEX prefix encoding applies to SIMD instructions operating on YMM registers, XMM registers, and in some cases
with a general-purpose register as one of the operand. VEX prefix is not supported for instructions operating on
MMX or x87 registers. Details of VEX prefix and instruction encoding are discussed in Chapter 2, “Instruction
Format,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
14.2
FUNCTIONAL OVERVIEW
Intel AVX provide comprehensive functional improvements over previous generations of SIMD instruction extensions. The functional improvements include:
•
256-bit floating-point arithmetic primitives: AVX enhances existing 128-bit floating-point arithmetic instructions with 256-bit capabilities for floating-point processing. Table 14-1 lists SIMD instructions promoted to AVX.
•
Enhancements for flexible SIMD data movements: AVX provides a number of new data movement primitives to
enable efficient SIMD programming in relation to loading non-unit-strided data into SIMD registers, intraregister SIMD data manipulation, conditional expression and branch handling, etc. Enhancements for SIMD
data movement primitives cover 256-bit and 128-bit vector floating-point data, and across 128-bit integer
SIMD data processing using VEX-encoded instructions.
Table 14-1. Promoted SSE/SSE2/SSE3/SSSE3/SSE4 Instructions
VEX.256
Encoding
VEX.128
Encoding
Group
YY 0F 1X
Instruction
If No, Reason?
yes
yes
no
yes
MOVUPS
MOVSS
yes
yes
MOVUPD
no
yes
MOVSD
no
yes
MOVLPS
Note 1
no
yes
MOVLPD
Note 1
Redundant with VPERMILPS
no
yes
MOVLHPS
yes
yes
MOVDDUP
scalar
scalar
yes
yes
MOVSLDUP
yes
yes
UNPCKLPS
yes
yes
UNPCKLPD
yes
yes
UNPCKHPS
yes
yes
UNPCKHPD
no
yes
MOVHPS
Note 1
no
yes
MOVHPD
Note 1
no
yes
MOVHLPS
Redundant with VPERMILPS
yes
yes
MOVAPS
yes
yes
MOVSHDUP
yes
yes
MOVAPD
no
no
CVTPI2PS
MMX
Vol. 1 14-3
PROGRAMMING WITH AVX, FMA AND AVX2
VEX.256
Encoding
VEX.128
Encoding
Group
Instruction
If No, Reason?
no
yes
CVTSI2SS
scalar
no
no
CVTPI2PD
MMX
scalar
no
yes
CVTSI2SD
no
yes
MOVNTPS
no
yes
MOVNTPD
no
no
CVTTPS2PI
MMX
no
yes
CVTTSS2SI
scalar
no
no
CVTTPD2PI
MMX
no
yes
CVTTSD2SI
scalar
no
no
CVTPS2PI
MMX
no
yes
CVTSS2SI
scalar
no
no
CVTPD2PI
MMX
no
yes
CVTSD2SI
scalar
no
yes
UCOMISS
scalar
no
yes
UCOMISD
scalar
no
yes
COMISS
scalar
COMISD
scalar
no
yes
yes
yes
yes
yes
MOVMSKPD
yes
yes
SQRTPS
YY 0F 5X
MOVMSKPS
no
yes
SQRTSS
yes
yes
SQRTPD
no
yes
SQRTSD
yes
yes
RSQRTPS
no
yes
RSQRTSS
yes
yes
RCPPS
no
yes
RCPSS
yes
yes
ANDPS
yes
yes
ANDPD
yes
yes
ANDNPS
yes
yes
ANDNPD
yes
yes
ORPS
yes
yes
ORPD
yes
yes
XORPS
yes
yes
XORPD
yes
yes
ADDPS
no
yes
ADDSS
yes
yes
ADDPD
no
yes
ADDSD
yes
yes
MULPS
no
yes
MULSS
yes
yes
MULPD
no
yes
MULSD
yes
yes
CVTPS2PD
14-4 Vol. 1
scalar
scalar
scalar
scalar
scalar
scalar
scalar
scalar
PROGRAMMING WITH AVX, FMA AND AVX2
VEX.256
Encoding
VEX.128
Encoding
Group
Instruction
no
yes
CVTSS2SD
yes
yes
CVTPD2PS
no
yes
CVTSD2SS
yes
yes
CVTDQ2PS
yes
yes
CVTPS2DQ
yes
yes
CVTTPS2DQ
yes
yes
SUBPS
no
yes
SUBSS
yes
yes
SUBPD
no
yes
SUBSD
yes
yes
MINPS
If No, Reason?
scalar
scalar
scalar
scalar
no
yes
MINSS
yes
yes
MINPD
no
yes
MINSD
yes
yes
DIVPS
no
yes
DIVSS
yes
yes
DIVPD
no
yes
DIVSD
yes
yes
MAXPS
no
yes
MAXSS
yes
yes
MAXPD
no
yes
MAXSD
scalar
PUNPCKLBW
VI
YY 0F 6X
scalar
scalar
scalar
scalar
scalar
no
yes
no
yes
PUNPCKLWD
VI
no
yes
PUNPCKLDQ
VI
no
yes
PACKSSWB
VI
no
yes
PCMPGTB
VI
no
yes
PCMPGTW
VI
no
yes
PCMPGTD
VI
no
yes
PACKUSWB
VI
no
yes
PUNPCKHBW
VI
no
yes
PUNPCKHWD
VI
no
yes
PUNPCKHDQ
VI
no
yes
PACKSSDW
VI
no
yes
PUNPCKLQDQ
VI
no
yes
PUNPCKHQDQ
VI
no
yes
MOVD
scalar
no
yes
MOVQ
scalar
yes
yes
MOVDQA
yes
yes
MOVDQU
no
yes
no
yes
YY 0F 7X
PSHUFHW
PSHUFD
VI
VI
no
yes
PSHUFLW
VI
no
yes
PCMPEQB
VI
Vol. 1 14-5
PROGRAMMING WITH AVX, FMA AND AVX2
VEX.256
Encoding
VEX.128
Encoding
Group
Instruction
If No, Reason?
no
yes
PCMPEQW
VI
no
yes
PCMPEQD
VI
yes
yes
HADDPD
yes
yes
HADDPS
yes
yes
HSUBPD
yes
yes
HSUBPS
no
yes
MOVD
VI
no
yes
MOVQ
VI
yes
yes
MOVDQA
yes
yes
MOVDQU
no
yes
YY 0F AX
LDMXCSR
YY 0F CX
CMPPS
no
yes
yes
yes
STMXCSR
no
yes
CMPSS
yes
yes
CMPPD
no
yes
CMPSD
scalar
scalar
no
yes
PINSRW
VI
no
yes
PEXTRW
VI
yes
yes
SHUFPS
yes
yes
SHUFPD
yes
yes
yes
yes
ADDSUBPS
no
yes
PSRLW
VI
no
yes
PSRLD
VI
no
yes
PSRLQ
VI
no
yes
PADDQ
VI
YY 0F DX
ADDSUBPD
no
yes
PMULLW
VI
no
no
MOVQ2DQ
MMX
MMX
no
no
MOVDQ2Q
no
yes
PMOVMSKB
VI
no
yes
PSUBUSB
VI
no
yes
PSUBUSW
VI
no
yes
PMINUB
VI
no
yes
PAND
VI
no
yes
PADDUSB
VI
no
yes
PADDUSW
VI
no
yes
PMAXUB
VI
no
yes
PANDN
VI
no
yes
PAVGB
VI
no
yes
PSRAW
VI
no
yes
PSRAD
VI
no
yes
PAVGW
VI
no
yes
PMULHUW
VI
no
yes
PMULHW
VI
14-6 Vol. 1
YY 0F EX
PROGRAMMING WITH AVX, FMA AND AVX2
VEX.256
Encoding
VEX.128
Encoding
Group
Instruction
If No, Reason?
yes
yes
CVTPD2DQ
yes
yes
CVTTPD2DQ
yes
yes
CVTDQ2PD
no
yes
MOVNTDQ
VI
no
yes
PSUBSB
VI
no
yes
PSUBSW
VI
no
yes
PMINSW
VI
no
yes
POR
VI
no
yes
PADDSB
VI
no
yes
PADDSW
VI
no
yes
PMAXSW
VI
no
yes
yes
yes
PXOR
VI
LDDQU
VI
no
yes
PSLLW
VI
no
yes
PSLLD
VI
no
yes
PSLLQ
VI
VI
YY 0F FX
no
yes
PMULUDQ
no
yes
PMADDWD
VI
no
yes
PSADBW
VI
no
yes
MASKMOVDQU
no
yes
PSUBB
VI
no
yes
PSUBW
VI
no
yes
PSUBD
VI
no
yes
PSUBQ
VI
no
yes
PADDB
VI
no
yes
PADDW
VI
PADDD
VI
PHADDW
VI
no
yes
no
yes
SSSE3
no
yes
PHADDSW
VI
no
yes
PHADDD
VI
no
yes
PHSUBW
VI
no
yes
PHSUBSW
VI
no
yes
PHSUBD
VI
no
yes
PMADDUBSW
VI
VI
no
yes
PALIGNR
no
yes
PSHUFB
VI
no
yes
PMULHRSW
VI
no
yes
PSIGNB
VI
no
yes
PSIGNW
VI
no
yes
PSIGND
VI
no
yes
PABSB
VI
no
yes
PABSW
VI
no
yes
PABSD
VI
yes
yes
SSE4.1
BLENDPS
Vol. 1 14-7
PROGRAMMING WITH AVX, FMA AND AVX2
VEX.256
Encoding
VEX.128
Encoding
Group
Instruction
If No, Reason?
yes
yes
BLENDPD
yes
yes
BLENDVPS
Note 2
Note 2
yes
yes
BLENDVPD
no
yes
DPPD
yes
yes
DPPS
no
yes
EXTRACTPS
Note 3
no
yes
INSERTPS
Note 3
no
yes
MOVNTDQA
no
yes
MPSADBW
VI
no
yes
PACKUSDW
VI
no
yes
PBLENDVB
VI
no
yes
PBLENDW
VI
no
yes
PCMPEQQ
VI
no
yes
PEXTRD
VI
no
yes
PEXTRQ
VI
no
yes
PEXTRB
VI
VI
no
yes
PEXTRW
no
yes
PHMINPOSUW
VI
no
yes
PINSRB
VI
no
yes
PINSRD
VI
no
yes
PINSRQ
VI
no
yes
PMAXSB
VI
no
yes
PMAXSD
VI
no
yes
PMAXUD
VI
no
yes
PMAXUW
VI
no
yes
PMINSB
VI
no
yes
PMINSD
VI
no
yes
PMINUD
VI
no
yes
PMINUW
VI
no
yes
PMOVSXxx
VI
no
yes
PMOVZXxx
VI
no
yes
PMULDQ
VI
VI
no
yes
PMULLD
yes
yes
PTEST
yes
yes
ROUNDPD
yes
yes
ROUNDPS
no
yes
ROUNDSD
scalar
no
yes
ROUNDSS
scalar
no
yes
SSE4.2
PCMPGTQ
VI
no
no
SSE4.2
CRC32c
integer
no
yes
PCMPESTRI
VI
no
yes
PCMPESTRM
VI
14-8 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
VEX.256
Encoding
VEX.128
Encoding
Group
Instruction
If No, Reason?
no
yes
PCMPISTRI
VI
no
yes
PCMPISTRM
VI
no
no
POPCNT
integer
14.2.1
SSE4.2
256-bit Floating-Point Arithmetic Processing Enhancements
Intel AVX provides 35 256-bit floating-point arithmetic instructions, see Table 14-2. The arithmetic operations
cover add, subtract, multiply, divide, square-root, compare, max, min, round, etc., on single-precision and doubleprecision floating-point data.
The enhancement in AVX on floating-point compare operation provides 32 conditional predicates to improve
programming flexibility in evaluating conditional expressions.
Table 14-2. Promoted 256-Bit and 128-bit Arithmetic AVX Instructions
VEX.256 Encoding
VEX.128 Encoding
Legacy Instruction Mnemonic
yes
yes
SQRTPS, SQRTPD, RSQRTPS, RCPPS
yes
yes
ADDPS, ADDPD, SUBPS, SUBPD
yes
yes
MULPS, MULPD, DIVPS, DIVPD
yes
yes
CVTPS2PD, CVTPD2PS
yes
yes
CVTDQ2PS, CVTPS2DQ
yes
yes
CVTTPS2DQ, CVTTPD2DQ
yes
yes
CVTPD2DQ, CVTDQ2PD
yes
yes
MINPS, MINPD, MAXPS, MAXPD
yes
yes
HADDPD, HADDPS, HSUBPD, HSUBPS
yes
yes
CMPPS, CMPPD
yes
yes
ADDSUBPD, ADDSUBPS, DPPS
yes
yes
ROUNDPD, ROUNDPS
14.2.2
256-bit Non-Arithmetic Instruction Enhancements
Intel AVX provides new primitives for handling data movement within 256-bit floating-point vectors and promotes
many 128-bit floating data processing instructions to handle 256-bit floating-point vectors.
AVX includes 39 256-bit data movement and processing instructions that are promoted from previous generations
of SIMD instruction extensions, ranging from logical, blend, convert, test, unpacking, shuffling, load and stores
(see Table 14-3).
Table 14-3. Promoted 256-bit and 128-bit Data Movement AVX Instructions
VEX.256 Encoding
VEX.128 Encoding
Legacy Instruction Mnemonic
yes
yes
MOVAPS, MOVAPD, MOVDQA
yes
yes
MOVUPS, MOVUPD, MOVDQU
yes
yes
MOVMSKPS, MOVMSKPD
yes
yes
LDDQU, MOVNTPS, MOVNTPD, MOVNTDQ, MOVNTDQA
yes
yes
MOVSHDUP, MOVSLDUP, MOVDDUP
Vol. 1 14-9
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-3. Promoted 256-bit and 128-bit Data Movement AVX Instructions
VEX.256 Encoding
VEX.128 Encoding
Legacy Instruction Mnemonic
yes
yes
UNPCKHPD, UNPCKHPS, UNPCKLPD
yes
yes
BLENDPS, BLENDPD
yes
yes
SHUFPD, SHUFPS, UNPCKLPS
yes
yes
BLENDVPS, BLENDVPD
yes
yes
PTEST, MOVMSKPD, MOVMSKPS
yes
yes
XORPS, XORPD, ORPS, ORPD
yes
yes
ANDNPD, ANDNPS, ANDPD, ANDPS
AVX introduces 18 new data processing instructions that operate on 256-bit vectors, Table 14-4. These new primitives cover the following operations:
•
Non-unit-strided fetching of SIMD data. AVX provides several flexible SIMD floating-point data fetching
primitives:
— broadcast of single or multiple data elements into a 256-bit destination,
— masked move primitives to load or store SIMD data elements conditionally,
•
Intra-register manipulation of SIMD data elements. AVX provides several flexible SIMD floating-point data
manipulation primitives:
— insert/extract multiple SIMD floating-point data elements to/from 256-bit SIMD registers
— permute primitives to facilitate efficient manipulation of floating-point data elements in 256-bit SIMD
registers
•
Branch handling. AVX provides several primitives to enable handling of branches in SIMD programming:
— new variable blend instructions supports four-operand syntax with non-destructive source syntax. This is
more flexible than the equivalent SSE4 instruction syntax which uses the XMM0 register as the implied
mask for blend selection.
— Packed TEST instructions for floating-point data.
Table 14-4. 256-bit AVX Instruction Enhancement
Instruction
Description
VBROADCASTF128 ymm1, m128
Broadcast 128-bit floating-point values in mem to low and high 128-bits in ymm1.
VBROADCASTSD ymm1, m64
Broadcast double-precision floating-point element in mem to four locations in ymm1.
VBROADCASTSS ymm1, m32
Broadcast single-precision floating-point element in mem to eight locations in ymm1.
VEXTRACTF128 xmm1/m128, ymm2,
imm8
Extracts 128-bits of packed floating-point values from ymm2 and store results in
xmm1/mem.
VINSERTF128 ymm1, ymm2,
xmm3/m128, imm8
Insert 128-bits of packed floating-point values from xmm3/mem and the remaining values from ymm2 into ymm1
VMASKMOVPS ymm1, ymm2, m256
Load packed single-precision values from mem using mask in ymm2 and store in ymm1
VMASKMOVPD ymm1, ymm2, m256
Load packed double-precision values from mem using mask in ymm2 and store in ymm1
VMASKMOVPS m256, ymm1, ymm2
Store packed single-precision values from ymm2 mask in ymm1
VMASKMOVPD m256, ymm1, ymm2
Store packed double-precision values from ymm2 using mask in ymm1
VPERMILPD ymm1, ymm2, ymm3/m256
Permute Double-Precision Floating-Point values in ymm2 using controls from xmm3/mem
and store result in ymm1
14-10 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-4. 256-bit AVX Instruction Enhancement
Instruction
Description
VPERMILPD ymm1, ymm2/m256 imm8
Permute Double-Precision Floating-Point values in ymm2/mem using controls from imm8
and store result in ymm1
VPERMILPS ymm1, ymm2, ymm/m256
Permute Single-Precision Floating-Point values in ymm2 using controls from ymm3/mem
and store result in ymm1
VPERMILPS ymm1, ymm2/m256, imm8
Permute Single-Precision Floating-Point values in ymm2/mem using controls from imm8
and store result in ymm1
VPERM2F128 ymm1, ymm2,
ymm3/m256, imm8
Permute 128-bit floating-point fields in ymm2 and ymm3/mem using controls from imm8
and store result in ymm1
VTESTPS ymm1, ymm2/m256
Set ZF if ymm2/mem AND ymm1 result is all 0s in packed single-precision sign bits. Set CF
if ymm2/mem AND NOT ymm1 result is all 0s in packed single-precision sign bits.
VTESTPD ymm1, ymm2/m256
Set ZF if ymm2/mem AND ymm1 result is all 0s in packed double-precision sign bits. Set
CF if ymm2/mem AND NOT ymm1 result is all 0s in packed double-precision sign bits.
VZEROALL
Zero all YMM registers
VZEROUPPER
Zero upper 128 bits of all YMM registers
14.2.3
Arithmetic Primitives for 128-bit Vector and Scalar processing
Intel AVX provides a full complement of 128-bit numeric processing instructions that employ VEX-prefix encoding.
These VEX-encoded instructions generally provide the same functionality over instructions operating on XMM
register that are encoded using SIMD prefixes. The 128-bit numeric processing instructions in AVX cover floatingpoint and integer data processing; across 128-bit vector and scalar processing. Table 14-5 lists the state of promotion of legacy SIMD arithmetic ISA to VEX-128 encoding. Legacy SIMD floating-point arithmetic ISA promoted to
VEX-256 encoding also support VEX-128 encoding (see Table 14-2).
The enhancement in AVX on 128-bit floating-point compare operation provides 32 conditional predicates to
improve programming flexibility in evaluating conditional expressions. This contrasts with floating-point SIMD
compare instructions in SSE and SSE2 supporting only 8 conditional predicates.
Table 14-5. Promotion of Legacy SIMD ISA to 128-bit Arithmetic AVX instruction
VEX.256
Encoding
no
VEX.128
Encoding
no
Instruction
Reason Not Promoted
CVTPI2PS, CVTPI2PD, CVTPD2PI
MMX
no
no
CVTTPS2PI, CVTTPD2PI, CVTPS2PI
MMX
no
yes
CVTSI2SS, CVTSI2SD, CVTSD2SI
scalar
no
yes
CVTTSS2SI, CVTTSD2SI, CVTSS2SI
scalar
no
yes
COMISD, RSQRTSS, RCPSS
scalar
no
yes
UCOMISS, UCOMISD, COMISS,
scalar
no
yes
ADDSS, ADDSD, SUBSS, SUBSD
scalar
no
yes
MULSS, MULSD, DIVSS, DIVSD
scalar
no
yes
SQRTSS, SQRTSD
scalar
no
yes
CVTSS2SD, CVTSD2SS
scalar
no
yes
MINSS, MINSD, MAXSS, MAXSD
scalar
no
yes
PAND, PANDN, POR, PXOR
VI
no
yes
PCMPGTB, PCMPGTW, PCMPGTD
VI
Vol. 1 14-11
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-5. Promotion of Legacy SIMD ISA to 128-bit Arithmetic AVX instruction
VEX.256
Encoding
VEX.128
Encoding
Instruction
Reason Not Promoted
no
yes
PMADDWD, PMADDUBSW
VI
no
yes
PAVGB, PAVGW, PMULUDQ
VI
no
yes
PCMPEQB, PCMPEQW, PCMPEQD
VI
no
yes
PMULLW, PMULHUW, PMULHW
VI
no
yes
PSUBSW, PADDSW, PSADBW
VI
no
yes
PADDUSB, PADDUSW, PADDSB
VI
no
yes
PSUBUSB, PSUBUSW, PSUBSB
VI
no
yes
PMINUB, PMINSW
VI
no
yes
PMAXUB, PMAXSW
VI
no
yes
PADDB, PADDW, PADDD, PADDQ
VI
no
yes
PSUBB, PSUBW, PSUBD, PSUBQ
VI
no
yes
PSLLW, PSLLD, PSLLQ, PSRAW
VI
no
yes
PSRLW, PSRLD, PSRLQ, PSRAD
VI
CPUID.SSSE3
no
yes
PHSUBW, PHSUBD, PHSUBSW
VI
no
yes
PHADDW, PHADDD, PHADDSW
VI
no
yes
PMULHRSW
VI
no
yes
PSIGNB, PSIGNW, PSIGND
VI
no
yes
PABSB, PABSW, PABSD
VI
CPUID.SSE4_1
no
yes
DPPD
no
yes
PHMINPOSUW, MPSADBW
VI
no
yes
PMAXSB, PMAXSD, PMAXUD
VI
no
yes
PMINSB, PMINSD, PMINUD
VI
no
yes
PMAXUW, PMINUW
VI
no
yes
PMOVSXxx, PMOVZXxx
VI
no
yes
PMULDQ, PMULLD
VI
no
yes
ROUNDSD, ROUNDSS
scalar
CPUID.POPCNT
no
yes
POPCNT
integer
CPUID.SSE4_2
no
yes
PCMPGTQ
VI
no
no
CRC32
integer
no
yes
PCMPESTRI, PCMPESTRM
VI
no
yes
PCMPISTRI, PCMPISTRM
VI
CPUID.CLMUL
no
yes
PCLMULQDQ
VI
CPUID.AESNI
14-12 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-5. Promotion of Legacy SIMD ISA to 128-bit Arithmetic AVX instruction
VEX.256
Encoding
VEX.128
Encoding
Instruction
Reason Not Promoted
no
yes
AESDEC, AESDECLAST
VI
no
yes
AESENC, AESENCLAST
VI
no
yes
AESIMX, AESKEYGENASSIST
VI
Description of Column “Reason not promoted?”
MMX: Instructions referencing MMX registers do not support VEX
Scalar: Scalar instructions are not promoted to 256-bit
integer: integer instructions are not promoted.
VI: “Vector Integer” instructions are not promoted to 256-bit
14.2.4
Non-Arithmetic Primitives for 128-bit Vector and Scalar Processing
Intel AVX provides a full complement of data processing instructions that employ VEX-prefix encoding. These VEXencoded instructions generally provide the same functionality over instructions operating on XMM register that are
encoded using SIMD prefixes.
A subset of new functionalities listed in Table 14-4 is also extended via VEX.128 encoding. These enhancements in
AVX on 128-bit data processing primitives include 11 new instructions (see Table 14-6) with the following capabilities:
•
Non-unit-strided fetching of SIMD data. AVX provides several flexible SIMD floating-point data fetching
primitives:
— broadcast of single data element into a 128-bit destination,
— masked move primitives to load or store SIMD data elements conditionally,
•
Intra-register manipulation of SIMD data elements. AVX provides several flexible SIMD floating-point data
manipulation primitives:
— permute primitives to facilitate efficient manipulation of floating-point data elements in 128-bit SIMD
registers
•
Branch handling. AVX provides several primitives to enable handling of branches in SIMD programming:
— new variable blend instructions supports four-operand syntax with non-destructive source syntax.
Branching conditions dependent on floating-point data or integer data can benefit from Intel AVX. This is
more flexible than non-VEX encoded instruction syntax that uses the XMM0 register as implied mask for
blend selection. While variable blend with implied XMM0 syntax is supported in SSE4 using SIMD prefix
encoding, VEX-encoded 128-bit variable blend instructions only support the more flexible four-operand
syntax.
— Packed TEST instructions for floating-point data.
Table 14-6. 128-bit AVX Instruction Enhancement
Instruction
Description
VBROADCASTSS xmm1, m32
Broadcast single-precision floating-point element in mem to four locations in xmm1.
VMASKMOVPS xmm1, xmm2, m128
Load packed single-precision values from mem using mask in xmm2 and store in xmm1
VMASKMOVPD xmm1, xmm2, m128
Load packed double-precision values from mem using mask in xmm2 and store in xmm1
VMASKMOVPS m128, xmm1, xmm2
Store packed single-precision values from xmm2 using mask in xmm1
VMASKMOVPD m128, xmm1, xmm2
Store packed double-precision values from xmm2 using mask in xmm1
Vol. 1 14-13
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-6. 128-bit AVX Instruction Enhancement
Instruction
Description
VPERMILPD xmm1, xmm2, xmm3/m128
Permute Double-Precision Floating-Point values in xmm2 using controls from xmm3/mem
and store result in xmm1
VPERMILPD xmm1, xmm2/m128, imm8
Permute Double-Precision Floating-Point values in xmm2/mem using controls from imm8
and store result in xmm1
VPERMILPS xmm1, xmm2, xmm3/m128
Permute Single-Precision Floating-Point values in xmm2 using controls from xmm3/mem
and store result in xmm1
VPERMILPS xmm1, xmm2/m128, imm8
Permute Single-Precision Floating-Point values in xmm2/mem using controls from imm8
and store result in xmm1
VTESTPS xmm1, xmm2/m128
Set ZF if xmm2/mem AND xmm1 result is all 0s in packed single-precision sign bits. Set
CF if xmm2/mem AND NOT xmm1 result is all 0s in packed single-precision sign bits.
VTESTPD xmm1, xmm2/m128
Set ZF if xmm2/mem AND xmm1 result is all 0s in packed single precision sign bits. Set CF
if xmm2/mem AND NOT xmm1 result is all 0s in packed double-precision sign bits.
The 128-bit data processing instructions in AVX cover floating-point and integer data movement primitives. Legacy
SIMD non-arithmetic ISA promoted to VEX-256 encoding also support VEX-128 encoding (see Table 14-3). Table
14-7 lists the state of promotion of the remaining legacy SIMD non-arithmetic ISA to VEX-128 encoding.
Table 14-7. Promotion of Legacy SIMD ISA to 128-bit Non-Arithmetic AVX instruction
VEX.256
Encoding
VEX.128
Encoding
Instruction
Reason Not Promoted
no
no
MOVQ2DQ, MOVDQ2Q
MMX
no
yes
LDMXCSR, STMXCSR
no
yes
MOVSS, MOVSD, CMPSS, CMPSD
scalar
no
yes
MOVHPS, MOVHPD
Note 1
no
yes
MOVLPS, MOVLPD
Note 1
no
yes
MOVLHPS, MOVHLPS
Redundant with VPERMILPS
no
yes
MOVQ, MOVD
scalar
no
yes
PACKUSWB, PACKSSDW, PACKSSWB
VI
no
yes
PUNPCKHBW, PUNPCKHWD
VI
no
yes
PUNPCKLBW, PUNPCKLWD
VI
no
yes
PUNPCKHDQ, PUNPCKLDQ
VI
no
yes
PUNPCKLQDQ, PUNPCKHQDQ
VI
no
yes
PSHUFHW, PSHUFLW, PSHUFD
VI
no
yes
PMOVMSKB, MASKMOVDQU
VI
no
yes
PAND, PANDN, POR, PXOR
VI
no
yes
PINSRW, PEXTRW,
VI
CPUID.SSSE3
no
yes
PALIGNR, PSHUFB
VI
no
yes
EXTRACTPS, INSERTPS
Note 3
no
yes
PACKUSDW, PCMPEQQ
VI
CPUID.SSE4_1
14-14 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-7. Promotion of Legacy SIMD ISA to 128-bit Non-Arithmetic AVX instruction
VEX.256
Encoding
VEX.128
Encoding
Instruction
Reason Not Promoted
no
yes
PBLENDVB, PBLENDW
VI
no
yes
PEXTRW, PEXTRB, PEXTRD, PEXTRQ
VI
no
yes
PINSRB, PINSRD, PINSRQ
VI
Description of Column “Reason not promoted?”
MMX: Instructions referencing MMX registers do not support VEX
Scalar: Scalar instructions are not promoted to 256-bit
VI: “Vector Integer” instructions are not promoted to 256-bit
Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided by
VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension
Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF128 would be better than promoting
INSERTPS to 256-bit (for example).
14.3
DETECTION OF AVX INSTRUCTIONS
Intel AVX instructions operate on the 256-bit YMM register state. Application detection of new instruction extensions operating on the YMM state follows the general procedural flow in Figure 14-2.
Prior to using AVX, the application must identify that the operating system supports the XGETBV instruction, the
YMM register state, in addition to processor’s support for YMM state management using XSAVE/XRSTOR and AVX
instructions. The following simplified sequence accomplishes both and is strongly recommended.
1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1)
2) Issue XGETBV and verify that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).
3) detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).
(Step 3 can be done in any order relative to 1 and 2)
Check feature flag
CPUID.1H:ECX.OSXSAVE = 1?
Yes
OS provides processor
extended state management
Implied HW support for
XSAVE, XRSTOR, XGETBV, XCR0
Check enabled state in
XCR0 via XGETBV
State
enabled
Check feature flag
for Instruction set
ok to use
Instructions
Figure 14-2. General Procedural Flow of Application Detection of AVX
1. If CPUID.01H:ECX.OSXSAVE reports 1, it also indirectly implies the processor supports XSAVE, XRSTOR, XGETBV, processor
extended state bit vector XCR0. Thus an application may streamline the checking of CPUID feature flags for XSAVE and OSXSAVE.
XSETBV is a privileged instruction.
Vol. 1 14-15
PROGRAMMING WITH AVX, FMA AND AVX2
The following pseudocode illustrates this recommended application AVX detection process:
Example 14-1. Detection of AVX Instruction
INT supports_AVX()
{ mov
eax, 1
cpuid
and
ecx, 018000000H
cmp
ecx, 018000000H; check both OSXSAVE and AVX feature flags
jne
not_supported
; processor supports AVX instructions and XGETBV is enabled by OS
mov
ecx, 0; specify 0 for XCR0 register
XGETBV
; result in EDX:EAX
and
eax, 06H
cmp
eax, 06H; check OS has enabled both XMM and YMM state support
jne
not_supported
mov
eax, 1
jmp
done
NOT_SUPPORTED:
mov
eax, 0
done:
}
Note: It is unwise for an application to rely exclusively on CPUID.1:ECX.AVX[bit 28] or at all on
CPUID.1:ECX.XSAVE[bit 26]: These indicate hardware support but not operating system support. If YMM state
management is not enabled by an operating systems, AVX instructions will #UD regardless of
CPUID.1:ECX.AVX[bit 28]. “CPUID.1:ECX.XSAVE[bit 26] = 1” does not guarantee the OS actually uses the XSAVE
process for state management.
These steps above also apply to enhanced 128-bit SIMD floating-pointing instructions in AVX (using VEX prefixencoding) that operate on the YMM states.
14-16 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
14.3.1
Detection of VEX-Encoded AES and VPCLMULQDQ
VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate on YMM
states. The detection sequence must combine checking for CPUID.1:ECX.AES[bit 25] = 1 and the sequence for
detection application support for AVX.
Example 14-2. Detection of VEX-Encoded AESNI Instructions
INT supports_VAESNI()
{ mov
eax, 1
cpuid
and
ecx, 01A000000H
cmp
ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags
jne
not_supported
; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS
mov
ecx, 0; specify 0 for XCR0 register
XGETBV
; result in EDX:EAX
and
eax, 06H
cmp
eax, 06H; check OS has enabled both XMM and YMM state support
jne
not_supported
mov
eax, 1
jmp
done
NOT_SUPPORTED:
mov
eax, 0
done:
Similarly, the detection sequence for VPCLMULQDQ must combine checking for CPUID.1:ECX.PCLMULQDQ[bit 1] =
1 and the sequence for detection application support for AVX.
This is shown in the pseudocode:
Example 14-3. Detection of VEX-Encoded AESNI Instructions
INT supports_VPCLMULQDQ)
{ mov
eax, 1
cpuid
and
ecx, 018000002H
cmp
ecx, 018000002H; check OSXSAVE AVX and PCLMULQDQ feature flags
jne
not_supported
; processor supports AVX and VEX-encoded PCLMULQDQ and XGETBV is enabled by OS
mov
ecx, 0; specify 0 for XCR0 register
XGETBV
; result in EDX:EAX
and
eax, 06H
cmp
eax, 06H; check OS has enabled both XMM and YMM state support
jne
not_supported
mov
eax, 1
jmp
done
NOT_SUPPORTED:
mov
eax, 0
done:
Vol. 1 14-17
PROGRAMMING WITH AVX, FMA AND AVX2
14.4
HALF-PRECISION FLOATING-POINT CONVERSION
VCVTPH2PS and VCVTPS2PH are two instructions supporting half-precision floating-point data type conversion to
and from single-precision floating-point data types.
Half-precision floating-point values are not used by the processor directly for arithmetic operations. But the conversion operation are subject to SIMD floating-point exceptions.
Additionally, The conversion operations of VCVTPS2PH allow programmer to specify rounding control using control
fields in an immediate byte. The effects of the immediate byte are listed in Table 14-8.
Rounding control can use Imm[2] to select an override RC field specified in Imm[1:0] or use MXCSR setting.
Table 14-8. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions
Bits
Field Name/value
Description
Imm[1:0]
RC=00B
Round to nearest even
RC=01B
Round down
RC=10B
Round up
RC=11B
Truncate
MS1=0
Use imm[1:0] for rounding
MS1=1
Use MXCSR.RC for rounding
Ignored
Ignored by processor
Imm[2]
Imm[7:3]
Comment
If Imm[2] = 0
Ignore MXCSR.RC
Specific SIMD floating-point exceptions that can occur in conversion operations are shown in Table 14-9 and
Table 14-10.
Table 14-9. Non-Numerical Behavior for VCVTPH2PS, VCVTPS2PH
Source Operands
Masked Result
Unmasked Result
QNaN
QNaN11
QNaN11 (not an exception)
SNaN
QNaN12
None
NOTES:
1. The half precision output QNaN1 is created from the single precision input QNaN as follows: the sign bit is preserved, the 8-bit exponent FFH is replaced by the 5-bit exponent 1FH, and the 24-bit significand is truncated to an 11-bit significand by removing its 14
least significant bits.
2. The half precision output QNaN1 is created from the single precision input SNaN as follows: the sign bit is preserved, the 8-bit exponent FFH is replaced by the 5-bit exponent 1FH, and the 24-bit significand is truncated to an 11-bit significand by removing its 14
least significant bits. The second most significant bit of the significand is changed from 0 to 1 to convert the signaling NaN into a quiet
NaN.
Table 14-10. Invalid Operation for VCVTPH2PS, VCVTPS2PH
Instruction
Condition
Masked Result
Unmasked Result
VCVTPH2PS
SRC = NaN
See Table 14-9
#I=1
VCVTPS2PH
SRC = NaN
See Table 14-9
#I=1
VCVTPS2PH can cause denormal exceptions if the value of the source operand is denormal relative to the numerical range represented by the source format (see Table 14-11).
14-18 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-11. Denormal Condition Summary
Instruction
Condition
Masked Result
Unmasked Result
VCVTPH2PS
SRC is denormal relative to
input format
res = Result rounded to the destination precision and
using the bounded exponent, but only if no unmasked
post-computation exception occurs.
#DE unchanged
Same as masked result.
VCVTPS2PH
SRC is denormal relative to
input format
res = Result rounded to the destination precision and
using the bounded exponent, but only if no unmasked
post-computation exception occurs.
#DE=1
#DE=1
VCVTPS2PH can cause an underflow exception if the result of the conversion is less than the underflow threshold
for half-precision floating-point data type , i.e. | x | < 1.0 ∗ 2−14.
Table 14-12. Underflow Condition for VCVTPS2PH
Instruction
VCVTPS2PH
Condition
Result < smallest destination
precision final normal value2
Masked Result1
Unmasked Result
Result = +0 or -0, denormal, normal.
#UE =1.
#PE = 1 if the result is inexact.
#UE=1,
#PE = 1 if the result is
inexact.
NOTES:
1. Masked and unmasked results are shown in Table 14-11.
2. MXCSR.FTZ is ignored, the processor behaves as if MXCSR.FTZ = 0.
VCVTPS2PH can cause an overflow exception if the result of the conversion is greater than the maximum representable value for half-precision floating-point data type, i.e. | x | ≥ 1.0 ∗ 216.
Table 14-13. Overflow Condition for VCVTPS2PH
Instruction
VCVTPS2PH
Condition
Result ≥ largest destination
precision finial normal value1
Masked Result
Unmasked Result
Result = +Inf or -Inf.
#OE=1.
#OE=1.
VCVTPS2PH can cause an inexact exception if the result of the conversion is not exactly representable in the
destination format.
Table 14-14. Inexact Condition for VCVTPS2PH
Instruction
VCVTPS2PH
Condition
The result is not
representable in
the destination
format
Masked Result1
Unmasked Result
res = Result rounded to the destination
precision and using the bounded
exponent, but only if no unmasked
underflow or overflow conditions occur
(this exception can occur in the presence
of a masked underflow or overflow).
#PE=1.
Only if no underflow/overflow condition occurred,
or if the corresponding exceptions are masked:
• Set #OE if masked overflow and set result as
described above for masked overflow.
• Set #UE if masked underflow and set result as
described above for masked underflow.
If neither underflow nor overflow, result equals
the result rounded to the destination precision and
using the bounded exponent set #PE = 1.
NOTES:
1. If a source is denormal relative to input format with DM masked and at least one of PM or UM unmasked, then an exception will be
raised with DE, UE and PE set.
Vol. 1 14-19
PROGRAMMING WITH AVX, FMA AND AVX2
14.4.1
Detection of F16C Instructions
Application using float 16 instruction must follow a detection sequence similar to AVX to ensure:
•
•
•
The OS has enabled YMM state management support,
The processor support AVX as indicated by the CPUID feature flag, i.e. CPUID.01H:ECX.AVX[bit 28] = 1.
The processor support 16-bit floating-point conversion instructions via a CPUID feature flag
(CPUID.01H:ECX.F16C[bit 29] = 1).
Application detection of Float-16 conversion instructions follow the general procedural flow in Figure 14-3.
Check feature flag
CPUID.1H:ECX.OSXSAVE = 1?
OS provides processor
extended state management
Yes
Implied HW support for
XSAVE, XRSTOR, XGETBV, XCR0
Check enabled YMM state in
XCR0 via XGETBV
Check feature flags
State
enabled
for AVX and F16C
ok to use
Instructions
Figure 14-3. General Procedural Flow of Application Detection of Float-16
---------------------------------------------------------------------------------------INT supports_f16c()
{
; result in eax
mov eax, 1
cpuid
and ecx, 038000000H
cmp ecx, 038000000H; check OSXSAVE, AVX, F16C feature flags
jne not_supported
; processor supports AVX,F16C instructions and XGETBV is enabled by OS
mov ecx, 0; specify 0 for XCR0 register
XGETBV; result in EDX:EAX
and eax, 06H
cmp eax, 06H; check OS has enabled both XMM and YMM state support
jne not_supported
mov eax, 1
jmp done
NOT_SUPPORTED:
mov eax, 0
done:
}
------------------------------------------------------------------------------14-20 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
14.5
FUSED-MULTIPLY-ADD (FMA) EXTENSIONS
FMA extensions enhances Intel AVX with high-throughput, arithmetic capabilities covering fused multiply-add,
fused multiply-subtract, fused multiply add/subtract interleave, signed-reversed multiply on fused multiply-add
and multiply-subtract. FMA extensions provide 36 256-bit floating-point instructions to perform computation on
256-bit vectors and additional 128-bit and scalar FMA instructions.
FMA extensions also provide 60 128-bit floating-point instructions to process 128-bit vector and scalar data. The
arithmetic operations cover fused multiply-add, fused multiply-subtract, signed-reversed multiply on fused
multiply-add and multiply-subtract.
Table 14-15. FMA Instructions
Instruction
Description
VFMADD132PD/VFMADD213PD/VFMADD231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Add of Packed Double-Precision Floating-Point
Values
VFMADD132PS/VFMADD213PS/VFMADD231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Add of Packed Single-Precision Floating-Point
Values
VFMADD132SD/VFMADD213SD/VFMADD231SD
xmm0, xmm1, xmm2/m64
Fused Multiply-Add of Scalar Double-Precision Floating-Point
Values
VFMADD132SS/VFMADD213SS/VFMADD231SS
xmm0, xmm1, xmm2/m32
Fused Multiply-Add of Scalar Single-Precision Floating-Point
Values
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Alternating Add/Subtract of Packed DoublePrecision Floating-Point Values
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Alternating Subtract/Add of Packed DoublePrecision Floating-Point Values
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Subtract of Packed Double-Precision FloatingPoint Values
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Multiply-Subtract of Packed Single-Precision FloatingPoint Values
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD
xmm0, xmm1, xmm2/m64
Fused Multiply-Subtract of Scalar Double-Precision FloatingPoint Values
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS
xmm0, xmm1, xmm2/m32
Fused Multiply-Subtract of Scalar Single-Precision FloatingPoint Values
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD
xmm0, xmm1, xmm2/m64
Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS
xmm0, xmm1, xmm2/m32
Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Negative Multiply-Subtract of Packed Double-Precision
Floating-Point Values
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256
Fused Negative Multiply-Subtract of Packed Single-Precision
Floating-Point Values
Vol. 1 14-21
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-15. FMA Instructions
Instruction
Description
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD
xmm0, xmm1, xmm2/m64
Fused Negative Multiply-Subtract of Scalar Double-Precision
Floating-Point Values
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS
xmm0, xmm1, xmm2/m32
Fused Negative Multiply-Subtract of Scalar Single-Precision
Floating-Point Values
14.5.1
FMA Instruction Operand Order and Arithmetic Behavior
FMA instruction mnemonics are defined explicitly with an ordered three digits, e.g. VFMADD132PD. The value of
each digit refers to the ordering of the three source operand as defined by instruction encoding specification:
•
•
•
‘1’: The first source operand (also the destination operand) in the syntactical order listed in this specification.
‘2’: The second source operand in the syntactical order. This is a YMM/XMM register, encoded using VEX prefix.
‘3’: The third source operand in the syntactical order. The first and third operand are encoded following ModR/M
encoding rules.
The ordering of each digit within the mnemonic refers to the floating-point data listed on the right-hand side of the
arithmetic equation of each FMA operation (see Table 14-17):
•
The first position in the three digits of a FMA mnemonic refers to the operand position of the first FP data
expressed in the arithmetic equation of FMA operation, the multiplicand.
•
The second position in the three digits of a FMA mnemonic refers to the operand position of the second FP data
expressed in the arithmetic equation of FMA operation, the multiplier.
•
The third position in the three digits of a FMA mnemonic refers to the operand position of the FP data being
added/subtracted to the multiplication result.
Note the non-numerical result of an FMA operation does not resemble the mathematically-defined commutative
property between the multiplicand and the multiplier values (see Table 14-17). Consequently, software tools (such
as an assembler) may support a complementary set of FMA mnemonics for each FMA instruction for ease of
programming to take advantage of the mathematical property of commutative multiplications. For example, an
assembler may optionally support the complementary mnemonic “VFMADD312PD” in addition to the true
mnemonic “VFMADD132PD“. The assembler will generate the same instruction opcode sequence corresponding to
VFMADD132PD. The processor executes VFMADD132PD and report any NAN conditions based on the definition of
VFMADD132PD. Similarly, if the complementary mnemonic VFMADD123PD is supported by an assembler at source
level, it must generate the opcode sequence corresponding to VFMADD213PD; the complementary mnemonic
VFMADD321PD must produce the opcode sequence defined by VFMADD231PD. In the absence of FMA operations
reporting a NAN result, the numerical results of using either mnemonic with an assembler supporting both
mnemonics will match the behavior defined in Table 14-17. Support for the complementary FMA mnemonics by
software tools is optional.
14.5.2
Fused-Multiply-ADD (FMA) Numeric Behavior
FMA instructions can perform fused-multiply-add operations (including fused-multiply-subtract, and other varieties) on packed and scalar data elements in the instruction operands. Separate FMA instructions are provided to
handle different types of arithmetic operations on the three source operands.
FMA instruction syntax is defined using three source operands and the first source operand is updated based on the
result of the arithmetic operations of the data elements of 128-bit or 256-bit operands, i.e. The first source operand
is also the destination operand.
The arithmetic FMA operation performed in an FMA instruction takes one of several forms, r=(x*y)+z, r=(x*y)-z,
r=-(x*y)+z, or r=-(x*y)-z. Packed FMA instructions can perform eight single-precision FMA operations or four
double-precision FMA operations with 256-bit vectors.
Scalar FMA instructions only perform one arithmetic operation on the low order data element. The content of the
rest of the data elements in the lower 128-bits of the destination operand is preserved. the upper 128bits of the
destination operand are filled with zero.
14-22 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
An arithmetic FMA operation of the form, r=(x*y)+z, takes two IEEE-754-2008 single (double) precision values
and multiplies them to form an infinite precision intermediate value. This intermediate value is added to a third
single (double) precision value (also at infinite precision) and rounded to produce a single (double) precision result.
The rounding and exception behavior are controlled by the MXCSR and control bits specified in lower 4-bits of the
8-bit immediate field (imm8). See Figure 14-4.
7
3
4
source register
specifier
S
2
O
1
0
RC
00: Nearest
01: Down / toward -INF
10: Up / toward +INF
11: truncate
0: use MXCSR:RC
1: use IMM8[1:0]
Suppress all FMA exceptions
1: Suppress FMA exception signaling and reporting
0: Honor MXCSR for FMA Exceptions
Figure 14-4. Immediate Byte for FMA instructions
Note: The imm8[7:4] specify one of the source register and is explained in detail in later sections.
If imm8[2] = 1 then rounding control mode is selected from imm8[1:0] otherwise rounding control mode is
selected from MXCSR. The imm8[3] bit controls the suppression of SIMD floating-point exception signaling and
reporting. When imm8[3]=1 no SIMD FP exceptions are raised and no flags are updated in MXCSR as a result of
executing the instruction. The numerical result is computed as if all SIMD FP exceptions were masked.
Table 14-17 describes the numerical behavior of the FMA operation, r=(x*y)+z, r=(x*y)-z, r=-(x*y)+z, r=-(x*y)z for various input values. The input values can be 0, finite non-zero (F in Table 14-17), infinity of either sign (INF
in Table 14-17), positive infinity (+INF in Table 14-17), negative infinity (-INF in Table 14-17), or NaN (including
QNaN or SNaN). If any one of the input values is a NAN, the result of FMA operation, r, may be a quietized NAN. The
result can be either Q(x), Q(y), or Q(z), see Table 14-17. If x is a NaN, then:
•
•
Q(x) = x if x is QNaN or
Q(x) = the quietized NaN obtained from x if x is SNaN
The notation for the output value in Table 14-17 are:
•
“+INF”: positive infinity, “-INF”: negative infinity. When the result depends on a conditional expression, both
values are listed in the result column and the condition is described in the comment column.
•
QNaNIndefinite represents the QNaN which has the sign bit equal to 1, the most significand field equal to 1, and
the remaining significand field bits equal to 0.
•
The summation or subtraction of 0s or identical values in FMA operation can lead to the following situations
shown in Table 14-16
•
If the FMA computation represents an invalid operation (e.g. when adding two INF with opposite signs)), the
invalid exception is signaled, and the MXCSR.IE flag is set.
Vol. 1 14-23
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-16. Rounding Behavior of Zero Result in FMA Operation
x*y
z
(x*y) + z
(x*y) - z
- (x*y) + z
- (x*y) - z
(+0)
(+0)
+0 in all rounding modes
- 0 when rounding down,
and +0 otherwise
- 0 when rounding down,
and +0 otherwise
- 0 in all rounding modes
(+0)
(-0)
- 0 when rounding down,
and +0 otherwise
+0 in all rounding modes
- 0 in all rounding modes
- 0 when rounding down,
and +0 otherwise
(-0)
(+0)
- 0 when rounding down,
and +0 otherwise
- 0 in all rounding modes
+ 0 in all rounding modes
- 0 when rounding down,
and +0 otherwise
(-0)
(-0)
- 0 in all rounding modes
- 0 when rounding down,
and +0 otherwise
- 0 when rounding down,
and +0 otherwise
+ 0 in all rounding modes
F
-F
- 0 when rounding down,
and +0 otherwise
2*F
-2*F
- 0 when rounding down,
and +0 otherwise
F
F
2*F
- 0 when rounding down,
and +0 otherwise
- 0 when rounding down,
and +0 otherwise
-2*F
Table 14-17. FMA Numeric Behavior
x
y
(multiplicand)
(multiplier)
NaN
0, F, INF,
NaN
0, F, INF
r=(x*y)
+z
r=(x*y)
-z
r=
-(x*y)+z
r=
-(x*y)-z
0, F,
INF,
NaN
Q(x)
Q(x)
Q(x)
Q(x)
Signal invalid exception if x or y or z is SNaN
NaN
0, F,
INF,
NaN
Q(y)
Q(y)
Q(y)
Q(y)
Signal invalid exception if y or z is SNaN
0, F, INF
0, F, INF
NaN
Q(z)
Q(z)
Q(z)
Q(z)
Signal invalid exception if z is SNaN
INF
F, INF
+IN
F
+INF
QNaNIn
definite
QNaNInd
efinite
-INF
if x*y and z have the same sign
QNaNIn
definite
-INF
+INF
QNaNInd
efinite
if x*y and z have opposite signs
-INF
QNaNIn
definite
QNaNInd
efinite
+INF
if x*y and z have the same sign
QNaNIn
definite
+INF
-INF
QNaNInd
efinite
if x*y and z have opposite signs
+INF
+INF
-INF
-INF
if x and y have the same sign
INF
F, INF
z
-INF
Comment
INF
F, INF
0, F
-INF
-INF
+INF
+INF
if x and y have opposite signs
INF
0
0, F,
INF
QNaNIn
definite
QNaNIn
definite
QNaNInd
efinite
QNaNInd
efinite
Signal invalid exception
0
INF
0, F,
INF
QNaNIn
definite
QNaNIn
definite
QNaNInd
efinite
QNaNInd
efinite
Signal invalid exception
F
INF
+IN
F
+INF
QNaNIn
definite
QNaNInd
efinite
-INF
if x*y and z have the same sign
QNaNIn
definite
-INF
+INF
-INF
QNaNIn
definite
QNaNInd
efinite
+INF
if x*y and z have the same sign
QNaNIn
definite
+INF
-INF
QNaNInd
efinite
if x*y and z have opposite signs
F
F
14-24 Vol. 1
INF
INF
-INF
0,F
QNaNInd
efinite
if x*y and z have opposite signs
+INF
+INF
-INF
-INF
if x * y > 0
-INF
-INF
+INF
+INF
if x * y < 0
PROGRAMMING WITH AVX, FMA AND AVX2
x
y
(multiplicand)
(multiplier)
0,F
0,F
z
INF
r=(x*y)
+z
r=(x*y)
-z
r=
-(x*y)+z
r=
-(x*y)-z
+INF
-INF
+INF
-INF
if z > 0
-INF
+INF
-INF
+INF
if z < 0
The sign of the result depends on the sign of
the operands and on the rounding mode. The
product x*y is +0 or -0, depending on the signs
of x and y. The summation/subtraction of the
zero representing (x*y) and the zero representing z can lead to one of the four cases shown in
Table 14-16.
Comment
0
0
0
0
0
0
0
0
F
0
0
0
0
0
F
0
0
0
0
0
0
0
0
F
z
-z
z
-z
0
F
F
z
-z
z
-z
F
0
F
z
-z
z
-z
F
F
0
x*y
x*y
-x*y
-x*y
Rounded to the destination precision, with
bounded exponent
F
F
F
(x*y)+z
(x*y)-z
-(x*y)+z
-(x*y)-z
Rounded to the destination precision, with
bounded exponent; however, if the exact values
of x*y and z are equal in magnitude with signs
resulting in the FMA operation producing 0, the
rounding behavior described in Table 14-16.
If unmasked floating-point exceptions are signaled (invalid operation, denormal operand, overflow, underflow, or
inexact result) the result register is left unchanged and a floating-point exception handler is invoked.
14.5.3
Detection of FMA
Hardware support for FMA is indicated by CPUID.1:ECX.FMA[bit 12]=1.
Application Software must identify that hardware supports AVX, after that it must also detect support for FMA by
CPUID.1:ECX.FMA[bit 12]. The recommended pseudocode sequence for detection of FMA is:
---------------------------------------------------------------------------------------INT supports_fma()
{
; result in eax
mov eax, 1
cpuid
and ecx, 018001000H
cmp ecx, 018001000H; check OSXSAVE, AVX, FMA feature flags
jne not_supported
; processor supports AVX,FMA instructions and XGETBV is enabled by OS
mov ecx, 0; specify 0 for XCR0 register
XGETBV; result in EDX:EAX
and eax, 06H
cmp eax, 06H; check OS has enabled both XMM and YMM state support
jne not_supported
mov eax, 1
jmp done
NOT_SUPPORTED:
mov eax, 0
Vol. 1 14-25
PROGRAMMING WITH AVX, FMA AND AVX2
done:
}
------------------------------------------------------------------------------Note that FMA comprises 256-bit and 128-bit SIMD instructions operating on YMM states.
14.6
OVERVIEW OF INTEL® ADVANCED VECTOR EXTENSIONS 2 (INTEL® AVX2)
Intel® AVX2 extends Intel AVX by promoting most of the 128-bit SIMD integer instructions with 256-bit numeric
processing capabilities. AVX2 instructions follow the same programming model as AVX instructions.
In addition, AVX2 provide enhanced functionalities for broadcast/permute operations on data elements, vector
shift instructions with variable-shift count per data element, and instructions to fetch non-contiguous data
elements from memory.
14.6.1
AVX2 and 256-bit Vector Integer Processing
AVX2 promotes the vast majority of 128-bit integer SIMD instruction sets to operate with 256-bit wide YMM registers. AVX2 instructions are encoded using the VEX prefix and require the same operating system support as AVX.
Generally, most of the promoted 256-bit vector integer instructions follow the 128-bit lane operation, similar to the
promoted 256-bit floating-point SIMD instructions in AVX.
Newer functionalities in AVX2 generally fall into the following categories:
•
Fetching non-contiguous data elements from memory using vector-index memory addressing. These “gather”
instructions introduce a new memory-addressing form, consisting of a base register and multiple indices
specified by a vector register (either XMM or YMM). Data elements sizes of 32 and 64-bits are supported, and
data types for floating-point and integer elements are also supported.
•
Cross-lane functionalities are provided with several new instructions for broadcast and permute operations.
Some of the 256-bit vector integer instructions promoted from legacy SSE instruction sets also exhibit crosslane behavior, e.g. VPMOVZ/VPMOVS family.
•
AVX2 complements the AVX instructions that are typed for floating-point operation with a full compliment of
equivalent set for operating with 32/64-bit integer data elements.
•
Vector shift instructions with per-element shift count. Data elements sizes of 32 and 64-bits are supported.
14.7
PROMOTED VECTOR INTEGER INSTRUCTIONS IN AVX2
In AVX2, most SSE/SSE2/SSE3/SSSE3/SSE4 vector integer instructions have been promoted to support VEX.256
encodings. Table 14-18 summarizes the promotion status for existing instructions. The column “VEX.128” indicates
whether the instruction using VEX.128 prefix encoding is supported.
The column “VEX.256” indicates whether 256-bit vector form of the instruction using the VEX.256 prefix encoding
is supported, and under which feature flag.
14-26 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-18. Promoted Vector Integer SIMD Instructions in AVX2
VEX.256 Encoding
VEX.128 Encoding
Group
Instruction
AVX2
AVX
YY 0F 6X
PUNPCKLBW
AVX2
AVX
PUNPCKLWD
AVX2
AVX
PUNPCKLDQ
AVX2
AVX
PACKSSWB
AVX2
AVX
PCMPGTB
AVX2
AVX
PCMPGTW
AVX2
AVX
PCMPGTD
AVX2
AVX
PACKUSWB
AVX2
AVX
PUNPCKHBW
AVX2
AVX
PUNPCKHWD
AVX2
AVX
PUNPCKHDQ
AVX2
AVX
PACKSSDW
AVX2
AVX
PUNPCKLQDQ
AVX2
AVX
PUNPCKHQDQ
no
AVX
MOVD
no
AVX
MOVQ
AVX
AVX
MOVDQA
AVX
AVX
MOVDQU
AVX2
AVX
AVX2
AVX
PSHUFHW
AVX2
AVX
PSHUFLW
AVX2
AVX
PCMPEQB
AVX2
AVX
PCMPEQW
AVX2
AVX
PCMPEQD
AVX
AVX
MOVDQA
AVX
AVX
MOVDQU
no
AVX
PINSRW
no
AVX
PEXTRW
AVX2
AVX
PSRLW
AVX2
AVX
PSRLD
AVX2
AVX
PSRLQ
AVX2
AVX
PADDQ
AVX2
AVX
PMULLW
AVX2
AVX
PMOVMSKB
AVX2
AVX
PSUBUSB
AVX2
AVX
PSUBUSW
AVX2
AVX
PMINUB
AVX2
AVX
PAND
YY 0F 7X
PSHUFD
Vol. 1 14-27
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-18. Promoted Vector Integer SIMD Instructions in AVX2
VEX.256 Encoding
VEX.128 Encoding
AVX2
AVX
PADDUSB
AVX2
AVX
PADDUSW
AVX2
AVX
PMAXUB
AVX2
AVX
PANDN
AVX2
AVX
AVX2
AVX
PSRAW
AVX2
AVX
PSRAD
AVX2
AVX
PAVGW
AVX2
AVX
PMULHUW
AVX2
AVX
PMULHW
AVX
AVX
MOVNTDQ
AVX2
AVX
PSUBSB
AVX2
AVX
PSUBSW
AVX2
AVX
PMINSW
AVX2
AVX
POR
AVX2
AVX
PADDSB
AVX2
AVX
PADDSW
AVX2
AVX
PMAXSW
AVX2
AVX
PXOR
AVX
AVX
AVX2
AVX
PSLLW
AVX2
AVX
PSLLD
AVX2
AVX
PSLLQ
AVX2
AVX
PMULUDQ
AVX2
AVX
PMADDWD
AVX2
AVX
PSADBW
AVX2
AVX
PSUBB
AVX2
AVX
PSUBW
AVX2
AVX
PSUBD
AVX2
AVX
PSUBQ
AVX2
AVX
PADDB
AVX2
AVX
PADDW
AVX2
AVX
AVX2
AVX
AVX2
AVX
PHADDSW
AVX2
AVX
PHADDD
AVX2
AVX
PHSUBW
AVX2
AVX
PHSUBSW
14-28 Vol. 1
Group
YY 0F EX
YY 0F FX
Instruction
PAVGB
LDDQU
PADDD
SSSE3
PHADDW
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-18. Promoted Vector Integer SIMD Instructions in AVX2
VEX.256 Encoding
VEX.128 Encoding
Group
Instruction
AVX2
AVX
PHSUBD
AVX2
AVX
PMADDUBSW
AVX2
AVX
PALIGNR
AVX2
AVX
PSHUFB
AVX2
AVX
PMULHRSW
AVX2
AVX
PSIGNB
AVX2
AVX
PSIGNW
AVX2
AVX
PSIGND
AVX2
AVX
PABSB
AVX2
AVX
PABSW
AVX2
AVX
PABSD
AVX2
AVX
MOVNTDQA
AVX2
AVX
MPSADBW
AVX2
AVX
PACKUSDW
AVX2
AVX
PBLENDVB
AVX2
AVX
PBLENDW
AVX2
AVX
PCMPEQQ
no
AVX
PEXTRD
no
AVX
PEXTRQ
no
AVX
PEXTRB
no
AVX
PEXTRW
no
AVX
PHMINPOSUW
no
AVX
PINSRB
no
AVX
PINSRD
no
AVX
PINSRQ
AVX2
AVX
PMAXSB
AVX2
AVX
PMAXSD
AVX2
AVX
PMAXUD
AVX2
AVX
PMAXUW
AVX2
AVX
PMINSB
AVX2
AVX
PMINSD
AVX2
AVX
PMINUD
AVX2
AVX
PMINUW
AVX2
AVX
PMOVSXxx
AVX2
AVX
PMOVZXxx
AVX2
AVX
PMULDQ
AVX2
AVX
PMULLD
AVX
AVX
PTEST
Vol. 1 14-29
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-18. Promoted Vector Integer SIMD Instructions in AVX2
VEX.256 Encoding
VEX.128 Encoding
Group
Instruction
AVX2
AVX
SSE4.2
PCMPGTQ
no
AVX
PCMPESTRI
no
AVX
PCMPESTRM
no
AVX
PCMPISTRI
no
AVX
no
AVX
no
AVX
AESDECLAST
no
AVX
AESENC
no
AVX
AESECNLAST
no
AVX
AESIMC
no
AVX
AESKEYGENASSIST
no
AVX
PCMPISTRM
AESNI
CLMUL
AESDEC
PCLMULQDQ
Table 14-19 compares complementary SIMD functionalities introduced in AVX and AVX2. instructions.
Table 14-19. VEX-Only SIMD Instructions in AVX and AVX2
AVX2
AVX
Comment
VBROADCASTI128
VBROADCASTF128
256-bit only
VBROADCASTSD ymm1, xmm
VBROADCASTSD ymm1, m64
256-bit only
VBROADCASTSS (from xmm)
VBROADCASTSS (from m32)
VEXTRACTI128
VEXTRACTF128
256-bit only
VINSERTI128
VINSERTF128
256-bit only
VPMASKMOVD
VMASKMOVPS
VPMASKMOVQ!
VMASKMOVPD
VPERM2I128
VPERMILPD
in-lane
VPERMILPS
in-lane
VPERM2F128
256-bit only
VPERMD
cross-lane
VPERMPS
cross-lane
VPERMQ
cross-lane
VPERMPD
cross-lane
VTESTPD
VTESTPS
14-30 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-19. VEX-Only SIMD Instructions in AVX and AVX2
AVX2
AVX
Comment
VPBLENDD
VPSLLVD/Q
VPSRAVD
VPSRLVD/Q
VGATHERDPD/QPD
VGATHERDPS/QPS
VPGATHERDD/QD
VPGATHERDQ/QQ
Table 14-20. New Primitive in AVX2 Instructions
Instruction
Description
VPERMD ymm1, ymm2, ymm3/m256
Permute doublewords in ymm3/m256 using indexes in ymm2 and store the result in ymm1.
VPERMPD ymm1, ymm2/m256, imm8
Permute double-precision FP elements in ymm2/m256 using indexes in imm8 and store the
result in ymm1.
VPERMPS ymm1, ymm2, ymm3/m256
Permute single-precision FP elements in ymm3/m256 using indexes in ymm2 and store the
result in ymm1.
VPERMQ ymm1, ymm2/m256, imm8
Permute quadwords in ymm2/m256 using indexes in imm8 and store the result in ymm1.
VPSLLVD xmm1, xmm2, xmm3/m128
Shift doublewords in xmm2 left by amount specified in the corresponding element of
xmm3/m128 while shifting in 0s.
VPSLLVQ xmm1, xmm2, xmm3/m128
Shift quadwords in xmm2 left by amount specified in the corresponding element of
xmm3/m128 while shifting in 0s.
VPSLLVD ymm1, ymm2, ymm3/m256
Shift doublewords in ymm2 left by amount specified in the corresponding element of
ymm3/m256 while shifting in 0s.
VPSLLVQ ymm1, ymm2, ymm3/m256
Shift quadwords in ymm2 left by amount specified in the corresponding element of
ymm3/m256 while shifting in 0s.
VPSRAVD xmm1, xmm2, xmm3/m128
Shift doublewords in xmm2 right by amount specified in the corresponding element of
xmm3/m128 while shifting in the sign bits.
VPSRLVD xmm1, xmm2, xmm3/m128
Shift doublewords in xmm2 right by amount specified in the corresponding element of
xmm3/m128 while shifting in 0s.
VPSRLVQ xmm1, xmm2, xmm3/m128
Shift quadwords in xmm2 right by amount specified in the corresponding element of
xmm3/m128 while shifting in 0s.
VPSRLVD ymm1, ymm2, ymm3/m256
Shift doublewords in ymm2 right by amount specified in the corresponding element of
ymm3/m256 while shifting in 0s.
VPSRLVQ ymm1, ymm2, ymm3/m256
Shift quadwords in ymm2 right by amount specified in the corresponding element of
ymm3/m256 while shifting in 0s.
VGATHERDD xmm1, vm32x, xmm2
Using dword indices specified in vm32x, gather dword values from memory conditioned on
mask specified by xmm2. Conditionally gathered elements are merged into xmm1.
VGATHERQD xmm1, vm64x, xmm2
Using qword indices specified in vm64x, gather dword values from memory conditioned on
mask specified by xmm2. Conditionally gathered elements are merged into xmm1.
VGATHERDD ymm1, vm32y, ymm2
Using dword indices specified in vm32y, gather dword values from memory conditioned on
mask specified by ymm2. Conditionally gathered elements are merged into ymm1.
VGATHERQD ymm1, vm64y, ymm2
Using qword indices specified in vm64y, gather dword values from memory conditioned on
mask specified by ymm2. Conditionally gathered elements are merged into ymm1.
Vol. 1 14-31
PROGRAMMING WITH AVX, FMA AND AVX2
Instruction
Description
VGATHERDPD xmm1, vm32x, xmm2
Using dword indices specified in vm32x, gather double-precision FP values from memory
conditioned on mask specified by xmm2. Conditionally gathered elements are merged into
xmm1.
VGATHERQPD xmm1, vm64x, xmm2
Using qword indices specified in vm64x, gather double-precision FP values from memory
conditioned on mask specified by xmm2. Conditionally gathered elements are merged into
xmm1.
VGATHERDPD ymm1, vm32x, ymm2
Using dword indices specified in vm32x, gather double-precision FP values from memory
conditioned on mask specified by ymm2. Conditionally gathered elements are merged into
ymm1.
VGATHERQPD ymm1, vm64y ymm2
Using qword indices specified in vm64y, gather double-precision FP values from memory
conditioned on mask specified by ymm2. Conditionally gathered elements are merged into
ymm1.
VGATHERDPS xmm1, vm32x, xmm2
Using dword indices specified in vm32x, gather single-precision FP values from memory
conditioned on mask specified by xmm2. Conditionally gathered elements are merged into
xmm1.
VGATHERQPS xmm1, vm64x, xmm2
Using qword indices specified in vm64x, gather single-precision FP values from memory
conditioned on mask specified by xmm2. Conditionally gathered elements are merged into
xmm1.
VGATHERDPS ymm1, vm32y, ymm2
Using dword indices specified in vm32y, gather single-precision FP values from memory
conditioned on mask specified by ymm2. Conditionally gathered elements are merged into
ymm1.
VGATHERQPS ymm1, vm64y, ymm2
Using qword indices specified in vm64y, gather single-precision FP values from memory
conditioned on mask specified by ymm2. Conditionally gathered elements are merged into
ymm1.
VGATHERDQ xmm1, vm32x, xmm2
Using dword indices specified in vm32x, gather qword values from memory conditioned on
mask specified by xmm2. Conditionally gathered elements are merged into xmm1.
VGATHERQQ xmm1, vm64x, xmm2
Using qword indices specified in vm64x, gather qword values from memory conditioned on
mask specified by xmm2. Conditionally gathered elements are merged into xmm1.
VGATHERDQ ymm1, vm32x, ymm2
Using dword indices specified in vm32x, gather qword values from memory conditioned on
mask specified by ymm2. Conditionally gathered elements are merged into ymm1.
VGATHERQQ ymm1, vm64y, ymm2
Using qword indices specified in vm64y, gather qword values from memory conditioned on
mask specified by ymm2. Conditionally gathered elements are merged into ymm1.
14.7.1
Detection of AVX2
Hardware support for AVX2 is indicated by CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]=1.
Application Software must identify that hardware supports AVX, after that it must also detect support for AVX2 by
checking CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]. The recommended pseudocode sequence for detection of
AVX2 is:
---------------------------------------------------------------------------------------INT supports_avx2()
{
; result in eax
mov eax, 1
cpuid
and ecx, 018000000H
cmp ecx, 018000000H; check both OSXSAVE and AVX feature flags
jne not_supported
; processor supports AVX instructions and XGETBV is enabled by OS
mov eax, 7
14-32 Vol. 1
PROGRAMMING WITH AVX, FMA AND AVX2
mov ecx, 0
cpuid
and ebx, 20H
cmp ebx, 20H; check AVX2 feature flags
jne not_supported
mov ecx, 0; specify 0 for XCR0 register
XGETBV; result in EDX:EAX
and eax, 06H
cmp eax, 06H; check OS has enabled both XMM and YMM state support
jne not_supported
mov eax, 1
jmp done
NOT_SUPPORTED:
mov eax, 0
done:
}
-------------------------------------------------------------------------------
14.8
ACCESSING YMM REGISTERS
The lower 128 bits of a YMM register is aliased to the corresponding XMM register. Legacy SSE instructions (i.e.
SIMD instructions operating on XMM state but not using the VEX prefix, also referred to non-VEX encoded SIMD
instructions) will not access the upper bits (255:128) of the YMM registers. AVX and FMA instructions with a VEX
prefix and vector length of 128-bits zeroes the upper 128 bits of the YMM register.
Upper bits of YMM registers (255:128) can be read and written by many instructions with a VEX.256 prefix.
XSAVE and XRSTOR may be used to save and restore the upper bits of the YMM registers.
14.9
MEMORY ALIGNMENT
Memory alignment requirements on VEX-encoded instruction differs from non-VEX-encoded instructions. Memory
alignment applies to non-VEX-encoded SIMD instructions in three categories:
•
Explicitly-aligned SIMD load and store instructions accessing 16 bytes of memory (e.g. MOVAPD, MOVAPS,
MOVDQA, etc.). These instructions always require memory address to be aligned on 16-byte boundary.
•
Explicitly-unaligned SIMD load and store instructions accessing 16 bytes or less of data from memory (e.g.
MOVUPD, MOVUPS, MOVDQU, MOVQ, MOVD, etc.). These instructions do not require memory address to be
aligned on 16-byte boundary.
•
The vast majority of arithmetic and data processing instructions in legacy SSE instructions (non-VEX-encoded
SIMD instructions) support memory access semantics. When these instructions access 16 bytes of data from
memory, the memory address must be aligned on 16-byte boundary.
Most arithmetic and data processing instructions encoded using the VEX prefix and performing memory accesses
have more flexible memory alignment requirements than instructions that are encoded without the VEX prefix.
Specifically,
•
With the exception of explicitly aligned 16 or 32 byte SIMD load/store instructions, most VEX-encoded,
arithmetic and data processing instructions operate in a flexible environment regarding memory address
alignment, i.e. VEX-encoded instruction with 32-byte or 16-byte load semantics will support unaligned load
operation by default. Memory arguments for most instructions with VEX prefix operate normally without
Vol. 1 14-33
PROGRAMMING WITH AVX, FMA AND AVX2
causing #GP(0) on any byte-granularity alignment (unlike Legacy SSE instructions). The instructions that
require explicit memory alignment requirements are listed in Table 14-22.
Software may see performance penalties when unaligned accesses cross cacheline boundaries, so reasonable
attempts to align commonly used data sets should continue to be pursued.
Atomic memory operation in Intel 64 and IA-32 architecture is guaranteed only for a subset of memory operand
sizes and alignment scenarios. The list of guaranteed atomic operations are described in Section 8.1.1 of IA-32
Intel® Architecture Software Developer’s Manual, Volumes 3A. AVX and FMA instructions do not introduce any new
guaranteed atomic memory operations.
AVX instructions can generate an #AC(0) fault on misaligned 4 or 8-byte memory references in Ring-3 when
CR0.AM=1. 16 and 32-byte memory references will not generate #AC(0) fault. See Table 14-21 for details.
Certain AVX instructions always require 16- or 32-byte alignment (see the complete list of such instructions in
Table 14-22). These instructions will #GP(0) if not aligned to 16-byte boundaries (for 16-byte granularity loads and
stores) or 32-byte boundaries (for 32-byte loads and stores).
Table 14-21. Alignment Faulting Conditions when Memory Access is Not Aligned
AVX, FMA,
SSE
Instruction Type
EFLAGS.AC==1 && Ring-3 && CR0.AM == 1
16- or 32-byte “explicitly unaligned” loads and stores (see Table
14-23)
0
1
no fault
no fault
VEX op YMM, m256
no fault
no fault
VEX op XMM, m128
no fault
no fault
“explicitly aligned” loads and stores (see Table 14-22)
#GP(0)
#GP(0)
2, 4, or 8-byte loads and stores
no fault
#AC(0)
16 byte “explicitly unaligned” loads and stores (see Table 14-23)
no fault
no fault
op XMM, m128
#GP(0)
#GP(0)
“explicitly aligned” loads and stores (see Table 14-22)
#GP(0)
#GP(0)
2, 4, or 8-byte loads and stores
no fault
#AC(0)
Table 14-22. Instructions Requiring Explicitly Aligned Memory
14-34 Vol. 1
Require 16-byte alignment
Require 32-byte alignment
(V)MOVDQA xmm, m128
VMOVDQA ymm, m256
(V)MOVDQA m128, xmm
VMOVDQA m256, ymm
(V)MOVAPS xmm, m128
VMOVAPS ymm, m256
(V)MOVAPS m128, xmm
VMOVAPS m256, ymm
(V)MOVAPD xmm, m128
VMOVAPD ymm, m256
(V)MOVAPD m128, xmm
VMOVAPD m256, ymm
(V)MOVNTPS m128, xmm
VMOVNTPS m256, ymm
(V)MOVNTPD m128, xmm
VMOVNTPD m256, ymm
(V)MOVNTDQ m128, xmm
VMOVNTDQ m256, ymm
(V)MOVNTDQA xmm, m128
VMOVNTDQA ymm, m256
PROGRAMMING WITH AVX, FMA AND AVX2
Table 14-23. Instructions Not Requiring Explicit Memory Alignment
(V)MOVDQU xmm, m128
(V)MOVDQU m128, m128
(V)MOVUPS xmm, m128
(V)MOVUPS m128, xmm
(V)MOVUPD xmm, m128
(V)MOVUPD m128, xmm
VMOVDQU ymm, m256
VMOVDQU m256, ymm
VMOVUPS ymm, m256
VMOVUPS m256, ymm
VMOVUPD ymm, m256
VMOVUPD m256, ymm
14.10
SIMD FLOATING-POINT EXCEPTIONS
AVX instructions can generate SIMD floating-point exceptions (#XM) and respond to exception masks in the same
way as Legacy SSE instructions. When CR4.OSXMMEXCPT=0 any unmasked FP exceptions generate an Undefined
Opcode exception (#UD).
AVX FP exceptions are created in a similar fashion (differing only in number of elements) to Legacy SSE and SSE2
instructions capable of generating SIMD floating-point exceptions.
AVX introduces no new arithmetic operations (AVX floating-point are analogues of existing Legacy SSE instructions).
F16C, FMA instructions can generate SIMD floating-point exceptions (#XM). The requirement that apply to AVX
also apply to F16C and FMA.
The subset of AVX2 instructions that operate on floating-point data do not generate #XM.
The detailed exception conditions for AVX instructions and legacy SIMD instructions (excluding instructions that
operates on MMX registers) are described in a number of exception class types, depending on the operand syntax
and memory operation characteristics. The complete list of SIMD instruction exception class types are defined in
Chapter 2, “Instruction Format,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
14.11
EMULATION
Setting the CR0.EMbit to 1 provides a technique to emulate Legacy SSE floating-point instruction sets in software.
This technique is not supported with AVX instructions.
If an operating system wishes to emulate AVX instructions, set XCR0[2:1] to zero. This will cause AVX instructions
to #UD. Emulation of F16C, AVX2, and FMA by operating system can be done similarly as with emulating AVX
instructions.
14.12
WRITING AVX FLOATING-POINT EXCEPTION HANDLERS
AVX and FMA floating-point exceptions are handled in an entirely analogous way to Legacy SSE floating-point
exceptions. To handle unmasked SIMD floating-point exceptions, the operating system or executive must provide
an exception handler. The section titled “SSE and SSE2 SIMD Floating-Point Exceptions” in Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2),” describes the SIMD floating-point exception classes and gives
suggestions for writing an exception handler to handle them.
Vol. 1 14-35
PROGRAMMING WITH AVX, FMA AND AVX2
To indicate that the operating system provides a handler for SIMD floating-point exceptions (#XM), the CR4.OSXMMEXCPT flag (bit 10) must be set.
The guidelines for writing AVX floating-point exception handlers also apply to F16C and FMA.
14.13
GENERAL PURPOSE INSTRUCTION SET ENHANCEMENTS
Enhancements in the general-purpose instruction set consist of several categories:
•
A rich collection of instructions to manipulate integer data at bit-granularity. Most of the bit-manipulation
instructions employ VEX-prefix encoding to support three-operand syntax with non-destructive source
operands. Two of the bit-manipulating instructions (LZCNT, TZCNT) are not encoded using VEX. The VEXencoded bit-manipulation instructions include: ANDN, BEXTR, BLSI, BLSMSK, BLSR, BZHI, PEXT, PDEP, SARX,
SHLX, SHRX, and RORX.
•
Enhanced integer multiply instruction (MULX) in conjunctions with some of the bit-manipulation instructions
allow software to accelerate calculation of large integer numerics (wider than 128-bits).
•
INVPCID instruction targets system software that manages processor context IDs.
14-36 Vol. 1
CHAPTER 15
PROGRAMMING WITH INTEL® AVX-512
15.1
OVERVIEW
The Intel AVX-512 family comprises of a collection of instruction set extensions, including AVX-512 Foundation,
AVX-512 Exponential and Reciprocal instructions, AVX-512 Conflict, AVX-512 Prefetch, and additional 512-bit
SIMD instruction extensions. Intel AVX-512 instructions are natural extensions to Intel AVX and Intel AVX2. Intel
AVX-512 introduces the following architectural enhancements:
•
Support for 512-bit wide vectors and SIMD register set. 512-bit register state is managed by the operating
system using XSAVE/XRSTOR instructions introduced in 45 nm Intel 64 processors (see Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2B, and Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A).
•
Support for 16 new, 512-bit SIMD registers (for a total of 32 SIMD registers, ZMM0 through ZMM31) in 64-bit
mode. The extra 16 registers state is managed by the operating system using XSAVE/XRSTOR/XSAVEOPT.
•
Support for 8 new opmask registers (k0 through k7) used for conditional execution and efficient merging of
destination operands. The opmask register state is managed by the operating system using the
XSAVE/XRSTOR/XSAVEOPT instructions.
•
A new encoding prefix (referred to as EVEX) to support additional vector length encoding up to 512 bits. The
EVEX prefix builds upon the foundations of the VEX prefix to provide compact, efficient encoding for functionality available to VEX encoding plus the following enhanced vector capabilities:
•
•
•
•
15.1.1
Opmasks.
Embedded broadcast.
Instruction prefix-embedded rounding control.
Compressed address displacements.
512-Bit Wide SIMD Register Support
Intel AVX-512 instructions support 512-bit wide SIMD registers (ZMM0-ZMM31). The lower 256-bits of the ZMM
registers are aliased to the respective 256-bit YMM registers and the lower 128-bit are aliased to the respective
128-bit XMM registers.
15.1.2
32 SIMD Register Support
Intel AVX-512 instructions also support 32 SIMD registers in 64-bit mode (XMM0-XMM31, YMM0-YMM31 and
ZMM0-ZMM31). The number of available vector registers in 32-bit mode is still 8.
15.1.3
Eight Opmask Register Support
Intel AVX-512 instructions support 8 opmask registers (k0-k7). The width of each opmask register is architecturally defined as size MAX_KL (64 bits). Seven of the eight opmask registers (k1-k7) can be used in conjunction with
EVEX-encoded AVX-512 Foundation instructions to provide conditional execution and efficient merging of data
elements in the destination operand. The encoding of opmask register k0 is typically used when all data elements
(unconditional processing) are desired. Additionally, the opmask registers are also used as vector flags/elementlevel vector sources to introduce novel SIMD functionality as seen in new instructions such as VCOMPRESSPS.
Vol. 1 15-1
PROGRAMMING WITH INTEL® AVX-512
256 255
511
Bit#
0
128 127
ZMM0
YMM0
XMM0
ZMM1
YMM1
XMM1
YMM31
XMM31
...
ZMM31
Figure 15-1. 512-Bit Wide Vectors and SIMD Register Set
15.1.4
Instruction Syntax Enhancement
The architecture of EVEX encoding enhances the vector instruction encoding scheme in the following way:
•
512-bit vector-length, up to 32 ZMM registers, and enhanced vector programming environment are supported
using the enhanced VEX (EVEX).
The EVEX prefix provides more encodable bit fields than the VEX prefix. In addition to encoding 32 ZMM registers
in 64-bit mode, instruction encoding using the EVEX prefix can directly encode 7 (out of 8) opmask register operands to provide conditional processing in vector instruction programming. The enhanced vector programming environment can be explicitly expressed in the instruction syntax to include the following elements:
•
An opmask operand: the opmask registers are expressed using the notation “k1” through “k7”. An EVEXencoded instruction supporting conditional vector operation using the opmask register k1 is expressed by
attaching the notation {k1} next to the destination operand. The use of this feature is optional for most instructions. There are two types of masking (merging and zeroing) differentiated using the EVEX.z bit ({z} in
instruction signature).
•
Embedded broadcast may be supported for some instructions on the source operand that can be encoded as a
memory vector. Data elements of a memory vector may be conditionally fetched or written to.
•
For instruction syntax that operates only on floating-point data in SIMD registers with rounding semantics, the
EVEX encoding can provide explicit rounding control within the EVEX bit fields at either scalar or 512-bit vector
length.
In AVX-512 instructions, vector addition of all elements of the source operands can be expressed in the same
syntax as AVX instruction:
VADDPS zmm1, zmm2, zmm3
Additionally, the EVEX encoding scheme of AVX-512 Foundation can express conditional vector addition as:
VADDPS zmm1 {k1}{z}, zmm2, zmm3
where:
•
•
Conditional processing and updates to destination are expressed with an opmask register.
Zeroing behavior of the opmask selected destination element is expressed by the {z} modifier (with merging
as the default if no modifier is specified).
15-2 Vol. 1
PROGRAMMING WITH INTEL® AVX-512
Note that some SIMD instructions supporting three-operand syntax but processing only less than or equal to 128bits of data are considered part of the 512-bit SIMD instruction set extensions, because bits MAX_VL-1:128 of the
destination register are zeroed by the processor. The same rule applies to instructions operating on 256-bits of data
where bits MAX_VL-1:256 of the destination register are zeroed.
15.1.5
EVEX Instruction Encoding Support
Intel AVX-512 instructions employ a new encoding prefix, referred to as EVEX, in the Intel 64 and IA-32 instruction
encoding format. Instruction encoding using the EVEX prefix provides the following capabilities:
•
Direct encoding of a SIMD register operand within EVEX (similar to VEX). This provides instruction syntax
support for three source operands.
•
Compaction of REX prefix functionality and extended SIMD register encoding: the equivalent REX-prefix
compaction functionality offered by the VEX prefix is provided within EVEX. Furthermore, EVEX extends the
operand encoding capability to allow direct addressing of up to 32 ZMM registers in 64-bit mode.
•
Compaction of SIMD prefix functionality and escape byte encoding: the functionality of a SIMD prefix (66H,
F2H, F3H) on opcode is equivalent to an opcode extension field to introduce new processing primitives. This
functionality is provided in the VEX prefix encoding scheme and employed within the EVEX prefix. Similarly, the
functionality of the escape opcode byte (0FH) and two-byte escape (0F38H, 0F3AH) are also compacted within
the EVEX prefix encoding.
•
Most EVEX-encoded SIMD numeric and data processing instruction semantics with memory operands have
more relaxed memory alignment requirements than instructions encoded using SIMD prefixes (see Section
15.7, “Memory Alignment”).
•
Direct encoding of an opmask operand within the EVEX prefix. This provides instruction syntax support for
conditional vector-element operation and merging of destination operand using an opmask register (k1-k7).
•
Direct encoding of a broadcast attribute for instructions with a memory operand source. This provides
instruction syntax support for elements broadcasting the second operand before being used in the actual
operation.
•
Compressed memory address displacements for a more compact instruction encoding byte sequence.
EVEX encoding applies to SIMD instructions operating on XMM, YMM and ZMM registers. EVEX is not supported for
instructions operating on MMX or x87 registers. Details of EVEX instruction encoding are discussed in Section 2.6,
“Intel® AVX-512 Encoding” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
15.2
DETECTION OF AVX-512 FOUNDATION INSTRUCTIONS
The majority of AVX-512 Foundation instructions are encoded using the EVEX encoding scheme. EVEX-encoded
instructions can operate on the 512-bit ZMM register state plus 8 opmask registers. The opmask instructions in
AVX-512 Foundation instructions operate only on opmask registers or with a general purpose register. System
software requirements to support the ZMM state and opmask instructions are described in Chapter 3, “System
Programming For Intel® AVX-512” of the Intel® Architecture Instruction Set Extensions Programming Reference.
Processor support of AVX-512 Foundation instructions is indicated by CPUID.(EAX=07H, ECX=0):EBX.AVX512F[bit
16] = 1. Detection of AVX-512 Foundation instructions operating on ZMM states and opmask registers needs to
follow the general procedural flow in Figure 15-2.
Vol. 1 15-3
PROGRAMMING WITH INTEL® AVX-512
Check feature flag
CPUID.1H:ECX.OSXSAVE = 1?
OS provides processor
extended state management
Yes
Implied HW support for
XSAVE, XRSTOR, XGETBV, XCR0
Check enabled state in
XCR0 via XGETBV
Opmask,
YMM,ZMM
Check AVX512F flag
States
enabled
ok to use
Instructions
Figure 15-2. Procedural Flow for Application Detection of AVX-512 Foundation Instructions
Prior to using AVX-512 Foundation instructions, the application must identify that the operating system supports
the XGETBV instruction and the ZMM register state, in addition to confirming the processor’s support for ZMM state
management using XSAVE/XRSTOR and AVX-512 Foundation instructions. The following simplified sequence
accomplishes both and is strongly recommended.
1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1).
2. Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by
OS).
3. Detect CPUID.0x7.0:EBX.AVX512F[bit 16] = 1.
15.2.1
Additional 512-bit Instruction Extensions of the Intel AVX-512 Family
Processor support of the Intel AVX-512 Exponential and Reciprocal instructions are indicated by querying the
feature flag:
•
If CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1, the collection of
VEXP2PD/VEXP2PS/VRCP28xx/VRSQRT28xx instructions are supported.
Processor support of the Intel AVX-512 Prefetch instructions are indicated by querying the feature flag:
•
If CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1, a collection of
VGATHERPF0xxx/VGATHERPF1xxx/VSCATTERPF0xxx/VSCATTERPF1xxx instructions are supported.
Detection of 512-bit instructions operating on ZMM states and opmask registers, outside of AVX-512 Foundation,
needs to follow the general procedural flow in Figure 15-3.
1. If CPUID.01H:ECX.OSXSAVE reports 1, it also indirectly implies the processor supports XSAVE, XRSTOR, XGETBV, processor
extended state bit vector XCR0 register. Thus an application may streamline the checking of CPUID feature flags for XSAVE and OSXSAVE. XSETBV is a privileged instruction.
15-4 Vol. 1
PROGRAMMING WITH INTEL® AVX-512
Check feature flag
CPUID.1H:ECX.OSXSAVE = 1?
OS provides processor
extended state management
Yes
Implied HW support for
XSAVE, XRSTOR, XGETBV, XCR0
Check enabled state in
XCR0 via XGETBV
Opmask,
YMM,ZMM
States
enabled
Check AVX512F and
additional 512-bit flags
ok to use
Instructions
Figure 15-3. Procedural Flow for Application Detection of 512-bit Instructions
PREFETCHT1W does not require OS support for XMM/YMM/ZMM/k-reg, SIMD FP exception support.
Procedural Flow of Application Detection of other 512-bit extensions:
Prior to using the Intel AVX-512 Exponential and Reciprocal instructions, the application must identify that the
operating system supports the XGETBV instruction and the ZMM register state, in addition to confirming the
processor’s support for ZMM state management using XSAVE/XRSTOR and AVX-512 Foundation instructions. The
following simplified sequence accomplishes both and is strongly recommended.
1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).
2. Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled
by OS).
3. Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, and CPUID.0x7.0:EBX.AVX512ER[bit 27] = 1.
Prior to using the Intel AVX-512 Prefetch instructions, the application must identify that the operating system
supports the XGETBV instruction and the ZMM register state, in addition to confirming the processor’s support for
ZMM state management using XSAVE/XRSTOR and AVX-512 Foundation instructions. The following simplified
sequence accomplishes both and is strongly recommended.
1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).
2. Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled
by OS).
3. Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, and CPUID.0x7.0:EBX.AVX512PF[bit 26] = 1.
15.3
DETECTION OF 512-BIT INSTRUCTION GROUPS OF INTEL® AVX-512
FAMILY
In addition to the Intel AVX-512 Foundation instructions, Intel AVX-512 family provides several groups of instruction extensions that can operate in vector lengths of 512/256/128 bits. Each group is enumerated by a CPUID leaf
7 feature flag and can be encoded via the EVEX.L’L field to support operation at vector lengths smaller than 512
bits. These instruction groups are listed in Table 15-1.
Vol. 1 15-5
PROGRAMMING WITH INTEL® AVX-512
Table 15-1. 512-bit Instruction Groups in the Intel AVX-512 Family
CPUID Leaf 7 Feature Flag Bit
Feature Flag abbreviation of 512-bit Instruction Group
SW Detection Flow
CPUID.(EAX=07H, ECX=0):EBX[bit 16]
AVX512F (AVX-512 Foundation)
Figure 15-2
CPUID.(EAX=07H, ECX=0):EBX[bit 28]
AVX512CD
Figure 15-4
CPUID.(EAX=07H, ECX=0):EBX[bit 17]
AVX512DQ
Figure 15-4
CPUID.(EAX=07H, ECX=0):EBX[bit 30]
AVX512BW
Figure 15-4
Software must follow the detection procedure for the 512-bit AVX-512 Foundation instructions as described in
Section 15.2.
Detection of other 512-bit sibling instruction groups listed in Table 15-1 (excluding AVX512F) follows the procedure
described in Figure 15-4:
Check feature flag
CPUID.1H:ECX.OXSAVE = 1?
OS provides processor
extended state management
Yes
Implied HW support for
XSAVE, XRSTOR, XGETBV, XCR0
Check enabled state in
XCR0 via XGETBV
Opmask,
YMM,ZMM
States
enabled
Check AVX512F and
a sibling 512-bit flag
ok to use
Instructions
Figure 15-4. Procedural Flow for Application Detection of 512-bit Instruction Groups
To detect 512-bit instructions enumerated by AVX512CD, the following sequence is strongly recommended.
1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).
2. Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by
OS).
3. Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512CD[bit 28] = 1.
Similarly, the detection procedure for enumerating 512-bit instructions reported by AVX512DW follows the same
flow.
15.4
DETECTION OF INTEL AVX-512 INSTRUCTION GROUPS OPERATING AT 256
AND 128-BIT VECTOR LENGTHS
For each of the 512-bit instruction groups in the Intel AVX-512 family listed in Table 15-1, the EVEX encoding
scheme may support a vast majority of these instructions operating at 256-bit or 128-bit (if applicable) vector
lengths. Encoding support for vector lengths smaller than 512-bits is indicated by CPUID.(EAX=07H,
ECX=0):EBX[bit 31], abbreviated as AVX512VL.
15-6 Vol. 1
PROGRAMMING WITH INTEL® AVX-512
The AVX512VL flag alone is never sufficient to determine a given Intel AVX-512 instruction may be encoded at
vector lengths smaller than 512 bits. Software must use the procedure described in Figure 15-5 and Table 15-2.
Check feature flag
CPUID.1H:ECX.OXSAVE = 1?
OS provides processor
extended state management
Yes
Implied HW support for
XSAVE, XRSTOR, XGETBV, XCR0
Check enabled state in
XCR0 via XGETBV
Opmask,
YMM,ZMM
States
enabled
Check applicable collection of
CPUID flags listed in Table 2-2
ok to use
Instructions
Figure 15-5. Procedural Flow for Detection of Intel AVX-512 Instructions Operating at Vector Lengths < 512
To illustrate the procedure described in Figure 15-5 and Table 15-2 for software to use EVEX.256 encoded VPCONFLICT, the following sequence is provided. It is strongly recommended this sequence is followed.
1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).
2) Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by
OS).
3) Verify CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512CD[bit 28] = 1, and
CPUID.0x7.0:EBX.AVX512VL[bit 31] = 1.
Table 15-2. Feature flag Collection Required of 256/128 Bit Vector Lengths for Each Instruction Group
Usage of 256/128 Vector Lengths
Feature Flag Collection to Verify
AVX512F
AVX512F & AVX512VL
AVX512CD
AVX512F & AVX512CD & AVX512VL
AVX512DQ
AVX512F & AVX512DQ & AVX512VL
AVX512BW
AVX512F & AVX512BW & AVX512VL
In some specific cases, AVX512VL may only support EVEX.256 encoding but not EVEX.128. These cases are listed
in Table 15-3.
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PROGRAMMING WITH INTEL® AVX-512
Table 15-3. Instruction Mnemonics That Do Not Support EVEX.128 Encoding
Instruction Group
Instruction Mnemonics Supporting EVEX.256 Only Using AVX512VL
AVX512F
VBROADCASTSD, VBROADCASTF32X4, VEXTRACTI32X4, VINSERTF32X4, VINSERTI32X4, VPERMD,
VPERMPD, VPERMPS, VPERMQ, VSHUFF32X4, VSHUFF64X2, VSHUFI32X4, VSHUFI64X2
AVX512CD
AVX512DQ
VBROADCASTF32X2, VBROADCASTF64X2, VBROADCASTI32X4, VBROADCASTI64X2, VEXTRACTI64X2,
VINSERTF64X2, VINSERTI64X2,
AVX512BW
15.5
ACCESSING XMM, YMM AND ZMM REGISTERS
The lower 128 bits of a YMM register is aliased to the corresponding XMM register. Legacy SSE instructions (i.e.,
SIMD instructions operating on XMM state but not using the VEX prefix, also referred to non-VEX encoded SIMD
instructions) will not access the upper bits (MAX_VL-1:128) of the YMM registers. AVX and FMA instructions with a
VEX prefix and vector length of 128-bits zeroes the upper 128 bits of the YMM register.
Upper bits of YMM registers (255:128) can be read and written to by many instructions with a VEX.256 prefix.
XSAVE and XRSTOR may be used to save and restore the upper bits of the YMM registers.
The lower 256 bits of a ZMM register are aliased to the corresponding YMM register. Legacy SSE instructions (i.e.,
SIMD instructions operating on XMM state but not using the VEX prefix, also referred to non-VEX encoded SIMD
instructions) will not access the upper bits (MAX_VL-1:128) of the ZMM registers, where MAX_VL is maximum
vector length (currently 512 bits). AVX and FMA instructions with a VEX prefix and vector length of 128-bits zero
the upper 384 bits of the ZMM register, while the VEX prefix and vector length of 256-bits zeroes the upper 256 bits
of the ZMM register.
Upper bits of ZMM registers (511:256) can be read and written to by instructions with an EVEX.512 prefix.
15.6
ENHANCED VECTOR PROGRAMMING ENVIRONMENT USING EVEX
ENCODING
EVEX-encoded AVX-512 instructions support an enhanced vector programming environment. The enhanced vector
programming environment uses the combination of EVEX bit-field encodings and a set of eight opmask registers to
provide the following capabilities:
•
Conditional vector processing of an EVEX-encoded instruction. Opmask registers k1 through k7 can be used to
conditionally govern the per-data-element computational operation and the per-element updates to the
destination operand of an AVX-512 Foundation instruction. Each bit of the opmask register governs one vector
element operation (a vector element can be 8 bits, 16 bits, 32 bits or 64 bits).
•
In addition to providing predication control on vector instructions via EVEX bit-field encoding, the opmask
registers can also be used similarly on general-purpose registers as source/destination operands using modR/M
encoding for non-mask-related instructions. In this case, an opmask register k0 through k7 can be selected.
•
•
In 64-bit mode, 32 vector registers can be encoded using the EVEX prefix.
•
Flexible rounding control for the register-to-register flavor of EVEX encoded 512-bit and scalar instructions.
Four rounding modes are supported by direct encoding within the EVEX prefix, overriding MXCSR settings.
•
•
Broadcast of one element to the rest of the destination vector register.
Broadcast may be supported for some instructions on the operand that can be encoded as a memory vector.
The data elements of a memory vector may be conditionally fetched or written to, and the vector size is
dependent on the data transformation function.
Compressed 8-bit displacement encoding scheme to increase the instruction encoding density for instructions
that normally require disp32 syntax.
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PROGRAMMING WITH INTEL® AVX-512
15.6.1
OPMASK Register to Predicate Vector Data Processing
AVX-512 instructions using EVEX encode a predicate operand to conditionally control per-element computational
operation and updating of the result to the destination operand. The predicate operand is known as the opmask
register. The opmask is a set of eight architectural registers of size MAX_KL (64-bit). Note that from this set of eight
architectural registers, only k1 through k7 can be addressed as a predicate operand. k0 can be used as a regular
source or destination but cannot be encoded as a predicate operand. Note also that a predicate operand can be
used to enable memory fault-suppression for some instructions with a memory operand (source or destination).
As a predicate operand, the opmask registers contain one bit to govern the operation/update to each data element
of a vector register. In general, opmask registers can support instructions with all element sizes: byte (int8), word
(int16), single-precision floating-point (float32), integer doubleword(int32), double-precision floating-point
(float64), integer quadword (int64). Therefore, a ZMM vector register can hold 8, 16, 32, or 64 elements in principle. The length of an opmask register, MAX_KL, is sufficient to handle up to 64 elements with one bit per element,
i.e., 64 bits. Masking is supported in most of the AVX-512 instructions. For a given vector length, each instruction
accesses only the number of least significant mask bits that are needed based on its data type. For example, AVX512 Foundation instructions operating on 64-bit data elements with a 512-bit vector length, only use the 8 least
significant bits of the opmask register.
An opmask register affects an AVX-512 instruction at per-element granularity. Any numeric or non-numeric operation of each data element and per-element updates of intermediate results to the destination operand are predicated on the corresponding bit of the opmask register.
An opmask serving as a predicate operand in AVX-512 obeys the following properties:
•
The instruction’s operation is not performed for an element if the corresponding opmask bit is not set. This
implies that no exception or violation can be caused by an operation on a masked-off element. Consequently,
no MXCSR exception flag is updated as a result of a masked-off operation.
•
A destination element is not updated with the result of the operation if the corresponding writemask bit is not
set. Instead, the destination element value must be preserved (merging-masking) or it must be zeroed out
(zeroing-masking).
•
For some instructions with a memory operand, memory faults are suppressed for elements with a mask bit of
0.
Note that this feature provides a versatile construct to implement control-flow predication as the mask in effect
provides a merging behavior for AVX-512 vector register destinations. As an alternative the masking can be used
for zeroing instead of merging, so that the masked out elements are updated with 0 instead of preserving the old
value. The zeroing behavior is provided to remove the implicit dependency on the old value when it is not needed.
Most instructions with masking enabled accept both forms of masking. Instructions that must have EVEX.aaa bits
different than 0 (gather and scatter) and instructions that write to memory only accept merging-masking.
It’s important to note that the per-element destination update rule also applies when the destination operand is a
memory location. Vectors are written on a per element basis, based on the opmask register used as a predicate
operand.
The value of an opmask register can be:
•
•
•
•
Generated as a result of a vector instruction (e.g., CMP, FPCLASS, etc.).
Loaded from memory.
Loaded from a GPR register.
Modified by mask-to-mask operations.
Opmask registers can be used for purposes outside of predication. For example, they can be used to manipulate
sparse sets of elements from a vector, or used to set the EFLAGS based on the 0/0xFFFFFFFFFFFFFFFF/other status
of the OR of two opmask registers.
15.6.1.1
Opmask Register K0
The only exception to the opmask rules described above is that opmask k0 can not be used as a predicate operand.
Opmask k0 cannot be encoded as a predicate operand for a vector operation; the encoding value that would select
opmask k0 will instead select an implicit opmask value of 0xFFFFFFFFFFFFFFFF, thereby effectively disabling
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PROGRAMMING WITH INTEL® AVX-512
masking. Opmask register k0 can still be used for any instruction that takes opmask register(s) as operand(s)
(either source or destination).
Note that certain instructions implicitly use the opmask as an extra destination operand. In such cases, trying to
use the “no mask” feature will translate into a #UD fault being raised.
15.6.1.2
Example of Opmask Usages
The example below illustrates the predicated vector add operation and predicated updates of added results into the
destination operand. The initial state of vector registers zmm0, zmm1, and zmm2 and k3 are:
MSB........................................LSB
zmm0 =
[ 0x00000003 0x00000002 0x00000001 0x00000000 ] (bytes 15 through 0)
[ 0x00000007 0x00000006 0x00000005 0x00000004 ] (bytes 31 through 16)
[ 0x0000000B 0x0000000A 0x00000009 0x00000008 ] (bytes 47 through 32)
[ 0x0000000F 0x0000000E 0x0000000D 0x0000000C ] (bytes 63 through 48)
zmm1 =
[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 15 through 0)
[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 31 through 16)
[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 47 through 32)
[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 63 through 48)
zmm2 =
[ 0xAAAAAAAA 0xAAAAAAAA 0xAAAAAAAA 0xAAAAAAAA ] (bytes 15 through 0)
[ 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB ] (bytes 31 through 16)
[ 0xCCCCCCCC 0xCCCCCCCC 0xCCCCCCCC 0xCCCCCCCC ] (bytes 47 through 32)
[ 0xDDDDDDDD 0xDDDDDDDD 0xDDDDDDDD 0xDDDDDDDD ] (bytes 63 through 48)
k3 = 0x8F03 (1000 1111 0000 0011)
An opmask register serving as a predicate operand is expressed as a curly-braces-enclosed decorator following the
first operand in the Intel assembly syntax. Given this state, we will execute the following instruction:
vpaddd zmm2 {k3}, zmm0, zmm1
The vpaddd instruction performs 32-bit integer additions on each data element conditionally based on the corresponding bit value in the predicate operand k3. Since per-element operations are not operated if the corresponding
bit of the predicate mask is not set, the intermediate result is:
[ ********** ********** 0x00000010 0x0000000F ] (bytes 15 through 0)
[ ********** ********** ********** ********** ] (bytes 31 through 16)
[ 0x0000001A 0x00000019 0x00000018 0x00000017 ] (bytes 47 through 32)
[ 0x0000001E ********** ********** ********** ] (bytes 63 through 48)
where ”**********” indicates that no operation is performed.
This intermediate result is then written into the destination vector register, zmm2, using the opmask register k3 as
the writemask, producing the following final result:
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PROGRAMMING WITH INTEL® AVX-512
zmm2 =
[ 0xAAAAAAAA 0xAAAAAAAA 0x00000010 0x0000000F ] (bytes 15 through 0)
[ 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB ] (bytes 31 through 16)
[ 0x0000001A 0x00000019 0x00000018 0x00000017 ] (bytes 47 through 32)
[ 0x0000001E 0xDDDDDDDD 0xDDDDDDDD 0xDDDDDDDD ] (bytes 63 through 48)
Note that for a 64-bit instruction (for example, vaddpd), only the 8 LSB of mask k3 (0x03) would be used to identify the predicate operation on each one of the 8 elements of the source/destination vectors.
15.6.2
OpMask Instructions
AVX-512 Foundation instructions provide a collection of opmask instructions that allow programmers to set, copy,
or operate on the contents of a given opmask register. There are three types of opmask instructions:
•
Mask read/write instructions: These instructions move data between a general-purpose integer register or
memory and an opmask mask register, or between two opmask registers. For example:
— kmovw k1, ebx; move lower 16 bits of ebx to k1.
•
Flag instructions: This category consists of instructions that modify EFLAGS based on the content of opmask
registers.
— kortestw k1, k2; OR registers k1 and k2 and updated EFLAGS accordingly.
•
Mask logical instructions: These instructions perform standard bitwise logical operations between opmask
registers.
— kandw k1, k2, k3; AND lowest 16 bits of registers k2 and k3, leaving the result in k1.
15.6.3
Broadcast
EVEX encoding provides a bit-field to encode data broadcast for some load-op instructions, i.e., instructions that
load data from memory and perform some computational or data movement operation. A source element from
memory can be broadcasted (repeated) across all the elements of the effective source operand (up to 16 times for
a 32-bit data element, up to 8 times for a 64-bit data element). This is useful when we want to reuse the same
scalar operand for all the operations in a vector instruction. Broadcast is only enabled on instructions with an
element size of 32 bits or 64 bits. Byte and word instructions do not support embedded broadcast.
The functionality of data broadcast is expressed as a curly-braces-enclosed decorator following the last
register/memory operand in the Intel assembly syntax.
For instance:
vmulps zmm1, zmm2, [rax] {1to16}
The {1to16} primitive loads one float32 (single precision) element from memory, replicates it 16 times to form a
vector of 16 32-bit floating-point elements, multiplies the 16 float32 elements with the corresponding elements in
the first source operand vector, and puts each of the 16 results into the destination operand.
AVX-512 instructions with store semantics and pure load instructions do not support broadcast primitives.
vmovaps [rax] {k3}, zmm19
In contrast, the k3 opmask register is used as the predicate operand in the above example. Only the store operation on data elements corresponding to the non-zero bits in k3 will be performed.
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PROGRAMMING WITH INTEL® AVX-512
15.6.4
STATIC ROUNDING MODE AND SUPPRESS ALL EXCEPTIONS
In previous SIMD instruction extensions (up to AVX and AVX2), rounding control is generally specified in MXCSR,
with a handful of instructions providing per-instruction rounding override via encoding fields within the imm8
operand. AVX-512 offers a more flexible encoding attribute to override MXCSR-based rounding control for floatingpointing instructions with rounding semantics. This rounding attribute embedded in the EVEX prefix is called Static
(per instruction) Rounding Mode or Rounding Mode override. This attribute allows programmers to statically apply
a specific arithmetic rounding mode irrespective of the value of RM bits in MXCSR. It is available only to register-toregister flavors of EVEX-encoded floating-point instructions with rounding semantic. The differences between these
three rounding control interfaces are summarized in Table 15-4.
Table 15-4. Characteristics of Three Rounding Control Interfaces
Rounding Interface
Static Rounding
Override
Imm8 Embedded Rounding
Override
MXCSR Rounding Control
Semantic Requirement
FP rounding
FP rounding
FP rounding
Prefix Requirement
EVEX.B = 1
NA
NA
Rounding Control
EVEX.L’L
IMM8[1:0] or MXCSR.RC
(depending on IMM8[2])
MXCSR.RC
Suppress All Exceptions (SAE)
Implied
no
no
SIMD FP Exception #XF
All suppressed
Can raise #I, #P (unless SPE is set) MXCSR masking controls
MXCSR flag update
No
yes (except PE if SPE is set)
Yes
Precedence
Above MXCSR.RC
Above EVEX.L’L
Default
Scope
512-bit, reg-reg,
Scalar reg-reg
ROUNDPx, ROUNDSx,
VCVTPS2PH, VRNDSCALExx
All SIMD operands, vector lengths
The static rounding-mode override in AVX-512 also implies the “suppress-all-exceptions” (SAE) attribute. The SAE
effect is as if all the MXCSR mask bits are set, and none of the MXCSR flags will be updated. Using static roundingmode via EVEX without SAE is not supported.
Static Rounding Mode and SAE control can be enabled in the encoding of the instruction by setting the EVEX.b bit
to 1 in a register-register vector instruction. In such a case, vector length is assumed to be MAX_VL (512-bit in case
of AVX-512 packed vector instructions) or 128-bit for scalar instructions. Table 15-5 summarizes the possible static
rounding-mode assignments in AVX-512 instructions.
Note that some instructions already allow specifying the rounding mode statically via immediate bits. In such
cases, the immediate bits take precedence over the embedded rounding mode (in the same vein that they take
precedence over whatever MXCSR.RM says).
Table 15-5. Static Rounding Mode
Function
Description
{rn-sae}
Round to nearest (even) + SAE
{rd-sae}
Round down (toward -inf) + SAE
{ru-sae}
Round up (toward +inf) + SAE
{rz-sae}
Round toward zero (Truncate) + SAE
An example of use would be as follows:
vaddps zmm7 {k6}, zmm2, zmm4, {rd-sae}
This would perform the single-precision floating-point addition of vectors zmm2 and zmm4 with round-towardsminus-infinity, leaving the result in vector zmm7 using k6 as conditional writemask.
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PROGRAMMING WITH INTEL® AVX-512
Note that MXCSR.RM bits are ignored and unaffected by the outcome of this instruction.
Examples of instruction instances where the static rounding-mode is not allowed are shown below:
; rounding-mode already specified in the instruction immediate
vrndscaleps zmm7 {k6}, zmm2, 0x00
; instructions with memory operands
vmulps zmm7 {k6}, zmm2,[rax], {rd-sae}
; instructions with vector length different than MAX_VL (512-bit)
vaddps ymm7 {k6}, ymm2, ymm4,{rd-sae}
15.6.5
Compressed Disp8*N Encoding
EVEX encoding supports a new displacement representation that allows for a more compact encoding of memory
addressing commonly used in unrolled code, where an 8-bit displacement can address a range exceeding the
dynamic range of an 8-bit value. This compressed displacement encoding is referred to as disp8*N, where N is a
constant implied by the memory operation characteristic of each instruction.
The compressed displacement is based on the assumption that the effective displacement (of a memory operand
occurring in a loop) is a multiple of the granularity of the memory access of each iteration. Since the base register
in memory addressing already provides byte-granular resolution, the lower bits of the traditional disp8 operand
become redundant, and can be implied from the memory operation characteristic.
The memory operation characteristics depend on the following:
•
•
The destination operand is updated as a full vector, a single element, or multi-element tuples.
The memory source operand (or vector source operand if the destination operand is memory) is fetched (or
treated) as a full vector, a single element, or multi-element tuples.
For example:
vaddps zmm7, zmm2, disp8[membase + index*8]
The destination zmm7 is updated as a full 512-bit vector, and 64-bytes of data are fetched from memory as a full
vector; the next unrolled iteration may fetch from memory in 64-byte granularity per iteration. There are 6 bits of
lowest address that can be compressed, hence N = 2^6 = 64. The contribution of “disp8” to effective address
calculation is 64*disp8.
vbroadcastf32x4 zmm7, disp8[membase + index*8]
In VBROADCASTF32x4, memory is fetched as a 4tuple of 4 32-bit entities. Hence the common lowest address bits
that can be compressed are 4, corresponding to the 4tuple width of 2^4 = 16 bytes (4x32 bits). Therefore, N =
2^4.
For EVEX encoded instructions that update only one element in the destination, or the source element is fetched
individually, the number of lowest address bits that can be compressed is generally the width in bytes of the data
element, hence N = 2^(width).
15.7
MEMORY ALIGNMENT
Memory alignment requirements on EVEX-encoded SIMD instructions are similar to VEX-encoded SIMD instructions. Memory alignment applies to EVEX-encoded SIMD instructions in three categories:
•
Explicitly-aligned SIMD load and store instructions accessing 64 bytes of memory with EVEX prefix encoded
vector length of 512 bits (e.g., VMOVAPD, VMOVAPS, VMOVDQA, etc.). These instructions always require the
memory address to be aligned on a 64-byte boundary.
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PROGRAMMING WITH INTEL® AVX-512
•
Explicitly-unaligned SIMD load and store instructions accessing 64 bytes or less of data from memory (e.g.,
VMOVUPD, VMOVUPS, VMOVDQU, VMOVQ, VMOVD, etc.). These instructions do not require the memory
address to be aligned on a natural vector-length byte boundary.
•
Most arithmetic and data processing instructions encoded using EVEX support memory access semantics.
When these instructions access from memory, there are no alignment restrictions.
Software may see performance penalties when unaligned accesses cross cacheline boundaries or vector-length
naturally-aligned boundaries, so reasonable attempts to align commonly used data sets should continue to be
pursued.
Atomic memory operation in Intel 64 and IA-32 architecture is guaranteed only for a subset of memory operand
sizes and alignment scenarios. The guaranteed atomic operations are described in Section 7.1.1, “Task Structure”
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. AVX and FMA instructions do
not introduce any new guaranteed atomic memory operations.
AVX-512 instructions may generate an #AC(0) fault on misaligned 4 or 8-byte memory references in Ring-3 when
CR0.AM=1. 16, 32 and 64-byte memory references will not generate an #AC(0) fault. See Table 15-7 for details.
Certain AVX-512 Foundation instructions always require 64-byte alignment (see the complete list of VEX and EVEX
encoded instructions in Table 15-6). These instructions will #GP(0) if not aligned to 64-byte boundaries.
Table 15-6. SIMD Instructions Requiring Explicitly Aligned Memory
Require 16-byte alignment
Require 32-byte alignment
Require 64-byte alignment*
(V)MOVDQA xmm, m128
VMOVDQA ymm, m256
VMOVDQA zmm, m512
(V)MOVDQA m128, xmm
VMOVDQA m256, ymm
VMOVDQA m512, zmm
(V)MOVAPS xmm, m128
VMOVAPS ymm, m256
VMOVAPS zmm, m512
(V)MOVAPS m128, xmm
VMOVAPS m256, ymm
VMOVAPS m512, zmm
(V)MOVAPD xmm, m128
VMOVAPD ymm, m256
VMOVAPD zmm, m512
(V)MOVAPD m128, xmm
VMOVAPD m256, ymm
VMOVAPD m512, zmm
(V)MOVNTDQA xmm, m128
VMOVNTPS m256, ymm
VMOVNTPS m512, zmm
(V)MOVNTPS m128, xmm
VMOVNTPD m256, ymm
VMOVNTPD m512, zmm
(V)MOVNTPD m128, xmm
VMOVNTDQ m256, ymm
VMOVNTDQ m512, zmm
(V)MOVNTDQ m128, xmm
VMOVNTDQA ymm, m256
VMOVNTDQA zmm, m512
Table 15-7. Instructions Not Requiring Explicit Memory Alignment
(V)MOVDQU xmm, m128
VMOVDQU ymm, m256
VMOVDQU zmm, m512
(V)MOVDQU m128, m128
VMOVDQU m256, ymm
VMOVDQU m512, zmm
(V)MOVUPS xmm, m128
VMOVUPS ymm, m256
VMOVUPS zmm, m512
(V)MOVUPS m128, xmm
VMOVUPS m256, ymm
VMOVUPS m512, zmm
(V)MOVUPD xmm, m128
VMOVUPD ymm, m256
VMOVUPD zmm, m512
(V)MOVUPD m128, xmm
VMOVUPD m256, ymm
VMOVUPD m512, zmm
15.8
SIMD FLOATING-POINT EXCEPTIONS
AVX-512 instructions can generate SIMD floating-point exceptions (#XM) if embedded “suppress all exceptions”
(SAE) in EVEX is not set. When SAE is not set, these instructions will respond to exception masks of MXCSR in the
same way as VEX-encoded AVX instructions. When CR4.OSXMMEXCPT=0, any unmasked FP exceptions generate
an Undefined Opcode exception (#UD).
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PROGRAMMING WITH INTEL® AVX-512
15.9
INSTRUCTION EXCEPTION SPECIFICATION
Exception behavior of VEX-encoded AVX / AVX2 instructions are described in Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 2A. Exception behavior of AVX-512 Foundation instructions and additional
512-bit extensions are described in Section 2.7, “Exception Classifications of EVEX-Encoded instructions” and
Section 2.8, “Exception Classifications of Opmask instructions”.
15.10
EMULATION
Setting the CR0.EM bit to 1 provides a technique to emulate legacy SSE floating-point instruction sets in software.
This technique is not supported with AVX instructions, nor FMA instructions.
If an operating system wishes to emulate AVX instructions, set XCR0[2:1] to zero. This will cause AVX instructions
to #UD. Emulation of FMA by the operating system can be done similarly as with emulating AVX instructions.
15.11
WRITING FLOATING-POINT EXCEPTION HANDLERS
AVX-512, AVX and FMA floating-point exceptions are handled in an entirely analogous way to legacy SSE floatingpoint exceptions. To handle unmasked SIMD floating-point exceptions, the operating system or executive must
provide an exception handler. Section 11.5.1, “SIMD Floating-Point Exceptions”, describes the SIMD floating-point
exception classes and gives suggestions for writing an exception handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point exceptions (#XM), the CR4.OSXMMEXCPT flag (bit 10) must be set.
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15-16 Vol. 1
CHAPTER 16
PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION
EXTENSIONS
16.1
OVERVIEW
This chapter describes the software programming interface to the Intel® Transactional Synchronization Extensions
of the Intel 64 architecture.
Multithreaded applications take advantage of increasing number of cores to achieve high performance. However,
writing multi-threaded applications requires programmers to reason about data sharing among multiple threads.
Access to shared data typically requires synchronization mechanisms. These mechanisms ensure multiple threads
update shared data by serializing operations on the shared data, often through the use of a critical section
protected by a lock. Since serialization limits concurrency, programmers try to limit synchronization overheads.
They do this either through minimizing the use of synchronization or through the use of fine-grain locks; where
multiple locks each protect different shared data. Unfortunately, this process is difficult and error prone; a missed
or incorrect synchronization can cause an application to fail. Conservatively adding synchronization and using
coarser granularity locks, where a few locks each protect many items of shared data, helps avoid correctness problems but limits performance due to excessive serialization. While programmers must use static information to
determine when to serialize, the determination as to whether actually to serialize is best done dynamically.
Intel® Transactional Synchronization Extensions aim to improve the performance of lock-protected critical sections
while maintaining the lock-based programming model.
16.2
INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS
Intel® Transactional Synchronization Extensions (Intel® TSX) allow the processor to determine dynamically
whether threads need to serialize through lock-protected critical sections, and to perform serialization only when
required. This lets the hardware expose and exploit concurrency hidden in an application due to dynamically
unnecessary synchronization through a technique known as lock elision.
With lock elision, the hardware executes the programmer-specified critical sections (also referred to as transactional regions) transactionally. In such an execution, the lock variable is only read within the transactional region;
it is not written to (and therefore not acquired) with the expectation that the lock variable remains unchanged after
the transactional region, thus exposing concurrency.
If the transactional execution completes successfully, then the hardware ensures that all memory operations
performed within the transactional region will appear to have occurred instantaneously when viewed from other
logical processors, a process referred to as an atomic commit. Any updates performed within the transactional
region are made visible to other processors only on an atomic commit.
Since a successful transactional execution ensures an atomic commit, the processor can execute the programmerspecified code section optimistically without synchronization. If synchronization was unnecessary for that specific
execution, execution can commit without any cross-thread serialization.
If the transactional execution is unsuccessful, the processor cannot commit the updates atomically. When this
happens, the processor will roll back the execution, a process referred to as a transactional abort. On a transactional abort, the processor will discard all updates performed in the region, restore architectural state to appear as
if the optimistic execution never occurred, and resume execution non-transactionally. Depending on the policy in
place, lock elision may be retried or the lock may be explicitly acquired to ensure forward progress.
Intel TSX provides two software interfaces for programmers.
•
Hardware Lock Elision (HLE) is a legacy compatible instruction set extension (comprising the XACQUIRE and
XRELEASE prefixes).
•
Restricted Transactional Memory (RTM) is a new instruction set interface (comprising the XBEGIN and XEND
instructions).
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Programmers who would like to run Intel TSX-enabled software on legacy hardware would use the HLE interface to
implement lock elision. On the other hand, programmers who do not have legacy hardware requirements and who
deal with more complex locking primitives would use the RTM software interface of Intel TSX to implement lock
elision. In the latter case when using new instructions, the programmer must always provide a non-transactional
path (which would have code to eventually acquire the lock being elided) to execute following a transactional abort
and must not rely on the transactional execution alone.
In addition, Intel TSX also provides the XTEST instruction to test whether a logical processor is executing transactionally, and the XABORT instruction to abort a transactional region.
A processor can perform a transactional abort for numerous reasons. A primary cause is due to conflicting accesses
between the transactionally executing logical processor and another logical processor. Such conflicting accesses
may prevent a successful transactional execution. Memory addresses read from within a transactional region
constitute the read-set of the transactional region and addresses written to within the transactional region constitute the write-set of the transactional region. Intel TSX maintains the read- and write-sets at the granularity of a
cache line.
A conflicting data access occurs if another logical processor either reads a location that is part of the transactional
region’s write-set or writes a location that is a part of either the read- or write-set of the transactional region. We
refer to this as a data conflict. Since Intel TSX detects data conflicts at the granularity of a cache line, unrelated
data locations placed in the same cache line will be detected as conflicts. Transactional aborts may also occur due
to limited transactional resources. For example, the amount of data accessed in the region may exceed an implementation-specific capacity. Additionally, some instructions and system events may cause transactional aborts.
16.2.1
HLE Software Interface
HLE provides two new instruction prefix hints: XACQUIRE and XRELEASE.
The programmer uses the XACQUIRE prefix in front of the instruction that is used to acquire the lock that is
protecting the critical section. The processor treats the indication as a hint to elide the write associated with the
lock acquire operation. Even though the lock acquire has an associated write operation to the lock, the processor
does not add the address of the lock to the transactional region’s write-set nor does it issue any write requests to
the lock. Instead, the address of the lock is added to the read-set. The logical processor enters transactional execution. If the lock was available before the XACQUIRE prefixed instruction, all other processors will continue to see it
as available afterwards. Since the transactionally executing logical processor neither added the address of the lock
to its write-set nor performed externally visible write operations to it, other logical processors can read the lock
without causing a data conflict. This allows other logical processors to also enter and concurrently execute the critical section protected by the lock. The processor automatically detects any data conflicts that occur during the
transactional execution and will perform a transactional abort if necessary.
Even though the eliding processor did not perform any external write operations to the lock, the hardware ensures
program order of operations on the lock. If the eliding processor itself reads the value of the lock in the critical
section, it will appear as if the processor had acquired the lock, i.e. the read will return the non-elided value. This
behavior makes an HLE execution functionally equivalent to an execution without the HLE prefixes.
The programmer uses the XRELEASE prefix in front of the instruction that is used to release the lock protecting the
critical section. This involves a write to the lock. If the instruction is restoring the value of the lock to the value it
had prior to the XACQUIRE prefixed lock acquire operation on the same lock, then the processor elides the external
write request associated with the release of the lock and does not add the address of the lock to the write-set. The
processor then attempts to commit the transactional execution.
With HLE, if multiple threads execute critical sections protected by the same lock but they do not perform any
conflicting operations on each other’s data, then the threads can execute concurrently and without serialization.
Even though the software uses lock acquisition operations on a common lock, the hardware recognizes this, elides
the lock, and executes the critical sections on the two threads without requiring any communication through the
lock — if such communication was dynamically unnecessary.
If the processor is unable to execute the region transactionally, it will execute the region non-transactionally and
without elision. HLE enabled software has the same forward progress guarantees as the underlying non-HLE lockbased execution. For successful HLE execution, the lock and the critical section code must follow certain guidelines
(discussed in Section 16.3.3 and Section 16.3.8). These guidelines only affect performance; not following these
guidelines will not cause a functional failure.
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Hardware without HLE support will ignore the XACQUIRE and XRELEASE prefix hints and will not perform any
elision since these prefixes correspond to the REPNE/REPE IA-32 prefixes which are ignored on the instructions
where XACQUIRE and XRELEASE are valid. Importantly, HLE is compatible with the existing lock-based programming model. Improper use of hints will not cause functional bugs though it may expose latent bugs already in the
code.
16.2.2
RTM Software Interface
RTM provides three new instructions: XBEGIN, XEND, and XABORT.
Software uses the XBEGIN instruction to specify the start of the transactional region and the XEND instruction to
specify the end of the transactional region. The XBEGIN instruction takes an operand that provides a relative offset
to the fallback instruction address if the transactional region could not be successfully executed transactionally.
Software using these instructions to implement lock elision must test the lock within the transactional region, and
only if free should try to commit. Further, the software may also define a policy to retry if the lock is not free.
A processor may abort transactional execution for many reasons. The hardware automatically detects transactional
abort conditions and restarts execution from the fallback instruction address with the architectural state corresponding to that at the start of the XBEGIN instruction and the EAX register updated to describe the abort status.
The XABORT instruction allows programmers to abort the execution of a transactional region explicitly. The
XABORT instruction takes an 8 bit immediate argument that is loaded into the EAX register and will thus be available to software following a transactional abort.
Hardware provides no guarantees as to whether a transactional execution will ever successfully commit. Programmers must always provide an alternative code sequence in the fallback path to guarantee forward progress. When
using the instructions for lock elision, this may be as simple as acquiring a lock and executing the specified code
region non-transactionally. Further, a transactional region that always aborts on a given implementation may
complete transactionally on a future implementation. Therefore, programmers must ensure the code paths for the
transactional region and the alternative code sequence are functionally tested.
If the RTM software interface is used for anything other than lock elision, the programmer must similarly ensure
that the fallback path is inter-operable with the transactionally executing path.
16.3
INTEL® TSX APPLICATION PROGRAMMING MODEL
16.3.1
Detection of Transactional Synchronization Support
16.3.1.1
Detection of HLE Support
A processor supports HLE execution if CPUID.07H.EBX.HLE [bit 4] = 1. However, an application can use the HLE
prefixes (XACQUIRE and XRELEASE) without checking whether the processor supports HLE. Processors without
HLE support ignore these prefixes and will execute the code without entering transactional execution.
16.3.1.2
Detection of RTM Support
A processor supports RTM execution if CPUID.07H.EBX.RTM [bit 11] = 1. An application must check if the processor
supports RTM before it uses the RTM instructions (XBEGIN, XEND, XABORT). These instructions will generate a
#UD exception when used on a processor that does not support RTM.
16.3.1.3
Detection of XTEST Instruction
A processor supports the XTEST instruction if it supports either HLE or RTM. An application must check either of
these feature flags before using the XTEST instruction. This instruction will generate a #UD exception when used
on a processor that does not support either HLE or RTM.
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16.3.2
Querying Transactional Execution Status
The XTEST instruction can be used to determine the transactional status of a transactional region specified by HLE
or RTM. Note, while the HLE prefixes are ignored on processors that do not support HLE, the XTEST instruction will
generate a #UD exception when used on processors that do not support either HLE or RTM.
16.3.3
Requirements for HLE Locks
For HLE execution to successfully commit transactionally, the lock must satisfy certain properties and access to the
lock must follow certain guidelines.
•
An XRELEASE prefixed instruction must restore the value of the elided lock to the value it had before the lock
acquisition. This allows hardware to safely elide locks by not adding them to the write-set. The data size and
data address of the lock release (XRELEASE prefixed) instruction must match that of the lock acquire
(XACQUIRE prefixed) and the lock must not cross a cache line boundary.
•
Software should not write to the elided lock inside a transactional HLE region with any instruction other than an
XRELEASE prefixed instruction, otherwise it may cause a transactional abort. In addition, recursive locks
(where a thread acquires the same lock multiple times without first releasing the lock) may also cause a transactional abort. Note that software can observe the result of the elided lock acquire inside the critical section.
Such a read operation will return the value of the write to the lock.
The processor automatically detects violations to these guidelines, and safely transitions to a non-transactional
execution without elision. Since Intel TSX detects conflicts at the granularity of a cache line, writes to data collocated on the same cache line as the elided lock may be detected as data conflicts by other logical processors eliding
the same lock.
16.3.4
Transactional Nesting
Both HLE- and RTM-based transactional executions support nested transactional regions. However, a transactional
abort restores state to the operation that started transactional execution: either the outermost XACQUIRE prefixed
HLE eligible instruction or the outermost XBEGIN instruction. The processor treats all nested transactional regions
as one monolithic transactional region.
16.3.4.1
HLE Nesting and Elision
Programmers can nest HLE regions up to an implementation specific depth of MAX_HLE_NEST_COUNT. Each logical
processor tracks the nesting count internally but this count is not available to software. An XACQUIRE prefixed HLEeligible instruction increments the nesting count, and an XRELEASE prefixed HLE-eligible instruction decrements it.
The logical processor enters transactional execution when the nesting count goes from zero to one. The logical
processor attempts to commit only when the nesting count becomes zero. A transactional abort may occur if the
nesting count exceeds MAX_HLE_NEST_COUNT.
In addition to supporting nested HLE regions, the processor can also elide multiple nested locks. The processor
tracks a lock for elision beginning with the XACQUIRE prefixed HLE eligible instruction for that lock and ending with
the XRELEASE prefixed HLE eligible instruction for that same lock. The processor can, at any one time, track up to
a MAX_HLE_ELIDED_LOCKS number of locks. For example, if the implementation supports a
MAX_HLE_ELIDED_LOCKS value of two and if the programmer nests three HLE identified critical sections (by
performing XACQUIRE prefixed HLE eligible instructions on three distinct locks without performing an intervening
XRELEASE prefixed HLE eligible instruction on any one of the locks), then the first two locks will be elided, but the
third won't be elided (but will be added to the transaction’s write-set). However, the execution will still continue
transactionally. Once an XRELEASE for one of the two elided locks is encountered, a subsequent lock acquired
through the XACQUIRE prefixed HLE eligible instruction will be elided.
The processor attempts to commit the HLE execution when all elided XACQUIRE and XRELEASE pairs have been
matched, the nesting count goes to zero, and the locks have satisfied the requirements described earlier. If execution cannot commit atomically, then execution transitions to a non-transactional execution without elision as if the
first instruction did not have an XACQUIRE prefix.
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16.3.4.2
RTM Nesting
Programmers can nest RTM-based transactional regions up to an implementation specific
MAX_RTM_NEST_COUNT. The logical processor tracks the nesting count internally but this count is not available to
software. An XBEGIN instruction increments the nesting count, and an XEND instruction decrements it. The logical
processor attempts to commit only if the nesting count becomes zero. A transactional abort occurs if the nesting
count exceeds MAX_RTM_NEST_COUNT.
16.3.4.3
Nesting HLE and RTM
HLE and RTM provide two alternative software interfaces to a common transactional execution capability. The
behavior when HLE and RTM are nested together—HLE inside RTM or RTM inside HLE—is implementation specific.
However, in all cases, the implementation will maintain HLE and RTM semantics. An implementation may choose to
ignore HLE hints when used inside RTM regions, and may cause a transactional abort when RTM instructions are
used inside HLE regions. In the latter case, the transition from transactional to non-transactional execution occurs
seamlessly since the processor will re-execute the HLE region without actually doing elision, and then execute the
RTM instructions.
16.3.5
RTM Abort Status Definition
RTM uses the EAX register to communicate abort status to software. Following an RTM abort the EAX register has
the following definition.
Table 16-1. RTM Abort Status Definition
EAX Register Bit
Position
Meaning
0
Set if abort caused by XABORT instruction.
1
If set, the transactional execution may succeed on a retry. This bit is always clear if bit 0 is set.
2
Set if another logical processor conflicted with a memory address that was part of the transactional execution
that aborted.
3
Set if an internal buffer to track transactional state overflowed.
4
Set if a debug exception (#DB) or breakpoint exception (#BP) was hit.
5
Set if an abort occurred during execution of a nested transactional execution.
23:6
Reserved.
31:24
XABORT argument (only valid if bit 0 set, otherwise reserved).
The EAX abort status for RTM only provides causes for aborts. It does not by itself encode whether an abort or
commit occurred for the RTM region. The value of EAX can be 0 following an RTM abort. For example, a CPUID
instruction when used inside an RTM region causes a transactional abort and may not satisfy the requirements for
setting any of the EAX bits. This may result in an EAX value of 0.
16.3.6
RTM Memory Ordering
A successful RTM commit causes all memory operations in the RTM region to appear to execute atomically. A
successfully committed RTM region consisting of an XBEGIN followed by an XEND, even with no memory operations
in the RTM region, has the same ordering semantics as a LOCK prefixed instruction.
The XBEGIN instruction does not have fencing semantics. However, if an RTM execution aborts, all memory
updates from within the RTM region are discarded and never made visible to any other logical processor.
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16.3.7
RTM-Enabled Debugger Support
Any debug exception (#DB) or breakpoint exception (#BP) inside an RTM region causes a transactional abort and,
by default, redirects control flow to the fallback instruction address with architectural state recovered and bit 4 in
EAX set. However, to allow software debuggers to intercept execution on debug or breakpoint exceptions, the RTM
architecture provides additional capability called advanced debugging of RTM transactional regions.
Advanced debugging of RTM transactional regions is enabled if bit 11 of DR7 and bit 15 of the IA32_DEBUGCTL MSR
are both 1. In this case, any RTM transactional abort due to a #DB or #BP causes execution to roll back to just
before the XBEGIN instruction (EAX is restored to the value it had before XBEGIN) and then delivers a #DB. (A #DB
is delivered even if the transactional abort was caused by a #BP.) DR6[16] is cleared to indicate that the exception
resulted from a debug or breakpoint exception inside an RTM region. See also Section 17.3.3, “Debug Exceptions,
Breakpoint Exceptions, and Restricted Transactional Memory (RTM),” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
16.3.8
Programming Considerations
Typical programmer-identified regions are expected to execute transactionally and to commit successfully.
However, Intel TSX does not provide any such guarantee. A transactional execution may abort for many reasons.
To take full advantage of the transactional capabilities, programmers should follow certain guidelines to increase
the probability of their transactional execution committing successfully.
This section discusses various events that may cause transactional aborts. The architecture ensures that updates
performed within a transactional region that subsequently aborts execution will never become visible. Only a
committed transactional execution updates architectural state. Transactional aborts never cause functional failures
and only affect performance.
16.3.8.1
Instruction Based Considerations
Programmers can use any instruction safely inside a transactional region. Further, programmers can use the Intel
TSX instructions and prefixes at any privilege level. However, some instructions will always abort the transactional
execution and cause execution to seamlessly and safely transition to a non-transactional path.
Intel TSX allows for most common instructions to be used inside transactional regions without causing aborts. The
following operations inside a transactional region do not typically cause an abort.
•
Operations on the instruction pointer register, general purpose registers (GPRs) and the status flags (CF, OF, SF,
PF, AF, and ZF).
•
Operations on XMM and YMM registers and the MXCSR register
However, programmers must be careful when intermixing SSE and AVX operations inside a transactional region.
Intermixing SSE instructions accessing XMM registers and AVX instructions accessing YMM registers may cause
transactional regions to abort.
CLD and STD instructions when used inside transactional regions may cause aborts if they change the value of the
DF flag. However, if DF is 1, the STD instruction will not cause an abort. Similarly, if DF is 0, the CLD instruction will
not cause an abort.
Instructions not enumerated here as causing abort when used inside a transactional region will typically not cause
the execution to abort (examples include but are not limited to MFENCE, LFENCE, SFENCE, RDTSC, RDTSCP, etc.).
The following instructions will abort transactional execution on any implementation:
•
•
•
•
•
XABORT
CPUID
PAUSE
ENCLS
ENCLU
In addition, in some implementations, the following instructions may always cause transactional aborts. These
instructions are not expected to be commonly used inside typical transactional regions. However, programmers
must not rely on these instructions to force a transactional abort, since whether they cause transactional aborts is
implementation dependent.
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•
Operations on X87 and MMX architecture state. This includes all MMX and X87 instructions, including the
FXRSTOR and FXSAVE instructions.
•
•
Update to non-status portion of EFLAGS: CLI, STI, POPFD, POPFQ.
•
•
Ring transitions: SYSENTER, SYSCALL, SYSEXIT, and SYSRET.
•
•
•
•
Processor state save: XSAVE, XSAVEOPT, and XRSTOR.
•
•
SMX: GETSEC.
Instructions that update segment registers, debug registers and/or control registers: MOV to
DS/ES/FS/GS/SS, POP DS/ES/FS/GS/SS, LDS, LES, LFS, LGS, LSS, SWAPGS, WRFSBASE, WRGSBASE, LGDT,
SGDT, LIDT, SIDT, LLDT, SLDT, LTR, STR, Far CALL, Far JMP, Far RET, IRET, MOV to DRx, MOV to
CR0/CR2/CR3/CR4/CR8, CLTS and LMSW.
TLB and Cacheability control: CLFLUSH, CLFLUSHOPT, INVD, WBINVD, INVLPG, INVPCID, and memory instructions with a non-temporal hint (V/MOVNTDQA, V/MOVNTDQ, V/MOVNTI, V/MOVNTPD, V/MOVNTPS,
V/MOVNTQ, V/MASKMOVQ, and V/MASKMOVDQU).
Interrupts: INTn, INTO.
IO: IN, INS, REP INS, OUT, OUTS, REP OUTS and their variants.
VMX: VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF,
VMXON, INVEPT, INVVPID, and VMFUNC.
UD2, RSM, RDMSR, WRMSR, HLT, MONITOR, MWAIT, XSETBV, VZEROUPPER, MASKMOVQ, and
V/MASKMOVDQU.
16.3.8.2
Runtime Considerations
In addition to the instruction-based considerations, runtime events may cause transactional execution to abort.
These may be due to data access patterns or micro-architectural implementation causes. Keep in mind that the
following list is not a comprehensive discussion of all abort causes.
Any fault or trap in a transactional region that must be exposed to software will be suppressed. Transactional
execution will abort and execution will transition to a non-transactional execution, as if the fault or trap had never
occurred. If any exception is not masked, that will result in a transactional abort and it will be as if the exception
had never occurred.
When executed in VMX non-root operation, certain instructions may result in a VM exit. When such instructions are
executed inside a transactional region, then instead of causing a VM exit, they will cause a transactional abort and
the execution will appear as if instruction that would have caused a VM exit never executed.
Synchronous exception events (#DE, #OF, #NP, #SS, #GP, #BR, #UD, #AC, #XM, #PF, #NM, #TS, #MF, #DB,
#BP/INT3) that occur during transactional execution may cause an execution not to commit transactionally, and
require a non-transactional execution. These events are suppressed as if they had never occurred. With HLE, since
the non-transactional code path is identical to the transactional code path, these events will typically re-appear
when the instruction that caused the exception is re-executed non-transactionally, causing the associated synchronous events to be delivered appropriately in the non-transactional execution. The same behavior also applies to
synchronous events (EPT violations, EPT misconfigurations, and accesses to the APIC-access page) that occur in
VMX non-root operation.
Asynchronous events (NMI, SMI, INTR, IPI, PMI, etc.) occurring during transactional execution may cause the
transactional execution to abort and transition to a non-transactional execution. The asynchronous events will be
pended and handled after the transactional abort is processed. The same behavior also applies to asynchronous
events (VMX-preemption timer expiry, virtual-interrupt delivery, and interrupt-window exiting) that occur in VMX
non-root operation.
Transactional execution only supports write-back cacheable memory type operations. A transactional region may
always abort if it includes operations on any other memory type. This includes instruction fetches to UC memory
type.
Memory accesses within a transactional region may require the processor to set the Accessed and Dirty flags of the
referenced page table entry. The behavior of how the processor handles this is implementation specific. Some
implementations may allow the updates to these flags to become externally visible even if the transactional region
subsequently aborts. Some Intel TSX implementations may choose to abort the transactional execution if these
flags need to be updated. Further, a processor's page-table walk may generate accesses to its own transactionally
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written but uncommitted state. Some Intel TSX implementations may choose to abort the execution of a transactional region in such situations. Regardless, the architecture ensures that, if the transactional region aborts, then
the transactionally written state will not be made architecturally visible through the behavior of structures such as
TLBs.
Executing self-modifying code transactionally may also cause transactional aborts. Programmers must continue to
follow the Intel recommended guidelines for writing self-modifying and cross-modifying code even when employing
Intel TSX.
While an Intel TSX implementation will typically provide sufficient resources for executing common transactional
regions, implementation constraints and excessive sizes for transactional regions may cause a transactional execution to abort and transition to a non-transactional execution. The architecture provides no guarantee of the amount
of resources available to do transactional execution and does not guarantee that a transactional execution will ever
succeed.
Conflicting requests to a cache line accessed within a transactional region may prevent the transactional region
from executing successfully. For example, if logical processor P0 reads line A in a transactional region and another
logical processor P1 writes A (either inside or outside a transactional region) then logical processor P0 may abort if
logical processor P1’s write interferes with processor P0's ability to execute transactionally. Similarly, if P0 writes
line A in a transactional region and P1reads or writes A (either inside or outside a transactional region), then P0
may abort if P1's access to A interferes with P0's ability to execute transactionally. In addition, other coherence
traffic may at times appear as conflicting requests and may cause aborts. While these false conflicts may happen,
they are expected to be uncommon. The conflict resolution policy to determine whether P0 or P1 aborts in the
above scenarios is implementation specific.
16-8 Vol. 1
CHAPTER 17
INTEL® MEMORY PROTECTION EXTENSIONS
17.1
INTEL® MEMORY PROTECTION EXTENSIONS (INTEL® MPX)
®
Intel Memory Protection Extensions (Intel® MPX) is a new capability introduced into Intel Architecture. Intel
MPX can increase the robustness of software when it is used in conjunction with compiler changes to check memory references, for those references whose compile-time normal intentions are usurped at runtime due to buffer
overflow or underflow. Two of the most important goals of Intel MPX are to provide this capability at low performance overhead for newly compiled code, and to provide compatibility mechanisms with legacy software components. A direct benefit Intel MPX provides is hardening software against malicious attacks designed to cause
or exploit buffer overruns. This chapter describes the software visible interfaces of this extension.
17.2
INTRODUCTION
Intel MPX is designed to allow a system (i.e., the logical processor(s) and the OS software) to run both Intel MPX
enabled software and legacy software (written for processors without Intel MPX). When executing software
containing a mixture of Intel MPX-unaware code (legacy code) and Intel MPX-enabled code, the legacy code does
not benefit from Intel MPX, but it also does not experience any change in functionality or reduction in performance.
The performance of Intel MPX-enabled code running on processors that do not support Intel MPX may be similar to
the use of embedding NOPs in the instruction stream.
Intel MPX is designed such that an Intel MPX enabled application can link with, call into, or be called from legacy
software (libraries, etc.) while maintaining existing application binary interfaces (ABIs). And in most cases, the
benefit of Intel MPX requires minimal changes to the source code at the application programming interfaces (APIs)
to legacy library/applications. As described later, Intel MPX associates bounds with pointers in a novel manner,
and the Intel MPX hardware uses bounds to check that the pointer based accesses are suitably constrained. Intel
MPX enabled software is not required to uniformly or universally utilize the new hardware capabilities over all
memory references. Specifically, programmers can selectively use Intel MPX to protect a subset of pointers.
The code enabled for Intel MPX benefits from memory protection against vulnerability such as buffer overrun.
Therefore there is a heightened incentive for software vendors to adopt this technology. At the same time, the
security benefit of Intel MPX-protection can be implemented according to the business priorities of software
vendors. A software vendor can choose to adopt Intel MPX in some modules to realize partial benefit from Intel MPX
quickly, and introduce Intel MPX in other modules in phases (e.g. some programmer intervention might be required
at the interface to legacy calls). This adaptive property of Intel MPX is designed to give software vendors control on
their schedule and modularity of adoption. It also allows a software vendor to secure defense for higher priority or
more attack-prone software first; and allows the use of Intel MPX features in one phase of software engineering
(e.g., testing) and not in another (e.g., general release) as dictated by business realities.
The initial goal of Intel MPX is twofold: (1) provide means to defend a system against attacks that originate
external to some trust perimeter where the trust perimeter subsumes the system memory and integral data repositories, and (2) provide means to pinpoint accidental logic defects in pointer usage, by undergirding memory references with hardware based pointer validation.
As with any instruction set extensions, Intel MPX can be used by application developers beyond detecting buffer
overflow, the processor does not limit the use of Intel MPX for buffer overflow detection.
17.3
INTEL MPX PROGRAMMING ENVIRONMENT
Intel MPX introduces new bounds registers and new instructions that operate on bounds registers. Intel MPX
allows an OS to support user mode software (operating at CPL=3) and supervisor mode software (CPL < 3) to add
memory protection capability against buffer overrun. It provides controls to enable Intel MPX extensions for user
mode and supervisor mode independently. Intel MPX extensions are designed to allow software to associate
bounds with pointers, and allow software to check memory references against the bounds associated with the
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pointer to prevent out of bound memory access (thus preventing buffer overflow).The bounds registers hold lower
bound and upper bound that can be checked when referencing memory. An out-of-bounds memory reference then
causes a #BR exception. Intel MPX also introduces configuration facilities that the OS must manage to support
enabling of user-mode (and/or supervisor-mode) software operations using bounds registers.
17.3.1
Detection and Enumeration of Intel MPX Interfaces
Detection of hardware support for processor extended state component is provided by the main CPUID leaf function 0DH with index ECX = 0. Specifically, the return value in EDX:EAX of CPUID.(EAX=0DH, ECX=0) provides a
64-bit wide bit vector of hardware support of processor state components.
If CPUID.(EAX=07H,ECX=0H):EBX.MPX[bit 14] = 1 (the processor supports Intel MPX),
CPUID.(EAX=0DH,ECX=0):EAX[bits 4:3] will enumerate the XSAVE state components associated with Intel MPX.
These two component states of Intel MPX are the following:
•
BNDREGS: CPUID.(EAX=0DH,ECX=0):EAX[3] indicates XCR0.BNDREGS[bit 3] is supported. This bit indicates
bound register component of Intel MPX state, comprised of four bounds registers, BND0-BND3 (see Section
17.3.2).
•
BNDCSR: CPUID.(EAX=0DH,ECX=0):EAX[4] indicates XCR0.BNDCSR[bit 4] is supported. This bit indicates
bounds configuration and status component of Intel MPX comprised of BNDCFGU and BNDSTATUS. OS must
enable both BNDCSR and BNDREGS bits in XCR0 to ensure full Intel MPX support to applications.
•
The size of the processor state component, enabled by XCR0.BNDREGS, is enumerated by
CPUID.(EAX=0DH,ECX=03H).EAX[31:0] and the byte offset of this component relative to the beginning of the
XSAVE/XRSTOR area is reported by CPUID.(EAX=0DH, ECX=03H).EBX[31:0].
•
The size of the processor state component, enabled by XCR0.BNDCSR, is enumerated by
CPUID.(EAX=0DH,ECX=04H).EAX[31:0] and the byte offset of this component relative to the beginning of the
XSAVE/XRSTOR area is reported by CPUID.(EAX=0DH, ECX=04H).EBX[31:0].
On processors that support Intel MPX, CPUID.(EAX=0DH,ECX=0):EAX[3] and CPUID.(EAX=0DH,ECX=0):EAX[4]
will both be 1. On processors that do not support Intel MPX, CPUID.(EAX=0DH,ECX=0):EAX[3] and
CPUID.(EAX=0DH,ECX=0):EAX[4] will both be 0.
The layout of XCR0 for extended processor state components defined in Intel Architecture is shown in Figure 2-8 of
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Enabling Intel MPX requires an OS to manage bits [4:3] of XCR0; see Section 13.5.
The BNDLDX and BNDSTX instructions (Section 17.4.3) each take an operand whose bits are used to traverse data
structures in memory. In 64-bit mode, these instructions operate only on the lower bits in the supplied 64-bit
addresses. The number of bits used is 48 plus a value called the MPX address-width adjust (MAWA). The MAWA
value depends on CPL:
•
•
If CPL < 3, the supervisor MAWA (MAWAS) is used. This value is 0.
If CPL = 3, the user MAWA (MAWAU) is used. The value of MAWAU is enumerated in
CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17].
(Outside of 64-bit mode, BNDLDX and BNDSTX use the entire 32 bits of the supplied linear-address operands.)
17.3.2
Bounds Registers
Intel MPX Architecture defines four new registers, BND0-BND3, which Intel MPX instructions operate on. Each
bounds register stores a pair of 64-bit values which are the lower bound (LB) and upper bound (UB) of a buffer, see
Figure 17-1.
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INTEL® MEMORY PROTECTION EXTENSIONS
127
0
64 63
Lower Bound (LB)
Upper Bound (UB)
Figure 17-1. Layout of the Bounds Registers BND0-BND3
The bounds are unsigned effective addresses, and are inclusive. The upper bounds are architecturally represented
in 1/’s complement form. Lower bound = 0, and upper bound = 0 (1’s complement of all 1s) will allow access to the
entire address space. The bounds are considered as INIT when both lower and upper bounds are 0 (cover the
entire address space). The two Intel MPX instructions which operate on the upper bound (BNDMK and BNDCU)
account for the 1’s complement representation of the upper bounds.
The instruction set does not impose any conventions on the use of bounds registers. Software has full flexibility
associating pointers to bounds registers including sharing them for multiple pointers.
RESET or INIT# will initialize (write zero to) BND0–BND3.
17.3.3
Configuration and Status Registers
Intel MPX defines two configuration registers and one status register. The two configuration registers are defined
for user mode (CPL = 3) and supervisor mode (CPL < 3). The user-mode configuration register BNDCFGU is accessible only with the XSAVE feature set instructions.
The supervisor mode configuration register is an MSR, referred to as IA32_BNDCFGS (MSR 0D90H). Because both
configuration registers share a common layout (see Figure 17-2), when describing the common behavior, these
configuration registers are often denoted as BNDCFGx, where x can be U or S, for user and supervisor mode
respectively.
63
2 1
12 11
Base of Bound Directory (Linear Address)
Reserved (must be zero)
0
En
Bprv: BNDPRESERVE
En: Enable
Figure 17-2. Common Layout of the Bound Configuration Registers BNDCFGU and BNDCFGS
The Enable bit in BNDCFGU enables Intel MPX in user mode (CPL = 3), and the Enable bit in BNDCFGS enables Intel
MPX in supervisor mode (CPL < 3). The BNDPRESERVE bit controls the initialization behavior of CALL/RET/JMP/Jcc
instructions without the BND (F2H) prefix -- see Section 17.5.3.
WRMSR to BNDCFGS will #GP if any of the reserved bits of BNDCFGS is not zero or if the base address of the bound
directory is not canonical. XRSTOR of BNDCFGU ignores the reserved bits and does not fault if any is non-zero;
similarly, it ignores the upper bits of the base address of the bound directory and sign-extends the highest implemented bit of the linear address to guarantee the canonicality of this address.
Intel MPX also defines a status register (BNDSTATUS) primarily used to communicate status information for #BR
exception. The layout of the status register is shown in Figure 17-3.
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INTEL® MEMORY PROTECTION EXTENSIONS
2 1 0
63
ABD: Address Bound Directory Entry - Linear Address
EC: Error Code
Figure 17-3. Layout of the Bound Status Registers BNDSTATUS
The BNDSTATUS register provides two fields to communicate the status of Intel MPX operations:
•
EC (bits 1:0): The error code field communicates status information of a bound range exception #BR or
operation involving bound directory.
•
ABD: (bits 63:2):The address field of a bound directory entry can provide information when operation on the
bound directory caused a #BR.
The valid error codes are defined in Table 17-1.
Table 17-1. Error Code Definition of BNDSTATUS
EC
00b1
Description
Meaning
No Intel MPX exception No exception caused by Intel MPX operations.
01b
Bounds violation
#BR caused by BNDCL, BNDCU or BNDCN instructions;
ABD is 0.
10b
Invalid BD entry
#BR caused by BNDLDX or BNDSTX instructions, ABD will be set to the linear address of the
invalid bound-directory entry
11b
Reserved
Reserved
NOTES:
1. When legacy BOUND instruction cause a #BR with Intel MPX enabled (see Section 17.5.4), EC is written with
Zero.
RESET or INIT# will set BNDCFGx and BNDSTATUS registers to zero.
17.3.4
Read and Write of IA32_BNDCFGS
The RDMSR and WRMSR instructions can be used to read and write the IA32_BNDCFGS MSR. (The XSAVE state
does not include IA32_BNDCFGS, and instructions in the XSAVE feature set do not access that register). Attempts
to write to IA32_BNDCFGS check for canonicality of the addresses being loaded into IA32_BNDCFGS (regardless of
mode at the time of execution) and will #GP if the address is not canonical or if reserved bits would be set.
Software can use RDMSR and WRMSR to read and write IA32_BNDCFGS as long as the processor implements Intel
MPX, i.e. CPUID.(EAX=07H, ECX=0H).EBX.MPX = 1. The states of CR4 and XCR0 have no impact on the ability to
access IA32_BNDCFGS.
17.4
INTEL MPX INSTRUCTION SUMMARY
When Intel MPX is not enabled or not present, all Intel MPX instructions behave as NOP. There are eight Intel MPX
instructions, Table 17-2 provides a summary.
A C/C++ compiler can implement intrinsic support for Intel MPX instructions to facilitate pointer operation with
capability of checking for valid bounds on pointers. Typically, Intel MPX intrinsics are implemented by compiler via
inline code generation where bounds register allocations are handled by the compiler without requiring the
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INTEL® MEMORY PROTECTION EXTENSIONS
programmer to directly manipulate any bounds registers. Therefore no new data type for a bounds register is
needed in the syntax of Intel MPX intrinsics.
Table 17-2. Intel MPX Instruction Summary
Intel MPX
Instruction
Description
BNDMK b, m
Create LowerBound (LB) and UpperBound (UB) in the bounds register b
BNDCL b, r/m
Checks the address of a memory reference or address in r against the lower bound
BNDCU b, r/m
Checks the address of a memory reference or address in r against the upper bound in 1's complement form
BNDCN b, r/m
Checks the address of a memory reference or address in r against the upper bound not in 1's complement
form
BNDMOV b, b/m
Copy/load LB and UB bounds from memory or a bounds register
BNDMOV b/m, b
Store LB and UB bounds in a bounds register to memory or another register
BNDLDX b, mib
Load bounds using address translation using an sib-addressing expression mib
BNDSTX mib, b
Store bounds using address translation using an sib-addressing expression mib
17.4.1
Instruction Encoding
All Intel MPX instructions are NOP on processors that report CPUID.(EAX=07H, ECX=0H).EBX.MPX [bit 14] = 0, or
if Intel MPX is not enabled by the operating system (see Section 13.5). Applications can selectively opt-in to use
Intel MPX instructions.
All Intel MPX opcodes encoded to operate on BND0-BND3 are valid Intel MPX instructions. All Intel MPX opcodes
encoded to operate on bound registers beyond BND3 will #UD if Intel MPX is enabled.
BNDLDX/BNDSTX opcodes require 66H as a mandatory prefix with its operand size tied to the address size attribute of the supported operating modes. Attempt to override operand size attribute with 66H or with REX.W in 64bit mode is ignored.
17.4.2
Usage and Examples
BNDMK is typically used after memory is allocated for a buffer, e.g., by functions such as malloc, calloc, or when
the memory is allocated on the stack. However, many other usages are possible such as when accessing an array
member of a structure.
Example 17-1. BNDMK Example Usage in Application and Library Code
int A[100]; //assume the array A is allocated on the stack at ‘offset’
from RBP.
// the instruction to store starting address of array will be:
LEA RAX, [RBP+offset]
// the instruction to create the bounds for array A will be:
BNDMK BND0, [RAX+399]
// Store RAX into BND0.LB, and ~(RAX+399) into BND0.UB.
// similarly, for a library implementation of dynamic allocated
memory
int * k = malloc(100);
// assuming that malloc returns pointer k in RAX and holds (size
- 1) in RCX
// the malloc implementation will execute the following
instruction before returning:
BNDMK BND0, [RAX+RCX]
// BND0.LB stores RAX, and BND0.UB stores ~(RAX+RCX)
BNDMOV is typically used to copy bounds from one bound register to another when a pointer is copied from one
general purpose register to another, or to spill/fill bounds into memory corresponding to a spill/fill of a pointer.
Example 17-2. BNDMOV Example
Spilling or caller save of bound register would use BNDMOV [RBP+ offset], BNDx.
Assuming that the calling convention is that bound of first pointer is passed in BND0, and that bound happens to be in BND3 before
the call, the software will add instruction BNDMOV BND0, BND3 prior to the call.
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INTEL® MEMORY PROTECTION EXTENSIONS
BNDCL/BNDCU/BNDCN are typically used before writing to a buffer but can be used in other instances as well. If
there are no bounds violations as a result of bound check instruction, the processor will proceed to execute the next
instruction. However, if the bound check fails, it will signal #BR exception (fault).
Typically, the pointer used to write to memory will be compared against lower bound. However, for upper bound
check, the software must add the (operand size - 1) to the pointer before upper bound checking.
For example, the software intend to write 32-bit integer in 64-bit mode into a buffer at address specified in RAX,
and the bounds are in register BND0, the instruction sequence will be:
BNDCL BND0, [RAX]
BNDCU BND0, [RAX+3] ; operand size is 4
MOV Dword ptr [RAX], RBX ; RBX has the data to be written to the buffer.
Software may move one of the two bound checks out of a loop if it can determine that memory is accessed strictly
in ascending or descending order. For string instructions of the form REP MOVS, the software may choose to do
check lower bound against first access and upper bound against last access to memory. However, if software wants
to also check for wrap around conditions as part of address computation, it should check for both upper and lower
bound for first and last instructions (total of four bound checks).
BNDSTX is used to store the bounds associated with a buffer and the “pointer value” of the pointer to that buffer
onto a bound table entry via address translation using a two-level structure, see Section 17.4.3.
For example, the software has a buffer with bounds stored in BND0, the pointer to the buffer is in ESI, the following
sequence will store the “pointer value” (the buffer) and the bounds into a configured bound table entry using
address translation from the linear address associated with the base of a SIB-addressing form consisting of a base
register and a index register:
MOV ECX, Dword ptr [ESI] ; store the pointer value in the index register ECX
MOV EAX, ESI ; store the pointer in the base register EAX
BNDSTX Dword ptr [EAX+ECX], BND0 ; perform address translation from the linear address of the base
EAX and store bounds and pointer value ECX onto a bound table entry.
Similarly to retrieve a buffer and its associated bounds from a bound table entry:
MOV EAX, dword ptr [EBX] ;
BNDLDX BND0, dword ptr [EBX+EAX]; perform address translation from the linear address of the base EBX,
and loads bounds and pointer value from a bound table entry
17.4.3
Loading and Storing Bounds in Memory
Intel MPX defines two instructions to load and store of the linear address of a pointer to a buffer, along with the
bounds of the buffer into a data structure of extended bounds. When storing these extended bounds, the processor
parses the address of the pointer (where it is stored) to locate an entry in a bound table in which to store the
extended bounds. Loading of an extended bounds performs the reverse sequence.
The memory representation of an extended bound is a 4-tuple consisting of lower bound, upper bound, pointer
value and a reserved field (for use by future versions of Intel MPX; software must not use this field). Accesses to
these extended bounds use 32-bit or 64-bit operands according to the current paging mode. Thus, a bound table
entry is 4*64 bits (32 bytes) in 64-bit mode and 4*32 bits (16 bytes) outside 64-bit mode The linear address of a
bound table is stored in a bound-directory entry (BDE). The linear address of the bound directory is derived from
either BNDCFGU (CPL = 3) or BNDCFGS (CPL < 3).
The bound directory and bound tables are stored in application memory and are allocated by the application (in
case of kernel use, the structures will be in kernel memory). The bound directory and each bound table are in
contiguous linear memory.
Software should take care to allocate sufficient memory for the bound directory and the bound tables. The amount
of memory required depends on the current operating mode and, in some cases, on CPL:
•
In 64-bit mode:
— Each bound table comprises of 217 32-byte entries thus, the size of a bound table in 64-bit mode is
4 MBytes.
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INTEL® MEMORY PROTECTION EXTENSIONS
— The size of the bound directory depends on the value of MAWA. Specifically, the bound directory comprises
of 228+MAWA 64-bit entries; thus, the size of a bound directory in 64-bit mode is 21+MAWA GBytes. The value
of MAWA depends on CPL:
•
If CPL < 3, the supervisor MAWA (MAWAS) is used. This value is 0. Thus, when CPL < 3, a bound
directory comprises of 228 64-bit entries and the size of a bound directory is 2 GBytes.
•
If CPL = 3, the user MAWA (MAWAU) is used. The value of MAWAU is enumerated in
CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. When CPL = 3, a bound directory comprises of
228+MAWAU 64-bit entries and the size of a bound directory is 21+MAWAU GBytes.
NOTE
Software operating with CPL = 3 in 64-bit mode should use CPUID to determine the proper amount
of memory to allocate for the bound directory.
•
Outside 64-bit mode:
— Each bound table comprises of 210 16-byte entries; thus, the size of a bound table outside 64-bit mode is
16 KBytes.
— The bound directory comprises of 220 32-bit entries; thus, the size of a bound directory outside 64-bit
mode is 4 MBytes. This size is independent of MAWA and CPL.
Bounds in memory are associated with the memory address where the pointer is stored, i.e., Ap. A linear address
LAp is computed by adding the appropriate segment base to Ap. (Note: for these instructions, the segment override applies only to the computation.) Section 17.4.3.1 and Section 17.4.3.2 describe how BNDLDX and BNDSTX
parse LAp to locate a bound-directory entry (BDE), which contains the address of a bound table, and then a boundtable entry (BTE), which contains the extended bounds for the pointer.
17.4.3.1
BNDLDX and BNDSTX in 64-Bit Mode
Figure 17-4 shows the two-level structures for address translation of extended bounds in 64-bit mode.
BNDCFGU/BNDCFGS
12 11
63
0
Base of Bound Directory (Linear Address)
63
12
BNDCFGx[63:12]
0
0
63
Linear Address of “pointer” (LAp)
20 19
47+MAWA
30+MAWA
3
LAp[47+MAWA:20]
LAp[19:3]
0
0
5
21
0
3
0
0
Reserved
Pointer Value
Upper Bound
Lower Bound
22
64
31+MAWA
24
16
8
0
Bound Table Entries
Bound Directory Entries
0
Bound Directory (21+MAWA GBytes)
61
0
Bound Table (4 MBytes)
Figure 17-4. Bound Paging Structure and Address Translation in 64-Bit Mode
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INTEL® MEMORY PROTECTION EXTENSIONS
As noted earlier, the linear address of the bound directory is derived from either BNDCFGU (CPL = 3) or BNDCFGS
(CPL < 3). In 64-bit mode, each bound-directory entry (BDE) is 8 bytes. The number of entries in the bound directory is determined by the MPX address-width adjust (MAWA; see Section 17.3.1). Specifically, the number of
entries is 228+MAWA.
In 64-bit mode, the processor uses the two-level structures to access extended bounds as follows:
•
A bound directory is located at the 4-KByte aligned linear address specified in bits 63:12 of BNDCFGx (see
Figure 17-2). A bound directory comprises of 228+MAWA 64-bit entries (BDEs); thus, the size of a bound
directory in 64-bit mode is 21+MAWA GBytes. A BDE is selected using the LAp (linear address of pointer to a
buffer) to construct a 64-bit offset as follows:
— bits 63:31+MAWA are 0;
— bits 30+MAWA:3 are LAp[47+MAWA:20]; and
— bits 2:0 are 0.
The address of the BDE is the sum of the bound-directory base address (from BNDCFGx) plus this 64-bit offset.
•
Bit 0 of a BDE is a valid bit. If this bit is 0, use of the BDE by BNDLDX or BNDSTX causes #BR, sets
BNDSTATUS[1:0] to 10b (the error code), and loads BNDSTATUS[63:2] with bits 63:2 of the linear address of
the BDE. Otherwise, the processor uses bits 63:3 of the BDE as the 8-byte aligned address of a bound table
(BT); the processor ignores bits 2:1 of a BDE.
A bound table comprises of 217 32-byte entries (BTEs); thus, the size of a bound table in 64-bit mode is
4 MBytes. A BTE is selected using the LAp (linear address of pointer to a buffer) to construct an offset as
follows:
— bits 21:5 are LAp[19:3]; and
— bits 4:0 are 0.
The address of the BTE is the sum of the bound-table base address (from the BDE) plus this offset.
•
Each BTE comprises the following:
— a 64-bit lower bound (LB) field;
— a 64-bit upper bound (UB) field;
— a 64-bit pointer value; and
— a 64-bit reserved field. This field is reserved for future Intel MPX; software must not use it.
17.4.3.2
BNDLDX and BNDSTX Outside 64-Bit Mode
Figure 17-5 shows the two-level structures for address translation of extended bounds outside 64-bit mode.
As noted earlier, the linear address of the bound directory is derived from either BNDCFGU (CPL = 3) or BNDCFGS
(CPL < 3). Outside 64-bit mode, each bound-directory entry (BDE) is 4 bytes. The number of entries in the bound
directory is 220.
Outside 64-bit mode, the processor uses the two-level structures to access extended bounds as follows:
•
A bound directory is located at the 4-KByte aligned linear address specified in bits 31:12 of BNDCFGx (see
Figure 17-2). A bound directory comprises of 220 32-bit entries (BDEs); thus, the size of a bound directory
outside 64-bit mode is 4 MBytes. A BDE is selected using the LAp (linear address of pointer to a buffer) to
construct an offset as follows:
— bits 21:2 are LAp[31:12]; and
— bits 1:0 are 0.
The address of the BDE is the sum of the bound-directory base address (from BNDCFGx) plus this offset.
•
Bit 0 of a BDE is a valid bit. If this bit is 0, use of the BDE by BNDLDX or BNDSTX causes #BR, sets
BNDSTATUS[1:0] to 10b (the error code), and loads BNDSTATUS[31:2] with bits 31:2 of the linear address of
the BDE. Otherwise, the processor uses bits 31:2 of the BDE as the 4-byte aligned address of a bound table
(BT); the processor ignores bit 1 of a BDE.
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INTEL® MEMORY PROTECTION EXTENSIONS
BNDCFGU/BNDCFGS
12 11
31
0
Base of Bound Directory (Linear Address)
31
12
BNDCFGx[31:12]
0
0
Linear Address of “pointer” (LAp)
12 11
31
21
2
LAp[31:12]
LAp[11:2]
0
0
4
13
0
2
0
0
Reserved
Pointer Value
Upper Bound
Lower Bound
14
32
22
12
8
4
0
Bound Table Entries
Bound Directory Entries
30
0
Bound Directory (4 MBytes)
0
Bound Table (16 KBytes)
Figure 17-5. Bound Paging Structure and Address Translation Outside 64-Bit Mode
A bound table comprises of 210 16-byte entries (BTEs); thus, the size of a bound table outside 64-bit mode is
16 KBytes. A BTE is selected using the LAp (linear address of pointer to a buffer) to construct an offset as
follows:
— bits 13:4 are LAp[11:2]; and
— bits 3:0 are 0.
The address of the BTE is the sum of the bound-table base address (from the BDE) plus this offset. This address
is use as an offset into the DS segment to determine the linear address of the BTE.
•
Each BTE comprises the following:
— a 32-bit lower bound (LB) field;
— a 32-bit upper bound (UB) field;
— a 32-bit pointer value; and
— a 32-bit reserved field. This field is reserved for future Intel MPX; software must not use it.
17.5
INTERACTIONS WITH INTEL MPX
17.5.1
Intel MPX and Operating Modes
In 64-bit Mode, all Intel MPX instructions use 64-bit operands for bounds and 64 bit addressing, i.e. REX.W & 67H
have no effect on data or address size.
XSAVE, XSAVEOPT and XRSTOR load/store 64-bit values in all modes, as these state-management instructions are
not Intel MPX instructions.
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INTEL® MEMORY PROTECTION EXTENSIONS
In compatibility and legacy modes (including 16-bit code segments, real and virtual 8086 modes) all Intel MPX
instructions use 32-bit operands for bounds and 32 bit addressing. The upper 32-bits of destination bound register
are cleared (consistent with behavior of integer registers)
In 32-bit and compatibility mode, the bounds are 32-bit, and are treated same as 32-bit integer registers. Therefore, when 32-bit bound is updated in a bound register, the upper 32-bits are undefined. When switching from 64bit, the behavior of content of bounds register will be similar to that of general purpose registers.
Table 17-3 describes the impact of 67H prefix on memory forms of Intel MPX instructions (register-only forms
ignore 67H prefix) when Intel MPX is enabled:
Table 17-3. Effective Address Size of Intel MPX Instructions with 67H Prefix
Addressing Mode
67H Prefix
64-bit Mode
Y
64 bit addressing used
64-bit Mode
N
64 bit addressing used
32-bit Mode
Y
#UD
32-bit Mode
N
32 bit addressing used
16-bit Mode
Y
32 bit addressing used
16-bit Mode
N
#UD
17.5.2
Effective Address Size used for Intel MPX instructions when Intel MPX is enabled
Intel MPX Support for Pointer Operations with Branching
Intel MPX provides flexibility in supporting pointer operation across control flow changes. Intel MPX allows
•
compatibility with legacy code that may perform pointer operation across control flow changes and are unaware
of Intel MPX, along with
•
Intel MPX-aware code that adds bounds checking protection to pointer operation across control flow changes.
The interface to provide such flexibility consists of:
•
•
Using a prefix, referred to as BND prefix, to relevant branch instructions: CALL, RET, JMP and Jcc
BNDCFGU and BNDCFGS provides the bit field, BNDPRESERVE (bit 1).
The value of BNDPRESERVE in conjunction with the presence/absence the BND prefix with those branching instruction will determine whether the values in BND0-BND3 will be initialized or unchanged.
17.5.3
CALL, RET, JMP and All Jcc
An application compiled to use Intel MPX will use the REPNE (F2H) prefix (denoted by BND) for all forms of near
CALL, near RET, near JMP, short & near Jcc instructions (BND+CALL, BND+RET, BND+JMP, BND+Jcc). See Table
17-4 for specific opcodes. All far CALL, RET and JMP instructions plus short JMP (JMP rel 8, opcode EB) instructions
will never cause bound registers to be initialized.
If BNDPRESERVE bit is one, above instructions will NOT INIT the bounds registers when BND prefix is not present
for above instructions (legacy behavior). However, If BNDPRESERVE is zero, above instructions will INIT ALL bound
registers (BND0-BND3) when BND prefix is not present for above instructions. If BND prefix is present for above
instructions, the BND registers will NOT INIT any bound registers (BND0-BND3).
The legacy code will continue to use non-prefixed forms of these instructions, so if BNDPRESERVE is zero, all the
bound registers will INIT by legacy code. This allows the legacy function to execute and return to callee with all
bound registers initialized (legacy code by definition cannot make or load bounds in bound registers because it does
not have Intel MPX instructions). This will eliminate compatibility concerns when legacy function might have
changed the pointer in registers but did not update the value of the bounds registers associated with these
pointers.
If BNDCFGx.BNDPRESERVE is clear then non-prefixed forms of these instructions will initialize all the bound registers. If this bit is set then non-prefixed and prefixed forms of these instructions will preserve the contents of bound
registers as shown in Table 17-4.
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INTEL® MEMORY PROTECTION EXTENSIONS
Table 17-4. Bounds Register INIT Behavior Due to BND Prefix with Branch Instructions
17.5.4
Instruction
Branch Instruction Opcodes
CALL
E8, FF/2
BND + CALL
F2 E8, F2 FF/2
RET
C2, C3
BND + RET
F2 C2, F2 C3
JMP
E9, FF/4
BND + JMP
F2 E9, F2 FF/4
Jcc
70 through 7F,
0F 80 through 0F 8F
BND + Jcc
F2 70 through F2 7F,
F2 0F 80 through F2 0F 8F
BNDPRESERVE = 0
BNDPRESERVE = 1
Init BND0-BND3
BND0-BND3 unchanged
BND0-BND3 unchanged
BND0-BND3 unchanged
Init BND0-BND3
BND0-BND3 unchanged
BND0-BND3 unchanged
BND0-BND3 unchanged
Init BND0-BND3
BND0-BND3 unchanged
BND0-BND3 unchanged
BND0-BND3 unchanged
Init BND0-BND3
BND0-BND3 unchanged
BND0-BND3 unchanged
BND0-BND3 unchanged
BOUND Instruction and Intel MPX
If Intel MPX in enabled (see Section 13.5) and a #BR was caused due to a BOUND instruction, then BOUND instruction will write zero to the BNDSTATUS register. In all other situations, BOUND instruction will not modify
BNDSTATUS. Specifically, the operation of the BOUND instruction can be described as:
IF ( ( BOUND instruction caused #BR) AND ( CR4.OXXSAVE =1 AND XCR0.BNDREGS=1 AND XCR0.BNDCSR =1) AND
( (CPL=3 AND BNDCFGU.ENABLE = 1) OR (CPL < 3 AND BNDCFGS.ENABLE = 1) ) ) THEN
BNDSTATUS 0;
ELSE
BNDSTATUS is not modified;
FI;
17.5.5
Programming Considerations
Intel MPX instruction set does not dictate any calling convention, but allows the calling convention extensions to be
interoperable with legacy code by making use of the of the bound registers and the bound tables to convey arguments and return values.
17.5.6
Intel MPX and System Manage Mode
Upon delivery of an SMI to a processor supporting Intel MPX, the contents of IA32_BNDCFGS is saved to SMM state
save map (at offset 7ED0H) and the register is then cleared when entering into SMM. RSM restores IA32_BNDCFGS
from the SMM state save map. The instruction forces the reserved bits (11:2) to 0 and sign-extends the highest
implemented bit of the linear address to guarantee the canonicality of this address (regardless of what is in SMM
state save map).
The content of IA32_BNDCFGS is cleared after entering into SMM. Thus, Intel MPX is disabled inside an SMM
handler until SMM code enables it explicitly. This will prevent the side-effect of INIT-ing bound registers by legacy
CALL/RET/JMP/Jcc in SMM code.
17.5.7
Support of Intel MPX in VMCS
A new guest-state field for IA32_BNDCFGS is added to the VMCS. In addition, two new controls are added:
•
•
a VM-exit control called “clear BNDCFGS”
a VM-entry control called “load BNDCFGS.”
Vol. 1 17-11
INTEL® MEMORY PROTECTION EXTENSIONS
VM exits always save IA32_BNDCFGS into BNDCFGS field of VMCS; if “clear BNDCFGS” is 1, VM exits clear
IA32_BNDCFGS. If “load BNDCFGS” is 1, VM entry loads IA32_BNDCFGS from VMCS. If loading IA32_BNDCFGS,
VM entry should check the value of that register in the guest-state area of the VMCS and cause the VM entry to fail
(late) if the value is one that would causes WRMSR to fault if executed in ring 0.
17.5.8
Support of Intel MPX in Intel TSX
For some processor implementations, the following Intel MPX instructions may always cause transactional aborts:
•
An Intel TSX transaction abort will occur in case of legacy branch (that causes bounds registers INIT) when at
least one bounds register was in a NON-INIT state.
•
An Intel TSX transaction abort will occur in case of a BNDLDX & BNDSTX instruction on non-flat segment.
Intel MPX Instructions (including BND prefix + branch instructions) not enumerated above as causing transactional
abort when used inside a transaction will typically not cause an Intel TSX transaction to abort.
17-12 Vol. 1
CHAPTER 18
INPUT/OUTPUT
In addition to transferring data to and from external memory, IA-32 processors can also transfer data to and from
input/output ports (I/O ports). I/O ports are created in system hardware by circuity that decodes the control, data,
and address pins on the processor. These I/O ports are then configured to communicate with peripheral devices. An
I/O port can be an input port, an output port, or a bidirectional port. Some I/O ports are used for transmitting data,
such as to and from the transmit and receive registers, respectively, of a serial interface device. Other I/O ports are
used to control peripheral devices, such as the control registers of a disk controller.
This chapter describes the processor’s I/O architecture. The topics discussed include:
•
•
•
I/O port addressing
I/O instructions
I/O protection mechanism
18.1
I/O PORT ADDRESSING
The processor permits applications to access I/O ports in either of two ways:
•
•
Through a separate I/O address space
Through memory-mapped I/O
Accessing I/O ports through the I/O address space is handled through a set of I/O instructions and a special I/O
protection mechanism. Accessing I/O ports through memory-mapped I/O is handled with the processor’s generalpurpose move and string instructions, with protection provided through segmentation or paging. I/O ports can be
mapped so that they appear in the I/O address space or the physical-memory address space (memory mapped
I/O) or both.
One benefit of using the I/O address space is that writes to I/O ports are guaranteed to be completed before the
next instruction in the instruction stream is executed. Thus, I/O writes to control system hardware cause the hardware to be set to its new state before any other instructions are executed. See Section 18.6, “Ordering I/O,” for
more information on serializing of I/O operations.
18.2
I/O PORT HARDWARE
From a hardware point of view, I/O addressing is handled through the processor’s address lines. For the P6 family,
Pentium 4, and Intel Xeon processors, the request command lines signal whether the address lines are being driven
with a memory address or an I/O address; for Pentium processors and earlier IA-32 processors, the M/IO# pin indicates a memory address (1) or an I/O address (0). When the separate I/O address space is selected, it is the
responsibility of the hardware to decode the memory-I/O bus transaction to select I/O ports rather than memory.
Data is transmitted between the processor and an I/O device through the data lines.
18.3
I/O ADDRESS SPACE
The processor’s I/O address space is separate and distinct from the physical-memory address space. The I/O
address space consists of 216 (64K) individually addressable 8-bit I/O ports, numbered 0 through FFFFH. I/O port
addresses 0F8H through 0FFH are reserved. Do not assign I/O ports to these addresses. The result of an attempt
to address beyond the I/O address space limit of FFFFH is implementation-specific; see the Developer’s Manuals for
specific processors for more details.
Any two consecutive 8-bit ports can be treated as a 16-bit port, and any four consecutive ports can be a 32-bit port.
In this manner, the processor can transfer 8, 16, or 32 bits to or from a device in the I/O address space. Like words
in memory, 16-bit ports should be aligned to even addresses (0, 2, 4, ...) so that all 16 bits can be transferred in a
Vol. 1 18-1
INPUT/OUTPUT
single bus cycle. Likewise, 32-bit ports should be aligned to addresses that are multiples of four (0, 4, 8, ...). The
processor supports data transfers to unaligned ports, but there is a performance penalty because one or more
extra bus cycle must be used.
The exact order of bus cycles used to access unaligned ports is undefined and is not guaranteed to remain the same
in future IA-32 processors. If hardware or software requires that I/O ports be written to in a particular order, that
order must be specified explicitly. For example, to load a word-length I/O port at address 2H and then another word
port at 4H, two word-length writes must be used, rather than a single doubleword write at 2H.
Note that the processor does not mask parity errors for bus cycles to the I/O address space. Accessing I/O ports
through the I/O address space is thus a possible source of parity errors.
18.3.1
Memory-Mapped I/O
I/O devices that respond like memory components can be accessed through the processor’s physical-memory
address space (see Figure 18-1). When using memory-mapped I/O, any of the processor’s instructions that reference memory can be used to access an I/O port located at a physical-memory address. For example, the MOV
instruction can transfer data between any register and a memory-mapped I/O port. The AND, OR, and TEST
instructions may be used to manipulate bits in the control and status registers of a memory-mapped peripheral
device.
Certain instructions may take an exception or VM exit after completing a memory access (either a read or a write)
to a memory-mapped I/O address. This exception or VM exit could be due to the instruction performing multiple
memory accesses (e.g., MOVS, PUSH mem, POP mem, PUSHAD, etc.) or could be due to the ordering of exceptions
or VM exits within the instruction (e.g., a DIV mem that takes a #DE or a CALL that causes a task switch VM exit).
If software later re-executes that instruction (e.g., after an IRET or VMRESUME), the MMIO (memory-mapped I/O)
access may occur again. If the memory-mapped I/O access has a side-effect, that side-effect may be executed
each time the memory-mapped I/O access occurs. If that is problematic, software must ensure that exceptions or
VM exits do not occur after accessing the MMIO.
When using memory-mapped I/O, caching of the address space mapped for I/O operations must be prevented.
With the Pentium 4, Intel Xeon, and P6 family processors, caching of I/O accesses can be prevented by using
memory type range registers (MTRRs) to map the address space used for the memory-mapped I/O as uncacheable
(UC). See Chapter 11, “Memory Cache Control” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A, for a complete discussion of the MTRRs.
The Pentium and Intel486 processors do not support MTRRs. Instead, they provide the KEN# pin, which when held
inactive (high) prevents caching of all addresses sent out on the system bus. To use this pin, external address
decoding logic is required to block caching in specific address spaces.
Physical Memory
FFFF
EPROM
I/O Port
I/O Port
I/O Port
RAM
0
Figure 18-1. Memory-Mapped I/O
18-2 Vol. 1
INPUT/OUTPUT
All the IA-32 processors that have on-chip caches also provide the PCD (page-level cache disable) flag in page
table and page directory entries. This flag allows caching to be disabled on a page-by-page basis. See “Page-Directory and Page-Table Entries” in Chapter 4 of in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A.
18.4
I/O INSTRUCTIONS
The processor’s I/O instructions provide access to I/O ports through the I/O address space. (These instructions
cannot be used to access memory-mapped I/O ports.) There are two groups of I/O instructions:
•
Those that transfer a single item (byte, word, or doubleword) between an I/O port and a general-purpose
register
•
Those that transfer strings of items (strings of bytes, words, or doublewords) between an I/O port and memory
The register I/O instructions IN (input from I/O port) and OUT (output to I/O port) move data between I/O ports
and the EAX register (32-bit I/O), the AX register (16-bit I/O), or the AL (8-bit I/O) register. The address of the I/O
port can be given with an immediate value or a value in the DX register.
The string I/O instructions INS (input string from I/O port) and OUTS (output string to I/O port) move data
between an I/O port and a memory location. The address of the I/O port being accessed is given in the DX register;
the source or destination memory address is given in the DS:ESI or ES:EDI register, respectively.
When used with the repeat prefix REP, the INS and OUTS instructions perform string (or block) input or output
operations. The repeat prefix REP modifies the INS and OUTS instructions to transfer blocks of data between an I/O
port and memory. Here, the ESI or EDI register is incremented or decremented (according to the setting of the DF
flag in the EFLAGS register) after each byte, word, or doubleword is transferred between the selected I/O port and
memory.
See the references for IN, INS, OUT, and OUTS in Chapter 3 and Chapter 4 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volumes 2A & 2B, for more information on these instructions.
18.5
PROTECTED-MODE I/O
When the processor is running in protected mode, the following protection mechanisms regulate access to I/O
ports:
•
When accessing I/O ports through the I/O address space, two protection devices control access:
— The I/O privilege level (IOPL) field in the EFLAGS register
— The I/O permission bit map of a task state segment (TSS)
•
When accessing memory-mapped I/O ports, the normal segmentation and paging protection and the MTRRs
(in processors that support them) also affect access to I/O ports. See Chapter 5, “Protection” and Chapter 11,
“Memory Cache Control” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A,
for a complete discussion of memory protection.
The following sections describe the protection mechanisms available when accessing I/O ports in the I/O address
space with the I/O instructions.
18.5.1
I/O Privilege Level
In systems where I/O protection is used, the IOPL field in the EFLAGS register controls access to the I/O address
space by restricting use of selected instructions. This protection mechanism permits the operating system or executive to set the privilege level needed to perform I/O. In a typical protection ring model, access to the I/O address
space is restricted to privilege levels 0 and 1. Here, the kernel and the device drivers are allowed to perform I/O,
while less privileged device drivers and application programs are denied access to the I/O address space. Application programs must then make calls to the operating system to perform I/O.
The following instructions can be executed only if the current privilege level (CPL) of the program or task currently
executing is less than or equal to the IOPL: IN, INS, OUT, OUTS, CLI (clear interrupt-enable flag), and STI (set
Vol. 1 18-3
INPUT/OUTPUT
interrupt-enable flag). These instructions are called I/O sensitive instructions, because they are sensitive to the
IOPL field. Any attempt by a less privileged program or task to use an I/O sensitive instruction results in a generalprotection exception (#GP) being signaled. Because each task has its own copy of the EFLAGS register, each task
can have a different IOPL.
The I/O permission bit map in the TSS can be used to modify the effect of the IOPL on I/O sensitive instructions,
allowing access to some I/O ports by less privileged programs or tasks (see Section 18.5.2, “I/O Permission Bit
Map”).
A program or task can change its IOPL only with the POPF and IRET instructions; however, such changes are privileged. No procedure may change the current IOPL unless it is running at privilege level 0. An attempt by a less privileged procedure to change the IOPL does not result in an exception; the IOPL simply remains unchanged.
The POPF instruction also may be used to change the state of the IF flag (as can the CLI and STI instructions);
however, the POPF instruction in this case is also I/O sensitive. A procedure may use the POPF instruction to change
the setting of the IF flag only if the CPL is less than or equal to the current IOPL. An attempt by a less privileged
procedure to change the IF flag does not result in an exception; the IF flag simply remains unchanged.
18.5.2
I/O Permission Bit Map
The I/O permission bit map is a device for permitting limited access to I/O ports by less privileged programs or
tasks and for tasks operating in virtual-8086 mode. The I/O permission bit map is located in the TSS (see
Figure 18-2) for the currently running task or program. The address of the first byte of the I/O permission bit map
is given in the I/O map base address field of the TSS. The size of the I/O permission bit map and its location in the
TSS are variable.
Task State Segment (TSS)
Last byte of
bitmap must be
followed by a
byte with all
bits set.
I/O map base
must not
exceed DFFFH.
31
24 23
0
1 1 1 1 1 1 1 1
I/O Permission Bit Map
I/O Map Base
64H
0
Figure 18-2. I/O Permission Bit Map
Because each task has its own TSS, each task has its own I/O permission bit map. Access to individual I/O ports
can thus be granted to individual tasks.
If in protected mode and the CPL is less than or equal to the current IOPL, the processor allows all I/O operations
to proceed. If the CPL is greater than the IOPL or if the processor is operating in virtual-8086 mode, the processor
checks the I/O permission bit map to determine if access to a particular I/O port is allowed. Each bit in the map
corresponds to an I/O port byte address. For example, the control bit for I/O port address 29H in the I/O address
space is found at bit position 1 of the sixth byte in the bit map. Before granting I/O access, the processor tests all
the bits corresponding to the I/O port being addressed. For a doubleword access, for example, the processors tests
the four bits corresponding to the four adjacent 8-bit port addresses. If any tested bit is set, a general-protection
exception (#GP) is signaled. If all tested bits are clear, the I/O operation is allowed to proceed.
18-4 Vol. 1
INPUT/OUTPUT
Because I/O port addresses are not necessarily aligned to word and doubleword boundaries, the processor reads
two bytes from the I/O permission bit map for every access to an I/O port. To prevent exceptions from being generated when the ports with the highest addresses are accessed, an extra byte needs to be included in the TSS immediately after the table. This byte must have all of its bits set, and it must be within the segment limit.
It is not necessary for the I/O permission bit map to represent all the I/O addresses. I/O addresses not spanned by
the map are treated as if they had set bits in the map. For example, if the TSS segment limit is 10 bytes past the
bit-map base address, the map has 11 bytes and the first 80 I/O ports are mapped. Higher addresses in the I/O
address space generate exceptions.
If the I/O bit map base address is greater than or equal to the TSS segment limit, there is no I/O permission map,
and all I/O instructions generate exceptions when the CPL is greater than the current IOPL.
18.6
ORDERING I/O
When controlling I/O devices it is often important that memory and I/O operations be carried out in precisely the
order programmed. For example, a program may write a command to an I/O port, then read the status of the I/O
device from another I/O port. It is important that the status returned be the status of the device after it receives
the command, not before.
When using memory-mapped I/O, caution should be taken to avoid situations in which the programmed order is
not preserved by the processor. To optimize performance, the processor allows cacheable memory reads to be
reordered ahead of buffered writes in most situations. Internally, processor reads (cache hits) can be reordered
around buffered writes. When using memory-mapped I/O, therefore, it is possible that an I/O read might be
performed before the memory write of a previous instruction. The recommended method of enforcing program
ordering of memory-mapped I/O accesses with the Pentium 4, Intel Xeon, and P6 family processors is to use the
MTRRs to make the memory mapped I/O address space uncacheable; for the Pentium and Intel486 processors,
either the KEN# pin or the PCD flags can be used for this purpose (see Section 18.3.1, “Memory-Mapped I/O”).
When the target of a read or write is in an uncacheable region of memory, memory reordering does not occur
externally at the processor’s pins (that is, reads and writes appear in-order). Designating a memory mapped I/O
region of the address space as uncacheable insures that reads and writes of I/O devices are carried out in program
order. See Chapter 11, “Memory Cache Control” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A, for more information on using MTRRs.
Another method of enforcing program order is to insert one of the serializing instructions, such as the CPUID
instruction, between operations. See Chapter 8, “Multiple-Processor Management” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A, for more information on serialization of instructions.
It should be noted that the chip set being used to support the processor (bus controller, memory controller, and/or
I/O controller) may post writes to uncacheable memory which can lead to out-of-order execution of memory
accesses. In situations where out-of-order processing of memory accesses by the chip set can potentially cause
faulty memory-mapped I/O processing, code must be written to force synchronization and ordering of I/O operations. Serializing instructions can often be used for this purpose.
When the I/O address space is used instead of memory-mapped I/O, the situation is different in two respects:
•
The processor never buffers I/O writes. Therefore, strict ordering of I/O operations is enforced by the
processor. (As with memory-mapped I/O, it is possible for a chip set to post writes in certain I/O ranges.)
•
The processor synchronizes I/O instruction execution with external bus activity (see Table 18-1).
Vol. 1 18-5
INPUT/OUTPUT
Table 18-1. I/O Instruction Serialization
Instruction Being
Executed
Processor Delays Execution of …
Until Completion of …
Current Instruction?
Pending Stores?
Next Instruction?
IN
Yes
Yes
INS
Yes
Yes
REP INS
Yes
Yes
Current Store?
OUT
Yes
Yes
Yes
OUTS
Yes
Yes
Yes
REP OUTS
Yes
Yes
Yes
18-6 Vol. 1
CHAPTER 19
PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
When writing software intended to run on IA-32 processors, it is necessary to identify the type of processor present
in a system and the processor features that are available to an application.
19.1
USING THE CPUID INSTRUCTION
Use the CPUID instruction for processor identification in the Pentium M processor family, Pentium 4 processor
family, Intel Xeon processor family, P6 family, Pentium processor, and later Intel486 processors. This instruction
returns the family, model and (for some processors) a brand string for the processor that executes the instruction.
It also indicates the features that are present in the processor and gives information about the processor’s caches
and TLB.
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. The CPUID instruction will cause the invalid opcode exception (#UD) if executed on a processor that does not support it.
To obtain processor identification information, a source operand value is placed in the EAX register to select the
type of information to be returned. When the CPUID instruction is executed, selected information is returned in the
EAX, EBX, ECX, and EDX registers. For a complete description of the CPUID instruction, tables indicating values
returned, and example code, see CPUID—CPU Identification in Chapter 3 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 2A.
19.1.1
Notes on Where to Start
The following guidelines are among the most important, and should always be followed when using the CPUID
instruction to determine available features:
•
Always begin by testing for the “GenuineIntel,” message in the EBX, EDX, and ECX registers when the CPUID
instruction is executed with EAX equal to 0. If the processor is not genuine Intel, the feature identification flags
may have different meanings than are described in Intel documentation.
•
Test feature identification flags individually and do not make assumptions about undefined bits.
19.1.2
Identification of Earlier IA-32 Processors
The CPUID instruction is not available in earlier IA-32 processors up through the earlier Intel486 processors. For
these processors, several other architectural features can be exploited to identify the processor.
The settings of bits 12 and 13 (IOPL), 14 (NT), and 15 (reserved) in the EFLAGS register are different for Intel’s 32bit processors than for the Intel 8086 and Intel 286 processors. By examining the settings of these bits (with the
PUSHF/PUSHFD and POPF/POPFD instructions), an application program can determine whether the processor is an
8086, Intel 286, or one of the Intel 32-bit processors:
•
•
•
8086 processor — Bits 12 through 15 of the EFLAGS register are always set.
Intel 286 processor — Bits 12 through 15 are always clear in real-address mode.
32-bit processors — In real-address mode, bit 15 is always clear and bits 12 through 14 have the last value
loaded into them. In protected mode, bit 15 is always clear, bit 14 has the last value loaded into it, and the IOPL
bits depend on the current privilege level (CPL). The IOPL field can be changed only if the CPL is 0.
Other EFLAGS register bits that can be used to differentiate between the 32-bit processors:
•
Bit 18 (AC) — Implemented only on the Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors.
The inability to set or clear this bit distinguishes an Intel386 processor from the later IA-32 processors.
•
Bit 21 (ID) — Determines if the processor is able to execute the CPUID instruction. The ability to set and clear
this bit indicates that it is a Pentium 4, Intel Xeon, P6 family, Pentium, or later-version Intel486 processor.
Vol. 1 19-1
PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
To determine whether an x87 FPU or NPX is present in a system, applications can write to the x87 FPU status and
control registers using the FNINIT instruction and then verify that the correct values are read back using the
FNSTENV instruction.
After determining that an x87 FPU or NPX is present, its type can then be determined. In most cases, the processor
type will determine the type of FPU or NPX; however, an Intel386 processor is compatible with either an Intel 287
or Intel 387 math coprocessor.
The method the coprocessor uses to represent ∞ (after the execution of the FINIT, FNINIT, or RESET instruction)
indicates which coprocessor is present. The Intel 287 math coprocessor uses the same bit representation for +∞
and −∞; whereas, the Intel 387 math coprocessor uses different representations for +∞ and −∞.
19-2 Vol. 1
APPENDIX A
EFLAGS CROSS-REFERENCE
A.1
EFLAGS AND INSTRUCTIONS
Table A-2 summarizes how the instructions affect the flags in the EFLAGS register. The following codes describe
how the flags are affected.
Table A-1. Codes Describing Flags
T
Instruction tests flag.
M
Instruction modifies flag (either sets or resets depending on operands).
0
Instruction resets flag.
1
Instruction sets flag.
—
Instruction's effect on flag is undefined.
R
Instruction restores prior value of flag.
Blank
Instruction does not affect flag.
Table A-2. EFLAGS Cross-Reference
Instruction
OF
SF
ZF
AF
PF
CF
TF
AAA
—
—
—
TM
—
M
AAD
—
M
M
—
M
—
AAM
—
M
M
—
M
—
AAS
—
—
—
TM
—
M
ADC
M
M
M
M
M
TM
ADD
M
M
M
M
M
M
AND
0
M
M
—
M
0
—
—
—
—
—
M
ARPL
IF
DF
NT
RF
M
BOUND
BSF/BSR
—
—
—
—
M
BSWAP
BT/BTS/BTR/BTC
CALL
CBW
CLC
0
CLD
0
CLI
0
CLTS
CMC
M
CMOVcc
T
T
T
CMP
M
M
M
M
T
T
M
M
Vol. 1 A-1
EFLAGS CROSS-REFERENCE
Table A-2. EFLAGS Cross-Reference (Contd.)
Instruction
OF
SF
ZF
CMPS
M
M
CMPXCHG
M
M
CMPXCHG8B
AF
PF
CF
TF
M
M
M
M
M
M
M
M
IF
DF
NT
T
M
COMISD
0
0
M
0
M
M
COMISS
0
0
M
0
M
M
DAA
—
M
M
TM
M
TM
DAS
—
M
M
TM
M
TM
DEC
M
M
M
M
M
DIV
—
—
—
—
—
—
T
T
CPUID
CWD
ENTER
ESC
FCMOVcc
FCOMI, FCOMIP, FUCOMI, FUCOMIP
T
0
0
M
0
M
M
IDIV
—
—
—
—
—
—
IMUL
M
—
—
—
—
M
M
M
M
M
M
HLT
IN
INC
INS
T
INT
INTO
T
0
0
0
0
INVD
INVLPG
UCOMISD
0
0
M
0
M
M
UCOMISS
0
0
M
0
M
M
IRET
R
R
R
R
R
R
Jcc
T
T
T
T
T
JCXZ
JMP
LAHF
LAR
LDS/LES/LSS/LFS/LGS
LEA
LEAVE
LGDT/LIDT/LLDT/LMSW
LOCK
A-2 Vol. 1
M
R
R
R
T
RF
EFLAGS CROSS-REFERENCE
Table A-2. EFLAGS Cross-Reference (Contd.)
Instruction
OF
SF
ZF
AF
PF
CF
TF
IF
DF
LODS
NT
RF
T
LOOP
LOOPE/LOOPNE
T
LSL
M
LTR
MONITOR
MWAIT
MOV
MOV control, debug, test
—
—
—
—
—
—
MOVS
T
MOVSX/MOVZX
MUL
M
—
—
—
—
M
NEG
M
M
M
M
M
M
0
M
M
—
M
0
NOP
NOT
OR
OUT
OUTS
T
POP/POPA
POPF
R
R
R
R
R
R
R
R
R
R
M
M
M
M
PUSH/PUSHA/PUSHF
RCL/RCR 1
M
TM
RCL/RCR count
—
TM
ROL/ROR 1
M
M
ROL/ROR count
—
RSM
M
RDMSR
RDPMC
RDTSC
REP/REPE/REPNE
RET
SAHF
M
M
M
M
M
M
R
R
R
R
R
SAL/SAR/SHL/SHR 1
M
M
M
—
M
M
SAL/SAR/SHL/SHR count
—
M
M
—
M
M
SBB
M
M
M
M
M
TM
SCAS
M
M
M
M
M
M
SETcc
T
T
T
T
T
M
T
SGDT/SIDT/SLDT/SMSW
Vol. 1 A-3
EFLAGS CROSS-REFERENCE
Table A-2. EFLAGS Cross-Reference (Contd.)
Instruction
SHLD/SHRD
OF
—
SF
M
ZF
M
AF
—
PF
M
STC
CF
TF
IF
DF
M
1
STD
1
STI
1
STOS
T
STR
SUB
M
M
M
M
M
M
TEST
0
M
M
—
M
0
UD2
VERR/VERRW
M
WAIT
WBINVD
WRMSR
XADD
M
M
M
M
M
M
0
M
M
—
M
0
XCHG
XLAT
XOR
A-4 Vol. 1
NT
RF
APPENDIX B
EFLAGS CONDITION CODES
B.1
CONDITION CODES
Table B-1 lists condition codes that can be queried using CMOVcc, FCMOVcc, Jcc, and SETcc. Condition codes refer
to the setting of one or more status flags (CF, OF, SF, ZF, and PF) in the EFLAGS register. In the table below:
•
•
•
•
The “Mnemonic” column provides the suffix (cc) added to the instruction to specify a test condition.
“Condition Tested For” describes the targeted condition.
“Instruction Subcode” provides the opcode suffix added to the main opcode to specify the test condition.
“Status Flags Setting” describes the flag setting.
Table B-1. EFLAGS Condition Codes
Mnemonic (cc)
Condition Tested For
Instruction
Subcode
Status Flags Setting
O
Overflow
0000
OF = 1
NO
No overflow
0001
OF = 0
B
NAE
Below
Neither above nor equal
0010
CF = 1
NB
AE
Not below
Above or equal
0011
CF = 0
E
Z
Equal
Zero
0100
ZF = 1
NE
NZ
Not equal
Not zero
0101
ZF = 0
BE
NA
Below or equal
Not above
0110
(CF OR ZF) = 1
NBE
A
Neither below nor equal
Above
0111
(CF OR ZF) = 0
S
Sign
1000
SF = 1
NS
No sign
1001
SF = 0
P
PE
Parity
Parity even
1010
PF = 1
NP
PO
No parity
Parity odd
1011
PF = 0
L
NGE
Less
Neither greater nor equal
1100
(SF XOR OF) = 1
NL
GE
Not less
Greater or equal
1101
(SF XOR OF) = 0
LE
NG
Less or equal
Not greater
1110
((SF XOR OF) OR ZF) = 1
NLE
G
Neither less nor equal
Greater
1111
((SF XOR OF) OR ZF) = 0
Many of the test conditions are described in two different ways. For example, LE (less or equal) and NG (not
greater) describe the same test condition. Alternate mnemonics are provided to make code more intelligible.
Vol. 1 B-1
EFLAGS CONDITION CODES
The terms “above” and “below” are associated with the CF flag and refer to the relation between two unsigned
integer values. The terms “greater” and “less” are associated with the SF and OF flags and refer to the relation
between two signed integer values.
B-2 Vol. 1
APPENDIX C
FLOATING-POINT EXCEPTIONS SUMMARY
C.1
OVERVIEW
This appendix shows which of the floating-point exceptions can be generated for:
•
•
•
•
•
x87 FPU instructions — see Table C-2
SSE instruction — see Table C-3
SSE2 instructions — see Table C-4
SSE3 instructions — see Table C-5
SSE4 instructions — see Table C-6
Table C-1 lists types of floating-point exceptions that potentially can be generated by the x87 FPU and by
SSE/SSE2/SSE3 instructions.
Table C-1. x87 FPU and SIMD Floating-Point Exceptions
Floatingpoint
Exception
Description
#IS
Invalid-operation exception for stack underflow or stack overflow (can only be generated for x87 FPU instructions)*
#IA or #I
Invalid-operation exception for invalid arithmetic operands and unsupported formats*
#D
Denormal-operand exception
#Z
Divide-by-zero exception
#O
Numeric-overflow exception
#U
Numeric-underflow exception
#P
Inexact-result (precision) exception
NOTE:
* The x87 FPU instruction set generates two types of invalid-operation exceptions: #IS (stack underflow or stack overflow) and #IA
(invalid arithmetic operation due to invalid arithmetic operands or unsupported formats). SSE/SSE2/SSE3 instructions potentially
generate #I (invalid operation exceptions due to invalid arithmetic operands or unsupported formats).
The floating point exceptions shown in Table C-1 (except for #D and #IS) are defined in IEEE Standard 754-1985
for Binary Floating-Point Arithmetic. See Section 4.9.1, “Floating-Point Exception Conditions,” for a detailed discussion of floating-point exceptions.
C.2
X87 FPU INSTRUCTIONS
Table C-2 lists the x87 FPU instructions in alphabetical order. For each instruction, it summarizes the floating-point
exceptions that the instruction can generate.
Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions
Mnemonic
Instruction
#IS #IA
F2XM1
Exponential
Y
FABS
Absolute value
Y
FADD(P)
Add floating-point
Y
FBLD
BCD load
Y
#D
Y
Y
Y
Y
#Z
#O
Y
#U
#P
Y
Y
Y
Y
Vol. 1 C-1
FLOATING-POINT EXCEPTIONS SUMMARY
Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions (Contd.)
Mnemonic
Instruction
#IS #IA
#D
#Z
#O
#U
FBSTP
BCD store and pop
Y
FCHS
Change sign
Y
FCLEX
Clear exceptions
FCMOVcc
Floating-point conditional move
FCOM, FCOMP, FCOMPP
Compare floating-point
Y
Y
Y
FCOMI, FCOMIP, FUCOMI,
FUCOMIP
Compare floating-point and set EFLAGS
Y
Y
Y
FCOS
Cosine
Y
Y
Y
FDECSTP
Decrement stack pointer
FDIV(R)(P)
Divide floating-point
Y
Y
Y
FFREE
Free register
FIADD
Integer add
Y
Y
Y
FICOM(P)
Integer compare
Y
Y
Y
FIDIV
Integer divide
Y
Y
Y
Y
FIDIVR
Integer divide reversed
Y
Y
Y
Y
FILD
Integer load
Y
FIMUL
Integer multiply
Y
Y
Y
FINCSTP
Increment stack pointer
FINIT
Initialize processor
FIST(P)
Integer store
Y
Y
Y
FISTTP
Truncate to integer
(SSE3 instruction)
Y
Y
Y
FISUB(R)
Integer subtract
Y
Y
Y
FLD extended or stack
Load floating-point
Y
FLD single or double
Load floating-point
Y
Y
Y
FLD1
Load + 1.0
Y
FLDCW
Load Control word
Y
Y
Y
FLDENV
Load environment
Y
Y
Y
FLDL2E
Load log2e
Y
FLDL2T
Load log210
Y
FLDLG2
Load log102
Y
FLDLN2
Load loge2
Y
FLDPI
Load π
Y
FLDZ
Load + 0.0
Y
FMUL(P)
Multiply floating-point
Y
Y
Y
FNOP
No operation
FPATAN
Partial arctangent
Y
Y
FPREM
Partial remainder
Y
FPREM1
IEEE partial remainder
Y
C-2 Vol. 1
Y
#P
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
FLOATING-POINT EXCEPTIONS SUMMARY
Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions (Contd.)
Mnemonic
FPTAN
Instruction
Partial tangent
#IS #IA
Y
#D
Y
#Z
#O
Y
#U
#P
Y
Y
FRNDINT
Round to integer
Y
Y
Y
FRSTOR
Restore state
Y
Y
Y
Y
FSAVE
Save state
FSCALE
Scale
Y
Y
Y
Y
Y
FSIN
Sine
Y
Y
Y
Y
Y
FSINCOS
Sine and cosine
Y
Y
Y
Y
Y
FSQRT
Square root
Y
Y
Y
FST(P) stack or extended
Store floating-point
Y
FST(P) single or double
Store floating-point
Y
Y
FSTCW
Store control word
FSTENV
Store environment
FSTSW (AX)
Store status word
FSUB(R)(P)
Subtract floating-point
Y
Y
Y
FTST
Test
Y
Y
Y
FUCOM(P)(P)
Unordered compare floating-point
Y
Y
Y
FWAIT
CPU Wait
Y
Y
Y
Y
Y
FXAM
Examine
FXCH
Exchange registers
Y
FXTRACT
Extract
Y
Y
Y
Y
FYL2X
Logarithm
Y
Y
Y
Y
FYL2XP1
Logarithm epsilon
Y
Y
Y
C.3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
#O
#U
#P
SSE INSTRUCTIONS
Table C-3 lists SSE instructions with at least one of the following characteristics:
•
•
•
have floating-point operands
generate floating-point results
read or write floating-point status and control information
The table also summarizes the floating-point exceptions that each instruction can generate.
Table C-3. Exceptions Generated with SSE Instructions
Mnemonic
Instruction
#I
#D
#Z
ADDPS
Packed add.
Y
Y
Y
Y
Y
ADDSS
Scalar add.
Y
Y
Y
Y
Y
ANDNPS
Packed logical INVERT and AND.
ANDPS
Packed logical AND.
CMPPS
Packed compare.
Y
Y
CMPSS
Scalar compare.
Y
Y
Vol. 1 C-3
FLOATING-POINT EXCEPTIONS SUMMARY
Table C-3. Exceptions Generated with SSE Instructions (Contd.)
Mnemonic
Instruction
#I
#D
Y
Y
#Z
#O
#U
#P
COMISS
Scalar ordered compare lower SP FP numbers and set the status
flags.
CVTPI2PS
Convert two 32-bit signed integers from MM2/Mem to two SP FP.
CVTPS2PI
Convert lower two SP FP from XMM/Mem to two 32-bit signed
integers in MM using rounding specified by MXCSR.
CVTSI2SS
Convert one 32-bit signed integer from Integer Reg/Mem to one
SP FP.
CVTSS2SI
Convert one SP FP from XMM/Mem to one 32-bit signed integer
using rounding mode specified by MXCSR, and move the result to
an integer register.
Y
Y
CVTTPS2PI
Convert two SP FP from XMM2/Mem to two 32-bit signed
integers in MM1 using truncate.
Y
Y
CVTTSS2SI
Convert lowest SP FP from XMM/Mem to one 32-bit signed
integer using truncate, and move the result to an integer register.
Y
Y
DIVPS
Packed divide.
Y
Y
Y
Y
Y
Y
DIVSS
Scalar divide.
Y
Y
Y
Y
Y
Y
LDMXCSR
Load control/status word.
MAXPS
Packed maximum.
Y
Y
MAXSS
Scalar maximum.
Y
Y
MINPS
Packed minimum.
Y
Y
MINSS
Scalar minimum.
Y
Y
MOVAPS
Move four packed SP values.
MOVHLPS
Move packed SP high to low.
MOVHPS
Move two packed SP values between memory and the high half of
an XMM register.
MOVLHPS
Move packed SP low to high.
MOVLPS
Move two packed SP values between memory and the low half of
an XMM register.
MOVMSKPS
Move sign mask to r32.
MOVSS
Move scalar SP number between an XMM register and memory or
a second XMM register.
MOVUPS
Move unaligned packed data.
MULPS
Packed multiply.
Y
Y
Y
Y
Y
MULSS
Scalar multiply.
Y
Y
Y
Y
Y
ORPS
Packed OR.
RCPPS
Packed reciprocal.
RCPSS
Scalar reciprocal.
RSQRTPS
Packed reciprocal square root.
RSQRTSS
Scalar reciprocal square root.
SHUFPS
Shuffle.
SQRTPS
Square Root of the packed SP FP numbers.
Y
Y
Y
SQRTSS
Scalar square root.
Y
Y
Y
C-4 Vol. 1
Y
Y
Y
Y
FLOATING-POINT EXCEPTIONS SUMMARY
Table C-3. Exceptions Generated with SSE Instructions (Contd.)
Mnemonic
Instruction
#I
#D
#Z
#O
#U
#P
STMXCSR
Store control/status word.
SUBPS
Packed subtract.
Y
Y
Y
Y
Y
SUBSS
Scalar subtract.
Y
Y
Y
Y
Y
UCOMISS
Unordered compare lower SP FP numbers and set the status flags.
Y
Y
UNPCKHPS
Interleave SP FP numbers.
UNPCKLPS
Interleave SP FP numbers.
XORPS
Packed XOR.
C.4
SSE2 INSTRUCTIONS
Table C-4 lists SSE2 instructions with at least one of the following characteristics:
•
•
floating-point operands
floating point results
For each instruction, the table summarizes the floating-point exceptions that the instruction can generate.
Table C-4. Exceptions Generated with SSE2 Instructions
Instruction
Description
#I
#D
#Z
#O
#U
#P
ADDPD
Add two packed DP FP numbers from XMM2/Mem to XMM1.
Y
Y
Y
Y
Y
ADDSD
Add the lower DP FP number from XMM2/Mem to XMM1.
Y
Y
Y
Y
Y
ANDNPD
Invert the 128 bits in XMM1and then AND the result with 128 bits
from XMM2/Mem.
ANDPD
Logical And of 128 bits from XMM2/Mem to XMM1 register.
CMPPD
Compare packed DP FP numbers from XMM2/Mem to packed DP
FP numbers in XMM1 register using imm8 as predicate.
Y
Y
CMPSD
Compare lowest DP FP number from XMM2/Mem to lowest DP FP
number in XMM1 register using imm8 as predicate.
Y
Y
COMISD
Compare lower DP FP number in XMM1 register with lower DP FP
number in XMM2/Mem and set the status flags accordingly
Y
Y
CVTDQ2PS
Convert four 32-bit signed integers from XMM/Mem to four SP FP.
CVTPS2DQ
Convert four SP FP from XMM/Mem to four 32-bit signed integers
in XMM using rounding specified by MXCSR.
Y
Y
CVTTPS2DQ
Convert four SP FP from XMM/Mem to four 32-bit signed integers
in XMM using truncate.
Y
Y
CVTDQ2PD
Convert two 32-bit signed integers in XMM2/Mem to 2 DP FP in
xmm1 using rounding specified by MXCSR.
CVTPD2DQ
Convert two DP FP from XMM2/Mem to two 32-bit signed
integers in xmm1 using rounding specified by MXCSR.
Y
Y
CVTPD2PI
Convert lower two DP FP from XMM/Mem to two 32-bit signed
integers in MM using rounding specified by MXCSR.
Y
Y
CVTPD2PS
Convert two DP FP to two SP FP.
Y
Y
CVTPI2PD
Convert two 32-bit signed integers from MM2/Mem to two DP FP.
CVTPS2PD
Convert two SP FP to two DP FP.
Y
Y
Y
Y
Y
Y
Vol. 1 C-5
FLOATING-POINT EXCEPTIONS SUMMARY
Table C-4. Exceptions Generated with SSE2 Instructions (Contd.)
Instruction
Description
#I
#D
#Z
#O
#U
#P
CVTSD2SI
Convert one DP FP from XMM/Mem to one 32 bit signed integer
using rounding mode specified by MXCSR, and move the result to
an integer register.
Y
CVTSD2SS
Convert scalar DP FP to scalar SP FP.
Y
Y
CVTSI2SD
Convert one 32-bit signed integer from Integer Reg/Mem to one
DP FP.
CVTSS2SD
Convert scalar SP FP to scalar DP FP.
Y
Y
CVTTPD2DQ
Convert two DP FP from XMM2/Mem to two 32-bit signed
integers in XMM1 using truncate.
Y
Y
CVTTPD2PI
Convert two DP FP from XMM2/Mem to two 32-bit signed
integers in MM1 using truncate.
Y
Y
CVTTSD2SI
Convert lowest DP FP from XMM/Mem to one 32 bit signed
integer using truncate, and move the result to an integer register.
Y
Y
DIVPD
Divide packed DP FP numbers in XMM1 by XMM2/Mem
Y
Y
Y
Y
Y
Y
DIVSD
Divide lower DP FP numbers in XMM1 by XMM2/Mem
Y
Y
Y
Y
Y
Y
MAXPD
Return the maximum DP FP numbers between XMM2/Mem and
XMM1.
Y
Y
MAXSD
Return the maximum DP FP number between the lower DP FP
numbers from XMM2/Mem and XMM1.
Y
Y
MINPD
Return the minimum DP numbers between XMM2/Mem and
XMM1.
Y
Y
MINSD
Return the minimum DP FP number between the lowest DP FP
numbers from XMM2/Mem and XMM1.
Y
Y
MOVAPD
Move 128 bits representing 2 packed DP data from XMM2/Mem to
XMM1 register.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Or Move 128 bits representing 2 packed DP from XMM1 register
to XMM2/Mem.
MOVHPD
Move 64 bits representing one DP operand from Mem to upper
field of XMM register.
Or move 64 bits representing one DP operand from upper field of
XMM register to Mem.
MOVLPD
Move 64 bits representing one DP operand from Mem to lower
field of XMM register.
Or move 64 bits representing one DP operand from lower field of
XMM register to Mem.
MOVMSKPD
Move the sign mask to r32.
MOVSD
Move 64 bits representing one scalar DP operand from
XMM2/Mem to XMM1 register.
Or move 64 bits representing one scalar DP operand from XMM1
register to XMM2/Mem.
MOVUPD
Move 128 bits representing 2 DP data from XMM2/Mem to XMM1
register.
Or move 128 bits representing 2 DP data from XMM1 register to
XMM2/Mem.
MULPD
C-6 Vol. 1
Multiply packed DP FP numbers in XMM2/Mem to XMM1.
FLOATING-POINT EXCEPTIONS SUMMARY
Table C-4. Exceptions Generated with SSE2 Instructions (Contd.)
Instruction
MULSD
Description
Multiply the lowest DP FP number in XMM2/Mem to XMM1.
#I
#D
Y
Y
#Z
#O
#U
#P
Y
Y
Y
ORPD
OR 128 bits from XMM2/Mem to XMM1 register.
SHUFPD
Shuffle Double.
SQRTPD
Square Root Packed Double-Precision
Y
Y
SQRTSD
Square Root Scaler Double-Precision
Y
Y
SUBPD
Subtract Packed Double-Precision.
Y
Y
Y
Y
Y
SUBSD
Subtract Scaler Double-Precision.
Y
Y
Y
Y
Y
UCOMISD
Compare lower DP FP number in XMM1 register with lower DP FP
number in XMM2/Mem and set the status flags accordingly.
Y
Y
UNPCKHPD
Interleaves DP FP numbers from the high halves of XMM1 and
XMM2/Mem into XMM1 register.
UNPCKLPD
Interleaves DP FP numbers from the low halves of XMM1 and
XMM2/Mem into XMM1 register.
XORPD
XOR 128 bits from XMM2/Mem to XMM1 register.
C.5
Y
Y
SSE3 INSTRUCTIONS
Table C-5 lists the SSE3 instructions that have at least one of the following characteristics:
•
•
have floating-point operands
generate floating-point results
For each instruction, the table summarizes the floating-point exceptions that the instruction can generate.
Table C-5. Exceptions Generated with SSE3 Instructions
Instruction
Description
#I
#D
#Z
#O
#U
#P
ADDSUBPD
Add /Sub packed DP FP numbers from XMM2/Mem to XMM1.
Y
Y
Y
Y
Y
ADDSUBPS
Add /Sub packed SP FP numbers from XMM2/Mem to XMM1.
Y
Y
Y
Y
Y
FISTTP
See Table C-2.
Y
HADDPD
Add horizontally packed DP FP numbers XMM2/Mem to XMM1.
Y
Y
Y
Y
HADDPS
Add horizontally packed SP FP numbers XMM2/Mem to XMM1
Y
Y
Y
Y
Y
HSUBPD
Sub horizontally packed DP FP numbers XMM2/Mem to XMM1
Y
Y
Y
Y
Y
HSUBPS
Sub horizontally packed SP FP numbers XMM2/Mem to XMM1
Y
Y
Y
Y
Y
Y
Y
Other SSE3 instructions do not generate floating-point exceptions.
C.6
SSSE3 INSTRUCTIONS
SSSE3 instructions operate on integer data elements. They do not generate floating-point exceptions.
C.7
SSE4 INSTRUCTIONS
Table C-6 lists the SSE4.1 instructions that generate floating-point results.
For each instruction, the table summarizes the floating-point exceptions that the instruction can generate.
Vol. 1 C-7
FLOATING-POINT EXCEPTIONS SUMMARY
Table C-6. Exceptions Generated with SSE4 Instructions
Instruction
Description
#I
#D
#O
#U
#P
DPPD
DP FP dot product.
Y
DPPS
SP FP dot product.
Y
Y
Y
Y
Y
Y
Y
Y
Y
ROUNDPD
Round packed DP FP values to integer FP values.
Y
Y1
ROUNDPS
Round packed SP FP values to integer FP values.
Y
Y1
ROUNDSD
Round scalar DP FP value to integer FP value.
Y
Y1
ROUNDSS
Round scalar SP FP value to integer FP value.
Y
Y1
NOTES:
1. If bit 3 of immediate operand is 0
Other SSE4.1 instructions and SSE4.2 instructions do not generate floating-point exceptions.
C-8 Vol. 1
#Z
APPENDIX D
GUIDELINES FOR WRITING X87 FPU
EXCEPTION HANDLERS
As described in Chapter 8, “Programming with the x87 FPU,” the IA-32 Architecture supports two mechanisms for
accessing exception handlers to handle unmasked x87 FPU exceptions: native mode and MS-DOS compatibility
mode. The primary purpose of this appendix is to provide detailed information to help software engineers design
and write x87 FPU exception-handling facilities to run on PC systems that use the MS-DOS compatibility mode1 for
handling x87 FPU exceptions. Some of the information in this appendix will also be of interest to engineers who are
writing native-mode x87 FPU exception handlers. The information provided is as follows:
•
Discussion of the origin of the MS-DOS x87 FPU exception handling mechanism and its relationship to the x87
FPU’s native exception handling mechanism.
•
Description of the IA-32 flags and processor pins that control the MS-DOS x87 FPU exception handling
mechanism.
•
•
Description of the external hardware typically required to support MS-DOS exception handling mechanism.
•
•
•
Code examples that demonstrate various levels of x87 FPU exception handlers.
Description of the x87 FPU’s exception handling mechanism and the typical protocol for x87 FPU exception
handlers.
Discussion of x87 FPU considerations in multitasking environments.
Discussion of native mode x87 FPU exception handling.
The information given is oriented toward the most recent generations of IA-32 processors, starting with the
Intel486. It is intended to augment the reference information given in Chapter 8, “Programming with the x87 FPU.”
A more extensive version of this appendix is available in the application note AP-578, Software and Hardware
Considerations for x87 FPU Exception Handlers for Intel Architecture Processors (Order Number 243291), which is
available from Intel.
D.1
MS-DOS COMPATIBILITY SUB-MODE FOR HANDLING X87 FPU EXCEPTIONS
The first generations of IA-32 processors (starting with the Intel 8086 and 8088 processors and going through the
Intel 286 and Intel386 processors) did not have an on-chip floating-point unit. Instead, floating-point capability
was provided on a separate numeric coprocessor chip. The first of these numeric coprocessors was the Intel 8087,
which was followed by the Intel 287 and Intel 387 numeric coprocessors.
To allow the 8087 to signal floating-point exceptions to its companion 8086 or 8088, the 8087 has an output pin,
INT, which it asserts when an unmasked floating-point exception occurs. The designers of the 8087 recommended
that the output from this pin be routed through a programmable interrupt controller (PIC) such as the Intel 8259A
to the INTR pin of the 8086 or 8088. The handler for the resulting interrupt could then be used to access the
floating-point exception handler.
However, the original IBM* PC design and MS-DOS operating system used a different mechanism for handling the
INT output from the 8087. It connected the INT pin directly to the NMI input pin of the 8086 or 8088. The NMI interrupt handler then had to determine if the interrupt was caused by a floating-point exception or another NMI event.
This mechanism is the origin of what is now called the “MS-DOS compatibility mode.” The decision to use this latter
floating-point exception handling mechanism came about because when the IBM PC was first designed, the 8087
was not available. When the 8087 did become available, other functions had already been assigned to the eight
inputs to the PIC. One of these functions was a BIOS video interrupt, which was assigned vector 16 for the 8086
and 8088.
1
Microsoft Windows* 95 and Windows 3.1 (and earlier versions) operating systems use almost the same x87 FPU exception handling
interface as MS-DOS. The recommendations in this appendix for a MS-DOS compatible exception handler thus apply to all three operating systems.
Vol. 1 D-1
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
The Intel 286 processor created the “native mode” for handling floating-point exceptions by providing a dedicated
input pin (ERROR#) for receiving floating-point exception signals and a dedicated interrupt vector, 16. Interrupt 16
was used to signal floating-point errors (also called math faults). It was intended that the ERROR# pin on the Intel
286 be connected to a corresponding ERROR# pin on the Intel 287 numeric coprocessor. When the Intel 287
signals a floating-point exception using this mechanism, the Intel 286 generates an interrupt 16, to invoke the
floating-point exception handler.
To maintain compatibility with existing PC software, the native floating-point exception handling mode of the Intel
286 and 287 was not used in the IBM PC AT system design. Instead, the ERROR# pin on the Intel 286 was tied
permanently high, and the ERROR# pin from the Intel 287 was routed to a second (cascaded) PIC. The resulting
output of this PIC was routed through an exception handler and eventually caused an interrupt 2 (NMI interrupt).
Here the NMI interrupt was shared with IBM PC AT’s new parity checking feature. Interrupt 16 remained assigned
to the BIOS video interrupt handler. The external hardware for the MS-DOS compatibility mode must prevent the
Intel 286 processor from executing past the next x87 FPU instruction when an unmasked exception has been generated. To do this, it asserts the BUSY# signal into the Intel 286 when the ERROR# signal is asserted by the Intel 287.
The Intel386 processor and its companion Intel 387 numeric coprocessor provided the same hardware mechanism
for signaling and handling floating-point exceptions as the Intel 286 and 287 processors. And again, to maintain
compatibility with existing MS-DOS software, basically the same MS-DOS compatibility floating-point exception
handling mechanism that was used in the IBM PC AT was used in PCs based on the Intel386 processor.
D.2
IMPLEMENTATION OF THE MS-DOS* COMPATIBILITY SUB-MODE IN THE
INTEL486™, PENTIUM®, AND P6 PROCESSOR FAMILY, AND PENTIUM® 4
PROCESSORS
Beginning with the Intel486™ processor, the IA-32 architecture provided a dedicated mechanism for enabling the
MS-DOS compatibility mode for x87 FPU exceptions and for generating external x87 FPU-exception signals while
operating in this mode. The following sections describe the implementation of the MS-DOS compatibility mode in
the Intel486 and Pentium processors and in the P6 family and Pentium 4 processors. Also described is the recommended external hardware to support this mode of operation.
D.2.1
MS-DOS* Compatibility Sub-mode in the Intel486™ and Pentium® Processors
In the Intel486 processor, several things were done to enhance and speed up the numeric coprocessor, now called
the floating-point unit (x87 FPU). The most important enhancement was that the x87 FPU was included in the same
chip as the processor, for increased speed in x87 FPU computations and reduced latency for x87 FPU exception
handling. Also, for the first time, the MS-DOS compatibility mode was built into the chip design, with the addition
of the NE bit in control register CR0 and the addition of the FERR# (Floating-point ERRor) and IGNNE# (IGNore
Numeric Error) pins.
The NE bit selects the native x87 FPU exception handling mode (NE = 1) or the MS-DOS compatibility mode (NE =
0). When native mode is selected, all signaling of floating-point exceptions is handled internally in the Intel486
chip, resulting in the generation of an interrupt 16.
When MS-DOS compatibility mode is selected, the FERRR# and IGNNE# pins are used to signal floating-point
exceptions. The FERR# output pin, which replaces the ERROR# pin from the previous generations of IA-32 numeric
coprocessors, is connected to a PIC. A new input signal, IGNNE#, is provided to allow the x87 FPU exception
handler to execute x87 FPU instructions, if desired, without first clearing the error condition and without triggering
the interrupt a second time. This IGNNE# feature is needed to replicate the capability that was provided on MSDOS compatible Intel 286 and Intel 287 and Intel386 and Intel 387 systems by turning off the BUSY# signal, when
inside the x87 FPU exception handler, before clearing the error condition.
Note that Intel, in order to provide Intel486 processors for market segments that had no need for an x87 FPU,
created the “SX” versions. These Intel486 SX processors did not contain the floating-point unit. Intel also produced
Intel 487 SX processors for end users who later decided to upgrade to a system with an x87 FPU. These Intel 487
SX processors are similar to standard Intel486 processors with a working x87 FPU on board.
Thus, the external circuitry necessary to support the MS-DOS compatibility mode for Intel 487 SX processors is the
same as for standard Intel486 DX processors.
D-2 Vol. 1
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
The Pentium, P6 family, and Pentium 4 processors offer the same mechanism (the NE bit and the FERR# and
IGNNE# pins) as the Intel486 processors for generating x87 FPU exceptions in MS-DOS compatibility mode. The
actions of these mechanisms are slightly different and more straightforward for the P6 family and Pentium 4
processors, as described in Section D.2.2, “MS-DOS* Compatibility Sub-mode in the P6 Family and Pentium® 4
Processors.”
For Pentium, P6 family, and Pentium 4 processors, it is important to note that the special DP (Dual Processing)
mode for Pentium processors and also the more general Intel MultiProcessor Specification for systems with
multiple Pentium, P6 family, or Pentium 4 processors support x87 FPU exception handling only in the native mode.
Intel does not recommend using the MS-DOS compatibility x87 FPU mode for systems using more than one
processor.
D.2.1.1
Basic Rules: When FERR# Is Generated
When MS-DOS compatibility mode is enabled for the Intel486 or Pentium processors (NE bit is set to 0) and the
IGNNE# input pin is de-asserted, the FERR# signal is generated as follows:
1. When an x87 FPU instruction causes an unmasked x87 FPU exception, the processor (in most cases) uses a
“deferred” method of reporting the error. This means that the processor does not respond immediately, but
rather freezes just before executing the next WAIT or x87 FPU instruction (except for “no-wait” instructions,
which the x87 FPU executes regardless of an error condition).
2. When the processor freezes, it also asserts the FERR# output.
3. The frozen processor waits for an external interrupt, which must be supplied by external hardware in response
to the FERR# assertion.
4. In MS-DOS compatibility systems, FERR# is fed to the IRQ13 input in the cascaded PIC. The PIC generates
interrupt 75H, which then branches to interrupt 2, as described earlier in this appendix for systems using the
Intel 286 and Intel 287 or Intel386 and Intel 387 processors.
The deferred method of error reporting is used for all exceptions caused by the basic arithmetic instructions
(including FADD, FSUB, FMUL, FDIV, FSQRT, FCOM and FUCOM), for precision exceptions caused by all types of x87
FPU instructions, and for numeric underflow and overflow exceptions caused by all types of x87 FPU instructions
except stores to memory.
Some x87 FPU instructions with some x87 FPU exceptions use an “immediate” method of reporting errors. Here,
the FERR# is asserted immediately, at the time that the exception occurs. The immediate method of error
reporting is used for x87 FPU stack fault, invalid operation and denormal exceptions caused by all transcendental
instructions, FSCALE, FXTRACT, FPREM and others, and all exceptions (except precision) when caused by x87 FPU
store instructions. Like deferred error reporting, immediate error reporting will cause the processor to freeze just
before executing the next WAIT or x87 FPU instruction if the error condition has not been cleared by that time.
Note that in general, whether deferred or immediate error reporting is used for an x87 FPU exception depends both
on which exception occurred and which instruction caused that exception. A complete specification of these cases,
which applies to both the Pentium and the Intel486 processors, is given in Section 5.1.21 in the Pentium Processor
Family Developer’s Manual: Volume 1.
If NE = 0 but the IGNNE# input is active while an unmasked x87 FPU exception is in effect, the processor disregards the exception, does not assert FERR#, and continues. If IGNNE# is then de-asserted and the x87 FPU exception has not been cleared, the processor will respond as described above. (That is, an immediate exception case
will assert FERR# immediately. A deferred exception case will assert FERR# and freeze just before the next x87
FPU or WAIT instruction.) The assertion of IGNNE# is intended for use only inside the x87 FPU exception handler,
where it is needed if one wants to execute non-control x87 FPU instructions for diagnosis, before clearing the
exception condition. When IGNNE# is asserted inside the exception handler, a preceding x87 FPU exception has
already caused FERR# to be asserted, and the external interrupt hardware has responded, but IGNNE# assertion
still prevents the freeze at x87 FPU instructions. Note that if IGNNE# is left active outside of the x87 FPU exception
handler, additional x87 FPU instructions may be executed after a given instruction has caused an x87 FPU exception. In this case, if the x87 FPU exception handler ever did get invoked, it could not determine which instruction
caused the exception.
To properly manage the interface between the processor’s FERR# output, its IGNNE# input, and the IRQ13 input
of the PIC, additional external hardware is needed. A recommended configuration is described in the following
section.
Vol. 1 D-3
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
D.2.1.2
Recommended External Hardware to Support the MS-DOS* Compatibility Sub-mode
Figure D-1 provides an external circuit that will assure proper handling of FERR# and IGNNE# when an x87 FPU
exception occurs. In particular, it assures that IGNNE# will be active only inside the x87 FPU exception handler
without depending on the order of actions by the exception handler. Some hardware implementations have been
less robust because they have depended on the exception handler to clear the x87 FPU exception interrupt request
to the PIC (FP_IRQ signal) before the handler causes FERR# to be de-asserted by clearing the exception from the
x87 FPU itself. Figure D-2 shows the details of how IGNNE# will behave when the circuit in Figure D-1 is implemented. The temporal regions within the x87 FPU exception handler activity are described as follows:
1. The FERR# signal is activated by an x87 FPU exception and sends an interrupt request through the PIC to the
processor’s INTR pin.
2. During the x87 FPU interrupt service routine (exception handler) the processor will need to clear the interrupt
request latch (Flip Flop #1). It may also want to execute non-control x87 FPU instructions before the exception
is cleared from the x87 FPU. For this purpose the IGNNE# must be driven low. Typically in the PC environment
an I/O access to Port 0F0H clears the external x87 FPU exception interrupt request (FP_IRQ). In the
recommended circuit, this access also is used to activate IGNNE#. With IGNNE# active, the x87 FPU exception
handler may execute any x87 FPU instruction without being blocked by an active x87 FPU exception.
3. Clearing the exception within the x87 FPU will cause the FERR# signal to be deactivated and then there is no
further need for IGNNE# to be active. In the recommended circuit, the deactivation of FERR# is used to
deactivate IGNNE#. If another circuit is used, the software and circuit together must assure that IGNNE# is
deactivated no later than the exit from the x87 FPU exception handler.
RESET
I/O Port F0H
Address Decode
+5V
FF #1
FERR#
Intel486™ Processor
Pentium® Processor
Pentium® Pro Processor
PR
+5V
+5V
CLR
FF #2
PR
+5V
IGNNE#
INTR
Interrupt
Controller
FP_IRQ
LEGEND:
FF #n Flip Flop #n
CLR Clear or Reset
Figure D-1. Recommended Circuit for MS-DOS Compatibility x87 FPU
Exception Handling
D-4 Vol. 1
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
In the circuit in Figure D-1, when the x87 FPU exception handler accesses I/O port 0F0H it clears the IRQ13 interrupt request output from Flip Flop #1 and also clocks out the IGNNE# signal (active) from Flip Flop #2. So the
handler can activate IGNNE#, if needed, by doing this 0F0H access before clearing the x87 FPU exception condition
(which de-asserts FERR#).
However, the circuit does not depend on the order of actions by the x87 FPU exception handler to guarantee the
correct hardware state upon exit from the handler. Flip Flop #2, which drives IGNNE# to the processor, has its
CLEAR input attached to the inverted FERR#. This ensures that IGNNE# can never be active when FERR# is inactive. So if the handler clears the x87 FPU exception condition before the 0F0H access, IGNNE# does not get activated and left on after exit from the handler.
0F0H Address
Decode
Figure D-2. Behavior of Signals During x87 FPU Exception Handling
D.2.1.3
No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window
The Pentium and Intel486 processors implement the “no-wait” floating-point instructions (FNINIT, FNCLEX,
FNSTENV, FNSAVE, FNSTSW, FNSTCW, FNENI, FNDISI or FNSETPM) in the MS-DOS compatibility mode in the
following manner. (See Section 8.3.11, “x87 FPU Control Instructions,” and Section 8.3.12, “Waiting vs. Nonwaiting Instructions,” for a discussion of the no-wait instructions.)
If an unmasked numeric exception is pending from a preceding x87 FPU instruction, a member of the no-wait class
of instructions will, at the beginning of its execution, assert the FERR# pin in response to that exception just like
other x87 FPU instructions, but then, unlike the other x87 FPU instructions, FERR# will be de-asserted. This deassertion was implemented to allow the no-wait class of instructions to proceed without an interrupt due to any
pending numeric exception. However, the brief assertion of FERR# is sufficient to latch the x87 FPU exception
request into most hardware interface implementations (including Intel’s recommended circuit).
All the x87 FPU instructions are implemented such that during their execution, there is a window in which the
processor will sample and accept external interrupts. If there is a pending interrupt, the processor services the
interrupt first before resuming the execution of the instruction. Consequently, it is possible that the no-wait
floating-point instruction may accept the external interrupt caused by it’s own assertion of the FERR# pin in the
event of a pending unmasked numeric exception, which is not an explicitly documented behavior of a no-wait
instruction. This process is illustrated in Figure D-3.
Vol. 1 D-5
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
Exception Generating
Floating-Point
Instruction
Assertion of FERR#
by the Processor
Start of the “No-Wait”
Floating-Point
Instruction
System
Dependent
Delay
Case 1
External Interrupt
Sampling Window
Assertion of INTR Pin
by the System
Case 2
Window Closed
Figure D-3. Timing of Receipt of External Interrupt
Figure D-3 assumes that a floating-point instruction that generates a “deferred” error (as defined in the Section
D.2.1.1, “Basic Rules: When FERR# Is Generated”), which asserts the FERR# pin only on encountering the next
floating-point instruction, causes an unmasked numeric exception. Assume that the next floating-point instruction
following this instruction is one of the no-wait floating-point instructions. The FERR# pin is asserted by the
processor to indicate the pending exception on encountering the no-wait floating-point instruction. After the assertion of the FERR# pin the no-wait floating-point instruction opens a window where the pending external interrupts
are sampled.
Then there are two cases possible depending on the timing of the receipt of the interrupt via the INTR pin (asserted
by the system in response to the FERR# pin) by the processor.
Case 1
If the system responds to the assertion of FERR# pin by the no-wait floating-point instruction via
the INTR pin during this window then the interrupt is serviced first, before resuming the execution of the no-wait floating-point instruction.
Case 2
If the system responds via the INTR pin after the window has closed then the interrupt is recognized
only at the next instruction boundary.
There are two other ways, in addition to Case 1 above, in which a no-wait floating-point instruction can service a
numeric exception inside its interrupt window. First, the first floating-point error condition could be of the “immediate” category (as defined in Section D.2.1.1, “Basic Rules: When FERR# Is Generated”) that asserts FERR#
immediately. If the system delay before asserting INTR is long enough, relative to the time elapsed before the nowait floating-point instruction, INTR can be asserted inside the interrupt window for the latter. Second, consider
two no-wait x87 FPU instructions in close sequence, and assume that a previous x87 FPU instruction has caused an
unmasked numeric exception. Then if the INTR timing is too long for an FERR# signal triggered by the first no-wait
instruction to hit the first instruction’s interrupt window, it could catch the interrupt window of the second.
The possible malfunction of a no-wait x87 FPU instruction explained above cannot happen if the instruction is being
used in the manner for which Intel originally designed it. The no-wait instructions were intended to be used inside
the x87 FPU exception handler, to allow manipulation of the x87 FPU before the error condition is cleared, without
hanging the processor because of the x87 FPU error condition, and without the need to assert IGNNE#. They will
perform this function correctly, since before the error condition is cleared, the assertion of FERR# that caused the
x87 FPU error handler to be invoked is still active. Thus the logic that would assert FERR# briefly at a no-wait
instruction causes no change since FERR# is already asserted. The no-wait instructions may also be used without
problem in the handler after the error condition is cleared, since now they will not cause FERR# to be asserted at
all.
D-6 Vol. 1
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
If a no-wait instruction is used outside of the x87 FPU exception handler, it may malfunction as explained above,
depending on the details of the hardware interface implementation and which particular processor is involved. The
actual interrupt inside the window in the no-wait instruction may be blocked by surrounding it with the instructions:
PUSHFD, CLI, no-wait, then POPFD. (CLI blocks interrupts, and the push and pop of flags preserves and restores
the original value of the interrupt flag.) However, if FERR# was triggered by the no-wait, its latched value and the
PIC response will still be in effect. Further code can be used to check for and correct such a condition, if needed.
Section D.3.6, “Considerations When x87 FPU Shared Between Tasks,” discusses an important example of this type
of problem and gives a solution.
D.2.2
MS-DOS* Compatibility Sub-mode in the P6 Family
and Pentium® 4 Processors
When bit NE = 0 in CR0, the MS-DOS compatibility mode of the P6 family and Pentium 4 processors provides
FERR# and IGNNE# functionality that is almost identical to the Intel486 and Pentium processors. The same
external hardware described in Section D.2.1.2, “Recommended External Hardware to Support the MS-DOS*
Compatibility Sub-mode,” is recommended for the P6 family and Pentium 4 processors as well as the two previous
generations. The only change to MS-DOS compatibility x87 FPU exception handling with the P6 family and Pentium
4 processors is that all exceptions for all x87 FPU instructions cause immediate error reporting. That is, FERR# is
asserted as soon as the x87 FPU detects an unmasked exception; there are no cases in which error reporting is
deferred to the next x87 FPU or WAIT instruction.
(As is discussed in Section D.2.1.1, “Basic Rules: When FERR# Is Generated,” most exception cases in the Intel486
and Pentium processors are of the deferred type.)
Although FERR# is asserted immediately upon detection of an unmasked x87 FPU error, this certainly does not
mean that the requested interrupt will always be serviced before the next instruction in the code sequence is
executed. To begin with, the P6 family and Pentium 4 processors execute several instructions simultaneously.
There also will be a delay, which depends on the external hardware implementation, between the FERR# assertion
from the processor and the responding INTR assertion to the processor. Further, the interrupt request to the PICs
(IRQ13) may be temporarily blocked by the operating system, or delayed by higher priority interrupts, and
processor response to INTR itself is blocked if the operating system has cleared the IF bit in EFLAGS. Note that
Streaming SIMD Extensions numeric exceptions will not cause assertion of FERR# (independent of the value of
CR0.NE). In addition, they ignore the assertion/deassertion of IGNNE#).
However, just as with the Intel486 and Pentium processors, if the IGNNE# input is inactive, a floating-point exception which occurred in the previous x87 FPU instruction and is unmasked causes the processor to freeze immediately when encountering the next WAIT or x87 FPU instruction (except for no-wait instructions). This means that if
the x87 FPU exception handler has not already been invoked due to the earlier exception (and therefore, the
handler not has cleared that exception state from the x87 FPU), the processor is forced to wait for the handler to
be invoked and handle the exception, before the processor can execute another WAIT or x87 FPU instruction.
As explained in Section D.2.1.3, “No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window,” if a no-wait
instruction is used outside of the x87 FPU exception handler, in the Intel486 and Pentium processors, it may accept
an unmasked exception from a previous x87 FPU instruction which happens to fall within the external interrupt
sampling window that is opened near the beginning of execution of all x87 FPU instructions. This will not happen in
the P6 family and Pentium 4 processors, because this sampling window has been removed from the no-wait group
of x87 FPU instructions.
D.3
RECOMMENDED PROTOCOL FOR MS-DOS* COMPATIBILITY HANDLERS
The activities of numeric programs can be split into two major areas: program control and arithmetic. The program
control part performs activities such as deciding what functions to perform, calculating addresses of numeric operands, and loop control. The arithmetic part simply adds, subtracts, multiplies, and performs other operations on
the numeric operands. The processor is designed to handle these two parts separately and efficiently. An x87 FPU
exception handler, if a system chooses to implement one, is often one of the most complicated parts of the program
control code.
Vol. 1 D-7
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
D.3.1
Floating-Point Exceptions and Their Defaults
The x87 FPU can recognize six classes of floating-point exception conditions while executing floating-point instructions:
1. #I — Invalid operation
#IS — Stack fault
#IA — IEEE standard invalid operation
2. #Z — Divide-by-zero
3. #D — Denormalized operand
4. #O — Numeric overflow
5. #U — Numeric underflow
6. #P — Inexact result (precision)
For complete details on these exceptions and their defaults, see Section 8.4, “x87 FPU Floating-Point Exception
Handling,” and Section 8.5, “x87 FPU Floating-Point Exception Conditions.”
D.3.2
Two Options for Handling Numeric Exceptions
Depending on options determined by the software system designer, the processor takes one of two possible
courses of action when a numeric exception occurs:
1. The x87 FPU can handle selected exceptions itself, producing a default fix-up that is reasonable in most
situations. This allows the numeric program execution to continue undisturbed. Programs can mask individual
exception types to indicate that the x87 FPU should generate this safe, reasonable result whenever the
exception occurs. The default exception fix-up activity is treated by the x87 FPU as part of the instruction
causing the exception; no external indication of the exception is given (except that the instruction takes longer
to execute when it handles a masked exception.) When masked exceptions are detected, a flag is set in the
numeric status register, but no information is preserved regarding where or when it was set.
2. A software exception handler can be invoked to handle the exception. When a numeric exception is unmasked
and the exception occurs, the x87 FPU stops further execution of the numeric instruction and causes a branch
to a software exception handler. The exception handler can then implement any sort of recovery procedures
desired for any numeric exception detectable by the x87 FPU.
D.3.2.1
Automatic Exception Handling: Using Masked Exceptions
Each of the six exception conditions described above has a corresponding flag bit in the x87 FPU status word and a
mask bit in the x87 FPU control word. If an exception is masked (the corresponding mask bit in the control word =
1), the processor takes an appropriate default action and continues with the computation.
The processor has a default fix-up activity for every possible exception condition it may encounter. These maskedexception responses are designed to be safe and are generally acceptable for most numeric applications.
For example, if the Inexact result (Precision) exception is masked, the system can specify whether the x87 FPU
should handle a result that cannot be represented exactly by one of four modes of rounding: rounding it normally,
chopping it toward zero, always rounding it up, or always down. If the Underflow exception is masked, the x87 FPU
will store a number that is too small to be represented in normalized form as a denormal (or zero if it’s smaller than
the smallest denormal). Note that when exceptions are masked, the x87 FPU may detect multiple exceptions in a
single instruction, because it continues executing the instruction after performing its masked response. For
example, the x87 FPU could detect a denormalized operand, perform its masked response to this exception, and
then detect an underflow.
As an example of how even severe exceptions can be handled safely and automatically using the default exception
responses, consider a calculation of the parallel resistance of several values using only the standard formula (see
Figure D-4). If R1 becomes zero, the circuit resistance becomes zero. With the divide-by-zero and precision exceptions masked, the processor will produce the correct result. FDIV of R1 into 1 gives infinity, and then FDIV of
(infinity +R2 +R3) into 1 gives zero.
D-8 Vol. 1
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
R1
R2
Equivalent Resistance =
R3
1
1
1
1
+
+
R1
R3
R2
Figure D-4. Arithmetic Example Using Infinity
By masking or unmasking specific numeric exceptions in the x87 FPU control word, programmers can delegate
responsibility for most exceptions to the processor, reserving the most severe exceptions for programmed exception handlers. Exception-handling software is often difficult to write, and the masked responses have been tailored
to deliver the most reasonable result for each condition. For the majority of applications, masking all exceptions
yields satisfactory results with the least programming effort. Certain exceptions can usefully be left unmasked
during the debugging phase of software development, and then masked when the clean software is actually run.
An invalid-operation exception for example, typically indicates a program error that must be corrected.
The exception flags in the x87 FPU status word provide a cumulative record of exceptions that have occurred since
these flags were last cleared. Once set, these flags can be cleared only by executing the FCLEX/FNCLEX (clear
exceptions) instruction, by reinitializing the x87 FPU with FINIT/FNINIT or FSAVE/FNSAVE, or by overwriting the
flags with an FRSTOR or FLDENV instruction. This allows a programmer to mask all exceptions, run a calculation,
and then inspect the status word to see if any exceptions were detected at any point in the calculation.
D.3.2.2
Software Exception Handling
If the x87 FPU in or with an IA-32 processor (Intel 286 and onwards) encounters an unmasked exception condition,
with the system operated in the MS-DOS compatibility mode and with IGNNE# not asserted, a software exception
handler is invoked through a PIC and the processor’s INTR pin. The FERR# (or ERROR#) output from the x87 FPU
that begins the process of invoking the exception handler may occur when the error condition is first detected, or
when the processor encounters the next WAIT or x87 FPU instruction. Which of these two cases occurs depends on
the processor generation and also on which exception and which x87 FPU instruction triggered it, as discussed
earlier in Section D.1, “MS-DOS Compatibility Sub-mode for Handling x87 FPU Exceptions,” and Section D.2,
“Implementation of the MS-DOS* Compatibility Sub-mode in the Intel486™, Pentium®, and P6 Processor Family,
and Pentium® 4 Processors.” The elapsed time between the initial error signal and the invocation of the x87 FPU
exception handler depends of course on the external hardware interface, and also on whether the external interrupt for x87 FPU errors is enabled. But the architecture ensures that the handler will be invoked before execution
of the next WAIT or floating-point instruction since an unmasked floating-point exception causes the processor to
freeze just before executing such an instruction (unless the IGNNE# input is active, or it is a no-wait x87 FPU
instruction).
The frozen processor waits for an external interrupt, which must be supplied by external hardware in response to
the FERR# (or ERROR#) output of the processor (or coprocessor), usually through IRQ13 on the “slave” PIC, and
then through INTR. Then the external interrupt invokes the exception handling routine. Note that if the external
interrupt for x87 FPU errors is disabled when the processor executes an x87 FPU instruction, the processor will
freeze until some other (enabled) interrupt occurs if an unmasked x87 FPU exception condition is in effect. If NE =
0 but the IGNNE# input is active, the processor disregards the exception and continues. Error reporting via an
external interrupt is supported for MS-DOS compatibility. Chapter 22, “IA-32 Architecture Compatibility,” of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, contains further discussion of compatibility issues.
Vol. 1 D-9
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
The references above to the ERROR# output from the x87 FPU apply to the Intel 387 and Intel 287 math coprocessors (NPX chips). If one of these coprocessors encounters an unmasked exception condition, it signals the exception to the Intel 286 or Intel386 processor using the ERROR# status line between the processor and the
coprocessor. See Section D.1, “MS-DOS Compatibility Sub-mode for Handling x87 FPU Exceptions,” in this
appendix, and Chapter 22, “IA-32 Architecture Compatibility,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3B, for differences in x87 FPU exception handling.
The exception-handling routine is normally a part of the systems software. The routine must clear (or disable) the
active exception flags in the x87 FPU status word before executing any floating-point instructions that cannot
complete execution when there is a pending floating-point exception. Otherwise, the floating-point instruction will
trigger the x87 FPU interrupt again, and the system will be caught in an endless loop of nested floating-point
exceptions, and hang. In any event, the routine must clear (or disable) the active exception flags in the x87 FPU
status word after handling them, and before IRET(D). Typical exception responses may include:
•
•
•
Incrementing an exception counter for later display or printing.
Printing or displaying diagnostic information (e.g., the x87 FPU environment and registers).
Aborting further execution, or using the exception pointers to build an instruction that will run without
exception and executing it.
Applications programmers should consult their operating system's reference manuals for the appropriate system
response to numerical exceptions. For systems programmers, some details on writing software exception handlers
are provided in Chapter 6, “Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A, as well as in Section D.3.4, “x87 FPU Exception Handling Examples,” in this
appendix.
As discussed in Section D.2.1.2, “Recommended External Hardware to Support the MS-DOS* Compatibility Submode,” some early FERR# to INTR hardware interface implementations are less robust than the recommended
circuit. This is because they depended on the exception handler to clear the x87 FPU exception interrupt request to
the PIC (by accessing port 0F0H) before the handler causes FERR# to be de-asserted by clearing the exception
from the x87 FPU itself. To eliminate the chance of a problem with this early hardware, Intel recommends that x87
FPU exception handlers always access port 0F0H before clearing the error condition from the x87 FPU.
D.3.3
Synchronization Required for Use of x87 FPU Exception Handlers
Concurrency or synchronization management requires a check for exceptions before letting the processor change
a value just used by the x87 FPU. It is important to remember that almost any numeric instruction can, under the
wrong circumstances, produce a numeric exception.
D.3.3.1
Exception Synchronization: What, Why, and When
Exception synchronization means that the exception handler inspects and deals with the exception in the context
in which it occurred. If concurrent execution is allowed, the state of the processor when it recognizes the exception
is often not in the context in which it occurred. The processor may have changed many of its internal registers and
be executing a totally different program by the time the exception occurs. If the exception handler cannot recapture the original context, it cannot reliably determine the cause of the exception or recover successfully from the
exception. To handle this situation, the x87 FPU has special registers updated at the start of each numeric instruction to describe the state of the numeric program when the failed instruction was attempted.
This provides tools to help the exception handler recapture the original context, but the application code must also
be written with synchronization in mind. Overall, exception synchronization must ensure that the x87 FPU and
other relevant parts of the context are in a well defined state when the handler is invoked after an unmasked
numeric exception occurs.
When the x87 FPU signals an unmasked exception condition, it is requesting help. The fact that the exception was
unmasked indicates that further numeric program execution under the arithmetic and programming rules of the
x87 FPU will probably yield invalid results. Thus the exception must be handled, and with proper synchronization,
or the program will not operate reliably.
For programmers using higher-level languages, all required synchronization is automatically provided by the
appropriate compiler. However, for assembly language programmers exception synchronization remains the
responsibility of the programmer. It is not uncommon for a programmer to expect that their numeric program will
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
not cause numeric exceptions after it has been tested and debugged, but in a different system or numeric environment, exceptions may occur regularly nonetheless. An obvious example would be use of the program with some
numbers beyond the range for which it was designed and tested. Example D-1 and Example D-2 in Section D.3.3.2,
“Exception Synchronization Examples,” show a subtle way in which unexpected exceptions can occur.
As described in Section D.3.1, “Floating-Point Exceptions and Their Defaults,” depending on options determined by
the software system designer, the processor can perform one of two possible courses of action when a numeric
exception occurs.
•
The x87 FPU can provide a default fix-up for selected numeric exceptions. If the x87 FPU performs its default
action for all exceptions, then the need for exception synchronization is not manifest. However, code is often
ported to contexts and operating systems for which it was not originally designed. Example D-1 and Example
D-2, below, illustrate that it is safest to always consider exception synchronization when designing code that
uses the x87 FPU.
•
Alternatively, a software exception handler can be invoked to handle the exception. When a numeric exception
is unmasked and the exception occurs, the x87 FPU stops further execution of the numeric instruction and
causes a branch to a software exception handler. When an x87 FPU exception handler will be invoked, synchronization must always be considered to assure reliable performance.
Example D-1 and Example D-2, below, illustrate the need to always consider exception synchronization when
writing numeric code, even when the code is initially intended for execution with exceptions masked.
D.3.3.2
Exception Synchronization Examples
In the following examples, three instructions are shown to load an integer, calculate its square root, then increment
the integer. The synchronous execution of the x87 FPU will allow both of these programs to execute correctly, with
INC COUNT being executed in parallel in the processor, as long as no exceptions occur on the FILD instruction.
However, if the code is later moved to an environment where exceptions are unmasked, the code in Example D-1
will not work correctly:
Example D-1. Incorrect Error Synchronization
FILD
COUNT
INC
COUNT
FSQRT
;x87 FPU instruction
;integer instruction alters operand
;subsequent x87 FPU instruction -- error
;from previous x87 FPU instruction detected here
Example D-2. Proper Error Synchronization
FILD
COUNT
FSQRT
INC
COUNT
;x87 FPU instruction
;subsequent x87 FPU instruction -- error from
;previous x87 FPU instruction detected here
;integer instruction alters operand
In some operating systems supporting the x87 FPU, the numeric register stack is extended to memory. To extend
the x87 FPU stack to memory, the invalid exception is unmasked. A push to a full register or pop from an empty
register sets SF (Stack Fault flag) and causes an invalid operation exception. The recovery routine for the exception
must recognize this situation, fix up the stack, then perform the original operation. The recovery routine will not
work correctly in Example D-1. The problem is that the value of COUNT increments before the exception handler is
invoked, so that the recovery routine will load an incorrect value of COUNT, causing the program to fail or behave
unreliably.
D.3.3.3
Proper Exception Synchronization
As explained in Section D.2.1.2, “Recommended External Hardware to Support the MS-DOS* Compatibility Submode,” if the x87 FPU encounters an unmasked exception condition a software exception handler is invoked before
execution of the next WAIT or floating-point instruction. This is because an unmasked floating-point exception
causes the processor to freeze immediately before executing such an instruction (unless the IGNNE# input is
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
active, or it is a no-wait x87 FPU instruction). Exactly when the exception handler will be invoked (in the interval
between when the exception is detected and the next WAIT or x87 FPU instruction) is dependent on the processor
generation, the system, and which x87 FPU instruction and exception is involved.
To be safe in exception synchronization, one should assume the handler will be invoked at the end of the interval.
Thus the program should not change any value that might be needed by the handler (such as COUNT in Example
D-1 and Example D-2) until after the next x87 FPU instruction following an x87 FPU instruction that could cause
an error. If the program needs to modify such a value before the next x87 FPU instruction (or if the next x87 FPU
instruction could also cause an error), then a WAIT instruction should be inserted before the value is modified. This
will force the handling of any exception before the value is modified. A WAIT instruction should also be placed after
the last floating-point instruction in an application so that any unmasked exceptions will be serviced before the task
completes.
D.3.4
x87 FPU Exception Handling Examples
There are many approaches to writing exception handlers. One useful technique is to consider the exception
handler procedure as consisting of “prologue,” “body,” and “epilogue” sections of code.
In the transfer of control to the exception handler due to an INTR, NMI, or SMI, external interrupts have been
disabled by hardware. The prologue performs all functions that must be protected from possible interruption by
higher-priority sources. Typically, this involves saving registers and transferring diagnostic information from the
x87 FPU to memory. When the critical processing has been completed, the prologue may re-enable interrupts to
allow higher-priority interrupt handlers to preempt the exception handler. The standard “prologue” not only saves
the registers and transfers diagnostic information from the x87 FPU to memory but also clears the floating-point
exception flags in the status word. Alternatively, when it is not necessary for the handler to be re-entrant, another
technique may also be used. In this technique, the exception flags are not cleared in the “prologue” and the body
of the handler must not contain any floating-point instructions that cannot complete execution when there is a
pending floating-point exception. (The no-wait instructions are discussed in Section 8.3.12, “Waiting vs. Nonwaiting Instructions.”) Note that the handler must still clear the exception flag(s) before executing the IRET. If the
exception handler uses neither of these techniques, the system will be caught in an endless loop of nested floatingpoint exceptions, and hang.
The body of the exception handler examines the diagnostic information and makes a response that is necessarily
application-dependent. This response may range from halting execution, to displaying a message, to attempting to
repair the problem and proceed with normal execution. The epilogue essentially reverses the actions of the
prologue, restoring the processor so that normal execution can be resumed. The epilogue must not load an
unmasked exception flag into the x87 FPU or another exception will be requested immediately.
The following code examples show the ASM386/486 coding of three skeleton exception handlers, with the save
spaces given as correct for 32-bit protected mode. They show how prologues and epilogues can be written for
various situations, but the application-dependent exception handling body is just indicated by comments showing
where it should be placed.
The first two are very similar; their only substantial difference is their choice of instructions to save and restore the
x87 FPU. The trade-off here is between the increased diagnostic information provided by FNSAVE and the faster
execution of FNSTENV. (Also, after saving the original contents, FNSAVE re-initializes the x87 FPU, while FNSTENV
only masks all x87 FPU exceptions.) For applications that are sensitive to interrupt latency or that do not need to
examine register contents, FNSTENV reduces the duration of the “critical region,” during which the processor does
not recognize another interrupt request. (See the Section 8.1.10, “Saving the x87 FPU’s State with
FSTENV/FNSTENV and FSAVE/FNSAVE,” for a complete description of the x87 FPU save image.) If the processor
supports Streaming SIMD Extensions and the operating system supports it, the FXSAVE instruction should be used
instead of FNSAVE. If the FXSAVE instruction is used, the save area should be increased to 512 bytes and aligned
to 16 bytes to save the entire state. These steps will ensure that the complete context is saved.
After the exception handler body, the epilogues prepare the processor to resume execution from the point of interruption (for example, the instruction following the one that generated the unmasked exception). Notice that the
exception flags in the memory image that is loaded into the x87 FPU are cleared to zero prior to reloading (in fact,
in these examples, the entire status word image is cleared).
Example D-3 and Example D-4 assume that the exception handler itself will not cause an unmasked exception.
Where this is a possibility, the general approach shown in Example D-5 can be employed. The basic technique is to
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
save the full x87 FPU state and then to load a new control word in the prologue. Note that considerable care should
be taken when designing an exception handler of this type to prevent the handler from being reentered endlessly.
Example D-3. Full-State Exception Handler
SAVE_ALL PROC
;
;SAVE REGISTERS, ALLOCATE STACK SPACE FOR x87 FPU STATE IMAGE
PUSH
EBP
.
.
MOV
EBP, ESP
SUB
ESP, 108 ; ALLOCATES 108 BYTES (32-bit PROTECTED MODE SIZE)
;SAVE FULL x87 FPU STATE, RESTORE INTERRUPT ENABLE FLAG (IF)
FNSAVE [EBP-108]
PUSH
[EBP + OFFSET_TO_EFLAGS] ; COPY OLD EFLAGS TO STACK TOP
POPFD ;RESTORE IF TO VALUE BEFORE x87 FPU EXCEPTION
;
;APPLICATION-DEPENDENT EXCEPTION HANDLING CODE GOES HERE
;
;CLEAR EXCEPTION FLAGS IN STATUS WORD (WHICH IS IN MEMORY)
;RESTORE MODIFIED STATE IMAGE
MOV
BYTE PTR [EBP-104], 0H
FRSTOR [EBP-108]
;DE-ALLOCATE STACK SPACE, RESTORE REGISTERS
MOV
ESP, EBP
.
.
POP
EBP
;
;RETURN TO INTERRUPTED CALCULATION
IRETD
SAVE_ALL
ENDP
Example D-4. Reduced-Latency Exception Handler
SAVE_ENVIRONMENTPROC
;
;SAVE REGISTERS, ALLOCATE STACK SPACE FOR x87 FPU ENVIRONMENT
PUSH
EBP
.
.
MOV
EBP, ESP
SUB
ESP, 28 ;ALLOCATES 28 BYTES (32-bit PROTECTED MODE SIZE)
;SAVE ENVIRONMENT, RESTORE INTERRUPT ENABLE FLAG (IF)
FNSTENV
[EBP - 28]
PUSH
[EBP + OFFSET_TO_EFLAGS] ; COPY OLD EFLAGS TO STACK TOP
POPFD ;RESTORE IF TO VALUE BEFORE x87 FPU EXCEPTION
;
;APPLICATION-DEPENDENT EXCEPTION HANDLING CODE GOES HERE
;
;CLEAR EXCEPTION FLAGS IN STATUS WORD (WHICH IS IN MEMORY)
;RESTORE MODIFIED ENVIRONMENT IMAGE
MOV
BYTE PTR [EBP-24], 0H
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
FLDENV [EBP-28]
;DE-ALLOCATE STACK SPACE, RESTORE REGISTERS
MOV
ESP, EBP
.
.
POP
EBP
;
;RETURN TO INTERRUPTED CALCULATION
IRETD
SAVE_ENVIRONMENT ENDP
Example D-5. Reentrant Exception Handler
.
.
LOCAL_CONTROL DW ?; ASSUME INITIALIZED
.
.
REENTRANTPROC
;
;SAVE REGISTERS, ALLOCATE STACK SPACE FOR x87 FPU STATE IMAGE
PUSH
EBP
.
.
MOV
EBP, ESP
SUB
ESP, 108 ;ALLOCATES 108 BYTES (32-bit PROTECTED MODE SIZE)
;SAVE STATE, LOAD NEW CONTROL WORD, RESTORE INTERRUPT ENABLE FLAG (IF)
FNSAVE [EBP-108]
FLDCW LOCAL_CONTROL
PUSH
[EBP + OFFSET_TO_EFLAGS] ;COPY OLD EFLAGS TO STACK TOP
POPFD ;RESTORE IF TO VALUE BEFORE x87 FPU EXCEPTION
.
.
;
;APPLICATION-DEPENDENT EXCEPTION HANDLING CODE
;GOES HERE - AN UNMASKED EXCEPTION
;GENERATED HERE WILL CAUSE THE EXCEPTION HANDLER TO BE REENTERED
;IF LOCAL STORAGE IS NEEDED, IT MUST BE ALLOCATED ON THE STACK
.
;CLEAR EXCEPTION FLAGS IN STATUS WORD (WHICH IS IN MEMORY)
;RESTORE MODIFIED STATE IMAGE
MOV
BYTE PTR [EBP-104], 0H
FRSTOR [EBP-108]
;DE-ALLOCATE STACK SPACE, RESTORE REGISTERS
MOV
ESP, EBP
.
.
POP
EBP
;
;RETURN TO POINT OF INTERRUPTION
IRETD
REENTRANT ENDP
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D.3.5
Need for Storing State of IGNNE# Circuit If Using x87 FPU and SMM
The recommended circuit (see Figure D-1) for MS-DOS compatibility x87 FPU exception handling for Intel486
processors and beyond contains two flip flops. When the x87 FPU exception handler accesses I/O port 0F0H it
clears the IRQ13 interrupt request output from Flip Flop #1 and also clocks out the IGNNE# signal (active) from
Flip Flop #2.
The assertion of IGNNE# may be used by the handler if needed to execute any x87 FPU instruction while ignoring
the pending x87 FPU errors. The problem here is that the state of Flip Flop #2 is effectively an additional (but
hidden) status bit that can affect processor behavior, and so ideally should be saved upon entering SMM, and
restored before resuming to normal operation. If this is not done, and also the SMM code saves the x87 FPU state,
AND an x87 FPU error handler is being used which relies on IGNNE# assertion, then (very rarely) the x87 FPU
handler will nest inside itself and malfunction. The following example shows how this can happen.
Suppose that the x87 FPU exception handler includes the following sequence:
FNSTSW save_sw
OUT
0F0H, AL
....
FLDCW new_cw
....
FCLEX
; save the x87 FPU status word
; using a no-wait x87 FPU instruction
; clears IRQ13 & activates IGNNE#
; loads new CW ignoring x87 FPU errors,
; since IGNNE# is assumed active; or any
; other x87 FPU instruction that is not a no-wait
; type will cause the same problem
; clear the x87 FPU error conditions & thus
; turn off FERR# & reset the IGNNE# FF
The problem will only occur if the processor enters SMM between the OUT and the FLDCW instructions. But if that
happens, AND the SMM code saves the x87 FPU state using FNSAVE, then the IGNNE# Flip Flop will be cleared
(because FNSAVE clears the x87 FPU errors and thus de-asserts FERR#). When the processor returns from SMM it
will restore the x87 FPU state with FRSTOR, which will re-assert FERR#, but the IGNNE# Flip Flop will not get set.
Then when the x87 FPU error handler executes the FLDCW instruction, the active error condition will cause the
processor to re-enter the x87 FPU error handler from the beginning. This may cause the handler to malfunction.
To avoid this problem, Intel recommends two measures:
1. Do not use the x87 FPU for calculations inside SMM code. (The normal power management, and sometimes
security, functions provided by SMM have no need for x87 FPU calculations; if they are needed for some special
case, use scaling or emulation instead.) This eliminates the need to do FNSAVE/FRSTOR inside SMM code,
except when going into a 0 V suspend state (in which, in order to save power, the CPU is turned off completely,
requiring its complete state to be saved).
2. The system should not call upon SMM code to put the processor into 0 V suspend while the processor is running
x87 FPU calculations, or just after an interrupt has occurred. Normal power management protocol avoids this
by going into power down states only after timed intervals in which no system activity occurs.
D.3.6
Considerations When x87 FPU Shared Between Tasks
The IA-32 architecture allows speculative deferral of floating-point state swaps on task switches. This feature
allows postponing an x87 FPU state swap until an x87 FPU instruction is actually encountered in another task. Since
kernel tasks rarely use floating-point, and some applications do not use floating-point or use it infrequently, the
amount of time saved by avoiding unnecessary stores of the floating-point state is significant. Speculative deferral
of x87 FPU saves does, however, place an extra burden on the kernel in three key ways:
1. The kernel must keep track of which thread owns the x87 FPU, which may be different from the currently
executing thread.
2. The kernel must associate any floating-point exceptions with the generating task. This requires special
handling since floating-point exceptions are delivered asynchronous with other system activity.
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
3. There are conditions under which spurious floating-point exception interrupts are generated, which the kernel
must recognize and discard.
D.3.6.1
Speculatively Deferring x87 FPU Saves, General Overview
In order to support multitasking, each thread in the system needs a save area for the general-purpose registers,
and each task that is allowed to use floating-point needs an x87 FPU save area large enough to hold the entire x87
FPU stack and associated x87 FPU state such as the control word and status word. (See Section 8.1.10, “Saving the
x87 FPU’s State with FSTENV/FNSTENV and FSAVE/FNSAVE,” for a complete description of the x87 FPU save
image.) If the processor and the operating system support Streaming SIMD Extensions, the save area should be
large enough and aligned correctly to hold x87 FPU and Streaming SIMD Extensions state.
On a task switch, the general-purpose registers are swapped out to their save area for the suspending thread, and
the registers of the resuming thread are loaded. The x87 FPU state does not need to be saved at this point. If the
resuming thread does not use the x87 FPU before it is itself suspended, then both a save and a load of the x87 FPU
state has been avoided. It is often the case that several threads may be executed without any usage of the x87
FPU.
The processor supports speculative deferral of x87 FPU saves via interrupt 7 “Device Not Available” (DNA), used in
conjunction with CR0 bit 3, the “Task Switched” bit (TS). (See “Control Registers” in Chapter 2 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A.) Every task switch via the hardware supported task
switching mechanism (see “Task Switching” in Chapter 7 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A) sets TS. Multi-threaded kernels that use software task switching1 can set the TS bit by
reading CR0, ORing a “1” into2 bit 3, and writing back CR0. Any subsequent floating-point instructions (now being
executed in a new thread context) will fault via interrupt 7 before execution.
This allows a DNA handler to save the old floating-point context and reload the x87 FPU state for the current
thread. The handler should clear the TS bit before exit using the CLTS instruction. On return from the handler the
faulting thread will proceed with its floating-point computation.
Some operating systems save the x87 FPU context on every task switch, typically because they also change the
linear address space between tasks. The problem and solution discussed in the following sections apply to these
operating systems also.
D.3.6.2
Tracking x87 FPU Ownership
Since the contents of the x87 FPU may not belong to the currently executing thread, the thread identifier for the
last x87 FPU user needs to be tracked separately. This is not complicated; the kernel should simply provide a variable to store the thread identifier of the x87 FPU owner, separate from the variable that stores the identifier for the
currently executing thread. This variable is updated in the DNA exception handler, and is used by the DNA exception handler to find the x87 FPU save areas of the old and new threads. A simplified flow for a DNA exception
handler is then:
1. Use the “x87 FPU Owner” variable to find the x87 FPU save area of the last thread to use the x87 FPU.
2. Save the x87 FPU contents to the old thread’s save area, typically using an FNSAVE or FXSAVE instruction.
3. Set the x87 FPU Owner variable to the identify the currently executing thread.
4. Reload the x87 FPU contents from the new thread’s save area, typically using an FRSTOR or FXSTOR
instruction.
5. Clear TS using the CLTS instruction and exit the DNA exception handler.
While this flow covers the basic requirements for speculatively deferred x87 FPU state swaps, there are some additional subtleties that need to be handled in a robust implementation.
1 In a software task switch, the operating system uses a sequence of instructions to save the suspending thread’s state and restore
the resuming thread’s state, instead of the single long non-interruptible task switch operation provided by the IA-32 architecture.
2 Although CR0, bit 2, the emulation flag (EM), also causes a DNA exception, do not use the EM bit as a surrogate for TS. EM means that
no x87 FPU is available and that floating-point instructions must be emulated. Using EM to trap on task switches is not compatible
with the MMX technology. If the EM flag is set, MMX instructions raise the invalid opcode exception.
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D.3.6.3
Interaction of x87 FPU State Saves and Floating-Point Exception Association
Recall these key points from earlier in this document: When considering floating-point exceptions across all implementations of the IA-32 architecture, and across all floating-point instructions, a floating-point exception can be
initiated from any time during the excepting floating-point instruction, up to just before the next floating-point
instruction. The “next” floating-point instruction may be the FNSAVE used to save the x87 FPU state for a task
switch. In the case of “no-wait:” instructions such as FNSAVE, the interrupt from a previously excepting instruction (NE = 0 case) may arrive just before the no-wait instruction, during, or shortly thereafter with a system
dependent delay.
Note that this implies that an floating-point exception might be registered during the state swap process itself, and
the kernel and floating-point exception interrupt handler must be prepared for this case.
A simple way to handle the case of exceptions arriving during x87 FPU state swaps is to allow the kernel to be one
of the x87 FPU owning threads. A reserved thread identifier is used to indicate kernel ownership of the x87 FPU.
During an floating-point state swap, the “x87 FPU owner” variable should be set to indicate the kernel as the
current owner. At the completion of the state swap, the variable should be set to indicate the new owning thread.
The numeric exception handler needs to check the x87 FPU owner and discard any numeric exceptions that occur
while the kernel is the x87 FPU owner. A more general flow for a DNA exception handler that handles this case is
shown in Figure D-5.
Numeric exceptions received while the kernel owns the x87 FPU for a state swap must be discarded in the kernel
without being dispatched to a handler. A flow for a numeric exception dispatch routine is shown in Figure D-6.
It may at first glance seem that there is a possibility of floating-point exceptions being lost because of exceptions
that are discarded during state swaps. This is not the case, as the exception will be re-issued when the floatingpoint state is reloaded. Walking through state swaps both with and without pending numeric exceptions will clarify
the operation of these two handlers.
DNA Handler Entry
Current Thread
same as
FPU Owner?
Yes
No
FPU Owner := Kernel
FNSAVE to Old Thread’s
FP Save Area
(may cause numeric exception)
FRSTOR from Current Thread’s
FP Save Area
CLTS (clears CR0.TS)
Exit DNA Handler
FPU Owner := Current Thread
Figure D-5. General Program Flow for DNA Exception Handler
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
Numeric Exception Entry
Is Kernel
FPU Owner?
Yes
No
Normal Dispatch to
Numeric Exception Handler
Exit
Figure D-6. Program Flow for a Numeric Exception Dispatch Routine
Case #1: x87 FPU State Swap Without Numeric Exception
Assume two threads A and B, both using the floating-point unit. Let A be the thread to have most recently executed
a floating-point instruction, with no pending numeric exceptions. Let B be the currently executing thread. CR0.TS
was set when thread A was suspended.
When B starts to execute a floating-point instruction the instruction will fault with the DNA exception because TS is
set.
At this point the handler is entered, and eventually it finds that the current x87 FPU Owner is not the currently
executing thread. To guard the x87 FPU state swap from extraneous numeric exceptions, the x87 FPU Owner is set
to be the kernel. The old owner’s x87 FPU state is saved with FNSAVE, and the current thread’s x87 FPU state is
restored with FRSTOR. Before exiting, the x87 FPU owner is set to thread B, and the TS bit is cleared.
On exit, thread B resumes execution of the faulting floating-point instruction and continues.
Case #2: x87 FPU State Swap with Discarded Numeric Exception
Again, assume two threads A and B, both using the floating-point unit. Let A be the thread to have most recently
executed a floating-point instruction, but this time let there be a pending numeric exception. Let B be the currently
executing thread. When B starts to execute a floating-point instruction the instruction will fault with the DNA
exception and enter the DNA handler. (If both numeric and DNA exceptions are pending, the DNA exception takes
precedence, in order to support handling the numeric exception in its own context.)
When the FNSAVE starts, it will trigger an interrupt via FERR# because of the pending numeric exception. After
some system dependent delay, the numeric exception handler is entered. It may be entered before the FNSAVE
starts to execute, or it may be entered shortly after execution of the FNSAVE. Since the x87 FPU Owner is the
kernel, the numeric exception handler simply exits, discarding the exception. The DNA handler resumes execution,
completing the FNSAVE of the old floating-point context of thread A and the FRSTOR of the floating-point context
for thread B.
Thread A eventually gets an opportunity to handle the exception that was discarded during the task switch. After
some time, thread B is suspended, and thread A resumes execution. When thread A starts to execute an floatingpoint instruction, once again the DNA exception handler is entered. B’s x87 FPU state is saved with FNSAVE, and A’s
x87 FPU state is restored with FRSTOR. Note that in restoring the x87 FPU state from A’s save area, the pending
numeric exception flags are reloaded into the floating-point status word. Now when the DNA exception handler
returns, thread A resumes execution of the faulting floating-point instruction just long enough to immediately
generate a numeric exception, which now gets handled in the normal way. The net result is that the task switch and
resulting x87 FPU state swap via the DNA exception handler causes an extra numeric exception which can be safely
discarded.
D.3.6.4
Interrupt Routing From the Kernel
In MS-DOS, an application that wishes to handle numeric exceptions hooks interrupt 16 by placing its handler
address in the interrupt vector table, and exiting via a jump to the previous interrupt 16 handler. Protected mode
systems that run MS-DOS programs under a subsystem can emulate this exception delivery mechanism. For
example, assume a protected mode OS. that runs with CR0.NE[bit 5] = 1, and that runs MS-DOS programs in a
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
virtual machine subsystem. The MS-DOS program is set up in a virtual machine that provides a virtualized interrupt table. The MS-DOS application hooks interrupt 16 in the virtual machine in the normal way. A numeric exception will trap to the kernel via the real INT 16 residing in the kernel at ring 0.
The INT 16 handler in the kernel then locates the correct MS-DOS virtual machine, and reflects the interrupt to the
virtual machine monitor. The virtual machine monitor then emulates an interrupt by jumping through the address
in the virtualized interrupt table, eventually reaching the application’s numeric exception handler.
D.3.6.5
Special Considerations for Operating Systems that Support Streaming SIMD Extensions
Operating systems that support Streaming SIMD Extensions instructions introduced with the Pentium III processor
should use the FXSAVE and FXRSTOR instructions to save and restore the new SIMD floating-point instruction
register state as well as the floating-point state. Such operating systems must consider the following issues:
1. Enlarged state save area — FNSAVE/FRSTOR instructions operate on a 94-byte or 108-byte memory region,
depending on whether they are executed in 16-bit or 32-bit mode. The FXSAVE/FXRSTOR instructions operate
on a 512-byte memory region.
2. Alignment requirements — FXSAVE/FXRSTOR instructions require the memory region on which they operate
to be 16-byte aligned (refer to the individual instruction instructions descriptions in Chapter 3 of the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 2A, for information about exceptions generated
if the memory region is not aligned).
3. Maintaining compatibility with legacy applications/libraries — The operating system changes to
support Streaming SIMD Extensions must be invisible to legacy applications or libraries that deal only with
floating-point instructions. The layout of the memory region operated on by the FXSAVE/FXRSTOR instructions
is different from the layout for the FNSAVE/FRSTOR instructions. Specifically, the format of the x87 FPU tag
word and the length of the various fields in the memory region is different. Care must be taken to return the
x87 FPU state to a legacy application (e.g., when reporting FP exceptions) in the format it expects.
4. Instruction semantic differences — There are some semantic differences between the way the FXSAVE and
FSAVE/FNSAVE instructions operate. The FSAVE/FNSAVE instructions clear the x87 FPU after they save the
state while the FXSAVE instruction saves the x87 FPU/Streaming SIMD Extensions state but does not clear it.
Operating systems that use FXSAVE to save the x87 FPU state before making it available for another thread
(e.g., during thread switch time) should take precautions not to pass a “dirty” x87 FPU to another application.
D.4
DIFFERENCES FOR HANDLERS USING NATIVE MODE
The 8087 has an INT pin which it asserts when an unmasked exception occurs. But there is no interrupt input pin
in the 8086 or 8088 dedicated to its attachment, nor an interrupt vector in the 8086 or 8088 specific for an x87 FPU
error assertion. Beginning with the Intel 286 and Intel 287 hardware, a connection was dedicated to support the
x87 FPU exception and interrupt vector 16 was assigned to it.
D.4.1
Origin with the Intel 286 and Intel 287, and Intel386 and Intel 387 Processors
The Intel 286 and Intel 287, and Intel386 and Intel 387 processor/coprocessor pairs are each provided with
ERROR# pins that are recommended to be connected between the processor and x87 FPU. If this is done, when an
unmasked x87 FPU exception occurs, the x87 FPU records the exception, and asserts its ERROR# pin. The
processor recognizes this active condition of the ERROR# status line immediately before execution of the next
WAIT or x87 FPU instruction (except for the no-wait type) in its instruction stream, and branches to the handler of
interrupt 16. Thus an x87 FPU exception will be handled before any other x87 FPU instruction (after the one
causing the error) is executed (except for no-wait instructions, which will be executed without triggering the x87
FPU exception interrupt, but it will remain pending).
Using the dedicated INT 16 for x87 FPU exception handling is referred to as the native mode. It is the simplest
approach, and the one recommended most highly by Intel.
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GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
D.4.2
Changes with Intel486, Pentium and Pentium Pro Processors with CR0.NE[bit 5] = 1
With these three generations of the IA-32 architecture, more enhancements and speedup features have been
added to the corresponding x87 FPUs. Also, the x87 FPU is now built into the same chip as the processor, which
allows further increases in the speed at which the x87 FPU can operate as part of the integrated system. This also
means that the native mode of x87 FPU exception handling, selected by setting bit NE of register CR0 to 1, is now
entirely internal.
If an unmasked exception occurs during an x87 FPU instruction, the x87 FPU records the exception internally, and
triggers the exception handler through interrupt 16 immediately before execution of the next WAIT or x87 FPU
instruction (except for no-wait instructions, which will be executed as described in Section D.4.1, “Origin with the
Intel 286 and Intel 287, and Intel386 and Intel 387 Processors”).
An unmasked numerical exception causes the FERR# output to be activated even with NE = 1, and at exactly the
same point in the program flow as it would have been asserted if NE were zero. However, the system would not
connect FERR# to a PIC to generate INTR when operating in the native, internal mode. (If the hardware of a system
has FERR# connected to trigger IRQ13 in order to support MS-DOS, but an operating system using the native mode
is actually running the system, it is the operating system’s responsibility to make sure that IRQ13 is not enabled in
the slave PIC.) With this configuration a system is immune to the problem discussed in Section D.2.1.3, “No-Wait
x87 FPU Instructions Can Get x87 FPU Interrupt in Window,” where for Intel486 and Pentium processors a no-wait
x87 FPU instruction can get an x87 FPU exception.
D.4.3
Considerations When x87 FPU Shared Between Tasks Using Native Mode
The protocols recommended in Section D.3.6, “Considerations When x87 FPU Shared Between Tasks,” for MS-DOS
compatibility x87 FPU exception handlers that are shared between tasks may be used without change with the
native mode. However, the protocols for a handler written specifically for native mode can be simplified, because
the problem of a spurious floating-point exception interrupt occurring while the kernel is executing cannot happen
in native mode.
The problem as actually found in practical code in a MS-DOS compatibility system happens when the DNA handler
uses FNSAVE to switch x87 FPU contexts. If an x87 FPU exception is active, then FNSAVE triggers FERR# briefly,
which usually will cause the x87 FPU exception handler to be invoked inside the DNA handler. In native mode,
neither FNSAVE nor any other no-wait instructions can trigger interrupt 16. (As discussed above, FERR# gets
asserted independent of the value of the NE bit, but when NE = 1, the operating system should not enable its path
through the PIC.) Another possible (very rare) way a floating-point exception interrupt could occur while the kernel
is executing is by an x87 FPU immediate exception case having its interrupt delayed by the external hardware until
execution has switched to the kernel. This also cannot happen in native mode because there is no delay through
external hardware.
Thus the native mode x87 FPU exception handler can omit the test to see if the kernel is the x87 FPU owner, and
the DNA handler for a native mode system can omit the step of setting the kernel as the x87 FPU owner at the
handler’s beginning. Since however these simplifications are minor and save little code, it would be a reasonable
and conservative habit (as long as the MS-DOS compatibility mode is widely used) to include these steps in all
systems.
Note that the special DP (Dual Processing) mode for Pentium processors, and also the more general Intel MultiProcessor Specification for systems with multiple Pentium, P6 family, or Pentium 4 processors, support x87 FPU
exception handling only in the native mode. Intel does not recommend using the MS-DOS compatibility mode for
systems using more than one processor.
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APPENDIX E
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION
HANDLERS
See Section 11.5, “SSE, SSE2, and SSE3 Exceptions,” for a detailed discussion of SIMD floating-point exceptions.
This appendix considers only SSE/SSE2/SSE3 instructions that can generate numeric (SIMD floating-point) exceptions, and gives an overview of the necessary support for handling such exceptions. This appendix does not
address instructions that do not generate floating-point exceptions (such as RSQRTSS, RSQRTPS, RCPSS, or
RCPPS), any x87 instructions, or any unlisted instruction.
For detailed information on which instructions generate numeric exceptions, and a listing of those exceptions, refer
to Appendix C, “Floating-Point Exceptions Summary.” Non-numeric exceptions are handled in a way similar to that
for the standard IA-32 instructions.
E.1
TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS
Just as for x87 FPU floating-point exceptions, the processor takes one of two possible courses of action when an
SSE/SSE2/SSE3 instruction raises a floating-point exception:
•
If the exception being raised is masked (by setting the corresponding mask bit in the MXCSR to 1), then a
default result is produced which is acceptable in most situations. No external indication of the exception is
given, but the corresponding exception flags in the MXCSR are set and may be examined later. Note though
that for packed operations, an exception flag that is set in the MXCSR will not tell which of the sub-operands
caused the event to occur.
•
If the exception being raised is not masked (by setting the corresponding mask bit in the MXCSR to 0), a
software exception handler previously registered by the user with operating system support will be invoked
through the SIMD floating-point exception (#XM, exception 19). This case is discussed below in Section E.2,
“Software Exception Handling.”
E.2
SOFTWARE EXCEPTION HANDLING
The #XM handler is usually part of the system software (the operating system kernel). Note that an interrupt
descriptor table (IDT) entry must have been previously set up for exception 19 (refer to Chapter 6, “Interrupt and
Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). Some
compilers use specific run-time libraries to assist in floating-point exception handling. If any x87 FPU floating-point
operations are going to be performed that might raise floating-point exceptions, then the exception handling
routine must either disable all floating-point exceptions (for example, loading a local control word with FLDCW), or
it must be implemented as re-entrant (for the case of x87 FPU exceptions, refer to Example D-1 in Appendix D,
“Guidelines for Writing x87 FPU Exception Handlers”). If this is not the case, the routine has to clear the status flags
for x87 FPU exceptions or to mask all x87 FPU floating-point exceptions. For SIMD floating-point exceptions
though, the exception flags in MXCSR do not have to be cleared, even if they remain unmasked (but they may still
be cleared). Exceptions are in this case precise and occur immediately, and a SIMD floating-point exception status
flag that is set when the corresponding exception is unmasked will not generate an exception.
Typical actions performed by this low-level exception handling routine are:
•
•
•
Incrementing an exception counter for later display or printing
•
Storing information about the exception in a data structure that will be passed to a higher level user exception
handler
Printing or displaying diagnostic information (e.g. the MXCSR and XMM registers)
Aborting further execution, or using the exception pointers to build an instruction that will run without
exception and executing it
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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
In most cases (and this applies also to SSE/SSE2/SSE3 instructions), there will be three main components of a lowlevel floating-point exception handler: a prologue, a body, and an epilogue.
The prologue performs functions that must be protected from possible interruption by higher-priority sources typically saving registers and transferring diagnostic information from the processor to memory. When the critical
processing has been completed, the prologue may re-enable interrupts to allow higher-priority interrupt handlers
to preempt the exception handler (assuming that the interrupt handler was called through an interrupt gate,
meaning that the processor cleared the interrupt enable (IF) flag in the EFLAGS register - refer to Section 6.4.1,
“Call and Return Operation for Interrupt or Exception Handling Procedures”).
The body of the exception handler examines the diagnostic information and makes a response that is applicationdependent. It may range from halting execution, to displaying a message, to attempting to fix the problem and
then proceeding with normal execution, to setting up a data structure, calling a higher-level user exception handler
and continuing execution upon return from it. This latter case will be assumed in Section E.4, “SIMD Floating-Point
Exceptions and the IEEE Standard 754” below.
Finally, the epilogue essentially reverses the actions of the prologue, restoring the processor state so that normal
execution can be resumed.
The following example represents a typical exception handler. To link it with Example E-2 that will follow in Section
E.4.3, “Example SIMD Floating-Point Emulation Implementation,” assume that the body of the handler (not shown
here in detail) passes the saved state to a routine that will examine in turn all the sub-operands of the excepting
instruction, invoking a user floating-point exception handler if a particular set of sub-operands raises an unmasked
(enabled) exception, or emulating the instruction otherwise.
Example E-1. SIMD Floating-Point Exception Handler
SIMD_FP_EXC_HANDLER PROC
;PROLOGUE
;SAVE REGISTERS THAT MIGHT BE USED BY THE EXCEPTION HANDLER
PUSH EBP
;SAVE EBP
PUSH EAX
;SAVE EAX
...
MOV EBP, ESP
;SAVE ESP in EBP
SUB ESP, 512
;ALLOCATE 512 BYTES
AND ESP, 0fffffff0h
;MAKE THE ADDRESS 16-BYTE ALIGNED
FXSAVE [ESP]
;SAVE FP, MMX, AND SIMD FP STATE
PUSH [EBP+EFLAGS_OFFSET]
;COPY OLD EFLAGS TO STACK TOP
POPFD
;RESTORE THE INTERRUPT ENABLE FLAG IF
;TO VALUE BEFORE SIMD FP EXCEPTION
;BODY
;APPLICATION-DEPENDENT EXCEPTION HANDLING CODE GOES HERE
LDMXCSR LOCAL_MXCSR
;LOAD LOCAL MXCSR VALUE IF NEEDED
...
...
;EPILOGUE
FXRSTOR [ESP]
;RESTORE MODIFIED STATE IMAGE
MOV ESP, EBP
;DE-ALLOCATE STACK SPACE
...
POP EAX
;RESTORE EAX
POP EBP
;RESTORE EBP
IRET
;RETURN TO INTERRUPTED CALCULATION
SIMD_FP_EXC_HANDLER ENDP
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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
E.3
EXCEPTION SYNCHRONIZATION
An SSE/SSE2/SSE3 instruction can execute in parallel with other similar instructions, with integer instructions, and
with floating-point or MMX instructions. Unlike for x87 instructions, special precaution for exception synchronization is not necessary in this case. This is because floating-point exceptions for SSE/SSE2/SSE3 instructions occur
immediately and are not delayed until a subsequent floating-point instruction is executed. However, floatingpoint emulation may be necessary when unmasked floating-point exceptions are generated.
E.4
SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754
SSE/SSE2/SSE3 extensions are 100% compatible with the IEEE Standard 754 for Binary Floating-Point Arithmetic,
satisfying all of its mandatory requirements (when the flush-to-zero or denormals-are-zeros modes are not
enabled). But a programming environment that includes SSE/SSE2/SSE3 instructions will comply with both the
obligatory and the strongly recommended requirements of the IEEE Standard 754 regarding floating-point exception handling, only as a combination of hardware and software (which is acceptable). The standard states that a
user should be able to request a trap on any of the five floating-point exceptions (note that the denormal exception
is an IA-32 addition), and it also specifies the values (operands or result) to be delivered to the exception handler.
The main issue is that for SSE/SSE2/SSE3 instructions that raise post-computation exceptions (traps: overflow,
underflow, or inexact), unlike for x87 FPU instructions, the processor does not provide the result recommended by
IEEE Standard 754 to the user handler. If a user program needs the result of an instruction that generated a postcomputation exception, it is the responsibility of the software to produce this result by emulating the faulting
SSE/SSE2/SSE3 instruction. Another issue is that the standard does not specify explicitly how to handle multiple
floating-point exceptions that occur simultaneously. For packed operations, a logical OR of the flags that would be
set by each sub-operation is used to set the exception flags in the MXCSR. The following subsections present one
possible way to solve these problems.
E.4.1
Floating-Point Emulation
Every operating system must provide a kernel level floating-point exception handler (a template was presented in
Section E.2, “Software Exception Handling” above). In the following discussion, assume that a user mode floatingpoint exception filter is supplied for SIMD floating-point exceptions (for example as part of a library of C functions),
that a user program can invoke in order to handle unmasked exceptions. The user mode floating-point exception
filter (not shown here) has to be able to emulate the subset of SSE/SSE2/SSE3 instructions that can generate
numeric exceptions, and has to be able to invoke a user provided floating-point exception handler for floating-point
exceptions. When a floating-point exception that is not masked is raised by an SSE/SSE2/SSE3 instruction, the
low-level floating-point exception handler will be called. This low-level handler may in turn call the user mode
floating-point exception filter. The filter function receives the original operands of the excepting instruction as no
results are provided by the hardware, whether a pre-computation or a post-computation exception has occurred.
The filter will unpack the operands into up to four sets of sub-operands, and will submit them one set at a time to
an emulation function (See Example E-2 in Section E.4.3, “Example SIMD Floating-Point Emulation Implementation”). The emulation function will examine the sub-operands, and will possibly redo the necessary calculation.
Two cases are possible:
•
If an unmasked (enabled) exception would occur in this process, the emulation function will return to its caller
(the filter function) with the appropriate information. The filter will invoke a (previously registered) user
floating-point exception handler for this set of sub-operands, and will record the result upon return from the
user handler (provided the user handler allows continuation of the execution).
•
If no unmasked (enabled) exception would occur, the emulation function will determine and will return to its
caller the result of the operation for the current set of sub-operands (it has to be IEEE Standard 754
compliant). The filter function will record the result (plus any new flag settings).
The user level filter function will then call the emulation function for the next set of sub-operands (if any). When
done with all the operand sets, the partial results will be packed (if the excepting instruction has a packed floatingpoint result, which is true for most SSE/SSE2/SSE3 numeric instructions) and the filter will return to the low-level
exception handler, which in turn will return from the interruption, allowing execution to continue. Note that the
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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
instruction pointer (EIP) has to be altered to point to the instruction following the excepting instruction, in order to
continue execution correctly.
If a user mode floating-point exception filter is not provided, then all the work for decoding the excepting instruction, reading its operands, emulating the instruction for the components of the result that do not correspond to
unmasked floating-point exceptions, and providing the compounded result will have to be performed by the userprovided floating-point exception handler.
Actual emulation might have to take place for one operand or pair of operands for scalar operations, and for all suboperands or pairs of sub-operands for packed operations. The steps to perform are the following:
•
•
The excepting instruction has to be decoded and the operands have to be read from the saved context.
•
The partial results have to be combined and written to the context that will be restored upon application
program resumption.
The instruction has to be emulated for each (pair of) sub-operand(s); if no floating-point exception occurs, the
partial result has to be saved; if a masked floating-point exception occurs, the masked result has to be
produced through emulation and saved, and the appropriate status flags have to be set; if an unmasked
floating-point exception occurs, the result has to be generated by the user provided floating-point exception
handler, and the appropriate status flags have to be set.
A diagram of the control flow in handling an unmasked floating-point exception is presented below.
User Application
Low-Level Floating-Point Exception Handler
User Level Floating-Point Exception Filter
User Floating-Point Exception Handler
Figure E-1. Control Flow for Handling Unmasked Floating-Point Exceptions
From the user-level floating-point filter, Example E-2 in Section E.4.3, “Example SIMD Floating-Point Emulation
Implementation,” will present only the floating-point emulation part. In order to understand the actions involved,
the expected response to exceptions has to be known for all SSE/SSE2/SSE3 numeric instructions in two situations: with exceptions enabled (unmasked result), and with exceptions disabled (masked result). The latter can be
found in Section 6.4, “Interrupts and Exceptions.” The response to NaN operands that do not raise an exception is
specified in Section 4.8.3.4, “NaNs.” Operations on NaNs are explained in the same source. This response is also
discussed in more detail in the next subsection, along with the unmasked and masked responses to floating-point
exceptions.
E.4.2
SSE/SSE2/SSE3 Response To Floating-Point Exceptions
This subsection specifies the unmasked response expected from the SSE/SSE2/SSE3 instructions that raise
floating-point exceptions. The masked response is given in parallel, as it is necessary in the emulation process of
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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
the instructions that raise unmasked floating-point exceptions. The response to NaN operands is also included in
more detail than in Section 4.8.3.4, “NaNs.” For floating-point exception priority, refer to “Priority Among Simultaneous Exceptions and Interrupts” in Chapter 6, “Interrupt and Exception Handling,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
E.4.2.1
Numeric Exceptions
There are six classes of numeric (floating-point) exception conditions that can occur: Invalid operation (#I),
Divide-by-Zero (#Z), Denormal Operand (#D), Numeric Overflow (#O), Numeric Underflow (#U), and Inexact
Result (precision) (#P). #I, #Z, #D are pre-computation exceptions (floating-point faults), detected before the
arithmetic operation. #O, #U, #P are post-computation exceptions (floating-point traps).
Users can control how the SSE/SSE2/SSE3 floating-point exceptions are handled by setting the mask/unmask bits
in MXCSR. Masked exceptions are handled by the processor, or by software if they are combined with unmasked
exceptions occurring in the same instruction. Unmasked exceptions are usually handled by the low-level exception
handler, in conjunction with user-level software.
E.4.2.2
Results of Operations with NaN Operands or a NaN Result for SSE/SSE2/SSE3 Numeric
Instructions
The tables below (E-1 through E-10) specify the response of SSE/SSE2/SSE3 instructions to NaN inputs, or to
other inputs that lead to NaN results.
These results will be referenced by subsequent tables (e.g., E-10). Most operations do not raise an invalid exception for quiet NaN operands, but even so, they will have higher precedence over raising floating-point exceptions
other than invalid operation.
Note that the single precision QNaN Indefinite value is FFC00000H, the double precision QNaN Indefinite value is
FFF8000000000000H, and the Integer Indefinite value is 80000000H (not a floating-point number, but it can be
the result of a conversion instruction from floating-point to integer).
For an unmasked exception, no result will be provided by the hardware to the user handler. If a user registered
floating-point exception handler is invoked, it may provide a result for the excepting instruction, that will be used
if execution of the application code is continued after returning from the interruption.
In Tables E-1 through Table E-12, the specified operands cause an invalid exception, unless the unmasked result is
marked with “not an exception”. In this latter case, the unmasked and masked results are the same.
Table E-1. ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIVSS, ADDPD, ADDSD, SUBPD, SUBSD, MULPD,
MULSD, DIVPD, DIVSD, ADDSUBPS, ADDSUBPD, HADDPS, HADDPD, HSUBPS, HSUBPD
Source Operands
Masked Result
Unmasked Result
SNaN1 op SNaN2
SNaN1 | 00400000H or
SNaN1 | 0008000000000000H2
None
SNaN1 op QNaN2
SNaN1 | 00400000H or
SNaN1 | 0008000000000000H2
None
QNaN1 op SNaN2
QNaN1
None
QNaN1 op QNaN2
QNaN1
QNaN1 (not an exception)
SNaN op real value
SNaN | 00400000H or
SNaN1 | 0008000000000000H2
None
Real value op SNaN
SNaN | 00400000H or
SNaN1 | 0008000000000000H2
None
QNaN op real value
QNaN
QNaN (not an exception)
Real value op QNaN
QNaN
QNaN (not an exception)
1
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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-1. ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIVSS, ADDPD, ADDSD, SUBPD, SUBSD, MULPD,
MULSD, DIVPD, DIVSD, ADDSUBPS, ADDSUBPD, HADDPS, HADDPD, HSUBPS, HSUBPD (Contd.)
Source Operands
Masked Result
Unmasked Result
Neither source operand is SNaN,
but #I is signaled (e.g. for Inf - Inf,
Inf ∗ 0, Inf / Inf, 0/0)
Single precision or double precision QNaN
Indefinite
None
NOTES:
1. For Tables E-1 to E-12: op denotes the operation to be performed.
2. SNaN | 00400000H is a quiet NaN in single precision format (if SNaN is in single precision) and SNaN | 0008000000000000H is a
quiet NaN in double precision format (if SNaN is in double precision), obtained from the signaling NaN given as input.
3. Operations involving only quiet NaNs do not raise floating-point exceptions.
Table E-2. CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD,
CMPPD.EQ, CMPSD.EQ, CMPPD.ORD, CMPSD.ORD
Source Operands
Masked Result
Unmasked Result
NaN op Opd2 (any Opd2)
00000000H or
0000000000000000H1
00000000H or 0000000000000000H1
(not an exception)
Opd1 op NaN (any Opd1)
00000000H or 0000000000000000H1
00000000H or 0000000000000000H1
(not an exception)
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Table E-3. CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD, CMPPD.NEQ, CMPSD.NEQ,
CMPPD.UNORD, CMPSD.UNORD
Source Operands
Masked Result
Unmasked Result
NaN op Opd2 (any Opd2)
FFFFFFFFH or
FFFFFFFFFFFFFFFFH1
FFFFFFFFH or FFFFFFFFFFFFFFFFH1 (not
an exception)
Opd1 op NaN (any Opd1)
FFFFFFFFH or FFFFFFFFFFFFFFFFH1
FFFFFFFFH or FFFFFFFFFFFFFFFFH1 (not
an exception)
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Table E-4. CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE, CMPPD.LT, CMPSD.LT, CMPPD.LE, CMPSD.LE
Source Operands
NaN op Opd2 (any Opd2)
Opd1 op NaN (any Opd1)
Masked Result
Unmasked Result
00000000H or
0000000000000000H1
None
00000000H or
0000000000000000H1
None
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-5. CMPPS.NLT, CMPSS.NLT, CMPPS.NLE, CMPSS.NLE, CMPPD.NLT, CMPSD.NLT, CMPPD.NLE, CMPSD.NLE
Source Operands
Masked Result
Unmasked Result
NaN op Opd2 (any Opd2)
1
FFFFFFFFH or FFFFFFFFFFFFFFFFH
None
Opd1 op NaN (any Opd1)
FFFFFFFFH or FFFFFFFFFFFFFFFFH1
None
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Table E-6. COMISS, COMISD
Source Operands
Masked Result
Unmasked Result
SNaN op Opd2 (any Opd2)
OF, SF, AF = 000
ZF, PF, CF = 111
None
Opd1 op SNaN (any Opd1)
OF, SF, AF = 000
ZF, PF, CF = 111
None
QNaN op Opd2 (any Opd2)
OF, SF, AF = 000
ZF, PF, CF = 111
None
Opd1 op QNaN (any Opd1)
OF, SF, AF = 000
ZF, PF, CF = 111
None
Table E-7. UCOMISS, UCOMISD
Source Operands
Masked Result
Unmasked Result
SNaN op Opd2 (any Opd2)
OF, SF, AF = 000
ZF, PF, CF = 111
None
Opd1 op SNaN (any Opd1)
OF, SF, AF = 000
ZF, PF, CF = 111
None
QNaN op Opd2
(any Opd2 ≠ SNaN)
OF, SF, AF = 000
ZF, PF, CF = 111
OF, SF, AF = 000
ZF, PF, CF = 111 (not an exception)
Opd1 op QNaN
(any Opd1 ≠ SNaN)
OF, SF, AF = 000
ZF, PF, CF = 111
OF, SF, AF = 000
ZF, PF, CF = 111 (not an exception)
Table E-8. CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI, CVTSD2SI, CVTTPD2PI, CVTTSD2SI,
CVTPS2DQ, CVTTPS2DQ, CVTPD2DQ, CVTTPD2DQ
Source Operand
Masked Result
Unmasked Result
SNaN
80000000000000001
80000000H or
(Integer Indefinite)
None
QNaN
80000000H or 80000000000000001
(Integer Indefinite)
None
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Vol. 1 E-7
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-9. MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, MINSD
Source Operands
Masked Result
Unmasked Result
Opd1 op NaN2 (any Opd1)
NaN2
None
NaN1 op Opd2 (any Opd2)
Opd2
None
NOTE:
1. SNaN and QNaN operands raise an Invalid Operation fault.
Table E-10. SQRTPS, SQRTSS, SQRTPD, SQRTSD
Source Operand
Masked Result
Unmasked Result
QNaN
QNaN
QNaN (not an exception)
SNaN
SNaN | 00400000H or
SNaN | 0008000000000000H1
None
Source operand is not SNaN;
but #I is signaled (e.g. for
sqrt (-1.0))
Single precision or
double precision QNaN Indefinite
None
NOTE:
1. SNaN | 00400000H is a quiet NaN in single precision format (if SNaN is in single precision) and SNaN | 0008000000000000H is a
quiet NaN in double precision format (if SNaN is in double precision), obtained from the signaling NaN given as input.
Table E-11. CVTPS2PD, CVTSS2SD
Source Operands
Masked Result
Unmasked Result
QNaN
QNaN11
QNaN11 (not an exception)
SNaN
QNaN12
None
NOTES:
1. The double precision output QNaN1 is created from the single precision input QNaN as follows: the sign bit is preserved, the 8-bit
exponent FFH is replaced by the 11-bit exponent 7FFH, and the 24-bit significand is extended to a 53-bit significand by appending
29 bits equal to 0.
2. The double precision output QNaN1 is created from the single precision input SNaN as follows: the sign bit is preserved, the 8-bit
exponent FFH is replaced by the 11-bit exponent 7FFH, and the 24-bit significand is extended to a 53-bit significand by pending
29 bits equal to 0. The second most significant bit of the significand is changed from 0 to 1 to convert the signaling NaN into a
quiet NaN.
Table E-12. CVTPD2PS, CVTSD2SS
Source Operands
Masked Result
Unmasked Result
QNaN
QNaN11
QNaN11 (not an exception)
SNaN
QNaN12
None
NOTES:
1. The single precision output QNaN1 is created from the double precision input QNaN as follows: the sign bit is preserved, the 11-bit
exponent 7FFH is replaced by the 8-bit exponent FFH, and the 53-bit significand is truncated to a 24-bit significand by removing its
29 least significant bits.
2. The single precision output QNaN1 is created from the double precision input SNaN as follows: the sign bit is preserved, the 11-bit
exponent 7FFH is replaced by the 8-bit exponent FFH, and the 53-bit significand is truncated to a 24-bit significand by removing its
29 least significant bits. The second most significant bit of the significand is changed from 0 to 1 to convert the signaling NaN into
a quiet NaN.
E-8 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
E.4.2.3
Condition Codes, Exception Flags, and Response for Masked and Unmasked Numeric
Exceptions
In the following, the masked response is what the processor provides when a masked exception is raised by an
SSE/SSE2/SSE3 numeric instruction. The same response is provided by the floating-point emulator for
SSE/SSE2/SSE3 numeric instructions, when certain components of the quadruple input operands generate exceptions that are masked (the emulator also generates the correct answer, as specified by IEEE Standard 754 wherever applicable, in the case when no floating-point exception occurs). The unmasked response is what the
emulator provides to the user handler for those components of the packed operands of SSE/SSE2/SSE3 instructions that raise unmasked exceptions. Note that for pre-computation exceptions (floating-point faults), no result is
provided to the user handler. For post-computation exceptions (floating-point traps), a result is provided to the
user handler, as specified below.
In the following tables, the result is denoted by 'res', with the understanding that for the actual instruction, the
destination coincides with the first source operand (except for COMISS, UCOMISS, COMISD, and UCOMISD, whose
destination is the EFLAGS register).
Table E-13. #I - Invalid Operations
Instruction
Condition
Masked Response
Unmasked Response
and Exception Code
ADDPS
ADDPD
ADDSS
ADDSD
HADDPS
HADDPD
src1 or src21 = SNaN
Refer to Table E-1 for
NaN operands, #IA = 1
src1, src2 unchanged; #IA
=1
ADDSUBPS (the
addition component)
ADDSUBPD (the
addition component)
src1 = +Inf, src2 = -Inf or
src1 = -Inf, src2 = +Inf
res1 = QNaN Indefinite,
#IA = 1
SUBPS
SUBPD
SUBSS
SUBSD
HSUBPS
HSUBPD
src1 or src2 = SNaN
Refer to Table E-1 for NaN
operands, #IA = 1
ADDSUBPS (the
subtraction
component)
ADDSUBPD (the
subtraction
component)
src1 = +Inf, src2 = +Inf or
src1 = -Inf, src2 = -Inf
res = QNaN Indefinite,
#IA = 1
MULPS
MULPD
src1 or src2 = SNaN
Refer to Table E-1 for
NaN operands, #IA = 1
MULSS
MULSD
src1 = ±Inf, src2 = ±0 or
src1 = ±0, src2 = ±Inf
res = QNaN Indefinite,
#IA = 1
DIVPS
DIVPD
src1 or src2 = SNaN
Refer to Table E-1 for
NaN operands, #IA = 1
DIVSS
DIVSD
src1 = ±Inf, src2 = ±Inf or
src1 = ±0, src2 = ±0
res = QNaN Indefinite,
#IA = 1
SQRTPS
SQRTPD
SQRTSS
SQRTSD
src = SNaN
Refer to Table E-10 for
NaN operands, #IA = 1
src < 0
(note that -0 < 0 is false)
res = QNaN Indefinite,
#IA = 1
src1, src2 unchanged; #IA
=1
src1, src2 unchanged;
#IA = 1
src1, src2 unchanged;
#IA = 1
src unchanged,
#IA = 1
Vol. 1 E-9
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-13. #I - Invalid Operations (Contd.)
Unmasked Response
and Exception Code
Instruction
Condition
Masked Response
MAXPS
MAXSS
MAXPD
MAXSD
src1 = NaN or src2 = NaN
res = src2, #IA = 1
src1, src2 unchanged; #IA
=1
MINPS
MINSS
MINPD
MINSD
src1 = NaN or src2 = NaN
res = src2, #IA = 1
src1, src2 unchanged; #IA
=1
CMPPS.LT
CMPPS.LE
CMPPS.NLT
CMPPS.NLE
CMPSS.LT
CMPSS.LE
CMPSS.NLT
CMPSS.NLE
CMPPD.LT
CMPPD.LE
CMPPD.NLT
CMPPD.NLE
CMPSD.LT
CMPSD.LE
CMPSD.NLT
CMPSD.NLE
src1 = NaN or src2 = NaN
Refer to Table E-4 and Table E-5 for
NaN operands; #IA = 1
src1, src2 unchanged; #IA
=1
COMISS
COMISD
src1 = NaN or src2 = NaN
Refer to Table E-6 for NaN operands src1, src2, EFLAGS
unchanged; #IA = 1
UCOMISS
UCOMISD
src1 = SNaN or src2 = SNaN
Refer to Table E-7 for NaN operands src1, src2, EFLAGS
unchanged; #IA = 1
CVTPS2PI
CVTSS2SI
CVTPD2PI
CVTSD2SI
CVTPS2DQ
CVTPD2DQ
src = NaN, ±Inf, or
|(src)rnd | > 7FFFFFFFH and (src)rnd ≠
80000000H
res = Integer Indefinite,
#IA = 1
src unchanged,
#IA = 1
CVTTPS2PI
CVTTSS2SI
CVTTPD2PI
CVTTSD2SI
CVTTPS2DQ
CVTTPD2DQ
src = NaN, ±Inf, or
|(src)rz | > 7FFFFFFFH and (src)rz ≠
80000000H
res = Integer Indefinite,
#IA = 1
src unchanged,
#IA = 1
E-10 Vol. 1
See Note2 for information
on rnd.
See Note2 for information
on rz.
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-13. #I - Invalid Operations (Contd.)
Instruction
Condition
Masked Response
Unmasked Response
and Exception Code
CVTPS2PD
CVTSS2SD
src = NAN
Refer to Table E-11 for
NaN operands
src unchanged,
#IA = 1
CVTPD2PS
CVTSD2SS
src = NAN
Refer to Table E-12 for
NaN operands
src unchanged,
#IA = 1
NOTES:
1. For Tables E-13 to E-18:
- src denotes the single source operand of a unary operation.
- src1, src2 denote the first and second source operand of a binary operation.
- res denotes the numerical result of an operation.
2. rnd signifies the user rounding mode from MXCSR, and rz signifies the rounding mode toward zero. (truncate), when rounding a
floating-point value to an integer. For more information, refer to Table 4-8.
3. For NAN encodings, see Table 4-3.
Table E-14. #Z - Divide-by-Zero
Instruction
Condition
Masked Response
Unmasked Response
and Exception Code
DIVPS
DIVSS
DIVPD
DIVPS
src1 = finite non-zero (normal, or
denormal)
src2 = ±0
res = ±Inf,
#ZE = 1
src1, src2 unchanged;
#ZE = 1
Vol. 1 E-11
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-15. #D - Denormal Operand
Unmasked Response and
Exception Code
Instruction
Condition
Masked Response
ADDPS
ADDPD
ADDSUBPS
ADDSUBPD
HADDPS
HADDPD
SUBPS
SUBPD
HSUBPS
HSUBPD
MULPS
MULPD
DIVPS
DIVPD
SQRTPS
SQRTPD
MAXPS
MAXPD
MINPS
MINPD
ADDSS
ADDSD
SUBSS
SUBSD
MULSS
MULSD
DIVSS
DIVSD
SQRTSS
SQRTSD
MAXSS
MAXSD
MINSS
MINSD
CVTPS2PD
CVTSS2SD
CVTPD2PS
CVTSD2SS
src1 = denormal1 or
src2 = denormal (and
the DAZ bit in MXCSR
is 0)
res = Result rounded to the
destination precision and using the
bounded exponent, but only if no
unmasked post-computation
exception occurs;
#DE = 1.
src1, src2 unchanged;
#DE = 1
CMPPS
CMPPD
CMPSS
CMPSD
src1 = denormal1 or
src2 = denormal (and
the DAZ bit in MXCSR
is 0)
Comparison result, stored in the
destination register;
#DE = 1
src1, src2 unchanged;
#DE = 1
COMISS
COMISD
UCOMISS
UCOMISD
src1 = denormal1 or
src2 = denormal (and
the DAZ bit in MXCSR
is 0)
Comparison result, stored in the
EFLAGS register;
#DE = 1
src1, src2 unchanged;
#DE = 1
NOTE:
1. For denormal encodings, see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers.”
E-12 Vol. 1
Note that SQRT, CVTPS2PD,
CVTSS2SD, CVTPD2PS, CVTSD2SS
have only 1 src.
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-16. #O - Numeric Overflow
Instruction
Condition
ADDPS
ADDSUBPS
HADDPS
SUBPS
HSUBPS
MULPS
DIVPS
ADDSS
SUBSS
MULSS
DIVSS
CVTPD2PS
CVTSD2SS
Rounded result >
largest single
precision finite
normal value
ADDPD
ADDSUBPD
HADDPD
SUBPD
HSUBPD
MULPD
DIVPD
ADDSD
SUBSD
MULSD
DIVSD
Rounded result >
largest double
precision finite
normal value
Unmasked Response and
Exception Code
Masked Response
Rounding
To
nearest
Toward – ∞
Toward + ∞
Toward
0
Rounding
To
nearest
Toward – ∞
Toward + ∞
Toward
0
Sign
Result & Status Flags
+
-
#OE = 1, #PE = 1
res = + ∞
res = – ∞
+
-
#OE = 1, #PE = 1
res = 1.11…1 * 2127
res = – ∞
+
-
#OE = 1, #PE = 1
res = + ∞
res = -1.11…1 * 2127
+
-
#OE = 1, #PE = 1
res = 1.11…1 * 2127
res = -1.11…1 * 2127
Sign
Result & Status Flags
+
-
#OE = 1, #PE = 1
res = + ∞
res = – ∞
+
-
#OE = 1, #PE = 1
res = 1.11…1 * 21023
res = – ∞
+
-
#OE = 1, #PE = 1
res = + ∞
res = -1.11…1 * 21023
+
-
#OE = 1, #PE = 1
res = 1.11…1 * 21023
res = -1.11…1 * 21023
res = (result calculated with
unbounded exponent and rounded
to the destination precision) / 2192
#OE = 1
#PE = 1 if the result is inexact
res = (result calculated with
unbounded exponent and rounded
to the destination precision) / 21536
• #OE = 1
• #PE = 1 if the result is inexact
Vol. 1 E-13
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-17. #U - Numeric Underflow
Instruction
Condition
Masked Response
ADDPS
ADDSUBPS
HADDPS
SUBPS
HSUBPS
MULPS
DIVPS
ADDSS
SUBSS
MULSS
DIVSS
CVTPD2PS
CVTSD2SS
Result calculated with unbounded
exponent and rounded to the
destination precision < smallest
single precision finite normal value.
res = ±0, denormal, or normal
ADDPD
ADDSUBPD
HADDPD
SUBPD
HSUBPD
MULPD
DIVPD
ADDSD
SUBSD
MULSD
DIVSD
Result calculated with unbounded
exponent and rounded to the
destination precision < smallest
double precision finite normal value.
res = ±0, denormal or normal
E-14 Vol. 1
#UE = 1 and #PE = 1,
but only if the result is
inexact
#UE = 1 and #PE = 1,
but only if the result is
inexact
Unmasked Response and
Exception Code
res = (result calculated with
unbounded exponent and rounded
to the destination precision) * 2192
• #UE = 1
• #PE = 1 if the result is inexact
res = (result calculated with
unbounded exponent and rounded
to the destination precision) * 21536
• #UE = 1
• #PE = 1 if the result is inexact
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-18. #P - Inexact Result (Precision)
Instruction
Condition
Masked Response
Unmasked Response and Exception Code
ADDPS
ADDPD
ADDSUBPS
ADDSUBPD
HADDPS
HADDPD
SUBPS
SUBPD
HSUBPS
HSUBPD
MULPS
MULPD
DIVPS
DIVPD
SQRTPS
SQRTPD
CVTDQ2PS
CVTPI2PS
CVTPS2PI
CVTPS2DQ
CVTPD2PI
CVTPD2DQ
CVTPD2PS
CVTTPS2PI
CVTTPD2PI
CVTTPD2DQ
CVTTPS2DQ
ADDSS
ADDSD
SUBSS
SUBSD
MULSS
MULSD
DIVSS
DIVSD
SQRTSS
SQRTSD
CVTSI2SS
CVTSS2SI
CVTSD2SI
CVTSD2SS
CVTTSS2SI
CVTTSD2SI
The result is not exactly
representable in the
destination format.
res = Result rounded to the
destination precision and
using the bounded
exponent, but only if no
unmasked underflow or
overflow conditions occur
(this exception can occur in
the presence of a masked
underflow or overflow); #PE
= 1.
Only if no underflow/overflow condition occurred, or
if the corresponding exceptions are masked:
• Set #OE if masked overflow and set result as
described above for masked overflow.
• Set #UE if masked underflow and set result as
described above for masked underflow.
If neither underflow nor overflow, res equals the
result rounded to the destination precision and using
the bounded exponent set #PE = 1.
E.4.3
Example SIMD Floating-Point Emulation Implementation
The sample code listed below may be considered as being part of a user-level floating-point exception filter for the
SSE/SSE2/SSE3 numeric instructions. It is assumed that the filter function is invoked by a low-level exception
handler (invoked for exception 19 when an unmasked floating-point exception occurs), and that it operates as
explained in Section E.4.1, “Floating-Point Emulation.” The sample code does the emulation only for the SSE
instructions for addition, subtraction, multiplication, and division. For this, it uses C code and x87 FPU operations.
Operations corresponding to other SSE/SSE2/SSE3 numeric instructions can be emulated similarly. The example
assumes that the emulation function receives a pointer to a data structure specifying a number of input parameters: the operation that caused the exception, a set of sub-operands (unpacked, of type float), the rounding mode
Vol. 1 E-15
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
(the precision is always single), exception masks (having the same relative bit positions as in the MXCSR but
starting from bit 0 in an unsigned integer), and flush-to-zero and denormals-are-zeros indicators.
The output parameters are a floating-point result (of type float), the cause of the exception (identified by constants
not explicitly defined below), and the exception status flags. The corresponding C definition is:
typedef struct {
unsigned int operation;
//SSE or SSE2 operation: ADDPS, ADDSS, ...
unsigned int operand1_uint32; //first operand value
unsigned int operand2_uint32; //second operand value (if any)
float result_fval; // result value (if any)
unsigned int rounding_mode; //rounding mode
unsigned int exc_masks; //exception masks, in the order P,U,O,Z,D,I
unsigned int exception_cause; //exception cause
unsigned int status_flag_inexact; //inexact status flag
unsigned int status_flag_underflow; //underflow status flag
unsigned int status_flag_overflow; //overflow status flag
unsigned int status_flag_divide_by_zero;
//divide by zero status flag
unsigned int status_flag_denormal_operand;
//denormal operand status flag
unsigned int status_flag_invalid_operation;
//invalid operation status flag
unsigned int ftz; // flush-to-zero flag
unsigned int daz; // denormals-are-zeros flag
} EXC_ENV;
The arithmetic operations exemplified are emulated as follows:
1. If the denormals-are-zeros mode is enabled (the DAZ bit in MXCSR is set to 1), replace all the denormal inputs
with zeroes of the same sign (the denormal flag is not affected by this change).
2. Perform the operation using x87 FPU instructions, with exceptions disabled, the original user rounding mode,
and single precision. This reveals invalid, denormal, or divide-by-zero exceptions (if there are any) and stores
the result in memory as a double precision value (whose exponent range is large enough to look like
“unbounded” to the result of the single precision computation).
3. If no unmasked exceptions were detected, determine if the magnitude of the result is less than the smallest
normal number that can be represented in single precision format, or greater than the largest normal number
that can be represented in single precision format (huge). If an unmasked overflow or underflow occurs,
calculate the scaled result that will be handed to the user exception handler, as specified by IEEE Standard 754.
4. If no exception was raised, calculate the result with a “bounded” exponent. If the result is tiny, it requires
denormalization (shifting the significand right while incrementing the exponent to bring it into the admissible
range of [-126,+127] for single precision floating-point numbers).
The result obtained in step 2 cannot be used because it might incur a double rounding error (it was rounded to
24 bits in step 2, and might have to be rounded again in the denormalization process). To overcome this is,
calculate the result as a double precision value, and store it to memory in single precision format.
Rounding first to 53 bits in the significand, and then to 24 never causes a double rounding error (exact
properties exist that state when double-rounding error occurs, but for the elementary arithmetic operations,
the rule of thumb is that if an infinitely precise result is rounded to 2p+1 bits and then again to p bits, the result
is the same as when rounding directly to p bits, which means that no double-rounding error occurs).
5. If the result is inexact and the inexact exceptions are unmasked, the calculated result will be delivered to the
user floating-point exception handler.
6. The flush-to-zero case is dealt with if the result is tiny.
E-16 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
7. The emulation function returns RAISE_EXCEPTION to the filter function if an exception has to be raised (the
exception_cause field indicates the cause). Otherwise, the emulation function returns DO_NOT_
RAISE_EXCEPTION. In the first case, the result is provided by the user exception handler called by the filter
function. In the second case, it is provided by the emulation function. The filter function has to collect all the
partial results, and to assemble the scalar or packed result that is used if execution is to continue.
Example E-2. SIMD Floating-Point Emulation
// masks for individual status word bits
#define PRECISION_MASK 20H
#define UNDERFLOW_MASK 10H
#define OVERFLOW_MASK 08H
#define ZERODIVIDE_MASK 04H
#define DENORMAL_MASK 02H
#define INVALID_MASK 01H
// 32-bit constants
static unsigned ZEROF_ARRAY[] = {00000000H};
#define ZEROF *(float *) ZEROF_ARRAY
// +0.0
static unsigned NZEROF_ARRAY[] = {80000000H};
#define NZEROF *(float *) NZEROF_ARRAY
// -0.0
static unsigned POSINFF_ARRAY[] = {7f800000H};
#define POSINFF *(float *)POSINFF_ARRAY
// +Inf
static unsigned NEGINFF_ARRAY[] = {ff800000H};
#define NEGINFF *(float *)NEGINFF_ARRAY
// -Inf
// 64-bit constants
static unsigned MIN_SINGLE_NORMAL_ARRAY [] = {00000000H, 38100000H};
#define MIN_SINGLE_NORMAL *(double *)MIN_SINGLE_NORMAL_ARRAY
// +1.0 * 2^-126
static unsigned MAX_SINGLE_NORMAL_ARRAY [] = {70000000H, 47efffffH};
#define MAX_SINGLE_NORMAL *(double *)MAX_SINGLE_NORMAL_ARRAY
// +1.1...1*2^127
static unsigned TWO_TO_192_ARRAY[] = {00000000H, 4bf00000H};
#define TWO_TO_192 *(double *)TWO_TO_192_ARRAY
// +1.0 * 2^192
static unsigned TWO_TO_M192_ARRAY[] = {00000000H, 33f00000H};
#define TWO_TO_M192 *(double *)TWO_TO_M192_ARRAY
// +1.0 * 2^-192
// auxiliary functions
static int isnanf (unsigned int ); // returns 1 if f is a NaN, and 0 otherwise
static float quietf (unsigned int ); // converts a signaling NaN to a quiet
// NaN, and leaves a quiet NaN unchanged
static unsigned int check_for_daz (unsigned int ); // converts denormals
// to zeros of the same sign;
// does not affect any status flags
// emulation of SSE and SSE2 instructions using
// C code and x87 FPU instructions
unsigned int
simd_fp_emulate (EXC_ENV *exc_env)
{
int uiopd1; // first operand of the add, subtract, multiply, or divide
int uiopd2; // second operand of the add, subtract, multiply, or divide
float res; // result of the add, subtract, multiply, or divide
double dbl_res24; // result with 24-bit significand, but "unbounded" exponent
Vol. 1 E-17
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
// (needed to check tininess, to provide a scaled result to
// an underflow/overflow trap handler, and in flush-to-zero mode)
double dbl_res; // result in double precision format (needed to avoid a
// double rounding error when denormalizing)
unsigned int result_tiny;
unsigned int result_huge;
unsigned short int sw; // 16 bits
unsigned short int cw; // 16 bits
// have to check first for faults (V, D, Z), and then for traps (O, U, I)
// initialize x87 FPU (floating-point exceptions are masked)
_asm {
fninit;
}
result_tiny = 0;
result_huge = 0;
switch (exc_env->operation) {
case
case
case
case
case
case
case
case
ADDPS:
ADDSS:
SUBPS:
SUBSS:
MULPS:
MULSS:
DIVPS:
DIVSS:
uiopd1 = exc_env->operand1_uint32; // copy as unsigned int
// do not copy as float to avoid conversion
// of SNaN to QNaN by compiled code
uiopd2 = exc_env->operand2_uint32;
// do not copy as float to avoid conversion of SNaN
// to QNaN by compiled code
uiopd1 = check_for_daz (uiopd1); // operand1 = +0.0 * operand1 if it is
// denormal and DAZ=1
uiopd2 = check_for_daz (uiopd2); // operand2 = +0.0 * operand2 if it is
// denormal and DAZ=1
// execute the operation and check whether the invalid, denormal, or
// divide by zero flags are set and the respective exceptions enabled
// set control word with rounding mode set to exc_env->rounding_mode,
// single precision, and all exceptions disabled
switch (exc_env->rounding_mode) {
case ROUND_TO_NEAREST:
cw = 003fH; // round to nearest, single precision, exceptions masked
break;
case ROUND_DOWN:
cw = 043fH; // round down, single precision, exceptions masked
break;
case ROUND_UP:
cw = 083fH; // round up, single precision, exceptions masked
break;
case ROUND_TO_ZERO:
cw = 0c3fH; // round to zero, single precision, exceptions masked
break;
default:
;
}
__asm {
fldcw WORD PTR cw;
E-18 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
}
// compute result and round to the destination precision, with
// "unbounded" exponent (first IEEE rounding)
switch (exc_env->operation) {
case ADDPS:
case ADDSS:
// perform the addition
__asm {
fnclex;
// load input operands
fld DWORD PTR uiopd1; // may set denormal or invalid status flags
fld DWORD PTR uiopd2; // may set denormal or invalid status flags
faddp st(1), st(0); // may set inexact or invalid status flags
// store result
fstp QWORD PTR dbl_res24; // exact
}
break;
case SUBPS:
case SUBSS:
// perform the subtraction
__asm {
fnclex;
// load input operands
fld DWORD PTR uiopd1; // may set denormal or invalid status flags
fld DWORD PTR uiopd2; // may set denormal or invalid status flags
fsubp st(1), st(0); // may set the inexact or invalid status flags
// store result
fstp QWORD PTR dbl_res24; // exact
}
break;
case MULPS:
case MULSS:
// perform the multiplication
__asm {
fnclex;
// load input operands
fld DWORD PTR uiopd1; // may set denormal or invalid status flags
fld DWORD PTR uiopd2; // may set denormal or invalid status flags
fmulp st(1), st(0); // may set inexact or invalid status flags
// store result
fstp QWORD PTR dbl_res24; // exact
}
break;
case DIVPS:
case DIVSS:
// perform the division
__asm {
fnclex;
// load input operands
fld DWORD PTR uiopd1; // may set denormal or invalid status flags
fld DWORD PTR uiopd2; // may set denormal or invalid status flags
fdivp st(1), st(0); // may set the inexact, divide by zero, or
// invalid status flags
// store result
fstp QWORD PTR dbl_res24; // exact
}
break;
Vol. 1 E-19
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
default:
; // will never occur
}
// read status word
__asm {
fstsw WORD PTR sw;
}
if (sw & ZERODIVIDE_MASK)
sw = sw & ~DENORMAL_MASK; // clear D flag for (denormal / 0)
// if invalid flag is set, and invalid exceptions are enabled, take trap
if (!(exc_env->exc_masks & INVALID_MASK) && (sw & INVALID_MASK)) {
exc_env->status_flag_invalid_operation = 1;
exc_env->exception_cause = INVALID_OPERATION;
return (RAISE_EXCEPTION);
}
//
//
//
//
if
checking for NaN operands has priority over denormal exceptions;
also fix for the SSE and SSE2
differences in treating two NaN inputs between the
instructions and other IA-32 instructions
(isnanf (uiopd1) || isnanf (uiopd2)) {
if (isnanf (uiopd1) && isnanf (uiopd2))
exc_env->result_fval = quietf (uiopd1);
else
exc_env->result_fval = (float)dbl_res24; // exact
if (sw & INVALID_MASK) exc_env->status_flag_invalid_operation = 1;
return (DO_NOT_RAISE_EXCEPTION);
}
// if denormal flag set, and denormal exceptions are enabled, take trap
if (!(exc_env->exc_masks & DENORMAL_MASK) && (sw & DENORMAL_MASK)) {
exc_env->status_flag_denormal_operand = 1;
exc_env->exception_cause = DENORMAL_OPERAND;
return (RAISE_EXCEPTION);
}
// if divide by zero flag set, and divide by zero exceptions are
// enabled, take trap (for divide only)
if (!(exc_env->exc_masks & ZERODIVIDE_MASK) && (sw & ZERODIVIDE_MASK)) {
exc_env->status_flag_divide_by_zero = 1;
exc_env->exception_cause = DIVIDE_BY_ZERO;
return (RAISE_EXCEPTION);
}
// done if the result is a NaN (QNaN Indefinite)
res = (float)dbl_res24;
if (isnanf (*(unsigned int *)&res)) {
exc_env->result_fval = res; // exact
exc_env->status_flag_invalid_operation = 1;
return (DO_NOT_RAISE_EXCEPTION);
}
// dbl_res24 is not a NaN at this point
if (sw & DENORMAL_MASK) exc_env->status_flag_denormal_operand = 1;
// Note: (dbl_res24 == 0.0 && sw & PRECISION_MASK) cannot occur
if (-MIN_SINGLE_NORMAL < dbl_res24 && dbl_res24 < 0.0 ||
0.0 < dbl_res24 && dbl_res24 < MIN_SINGLE_NORMAL) {
E-20 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
result_tiny = 1;
}
// check if the result is huge
if (NEGINFF < dbl_res24 && dbl_res24 < -MAX_SINGLE_NORMAL ||
MAX_SINGLE_NORMAL < dbl_res24 && dbl_res24 < POSINFF) {
result_huge = 1;
}
//
//
//
//
//
//
//
//
//
//
//
//
at this point, there are no enabled I,D, or Z exceptions
to take; the instr.
might lead to an enabled underflow, enabled underflow and inexact,
enabled overflow, enabled overflow and inexact, enabled inexact, or
none of these; if there are no U or O enabled exceptions, re-execute
the instruction using IA-32 double precision format, and the
user's rounding mode; exceptions must have
been disabled before calling
this function; an inexact exception may be reported on the 53-bit
fsubp, fmulp, or on both the 53-bit and 24-bit conversions, while an
overflow or underflow (with traps disabled) may be reported on the
conversion from dbl_res to res
//
//
//
//
check whether there is an underflow, overflow,
or inexact trap to be taken
if the underflow traps are enabled and the result is
tiny, take underflow trap
if (!(exc_env->exc_masks & UNDERFLOW_MASK) && result_tiny) {
dbl_res24 = TWO_TO_192 * dbl_res24; // exact
exc_env->status_flag_underflow = 1;
exc_env->exception_cause = UNDERFLOW;
exc_env->result_fval = (float)dbl_res24; // exact
if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
return (RAISE_EXCEPTION);
}
// if overflow traps are enabled and the result is huge, take
// overflow trap
if (!(exc_env->exc_masks & OVERFLOW_MASK) && result_huge) {
dbl_res24 = TWO_TO_M192 * dbl_res24; // exact
exc_env->status_flag_overflow = 1;
exc_env->exception_cause = OVERFLOW;
exc_env->result_fval = (float)dbl_res24; // exact
if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
return (RAISE_EXCEPTION);
}
// set control word with rounding mode set to exc_env->rounding_mode,
// double precision, and all exceptions disabled
cw = cw | 0200H; // set precision to double
__asm {
fldcw WORD PTR cw;
}
switch (exc_env->operation) {
case ADDPS:
case ADDSS:
// perform the addition
__asm {
// load input operands
fld DWORD PTR uiopd1; // may set the denormal status flag
fld DWORD PTR uiopd2; // may set the denormal status flag
faddp st(1), st(0); // rounded to 53 bits, may set the inexact
// status flag
Vol. 1 E-21
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
// store result
fstp QWORD PTR dbl_res; // exact, will not set any flag
}
break;
case SUBPS:
case SUBSS:
// perform the subtraction
__asm {
// load input operands
fld DWORD PTR uiopd1; //
fld DWORD PTR uiopd2; //
fsubp st(1), st(0);
//
//
// store result
fstp QWORD PTR dbl_res;
}
break;
may set the denormal status flag
may set the denormal status flag
rounded to 53 bits, may set the inexact
status flag
// exact, will not set any flag
case MULPS:
case MULSS:
// perform the multiplication
__asm {
// load input operands
fld DWORD PTR uiopd1; // may set the denormal status flag
fld DWORD PTR uiopd2; // may set the denormal status flag
fmulp st(1), st(0);
// rounded to 53 bits, exact
// store result
fstp QWORD PTR dbl_res; // exact, will not set any flag
}
break;
case DIVPS:
case DIVSS:
// perform the division
__asm {
// load input operands
fld DWORD PTR uiopd1; // may set the denormal status flag
fld DWORD PTR uiopd2; // may set the denormal status flag
fdivp st(1), st(0);
// rounded to 53 bits, may set the inexact
// status flag
// store result
fstp QWORD PTR dbl_res; // exact, will not set any flag
}
break;
default:
; // will never occur
}
// calculate result for the case an inexact trap has to be taken, or
// when no trap occurs (second IEEE rounding)
res = (float)dbl_res;
// may set P, U or O; may also involve denormalizing the result
// read status word
__asm {
fstsw WORD PTR sw;
}
// if inexact traps are enabled and result is inexact, take inexact trap
if (!(exc_env->exc_masks & PRECISION_MASK) &&
((sw & PRECISION_MASK) || (exc_env->ftz && result_tiny))) {
exc_env->status_flag_inexact = 1;
E-22 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
exc_env->exception_cause = INEXACT;
if (result_tiny) {
exc_env->status_flag_underflow = 1;
//
//
//
//
if
if ftz = 1 and result is tiny, result = 0.0
(no need to check for underflow traps disabled: result tiny and
underflow traps enabled would have caused taking an underflow
trap above)
(exc_env->ftz) {
if (res > 0.0)
res = ZEROF;
else if (res < 0.0)
res = NZEROF;
// else leave res unchanged
}
}
if (result_huge) exc_env->status_flag_overflow = 1;
exc_env->result_fval = res;
return (RAISE_EXCEPTION);
}
//
//
//
//
//
//
//
//
//
//
//
//
if it got here, then there is no trap to be taken; the following must
hold: ((the MXCSR U exceptions are disabled or
the MXCSR underflow exceptions are enabled and the underflow flag is
clear and (the inexact flag is set or the inexact flag is clear and
the 24-bit result with unbounded exponent is not tiny)))
and (the MXCSR overflow traps are disabled or the overflow flag is
clear) and (the MXCSR inexact traps are disabled or the inexact flag
is clear)
in this case, the result has to be delivered (the status flags are
sticky, so they are all set correctly already)
// read status word to see if result is inexact
__asm {
fstsw WORD PTR sw;
}
if (sw & UNDERFLOW_MASK) exc_env->status_flag_underflow = 1;
if (sw & OVERFLOW_MASK) exc_env->status_flag_overflow = 1;
if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
// if ftz = 1, and result is tiny (underflow traps must be disabled),
// result = 0.0
if (exc_env->ftz && result_tiny) {
if (res > 0.0)
res = ZEROF;
else if (res < 0.0)
res = NZEROF;
// else leave res unchanged
exc_env->status_flag_inexact = 1;
exc_env->status_flag_underflow = 1;
}
exc_env->result_fval = res;
if (sw & ZERODIVIDE_MASK) exc_env->status_flag_divide_by_zero = 1;
if (sw & DENORMAL_MASK) exc_env->status_flag_denormal= 1;
if (sw & INVALID_MASK) exc_env->status_flag_invalid_operation = 1;
return (DO_NOT_RAISE_EXCEPTION);
break;
case CMPPS:
Vol. 1 E-23
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
case CMPSS:
...
break;
case COMISS:
case UCOMISS:
...
break;
case CVTPI2PS:
case CVTSI2SS:
...
break;
case
case
case
case
CVTPS2PI:
CVTSS2SI:
CVTTPS2PI:
CVTTSS2SI:
...
break;
case
case
case
case
MAXPS:
MAXSS:
MINPS:
MINSS:
...
break;
case SQRTPS:
case SQRTSS:
...
break;
...
case UNSPEC:
...
break;
default:
...
}
}
E-24 Vol. 1
Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 2 (2A, 2B, 2C & 2D):
Instruction Set Reference, A-Z
NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of three volumes:
Basic Architecture, Order Number 253665; Instruction Set Reference A-Z, Order Number 325383;
System Programming Guide, Order Number 325384. Refer to all three volumes when evaluating your
design needs.
Order Number: 325383-060US
September 2016
Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn
more at intel.com, or from the OEM or retailer.
No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting
from such losses.
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products
described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject
matter disclosed herein.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
This document contains information on products, services and/or processes in development. All information provided here is subject to change
without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1800-548-4725, or by visiting http://www.intel.com/design/literature.htm.
Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S.
and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 1997-2016, Intel Corporation. All Rights Reserved.
CONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
OVERVIEW OF VOLUME 2A, 2B, 2C AND 2D: INSTRUCTION SET REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3
NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.1
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.3.2
Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.3
Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.4
Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.5
Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.6
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.7
A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.4
RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
CHAPTER 2
INSTRUCTION FORMAT
2.1
INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
Instruction Prefixes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.2
Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.3
ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.4
Displacement and Immediate Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.5
Addressing-Mode Encoding of ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.2
IA-32E MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1
REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.1.1
Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.1.2
More on REX Prefix Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.1.3
Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.4
Direct Memory-Offset MOVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.5
Immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.6
RIP-Relative Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.1.7
Default 64-Bit Operand Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.2
Additional Encodings for Control and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3
INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.1
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.2
VEX and the LOCK prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.3
VEX and the 66H, F2H, and F3H prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.4
VEX and the REX prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.5
The VEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.5.1
VEX Byte 0, bits[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.5.2
VEX Byte 1, bit [7] - ‘R’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.5.3
3-byte VEX byte 1, bit[6] - ‘X’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.4
3-byte VEX byte 1, bit[5] - ‘B’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.5
3-byte VEX byte 2, bit[7] - ‘W’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.6
2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or Dest Register Specifier. . . . . 2-16
2.3.6
Instruction Operand Encoding and VEX.vvvv, ModR/M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.6.1
3-byte VEX byte 1, bits[4:0] - “m-mmmm”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.6.2
2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.6.3
2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.7
The Opcode Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.8
The MODRM, SIB, and Displacement Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.9
The Third Source Operand (Immediate Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.10
AVX Instructions and the Upper 128-bits of YMM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.10.1
Vector Length Transition and Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Vol. 2A iii
CONTENTS
PAGE
2.3.11
2.3.12
2.3.12.1
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
2.4.10
2.5
2.5.1
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
2.6.9
2.6.10
2.6.11
2.6.11.1
2.6.11.2
2.6.11.3
2.6.12
2.6.13
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.7.10
2.7.11
2.8
AVX Instruction Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Vector SIB (VSIB) Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
64-bit Mode VSIB Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
AVX AND SSE INSTRUCTION EXCEPTION SPECIFICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Exceptions Type 1 (Aligned memory reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Exceptions Type 3 (<16 Byte memory argument) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Exceptions Type 4 (>=16 Byte mem arg no alignment, no floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Exceptions Type 5 (<16 Byte mem arg and no FP exceptions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Exceptions Type 7 (No FP exceptions, no memory arg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Exceptions Type 8 (AVX and no memory argument) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Exception Type 11 (VEX-only, mem arg no AC, floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Exception Type 12 (VEX-only, VSIB mem arg, no AC, no floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
VEX ENCODING SUPPORT FOR GPR INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Exception Conditions for VEX-Encoded GPR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
INTEL® AVX-512 ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Instruction Format and EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Register Specifier Encoding and EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Opmask Register Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Masking Support in EVEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Compressed Displacement (disp8*N) Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
EVEX Encoding of Broadcast/Rounding/SAE Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Embedded Broadcast Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Static Rounding Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
SAE Support in EVEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Vector Length Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
#UD Equations for EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
State Dependent #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Opcode Independent #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Opcode Dependent #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Device Not Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
Scalar Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
EXCEPTION CLASSIFICATIONS OF EVEX-ENCODED INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
Exceptions Type E1 and E1NF of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
Exceptions Type E2 of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Exceptions Type E3 and E3NF of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Exceptions Type E4 and E4NF of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Exceptions Type E5 and E5NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
Exceptions Type E6 and E6NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Exceptions Type E7NM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Exceptions Type E9 and E9NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Exceptions Type E10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
Exception Type E11 (EVEX-only, mem arg no AC, floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Exception Type E12 and E12NP (VSIB mem arg, no AC, no floating-point exceptions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
EXCEPTION CLASSIFICATIONS OF OPMASK INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
CHAPTER 3
INSTRUCTION SET REFERENCE, A-L
3.1
INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1.1.1
Opcode Column in the Instruction Summary Table (Instructions without VEX Prefix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.1.1.2
Opcode Column in the Instruction Summary Table (Instructions with VEX prefix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.1.1.3
Instruction Column in the Opcode Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.1.1.4
Operand Encoding Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.1.1.5
64/32-bit Mode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.1.1.6
CPUID Support Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.1.1.7
Description Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.1.1.8
Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
iv Vol. 2A
CONTENTS
PAGE
3.1.1.9
Operation Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.1.10
Intel® C/C++ Compiler Intrinsics Equivalents Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
3.1.1.11
Flags Affected Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.1.1.12
FPU Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.1.1.13
Protected Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.1.1.14
Real-Address Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
3.1.1.15
Virtual-8086 Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
3.1.1.16
Floating-Point Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.1.1.17
SIMD Floating-Point Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.1.1.18
Compatibility Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.1.1.19
64-Bit Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.2
INSTRUCTIONS (A-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
AAA—ASCII Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
AAD—ASCII Adjust AX Before Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
AAM—ASCII Adjust AX After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
AAS—ASCII Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
ADC—Add with Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
ADD—Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
ADDPD—Add Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
ADDPS—Add Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
ADDSD—Add Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
ADDSS—Add Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
ADDSUBPS—Packed Single-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
AESDEC—Perform One Round of an AES Decryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
AESDECLAST—Perform Last Round of an AES Decryption Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
AESENC—Perform One Round of an AES Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
AESENCLAST—Perform Last Round of an AES Encryption Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
AESIMC—Perform the AES InvMixColumn Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
AESKEYGENASSIST—AES Round Key Generation Assist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
ANDN — Logical AND NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
ARPL—Adjust RPL Field of Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
BLENDPD — Blend Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
BEXTR — Bit Field Extract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
BLENDPS — Blend Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
BLSI — Extract Lowest Set Isolated Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88
BLSMSK — Get Mask Up to Lowest Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
BLSR — Reset Lowest Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
BNDCL—Check Lower Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
BNDCU/BNDCN—Check Upper Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93
BNDLDX—Load Extended Bounds Using Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95
BNDMK—Make Bounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98
BNDMOV—Move Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100
BNDSTX—Store Extended Bounds Using Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
BOUND—Check Array Index Against Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106
BSF—Bit Scan Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108
BSR—Bit Scan Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
BSWAP—Byte Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112
BT—Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113
BTC—Bit Test and Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
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BTR—Bit Test and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-117
BTS—Bit Test and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-119
BZHI — Zero High Bits Starting with Specified Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-121
CALL—Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-122
CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword . . . . . . .3-135
CLAC—Clear AC Flag in EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-136
CLC—Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-137
CLD—Clear Direction Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-138
CLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-139
CLFLUSHOPT—Flush Cache Line Optimized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-141
CLI — Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-143
CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-145
CLWB—Cache Line Write Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-146
CMC—Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-148
CMOVcc—Conditional Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-149
CMP—Compare Two Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-153
CMPPD—Compare Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-155
CMPPS—Compare Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-162
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-169
CMPSD—Compare Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-173
CMPSS—Compare Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-177
CMPXCHG—Compare and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-181
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-183
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . .3-186
COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . .3-188
CPUID—CPU Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-190
CRC32 — Accumulate CRC32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-225
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values . . . . . . . . . . . . .3-228
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . .3-232
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . .3-235
CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-239
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-240
CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-244
CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-245
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values .3-246
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-249
CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-252
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . .3-253
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value. .3-255
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . .3-257
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . .3-259
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value. .3-261
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . . .3-263
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword
Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-265
CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers . . . . . . . . . . . . .3-269
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword
Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-270
CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers . . . . . . . . . . . . . .3-273
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer . . . . . . . . . . . . .3-274
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer . . . . . . . . . . . . . . . . . . . . .3-276
CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-278
DAA—Decimal Adjust AL after Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-279
DAS—Decimal Adjust AL after Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-281
DEC—Decrement by 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-283
DIV—Unsigned Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-285
DIVPD—Divide Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-288
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DIVPS—Divide Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-291
DIVSD—Divide Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-294
DIVSS—Divide Scalar Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-296
DPPD — Dot Product of Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-298
DPPS — Dot Product of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-300
EMMS—Empty MMX Technology State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-303
ENTER—Make Stack Frame for Procedure Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-304
EXTRACTPS—Extract Packed Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-307
F2XM1—Compute 2x–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-309
FABS—Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-311
FADD/FADDP/FIADD—Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-312
FBLD—Load Binary Coded Decimal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-315
FBSTP—Store BCD Integer and Pop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-317
FCHS—Change Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-319
FCLEX/FNCLEX—Clear Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-321
FCMOVcc—Floating-Point Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-323
FCOM/FCOMP/FCOMPP—Compare Floating Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-325
FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-328
FCOS— Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-331
FDECSTP—Decrement Stack-Top Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-333
FDIV/FDIVP/FIDIV—Divide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-334
FDIVR/FDIVRP/FIDIVR—Reverse Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-337
FFREE—Free Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-340
FICOM/FICOMP—Compare Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341
FILD—Load Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-343
FINCSTP—Increment Stack-Top Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-345
FINIT/FNINIT—Initialize Floating-Point Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-346
FIST/FISTP—Store Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348
FISTTP—Store Integer with Truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-351
FLD—Load Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-353
FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-355
FLDCW—Load x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-357
FLDENV—Load x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-359
FMUL/FMULP/FIMUL—Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-361
FNOP—No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-364
FPATAN—Partial Arctangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365
FPREM—Partial Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-367
FPREM1—Partial Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-369
FPTAN—Partial Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-371
FRNDINT—Round to Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-373
FRSTOR—Restore x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-374
FSAVE/FNSAVE—Store x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-376
FSCALE—Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-379
FSIN—Sine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381
FSINCOS—Sine and Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-383
FSQRT—Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-385
FST/FSTP—Store Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-387
FSTCW/FNSTCW—Store x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-389
FSTENV/FNSTENV—Store x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-391
FSTSW/FNSTSW—Store x87 FPU Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-393
FSUB/FSUBP/FISUB—Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-395
FSUBR/FSUBRP/FISUBR—Reverse Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-398
FTST—TEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-401
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403
FXAM—Examine Floating-Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-406
FXCH—Exchange Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-408
FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-410
FXSAVE—Save x87 FPU, MMX Technology, and SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413
FXTRACT—Extract Exponent and Significand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-421
Vol. 2A vii
CONTENTS
PAGE
FYL2X—Compute y * log2x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-423
FYL2XP1—Compute y * log2(x +1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-425
HADDPD—Packed Double-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-427
HADDPS—Packed Single-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-430
HLT—Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-433
HSUBPD—Packed Double-FP Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-434
HSUBPS—Packed Single-FP Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-437
IDIV—Signed Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-440
IMUL—Signed Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-443
IN—Input from Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-447
INC—Increment by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-449
INS/INSB/INSW/INSD—Input from Port to String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-451
INSERTPS—Insert Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-454
INT n/INTO/INT 3—Call to Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-457
INVD—Invalidate Internal Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-469
INVLPG—Invalidate TLB Entries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-471
INVPCID—Invalidate Process-Context Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-473
IRET/IRETD—Interrupt Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-476
Jcc—Jump if Condition Is Met. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-483
JMP—Jump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-488
KADDW/KADDB/KADDQ/KADDD—ADD Two Masks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-496
KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-497
KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-498
KMOVW/KMOVB/KMOVQ/KMOVD—Move from and to Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-499
KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-501
KORW/KORB/KORQ/KORD—Bitwise Logical OR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-502
KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks And Set Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-503
KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-505
KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-507
KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-509
KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-511
KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-512
KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-513
LAHF—Load Status Flags into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-514
LAR—Load Access Rights Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-515
LDDQU—Load Unaligned Integer 128 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-518
LDMXCSR—Load MXCSR Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-520
LDS/LES/LFS/LGS/LSS—Load Far Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-521
LEA—Load Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-525
LEAVE—High Level Procedure Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-527
LFENCE—Load Fence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-529
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-530
LLDT—Load Local Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-533
LMSW—Load Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-535
LOCK—Assert LOCK# Signal Prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-537
LODS/LODSB/LODSW/LODSD/LODSQ—Load String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-539
LOOP/LOOPcc—Loop According to ECX Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-542
LSL—Load Segment Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-544
LTR—Load Task Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-547
LZCNT— Count the Number of Leading Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-549
CHAPTER 4
INSTRUCTION SET REFERENCE, M-U
4.1
IMM8 CONTROL BYTE OPERATION FOR PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.2
Source Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.3
Aggregation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.4
Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.1.5
Output Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
viii Vol. 2A
CONTENTS
PAGE
4.1.6
4.1.7
4.1.8
4.2
4.3
Valid/Invalid Override of Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Summary of Im8 Control byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Diagram Comparison and Aggregation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
COMMON TRANSFORMATION AND PRIMITIVE FUNCTIONS FOR SHA1XXX AND SHA256XXX . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
INSTRUCTIONS (M-U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
MASKMOVDQU—Store Selected Bytes of Double Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
MASKMOVQ—Store Selected Bytes of Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
MAXPD—Maximum of Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
MAXPS—Maximum of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
MFENCE—Memory Fence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
MINPD—Minimum of Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
MINPS—Minimum of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
MINSD—Return Minimum Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
MINSS—Return Minimum Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
MONITOR—Set Up Monitor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
MOV—Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
MOV—Move to/from Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
MOV—Move to/from Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
MOVBE—Move Data After Swapping Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
MOVD/MOVQ—Move Doubleword/Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
MOVDDUP—Replicate Double FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
MOVDQ2Q—Move Quadword from XMM to MMX Technology Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
MOVHLPS—Move Packed Single-Precision Floating-Point Values High to Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76
MOVHPD—Move High Packed Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
MOVHPS—Move High Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
MOVLPD—Move Low Packed Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
MOVLPS—Move Low Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-90
MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
MOVNTDQ—Store Packed Integers Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
MOVNTI—Store Doubleword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . 4-98
MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . 4-100
MOVNTQ—Store of Quadword Using Non-Temporal Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-102
MOVQ—Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-103
MOVQ2DQ—Move Quadword from MMX Technology to XMM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-107
MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-111
MOVSHDUP—Replicate Single FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114
MOVSLDUP—Replicate Single FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-117
MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-120
MOVSX/MOVSXD—Move with Sign-Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-124
MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-126
MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-130
MOVZX—Move with Zero-Extend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134
MPSADBW — Compute Multiple Packed Sums of Absolute Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-136
MUL—Unsigned Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144
MULPD—Multiply Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-146
MULPS—Multiply Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-149
MULSD—Multiply Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-152
MULSS—Multiply Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154
Vol. 2A ix
CONTENTS
PAGE
MULX — Unsigned Multiply Without Affecting Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-156
MWAIT—Monitor Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-158
NEG—Two's Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-161
NOP—No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-163
NOT—One's Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-164
OR—Logical Inclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-166
ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-168
ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-171
OUT—Output to Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-174
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-176
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-180
PACKSSWB/PACKSSDW—Pack with Signed Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-186
PACKUSDW—Pack with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-194
PACKUSWB—Pack with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-199
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-204
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-211
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-215
PALIGNR — Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-219
PAND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-223
PANDN—Logical AND NOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-226
PAUSE—Spin Loop Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-229
PAVGB/PAVGW—Average Packed Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-230
PBLENDVB — Variable Blend Packed Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-234
PBLENDW — Blend Packed Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-238
PCLMULQDQ - Carry-Less Multiplication Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-241
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-244
PCMPEQQ — Compare Packed Qword Data for Equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-250
PCMPESTRI — Packed Compare Explicit Length Strings, Return Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-253
PCMPESTRM — Packed Compare Explicit Length Strings, Return Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-255
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-257
PCMPGTQ — Compare Packed Data for Greater Than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-263
PCMPISTRI — Packed Compare Implicit Length Strings, Return Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-266
PCMPISTRM — Packed Compare Implicit Length Strings, Return Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-268
PDEP — Parallel Bits Deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-270
PEXT — Parallel Bits Extract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-272
PEXTRB/PEXTRD/PEXTRQ — Extract Byte/Dword/Qword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-274
PEXTRW—Extract Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-277
PHADDW/PHADDD — Packed Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-280
PHADDSW — Packed Horizontal Add and Saturate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-284
PHMINPOSUW — Packed Horizontal Word Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-286
PHSUBW/PHSUBD — Packed Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-288
PHSUBSW — Packed Horizontal Subtract and Saturate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-291
PINSRB/PINSRD/PINSRQ — Insert Byte/Dword/Qword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-293
PINSRW—Insert Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-296
PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-298
PMADDWD—Multiply and Add Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-301
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-304
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-311
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-316
PMINSB/PMINSW—Minimum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-320
PMINSD/PMINSQ—Minimum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-325
PMINUB/PMINUW—Minimum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-329
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-334
PMOVMSKB—Move Byte Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-338
PMOVSX—Packed Move with Sign Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-340
PMOVZX—Packed Move with Zero Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-350
PMULDQ—Multiply Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-359
PMULHRSW — Packed Multiply High with Round and Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-362
PMULHUW—Multiply Packed Unsigned Integers and Store High Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-366
x Vol. 2A
CONTENTS
PAGE
PMULHW—Multiply Packed Signed Integers and Store High Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-370
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-374
PMULLW—Multiply Packed Signed Integers and Store Low Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-378
PMULUDQ—Multiply Packed Unsigned Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-382
POP—Pop a Value from the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-385
POPA/POPAD—Pop All General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-390
POPCNT — Return the Count of Number of Bits Set to 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-392
POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-394
POR—Bitwise Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-399
PREFETCHh—Prefetch Data Into Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-402
PREFETCHW—Prefetch Data into Caches in Anticipation of a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-404
PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-406
PSADBW—Compute Sum of Absolute Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-408
PSHUFB — Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-412
PSHUFD—Shuffle Packed Doublewords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-416
PSHUFHW—Shuffle Packed High Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-420
PSHUFLW—Shuffle Packed Low Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-423
PSHUFW—Shuffle Packed Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-426
PSIGNB/PSIGNW/PSIGND — Packed SIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-427
PSLLDQ—Shift Double Quadword Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-431
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-433
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-445
PSRLDQ—Shift Double Quadword Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-455
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-457
PSUBB/PSUBW/PSUBD—Subtract Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-469
PSUBQ—Subtract Packed Quadword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-476
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-479
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-483
PTEST- Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-487
PTWRITE - Write Data to a Processor Trace Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-489
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-491
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-501
PUSH—Push Word, Doubleword or Quadword Onto the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-511
PUSHA/PUSHAD—Push All General-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-514
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-516
PXOR—Logical Exclusive OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-518
RCL/RCR/ROL/ROR—Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-521
RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-526
RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-528
RDFSBASE/RDGSBASE—Read FS/GS Segment Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-530
RDMSR—Read from Model Specific Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-532
RDPID—Read Processor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-534
RDPKRU—Read Protection Key Rights for User Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-535
RDPMC—Read Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-537
RDRAND—Read Random Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-541
RDSEED—Read Random SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-543
RDTSC—Read Time-Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-545
RDTSCP—Read Time-Stamp Counter and Processor ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-547
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-549
RET—Return from Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-553
RORX — Rotate Right Logical Without Affecting Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-563
ROUNDPD — Round Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-564
ROUNDPS — Round Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-567
ROUNDSD — Round Scalar Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-570
ROUNDSS — Round Scalar Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-572
RSM—Resume from System Management Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-574
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . 4-576
RSQRTSS—Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . 4-578
SAHF—Store AH into Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-580
Vol. 2A xi
CONTENTS
PAGE
SAL/SAR/SHL/SHR—Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-582
SARX/SHLX/SHRX — Shift Without Affecting Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-587
SBB—Integer Subtraction with Borrow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-589
SCAS/SCASB/SCASW/SCASD—Scan String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-592
SETcc—Set Byte on Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-596
SFENCE—Store Fence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-599
SGDT—Store Global Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-600
SHA1RNDS4—Perform Four Rounds of SHA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-602
SHA1NEXTE—Calculate SHA1 State Variable E after Four Rounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-604
SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords . . . . . . . . . . . . . . . . . . . . .4-605
SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-606
SHA256RNDS2—Perform Two Rounds of SHA256 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-607
SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords . . . . . . . . . . . . . . . .4-609
SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords . . . . . . . . . . . . . . . . . . . . . . . . .4-610
SHLD—Double Precision Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-611
SHRD—Double Precision Shift Right. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-614
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . .4-617
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . .4-622
SIDT—Store Interrupt Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-626
SLDT—Store Local Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-628
SMSW—Store Machine Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-630
SQRTPD—Square Root of Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-632
SQRTPS—Square Root of Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-635
SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-638
SQRTSS—Compute Square Root of Scalar Single-Precision Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-640
STAC—Set AC Flag in EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-642
STC—Set Carry Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-643
STD—Set Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-644
STI—Set Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-645
STMXCSR—Store MXCSR Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-647
STOS/STOSB/STOSW/STOSD/STOSQ—Store String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-648
STR—Store Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-652
SUB—Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-654
SUBPD—Subtract Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-656
SUBPS—Subtract Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-659
SUBSD—Subtract Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-662
SUBSS—Subtract Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-664
SWAPGS—Swap GS Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-666
SYSCALL—Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-668
SYSENTER—Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-670
SYSEXIT—Fast Return from Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-673
SYSRET—Return From Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-676
TEST—Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-679
TZCNT — Count the Number of Trailing Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-681
UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . .4-683
UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . .4-685
UD2—Undefined Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-687
UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . .4-688
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . .4-692
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . .4-696
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . .4-700
CHAPTER 5
INSTRUCTION SET REFERENCE, V-Z
5.1
TERNARY BIT VECTOR LOGIC TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2
INSTRUCTIONS (V-Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
VBROADCAST—Load with Broadcast Floating-Point Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
xii Vol. 2A
CONTENTS
PAGE
VPBROADCASTM—Broadcast Mask to Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
VCOMPRESSPD—Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory. . . . . . . . . . . . . . . . . 5-21
VCOMPRESSPS—Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory . . . . . . . . . . . . . . . . . . 5-23
VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers . . . . . . . . . . . . . . 5-25
VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers . 5-28
VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers . . . 5-31
VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values . . 5-44
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values5-47
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . 5-50
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . 5-52
VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer . . . . . . . . . . . . . 5-54
VCVTSS2USI—Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer . . . . . . . . . . . . . . 5-55
VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword
Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned
Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
VCVTTPD2UQQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned
Quadword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
VCVTTPS2UDQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned
Doubleword Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword
Integer Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66
VCVTTPS2UQQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned
Quadword Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
VCVTTSD2USI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer . . . . . . . . 5-70
VCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer . . . . . . . . . 5-71
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values . 5-73
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values . . 5-75
VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values . . . 5-77
VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values . . . . 5-79
VCVTUSI2SD—Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
VCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . 5-85
VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory . . . . . . . . . . . . . . . . . . . 5-89
VEXPANDPS—Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory . . . . . . . . . . . . . . . . . . . . 5-91
VERR/VERW—Verify a Segment for Reading or Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
VEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less
Than 2^-23 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
VEXP2PS—Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less
Than 2^-23 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106
VFIXUPIMMPD—Fix Up Special Packed Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
VFIXUPIMMPS—Fix Up Special Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-116
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-123
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-126
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-133
VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar Double-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point
Vol. 2A xiii
CONTENTS
PAGE
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-143
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed
Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-146
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed
Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-156
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed
Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-165
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed
Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-175
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-185
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-192
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-199
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single-Precision Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-202
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-205
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-212
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-218
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-221
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-224
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-230
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-236
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single-Precision
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-239
VFPCLASSPD—Tests Types Of a Packed Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-242
VFPCLASSPS—Tests Types Of a Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-245
VFPCLASSSD—Tests Types Of a Scalar Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-247
VFPCLASSSS—Tests Types Of a Scalar Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-249
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices. . . . . . . . . . . . . . . . .5-251
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices. . . . . . . . . . . . . . . . . .5-256
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword . . . . . . . . . . . . . . . . . . . . . . . . .5-261
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data
Values with Signed Dword, Signed Qword Indices Using T0 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-264
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data
Values with Signed Dword, Signed Qword Indices Using T1 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-267
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices . . . . . . . . . . . . . . . . . .5-270
VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword Indices . . . . . . . . . . . . . . . .5-273
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword with Signed Dword Indices. . . . . . . . . . . . . . . . . .5-277
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices . . . . . . . . . . . . . . . .5-280
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices . . . . . . . . . . . . . . . . .5-285
VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-288
VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-291
VGETEXPSD—Convert Exponents of Scalar DP FP Values to DP FP Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-295
VGETEXPSS—Convert Exponents of Scalar SP FP Values to SP FP Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-297
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . .5-299
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . .5-303
VGETMANTSD—Extract Float64 of Normalized Mantissas from Float64 Scalar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-306
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa from Float32 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-308
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-310
xiv Vol. 2A
CONTENTS
PAGE
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values . . . . . . 5-314
VMASKMOV—Conditional SIMD Packed Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-318
VPBLENDD — Blend Packed Dwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-321
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-323
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-325
VPBROADCASTB/W/D/Q—Load with Broadcast Integer Data from General Purpose Register . . . . . . . . . . . . . . . . . . . . . 5-328
VPBROADCAST—Load Integer and Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-331
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-339
VPCMPD/VPCMPUD—Compare Packed Integer Values into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-342
VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-345
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-348
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values into Dense Memory/Register . . . . . . . . . . . . . . . . . . 5-351
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values into Dense Memory/Register . . . . . . . . . . . . . . . . . . . 5-353
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register. 5-355
VPERM2F128 — Permute Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-358
VPERM2I128 — Permute Integer Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-360
VPERMD/VPERMW—Permute Packed Doublewords/Words Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-362
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-365
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-371
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-376
VPERMPD—Permute Double-Precision Floating-Point Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-381
VPERMPS—Permute Single-Precision Floating-Point Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-384
VPERMQ—Qwords Element Permutation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-387
VPEXPANDD—Load Sparse Packed Doubleword Integer Values from Dense Memory / Register . . . . . . . . . . . . . . . . . . . 5-390
VPEXPANDQ—Load Sparse Packed Quadword Integer Values from Dense Memory / Register . . . . . . . . . . . . . . . . . . . . 5-392
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values . . . . . . . . . . . . . . . . . 5-394
VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-397
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register . . . . . . . . . . . . . . 5-400
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask . . . . . . . . . . . . . . . . . . . . . . 5-403
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-406
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-410
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-414
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-418
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-422
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-426
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-430
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-435
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed
Dword, Signed Qword Indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-440
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-445
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-450
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-455
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-460
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-463
VPTESTNMB/W/D/Q—Logical NAND and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-466
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-470
VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-475
VRANGESD—Range Restriction Calculation From a pair of Scalar Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-479
VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-482
VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-485
VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-487
VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-489
VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-491
VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than
2^-28 Relative Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-493
VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28
Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-495
VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28
Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-497
Vol. 2A xv
CONTENTS
PAGE
VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28
Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-499
VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-501
VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-504
VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-506
VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-508
VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits . . . . . . . . . . . . . . . . . . . . . .5-510
VRNDSCALESD—Round Scalar Float64 Value To Include A Given Number Of Fraction Bits . . . . . . . . . . . . . . . . . . . . . . . .5-514
VRNDSCALEPS—Round Packed Float32 Values To Include A Given Number Of Fraction Bits . . . . . . . . . . . . . . . . . . . . . .5-516
VRNDSCALESS—Round Scalar Float32 Value To Include A Given Number Of Fraction Bits. . . . . . . . . . . . . . . . . . . . . . . . .5-519
VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values. . . . . . . . . . . . . . . . . . . .5-521
VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . .5-523
VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values . . . . . . . . . . . . . . . . . . . .5-525
VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . .5-527
VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with
Less Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-529
VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with
Less Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-531
VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with
Less Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-533
VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-Point Value with Less
Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-535
VSCALEFPD—Scale Packed Float64 Values With Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-537
VSCALEFSD—Scale Scalar Float64 Values With Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-540
VSCALEFPS—Scale Packed Float32 Values With Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-542
VSCALEFSS—Scale Scalar Float32 Value With Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-544
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed
Dword and Qword Indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-546
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data
Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-551
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch Packed SP/DP Data
Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-553
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity . . . . . . . . . . .5-555
VTESTPD/VTESTPS—Packed Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-560
VZEROALL—Zero All YMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-563
VZEROUPPER—Zero Upper Bits of YMM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-565
WAIT/FWAIT—Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-567
WBINVD—Write Back and Invalidate Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-568
WRFSBASE/WRGSBASE—Write FS/GS Segment Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-570
WRMSR—Write to Model Specific Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-572
WRPKRU—Write Data to User Page Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-574
XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-575
XABORT — Transactional Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-579
XADD—Exchange and Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-581
XBEGIN — Transactional Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-583
XCHG—Exchange Register/Memory with Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-586
XEND — Transactional End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-588
XGETBV—Get Value of Extended Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-590
XLAT/XLATB—Table Look-up Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-592
XOR—Logical Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-594
XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-596
XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-599
XRSTOR—Restore Processor Extended States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-602
XRSTORS—Restore Processor Extended States Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-606
XSAVE—Save Processor Extended States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-610
XSAVEC—Save Processor Extended States with Compaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-613
XSAVEOPT—Save Processor Extended States Optimized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-616
XSAVES—Save Processor Extended States Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-619
XSETBV—Set Extended Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-622
xvi Vol. 2A
CONTENTS
PAGE
XTEST — Test If In Transactional Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-624
CHAPTER 6
SAFER MODE EXTENSIONS REFERENCE
6.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2
SMX FUNCTIONALITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.1
Detecting and Enabling SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.2
SMX Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2.1
GETSEC[CAPABILITIES] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2.2
GETSEC[ENTERACCS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.2.3
GETSEC[EXITAC]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.2.4
GETSEC[SENTER] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.2.5
GETSEC[SEXIT] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.2.6
GETSEC[PARAMETERS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.2.7
GETSEC[SMCTRL]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.2.8
GETSEC[WAKEUP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.3
Measured Environment and SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3
GETSEC LEAF FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
GETSEC[CAPABILITIES] - Report the SMX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
GETSEC[EXITAC]—Exit Authenticated Code Execution Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
GETSEC[SENTER]—Enter a Measured Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
GETSEC[SEXIT]—Exit Measured Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
GETSEC[PARAMETERS]—Report the SMX Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
GETSEC[SMCTRL]—SMX Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
GETSEC[WAKEUP]—Wake up sleeping processors in measured environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
APPENDIX A
OPCODE MAP
A.1
USING OPCODE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2
KEY TO ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2.1
Codes for Addressing Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
A.2.2
Codes for Operand Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2
A.2.3
Register Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-3
A.2.4
Opcode Look-up Examples for One, Two, and Three-Byte Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-3
A.2.4.1
One-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.2.4.2
Two-Byte Opcode Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.2.4.3
Three-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.4.4
VEX Prefix Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.5
Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-6
A.3
ONE, TWO, AND THREE-BYTE OPCODE MAPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.4
OPCODE EXTENSIONS FOR ONE-BYTE AND TWO-BYTE OPCODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.4.1
Opcode Look-up Examples Using Opcode Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.4.2
Opcode Extension Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.5
ESCAPE OPCODE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.1
Opcode Look-up Examples for Escape Instruction Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2
Escape Opcode Instruction Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2.1
Escape Opcodes with D8 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2.2
Escape Opcodes with D9 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
A.5.2.3
Escape Opcodes with DA as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
A.5.2.4
Escape Opcodes with DB as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
A.5.2.5
Escape Opcodes with DC as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
A.5.2.6
Escape Opcodes with DD as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
A.5.2.7
Escape Opcodes with DE as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
A.5.2.8
Escape Opcodes with DF As First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
APPENDIX B
INSTRUCTION FORMATS AND ENCODINGS
B.1
MACHINE INSTRUCTION FORMAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Vol. 2A xvii
CONTENTS
PAGE
B.1.1
B.1.2
B.1.3
B.1.4
B.1.4.1
B.1.4.2
B.1.4.3
B.1.4.4
B.1.4.5
B.1.4.6
B.1.4.7
B.1.4.8
B.1.5
B.2
B.2.1
B.3
B.4
B.5
B.5.1
B.5.2
B.5.3
B.6
B.7
B.8
B.9
B.9.1
B.10
B.11
B.12
B.13
B.14
B.15
B.16
B.17
B.18
B.19
Legacy Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Opcode Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Special Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Reg Field (reg) for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-3
Reg Field (reg) for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Segment Register (sreg) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Condition Test (tttn) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
Direction (d) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
Other Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
GENERAL-PURPOSE INSTRUCTION FORMATS AND ENCODINGS FOR NON-64-BIT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
General Purpose Instruction Formats and Encodings for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
MMX INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Granularity Field (gg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
MMX Technology and General-Purpose Register Fields (mmxreg and reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
MMX Instruction Formats and Encodings Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
PROCESSOR EXTENDED STATE INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
SSE INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42
SSE2 INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
Granularity Field (gg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
SSE3 FORMATS AND ENCODINGS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
SSSE3 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
AESNI AND PCLMULQDQ INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-63
SPECIAL ENCODINGS FOR 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
SSE4.1 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-66
SSE4.2 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-71
AVX FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-73
FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
VMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-117
SMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-118
APPENDIX C
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
C.1
SIMPLE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C.2
COMPOSITE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14
xviii Vol. 2A
CONTENTS
PAGE
FIGURES
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 3-12.
Figure 3-13.
Figure 3-14.
Figure 3-15.
Figure 3-16.
Figure 3-17.
Figure 3-18.
Figure 3-19.
Figure 3-20.
Figure 3-21.
Figure 3-22.
Figure 3-23.
Figure 3-24.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
Figure 4-13.
Figure 4-14.
Figure 4-15.
Figure 4-16.
Figure 4-17.
Figure 4-18.
Figure 4-19.
Figure 4-20.
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Intel 64 and IA-32 Architectures Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table Interpretation of ModR/M Byte (C8H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Prefix Ordering in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Memory Addressing Without an SIB Byte; REX.X Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Register-Register Addressing (No Memory Operand); REX.X Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Memory Addressing With a SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Instruction Encoding Format with VEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
VEX bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
AVX-512 Instruction Format and the EVEX Prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Bit Field Layout of the EVEX Prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Bit Offset for BIT[RAX, 21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Memory Bit Indexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
ADDSUBPS—Packed Single-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
Memory Layout of BNDMOV to/from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100
Version Information Returned by CPUID in EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-204
Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-206
Feature Information Returned in the EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-208
Determination of Support for the Processor Brand String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-217
Algorithm for Extracting Processor Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-218
CVTDQ2PD (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-229
VCVTPD2DQ (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-236
VCVTPD2PS (VEX.256 encoded version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-241
CVTPS2PD (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-250
VCVTTPD2DQ (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-266
HADDPD—Packed Double-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-427
VHADDPD operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-428
HADDPS—Packed Single-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431
VHADDPS operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431
HSUBPD—Packed Double-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-434
VHSUBPD operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-435
HSUBPS—Packed Single-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-438
VHSUBPS operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-438
INVPCID Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-473
Operation of PCMPSTRx and PCMPESTRx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
VMOVDDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
MOVSHDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114
MOVSLDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-117
256-bit VMPSADBW Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-137
Operation of the PACKSSDW Instruction Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187
256-bit VPALIGN Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-220
PDEP Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-270
PEXT Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-272
256-bit VPHADDD Instruction Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-281
PMADDWD Execution Model Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-302
PMULHUW and PMULHW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367
PMULLU Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-379
PSADBW Instruction Operation Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-409
PSHUFB with 64-Bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-414
256-bit VPSHUFD Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-417
PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-435
PSRAW and PSRAD Instruction Operation Using a 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-447
PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-459
PUNPCKHBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-493
Vol. 2A xix
CONTENTS
PAGE
Figure 4-21.
Figure 4-22.
Figure 4-23.
Figure 4-24.
Figure 4-25.
Figure 4-26.
Figure 4-27.
Figure 4-28.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10.
Figure 5-11.
Figure 5-12.
Figure 5-13.
Figure 5-14.
Figure 5-15.
Figure 5-16.
Figure 5-17.
Figure 5-18.
Figure 5-19.
Figure 5-20.
Figure 5-21.
Figure 5-22.
Figure 5-23.
Figure 5-24.
Figure 5-25.
Figure 5-26.
Figure 5-27.
Figure 5-28.
Figure 5-29.
Figure A-1.
Figure B-1.
Figure B-2.
xx Vol. 2A
256-bit VPUNPCKHDQ Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-493
PUNPCKLBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-503
256-bit VPUNPCKLDQ Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-503
Bit Control Fields of Immediate Byte for ROUNDxx Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-565
256-bit VSHUFPD Operation of Four Pairs of DP FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-618
256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved Result . . . . . . . . . . . . . 4-623
VUNPCKHPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-693
VUNPCKLPS Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-701
VBROADCASTSS Operation (VEX.256 encoded version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
VBROADCASTSS Operation (VEX.128-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
VBROADCASTSD Operation (VEX.256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
VBROADCASTF128 Operation (VEX.256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
VBROADCASTF64X4 Operation (512-bit version with writemask all 1s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
VCVTPH2PS (128-bit Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
VCVTPS2PH (128-bit Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
64-bit Super Block of SAD Operation in VDBPSADBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
VFIXUPIMMPD Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115
VFIXUPIMMPS Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-119
VFIXUPIMMSD Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-122
VFIXUPIMMSS Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-125
Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-242
VGETEXPPS Functionality On Normal Input values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-292
Imm8 Controls for VGETMANTPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-299
VPBROADCASTD Operation (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VPBROADCASTD Operation (128-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VPBROADCASTQ Operation (256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VBROADCASTI128 Operation (256-bit version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VBROADCASTI256 Operation (512-bit version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-334
VPERM2F128 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-358
VPERM2I128 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-360
VPERMILPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-372
VPERMILPD Shuffle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-372
VPERMILPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-377
VPERMILPS Shuffle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-377
Imm8 Controls for VRANGEPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-470
Imm8 Controls for VREDUCEPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-501
Imm8 Controls for VRNDSCALEPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-511
ModR/M Byte nnn Field (Bits 5, 4, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
General Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
Hybrid Notation of VEX-Encoded Key Instruction Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-73
CONTENTS
PAGE
TABLES
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-6.
Table 2-5.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 2-14.
Table 2-15.
Table 2-16.
Table 2-17.
Table 2-18.
Table 2-19.
Table 2-20.
Table 2-21.
Table 2-22.
Table 2-23.
Table 2-24.
Table 2-25.
Table 2-26.
Table 2-27.
Table 2-28.
Table 2-29.
Table 2-30.
Table 2-31.
Table 2-32.
Table 2-33.
Table 2-34.
Table 2-35.
Table 2-36.
Table 2-37.
Table 2-38.
Table 2-39.
Table 2-40.
Table 2-41.
Table 2-42.
Table 2-43.
Table 2-44.
Table 2-45.
Table 2-46.
Table 2-47.
Table 2-48.
Table 2-49.
Table 2-50.
Table 2-51.
Table 2-52.
Table 2-53.
Table 2-54.
Table 2-55.
Table 2-56.
Table 2-57.
16-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
32-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
32-Bit Addressing Forms with the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
REX Prefix Fields [BITS: 0100WRXB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Direct Memory Offset Form of MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Special Cases of REX Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
VEX.vvvv to register name mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Instructions with a VEX.vvvv destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
VEX.m-mmmm interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
VEX.L interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
VEX.pp interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
32-Bit VSIB Addressing Forms of the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Exception class description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Instructions in each Exception Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
#UD Exception and VEX.W=1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
#UD Exception and VEX.L Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Type 1 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Type 2 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Type 3 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Type 4 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Type 5 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Type 6 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Type 7 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Type 8 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Type 11 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Type 12 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
VEX-Encoded GPR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Exception Definition (VEX-Encoded GPR Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
EVEX Prefix Bit Field Functional Grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
32-Register Support in 64-bit Mode Using EVEX with Embedded REX Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
EVEX Encoding Register Specifiers in 32-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Opmask Register Specifier Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Compressed Displacement (DISP8*N) Affected by Embedded Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
EVEX DISP8*N for Instructions Not Affected by Embedded Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
OS XSAVE Enabling Requirements of Instruction Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Opcode Independent, State Dependent EVEX Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
#UD Conditions of Operand-Encoding EVEX Prefix Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
#UD Conditions of Opmask Related Encoding Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
#UD Conditions Dependent on EVEX.b Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
EVEX-Encoded Instruction Exception Class Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
EVEX Instructions in each Exception Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
Type E1 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
Type E1NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Type E2 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Type E3 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Type E3NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
Type E4 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Type E4NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
Type E5 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
Type E5NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
Type E6 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Type E6NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Type E7NM Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Type E9 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Type E9NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Vol. 2A xxi
CONTENTS
PAGE
Table 2-58.
Table 2-59.
Table 2-60.
Table 2-61.
Table 2-62.
Table 2-63.
Table 2-64.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-8.
Table 3-9.
Table 3-10.
Table 3-11.
Table 3-12.
Table 3-13.
Table 3-14.
Table 3-15.
Table 3-16.
Table 3-17.
Table 3-18.
Table 3-19.
Table 3-20.
Table 3-21.
Table 3-22.
Table 3-23.
Table 3-24.
Table 3-25.
Table 3-26.
Table 3-27.
Table 3-28.
Table 3-29.
Table 3-30.
Table 3-31.
Table 3-32.
Table 3-33.
Table 3-34.
Table 3-35.
Table 3-36.
Table 3-37.
Table 3-38.
Table 3-39.
Table 3-40.
Table 3-41.
Table 3-42.
Table 3-43.
xxii Vol. 2A
Type E10 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
Type E10NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
Type E11 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Type E12 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
Type E12NP Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
TYPE K21 Exception Definition (VEX-Encoded OpMask Instructions Addressing Memory) . . . . . . . . . . . . . . . . . . . . . . . 2-68
Register Codes Associated With +rb, +rw, +rd, +ro. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Range of Bit Positions Specified by Bit Offset Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Standard and Non-standard Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Intel 64 and IA-32 General Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
x87 FPU Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
SIMD Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Decision Table for CLI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143
Comparison Predicate for CMPPD and CMPPS Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156
Pseudo-Op and CMPPD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157
Pseudo-Op and VCMPPD Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-158
Pseudo-Op and CMPPS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
Pseudo-Op and VCMPPS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-164
Pseudo-Op and CMPSD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174
Pseudo-Op and VCMPSD Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174
Pseudo-Op and CMPSS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
Pseudo-Op and VCMPSS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
Information Returned by CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-191
Processor Type Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-205
Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-206
More on Feature Information Returned in the EDX Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-209
Encoding of CPUID Leaf 2 Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-211
Processor Brand String Returned with Pentium 4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-218
Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-219
DIV Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-285
Results Obtained from F2XM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-309
Results Obtained from FABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-311
FADD/FADDP/FIADD Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-313
FBSTP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-317
FCHS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-319
FCOM/FCOMP/FCOMPP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-325
FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-328
FCOS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-331
FDIV/FDIVP/FIDIV Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-335
FDIVR/FDIVRP/FIDIVR Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-338
FICOM/FICOMP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341
FIST/FISTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348
FISTTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-351
FMUL/FMULP/FIMUL Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-362
FPATAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365
FPREM Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-367
FPREM1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-369
FPTAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-371
FSCALE Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-379
FSIN Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381
FSINCOS Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-383
FSQRT Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-385
FSUB/FSUBP/FISUB Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-396
FSUBR/FSUBRP/FISUBR Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-399
FTST Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-401
FUCOM/FUCOMP/FUCOMPP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403
FXAM Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-406
Non-64-bit-Mode Layout of FXSAVE and FXRSTOR Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413
CONTENTS
PAGE
Table 3-44.
Table 3-45.
Table 3-46.
Table 3-47.
Table 3-48.
Table 3-49.
Table 3-50.
Table 3-51.
Table 3-52.
Table 3-53.
Table 3-54.
Table 3-55.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
Table 4-9.
Table 4-10.
Table 4-11.
Table 4-12.
Table 4-13.
Table 4-14.
Table 4-15.
Table 4-16.
Table 4-17.
Table 4-18.
Table 4-19.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 5-10.
Table 5-11.
Table 5-12.
Table 5-13.
Table 5-14.
Table 5-15.
Table 5-16.
Table 5-17.
Table 5-18.
Table 5-19.
Table 5-20.
Table 5-21.
Table 5-22.
Table 5-23.
Table 5-24.
Table 5-25.
Table 5-26.
Table 5-27.
Table 5-28.
Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-414
Recreating FSAVE Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-416
Layout of the 64-bit-mode FXSAVE64 Map (requires REX.W = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-417
Layout of the 64-bit-mode FXSAVE Map (REX.W = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-418
FYL2X Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-423
FYL2XP1 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-425
IDIV Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-440
Decision Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-458
Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-516
Non-64-bit Mode LEA Operation with Address and Operand Size Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-525
64-bit Mode LEA Operation with Address and Operand Size Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-525
Segment and Gate Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-545
Source Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Aggregation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Aggregation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Comparison Result for Each Element Pair BoolRes[i.j] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Summary of Imm8 Control Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
MUL Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144
MWAIT Extension Register (ECX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-159
MWAIT Hints Register (EAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-159
Recommended Multi-Byte Sequence of NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-163
PCLMULQDQ Quadword Selection of Immediate Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-241
Pseudo-Op and PCLMULQDQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-241
Effect of POPF/POPFD on the EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-395
Valid General and Special Purpose Performance Counter Index Range for RDPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-537
Repeat Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-550
Rounding Modes and Encoding of Rounding Control (RC) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-565
Decision Table for STI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-645
Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Special Values Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
Special Values Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98
Classifier Operations for VFPCLASSPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-242
VGETEXPPD/SD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-288
VGETEXPPS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-291
GetMant() Special Float Values Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-300
Pseudo-Op and VPCMP* Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-340
Examples of VPTERNLOGD/Q Imm8 Boolean Function and Input Index Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-461
Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2] . . . . . . . . . . . . . . . . . 5-471
Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS and MAX, MAX_ABS . . . . . . . . . . . . . . . . . . . . 5-471
Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0). . . . . . . . . . . . 5-471
VRCP14PD/VRCP14SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-485
VRCP14PS/VRCP14SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-489
VRCP28PD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-494
VRCP28SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-496
VRCP28PS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-498
VRCP28SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-500
VREDUCEPD/SD/PS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-502
VRNDSCALEPD/SD/PS/SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-511
VRSQRT14PD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-522
VRSQRT14SD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-524
VRSQRT14PS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-526
VRSQRT14SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-528
VRSQRT28PD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-530
VRSQRT28SD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-532
Vol. 2A xxiii
CONTENTS
PAGE
Table 5-29.
Table 5-30.
Table 5-31.
Table 5-32.
Table 5-33.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 6-8.
Table 6-9.
Table 6-10.
Table 6-11.
Table 6-12.
Table A-1.
Table A-2.
Table A-3.
Table A-4.
Table A-5.
Table A-6.
Table A-7.
Table A-8.
Table A-9.
Table A-10.
Table A-11.
Table A-12.
Table A-13.
Table A-14.
Table A-15.
Table A-16.
Table A-17.
Table A-18.
Table A-19.
Table A-20.
Table A-21.
Table A-22.
Table B-1.
Table B-2.
Table B-3.
Table B-4.
Table B-5.
Table B-6.
Table B-7.
Table B-8.
Table B-9.
Table B-10.
Table B-11.
Table B-13.
Table B-12.
Table B-14.
Table B-15.
Table B-16.
Table B-17.
Table B-18.
Table B-19.
Table B-20.
xxiv Vol. 2A
VRSQRT28PS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-534
VRSQRT28SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-536
\VSCALEFPD/SD/PS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-537
Additional VSCALEFPD/SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-538
Additional VSCALEFPS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-542
Layout of IA32_FEATURE_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
GETSEC Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Getsec Capability Result Encoding (EBX = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Register State Initialization after GETSEC[ENTERACCS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
IA32_MISC_ENABLE MSR Initialization by ENTERACCS and SENTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Register State Initialization after GETSEC[SENTER] and GETSEC[WAKEUP]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
SMX Reporting Parameters Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
TXT Feature Extensions Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
External Memory Types Using Parameter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Default Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Supported Actions for GETSEC[SMCTRL(0)] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
RLP MVMM JOIN Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
One-byte Opcode Map: (00H — F7H) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
Three-byte Opcode Map: 00H — F7H (First Two Bytes are 0F 38H) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
Three-byte Opcode Map: 00H — F7H (First two bytes are 0F 3AH) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
Opcode Extensions for One- and Two-byte Opcodes by Group Number * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18
D8 Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
D8 Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
D9 Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
D9 Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
DA Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
DA Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
DB Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
DB Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
DC Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
DC Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
DD Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
DD Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
DE Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
DE Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
DF Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
DF Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-28
Special Fields Within Instruction Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Encoding of reg Field When w Field is Not Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Encoding of reg Field When w Field is Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Encoding of reg Field When w Field is Not Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encoding of reg Field When w Field is Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encoding of Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Encoding of the Segment Register (sreg) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Encoding of Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Encoding of Conditional Test (tttn) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
Encoding of Operation Direction (d) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
General Purpose Instruction Formats and Encodings for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Notes on Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Special Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
General Purpose Instruction Formats and Encodings for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
Pentium Processor Family Instruction Formats and Encodings, Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Pentium Processor Family Instruction Formats and Encodings, 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
MMX Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
CONTENTS
PAGE
Table B-21.
Table B-22.
Table B-23.
Table B-25.
Table B-24.
Table B-26.
Table B-27.
Table B-28.
Table B-29.
Table B-30.
Table B-31.
Table B-32.
Table B-33.
Table B-34.
Table B-35.
Table B-36.
Table B-37.
Table B-38.
Table B-39.
Table B-40.
Table B-41.
Table C-1.
Table C-2.
Formats and Encodings of P6 Family Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
Formats and Encodings of SSE Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42
Formats and Encodings of SSE Integer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47
Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
Format and Encoding of SSE Cacheability & Memory Ordering Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
Formats and Encodings of SSE2 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-49
Formats and Encodings of SSE2 Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-54
Format and Encoding of SSE2 Cacheability Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58
Formats and Encodings of SSE3 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
Formats and Encodings for SSE3 Event Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
Formats and Encodings for SSE3 Integer and Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
Formats and Encodings for SSSE3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
Formats and Encodings of AESNI and PCLMULQDQ Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-63
Special Case Instructions Promoted Using REX.W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
Encodings of SSE4.1 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-66
Encodings of SSE4.2 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-72
Encodings of AVX instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-73
General Floating-Point Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
Floating-Point Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
Encodings for VMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-117
Encodings for SMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-118
Simple Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Composite Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14
Vol. 2A xxv
CONTENTS
PAGE
xxvi Vol. 2A
CHAPTER 1
ABOUT THIS MANUAL
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set
Reference (order numbers 253666, 253667, 326018 and 334569) are part of a set that describes the architecture
and programming environment of all Intel 64 and IA-32 architecture processors. Other volumes in this set are:
•
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (Order
Number 253665).
•
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D: System
Programming Guide (order numbers 253668, 253669, 326019 and 332831).
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture
and programming environment of Intel 64 and IA-32 processors. The Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volumes 2A, 2B, 2C & 2D, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers who write operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D, describe
the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operatingsystem and BIOS designers. In addition, the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B, addresses the programming environment for classes of software that host operating systems.
1.1
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL
This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which
include:
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Pentium® processors
P6 family processors
Pentium® 4 processors
Pentium® M processors
Intel® Xeon® processors
Pentium® D processors
Pentium® processor Extreme Editions
64-bit Intel® Xeon® processors
Intel® Core™ Duo processor
Intel® Core™ Solo processor
Dual-Core Intel® Xeon® processor LV
Intel® Core™2 Duo processor
Intel® Core™2 Quad processor Q6000 series
Intel® Xeon® processor 3000, 3200 series
Intel® Xeon® processor 5000 series
Intel® Xeon® processor 5100, 5300 series
Intel® Core™2 Extreme processor X7000 and X6800 series
Intel® Core™2 Extreme processor QX6000 series
Intel® Xeon® processor 7100 series
Intel® Pentium® Dual-Core processor
Intel® Xeon® processor 7200, 7300 series
Intel® Xeon® processor 5200, 5400, 7400 series
Vol. 2A 1-1
ABOUT THIS MANUAL
•
•
•
•
•
Intel® Core™2 Extreme processor QX9000 and X9000 series
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
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•
Intel® Core™ i7 processor
Intel® Core™2 Quad processor Q9000 series
Intel® Core™2 Duo processor E8000, T9000 series
Intel® Atom™ processor family
Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are built from 45 nm and 32 nm processes
Intel® Core™ i5 processor
Intel® Xeon® processor E7-8800/4800/2800 product families
Intel® Core™ i7-3930K processor
2nd generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series
Intel® Xeon® processor E3-1200 product family
Intel® Xeon® processor E5-2400/1400 product family
Intel® Xeon® processor E5-4600/2600/1600 product family
3rd generation Intel® Core™ processors
Intel® Xeon® processor E3-1200 v2 product family
Intel® Xeon® processor E5-2400/1400 v2 product families
Intel® Xeon® processor E5-4600/2600/1600 v2 product families
Intel® Xeon® processor E7-8800/4800/2800 v2 product families
4th generation Intel® Core™ processors
The Intel® Core™ M processor family
Intel® Core™ i7-59xx Processor Extreme Edition
Intel® Core™ i7-49xx Processor Extreme Edition
Intel® Xeon® processor E3-1200 v3 product family
Intel® Xeon® processor E5-2600/1600 v3 product families
5th generation Intel® Core™ processors
Intel® Xeon® processor D-1500 product family
Intel® Xeon® processor E5 v4 family
Intel® Atom™ processor X7-Z8000 and X5-Z8000 series
Intel® Atom™ processor Z3400 series
Intel® Atom™ processor Z3500 series
6th generation Intel® Core™ processors
Intel® Xeon® processor E3-1500m v5 product family
P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium®
Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors.
The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microarchitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture. Intel Xeon
processor 5000, 7100 series are based on the Intel NetBurst® microarchitecture.
The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LV are based on an improved
Pentium® M processor microarchitecture.
The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel® Pentium® dual-core, Intel®
Core™2 Duo, Intel® Core™2 Quad, and Intel® Core™2 Extreme processors are based on Intel® Core™ microarchitecture.
1-2 Vol. 2A
ABOUT THIS MANUAL
The Intel® Xeon® processor 5200, 5400, 7400 series, Intel® Core™2 Quad processor Q9000 series, and Intel®
Core™2 Extreme processors QX9000, X9000 series, Intel® Core™2 processor E8000 series are based on Enhanced
Intel® Core™ microarchitecture.
The Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are based on the Intel® Atom™ microarchitecture and supports Intel 64 architecture.
The Intel® Core™ i7 processor and Intel® Xeon® processor 3400, 5500, 7500 series are based on 45 nm Intel®
microarchitecture code name Nehalem. Intel® microarchitecture code name Westmere is a 32 nm version of Intel®
microarchitecture code name Nehalem. Intel® Xeon® processor 5600 series, Intel Xeon processor E7 and various
Intel Core i7, i5, i3 processors are based on Intel® microarchitecture code name Westmere. These processors
support Intel 64 architecture.
The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor E78800/4800/2800 product families, Intel® Core™ i7-3930K processor, and 2nd generation Intel® Core™ i7-2xxx,
Intel® CoreTM i5-2xxx, Intel® Core™ i3-2xxx processor series are based on the Intel® microarchitecture code name
Sandy Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E7-8800/4800/2800 v2 product families, Intel® Xeon® processor E3-1200 v2 product
family and 3rd generation Intel® Core™ processors are based on the Intel® microarchitecture code name Ivy
Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E5-4600/2600/1600 v2 product families, Intel® Xeon® processor E5-2400/1400 v2
product families and Intel® Core™ i7-49xx Processor Extreme Edition are based on the Intel® microarchitecture
code name Ivy Bridge-E and support Intel 64 architecture.
The Intel® Xeon® processor E3-1200 v3 product family and 4th Generation Intel® Core™ processors are based on
the Intel® microarchitecture code name Haswell and support Intel 64 architecture.
The Intel® Core™ M processor family, 5th generation Intel® Core™ processors, Intel® Xeon® processor D-1500
product family and the Intel® Xeon® processor E5 v4 family are based on the Intel® microarchitecture code name
Broadwell and support Intel 64 architecture.
The Intel® Xeon® processor E3-1500m v5 product family and 6th generation Intel® Core™ processors are based
on the Intel® microarchitecture code name Skylake and support Intel 64 architecture.
The Intel® Xeon® processor E5-2600/1600 v3 product families and the Intel® Core™ i7-59xx Processor Extreme
Edition are based on the Intel® microarchitecture code name Haswell-E and support Intel 64 architecture.
The Intel® Atom™ processor Z8000 series is based on the Intel microarchitecture code name Airmont.
The Intel® Atom™ processor Z3400 series and the Intel® Atom™ processor Z3500 series are based on the Intel
microarchitecture code name Silvermont.
P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-core Intel® Xeon® processor LV,
and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel® AtomTM
processor Z5xx series support IA-32 architecture.
The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel®
Core™2 Duo, Intel® Core™2 Extreme, Intel® Core™2 Quad processors, Pentium® D processors, Pentium® DualCore processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel® 64 architecture.
IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microprocessors. Intel® 64 architecture is the instruction set architecture and programming environment which is the superset
of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.
1.2
OVERVIEW OF VOLUME 2A, 2B, 2C AND 2D: INSTRUCTION SET REFERENCE
A description of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D content
follows:
Chapter 1 — About This Manual. Gives an overview of all seven volumes of the Intel® 64 and IA-32 Architectures Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related
Intel® manuals and documentation of interest to programmers and hardware designers.
Vol. 2A 1-3
ABOUT THIS MANUAL
Chapter 2 — Instruction Format. Describes the machine-level instruction format used for all IA-32 instructions
and gives the allowable encodings of prefixes, the operand-identifier byte (ModR/M byte), the addressing-mode
specifier byte (SIB byte), and the displacement and immediate bytes.
Chapter 3 — Instruction Set Reference, A-L. Describes Intel 64 and IA-32 instructions in detail, including an
algorithmic description of operations, the effect on flags, the effect of operand- and address-size attributes, and
the exceptions that may be generated. The instructions are arranged in alphabetical order. General-purpose, x87
FPU, Intel MMX™ technology, SSE/SSE2/SSE3/SSSE3/SSE4 extensions, and system instructions are included.
Chapter 4 — Instruction Set Reference, M-U. Continues the description of Intel 64 and IA-32 instructions
started in Chapter 3. It starts Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
Chapter 5 — Instruction Set Reference, V-Z. Continues the description of Intel 64 and IA-32 instructions
started in chapters 3 and 4. It provides the balance of the alphabetized list of instructions and starts Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2C.
Chapter 6— Safer Mode Extensions Reference. Describes the safer mode extensions (SMX). SMX is intended
for a system executive to support launching a measured environment in a platform where the identity of the software controlling the platform hardware can be measured for the purpose of making trust decisions. This chapter
starts Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D.
Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set.
Appendix B — Instruction Formats and Encodings. Gives the binary encoding of each form of each IA-32
instruction.
Appendix C — Intel® C/C++ Compiler Intrinsics and Functional Equivalents. Lists the Intel® C/C++ compiler
intrinsics and their assembly code equivalents for each of the IA-32 MMX and SSE/SSE2/SSE3 instructions.
1.3
NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for
hexadecimal and binary numbers. A review of this notation makes the manual easier to read.
1.3.1
Bit and Byte Order
In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses
increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to
two raised to the power of the bit position. IA-32 processors are “little endian” machines; this means the bytes of
a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.
Highest
Address 31
24 23
Byte 3
Data Structure
8 7
16 15
Byte 2
Byte 1
0
Byte 0
Bit offset
28
24
20
16
12
8
4
0
Byte Offset
Figure 1-1. Bit and Byte Order
1-4 Vol. 2A
Lowest
Address
ABOUT THIS MANUAL
1.3.2
Reserved Bits and Software Compatibility
In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as
reserved, it is essential for compatibility with future processors that software treat these bits as having a future,
though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable. Software should follow these guidelines in dealing with reserved bits:
•
Do not depend on the states of any reserved bits when testing the values of registers which contain such bits.
Mask out the reserved bits before testing.
•
•
•
Do not depend on the states of any reserved bits when storing to memory or to a register.
Do not depend on the ability to retain information written into any reserved bits.
When loading a register, always load the reserved bits with the values indicated in the documentation, if any,
or reload them with values previously read from the same register.
NOTE
Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon
the values of reserved register bits will make software dependent upon the unspecified manner in
which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors.
1.3.3
Instruction Operands
When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset,
an instruction has the following format:
label: mnemonic argument1, argument2, argument3
where:
•
•
•
A label is an identifier which is followed by a colon.
A mnemonic is a reserved name for a class of instruction opcodes which have the same function.
The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands,
depending on the opcode. When present, they take the form of either literals or identifiers for data items.
Operand identifiers are either reserved names of registers or are assumed to be assigned to data items
declared in another part of the program (which may not be shown in the example).
When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left
operand is the destination.
For example:
LOADREG: MOV EAX, SUBTOTAL
In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,
and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.
1.3.4
Hexadecimal and Binary Numbers
Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for
example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, and F.
Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for
example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might
arise.
Vol. 2A 1-5
ABOUT THIS MANUAL
1.3.5
Segmented Addressing
The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes.
Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes in memory. The
range of memory that can be addressed is called an address space.
The processor also supports segmented addressing. This is a form of addressing where a program may have many
independent address spaces, called segments. For example, a program can keep its code (instructions) and stack
in separate segments. Code addresses would always refer to the code space, and stack addresses would always
refer to the stack space. The following notation is used to specify a byte address within a segment:
Segment-register:Byte-address
For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS
register:
DS:FF79H
The following segment address identifies an instruction address in the code segment. The CS register points to the
code segment and the EIP register contains the address of the instruction.
CS:EIP
1.3.6
Exceptions
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the
error. An example of the notation used to show an exception and error code is shown below:
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is
reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate
code. In this case, the error code is zero, as shown below for a general-protection exception:
#GP(0)
1.3.7
A New Syntax for CPUID, CR, and MSR Values
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information.
See Figure 1-2.
1-6 Vol. 2A
ABOUT THIS MANUAL
CPUID Input and Output
CPUID.01H:ECX.SSE[bit 25] = 1
Input value for EAX register
Output register and feature flag or field
name with bit position(s)
Value (or range) of output
Control Register Values
CR4.OSFXSR[bit 9] = 1
Example CR name
Feature flag or field name
with bit position(s)
Value (or range) of output
Model-Specific Register Values
IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1
Example MSR name
Feature flag or field name with bit position(s)
Value (or range) of output
SDM20002
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation
1.4
RELATED LITERATURE
Literature related to Intel 64 and IA-32 processors is listed and viewable on-line at:
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
See also:
•
•
•
The data sheet for a particular Intel 64 or IA-32 processor
•
Intel® Fortran Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
The specification update for a particular Intel 64 or IA-32 processor
Intel® C++ Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
Vol. 2A 1-7
ABOUT THIS MANUAL
•
Intel® Software Development Tools:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual (in three or seven volumes):
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
•
Intel® 64 and IA-32 Architectures Optimization Reference Manual:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimizationmanual.html
•
Intel 64 Architecture x2APIC Specification:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-architecture-x2apic-specification.html
•
Intel® Trusted Execution Technology Measured Launched Environment Programming Guide:
http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html
•
Developing Multi-threaded Applications: A Platform Consistent Approach:
https://software.intel.com/sites/default/files/article/147714/51534-developing-multithreaded-applications.pdf
•
Using Spin-Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor:
http://software.intel.com/en-us/articles/ap949-using-spin-loops-on-intel-pentiumr-4-processor-and-intelxeonr-processor/
•
Performance Monitoring Unit Sharing Guide
http://software.intel.com/file/30388
Literature related to selected features in future Intel processors are available at:
•
Intel® Architecture Instruction Set Extensions Programming Reference
https://software.intel.com/en-us/isa-extensions
•
Intel® Software Guard Extensions (Intel® SGX) Programming Reference
https://software.intel.com/en-us/isa-extensions/intel-sgx
More relevant links are:
•
Intel® Developer Zone:
•
Developer centers:
https://software.intel.com/en-us
http://www.intel.com/content/www/us/en/hardware-developers/developer-centers.html
•
Processor support general link:
http://www.intel.com/support/processors/
•
Software products and packages:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® Hyper-Threading Technology (Intel® HT Technology):
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm
1-8 Vol. 2A
CHAPTER 2
INSTRUCTION FORMAT
This chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for
protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for
IA-32e mode and its sub-modes are described in Section 2.2.
2.1
INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE,
AND VIRTUAL-8086 MODE
The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), primary opcode bytes (up to three bytes), an
addressing-form specifier (if required) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base)
byte, a displacement (if required), and an immediate data field (if required).
Instruction
Prefixes
Opcode
ModR/M
SIB
Prefixes of
1-, 2-, or 3-byte 1 byte
1 byte each opcode
(if required)
(optional)1, 2
7
6 5
Mod
3 2
Reg/
Opcode
0
R/M
1 byte
(if required)
7
Immediate
Address
displacement
of 1, 2, or 4
bytes or none3
Immediate
data of
1, 2, or 4
bytes or none3
3 2
6 5
Scale
Displacement
Index
0
Base
1. The REX prefix is optional, but if used must be immediately before the opcode; see Section
2.2.1, “REX Prefixes” for additional information.
2. For VEX encoding information, see Section 2.3, “Intel® Advanced Vector Extensions (Intel®
AVX)”.
3. Some rare instructions can take an 8B immediate or 8B displacement.
Figure 2-1. Intel 64 and IA-32 Architectures Instruction Format
2.1.1
Instruction Prefixes
Instruction prefixes are divided into four groups, each with a set of allowable prefix codes. For each instruction, it
is only useful to include up to one prefix code from each of the four groups (Groups 1, 2, 3, 4). Groups 1 through 4
may be placed in any order relative to each other.
•
Group 1
— Lock and repeat prefixes:
•
•
•
LOCK prefix is encoded using F0H.
REPNE/REPNZ prefix is encoded using F2H. Repeat-Not-Zero prefix applies only to string and
input/output instructions. (F2H is also used as a mandatory prefix for some instructions.)
REP or REPE/REPZ is encoded using F3H. The repeat prefix applies only to string and input/output
instructions. F3H is also used as a mandatory prefix for POPCNT, LZCNT and ADOX instructions.
— Bound prefix is encoded using F2H if the following conditions are true:
•
CPUID.(EAX=07H, ECX=0):EBX.MPX[bit 14] is set.
Vol. 2A 2-1
INSTRUCTION FORMAT
•
•
•
BNDCFGU.EN and/or IA32_BNDCFGS.EN is set.
When the F2 prefix precedes a near CALL, a near RET, a near JMP, or a near Jcc instruction (see Chapter
17, “Intel® MPX,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
Group 2
— Segment override prefixes:
•
•
•
•
•
•
2EH—CS segment override (use with any branch instruction is reserved).
36H—SS segment override prefix (use with any branch instruction is reserved).
3EH—DS segment override prefix (use with any branch instruction is reserved).
26H—ES segment override prefix (use with any branch instruction is reserved).
64H—FS segment override prefix (use with any branch instruction is reserved).
65H—GS segment override prefix (use with any branch instruction is reserved).
— Branch hints1:
•
•
•
3EH—Branch taken (used only with Jcc instructions).
Group 3
•
•
2EH—Branch not taken (used only with Jcc instructions).
Operand-size override prefix is encoded using 66H (66H is also used as a mandatory prefix for some
instructions).
Group 4
•
67H—Address-size override prefix.
The LOCK prefix (F0H) forces an operation that ensures exclusive use of shared memory in a multiprocessor environment. See “LOCK—Assert LOCK# Signal Prefix” in Chapter 3, “Instruction Set Reference, A-L,” for a description
of this prefix.
Repeat prefixes (F2H, F3H) cause an instruction to be repeated for each element of a string. Use these prefixes
only with string and I/O instructions (MOVS, CMPS, SCAS, LODS, STOS, INS, and OUTS). Use of repeat prefixes
and/or undefined opcodes with other Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable
behavior.
Some instructions may use F2H,F3H as a mandatory prefix to express distinct functionality.
Branch hint prefixes (2EH, 3EH) allow a program to give a hint to the processor about the most likely code path for
a branch. Use these prefixes only with conditional branch instructions (Jcc). Other use of branch hint prefixes
and/or other undefined opcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable
behavior.
The operand-size override prefix allows a program to switch between 16- and 32-bit operand sizes. Either size can
be the default; use of the prefix selects the non-default size.
Some SSE2/SSE3/SSSE3/SSE4 instructions and instructions using a three-byte sequence of primary opcode bytes
may use 66H as a mandatory prefix to express distinct functionality.
Other use of the 66H prefix is reserved; such use may cause unpredictable behavior.
The address-size override prefix (67H) allows programs to switch between 16- and 32-bit addressing. Either size
can be the default; the prefix selects the non-default size. Using this prefix and/or other undefined opcodes when
operands for the instruction do not reside in memory is reserved; such use may cause unpredictable behavior.
1. Some earlier microarchitectures used these as branch hints, but recent generations have not and they are reserved for future hint
usage.
2-2 Vol. 2A
INSTRUCTION FORMAT
2.1.2
Opcodes
A primary opcode can be 1, 2, or 3 bytes in length. An additional 3-bit opcode field is sometimes encoded in the
ModR/M byte. Smaller fields can be defined within the primary opcode. Such fields define the direction of operation, size of displacements, register encoding, condition codes, or sign extension. Encoding fields used by an
opcode vary depending on the class of operation.
Two-byte opcode formats for general-purpose and SIMD instructions consist of one of the following:
•
•
An escape opcode byte 0FH as the primary opcode and a second opcode byte.
A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, and a second opcode byte (same as previous
bullet).
For example, CVTDQ2PD consists of the following sequence: F3 0F E6. The first byte is a mandatory prefix (it is not
considered as a repeat prefix).
Three-byte opcode formats for general-purpose and SIMD instructions consist of one of the following:
•
•
An escape opcode byte 0FH as the primary opcode, plus two additional opcode bytes.
A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, plus two additional opcode bytes (same as
previous bullet).
For example, PHADDW for XMM registers consists of the following sequence: 66 0F 38 01. The first byte is the
mandatory prefix.
Valid opcode expressions are defined in Appendix A and Appendix B.
2.1.3
ModR/M and SIB Bytes
Many instructions that refer to an operand in memory have an addressing-form specifier byte (called the ModR/M
byte) following the primary opcode. The ModR/M byte contains three fields of information:
•
•
The mod field combines with the r/m field to form 32 possible values: eight registers and 24 addressing modes.
•
The r/m field can specify a register as an operand or it can be combined with the mod field to encode an
addressing mode. Sometimes, certain combinations of the mod field and the r/m field are used to express
opcode information for some instructions.
The reg/opcode field specifies either a register number or three more bits of opcode information. The purpose
of the reg/opcode field is specified in the primary opcode.
Certain encodings of the ModR/M byte require a second addressing byte (the SIB byte). The base-plus-index and
scale-plus-index forms of 32-bit addressing require the SIB byte. The SIB byte includes the following fields:
•
•
•
The scale field specifies the scale factor.
The index field specifies the register number of the index register.
The base field specifies the register number of the base register.
See Section 2.1.5 for the encodings of the ModR/M and SIB bytes.
2.1.4
Displacement and Immediate Bytes
Some addressing forms include a displacement immediately following the ModR/M byte (or the SIB byte if one is
present). If a displacement is required, it can be 1, 2, or 4 bytes.
If an instruction specifies an immediate operand, the operand always follows any displacement bytes. An immediate operand can be 1, 2 or 4 bytes.
Vol. 2A 2-3
INSTRUCTION FORMAT
2.1.5
Addressing-Mode Encoding of ModR/M and SIB Bytes
The values and corresponding addressing forms of the ModR/M and SIB bytes are shown in Table 2-1 through Table
2-3: 16-bit addressing forms specified by the ModR/M byte are in Table 2-1 and 32-bit addressing forms are in
Table 2-2. Table 2-3 shows 32-bit addressing forms specified by the SIB byte. In cases where the reg/opcode field
in the ModR/M byte represents an extended opcode, valid encodings are shown in Appendix B.
In Table 2-1 and Table 2-2, the Effective Address column lists 32 effective addresses that can be assigned to the
first operand of an instruction by using the Mod and R/M fields of the ModR/M byte. The first 24 options provide
ways of specifying a memory location; the last eight (Mod = 11B) provide ways of specifying general-purpose, MMX
technology and XMM registers.
The Mod and R/M columns in Table 2-1 and Table 2-2 give the binary encodings of the Mod and R/M fields required
to obtain the effective address listed in the first column. For example: see the row indicated by Mod = 11B, R/M =
000B. The row identifies the general-purpose registers EAX, AX or AL; MMX technology register MM0; or XMM
register XMM0. The register used is determined by the opcode byte and the operand-size attribute.
Now look at the seventh row in either table (labeled “REG =”). This row specifies the use of the 3-bit Reg/Opcode
field when the field is used to give the location of a second operand. The second operand must be a generalpurpose, MMX technology, or XMM register. Rows one through five list the registers that may correspond to the
value in the table. Again, the register used is determined by the opcode byte along with the operand-size attribute.
If the instruction does not require a second operand, then the Reg/Opcode field may be used as an opcode extension. This use is represented by the sixth row in the tables (labeled “/digit (Opcode)”). Note that values in row six
are represented in decimal form.
The body of Table 2-1 and Table 2-2 (under the label “Value of ModR/M Byte (in Hexadecimal)”) contains a 32 by
8 array that presents all of 256 values of the ModR/M byte (in hexadecimal). Bits 3, 4 and 5 are specified by the
column of the table in which a byte resides. The row specifies bits 0, 1 and 2; and bits 6 and 7. The figure below
demonstrates interpretation of one table value.
Mod 11
RM
000
/digit (Opcode); REG =
001
C8H 11001000
Figure 2-2. Table Interpretation of ModR/M Byte (C8H)
2-4 Vol. 2A
INSTRUCTION FORMAT
Table 2-1. 16-Bit Addressing Forms with the ModR/M Byte
r8(/r)
r16(/r)
r32(/r)
mm(/r)
xmm(/r)
(In decimal) /digit (Opcode)
(In binary) REG =
Effective Address
AL
AX
EAX
MM0
XMM0
0
000
Mod
CL
CX
ECX
MM1
XMM1
1
001
R/M
DL
DX
EDX
MM2
XMM2
2
010
BL
BX
EBX
MM3
XMM3
3
011
AH
SP
ESP
MM4
XMM4
4
100
CH
BP1
EBP
MM5
XMM5
5
101
DH
SI
ESI
MM6
XMM6
6
110
BH
DI
EDI
MM7
XMM7
7
111
Value of ModR/M Byte (in Hexadecimal)
[BX+SI]
[BX+DI]
[BP+SI]
[BP+DI]
[SI]
[DI]
disp162
[BX]
00
000
001
010
011
100
101
110
111
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
[BX+SI]+disp83
[BX+DI]+disp8
[BP+SI]+disp8
[BP+DI]+disp8
[SI]+disp8
[DI]+disp8
[BP]+disp8
[BX]+disp8
01
000
001
010
011
100
101
110
111
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
[BX+SI]+disp16
[BX+DI]+disp16
[BP+SI]+disp16
[BP+DI]+disp16
[SI]+disp16
[DI]+disp16
[BP]+disp16
[BX]+disp16
10
000
001
010
011
100
101
110
111
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
EAX/AX/AL/MM0/XMM0
ECX/CX/CL/MM1/XMM1
EDX/DX/DL/MM2/XMM2
EBX/BX/BL/MM3/XMM3
ESP/SP/AHMM4/XMM4
EBP/BP/CH/MM5/XMM5
ESI/SI/DH/MM6/XMM6
EDI/DI/BH/MM7/XMM7
11
000
001
010
011
100
101
110
111
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
EQ
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
NOTES:
1. The default segment register is SS for the effective addresses containing a BP index, DS for other effective addresses.
2. The disp16 nomenclature denotes a 16-bit displacement that follows the ModR/M byte and that is added to the index.
3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte and that is sign-extended and added to the
index.
Vol. 2A 2-5
INSTRUCTION FORMAT
Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte
r8(/r)
r16(/r)
r32(/r)
mm(/r)
xmm(/r)
(In decimal) /digit (Opcode)
(In binary) REG =
Effective Address
AL
AX
EAX
MM0
XMM0
0
000
Mod
CL
CX
ECX
MM1
XMM1
1
001
R/M
DL
DX
EDX
MM2
XMM2
2
010
BL
BX
EBX
MM3
XMM3
3
011
AH
SP
ESP
MM4
XMM4
4
100
CH
BP
EBP
MM5
XMM5
5
101
DH
SI
ESI
MM6
XMM6
6
110
BH
DI
EDI
MM7
XMM7
7
111
Value of ModR/M Byte (in Hexadecimal)
[EAX]
[ECX]
[EDX]
[EBX]
[--][--]1
disp322
[ESI]
[EDI]
00
000
001
010
011
100
101
110
111
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
[EAX]+disp83
[ECX]+disp8
[EDX]+disp8
[EBX]+disp8
[--][--]+disp8
[EBP]+disp8
[ESI]+disp8
[EDI]+disp8
01
000
001
010
011
100
101
110
111
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
[EAX]+disp32
[ECX]+disp32
[EDX]+disp32
[EBX]+disp32
[--][--]+disp32
[EBP]+disp32
[ESI]+disp32
[EDI]+disp32
10
000
001
010
011
100
101
110
111
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
EAX/AX/AL/MM0/XMM0
ECX/CX/CL/MM/XMM1
EDX/DX/DL/MM2/XMM2
EBX/BX/BL/MM3/XMM3
ESP/SP/AH/MM4/XMM4
EBP/BP/CH/MM5/XMM5
ESI/SI/DH/MM6/XMM6
EDI/DI/BH/MM7/XMM7
11
000
001
010
011
100
101
110
111
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
NOTES:
1. The [--][--] nomenclature means a SIB follows the ModR/M byte.
2. The disp32 nomenclature denotes a 32-bit displacement that follows the ModR/M byte (or the SIB byte if one is present) and that is
added to the index.
3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte (or the SIB byte if one is present) and that is
sign-extended and added to the index.
Table 2-3 is organized to give 256 possible values of the SIB byte (in hexadecimal). General purpose registers used
as a base are indicated across the top of the table, along with corresponding values for the SIB byte’s base field.
Table rows in the body of the table indicate the register used as the index (SIB byte bits 3, 4 and 5) and the scaling
factor (determined by SIB byte bits 6 and 7).
2-6 Vol. 2A
INSTRUCTION FORMAT
Table 2-3. 32-Bit Addressing Forms with the SIB Byte
r32
(In decimal) Base =
(In binary) Base =
EAX
0
000
Scaled Index
SS
ECX
1
001
Index
EDX
2
010
EBX
3
011
ESP
4
100
[*]
5
101
ESI
6
110
EDI
7
111
Value of SIB Byte (in Hexadecimal)
[EAX]
[ECX]
[EDX]
[EBX]
none
[EBP]
[ESI]
[EDI]
00
000
001
010
011
100
101
110
111
00
08
10
18
20
28
30
38
01
09
11
19
21
29
31
39
02
0A
12
1A
22
2A
32
3A
03
0B
13
1B
23
2B
33
3B
04
0C
14
1C
24
2C
34
3C
05
0D
15
1D
25
2D
35
3D
06
0E
16
1E
26
2E
36
3E
07
0F
17
1F
27
2F
37
3F
[EAX*2]
[ECX*2]
[EDX*2]
[EBX*2]
none
[EBP*2]
[ESI*2]
[EDI*2]
01
000
001
010
011
100
101
110
111
40
48
50
58
60
68
70
78
41
49
51
59
61
69
71
79
42
4A
52
5A
62
6A
72
7A
43
4B
53
5B
63
6B
73
7B
44
4C
54
5C
64
6C
74
7C
45
4D
55
5D
65
6D
75
7D
46
4E
56
5E
66
6E
76
7E
47
4F
57
5F
67
6F
77
7F
[EAX*4]
[ECX*4]
[EDX*4]
[EBX*4]
none
[EBP*4]
[ESI*4]
[EDI*4]
10
000
001
010
011
100
101
110
111
80
88
90
98
A0
A8
B0
B8
81
89
91
99
A1
A9
B1
B9
82
8A
92
9A
A2
AA
B2
BA
83
8B
93
9B
A3
AB
B3
BB
84
8C
94
9C
A4
AC
B4
BC
85
8D
95
9D
A5
AD
B5
BD
86
8E
96
9E
A6
AE
B6
BE
87
8F
97
9F
A7
AF
B7
BF
[EAX*8]
[ECX*8]
[EDX*8]
[EBX*8]
none
[EBP*8]
[ESI*8]
[EDI*8]
11
000
001
010
011
100
101
110
111
C0
C8
D0
D8
E0
E8
F0
F8
C1
C9
D1
D9
E1
E9
F1
F9
C2
CA
D2
DA
E2
EA
F2
FA
C3
CB
D3
DB
E3
EB
F3
FB
C4
CC
D4
DC
E4
EC
F4
FC
C5
CD
D5
DD
E5
ED
F5
FD
C6
CE
D6
DE
E6
EE
F6
FE
C7
CF
D7
DF
E7
EF
F7
FF
NOTES:
1. The [*] nomenclature means a disp32 with no base if the MOD is 00B. Otherwise, [*] means disp8 or disp32 + [EBP]. This provides the
following address modes:
MOD bits Effective Address
00
[scaled index] + disp32
01
[scaled index] + disp8 + [EBP]
10
[scaled index] + disp32 + [EBP]
2.2
IA-32E MODE
IA-32e mode has two sub-modes. These are:
•
Compatibility Mode. Enables a 64-bit operating system to run most legacy protected mode software
unmodified.
•
64-Bit Mode. Enables a 64-bit operating system to run applications written to access 64-bit address space.
Vol. 2A 2-7
INSTRUCTION FORMAT
2.2.1
REX Prefixes
REX prefixes are instruction-prefix bytes used in 64-bit mode. They do the following:
•
•
•
Specify GPRs and SSE registers.
Specify 64-bit operand size.
Specify extended control registers.
Not all instructions require a REX prefix in 64-bit mode. A prefix is necessary only if an instruction references one
of the extended registers or uses a 64-bit operand. If a REX prefix is used when it has no meaning, it is ignored.
Only one REX prefix is allowed per instruction. If used, the REX prefix byte must immediately precede the opcode
byte or the escape opcode byte (0FH). When a REX prefix is used in conjunction with an instruction containing a
mandatory prefix, the mandatory prefix must come before the REX so the REX prefix can be immediately preceding
the opcode or the escape byte. For example, CVTDQ2PD with a REX prefix should have REX placed between F3 and
0F E6. Other placements are ignored. The instruction-size limit of 15 bytes still applies to instructions with a REX
prefix. See Figure 2-3.
Legacy
Prefixes
REX
Prefix
Grp 1, Grp
2, Grp 3,
Grp 4
(optional)
(optional)
Opcode
ModR/M
1-, 2-, or
3-byte
opcode
1 byte
(if required)
SIB
1 byte
(if required)
Displacement
Address
displacement of
1, 2, or 4 bytes
Immediate
Immediate data
of 1, 2, or 4
bytes or none
Figure 2-3. Prefix Ordering in 64-bit Mode
2.2.1.1
Encoding
Intel 64 and IA-32 instruction formats specify up to three registers by using 3-bit fields in the encoding, depending
on the format:
•
•
ModR/M: the reg and r/m fields of the ModR/M byte.
•
Instructions without ModR/M: the reg field of the opcode.
ModR/M with SIB: the reg field of the ModR/M byte, the base and index fields of the SIB (scale, index, base)
byte.
In 64-bit mode, these formats do not change. Bits needed to define fields in the 64-bit context are provided by the
addition of REX prefixes.
2.2.1.2
More on REX Prefix Fields
REX prefixes are a set of 16 opcodes that span one row of the opcode map and occupy entries 40H to 4FH. These
opcodes represent valid instructions (INC or DEC) in IA-32 operating modes and in compatibility mode. In 64-bit
mode, the same opcodes represent the instruction prefix REX and are not treated as individual instructions.
The single-byte-opcode forms of the INC/DEC instructions are not available in 64-bit mode. INC/DEC functionality
is still available using ModR/M forms of the same instructions (opcodes FF/0 and FF/1).
See Table 2-4 for a summary of the REX prefix format. Figure 2-4 though Figure 2-7 show examples of REX prefix
fields in use. Some combinations of REX prefix fields are invalid. In such cases, the prefix is ignored. Some additional information follows:
•
Setting REX.W can be used to determine the operand size but does not solely determine operand width. Like
the 66H size prefix, 64-bit operand size override has no effect on byte-specific operations.
•
•
For non-byte operations: if a 66H prefix is used with prefix (REX.W = 1), 66H is ignored.
If a 66H override is used with REX and REX.W = 0, the operand size is 16 bits.
2-8 Vol. 2A
INSTRUCTION FORMAT
•
REX.R modifies the ModR/M reg field when that field encodes a GPR, SSE, control or debug register. REX.R is
ignored when ModR/M specifies other registers or defines an extended opcode.
•
•
REX.X bit modifies the SIB index field.
REX.B either modifies the base in the ModR/M r/m field or SIB base field; or it modifies the opcode reg field
used for accessing GPRs.
Table 2-4. REX Prefix Fields [BITS: 0100WRXB]
Field Name
Bit Position
Definition
-
7:4
0100
W
3
0 = Operand size determined by CS.D
1 = 64 Bit Operand Size
R
2
Extension of the ModR/M reg field
X
1
Extension of the SIB index field
B
0
Extension of the ModR/M r/m field, SIB base field, or Opcode reg field
ModRM Byte
REX PREFIX
Opcode
mod
≠11
0100WR0B
reg
rrr
r/m
bbb
Rrrr
Bbbb
OM17Xfig1-3
Figure 2-4. Memory Addressing Without an SIB Byte; REX.X Not Used
ModRM Byte
REX PREFIX
0100WR0B
Opcode
mod
11
reg
rrr
Rrrr
r/m
bbb
Bbbb
OM17Xfig1-4
Figure 2-5. Register-Register Addressing (No Memory Operand); REX.X Not Used
Vol. 2A 2-9
INSTRUCTION FORMAT
ModRM Byte
REX PREFIX
Opcode
mod
≠ 11
0100WRXB
reg
rrr
SIB Byte
r/m
100
index
xxx
scale
ss
Rrrr
Xxxx
base
bbb
Bbbb
OM17Xfig1-5
Figure 2-6. Memory Addressing With a SIB Byte
REX PREFIX
0100W00B
Opcode
reg
bbb
Bbbb
OM17Xfig1-6
Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used
In the IA-32 architecture, byte registers (AH, AL, BH, BL, CH, CL, DH, and DL) are encoded in the ModR/M byte’s
reg field, the r/m field or the opcode reg field as registers 0 through 7. REX prefixes provide an additional
addressing capability for byte-registers that makes the least-significant byte of GPRs available for byte operations.
Certain combinations of the fields of the ModR/M byte and the SIB byte have special meaning for register encodings. For some combinations, fields expanded by the REX prefix are not decoded. Table 2-5 describes how each
case behaves.
2-10 Vol. 2A
INSTRUCTION FORMAT
Table 2-5. Special Cases of REX Encodings
ModR/M or
SIB
Sub-field
Encodings
ModR/M Byte mod ≠ 11
Compatibility Mode
Operation
Compatibility Mode
Implications
SIB byte present.
SIB byte required for REX prefix adds a fourth bit (b) which is not decoded
ESP-based addressing. (don't care).
r/m =
b*100(ESP)
ModR/M Byte mod = 0
r/m =
b*101(EBP)
Additional Implications
SIB byte also required for R12-based addressing.
Base register not
used.
EBP without a
REX prefix adds a fourth bit (b) which is not decoded
displacement must be (don't care).
done using
Using RBP or R13 without displacement must be done
mod = 01 with
using mod = 01 with a displacement of 0.
displacement of 0.
SIB Byte
index =
0100(ESP)
Index register not
used.
ESP cannot be used as REX prefix adds a fourth bit (b) which is decoded.
an index register.
There are no additional implications. The expanded
index field allows distinguishing RSP from R12,
therefore R12 can be used as an index.
SIB Byte
base =
0101(EBP)
Base register is
unused if mod = 0.
Base register depends REX prefix adds a fourth bit (b) which is not decoded.
on mod encoding.
This requires explicit displacement to be used with
EBP/RBP or R13.
NOTES:
* Don’t care about value of REX.B
2.2.1.3
Displacement
Addressing in 64-bit mode uses existing 32-bit ModR/M and SIB encodings. The ModR/M and SIB displacement
sizes do not change. They remain 8 bits or 32 bits and are sign-extended to 64 bits.
2.2.1.4
Direct Memory-Offset MOVs
In 64-bit mode, direct memory-offset forms of the MOV instruction are extended to specify a 64-bit immediate
absolute address. This address is called a moffset. No prefix is needed to specify this 64-bit memory offset. For
these MOV instructions, the size of the memory offset follows the address-size default (64 bits in 64-bit mode). See
Table 2-6.
Table 2-6. Direct Memory Offset Form of MOV
Opcode
Instruction
A0
MOV AL, moffset
A1
MOV EAX, moffset
A2
MOV moffset, AL
A3
MOV moffset, EAX
2.2.1.5
Immediates
In 64-bit mode, the typical size of immediate operands remains 32 bits. When the operand size is 64 bits, the
processor sign-extends all immediates to 64 bits prior to their use.
Support for 64-bit immediate operands is accomplished by expanding the semantics of the existing move (MOV
reg, imm16/32) instructions. These instructions (opcodes B8H – BFH) move 16-bits or 32-bits of immediate data
(depending on the effective operand size) into a GPR. When the effective operand size is 64 bits, these instructions
can be used to load an immediate into a GPR. A REX prefix is needed to override the 32-bit default operand size to
a 64-bit operand size.
For example:
48 B8 8877665544332211 MOV RAX,1122334455667788H
Vol. 2A 2-11
INSTRUCTION FORMAT
2.2.1.6
RIP-Relative Addressing
A new addressing form, RIP-relative (relative instruction-pointer) addressing, is implemented in 64-bit mode. An
effective address is formed by adding displacement to the 64-bit RIP of the next instruction.
In IA-32 architecture and compatibility mode, addressing relative to the instruction pointer is available only with
control-transfer instructions. In 64-bit mode, instructions that use ModR/M addressing can use RIP-relative
addressing. Without RIP-relative addressing, all ModR/M modes address memory relative to zero.
RIP-relative addressing allows specific ModR/M modes to address memory relative to the 64-bit RIP using a signed
32-bit displacement. This provides an offset range of ±2GB from the RIP. Table 2-7 shows the ModR/M and SIB
encodings for RIP-relative addressing. Redundant forms of 32-bit displacement-addressing exist in the current
ModR/M and SIB encodings. There is one ModR/M encoding and there are several SIB encodings. RIP-relative
addressing is encoded using a redundant form.
In 64-bit mode, the ModR/M Disp32 (32-bit displacement) encoding is re-defined to be RIP+Disp32 rather than
displacement-only. See Table 2-7.
Table 2-7. RIP-Relative Addressing
ModR/M and SIB Sub-field Encodings Compatibility Mode
Operation
64-bit Mode
Operation
Additional Implications in 64-bit mode
ModR/M Byte
Disp32
RIP + Disp32
Must use SIB form with normal (zero-based)
displacement addressing
if mod = 00, Disp32
Same as legacy
None
mod = 00
r/m = 101 (none)
SIB Byte
base = 101 (none)
index = 100 (none)
scale = 0, 1, 2, 4
The ModR/M encoding for RIP-relative addressing does not depend on using a prefix. Specifically, the r/m bit field
encoding of 101B (used to select RIP-relative addressing) is not affected by the REX prefix. For example, selecting
R13 (REX.B = 1, r/m = 101B) with mod = 00B still results in RIP-relative addressing. The 4-bit r/m field of REX.B
combined with ModR/M is not fully decoded. In order to address R13 with no displacement, software must encode
R13 + 0 using a 1-byte displacement of zero.
RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. The use of the address-size prefix
does not disable RIP-relative addressing. The effect of the address-size prefix is to truncate and zero-extend the
computed effective address to 32 bits.
2.2.1.7
Default 64-Bit Operand Size
In 64-bit mode, two groups of instructions have a default operand size of 64 bits (do not need a REX prefix for this
operand size). These are:
•
•
Near branches.
All instructions, except far branches, that implicitly reference the RSP.
2.2.2
Additional Encodings for Control and Debug Registers
In 64-bit mode, more encodings for control and debug registers are available. The REX.R bit is used to modify the
ModR/M reg field when that field encodes a control or debug register (see Table 2-4). These encodings enable the
processor to address CR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bit mode. CR8
becomes the Task Priority Register (TPR).
In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not implemented. Any attempt to access
unimplemented registers results in an invalid-opcode exception (#UD).
2-12 Vol. 2A
INSTRUCTION FORMAT
2.3
INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)
Intel AVX instructions are encoded using an encoding scheme that combines prefix bytes, opcode extension field,
operand encoding fields, and vector length encoding capability into a new prefix, referred to as VEX. In the VEX
encoding scheme, the VEX prefix may be two or three bytes long, depending on the instruction semantics. Despite
the two-byte or three-byte length of the VEX prefix, the VEX encoding format provides a more compact representation/packing of the components of encoding an instruction in Intel 64 architecture. The VEX encoding scheme
also allows more headroom for future growth of Intel 64 architecture.
2.3.1
Instruction Format
Instruction encoding using VEX prefix provides several advantages:
•
Instruction syntax support for three operands and up-to four operands when necessary. For example, the third
source register used by VBLENDVPD is encoded using bits 7:4 of the immediate byte.
•
•
•
Encoding support for vector length of 128 bits (using XMM registers) and 256 bits (using YMM registers).
Encoding support for instruction syntax of non-destructive source operands.
Elimination of escape opcode byte (0FH), SIMD prefix byte (66H, F2H, F3H) via a compact bit field representation within the VEX prefix.
•
Elimination of the need to use REX prefix to encode the extended half of general-purpose register sets (R8R15) for direct register access, memory addressing, or accessing XMM8-XMM15 (including YMM8-YMM15).
•
Flexible and more compact bit fields are provided in the VEX prefix to retain the full functionality provided by
REX prefix. REX.W, REX.X, REX.B functionalities are provided in the three-byte VEX prefix only because only a
subset of SIMD instructions need them.
•
Extensibility for future instruction extensions without significant instruction length increase.
Figure 2-8 shows the Intel 64 instruction encoding format with VEX prefix support. Legacy instruction without a
VEX prefix is fully supported and unchanged. The use of VEX prefix in an Intel 64 instruction is optional, but a VEX
prefix is required for Intel 64 instructions that operate on YMM registers or support three and four operand syntax.
VEX prefix is not a constant-valued, “single-purpose” byte like 0FH, 66H, F2H, F3H in legacy SSE instructions. VEX
prefix provides substantially richer capability than the REX prefix.
# Bytes
[Prefixes]
2,3
[VEX]
1
OPCODE
1
0,1
ModR/M
[SIB]
0,1,2,4
[DISP]
0,1
[IMM]
Figure 2-8. Instruction Encoding Format with VEX Prefix
2.3.2
VEX and the LOCK prefix
Any VEX-encoded instruction with a LOCK prefix preceding VEX will #UD.
2.3.3
VEX and the 66H, F2H, and F3H prefixes
Any VEX-encoded instruction with a 66H, F2H, or F3H prefix preceding VEX will #UD.
2.3.4
VEX and the REX prefix
Any VEX-encoded instruction with a REX prefix proceeding VEX will #UD.
Vol. 2A 2-13
INSTRUCTION FORMAT
2.3.5
The VEX Prefix
The VEX prefix is encoded in either the two-byte form (the first byte must be C5H) or in the three-byte form (the
first byte must be C4H). The two-byte VEX is used mainly for 128-bit, scalar, and the most common 256-bit AVX
instructions; while the three-byte VEX provides a compact replacement of REX and 3-byte opcode instructions
(including AVX and FMA instructions). Beyond the first byte of the VEX prefix, it consists of a number of bit fields
providing specific capability, they are shown in Figure 2-9.
The bit fields of the VEX prefix can be summarized by its functional purposes:
•
Non-destructive source register encoding (applicable to three and four operand syntax): This is the first source
operand in the instruction syntax. It is represented by the notation, VEX.vvvv. This field is encoded using 1’s
complement form (inverted form), i.e. XMM0/YMM0/R0 is encoded as 1111B, XMM15/YMM15/R15 is encoded
as 0000B.
•
Vector length encoding: This 1-bit field represented by the notation VEX.L. L= 0 means vector length is 128 bits
wide, L=1 means 256 bit vector. The value of this field is written as VEX.128 or VEX.256 in this document to
distinguish encoded values of other VEX bit fields.
•
REX prefix functionality: Full REX prefix functionality is provided in the three-byte form of VEX prefix. However
the VEX bit fields providing REX functionality are encoded using 1’s complement form, i.e. XMM0/YMM0/R0 is
encoded as 1111B, XMM15/YMM15/R15 is encoded as 0000B.
— Two-byte form of the VEX prefix only provides the equivalent functionality of REX.R, using 1’s complement
encoding. This is represented as VEX.R.
— Three-byte form of the VEX prefix provides REX.R, REX.X, REX.B functionality using 1’s complement
encoding and three dedicated bit fields represented as VEX.R, VEX.X, VEX.B.
— Three-byte form of the VEX prefix provides the functionality of REX.W only to specific instructions that need
to override default 32-bit operand size for a general purpose register to 64-bit size in 64-bit mode. For
those applicable instructions, VEX.W field provides the same functionality as REX.W. VEX.W field can
provide completely different functionality for other instructions.
Consequently, the use of REX prefix with VEX encoded instructions is not allowed. However, the intent of the
REX prefix for expanding register set is reserved for future instruction set extensions using VEX prefix
encoding format.
•
Compaction of SIMD prefix: Legacy SSE instructions effectively use SIMD prefixes (66H, F2H, F3H) as an
opcode extension field. VEX prefix encoding allows the functional capability of such legacy SSE instructions
(operating on XMM registers, bits 255:128 of corresponding YMM unmodified) to be encoded using the VEX.pp
field without the presence of any SIMD prefix. The VEX-encoded 128-bit instruction will zero-out bits 255:128
of the destination register. VEX-encoded instruction may have 128 bit vector length or 256 bits length.
•
Compaction of two-byte and three-byte opcode: More recently introduced legacy SSE instructions employ two
and three-byte opcode. The one or two leading bytes are: 0FH, and 0FH 3AH/0FH 38H. The one-byte escape
(0FH) and two-byte escape (0FH 3AH, 0FH 38H) can also be interpreted as an opcode extension field. The
VEX.mmmmm field provides compaction to allow many legacy instruction to be encoded without the constant
byte sequence, 0FH, 0FH 3AH, 0FH 38H. These VEX-encoded instruction may have 128 bit vector length or 256
bits length.
The VEX prefix is required to be the last prefix and immediately precedes the opcode bytes. It must follow any
other prefixes. If VEX prefix is present a REX prefix is not supported.
The 3-byte VEX leaves room for future expansion with 3 reserved bits. REX and the 66h/F2h/F3h prefixes are
reclaimed for future use.
VEX prefix has a two-byte form and a three byte form. If an instruction syntax can be encoded using the two-byte
form, it can also be encoded using the three byte form of VEX. The latter increases the length of the instruction by
one byte. This may be helpful in some situations for code alignment.
The VEX prefix supports 256-bit versions of floating-point SSE, SSE2, SSE3, and SSE4 instructions. Note, certain
new instruction functionality can only be encoded with the VEX prefix.
The VEX prefix will #UD on any instruction containing MMX register sources or destinations.
2-14 Vol. 2A
INSTRUCTION FORMAT
3-byte VEX
0 7 6 5 4
11000100
7
2-byte VEX
Byte 2
Byte 1
Byte 0
(Bit Position) 7
0
11000101
0
RXB
m-mmmm
7
3
R
6
vvvv
1
7
W
6
3
vvvv
1
2 1 0
L pp
2 1 0
L
pp
R: REX.R in 1’s complement (inverted) form
1: Same as REX.R=0 (must be 1 in 32-bit mode)
0: Same as REX.R=1 (64-bit mode only)
X: REX.X in 1’s complement (inverted) form
1: Same as REX.X=0 (must be 1 in 32-bit mode)
0: Same as REX.X=1 (64-bit mode only)
B: REX.B in 1’s complement (inverted) form
1: Same as REX.B=0 (Ignored in 32-bit mode).
0: Same as REX.B=1 (64-bit mode only)
W: opcode specific (use like REX.W, or used for opcode
extension, or ignored, depending on the opcode byte)
m-mmmm:
00000: Reserved for future use (will #UD)
00001: implied 0F leading opcode byte
00010: implied 0F 38 leading opcode bytes
00011: implied 0F 3A leading opcode bytes
00100-11111: Reserved for future use (will #UD)
vvvv: a register specifier (in 1’s complement form) or 1111 if unused.
L: Vector Length
0: scalar or 128-bit vector
1: 256-bit vector
pp: opcode extension providing equivalent functionality of a SIMD prefix
00: None
01: 66
10: F3
11: F2
Figure 2-9. VEX bit fields
The following subsections describe the various fields in two or three-byte VEX prefix.
2.3.5.1
VEX Byte 0, bits[7:0]
VEX Byte 0, bits [7:0] must contain the value 11000101b (C5h) or 11000100b (C4h). The 3-byte VEX uses the C4h
first byte, while the 2-byte VEX uses the C5h first byte.
2.3.5.2
VEX Byte 1, bit [7] - ‘R’
VEX Byte 1, bit [7] contains a bit analogous to a bit inverted REX.R. In protected and compatibility modes the bit
must be set to ‘1’ otherwise the instruction is LES or LDS.
Vol. 2A 2-15
INSTRUCTION FORMAT
This bit is present in both 2- and 3-byte VEX prefixes.
The usage of WRXB bits for legacy instructions is explained in detail section 2.2.1.2 of Intel 64 and IA-32 Architectures Software developer’s manual, Volume 2A.
This bit is stored in bit inverted format.
2.3.5.3
3-byte VEX byte 1, bit[6] - ‘X’
Bit[6] of the 3-byte VEX byte 1 encodes a bit analogous to a bit inverted REX.X. It is an extension of the SIB Index
field in 64-bit modes. In 32-bit modes, this bit must be set to ‘1’ otherwise the instruction is LES or LDS.
This bit is available only in the 3-byte VEX prefix.
This bit is stored in bit inverted format.
2.3.5.4
3-byte VEX byte 1, bit[5] - ‘B’
Bit[5] of the 3-byte VEX byte 1 encodes a bit analogous to a bit inverted REX.B. In 64-bit modes, it is an extension
of the ModR/M r/m field, or the SIB base field. In 32-bit modes, this bit is ignored.
This bit is available only in the 3-byte VEX prefix.
This bit is stored in bit inverted format.
2.3.5.5
3-byte VEX byte 2, bit[7] - ‘W’
Bit[7] of the 3-byte VEX byte 2 is represented by the notation VEX.W. It can provide following functions, depending
on the specific opcode.
• For AVX instructions that have equivalent legacy SSE instructions (typically these SSE instructions have a
general-purpose register operand with its operand size attribute promotable by REX.W), if REX.W promotes
the operand size attribute of the general-purpose register operand in legacy SSE instruction, VEX.W has same
meaning in the corresponding AVX equivalent form. In 32-bit modes, VEX.W is silently ignored.
• For AVX instructions that have equivalent legacy SSE instructions (typically these SSE instructions have operands with their operand size attribute fixed and not promotable by REX.W), if REX.W is don’t care in legacy
SSE instruction, VEX.W is ignored in the corresponding AVX equivalent form irrespective of mode.
• For new AVX instructions where VEX.W has no defined function (typically these meant the combination of the
opcode byte and VEX.mmmmm did not have any equivalent SSE functions), VEX.W is reserved as zero and
setting to other than zero will cause instruction to #UD.
2.3.5.6
2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or Dest
Register Specifier
In 32-bit mode the VEX first byte C4 and C5 alias onto the LES and LDS instructions. To maintain compatibility with
existing programs the VEX 2nd byte, bits [7:6] must be 11b. To achieve this, the VEX payload bits are selected to
place only inverted, 64-bit valid fields (extended register selectors) in these upper bits.
The 2-byte VEX Byte 1, bits [6:3] and the 3-byte VEX, Byte 2, bits [6:3] encode a field (shorthand VEX.vvvv) that
for instructions with 2 or more source registers and an XMM or YMM or memory destination encodes the first source
register specifier stored in inverted (1’s complement) form.
VEX.vvvv is not used by the instructions with one source (except certain shifts, see below) or on instructions with
no XMM or YMM or memory destination. If an instruction does not use VEX.vvvv then it should be set to 1111b
otherwise instruction will #UD.
In 64-bit mode all 4 bits may be used. See Table 2-8 for the encoding of the XMM or YMM registers. In 32-bit and
16-bit modes bit 6 must be 1 (if bit 6 is not 1, the 2-byte VEX version will generate LDS instruction and the 3-byte
VEX version will ignore this bit).
2-16 Vol. 2A
INSTRUCTION FORMAT
Table 2-8. VEX.vvvv to register name mapping
VEX.vvvv
Dest Register
Valid in Legacy/Compatibility 32-bit modes?
1111B
XMM0/YMM0
Valid
1110B
XMM1/YMM1
Valid
1101B
XMM2/YMM2
Valid
1100B
XMM3/YMM3
Valid
1011B
XMM4/YMM4
Valid
1010B
XMM5/YMM5
Valid
1001B
XMM6/YMM6
Valid
1000B
XMM7/YMM7
Valid
0111B
XMM8/YMM8
Invalid
0110B
XMM9/YMM9
Invalid
0101B
XMM10/YMM10
Invalid
0100B
XMM11/YMM11
Invalid
0011B
XMM12/YMM12
Invalid
0010B
XMM13/YMM13
Invalid
0001B
XMM14/YMM14
Invalid
0000B
XMM15/YMM15
Invalid
The VEX.vvvv field is encoded in bit inverted format for accessing a register operand.
2.3.6
Instruction Operand Encoding and VEX.vvvv, ModR/M
VEX-encoded instructions support three-operand and four-operand instruction syntax. Some VEX-encoded
instructions have syntax with less than three operands, e.g. VEX-encoded pack shift instructions support one
source operand and one destination operand).
The roles of VEX.vvvv, reg field of ModR/M byte (ModR/M.reg), r/m field of ModR/M byte (ModR/M.r/m) with
respect to encoding destination and source operands vary with different type of instruction syntax.
The role of VEX.vvvv can be summarized to three situations:
•
VEX.vvvv encodes the first source register operand, specified in inverted (1’s complement) form and is valid for
instructions with 2 or more source operands.
•
VEX.vvvv encodes the destination register operand, specified in 1’s complement form for certain vector shifts.
The instructions where VEX.vvvv is used as a destination are listed in Table 2-9. The notation in the “Opcode”
column in Table 2-9 is described in detail in section 3.1.1.
•
VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b.
Table 2-9. Instructions with a VEX.vvvv destination
Opcode
Instruction mnemonic
VEX.NDD.128.66.0F 73 /7 ib
VPSLLDQ xmm1, xmm2, imm8
VEX.NDD.128.66.0F 73 /3 ib
VPSRLDQ xmm1, xmm2, imm8
VEX.NDD.128.66.0F 71 /2 ib
VPSRLW xmm1, xmm2, imm8
VEX.NDD.128.66.0F 72 /2 ib
VPSRLD xmm1, xmm2, imm8
VEX.NDD.128.66.0F 73 /2 ib
VPSRLQ xmm1, xmm2, imm8
VEX.NDD.128.66.0F 71 /4 ib
VPSRAW xmm1, xmm2, imm8
VEX.NDD.128.66.0F 72 /4 ib
VPSRAD xmm1, xmm2, imm8
VEX.NDD.128.66.0F 71 /6 ib
VPSLLW xmm1, xmm2, imm8
VEX.NDD.128.66.0F 72 /6 ib
VPSLLD xmm1, xmm2, imm8
VEX.NDD.128.66.0F 73 /6 ib
VPSLLQ xmm1, xmm2, imm8
Vol. 2A 2-17
INSTRUCTION FORMAT
The role of ModR/M.r/m field can be summarized to two situations:
•
•
ModR/M.r/m encodes the instruction operand that references a memory address.
For some instructions that do not support memory addressing semantics, ModR/M.r/m encodes either the
destination register operand or a source register operand.
The role of ModR/M.reg field can be summarized to two situations:
•
•
ModR/M.reg encodes either the destination register operand or a source register operand.
For some instructions, ModR/M.reg is treated as an opcode extension and not used to encode any instruction
operand.
For instruction syntax that support four operands, VEX.vvvv, ModR/M.r/m, ModR/M.reg encodes three of the four
operands. The role of bits 7:4 of the immediate byte serves the following situation:
•
Imm8[7:4] encodes the third source register operand.
2.3.6.1
3-byte VEX byte 1, bits[4:0] - “m-mmmm”
Bits[4:0] of the 3-byte VEX byte 1 encode an implied leading opcode byte (0F, 0F 38, or 0F 3A). Several bits are
reserved for future use and will #UD unless 0.
Table 2-10. VEX.m-mmmm interpretation
VEX.m-mmmm
Implied Leading Opcode Bytes
00000B
Reserved
00001B
0F
00010B
0F 38
00011B
0F 3A
00100-11111B
Reserved
(2-byte VEX)
0F
VEX.m-mmmm is only available on the 3-byte VEX. The 2-byte VEX implies a leading 0Fh opcode byte.
2.3.6.2
2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”
The vector length field, VEX.L, is encoded in bit[2] of either the second byte of 2-byte VEX, or the third byte of 3byte VEX. If “VEX.L = 1”, it indicates 256-bit vector operation. “VEX.L = 0” indicates scalar and 128-bit vector
operations.
The instruction VZEROUPPER is a special case that is encoded with VEX.L = 0, although its operation zero’s bits
255:128 of all YMM registers accessible in the current operating mode.
See the following table.
Table 2-11. VEX.L interpretation
2.3.6.3
VEX.L
Vector Length
0
128-bit (or 32/64-bit scalar)
1
256-bit
2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”
Up to one implied prefix is encoded by bits[1:0] of either the 2-byte VEX byte 1 or the 3-byte VEX byte 2. The prefix
behaves as if it was encoded prior to VEX, but after all other encoded prefixes.
See the following table.
2-18 Vol. 2A
INSTRUCTION FORMAT
Table 2-12. VEX.pp interpretation
2.3.7
pp
Implies this prefix after other prefixes but before VEX
00B
None
01B
66
10B
F3
11B
F2
The Opcode Byte
One (and only one) opcode byte follows the 2 or 3 byte VEX. Legal opcodes are specified in Appendix B, in color.
Any instruction that uses illegal opcode will #UD.
2.3.8
The MODRM, SIB, and Displacement Bytes
The encodings are unchanged but the interpretation of reg_field or rm_field differs (see above).
2.3.9
The Third Source Operand (Immediate Byte)
VEX-encoded instructions can support instruction with a four operand syntax. VBLENDVPD, VBLENDVPS, and
PBLENDVB use imm8[7:4] to encode one of the source registers.
2.3.10
AVX Instructions and the Upper 128-bits of YMM registers
If an instruction with a destination XMM register is encoded with a VEX prefix, the processor zeroes the upper bits
(above bit 128) of the equivalent YMM register. Legacy SSE instructions without VEX preserve the upper bits.
2.3.10.1
Vector Length Transition and Programming Considerations
An instruction encoded with a VEX.128 prefix that loads a YMM register operand operates as follows:
•
•
Data is loaded into bits 127:0 of the register
Bits above bit 127 in the register are cleared.
Thus, such an instruction clears bits 255:128 of a destination YMM register on processors with a maximum vectorregister width of 256 bits. In the event that future processors extend the vector registers to greater widths, an
instruction encoded with a VEX.128 or VEX.256 prefix will also clear any bits beyond bit 255. (This is in contrast
with legacy SSE instructions, which have no VEX prefix; these modify only bits 127:0 of any destination register
operand.)
Programmers should bear in mind that instructions encoded with VEX.128 and VEX.256 prefixes will clear any
future extensions to the vector registers. A calling function that uses such extensions should save their state before
calling legacy functions. This is not possible for involuntary calls (e.g., into an interrupt-service routine). It is
recommended that software handling involuntary calls accommodate this by not executing instructions encoded
with VEX.128 and VEX.256 prefixes. In the event that it is not possible or desirable to restrict these instructions,
then software must take special care to avoid actions that would, on future processors, zero the upper bits of
vector registers.
Processors that support further vector-register extensions (defining bits beyond bit 255) will also extend the
XSAVE and XRSTOR instructions to save and restore these extensions. To ensure forward compatibility, software
that handles involuntary calls and that uses instructions encoded with VEX.128 and VEX.256 prefixes should first
save and then restore the vector registers (with any extensions) using the XSAVE and XRSTOR instructions with
save/restore masks that set bits that correspond to all vector-register extensions. Ideally, software should rely on
a mechanism that is cognizant of which bits to set. (E.g., an OS mechanism that sets the save/restore mask bits
for all vector-register extensions that are enabled in XCR0.) Saving and restoring state with instructions other than
XSAVE and XRSTOR will, on future processors with wider vector registers, corrupt the extended state of the vector
registers - even if doing so functions correctly on processors supporting 256-bit vector registers. (The same is true
Vol. 2A 2-19
INSTRUCTION FORMAT
if XSAVE and XRSTOR are used with a save/restore mask that does not set bits corresponding to all supported
extensions to the vector registers.)
2.3.11
AVX Instruction Length
The AVX instructions described in this document (including VEX and ignoring other prefixes) do not exceed 11
bytes in length, but may increase in the future. The maximum length of an Intel 64 and IA-32 instruction remains
15 bytes.
2.3.12
Vector SIB (VSIB) Memory Addressing
®
In Intel Advanced Vector Extensions 2 (Intel® AVX2), an SIB byte that follows the ModR/M byte can support VSIB
memory addressing to an array of linear addresses. VSIB addressing is only supported in a subset of Intel AVX2
instructions. VSIB memory addressing requires 32-bit or 64-bit effective address. In 32-bit mode, VSIB addressing
is not supported when address size attribute is overridden to 16 bits. In 16-bit protected mode, VSIB memory
addressing is permitted if address size attribute is overridden to 32 bits. Additionally, VSIB memory addressing is
supported only with VEX prefix.
In VSIB memory addressing, the SIB byte consists of:
•
•
The scale field (bit 7:6) specifies the scale factor.
•
The base field (bits 2:0) specifies the register number of the base register.
The index field (bits 5:3) specifies the register number of the vector index register, each element in the vector
register specifies an index.
Table 2-3 shows the 32-bit VSIB addressing form. It is organized to give 256 possible values of the SIB byte (in
hexadecimal). General purpose registers used as a base are indicated across the top of the table, along with corresponding values for the SIB byte’s base field. The register names also include R8L-R15L applicable only in 64-bit
mode (when address size override prefix is used, but the value of VEX.B is not shown in Table 2-3). In 32-bit mode,
R8L-R15L does not apply.
Table rows in the body of the table indicate the vector index register used as the index field and each supported
scaling factor shown separately. Vector registers used in the index field can be XMM or YMM registers. The leftmost column includes vector registers VR8-VR15 (i.e. XMM8/YMM8-XMM15/YMM15), which are only available in
64-bit mode and does not apply if encoding in 32-bit mode.
Table 2-13. 32-Bit VSIB Addressing Forms of the SIB Byte
r32
(In decimal) Base =
(In binary) Base =
Scaled Index
SS
EAX/
R8L
0
000
ECX/
R9L
1
001
EDX/
R10L
2
010
Index
EBX/
R11L
3
011
ESP/
R12L
4
100
EBP/
R13L1
5
101
ESI/
R14L
6
110
EDI/
R15L
7
111
Value of SIB Byte (in Hexadecimal)
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*1
00
000
001
010
011
100
101
110
111
00
08
10
18
20
28
30
38
01
09
11
19
21
29
31
39
02
0A
12
1A
22
2A
32
3A
03
0B
13
1B
23
2B
33
3B
04
0C
14
1C
24
2C
34
3C
05
0D
15
1D
25
2D
35
3D
06
0E
16
1E
26
2E
36
3E
07
0F
17
1F
27
2F
37
3F
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*2
01
000
001
010
011
100
101
110
111
40
48
50
58
60
68
70
78
41
49
51
59
61
69
71
79
42
4A
52
5A
62
6A
72
7A
43
4B
53
5B
63
6B
73
7B
44
4C
54
5C
64
6C
74
7C
45
4D
55
5D
65
6D
75
7D
46
4E
56
5E
66
6E
76
7E
47
4F
57
5F
67
6F
77
7F
2-20 Vol. 2A
INSTRUCTION FORMAT
Table 2-13. 32-Bit VSIB Addressing Forms of the SIB Byte (Contd.)
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*4
10
000
001
010
011
100
101
110
111
80
88
90
98
A0
A8
B0
B8
81
89
91
89
A1
A9
B1
B9
82
8A
92
9A
A2
AA
B2
BA
83
8B
93
9B
A3
AB
B3
BB
84
8C
94
9C
A4
AC
B4
BC
85
8D
95
9D
A5
AD
B5
BD
86
8E
96
9E
A6
AE
B6
BE
87
8F
97
9F
A7
AF
B7
BF
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*8
11
000
001
010
011
100
101
110
111
C0
C8
D0
D8
E0
E8
F0
F8
C1
C9
D1
D9
E1
E9
F1
F9
C2
CA
D2
DA
E2
EA
F2
FA
C3
CB
D3
DB
E3
EB
F3
FB
C4
CC
D4
DC
E4
EC
F4
FC
C5
CD
D5
DD
E5
ED
F5
FD
C6
CE
D6
DE
E6
EE
F6
FE
C7
CF
D7
DF
E7
EF
F7
FF
NOTES:
1. If ModR/M.mod = 00b, the base address is zero, then effective address is computed as [scaled vector index] + disp32. Otherwise the
base address is computed as [EBP/R13]+ disp, the displacement is either 8 bit or 32 bit depending on the value of ModR/M.mod:
MOD
Effective Address
00b
[Scaled Vector Register] + Disp32
01b
[Scaled Vector Register] + Disp8 + [EBP/R13]
10b
[Scaled Vector Register] + Disp32 + [EBP/R13]
2.3.12.1
64-bit Mode VSIB Memory Addressing
In 64-bit mode VSIB memory addressing uses the VEX.B field and the base field of the SIB byte to encode one of
the 16 general-purpose register as the base register. The VEX.X field and the index field of the SIB byte encode one
of the 16 vector registers as the vector index register.
In 64-bit mode the top row of Table 2-13 base register should be interpreted as the full 64-bit of each register.
2.4
AVX AND SSE INSTRUCTION EXCEPTION SPECIFICATION
To look up the exceptions of legacy 128-bit SIMD instruction, 128-bit VEX-encoded instructions, and 256-bit VEXencoded instruction, Table 2-14 summarizes the exception behavior into separate classes, with detailed exception
conditions defined in sub-sections 2.4.1 through 2.5.1. For example, ADDPS contains the entry:
“See Exceptions Type 2”
In this entry, “Type2” can be looked up in Table 2-14.
The instruction’s corresponding CPUID feature flag can be identified in the fourth column of the Instruction
summary table.
Note: #UD on CPUID feature flags=0 is not guaranteed in a virtualized environment if the hardware supports the
feature flag.
NOTE
Instructions that operate only with MMX, X87, or general-purpose registers are not covered by the
exception classes defined in this section. For instructions that operate on MMX registers, see
Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Vol. 2A 2-21
INSTRUCTION FORMAT
Table 2-14. Exception class description
Exception Class
Instruction set
Mem arg
Floating-Point
Exceptions (#XM)
Type 1
AVX,
Legacy SSE
16/32 byte explicitly
aligned
None
Type 2
AVX,
Legacy SSE
16/32 byte not explicitly
aligned
Yes
Type 3
AVX,
Legacy SSE
< 16 byte
Yes
Type 4
AVX,
Legacy SSE
16/32 byte not explicitly
aligned
No
Type 5
AVX,
Legacy SSE
< 16 byte
No
Type 6
AVX (no Legacy SSE)
Varies
(At present, none do)
Type 7
AVX,
Legacy SSE
None
None
Type 8
AVX
None
None
F16C
8 or 16 byte, Not explicitly
aligned, no AC#
Yes
AVX2
Not explicitly aligned, no
AC#
No
Type 11
Type 12
See Table 2-15 for lists of instructions in each exception class.
2-22 Vol. 2A
INSTRUCTION FORMAT
Table 2-15. Instructions in each Exception Class
Exception Class
Instruction
Type 1
(V)MOVAPD, (V)MOVAPS, (V)MOVDQA, (V)MOVNTDQ, (V)MOVNTDQA, (V)MOVNTPD, (V)MOVNTPS
Type 2
(V)ADDPD, (V)ADDPS, (V)ADDSUBPD, (V)ADDSUBPS, (V)CMPPD, (V)CMPPS, (V)CVTDQ2PS, (V)CVTPD2DQ,
(V)CVTPD2PS, (V)CVTPS2DQ, (V)CVTTPD2DQ, (V)CVTTPS2DQ, (V)DIVPD, (V)DIVPS, (V)DPPD*, (V)DPPS*,
VFMADD132PD, VFMADD213PD, VFMADD231PD, VFMADD132PS, VFMADD213PS, VFMADD231PS,
VFMADDSUB132PD, VFMADDSUB213PD, VFMADDSUB231PD, VFMADDSUB132PS, VFMADDSUB213PS,
VFMADDSUB231PS, VFMSUBADD132PD, VFMSUBADD213PD, VFMSUBADD231PD, VFMSUBADD132PS,
VFMSUBADD213PS, VFMSUBADD231PS, VFMSUB132PD, VFMSUB213PD, VFMSUB231PD, VFMSUB132PS,
VFMSUB213PS, VFMSUB231PS, VFNMADD132PD, VFNMADD213PD, VFNMADD231PD, VFNMADD132PS,
VFNMADD213PS, VFNMADD231PS, VFNMSUB132PD, VFNMSUB213PD, VFNMSUB231PD, VFNMSUB132PS,
VFNMSUB213PS, VFNMSUB231PS, (V)HADDPD, (V)HADDPS, (V)HSUBPD, (V)HSUBPS, (V)MAXPD, (V)MAXPS,
(V)MINPD, (V)MINPS, (V)MULPD, (V)MULPS, (V)ROUNDPS, (V)SQRTPD, (V)SQRTPS, (V)SUBPD, (V)SUBPS
Type 3
(V)ADDSD, (V)ADDSS, (V)CMPSD, (V)CMPSS, (V)COMISD, (V)COMISS, (V)CVTPS2PD, (V)CVTSD2SI, (V)CVTSD2SS,
(V)CVTSI2SD, (V)CVTSI2SS, (V)CVTSS2SD, (V)CVTSS2SI, (V)CVTTSD2SI, (V)CVTTSS2SI, (V)DIVSD, (V)DIVSS,
VFMADD132SD, VFMADD213SD, VFMADD231SD, VFMADD132SS, VFMADD213SS, VFMADD231SS,
VFMSUB132SD, VFMSUB213SD, VFMSUB231SD, VFMSUB132SS, VFMSUB213SS, VFMSUB231SS,
VFNMADD132SD, VFNMADD213SD, VFNMADD231SD, VFNMADD132SS, VFNMADD213SS, VFNMADD231SS,
VFNMSUB132SD, VFNMSUB213SD, VFNMSUB231SD, VFNMSUB132SS, VFNMSUB213SS, VFNMSUB231SS,
(V)MAXSD, (V)MAXSS, (V)MINSD, (V)MINSS, (V)MULSD, (V)MULSS, (V)ROUNDSD, (V)ROUNDSS, (V)SQRTSD,
(V)SQRTSS, (V)SUBSD, (V)SUBSS, (V)UCOMISD, (V)UCOMISS
Type 4
(V)AESDEC, (V)AESDECLAST, (V)AESENC, (V)AESENCLAST, (V)AESIMC, (V)AESKEYGENASSIST, (V)ANDPD,
(V)ANDPS, (V)ANDNPD, (V)ANDNPS, (V)BLENDPD, (V)BLENDPS, VBLENDVPD, VBLENDVPS, (V)LDDQU***,
(V)MASKMOVDQU, (V)PTEST, VTESTPS, VTESTPD, (V)MOVDQU*, (V)MOVSHDUP, (V)MOVSLDUP, (V)MOVUPD*,
(V)MOVUPS*, (V)MPSADBW, (V)ORPD, (V)ORPS, (V)PABSB, (V)PABSW, (V)PABSD, (V)PACKSSWB, (V)PACKSSDW,
(V)PACKUSWB, (V)PACKUSDW, (V)PADDB, (V)PADDW, (V)PADDD, (V)PADDQ, (V)PADDSB, (V)PADDSW,
(V)PADDUSB, (V)PADDUSW, (V)PALIGNR, (V)PAND, (V)PANDN, (V)PAVGB, (V)PAVGW, (V)PBLENDVB,
(V)PBLENDW, (V)PCMP(E/I)STRI/M***, (V)PCMPEQB, (V)PCMPEQW, (V)PCMPEQD, (V)PCMPEQQ, (V)PCMPGTB,
(V)PCMPGTW, (V)PCMPGTD, (V)PCMPGTQ, (V)PCLMULQDQ, (V)PHADDW, (V)PHADDD, (V)PHADDSW,
(V)PHMINPOSUW, (V)PHSUBD, (V)PHSUBW, (V)PHSUBSW, (V)PMADDWD, (V)PMADDUBSW, (V)PMAXSB,
(V)PMAXSW, (V)PMAXSD, (V)PMAXUB, (V)PMAXUW, (V)PMAXUD, (V)PMINSB, (V)PMINSW, (V)PMINSD,
(V)PMINUB, (V)PMINUW, (V)PMINUD, (V)PMULHUW, (V)PMULHRSW, (V)PMULHW, (V)PMULLW, (V)PMULLD,
(V)PMULUDQ, (V)PMULDQ, (V)POR, (V)PSADBW, (V)PSHUFB, (V)PSHUFD, (V)PSHUFHW, (V)PSHUFLW, (V)PSIGNB,
(V)PSIGNW, (V)PSIGND, (V)PSLLW, (V)PSLLD, (V)PSLLQ, (V)PSRAW, (V)PSRAD, (V)PSRLW, (V)PSRLD, (V)PSRLQ,
(V)PSUBB, (V)PSUBW, (V)PSUBD, (V)PSUBQ, (V)PSUBSB, (V)PSUBSW, (V)PUNPCKHBW, (V)PUNPCKHWD,
(V)PUNPCKHDQ, (V)PUNPCKHQDQ, (V)PUNPCKLBW, (V)PUNPCKLWD, (V)PUNPCKLDQ, (V)PUNPCKLQDQ,
(V)PXOR, (V)RCPPS, (V)RSQRTPS, (V)SHUFPD, (V)SHUFPS, (V)UNPCKHPD, (V)UNPCKHPS, (V)UNPCKLPD,
(V)UNPCKLPS, (V)XORPD, (V)XORPS, VPBLENDD, VPERMD, VPERMPS, VPERMPD, VPERMQ, VPSLLVD, VPSLLVQ,
VPSRAVD, VPSRLVD, VPSRLVQ, VPERMILPD, VPERMILPS, VPERM2F128
Type 5
(V)CVTDQ2PD, (V)EXTRACTPS, (V)INSERTPS, (V)MOVD, (V)MOVQ, (V)MOVDDUP, (V)MOVLPD, (V)MOVLPS,
(V)MOVHPD, (V)MOVHPS, (V)MOVSD, (V)MOVSS, (V)PEXTRB, (V)PEXTRD, (V)PEXTRW, (V)PEXTRQ, (V)PINSRB,
(V)PINSRD, (V)PINSRW, (V)PINSRQ, (V)RCPSS, (V)RSQRTSS, (V)PMOVSX/ZX, VLDMXCSR*, VSTMXCSR
Type 6
VEXTRACTF128, VBROADCASTSS, VBROADCASTSD, VBROADCASTF128, VINSERTF128, VMASKMOVPS**,
VMASKMOVPD**, VPMASKMOVD, VPMASKMOVQ, VBROADCASTI128, VPBROADCASTB, VPBROADCASTD,
VPBROADCASTW, VPBROADCASTQ, VEXTRACTI128, VINSERTI128, VPERM2I128
Type 7
(V)MOVLHPS, (V)MOVHLPS, (V)MOVMSKPD, (V)MOVMSKPS, (V)PMOVMSKB, (V)PSLLDQ, (V)PSRLDQ, (V)PSLLW,
(V)PSLLD, (V)PSLLQ, (V)PSRAW, (V)PSRAD, (V)PSRLW, (V)PSRLD, (V)PSRLQ
Type 8
VZEROALL, VZEROUPPER
Type 11
VCVTPH2PS, VCVTPS2PH
Type 12
VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHERQPD, VPGATHERDD, VPGATHERDQ, VPGATHERQD,
VPGATHERQQ
(*) - Additional exception restrictions are present - see the Instruction description for details
(**) - Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits of all 1s, i.e. no
alignment checks are performed.
Vol. 2A 2-23
INSTRUCTION FORMAT
(***) - PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM and LDDQU instructions do not cause #GP if the memory operand is not
aligned to 16-Byte boundary.
Table 2-15 classifies exception behaviors for AVX instructions. Within each class of exception conditions that are
listed in Table 2-18 through Table 2-27, certain subsets of AVX instructions may be subject to #UD exception
depending on the encoded value of the VEX.L field. Table 2-17 provides supplemental information of AVX instructions that may be subject to #UD exception if encoded with incorrect values in the VEX.W or VEX.L field.
Table 2-16. #UD Exception and VEX.W=1 Encoding
Exception Class
#UD If VEX.W = 1 in all modes
#UD If VEX.W = 1 in
non-64-bit modes
Type 1
Type 2
Type 3
Type 4
VBLENDVPD, VBLENDVPS, VPBLENDVB, VTESTPD, VTESTPS, VPBLENDD, VPERMD,
VPERMPS, VPERM2I128, VPSRAVD, VPERMILPD, VPERMILPS, VPERM2F128
Type 5
Type 6
VPEXTRQ, VPINSRQ,
VEXTRACTF128, VBROADCASTSS, VBROADCASTSD, VBROADCASTF128,
VINSERTF128, VMASKMOVPS, VMASKMOVPD, VBROADCASTI128,
VPBROADCASTB/W/D, VEXTRACTI128, VINSERTI128
Type 7
Type 8
Type 11
Type 12
2-24 Vol. 2A
VCVTPH2PS, VCVTPS2PH
INSTRUCTION FORMAT
Table 2-17. #UD Exception and VEX.L Field Encoding
Exception
Class
#UD If VEX.L = 0
Type 1
#UD If (VEX.L = 1 && AVX2 not present && AVX
present)
#UD If (VEX.L = 1 && AVX2
present)
VMOVNTDQA
VDPPD
VDPPD
VPCMP(E/I)STRI/M,
PHMINPOSUW
Type 4
VMASKMOVDQU, VMPSADBW, VPABSB/W/D,
VPACKSSWB/DW, VPACKUSWB/DW, VPADDB/W/D,
VPADDQ, VPADDSB/W, VPADDUSB/W, VPALIGNR, VPAND,
VPANDN, VPAVGB/W, VPBLENDVB, VPBLENDW,
VPCMP(E/I)STRI/M, VPCMPEQB/W/D/Q, VPCMPGTB/W/D/Q,
VPHADDW/D, VPHADDSW, VPHMINPOSUW, VPHSUBD/W,
VPHSUBSW, VPMADDWD, VPMADDUBSW, VPMAXSB/W/D,
VPMAXUB/W/D, VPMINSB/W/D, VPMINUB/W/D,
VPMULHUW, VPMULHRSW, VPMULHW/LW, VPMULLD,
VPMULUDQ, VPMULDQ, VPOR, VPSADBW, VPSHUFB/D,
VPSHUFHW/LW, VPSIGNB/W/D, VPSLLW/D/Q, VPSRAW/D,
VPSRLW/D/Q, VPSUBB/W/D/Q, VPSUBSB/W,
VPUNPCKHBW/WD/DQ, VPUNPCKHQDQ,
VPUNPCKLBW/WD/DQ, VPUNPCKLQDQ, VPXOR
Same as column 3
Type 5
VEXTRACTPS, VINSERTPS, VMOVD, VMOVQ, VMOVLPD,
VMOVLPS, VMOVHPD, VMOVHPS, VPEXTRB, VPEXTRD,
VPEXTRW, VPEXTRQ, VPINSRB, VPINSRD, VPINSRW,
VPINSRQ, VPMOVSX/ZX, VLDMXCSR, VSTMXCSR
VMOVLHPS, VMOVHLPS, VPMOVMSKB, VPSLLDQ,
VPSRLDQ, VPSLLW, VPSLLD, VPSLLQ, VPSRAW, VPSRAD,
VPSRLW, VPSRLD, VPSRLQ
VMOVLHPS, VMOVHLPS
Type 2
Type 3
Type 6
Type 7
VEXTRACTF128,
VPERM2F128,
VBROADCASTSD,
VBROADCASTF128,
VINSERTF128,
Type 8
Type 11
Type 12
Vol. 2A 2-25
INSTRUCTION FORMAT
2.4.1
Exceptions Type 1 (Aligned memory reference)
Invalid Opcode,
#UD
Device Not Available, #NM
X
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
X
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
X
X
VEX.256: Memory operand is not 32-byte aligned.
VEX.128: Memory operand is not 16-byte aligned.
X
X
Legacy SSE: Memory operand is not 16-byte aligned.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
X
Page Fault
#PF(fault-code)
2-26 Vol. 2A
Cause of Exception
X
Stack, SS(0)
General Protection, #GP(0)
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-18. Type 1 Class Exception Conditions
X
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
X
X
For a page fault.
INSTRUCTION FORMAT
2.4.2
Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned)
Invalid Opcode,
#UD
Device Not Available, #NM
X
X
X
X
X
X
X
Cause of Exception
VEX prefix.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
X
X
X
X
X
General Protection, #GP(0)
Page Fault
#PF(fault-code)
X
If a memory address referencing the SS segment is in a non-canonical form.
Legacy SSE: Memory operand is not 16-byte aligned.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
SIMD Floatingpoint Exception,
#XM
64-bit
X
Protected and
Compatibility
Virtual 8086
Exception
Real
Table 2-19. Type 2 Class Exception Conditions
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
X
X
X
For a page fault.
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
Vol. 2A 2-27
INSTRUCTION FORMAT
2.4.3
Exceptions Type 3 (<16 Byte memory argument)
X
X
X
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-20. Type 3 Class Exception Conditions
VEX prefix.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
Invalid Opcode, #UD
Device Not Available,
#NM
X
X
X
X
Cause of Exception
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault
#PF(fault-code)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 Bytes or
less is made while the current privilege level is 3.
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
SIMD Floating-point
Exception, #XM
2-28 Vol. 2A
X
INSTRUCTION FORMAT
2.4.4
Exceptions Type 4 (>=16 Byte mem arg no alignment, no floating-point exceptions)
Invalid Opcode, #UD
Device Not Available,
#NM
X
Cause of Exception
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
X
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
X
Legacy SSE: Memory operand is not 16-byte aligned.1
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
Page Fault
#PF(fault-code)
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-21. Type 4 Class Exception Conditions
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
If the memory address is in a non-canonical form.
X
X
For a page fault.
NOTES:
1. PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM and LDDQU instructions do not cause #GP if the memory operand is not aligned to
16-Byte boundary.
Vol. 2A 2-29
INSTRUCTION FORMAT
2.4.5
Exceptions Type 5 (<16 Byte mem arg and no FP exceptions)
Invalid Opcode, #UD
Device Not Available,
#NM
X
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-22. Type 5 Class Exception Conditions
Cause of Exception
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault
#PF(fault-code)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made
while the current privilege level is 3.
2-30 Vol. 2A
INSTRUCTION FORMAT
2.4.6
Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues)
Note: At present, the AVX instructions in this category do not generate floating-point exceptions.
X
Device Not Available,
#NM
Stack, SS(0)
General Protection,
#GP(0)
Page Fault
#PF(fault-code)
Alignment Check
#AC(0)
Cause of Exception
VEX prefix.
X
Invalid Opcode, #UD
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-23. Type 6 Class Exception Conditions
X
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If the memory address is in a non-canonical form.
X
X
For a page fault.
X
X
For 4 or 8 byte memory references if alignment checking is enabled and an
unaligned memory reference is made while the current privilege level is 3.
Vol. 2A 2-31
INSTRUCTION FORMAT
2.4.7
Exceptions Type 7 (No FP exceptions, no memory arg)
Invalid Opcode, #UD
X
Cause of Exception
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
Device Not Available,
#NM
2.4.8
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-24. Type 7 Class Exception Conditions
Exceptions Type 8 (AVX and no memory argument)
X
X
X
2-32 Vol. 2A
X
Cause of Exception
Always in Real or Virtual-8086 mode.
X
Device Not Available,
#NM
64-bit
Virtual-8086
Invalid Opcode, #UD
Protected and
Compatibility
Exception
Real
Table 2-25. Type 8 Class Exception Conditions
X
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
If CPUID.01H.ECX.AVX[bit 28]=0.
If VEX.vvvv ≠ 1111B.
X
X
If proceeded by a LOCK prefix (F0H).
X
X
If CR0.TS[bit 3]=1.
INSTRUCTION FORMAT
2.4.9
Exception Type 11 (VEX-only, mem arg no AC, floating-point exceptions)
X
X
Device Not Available, #NM
64-bit
Virtual-8086
Invalid Opcode, #UD
Protected and
Compatibility
Exception
Real
Table 2-26. Type 11 Class Exception Conditions
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
General Protection,
#GP(0)
X
For an illegal address in the SS segment.
X
X
Page Fault #PF
(fault-code)
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
SIMD Floating-Point
Exception, #XM
Cause of Exception
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
X
For a page fault.
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
Vol. 2A 2-33
INSTRUCTION FORMAT
2.4.10
Exception Type 12 (VEX-only, VSIB mem arg, no AC, no floating-point exceptions)
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-27. Type 12 Class Exception Conditions
X
X
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
NA
If address size attribute is 16 bit.
X
X
X
X
If ModR/M.mod = ‘11b’.
X
X
X
X
If ModR/M.rm ≠ ‘100b’.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If any vector register is used more than once between the destination register,
mask register and the index register in VSIB addressing.
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
2.5
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
Page Fault #PF (faultcode)
Cause of Exception
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
For a page fault.
VEX ENCODING SUPPORT FOR GPR INSTRUCTIONS
VEX prefix may be used to encode instructions that operate on neither YMM nor XMM registers. VEX-encoded
general-purpose-register instructions have the following properties:
•
•
Instruction syntax support for three encodable operands.
•
Elimination of escape opcode byte (0FH), two-byte escape via a compact bit field representation within the VEX
prefix.
•
Elimination of the need to use REX prefix to encode the extended half of general-purpose register sets (R8-R15)
for direct register access or memory addressing.
•
Flexible and more compact bit fields are provided in the VEX prefix to retain the full functionality provided by
REX prefix. REX.W, REX.X, REX.B functionalities are provided in the three-byte VEX prefix only.
•
VEX-encoded GPR instructions are encoded with VEX.L=0.
Encoding support for instruction syntax of non-destructive source operand, destination operand encoded via
VEX.vvvv, and destructive three-operand syntax.
2-34 Vol. 2A
INSTRUCTION FORMAT
Any VEX-encoded GPR instruction with a 66H, F2H, or F3H prefix preceding VEX will #UD.
Any VEX-encoded GPR instruction with a REX prefix proceeding VEX will #UD.
VEX-encoded GPR instructions are not supported in real and virtual 8086 modes.
2.5.1
Exception Conditions for VEX-Encoded GPR Instructions
The exception conditions applicable to VEX-encoded GPR instruction differs from those of legacy GPR instructions.
Table 2-28 lists VEX-encoded GPR instructions. The exception conditions for VEX-encoded GRP instructions are
found in Table 2-29 for those instructions which have a default operand size of 32 bits and 16-bit operand size is
not encodable.
Table 2-28. VEX-Encoded GPR Instructions
Exception Class
Instruction
See Table 2-29
ANDN, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX
(*) - Additional exception restrictions are present - see the Instruction description for details.
X
X
X
64-bit
X
Protected and
Compatibility
Invalid Opcode, #UD
Virtual-8086
Exception
Real
Table 2-29. Exception Definition (VEX-Encoded GPR Instructions)
X
X
X
X
X
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null
segment selector.
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
If BMI1/BMI2 CPUID feature flag is ‘0’.
If a VEX prefix is present.
X
Stack, SS(0)
Cause of Exception
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made
while the current privilege level is 3.
2.6
INTEL® AVX-512 ENCODING
The majority of the Intel AVX-512 family of instructions (operating on 512/256/128-bit vector register operands)
are encoded using a new prefix (called EVEX). Opmask instructions (operating on opmask register operands) are
encoded using the VEX prefix. The EVEX prefix has some parts resembling the instruction encoding scheme using
the VEX prefix, and many other capabilities not available with the VEX prefix.
The significant feature differences between EVEX and VEX are summarized below.
Vol. 2A 2-35
INSTRUCTION FORMAT
•
EVEX is a 4-Byte prefix (the first byte must be 62H); VEX is either a 2-Byte (C5H is the first byte) or 3-Byte
(C4H is the first byte) prefix.
•
•
EVEX prefix can encode 32 vector registers (XMM/YMM/ZMM) in 64-bit mode.
•
EVEX memory addressing with disp8 form uses a compressed disp8 encoding scheme to improve the encoding
density of the instruction byte stream.
•
EVEX prefix can encode functionality that are specific to instruction classes (e.g., packed instruction with
“load+op” semantic can support embedded broadcast functionality, floating-point instruction with rounding
semantic can support static rounding functionality, floating-point instruction with non-rounding arithmetic
semantic can support “suppress all exceptions” functionality).
EVEX prefix can encode an opmask register for conditional processing or selection control in EVEX-encoded
vector instructions. Opmask instructions, whose source/destination operands are opmask registers and treat
the content of an opmask register as a single value, are encoded using the VEX prefix.
2.6.1
Instruction Format and EVEX
The placement of the EVEX prefix in an IA instruction is represented in Figure 2-10.
# of bytes:
[Prefixes]
1
4
EVEX
1
Opcode
1
ModR/M
[SIB]
4
[Disp32]
1
[Immediate]
1
[Disp8*N]
Figure 2-10. AVX-512 Instruction Format and the EVEX Prefix
The EVEX prefix is a 4-byte prefix, with the first two bytes derived from unused encoding form of the 32-bit-modeonly BOUND instruction. The layout of the EVEX prefix is shown in Figure 2-11. The first byte must be 62H, followed
by three payload bytes, denoted as P0, P1, and P2 individually or collectively as P[23:0] (see Figure 2-11).
EVEX
62H
P0
P1
7
P0
R
7
P1
W
7
P2
z
6
X
6
v
6
L’
P2
5
B
5
v
5
L
4
R’
4
v
4
b
3
0
3
v
3
V’
2
0
2
1
2
a
1
0
m
1
m
0
p
1
p
P[15:8]
0
a
Figure 2-11. Bit Field Layout of the EVEX Prefix
2-36 Vol. 2A
P[7:0]
a
P[23:16]
INSTRUCTION FORMAT
Table 2-30. EVEX Prefix Bit Field Functional Grouping
Notation
Bit field Group
Position
Comment
--
Reserved
P[3 : 2]
Must be 0.
--
Fixed Value
P[10]
Must be 1.
EVEX.mm
Compressed legacy escape
P[1: 0]
Identical to low two bits of VEX.mmmmm.
EVEX.pp
Compressed legacy prefix
P[9 : 8]
Identical to VEX.pp.
EVEX.RXB
Next-8 register specifier modifier
P[7 : 5]
Combine with ModR/M.reg, ModR/M.rm (base, index/vidx).
EVEXR’
High-16 register specifier modifier
P[4]
Combine with EVEX.R and ModR/M.reg.
EVEXX
High-16 register specifier modifier
P[6]
Combine with EVEX.B and ModR/M.rm, when SIB/VSIB absent.
EVEX.vvvv
NDS register specifier
P[14 : 11]
Same as VEX.vvvv.
EVEXV’
High-16 NDS/VIDX register specifier
P[19]
Combine with EVEX.vvvv or when VSIB present.
EVEX.aaa
Embedded opmask register specifier
P[18 : 16]
EVEX.W
Osize promotion/Opcode extension
P[15]
EVEX.z
Zeroing/Merging
P[23]
EVEX.b
Broadcast/RC/SAE Context
P[20]
EVEX.L’L
Vector length/RC
P[22 : 21]
The bit fields in P[23:0] are divided into the following functional groups (Table 2-30 provides a tabular summary):
•
•
•
Reserved bits: P[3:2] must be 0, otherwise #UD.
•
Operand specifier modifier bits for vector register, general purpose register, memory addressing: P[7:5] allows
access to the next set of 8 registers beyond the low 8 registers when combined with ModR/M register specifiers.
•
Operand specifier modifier bit for vector register: P[4] (or EVEX.R’) allows access to the high 16 vector register
set when combined with P[7] and ModR/M.reg specifier; P[6] can also provide access to a high 16 vector
register when SIB or VSIB addressing are not needed.
•
Non-destructive source /vector index operand specifier: P[19] and P[14:11] encode the second source vector
register operand in a non-destructive source syntax, vector index register operand can access an upper 16
vector register using P[19].
•
Op-mask register specifiers: P[18:16] encodes op-mask register set k0-k7 in instructions operating on vector
registers.
•
EVEX.W: P[15] is similar to VEX.W which serves either as opcode extension bit or operand size promotion to
64-bit in 64-bit mode.
•
Vector destination merging/zeroing: P[23] encodes the destination result behavior which either zeroes the
masked elements or leave masked element unchanged.
•
Broadcast/Static-rounding/SAE context bit: P[20] encodes multiple functionality, which differs across different
classes of instructions and can affect the meaning of the remaining field (EVEX.L’L). The functionality for the
following instruction classes are:
Fixed-value bit: P[10] must be 1, otherwise #UD.
Compressed legacy prefix/escape bytes: P[1:0] is identical to the lowest 2 bits of VEX.mmmmm; P[9:8] is
identical to VEX.pp.
— Broadcasting a single element across the destination vector register: this applies to the instruction class
with Load+Op semantic where one of the source operand is from memory.
— Redirect L’L field (P[22:21]) as static rounding control for floating-point instructions with rounding
semantic. Static rounding control overrides MXCSR.RC field and implies “Suppress all exceptions” (SAE).
— Enable SAE for floating -point instructions with arithmetic semantic that is not rounding.
— For instruction classes outside of the afore-mentioned three classes, setting EVEX.b will cause #UD.
Vol. 2A 2-37
INSTRUCTION FORMAT
•
Vector length/rounding control specifier: P[22:21] can serve one of three options.
— Vector length information for packed vector instructions.
— Ignored for instructions operating on vector register content as a single data element.
— Rounding control for floating-point instructions that have a rounding semantic and whose source and
destination operands are all vector registers.
2.6.2
Register Specifier Encoding and EVEX
EVEX-encoded instruction can access 8 opmask registers, 16 general-purpose registers and 32 vector registers in
64-bit mode (8 general-purpose registers and 8 vector registers in non-64-bit modes). EVEX-encoding can support
instruction syntax that access up to 4 instruction operands. Normal memory addressing modes and VSIB memory
addressing are supported with EVEX prefix encoding. The mapping of register operands used by various instruction
syntax and memory addressing in 64-bit mode are shown in Table 2-31. Opmask register encoding is described in
Section 2.6.3.
Table 2-31. 32-Register Support in 64-bit Mode Using EVEX with Embedded REX Bits
41
3
[2:0]
Reg. Type
Common Usages
REG
EVEX.R’
REX.R
modrm.reg
GPR, Vector
Destination or Source
NDS/NDD
EVEX.V’
GPR, Vector
2ndSource or Destination
RM
EVEX.X
EVEX.B
modrm.r/m
GPR, Vector
1st Source or Destination
BASE
0
EVEX.B
modrm.r/m
GPR
memory addressing
INDEX
0
EVEX.X
sib.index
GPR
memory addressing
EVEX.V’
EVEX.X
sib.index
Vector
VSIB memory addressing
VIDX
EVEX.vvvv
NOTES:
1. Not applicable for accessing general purpose registers.
The mapping of register operands used by various instruction syntax and memory addressing in 32-bit modes are
shown in Table 2-32.
Table 2-32. EVEX Encoding Register Specifiers in 32-bit Mode
[2:0]
Reg. Type
Common Usages
REG
modrm.reg
GPR, Vector
Destination or Source
NDS/NDD
EVEX.vvv
GPR, Vector
2nd Source or Destination
RM
modrm.r/m
GPR, Vector
1st Source or Destination
BASE
modrm.r/m
GPR
Memory Addressing
INDEX
sib.index
GPR
Memory Addressing
VIDX
sib.index
Vector
VSIB Memory Addressing
2.6.3
Opmask Register Encoding
There are eight opmask registers, k0-k7. Opmask register encoding falls into two categories:
•
Opmask registers that are the source or destination operands of an instruction treating the content of opmask
register as a scalar value, are encoded using the VEX prefix scheme. It can support up to three operands using
standard modR/M byte’s reg field and rm field and VEX.vvvv. Such a scalar opmask instruction does not support
conditional update of the destination operand.
•
An opmask register providing conditional processing and/or conditional update of the destination register of a
vector instruction is encoded using EVEX.aaa field (see Section 2.6.4).
2-38 Vol. 2A
INSTRUCTION FORMAT
•
An opmask register serving as the destination or source operand of a vector instruction is encoded using
standard modR/M byte’s reg field and rm fields.
Table 2-33. Opmask Register Specifier Encoding
[2:0]
Register Access
Common Usages
REG
modrm.reg
k0-k7
Source
NDS
VEX.vvvv
k0-k7
2nd Source
RM
modrm.r/m
k0-7
1st Source
{k1}
EVEX.aaa
1
k0 -k7
Opmask
NOTES:
1. Instructions that overwrite the conditional mask in opmask do not permit using k0 as the embedded mask.
2.6.4
Masking Support in EVEX
EVEX can encode an opmask register to conditionally control per-element computational operation and updating of
result of an instruction to the destination operand. The predicate operand is known as the opmask register. The
EVEX.aaa field, P[18:16] of the EVEX prefix, is used to encode one out of a set of eight 64-bit architectural registers. Note that from this set of 8 architectural registers, only k1 through k7 can be addressed as predicate operands. k0 can be used as a regular source or destination but cannot be encoded as a predicate operand.
AVX-512 instructions support two types of masking with EVEX.z bit (P[23]) controlling the type of masking:
•
Merging-masking, which is the default type of masking for EVEX-encoded vector instructions, preserves the old
value of each element of the destination where the corresponding mask bit has a 0. It corresponds to the case
of EVEX.z = 0.
•
Zeroing-masking, is enabled by having the EVEX.z bit set to 1. In this case, an element of the destination is set
to 0 when the corresponding mask bit has a 0 value.
AVX-512 Foundation instructions can be divided into the following groups:
•
Instructions which support “zeroing-masking”.
— Also allow merging-masking.
•
Instructions which require aaa = 000.
— Do not allow any form of masking.
•
Instructions which allow merging-masking but do not allow zeroing-masking.
— Require EVEX.z to be set to 0.
— This group is mostly composed of instructions that write to memory.
•
Instructions which require aaa <> 000 do not allow EVEX.z to be set to 1.
— Allow merging-masking and do not allow zeroing-masking, e.g., gather instructions.
2.6.5
Compressed Displacement (disp8*N) Support in EVEX
For memory addressing using disp8 form, EVEX-encoded instructions always use a compressed displacement
scheme by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length,
the value of EVEX.b bit (embedded broadcast) and the input element size of the instruction. In general, the factor
N corresponds to the number of bytes characterizing the internal memory operation of the input operand (e.g., 64
when the accessing a full 512-bit memory vector). The scale factor N is listed in Table 2-34 and Table 2-35 below,
where EVEX encoded instructions are classified using the tupletype attribute. The scale factor N of each tupletype
is listed based on the vector length (VL) and other factors affecting it.
Table 2-34 covers EVEX-encoded instructions which has a load semantic in conjunction with additional computational or data element movement operation, operating either on the full vector or half vector (due to conversion of
Vol. 2A 2-39
INSTRUCTION FORMAT
numerical precision from a wider format to narrower format). EVEX.b is supported for such instructions for data
element sizes which are either dword or qword (see Section 2.6.11).
EVEX-encoded instruction that are pure load/store, and “Load+op” instruction semantic that operate on data
element size less then dword do not support broadcasting using EVEX.b. These are listed in Table 2-35. Table 2-35
also includes many broadcast instructions which perform broadcast using a subset of data elements without using
EVEX.b. These instructions and a few data element size conversion instruction are covered in Table 2-35. Instruction classified in Table 2-35 do not use EVEX.b and EVEX.b must be 0, otherwise #UD will occur.
The tupletype abbreviation will be referenced in the instruction operand encoding table in the reference page of
each instruction, providing the cross reference for the scaling factor N to encoding memory addressing operand.
Note that the disp8*N rules still apply when using 16b addressing.
Table 2-34. Compressed Displacement (DISP8*N) Affected by Embedded Broadcast
TupleType
EVEX.b
InputSize
EVEX.W
0
32bit
0
none
16
32
64
1
32bit
0
{1tox}
4
4
4
0
64bit
1
none
16
32
64
1
64bit
1
{1tox}
8
8
8
0
32bit
0
none
8
16
32
1
32bit
0
{1tox}
4
4
4
Full Vector
(FV)
Half Vector
(HV)
Broadcast N (VL=128) N (VL=256)
N (VL= 512)
Comment
Load+Op (Full Vector
Dword/Qword)
Load+Op (Half Vector)
Table 2-35. EVEX DISP8*N for Instructions Not Affected by Embedded Broadcast
TupleType
InputSize
Full Vector Mem (FVM)
N/A
N/A
16
32
64
8bit
N/A
1
1
1
16bit
N/A
2
2
2
32bit
0
4
4
4
64bit
1
8
8
8
32bit
N/A
4
4
4
64bit
N/A
8
8
8
32bit
0
8
8
8
64bit
1
NA
16
16
32bit
0
NA
16
16
64bit
1
NA
NA
32
Tuple8 (T8)
32bit
0
NA
NA
32
Broadcast (8 elements)
Half Mem (HVM)
N/A
N/A
8
16
32
SubQword Conversion
QuarterMem (QVM)
N/A
N/A
4
8
16
SubDword Conversion
OctMem (OVM)
N/A
N/A
2
4
8
SubWord Conversion
Mem128 (M128)
N/A
N/A
16
16
16
Shift count from memory
MOVDDUP (DUP)
N/A
N/A
8
32
64
VMOVDDUP
Tuple1 Scalar (T1S)
Tuple1 Fixed (T1F)
Tuple2 (T2)
Tuple4 (T4)
2.6.6
EVEX.W N (VL= 128) N (VL= 256) N (VL= 512)
Comment
Load/store or subDword full vector
1Tuple less than Full Vector
1 Tuple memsize not affected by
EVEX.W
Broadcast (2 elements)
Broadcast (4 elements)
EVEX Encoding of Broadcast/Rounding/SAE Support
EVEX.b can provide three types of encoding context, depending on the instruction classes:
2-40 Vol. 2A
INSTRUCTION FORMAT
•
Embedded broadcasting of one data element from a source memory operand to the destination for vector
instructions with “load+op” semantic.
•
•
Static rounding control overriding MXCSR.RC for floating-point instructions with rounding semantic.
“Suppress All exceptions” (SAE) overriding MXCSR mask control for floating-point arithmetic instructions that
do not have rounding semantic.
2.6.7
Embedded Broadcast Support in EVEX
EVEX encodes an embedded broadcast functionality that is supported on many vector instructions with 32-bit
(double word or single-precision floating-point) and 64-bit data elements, and when the source operand is from
memory. EVEX.b (P[20]) bit is used to enable broadcast on load-op instructions. When enabled, only one element
is loaded from memory and broadcasted to all other elements instead of loading the full memory size.
The following instruction classes do not support embedded broadcasting:
•
•
•
Instructions with only one scalar result is written to the vector destination.
Instructions with explicit broadcast functionality provided by its opcode.
Instruction semantic is a pure load or a pure store operation.
2.6.8
Static Rounding Support in EVEX
Static rounding control embedded in the EVEX encoding system applies only to register-to-register flavor of
floating-point instructions with rounding semantic at two distinct vector lengths: (i) scalar, (ii) 512-bit. In both
cases, the field EVEX.L’L expresses rounding mode control overriding MXCSR.RC if EVEX.b is set. When EVEX.b is
set, “suppress all exceptions” is implied. The processor behave as if all MXCSR masking controls are set.
2.6.9
SAE Support in EVEX
The EVEX encoding system allows arithmetic floating-point instructions without rounding semantic to be encoded
with the SAE attribute. This capability applies to scalar and 512-bit vector lengths, register-to-register only, by
setting EVEX.b. When EVEX.b is set, “suppress all exceptions” is implied. The processor behaves as if all MXCSR
masking controls are set.
2.6.10
Vector Length Orthogonality
The architecture of EVEX encoding scheme can support SIMD instructions operating at multiple vector lengths.
Many AVX-512 Foundation instructions operate at 512-bit vector length. The vector length of EVEX encoded vector
instructions are generally determined using the L’L field in EVEX prefix, except for 512-bit floating-point, reg-reg
instructions with rounding semantic. The table below shows the vector length corresponding to various values of
the L’L bits. When EVEX is used to encode scalar instructions, L’L is generally ignored.
When EVEX.b bit is set for a register-register instructions with floating-point rounding semantic, the same two bits
P2[6:5] specifies rounding mode for the instruction, with implied SAE behavior. The mapping of different instruction classes relative to the embedded broadcast/rounding/SAE control and the EVEX.L’L fields are summarized in
Table 2-36.
Table 2-36. EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions
Position
P2[4]
P2[6:5]
P2[6:5]
Broadcast/Rounding/SAE Context
EVEX.b
EVEX.L’L
EVEX.RC
Reg-reg, FP Instructions w/ rounding semantic
Enable static rounding
control (SAE implied)
Vector length Implied
(512 bit or scalar)
00b: SAE + RNE
01b: SAE + RD
10b: SAE + RU
11b: SAE + RZ
Vol. 2A 2-41
INSTRUCTION FORMAT
Table 2-36. EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions
Position
P2[4]
P2[6:5]
P2[6:5]
Broadcast/Rounding/SAE Context
EVEX.b
EVEX.L’L
EVEX.RC
FP Instructions w/o rounding semantic, can cause #XF
SAE control
Load+op Instructions w/ memory source
Broadcast Control
Other Instructions (
Explicit Load/Store/Broadcast/Gather/Scatter)
Must be 0 (otherwise
#UD)
2.6.11
00b: 128-bit
01b: 256-bit
10b: 512-bit
11b: Reserved (#UD)
NA
NA
NA
#UD Equations for EVEX
Instructions encoded using EVEX can face three types of UD conditions: state dependent, opcode independent and
opcode dependent.
2.6.11.1
State Dependent #UD
In general, attempts of execute an instruction, which required OS support for incremental extended state component, will #UD if required state components were not enabled by OS. Table 2-37 lists instruction categories with
respect to required processor state components. Attempts to execute a given category of instructions while
enabled states were less than the required bit vector in XCR0 shown in Table 2-37 will cause #UD.
Table 2-37. OS XSAVE Enabling Requirements of Instruction Categories
Vector Register State Access
Required XCR0 Bit Vector [7:0]
Legacy SIMD prefix encoded Instructions (e.g SSE)
XMM
xxxxxx11b
VEX-encoded instructions operating on YMM
YMM
xxxxx111b
EVEX-encoded 128-bit instructions
ZMM
111xx111b
EVEX-encoded 256-bit instructions
ZMM
111xx111b
EVEX-encoded 512-bit instructions
ZMM
111xx111b
VEX-encoded instructions operating on opmask
k-reg
xx1xxx11b
Instruction Categories
2.6.11.2
Opcode Independent #UD
A number of bit fields in EVEX encoded instruction must obey mode-specific but opcode-independent patterns
listed in Table 2-38.
Table 2-38. Opcode Independent, State Dependent EVEX Bit Fields
Position
Notation
64-bit #UD
Non-64-bit #UD
P[3 : 2]
--
if > 0
if > 0
P[10]
--
if 0
if 0
P[1: 0]
EVEX.mm
if 00b
if 00b
P[7 : 6]
EVEX.RX
None (valid)
None (BOUND if EVEX.RX != 11b)
2.6.11.3
Opcode Dependent #UD
This section describes legal values for the rest of the EVEX bit fields. Table 2-39 lists the #UD conditions of EVEX
prefix bit fields which encodes or modifies register operands.
Table 2-39. #UD Conditions of Operand-Encoding EVEX Prefix Bit Fields
Notation
2-42 Vol. 2A
Position
Operand Encoding
64-bit #UD
Non-64-bit #UD
INSTRUCTION FORMAT
Table 2-39. #UD Conditions of Operand-Encoding EVEX Prefix Bit Fields (Contd.)
EVEX.R
EVEX.X
EVEX.B
EVEXR’
EVEX.vvvv
EVEXV’
P[7]
P[6]
P[5]
P[4]
P[14 : 11]
P[19]
ModRM.reg encodes k-reg
if EVEX.R = 0
ModRM.reg is opcode extension
None (ignored)
ModRM.reg encodes all other registers
None (valid)
ModRM.r/m encodes ZMM/YMM/XMM
None (valid)
ModRM.r/m encodes k-reg or GPR
None (ignored)
ModRM.r/m without SIB/VSIB
None (ignored)
ModRM.r/m with SIB/VSIB
None (valid)
ModRM.r/m encodes k-reg
None (ignored)
ModRM.r/m encodes other registers
None (valid)
ModRM.r/m base present
None (valid)
ModRM.r/m base not present
None (ignored)
ModRM.reg encodes k-reg or GPR
if 0
None (BOUND if
EVEX.RX != 11b)
None (ignored)
None (ignored)
ModRM.reg is opcode extension
None (ignored)
ModRM.reg encodes ZMM/YMM/XMM
None (valid)
vvvv encodes ZMM/YMM/XMM
None (valid)
None (valid)
P[14] ignored
Otherwise
if != 1111b
if != 1111b
Encodes ZMM/YMM/XMM
None (valid)
if 0
Otherwise
if 0
if 0
Table 2-40 lists the #UD conditions of instruction encoding of opmask register using EVEX.aaa and EVEX.z
Table 2-40. #UD Conditions of Opmask Related Encoding Field
Notation
EVEX.aaa
EVEX.z
Position
P[18 : 16]
P[23]
Operand Encoding
Instructions do not use opmask for conditional
64-bit #UD
processing1.
Non-64-bit #UD
if aaa != 000b
if aaa != 000b
Opmask used as conditional processing mask and updated
at completion2.
if aaa = 000b
if aaa = 000b;
Opmask used as conditional processing.
None (valid3)
None (valid1)
Vector instruction using opmask as source or destination4.
if EVEX.z != 0
if EVEX.z != 0
Store instructions or gather/scatter instructions.
if EVEX.z != 0
if EVEX.z != 0
Instruction supporting conditional processing mask with
EVEX.aaa = 000b.
if EVEX.z != 0
if EVEX.z != 0
NOTES:
1. E.g., VBROADCASTMxxx, VPMOVM2x, VPMOVx2M.
2. E.g., Gather/Scatter family.
3. aaa can take any value. A value of 000 indicates that there is no masking on the instruction; in this case, all elements will be processed as if there was a mask of ‘all ones’ regardless of the actual value in K0.
4. E.g., VFPCLASSPD/PS, VCMPB/D/Q/W family, VPMOVM2x, VPMOVx2M.
Table 2-41 lists the #UD conditions of EVEX bit fields that depends on the context of EVEX.b.
Table 2-41. #UD Conditions Dependent on EVEX.b Context
Notation
Position
Operand Encoding
64-bit #UD
Non-64-bit #UD
Vol. 2A 2-43
INSTRUCTION FORMAT
Table 2-41. #UD Conditions Dependent on EVEX.b Context (Contd.)
EVEX.L’Lb
P[22 : 20]
Reg-reg, FP instructions with rounding semantic.
None (valid1)
None (valid1)
Other reg-reg, FP instructions that can cause #XF.
None (valid2)
None (valid2)
Other reg-mem instructions in Table 2-34.
None (valid3)
None (valid3)
Other instruction classes4 in Table 2-35.
If EVEX.b > 0
If EVEX.b > 0
NOTES:
1. L’L specifies rounding control, see Table 2-36, supports {er} syntax.
2. L’L specifies vector length, see Table 2-36, supports {sae} syntax.
3. L’L specifies vector length, see Table 2-36, supports embedded broadcast syntax
4. L’L specifies either vector length or ignored.
2.6.12
Device Not Available
EVEX-encoded instructions follow the same rules when it comes to generating #NM (Device Not Available) exception. In particular, it is generated when CR0.TS[bit 3]= 1.
2.6.13
Scalar Instructions
EVEX-encoded scalar SIMD instructions can access up to 32 registers in 64-bit mode. Scalar instructions support
masking (using the least significant bit of the opmask register), but broadcasting is not supported.
2.7
EXCEPTION CLASSIFICATIONS OF EVEX-ENCODED INSTRUCTIONS
The exception behavior of EVEX-encoded instructions can be classified into the classes shown in the rest of this
section. The classification of EVEX-encoded instructions follow a similar framework as those of AVX and AVX2
instructions using the VEX prefix. Exception types for EVEX-encoded instructions are named in the style of
“E##” or with a suffix “E##XX”. The “##” designation generally follows that of AVX/AVX2 instructions. The
majority of EVEX encoded instruction with “Load+op” semantic supports memory fault suppression, which is represented by E##. The instructions with “Load+op” semantic but do not support fault suppression are named
“E##NF”. A summary table of exception classes by class names are shown below.
Table 2-42. EVEX-Encoded Instruction Exception Class Summary
Exception Class
Instruction set
Mem arg
(#XM)
Type E1
Vector Moves/Load/Stores
Explicitly aligned, w/ fault suppression
None
Type E1NF
Vector Non-temporal Stores
Explicitly aligned, no fault suppression
None
Type E2
FP Vector Load+op
Support fault suppression
Yes
Type E2NF
FP Vector Load+op
No fault suppression
Yes
Type E3
FP Scalar/Partial Vector, Load+Op
Support fault suppression
Yes
Type E3NF
FP Scalar/Partial Vector, Load+Op
No fault suppression
Yes
Type E4
Integer Vector Load+op
Support fault suppression
No
Type E4NF
Integer Vector Load+op
No fault suppression
No
Type E5
Legacy-like Promotion
Varies, Support fault suppression
No
Type E5NF
Legacy-like Promotion
Varies, No fault suppression
No
Type E6
Post AVX Promotion
Varies, w/ fault suppression
No
Type E6NF
Post AVX Promotion
Varies, no fault suppression
No
2-44 Vol. 2A
INSTRUCTION FORMAT
Table 2-42. EVEX-Encoded Instruction Exception Class Summary
Exception Class
Instruction set
Mem arg
(#XM)
Type E7NM
Register-to-register op
None
None
Type E9NF
Miscellaneous 128-bit
Vector-length Specific, no fault suppression
None
Type E10
Non-XF Scalar
Vector Length ignored, w/ fault suppression
None
Type E10NF
Non-XF Scalar
Vector Length ignored, no fault suppression
None
Type E11
VCVTPH2PS
Half Vector Length, w/ fault suppression
Yes
Type E11NF
VCVTPS2PH
Half Vector Length, no fault suppression
Yes
Type E12
Gather and Scatter Family
VSIB addressing, w/ fault suppression
None
Type E12NP
Gather and Scatter Prefetch Family
VSIB addressing, w/o page fault
None
Table 2-43 lists EVEX-encoded instruction mnemonic by exception classes.
Table 2-43. EVEX Instructions in each Exception Class
Exception Class
Type E1
Type E1NF
Instruction
VMOVAPD, VMOVAPS, VMOVDQA32, VMOVDQA64
VMOVNTDQ, VMOVNTDQA, VMOVNTPD, VMOVNTPS
VADDPD, VADDPS, VCMPPD, VCMPPS, VCVTDQ2PS, VCVTPD2DQ, VCVTPD2PS, VCVTPS2DQ, VCVTTPD2DQ,
VCVTTPS2DQ, VDIVPD, VDIVPS, VFMADDxxxPD, VFMADDxxxPS, VFMSUBADDxxxPD, VFMSUBADDxxxPS,
VFMSUBxxxPD, VFMSUBxxxPS, VFNMADDxxxPD, VFNMADDxxxPS, VFNMSUBxxxPD, VFNMSUBxxxPS, VMAXPD,
VMAXPS, VMINPD, VMINPS, VMULPD, VMULPS, VSQRTPD, VSQRTPS, VSUBPD, VSUBPS
Type E2
VCVTPD2QQ, VCVTPD2UQQ, VCVTPD2UDQ, VCVTPS2UDQS, VCVTQQ2PD, VCVTQQ2PS, VCVTTPD2DQ,
VCVTTPD2QQ, VCVTTPD2UDQ, VCVTTPD2UQQ, VCVTTPS2DQ, VCVTTPS2UDQ, VCVTUDQ2PS, VCVTUQQ2PD,
VCVTUQQ2PS, VFIXUPIMMPD, VFIXUPIMMPS, VGETEXPPD, VGETEXPPS, VGETMANTPD, VGETMANTPS, VRANGEPD,
VRANGEPS, VREDUCEPD, VREDUCEPS, VRNDSCALEPD, VRNDSCALEPS, VSCALEFPD, VSCALEFPS, VRCP28PD,
VRCP28PS, VRSQRT28PD, VRSQRT28PS
VADDSD, VADDSS, VCMPSD, VCMPSS, VCVTPS2PD, VCVTSD2SS, VCVTSS2SD, VDIVSD, VDIVSS, VMAXSD, VMAXSS,
VMINSD, VMINSS, VMULSD, VMULSS, VSQRTSD, VSQRTSS, VSUBSD, VSUBSS
Type E3
Type E3NF
VCVTPS2QQ, VCVTPS2UQQ, VCVTTPS2QQ, VCVTTPS2UQQ, VFMADDxxxSD, VFMADDxxxSS, VFMSUBxxxSD,
VFMSUBxxxSS, VFNMADDxxxSD, VFNMADDxxxSS, VFNMSUBxxxSD, VFNMSUBxxxSS, VFIXUPIMMSD,
VFIXUPIMMSS, VGETEXPSD, VGETEXPSS, VGETMANTSD, VGETMANTSS, VRANGESD, VRANGESS, VREDUCESD,
VREDUCESS, VRNDSCALESD, VRNDSCALESS, VSCALEFSD, VSCALEFSS, VRCP28SD, VRCP28SS, VRSQRT28SD,
VRSQRT28SS
VCOMISD, VCOMISS, VCVTSD2SI, VCVTSI2SD, VCVTSI2SS, VCVTSS2SI, VCVTTSD2SI, VCVTTSS2SI, VUCOMISD,
VUCOMISS
VCVTSD2USI, VCVTTSD2USI, VCVTSS2USI, VCVTTSS2USI, VCVTUSI2SD, VCVTUSI2SS
Vol. 2A 2-45
INSTRUCTION FORMAT
Table 2-43. EVEX Instructions in each Exception Class (Contd.)
Exception Class
Instruction
VANDPD, VANDPS, VANDNPD, VANDNPS, VORPD, VORPS, VPABSD, VPABSQ, VPADDD, VPADDQ, VPANDD, VPANDQ,
VPANDND, VPANDNQ, VPCMPEQD, VPCMPEQQ, VPCMPGTD, VPCMPGTQ, VPMAXSD, VPMAXSQ, VPMAXUD,
VPMAXUQ, VPMINSD, VPMINSQ, VPMINUD, VPMINUQ, VPMULLD, VPMULLQ, VPMULUDQ, VPMULDQ, VPORD,
VPORQ, VPSUBD, VPSUBQ, VPXORD, VPXORQ, VXORPD, VXORPS, VPSLLVD, VPSLLVQ,
Type E4
VBLENDMPD, VBLENDMPS, VPBLENDMD, VPBLENDMQ, VFPCLASSPD, VFPCLASSPS, VPCMPD, VPCMPQ, VPCMPUD,
VPCMPUQ, VPLZCNTD, VPLZCNTQ, VPROLD, VPROLQ, (VPSLLD, VPSLLQ, VPSRAD, VPSRAQ, VPSRLD, VPSRLQ)1,
VPTERNLOGD, VPTERNLOGQ, VPTESTMD, VPTESTMQ, VPTESTNMD, VPTESTNMQ, VRCP14PD, VRCP14PS,
VRSQRT14PD, VRSQRT14PS, VPCONFLICTD, VPCONFLICTQ, VPSRAVW, VPSRAVD, VPSRAVW, VPSRAVQ,
VPMADD52LUQ, VPMADD52HUQ
VMOVUPD, VMOVUPS, VMOVDQU8, VMOVDQU16, VMOVDQU32, VMOVDQU64, VPCMPB, VPCMPW, VPCMPUB,
VPCMPUW, VEXPANDPD, VEXPANDPS, VPCOMPRESSD, VPCOMPRESSQ, VPEXPANDD, VPEXPANDQ,
VCOMPRESSPD, VCOMPRESSPS, VPABSB, VPABSW, VPADDB, VPADDW, VPADDSB, VPADDSW, VPADDUSB,
VPADDUSW, VPAVGB, VPAVGW, VPCMPEQB, VPCMPEQW, VPCMPGTB, VPCMPGTW, VPMAXSB, VPMAXSW,
VPMAXUB, VPMAXUW, VPMINSB, VPMINSW, VPMINUB, VPMINUW, VPMULHRSW, VPMULHUW, VPMULHW,
VPMULLW, VPSUBB, VPSUBW, VPSUBSB, VPSUBSW, VPTESTMB, VPTESTMW, VPTESTNMB, VPTESTNMW, VPSLLW,
VPSRAW, VPSRLW, VPSLLVW, VPSRLVW
E4.nb2
VPACKSSDW, VPACKUSDW VPSHUFD, VPUNPCKHDQ, VPUNPCKHQDQ, VPUNPCKLDQ, VPUNPCKLQDQ, VSHUFPD,
VSHUFPS, VUNPCKHPD, VUNPCKHPS, VUNPCKLPD, VUNPCKLPS, VPERMD, VPERMPS, VPERMPD, VPERMQ,
Type E4NF
E4NF.nb
2
Type E5
VALIGND, VALIGNQ, VPERMI2D, VPERMI2PS, VPERMI2PD, VPERMI2Q, VPERMT2D, VPERMT2PS, VPERMT2Q,
VPERMT2PD, VPERMILPD, VPERMILPS, VSHUFI32X4, VSHUFI64X2, VSHUFF32X4, VSHUFF64X2,
VPMULTISHIFTQB
VDBPSADBW, VPACKSSWB, VPACKUSWB, VPALIGNR, VPMADDWD, VPMADDUBSW, VMOVSHDUP, VMOVSLDUP,
VPSADBW, VPSHUFB, VPSHUFHW, VPSHUFLW, VPSLLDQ, VPSRLDQ, VPSLLW, VPSRAW, VPSRLW, (VPSLLD,
VPSLLQ, VPSRAD, VPSRAQ, VPSRLD, VPSRLQ)3, VPUNPCKHBW, VPUNPCKHWD, VPUNPCKLBW, VPUNPCKLWD,
VPERMW, VPERMI2W, VPERMT2W, VPERMB, VPERMI2B, VPERMT2B
VCVTDQ2PD, PMOVSXBW, PMOVSXBW, PMOVSXBD, PMOVSXBQ, PMOVSXWD, PMOVSXWQ, PMOVSXDQ,
PMOVZXBW, PMOVZXBD, PMOVZXBQ, PMOVZXWD, PMOVZXWQ, PMOVZXDQ
VCVTUDQ2PD
Type E5NF
VMOVDDUP
VBROADCASTSS, VBROADCASTSD, VBROADCASTF32X4, VBROADCASTI32X4, VPBROADCASTB, VPBROADCASTD,
VPBROADCASTW, VPBROADCASTQ,
Type E6
Type E6NF
Type
E7NM.1284
Type E7NM.
2-46 Vol. 2A
VBROADCASTF32X2, VBROADCASTF32X4, VBROADCASTF64X2, VBROADCASTF32X8, VBROADCASTF64X4,
VBROADCASTI32X2, VBROADCASTI32X4, VBROADCASTI64X2, VBROADCASTI32X8, VBROADCASTI64X4,
VFPCLASSSD, VFPCLASSSS, VPMOVQB, VPMOVSQB, VPMOVUSQB, VPMOVQW, VPMOVSQW, VPMOVUSQW,
VPMOVQD, VPMOVSQD, VPMOVUSQD, VPMOVDB, VPMOVSDB, VPMOVUSDB, VPMOVDW, VPMOVSDW,
VPMOVUSDW
VEXTRACTF32X4, VEXTRACTF64X2, VEXTRACTF32X8, VINSERTF32X4, VINSERTF64X2, VINSERTF64X4,
VINSERTF32X8, VINSERTI32X4, VINSERTI64X2, VINSERTI64X4, VINSERTI32X8, VEXTRACTI32X4,
VEXTRACTI64X2, VEXTRACTI32X8, VEXTRACTI64X4, VPBROADCASTMB2Q, VPBROADCASTMW2D, VPMOVWB,
VPMOVSWB, VPMOVUSWB
VMOVLHPS, VMOVHLPS
(VPBROADCASTD, VPBROADCASTQ, VPBROADCASTB, VPBROADCASTW)5, VPMOVM2B, VPMOVM2D, VPMOVM2Q,
VPMOVM2W, VPMOVB2M, VPMOVD2M, VPMOVQ2M, VPMOVW2M
INSTRUCTION FORMAT
Table 2-43. EVEX Instructions in each Exception Class (Contd.)
Exception Class
Instruction
Type E9NF
VEXTRACTPS, VINSERTPS, VMOVHPD, VMOVHPS, VMOVLPD, VMOVLPS, VMOVD, VMOVQ, VPEXTRB, VPEXTRD,
VPEXTRW, VPEXTRQ, VPINSRB, VPINSRD, VPINSRW, VPINSRQ
Type E10
VMOVSD, VMOVSS, VRCP14SD, VRCP14SS, VRSQRT14SD, VRSQRT14SS,
Type E10NF
(VCVTSI2SD, VCVTUSI2SD)6
Type E11
VCVTPH2PS, VCVTPS2PH
Type E12
VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHERQPD, VPGATHERDD, VPGATHERDQ, VPGATHERQD,
VPGATHERQQ, VPSCATTERDD, VPSCATTERDQ, VPSCATTERQD, VPSCATTERQQ, VSCATTERDPD, VSCATTERDPS,
VSCATTERQPD, VSCATTERQPS
Type E12NP
VGATHERPF0DPD, VGATHERPF0DPS, VGATHERPF0QPD, VGATHERPF0QPS, VGATHERPF1DPD, VGATHERPF1DPS,
VGATHERPF1QPD, VGATHERPF1QPS, VSCATTERPF0DPD, VSCATTERPF0DPS, VSCATTERPF0QPD,
VSCATTERPF0QPS, VSCATTERPF1DPD, VSCATTERPF1DPS, VSCATTERPF1QPD, VSCATTERPF1QPS
NOTES:
1. Operand encoding FVI tupletype with immediate.
2. Embedded broadcast is not supported with the “.nb” suffix.
3. Operand encoding M128 tupletype.
4. #UD raised if EVEX.L’L !=00b (VL=128).
5. The source operand is a general purpose register.
6. W0 encoding only.
Vol. 2A 2-47
INSTRUCTION FORMAT
2.7.1
Exceptions Type E1 and E1NF of EVEX-Encoded Instructions
EVEX-encoded instructions with memory alignment restrictions, and supporting memory fault suppression follow
exception class E1.
X
Invalid Opcode,
#UD
X
Device Not Available, #NM
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-44. Type E1 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
General Protection,
#GP(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and a memory address referencing the SS segment is in
a non-canonical form.
X
EVEX.512: Memory operand is not 64-byte aligned.
EVEX.256: Memory operand is not 32-byte aligned.
EVEX.128: Memory operand is not 16-byte aligned.
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
X
X
Page Fault
#PF(fault-code)
2-48 Vol. 2A
Cause of Exception
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
If fault suppression not set, and the memory address is in a non-canonical form.
X
X
If fault suppression not set, and a page fault.
INSTRUCTION FORMAT
EVEX-encoded instructions with memory alignment restrictions, but do not support memory fault suppression
follow exception class E1NF.
X
Invalid Opcode,
#UD
X
Device Not Available, #NM
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-45. Type E1NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
General Protection,
#GP(0)
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
X
EVEX.512: Memory operand is not 64-byte aligned.
EVEX.256: Memory operand is not 32-byte aligned.
EVEX.128: Memory operand is not 16-byte aligned.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
X
Page Fault
#PF(fault-code)
Cause of Exception
X
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
X
X
For a page fault.
Vol. 2A 2-49
INSTRUCTION FORMAT
2.7.2
Exceptions Type E2 of EVEX-Encoded Instructions
EVEX-encoded vector instructions with arithmetic semantic follow exception class E2.
X
X
X
Invalid Opcode,
#UD
X
Device Not Available, #NM
X
64-bit
X
Protected and
Compatibility
Virtual 8086
Exception
Real
Table 2-46. Type E2 Class Exception Conditions
If EVEX prefix present.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
General Protection, #GP(0)
X
X
Page Fault
#PF(fault-code)
2-50 Vol. 2A
X
If fault suppression not set, and a memory address referencing the SS segment is in a
non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in the CS,
DS, ES, FS or GS segments.
X
SIMD Floatingpoint Exception,
#XM
Cause of Exception
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
X
X
If fault suppression not set, and a page fault.
X
X
X
If an unmasked SIMD floating-point exception, {sae} or {er} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION FORMAT
2.7.3
Exceptions Type E3 and E3NF of EVEX-Encoded Instructions
EVEX-encoded scalar instructions with arithmetic semantic that support memory fault suppression follow exception class E3.
X
X
X
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-47. Type E3 Class Exception Conditions
Cause of Exception
If EVEX prefix present.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in
the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes
or less is made while the current privilege level is 3.
X
X
X
If an unmasked SIMD floating-point exception, {sae} or {er} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
SIMD Floating-point
Exception, #XM
X
Vol. 2A 2-51
INSTRUCTION FORMAT
EVEX-encoded scalar instructions with arithmetic semantic that do not support memory fault suppression follow
exception class E3NF.
X
X
X
Invalid Opcode, #UD
Device Not Available,
#NM
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-48. Type E3NF Class Exception Conditions
Cause of Exception
EVEX prefix.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes
or less is made while the current privilege level is 3.
X
X
X
If an unmasked SIMD floating-point exception, {sae} or {er} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
SIMD Floating-point
Exception, #XM
2-52 Vol. 2A
X
INSTRUCTION FORMAT
2.7.4
Exceptions Type E4 and E4NF of EVEX-Encoded Instructions
EVEX-encoded vector instructions that cause no SIMD FP exception and support memory fault suppression follow
exception class E4.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-49. Type E4 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0 and in E4.nb subclass (see E4.nb entries in Table 2-43).
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
X
X
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in
the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
Page Fault #PF(faultcode)
Cause of Exception
X
X
If fault suppression not set, and a page fault.
Vol. 2A 2-53
INSTRUCTION FORMAT
EVEX-encoded vector instructions that do not cause SIMD FP exception nor support memory fault suppression
follow exception class E4NF.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-50. Type E4NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0 and in E4NF.nb subclass (see E4NF.nb entries in Table 2-43).
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
2-54 Vol. 2A
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
Page Fault #PF(faultcode)
Cause of Exception
X
X
For a page fault.
INSTRUCTION FORMAT
2.7.5
Exceptions Type E5 and E5NF
EVEX-encoded scalar/partial-vector instructions that cause no SIMD FP exception and support memory fault
suppression follow exception class E5.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-51. Type E5 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
EVEX-encoded scalar/partial vector instructions that do not cause SIMD FP exception nor support memory fault
suppression follow exception class E5NF.
Vol. 2A 2-55
INSTRUCTION FORMAT
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-52. Type E5NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If an illegal address in the SS segment.
X
X
General Protection,
#GP(0)
Cause of Exception
If an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-56 Vol. 2A
INSTRUCTION FORMAT
2.7.6
Exceptions Type E6 and E6NF
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-53. Type E6 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
Invalid Opcode, #UD
Device Not Available,
#NM
X
Stack, SS(0)
General Protection,
#GP(0)
Cause of Exception
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
X
If fault suppression not set, and the memory address is in a non-canonical form.
Page Fault #PF(faultcode)
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
For 4 or 8 byte memory references if alignment checking is enabled and an
unaligned memory reference of 8 bytes or less is made while the current privilege
level is 3.
Vol. 2A 2-57
INSTRUCTION FORMAT
EVEX-encoded instructions that do not cause SIMD FP exception nor support memory fault suppression follow
exception class E6NF.
Invalid Opcode, #UD
Device Not Available,
#NM
Stack, SS(0)
General Protection,
#GP(0)
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-54. Type E6NF Class Exception Conditions
Cause of Exception
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If the memory address is in a non-canonical form.
Page Fault #PF(faultcode)
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
For 4 or 8 byte memory references if alignment checking is enabled and an
unaligned memory reference of 8 bytes or less is made while the current privilege
level is 3.
2-58 Vol. 2A
INSTRUCTION FORMAT
2.7.7
Exceptions Type E7NM
EVEX-encoded instructions that cause no SIMD FP exception and do not reference memory follow exception class
E7NM.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-55. Type E7NM Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• Instruction specific EVEX.L’L restriction not met.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
X
X
Cause of Exception
Vol. 2A 2-59
INSTRUCTION FORMAT
2.7.8
Exceptions Type E9 and E9NF
EVEX-encoded vector or partial-vector instructions that do not cause no SIMD FP exception and support memory
fault suppression follow exception class E9.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-56. Type E9 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 00b (VL=128).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-60 Vol. 2A
INSTRUCTION FORMAT
EVEX-encoded vector or partial-vector instructions that must be encoded with VEX.L’L = 0, do not cause SIMD FP
exception nor support memory fault suppression follow exception class E9NF.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-57. Type E9NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 00b (VL=128).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If an illegal address in the SS segment.
X
X
General Protection,
#GP(0)
Cause of Exception
If an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made while
the current privilege level is 3.
Vol. 2A 2-61
INSTRUCTION FORMAT
2.7.9
Exceptions Type E10
EVEX-encoded scalar instructions that ignore EVEX.L’L vector length encoding and do not cause no SIMD FP exception, support memory fault suppression follow exception class E10.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-58. Type E10 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-62 Vol. 2A
INSTRUCTION FORMAT
EVEX-encoded scalar instructions that must be encoded with VEX.L’L = 0, do not cause SIMD FP exception nor
support memory fault suppression follow exception class E10NF.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-59. Type E10NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
Vol. 2A 2-63
INSTRUCTION FORMAT
2.7.10
Exception Type E11 (EVEX-only, mem arg no AC, floating-point exceptions)
EVEX-encoded instructions that can cause SIMD FP exception, memory operand support fault suppression but do
not cause #AC follow exception class E11.
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-60. Type E11 Class Exception Conditions
X
X
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
If fault suppression not set, and an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
Page Fault #PF (faultcode)
2-64 Vol. 2A
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
SIMD Floating-Point
Exception, #XM
Cause of Exception
X
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
X
If fault suppression not set, and a page fault.
X
X
X
If an unmasked SIMD floating-point exception, {sae} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION FORMAT
2.7.11
Exception Type E12 and E12NP (VSIB mem arg, no AC, no floating-point exceptions)
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-61. Type E12 Class Exception Conditions
X
X
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
• If vvvv != 1111b.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
NA
If address size attribute is 16 bit.
X
X
X
X
If ModR/M.mod = ‘11b’.
X
X
X
X
If ModR/M.rm != ‘100b’.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If k0 is used (gather or scatter operation).
X
X
X
X
If index = destination register (gather operation).
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
Page Fault #PF (faultcode)
Cause of Exception
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
For a page fault.
Vol. 2A 2-65
INSTRUCTION FORMAT
EVEX-encoded prefetch instructions that do not cause #PF follow exception class E12NP.
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-62. Type E12NP Class Exception Conditions
X
X
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
NA
If address size attribute is 16 bit.
X
X
X
X
If ModR/M.mod = ‘11b’.
X
X
X
X
If ModR/M.rm != ‘100b’.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If k0 is used (gather or scatter operation).
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
2-66 Vol. 2A
Cause of Exception
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
INSTRUCTION FORMAT
2.8
EXCEPTION CLASSIFICATIONS OF OPMASK INSTRUCTIONS
The exception behavior of VEX-encoded opmask instructions are listed below.
Exception conditions of Opmask instructions that do not address memory are listed as Type K20.
Device Not Available,
#NM
X
X
X
X
64-bit
X
Protected and
Compatibility
Invalid Opcode, #UD
Virtual 80x86
Exception
Real
Table 2-63. TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)
X
X
Cause of Exception
If relevant CPUID feature flag is ‘0’.
If a VEX prefix is present.
X
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
If ModRM:[7:6] != 11b.
X
X
If CR0.TS[bit 3]=1.
Vol. 2A 2-67
INSTRUCTION FORMAT
Exception conditions of Opmask instructions that address memory are listed as Type K21.
X
X
X
64-bit
X
Protected and
Compatibility
Invalid Opcode, #UD
Virtual 80x86
Exception
Real
Table 2-64. TYPE K21 Exception Definition (VEX-Encoded OpMask Instructions Addressing Memory)
X
X
X
X
X
X
X
X
X
Stack, SS(0)
X
X
X
X
If CR0.TS[bit 3]=1.
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null
segment selector.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
If relevant CPUID feature flag is ‘0’.
If a VEX prefix is present.
X
Device Not Available,
#NM
Cause of Exception
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-68 Vol. 2A
CHAPTER 3
INSTRUCTION SET REFERENCE, A-L
This chapter describes the instruction set for the Intel 64 and IA-32 architectures (A-L) in IA-32e, protected,
virtual-8086, and real-address modes of operation. The set includes general-purpose, x87 FPU, MMX,
SSE/SSE2/SSE3/SSSE3/SSE4, AESNI/PCLMULQDQ, AVX and system instructions. See also Chapter 4, “Instruction
Set Reference, M-U,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, and
Chapter 5, “Instruction Set Reference, V-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2C.
For each instruction, each operand combination is described. A description of the instruction and its operand, an
operational description, a description of the effect of the instructions on flags in the EFLAGS register, and a
summary of exceptions that can be generated are also provided.
3.1
INTERPRETING THE INSTRUCTION REFERENCE PAGES
This section describes the format of information contained in the instruction reference pages in this chapter. It
explains notational conventions and abbreviations used in these sections.
3.1.1
Instruction Format
The following is an example of the format used for each instruction description in this chapter. The heading below
introduces the example. The table below provides an example summary table.
CMC—Complement Carry Flag [this is an example]
Opcode
Instruction
Op/En
64/32-bit CPUID
Description
Mode
Feature Flag
F5
CMC
A
V/V
NP
Complement carry flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
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3.1.1.1
Opcode Column in the Instruction Summary Table (Instructions without VEX Prefix)
The “Opcode” column in the table above shows the object code produced for each form of the instruction. When
possible, codes are given as hexadecimal bytes in the same order in which they appear in memory. Definitions of
entries other than hexadecimal bytes are as follows:
•
REX.W — Indicates the use of a REX prefix that affects operand size or instruction semantics. The ordering of
the REX prefix and other optional/mandatory instruction prefixes are discussed Chapter 2. Note that REX
prefixes that promote legacy instructions to 64-bit behavior are not listed explicitly in the opcode column.
•
/digit — A digit between 0 and 7 indicates that the ModR/M byte of the instruction uses only the r/m (register
or memory) operand. The reg field contains the digit that provides an extension to the instruction's opcode.
•
•
/r — Indicates that the ModR/M byte of the instruction contains a register operand and an r/m operand.
cb, cw, cd, cp, co, ct — A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-byte (cp), 8-byte (co) or 10-byte (ct) value
following the opcode. This value is used to specify a code offset and possibly a new value for the code segment
register.
•
ib, iw, id, io — A 1-byte (ib), 2-byte (iw), 4-byte (id) or 8-byte (io) immediate operand to the instruction that
follows the opcode, ModR/M bytes or scale-indexing bytes. The opcode determines if the operand is a signed
value. All words, doublewords and quadwords are given with the low-order byte first.
•
+rb, +rw, +rd, +ro — Indicated the lower 3 bits of the opcode byte is used to encode the register operand
without a modR/M byte. The instruction lists the corresponding hexadecimal value of the opcode byte with low
3 bits as 000b. In non-64-bit mode, a register code, from 0 through 7, is added to the hexadecimal value of the
opcode byte. In 64-bit mode, indicates the four bit field of REX.b and opcode[2:0] field encodes the register
operand of the instruction. “+ro” is applicable only in 64-bit mode. See Table 3-1 for the codes.
•
+i — A number used in floating-point instructions when one of the operands is ST(i) from the FPU register stack.
The number i (which can range from 0 to 7) is added to the hexadecimal byte given at the left of the plus sign
to form a single opcode byte.
Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro
0
RAX
None
Reg Field
REX.B
Register
quadword register
(64-Bit Mode only)
Reg Field
REX.B
Register
dword register
Reg Field
REX.B
Register
word register
Reg Field
REX.B
Register
byte register
AL
None
0
AX
None
0
EAX
None
0
CL
None
1
CX
None
1
ECX
None
1
RCX
None
1
DL
None
2
DX
None
2
EDX
None
2
RDX
None
2
BL
None
3
BX
None
3
EBX
None
3
RBX
None
3
AH
Not
encodab
le (N.E.)
4
SP
None
4
ESP
None
4
N/A
N/A
N/A
CH
N.E.
5
BP
None
5
EBP
None
5
N/A
N/A
N/A
DH
N.E.
6
SI
None
6
ESI
None
6
N/A
N/A
N/A
BH
N.E.
7
DI
None
7
EDI
None
7
N/A
N/A
N/A
SPL
Yes
4
SP
None
4
ESP
None
4
RSP
None
4
BPL
Yes
5
BP
None
5
EBP
None
5
RBP
None
5
SIL
Yes
6
SI
None
6
ESI
None
6
RSI
None
6
DIL
Yes
7
DI
None
7
EDI
None
7
RDI
None
7
Registers R8 - R15 (see below): Available in 64-Bit Mode Only
R8L
Yes
0
R8W
Yes
0
R8D
Yes
0
R8
Yes
0
R9L
Yes
1
R9W
Yes
1
R9D
Yes
1
R9
Yes
1
R10L
Yes
2
R10W
Yes
2
R10D
Yes
2
R10
Yes
2
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INSTRUCTION SET REFERENCE, A-L
Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro (Contd.)
Reg Field
REX.B
Register
quadword register
(64-Bit Mode only)
Reg Field
REX.B
Register
dword register
Reg Field
REX.B
Register
word register
Reg Field
REX.B
Register
byte register
R11L
Yes
3
R11W
Yes
3
R11D
Yes
3
R11
Yes
3
R12L
Yes
4
R12W
Yes
4
R12D
Yes
4
R12
Yes
4
R13L
Yes
5
R13W
Yes
5
R13D
Yes
5
R13
Yes
5
R14L
Yes
6
R14W
Yes
6
R14D
Yes
6
R14
Yes
6
R15L
Yes
7
R15W
Yes
7
R15D
Yes
7
R15
Yes
7
3.1.1.2
Opcode Column in the Instruction Summary Table (Instructions with VEX prefix)
In the Instruction Summary Table, the Opcode column presents each instruction encoded using the VEX prefix in
following form (including the modR/M byte if applicable, the immediate byte if applicable):
VEX.[NDS].[128,256].[66,F2,F3].0F/0F3A/0F38.[W0,W1] opcode [/r] [/ib,/is4]
•
VEX — Indicates the presence of the VEX prefix is required. The VEX prefix can be encoded using the threebyte form (the first byte is C4H), or using the two-byte form (the first byte is C5H). The two-byte form of VEX
only applies to those instructions that do not require the following fields to be encoded: VEX.mmmmm, VEX.W,
VEX.X, VEX.B. Refer to Section 2.3 for more detail on the VEX prefix.
The encoding of various sub-fields of the VEX prefix is described using the following notations:
— NDS, NDD, DDS: Specifies that VEX.vvvv field is valid for the encoding of a register operand:
•
VEX.NDS: VEX.vvvv encodes the first source register in an instruction syntax where the content of
source registers will be preserved.
•
•
VEX.NDD: VEX.vvvv encodes the destination register that cannot be encoded by ModR/M:reg field.
•
VEX.DDS: VEX.vvvv encodes the second source register in a three-operand instruction syntax where
the content of first source register will be overwritten by the result.
If none of NDS, NDD, and DDS is present, VEX.vvvv must be 1111b (i.e. VEX.vvvv does not encode an
operand). The VEX.vvvv field can be encoded using either the 2-byte or 3-byte form of the VEX prefix.
— 128,256: VEX.L field can be 0 (denoted by VEX.128 or VEX.LZ) or 1 (denoted by VEX.256). The VEX.L field
can be encoded using either the 2-byte or 3-byte form of the VEX prefix. The presence of the notation
VEX.256 or VEX.128 in the opcode column should be interpreted as follows:
•
If VEX.256 is present in the opcode column: The semantics of the instruction must be encoded with
VEX.L = 1. An attempt to encode this instruction with VEX.L= 0 can result in one of two situations: (a)
if VEX.128 version is defined, the processor will behave according to the defined VEX.128 behavior; (b)
an #UD occurs if there is no VEX.128 version defined.
•
If VEX.128 is present in the opcode column but there is no VEX.256 version defined for the same
opcode byte: Two situations apply: (a) For VEX-encoded, 128-bit SIMD integer instructions, software
must encode the instruction with VEX.L = 0. The processor will treat the opcode byte encoded with
VEX.L= 1 by causing an #UD exception; (b) For VEX-encoded, 128-bit packed floating-point instructions, software must encode the instruction with VEX.L = 0. The processor will treat the opcode byte
encoded with VEX.L= 1 by causing an #UD exception (e.g. VMOVLPS).
•
If VEX.LIG is present in the opcode column: The VEX.L value is ignored. This generally applies to VEXencoded scalar SIMD floating-point instructions. Scalar SIMD floating-point instruction can be distinguished from the mnemonic of the instruction. Generally, the last two letters of the instruction
mnemonic would be either “SS“, “SD“, or “SI“ for SIMD floating-point conversion instructions.
•
If VEX.LZ is present in the opcode column: The VEX.L must be encoded to be 0B, an #UD occurs if
VEX.L is not zero.
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INSTRUCTION SET REFERENCE, A-L
— 66,F2,F3: The presence or absence of these values map to the VEX.pp field encodings. If absent, this
corresponds to VEX.pp=00B. If present, the corresponding VEX.pp value affects the “opcode” byte in the
same way as if a SIMD prefix (66H, F2H or F3H) does to the ensuing opcode byte. Thus a non-zero encoding
of VEX.pp may be considered as an implied 66H/F2H/F3H prefix. The VEX.pp field may be encoded using
either the 2-byte or 3-byte form of the VEX prefix.
— 0F,0F3A,0F38: The presence maps to a valid encoding of the VEX.mmmmm field. Only three encoded
values of VEX.mmmmm are defined as valid, corresponding to the escape byte sequence of 0FH, 0F3AH
and 0F38H. The effect of a valid VEX.mmmmm encoding on the ensuing opcode byte is same as if the corresponding escape byte sequence on the ensuing opcode byte for non-VEX encoded instructions. Thus a valid
encoding of VEX.mmmmm may be consider as an implies escape byte sequence of either 0FH, 0F3AH or
0F38H. The VEX.mmmmm field must be encoded using the 3-byte form of VEX prefix.
— 0F,0F3A,0F38 and 2-byte/3-byte VEX: The presence of 0F3A and 0F38 in the opcode column implies
that opcode can only be encoded by the three-byte form of VEX. The presence of 0F in the opcode column
does not preclude the opcode to be encoded by the two-byte of VEX if the semantics of the opcode does not
require any subfield of VEX not present in the two-byte form of the VEX prefix.
— W0: VEX.W=0.
— W1: VEX.W=1.
— The presence of W0/W1 in the opcode column applies to two situations: (a) it is treated as an extended
opcode bit, (b) the instruction semantics support an operand size promotion to 64-bit of a general-purpose
register operand or a 32-bit memory operand. The presence of W1 in the opcode column implies the opcode
must be encoded using the 3-byte form of the VEX prefix. The presence of W0 in the opcode column does
not preclude the opcode to be encoded using the C5H form of the VEX prefix, if the semantics of the opcode
does not require other VEX subfields not present in the two-byte form of the VEX prefix. Please see Section
2.3 on the subfield definitions within VEX.
— WIG: can use C5H form (if not requiring VEX.mmmmm) or VEX.W value is ignored in the C4H form of VEX
prefix.
— If WIG is present, the instruction may be encoded using either the two-byte form or the three-byte form of
VEX. When encoding the instruction using the three-byte form of VEX, the value of VEX.W is ignored.
•
•
opcode — Instruction opcode.
•
In general, the encoding o f VEX.R, VEX.X, VEX.B field are not shown explicitly in the opcode column. The
encoding scheme of VEX.R, VEX.X, VEX.B fields must follow the rules defined in Section 2.3.
/is4 — An 8-bit immediate byte is present containing a source register specifier in either imm8[7:4] (for 64bit mode) or imm8[6:4] (for 32-bit mode), and instruction-specific payload in imm8[3:0].
EVEX.[NDS/NDD/DDS].[128,256,512,LIG].[66,F2,F3].0F/0F3A/0F38.[W0,W1,WIG] opcode [/r] [ib]
•
EVEX — The EVEX prefix is encoded using the four-byte form (the first byte is 62H). Refer to Section 2.6.1 for
more detail on the EVEX prefix.
The encoding of various sub-fields of the EVEX prefix is described using the following notations:
— NDS, NDD, DDS: implies that EVEX.vvvv (and EVEX.v’) field is valid for the encoding of an operand. It may
specify either the source register (NDS) or the destination register (NDD). DDS expresses a syntax where
vvvv encodes the second source register in a three-operand instruction syntax where the content of first
source register will be overwritten by the result. If both NDS and NDD absent (i.e. EVEX.vvvv does not
encode an operand), EVEX.vvvv must be 1111b (and EVEX.v’ must be 1b).
— 128, 256, 512, LIG: This corresponds to the vector length; three values are allowed by EVEX: 512-bit,
256-bit and 128-bit. Alternatively, vector length is ignored (LIG) for certain instructions; this typically
applies to scalar instructions operating on one data element of a vector register.
— 66,F2,F3: The presence of these value maps to the EVEX.pp field encodings. The corresponding VEX.pp
value affects the “opcode” byte in the same way as if a SIMD prefix (66H, F2H or F3H) does to the ensuing
opcode byte. Thus a non-zero encoding of VEX.pp may be considered as an implied 66H/F2H/F3H prefix.
— 0F,0F3A,0F38: The presence maps to a valid encoding of the EVEX.mmm field. Only three encoded values
of EVEX.mmm are defined as valid, corresponding to the escape byte sequence of 0FH, 0F3AH and 0F38H.
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INSTRUCTION SET REFERENCE, A-L
The effect of a valid EVEX.mmm encoding on the ensuing opcode byte is the same as if the corresponding
escape byte sequence on the ensuing opcode byte for non-EVEX encoded instructions. Thus a valid
encoding of EVEX.mmm may be considered as an implied escape byte sequence of either 0FH, 0F3AH or
0F38H.
— W0: EVEX.W=0.
— W1: EVEX.W=1.
— WIG: EVEX.W bit ignored
•
•
opcode — Instruction opcode.
In general, the encoding of EVEX.R and R’, EVEX.X and X’, and EVEX.B and B’ fields are not shown explicitly in
the opcode column.
3.1.1.3
Instruction Column in the Opcode Summary Table
The “Instruction” column gives the syntax of the instruction statement as it would appear in an ASM386 program.
The following is a list of the symbols used to represent operands in the instruction statements:
•
rel8 — A relative address in the range from 128 bytes before the end of the instruction to 127 bytes after the
end of the instruction.
•
rel16, rel32 — A relative address within the same code segment as the instruction assembled. The rel16
symbol applies to instructions with an operand-size attribute of 16 bits; the rel32 symbol applies to instructions
with an operand-size attribute of 32 bits.
•
ptr16:16, ptr16:32 — A far pointer, typically to a code segment different from that of the instruction. The
notation 16:16 indicates that the value of the pointer has two parts. The value to the left of the colon is a 16bit selector or value destined for the code segment register. The value to the right corresponds to the offset
within the destination segment. The ptr16:16 symbol is used when the instruction's operand-size attribute is
16 bits; the ptr16:32 symbol is used when the operand-size attribute is 32 bits.
•
r8 — One of the byte general-purpose registers: AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL and SIL; or one
of the byte registers (R8L - R15L) available when using REX.R and 64-bit mode.
•
r16 — One of the word general-purpose registers: AX, CX, DX, BX, SP, BP, SI, DI; or one of the word registers
(R8-R15) available when using REX.R and 64-bit mode.
•
r32 — One of the doubleword general-purpose registers: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI; or one of
the doubleword registers (R8D - R15D) available when using REX.R in 64-bit mode.
•
r64 — One of the quadword general-purpose registers: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8–R15.
These are available when using REX.R and 64-bit mode.
•
imm8 — An immediate byte value. The imm8 symbol is a signed number between –128 and +127 inclusive.
For instructions in which imm8 is combined with a word or doubleword operand, the immediate value is signextended to form a word or doubleword. The upper byte of the word is filled with the topmost bit of the
immediate value.
•
imm16 — An immediate word value used for instructions whose operand-size attribute is 16 bits. This is a
number between –32,768 and +32,767 inclusive.
•
imm32 — An immediate doubleword value used for instructions whose operand-size attribute is 32
bits. It allows the use of a number between +2,147,483,647 and –2,147,483,648 inclusive.
•
imm64 — An immediate quadword value used for instructions whose operand-size attribute is 64 bits.
The value allows the use of a number between +9,223,372,036,854,775,807 and –
9,223,372,036,854,775,808 inclusive.
•
r/m8 — A byte operand that is either the contents of a byte general-purpose register (AL, CL, DL, BL, AH, CH,
DH, BH, BPL, SPL, DIL and SIL) or a byte from memory. Byte registers R8L - R15L are available using REX.R in
64-bit mode.
•
r/m16 — A word general-purpose register or memory operand used for instructions whose operand-size
attribute is 16 bits. The word general-purpose registers are: AX, CX, DX, BX, SP, BP, SI, DI. The contents of
memory are found at the address provided by the effective address computation. Word registers R8W - R15W
are available using REX.R in 64-bit mode.
Vol. 2A 3-5
INSTRUCTION SET REFERENCE, A-L
•
r/m32 — A doubleword general-purpose register or memory operand used for instructions whose operandsize attribute is 32 bits. The doubleword general-purpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI,
EDI. The contents of memory are found at the address provided by the effective address computation.
Doubleword registers R8D - R15D are available when using REX.R in 64-bit mode.
•
r/m64 — A quadword general-purpose register or memory operand used for instructions whose operand-size
attribute is 64 bits when using REX.W. Quadword general-purpose registers are: RAX, RBX, RCX, RDX, RDI,
RSI, RBP, RSP, R8–R15; these are available only in 64-bit mode. The contents of memory are found at the
address provided by the effective address computation.
•
•
m — A 16-, 32- or 64-bit operand in memory.
•
m16 — A word operand in memory, usually expressed as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions.
•
m32 — A doubleword operand in memory, usually expressed as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions.
•
•
•
m64 — A memory quadword operand in memory.
m8 — A byte operand in memory, usually expressed as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. In 64-bit mode, it is pointed to by the RSI or RDI registers.
m128 — A memory double quadword operand in memory.
m16:16, m16:32 & m16:64 — A memory operand containing a far pointer composed of two numbers. The
number to the left of the colon corresponds to the pointer's segment selector. The number to the right
corresponds to its offset.
•
m16&32, m16&16, m32&32, m16&64 — A memory operand consisting of data item pairs whose sizes are
indicated on the left and the right side of the ampersand. All memory addressing modes are allowed. The
m16&16 and m32&32 operands are used by the BOUND instruction to provide an operand containing an upper
and lower bounds for array indices. The m16&32 operand is used by LIDT and LGDT to provide a word with
which to load the limit field, and a doubleword with which to load the base field of the corresponding GDTR and
IDTR registers. The m16&64 operand is used by LIDT and LGDT in 64-bit mode to provide a word with which to
load the limit field, and a quadword with which to load the base field of the corresponding GDTR and IDTR
registers.
•
moffs8, moffs16, moffs32, moffs64 — A simple memory variable (memory offset) of type byte, word, or
doubleword used by some variants of the MOV instruction. The actual address is given by a simple offset
relative to the segment base. No ModR/M byte is used in the instruction. The number shown with moffs
indicates its size, which is determined by the address-size attribute of the instruction.
•
Sreg — A segment register. The segment register bit assignments are ES = 0, CS = 1, SS = 2, DS = 3, FS = 4,
and GS = 5.
•
m32fp, m64fp, m80fp — A single-precision, double-precision, and double extended-precision (respectively)
floating-point operand in memory. These symbols designate floating-point values that are used as operands for
x87 FPU floating-point instructions.
•
m16int, m32int, m64int — A word, doubleword, and quadword integer (respectively) operand in memory.
These symbols designate integers that are used as operands for x87 FPU integer instructions.
•
•
•
•
ST or ST(0) — The top element of the FPU register stack.
•
mm/m64 — An MMX register or a 64-bit memory operand. The 64-bit MMX registers are: MM0 through MM7.
The contents of memory are found at the address provided by the effective address computation.
•
xmm — An XMM register. The 128-bit XMM registers are: XMM0 through XMM7; XMM8 through XMM15 are
available using REX.R in 64-bit mode.
•
xmm/m32— An XMM register or a 32-bit memory operand. The 128-bit XMM registers are XMM0 through
XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at
the address provided by the effective address computation.
ST(i) — The ith element from the top of the FPU register stack (i ← 0 through 7).
mm — An MMX register. The 64-bit MMX registers are: MM0 through MM7.
mm/m32 — The low order 32 bits of an MMX register or a 32-bit memory operand. The 64-bit MMX registers
are: MM0 through MM7. The contents of memory are found at the address provided by the effective address
computation.
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INSTRUCTION SET REFERENCE, A-L
•
xmm/m64 — An XMM register or a 64-bit memory operand. The 128-bit SIMD floating-point registers are
XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of
memory are found at the address provided by the effective address computation.
•
xmm/m128 — An XMM register or a 128-bit memory operand. The 128-bit XMM registers are XMM0 through
XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at
the address provided by the effective address computation.
•
— Indicates implied use of the XMM0 register.
When there is ambiguity, xmm1 indicates the first source operand using an XMM register and xmm2 the second
source operand using an XMM register.
Some instructions use the XMM0 register as the third source operand, indicated by . The use of the
third XMM register operand is implicit in the instruction encoding and does not affect the ModR/M encoding.
•
ymm — A YMM register. The 256-bit YMM registers are: YMM0 through YMM7; YMM8 through YMM15 are
available in 64-bit mode.
•
•
•
•
•
m256 — A 32-byte operand in memory. This nomenclature is used only with AVX instructions.
•
•
•
m512 — A 64-byte operand in memory.
•
{k1} — Without {z}: a mask register used as instruction writemask for instructions that do not allow zeroingmasking but support merging-masking. This corresponds to instructions that require the value of the aaa field
to be different than 0 (e.g., gather) and store-type instructions which allow only merging-masking.
•
k1 — A mask register used as a regular operand (either destination or source). The 64-bit k registers are: k0
through k7.
•
•
mV — A vector memory operand; the operand size is dependent on the instruction.
ymm/m256 — A YMM register or 256-bit memory operand.
— Indicates use of the YMM0 register as an implicit argument.
bnd — A 128-bit bounds register. BND0 through BND3.
mib — A memory operand using SIB addressing form, where the index register is not used in address calculation, Scale is ignored. Only the base and displacement are used in effective address calculation.
zmm/m512 — A ZMM register or 512-bit memory operand.
{k1}{z} — A mask register used as instruction writemask. The 64-bit k registers are: k1 through k7.
Writemask specification is available exclusively via EVEX prefix. The masking can either be done as a mergingmasking, where the old values are preserved for masked out elements or as a zeroing masking. The type of
masking is determined by using the EVEX.z bit.
vm32{x,y, z} — A vector array of memory operands specified using VSIB memory addressing. The array of
memory addresses are specified using a common base register, a constant scale factor, and a vector index
register with individual elements of 32-bit index value in an XMM register (vm32x), a YMM register (vm32y) or
a ZMM register (vm32z).
•
vm64{x,y, z} — A vector array of memory operands specified using VSIB memory addressing. The array of
memory addresses are specified using a common base register, a constant scale factor, and a vector index
register with individual elements of 64-bit index value in an XMM register (vm64x), a YMM register (vm64y) or
a ZMM register (vm64z).
•
zmm/m512/m32bcst — An operand that can be a ZMM register, a 512-bit memory location or a 512-bit
vector loaded from a 32-bit memory location.
•
zmm/m512/m64bcst — An operand that can be a ZMM register, a 512-bit memory location or a 512-bit
vector loaded from a 64-bit memory location.
•
•
— Indicates use of the ZMM0 register as an implicit argument.
•
{sae} — Indicates support for SAE (Suppress All Exceptions). This is used for instructions that support SAE,
but do not support embedded rounding control.
•
SRC1 — Denotes the first source operand in the instruction syntax of an instruction encoded with the
VEX/EVEX prefix and having two or more source operands.
{er} — Indicates support for embedded rounding control, which is only applicable to the register-register form
of the instruction. This also implies support for SAE (Suppress All Exceptions).
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•
SRC2 — Denotes the second source operand in the instruction syntax of an instruction encoded with the
VEX/EVEX prefix and having two or more source operands.
•
SRC3 — Denotes the third source operand in the instruction syntax of an instruction encoded with the
VEX/EVEX prefix and having three source operands.
•
•
SRC — The source in a single-source instruction.
DST — the destination in an instruction. This field is encoded by reg_field.
3.1.1.4
Operand Encoding Column in the Instruction Summary Table
The “operand encoding” column is abbreviated as Op/En in the Instruction Summary table heading. Instruction
operand encoding information is provided for each assembly instruction syntax using a letter to cross reference to
a row entry in the operand encoding definition table that follows the instruction summary table. The operand
encoding table in each instruction reference page lists each instruction operand (according to each instruction
syntax and operand ordering shown in the instruction column) relative to the ModRM byte, VEX.vvvv field or additional operand encoding placement.
EVEX encoded instructions employ compressed disp8*N encoding of the displacement bytes, where N is defined in
Table 2-34 and Table 2-35, according to tupletypes. The Op/En column of an EVEX encoded instruction uses an
abbreviation that corresponds to the tupletype abbreviation (and may include an additional abbreviation related to
ModR/M and vvvv encoding). Most EVEX encoded instructions with VEX encoded equivalent have the ModR/M and
vvvv encoding order. In such cases, the Tuple abbreviation is shown and the ModR/M, vvvv encoding abbreviation
may be omitted.
NOTES
•
•
3.1.1.5
The letters in the Op/En column of an instruction apply ONLY to the encoding definition table
immediately following the instruction summary table.
In the encoding definition table, the letter ‘r’ within a pair of parenthesis denotes the content of
the operand will be read by the processor. The letter ‘w’ within a pair of parenthesis denotes the
content of the operand will be updated by the processor.
64/32-bit Mode Column in the Instruction Summary Table
The “64/32-bit Mode” column indicates whether the opcode sequence is supported in (a) 64-bit mode or (b) the
Compatibility mode and other IA-32 modes that apply in conjunction with the CPUID feature flag associated
specific instruction extensions.
The 64-bit mode support is to the left of the ‘slash’ and has the following notation:
•
•
•
V — Supported.
•
•
•
N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit mode.
I — Not supported.
N.E. — Indicates an instruction syntax is not encodable in 64-bit mode (it may represent part of a sequence of
valid instructions in other modes).
N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode.
N.S. — Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not
supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior.
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The Compatibility/Legacy Mode support is to the right of the ‘slash’ and has the following notation:
• V — Supported.
• I — Not supported.
• N.E. — Indicates an Intel 64 instruction mnemonics/syntax that is not encodable; the opcode sequence is not
applicable as an individual instruction in compatibility mode or IA-32 mode. The opcode may represent a valid
sequence of legacy IA-32 instructions.
3.1.1.6
CPUID Support Column in the Instruction Summary Table
The fourth column holds abbreviated CPUID feature flags (e.g., appropriate bit in CPUID.1.ECX, CPUID.1.EDX
for SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AESNI/PCLMULQDQ/AVX/RDRAND support) that indicate processor
support for the instruction. If the corresponding flag is ‘0’, the instruction will #UD.
3.1.1.7
Description Column in the Instruction Summary Table
The “Description” column briefly explains forms of the instruction.
3.1.1.8
Description Section
Each instruction is then described by number of information sections. The “Description” section describes the
purpose of the instructions and required operands in more detail.
Summary of terms that may be used in the description section:
•
Legacy SSE — Refers to SSE, SSE2, SSE3, SSSE3, SSE4, AESNI, PCLMULQDQ and any future instruction sets
referencing XMM registers and encoded without a VEX prefix.
•
•
•
VEX.vvvv — The VEX bit field specifying a source or destination register (in 1’s complement form).
rm_field — shorthand for the ModR/M r/m field and any REX.B
reg_field — shorthand for the ModR/M reg field and any REX.R
3.1.1.9
Operation Section
The “Operation” section contains an algorithm description (frequently written in pseudo-code) for the instruction.
Algorithms are composed of the following elements:
•
•
Comments are enclosed within the symbol pairs “(*” and “*)”.
•
A register name implies the contents of the register. A register name enclosed in brackets implies the contents
of the location whose address is contained in that register. For example, ES:[DI] indicates the contents of the
location whose ES segment relative address is in register DI. [SI] indicates the contents of the address
contained in register SI relative to the SI register’s default segment (DS) or the overridden segment.
•
Parentheses around the “E” in a general-purpose register name, such as (E)SI, indicates that the offset is read
from the SI register if the address-size attribute is 16, from the ESI register if the address-size attribute is 32.
Parentheses around the “R” in a general-purpose register name, (R)SI, in the presence of a 64-bit register
definition such as (R)SI, indicates that the offset is read from the 64-bit RSI register if the address-size
attribute is 64.
•
Brackets are used for memory operands where they mean that the contents of the memory location is a
segment-relative offset. For example, [SRC] indicates that the content of the source operand is a segmentrelative offset.
•
•
A ← B indicates that the value of B is assigned to A.
Compound statements are enclosed in keywords, such as: IF, THEN, ELSE and FI for an if statement; DO and
OD for a do statement; or CASE... OF for a case statement.
The symbols =, ≠, >, <, ≥, and ≤ are relational operators used to compare two values: meaning equal, not
equal, greater or equal, less or equal, respectively. A relational expression such as A = B is TRUE if the value of
A is equal to B; otherwise it is FALSE.
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•
The expression “« COUNT” and “» COUNT” indicates that the destination operand should be shifted left or right
by the number of bits indicated by the count operand.
The following identifiers are used in the algorithmic descriptions:
•
OperandSize and AddressSize — The OperandSize identifier represents the operand-size attribute of the
instruction, which is 16, 32 or 64-bits. The AddressSize identifier represents the address-size attribute, which
is 16, 32 or 64-bits. For example, the following pseudo-code indicates that the operand-size attribute depends
on the form of the MOV instruction used.
IF Instruction = MOVW
THEN OperandSize ← 16;
ELSE
IF Instruction = MOVD
THEN OperandSize ← 32;
ELSE
IF Instruction = MOVQ
THEN OperandSize ← 64;
FI;
FI;
FI;
See “Operand-Size and Address-Size Attributes” in Chapter 3 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for guidelines on how these attributes are determined.
•
StackAddrSize — Represents the stack address-size attribute associated with the instruction, which has a
value of 16, 32 or 64-bits. See “Address-Size Attribute for Stack” in Chapter 6, “Procedure Calls, Interrupts, and
Exceptions,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
•
•
•
SRC — Represents the source operand.
DEST — Represents the destination operand.
VLMAX — The maximum vector register width pertaining to the instruction. This is not the vector-length
encoding in the instruction's prefix but is instead determined by the current value of XCR0. For existing
processors, VLMAX is 256 whenever XCR0.YMM[bit 2] is 1. Future processors may defined new bits in XCR0
whose setting may imply other values for VLMAX.
VLMAX Definition
XCR0 Component
VLMAX
XCR0.YMM
256
The following functions are used in the algorithmic descriptions:
•
ZeroExtend(value) — Returns a value zero-extended to the operand-size attribute of the instruction. For
example, if the operand-size attribute is 32, zero extending a byte value of –10 converts the byte from F6H to
a doubleword value of 000000F6H. If the value passed to the ZeroExtend function and the operand-size
attribute are the same size, ZeroExtend returns the value unaltered.
•
SignExtend(value) — Returns a value sign-extended to the operand-size attribute of the instruction. For
example, if the operand-size attribute is 32, sign extending a byte containing the value –10 converts the byte
from F6H to a doubleword value of FFFFFFF6H. If the value passed to the SignExtend function and the operandsize attribute are the same size, SignExtend returns the value unaltered.
•
SaturateSignedWordToSignedByte — Converts a signed 16-bit value to a signed 8-bit value. If the signed
16-bit value is less than –128, it is represented by the saturated value -128 (80H); if it is greater than 127, it
is represented by the saturated value 127 (7FH).
•
SaturateSignedDwordToSignedWord — Converts a signed 32-bit value to a signed 16-bit value. If the
signed 32-bit value is less than –32768, it is represented by the saturated value –32768 (8000H); if it is greater
than 32767, it is represented by the saturated value 32767 (7FFFH).
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•
SaturateSignedWordToUnsignedByte — Converts a signed 16-bit value to an unsigned 8-bit value. If the
signed 16-bit value is less than zero, it is represented by the saturated value zero (00H); if it is greater than
255, it is represented by the saturated value 255 (FFH).
•
SaturateToSignedByte — Represents the result of an operation as a signed 8-bit value. If the result is less
than –128, it is represented by the saturated value –128 (80H); if it is greater than 127, it is represented by
the saturated value 127 (7FH).
•
SaturateToSignedWord — Represents the result of an operation as a signed 16-bit value. If the result is less
than –32768, it is represented by the saturated value –32768 (8000H); if it is greater than 32767, it is
represented by the saturated value 32767 (7FFFH).
•
SaturateToUnsignedByte — Represents the result of an operation as a signed 8-bit value. If the result is less
than zero it is represented by the saturated value zero (00H); if it is greater than 255, it is represented by the
saturated value 255 (FFH).
•
SaturateToUnsignedWord — Represents the result of an operation as a signed 16-bit value. If the result is
less than zero it is represented by the saturated value zero (00H); if it is greater than 65535, it is represented
by the saturated value 65535 (FFFFH).
•
LowOrderWord(DEST * SRC) — Multiplies a word operand by a word operand and stores the least significant
word of the doubleword result in the destination operand.
•
HighOrderWord(DEST * SRC) — Multiplies a word operand by a word operand and stores the most
significant word of the doubleword result in the destination operand.
•
Push(value) — Pushes a value onto the stack. The number of bytes pushed is determined by the operand-size
attribute of the instruction. See the “Operation” subsection of the “PUSH—Push Word, Doubleword or
Quadword Onto the Stack” section in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2B.
•
Pop() — removes the value from the top of the stack and returns it. The statement EAX ← Pop(); assigns to
EAX the 32-bit value from the top of the stack. Pop will return either a word, a doubleword or a quadword
depending on the operand-size attribute. See the “Operation” subsection in the “POP—Pop a Value from the
Stack” section of Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
•
PopRegisterStack — Marks the FPU ST(0) register as empty and increments the FPU register stack pointer
(TOP) by 1.
•
•
Switch-Tasks — Performs a task switch.
Bit(BitBase, BitOffset) — Returns the value of a bit within a bit string. The bit string is a sequence of bits in
memory or a register. Bits are numbered from low-order to high-order within registers and within memory
bytes. If the BitBase is a register, the BitOffset can be in the range 0 to [15, 31, 63] depending on the mode
and register size. See Figure 3-1: the function Bit[RAX, 21] is illustrated.
63
31
21
0
Bit Offset ← 21
Figure 3-1. Bit Offset for BIT[RAX, 21]
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If BitBase is a memory address, the BitOffset can range has different ranges depending on the operand size
(see Table 3-2).
Table 3-2. Range of Bit Positions Specified by Bit Offset Operands
Operand Size
Immediate BitOffset
Register BitOffset
16
0 to 15
− 215 to 215 − 1
32
0 to 31
− 231 to 231 − 1
64
0 to 63
− 263 to 263 − 1
The addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where
DIV is signed division with rounding towards negative infinity and MOD returns a positive number (see
Figure 3-2).
7
5
0 7
BitBase +
0 7
BitBase
0
BitBase −
BitOffset ← +13
7
0 7
BitBase
0 7
BitBase −
5
0
BitBase −
BitOffset ← −
Figure 3-2. Memory Bit Indexing
3.1.1.10
Intel® C/C++ Compiler Intrinsics Equivalents Section
The Intel C/C++ compiler intrinsic functions give access to the full power of the Intel Architecture Instruction Set,
while allowing the compiler to optimize register allocation and instruction scheduling for faster execution. Most of
these functions are associated with a single IA instruction, although some may generate multiple instructions or
different instructions depending upon how they are used. In particular, these functions are used to invoke instructions that perform operations on vector registers that can hold multiple data elements. These SIMD instructions
use the following data types.
•
__m128, __m256 and __m512 can represent 4, 8 or 16 packed single-precision floating-point values, and are
used with the vector registers and SSE, AVX, or AVX-512 instruction set extension families. The __m128 data
type is also used with various single-precision floating-point scalar instructions that perform calculations using
only the lowest 32 bits of a vector register; the remaining bits of the result come from one of the sources or are
set to zero depending upon the instruction.
•
__m128d, __m256d and __m512d can represent 2, 4 or 8 packed double-precision floating-point values, and
are used with the vector registers and SSE, AVX, or AVX-512 instruction set extension families. The __m128d
data type is also used with various double-precision floating-point scalar instructions that perform calculations
using only the lowest 64 bits of a vector register; the remaining bits of the result come from one of the sources
or are set to zero depending upon the instruction.
•
__m128i, __m256i and __m512i can represent integer data in bytes, words, doublewords, quadwords, and
occasionally larger data types.
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Each of these data types incorporates in its name the number of bits it can hold. For example, the __m128 type
holds 128 bits, and because each single-precision floating-point value is 32 bits long the __m128 type holds
(128/32) or four values. Normally the compiler will allocate memory for these data types on an even multiple of the
size of the type. Such aligned memory locations may be faster to read and write than locations at other addresses.
These SIMD data types are not basic Standard C data types or C++ objects, so they may be used only with the
assignment operator, passed as function arguments, and returned from a function call. If you access the internal
members of these types directly, or indirectly by using them in a union, there may be side effects affecting optimization, so it is recommended to use them only with the SIMD instruction intrinsic functions described in this manual
or the Intel C/C++ compiler documentation.
Many intrinsic functions names are prefixed with an indicator of the vector length and suffixed by an indicator of
the vector element data type, although some functions do not follow the rules below. The prefixes are:
•
•
•
_mm_ indicates that the function operates on 128-bit (or sometimes 64-bit) vectors.
_mm256_ indicates the function operates on 256-bit vectors.
_mm512_ indicates that the function operates on 512-bit vectors.
The suffixes include:
•
_ps, which indicates a function that operates on packed single-precision floating-point data. Packed singleprecision floating-point data corresponds to arrays of the C/C++ type float with either 4, 8 or 16 elements.
Values of this type can be loaded from an array using the _mm_loadu_ps, _mm256_loadu_ps, or
_mm512_loadu_ps functions, or created from individual values using _mm_set_ps, _mm256_set_ps, or
_mm512_set_ps functions, and they can be stored in an array using _mm_storeu_ps, _mm256_storeu_ps, or
_mm512_storeu_ps.
•
_ss, which indicates a function that operates on scalar single-precision floating-point data. Single-precision
floating-point data corresponds to the C/C++ type float, and values of type float can be converted to type
__m128 for use with these functions using the _mm_set_ss function, and converted back using the
_mm_cvtss_f32 function. When used with functions that operate on packed single-precision floating-point data
the scalar element corresponds with the first packed value.
•
_pd, which indicates a function that operates on packed double-precision floating-point data. Packed doubleprecision floating-point data corresponds to arrays of the C/C++ type double with either 2, 4, or 8 elements.
Values of this type can be loaded from an array using the _mm_loadu_pd, _mm256_loadu_pd, or
_mm512_loadu_pd functions, or created from individual values using _mm_set_pd, _mm2566_set_pd, or
_mm512_set_pd functions, and they can be stored in an array using _mm_storeu_pd, _mm256_storeu_pd, or
_mm512_storeu_pd.
•
_sd, which indicates a function that operates on scalar double-precision floating-point data. Double-precision
floating-point data corresponds to the C/C++ type double, and values of type double can be converted to type
__m128d for use with these functions using the _mm_set_sd function, and converted back using the
_mm_cvtsd_f64 function. When used with functions that operate on packed double-precision floating-point
data the scalar element corresponds with the first packed value.
•
_epi8, which indicates a function that operates on packed 8-bit signed integer values. Packed 8-bit signed
integers correspond to an array of signed char with 16, 32 or 64 elements. Values of this type can be created
from individual elements using _mm_set_epi8, _mm256_set_epi8, or _mm512_set_epi8 functions.
•
_epi16, which indicates a function that operates on packed 16-bit signed integer values. Packed 16-bit signed
integers correspond to an array of short with 8, 16 or 32 elements. Values of this type can be created from
individual elements using _mm_set_epi16, _mm256_set_epi16, or _mm512_set_epi16 functions.
•
_epi32, which indicates a function that operates on packed 32-bit signed integer values. Packed 32-bit signed
integers correspond to an array of int with 4, 8 or 16 elements. Values of this type can be created from
individual elements using _mm_set_epi32, _mm256_set_epi32, or _mm512_set_epi32 functions.
•
_epi64, which indicates a function that operates on packed 64-bit signed integer values. Packed 64-bit signed
integers correspond to an array of long long (or long if it is a 64-bit data type) with 2, 4 or 8 elements. Values
of this type can be created from individual elements using _mm_set_epi32, _mm256_set_epi32, or
_mm512_set_epi32 functions.
•
_epu8, which indicates a function that operates on packed 8-bit unsigned integer values. Packed 8-bit unsigned
integers correspond to an array of unsigned char with 16, 32 or 64 elements.
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•
_epu16, which indicates a function that operates on packed 16-bit unsigned integer values. Packed 16-bit
unsigned integers correspond to an array of unsigned short with 8, 16 or 32 elements.
•
_epu32, which indicates a function that operates on packed 32-bit unsigned integer values. Packed 32-bit
unsigned integers correspond to an array of unsigned with 4, 8 or 16 elements.
•
_epu64, which indicates a function that operates on packed 64-bit unsigned integer values. Packed 64-bit
unsigned integers correspond to an array of unsigned long long (or unsigned long if it is a 64-bit data type) with
2, 4 or 8 elements.
•
•
•
_si128, which indicates a function that operates on a single 128-bit value of type __m128i.
_si256, which indicates a function that operates on a single a 256-bit value of type __m256i.
_si512, which indicates a function that operates on a single a 512-bit value of type __m512i.
Values of any packed integer type can be loaded from an array using the _mm_loadu_si128,
_mm256_loadu_si256, or _mm512_loadu_si512 functions, and they can be stored in an array using
_mm_storeu_si128, _mm256_storeu_si256, or _mm512_storeu_si512.
These functions and data types are used with the SSE, AVX, and AVX-512 instruction set extension families. In
addition there are similar functions that correspond to MMX instructions. These are less frequently used because
they require additional state management, and only operate on 64-bit packed integer values.
The declarations of Intel C/C++ compiler intrinsic functions may reference some non-standard data types, such as
__int64. The C Standard header stdint.h defines similar platform-independent types, and the documentation for
that header gives characteristics that apply to corresponding non-standard types according to the following table.
Table 3-3. Standard and Non-standard Data Types
Non-standard Type
Standard Type (from stdint.h)
__int64
int64_t
unsigned __int64
uint64_t
__int32
int32_t
unsigned __int32
uint32_t
__int16
int16_t
unsigned __int16
uint16_t
For a more detailed description of each intrinsic function and additional information related to its usage, refer to the
online Intel Intrinsics Guide, https://software.intel.com/sites/landingpage/IntrinsicsGuide.
3.1.1.11
Flags Affected Section
The “Flags Affected” section lists the flags in the EFLAGS register that are affected by the instruction. When a flag
is cleared, it is equal to 0; when it is set, it is equal to 1. The arithmetic and logical instructions usually assign
values to the status flags in a uniform manner (see Appendix A, “EFLAGS Cross-Reference,” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1). Non-conventional assignments are described in the
“Operation” section. The values of flags listed as undefined may be changed by the instruction in an indeterminate
manner. Flags that are not listed are unchanged by the instruction.
3.1.1.12
FPU Flags Affected Section
The floating-point instructions have an “FPU Flags Affected” section that describes how each instruction can affect
the four condition code flags of the FPU status word.
3.1.1.13
Protected Mode Exceptions Section
The “Protected Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in
protected mode and the reasons for the exceptions. Each exception is given a mnemonic that consists of a pound
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sign (#) followed by two letters and an optional error code in parentheses. For example, #GP(0) denotes a general
protection exception with an error code of 0. Table 3-4 associates each two-letter mnemonic with the corresponding exception vector and name. See Chapter 6, “Procedure Calls, Interrupts, and Exceptions,” in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for a detailed description of the exceptions.
Application programmers should consult the documentation provided with their operating systems to determine
the actions taken when exceptions occur.
Table 3-4. Intel 64 and IA-32 General Exceptions
Vector
Name
Source
Protected
Mode1
Real
Address
Mode
Virtual
8086
Mode
0
#DE—Divide Error
DIV and IDIV instructions.
Yes
Yes
Yes
1
#DB—Debug
Any code or data reference.
Yes
Yes
Yes
3
#BP—Breakpoint
INT 3 instruction.
Yes
Yes
Yes
4
#OF—Overflow
INTO instruction.
Yes
Yes
Yes
5
#BR—BOUND Range Exceeded
BOUND instruction.
Yes
Yes
Yes
6
#UD—Invalid Opcode (Undefined
Opcode)
UD2 instruction or reserved opcode.
Yes
Yes
Yes
7
#NM—Device Not Available (No
Math Coprocessor)
Floating-point or WAIT/FWAIT instruction.
Yes
Yes
Yes
8
#DF—Double Fault
Any instruction that can generate an
exception, an NMI, or an INTR.
Yes
Yes
Yes
10
#TS—Invalid TSS
Task switch or TSS access.
Yes
Reserved
Yes
11
#NP—Segment Not Present
Loading segment registers or accessing system
segments.
Yes
Reserved
Yes
12
#SS—Stack Segment Fault
Stack operations and SS register loads.
Yes
Yes
Yes
13
#GP—General Protection2
Any memory reference and other protection
checks.
Yes
Yes
Yes
14
#PF—Page Fault
Any memory reference.
Yes
Reserved
Yes
16
#MF—Floating-Point Error (Math
Fault)
Floating-point or WAIT/FWAIT instruction.
Yes
Yes
Yes
17
#AC—Alignment Check
Any data reference in memory.
Yes
Reserved
Yes
18
#MC—Machine Check
Model dependent machine check errors.
Yes
Yes
Yes
19
#XM—SIMD Floating-Point
Numeric Error
SSE/SSE2/SSE3 floating-point instructions.
Yes
Yes
Yes
NOTES:
1. Apply to protected mode, compatibility mode, and 64-bit mode.
2. In the real-address mode, vector 13 is the segment overrun exception.
3.1.1.14
Real-Address Mode Exceptions Section
The “Real-Address Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in
real-address mode (see Table 3-4).
3.1.1.15
Virtual-8086 Mode Exceptions Section
The “Virtual-8086 Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in
virtual-8086 mode (see Table 3-4).
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3.1.1.16
Floating-Point Exceptions Section
The “Floating-Point Exceptions” section lists exceptions that can occur when an x87 FPU floating-point instruction
is executed. All of these exception conditions result in a floating-point error exception (#MF, exception 16) being
generated. Table 3-5 associates a one- or two-letter mnemonic with the corresponding exception name. See
“Floating-Point Exception Conditions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, for a detailed description of these exceptions.
Table 3-5. x87 FPU Floating-Point Exceptions
Mnemonic
Name
Source
Floating-point invalid operation:
#IS
#IA
- Stack overflow or underflow
- x87 FPU stack overflow or underflow
- Invalid arithmetic operation
- Invalid FPU arithmetic operation
#Z
Floating-point divide-by-zero
Divide-by-zero
#D
Floating-point denormal operand
Source operand that is a denormal number
#O
Floating-point numeric overflow
Overflow in result
#U
Floating-point numeric underflow
Underflow in result
#P
Floating-point inexact result (precision)
Inexact result (precision)
3.1.1.17
SIMD Floating-Point Exceptions Section
The “SIMD Floating-Point Exceptions” section lists exceptions that can occur when an SSE/SSE2/SSE3 floatingpoint instruction is executed. All of these exception conditions result in a SIMD floating-point error exception (#XM,
exception 19) being generated. Table 3-6 associates a one-letter mnemonic with the corresponding exception
name. For a detailed description of these exceptions, refer to ”SSE and SSE2 Exceptions”, in Chapter 11 of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Table 3-6. SIMD Floating-Point Exceptions
Mnemonic
Name
Source
#I
Floating-point invalid operation
Invalid arithmetic operation or source operand
#Z
Floating-point divide-by-zero
Divide-by-zero
#D
Floating-point denormal operand
Source operand that is a denormal number
#O
Floating-point numeric overflow
Overflow in result
#U
Floating-point numeric underflow
Underflow in result
#P
Floating-point inexact result
Inexact result (precision)
3.1.1.18
Compatibility Mode Exceptions Section
This section lists exceptions that occur within compatibility mode.
3.1.1.19
64-Bit Mode Exceptions Section
This section lists exceptions that occur within 64-bit mode.
3-16 Vol. 2A
INSTRUCTION SET REFERENCE, A-L
3.2
INSTRUCTIONS (A-L)
The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions (A-L). See also: Chapter 4,
“Instruction Set Reference, M-U,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2B, and Chapter 5, “Instruction Set Reference, V-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2C.
Vol. 2A 3-17
INSTRUCTION SET REFERENCE, A-L
AAA—ASCII Adjust After Addition
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
37
AAA
NP
Invalid
Valid
ASCII adjust AL after addition.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied
source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD
instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The
AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.
If the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there
was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4
through 7 of the AL register are set to 0.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
IF ((AL AND 0FH) > 9) or (AF = 1)
THEN
AX ← AX + 106H;
AF ← 1;
CF ← 1;
ELSE
AF ← 0;
CF ← 0;
FI;
AL ← AL AND 0FH;
FI;
Flags Affected
The AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF,
SF, ZF, and PF flags are undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
3-18 Vol. 2A
AAA—ASCII Adjust After Addition
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAA—ASCII Adjust After Addition
Vol. 2A 3-19
INSTRUCTION SET REFERENCE, A-L
AAD—ASCII Adjust AX Before Division
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
D5 0A
AAD
NP
Invalid
Valid
ASCII adjust AX before division.
D5 ib
AAD imm8
NP
Invalid
Valid
Adjust AX before division to number base
imm8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the
AH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD
instruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the
AX register by an unpacked BCD value.
The AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H.
The value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10)
number in registers AH and AL.
The generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the
“Operation” section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH
for decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust
ASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine
code (D5 imm8).
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
tempAL ← AL;
tempAH ← AH;
AL ← (tempAL + (tempAH ∗ imm8)) AND FFH;
(* imm8 is set to 0AH for the AAD mnemonic.*)
AH ← 0;
FI;
The immediate value (imm8) is taken from the second byte of the instruction.
Flags Affected
The SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags
are undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
3-20 Vol. 2A
AAD—ASCII Adjust AX Before Division
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAD—ASCII Adjust AX Before Division
Vol. 2A 3-21
INSTRUCTION SET REFERENCE, A-L
AAM—ASCII Adjust AX After Multiply
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
D4 0A
AAM
NP
Invalid
Valid
ASCII adjust AX after multiply.
D4 ib
AAM imm8
NP
Invalid
Valid
Adjust AX after multiply to number base
imm8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD
values. The AX register is the implied source and destination operand for this instruction. The AAM instruction is
only useful when it follows an MUL instruction that multiplies (binary multiplication) two unpacked BCD values and
stores a word result in the AX register. The AAM instruction then adjusts the contents of the AX register to contain
the correct 2-digit unpacked (base 10) BCD result.
The generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked
digits of any number base (see the “Operation” section below). Here, the imm8 byte is set to the selected number
base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted
by all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the
instruction must be hand coded in machine code (D4 imm8).
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
tempAL ← AL;
AH ← tempAL / imm8; (* imm8 is set to 0AH for the AAM mnemonic *)
AL ← tempAL MOD imm8;
FI;
The immediate value (imm8) is taken from the second byte of the instruction.
Flags Affected
The SF, ZF, and PF flags are set according to the resulting binary value in the AL register. The OF, AF, and CF flags
are undefined.
Protected Mode Exceptions
#DE
If an immediate value of 0 is used.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
3-22 Vol. 2A
AAM—ASCII Adjust AX After Multiply
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAM—ASCII Adjust AX After Multiply
Vol. 2A 3-23
INSTRUCTION SET REFERENCE, A-L
AAS—ASCII Adjust AL After Subtraction
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
3F
AAS
NP
Invalid
Valid
ASCII adjust AL after subtraction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register
is the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows
a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte
result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1digit unpacked BCD result.
If the subtraction produced a decimal carry, the AH register decrements by 1, and the CF and AF flags are set. If no
decimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL
register is left with its top four bits set to 0.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-bit mode
THEN
#UD;
ELSE
IF ((AL AND 0FH) > 9) or (AF = 1)
THEN
AX ← AX – 6;
AH ← AH – 1;
AF ← 1;
CF ← 1;
AL ← AL AND 0FH;
ELSE
CF ← 0;
AF ← 0;
AL ← AL AND 0FH;
FI;
FI;
Flags Affected
The AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0. The OF, SF, ZF, and
PF flags are undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
3-24 Vol. 2A
AAS—ASCII Adjust AL After Subtraction
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAS—ASCII Adjust AL After Subtraction
Vol. 2A 3-25
INSTRUCTION SET REFERENCE, A-L
ADC—Add with Carry
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
14 ib
ADC AL, imm8
I
Valid
Valid
Add with carry imm8 to AL.
15 iw
ADC AX, imm16
I
Valid
Valid
Add with carry imm16 to AX.
15 id
ADC EAX, imm32
I
Valid
Valid
Add with carry imm32 to EAX.
REX.W + 15 id
ADC RAX, imm32
I
Valid
N.E.
Add with carry imm32 sign extended to 64bits to RAX.
80 /2 ib
ADC r/m8, imm8
MI
Valid
Valid
Add with carry imm8 to r/m8.
REX + 80 /2 ib
*
ADC r/m8 , imm8
MI
Valid
N.E.
Add with carry imm8 to r/m8.
81 /2 iw
ADC r/m16, imm16
MI
Valid
Valid
Add with carry imm16 to r/m16.
81 /2 id
ADC r/m32, imm32
MI
Valid
Valid
Add with CF imm32 to r/m32.
REX.W + 81 /2 id
ADC r/m64, imm32
MI
Valid
N.E.
Add with CF imm32 sign extended to 64-bits
to r/m64.
83 /2 ib
ADC r/m16, imm8
MI
Valid
Valid
Add with CF sign-extended imm8 to r/m16.
83 /2 ib
ADC r/m32, imm8
MI
Valid
Valid
Add with CF sign-extended imm8 into r/m32.
REX.W + 83 /2 ib
ADC r/m64, imm8
MI
Valid
N.E.
Add with CF sign-extended imm8 into r/m64.
10 /r
ADC r/m8, r8
MR
Valid
Valid
Add with carry byte register to r/m8.
REX + 10 /r
ADC r/m8*, r8*
MR
Valid
N.E.
Add with carry byte register to r/m64.
11 /r
ADC r/m16, r16
MR
Valid
Valid
Add with carry r16 to r/m16.
11 /r
ADC r/m32, r32
MR
Valid
Valid
Add with CF r32 to r/m32.
REX.W + 11 /r
ADC r/m64, r64
MR
Valid
N.E.
Add with CF r64 to r/m64.
12 /r
ADC r8, r/m8
RM
Valid
Valid
Add with carry r/m8 to byte register.
REX + 12 /r
ADC r8*, r/m8*
RM
Valid
N.E.
Add with carry r/m64 to byte register.
13 /r
ADC r16, r/m16
RM
Valid
Valid
Add with carry r/m16 to r16.
13 /r
ADC r32, r/m32
RM
Valid
Valid
Add with CF r/m32 to r32.
REX.W + 13 /r
ADC r64, r/m64
RM
Valid
N.E.
Add with CF r/m64 to r64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
I
AL/AX/EAX/RAX
imm8
NA
NA
Description
Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and
stores the result in the destination operand. The destination operand can be a register or a memory location; the
source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be
used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate
value is used as an operand, it is sign-extended to the length of the destination operand format.
3-26 Vol. 2A
ADC—Add with Carry
INSTRUCTION SET REFERENCE, A-L
The ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates
the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result,
respectively. The SF flag indicates the sign of the signed result.
The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is
followed by an ADC instruction.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← DEST + SRC + CF;
Intel C/C++ Compiler Intrinsic Equivalent
ADC:
extern unsigned char _addcarry_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *sum_out);
ADC:
extern unsigned char _addcarry_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short
*sum_out);
ADC:
extern unsigned char _addcarry_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *sum_out);
ADC:
extern unsigned char _addcarry_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64
*sum_out);
Flags Affected
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
ADC—Add with Carry
Vol. 2A 3-27
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-28 Vol. 2A
ADC—Add with Carry
INSTRUCTION SET REFERENCE, A-L
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
ADX
Description
RM
64/32bit
Mode
Support
V/V
66 0F 38 F6 /r
ADCX r32, r/m32
66 REX.w 0F 38 F6 /r
ADCX r64, r/m64
RM
V/NE
ADX
Unsigned addition of r64 with CF, r/m64 to r64, writes CF.
Unsigned addition of r32 with CF, r/m32 to r32, writes CF.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Performs an unsigned addition of the destination operand (first operand), the source operand (second operand)
and the carry-flag (CF) and stores the result in the destination operand. The destination operand is a generalpurpose register, whereas the source operand can be a general-purpose register or memory location. The state of
CF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the
unsigned addition of the operands.
The ADCX instruction is executed in the context of multi-precision addition, where we add a series of operands with
a carry-chain. At the beginning of a chain of additions, we need to make sure the CF is in a desired initial state.
Often, this initial state needs to be 0, which can be achieved with an instruction to zero the CF (e.g. XOR).
This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64bit mode.
In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to additional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64 bits.
ADCX executes normally either inside or outside a transaction region.
Note: ADCX defines the OF flag differently than the ADD/ADC instructions as defined in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Operation
IF OperandSize is 64-bit
THEN CF:DEST[63:0] ← DEST[63:0] + SRC[63:0] + CF;
ELSE CF:DEST[31:0] ← DEST[31:0] + SRC[31:0] + CF;
FI;
Flags Affected
CF is updated based on result. OF, SF, ZF, AF and PF flags are unmodified.
Intel C/C++ Compiler Intrinsic Equivalent
unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);
unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
SIMD Floating-Point Exceptions
None
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag
Vol. 2A 3-29
INSTRUCTION SET REFERENCE, A-L
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
selector.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-30 Vol. 2A
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag
INSTRUCTION SET REFERENCE, A-L
ADD—Add
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
04 ib
ADD AL, imm8
I
Valid
Valid
Add imm8 to AL.
05 iw
ADD AX, imm16
I
Valid
Valid
Add imm16 to AX.
05 id
ADD EAX, imm32
I
Valid
Valid
Add imm32 to EAX.
REX.W + 05 id
ADD RAX, imm32
I
Valid
N.E.
Add imm32 sign-extended to 64-bits to RAX.
80 /0 ib
ADD r/m8, imm8
MI
Valid
Valid
Add imm8 to r/m8.
REX + 80 /0 ib
ADD r/m8*, imm8
MI
Valid
N.E.
Add sign-extended imm8 to r/m64.
81 /0 iw
ADD r/m16, imm16
MI
Valid
Valid
Add imm16 to r/m16.
81 /0 id
ADD r/m32, imm32
MI
Valid
Valid
Add imm32 to r/m32.
REX.W + 81 /0 id
ADD r/m64, imm32
MI
Valid
N.E.
Add imm32 sign-extended to 64-bits to
r/m64.
83 /0 ib
ADD r/m16, imm8
MI
Valid
Valid
Add sign-extended imm8 to r/m16.
83 /0 ib
ADD r/m32, imm8
MI
Valid
Valid
Add sign-extended imm8 to r/m32.
REX.W + 83 /0 ib
ADD r/m64, imm8
MI
Valid
N.E.
Add sign-extended imm8 to r/m64.
00 /r
ADD r/m8, r8
MR
Valid
Valid
Add r8 to r/m8.
MR
Valid
N.E.
Add r8 to r/m8.
MR
Valid
Valid
Add r16 to r/m16.
*
*
REX + 00 /r
ADD r/m8 , r8
01 /r
ADD r/m16, r16
01 /r
ADD r/m32, r32
MR
Valid
Valid
Add r32 to r/m32.
REX.W + 01 /r
ADD r/m64, r64
MR
Valid
N.E.
Add r64 to r/m64.
02 /r
ADD r8, r/m8
RM
Valid
Valid
Add r/m8 to r8.
RM
Valid
N.E.
Add r/m8 to r8.
REX + 02 /r
*
ADD r8 , r/m8
*
03 /r
ADD r16, r/m16
RM
Valid
Valid
Add r/m16 to r16.
03 /r
ADD r32, r/m32
RM
Valid
Valid
Add r/m32 to r32.
REX.W + 03 /r
ADD r64, r/m64
RM
Valid
N.E.
Add r/m64 to r64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
I
AL/AX/EAX/RAX
imm8
NA
NA
Description
Adds the destination operand (first operand) and the source operand (second operand) and then stores the result
in the destination operand. The destination operand can be a register or a memory location; the source operand
can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one
instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination
operand format.
The ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer operands and sets the CF and OF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The
SF flag indicates the sign of the signed result.
ADD—Add
Vol. 2A 3-31
INSTRUCTION SET REFERENCE, A-L
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← DEST + SRC;
Flags Affected
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-32 Vol. 2A
ADD—Add
INSTRUCTION SET REFERENCE, A-L
ADDPD—Add Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 58 /r
ADDPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 58 /r
VADDPD xmm1,xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG 58 /r
VADDPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 58 /r
VADDPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 58 /r
VADDPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 58 /r
VADDPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
RVM
V/V
AVX
RVM
V/V
AVX
Add packed double-precision floating-point values from
ymm3/mem to ymm2 and store result in ymm1.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Add packed double-precision floating-point values from
xmm3/m128/m64bcst to xmm2 and store result in xmm1
with writemask k1.
Add packed double-precision floating-point values from
ymm3/m256/m64bcst to ymm2 and store result in ymm1
with writemask k1.
Add packed double-precision floating-point values from
zmm3/m512/m64bcst to zmm2 and store result in zmm1
with writemask k1.
Description
Add packed double-precision floating-point values from
xmm2/mem to xmm1 and store result in xmm1.
Add packed double-precision floating-point values from
xmm3/mem to xmm2 and store result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Add two, four or eight packed double-precision floating-point values from the first source operand to the second
source operand, and stores the packed double-precision floating-point results in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
Operation
VADDPD (EVEX encoded versions) when src2 operand is a vector register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
ADDPD—Add Packed Double-Precision Floating-Point Values
Vol. 2A 3-33
INSTRUCTION SET REFERENCE, A-L
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC1[i+63:i] + SRC2[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VADDPD (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i] SRC1[i+63:i] + SRC2[63:0]
ELSE
DEST[i+63:i] SRC1[i+63:i] + SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VADDPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] + SRC2[63:0]
DEST[127:64] SRC1[127:64] + SRC2[127:64]
DEST[191:128] SRC1[191:128] + SRC2[191:128]
DEST[255:192] SRC1[255:192] + SRC2[255:192]
DEST[MAX_VL-1:256] 0
.
3-34 Vol. 2A
ADDPD—Add Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
VADDPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] + SRC2[63:0]
DEST[127:64] SRC1[127:64] + SRC2[127:64]
DEST[MAX_VL-1:128] 0
ADDPD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] + SRC[63:0]
DEST[127:64] DEST[127:64] + SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDPD __m512d _mm512_add_pd (__m512d a, __m512d b);
VADDPD __m512d _mm512_mask_add_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VADDPD __m512d _mm512_maskz_add_pd (__mmask8 k, __m512d a, __m512d b);
VADDPD __m256d _mm256_mask_add_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VADDPD __m256d _mm256_maskz_add_pd (__mmask8 k, __m256d a, __m256d b);
VADDPD __m128d _mm_mask_add_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VADDPD __m128d _mm_maskz_add_pd (__mmask8 k, __m128d a, __m128d b);
VADDPD __m512d _mm512_add_round_pd (__m512d a, __m512d b, int);
VADDPD __m512d _mm512_mask_add_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VADDPD __m512d _mm512_maskz_add_round_pd (__mmask8 k, __m512d a, __m512d b, int);
ADDPD __m256d _mm256_add_pd (__m256d a, __m256d b);
ADDPD __m128d _mm_add_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
ADDPD—Add Packed Double-Precision Floating-Point Values
Vol. 2A 3-35
INSTRUCTION SET REFERENCE, A-L
ADDPS—Add Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 58 /r
ADDPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 58 /r
VADDPS xmm1,xmm2, xmm3/m128
VEX.NDS.256.0F.WIG 58 /r
VADDPS ymm1, ymm2, ymm3/m256
EVEX.NDS.128.0F.W0 58 /r
VADDPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 58 /r
VADDPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 58 /r
VADDPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst {er}
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Add packed single-precision floating-point values from
xmm2/m128 to xmm1 and store result in xmm1.
Add packed single-precision floating-point values from
xmm3/m128 to xmm2 and store result in xmm1.
Add packed single-precision floating-point values from
ymm3/m256 to ymm2 and store result in ymm1.
Add packed single-precision floating-point values from
xmm3/m128/m32bcst to xmm2 and store result in
xmm1 with writemask k1.
Add packed single-precision floating-point values from
ymm3/m256/m32bcst to ymm2 and store result in
ymm1 with writemask k1.
Add packed single-precision floating-point values from
zmm3/m512/m32bcst to zmm2 and store result in
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Add four, eight or sixteen packed single-precision floating-point values from the first source operand with the
second source operand, and stores the packed single-precision floating-point results in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
Operation
VADDPS (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
3-36 Vol. 2A
ADDPS—Add Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC1[i+31:i] + SRC2[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VADDPS (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] SRC1[i+31:i] + SRC2[31:0]
ELSE
DEST[i+31:i] SRC1[i+31:i] + SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
ADDPS—Add Packed Single-Precision Floating-Point Values
Vol. 2A 3-37
INSTRUCTION SET REFERENCE, A-L
VADDPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] + SRC2[31:0]
DEST[63:32] SRC1[63:32] + SRC2[63:32]
DEST[95:64] SRC1[95:64] + SRC2[95:64]
DEST[127:96] SRC1[127:96] + SRC2[127:96]
DEST[159:128] SRC1[159:128] + SRC2[159:128]
DEST[191:160] SRC1[191:160] + SRC2[191:160]
DEST[223:192] SRC1[223:192] + SRC2[223:192]
DEST[255:224] SRC1[255:224] + SRC2[255:224].
DEST[MAX_VL-1:256] 0
VADDPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] + SRC2[31:0]
DEST[63:32] SRC1[63:32] + SRC2[63:32]
DEST[95:64] SRC1[95:64] + SRC2[95:64]
DEST[127:96] SRC1[127:96] + SRC2[127:96]
DEST[MAX_VL-1:128] 0
ADDPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] + SRC2[31:0]
DEST[63:32] SRC1[63:32] + SRC2[63:32]
DEST[95:64] SRC1[95:64] + SRC2[95:64]
DEST[127:96] SRC1[127:96] + SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDPS __m512 _mm512_add_ps (__m512 a, __m512 b);
VADDPS __m512 _mm512_mask_add_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VADDPS __m512 _mm512_maskz_add_ps (__mmask16 k, __m512 a, __m512 b);
VADDPS __m256 _mm256_mask_add_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VADDPS __m256 _mm256_maskz_add_ps (__mmask8 k, __m256 a, __m256 b);
VADDPS __m128 _mm_mask_add_ps (__m128d s, __mmask8 k, __m128 a, __m128 b);
VADDPS __m128 _mm_maskz_add_ps (__mmask8 k, __m128 a, __m128 b);
VADDPS __m512 _mm512_add_round_ps (__m512 a, __m512 b, int);
VADDPS __m512 _mm512_mask_add_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VADDPS __m512 _mm512_maskz_add_round_ps (__mmask16 k, __m512 a, __m512 b, int);
ADDPS __m256 _mm256_add_ps (__m256 a, __m256 b);
ADDPS __m128 _mm_add_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
3-38 Vol. 2A
ADDPS—Add Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ADDSD—Add Scalar Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 58 /r
ADDSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 58 /r
VADDSD xmm1, xmm2,
xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 58 /r
VADDSD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Add the low double-precision floating-point value from
xmm2/mem to xmm1 and store the result in xmm1.
Add the low double-precision floating-point value from
xmm3/mem to xmm2 and store the result in xmm1.
Add the low double-precision floating-point value from
xmm3/m64 to xmm2 and store the result in xmm1 with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S-RVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Adds the low double-precision floating-point values from the second source operand and the first source operand
and stores the double-precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
EVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:64) of
the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low quadword element of the destination is updated according to the writemask.
Software should ensure VADDSD is encoded with VEX.L=0. Encoding VADDSD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
VADDSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] SRC1[63:0] + SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
ADDSD—Add Scalar Double-Precision Floating-Point Values
Vol. 2A 3-39
INSTRUCTION SET REFERENCE, A-L
DEST[MAX_VL-1:128] 0
VADDSD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] + SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
ADDSD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] + SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDSD __m128d _mm_mask_add_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_maskz_add_sd (__mmask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_add_round_sd (__m128d a, __m128d b, int);
VADDSD __m128d _mm_mask_add_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VADDSD __m128d _mm_maskz_add_round_sd (__mmask8 k, __m128d a, __m128d b, int);
ADDSD __m128d _mm_add_sd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
3-40 Vol. 2A
ADDSD—Add Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ADDSS—Add Scalar Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 58 /r
ADDSS xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 58 /r
VADDSS xmm1,xmm2,
xmm3/m32
EVEX.NDS.LIG.F3.0F.W0 58 /r
VADDSS xmm1{k1}{z}, xmm2,
xmm3/m32{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Add the low single-precision floating-point value from
xmm2/mem to xmm1 and store the result in xmm1.
Add the low single-precision floating-point value from
xmm3/mem to xmm2 and store the result in xmm1.
Add the low single-precision floating-point value from
xmm3/m32 to xmm2 and store the result in xmm1with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Adds the low single-precision floating-point values from the second source operand and the first source operand,
and stores the double-precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:32) of the
corresponding the destination register remain unchanged.
EVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:32) of
the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VADDSS is encoded with VEX.L=0. Encoding VADDSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
Operation
VADDSS (EVEX encoded versions)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] SRC1[31:0] + SRC2[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
ADDSS—Add Scalar Single-Precision Floating-Point Values
Vol. 2A 3-41
INSTRUCTION SET REFERENCE, A-L
DEST[MAX_VL-1:128] 0
VADDSS DEST, SRC1, SRC2 (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] + SRC2[31:0]
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
ADDSS DEST, SRC (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0] + SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDSS __m128 _mm_mask_add_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_maskz_add_ss (__mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_add_round_ss (__m128 a, __m128 b, int);
VADDSS __m128 _mm_mask_add_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VADDSS __m128 _mm_maskz_add_round_ss (__mmask8 k, __m128 a, __m128 b, int);
ADDSS __m128 _mm_add_ss (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
3-42 Vol. 2A
ADDSS—Add Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ADDSUBPD—Packed Double-FP Add/Subtract
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F D0 /r
RM
V/V
SSE3
Add/subtract double-precision floating-point
values from xmm2/m128 to xmm1.
RVM V/V
AVX
Add/subtract packed double-precision
floating-point values from xmm3/mem to
xmm2 and stores result in xmm1.
RVM V/V
AVX
Add / subtract packed double-precision
floating-point values from ymm3/mem to
ymm2 and stores result in ymm1.
ADDSUBPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG D0 /r
VADDSUBPD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG D0 /r
VADDSUBPD ymm1, ymm2, ymm3/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Adds odd-numbered double-precision floating-point values of the first source operand (second operand) with the
corresponding double-precision floating-point values from the second source operand (third operand); stores the
result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered
double-precision floating-point values from the second source operand from the corresponding double-precision
floating values in the first source operand; stores the result into the even-numbered values of the destination
operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. See Figure 3-3.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
ADDSUBPD—Packed Double-FP Add/Subtract
Vol. 2A 3-43
INSTRUCTION SET REFERENCE, A-L
ADDSUBPD xmm1, xmm2/m128
xmm2/m128
[127:64]
[63:0]
xmm1[127:64] + xmm2/m128[127:64]
xmm1[63:0] - xmm2/m128[63:0]
[127:64]
[63:0]
RESULT:
xmm1
Figure 3-3. ADDSUBPD—Packed Double-FP Add/Subtract
Operation
ADDSUBPD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] - SRC[63:0]
DEST[127:64] DEST[127:64] + SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VADDSUBPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] - SRC2[63:0]
DEST[127:64] SRC1[127:64] + SRC2[127:64]
DEST[VLMAX-1:128] 0
VADDSUBPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] - SRC2[63:0]
DEST[127:64] SRC1[127:64] + SRC2[127:64]
DEST[191:128] SRC1[191:128] - SRC2[191:128]
DEST[255:192] SRC1[255:192] + SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
ADDSUBPD:
__m128d _mm_addsub_pd(__m128d a, __m128d b)
VADDSUBPD:
__m256d _mm256_addsub_pd (__m256d a, __m256d b)
Exceptions
When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
See Exceptions Type 2.
3-44 Vol. 2A
ADDSUBPD—Packed Double-FP Add/Subtract
INSTRUCTION SET REFERENCE, A-L
ADDSUBPS—Packed Single-FP Add/Subtract
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
F2 0F D0 /r
RM
V/V
SSE3
Add/subtract single-precision floating-point
values from xmm2/m128 to xmm1.
RVM V/V
AVX
Add/subtract single-precision floating-point
values from xmm3/mem to xmm2 and stores
result in xmm1.
RVM V/V
AVX
Add / subtract single-precision floating-point
values from ymm3/mem to ymm2 and stores
result in ymm1.
ADDSUBPS xmm1, xmm2/m128
VEX.NDS.128.F2.0F.WIG D0 /r
VADDSUBPS xmm1, xmm2, xmm3/m128
VEX.NDS.256.F2.0F.WIG D0 /r
VADDSUBPS ymm1, ymm2, ymm3/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Adds odd-numbered single-precision floating-point values of the first source operand (second operand) with the
corresponding single-precision floating-point values from the second source operand (third operand); stores the
result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered
single-precision floating-point values from the second source operand from the corresponding single-precision
floating values in the first source operand; stores the result into the even-numbered values of the destination
operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. See Figure 3-4.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
ADDSUBPS—Packed Single-FP Add/Subtract
Vol. 2A 3-45
INSTRUCTION SET REFERENCE, A-L
ADDSUBPS xmm1, xmm2/m128
xmm2/
m128
[127:96]
[95:64]
[63:32]
[31:0]
xmm1[127:96] +
xmm2/m128[127:96]
xmm1[95:64] - xmm2/
m128[95:64]
xmm1[63:32] +
xmm2/m128[63:32]
xmm1[31:0] xmm2/m128[31:0]
[127:96]
[95:64]
[63:32]
[31:0]
RESULT:
xmm1
OM15992
Figure 3-4. ADDSUBPS—Packed Single-FP Add/Subtract
Operation
ADDSUBPS (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0] - SRC[31:0]
DEST[63:32] DEST[63:32] + SRC[63:32]
DEST[95:64] DEST[95:64] - SRC[95:64]
DEST[127:96] DEST[127:96] + SRC[127:96]
DEST[VLMAX-1:128] (Unmodified)
VADDSUBPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] - SRC2[31:0]
DEST[63:32] SRC1[63:32] + SRC2[63:32]
DEST[95:64] SRC1[95:64] - SRC2[95:64]
DEST[127:96] SRC1[127:96] + SRC2[127:96]
DEST[VLMAX-1:128] 0
VADDSUBPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] - SRC2[31:0]
DEST[63:32] SRC1[63:32] + SRC2[63:32]
DEST[95:64] SRC1[95:64] - SRC2[95:64]
DEST[127:96] SRC1[127:96] + SRC2[127:96]
DEST[159:128] SRC1[159:128] - SRC2[159:128]
DEST[191:160] SRC1[191:160] + SRC2[191:160]
DEST[223:192] SRC1[223:192] - SRC2[223:192]
DEST[255:224] SRC1[255:224] + SRC2[255:224].
Intel C/C++ Compiler Intrinsic Equivalent
ADDSUBPS:
__m128 _mm_addsub_ps(__m128 a, __m128 b)
VADDSUBPS:
__m256 _mm256_addsub_ps (__m256 a, __m256 b)
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a generalprotection exception (#GP) will be generated.
3-46 Vol. 2A
ADDSUBPS—Packed Single-FP Add/Subtract
INSTRUCTION SET REFERENCE, A-L
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
See Exceptions Type 2.
ADDSUBPS—Packed Single-FP Add/Subtract
Vol. 2A 3-47
INSTRUCTION SET REFERENCE, A-L
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
ADX
Description
RM
64/32bit
Mode
Support
V/V
F3 0F 38 F6 /r
ADOX r32, r/m32
F3 REX.w 0F 38 F6 /r
ADOX r64, r/m64
RM
V/NE
ADX
Unsigned addition of r64 with OF, r/m64 to r64, writes OF.
Unsigned addition of r32 with OF, r/m32 to r32, writes OF.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Performs an unsigned addition of the destination operand (first operand), the source operand (second operand)
and the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a generalpurpose register, whereas the source operand can be a general-purpose register or memory location. The state of
OF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the
unsigned addition of the operands.
The ADOX instruction is executed in the context of multi-precision addition, where we add a series of operands with
a carry-chain. At the beginning of a chain of additions, we execute an instruction to zero the OF (e.g. XOR).
This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit
mode.
In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to additional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64-bits.
ADOX executes normally either inside or outside a transaction region.
Note: ADOX defines the CF and OF flags differently than the ADD/ADC instructions as defined in Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A.
Operation
IF OperandSize is 64-bit
THEN OF:DEST[63:0] ← DEST[63:0] + SRC[63:0] + OF;
ELSE OF:DEST[31:0] ← DEST[31:0] + SRC[31:0] + OF;
FI;
Flags Affected
OF is updated based on result. CF, SF, ZF, AF and PF flags are unmodified.
Intel C/C++ Compiler Intrinsic Equivalent
unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);
unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
SIMD Floating-Point Exceptions
None
3-48 Vol. 2A
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
#GP(0)
For an illegal address in the SS segment.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
selector.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag
Vol. 2A 3-49
INSTRUCTION SET REFERENCE, A-L
AESDEC—Perform One Round of an AES Decryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DE /r
AESDEC xmm1, xmm2/m128
RM
V/V
AES
Perform one round of an AES decryption flow,
using the Equivalent Inverse Cipher, operating
on a 128-bit data (state) from xmm1 with a
128-bit round key from xmm2/m128.
VEX.NDS.128.66.0F38.WIG DE /r
VAESDEC xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform one round of an AES decryption flow,
using the Equivalent Inverse Cipher, operating
on a 128-bit data (state) from xmm2 with a
128-bit round key from xmm3/m128; store
the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, with the
round key from the second source operand, operating on a 128-bit data (state) from the first source operand, and
store the result in the destination operand.
Use the AESDEC instruction for all but the last decryption round. For the last decryption round, use the AESDECLAST instruction.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESDEC
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
STATE ← InvMixColumns( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESDEC
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
STATE ← InvMixColumns( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] ← 0
3-50 Vol. 2A
AESDEC—Perform One Round of an AES Decryption Flow
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESDEC:
__m128i _mm_aesdec (__m128i, __m128i)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESDEC—Perform One Round of an AES Decryption Flow
Vol. 2A 3-51
INSTRUCTION SET REFERENCE, A-L
AESDECLAST—Perform Last Round of an AES Decryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DF /r
AESDECLAST xmm1, xmm2/m128
RM
V/V
AES
Perform the last round of an AES decryption
flow, using the Equivalent Inverse Cipher,
operating on a 128-bit data (state) from
xmm1 with a 128-bit round key from
xmm2/m128.
VEX.NDS.128.66.0F38.WIG DF /r
VAESDECLAST xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform the last round of an AES decryption
flow, using the Equivalent Inverse Cipher,
operating on a 128-bit data (state) from
xmm2 with a 128-bit round key from
xmm3/m128; store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, with the
round key from the second source operand, operating on a 128-bit data (state) from the first source operand, and
store the result in the destination operand.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESDECLAST
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESDECLAST
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] ← 0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESDECLAST:
3-52 Vol. 2A
__m128i _mm_aesdeclast (__m128i, __m128i)
AESDECLAST—Perform Last Round of an AES Decryption Flow
INSTRUCTION SET REFERENCE, A-L
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESDECLAST—Perform Last Round of an AES Decryption Flow
Vol. 2A 3-53
INSTRUCTION SET REFERENCE, A-L
AESENC—Perform One Round of an AES Encryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DC /r
AESENC xmm1, xmm2/m128
RM
V/V
AES
Perform one round of an AES encryption flow,
operating on a 128-bit data (state) from
xmm1 with a 128-bit round key from
xmm2/m128.
VEX.NDS.128.66.0F38.WIG DC /r
VAESENC xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform one round of an AES encryption flow,
operating on a 128-bit data (state) from
xmm2 with a 128-bit round key from the
xmm3/m128; store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs a single round of an AES encryption flow using a round key from the second source
operand, operating on 128-bit data (state) from the first source operand, and store the result in the destination
operand.
Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENCCLAST instruction.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESENC
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← ShiftRows( STATE );
STATE ← SubBytes( STATE );
STATE ← MixColumns( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESENC
STATE SRC1;
RoundKey SRC2;
STATE ShiftRows( STATE );
STATE SubBytes( STATE );
STATE MixColumns( STATE );
DEST[127:0] STATE XOR RoundKey;
DEST[VLMAX-1:128] 0
3-54 Vol. 2A
AESENC—Perform One Round of an AES Encryption Flow
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESENC:
__m128i _mm_aesenc (__m128i, __m128i)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESENC—Perform One Round of an AES Encryption Flow
Vol. 2A 3-55
INSTRUCTION SET REFERENCE, A-L
AESENCLAST—Perform Last Round of an AES Encryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DD /r
AESENCLAST xmm1, xmm2/m128
RM
V/V
AES
Perform the last round of an AES encryption
flow, operating on a 128-bit data (state) from
xmm1 with a 128-bit round key from
xmm2/m128.
VEX.NDS.128.66.0F38.WIG DD /r
VAESENCLAST xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform the last round of an AES encryption
flow, operating on a 128-bit data (state) from
xmm2 with a 128 bit round key from
xmm3/m128; store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs the last round of an AES encryption flow using a round key from the second source
operand, operating on 128-bit data (state) from the first source operand, and store the result in the destination
operand.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESENCLAST
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← ShiftRows( STATE );
STATE ← SubBytes( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESENCLAST
STATE SRC1;
RoundKey SRC2;
STATE ShiftRows( STATE );
STATE SubBytes( STATE );
DEST[127:0] STATE XOR RoundKey;
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESENCLAST:
3-56 Vol. 2A
__m128i _mm_aesenclast (__m128i, __m128i)
AESENCLAST—Perform Last Round of an AES Encryption Flow
INSTRUCTION SET REFERENCE, A-L
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESENCLAST—Perform Last Round of an AES Encryption Flow
Vol. 2A 3-57
INSTRUCTION SET REFERENCE, A-L
AESIMC—Perform the AES InvMixColumn Transformation
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DB /r
AESIMC xmm1, xmm2/m128
RM
V/V
AES
Perform the InvMixColumn transformation on
a 128-bit round key from xmm2/m128 and
store the result in xmm1.
VEX.128.66.0F38.WIG DB /r
VAESIMC xmm1, xmm2/m128
RM
V/V
Both AES
and
AVX flags
Perform the InvMixColumn transformation on
a 128-bit round key from xmm2/m128 and
store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Perform the InvMixColumns transformation on the source operand and store the result in the destination operand.
The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory location.
Note: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round
key) in order to prepare them for decryption using the “Equivalent Inverse Cipher” (defined in FIPS 197).
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESIMC
DEST[127:0] ← InvMixColumns( SRC );
DEST[VLMAX-1:128] (Unmodified)
VAESIMC
DEST[127:0] InvMixColumns( SRC );
DEST[VLMAX-1:128] 0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESIMC:
__m128i _mm_aesimc (__m128i)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
3-58 Vol. 2A
If VEX.vvvv ≠ 1111B.
AESIMC—Perform the AES InvMixColumn Transformation
INSTRUCTION SET REFERENCE, A-L
AESKEYGENASSIST—AES Round Key Generation Assist
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A DF /r ib
AESKEYGENASSIST xmm1, xmm2/m128, imm8
RMI
V/V
AES
Assist in AES round key generation using an 8
bits Round Constant (RCON) specified in the
immediate byte, operating on 128 bits of data
specified in xmm2/m128 and stores the
result in xmm1.
VEX.128.66.0F3A.WIG DF /r ib
VAESKEYGENASSIST xmm1, xmm2/m128, imm8
RMI
V/V
Both AES
and
AVX flags
Assist in AES round key generation using 8
bits Round Constant (RCON) specified in the
immediate byte, operating on 128 bits of data
specified in xmm2/m128 and stores the
result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
Description
Assist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using
128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the
result in the destination operand.
The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory location.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESKEYGENASSIST
X3[31:0] ← SRC [127: 96];
X2[31:0] ← SRC [95: 64];
X1[31:0] ← SRC [63: 32];
X0[31:0] ← SRC [31: 0];
RCON[31:0] ← ZeroExtend(Imm8[7:0]);
DEST[31:0] ← SubWord(X1);
DEST[63:32 ] ← RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] ← SubWord(X3);
DEST[127:96] ← RotWord( SubWord(X3) ) XOR RCON;
DEST[VLMAX-1:128] (Unmodified)
AESKEYGENASSIST—AES Round Key Generation Assist
Vol. 2A 3-59
INSTRUCTION SET REFERENCE, A-L
VAESKEYGENASSIST
X3[31:0] SRC [127: 96];
X2[31:0] SRC [95: 64];
X1[31:0] SRC [63: 32];
X0[31:0] SRC [31: 0];
RCON[31:0] ZeroExtend(Imm8[7:0]);
DEST[31:0] SubWord(X1);
DEST[63:32 ] RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] SubWord(X3);
DEST[127:96] RotWord( SubWord(X3) ) XOR RCON;
DEST[VLMAX-1:128] 0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESKEYGENASSIST:
__m128i _mm_aeskeygenassist (__m128i, const int)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
3-60 Vol. 2A
If VEX.vvvv ≠ 1111B.
AESKEYGENASSIST—AES Round Key Generation Assist
INSTRUCTION SET REFERENCE, A-L
AND—Logical AND
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
24 ib
AND AL, imm8
I
Valid
Valid
AL AND imm8.
25 iw
AND AX, imm16
I
Valid
Valid
AX AND imm16.
25 id
AND EAX, imm32
I
Valid
Valid
EAX AND imm32.
REX.W + 25 id
AND RAX, imm32
I
Valid
N.E.
RAX AND imm32 sign-extended to 64-bits.
80 /4 ib
AND r/m8, imm8
MI
Valid
Valid
r/m8 AND imm8.
REX + 80 /4 ib
AND r/m8*, imm8
MI
Valid
N.E.
r/m8 AND imm8.
81 /4 iw
AND r/m16, imm16
MI
Valid
Valid
r/m16 AND imm16.
81 /4 id
AND r/m32, imm32
MI
Valid
Valid
r/m32 AND imm32.
REX.W + 81 /4 id
AND r/m64, imm32
MI
Valid
N.E.
r/m64 AND imm32 sign extended to 64-bits.
83 /4 ib
AND r/m16, imm8
MI
Valid
Valid
r/m16 AND imm8 (sign-extended).
83 /4 ib
AND r/m32, imm8
MI
Valid
Valid
r/m32 AND imm8 (sign-extended).
REX.W + 83 /4 ib
AND r/m64, imm8
MI
Valid
N.E.
r/m64 AND imm8 (sign-extended).
20 /r
AND r/m8, r8
MR
Valid
Valid
r/m8 AND r8.
REX + 20 /r
AND r/m8*, r8*
MR
Valid
N.E.
r/m64 AND r8 (sign-extended).
21 /r
AND r/m16, r16
MR
Valid
Valid
r/m16 AND r16.
21 /r
AND r/m32, r32
MR
Valid
Valid
r/m32 AND r32.
REX.W + 21 /r
AND r/m64, r64
MR
Valid
N.E.
r/m64 AND r32.
22 /r
AND r8, r/m8
RM
Valid
Valid
r8 AND r/m8.
REX + 22 /r
AND r8*, r/m8*
RM
Valid
N.E.
r/m64 AND r8 (sign-extended).
23 /r
AND r16, r/m16
RM
Valid
Valid
r16 AND r/m16.
23 /r
AND r32, r/m32
RM
Valid
Valid
r32 AND r/m32.
REX.W + 23 /r
AND r64, r/m64
RM
Valid
N.E.
r64 AND r/m64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
I
AL/AX/EAX/RAX
imm8
NA
NA
Description
Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in
the destination operand location. The source operand can be an immediate, a register, or a memory location; the
destination operand can be a register or a memory location. (However, two memory operands cannot be used in
one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1;
otherwise, it is set to 0.
This instruction can be used with a LOCK prefix to allow the it to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
AND—Logical AND
Vol. 2A 3-61
INSTRUCTION SET REFERENCE, A-L
Operation
DEST ← DEST AND SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is
undefined.
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-62 Vol. 2A
AND—Logical AND
INSTRUCTION SET REFERENCE, A-L
ANDN — Logical AND NOT
Opcode/Instruction
Op/
En
CPUID
Feature
Flag
BMI1
Description
RVM
64/32
-bit
Mode
V/V
VEX.NDS.LZ.0F38.W0 F2 /r
ANDN r32a, r32b, r/m32
VEX.NDS.LZ. 0F38.W1 F2 /r
ANDN r64a, r64b, r/m64
RVM
V/NE
BMI1
Bitwise AND of inverted r64b with r/m64, store result in r64a.
Bitwise AND of inverted r32b with r/m32, store result in r32a.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the
second source operand). The result is stored in the first operand (destination operand).
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
DEST ← (NOT SRC1) bitwiseAND SRC2;
SF ← DEST[OperandSize -1];
ZF ← (DEST = 0);
Flags Affected
SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
ANDN — Logical AND NOT
If VEX.W = 1.
Vol. 2A 3-63
INSTRUCTION SET REFERENCE, A-L
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 54 /r
ANDPD xmm1, xmm2/m128
VEX.NDS.128.66.0F 54 /r
VANDPD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F 54 /r
VANDPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 54 /r
VANDPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 54 /r
VANDPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 54 /r
VANDPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND of packed doubleprecision floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND of packed doubleprecision floating-point values in xmm2 and
xmm3/m128/m64bcst subject to writemask k1.
Return the bitwise logical AND of packed doubleprecision floating-point values in ymm2 and
ymm3/m256/m64bcst subject to writemask k1.
Return the bitwise logical AND of packed doubleprecision floating-point values in zmm2 and
zmm3/m512/m64bcst subject to writemask k1.
Return the bitwise logical AND of packed doubleprecision floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND of packed doubleprecision floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND of the two, four or eight packed double-precision floating-point values from the first
source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
3-64 Vol. 2A
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VANDPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] SRC1[i+63:i] BITWISE AND SRC2[63:0]
ELSE
DEST[i+63:i] SRC1[i+63:i] BITWISE AND SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VANDPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[127:64] SRC1[127:64] BITWISE AND SRC2[127:64]
DEST[191:128] SRC1[191:128] BITWISE AND SRC2[191:128]
DEST[255:192] SRC1[255:192] BITWISE AND SRC2[255:192]
DEST[MAX_VL-1:256] 0
VANDPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[127:64] SRC1[127:64] BITWISE AND SRC2[127:64]
DEST[MAX_VL-1:128] 0
ANDPD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] BITWISE AND SRC[63:0]
DEST[127:64] DEST[127:64] BITWISE AND SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VANDPD __m512d _mm512_and_pd (__m512d a, __m512d b);
VANDPD __m512d _mm512_mask_and_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VANDPD __m512d _mm512_maskz_and_pd (__mmask8 k, __m512d a, __m512d b);
VANDPD __m256d _mm256_mask_and_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VANDPD __m256d _mm256_maskz_and_pd (__mmask8 k, __m256d a, __m256d b);
VANDPD __m128d _mm_mask_and_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VANDPD __m128d _mm_maskz_and_pd (__mmask8 k, __m128d a, __m128d b);
VANDPD __m256d _mm256_and_pd (__m256d a, __m256d b);
ANDPD __m128d _mm_and_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
Vol. 2A 3-65
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
3-66 Vol. 2A
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 54 /r
ANDPS xmm1, xmm2/m128
VEX.NDS.128.0F 54 /r
VANDPS xmm1,xmm2,
xmm3/m128
VEX.NDS.256.0F 54 /r
VANDPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.0F.W0 54 /r
VANDPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 54 /r
VANDPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 54 /r
VANDPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND of packed single-precision
floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND of packed single-precision
floating-point values in xmm2 and xmm3/m128/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in ymm2 and ymm3/m256/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in zmm2 and zmm3/m512/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND of packed single-precision
floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND of the four, eight or sixteen packed single-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Vol. 2A 3-67
INSTRUCTION SET REFERENCE, A-L
Operation
VANDPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] SRC1[i+31:i] BITWISE AND SRC2[31:0]
ELSE
DEST[i+31:i] SRC1[i+31:i] BITWISE AND SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0;
VANDPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE AND SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE AND SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE AND SRC2[127:96]
DEST[159:128] SRC1[159:128] BITWISE AND SRC2[159:128]
DEST[191:160] SRC1[191:160] BITWISE AND SRC2[191:160]
DEST[223:192] SRC1[223:192] BITWISE AND SRC2[223:192]
DEST[255:224] SRC1[255:224] BITWISE AND SRC2[255:224].
DEST[MAX_VL-1:256] 0;
VANDPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE AND SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE AND SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE AND SRC2[127:96]
DEST[MAX_VL-1:128] 0;
ANDPS (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0] BITWISE AND SRC[31:0]
DEST[63:32] DEST[63:32] BITWISE AND SRC[63:32]
DEST[95:64] DEST[95:64] BITWISE AND SRC[95:64]
DEST[127:96] DEST[127:96] BITWISE AND SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)
3-68 Vol. 2A
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VANDPS __m512 _mm512_and_ps (__m512 a, __m512 b);
VANDPS __m512 _mm512_mask_and_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VANDPS __m512 _mm512_maskz_and_ps (__mmask16 k, __m512 a, __m512 b);
VANDPS __m256 _mm256_mask_and_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VANDPS __m256 _mm256_maskz_and_ps (__mmask8 k, __m256 a, __m256 b);
VANDPS __m128 _mm_mask_and_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VANDPS __m128 _mm_maskz_and_ps (__mmask8 k, __m128 a, __m128 b);
VANDPS __m256 _mm256_and_ps (__m256 a, __m256 b);
ANDPS __m128 _mm_and_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Vol. 2A 3-69
INSTRUCTION SET REFERENCE, A-L
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 55 /r
ANDNPD xmm1, xmm2/m128
VEX.NDS.128.66.0F 55 /r
VANDNPD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F 55/r
VANDNPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 55 /r
VANDNPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 55 /r
VANDNPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 55 /r
VANDNPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm2 and
xmm3/m128/m64bcst subject to writemask k1.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in ymm2 and
ymm3/m256/m64bcst subject to writemask k1.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in zmm2 and
zmm3/m512/m64bcst subject to writemask k1.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND NOT of the two, four or eight packed double-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
3-70 Vol. 2A
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VANDNPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] (NOT(SRC1[i+63:i])) BITWISE AND SRC2[63:0]
ELSE
DEST[i+63:i] (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VANDNPD (VEX.256 encoded version)
DEST[63:0] (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64] (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[191:128] (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]
DEST[255:192] (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]
DEST[MAX_VL-1:256] 0
VANDNPD (VEX.128 encoded version)
DEST[63:0] (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64] (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[MAX_VL-1:128] 0
ANDNPD (128-bit Legacy SSE version)
DEST[63:0] (NOT(DEST[63:0])) BITWISE AND SRC[63:0]
DEST[127:64] (NOT(DEST[127:64])) BITWISE AND SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);
VANDNPD __m512d _mm512_mask_andnot_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);
VANDNPD __m256d _mm256_mask_andnot_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);
VANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VANDNPD __m128d _mm_maskz_andnot_pd (__mmask8 k, __m128d a, __m128d b);
VANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);
ANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Vol. 2A 3-71
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
3-72 Vol. 2A
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 55 /r
ANDNPS xmm1, xmm2/m128
VEX.NDS.128.0F 55 /r
VANDNPS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.0F 55 /r
VANDNPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.0F.W0 55 /r
VANDNPS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 55 /r
VANDNPS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 55 /r
VANDNPS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND NOT of packed single-precision
floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND of packed single-precision
floating-point values in xmm2 and xmm3/m128/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in ymm2 and ymm3/m256/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in zmm2 and zmm3/m512/m32bcst
subject to writemask k1.
Return the bitwise logical AND NOT of packed single-precision
floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND NOT of packed single-precision
floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND NOT of the four, eight or sixteen packed single-precision floating-point values from
the first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Vol. 2A 3-73
INSTRUCTION SET REFERENCE, A-L
Operation
VANDNPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] (NOT(SRC1[i+31:i])) BITWISE AND SRC2[31:0]
ELSE
DEST[i+31:i] (NOT(SRC1[i+31:i])) BITWISE AND SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] = 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VANDNPS (VEX.256 encoded version)
DEST[31:0] (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]
DEST[63:32] (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]
DEST[95:64] (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]
DEST[127:96] (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]
DEST[159:128] (NOT(SRC1[159:128])) BITWISE AND SRC2[159:128]
DEST[191:160] (NOT(SRC1[191:160])) BITWISE AND SRC2[191:160]
DEST[223:192] (NOT(SRC1[223:192])) BITWISE AND SRC2[223:192]
DEST[255:224] (NOT(SRC1[255:224])) BITWISE AND SRC2[255:224].
DEST[MAX_VL-1:256] 0
VANDNPS (VEX.128 encoded version)
DEST[31:0] (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]
DEST[63:32] (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]
DEST[95:64] (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]
DEST[127:96] (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]
DEST[MAX_VL-1:128] 0
ANDNPS (128-bit Legacy SSE version)
DEST[31:0] (NOT(DEST[31:0])) BITWISE AND SRC[31:0]
DEST[63:32] (NOT(DEST[63:32])) BITWISE AND SRC[63:32]
DEST[95:64] (NOT(DEST[95:64])) BITWISE AND SRC[95:64]
DEST[127:96] (NOT(DEST[127:96])) BITWISE AND SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)
3-74 Vol. 2A
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VANDNPS __m512 _mm512_andnot_ps (__m512 a, __m512 b);
VANDNPS __m512 _mm512_mask_andnot_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VANDNPS __m512 _mm512_maskz_andnot_ps (__mmask16 k, __m512 a, __m512 b);
VANDNPS __m256 _mm256_mask_andnot_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VANDNPS __m256 _mm256_maskz_andnot_ps (__mmask8 k, __m256 a, __m256 b);
VANDNPS __m128 _mm_mask_andnot_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VANDNPS __m128 _mm_maskz_andnot_ps (__mmask8 k, __m128 a, __m128 b);
VANDNPS __m256 _mm256_andnot_ps (__m256 a, __m256 b);
ANDNPS __m128 _mm_andnot_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Vol. 2A 3-75
INSTRUCTION SET REFERENCE, A-L
ARPL—Adjust RPL Field of Segment Selector
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
63 /r
ARPL r/m16, r16
NP
N. E.
Valid
Adjust RPL of r/m16 to not less than RPL of
r16.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one
segment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0
and 1 of each operand.) If the RPL field of the destination operand is less than the RPL field of the source operand,
the ZF flag is set and the RPL field of the destination operand is increased to match that of the source operand.
Otherwise, the ZF flag is cleared and no change is made to the destination operand. (The destination operand can
be a word register or a memory location; the source operand must be a word register.)
The ARPL instruction is provided for use by operating-system procedures (however, it can also be used by applications). It is generally used to adjust the RPL of a segment selector that has been passed to the operating system
by an application program to match the privilege level of the application program. Here the segment selector
passed to the operating system is placed in the destination operand and segment selector for the application
program’s code segment is placed in the source operand. (The RPL field in the source operand represents the privilege level of the application program.) Execution of the ARPL instruction then ensures that the RPL of the segment
selector received by the operating system is no lower (does not have a higher privilege) than the privilege level of
the application program (the segment selector for the application program’s code segment can be read from the
stack following a procedure call).
This instruction executes as described in compatibility mode and legacy mode. It is not encodable in 64-bit mode.
See “Checking Caller Access Privileges” in Chapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about the use of this instruction.
Operation
IF 64-BIT MODE
THEN
See MOVSXD;
ELSE
IF DEST[RPL] < SRC[RPL]
THEN
ZF ← 1;
DEST[RPL] ← SRC[RPL];
ELSE
ZF ← 0;
FI;
FI;
Flags Affected
The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise,
it is set to 0.
3-76 Vol. 2A
ARPL—Adjust RPL Field of Segment Selector
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The ARPL instruction is not recognized in real-address mode.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
The ARPL instruction is not recognized in virtual-8086 mode.
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Not applicable.
ARPL—Adjust RPL Field of Segment Selector
Vol. 2A 3-77
INSTRUCTION SET REFERENCE, A-L
BLENDPD — Blend Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A 0D /r ib
RMI
V/V
SSE4_1
Select packed DP-FP values from xmm1 and
xmm2/m128 from mask specified in imm8
and store the values into xmm1.
RVMI V/V
AVX
Select packed double-precision floating-point
Values from xmm2 and xmm3/m128 from
mask in imm8 and store the values in xmm1.
RVMI V/V
AVX
Select packed double-precision floating-point
Values from ymm2 and ymm3/m256 from
mask in imm8 and store the values in ymm1.
BLENDPD xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 0D /r ib
VBLENDPD xmm1, xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.WIG 0D /r ib
VBLENDPD ymm1, ymm2, ymm3/m256, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8[3:0]
Description
Double-precision floating-point values from the second source operand (third operand) are conditionally merged
with values from the first source operand (second operand) and written to the destination operand (first operand).
The immediate bits [3:0] determine whether the corresponding double-precision floating-point value in the destination is copied from the second source or first source. If a bit in the mask, corresponding to a word, is ”1”, then
the double-precision floating-point value in the second source operand is copied, else the value in the first source
operand is copied.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Operation
BLENDPD (128-bit Legacy SSE version)
IF (IMM8[0] = 0)THEN DEST[63:0] DEST[63:0]
ELSE DEST [63:0] SRC[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] DEST[127:64]
ELSE DEST [127:64] SRC[127:64] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDPD (VEX.128 encoded version)
IF (IMM8[0] = 0)THEN DEST[63:0] SRC1[63:0]
ELSE DEST [63:0] SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] SRC1[127:64]
ELSE DEST [127:64] SRC2[127:64] FI
DEST[VLMAX-1:128] 0
3-78 Vol. 2A
BLENDPD — Blend Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
VBLENDPD (VEX.256 encoded version)
IF (IMM8[0] = 0)THEN DEST[63:0] SRC1[63:0]
ELSE DEST [63:0] SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] SRC1[127:64]
ELSE DEST [127:64] SRC2[127:64] FI
IF (IMM8[2] = 0) THEN DEST[191:128] SRC1[191:128]
ELSE DEST [191:128] SRC2[191:128] FI
IF (IMM8[3] = 0) THEN DEST[255:192] SRC1[255:192]
ELSE DEST [255:192] SRC2[255:192] FI
Intel C/C++ Compiler Intrinsic Equivalent
BLENDPD:
__m128d _mm_blend_pd (__m128d v1, __m128d v2, const int mask);
VBLENDPD:
__m256d _mm256_blend_pd (__m256d a, __m256d b, const int mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
BLENDPD — Blend Packed Double Precision Floating-Point Values
Vol. 2A 3-79
INSTRUCTION SET REFERENCE, A-L
BEXTR — Bit Field Extract
Opcode/Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDS.LZ.0F38.W0 F7 /r
BEXTR r32a, r/m32, r32b
VEX.NDS.LZ.0F38.W1 F7 /r
BEXTR r64a, r/m64, r64b
RMV
V/N.E.
BMI1
Description
Contiguous bitwise extract from r/m32 using r32b as control; store
result in r32a.
Contiguous bitwise extract from r/m64 using r64b as control; store
result in r64a
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (w)
ModRM:r/m (r)
VEX.vvvv (r)
NA
Description
Extracts contiguous bits from the first source operand (the second operand) using an index value and length value
specified in the second source operand (the third operand). Bit 7:0 of the second source operand specifies the
starting bit position of bit extraction. A START value exceeding the operand size will not extract any bits from the
second source operand. Bit 15:8 of the second source operand specifies the maximum number of bits (LENGTH)
beginning at the START position to extract. Only bit positions up to (OperandSize -1) of the first source operand are
extracted. The extracted bits are written to the destination register, starting from the least significant bit. All higher
order bits in the destination operand (starting at bit position LENGTH) are zeroed. The destination register is
cleared if no bits are extracted.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
START ← SRC2[7:0];
LEN ← SRC2[15:8];
TEMP ← ZERO_EXTEND_TO_512 (SRC1 );
DEST ← ZERO_EXTEND(TEMP[START+LEN -1: START]);
ZF ← (DEST = 0);
Flags Affected
ZF is updated based on the result. AF, SF, and PF are undefined. All other flags are cleared.
Intel C/C++ Compiler Intrinsic Equivalent
BEXTR:
unsigned __int32 _bextr_u32(unsigned __int32 src, unsigned __int32 start. unsigned __int32 len);
BEXTR:
unsigned __int64 _bextr_u64(unsigned __int64 src, unsigned __int32 start. unsigned __int32 len);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
3-80 Vol. 2A
If VEX.W = 1.
BEXTR — Bit Field Extract
INSTRUCTION SET REFERENCE, A-L
BLENDPS — Blend Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A 0C /r ib
RMI
V/V
SSE4_1
Select packed single precision floating-point
values from xmm1 and xmm2/m128 from
mask specified in imm8 and store the values
into xmm1.
RVMI V/V
AVX
Select packed single-precision floating-point
values from xmm2 and xmm3/m128 from
mask in imm8 and store the values in xmm1.
RVMI V/V
AVX
Select packed single-precision floating-point
values from ymm2 and ymm3/m256 from
mask in imm8 and store the values in ymm1.
BLENDPS xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 0C /r ib
VBLENDPS xmm1, xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.WIG 0C /r ib
VBLENDPS ymm1, ymm2, ymm3/m256, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Packed single-precision floating-point values from the second source operand (third operand) are conditionally
merged with values from the first source operand (second operand) and written to the destination operand (first
operand). The immediate bits [7:0] determine whether the corresponding single precision floating-point value in
the destination is copied from the second source or first source. If a bit in the mask, corresponding to a word, is
“1”, then the single-precision floating-point value in the second source operand is copied, else the value in the first
source operand is copied.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: The first source operand an XMM register. The second source operand is an XMM register
or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the
corresponding YMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Operation
BLENDPS (128-bit Legacy SSE version)
IF (IMM8[0] = 0) THEN DEST[31:0] DEST[31:0]
ELSE DEST [31:0] SRC[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] DEST[63:32]
ELSE DEST [63:32] SRC[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] DEST[95:64]
ELSE DEST [95:64] SRC[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] DEST[127:96]
ELSE DEST [127:96] SRC[127:96] FI
DEST[VLMAX-1:128] (Unmodified)
BLENDPS — Blend Packed Single Precision Floating-Point Values
Vol. 2A 3-81
INSTRUCTION SET REFERENCE, A-L
VBLENDPS (VEX.128 encoded version)
IF (IMM8[0] = 0) THEN DEST[31:0] SRC1[31:0]
ELSE DEST [31:0] SRC2[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] SRC1[63:32]
ELSE DEST [63:32] SRC2[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] SRC1[95:64]
ELSE DEST [95:64] SRC2[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] SRC1[127:96]
ELSE DEST [127:96] SRC2[127:96] FI
DEST[VLMAX-1:128] 0
VBLENDPS (VEX.256 encoded version)
IF (IMM8[0] = 0) THEN DEST[31:0] SRC1[31:0]
ELSE DEST [31:0] SRC2[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] SRC1[63:32]
ELSE DEST [63:32] SRC2[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] SRC1[95:64]
ELSE DEST [95:64] SRC2[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] SRC1[127:96]
ELSE DEST [127:96] SRC2[127:96] FI
IF (IMM8[4] = 0) THEN DEST[159:128] SRC1[159:128]
ELSE DEST [159:128] SRC2[159:128] FI
IF (IMM8[5] = 0) THEN DEST[191:160] SRC1[191:160]
ELSE DEST [191:160] SRC2[191:160] FI
IF (IMM8[6] = 0) THEN DEST[223:192] SRC1[223:192]
ELSE DEST [223:192] SRC2[223:192] FI
IF (IMM8[7] = 0) THEN DEST[255:224] SRC1[255:224]
ELSE DEST [255:224] SRC2[255:224] FI.
Intel C/C++ Compiler Intrinsic Equivalent
BLENDPS:
__m128 _mm_blend_ps (__m128 v1, __m128 v2, const int mask);
VBLENDPS:
__m256 _mm256_blend_ps (__m256 a, __m256 b, const int mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
3-82 Vol. 2A
BLENDPS — Blend Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 15 /r
RM0
V/V
SSE4_1
Select packed DP FP values from xmm1 and
xmm2 from mask specified in XMM0 and
store the values in xmm1.
RVMR V/V
AVX
Conditionally copy double-precision floatingpoint values from xmm2 or xmm3/m128 to
xmm1, based on mask bits in the mask
operand, xmm4.
RVMR V/V
AVX
Conditionally copy double-precision floatingpoint values from ymm2 or ymm3/m256 to
ymm1, based on mask bits in the mask
operand, ymm4.
BLENDVPD xmm1, xmm2/m128 ,
VEX.NDS.128.66.0F3A.W0 4B /r /is4
VBLENDVPD xmm1, xmm2, xmm3/m128, xmm4
VEX.NDS.256.66.0F3A.W0 4B /r /is4
VBLENDVPD ymm1, ymm2, ymm3/m256, ymm4
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM0
ModRM:reg (r, w)
ModRM:r/m (r)
implicit XMM0
NA
RVMR
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8[7:4]
Description
Conditionally copy each quadword data element of double-precision floating-point value from the second source
operand and the first source operand depending on mask bits defined in the mask register operand. The mask bits
are the most significant bit in each quadword element of the mask register.
Each quadword element of the destination operand is copied from:
•
•
the corresponding quadword element in the second source operand, if a mask bit is “1”; or
the corresponding quadword element in the first source operand, if a mask bit is “0”
The register assignment of the implicit mask operand for BLENDVPD is defined to be the architectural register
XMM0.
128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined
to be the architectural register XMM0. An attempt to execute BLENDVPD with a VEX prefix will cause #UD.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.
VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source
operand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. VEX.W must be 0, otherwise, the instruction will #UD.
VBLENDVPD permits the mask to be any XMM or YMM register. In contrast, BLENDVPD treats XMM0 implicitly as the
mask and do not support non-destructive destination operation.
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values
Vol. 2A 3-83
INSTRUCTION SET REFERENCE, A-L
Operation
BLENDVPD (128-bit Legacy SSE version)
MASK XMM0
IF (MASK[63] = 0) THEN DEST[63:0] DEST[63:0]
ELSE DEST [63:0] SRC[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64] DEST[127:64]
ELSE DEST [127:64] SRC[127:64] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDVPD (VEX.128 encoded version)
MASK SRC3
IF (MASK[63] = 0) THEN DEST[63:0] SRC1[63:0]
ELSE DEST [63:0] SRC2[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64] SRC1[127:64]
ELSE DEST [127:64] SRC2[127:64] FI
DEST[VLMAX-1:128] 0
VBLENDVPD (VEX.256 encoded version)
MASK SRC3
IF (MASK[63] = 0) THEN DEST[63:0] SRC1[63:0]
ELSE DEST [63:0] SRC2[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64] SRC1[127:64]
ELSE DEST [127:64] SRC2[127:64] FI
IF (MASK[191] = 0) THEN DEST[191:128] SRC1[191:128]
ELSE DEST [191:128] SRC2[191:128] FI
IF (MASK[255] = 0) THEN DEST[255:192] SRC1[255:192]
ELSE DEST [255:192] SRC2[255:192] FI
Intel C/C++ Compiler Intrinsic Equivalent
BLENDVPD:
__m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3);
VBLENDVPD:
__m128 _mm_blendv_pd (__m128d a, __m128d b, __m128d mask);
VBLENDVPD:
__m256 _mm256_blendv_pd (__m256d a, __m256d b, __m256d mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
3-84 Vol. 2A
If VEX.W = 1.
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 14 /r
RM0
V/V
SSE4_1
Select packed single precision floating-point
values from xmm1 and xmm2/m128 from
mask specified in XMM0 and store the values
into xmm1.
RVMR V/V
AVX
Conditionally copy single-precision floatingpoint values from xmm2 or xmm3/m128 to
xmm1, based on mask bits in the specified
mask operand, xmm4.
RVMR V/V
AVX
Conditionally copy single-precision floatingpoint values from ymm2 or ymm3/m256 to
ymm1, based on mask bits in the specified
mask register, ymm4.
BLENDVPS xmm1, xmm2/m128,
VEX.NDS.128.66.0F3A.W0 4A /r /is4
VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4
VEX.NDS.256.66.0F3A.W0 4A /r /is4
VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM0
ModRM:reg (r, w)
ModRM:r/m (r)
implicit XMM0
NA
RVMR
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8[7:4]
Description
Conditionally copy each dword data element of single-precision floating-point value from the second source
operand and the first source operand depending on mask bits defined in the mask register operand. The mask bits
are the most significant bit in each dword element of the mask register.
Each quadword element of the destination operand is copied from:
•
•
the corresponding dword element in the second source operand, if a mask bit is “1”; or
the corresponding dword element in the first source operand, if a mask bit is “0”
The register assignment of the implicit mask operand for BLENDVPS is defined to be the architectural register
XMM0.
128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined
to be the architectural register XMM0. An attempt to execute BLENDVPS with a VEX prefix will cause #UD.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.
VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source
operand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. VEX.W must be 0, otherwise, the instruction will #UD.
VBLENDVPS permits the mask to be any XMM or YMM register. In contrast, BLENDVPS treats XMM0 implicitly as the
mask and do not support non-destructive destination operation.
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
Vol. 2A 3-85
INSTRUCTION SET REFERENCE, A-L
Operation
BLENDVPS (128-bit Legacy SSE version)
MASK XMM0
IF (MASK[31] = 0) THEN DEST[31:0] DEST[31:0]
ELSE DEST [31:0] SRC[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32] DEST[63:32]
ELSE DEST [63:32] SRC[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64] DEST[95:64]
ELSE DEST [95:64] SRC[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96] DEST[127:96]
ELSE DEST [127:96] SRC[127:96] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDVPS (VEX.128 encoded version)
MASK SRC3
IF (MASK[31] = 0) THEN DEST[31:0] SRC1[31:0]
ELSE DEST [31:0] SRC2[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32] SRC1[63:32]
ELSE DEST [63:32] SRC2[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64] SRC1[95:64]
ELSE DEST [95:64] SRC2[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96] SRC1[127:96]
ELSE DEST [127:96] SRC2[127:96] FI
DEST[VLMAX-1:128] 0
VBLENDVPS (VEX.256 encoded version)
MASK SRC3
IF (MASK[31] = 0) THEN DEST[31:0] SRC1[31:0]
ELSE DEST [31:0] SRC2[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32] SRC1[63:32]
ELSE DEST [63:32] SRC2[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64] SRC1[95:64]
ELSE DEST [95:64] SRC2[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96] SRC1[127:96]
ELSE DEST [127:96] SRC2[127:96] FI
IF (MASK[159] = 0) THEN DEST[159:128] SRC1[159:128]
ELSE DEST [159:128] SRC2[159:128] FI
IF (MASK[191] = 0) THEN DEST[191:160] SRC1[191:160]
ELSE DEST [191:160] SRC2[191:160] FI
IF (MASK[223] = 0) THEN DEST[223:192] SRC1[223:192]
ELSE DEST [223:192] SRC2[223:192] FI
IF (MASK[255] = 0) THEN DEST[255:224] SRC1[255:224]
ELSE DEST [255:224] SRC2[255:224] FI
Intel C/C++ Compiler Intrinsic Equivalent
BLENDVPS:
__m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3);
VBLENDVPS:
__m128 _mm_blendv_ps (__m128 a, __m128 b, __m128 mask);
VBLENDVPS:
__m256 _mm256_blendv_ps (__m256 a, __m256 b, __m256 mask);
SIMD Floating-Point Exceptions
None
3-86 Vol. 2A
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.W = 1.
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
Vol. 2A 3-87
INSTRUCTION SET REFERENCE, A-L
BLSI — Extract Lowest Set Isolated Bit
Opcode/Instruction
Op/
En
VM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDD.LZ.0F38.W0 F3 /3
BLSI r32, r/m32
VEX.NDD.LZ.0F38.W1 F3 /3
BLSI r64, r/m64
Description
Extract lowest set bit from r/m32 and set that bit in r32.
VM
V/N.E.
BMI1
Extract lowest set bit from r/m64, and set that bit in r64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
VM
VEX.vvvv (w)
ModRM:r/m (r)
NA
NA
Description
Extracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All
other bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in
the destination to 0 and sets ZF and CF.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
temp ← (-SRC) bitwiseAND (SRC);
SF ← temp[OperandSize -1];
ZF ← (temp = 0);
IF SRC = 0
CF ← 0;
ELSE
CF ← 1;
FI
DEST ← temp;
Flags Affected
ZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF
flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BLSI:
unsigned __int32 _blsi_u32(unsigned __int32 src);
BLSI:
unsigned __int64 _blsi_u64(unsigned __int64 src);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
3-88 Vol. 2A
If VEX.W = 1.
BLSI — Extract Lowest Set Isolated Bit
INSTRUCTION SET REFERENCE, A-L
BLSMSK — Get Mask Up to Lowest Set Bit
Opcode/Instruction
Op/
En
VM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDD.LZ.0F38.W0 F3 /2
BLSMSK r32, r/m32
VEX.NDD.LZ.0F38.W1 F3 /2
BLSMSK r64, r/m64
VM
V/N.E.
BMI1
Description
Set all lower bits in r32 to “1” starting from bit 0 to lowest set bit in
r/m32.
Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in
r/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
VM
VEX.vvvv (w)
ModRM:r/m (r)
NA
NA
Description
Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source
operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
temp ← (SRC-1) XOR (SRC) ;
SF ← temp[OperandSize -1];
ZF ← 0;
IF SRC = 0
CF ← 1;
ELSE
CF ← 0;
FI
DEST ← temp;
Flags Affected
SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are
undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BLSMSK:
unsigned __int32 _blsmsk_u32(unsigned __int32 src);
BLSMSK:
unsigned __int64 _blsmsk_u64(unsigned __int64 src);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
BLSMSK — Get Mask Up to Lowest Set Bit
Vol. 2A 3-89
INSTRUCTION SET REFERENCE, A-L
BLSR — Reset Lowest Set Bit
Opcode/Instruction
Op/
En
VM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDD.LZ.0F38.W0 F3 /1
BLSR r32, r/m32
VEX.NDD.LZ.0F38.W1 F3 /1
BLSR r64, r/m64
VM
V/N.E.
BMI1
Description
Reset lowest set bit of r/m32, keep all other bits of r/m32 and write
result to r32.
Reset lowest set bit of r/m64, keep all other bits of r/m64 and write
result to r64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
VM
VEX.vvvv (w)
ModRM:r/m (r)
NA
NA
Description
Copies all bits from the source operand to the destination operand and resets (=0) the bit position in the destination operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets
CF.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
temp ← (SRC-1) bitwiseAND ( SRC );
SF ← temp[OperandSize -1];
ZF ← (temp = 0);
IF SRC = 0
CF ← 1;
ELSE
CF ← 0;
FI
DEST ← temp;
Flags Affected
ZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags
are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BLSR:
unsigned __int32 _blsr_u32(unsigned __int32 src);
BLSR:
unsigned __int64 _blsr_u64(unsigned __int64 src);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
3-90 Vol. 2A
If VEX.W = 1.
BLSR — Reset Lowest Set Bit
INSTRUCTION SET REFERENCE, A-L
BNDCL—Check Lower Bound
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
NE/V
CPUID
Feature
Flag
MPX
F3 0F 1A /r
BNDCL bnd, r/m32
F3 0F 1A /r
BNDCL bnd, r/m64
RM
V/NE
MPX
Description
Generate a #BR if the address in r/m32 is lower than the lower
bound in bnd.LB.
Generate a #BR if the address in r/m64 is lower than the lower
bound in bnd.LB.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
Description
Compare the address in the second operand with the lower bound in bnd. The second operand can be either a
register or memory operand. If the address is lower than the lower bound in bnd.LB, it will set BNDSTATUS to 01H
and signal a #BR exception.
This instruction does not cause any memory access, and does not read or write any flags.
Operation
BNDCL BND, reg
IF reg < BND.LB Then
BNDSTATUS 01H;
#BR;
FI;
BNDCL BND, mem
TEMP LEA(mem);
IF TEMP < BND.LB Then
BNDSTATUS 01H;
#BR;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDCL void _bnd_chk_ptr_lbounds(const void *q)
Flags Affected
None
Protected Mode Exceptions
#BR
If lower bound check fails.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
BNDCL—Check Lower Bound
Vol. 2A 3-91
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#BR
#UD
If lower bound check fails.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Virtual-8086 Mode Exceptions
#BR
#UD
If lower bound check fails.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
Same exceptions as in protected mode.
3-92 Vol. 2A
BNDCL—Check Lower Bound
INSTRUCTION SET REFERENCE, A-L
BNDCU/BNDCN—Check Upper Bound
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
NE/V
CPUID
Feature
Flag
MPX
F2 0F 1A /r
BNDCU bnd, r/m32
F2 0F 1A /r
BNDCU bnd, r/m64
F2 0F 1B /r
BNDCN bnd, r/m32
F2 0F 1B /r
BNDCN bnd, r/m64
RM
V/NE
MPX
RM
NE/V
MPX
RM
V/NE
MPX
Description
Generate a #BR if the address in r/m32 is higher than the upper
bound in bnd.UB (bnb.UB in 1's complement form).
Generate a #BR if the address in r/m64 is higher than the upper
bound in bnd.UB (bnb.UB in 1's complement form).
Generate a #BR if the address in r/m32 is higher than the upper
bound in bnd.UB (bnb.UB not in 1's complement form).
Generate a #BR if the address in r/m64 is higher than the upper
bound in bnd.UB (bnb.UB not in 1's complement form).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
Description
Compare the address in the second operand with the upper bound in bnd. The second operand can be either a
register or a memory operand. If the address is higher than the upper bound in bnd.UB, it will set BNDSTATUS to
01H and signal a #BR exception.
BNDCU perform 1’s complement operation on the upper bound of bnd first before proceeding with address comparison. BNDCN perform address comparison directly using the upper bound in bnd that is already reverted out of 1’s
complement form.
This instruction does not cause any memory access, and does not read or write any flags.
Effective address computation of m32/64 has identical behavior to LEA
Operation
BNDCU BND, reg
IF reg > NOT(BND.UB) Then
BNDSTATUS 01H;
#BR;
FI;
BNDCU BND, mem
TEMP LEA(mem);
IF TEMP > NOT(BND.UB) Then
BNDSTATUS 01H;
#BR;
FI;
BNDCN BND, reg
IF reg > BND.UB Then
BNDSTATUS 01H;
#BR;
FI;
BNDCU/BNDCN—Check Upper Bound
Vol. 2A 3-93
INSTRUCTION SET REFERENCE, A-L
BNDCN BND, mem
TEMP LEA(mem);
IF TEMP > BND.UB Then
BNDSTATUS 01H;
#BR;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDCU .void _bnd_chk_ptr_ubounds(const void *q)
Flags Affected
None
Protected Mode Exceptions
#BR
If upper bound check fails.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
Real-Address Mode Exceptions
#BR
#UD
If upper bound check fails.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Virtual-8086 Mode Exceptions
#BR
If upper bound check fails.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
Same exceptions as in protected mode.
3-94 Vol. 2A
BNDCU/BNDCN—Check Upper Bound
INSTRUCTION SET REFERENCE, A-L
BNDLDX—Load Extended Bounds Using Address Translation
Opcode/
Instruction
Op/En
0F 1A /r
BNDLDX bnd, mib
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
MPX
Description
Load the bounds stored in a bound table entry (BTE) into bnd with
address translation using the base of mib and conditional on the
index of mib matching the pointer value in the BTE.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
SIB.base (r): Address of pointer
SIB.index(r)
NA
Description
BNDLDX uses the linear address constructed from the base register and displacement of the SIB-addressing form
of the memory operand (mib) to perform address translation to access a bound table entry and conditionally load
the bounds in the BTE to the destination. The destination register is updated with the bounds in the BTE, if the
content of the index register of mib matches the pointer value stored in the BTE.
If the pointer value comparison fails, the destination is updated with INIT bounds (lb = 0x0, ub = 0x0) (note: as
articulated earlier, the upper bound is represented using 1's complement, therefore, the 0x0 value of upper bound
allows for access to full memory).
This instruction does not cause memory access to the linear address of mib nor the effective address referenced by
the base, and does not read or write any flags.
Segment overrides apply to the linear address computation with the base of mib, and are used during address
translation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be
linear address. There are no segmentation checks performed on the base of mib.
The base of mib will not be checked for canonical address violation as it does not access memory.
Any encoding of this instruction that does not specify base or index register will treat those registers as zero
(constant). The reg-reg form of this instruction will remain a NOP.
The scale field of the SIB byte has no effect on these instructions and is ignored.
The bound register may be partially updated on memory faults. The order in which memory operands are loaded is
implementation specific.
Operation
base mib.SIB.base ? mib.SIB.base + Disp: 0;
ptr_value mib.SIB.index ? mib.SIB.index : 0;
Outside 64-bit mode
A_BDE[31:0] (Zero_extend32(base[31:12] « 2) + (BNDCFG[31:12] «12 );
A_BT[31:0] LoadFrom(A_BDE );
IF A_BT[0] equal 0 Then
BNDSTATUS A_BDE | 02H;
#BR;
FI;
A_BTE[31:0] (Zero_extend32(base[11:2] « 4) + (A_BT[31:2] « 2 );
Temp_lb[31:0] LoadFrom(A_BTE);
Temp_ub[31:0] LoadFrom(A_BTE + 4);
Temp_ptr[31:0] LoadFrom(A_BTE + 8);
IF Temp_ptr equal ptr_value Then
BND.LB Temp_lb;
BND.UB Temp_ub;
BNDLDX—Load Extended Bounds Using Address Translation
Vol. 2A 3-95
INSTRUCTION SET REFERENCE, A-L
ELSE
BND.LB 0;
BND.UB 0;
FI;
In 64-bit mode
A_BDE[63:0] (Zero_extend64(base[47+MAWA:20] « 3) + (BNDCFG[63:20] «12 );1
A_BT[63:0] LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
BNDSTATUS A_BDE | 02H;
#BR;
FI;
A_BTE[63:0] (Zero_extend64(base[19:3] « 5) + (A_BT[63:3] « 3 );
Temp_lb[63:0] LoadFrom(A_BTE);
Temp_ub[63:0] LoadFrom(A_BTE + 8);
Temp_ptr[63:0] LoadFrom(A_BTE + 16);
IF Temp_ptr equal ptr_value Then
BND.LB Temp_lb;
BND.UB Temp_ub;
ELSE
BND.LB 0;
BND.UB 0;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDLDX: Generated by compiler as needed.
Flags Affected
None
Protected Mode Exceptions
#BR
If the bound directory entry is invalid.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
If DS register contains a NULL segment selector.
#PF(fault code)
If a page fault occurs.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumerated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
3-96 Vol. 2A
BNDLDX—Load Extended Bounds Using Address Translation
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
#PF(fault code)
If a page fault occurs.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#BR
#UD
If the bound directory entry is invalid.
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#GP(0)
If the memory address (A_BDE or A_BTE) is in a non-canonical form.
#PF(fault code)
If a page fault occurs.
BNDLDX—Load Extended Bounds Using Address Translation
Vol. 2A 3-97
INSTRUCTION SET REFERENCE, A-L
BNDMK—Make Bounds
Opcode/
Instruction
Op/En
CPUID
Feature
Flag
MPX
Description
RM
64/32
bit Mode
Support
NE/V
F3 0F 1B /r
BNDMK bnd, m32
F3 0F 1B /r
BNDMK bnd, m64
RM
V/NE
MPX
Make lower and upper bounds from m64 and store them in bnd.
Make lower and upper bounds from m32 and store them in bnd.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
Description
Makes bounds from the second operand and stores the lower and upper bounds in the bound register bnd. The
second operand must be a memory operand. The content of the base register from the memory operand is stored
in the lower bound bnd.LB. The 1's complement of the effective address of m32/m64 is stored in the upper bound
b.UB. Computation of m32/m64 has identical behavior to LEA.
This instruction does not cause any memory access, and does not read or write any flags.
If the instruction did not specify base register, the lower bound will be zero. The reg-reg form of this instruction
retains legacy behavior (NOP).
RIP relative instruction in 64-bit will #UD.
Operation
BND.LB SRCMEM.base;
IF 64-bit mode Then
BND.UB NOT(LEA.64_bits(SRCMEM));
ELSE
BND.UB Zero_Extend.64_bits(NOT(LEA.32_bits(SRCMEM)));
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDMKvoid * _bnd_set_ptr_bounds(const void * q, size_t size);
Flags Affected
None
Protected Mode Exceptions
#UD
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
Real-Address Mode Exceptions
#UD
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
3-98 Vol. 2A
BNDMK—Make Bounds
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#SS(0)
If the memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
Same exceptions as in protected mode.
BNDMK—Make Bounds
Vol. 2A 3-99
INSTRUCTION SET REFERENCE, A-L
BNDMOV—Move Bounds
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
NE/V
CPUID
Feature
Flag
MPX
66 0F 1A /r
BNDMOV bnd1, bnd2/m64
66 0F 1A /r
BNDMOV bnd1, bnd2/m128
66 0F 1B /r
BNDMOV bnd1/m64, bnd2
66 0F 1B /r
BNDMOV bnd1/m128, bnd2
RM
V/NE
MPX
MR
NE/V
MPX
MR
V/NE
MPX
Description
Move lower and upper bound from bnd2/m64 to bound register
bnd1.
Move lower and upper bound from bnd2/m128 to bound register
bnd1.
Move lower and upper bound from bnd2 to bnd1/m64.
Move lower and upper bound from bnd2 to bound register
bnd1/m128.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
Description
BNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the
destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction.
The memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.
Upper Bound (UB)
BNDMOV to memory in 64-bit mode
Lower Bound (LB)
16
0
8
Upper Bound (UB)
16
BNDMOV to memory in 32-bit mode
Lower Bound (LB)
8
Byte offset
4
0
Byte offset
Figure 3-5. Memory Layout of BNDMOV to/from Memory
This instruction does not change flags.
Operation
BNDMOV register to register
DEST.LB SRC.LB;
DEST.UB SRC.UB;
3-100 Vol. 2A
BNDMOV—Move Bounds
INSTRUCTION SET REFERENCE, A-L
BNDMOV from memory
IF 64-bit mode THEN
DEST.LB LOAD_QWORD(SRC);
DEST.UB LOAD_QWORD(SRC+8);
ELSE
DEST.LB LOAD_DWORD_ZERO_EXT(SRC);
DEST.UB LOAD_DWORD_ZERO_EXT(SRC+4);
FI;
BNDMOV to memory
IF 64-bit mode THEN
DEST[63:0] SRC.LB;
DEST[127:64] SRC.UB;
ELSE
DEST[31:0] SRC.LB;
DEST[63:32] SRC.UB;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDMOV
void * _bnd_copy_ptr_bounds(const void *q, const void *r)
Flags Affected
None
Protected Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
#SS(0)
#GP(0)
If the memory operand effective address is outside the SS segment limit.
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the destination operand points to a non-writable segment
If the DS, ES, FS, or GS segment register contains a NULL segment selector.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code)
If a page fault occurs.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If the memory operand effective address is outside the SS segment limit.
BNDMOV—Move Bounds
Vol. 2A 3-101
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If the memory operand effective address is outside the SS segment limit.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code)
If a page fault occurs.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#SS(0)
If the memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code)
If a page fault occurs.
3-102 Vol. 2A
BNDMOV—Move Bounds
INSTRUCTION SET REFERENCE, A-L
BNDSTX—Store Extended Bounds Using Address Translation
Opcode/
Instruction
Op/En
0F 1B /r
BNDSTX mib, bnd
MR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
MPX
Description
Store the bounds in bnd and the pointer value in the index register of mib to a bound table entry (BTE) with address translation
using the base of mib.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
MR
SIB.base (r): Address of pointer
SIB.index(r)
ModRM:reg (r)
NA
Description
BNDSTX uses the linear address constructed from the displacement and base register of the SIB-addressing form
of the memory operand (mib) to perform address translation to store to a bound table entry. The bounds in the
source operand bnd are written to the lower and upper bounds in the BTE. The content of the index register of mib
is written to the pointer value field in the BTE.
This instruction does not cause memory access to the linear address of mib nor the effective address referenced by
the base, and does not read or write any flags.
Segment overrides apply to the linear address computation with the base of mib, and are used during address
translation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be
linear address. There are no segmentation checks performed on the base of mib.
The base of mib will not be checked for canonical address violation as it does not access memory.
Any encoding of this instruction that does not specify base or index register will treat those registers as zero
(constant). The reg-reg form of this instruction will remain a NOP.
The scale field of the SIB byte has no effect on these instructions and is ignored.
The bound register may be partially updated on memory faults. The order in which memory operands are loaded is
implementation specific.
Operation
base mib.SIB.base ? mib.SIB.base + Disp: 0;
ptr_value mib.SIB.index ? mib.SIB.index : 0;
Outside 64-bit mode
A_BDE[31:0] (Zero_extend32(base[31:12] « 2) + (BNDCFG[31:12] «12 );
A_BT[31:0] LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
BNDSTATUS A_BDE | 02H;
#BR;
FI;
A_DEST[31:0] (Zero_extend32(base[11:2] « 4) + (A_BT[31:2] « 2 ); // address of Bound table entry
A_DEST[8][31:0] ptr_value;
A_DEST[0][31:0] BND.LB;
A_DEST[4][31:0] BND.UB;
BNDSTX—Store Extended Bounds Using Address Translation
Vol. 2A 3-103
INSTRUCTION SET REFERENCE, A-L
In 64-bit mode
A_BDE[63:0] (Zero_extend64(base[47+MAWA:20] « 3) + (BNDCFG[63:20] «12 );1
A_BT[63:0] LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
BNDSTATUS A_BDE | 02H;
#BR;
FI;
A_DEST[63:0] (Zero_extend64(base[19:3] « 5) + (A_BT[63:3] « 3 ); // address of Bound table entry
A_DEST[16][63:0] ptr_value;
A_DEST[0][63:0] BND.LB;
A_DEST[8][63:0] BND.UB;
Intel C/C++ Compiler Intrinsic Equivalent
BNDSTX: _bnd_store_ptr_bounds(const void **ptr_addr, const void *ptr_val);
Flags Affected
None
Protected Mode Exceptions
#BR
If the bound directory entry is invalid.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
If DS register contains a NULL segment selector.
If the destination operand points to a non-writable segment
#PF(fault code)
If a page fault occurs.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
#PF(fault code)
If a page fault occurs.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumerated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
3-104 Vol. 2A
BNDSTX—Store Extended Bounds Using Address Translation
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
#BR
#UD
If the bound directory entry is invalid.
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#GP(0)
If the memory address (A_BDE or A_BTE) is in a non-canonical form.
If the destination operand points to a non-writable segment
#PF(fault code)
If a page fault occurs.
BNDSTX—Store Extended Bounds Using Address Translation
Vol. 2A 3-105
INSTRUCTION SET REFERENCE, A-L
BOUND—Check Array Index Against Bounds
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
62 /r
BOUND r16, m16&16
RM
Invalid
Valid
Check if r16 (array index) is within bounds
specified by m16&16.
62 /r
BOUND r32, m32&32
RM
Invalid
Valid
Check if r32 (array index) is within bounds
specified by m32&32.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
Description
BOUND determines if the first operand (array index) is within the bounds of an array specified the second operand
(bounds operand). The array index is a signed integer located in a register. The bounds operand is a memory location that contains a pair of signed doubleword-integers (when the operand-size attribute is 32) or a pair of signed
word-integers (when the operand-size attribute is 16). The first doubleword (or word) is the lower bound of the
array and the second doubleword (or word) is the upper bound of the array. The array index must be greater than
or equal to the lower bound and less than or equal to the upper bound plus the operand size in bytes. If the index
is not within bounds, a BOUND range exceeded exception (#BR) is signaled. When this exception is generated, the
saved return instruction pointer points to the BOUND instruction.
The bounds limit data structure (two words or doublewords containing the lower and upper limits of the array) is
usually placed just before the array itself, making the limits addressable via a constant offset from the beginning of
the array. Because the address of the array already will be present in a register, this practice avoids extra bus cycles
to obtain the effective address of the array bounds.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64bit Mode
THEN
#UD;
ELSE
IF (ArrayIndex < LowerBound OR ArrayIndex > UpperBound)
(* Below lower bound or above upper bound *)
THEN #BR; FI;
FI;
Flags Affected
None.
Protected Mode Exceptions
#BR
If the bounds test fails.
#UD
If second operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-106 Vol. 2A
BOUND—Check Array Index Against Bounds
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#BR
#UD
If the bounds test fails.
If second operand is not a memory location.
If the LOCK prefix is used.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
Virtual-8086 Mode Exceptions
#BR
If the bounds test fails.
#UD
If second operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
BOUND—Check Array Index Against Bounds
Vol. 2A 3-107
INSTRUCTION SET REFERENCE, A-L
BSF—Bit Scan Forward
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F BC /r
BSF r16, r/m16
RM
Valid
Valid
Bit scan forward on r/m16.
0F BC /r
BSF r32, r/m32
RM
Valid
Valid
Bit scan forward on r/m32.
REX.W + 0F BC /r
BSF r64, r/m64
RM
Valid
N.E.
Bit scan forward on r/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Searches the source operand (second operand) for the least significant set bit (1 bit). If a least significant 1 bit is
found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a
memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source
operand. If the content of the source operand is 0, the content of the destination operand is undefined.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
IF SRC = 0
THEN
ZF ← 1;
DEST is undefined;
ELSE
ZF ← 0;
temp ← 0;
WHILE Bit(SRC, temp) = 0
DO
temp ← temp + 1;
OD;
DEST ← temp;
FI;
Flags Affected
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags
are undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-108 Vol. 2A
BSF—Bit Scan Forward
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
BSF—Bit Scan Forward
Vol. 2A 3-109
INSTRUCTION SET REFERENCE, A-L
BSR—Bit Scan Reverse
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F BD /r
BSR r16, r/m16
RM
Valid
Valid
Bit scan reverse on r/m16.
0F BD /r
BSR r32, r/m32
RM
Valid
Valid
Bit scan reverse on r/m32.
REX.W + 0F BD /r
BSR r64, r/m64
RM
Valid
N.E.
Bit scan reverse on r/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Searches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is
found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a
memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source
operand. If the content source operand is 0, the content of the destination operand is undefined.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
IF SRC = 0
THEN
ZF ← 1;
DEST is undefined;
ELSE
ZF ← 0;
temp ← OperandSize – 1;
WHILE Bit(SRC, temp) = 0
DO
temp ← temp - 1;
OD;
DEST ← temp;
FI;
Flags Affected
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags
are undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-110 Vol. 2A
BSR—Bit Scan Reverse
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
BSR—Bit Scan Reverse
Vol. 2A 3-111
INSTRUCTION SET REFERENCE, A-L
BSWAP—Byte Swap
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F C8+rd
BSWAP r32
O
Valid*
Valid
Reverses the byte order of a 32-bit register.
REX.W + 0F C8+rd
BSWAP r64
O
Valid
N.E.
Reverses the byte order of a 64-bit register.
NOTES:
* See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
O
opcode + rd (r, w)
NA
NA
NA
Description
Reverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting littleendian values to big-endian format and vice versa. To swap bytes in a word value (16-bit register), use the XCHG
instruction. When the BSWAP instruction references a 16-bit register, the result is undefined.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
IA-32 Architecture Legacy Compatibility
The BSWAP instruction is not supported on IA-32 processors earlier than the Intel486™ processor family. For
compatibility with this instruction, software should include functionally equivalent code for execution on Intel
processors earlier than the Intel486 processor family.
Operation
TEMP ← DEST
IF 64-bit mode AND OperandSize = 64
THEN
DEST[7:0] ← TEMP[63:56];
DEST[15:8] ← TEMP[55:48];
DEST[23:16] ← TEMP[47:40];
DEST[31:24] ← TEMP[39:32];
DEST[39:32] ← TEMP[31:24];
DEST[47:40] ← TEMP[23:16];
DEST[55:48] ← TEMP[15:8];
DEST[63:56] ← TEMP[7:0];
ELSE
DEST[7:0] ← TEMP[31:24];
DEST[15:8] ← TEMP[23:16];
DEST[23:16] ← TEMP[15:8];
DEST[31:24] ← TEMP[7:0];
FI;
Flags Affected
None.
Exceptions (All Operating Modes)
#UD
3-112 Vol. 2A
If the LOCK prefix is used.
BSWAP—Byte Swap
INSTRUCTION SET REFERENCE, A-L
BT—Bit Test
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F A3 /r
BT r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag.
0F A3 /r
BT r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag.
REX.W + 0F A3 /r
BT r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag.
0F BA /4 ib
BT r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag.
0F BA /4 ib
BT r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag.
REX.W + 0F BA /4 ib
BT r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset (specified by the second operand) and stores the value of the bit in the CF flag. The bit base operand
can be a register or a memory location; the bit offset operand can be a register or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode).
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bit operands) of the immediate bit offset are stored in the immediate bit offset field, and the highorder bits are shifted and combined with the byte displacement in the addressing mode by the assembler. The
processor will ignore the high order bits if they are not zero.
When accessing a bit in memory, the processor may access 4 bytes starting from the memory address for a 32-bit
operand size, using by the following relationship:
Effective Address + (4 ∗ (BitOffset DIV 32))
Or, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship:
Effective Address + (2 ∗ (BitOffset DIV 16))
It may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit
addressing mechanism, software should avoid referencing areas of memory close to address space holes. In particular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOV instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the
data.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit operands. See the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
BT—Bit Test
Vol. 2A 3-113
INSTRUCTION SET REFERENCE, A-L
Flags Affected
The CF flag contains the value of the selected bit. The ZF flag is unaffected. The OF, SF, AF, and PF flags are
undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-114 Vol. 2A
BT—Bit Test
INSTRUCTION SET REFERENCE, A-L
BTC—Bit Test and Complement
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F BB /r
BTC r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag and complement.
0F BB /r
BTC r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag and complement.
REX.W + 0F BB /r
BTC r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag and complement.
0F BA /7 ib
BTC r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag and complement.
0F BA /7 ib
BTC r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag and complement.
REX.W + 0F BA /7 ib
BTC r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag and complement.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected
bit in the bit string. The bit base operand can be a register or a memory location; the bit offset operand can be a
register or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode). This allows any bit position to be selected.
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on
this addressing mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) ← NOT Bit(BitBase, BitOffset);
Flags Affected
The CF flag contains the value of the selected bit before it is complemented. The ZF flag is unaffected. The OF, SF,
AF, and PF flags are undefined.
BTC—Bit Test and Complement
Vol. 2A 3-115
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-116 Vol. 2A
BTC—Bit Test and Complement
INSTRUCTION SET REFERENCE, A-L
BTR—Bit Test and Reset
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F B3 /r
BTR r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag and clear.
0F B3 /r
BTR r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag and clear.
REX.W + 0F B3 /r
BTR r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag and clear.
0F BA /6 ib
BTR r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag and clear.
0F BA /6 ib
BTR r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag and clear.
REX.W + 0F BA /6 ib
BTR r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag and clear.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset operand (second operand), stores the value of the bit in the CF flag, and clears the selected bit in the
bit string to 0. The bit base operand can be a register or a memory location; the bit offset operand can be a register
or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode). This allows any bit position to be selected.
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on
this addressing mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) ← 0;
Flags Affected
The CF flag contains the value of the selected bit before it is cleared. The ZF flag is unaffected. The OF, SF, AF, and
PF flags are undefined.
BTR—Bit Test and Reset
Vol. 2A 3-117
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-118 Vol. 2A
BTR—Bit Test and Reset
INSTRUCTION SET REFERENCE, A-L
BTS—Bit Test and Set
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F AB /r
BTS r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag and set.
0F AB /r
BTS r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag and set.
REX.W + 0F AB /r
BTS r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag and set.
0F BA /5 ib
BTS r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag and set.
0F BA /5 ib
BTS r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag and set.
REX.W + 0F BA /5 ib
BTS r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag and set.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset operand (second operand), stores the value of the bit in the CF flag, and sets the selected bit in the
bit string to 1. The bit base operand can be a register or a memory location; the bit offset operand can be a register
or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode). This allows any bit position to be selected.
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on
this addressing mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) ← 1;
Flags Affected
The CF flag contains the value of the selected bit before it is set. The ZF flag is unaffected. The OF, SF, AF, and PF
flags are undefined.
BTS—Bit Test and Set
Vol. 2A 3-119
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-120 Vol. 2A
BTS—Bit Test and Set
INSTRUCTION SET REFERENCE, A-L
BZHI — Zero High Bits Starting with Specified Bit Position
Opcode/Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI2
VEX.NDS.LZ.0F38.W0 F5 /r
BZHI r32a, r/m32, r32b
VEX.NDS.LZ.0F38.W1 F5 /r
BZHI r64a, r/m64, r64b
RMV
V/N.E.
BMI2
Description
Zero bits in r/m32 starting with the position in r32b, write result to
r32a.
Zero bits in r/m64 starting with the position in r64b, write result to
r64a.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (w)
ModRM:r/m (r)
VEX.vvvv (r)
NA
Description
BZHI copies the bits of the first source operand (the second operand) into the destination operand (the first
operand) and clears the higher bits in the destination according to the INDEX value specified by the second source
operand (the third operand). The INDEX is specified by bits 7:0 of the second source operand. The INDEX value is
saturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand
is greater than OperandSize -1.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
N ← SRC2[7:0]
DEST ← SRC1
IF (N < OperandSize)
DEST[OperandSize-1:N] ← 0
FI
IF (N > OperandSize - 1)
CF ← 1
ELSE
CF ← 0
FI
Flags Affected
ZF, CF and SF flags are updated based on the result. OF flag is cleared. AF and PF flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BZHI:
unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index);
BZHI:
unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
BZHI — Zero High Bits Starting with Specified Bit Position
Vol. 2A 3-121
INSTRUCTION SET REFERENCE, A-L
CALL—Call Procedure
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
E8 cw
CALL rel16
M
N.S.
Valid
Call near, relative, displacement relative to next
instruction.
E8 cd
CALL rel32
M
Valid
Valid
Call near, relative, displacement relative to next
instruction. 32-bit displacement sign extended to
64-bits in 64-bit mode.
FF /2
CALL r/m16
M
N.E.
Valid
Call near, absolute indirect, address given in r/m16.
FF /2
CALL r/m32
M
N.E.
Valid
Call near, absolute indirect, address given in r/m32.
FF /2
CALL r/m64
M
Valid
N.E.
Call near, absolute indirect, address given in r/m64.
9A cd
CALL ptr16:16
D
Invalid
Valid
Call far, absolute, address given in operand.
9A cp
CALL ptr16:32
D
Invalid
Valid
Call far, absolute, address given in operand.
FF /3
CALL m16:16
M
Valid
Valid
Call far, absolute indirect address given in m16:16.
In 32-bit mode: if selector points to a gate, then RIP
= 32-bit zero extended displacement taken from
gate; else RIP = zero extended 16-bit offset from
far pointer referenced in the instruction.
FF /3
CALL m16:32
M
Valid
Valid
In 64-bit mode: If selector points to a gate, then RIP
= 64-bit displacement taken from gate; else RIP =
zero extended 32-bit offset from far pointer
referenced in the instruction.
REX.W + FF /3
CALL m16:64
M
Valid
N.E.
In 64-bit mode: If selector points to a gate, then RIP
= 64-bit displacement taken from gate; else RIP =
64-bit offset from far pointer referenced in the
instruction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
D
Offset
NA
NA
NA
M
ModRM:r/m (r)
NA
NA
NA
Description
Saves procedure linking information on the stack and branches to the called procedure specified using the target
operand. The target operand specifies the address of the first instruction in the called procedure. The operand can
be an immediate value, a general-purpose register, or a memory location.
This instruction can be used to execute four types of calls:
•
Near Call — A call to a procedure in the current code segment (the segment currently pointed to by the CS
register), sometimes referred to as an intra-segment call.
•
Far Call — A call to a procedure located in a different segment than the current code segment, sometimes
referred to as an inter-segment call.
•
Inter-privilege-level far call — A far call to a procedure in a segment at a different privilege level than that
of the currently executing program or procedure.
•
Task switch — A call to a procedure located in a different task.
The latter two call types (inter-privilege-level call and task switch) can only be executed in protected mode. See
“Calling Procedures Using Call and RET” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for additional information on near, far, and inter-privilege-level calls. See Chapter 7,
“Task Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for information on performing task switches with the CALL instruction.
3-122 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
Near Call. When executing a near call, the processor pushes the value of the EIP register (which contains the offset
of the instruction following the CALL instruction) on the stack (for use later as a return-instruction pointer). The
processor then branches to the address in the current code segment specified by the target operand. The target
operand specifies either an absolute offset in the code segment (an offset from the base of the code segment) or a
relative offset (a signed displacement relative to the current value of the instruction pointer in the EIP register; this
value points to the instruction following the CALL instruction). The CS register is not changed on near calls.
For a near call absolute, an absolute offset is specified indirectly in a general-purpose register or a memory location
(r/m16, r/m32, or r/m64). The operand-size attribute determines the size of the target operand (16, 32 or 64
bits). When in 64-bit mode, the operand size for near call (and all near branches) is forced to 64-bits. Absolute
offsets are loaded directly into the EIP(RIP) register. If the operand size attribute is 16, the upper two bytes of the
EIP register are cleared, resulting in a maximum instruction pointer size of 16 bits. When accessing an absolute
offset indirectly using the stack pointer [ESP] as the base register, the base value used is the value of the ESP
before the instruction executes.
A relative offset (rel16 or rel32) is generally specified as a label in assembly code. But at the machine code level, it
is encoded as a signed, 16- or 32-bit immediate value. This value is added to the value in the EIP(RIP) register. In
64-bit mode the relative offset is always a 32-bit immediate value which is sign extended to 64-bits before it is
added to the value in the RIP register for the target calculation. As with absolute offsets, the operand-size attribute
determines the size of the target operand (16, 32, or 64 bits). In 64-bit mode the target operand will always be 64bits because the operand size is forced to 64-bits for near branches.
Far Calls in Real-Address or Virtual-8086 Mode. When executing a far call in real- address or virtual-8086 mode, the
processor pushes the current value of both the CS and EIP registers on the stack for use as a return-instruction
pointer. The processor then performs a “far branch” to the code segment and offset specified with the target
operand for the called procedure. The target operand specifies an absolute far address either directly with a pointer
(ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). With the pointer method, the
segment and offset of the called procedure is encoded in the instruction using a 4-byte (16-bit operand size) or 6byte (32-bit operand size) far address immediate. With the indirect method, the target operand specifies a memory
location that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address. The operand-size
attribute determines the size of the offset (16 or 32 bits) in the far address. The far address is loaded directly into
the CS and EIP registers. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared.
Far Calls in Protected Mode. When the processor is operating in protected mode, the CALL instruction can be used to
perform the following types of far calls:
•
•
•
Far call to the same privilege level
Far call to a different privilege level (inter-privilege level call)
Task switch (far call to another task)
In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access
rights determine the type of call operation to be performed.
If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is
performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,
a general-protection exception is generated.) A far call to the same privilege level in protected mode is very similar
to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far address either
directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The
operand- size attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment
selector and its descriptor are loaded into CS register; the offset from the instruction is loaded into the EIP register.
A call gate (described in the next paragraph) can also be used to perform a far call to a code segment at the same
privilege level. Using this mechanism provides an extra level of indirection and is the preferred method of making
calls between 16-bit and 32-bit code segments.
When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed
through a call gate. The segment selector specified by the target operand identifies the call gate. The target
operand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly
with a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code
segment and the new instruction pointer (offset) from the call gate descriptor. (The offset from the target operand
is ignored when a call gate is used.)
CALL—Call Procedure
Vol. 2A 3-123
INSTRUCTION SET REFERENCE, A-L
On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The
segment selector for the new stack segment is specified in the TSS for the currently running task. The branch to
the new code segment occurs after the stack switch. (Note that when using a call gate to perform a far call to a
segment at the same privilege level, no stack switch occurs.) On the new stack, the processor pushes the segment
selector and stack pointer for the calling procedure’s stack, an optional set of parameters from the calling procedures stack, and the segment selector and instruction pointer for the calling procedure’s code segment. (A value in
the call gate descriptor determines how many parameters to copy to the new stack.) Finally, the processor
branches to the address of the procedure being called within the new code segment.
Executing a task switch with the CALL instruction is similar to executing a call through a call gate. The target
operand specifies the segment selector of the task gate for the new task activated by the switch (the offset in the
target operand is ignored). The task gate in turn points to the TSS for the new task, which contains the segment
selectors for the task’s code and stack segments. Note that the TSS also contains the EIP value for the next instruction that was to be executed before the calling task was suspended. This instruction pointer value is loaded into the
EIP register to re-start the calling task.
The CALL instruction can also specify the segment selector of the TSS directly, which eliminates the indirection of
the task gate. See Chapter 7, “Task Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A, for information on the mechanics of a task switch.
When you execute at task switch with a CALL instruction, the nested task flag (NT) is set in the EFLAGS register and
the new TSS’s previous task link field is loaded with the old task’s TSS selector. Code is expected to suspend this
nested task by executing an IRET instruction which, because the NT flag is set, automatically uses the previous
task link to return to the calling task. (See “Task Linking” in Chapter 7 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A, for information on nested tasks.) Switching tasks with the CALL instruction differs in this regard from JMP instruction. JMP does not set the NT flag and therefore does not expect an IRET
instruction to suspend the task.
Mixing 16-Bit and 32-Bit Calls. When making far calls between 16-bit and 32-bit code segments, use a call gate. If
the far call is from a 32-bit code segment to a 16-bit code segment, the call should be made from the first 64
KBytes of the 32-bit code segment. This is because the operand-size attribute of the instruction is set to 16, so only
a 16-bit return address offset can be saved. Also, the call should be made using a 16-bit call gate so that 16-bit
values can be pushed on the stack. See Chapter 21, “Mixing 16-Bit and 32-Bit Code,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3B, for more information.
Far Calls in Compatibility Mode. When the processor is operating in compatibility mode, the CALL instruction can be
used to perform the following types of far calls:
•
•
•
Far call to the same privilege level, remaining in compatibility mode
Far call to the same privilege level, transitioning to 64-bit mode
Far call to a different privilege level (inter-privilege level call), transitioning to 64-bit mode
Note that a CALL instruction can not be used to cause a task switch in compatibility mode since task switches are
not supported in IA-32e mode.
In compatibility mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate) and access rights determine
the type of call operation to be performed.
If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is
performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,
a general-protection exception is generated.) A far call to the same privilege level in compatibility mode is very
similar to one carried out in protected mode. The target operand specifies an absolute far address either directly
with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The operand-size
attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment selector and its
descriptor are loaded into CS register and the offset from the instruction is loaded into the EIP register. The difference is that 64-bit mode may be entered. This specified by the L bit in the new code segment descriptor.
Note that a 64-bit call gate (described in the next paragraph) can also be used to perform a far call to a code
segment at the same privilege level. However, using this mechanism requires that the target code segment
descriptor have the L bit set, causing an entry to 64-bit mode.
When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed
through a 64-bit call gate. The segment selector specified by the target operand identifies the call gate. The target
3-124 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
operand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly
with a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code
segment and the new instruction pointer (offset) from the 16-byte call gate descriptor. (The offset from the target
operand is ignored when a call gate is used.)
On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The
segment selector for the new stack segment is set to NULL. The new stack pointer is specified in the TSS for the
currently running task. The branch to the new code segment occurs after the stack switch. (Note that when using
a call gate to perform a far call to a segment at the same privilege level, an implicit stack switch occurs as a result
of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use a segment base of 0x0,
the limit is ignored, and the default stack size is 64-bits. The full value of RSP is used for the offset, of which the
upper 32-bits are undefined.) On the new stack, the processor pushes the segment selector and stack pointer for
the calling procedure’s stack and the segment selector and instruction pointer for the calling procedure’s code
segment. (Parameter copy is not supported in IA-32e mode.) Finally, the processor branches to the address of the
procedure being called within the new code segment.
Near/(Far) Calls in 64-bit Mode. When the processor is operating in 64-bit mode, the CALL instruction can be used to
perform the following types of far calls:
•
•
•
Far call to the same privilege level, transitioning to compatibility mode
Far call to the same privilege level, remaining in 64-bit mode
Far call to a different privilege level (inter-privilege level call), remaining in 64-bit mode
Note that in this mode the CALL instruction can not be used to cause a task switch in 64-bit mode since task
switches are not supported in IA-32e mode.
In 64-bit mode, the processor always uses the segment selector part of the far address to access the corresponding
descriptor in the GDT or LDT. The descriptor type (code segment, call gate) and access rights determine the type
of call operation to be performed.
If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is
performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,
a general-protection exception is generated.) A far call to the same privilege level in 64-bit mode is very similar to
one carried out in compatibility mode. The target operand specifies an absolute far address indirectly with a
memory location (m16:16, m16:32 or m16:64). The form of CALL with a direct specification of absolute far
address is not defined in 64-bit mode. The operand-size attribute determines the size of the offset (16, 32, or 64
bits) in the far address. The new code segment selector and its descriptor are loaded into the CS register; the offset
from the instruction is loaded into the EIP register. The new code segment may specify entry either into compatibility or 64-bit mode, based on the L bit value.
A 64-bit call gate (described in the next paragraph) can also be used to perform a far call to a code segment at the
same privilege level. However, using this mechanism requires that the target code segment descriptor have the L
bit set.
When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed
through a 64-bit call gate. The segment selector specified by the target operand identifies the call gate. The target
operand can only specify the call gate segment selector indirectly with a memory location (m16:16, m16:32 or
m16:64). The processor obtains the segment selector for the new code segment and the new instruction pointer
(offset) from the 16-byte call gate descriptor. (The offset from the target operand is ignored when a call gate is
used.)
On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The
segment selector for the new stack segment is set to NULL. The new stack pointer is specified in the TSS for the
currently running task. The branch to the new code segment occurs after the stack switch.
Note that when using a call gate to perform a far call to a segment at the same privilege level, an implicit stack
switch occurs as a result of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use
a segment base of 0x0, the limit is ignored, and the default stack size is 64-bits. (The full value of RSP is used for
the offset.) On the new stack, the processor pushes the segment selector and stack pointer for the calling procedure’s stack and the segment selector and instruction pointer for the calling procedure’s code segment. (Parameter
copy is not supported in IA-32e mode.) Finally, the processor branches to the address of the procedure being called
within the new code segment.
CALL—Call Procedure
Vol. 2A 3-125
INSTRUCTION SET REFERENCE, A-L
Operation
IF near call
THEN IF near relative call
THEN
IF OperandSize = 64
THEN
tempDEST ← SignExtend(DEST); (* DEST is rel32 *)
tempRIP ← RIP + tempDEST;
IF stack not large enough for a 8-byte return address
THEN #SS(0); FI;
Push(RIP);
RIP ← tempRIP;
FI;
IF OperandSize = 32
THEN
tempEIP ← EIP + DEST; (* DEST is rel32 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
IF stack not large enough for a 4-byte return address
THEN #SS(0); FI;
Push(EIP);
EIP ← tempEIP;
FI;
IF OperandSize = 16
THEN
tempEIP ← (EIP + DEST) AND 0000FFFFH; (* DEST is rel16 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
IF stack not large enough for a 2-byte return address
THEN #SS(0); FI;
Push(IP);
EIP ← tempEIP;
FI;
ELSE (* Near absolute call *)
IF OperandSize = 64
THEN
tempRIP ← DEST; (* DEST is r/m64 *)
IF stack not large enough for a 8-byte return address
THEN #SS(0); FI;
Push(RIP);
RIP ← tempRIP;
FI;
IF OperandSize = 32
THEN
tempEIP ← DEST; (* DEST is r/m32 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
IF stack not large enough for a 4-byte return address
THEN #SS(0); FI;
Push(EIP);
EIP ← tempEIP;
FI;
IF OperandSize = 16
THEN
tempEIP ← DEST AND 0000FFFFH; (* DEST is r/m16 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
3-126 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
FI;
IF stack not large enough for a 2-byte return address
THEN #SS(0); FI;
Push(IP);
EIP ← tempEIP;
FI;rel/abs
FI; near
IF far call and (PE = 0 or (PE = 1 and VM = 1)) (* Real-address or virtual-8086 mode *)
THEN
IF OperandSize = 32
THEN
IF stack not large enough for a 6-byte return address
THEN #SS(0); FI;
IF DEST[31:16] is not zero THEN #GP(0); FI;
Push(CS); (* Padded with 16 high-order bits *)
Push(EIP);
CS ← DEST[47:32]; (* DEST is ptr16:32 or [m16:32] *)
EIP ← DEST[31:0]; (* DEST is ptr16:32 or [m16:32] *)
ELSE (* OperandSize = 16 *)
IF stack not large enough for a 4-byte return address
THEN #SS(0); FI;
Push(CS);
Push(IP);
CS ← DEST[31:16]; (* DEST is ptr16:16 or [m16:16] *)
EIP ← DEST[15:0]; (* DEST is ptr16:16 or [m16:16]; clear upper 16 bits *)
FI;
FI;
IF far call and (PE = 1 and VM = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*)
THEN
IF segment selector in target operand NULL
THEN #GP(0); FI;
IF segment selector index not within descriptor table limits
THEN #GP(new code segment selector); FI;
Read type and access rights of selected segment descriptor;
IF IA32_EFER.LMA = 0
THEN
IF segment type is not a conforming or nonconforming code segment, call
gate, task gate, or TSS
THEN #GP(segment selector); FI;
ELSE
IF segment type is not a conforming or nonconforming code segment or
64-bit call gate,
THEN #GP(segment selector); FI;
FI;
Depending on type and access rights:
GO TO CONFORMING-CODE-SEGMENT;
GO TO NONCONFORMING-CODE-SEGMENT;
GO TO CALL-GATE;
GO TO TASK-GATE;
GO TO TASK-STATE-SEGMENT;
FI;
CALL—Call Procedure
Vol. 2A 3-127
INSTRUCTION SET REFERENCE, A-L
CONFORMING-CODE-SEGMENT:
IF L bit = 1 and D bit = 1 and IA32_EFER.LMA = 1
THEN GP(new code segment selector); FI;
IF DPL > CPL
THEN #GP(new code segment selector); FI;
IF segment not present
THEN #NP(new code segment selector); FI;
IF stack not large enough for return address
THEN #SS(0); FI;
tempEIP ← DEST(Offset);
IF OperandSize = 16
THEN
tempEIP ← tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code
segment limit)
THEN #GP(0); FI;
IF tempEIP is non-canonical
THEN #GP(0); FI;
IF OperandSize = 32
THEN
Push(CS); (* Padded with 16 high-order bits *)
Push(EIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE
IF OperandSize = 16
THEN
Push(CS);
Push(IP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE (* OperandSize = 64 *)
Push(CS); (* Padded with 48 high-order bits *)
Push(RIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
RIP ← tempEIP;
FI;
FI;
END;
NONCONFORMING-CODE-SEGMENT:
IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1
THEN GP(new code segment selector); FI;
IF (RPL > CPL) or (DPL ≠ CPL)
THEN #GP(new code segment selector); FI;
IF segment not present
THEN #NP(new code segment selector); FI;
IF stack not large enough for return address
3-128 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
THEN #SS(0); FI;
tempEIP ← DEST(Offset);
IF OperandSize = 16
THEN tempEIP ← tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code
segment limit)
THEN #GP(0); FI;
IF tempEIP is non-canonical
THEN #GP(0); FI;
IF OperandSize = 32
THEN
Push(CS); (* Padded with 16 high-order bits *)
Push(EIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE
IF OperandSize = 16
THEN
Push(CS);
Push(IP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE (* OperandSize = 64 *)
Push(CS); (* Padded with 48 high-order bits *)
Push(RIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
RIP ← tempEIP;
FI;
FI;
END;
CALL-GATE:
IF call gate (DPL < CPL) or (RPL > DPL)
THEN #GP(call-gate selector); FI;
IF call gate not present
THEN #NP(call-gate selector); FI;
IF call-gate code-segment selector is NULL
THEN #GP(0); FI;
IF call-gate code-segment selector index is outside descriptor table limits
THEN #GP(call-gate code-segment selector); FI;
Read call-gate code-segment descriptor;
IF call-gate code-segment descriptor does not indicate a code segment
or call-gate code-segment descriptor DPL > CPL
THEN #GP(call-gate code-segment selector); FI;
IF IA32_EFER.LMA = 1 AND (call-gate code-segment descriptor is
not a 64-bit code segment or call-gate code-segment descriptor has both L-bit and D-bit set)
THEN #GP(call-gate code-segment selector); FI;
IF call-gate code segment not present
CALL—Call Procedure
Vol. 2A 3-129
INSTRUCTION SET REFERENCE, A-L
THEN #NP(call-gate code-segment selector); FI;
IF call-gate code segment is non-conforming and DPL < CPL
THEN go to MORE-PRIVILEGE;
ELSE go to SAME-PRIVILEGE;
FI;
END;
MORE-PRIVILEGE:
IF current TSS is 32-bit
THEN
TSSstackAddress ← (new code-segment DPL ∗ 8) + 4;
IF (TSSstackAddress + 5) > current TSS limit
THEN #TS(current TSS selector); FI;
NewSS ← 2 bytes loaded from (TSS base + TSSstackAddress + 4);
NewESP ← 4 bytes loaded from (TSS base + TSSstackAddress);
ELSE
IF current TSS is 16-bit
THEN
TSSstackAddress ← (new code-segment DPL ∗ 4) + 2
IF (TSSstackAddress + 3) > current TSS limit
THEN #TS(current TSS selector); FI;
NewSS ← 2 bytes loaded from (TSS base + TSSstackAddress + 2);
NewESP ← 2 bytes loaded from (TSS base + TSSstackAddress);
ELSE (* current TSS is 64-bit *)
TSSstackAddress ← (new code-segment DPL ∗ 8) + 4;
IF (TSSstackAddress + 7) > current TSS limit
THEN #TS(current TSS selector); FI;
NewSS ← new code-segment DPL; (* NULL selector with RPL = new CPL *)
NewRSP ← 8 bytes loaded from (current TSS base + TSSstackAddress);
FI;
FI;
IF IA32_EFER.LMA = 0 and NewSS is NULL
THEN #TS(NewSS); FI;
Read new code-segment descriptor and new stack-segment descriptor;
IF IA32_EFER.LMA = 0 and (NewSS RPL ≠ new code-segment DPL
or new stack-segment DPL ≠ new code-segment DPL or new stack segment is not a
writable data segment)
THEN #TS(NewSS); FI
IF IA32_EFER.LMA = 0 and new stack segment not present
THEN #SS(NewSS); FI;
IF CallGateSize = 32
THEN
IF new stack does not have room for parameters plus 16 bytes
THEN #SS(NewSS); FI;
IF CallGate(InstructionPointer) not within new code-segment limit
THEN #GP(0); FI;
SS ← newSS; (* Segment descriptor information also loaded *)
ESP ← newESP;
CS:EIP ← CallGate(CS:InstructionPointer);
(* Segment descriptor information also loaded *)
Push(oldSS:oldESP); (* From calling procedure *)
temp ← parameter count from call gate, masked to 5 bits;
Push(parameters from calling procedure’s stack, temp)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
3-130 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
ELSE
IF CallGateSize = 16
THEN
IF new stack does not have room for parameters plus 8 bytes
THEN #SS(NewSS); FI;
IF (CallGate(InstructionPointer) AND FFFFH) not in new code-segment limit
THEN #GP(0); FI;
SS ← newSS; (* Segment descriptor information also loaded *)
ESP ← newESP;
CS:IP ← CallGate(CS:InstructionPointer);
(* Segment descriptor information also loaded *)
Push(oldSS:oldESP); (* From calling procedure *)
temp ← parameter count from call gate, masked to 5 bits;
Push(parameters from calling procedure’s stack, temp)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
ELSE (* CallGateSize = 64 *)
IF pushing 32 bytes on the stack would use a non-canonical address
THEN #SS(NewSS); FI;
IF (CallGate(InstructionPointer) is non-canonical)
THEN #GP(0); FI;
SS ← NewSS; (* NewSS is NULL)
RSP ← NewESP;
CS:IP ← CallGate(CS:InstructionPointer);
(* Segment descriptor information also loaded *)
Push(oldSS:oldESP); (* From calling procedure *)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
FI;
FI;
CPL ← CodeSegment(DPL)
CS(RPL) ← CPL
END;
SAME-PRIVILEGE:
IF CallGateSize = 32
THEN
IF stack does not have room for 8 bytes
THEN #SS(0); FI;
IF CallGate(InstructionPointer) not within code segment limit
THEN #GP(0); FI;
CS:EIP ← CallGate(CS:EIP) (* Segment descriptor information also loaded *)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
ELSE
If CallGateSize = 16
THEN
IF stack does not have room for 4 bytes
THEN #SS(0); FI;
IF CallGate(InstructionPointer) not within code segment limit
THEN #GP(0); FI;
CS:IP ← CallGate(CS:instruction pointer);
(* Segment descriptor information also loaded *)
Push(oldCS:oldIP); (* Return address to calling procedure *)
ELSE (* CallGateSize = 64)
IF pushing 16 bytes on the stack touches non-canonical addresses
THEN #SS(0); FI;
CALL—Call Procedure
Vol. 2A 3-131
INSTRUCTION SET REFERENCE, A-L
IF RIP non-canonical
THEN #GP(0); FI;
CS:IP ← CallGate(CS:instruction pointer);
(* Segment descriptor information also loaded *)
Push(oldCS:oldIP); (* Return address to calling procedure *)
FI;
FI;
CS(RPL) ← CPL
END;
TASK-GATE:
IF task gate DPL < CPL or RPL
THEN #GP(task gate selector); FI;
IF task gate not present
THEN #NP(task gate selector); FI;
Read the TSS segment selector in the task-gate descriptor;
IF TSS segment selector local/global bit is set to local
or index not within GDT limits
THEN #GP(TSS selector); FI;
Access TSS descriptor in GDT;
IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)
THEN #GP(TSS selector); FI;
IF TSS not present
THEN #NP(TSS selector); FI;
SWITCH-TASKS (with nesting) to TSS;
IF EIP not within code segment limit
THEN #GP(0); FI;
END;
TASK-STATE-SEGMENT:
IF TSS DPL < CPL or RPL
or TSS descriptor indicates TSS not available
THEN #GP(TSS selector); FI;
IF TSS is not present
THEN #NP(TSS selector); FI;
SWITCH-TASKS (with nesting) to TSS;
IF EIP not within code segment limit
THEN #GP(0); FI;
END;
Flags Affected
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.
3-132 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the target offset in destination operand is beyond the new code segment limit.
If the segment selector in the destination operand is NULL.
If the code segment selector in the gate is NULL.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#GP(selector)
If a code segment or gate or TSS selector index is outside descriptor table limits.
If the segment descriptor pointed to by the segment selector in the destination operand is not
for a conforming-code segment, nonconforming-code segment, call gate, task gate, or task
state segment.
If the DPL for a nonconforming-code segment is not equal to the CPL or the RPL for the
segment’s segment selector is greater than the CPL.
If the DPL for a conforming-code segment is greater than the CPL.
If the DPL from a call-gate, task-gate, or TSS segment descriptor is less than the CPL or than
the RPL of the call-gate, task-gate, or TSS’s segment selector.
If the segment descriptor for a segment selector from a call gate does not indicate it is a code
segment.
If the segment selector from a call gate is beyond the descriptor table limits.
If the DPL for a code-segment obtained from a call gate is greater than the CPL.
If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is busy or not available.
#SS(0)
If pushing the return address, parameters, or stack segment pointer onto the stack exceeds
the bounds of the stack segment, when no stack switch occurs.
If a memory operand effective address is outside the SS segment limit.
#SS(selector)
If pushing the return address, parameters, or stack segment pointer onto the stack exceeds
the bounds of the stack segment, when a stack switch occurs.
If the SS register is being loaded as part of a stack switch and the segment pointed to is
marked not present.
If stack segment does not have room for the return address, parameters, or stack segment
pointer, when stack switch occurs.
#NP(selector)
If a code segment, data segment, stack segment, call gate, task gate, or TSS is not present.
#TS(selector)
If the new stack segment selector and ESP are beyond the end of the TSS.
If the new stack segment selector is NULL.
If the RPL of the new stack segment selector in the TSS is not equal to the DPL of the code
segment being accessed.
If DPL of the stack segment descriptor for the new stack segment is not equal to the DPL of the
code segment descriptor.
If the new stack segment is not a writable data segment.
If segment-selector index for stack segment is outside descriptor table limits.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the target offset is beyond the code segment limit.
#UD
CALL—Call Procedure
If the LOCK prefix is used.
Vol. 2A 3-133
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#PF(fault-code)
If a page fault occurs.
If the target offset is beyond the code segment limit.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
#GP(selector)
If a memory address accessed by the selector is in non-canonical space.
#GP(0)
If the target offset in the destination operand is non-canonical.
64-Bit Mode Exceptions
#GP(0)
If a memory address is non-canonical.
If target offset in destination operand is non-canonical.
If the segment selector in the destination operand is NULL.
If the code segment selector in the 64-bit gate is NULL.
#GP(selector)
If code segment or 64-bit call gate is outside descriptor table limits.
If code segment or 64-bit call gate overlaps non-canonical space.
If the segment descriptor pointed to by the segment selector in the destination operand is not
for a conforming-code segment, nonconforming-code segment, or 64-bit call gate.
If the segment descriptor pointed to by the segment selector in the destination operand is a
code segment and has both the D-bit and the L- bit set.
If the DPL for a nonconforming-code segment is not equal to the CPL, or the RPL for the
segment’s segment selector is greater than the CPL.
If the DPL for a conforming-code segment is greater than the CPL.
If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.
If the upper type field of a 64-bit call gate is not 0x0.
If the segment selector from a 64-bit call gate is beyond the descriptor table limits.
If the DPL for a code-segment obtained from a 64-bit call gate is greater than the CPL.
If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the Lbit set and the D-bit clear.
If the segment descriptor for a segment selector from the 64-bit call gate does not indicate it
is a code segment.
#SS(0)
If pushing the return offset or CS selector onto the stack exceeds the bounds of the stack
segment when no stack switch occurs.
If a memory operand effective address is outside the SS segment limit.
If the stack address is in a non-canonical form.
#SS(selector)
If pushing the old values of SS selector, stack pointer, EFLAGS, CS selector, offset, or error
code onto the stack violates the canonical boundary when a stack switch occurs.
#NP(selector)
If a code segment or 64-bit call gate is not present.
#TS(selector)
If the load of the new RSP exceeds the limit of the TSS.
#UD
(64-bit mode only) If a far call is direct to an absolute address in memory.
If the LOCK prefix is used.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-134 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to
Quadword
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
98
CBW
NP
Valid
Valid
AX ← sign-extend of AL.
98
CWDE
NP
Valid
Valid
EAX ← sign-extend of AX.
REX.W + 98
CDQE
NP
Valid
N.E.
RAX ← sign-extend of EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Double the size of the source operand by means of sign extension. The CBW (convert byte to word) instruction
copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to doubleword) instruction copies the sign (bit 15) of the word in the AX register into the high 16 bits of the EAX register.
CBW and CWDE reference the same opcode. The CBW instruction is intended for use when the operand-size attribute is 16; CWDE is intended for use when the operand-size attribute is 32. Some assemblers may force the
operand size. Others may treat these two mnemonics as synonyms (CBW/CWDE) and use the setting of the
operand-size attribute to determine the size of values to be converted.
In 64-bit mode, the default operation size is the size of the destination register. Use of the REX.W prefix promotes
this instruction (CDQE when promoted) to operate on 64-bit operands. In which case, CDQE copies the sign (bit
31) of the doubleword in the EAX register into the high 32 bits of RAX.
Operation
IF OperandSize = 16 (* Instruction = CBW *)
THEN
AX ← SignExtend(AL);
ELSE IF (OperandSize = 32, Instruction = CWDE)
EAX ← SignExtend(AX); FI;
ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*)
RAX ← SignExtend(EAX);
FI;
Flags Affected
None.
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword
Vol. 2A 3-135
INSTRUCTION SET REFERENCE, A-L
CLAC—Clear AC Flag in EFLAGS Register
Opcode/
Instruction
Op /
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 01 CA
NP
V/V
SMAP
Clear the AC flag in the EFLAGS register.
CLAC
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the AC flag bit in EFLAGS register. This disables any alignment checking of user-mode data accesses. If the
SMAP bit is set in the CR4 register, this disallows explicit supervisor-mode data accesses to user-mode pages.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute CLAC when
CPL > 0 cause #UD.
Operation
EFLAGS.AC ← 0;
Flags Affected
AC cleared. Other flags are unaffected.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
Virtual-8086 Mode Exceptions
#UD
The CLAC instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
3-136 Vol. 2A
CLAC—Clear AC Flag in EFLAGS Register
INSTRUCTION SET REFERENCE, A-L
CLC—Clear Carry Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
F8
CLC
NP
Valid
Valid
Clear CF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the CF flag in the EFLAGS register. Operation is the same in all modes.
Operation
CF ← 0;
Flags Affected
The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
CLC—Clear Carry Flag
If the LOCK prefix is used.
Vol. 2A 3-137
INSTRUCTION SET REFERENCE, A-L
CLD—Clear Direction Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
FC
CLD
NP
Valid
Valid
Clear DF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI). Operation is the same in all modes.
Operation
DF ← 0;
Flags Affected
The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
3-138 Vol. 2A
If the LOCK prefix is used.
CLD—Clear Direction Flag
INSTRUCTION SET REFERENCE, A-L
CLFLUSH—Flush Cache Line
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F AE /7
CLFLUSH m8
M
Valid
Valid
Flushes cache line containing m8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the
linear address specified with the memory operand. If that cache line contains modified data at any level of the
cache hierarchy, that data is written back to memory. The source operand is a byte memory location.
The availability of CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH
(CPUID.01H:EDX[bit 19]). The aligned cache line size affected is also indicated with the CPUID instruction (bits 8
through 15 of the EBX register when the initial value in the EAX register is 1).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It
should be noted that processors are free to speculatively fetch and cache data from system memory regions
assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh
instructions can be used to provide the processor with hints for this speculative behavior. Because this speculative
fetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with
respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be speculatively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references
the cache line).
Executions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes, locked
read-modify-write instructions, fence instructions, and executions of CLFLUSHOPT to the same cache line.1 They
are not ordered with respect to executions of CLFLUSHOPT to different cache lines.
The CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load (and in addition, a CLFLUSH instruction is allowed to flush a linear address in an executeonly segment). Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the page tables.
In some implementations, the CLFLUSH instruction may always cause transactional abort with Transactional
Synchronization Extensions (TSX). The CLFLUSH instruction is not expected to be commonly used inside typical
transactional regions. However, programmers must not rely on CLFLUSH instruction to force a transactional abort,
since whether they cause transactional abort is implementation dependent.
The CLFLUSH instruction was introduced with the SSE2 extensions; however, because it has its own CPUID feature
flag, it can be implemented in IA-32 processors that do not include the SSE2 extensions. Also, detecting the presence of the SSE2 extensions with the CPUID instruction does not guarantee that the CLFLUSH instruction is implemented in the processor.
CLFLUSH operation is the same in non-64-bit modes and 64-bit mode.
Operation
Flush_Cache_Line(SRC);
Intel C/C++ Compiler Intrinsic Equivalents
CLFLUSH:
void _mm_clflush(void const *p)
1. Earlier versions of this manual specified that executions of the CLFLUSH instruction were ordered only by the MFENCE instruction.
All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above.
CLFLUSH—Flush Cache Line
Vol. 2A 3-139
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#UD
If CPUID.01H:EDX.CLFSH[bit 19] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Real-Address Mode Exceptions
#GP
#UD
If any part of the operand lies outside the effective address space from 0 to FFFFH.
If CPUID.01H:EDX.CLFSH[bit 19] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#UD
If CPUID.01H:EDX.CLFSH[bit 19] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
3-140 Vol. 2A
CLFLUSH—Flush Cache Line
INSTRUCTION SET REFERENCE, A-L
CLFLUSHOPT—Flush Cache Line Optimized
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
66 0F AE /7
CLFLUSHOPT m8
M
Valid
Valid
Flushes cache line containing m8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the
linear address specified with the memory operand. If that cache line contains modified data at any level of the
cache hierarchy, that data is written back to memory. The source operand is a byte memory location.
The availability of CLFLUSHOPT is indicated by the presence of the CPUID feature flag CLFLUSHOPT
(CPUID.(EAX=7,ECX=0):EBX[bit 23]). The aligned cache line size affected is also indicated with the CPUID instruction (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It
should be noted that processors are free to speculatively fetch and cache data from system memory regions
assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh
instructions can be used to provide the processor with hints for this speculative behavior. Because this speculative
fetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with
respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be speculatively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references
the cache line).
Executions of the CLFLUSHOPT instruction are ordered with respect to fence instructions and to locked readmodify-write instructions; they are also ordered with respect to the following accesses to the cache line being
invalidated: writes, executions of CLFLUSH, and executions of CLFLUSHOPT. They are not ordered with respect to
writes, executions of CLFLUSH, or executions of CLFLUSHOPT that access other cache lines; to enforce ordering
with such an operation, software can insert an SFENCE instruction between CFLUSHOPT and that operation.
The CLFLUSHOPT instruction can be used at all privilege levels and is subject to all permission checking and faults
associated with a byte load (and in addition, a CLFLUSHOPT instruction is allowed to flush a linear address in an
execute-only segment). Like a load, the CLFLUSHOPT instruction sets the A bit but not the D bit in the page tables.
In some implementations, the CLFLUSHOPT instruction may always cause transactional abort with Transactional
Synchronization Extensions (TSX). The CLFLUSHOPT instruction is not expected to be commonly used inside
typical transactional regions. However, programmers must not rely on CLFLUSHOPT instruction to force a transactional abort, since whether they cause transactional abort is implementation dependent.
CLFLUSHOPT operation is the same in non-64-bit modes and 64-bit mode.
Operation
Flush_Cache_Line_Optimized(SRC);
Intel C/C++ Compiler Intrinsic Equivalents
CLFLUSHOPT:void _mm_clflushopt(void const *p)
CLFLUSHOPT—Flush Cache Line Optimized
Vol. 2A 3-141
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#UD
If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Real-Address Mode Exceptions
#GP
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#UD
If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#UD
If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
3-142 Vol. 2A
CLFLUSHOPT—Flush Cache Line Optimized
INSTRUCTION SET REFERENCE, A-L
CLI — Clear Interrupt Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
FA
CLI
NP
Valid
Valid
Clear interrupt flag; interrupts disabled when
interrupt flag cleared.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
If protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags
are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts. The IF flag and the
CLI and STI instruction have no affect on the generation of exceptions and NMI interrupts.
When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the
EFLAGS register, leaving IF unaffected. Table 3-7 indicates the action of the CLI instruction depending on the
processor operating mode and the CPL/IOPL of the running program or procedure.
Operation is the same in all modes.
Table 3-7. Decision Table for CLI Results
PE
VM
IOPL
CPL
PVI
VIP
VME
CLI Result
0
X
X
X
X
X
X
IF = 0
1
0
≥ CPL
X
X
X
X
IF = 0
1
0
< CPL
3
1
X
X
VIF = 0
1
0
< CPL
<3
X
X
X
GP Fault
1
0
< CPL
X
0
X
X
GP Fault
1
1
3
X
X
X
X
IF = 0
1
1
<3
X
X
X
1
VIF = 0
1
1
<3
X
X
X
0
GP Fault
NOTES:
* X = This setting has no impact.
Operation
IF PE = 0
THEN
IF ← 0; (* Reset Interrupt Flag *)
ELSE
IF VM = 0;
THEN
IF IOPL ≥ CPL
THEN
IF ← 0; (* Reset Interrupt Flag *)
ELSE
IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1))
THEN
VIF ← 0; (* Reset Virtual Interrupt Flag *)
ELSE
#GP(0);
CLI — Clear Interrupt Flag
Vol. 2A 3-143
INSTRUCTION SET REFERENCE, A-L
FI;
FI;
ELSE (* VM = 1 *)
IF IOPL = 3
THEN
IF ← 0; (* Reset Interrupt Flag *)
ELSE
IF (IOPL < 3) AND (VME = 1)
THEN
VIF ← 0; (* Reset Virtual Interrupt Flag *)
ELSE
#GP(0);
FI;
FI;
FI;
FI;
Flags Affected
If protected-mode virtual interrupts are not enabled, IF is set to 0 if the CPL is equal to or less than the IOPL; otherwise, it is not affected. Other flags are unaffected.
When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the
EFLAGS register, leaving IF unaffected. Other flags are unaffected.
Protected Mode Exceptions
#GP(0)
If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD
If the LOCK prefix is used.
3-144 Vol. 2A
CLI — Clear Interrupt Flag
INSTRUCTION SET REFERENCE, A-L
CLTS—Clear Task-Switched Flag in CR0
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F 06
CLTS
NP
Valid
Valid
Clears TS flag in CR0.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system
procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in realaddress mode to allow initialization for protected mode.
The processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU
context in multitasking applications. See the description of the TS flag in the section titled “Control Registers” in
Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information
about this flag.
CLTS operation is the same in non-64-bit modes and 64-bit mode.
See Chapter 25, “VMX Non-Root Operation,” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C, for more information about the behavior of this instruction in VMX non-root operation.
Operation
CR0.TS[bit 3] ← 0;
Flags Affected
The TS flag in CR0 register is cleared.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
CLTS is not recognized in virtual-8086 mode.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the CPL is greater than 0.
#UD
If the LOCK prefix is used.
CLTS—Clear Task-Switched Flag in CR0
Vol. 2A 3-145
INSTRUCTION SET REFERENCE, A-L
CLWB—Cache Line Write Back
Opcode/
Instruction
Op/
En
66 0F AE /6
CLWB m8
M
64/32 bit
Mode
Support
V/V
CPUID
Feature Flag
Description
CLWB
Writes back modified cache line containing m8, and may
retain the line in cache hierarchy in non-modified state.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Writes back to memory the cache line (if modified) that contains the linear address specified with the memory
operand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the
cache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization
(treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may
choose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from
the cache hierarchy. The source operand is a byte memory location.
The availability of CLWB instruction is indicated by the presence of the CPUID feature flag CLWB (bit 24 of the EBX
register, see “CPUID — CPU Identification” in this chapter). The aligned cache line size affected is also indicated
with the CPUID instruction (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It
should be noted that processors are free to speculatively fetch and cache data from system memory regions that
are assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types).
PREFETCHh instructions can be used to provide the processor with hints for this speculative behavior. Because this
speculative fetching can occur at any time and is not tied to instruction execution, the CLWB instruction is not
ordered with respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can
be speculatively loaded into a cache line just before, during, or after the execution of a CLWB instruction that references the cache line).
CLWB instruction is ordered only by store-fencing operations. For example, software can use an SFENCE, MFENCE,
XCHG, or LOCK-prefixed instructions to ensure that previous stores are included in the write-back. CLWB instruction need not be ordered by another CLWB or CLFLUSHOPT instruction. CLWB is implicitly ordered with older stores
executed by the logical processor to the same address.
For usages that require only writing back modified data from cache lines to memory (do not require the line to be
invalidated), and expect to subsequently access the data, software is recommended to use CLWB (with appropriate
fencing) instead of CLFLUSH or CLFLUSHOPT for improved performance.
The CLWB instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load. Like a load, the CLWB instruction sets the accessed flag but not the dirty flag in the page
tables.
In some implementations, the CLWB instruction may always cause transactional abort with Transactional Synchronization Extensions (TSX). CLWB instruction is not expected to be commonly used inside typical transactional
regions. However, programmers must not rely on CLWB instruction to force a transactional abort, since whether
they cause transactional abort is implementation dependent.
Operation
Cache_Line_Write_Back(m8);
Flags Affected
None.
1. ModRM.MOD != 011B
3-146 Vol. 2A
CLWB—Cache Line Write Back
INSTRUCTION SET REFERENCE, A-L
C/C++ Compiler Intrinsic Equivalent
CLWB void _mm_clwb(void const *p);
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.
#GP
If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
CLWB—Cache Line Write Back
Vol. 2A 3-147
INSTRUCTION SET REFERENCE, A-L
CMC—Complement Carry Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
F5
CMC
NP
Valid
Valid
Complement CF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Complements the CF flag in the EFLAGS register. CMC operation is the same in non-64-bit modes and 64-bit mode.
Operation
EFLAGS.CF[bit 0]← NOT EFLAGS.CF[bit 0];
Flags Affected
The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
3-148 Vol. 2A
If the LOCK prefix is used.
CMC—Complement Carry Flag
INSTRUCTION SET REFERENCE, A-L
CMOVcc—Conditional Move
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 47 /r
CMOVA r16, r/m16
RM
Valid
Valid
Move if above (CF=0 and ZF=0).
0F 47 /r
CMOVA r32, r/m32
RM
Valid
Valid
Move if above (CF=0 and ZF=0).
REX.W + 0F 47 /r
CMOVA r64, r/m64
RM
Valid
N.E.
Move if above (CF=0 and ZF=0).
0F 43 /r
CMOVAE r16, r/m16
RM
Valid
Valid
Move if above or equal (CF=0).
0F 43 /r
CMOVAE r32, r/m32
RM
Valid
Valid
Move if above or equal (CF=0).
REX.W + 0F 43 /r
CMOVAE r64, r/m64
RM
Valid
N.E.
Move if above or equal (CF=0).
0F 42 /r
CMOVB r16, r/m16
RM
Valid
Valid
Move if below (CF=1).
0F 42 /r
CMOVB r32, r/m32
RM
Valid
Valid
Move if below (CF=1).
REX.W + 0F 42 /r
CMOVB r64, r/m64
RM
Valid
N.E.
Move if below (CF=1).
0F 46 /r
CMOVBE r16, r/m16
RM
Valid
Valid
Move if below or equal (CF=1 or ZF=1).
0F 46 /r
CMOVBE r32, r/m32
RM
Valid
Valid
Move if below or equal (CF=1 or ZF=1).
REX.W + 0F 46 /r
CMOVBE r64, r/m64
RM
Valid
N.E.
Move if below or equal (CF=1 or ZF=1).
0F 42 /r
CMOVC r16, r/m16
RM
Valid
Valid
Move if carry (CF=1).
0F 42 /r
CMOVC r32, r/m32
RM
Valid
Valid
Move if carry (CF=1).
REX.W + 0F 42 /r
CMOVC r64, r/m64
RM
Valid
N.E.
Move if carry (CF=1).
0F 44 /r
CMOVE r16, r/m16
RM
Valid
Valid
Move if equal (ZF=1).
0F 44 /r
CMOVE r32, r/m32
RM
Valid
Valid
Move if equal (ZF=1).
REX.W + 0F 44 /r
CMOVE r64, r/m64
RM
Valid
N.E.
Move if equal (ZF=1).
0F 4F /r
CMOVG r16, r/m16
RM
Valid
Valid
Move if greater (ZF=0 and SF=OF).
0F 4F /r
CMOVG r32, r/m32
RM
Valid
Valid
Move if greater (ZF=0 and SF=OF).
REX.W + 0F 4F /r
CMOVG r64, r/m64
RM
V/N.E.
NA
Move if greater (ZF=0 and SF=OF).
0F 4D /r
CMOVGE r16, r/m16
RM
Valid
Valid
Move if greater or equal (SF=OF).
0F 4D /r
CMOVGE r32, r/m32
RM
Valid
Valid
Move if greater or equal (SF=OF).
REX.W + 0F 4D /r
CMOVGE r64, r/m64
RM
Valid
N.E.
Move if greater or equal (SF=OF).
0F 4C /r
CMOVL r16, r/m16
RM
Valid
Valid
Move if less (SF≠ OF).
0F 4C /r
CMOVL r32, r/m32
RM
Valid
Valid
Move if less (SF≠ OF).
REX.W + 0F 4C /r
CMOVL r64, r/m64
RM
Valid
N.E.
Move if less (SF≠ OF).
0F 4E /r
CMOVLE r16, r/m16
RM
Valid
Valid
Move if less or equal (ZF=1 or SF≠ OF).
0F 4E /r
CMOVLE r32, r/m32
RM
Valid
Valid
Move if less or equal (ZF=1 or SF≠ OF).
REX.W + 0F 4E /r
CMOVLE r64, r/m64
RM
Valid
N.E.
Move if less or equal (ZF=1 or SF≠ OF).
0F 46 /r
CMOVNA r16, r/m16
RM
Valid
Valid
Move if not above (CF=1 or ZF=1).
0F 46 /r
CMOVNA r32, r/m32
RM
Valid
Valid
Move if not above (CF=1 or ZF=1).
REX.W + 0F 46 /r
CMOVNA r64, r/m64
RM
Valid
N.E.
Move if not above (CF=1 or ZF=1).
0F 42 /r
CMOVNAE r16, r/m16
RM
Valid
Valid
Move if not above or equal (CF=1).
0F 42 /r
CMOVNAE r32, r/m32
RM
Valid
Valid
Move if not above or equal (CF=1).
REX.W + 0F 42 /r
CMOVNAE r64, r/m64
RM
Valid
N.E.
Move if not above or equal (CF=1).
0F 43 /r
CMOVNB r16, r/m16
RM
Valid
Valid
Move if not below (CF=0).
0F 43 /r
CMOVNB r32, r/m32
RM
Valid
Valid
Move if not below (CF=0).
REX.W + 0F 43 /r
CMOVNB r64, r/m64
RM
Valid
N.E.
Move if not below (CF=0).
0F 47 /r
CMOVNBE r16, r/m16
RM
Valid
Valid
Move if not below or equal (CF=0 and ZF=0).
CMOVcc—Conditional Move
Vol. 2A 3-149
INSTRUCTION SET REFERENCE, A-L
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 47 /r
CMOVNBE r32, r/m32
RM
Valid
Valid
Move if not below or equal (CF=0 and ZF=0).
REX.W + 0F 47 /r
CMOVNBE r64, r/m64
RM
Valid
N.E.
Move if not below or equal (CF=0 and ZF=0).
0F 43 /r
CMOVNC r16, r/m16
RM
Valid
Valid
Move if not carry (CF=0).
0F 43 /r
CMOVNC r32, r/m32
RM
Valid
Valid
Move if not carry (CF=0).
REX.W + 0F 43 /r
CMOVNC r64, r/m64
RM
Valid
N.E.
Move if not carry (CF=0).
0F 45 /r
CMOVNE r16, r/m16
RM
Valid
Valid
Move if not equal (ZF=0).
0F 45 /r
CMOVNE r32, r/m32
RM
Valid
Valid
Move if not equal (ZF=0).
REX.W + 0F 45 /r
CMOVNE r64, r/m64
RM
Valid
N.E.
Move if not equal (ZF=0).
0F 4E /r
CMOVNG r16, r/m16
RM
Valid
Valid
Move if not greater (ZF=1 or SF≠ OF).
0F 4E /r
CMOVNG r32, r/m32
RM
Valid
Valid
Move if not greater (ZF=1 or SF≠ OF).
REX.W + 0F 4E /r
CMOVNG r64, r/m64
RM
Valid
N.E.
Move if not greater (ZF=1 or SF≠ OF).
0F 4C /r
CMOVNGE r16, r/m16
RM
Valid
Valid
Move if not greater or equal (SF≠ OF).
0F 4C /r
CMOVNGE r32, r/m32
RM
Valid
Valid
Move if not greater or equal (SF≠ OF).
REX.W + 0F 4C /r
CMOVNGE r64, r/m64
RM
Valid
N.E.
Move if not greater or equal (SF≠ OF).
0F 4D /r
CMOVNL r16, r/m16
RM
Valid
Valid
Move if not less (SF=OF).
0F 4D /r
CMOVNL r32, r/m32
RM
Valid
Valid
Move if not less (SF=OF).
REX.W + 0F 4D /r
CMOVNL r64, r/m64
RM
Valid
N.E.
Move if not less (SF=OF).
0F 4F /r
CMOVNLE r16, r/m16
RM
Valid
Valid
Move if not less or equal (ZF=0 and SF=OF).
0F 4F /r
CMOVNLE r32, r/m32
RM
Valid
Valid
Move if not less or equal (ZF=0 and SF=OF).
REX.W + 0F 4F /r
CMOVNLE r64, r/m64
RM
Valid
N.E.
Move if not less or equal (ZF=0 and SF=OF).
0F 41 /r
CMOVNO r16, r/m16
RM
Valid
Valid
Move if not overflow (OF=0).
0F 41 /r
CMOVNO r32, r/m32
RM
Valid
Valid
Move if not overflow (OF=0).
REX.W + 0F 41 /r
CMOVNO r64, r/m64
RM
Valid
N.E.
Move if not overflow (OF=0).
0F 4B /r
CMOVNP r16, r/m16
RM
Valid
Valid
Move if not parity (PF=0).
0F 4B /r
CMOVNP r32, r/m32
RM
Valid
Valid
Move if not parity (PF=0).
REX.W + 0F 4B /r
CMOVNP r64, r/m64
RM
Valid
N.E.
Move if not parity (PF=0).
0F 49 /r
CMOVNS r16, r/m16
RM
Valid
Valid
Move if not sign (SF=0).
0F 49 /r
CMOVNS r32, r/m32
RM
Valid
Valid
Move if not sign (SF=0).
REX.W + 0F 49 /r
CMOVNS r64, r/m64
RM
Valid
N.E.
Move if not sign (SF=0).
0F 45 /r
CMOVNZ r16, r/m16
RM
Valid
Valid
Move if not zero (ZF=0).
0F 45 /r
CMOVNZ r32, r/m32
RM
Valid
Valid
Move if not zero (ZF=0).
REX.W + 0F 45 /r
CMOVNZ r64, r/m64
RM
Valid
N.E.
Move if not zero (ZF=0).
0F 40 /r
CMOVO r16, r/m16
RM
Valid
Valid
Move if overflow (OF=1).
0F 40 /r
CMOVO r32, r/m32
RM
Valid
Valid
Move if overflow (OF=1).
REX.W + 0F 40 /r
CMOVO r64, r/m64
RM
Valid
N.E.
Move if overflow (OF=1).
0F 4A /r
CMOVP r16, r/m16
RM
Valid
Valid
Move if parity (PF=1).
0F 4A /r
CMOVP r32, r/m32
RM
Valid
Valid
Move if parity (PF=1).
REX.W + 0F 4A /r
CMOVP r64, r/m64
RM
Valid
N.E.
Move if parity (PF=1).
0F 4A /r
CMOVPE r16, r/m16
RM
Valid
Valid
Move if parity even (PF=1).
0F 4A /r
CMOVPE r32, r/m32
RM
Valid
Valid
Move if parity even (PF=1).
REX.W + 0F 4A /r
CMOVPE r64, r/m64
RM
Valid
N.E.
Move if parity even (PF=1).
3-150 Vol. 2A
CMOVcc—Conditional Move
INSTRUCTION SET REFERENCE, A-L
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 4B /r
CMOVPO r16, r/m16
RM
Valid
Valid
Move if parity odd (PF=0).
0F 4B /r
CMOVPO r32, r/m32
RM
Valid
Valid
Move if parity odd (PF=0).
REX.W + 0F 4B /r
CMOVPO r64, r/m64
RM
Valid
N.E.
Move if parity odd (PF=0).
0F 48 /r
CMOVS r16, r/m16
RM
Valid
Valid
Move if sign (SF=1).
0F 48 /r
CMOVS r32, r/m32
RM
Valid
Valid
Move if sign (SF=1).
REX.W + 0F 48 /r
CMOVS r64, r/m64
RM
Valid
N.E.
Move if sign (SF=1).
0F 44 /r
CMOVZ r16, r/m16
RM
Valid
Valid
Move if zero (ZF=1).
0F 44 /r
CMOVZ r32, r/m32
RM
Valid
Valid
Move if zero (ZF=1).
REX.W + 0F 44 /r
CMOVZ r64, r/m64
RM
Valid
N.E.
Move if zero (ZF=1).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
The CMOVcc instructions check the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF,
and ZF) and perform a move operation if the flags are in a specified state (or condition). A condition code (cc) is
associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, a move
is not performed and execution continues with the instruction following the CMOVcc instruction.
These instructions can move 16-bit, 32-bit or 64-bit values from memory to a general-purpose register or from one
general-purpose register to another. Conditional moves of 8-bit register operands are not supported.
The condition for each CMOVcc mnemonic is given in the description column of the above table. The terms “less”
and “greater” are used for comparisons of signed integers and the terms “above” and “below” are used for
unsigned integers.
Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are
defined for some opcodes. For example, the CMOVA (conditional move if above) instruction and the CMOVNBE
(conditional move if not below or equal) instruction are alternate mnemonics for the opcode 0F 47H.
The CMOVcc instructions were introduced in P6 family processors; however, these instructions may not be
supported by all IA-32 processors. Software can determine if the CMOVcc instructions are supported by checking
the processor’s feature information with the CPUID instruction (see “CPUID—CPU Identification” in this chapter).
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
temp ← SRC
IF condition TRUE
THEN
DEST ← temp;
FI;
ELSE
IF (OperandSize = 32 and IA-32e mode active)
THEN
DEST[63:32] ← 0;
FI;
FI;
CMOVcc—Conditional Move
Vol. 2A 3-151
INSTRUCTION SET REFERENCE, A-L
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-152 Vol. 2A
CMOVcc—Conditional Move
INSTRUCTION SET REFERENCE, A-L
CMP—Compare Two Operands
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
3C ib
CMP AL, imm8
I
Valid
Valid
Compare imm8 with AL.
3D iw
CMP AX, imm16
I
Valid
Valid
Compare imm16 with AX.
3D id
CMP EAX, imm32
I
Valid
Valid
Compare imm32 with EAX.
REX.W + 3D id
CMP RAX, imm32
I
Valid
N.E.
Compare imm32 sign-extended to 64-bits
with RAX.
80 /7 ib
CMP r/m8, imm8
MI
Valid
Valid
Compare imm8 with r/m8.
REX + 80 /7 ib
CMP r/m8*, imm8
MI
Valid
N.E.
Compare imm8 with r/m8.
81 /7 iw
CMP r/m16, imm16
MI
Valid
Valid
Compare imm16 with r/m16.
81 /7 id
CMP r/m32, imm32
MI
Valid
Valid
Compare imm32 with r/m32.
REX.W + 81 /7 id
CMP r/m64, imm32
MI
Valid
N.E.
Compare imm32 sign-extended to 64-bits
with r/m64.
83 /7 ib
CMP r/m16, imm8
MI
Valid
Valid
Compare imm8 with r/m16.
83 /7 ib
CMP r/m32, imm8
MI
Valid
Valid
Compare imm8 with r/m32.
REX.W + 83 /7 ib
CMP r/m64, imm8
MI
Valid
N.E.
Compare imm8 with r/m64.
38 /r
CMP r/m8, r8
MR
Valid
Valid
Compare r8 with r/m8.
MR
Valid
N.E.
Compare r8 with r/m8.
*
*
REX + 38 /r
CMP r/m8 , r8
39 /r
CMP r/m16, r16
MR
Valid
Valid
Compare r16 with r/m16.
39 /r
CMP r/m32, r32
MR
Valid
Valid
Compare r32 with r/m32.
REX.W + 39 /r
CMP r/m64,r64
MR
Valid
N.E.
Compare r64 with r/m64.
3A /r
CMP r8, r/m8
RM
Valid
Valid
Compare r/m8 with r8.
*
*
REX + 3A /r
CMP r8 , r/m8
RM
Valid
N.E.
Compare r/m8 with r8.
3B /r
CMP r16, r/m16
RM
Valid
Valid
Compare r/m16 with r16.
3B /r
CMP r32, r/m32
RM
Valid
Valid
Compare r/m32 with r32.
REX.W + 3B /r
CMP r64, r/m64
RM
Valid
N.E.
Compare r/m64 with r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r)
imm8
NA
NA
I
AL/AX/EAX/RAX (r)
imm8
NA
NA
Description
Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register
according to the results. The comparison is performed by subtracting the second operand from the first operand
and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as
an operand, it is sign-extended to the length of the first operand.
The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction.
Appendix B, “EFLAGS Condition Codes,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, shows the relationship of the status flags and the condition codes.
CMP—Compare Two Operands
Vol. 2A 3-153
INSTRUCTION SET REFERENCE, A-L
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
temp ← SRC1 − SignExtend(SRC2);
ModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*)
Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-154 Vol. 2A
CMP—Compare Two Operands
INSTRUCTION SET REFERENCE, A-L
CMPPD—Compare Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F C2 /r ib
CMPPD xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F.WIG C2 /r ib
VCMPPD xmm1, xmm2, xmm3/m128,
imm8
VEX.NDS.256.66.0F.WIG C2 /r ib
VCMPPD ymm1, ymm2, ymm3/m256,
imm8
EVEX.NDS.128.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, xmm2,
xmm3/m128/m64bcst, imm8
RVMI
V/V
AVX
RVMI
V/V
AVX
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, zmm2,
zmm3/m512/m64bcst{sae}, imm8
FV
V/V
AVX512F
Description
Compare packed double-precision floating-point values
in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a
comparison predicate.
Compare packed double-precision floating-point values
in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a
comparison predicate.
Compare packed double-precision floating-point values
in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a
comparison predicate.
Compare packed double-precision floating-point values
in xmm3/m128/m64bcst and xmm2 using bits 4:0 of
imm8 as a comparison predicate with writemask k2
and leave the result in mask register k1.
Compare packed double-precision floating-point values
in ymm3/m256/m64bcst and ymm2 using bits 4:0 of
imm8 as a comparison predicate with writemask k2
and leave the result in mask register k1.
Compare packed double-precision floating-point values
in zmm3/m512/m64bcst and zmm2 using bits 4:0 of
imm8 as a comparison predicate with writemask k2
and leave the result in mask register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Performs a SIMD compare of the packed double-precision floating-point values in the second source operand and
the first source operand and returns the results of the comparison to the destination operand. The comparison
predicate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in
the two source operands.
EVEX encoded versions: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand (first operand) is an opmask register.
Comparison results are written to the destination operand under the writemask k2. Each comparison result is a
single mask bit of 1 (comparison true) or 0 (comparison false).
VEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source
operand (third operand) can be a YMM register or a 256-bit memory location. The destination operand (first
operand) is a YMM register. Four comparisons are performed with results written to the destination operand. The
result of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).
128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The
second source operand (second operand) can be an XMM register or 128-bit memory location. Bits (MAX_VL1:128) of the corresponding ZMM destination register remain unchanged. Two comparisons are performed with
results written to bits 127:0 of the destination operand. The result of each comparison is a quadword mask of all
1s (comparison true) or all 0s (comparison false).
CMPPD—Compare Packed Double-Precision Floating-Point Values
Vol. 2A 3-155
INSTRUCTION SET REFERENCE, A-L
VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed. Two comparisons are performed with results written to bits 127:0 of the destination operand.
The comparison predicate operand is an 8-bit immediate:
•
For instructions encoded using the VEX or EVEX prefix, bits 4:0 define the type of comparison to be performed
(see Table 3-1). Bits 5 through 7 of the immediate are reserved.
•
For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see the
first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.
Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions
Predicate
imm8
Value
Description
EQ_OQ (EQ)
0H
Equal (ordered, non-signaling)
False
False
True
False
No
LT_OS (LT)
1H
Less-than (ordered, signaling)
False
True
False
False
Yes
LE_OS (LE)
2H
Less-than-or-equal (ordered, signaling)
False
True
True
False
Yes
Unordered (non-signaling)
False
False
False
True
No
UNORD_Q (UNORD) 3H
Result: A Is 1st Operand, B Is 2nd Operand Signals
#IA on
AB
NEQ_UQ (NEQ)
4H
Not-equal (unordered, non-signaling)
True
True
False
True
No
NLT_US (NLT)
5H
Not-less-than (unordered, signaling)
True
False
True
True
Yes
NLE_US (NLE)
6H
Not-less-than-or-equal (unordered, signaling)
True
False
False
True
Yes
ORD_Q (ORD)
7H
Ordered (non-signaling)
True
True
True
False
No
EQ_UQ
8H
Equal (unordered, non-signaling)
False
False
True
True
No
NGE_US (NGE)
9H
Not-greater-than-or-equal (unordered,
signaling)
False
True
False
True
Yes
NGT_US (NGT)
AH
Not-greater-than (unordered, signaling)
False
True
True
True
Yes
FALSE_OQ(FALSE)
BH
False (ordered, non-signaling)
False
False
False
False
No
NEQ_OQ
CH
Not-equal (ordered, non-signaling)
True
True
False
False
No
GE_OS (GE)
DH
Greater-than-or-equal (ordered, signaling)
True
False
True
False
Yes
GT_OS (GT)
EH
Greater-than (ordered, signaling)
True
False
False
False
Yes
TRUE_UQ(TRUE)
FH
True (unordered, non-signaling)
True
True
True
True
No
EQ_OS
10H
Equal (ordered, signaling)
False
False
True
False
Yes
LT_OQ
11H
Less-than (ordered, nonsignaling)
False
True
False
False
No
LE_OQ
12H
Less-than-or-equal (ordered, nonsignaling)
False
True
True
False
No
UNORD_S
13H
Unordered (signaling)
False
False
False
True
Yes
NEQ_US
14H
Not-equal (unordered, signaling)
True
True
False
True
Yes
NLT_UQ
15H
Not-less-than (unordered, nonsignaling)
True
False
True
True
No
NLE_UQ
16H
Not-less-than-or-equal (unordered, nonsignaling)
True
False
False
True
No
ORD_S
17H
Ordered (signaling)
True
True
True
False
Yes
EQ_US
18H
Equal (unordered, signaling)
False
False
True
True
Yes
NGE_UQ
19H
Not-greater-than-or-equal (unordered, nonsignaling)
False
True
False
True
No
3-156 Vol. 2A
CMPPD—Compare Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions (Contd.)
Predicate
imm8
Value
Description
Result: A Is 1st Operand, B Is 2nd Operand Signals
#IA on
A >B
A SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF 111;
GREATER_THAN: ZF,PF,CF 000;
LESS_THAN: ZF,PF,CF 001;
EQUAL: ZF,PF,CF 100;
ESAC;
OF, AF, SF 0; }
3-186 Vol. 2A
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);
VCOMISD int _mm_comieq_sd (__m128d a, __m128d b)
VCOMISD int _mm_comilt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comile_sd (__m128d a, __m128d b)
VCOMISD int _mm_comigt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comige_sd (__m128d a, __m128d b)
VCOMISD int _mm_comineq_sd (__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Invalid (if SNaN or QNaN operands), Denormal.
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
Vol. 2A 3-187
INSTRUCTION SET REFERENCE, A-L
COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 2F /r
COMISS xmm1, xmm2/m32
VEX.128.0F.WIG 2F /r
VCOMISS xmm1, xmm2/m32
RM
V/V
AVX
EVEX.LIG.0F.W0 2F /r
VCOMISS xmm1, xmm2/m32{sae}
T1S
V/V
AVX512F
Description
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Compares the single-precision floating-point values in the low quadwords of operand 1 (first operand) and operand
2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered,
greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result
is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.
The COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid
numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
COMISS (all versions)
RESULT OrderedCompare(DEST[31:0] <> SRC[31:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF 111;
GREATER_THAN: ZF,PF,CF 000;
LESS_THAN: ZF,PF,CF 001;
EQUAL: ZF,PF,CF 100;
ESAC;
OF, AF, SF 0; }
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COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);
VCOMISS int _mm_comieq_ss (__m128 a, __m128 b)
VCOMISS int _mm_comilt_ss (__m128 a, __m128 b)
VCOMISS int _mm_comile_ss (__m128 a, __m128 b)
VCOMISS int _mm_comigt_ss (__m128 a, __m128 b)
VCOMISS int _mm_comige_ss (__m128 a, __m128 b)
VCOMISS int _mm_comineq_ss (__m128 a, __m128 b)
SIMD Floating-Point Exceptions
Invalid (if SNaN or QNaN operands), Denormal.
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
Vol. 2A 3-189
INSTRUCTION SET REFERENCE, A-L
CPUID—CPU Identification
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F A2
CPUID
NP
Valid
Valid
Returns processor identification and feature
information to the EAX, EBX, ECX, and EDX
registers, as determined by input entered in
EAX (in some cases, ECX as well).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non-64-bit modes and 64-bit mode.
CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.1 The
instruction’s output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well).
For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value
and the Vendor Identification String in the appropriate registers:
MOV EAX, 00H
CPUID
Table 3-8 shows information returned, depending on the initial value loaded into the EAX register.
Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX
is higher than the maximum input value for basic or extended function for that processor then the data for the
highest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true:
CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)
CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)
CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *)
CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)
CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)
If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on
that processor then 0 is returned in all the registers.
When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence
on input ECX value in the basic leaf is honored.
CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution
guarantees that any modifications to flags, registers, and memory for previous instructions are completed before
the next instruction is fetched and executed.
See also:
“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A.
“Caching Translation Information” in Chapter 4, “Paging,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.
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CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction
Initial EAX
Value
Information Provided about the Processor
Basic CPUID Information
0H
01H
EAX
Maximum Input Value for Basic CPUID Information.
EBX
“Genu”
ECX
“ntel”
EDX
“ineI”
EAX
Version Information: Type, Family, Model, and Stepping ID (see Figure 3-6).
EBX
Bits 07 - 00: Brand Index.
Bits 15 - 08: CLFLUSH line size (Value ∗ 8 = cache line size in bytes; used also by CLFLUSHOPT).
Bits 23 - 16: Maximum number of addressable IDs for logical processors in this physical package*.
Bits 31 - 24: Initial APIC ID.
ECX
Feature Information (see Figure 3-7 and Table 3-10).
EDX
Feature Information (see Figure 3-8 and Table 3-11).
NOTES:
* The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC
IDs reserved for addressing different logical processors in a physical package. This field is only valid if
CPUID.1.EDX.HTT[bit 28]= 1.
02H
03H
EAX
Cache and TLB Information (see Table 3-12).
EBX
Cache and TLB Information.
ECX
Cache and TLB Information.
EDX
Cache and TLB Information.
EAX
Reserved.
EBX
Reserved.
ECX
Bits 00 - 31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
value in this register is reserved.)
EDX
Bits 32 - 63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
value in this register is reserved.)
NOTES:
Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use
the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.
CPUID leaves above 2 and below 80000000H are visible only when IA32_MISC_ENABLE[bit 22] has its default value of 0.
Deterministic Cache Parameters Leaf
04H
NOTES:
Leaf 04H output depends on the initial value in ECX.*
See also: “INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level” on page 214.
EAX
CPUID—CPU Identification
Bits 04 - 00: Cache Type Field.
0 = Null - No more caches.
1 = Data Cache.
2 = Instruction Cache.
3 = Unified Cache.
4-31 = Reserved.
Vol. 2A 3-191
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Bits 07 - 05: Cache Level (starts at 1).
Bit 08: Self Initializing cache level (does not need SW initialization).
Bit 09: Fully Associative cache.
Bits 13 - 10: Reserved.
Bits 25 - 14: Maximum number of addressable IDs for logical processors sharing this cache**, ***.
Bits 31 - 26: Maximum number of addressable IDs for processor cores in the physical
package**, ****, *****.
EBX
Bits 11 - 00: L = System Coherency Line Size**.
Bits 21 - 12: P = Physical Line partitions**.
Bits 31 - 22: W = Ways of associativity**.
ECX
Bits 31-00: S = Number of Sets**.
EDX
Bit 00: Write-Back Invalidate/Invalidate.
0 = WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this
cache.
1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing
this cache.
Bit 01: Cache Inclusiveness.
0 = Cache is not inclusive of lower cache levels.
1 = Cache is inclusive of lower cache levels.
Bit 02: Complex Cache Indexing.
0 = Direct mapped cache.
1 = A complex function is used to index the cache, potentially using all address bits.
Bits 31 - 03: Reserved = 0.
NOTES:
* If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if subleaf n returns EAX[4:0] as 0.
** Add one to the return value to get the result.
***The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing different logical processors sharing this cache.
**** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique
Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of
bits of the initial APIC ID.
***** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.
MONITOR/MWAIT Leaf
05H
EAX
Bits 15 - 00: Smallest monitor-line size in bytes (default is processor's monitor granularity).
Bits 31 - 16: Reserved = 0.
EBX
Bits 15 - 00: Largest monitor-line size in bytes (default is processor's monitor granularity).
Bits 31 - 16: Reserved = 0.
ECX
Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported.
Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled.
Bits 31 - 02: Reserved.
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CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
EDX
Bits 03 - 00: Number of C0* sub C-states supported using MWAIT.
Bits 07 - 04: Number of C1* sub C-states supported using MWAIT.
Bits 11 - 08: Number of C2* sub C-states supported using MWAIT.
Bits 15 - 12: Number of C3* sub C-states supported using MWAIT.
Bits 19 - 16: Number of C4* sub C-states supported using MWAIT.
Bits 23 - 20: Number of C5* sub C-states supported using MWAIT.
Bits 27 - 24: Number of C6* sub C-states supported using MWAIT.
Bits 31 - 28: Number of C7* sub C-states supported using MWAIT.
NOTE:
* The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI Cstates.
Thermal and Power Management Leaf
06H
EAX
Bit 00: Digital temperature sensor is supported if set.
Bit 01: Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).
Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
Bit 03: Reserved.
Bit 04: PLN. Power limit notification controls are supported if set.
Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
Bit 06: PTM. Package thermal management is supported if set.
Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES,
IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set.
Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.
Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.
Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set.
Bit 12: Reserved.
Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are
supported if set.
Bits 31 - 15: Reserved.
EBX
Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor.
Bits 31 - 04: Reserved.
ECX
Bit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The
capability to provide a measure of delivered processor performance (since last reset of the counters), as
a percentage of the expected processor performance when running at the TSC frequency.
Bits 02 - 01: Reserved = 0.
Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set
and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
Bits 31 - 04: Reserved = 0.
EDX
Reserved = 0.
CPUID—CPU Identification
Vol. 2A 3-193
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Structured Extended Feature Flags Enumeration Leaf (Output depends on ECX input value)
07H
Sub-leaf 0 (Input ECX = 0). *
EAX
Bits 31 - 00: Reports the maximum input value for supported leaf 7 sub-leaves.
EBX
Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
Bit 01: IA32_TSC_ADJUST MSR is supported if 1.
Bit 02: SGX. Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1.
Bit 03: BMI1.
Bit 04: HLE.
Bit 05: AVX2.
Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.
Bit 07: SMEP. Supports Supervisor-Mode Execution Prevention if 1.
Bit 08: BMI2.
Bit 09: Supports Enhanced REP MOVSB/STOSB if 1.
Bit 10: INVPCID. If 1, supports INVPCID instruction for system software that manages process-context
identifiers.
Bit 11: RTM.
Bit 12: RDT-M. Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1.
Bit 13: Deprecates FPU CS and FPU DS values if 1.
Bit 14: MPX. Supports Intel® Memory Protection Extensions if 1.
Bit 15: RDT-A. Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1.
Bits 17:16: Reserved.
Bit 18: RDSEED.
Bit 19: ADX.
Bit 20: SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
Bits 22 - 21: Reserved.
Bit 23: CLFLUSHOPT.
Bit 24: CLWB.
Bit 25: Intel Processor Trace.
Bits 28 - 26: Reserved.
Bit 29: SHA. supports Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) if 1.
Bits 31 - 30: Reserved.
ECX
Bit 00: PREFETCHWT1.
Bit 01: Reserved.
Bit 02: UMIP. Supports user-mode instruction prevention if 1.
Bit 03: PKU. Supports protection keys for user-mode pages if 1.
Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions).
Bits 16 - 5: Reserved.
Bits 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
Bit 22: RDPID. Supports Read Processor ID if 1.
Bits 29 - 23: Reserved.
Bit 30: SGX_LC. Supports SGX Launch Configuration if 1.
Bit 31: Reserved.
EDX
Reserved.
NOTE:
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n
exceeds the value that sub-leaf 0 returns in EAX.
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CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Direct Cache Access Information Leaf
09H
EAX
Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
EBX
Reserved.
ECX
Reserved.
EDX
Reserved.
Architectural Performance Monitoring Leaf
0AH
EAX
Bits 07 - 00: Version ID of architectural performance monitoring.
Bits 15 - 08: Number of general-purpose performance monitoring counter per logical processor.
Bits 23 - 16: Bit width of general-purpose, performance monitoring counter.
Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events.
EBX
Bit 00: Core cycle event not available if 1.
Bit 01: Instruction retired event not available if 1.
Bit 02: Reference cycles event not available if 1.
Bit 03: Last-level cache reference event not available if 1.
Bit 04: Last-level cache misses event not available if 1.
Bit 05: Branch instruction retired event not available if 1.
Bit 06: Branch mispredict retired event not available if 1.
Bits 31 - 07: Reserved = 0.
ECX
Reserved = 0.
EDX
Bits 04 - 00: Number of fixed-function performance counters (if Version ID > 1).
Bits 12 - 05: Bit width of fixed-function performance counters (if Version ID > 1).
Reserved = 0.
Extended Topology Enumeration Leaf
0BH
NOTES:
Most of Leaf 0BH output depends on the initial value in ECX.
The EDX output of leaf 0BH is always valid and does not vary with input value in ECX.
Output value in ECX[7:0] always equals input value in ECX[7:0].
For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0.
If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX >
n also return 0 in ECX[15:8].
EAX
Bits 04 - 00: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*.
All logical processors with the same next level ID share current level.
Bits 31 - 05: Reserved.
EBX
Bits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped
by Intel**.
Bits 31- 16: Reserved.
ECX
Bits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type***.
Bits 31 - 16: Reserved.
EDX
Bits 31- 00: x2APIC ID the current logical processor.
NOTES:
* Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
CPUID—CPU Identification
Vol. 2A 3-195
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this
field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors
available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software
and platform hardware configurations.
*** The value of the “level type” field is not related to level numbers in any way, higher “level type” values do not mean higher levels. Level type field has the following encoding:
0: Invalid.
1: SMT.
2: Core.
3-255: Reserved.
Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)
0DH
NOTES:
Leaf 0DH main leaf (ECX = 0).
EAX
Bits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if
EAX[n] is 1.
Bit 00: x87 state.
Bit 01: SSE state.
Bit 02: AVX state.
Bits 04 - 03: MPX state.
Bits 07 - 05: AVX-512 state.
Bit 08: Used for IA32_XSS.
Bit 09: PKRU state.
Bits 31 - 10: Reserved.
EBX
Bits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by
enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area
are not enabled.
ECX
Bit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the
XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in
XCR0.
EDX
Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if
EDX[n] is 1.
Bits 31 - 00: Reserved.
Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
0DH
3-196 Vol. 2A
EAX
Bit 00: XSAVEOPT is available.
Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
Bit 02: Supports XGETBV with ECX = 1 if set.
Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
Bits 31 - 04: Reserved.
EBX
Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
ECX
Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be
set to 1 only if ECX[n] is 1.
Bits 07 - 00: Used for XCR0.
Bit 08: PT state.
Bit 09: Used for XCR0.
Bits 31 - 10: Reserved.
EDX
Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can
be set to 1 only if EDX[n] is 1.
Bits 31 - 00: Reserved.
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)
0DH
NOTES:
Leaf 0DH output depends on the initial value in ECX.
Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the
XCR0 register or the IA32_XSS MSR.
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 ≤ n ≤ 31) is invalid
if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 ≤ n ≤ 63) is invalid if
sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
EAX
Bits 31 - 0: The size in bytes (from the offset specified in EBX) of the save area for an extended state
feature associated with a valid sub-leaf index, n.
EBX
Bits 31 - 0: The offset in bytes of this extended state component’s save area from the beginning of the
XSAVE/XRSTOR area.
This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.
ECX
Bit 00 is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear
if bit n is instead supported in XCR0.
Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component
located on the next 64-byte boundary following the preceding state component (otherwise, it is located
immediately following the preceding state component).
Bits 31 - 02 are reserved.
This field reports 0 if the sub-leaf index, n, is invalid*.
EDX
This field reports 0 if the sub-leaf index, n, is invalid*; otherwise it is reserved.
Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Sub-leaf (EAX = 0FH, ECX = 0)
0FH
NOTES:
Leaf 0FH output depends on the initial value in ECX.
Sub-leaf index 0 reports valid resource type starting at bit position 1 of EDX.
EAX
Reserved.
EBX
Bits 31 - 00: Maximum range (zero-based) of RMID within this physical processor of all types.
ECX
Reserved.
EDX
Bit 00: Reserved.
Bit 01: Supports L3 Cache Intel RDT Monitoring if 1.
Bits 31 - 02: Reserved.
L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf (EAX = 0FH, ECX = 1)
0FH
NOTES:
Leaf 0FH output depends on the initial value in ECX.
EAX
Reserved.
EBX
Bits 31 - 00: Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
ECX
Maximum range (zero-based) of RMID of this resource type.
EDX
Bit 00: Supports L3 occupancy monitoring if 1.
Bit 01: Supports L3 Total Bandwidth monitoring if 1.
Bit 02: Supports L3 Local Bandwidth monitoring if 1.
Bits 31 - 03: Reserved.
CPUID—CPU Identification
Vol. 2A 3-197
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf (EAX = 10H, ECX = 0)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
Sub-leaf index 0 reports valid resource identification (ResID) starting at bit position 1 of EBX.
EAX
Reserved.
EBX
Bit 00: Reserved.
Bit 01: Supports L3 Cache Allocation Technology if 1.
Bit 02: Supports L2 Cache Allocation Technology if 1.
Bits 31 - 03: Reserved.
ECX
Reserved.
EDX
Reserved.
L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =1)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
EAX
Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.
Bits 31 - 05: Reserved.
EBX
Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.
ECX
Bit 00: Reserved.
Bit 01: Updates of COS should be infrequent if 1.
Bit 02: Code and Data Prioritization Technology supported if 1.
Bits 31 - 03: Reserved.
EDX
Bits 15 - 00: Highest COS number supported for this ResID.
Bits 31 - 16: Reserved.
L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =2)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
EAX
Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.
Bits 31 - 05: Reserved.
EBX
Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.
ECX
Bits 31 - 00: Reserved.
EDX
Bits 15 - 00: Highest COS number supported for this ResID.
Bits 31 - 16: Reserved.
Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0)
NOTES:
Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
12H
3-198 Vol. 2A
EAX
Bit 00: SGX1. If 1, Indicates Intel SGX supports the collection of SGX1 leaf functions.
Bit 01: SGX2. If 1, Indicates Intel SGX supports the collection of SGX2 leaf functions.
Bit 31 - 02: Reserved.
EBX
Bit 31 - 00: MISCSELECT. Bit vector of supported extended SGX features.
ECX
Bit 31 - 00: Reserved.
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
EDX
Bit 07 - 00: MaxEnclaveSize_Not64. The maximum supported enclave size in non-64-bit mode is
2^(EDX[7:0]).
Bit 15 - 08: MaxEnclaveSize_64. The maximum supported enclave size in 64-bit mode is 2^(EDX[15:8]).
Bits 31 - 16: Reserved.
Intel SGX Attributes Enumeration Leaf, sub-leaf 1 (EAX = 12H, ECX = 1)
NOTES:
Leaf 12H sub-leaf 1 (ECX = 1) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
12H
EAX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE.
EBX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE.
ECX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.
EDX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.
Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)
NOTES:
Leaf 12H sub-leaf 2 or higher (ECX >= 2) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
For sub-leaves (ECX = 2 or higher), definition of EDX,ECX,EBX,EAX[31:4] depends on the sub-leaf type
listed below.
12H
EAX
Bit 03 - 00: Sub-leaf Type
0000b: Indicates this sub-leaf is invalid.
0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the
Enclave Page Cache (EPC) section.
All other type encodings are reserved.
Type
0000b. This sub-leaf is invalid.
EDX:ECX:EBX:EAX return 0.
Type
0001b. This sub-leaf enumerates an EPC sections with EDX:ECX, EBX:EAX defined as follows.
EAX[11:04]: Reserved (enumerate 0).
EAX[31:12]: Bits 31:12 of the physical address of the base of the EPC section.
EBX[19:00]: Bits 51:32 of the physical address of the base of the EPC section.
EBX[31:20]: Reserved.
ECX[03:00]: EPC section property encoding defined as follows:
If EAX[3:0] 0000b, then all bits of the EDX:ECX pair are enumerated as 0.
If EAX[3:0] 0001b, then this section has confidentiality and integrity protection.
All other encodings are reserved.
ECX[11:04]: Reserved (enumerate 0).
ECX[31:12]: Bits 31:12 of the size of the corresponding EPC section within the Processor Reserved
Memory.
EDX[19:00]: Bits 51:32 of the size of the corresponding EPC section within the Processor Reserved
Memory.
EDX[31:20]: Reserved.
CPUID—CPU Identification
Vol. 2A 3-199
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Intel Processor Trace Enumeration Main Leaf (EAX = 14H, ECX = 0)
NOTES:
Leaf 14H main leaf (ECX = 0).
14H
EAX
Bits 31 - 00: Reports the maximum sub-leaf supported in leaf 14H.
EBX
Bit 00: If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH
MSR can be accessed.
Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.
Bit 02: If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across
warm reset.
Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets.
Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and
IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets.
Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn),
enabling Power Event Trace packet generation.
Bit 31 - 06: Reserved.
ECX
Bit 00: If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output
scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
Bit 01: If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.
Bit 02: If 1, indicates support of Single-Range Output scheme.
Bit 03: If 1, indicates support of output to Trace Transport subsystem.
Bit 30 - 04: Reserved.
Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base component.
EDX
Bits 31 - 00: Reserved.
Intel Processor Trace Enumeration Sub-leaf (EAX = 14H, ECX = 1)
14H
EAX
Bits 02 - 00: Number of configurable Address Ranges for filtering.
Bits 15 - 03: Reserved.
Bits 31 - 16: Bitmap of supported MTC period encodings.
EBX
Bits 15 - 00: Bitmap of supported Cycle Threshold value encodings.
Bit 31 - 16: Bitmap of supported Configurable PSB frequency encodings.
ECX
Bits 31 - 00: Reserved.
EDX
Bits 31 - 00: Reserved.
Time Stamp Counter and Nominal Core Crystal Clock Information Leaf
15H
3-200 Vol. 2A
NOTES:
If EBX[31:0] is 0, the TSC/”core crystal clock” ratio is not enumerated.
EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.
If ECX is 0, the nominal core crystal clock frequency is not enumerated.
“TSC frequency” = “core crystal clock frequency” * EBX/EAX.
The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
EAX
Bits 31 - 00: An unsigned integer which is the denominator of the TSC/”core crystal clock” ratio.
EBX
Bits 31 - 00: An unsigned integer which is the numerator of the TSC/”core crystal clock” ratio.
ECX
Bits 31 - 00: An unsigned integer which is the nominal frequency of the core crystal clock in Hz.
EDX
Bits 31 - 00: Reserved = 0.
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Processor Frequency Information Leaf
16H
EAX
Bits 15 - 00: Processor Base Frequency (in MHz).
Bits 31 - 16: Reserved =0.
EBX
Bits 15 - 00: Maximum Frequency (in MHz).
Bits 31 - 16: Reserved = 0.
ECX
Bits 15 - 00: Bus (Reference) Frequency (in MHz).
Bits 31 - 16: Reserved = 0.
EDX
Reserved.
NOTES:
* Data is returned from this interface in accordance with the processor's specification and does not reflect
actual values. Suitable use of this data includes the display of processor information in like manner to the
processor brand string and for determining the appropriate range to use when displaying processor
information e.g. frequency history graphs. The returned information should not be used for any other
purpose as the returned information does not accurately correlate to information / counters returned by
other processor interfaces.
While a processor may support the Processor Frequency Information leaf, fields that return a value of
zero are not supported.
System-On-Chip Vendor Attribute Enumeration Main Leaf (EAX = 17H, ECX = 0)
17H
NOTES:
Leaf 17H main leaf (ECX = 0).
Leaf 17H output depends on the initial value in ECX.
Leaf 17H sub-leaves 1 through 3 reports SOC Vendor Brand String.
Leaf 17H is valid if MaxSOCID_Index >= 3.
Leaf 17H sub-leaves 4 and above are reserved.
EAX
Bits 31 - 00: MaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.
EBX
Bits 15 - 00: SOC Vendor ID.
Bit 16: IsVendorScheme. If 1, the SOC Vendor ID field is assigned via an industry standard enumeration
scheme. Otherwise, the SOC Vendor ID field is assigned by Intel.
Bits 31 - 17: Reserved = 0.
ECX
Bits 31 - 00: Project ID. A unique number an SOC vendor assigns to its SOC projects.
EDX
Bits 31 - 00: Stepping ID. A unique number within an SOC project that an SOC vendor assigns.
System-On-Chip Vendor Attribute Enumeration Sub-leaf (EAX = 17H, ECX = 1..3)
17H
EAX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
EBX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
ECX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
EDX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
NOTES:
Leaf 17H output depends on the initial value in ECX.
SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H.
The complete SOC Vendor Brand String is constructed by concatenating in ascending order of
EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
CPUID—CPU Identification
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INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
System-On-Chip Vendor Attribute Enumeration Sub-leaves (EAX = 17H, ECX > MaxSOCID_Index)
17H
NOTES:
Leaf 17H output depends on the initial value in ECX.
EAX
Bits 31 - 00: Reserved = 0.
EBX
Bits 31 - 00: Reserved = 0.
ECX
Bits 31 - 00: Reserved = 0.
EDX
Bits 31 - 00: Reserved = 0.
Unimplemented CPUID Leaf Functions
40000000H
4FFFFFFFH
Invalid. No existing or future CPU will return processor identification or feature information if the initial
EAX value is in the range 40000000H to 4FFFFFFFH.
Extended Function CPUID Information
80000000H EAX
Maximum Input Value for Extended Function CPUID Information.
EBX
Reserved.
ECX
Reserved.
EDX
Reserved.
80000001H EAX
Extended Processor Signature and Feature Bits.
EBX
Reserved.
ECX
Bit 00: LAHF/SAHF available in 64-bit mode.
Bits 04 - 01: Reserved.
Bit 05: LZCNT.
Bits 07 - 06: Reserved.
Bit 08: PREFETCHW.
Bits 31 - 09: Reserved.
EDX
Bits 10 - 00: Reserved.
Bit 11: SYSCALL/SYSRET available in 64-bit mode.
Bits 19 - 12: Reserved = 0.
Bit 20: Execute Disable Bit available.
Bits 25 - 21: Reserved = 0.
Bit 26: 1-GByte pages are available if 1.
Bit 27: RDTSCP and IA32_TSC_AUX are available if 1.
Bit 28: Reserved = 0.
Bit 29: Intel® 64 Architecture available if 1.
Bits 31 - 30: Reserved = 0.
80000002H EAX
EBX
ECX
EDX
Processor Brand String.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
80000003H EAX
EBX
ECX
EDX
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
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INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
80000004H EAX
EBX
ECX
EDX
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
80000005H EAX
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
Reserved = 0.
80000006H EAX
EBX
Reserved = 0.
Reserved = 0.
ECX
EDX
Bits 07 - 00: Cache Line size in bytes.
Bits 11 - 08: Reserved.
Bits 15 - 12: L2 Associativity field *.
Bits 31 - 16: Cache size in 1K units.
Reserved = 0.
NOTES:
* L2 associativity field encodings:
00H - Disabled.
01H - Direct mapped.
02H - 2-way.
04H - 4-way.
06H - 8-way.
08H - 16-way.
0FH - Fully associative.
80000007H EAX
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
Bits 07 - 00: Reserved = 0.
Bit 08: Invariant TSC available if 1.
Bits 31 - 09: Reserved = 0.
80000008H EAX
Linear/Physical Address size.
Bits 07 - 00: #Physical Address Bits*.
Bits 15 - 08: #Linear Address Bits.
Bits 31 - 16: Reserved = 0.
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
NOTES:
* If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should
come from this field.
INPUT EAX = 0: Returns CPUID’s Highest Value for Basic Processor Information and the Vendor Identification String
When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for
returning basic processor information. The value is returned in the EAX register and is processor specific.
CPUID—CPU Identification
Vol. 2A 3-203
INSTRUCTION SET REFERENCE, A-L
A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is “GenuineIntel” and is expressed:
EBX ← 756e6547h (* “Genu”, with G in the low eight bits of BL *)
EDX ← 49656e69h (* “ineI”, with i in the low eight bits of DL *)
ECX ← 6c65746eh (* “ntel”, with n in the low eight bits of CL *)
INPUT EAX = 80000000H: Returns CPUID’s Highest Value for Extended Processor Information
When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recognizes for returning extended processor information. The value is returned in the EAX register and is processor
specific.
IA32_BIOS_SIGN_ID Returns Microcode Update Signature
For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update
signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
INPUT EAX = 01H: Returns Model, Family, Stepping Information
When CPUID executes with EAX set to 01H, version information is returned in EAX (see Figure 3-6). For example:
model, family, and processor type for the Intel Xeon processor 5100 series is as follows:
•
•
•
Model — 1111B
Family — 0101B
Processor Type — 00B
See Table 3-9 for available processor type values. Stepping IDs are provided as needed.
31
28 27
20 19
Extended
Family ID
EAX
16 15 14 13 12 11
Extended
Model ID
8 7
Family
ID
4
Model
3
0
Stepping
ID
Extended Family ID (0)
Extended Model ID (0)
Processor Type
Family (0FH for the Pentium 4 Processor Family)
Model
Reserved
OM16525
Figure 3-6. Version Information Returned by CPUID in EAX
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INSTRUCTION SET REFERENCE, A-L
Table 3-9. Processor Type Field
Type
Encoding
Original OEM Processor
00B
®
Intel OverDrive Processor
01B
Dual processor (not applicable to Intel486 processors)
10B
Intel reserved
11B
NOTE
See Chapter 19 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,
for information on identifying earlier IA-32 processors.
The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display
using the following rule:
IF Family_ID ≠ 0FH
THEN DisplayFamily = Family_ID;
ELSE DisplayFamily = Extended_Family_ID + Family_ID;
(* Right justify and zero-extend 4-bit field. *)
FI;
(* Show DisplayFamily as HEX field. *)
The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a
display using the following rule:
IF (Family_ID = 06H or Family_ID = 0FH)
THEN DisplayModel = (Extended_Model_ID « 4) + Model_ID;
(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)
ELSE DisplayModel = Model_ID;
FI;
(* Show DisplayModel as HEX field. *)
INPUT EAX = 01H: Returns Additional Information in EBX
When CPUID executes with EAX set to 01H, additional information is returned to the EBX register:
•
Brand index (low byte of EBX) — this number provides an entry into a brand string table that contains brand
strings for IA-32 processors. More information about this field is provided later in this section.
•
CLFLUSH instruction cache line size (second byte of EBX) — this number indicates the size of the cache line
flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the
Pentium 4 processor.
•
Local APIC ID (high byte of EBX) — this number is the 8-bit ID that is assigned to the local APIC on the
processor during power up. This field was introduced in the Pentium 4 processor.
INPUT EAX = 01H: Returns Feature Information in ECX and EDX
When CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.
•
•
Figure 3-7 and Table 3-10 show encodings for ECX.
Figure 3-8 and Table 3-11 show encodings for EDX.
For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.
NOTE
Software must confirm that a processor feature is present using feature flags returned by CPUID
prior to using the feature. Software should not depend on future offerings retaining all features.
CPUID—CPU Identification
Vol. 2A 3-205
INSTRUCTION SET REFERENCE, A-L
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
ECX
3 2 1
0
0
RDRAND
F16C
AVX
OSXSAVE
XSAVE
AES
TSC-Deadline
POPCNT
MOVBE
x2APIC
SSE4_2 — SSE4.2
SSE4_1 — SSE4.1
DCA — Direct Cache Access
PCID — Process-context Identifiers
PDCM — Perf/Debug Capability MSR
xTPR Update Control
CMPXCHG16B
FMA — Fused Multiply Add
SDBG
CNXT-ID — L1 Context ID
SSSE3 — SSSE3 Extensions
TM2 — Thermal Monitor 2
EIST — Enhanced Intel SpeedStep® Technology
SMX — Safer Mode Extensions
VMX — Virtual Machine Extensions
DS-CPL — CPL Qualified Debug Store
MONITOR — MONITOR/MWAIT
DTES64 — 64-bit DS Area
PCLMULQDQ — Carryless Multiplication
SSE3 — SSE3 Extensions
OM16524b
Reserved
Figure 3-7. Feature Information Returned in the ECX Register
Table 3-10. Feature Information Returned in the ECX Register
Bit #
Mnemonic
Description
0
SSE3
Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this
technology.
1
PCLMULQDQ
PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction.
2
DTES64
64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.
3
MONITOR
MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.
4
DS-CPL
CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the
Debug Store feature to allow for branch message storage qualified by CPL.
5
VMX
Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.
6
SMX
Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See
Chapter 6, “Safer Mode Extensions Reference”.
7
EIST
Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this
technology.
8
TM2
Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.
9
SSSE3
A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A
value of 0 indicates the instruction extensions are not present in the processor.
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INSTRUCTION SET REFERENCE, A-L
Table 3-10. Feature Information Returned in the ECX Register (Contd.)
Bit #
Mnemonic
Description
10
CNXT-ID
L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode
or shared mode. A value of 0 indicates this feature is not supported. See definition of the
IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.
11
SDBG
A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.
12
FMA
A value of 1 indicates the processor supports FMA extensions using YMM state.
13
CMPXCHG16B
CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the
“CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes” section in this chapter for a
description.
14
xTPR Update
Control
xTPR Update Control. A value of 1 indicates that the processor supports changing
IA32_MISC_ENABLE[bit 23].
15
PDCM
Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance
and debug feature indication MSR IA32_PERF_CAPABILITIES.
16
Reserved
Reserved
17
PCID
Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that
software may set CR4.PCIDE to 1.
18
DCA
A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped
device.
19
SSE4.1
A value of 1 indicates that the processor supports SSE4.1.
20
SSE4.2
A value of 1 indicates that the processor supports SSE4.2.
21
x2APIC
A value of 1 indicates that the processor supports x2APIC feature.
22
MOVBE
A value of 1 indicates that the processor supports MOVBE instruction.
23
POPCNT
A value of 1 indicates that the processor supports the POPCNT instruction.
24
TSC-Deadline
A value of 1 indicates that the processor’s local APIC timer supports one-shot operation using a
TSC deadline value.
25
AESNI
A value of 1 indicates that the processor supports the AESNI instruction extensions.
26
XSAVE
A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states
feature, the XSETBV/XGETBV instructions, and XCR0.
27
OSXSAVE
A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV
instructions to access XCR0 and to support processor extended state management using
XSAVE/XRSTOR.
28
AVX
A value of 1 indicates the processor supports the AVX instruction extensions.
29
F16C
A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.
30
RDRAND
A value of 1 indicates that processor supports RDRAND instruction.
31
Not Used
Always returns 0.
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INSTRUCTION SET REFERENCE, A-L
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
EDX
PBE–Pend. Brk. EN.
TM–Therm. Monitor
HTT–Multi-threading
SS–Self Snoop
SSE2–SSE2 Extensions
SSE–SSE Extensions
FXSR–FXSAVE/FXRSTOR
MMX–MMX Technology
ACPI–Thermal Monitor and Clock Ctrl
DS–Debug Store
CLFSH–CLFLUSH instruction
PSN–Processor Serial Number
PSE-36 – Page Size Extension
PAT–Page Attribute Table
CMOV–Conditional Move/Compare Instruction
MCA–Machine Check Architecture
PGE–PTE Global Bit
MTRR–Memory Type Range Registers
SEP–SYSENTER and SYSEXIT
APIC–APIC on Chip
CX8–CMPXCHG8B Inst.
MCE–Machine Check Exception
PAE–Physical Address Extensions
MSR–RDMSR and WRMSR Support
TSC–Time Stamp Counter
PSE–Page Size Extensions
DE–Debugging Extensions
VME–Virtual-8086 Mode Enhancement
FPU–x87 FPU on Chip
Reserved
OM16523
Figure 3-8. Feature Information Returned in the EDX Register
3-208 Vol. 2A
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INSTRUCTION SET REFERENCE, A-L
Table 3-11. More on Feature Information Returned in the EDX Register
Bit #
Mnemonic
Description
0
FPU
Floating Point Unit On-Chip. The processor contains an x87 FPU.
1
VME
Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the
feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS
with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
2
DE
Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional
trapping of accesses to DR4 and DR5.
3
PSE
Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the
feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and
PTEs.
4
TSC
Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.
5
MSR
Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are
supported. Some of the MSRs are implementation dependent.
6
PAE
Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table
entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of
4 Mbyte pages if PAE bit is 1.
7
MCE
Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the
feature. This feature does not define the model-specific implementations of machine-check error logging,
reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor
version to do model specific processing of the exception, or test for the presence of the Machine Check feature.
8
CX8
CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly
locked and atomic).
9
APIC
APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to
memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some
processors permit the APIC to be relocated).
10
Reserved
Reserved
11
SEP
SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.
12
MTRR
Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe
what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are
supported.
13
PGE
Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries
that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.
14
MCA
Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine
errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting
MSRs are supported.
15
CMOV
Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is
present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported
16
PAT
Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range
Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear
address on a 4KB granularity.
17
PSE-36
36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with
32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in
bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to
40 bits in size.
18
PSN
Processor Serial Number. The processor supports the 96-bit processor identification number feature and the
feature is enabled.
19
CLFSH
CLFLUSH Instruction. CLFLUSH Instruction is supported.
20
Reserved
Reserved
CPUID—CPU Identification
Vol. 2A 3-209
INSTRUCTION SET REFERENCE, A-L
Table 3-11. More on Feature Information Returned in the EDX Register (Contd.)
Bit #
Mnemonic
Description
21
DS
Debug Store. The processor supports the ability to write debug information into a memory resident buffer.
This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see
Chapter 23, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3C).
22
ACPI
Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that
allow processor temperature to be monitored and processor performance to be modulated in predefined duty
cycles under software control.
23
MMX
Intel MMX Technology. The processor supports the Intel MMX technology.
24
FXSR
FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and
restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an
operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.
25
SSE
SSE. The processor supports the SSE extensions.
26
SSE2
SSE2. The processor supports the SSE2 extensions.
27
SS
Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its
own cache structure for transactions issued to the bus.
28
HTT
Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in
the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the
value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is
valid for the package.
29
TM
Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).
30
Reserved
Reserved
31
PBE
Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the
stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the
processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the
IA32_MISC_ENABLE MSR enables this capability.
INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX
When CPUID executes with EAX set to 02H, the processor returns information about the processor’s internal TLBs,
cache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form
and fall into the following categories:
•
The least-significant byte in register EAX (register AL) will always return 01H. Software should ignore this value
and not interpret it as an informational descriptor.
•
The most significant bit (bit 31) of each register indicates whether the register contains valid information (set
to 0) or is reserved (set to 1).
•
If a register contains valid information, the information is contained in 1 byte descriptors. There are four types
of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table
3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX
registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache,
prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general
descriptor type (FFH) and not report any byte descriptor of “cache type” via CPUID leaf 2.
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Table 3-12. Encoding of CPUID Leaf 2 Descriptors
Value
Type
Description
00H
General
01H
TLB
Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries
02H
TLB
Instruction TLB: 4 MByte pages, fully associative, 2 entries
03H
TLB
Data TLB: 4 KByte pages, 4-way set associative, 64 entries
04H
TLB
Data TLB: 4 MByte pages, 4-way set associative, 8 entries
05H
TLB
Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
06H
Cache
1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size
08H
Cache
1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size
09H
Cache
1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size
0AH
Cache
1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
0BH
TLB
0CH
Cache
1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
0DH
Cache
1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size
Null descriptor, this byte contains no information
Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries
0EH
Cache
1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size
1DH
Cache
2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size
21H
Cache
2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size
22H
Cache
3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector
23H
Cache
3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
24H
Cache
2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size
25H
Cache
3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
29H
Cache
3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
2CH
Cache
1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size
30H
Cache
1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size
40H
Cache
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache
41H
Cache
2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
42H
Cache
2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
43H
Cache
2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
44H
Cache
2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
45H
Cache
2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
46H
Cache
3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
47H
Cache
3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
48H
Cache
2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
49H
Cache
3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model
06H);
2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
4AH
Cache
3rd-level cache: 6MByte, 12-way set associative, 64 byte line size
4BH
Cache
3rd-level cache: 8MByte, 16-way set associative, 64 byte line size
4CH
Cache
3rd-level cache: 12MByte, 12-way set associative, 64 byte line size
4DH
Cache
3rd-level cache: 16MByte, 16-way set associative, 64 byte line size
4EH
Cache
2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
4FH
TLB
Instruction TLB: 4 KByte pages, 32 entries
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Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)
Value
Type
Description
50H
TLB
Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
51H
TLB
Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
52H
TLB
Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries
55H
TLB
Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries
56H
TLB
Data TLB0: 4 MByte pages, 4-way set associative, 16 entries
57H
TLB
Data TLB0: 4 KByte pages, 4-way associative, 16 entries
59H
TLB
Data TLB0: 4 KByte pages, fully associative, 16 entries
5AH
TLB
Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries
5BH
TLB
Data TLB: 4 KByte and 4 MByte pages, 64 entries
5CH
TLB
Data TLB: 4 KByte and 4 MByte pages,128 entries
5DH
TLB
Data TLB: 4 KByte and 4 MByte pages,256 entries
60H
Cache
61H
TLB
Instruction TLB: 4 KByte pages, fully associative, 48 entries
63H
TLB
Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte
pages, 4-way set associative, 4 entries
64H
TLB
Data TLB: 4 KByte pages, 4-way set associative, 512 entries
66H
Cache
1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size
67H
Cache
1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size
68H
Cache
1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size
6AH
Cache
uTLB: 4 KByte pages, 8-way set associative, 64 entries
6BH
Cache
DTLB: 4 KByte pages, 8-way set associative, 256 entries
1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size
6CH
Cache
DTLB: 2M/4M pages, 8-way set associative, 128 entries
6DH
Cache
DTLB: 1 GByte pages, fully associative, 16 entries
70H
Cache
Trace cache: 12 K-μop, 8-way set associative
71H
Cache
Trace cache: 16 K-μop, 8-way set associative
72H
Cache
Trace cache: 32 K-μop, 8-way set associative
76H
TLB
78H
Cache
2nd-level cache: 1 MByte, 4-way set associative, 64byte line size
79H
Cache
2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
Instruction TLB: 2M/4M pages, fully associative, 8 entries
7AH
Cache
2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7BH
Cache
2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7CH
Cache
2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector
7DH
Cache
2nd-level cache: 2 MByte, 8-way set associative, 64byte line size
7FH
Cache
2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size
80H
Cache
2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size
82H
Cache
2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size
83H
Cache
2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size
84H
Cache
2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size
85H
Cache
2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size
86H
Cache
2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size
87H
Cache
2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size
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Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)
Value
Type
Description
A0H
DTLB
B0H
TLB
Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries
B1H
TLB
Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
B2H
TLB
Instruction TLB: 4KByte pages, 4-way set associative, 64 entries
B3H
TLB
Data TLB: 4 KByte pages, 4-way set associative, 128 entries
B4H
TLB
Data TLB1: 4 KByte pages, 4-way associative, 256 entries
B5H
TLB
Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
B6H
TLB
Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
BAH
TLB
Data TLB1: 4 KByte pages, 4-way associative, 64 entries
C0H
TLB
Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries
C1H
STLB
Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
C2H
DTLB
DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries
C3H
STLB
Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way,
16 entries.
C4H
DTLB
DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
CAH
STLB
Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries
D0H
Cache
3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size
D1H
Cache
3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size
D2H
Cache
3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size
D6H
Cache
3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size
D7H
Cache
3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size
DTLB: 4k pages, fully associative, 32 entries
D8H
Cache
3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size
DCH
Cache
3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size
DDH
Cache
3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size
DEH
Cache
3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size
E2H
Cache
3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size
E3H
Cache
3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size
E4H
Cache
3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size
EAH
Cache
3rd-level cache: 12MByte, 24-way set associative, 64 byte line size
EBH
Cache
3rd-level cache: 18MByte, 24-way set associative, 64 byte line size
ECH
Cache
3rd-level cache: 24MByte, 24-way set associative, 64 byte line size
F0H
Prefetch
64-Byte prefetching
F1H
Prefetch
128-Byte prefetching
FFH
General
CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters
Example 3-1. Example of Cache and TLB Interpretation
The first member of the family of Pentium 4 processors returns the following information about caches and TLBs
when the CPUID executes with an input value of 2:
EAX
EBX
ECX
EDX
66 5B 50 01H
0H
0H
00 7A 70 00H
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Which means:
•
•
The least-significant byte (byte 0) of register EAX is set to 01H. This value should be ignored.
•
Bytes 1, 2, and 3 of register EAX indicate that the processor has:
The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register
contains valid 1-byte descriptors.
— 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.
— 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.
— 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.
•
•
The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.
Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:
— 00H - NULL descriptor.
— 70H - Trace cache: 12 K-μop, 8-way set associative.
— 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.
— 00H - NULL descriptor.
INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level
When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data
that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid
index values start from 0.
Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an
index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally
defined fields reported by deterministic cache parameters are documented in Table 3-8.
This Cache Size in Bytes
= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)
= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)
The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical
package. This information is constant for all valid index values. Software can query the raw data reported by
executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in
Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
INPUT EAX = 05H: Returns MONITOR and MWAIT Features
When CPUID executes with EAX set to 05H, the processor returns information about features available to
MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with
MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power management. See Table 3-8.
INPUT EAX = 06H: Returns Thermal and Power Management Features
When CPUID executes with EAX set to 06H, the processor returns information about thermal and power management features. See Table 3-8.
INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information
When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum
input value for sub-leaves that contain extended feature flags. See Table 3-8.
When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8),
the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest
leaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.
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INPUT EAX = 09H: Returns Direct Cache Access Information
When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabilities. See Table 3-8.
INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features
When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural
performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see
Table 3-8) is greater than Pn 0. See Table 3-8.
For each version of architectural performance monitoring capability, software must enumerate this leaf to discover
the programming facilities and the architectural performance events available in the processor. The details are
described in Chapter 23, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3C.
INPUT EAX = 0BH: Returns Extended Topology Information
When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumeration data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported
by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.
INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information
When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector
representation of all processor state extensions that are supported in the processor and storage size requirements
of the XSAVE/XRSTOR area. See Table 3-8.
When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns
information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area.
See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves
and obtain size and offset information for each processor extended state save area:
For i = 2 to 62 // sub-leaf 1 is reserved
IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX
Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;
FI;
INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information
When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector
representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID
values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds
to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that software must use to query QoS monitoring capability available for that type. See Table 3-8.
When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns information software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the
IA32_QM_CTR MSR.
INPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information
When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector
representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit
1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or
ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.
When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns information about available classes of service and range of QoS mask MSRs that software can use to configure each
class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.
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INPUT EAX = 12H: Returns Intel SGX Enumeration Information
When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capabilities. See Table 3-8.
When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attributes. See Table 3-8.
When CPUID executes with EAX set to 12H and ECX = n (n > 1), the processor returns information about Intel SGX
Enclave Page Cache. See Table 3-8.
INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information
When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor
Trace extensions. See Table 3-8.
When CPUID executes with EAX set to 14H and ECX = n (n > 0 and less than the number of non-zero bits in
CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor
Trace. See Table 3-8.
INPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information
When CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp
Counter and Core Crystal Clock. See Table 3-8.
INPUT EAX = 16H: Returns Processor Frequency Information
When CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Information. See Table 3-8.
INPUT EAX = 17H: Returns System-On-Chip Information
When CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor
Attribute Enumeration. See Table 3-8.
METHODS FOR RETURNING BRANDING INFORMATION
Use the following techniques to access branding information:
1. Processor brand string method.
2. Processor brand index; this method uses a software supplied brand string table.
These two methods are discussed in the following sections. For methods that are available in early processors, see
Section: “Identification of Earlier IA-32 Processors” in Chapter 19 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
The Processor Brand String Method
Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software
should execute this algorithm on all Intel 64 and IA-32 processors.
This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor
Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.
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INSTRUCTION SET REFERENCE, A-L
Input: EAX=
0x80000000
CPUID
IF (EAX & 0x80000000)
CPUID
Function
Supported
False
Processor Brand
String Not
Supported
True
Processor Brand
String Supported
True ≥
Extended
EAX Return Value =
Max. Extended CPUID
Function Index
IF (EAX Return Value
≥ 0x80000004)
OM15194
Figure 3-9. Determination of Support for the Processor Brand String
How Brand Strings Work
To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input
value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-terminated.
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Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.
Table 3-13. Processor Brand String Returned with Pentium 4 Processor
EAX Input Value
80000002H
80000003H
80000004H
Return Values
ASCII Equivalent
EAX = 20202020H
“
”
EBX = 20202020H
“ ”
ECX = 20202020H
“ ”
EDX = 6E492020H
“nI ”
EAX = 286C6574H
“(let”
EBX = 50202952H
“P )R”
ECX = 69746E65H
“itne”
EDX = 52286D75H
“R(mu”
EAX = 20342029H
“ 4 )”
EBX = 20555043H
“ UPC”
ECX = 30303531H
“0051”
EDX = 007A484DH
“\0zHM”
Extracting the Processor Frequency from Brand Strings
Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the
processor brand string.
Scan "Brand String" in
Reverse Byte Order
"zHM", or
"zHG", or
"zHT"
Match
Substring
IF Substring Matched
Determine "Freq"
and "Multiplier"
True
False
If "zHM"
If "zHG"
Determine "Multiplier"
Determine "Freq"
Processor Base
Frequency =
"Freq" x "Multiplier"
If "zHT"
Scan Digits
Until Blank
In Reverse Order
Report Error
Multiplier = 1 x 106
Multiplier = 1 x 109
Multiplier = 1 x 1012
Reverse Digits
To Decimal Value
"Freq" = X.YZ if
Digits = "ZY.X"
OM15195
Figure 3-10. Algorithm for Extracting Processor Frequency
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The Processor Brand Index Method
The brand index method (introduced with Pentium® III Xeon® processors) provides an entry point into a brand
identification table that is maintained in memory by system software and is accessible from system- and user-level
code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official
Intel family and model number of a processor.
When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can
then use this index to locate the brand identification string for the processor in the brand identification table. The
first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not
support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand
index method is no longer supported. Use brand string method instead.
Table 3-14 shows brand indices that have identification strings associated with them.
Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings
Brand Index
Brand String
00H
This processor does not support the brand identification feature
01H
Intel(R) Celeron(R) processor1
02H
Intel(R) Pentium(R) III processor1
03H
Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R)
processor
04H
Intel(R) Pentium(R) III processor
06H
Mobile Intel(R) Pentium(R) III processor-M
07H
Mobile Intel(R) Celeron(R) processor1
08H
Intel(R) Pentium(R) 4 processor
09H
Intel(R) Pentium(R) 4 processor
0AH
Intel(R) Celeron(R) processor1
0BH
Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP
0CH
Intel(R) Xeon(R) processor MP
0EH
Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor
0FH
Mobile Intel(R) Celeron(R) processor1
11H
Mobile Genuine Intel(R) processor
12H
Intel(R) Celeron(R) M processor
13H
Mobile Intel(R) Celeron(R) processor1
14H
Intel(R) Celeron(R) processor
15H
Mobile Genuine Intel(R) processor
16H
Intel(R) Pentium(R) M processor
17H
Mobile Intel(R) Celeron(R) processor1
18H – 0FFH
RESERVED
NOTES:
1. Indicates versions of these processors that were introduced after the Pentium III
IA-32 Architecture Compatibility
CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the
Intel486 processor.
CPUID—CPU Identification
Vol. 2A 3-219
INSTRUCTION SET REFERENCE, A-L
Operation
IA32_BIOS_SIGN_ID MSR ← Update with installed microcode revision number;
CASE (EAX) OF
EAX = 0:
EAX ← Highest basic function input value understood by CPUID;
EBX ← Vendor identification string;
EDX ← Vendor identification string;
ECX ← Vendor identification string;
BREAK;
EAX = 1H:
EAX[3:0] ← Stepping ID;
EAX[7:4] ← Model;
EAX[11:8] ← Family;
EAX[13:12] ← Processor type;
EAX[15:14] ← Reserved;
EAX[19:16] ← Extended Model;
EAX[27:20] ← Extended Family;
EAX[31:28] ← Reserved;
EBX[7:0] ← Brand Index; (* Reserved if the value is zero. *)
EBX[15:8] ← CLFLUSH Line Size;
EBX[16:23] ← Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)
EBX[24:31] ← Initial APIC ID;
ECX ← Feature flags; (* See Figure 3-7. *)
EDX ← Feature flags; (* See Figure 3-8. *)
BREAK;
EAX = 2H:
EAX ← Cache and TLB information;
EBX ← Cache and TLB information;
ECX ← Cache and TLB information;
EDX ← Cache and TLB information;
BREAK;
EAX = 3H:
EAX ← Reserved;
EBX ← Reserved;
ECX ← ProcessorSerialNumber[31:0];
(* Pentium III processors only, otherwise reserved. *)
EDX ← ProcessorSerialNumber[63:32];
(* Pentium III processors only, otherwise reserved. *
BREAK
EAX = 4H:
EAX ← Deterministic Cache Parameters Leaf; (* See Table 3-8. *)
EBX ← Deterministic Cache Parameters Leaf;
ECX ← Deterministic Cache Parameters Leaf;
EDX ← Deterministic Cache Parameters Leaf;
BREAK;
EAX = 5H:
EAX ← MONITOR/MWAIT Leaf; (* See Table 3-8. *)
EBX ← MONITOR/MWAIT Leaf;
ECX ← MONITOR/MWAIT Leaf;
EDX ← MONITOR/MWAIT Leaf;
BREAK;
3-220 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
EAX = 6H:
EAX ← Thermal and Power Management Leaf; (* See Table 3-8. *)
EBX ← Thermal and Power Management Leaf;
ECX ← Thermal and Power Management Leaf;
EDX ← Thermal and Power Management Leaf;
BREAK;
EAX = 7H:
EAX ← Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)
EBX ← Structured Extended Feature Flags Enumeration Leaf;
ECX ← Structured Extended Feature Flags Enumeration Leaf;
EDX ← Structured Extended Feature Flags Enumeration Leaf;
BREAK;
EAX = 8H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX = 9H:
EAX ← Direct Cache Access Information Leaf; (* See Table 3-8. *)
EBX ← Direct Cache Access Information Leaf;
ECX ← Direct Cache Access Information Leaf;
EDX ← Direct Cache Access Information Leaf;
BREAK;
EAX = AH:
EAX ← Architectural Performance Monitoring Leaf; (* See Table 3-8. *)
EBX ← Architectural Performance Monitoring Leaf;
ECX ← Architectural Performance Monitoring Leaf;
EDX ← Architectural Performance Monitoring Leaf;
BREAK
EAX = BH:
EAX ← Extended Topology Enumeration Leaf; (* See Table 3-8. *)
EBX ← Extended Topology Enumeration Leaf;
ECX ← Extended Topology Enumeration Leaf;
EDX ← Extended Topology Enumeration Leaf;
BREAK;
EAX = CH:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX = DH:
EAX ← Processor Extended State Enumeration Leaf; (* See Table 3-8. *)
EBX ← Processor Extended State Enumeration Leaf;
ECX ← Processor Extended State Enumeration Leaf;
EDX ← Processor Extended State Enumeration Leaf;
BREAK;
EAX = EH:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
CPUID—CPU Identification
Vol. 2A 3-221
INSTRUCTION SET REFERENCE, A-L
EAX = FH:
EAX ← Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
ECX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
EDX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
BREAK;
EAX = 10H:
EAX ← Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel Resource Director Technology Allocation Enumeration Leaf;
ECX ← Intel Resource Director Technology Allocation Enumeration Leaf;
EDX ← Intel Resource Director Technology Allocation Enumeration Leaf;
BREAK;
EAX = 12H:
EAX ← Intel SGX Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel SGX Enumeration Leaf;
ECX ← Intel SGX Enumeration Leaf;
EDX ← Intel SGX Enumeration Leaf;
BREAK;
EAX = 14H:
EAX ← Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel Processor Trace Enumeration Leaf;
ECX ← Intel Processor Trace Enumeration Leaf;
EDX ← Intel Processor Trace Enumeration Leaf;
BREAK;
EAX = 15H:
EAX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)
EBX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
ECX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
EDX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
BREAK;
EAX = 16H:
EAX ← Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)
EBX ← Processor Frequency Information Enumeration Leaf;
ECX ← Processor Frequency Information Enumeration Leaf;
EDX ← Processor Frequency Information Enumeration Leaf;
BREAK;
EAX = 17H:
EAX ← System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)
EBX ← System-On-Chip Vendor Attribute Enumeration Leaf;
ECX ← System-On-Chip Vendor Attribute Enumeration Leaf;
EDX ← System-On-Chip Vendor Attribute Enumeration Leaf;
BREAK;
EAX = 80000000H:
EAX ← Highest extended function input value understood by CPUID;
EBX ← Reserved;
ECX ← Reserved;
EDX ← Reserved;
BREAK;
EAX = 80000001H:
EAX ← Reserved;
EBX ← Reserved;
ECX ← Extended Feature Bits (* See Table 3-8.*);
EDX ← Extended Feature Bits (* See Table 3-8. *);
BREAK;
3-222 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
= 80000002H:
EAX ← Processor Brand String;
EBX ← Processor Brand String, continued;
ECX ← Processor Brand String, continued;
EDX ← Processor Brand String, continued;
BREAK;
EAX = 80000003H:
EAX ← Processor Brand String, continued;
EBX ← Processor Brand String, continued;
ECX ← Processor Brand String, continued;
EDX ← Processor Brand String, continued;
BREAK;
EAX = 80000004H:
EAX ← Processor Brand String, continued;
EBX ← Processor Brand String, continued;
ECX ← Processor Brand String, continued;
EDX ← Processor Brand String, continued;
BREAK;
EAX = 80000005H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX = 80000006H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Cache information;
EDX ← Reserved = 0;
BREAK;
EAX = 80000007H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = Misc Feature Flags;
BREAK;
EAX = 80000008H:
EAX ← Reserved = Physical Address Size Information;
EBX ← Reserved = Virtual Address Size Information;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX >= 40000000H and EAX <= 4FFFFFFFH:
DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
(* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)
EAX ← Reserved; (* Information returned for highest basic information leaf. *)
EBX ← Reserved; (* Information returned for highest basic information leaf. *)
ECX ← Reserved; (* Information returned for highest basic information leaf. *)
EDX ← Reserved; (* Information returned for highest basic information leaf. *)
BREAK;
ESAC;
EAX
Flags Affected
None.
CPUID—CPU Identification
Vol. 2A 3-223
INSTRUCTION SET REFERENCE, A-L
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.
3-224 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
CRC32 — Accumulate CRC32 Value
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F2 0F 38 F0 /r
RM
Valid
Valid
Accumulate CRC32 on r/m8.
RM
Valid
N.E.
Accumulate CRC32 on r/m8.
RM
Valid
Valid
Accumulate CRC32 on r/m16.
RM
Valid
Valid
Accumulate CRC32 on r/m32.
RM
Valid
N.E.
Accumulate CRC32 on r/m8.
RM
Valid
N.E.
Accumulate CRC32 on r/m64.
CRC32 r32, r/m8
F2 REX 0F 38 F0 /r
CRC32 r32, r/m8*
F2 0F 38 F1 /r
CRC32 r32, r/m16
F2 0F 38 F1 /r
CRC32 r32, r/m32
F2 REX.W 0F 38 F0 /r
CRC32 r64, r/m8
F2 REX.W 0F 38 F1 /r
CRC32 r64, r/m64
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Starting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial
11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The
source operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If
the destination is an r64 register, then the 32-bit result is stored in the least significant double word and
00000000H is stored in the most significant double word of the r64 register.
The initial value supplied in the destination operand is a double word integer stored in the r32 register or the least
significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result
of the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new
input data in the source operand. Data contained in the source operand is processed in reflected bit order. This
means that the most significant bit of the source operand is treated as the least significant bit of the quotient, and
so on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination
operand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the
least significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.
Operation
Notes:
BIT_REFLECT64: DST[63-0] = SRC[0-63]
BIT_REFLECT32: DST[31-0] = SRC[0-31]
BIT_REFLECT16: DST[15-0] = SRC[0-15]
BIT_REFLECT8: DST[7-0] = SRC[0-7]
MOD2: Remainder from Polynomial division modulus 2
CRC32 — Accumulate CRC32 Value
Vol. 2A 3-225
INSTRUCTION SET REFERENCE, A-L
CRC32 instruction for 64-bit source operand and 64-bit destination operand:
TEMP1[63-0] BIT_REFLECT64 (SRC[63-0])
TEMP2[31-0] BIT_REFLECT32 (DEST[31-0])
TEMP3[95-0] TEMP1[63-0] « 32
TEMP4[95-0] TEMP2[31-0] « 64
TEMP5[95-0] TEMP3[95-0] XOR TEMP4[95-0]
TEMP6[31-0] TEMP5[95-0] MOD2 11EDC6F41H
DEST[31-0] BIT_REFLECT (TEMP6[31-0])
DEST[63-32] 00000000H
CRC32 instruction for 32-bit source operand and 32-bit destination operand:
TEMP1[31-0] BIT_REFLECT32 (SRC[31-0])
TEMP2[31-0] BIT_REFLECT32 (DEST[31-0])
TEMP3[63-0] TEMP1[31-0] « 32
TEMP4[63-0] TEMP2[31-0] « 32
TEMP5[63-0] TEMP3[63-0] XOR TEMP4[63-0]
TEMP6[31-0] TEMP5[63-0] MOD2 11EDC6F41H
DEST[31-0] BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 16-bit source operand and 32-bit destination operand:
TEMP1[15-0] BIT_REFLECT16 (SRC[15-0])
TEMP2[31-0] BIT_REFLECT32 (DEST[31-0])
TEMP3[47-0] TEMP1[15-0] « 32
TEMP4[47-0] TEMP2[31-0] « 16
TEMP5[47-0] TEMP3[47-0] XOR TEMP4[47-0]
TEMP6[31-0] TEMP5[47-0] MOD2 11EDC6F41H
DEST[31-0] BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 8-bit source operand and 64-bit destination operand:
TEMP1[7-0] BIT_REFLECT8(SRC[7-0])
TEMP2[31-0] BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0] TEMP1[7-0] « 32
TEMP4[39-0] TEMP2[31-0] « 8
TEMP5[39-0] TEMP3[39-0] XOR TEMP4[39-0]
TEMP6[31-0] TEMP5[39-0] MOD2 11EDC6F41H
DEST[31-0] BIT_REFLECT (TEMP6[31-0])
DEST[63-32] 00000000H
CRC32 instruction for 8-bit source operand and 32-bit destination operand:
TEMP1[7-0] BIT_REFLECT8(SRC[7-0])
TEMP2[31-0] BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0] TEMP1[7-0] « 32
TEMP4[39-0] TEMP2[31-0] « 8
TEMP5[39-0] TEMP3[39-0] XOR TEMP4[39-0]
TEMP6[31-0] TEMP5[39-0] MOD2 11EDC6F41H
DEST[31-0] BIT_REFLECT (TEMP6[31-0])
Flags Affected
None
3-226 Vol. 2A
CRC32 — Accumulate CRC32 Value
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
unsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )
unsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )
unsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )
unsinged __int64 _mm_crc32_u64( unsinged __int64 crc, unsigned __int64 data )
SIMD Floating Point Exceptions
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
Real-Address Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
Virtual 8086 Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
CRC32 — Accumulate CRC32 Value
Vol. 2A 3-227
INSTRUCTION SET REFERENCE, A-L
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point
Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F3 0F E6 /r
CVTDQ2PD xmm1, xmm2/m64
VEX.128.F3.0F.WIG E6 /r
VCVTDQ2PD xmm1, xmm2/m64
RM
V/V
AVX
VEX.256.F3.0F.WIG E6 /r
VCVTDQ2PD ymm1, xmm2/m128
RM
V/V
AVX
EVEX.128.F3.0F.W0 E6 /r
VCVTDQ2PD xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.F3.0F.W0 E6 /r
VCVTDQ2PD ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.F3.0F.W0 E6 /r
VCVTDQ2PD zmm1 {k1}{z},
ymm2/m256/m32bcst
HV
V/V
AVX512VL
AVX512F
HV
V/V
AVX512VL
AVX512F
HV
V/V
AVX512F
Description
Convert two packed signed doubleword integers from
xmm2/mem to two packed double-precision floatingpoint values in xmm1.
Convert two packed signed doubleword integers from
xmm2/mem to two packed double-precision floatingpoint values in xmm1.
Convert four packed signed doubleword integers from
xmm2/mem to four packed double-precision floatingpoint values in ymm1.
Convert 2 packed signed doubleword integers from
xmm2/m128/m32bcst to eight packed double-precision
floating-point values in xmm1 with writemask k1.
Convert 4 packed signed doubleword integers from
xmm2/m128/m32bcst to 4 packed double-precision
floating-point values in ymm1 with writemask k1.
Convert eight packed signed doubleword integers from
ymm2/m256/m32bcst to eight packed double-precision
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two,
four or eight packed double-precision floating-point values in the destination operand (the first operand).
EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit
memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand
is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX
embedded rounding is ignored.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a YMM register.
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination
operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
3-228 Vol. 2A
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
X3
SRC
DEST
X3
X2
X2
X1
X1
X0
X0
Figure 3-11. CVTDQ2PD (VEX.256 encoded version)
Operation
VCVTDQ2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
Vol. 2A 3-229
INSTRUCTION SET REFERENCE, A-L
VCVTDQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+63:i]
Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTDQ2PD (VEX.256 encoded version)
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAX_VL-1:256] 0
VCVTDQ2PD (VEX.128 encoded version)
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] 0
CVTDQ2PD (128-bit Legacy SSE version)
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);
VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);
VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);
VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);
VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);
VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);
VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);
CVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src)
CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)
3-230 Vol. 2A
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instructions, see Exceptions Type 5;
EVEX-encoded instructions, see Exceptions Type E5.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
Vol. 2A 3-231
INSTRUCTION SET REFERENCE, A-L
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point
Values
Opcode
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
0F 5B /r
CVTDQ2PS xmm1, xmm2/m128
VEX.128.0F.WIG 5B /r
VCVTDQ2PS xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.0F.WIG 5B /r
VCVTDQ2PS ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.0F.W0 5B /r
VCVTDQ2PS xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.0F.W0 5B /r
VCVTDQ2PS ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.0F.W0 5B /r
VCVTDQ2PS zmm1 {k1}{z},
zmm2/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert four packed signed doubleword integers from
xmm2/mem to four packed single-precision floatingpoint values in xmm1.
Convert four packed signed doubleword integers from
xmm2/mem to four packed single-precision floatingpoint values in xmm1.
Convert eight packed signed doubleword integers from
ymm2/mem to eight packed single-precision floatingpoint values in ymm1.
Convert four packed signed doubleword integers from
xmm2/m128/m32bcst to four packed single-precision
floating-point values in xmm1with writemask k1.
Convert eight packed signed doubleword integers from
ymm2/m256/m32bcst to eight packed single-precision
floating-point values in ymm1with writemask k1.
Convert sixteen packed signed doubleword integers
from zmm2/m512/m32bcst to sixteen packed singleprecision floating-point values in zmm1with writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen
packed single-precision floating-point values in the destination operand.
EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
3-232 Vol. 2A
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTDQ2PS (EVEX encoded versions) when SRC operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
; refer to Table 2-4 in the Intel® Architecture Instruction Set Extensions Programming Reference
ELSE
SET_RM(MXCSR.RM);
; refer to Table 2-4 in the Intel® Architecture Instruction Set Extensions Programming Reference
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+31:i]
Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
Vol. 2A 3-233
INSTRUCTION SET REFERENCE, A-L
VCVTDQ2PS (VEX.256 encoded version)
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)
DEST[159:128] Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])
DEST[191:160] Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])
DEST[223:192] Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])
DEST[255:224] Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)
DEST[MAX_VL-1:256] 0
VCVTDQ2PS (VEX.128 encoded version)
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] 0
CVTDQ2PS (128-bit Legacy SSE version)
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);
VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);
VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);
VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);
VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);
CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)
CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)
SIMD Floating-Point Exceptions
Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-234 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword
Integers
Opcode
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F E6 /r
CVTPD2DQ xmm1, xmm2/m128
VEX.128.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1, ymm2/m256
RM
V/V
AVX
EVEX.128.F2.0F.W1 E6 /r
VCVTPD2DQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.F2.0F.W1 E6 /r
VCVTPD2DQ xmm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.F2.0F.W1 E6 /r
VCVTPD2DQ ymm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1.
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1.
Convert four packed double-precision floating-point
values in ymm2/mem to four signed doubleword
integers in xmm1.
Convert two packed double-precision floating-point
values in xmm2/m128/m64bcst to two signed
doubleword integers in xmm1 subject to writemask k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four signed
doubleword integers in xmm1 subject to writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight signed
doubleword integers in ymm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed double-precision floating-point values in the source operand (second operand) to packed signed
doubleword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256/128/64) of the corresponding destination are
zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits
(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-235
INSTRUCTION SET REFERENCE, A-L
SRC
DEST
X3
X2
0
X1
X3
X0
X2
X1
X0
Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)
Operation
VCVTPD2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
3-236 Vol. 2A
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
VCVTPD2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
ELSE
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
VCVTPD2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[95:64] Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])
DEST[127:96] Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)
DEST[MAX_VL-1:128]0
VCVTPD2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[MAX_VL-1:64]0
CVTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[127:64] 0
DEST[MAX_VL-1:128] (unmodified)
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-237
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);
VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);
VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);
VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);
VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)
CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Exceptions Type 2; additionally
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-238 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
66 0F 2D /r
RM
Valid
Valid
Convert two packed double-precision floatingpoint values from xmm/m128 to two packed
signed doubleword integers in mm.
CVTPD2PI mm, xmm/m128
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed double-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid
exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);
DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPD1PI:
__m64 _mm_cvtpd_pi32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers
Vol. 2A 3-239
INSTRUCTION SET REFERENCE, A-L
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5A /r
CVTPD2PS xmm1, xmm2/m128
VEX.128.66.0F.WIG 5A /r
VCVTPD2PS xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.66.0F.WIG 5A /r
VCVTPD2PS xmm1, ymm2/m256
RM
V/V
AVX
EVEX.128.66.0F.W1 5A /r
VCVTPD2PS xmm1 {k1}{z},
xmm2/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 5A /r
VCVTPD2PS xmm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F.W1 5A /r
VCVTPD2PS ymm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point
values in xmm2/mem to two single-precision
floating-point values in xmm1.
Convert two packed double-precision floating-point
values in xmm2/mem to two single-precision
floating-point values in xmm1.
Convert four packed double-precision floating-point
values in ymm2/mem to four single-precision
floating-point values in xmm1.
Convert two packed double-precision floating-point
values in xmm2/m128/m64bcst to two singleprecision floating-point values in xmm1with
writemask k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four singleprecision floating-point values in xmm1with
writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight singleprecision floating-point values in ymm1with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed double-precision floating-point values in the source operand (second operand)
to two, four or eight packed single-precision floating-point values in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
YMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAX_VL1:256/128/64) of the corresponding destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper Bits
(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
3-240 Vol. 2A
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
SRC
DEST
X3
X2
0
X1
X3
X0
X2
X1
X0
Figure 3-13. VCVTPD2PS (VEX.256 encoded version)
Operation
VCVTPD2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
Vol. 2A 3-241
INSTRUCTION SET REFERENCE, A-L
VCVTPD2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+31:i] Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
VCVTPD2PS (VEX.256 encoded version)
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[95:64] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])
DEST[127:96] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)
DEST[MAX_VL-1:128] 0
VCVTPD2PS (VEX.128 encoded version)
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[MAX_VL-1:64] 0
CVTPD2PS (128-bit Legacy SSE version)
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[127:64] 0
DEST[MAX_VL-1:128] (unmodified)
3-242 Vol. 2A
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);
VCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);
VCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);
VCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);
VCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);
VCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);
VCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);
VCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);
VCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);
VCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);
VCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)
CVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision, Underflow, Overflow, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
Vol. 2A 3-243
INSTRUCTION SET REFERENCE, A-L
CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
66 0F 2A /r
RM
Valid
Valid
Convert two packed signed doubleword
integers from mm/mem64 to two packed
double-precision floating-point values in xmm.
CVTPI2PD xmm, mm/m64*
NOTES:
*Operation is different for different operand sets; see the Description section.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed signed doubleword integers in the source operand (second operand) to two packed doubleprecision floating-point values in the destination operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
XMM register. In addition, depending on the operand configuration:
•
For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that
is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this
instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before
the CVTPI2PD instruction is executed.
•
For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take
x87 FPU exceptions.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[127:64] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPI2PD:
__m128d _mm_cvtpi32_pd(__m64 a)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 22-6, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception,” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
3-244 Vol. 2A
CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values
INSTRUCTION SET REFERENCE, A-L
CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 2A /r
RM
Valid
Valid
Convert two signed doubleword integers
from mm/m64 to two single-precision
floating-point values in xmm.
CVTPI2PS xmm, mm/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed signed doubleword integers in the source operand (second operand) to two packed singleprecision floating-point values in the destination operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
XMM register. The results are stored in the low quadword of the destination operand, and the high quadword
remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
DEST[63:32] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);
(* High quadword of destination unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
CVTPI2PS:
__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
SIMD Floating-Point Exceptions
Precision
Other Exceptions
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values
Vol. 2A 3-245
INSTRUCTION SET REFERENCE, A-L
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed
Doubleword Integer Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5B /r
CVTPS2DQ xmm1, xmm2/m128
VEX.128.66.0F.WIG 5B /r
VCVTPS2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.66.0F.WIG 5B /r
VCVTPS2DQ ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.66.0F.W0 5B /r
VCVTPS2DQ xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.66.0F.W0 5B /r
VCVTPS2DQ ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.66.0F.W0 5B /r
VCVTPS2DQ zmm1 {k1}{z},
zmm2/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert four packed single-precision floating-point values
from xmm2/mem to four packed signed doubleword
values in xmm1.
Convert four packed single-precision floating-point values
from xmm2/mem to four packed signed doubleword
values in xmm1.
Convert eight packed single-precision floating-point values
from ymm2/mem to eight packed signed doubleword
values in ymm1.
Convert four packed single precision floating-point values
from xmm2/m128/m32bcst to four packed signed
doubleword values in xmm1 subject to writemask k1.
Convert eight packed single precision floating-point values
from ymm2/m256/m32bcst to eight packed signed
doubleword values in ymm1 subject to writemask k1.
Convert sixteen packed single-precision floating-point
values from zmm2/m512/m32bcst to sixteen packed
signed doubleword values in zmm1 subject to writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or
sixteen signed doubleword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX encoded versions: The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
3-246 Vol. 2A
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTPS2DQ (encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPS2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO 15
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
ELSE
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
Vol. 2A 3-247
INSTRUCTION SET REFERENCE, A-L
VCVTPS2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)
DEST[159:128] Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])
DEST[191:160] Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])
DEST[223:192] Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])
DEST[255:224] Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])
VCVTPS2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[MAX_VL-1:128] 0
CVTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);
VCVTPS2DQ __m512i _mm512_mask_cvtps_epi32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);
VCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);
VCVTPS2DQ __m512i _mm512_mask_cvt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);
VCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);
VCVTPS2DQ __m128i _mm_mask_cvtps_epi32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);
VCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)
CVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-248 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
0F 5A /r
CVTPS2PD xmm1, xmm2/m64
VEX.128.0F.WIG 5A /r
VCVTPS2PD xmm1, xmm2/m64
RM
V/V
AVX
VEX.256.0F.WIG 5A /r
VCVTPS2PD ymm1, xmm2/m128
RM
V/V
AVX
EVEX.128.0F.W0 5A /r
VCVTPS2PD xmm1 {k1}{z},
xmm2/m64/m32bcst
EVEX.256.0F.W0 5A /r
VCVTPS2PD ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.0F.W0 5A /r
VCVTPS2PD zmm1 {k1}{z},
ymm2/m256/m32bcst{sae}
HV
V/V
AVX512VL
AVX512F
HV
V/V
AVX512VL
HV
V/V
AVX512F
Description
Convert two packed single-precision floating-point values in
xmm2/m64 to two packed double-precision floating-point
values in xmm1.
Convert two packed single-precision floating-point values in
xmm2/m64 to two packed double-precision floating-point
values in xmm1.
Convert four packed single-precision floating-point values
in xmm2/m128 to four packed double-precision floatingpoint values in ymm1.
Convert two packed single-precision floating-point values in
xmm2/m64/m32bcst to packed double-precision floatingpoint values in xmm1 with writemask k1.
Convert four packed single-precision floating-point values
in xmm2/m128/m32bcst to packed double-precision
floating-point values in ymm1 with writemask k1.
Convert eight packed single-precision floating-point values
in ymm2/m256/b32bcst to eight packed double-precision
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed single-precision floating-point values in the source operand (second operand)
to two, four or eight packed double-precision floating-point values in the destination operand (first operand).
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory
location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination
operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
Vol. 2A 3-249
INSTRUCTION SET REFERENCE, A-L
X3
SRC
DEST
X3
X2
X2
X1
X1
X0
X0
Figure 3-14. CVTPS2PD (VEX.256 encoded version)
Operation
VCVTPS2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPS2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+63:i]
Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])
FI;
ELSE
3-250 Vol. 2A
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPS2PD (VEX.256 encoded version)
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAX_VL-1:256] 0
VCVTPS2PD (VEX.128 encoded version)
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] 0
CVTPS2PD (128-bit Legacy SSE version)
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);
VCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);
VCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);
VCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);
VCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);
VCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd( __mmask8 k, __m256 a, int sae);
VCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);
VCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);
VCVTPS2PD __m128d _mm_mask_cvtps_pd( __m128d s, __mmask8 k, __m128 a);
VCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);
VCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)
CVTPS2PD __m128d _mm_cvtps_pd (__m128 a)
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
Vol. 2A 3-251
INSTRUCTION SET REFERENCE, A-L
CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 2D /r
RM
Valid
Valid
Convert two packed single-precision floatingpoint values from xmm/m64 to two packed
signed doubleword integers in mm.
CVTPS2PI mm, xmm/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed single-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register. When the source operand is an XMM register, the two single-precision floating-point values are
contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded
according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum
signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer
is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floatingpoint exception is pending, the exception is handled before the CVTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPS2PI:
__m64 _mm_cvtps_pi32(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
3-252 Vol. 2A
CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers
INSTRUCTION SET REFERENCE, A-L
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
Opcode/
Instruction
Op /
En
F2 0F 2D /r
CVTSD2SI r32, xmm1/m64
F2 REX.W 0F 2D /r
CVTSD2SI r64, xmm1/m64
VEX.128.F2.0F.W0 2D /r
VCVTSD2SI r32, xmm1/m64
VEX.128.F2.0F.W1 2D /r
VCVTSD2SI r64, xmm1/m64
EVEX.LIG.F2.0F.W0 2D /r
VCVTSD2SI r32, xmm1/m64{er}
EVEX.LIG.F2.0F.W1 2D /r
VCVTSD2SI r64, xmm1/m64{er}
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
RM
V/N.E.
SSE2
RM
V/V
AVX
RM
V/N.E.1
AVX
T1F
V/V
AVX512F
T1F
V/N.E.1
AVX512F
Description
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer r32.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer signextended into r64.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer r32.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer signextended into r64.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer r32.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer signextended into r64.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a double-precision floating-point value in the source operand (the second operand) to a signed doubleword integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit
memory location. The destination operand is a general-purpose register. When the source operand is an XMM
register, the double-precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000_00000000H) is returned.
Legacy SSE instruction: Use of the REX.W prefix promotes the instruction to produce 64-bit data in 64-bit mode.
See the summary chart at the beginning of this section for encoding data and limits.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
Vol. 2A 3-253
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSD2SI (EVEX encoded version)
IF SRC *is register* AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
ELSE
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI
(V)CVTSD2SI
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
ELSE
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SI int _mm_cvtsd_i32(__m128d);
VCVTSD2SI int _mm_cvt_roundsd_i32(__m128d, int r);
VCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);
VCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);
CVTSD2SI __int64 _mm_cvtsd_si64(__m128d);
CVTSD2SI int _mm_cvtsd_si32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD
3-254 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
INSTRUCTION SET REFERENCE, A-L
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision
Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 5A /r
CVTSD2SS xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 5A /r
VCVTSD2SS xmm1,xmm2,
xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 5A /r
VCVTSD2SS xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Convert one double-precision floating-point value in
xmm2/m64 to one single-precision floating-point value
in xmm1.
Convert one double-precision floating-point value in
xmm3/m64 to one single-precision floating-point value
and merge with high bits in xmm2.
Convert one double-precision floating-point value in
xmm3/m64 to one single-precision floating-point value
and merge with high bits in xmm2 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a double-precision floating-point value in the “convert-from” source operand (the second operand in
SSE2 version, otherwise the third operand) to a single-precision floating-point value in the destination operand.
When the “convert-from” operand is an XMM register, the double-precision floating-point value is contained in the
low quadword of the register. The result is stored in the low doubleword of the destination operand. When the
conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or
memory location. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged. The destination operand is an XMM register.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM
register or a 64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of
the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the
writemask.
Software should ensure VCVTSD2SS is encoded with VEX.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
Vol. 2A 3-255
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSD2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VCVTSD2SS (VEX.128 encoded version)
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
CVTSD2SS (128-bit Legacy SSE version)
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);
(* DEST[MAX_VL-1:32] Unmodified *)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SS __m128 _mm_mask_cvtsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b);
VCVTSD2SS __m128 _mm_maskz_cvtsd_ss( __mmask8 k, __m128 a,__m128d b);
VCVTSD2SS __m128 _mm_cvt_roundsd_ss(__m128 a, __m128d b, int r);
VCVTSD2SS __m128 _mm_mask_cvt_roundsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b, int r);
VCVTSD2SS __m128 _mm_maskz_cvt_roundsd_ss( __mmask8 k, __m128 a,__m128d b, int r);
CVTSD2SS __m128_mm_cvtsd_ss(__m128 a, __m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
3-256 Vol. 2A
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 2A /r
CVTSI2SD xmm1, r32/m32
F2 REX.W 0F 2A /r
CVTSI2SD xmm1, r/m64
RM
V/N.E.
SSE2
VEX.NDS.128.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m32
RVM
V/V
AVX
VEX.NDS.128.F2.0F.W1 2A /r
VCVTSI2SD xmm1, xmm2, r/m64
RVM
V/N.E.1
AVX
EVEX.NDS.LIG.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m32
T1S
V/V
AVX512F
EVEX.NDS.LIG.F2.0F.W1 2A /r
VCVTSI2SD xmm1, xmm2, r/m64{er}
T1S
V/N.E.1
AVX512F
Description
Convert one signed doubleword integer from
r32/m32 to one double-precision floating-point
value in xmm1.
Convert one signed quadword integer from r/m64
to one double-precision floating-point value in
xmm1.
Convert one signed doubleword integer from
r/m32 to one double-precision floating-point
value in xmm1.
Convert one signed quadword integer from r/m64
to one double-precision floating-point value in
xmm1.
Convert one signed doubleword integer from
r/m32 to one double-precision floating-point
value in xmm1.
Convert one signed quadword integer from r/m64
to one double-precision floating-point value in
xmm1.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”
source operand to a double-precision floating-point value in the destination operand. The result is stored in the low
quadword of the destination operand, and the high quadword left unchanged. When conversion is inexact, the
value returned is rounded according to the rounding control bits in the MXCSR register.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers.
128-bit Legacy SSE version: Use of the REX.W prefix promotes the instruction to 64-bit operands. The “convertfrom” source operand (the second operand) is a general-purpose register or memory location. The destination is
an XMM register Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a generalpurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64)
of the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.
VEX.W1 and EVEX.W1 versions: promotes the instruction to use 64-bit input value in 64-bit mode.
Software should ensure VCVTSI2SD is encoded with VEX.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
Vol. 2A 3-257
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSI2SD (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VCVTSI2SD (VEX.128 encoded version)
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
CVTSI2SD
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SD __m128d _mm_cvti32_sd(__m128d s, int a);
VCVTSI2SD __m128d _mm_cvt_roundi32_sd(__m128d s, int a, int r);
VCVTSI2SD __m128d _mm_cvti64_sd(__m128d s, __int64 a);
VCVTSI2SD __m128d _mm_cvt_roundi64_sd(__m128d s, __int64 a, int r);
CVTSI2SD __m128d _mm_cvtsi64_sd(__m128d s, __int64 a);
CVTSI2SD __m128d_mm_cvtsi32_sd(__m128d a, int b)
SIMD Floating-Point Exceptions
Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3 if W1, else Type 5.
EVEX-encoded instructions, see Exceptions Type E3NF if W1, else Type E10NF.
3-258 Vol. 2A
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 2A /r
CVTSI2SS xmm1, r/m32
F3 REX.W 0F 2A /r
CVTSI2SS xmm1, r/m64
VEX.NDS.128.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m32
VEX.NDS.128.F3.0F.W1 2A /r
VCVTSI2SS xmm1, xmm2, r/m64
EVEX.NDS.LIG.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m32{er}
EVEX.NDS.LIG.F3.0F.W1 2A /r
VCVTSI2SS xmm1, xmm2, r/m64{er}
RM
V/N.E.
SSE
RVM
V/V
AVX
RVM
V/N.E.1
AVX
T1S
V/V
AVX512F
T1S
V/N.E.1
AVX512F
Description
Convert one signed doubleword integer from r/m32
to one single-precision floating-point value in xmm1.
Convert one signed quadword integer from r/m64
to one single-precision floating-point value in xmm1.
Convert one signed doubleword integer from r/m32
to one single-precision floating-point value in xmm1.
Convert one signed quadword integer from r/m64
to one single-precision floating-point value in xmm1.
Convert one signed doubleword integer from r/m32
to one single-precision floating-point value in xmm1.
Convert one signed quadword integer from r/m64
to one single-precision floating-point value in xmm1.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”
source operand to a single-precision floating-point value in the destination operand (first operand). The “convertfrom” source operand can be a general-purpose register or a memory location. The destination operand is an XMM
register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords
are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register or the embedded rounding control bits.
128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input
value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location.
Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a generalpurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32)
of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the
writemask.
Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
Vol. 2A 3-259
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSI2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VCVTSI2SS (VEX.128 encoded version)
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
CVTSI2SS (128-bit Legacy SSE version)
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);
VCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);
VCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a);
VCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);
CVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);
CVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3NF.
3-260 Vol. 2A
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision
Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F3 0F 5A /r
CVTSS2SD xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 5A /r
VCVTSS2SD xmm1, xmm2,
xmm3/m32
EVEX.NDS.LIG.F3.0F.W0 5A /r
VCVTSS2SD xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Convert one single-precision floating-point value in
xmm2/m32 to one double-precision floating-point value
in xmm1.
Convert one single-precision floating-point value in
xmm3/m32 to one double-precision floating-point value
and merge with high bits of xmm2.
Convert one single-precision floating-point value in
xmm3/m32 to one double-precision floating-point value
and merge with high bits of xmm2 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a single-precision floating-point value in the “convert-from” source operand to a double-precision
floating-point value in the destination operand. When the “convert-from” source operand is an XMM register, the
single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the
low quadword of the destination operand.
128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or
memory location. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged. The destination operand is an XMM register.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM
register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of
the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
VCVTSS2SD (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] = 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
Vol. 2A 3-261
INSTRUCTION SET REFERENCE, A-L
VCVTSS2SD (VEX.128 encoded version)
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
CVTSS2SD (128-bit Legacy SSE version)
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);
VCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);
VCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);
VCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);
VCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);
CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
3-262 Vol. 2A
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 2D /r
CVTSS2SI r32, xmm1/m32
F3 REX.W 0F 2D /r
CVTSS2SI r64, xmm1/m32
VEX.128.F3.0F.W0 2D /r
VCVTSS2SI r32, xmm1/m32
VEX.128.F3.0F.W1 2D /r
VCVTSS2SI r64, xmm1/m32
EVEX.LIG.F3.0F.W0 2D /r
VCVTSS2SI r32, xmm1/m32{er}
EVEX.LIG.F3.0F.W1 2D /r
VCVTSS2SI r64, xmm1/m32{er}
RM
V/N.E.
SSE
RM
V/V
AVX
RM
V/N.E.1
AVX
T1F
V/V
AVX512F
T1F
V/N.E.1
AVX512F
Description
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).
The source operand can be an XMM register or a memory location. The destination operand is a general-purpose
register. When the source operand is an XMM register, the single-precision floating-point value is contained in the
low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data.
See the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
Vol. 2A 3-263
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSS2SI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;
(V)CVTSS2SI (Legacy and VEX.128 encoded version)
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SI int _mm_cvtss_i32( __m128 a);
VCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);
VCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);
VCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
3-264 Vol. 2A
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
INSTRUCTION SET REFERENCE, A-L
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Doubleword Integers
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F E6 /r
CVTTPD2DQ xmm1, xmm2/m128
VEX.128.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1, ymm2/m256
RM
V/V
AVX
EVEX.128.66.0F.W1 E6 /r
VCVTTPD2DQ xmm1 {k1}{z},
xmm2/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 E6 /r
VCVTTPD2DQ xmm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F.W1 E6 /r
VCVTTPD2DQ ymm1 {k1}{z},
zmm2/m512/m64bcst{sae}
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1 using truncation.
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1 using truncation.
Convert four packed double-precision floating-point
values in ymm2/mem to four signed doubleword
integers in xmm1 using truncation.
Convert two packed double-precision floating-point
values in xmm2/m128/m64bcst to two signed
doubleword integers in xmm1 using truncation subject
to writemask k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four signed
doubleword integers in xmm1 using truncation subject
to writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight signed
doubleword integers in ymm1 using truncation subject
to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed double-precision floating-point values in the source operand (second operand)
to two, four or eight packed signed doubleword integers in the destination operand (first operand).
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of
the corresponding destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-265
INSTRUCTION SET REFERENCE, A-L
SRC
DEST
X3
X2
0
X1
X3
X0
X2
X1
X0
Figure 3-15. VCVTTPD2DQ (VEX.256 encoded version)
Operation
VCVTTPD2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
3-266 Vol. 2A
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
VCVTTPD2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
ELSE
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
VCVTTPD2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[95:64] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[191:128])
DEST[127:96] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[255:192)
DEST[MAX_VL-1:128]0
VCVTTPD2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[MAX_VL-1:64]0
CVTTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[127:64] 0
DEST[MAX_VL-1:128] (unmodified)
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-267
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2DQ __m256i _mm512_cvttpd_epi32( __m512d a);
VCVTTPD2DQ __m256i _mm512_mask_cvttpd_epi32( __m256i s, __mmask8 k, __m512d a);
VCVTTPD2DQ __m256i _mm512_maskz_cvttpd_epi32( __mmask8 k, __m512d a);
VCVTTPD2DQ __m256i _mm512_cvtt_roundpd_epi32( __m512d a, int sae);
VCVTTPD2DQ __m256i _mm512_mask_cvtt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2DQ __m256i _mm512_maskz_cvtt_roundpd_epi32( __mmask8 k, __m512d a, int sae);
VCVTTPD2DQ __m128i _mm256_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m256d a);
VCVTTPD2DQ __m128i _mm256_maskz_cvttpd_epi32( __mmask8 k, __m256d a);
VCVTTPD2DQ __m128i _mm_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2DQ __m128i _mm_maskz_cvttpd_epi32( __mmask8 k, __m128d a);
VCVTTPD2DQ __m128i _mm256_cvttpd_epi32 (__m256d src);
CVTTPD2DQ __m128i _mm_cvttpd_epi32 (__m128d src);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-268 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword
Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
66 0F 2C /r
RM
Valid
Valid
Convert two packer double-precision floatingpoint values from xmm/m128 to two packed
signed doubleword integers in mm using
truncation.
CVTTPD2PI mm, xmm/m128
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed double-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register
or a 128-bit memory location. The destination operand is an MMX technology register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);
DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32_
Truncate(SRC[127:64]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTTPD1PI:
__m64 _mm_cvttpd_pi32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Mode Exceptions
See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers
Vol. 2A 3-269
INSTRUCTION SET REFERENCE, A-L
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed
Signed Doubleword Integer Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F3 0F 5B /r
CVTTPS2DQ xmm1, xmm2/m128
VEX.128.F3.0F.WIG 5B /r
VCVTTPS2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.F3.0F.WIG 5B /r
VCVTTPS2DQ ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.F3.0F.W0 5B /r
VCVTTPS2DQ xmm1 {k1}{z},
xmm2/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F.W0 5B /r
VCVTTPS2DQ ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F.W0 5B /r
VCVTTPS2DQ zmm1 {k1}{z},
zmm2/m512/m32bcst {sae}
FV
V/V
AVX512F
Description
Convert four packed single-precision floating-point
values from xmm2/mem to four packed signed
doubleword values in xmm1 using truncation.
Convert four packed single-precision floating-point
values from xmm2/mem to four packed signed
doubleword values in xmm1 using truncation.
Convert eight packed single-precision floating-point
values from ymm2/mem to eight packed signed
doubleword values in ymm1 using truncation.
Convert four packed single precision floating-point
values from xmm2/m128/m32bcst to four packed
signed doubleword values in xmm1 using truncation
subject to writemask k1.
Convert eight packed single precision floating-point
values from ymm2/m256/m32bcst to eight packed
signed doubleword values in ymm1 using truncation
subject to writemask k1.
Convert sixteen packed single-precision floating-point
values from zmm2/m512/m32bcst to sixteen packed
signed doubleword values in zmm1 using truncation
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or
sixteen signed doubleword integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or
a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
3-270 Vol. 2A
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTTPS2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTTPS2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO 15
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
ELSE
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTTPS2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96)
DEST[159:128] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])
DEST[191:160] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])
DEST[223:192] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])
DEST[255:224] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
Vol. 2A 3-271
INSTRUCTION SET REFERENCE, A-L
VCVTTPS2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[MAX_VL-1:128] 0
CVTTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2DQ __m512i _mm512_cvttps_epi32( __m512 a);
VCVTTPS2DQ __m512i _mm512_mask_cvttps_epi32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_maskz_cvttps_epi32( __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_cvtt_roundps_epi32( __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_mask_cvtt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_maskz_cvtt_roundps_epi32( __mmask16 k, __m512 a, int sae);
VCVTTPS2DQ __m256i _mm256_mask_cvttps_epi32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2DQ __m256i _mm256_maskz_cvttps_epi32( __mmask8 k, __m256 a);
VCVTTPS2DQ __m128i _mm_mask_cvttps_epi32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2DQ __m128i _mm_maskz_cvttps_epi32( __mmask8 k, __m128 a);
VCVTTPS2DQ __m256i _mm256_cvttps_epi32 (__m256 a)
CVTTPS2DQ __m128i _mm_cvttps_epi32 (__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2; additionally
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-272 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword
Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 2C /r
RM
Valid
Valid
Convert two single-precision floating-point
values from xmm/m64 to two signed
doubleword signed integers in mm using
truncation.
CVTTPS2PI mm, xmm/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed single-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register
or a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is
an XMM register, the two single-precision floating-point values are contained in the low quadword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTTPS2PI:
__m64 _mm_cvttps_pi32(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers
Vol. 2A 3-273
INSTRUCTION SET REFERENCE, A-L
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed
Integer
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 2C /r
CVTTSD2SI r32, xmm1/m64
F2 REX.W 0F 2C /r
CVTTSD2SI r64, xmm1/m64
RM
V/N.E.
SSE2
VEX.128.F2.0F.W0 2C /r
VCVTTSD2SI r32, xmm1/m64
RM
V/V
AVX
VEX.128.F2.0F.W1 2C /r
VCVTTSD2SI r64, xmm1/m64
T1F
V/N.E.1
AVX
EVEX.LIG.F2.0F.W0 2C /r
VCVTTSD2SI r32, xmm1/m64{sae}
T1F
V/V
AVX512F
EVEX.LIG.F2.0F.W1 2C /r
VCVTTSD2SI r64, xmm1/m64{sae}
T1F
V/N.E.1
AVX512F
Description
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer in r32
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer in r64
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer in r32
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer in r64
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer in r32
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer in r64
using truncation.
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a double-precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).
The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general
purpose register. When the source operand is an XMM register, the double-precision floating-point value is
contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000_00000000H) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See
the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
3-274 Vol. 2A
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer
INSTRUCTION SET REFERENCE, A-L
Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may
encounter unpredictable behavior across different processor generations.
Operation
(V)CVTTSD2SI (All versions)
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
ELSE
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2SI int _mm_cvttsd_i32( __m128d a);
VCVTTSD2SI int _mm_cvtt_roundsd_i32( __m128d a, int sae);
VCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);
VCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);
CVTTSD2SI int _mm_cvttsd_si32( __m128d a);
CVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer
Vol. 2A 3-275
INSTRUCTION SET REFERENCE, A-L
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 2C /r
CVTTSS2SI r32, xmm1/m32
F3 REX.W 0F 2C /r
CVTTSS2SI r64, xmm1/m32
RM
V/N.E.
SSE
VEX.128.F3.0F.W0 2C /r
VCVTTSS2SI r32, xmm1/m32
RM
V/V
AVX
VEX.128.F3.0F.W1 2C /r
VCVTTSS2SI r64, xmm1/m32
RM
V/N.E.1
AVX
EVEX.LIG.F3.0F.W0 2C /r
VCVTTSS2SI r32, xmm1/m32{sae}
T1F
V/V
AVX512F
EVEX.LIG.F3.0F.W1 2C /r
VCVTTSS2SI r64, xmm1/m32{sae}
T1F
V/N.E.1
AVX512F
Description
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64
using truncation.
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword
integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The
source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose
register. When the source operand is an XMM register, the single-precision floating-point value is contained in the
low doubleword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked,
the indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See
the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may
encounter unpredictable behavior across different processor generations.
3-276 Vol. 2A
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer
INSTRUCTION SET REFERENCE, A-L
Operation
(V)CVTTSS2SI (All versions)
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
ELSE
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSS2SI int _mm_cvttss_i32( __m128 a);
VCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);
VCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);
VCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);
CVTTSS2SI int _mm_cvttss_si32( __m128 a);
CVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer
Vol. 2A 3-277
INSTRUCTION SET REFERENCE, A-L
CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
99
CWD
NP
Valid
Valid
DX:AX ← sign-extend of AX.
99
CDQ
NP
Valid
Valid
EDX:EAX ← sign-extend of EAX.
REX.W + 99
CQO
NP
Valid
N.E.
RDX:RAX← sign-extend of RAX.
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Instruction Operand Encoding
Description
Doubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign
extension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction
copies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction
copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruction (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position
in the RDX register.
The CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ
instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO
instruction can be used to produce a double quadword dividend from a quadword before a quadword division.
The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the
operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers
may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these
mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the
size of values to be converted, regardless of the mnemonic used.
In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same
opcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF OperandSize = 16 (* CWD instruction *)
THEN
DX ← SignExtend(AX);
ELSE IF OperandSize = 32 (* CDQ instruction *)
EDX ← SignExtend(EAX); FI;
ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)
RDX ← SignExtend(RAX); FI;
FI;
Flags Affected
None
Exceptions (All Operating Modes)
#UD
3-278 Vol. 2A
If the LOCK prefix is used.
CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword
INSTRUCTION SET REFERENCE, A-L
DAA—Decimal Adjust AL after Addition
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
27
DAA
NP
Invalid
Valid
Decimal adjust AL after addition.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and
destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts
the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the
CF and AF flags are set accordingly.
This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
old_AL ← AL;
old_CF ← CF;
CF ← 0;
IF (((AL AND 0FH) > 9) or AF = 1)
THEN
AL ← AL + 6;
CF ← old_CF or (Carry from AL ← AL + 6);
AF ← 1;
ELSE
AF ← 0;
FI;
IF ((old_AL > 99H) or (old_CF = 1))
THEN
AL ← AL + 60H;
CF ← 1;
ELSE
CF ← 0;
FI;
FI;
Example
ADD
DAA
DAA
AL, BL
Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX
After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000
Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000
After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111
Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000
After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101
DAA—Decimal Adjust AL after Addition
Vol. 2A 3-279
INSTRUCTION SET REFERENCE, A-L
Flags Affected
The CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see
the “Operation” section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
64-Bit Mode Exceptions
#UD
3-280 Vol. 2A
If in 64-bit mode.
DAA—Decimal Adjust AL after Addition
INSTRUCTION SET REFERENCE, A-L
DAS—Decimal Adjust AL after Subtraction
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
2F
DAS
NP
Invalid
Valid
Decimal adjust AL after subtraction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the
implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that
subtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL
register. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD
result. If a decimal borrow is detected, the CF and AF flags are set accordingly.
This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
old_AL ← AL;
old_CF ← CF;
CF ← 0;
IF (((AL AND 0FH) > 9) or AF = 1)
THEN
AL ← AL - 6;
CF ← old_CF or (Borrow from AL ← AL − 6);
AF ← 1;
ELSE
AF ← 0;
FI;
IF ((old_AL > 99H) or (old_CF = 1))
THEN
AL ← AL − 60H;
CF ← 1;
FI;
FI;
Example
SUB
AL, BL
DAA
Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX
After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111
Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111
After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111
Flags Affected
The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result
(see the “Operation” section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
DAS—Decimal Adjust AL after Subtraction
Vol. 2A 3-281
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
64-Bit Mode Exceptions
#UD
3-282 Vol. 2A
If in 64-bit mode.
DAS—Decimal Adjust AL after Subtraction
INSTRUCTION SET REFERENCE, A-L
DEC—Decrement by 1
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
FE /1
DEC r/m8
M
Valid
Valid
Decrement r/m8 by 1.
REX + FE /1
DEC r/m8
*
M
Valid
N.E.
Decrement r/m8 by 1.
FF /1
DEC r/m16
M
Valid
Valid
Decrement r/m16 by 1.
FF /1
DEC r/m32
M
Valid
Valid
Decrement r/m32 by 1.
REX.W + FF /1
DEC r/m64
M
Valid
N.E.
Decrement r/m64 by 1.
48+rw
DEC r16
O
N.E.
Valid
Decrement r16 by 1.
48+rd
DEC r32
O
N.E.
Valid
Decrement r32 by 1.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r, w)
NA
NA
NA
O
opcode + rd (r, w)
NA
NA
NA
Description
Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be
a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.
(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of
1.)
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes).
Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to
additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.
See the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← DEST – 1;
Flags Affected
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination operand is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
DEC—Decrement by 1
Vol. 2A 3-283
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-284 Vol. 2A
DEC—Decrement by 1
INSTRUCTION SET REFERENCE, A-L
DIV—Unsigned Divide
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F6 /6
DIV r/m8
M
Valid
Valid
Unsigned divide AX by r/m8, with result
stored in AL ← Quotient, AH ← Remainder.
REX + F6 /6
DIV r/m8*
M
Valid
N.E.
Unsigned divide AX by r/m8, with result
stored in AL ← Quotient, AH ← Remainder.
F7 /6
DIV r/m16
M
Valid
Valid
Unsigned divide DX:AX by r/m16, with result
stored in AX ← Quotient, DX ← Remainder.
F7 /6
DIV r/m32
M
Valid
Valid
Unsigned divide EDX:EAX by r/m32, with
result stored in EAX ← Quotient, EDX ←
Remainder.
REX.W + F7 /6
DIV r/m64
M
Valid
N.E.
Unsigned divide RDX:RAX by r/m64, with
result stored in RAX ← Quotient, RDX ←
Remainder.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand
(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can
be a general-purpose register or a memory location. The action of this instruction depends on the operand size
(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.
Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is
applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in
RAX, the remainder in RDX.
See the summary chart at the beginning of this section for encoding data and limits. See Table 3-15.
Table 3-15. DIV Action
Operand Size
Dividend
Divisor
Quotient
Remainder
Maximum
Quotient
Word/byte
AX
r/m8
AL
AH
255
Doubleword/word
DX:AX
r/m16
AX
DX
65,535
Quadword/doubleword
EDX:EAX
r/m32
EAX
EDX
232 − 1
Doublequadword/
RDX:RAX
r/m64
RAX
RDX
264 − 1
quadword
DIV—Unsigned Divide
Vol. 2A 3-285
INSTRUCTION SET REFERENCE, A-L
Operation
IF SRC = 0
THEN #DE; FI; (* Divide Error *)
IF OperandSize = 8 (* Word/Byte Operation *)
THEN
temp ← AX / SRC;
IF temp > FFH
THEN #DE; (* Divide error *)
ELSE
AL ← temp;
AH ← AX MOD SRC;
FI;
ELSE IF OperandSize = 16 (* Doubleword/word operation *)
THEN
temp ← DX:AX / SRC;
IF temp > FFFFH
THEN #DE; (* Divide error *)
ELSE
AX ← temp;
DX ← DX:AX MOD SRC;
FI;
FI;
ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)
THEN
temp ← EDX:EAX / SRC;
IF temp > FFFFFFFFH
THEN #DE; (* Divide error *)
ELSE
EAX ← temp;
EDX ← EDX:EAX MOD SRC;
FI;
FI;
ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)
THEN
temp ← RDX:RAX / SRC;
IF temp > FFFFFFFFFFFFFFFFH
THEN #DE; (* Divide error *)
ELSE
RAX ← temp;
RDX ← RDX:RAX MOD SRC;
FI;
FI;
FI;
Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are undefined.
3-286 Vol. 2A
DIV—Unsigned Divide
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#DE
If the source operand (divisor) is 0
If the quotient is too large for the designated register.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#DE
If the source operand (divisor) is 0.
If the quotient is too large for the designated register.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#DE
If the source operand (divisor) is 0.
If the quotient is too large for the designated register.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#DE
If the source operand (divisor) is 0
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
If the quotient is too large for the designated register.
DIV—Unsigned Divide
Vol. 2A 3-287
INSTRUCTION SET REFERENCE, A-L
DIVPD—Divide Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5E /r
DIVPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 5E /r
VDIVPD xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F.WIG 5E /r
VDIVPD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX
EVEX.NDS.128.66.0F.W1 5E /r
VDIVPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F.W1 5E /r
VDIVPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F.W1 5E /r
VDIVPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
FV
V/V
AVX512F
Description
Divide packed double-precision floating-point values
in xmm1 by packed double-precision floating-point
values in xmm2/mem.
Divide packed double-precision floating-point values
in xmm2 by packed double-precision floating-point
values in xmm3/mem.
Divide packed double-precision floating-point values
in ymm2 by packed double-precision floating-point
values in ymm3/mem.
Divide packed double-precision floating-point values
in xmm2 by packed double-precision floating-point
values in xmm3/m128/m64bcst and write results to
xmm1 subject to writemask k1.
Divide packed double-precision floating-point values
in ymm2 by packed double-precision floating-point
values in ymm3/m256/m64bcst and write results to
ymm1 subject to writemask k1.
Divide packed double-precision floating-point values
in zmm2 by packed double-precision FP values in
zmm3/m512/m64bcst and write results to zmm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD divide of the double-precision floating-point values in the first source operand by the floatingpoint values in the second source operand (the third operand). Results are written to the destination operand (the
first operand).
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source
operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper
bits (MAX_VL-1:256) of the corresponding destination are zeroed.
VEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source
operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper
bits (MAX_VL-1:128) of the corresponding destination are zeroed.
128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128bit memory location. The destination is the same as the first source operand. The upper bits (MAX_VL-1:128) of the
corresponding destination are unmodified.
3-288 Vol. 2A
DIVPD—Divide Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VDIVPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
; refer to Table 2-4 in the Intel® Architecture Instruction Set Extensions Programming Reference
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] SRC1[i+63:i] / SRC2[63:0]
ELSE
DEST[i+63:i] SRC1[i+63:i] / SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VDIVPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64] / SRC2[127:64]
DEST[191:128] SRC1[191:128] / SRC2[191:128]
DEST[255:192] SRC1[255:192] / SRC2[255:192]
DEST[MAX_VL-1:256] 0;
VDIVPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64] / SRC2[127:64]
DEST[MAX_VL-1:128] 0;
DIVPD (128-bit Legacy SSE version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64] / SRC2[127:64]
DEST[MAX_VL-1:128] (Unmodified)
DIVPD—Divide Packed Double-Precision Floating-Point Values
Vol. 2A 3-289
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VDIVPD __m512d _mm512_div_pd( __m512d a, __m512d b);
VDIVPD __m512d _mm512_mask_div_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VDIVPD __m512d _mm512_maskz_div_pd( __mmask8 k, __m512d a, __m512d b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPD __m512d _mm512_div_round_pd( __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_mask_div_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_maskz_div_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m256d _mm256_div_pd (__m256d a, __m256d b);
DIVPD __m128d _mm_div_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
3-290 Vol. 2A
DIVPD—Divide Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
DIVPS—Divide Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 5E /r
DIVPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 5E /r
VDIVPS xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.0F.WIG 5E /r
VDIVPS ymm1, ymm2, ymm3/m256
RVM
V/V
AVX
EVEX.NDS.128.0F.W0 5E /r
VDIVPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.0F.W0 5E /r
VDIVPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.0F.W0 5E /r
VDIVPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{er}
FV
V/V
AVX512F
Description
Divide packed single-precision floating-point values
in xmm1 by packed single-precision floating-point
values in xmm2/mem.
Divide packed single-precision floating-point values
in xmm2 by packed single-precision floating-point
values in xmm3/mem.
Divide packed single-precision floating-point values
in ymm2 by packed single-precision floating-point
values in ymm3/mem.
Divide packed single-precision floating-point values
in xmm2 by packed single-precision floating-point
values in xmm3/m128/m32bcst and write results to
xmm1 subject to writemask k1.
Divide packed single-precision floating-point values
in ymm2 by packed single-precision floating-point
values in ymm3/m256/m32bcst and write results to
ymm1 subject to writemask k1.
Divide packed single-precision floating-point values
in zmm2 by packed single-precision floating-point
values in zmm3/m512/m32bcst and write results to
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD divide of the four, eight or sixteen packed single-precision floating-point values in the first source
operand (the second operand) by the four, eight or sixteen packed single-precision floating-point values in the
second source operand (the third operand). Results are written to the destination operand (the first operand).
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
DIVPS—Divide Packed Single-Precision Floating-Point Values
Vol. 2A 3-291
INSTRUCTION SET REFERENCE, A-L
Operation
VDIVPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] SRC1[i+31:i] / SRC2[31:0]
ELSE
DEST[i+31:i] SRC1[i+31:i] / SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VDIVPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] / SRC2[31:0]
DEST[63:32] SRC1[63:32] / SRC2[63:32]
DEST[95:64] SRC1[95:64] / SRC2[95:64]
DEST[127:96] SRC1[127:96] / SRC2[127:96]
DEST[159:128] SRC1[159:128] / SRC2[159:128]
DEST[191:160]SRC1[191:160] / SRC2[191:160]
DEST[223:192] SRC1[223:192] / SRC2[223:192]
DEST[255:224] SRC1[255:224] / SRC2[255:224].
DEST[MAX_VL-1:256] 0;
VDIVPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] / SRC2[31:0]
DEST[63:32] SRC1[63:32] / SRC2[63:32]
DEST[95:64] SRC1[95:64] / SRC2[95:64]
DEST[127:96] SRC1[127:96] / SRC2[127:96]
DEST[MAX_VL-1:128] 0
3-292 Vol. 2A
DIVPS—Divide Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
DIVPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] / SRC2[31:0]
DEST[63:32] SRC1[63:32] / SRC2[63:32]
DEST[95:64] SRC1[95:64] / SRC2[95:64]
DEST[127:96] SRC1[127:96] / SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);
VDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);
DIVPS __m128 _mm_div_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
DIVPS—Divide Packed Single-Precision Floating-Point Values
Vol. 2A 3-293
INSTRUCTION SET REFERENCE, A-L
DIVSD—Divide Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 5E /r
DIVSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 5E /r
VDIVSD xmm1, xmm2, xmm3/m64
RVM
V/V
AVX
EVEX.NDS.LIG.F2.0F.W1 5E /r
VDIVSD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
T1S
V/V
AVX512F
Description
Divide low double-precision floating-point value in
xmm1 by low double-precision floating-point value
in xmm2/m64.
Divide low double-precision floating-point value in
xmm2 by low double-precision floating-point value
in xmm3/m64.
Divide low double-precision floating-point value in
xmm2 by low double-precision floating-point value
in xmm3/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Divides the low double-precision floating-point value in the first source operand by the low double-precision
floating-point value in the second source operand, and stores the double-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source
and destination are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL1:64) of the corresponding ZMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits
127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword
element of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low quadword element of the destination is updated according to the writemask.
Software should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
3-294 Vol. 2A
DIVSD—Divide Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
Operation
VDIVSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] SRC1[63:0] / SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VDIVSD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
DIVSD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] / SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VDIVSD __m128d _mm_mask_div_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVSD __m128d _mm_maskz_div_sd( __mmask8 k, __m128d a, __m128d b);
VDIVSD __m128d _mm_div_round_sd( __m128d a, __m128d b, int);
VDIVSD __m128d _mm_mask_div_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VDIVSD __m128d _mm_maskz_div_round_sd( __mmask8 k, __m128d a, __m128d b, int);
DIVSD __m128d _mm_div_sd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
DIVSD—Divide Scalar Double-Precision Floating-Point Value
Vol. 2A 3-295
INSTRUCTION SET REFERENCE, A-L
DIVSS—Divide Scalar Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 5E /r
DIVSS xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 5E /r
VDIVSS xmm1, xmm2, xmm3/m32
RVM
V/V
AVX
EVEX.NDS.LIG.F3.0F.W0 5E /r
VDIVSS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
T1S
V/V
AVX512F
Description
Divide low single-precision floating-point value in
xmm1 by low single-precision floating-point value in
xmm2/m32.
Divide low single-precision floating-point value in
xmm2 by low single-precision floating-point value in
xmm3/m32.
Divide low single-precision floating-point value in
xmm2 by low single-precision floating-point value in
xmm3/m32.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Divides the low single-precision floating-point value in the first source operand by the low single-precision floatingpoint value in the second source operand, and stores the single-precision floating-point result in the destination
operand. The second source operand can be an XMM register or a 32-bit memory location.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order
doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128) of the
destination register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword
elements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
3-296 Vol. 2A
DIVSS—Divide Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VDIVSS (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] SRC1[31:0] / SRC2[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VDIVSS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] / SRC2[31:0]
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
DIVSS (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0] / SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VDIVSS __m128 _mm_mask_div_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VDIVSS __m128 _mm_maskz_div_ss( __mmask8 k, __m128 a, __m128 b);
VDIVSS __m128 _mm_div_round_ss( __m128 a, __m128 b, int);
VDIVSS __m128 _mm_mask_div_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VDIVSS __m128 _mm_maskz_div_round_ss( __mmask8 k, __m128 a, __m128 b, int);
DIVSS __m128 _mm_div_ss(__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
DIVSS—Divide Scalar Single-Precision Floating-Point Values
Vol. 2A 3-297
INSTRUCTION SET REFERENCE, A-L
DPPD — Dot Product of Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A 41 /r ib
RMI
V/V
SSE4_1
Selectively multiply packed DP floating-point
values from xmm1 with packed DP floatingpoint values from xmm2, add and selectively
store the packed DP floating-point values to
xmm1.
AVX
Selectively multiply packed DP floating-point
values from xmm2 with packed DP floatingpoint values from xmm3, add and selectively
store the packed DP floating-point values to
xmm1.
DPPD xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 41 /r ib
RVMI V/V
VDPPD xmm1,xmm2, xmm3/m128, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Conditionally multiplies the packed double-precision floating-point values in the destination operand (first operand)
with the packed double-precision floating-point values in the source (second operand) depending on a mask
extracted from bits [5:4] of the immediate operand (third operand). If a condition mask bit is zero, the corresponding multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1.
The two resulting double-precision values are summed into an intermediate result. The intermediate result is
conditionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte.
If a broadcast mask bit is “1”, the intermediate result is copied to the corresponding qword element in the destination operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.
DPPD follows the NaN forwarding rules stated in the Software Developer’s Manual, vol. 1, table 4.7. These rules do
not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of
those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally generated NaNs will have at least one NaN propagated to the destination.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
If VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an
#UD exception.
3-298 Vol. 2A
DPPD — Dot Product of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1)
THEN Temp1[63:0] DEST[63:0] * SRC[63:0]; // update SIMD exception flags
ELSE Temp1[63:0] +0.0; FI;
IF (imm8[5] = 1)
THEN Temp1[127:64] DEST[127:64] * SRC[127:64]; // update SIMD exception flags
ELSE Temp1[127:64] +0.0; FI;
/* if unmasked exception reported, execute exception handler*/
Temp2[63:0] Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
IF (imm8[0] = 1)
THEN DEST[63:0] Temp2[63:0];
ELSE DEST[63:0] +0.0; FI;
IF (imm8[1] = 1)
THEN DEST[127:64] Temp2[63:0];
ELSE DEST[127:64] +0.0; FI;
DPPD (128-bit Legacy SSE version)
DEST[127:0]DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] (Unmodified)
VDPPD (VEX.128 encoded version)
DEST[127:0]DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] 0
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
DPPD:
__m128d _mm_dp_pd ( __m128d a, __m128d b, const int mask);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Exceptions are determined separately for each add and multiply operation. Unmasked exceptions will leave the
destination untouched.
Other Exceptions
See Exceptions Type 2; additionally
#UD
If VEX.L= 1.
DPPD — Dot Product of Packed Double Precision Floating-Point Values
Vol. 2A 3-299
INSTRUCTION SET REFERENCE, A-L
DPPS — Dot Product of Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A 40 /r ib
RMI
V/V
SSE4_1
Selectively multiply packed SP floating-point
values from xmm1 with packed SP floatingpoint values from xmm2, add and selectively
store the packed SP floating-point values or
zero values to xmm1.
RVMI V/V
AVX
Multiply packed SP floating point values from
xmm1 with packed SP floating point values
from xmm2/mem selectively add and store to
xmm1.
RVMI V/V
AVX
Multiply packed single-precision floating-point
values from ymm2 with packed SP floating
point values from ymm3/mem, selectively add
pairs of elements and store to ymm1.
DPPS xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 40 /r ib
VDPPS xmm1,xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.WIG 40 /r ib
VDPPS ymm1, ymm2, ymm3/m256, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Conditionally multiplies the packed single precision floating-point values in the destination operand (first operand)
with the packed single-precision floats in the source (second operand) depending on a mask extracted from the
high 4 bits of the immediate byte (third operand). If a condition mask bit in Imm8[7:4] is zero, the corresponding
multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
The four resulting single-precision values are summed into an intermediate result. The intermediate result is conditionally broadcasted to the destination using a broadcast mask specified by bits [3:0] of the immediate byte.
If a broadcast mask bit is “1”, the intermediate result is copied to the corresponding dword element in the destination operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.
DPPS follows the NaN forwarding rules stated in the Software Developer’s Manual, vol. 1, table 4.7. These rules do
not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of
those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally generated NaNs will have at least one NaN propagated to the destination.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
3-300 Vol. 2A
DPPS — Dot Product of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1)
THEN Temp1[31:0] DEST[31:0] * SRC[31:0]; // update SIMD exception flags
ELSE Temp1[31:0] +0.0; FI;
IF (imm8[5] = 1)
THEN Temp1[63:32] DEST[63:32] * SRC[63:32]; // update SIMD exception flags
ELSE Temp1[63:32] +0.0; FI;
IF (imm8[6] = 1)
THEN Temp1[95:64] DEST[95:64] * SRC[95:64]; // update SIMD exception flags
ELSE Temp1[95:64] +0.0; FI;
IF (imm8[7] = 1)
THEN Temp1[127:96] DEST[127:96] * SRC[127:96]; // update SIMD exception flags
ELSE Temp1[127:96] +0.0; FI;
Temp2[31:0] Temp1[31:0] + Temp1[63:32]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
Temp3[31:0] Temp1[95:64] + Temp1[127:96]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
Temp4[31:0] Temp2[31:0] + Temp3[31:0]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
IF (imm8[0] = 1)
THEN DEST[31:0] Temp4[31:0];
ELSE DEST[31:0] +0.0; FI;
IF (imm8[1] = 1)
THEN DEST[63:32] Temp4[31:0];
ELSE DEST[63:32] +0.0; FI;
IF (imm8[2] = 1)
THEN DEST[95:64] Temp4[31:0];
ELSE DEST[95:64] +0.0; FI;
IF (imm8[3] = 1)
THEN DEST[127:96] Temp4[31:0];
ELSE DEST[127:96] +0.0; FI;
DPPS (128-bit Legacy SSE version)
DEST[127:0]DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] (Unmodified)
VDPPS (VEX.128 encoded version)
DEST[127:0]DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] 0
VDPPS (VEX.256 encoded version)
DEST[127:0]DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[255:128]DP_Primitive(SRC1[255:128], SRC2[255:128]);
Flags Affected
None
DPPS — Dot Product of Packed Single Precision Floating-Point Values
Vol. 2A 3-301
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
(V)DPPS:
__m128 _mm_dp_ps ( __m128 a, __m128 b, const int mask);
VDPPS:
__m256 _mm256_dp_ps ( __m256 a, __m256 b, const int mask);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Exceptions are determined separately for each add and multiply operation, in the order of their execution.
Unmasked exceptions will leave the destination operands unchanged.
Other Exceptions
See Exceptions Type 2.
3-302 Vol. 2A
DPPS — Dot Product of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
EMMS—Empty MMX Technology State
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 77
EMMS
NP
Valid
Valid
Set the x87 FPU tag word to empty.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data
registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instructions. (See Figure 8-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the
format of the x87 FPU tag word.) All other MMX instructions (other than the EMMS instruction) set all the tags in
x87 FPU tag word to valid (all 0s).
The EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures
or subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions.
If a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag
word has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will
result in an x87 floating-point exception or incorrect result.
EMMS operation is the same in non-64-bit modes and 64-bit mode.
Operation
x87FPUTagWord ← FFFFH;
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_empty()
Flags Affected
None
Protected Mode Exceptions
#UD
If CR0.EM[bit 2] = 1.
#NM
If CR0.TS[bit 3] = 1.
#MF
If there is a pending FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
EMMS—Empty MMX Technology State
Vol. 2A 3-303
INSTRUCTION SET REFERENCE, A-L
ENTER—Make Stack Frame for Procedure Parameters
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
C8 iw 00
ENTER imm16, 0
II
Valid
Valid
Create a stack frame for a procedure.
C8 iw 01
ENTER imm16,1
II
Valid
Valid
Create a stack frame with a nested pointer for
a procedure.
C8 iw ib
ENTER imm16, imm8
II
Valid
Valid
Create a stack frame with nested pointers for
a procedure.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
II
iw
imm8
NA
NA
Description
Creates a stack frame (comprising of space for dynamic storage and 1-32 frame pointer storage) for a procedure.
The first operand (imm16) specifies the size of the dynamic storage in the stack frame (that is, the number of bytes
of dynamically allocated on the stack for the procedure). The second operand (imm8) gives the lexical nesting level
(0 to 31) of the procedure. The nesting level (imm8 mod 32) and the OperandSize attribute determine the size in
bytes of the storage space for frame pointers.
The nesting level determines the number of frame pointers that are copied into the “display area” of the new stack
frame from the preceding frame. The default size of the frame pointer is the StackAddrSize attribute, but can be
overridden using the 66H prefix. Thus, the OperandSize attribute determines the size of each frame pointer that
will be copied into the stack frame and the data being transferred from SP/ESP/RSP register into the BP/EBP/RBP
register.
The ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER
instruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for
a procedure. The LEAVE instruction is then used at the end of the procedure (just before the RET instruction) to
release the stack frame.
If the nesting level is 0, the processor pushes the frame pointer from the BP/EBP/RBP register onto the stack,
copies the current stack pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and loads the
SP/ESP/RSP register with the current stack-pointer value minus the value in the size operand. For nesting levels of
1 or greater, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. These
additional frame pointers provide the called procedure with access points to other nested frames on the stack. See
“Procedure Calls for Block-Structured Languages” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for more information about the actions of the ENTER instruction.
The ENTER instruction causes a page fault whenever a write using the final value of the stack pointer (within the
current stack segment) would do so.
In 64-bit mode, default operation size is 64 bits; 32-bit operation size cannot be encoded. Use of 66H prefix
changes frame pointer operand size to 16 bits.
When the 66H prefix is used and causing the OperandSize attribute to be less than the StackAddrSize, software is
responsible for the following:
•
•
The companion LEAVE instruction must also use the 66H prefix,
The value in the RBP/EBP register prior to executing “66H ENTER” must be within the same 16KByte region of
the current stack pointer (RSP/ESP), such that the value of RBP/EBP after “66H ENTER” remains a valid address
in the stack. This ensures “66H LEAVE” can restore 16-bits of data from the stack.
3-304 Vol. 2A
ENTER—Make Stack Frame for Procedure Parameters
INSTRUCTION SET REFERENCE, A-L
Operation
AllocSize ← imm16;
NestingLevel ← imm8 MOD 32;
IF (OperandSize = 64)
THEN
Push(RBP); (* RSP decrements by 8 *)
FrameTemp ← RSP;
ELSE IF OperandSize = 32
THEN
Push(EBP); (* (E)SP decrements by 4 *)
FrameTemp ← ESP; FI;
ELSE (* OperandSize = 16 *)
Push(BP); (* RSP or (E)SP decrements by 2 *)
FrameTemp ← SP;
FI;
IF NestingLevel = 0
THEN GOTO CONTINUE;
FI;
IF (NestingLevel > 1)
THEN FOR i ← 1 to (NestingLevel - 1)
DO
IF (OperandSize = 64)
THEN
RBP ← RBP - 8;
Push([RBP]); (* Quadword push *)
ELSE IF OperandSize = 32
THEN
IF StackSize = 32
EBP ← EBP - 4;
Push([EBP]); (* Doubleword push *)
ELSE (* StackSize = 16 *)
BP ← BP - 4;
Push([BP]); (* Doubleword push *)
FI;
FI;
ELSE (* OperandSize = 16 *)
IF StackSize = 32
THEN
EBP ← EBP - 2;
Push([EBP]); (* Word push *)
ELSE (* StackSize = 16 *)
BP ← BP - 2;
Push([BP]); (* Word push *)
FI;
FI;
OD;
FI;
IF (OperandSize = 64) (* nestinglevel 1 *)
THEN
Push(FrameTemp); (* Quadword push and RSP decrements by 8 *)
ELSE IF OperandSize = 32
ENTER—Make Stack Frame for Procedure Parameters
Vol. 2A 3-305
INSTRUCTION SET REFERENCE, A-L
THEN
Push(FrameTemp); FI; (* Doubleword push and (E)SP decrements by 4 *)
ELSE (* OperandSize = 16 *)
Push(FrameTemp); (* Word push and RSP|ESP|SP decrements by 2 *)
FI;
CONTINUE:
IF 64-Bit Mode (StackSize = 64)
THEN
RBP ← FrameTemp;
RSP ← RSP − AllocSize;
ELSE IF OperandSize = 32
THEN
EBP ← FrameTemp;
ESP ← ESP − AllocSize; FI;
ELSE (* OperandSize = 16 *)
BP ← FrameTemp[15:1]; (* Bits 16 and above of applicable RBP/EBP are unmodified *)
SP ← SP − AllocSize;
FI;
END;
Flags Affected
None.
Protected Mode Exceptions
#SS(0)
If the new value of the SP or ESP register is outside the stack segment limit.
#PF(fault-code)
If a page fault occurs or if a write using the final value of the stack pointer (within the current
stack segment) would cause a page fault.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#SS
If the new value of the SP or ESP register is outside the stack segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#SS(0)
If the new value of the SP or ESP register is outside the stack segment limit.
#PF(fault-code)
If a page fault occurs or if a write using the final value of the stack pointer (within the current
stack segment) would cause a page fault.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If the stack address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs or if a write using the final value of the stack pointer (within the current
stack segment) would cause a page fault.
#UD
If the LOCK prefix is used.
3-306 Vol. 2A
ENTER—Make Stack Frame for Procedure Parameters
INSTRUCTION SET REFERENCE, A-L
EXTRACTPS—Extract Packed Floating-Point Values
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
VV
CPUID
Feature
Flag
SSE4_1
66 0F 3A 17 /r ib
EXTRACTPS reg/m32, xmm1, imm8
VEX.128.66.0F3A.WIG 17 /r ib
VEXTRACTPS reg/m32, xmm1, imm8
RMI
V/V
AVX
EVEX.128.66.0F3A.WIG 17 /r ib
VEXTRACTPS reg/m32, xmm1, imm8
T1S
V/V
AVX512F
Description
Extract one single-precision floating-point value
from xmm1 at the offset specified by imm8 and
store the result in reg or m32. Zero extend the
results in 64-bit register if applicable.
Extract one single-precision floating-point value
from xmm1 at the offset specified by imm8 and
store the result in reg or m32. Zero extend the
results in 64-bit register if applicable.
Extract one single-precision floating-point value
from xmm1 at the offset specified by imm8 and
store the result in reg or m32. Zero extend the
results in 64-bit register if applicable.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
T1S
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
Description
Extracts a single-precision floating-point value from the source operand (second operand) at the 32-bit offset specified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored.
The extracted single-precision floating-point value is stored in the low 32-bits of the destination operand
In 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register
are filled with zero. REX.W is ignored.
VEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general
purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits.
VEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as
a destination operand, the packed single quantity is zero extended to 64 bits.
The source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the
32-bit floating-point value.
If VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause
an #UD exception.
Operation
VEXTRACTPS (EVEX and VEX.128 encoded version)
SRC_OFFSET IMM8[1:0]
IF (64-Bit Mode and DEST is register)
DEST[31:0] (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
DEST[63:32] 0
ELSE
DEST[31:0] (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
FI
EXTRACTPS—Extract Packed Floating-Point Values
Vol. 2A 3-307
INSTRUCTION SET REFERENCE, A-L
EXTRACTPS (128-bit Legacy SSE version)
SRC_OFFSET IMM8[1:0]
IF (64-Bit Mode and DEST is register)
DEST[31:0] (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
DEST[63:32] 0
ELSE
DEST[31:0] (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
FI
Intel C/C++ Compiler Intrinsic Equivalent
EXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instructions, see Exceptions Type 5; Additionally
EVEX-encoded instructions, see Exceptions Type E9NF.
#UD
IF VEX.L = 0.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
3-308 Vol. 2A
EXTRACTPS—Extract Packed Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
F2XM1—Compute 2x–1
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 F0
F2XM1
Valid
Valid
Replace ST(0) with (2ST(0) – 1).
Description
Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in
register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range –1.0 to
+1.0. If the source value is outside this range, the result is undefined.
The following table shows the results obtained when computing the exponential value of various classes of
numbers, assuming that neither overflow nor underflow occurs.
Table 3-16. Results Obtained from F2XM1
ST(0) SRC
ST(0) DEST
− 1.0 to −0
− 0.5 to − 0
−0
−0
+0
+0
+ 0 to +1.0
+ 0 to 1.0
Values other than 2 can be exponentiated using the following formula:
xy ← 2(y ∗ log2x)
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
ST(0) ← (2ST(0) − 1);
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
Source operand is an SNaN value or unsupported format.
#D
Source is a denormal value.
#U
Result is too small for destination format.
#P
Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
F2XM1—Compute 2x–1
Vol. 2A 3-309
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-310 Vol. 2A
F2XM1—Compute 2x–1
INSTRUCTION SET REFERENCE, A-L
FABS—Absolute Value
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 E1
FABS
Valid
Valid
Replace ST with its absolute value.
Description
Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results
obtained when creating the absolute value of various classes of numbers.
Table 3-17. Results Obtained from FABS
ST(0) SRC
ST(0) DEST
−∞
+∞
−F
+F
−0
+0
+0
+0
+F
+F
+∞
+∞
NaN
NaN
NOTES:
F Means finite floating-point value.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
ST(0) ← |ST(0)|;
FPU Flags Affected
C1
Set to 0.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
FABS—Absolute Value
Vol. 2A 3-311
INSTRUCTION SET REFERENCE, A-L
FADD/FADDP/FIADD—Add
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D8 /0
FADD m32fp
Valid
Valid
Add m32fp to ST(0) and store result in ST(0).
DC /0
FADD m64fp
Valid
Valid
Add m64fp to ST(0) and store result in ST(0).
D8 C0+i
FADD ST(0), ST(i)
Valid
Valid
Add ST(0) to ST(i) and store result in ST(0).
DC C0+i
FADD ST(i), ST(0)
Valid
Valid
Add ST(i) to ST(0) and store result in ST(i).
DE C0+i
FADDP ST(i), ST(0)
Valid
Valid
Add ST(0) to ST(i), store result in ST(i), and pop the
register stack.
DE C1
FADDP
Valid
Valid
Add ST(0) to ST(1), store result in ST(1), and pop the
register stack.
DA /0
FIADD m32int
Valid
Valid
Add m32int to ST(0) and store result in ST(0).
DE /0
FIADD m16int
Valid
Valid
Add m16int to ST(0) and store result in ST(0).
Description
Adds the destination and source operands and stores the sum in the destination location. The destination operand
is always an FPU register; the source operand can be a register or a memory location. Source operands in memory
can be in single-precision or double-precision floating-point format or in word or doubleword integer format.
The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The oneoperand version adds the contents of a memory location (either a floating-point or an integer value) to the contents
of the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice
versa. The value in ST(0) can be doubled by coding:
FADD ST(0), ST(0);
The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)
by 1. (The no-operand version of the floating-point add instructions always results in the register stack being
popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)
The FIADD instructions convert an integer source operand to double extended-precision floating-point format
before performing the addition.
The table on the following page shows the results obtained when adding various classes of numbers, assuming that
neither overflow nor underflow occurs.
When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward −∞ mode, in
which case the result is −0. When the source operand is an integer 0, it is treated as a +0.
When both operand are infinities of the same sign, the result is ∞ of the expected sign. If both operands are infinities of opposite signs, an invalid-operation exception is generated. See Table 3-18.
3-312 Vol. 2A
FADD/FADDP/FIADD—Add
INSTRUCTION SET REFERENCE, A-L
Table 3-18. FADD/FADDP/FIADD Results
DEST
SRC
−∞
−F
−0
+0
+F
+∞
NaN
−∞
−∞
−∞
−∞
−∞
−∞
*
NaN
− F or − I
−∞
−F
SRC
SRC
± F or ± 0
+∞
NaN
−0
−∞
DEST
−0
±0
DEST
+∞
NaN
+0
−∞
DEST
±0
+0
DEST
+∞
NaN
+ F or + I
−∞
± F or ± 0
SRC
SRC
+F
+∞
NaN
+∞
*
+∞
+∞
+∞
+∞
+∞
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NOTES:
F Means finite floating-point value.
I Means integer.
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF Instruction = FIADD
THEN
DEST ← DEST + ConvertToDoubleExtendedPrecisionFP(SRC);
ELSE (* Source operand is floating-point value *)
DEST ← DEST + SRC;
FI;
IF Instruction = FADDP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
Operand is an SNaN value or unsupported format.
Operands are infinities of unlike sign.
#D
Source operand is a denormal value.
#U
Result is too small for destination format.
#O
Result is too large for destination format.
#P
Value cannot be represented exactly in destination format.
FADD/FADDP/FIADD—Add
Vol. 2A 3-313
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-314 Vol. 2A
FADD/FADDP/FIADD—Add
INSTRUCTION SET REFERENCE, A-L
FBLD—Load Binary Coded Decimal
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DF /4
FBLD m80dec
Valid
Valid
Convert BCD value to floating-point and push onto the
FPU stack.
Description
Converts the BCD source operand into double extended-precision floating-point format and pushes the value onto
the FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved,
including that of −0.
The packed BCD digits are assumed to be in the range 0 through 9; the instruction does not check for invalid digits
(AH through FH). Attempting to load an invalid encoding produces an undefined result.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
TOP ← TOP − 1;
ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC);
FPU Flags Affected
C1
Set to 1 if stack overflow occurred; otherwise, set to 0.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack overflow occurred.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
FBLD—Load Binary Coded Decimal
Vol. 2A 3-315
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-316 Vol. 2A
FBLD—Load Binary Coded Decimal
INSTRUCTION SET REFERENCE, A-L
FBSTP—Store BCD Integer and Pop
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DF /6
FBSTP m80bcd
Valid
Valid
Store ST(0) in m80bcd and pop ST(0).
Description
Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination
operand, and pops the register stack. If the source value is a non-integral value, it is rounded to an integer value,
according to rounding mode specified by the RC field of the FPU control word. To pop the register stack, the
processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The destination operand specifies the address where the first byte destination value is to be stored. The BCD value
(including its sign bit) requires 10 bytes of space in memory.
The following table shows the results obtained when storing various classes of numbers in packed BCD format.
Table 3-19. FBSTP Results
ST(0)
DEST
− ∞ or Value Too Large for DEST Format
*
F≤−1
−D
−1 < F < -0
**
−0
−0
+0
+0
+ 0 < F < +1
**
F ≥ +1
+D
+ ∞ or Value Too Large for DEST Format
*
NaN
*
NOTES:
F Means finite floating-point value.
D Means packed-BCD number.
* Indicates floating-point invalid-operation (#IA) exception.
** ±0 or ±1, depending on the rounding mode.
If the converted value is too large for the destination format, or if the source operand is an ∞, SNaN, QNAN, or is in
an unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is
not masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination
operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
DEST ← BCD(ST(0));
PopRegisterStack;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3
Undefined.
FBSTP—Store BCD Integer and Pop
Vol. 2A 3-317
INSTRUCTION SET REFERENCE, A-L
Floating-Point Exceptions
#IS
#IA
Stack underflow occurred.
Converted value that exceeds 18 BCD digits in length.
Source operand is an SNaN, QNaN, ±∞, or in an unsupported format.
#P
Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#GP(0)
If a segment register is being loaded with a segment selector that points to a non-writable
segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-318 Vol. 2A
FBSTP—Store BCD Integer and Pop
INSTRUCTION SET REFERENCE, A-L
FCHS—Change Sign
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 E0
FCHS
Valid
Valid
Complements sign of ST(0).
Description
Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magnitude or vice versa. The following table shows the results obtained when changing the sign of various classes of
numbers.
Table 3-20. FCHS Results
ST(0) SRC
ST(0) DEST
−∞
+∞
−F
+F
−0
+0
+0
−0
+F
−F
+∞
−∞
NaN
NaN
NOTES:
* F means finite floating-point value.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
SignBit(ST(0)) ← NOT (SignBit(ST(0)));
FPU Flags Affected
C1
Set to 0.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
FCHS—Change Sign
Vol. 2A 3-319
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-320 Vol. 2A
FCHS—Change Sign
INSTRUCTION SET REFERENCE, A-L
FCLEX/FNCLEX—Clear Exceptions
Opcode*
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
9B DB E2
FCLEX
Valid
Valid
Clear floating-point exception flags after checking for
pending unmasked floating-point exceptions.
DB E2
FNCLEX*
Valid
Valid
Clear floating-point exception flags without checking for
pending unmasked floating-point exceptions.
NOTES:
* See IA-32 Architecture Compatibility section below.
Description
Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the
stack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles
any pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does
not.
The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX
instruction), and the processor executes each of these instructions separately. If an exception is generated for
either of these instructions, the save EIP points to the instruction that caused the exception.
IA-32 Architecture Compatibility
When operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual
circumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An
FNCLEX instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000
processor.
This instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point
exception flags in the MXCRS register.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
FPUStatusWord[0:7] ← 0;
FPUStatusWord[15] ← 0;
FPU Flags Affected
The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are
undefined.
Floating-Point Exceptions
None
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
FCLEX/FNCLEX—Clear Exceptions
Vol. 2A 3-321
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-322 Vol. 2A
FCLEX/FNCLEX—Clear Exceptions
INSTRUCTION SET REFERENCE, A-L
FCMOVcc—Floating-Point Conditional Move
Opcode*
Instruction
64-Bit
Mode
Compat/
Description
Leg Mode*
DA C0+i
FCMOVB ST(0), ST(i)
Valid
Valid
Move if below (CF=1).
DA C8+i
FCMOVE ST(0), ST(i)
Valid
Valid
Move if equal (ZF=1).
DA D0+i
FCMOVBE ST(0), ST(i)
Valid
Valid
Move if below or equal (CF=1 or ZF=1).
DA D8+i
FCMOVU ST(0), ST(i)
Valid
Valid
Move if unordered (PF=1).
DB C0+i
FCMOVNB ST(0), ST(i)
Valid
Valid
Move if not below (CF=0).
DB C8+i
FCMOVNE ST(0), ST(i)
Valid
Valid
Move if not equal (ZF=0).
DB D0+i
FCMOVNBE ST(0), ST(i)
Valid
Valid
Move if not below or equal (CF=0 and ZF=0).
DB D8+i
FCMOVNU ST(0), ST(i)
Valid
Valid
Move if not unordered (PF=0).
NOTES:
* See IA-32 Architecture Compatibility section below.
Description
Tests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination
operand (first operand) if the given test condition is true. The condition for each mnemonic os given in the Description column above and in Chapter 8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
1. The source operand is always in the ST(i) register and the destination operand is always ST(0).
The FCMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching
overhead for IF operations and the possibility of branch mispredictions by the processor.
A processor may not support the FCMOVcc instructions. Software can check if the FCMOVcc instructions are
supported by checking the processor’s feature information with the CPUID instruction (see “COMISS—Compare
Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS” in this chapter). If both the CMOV and FPU
feature bits are set, the FCMOVcc instructions are supported.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IA-32 Architecture Compatibility
The FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 family processors and are not available in earlier IA-32 processors.
Operation
IF condition TRUE
THEN ST(0) ← ST(i);
FI;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
Integer Flags Affected
None.
FCMOVcc—Floating-Point Conditional Move
Vol. 2A 3-323
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-324 Vol. 2A
FCMOVcc—Floating-Point Conditional Move
INSTRUCTION SET REFERENCE, A-L
FCOM/FCOMP/FCOMPP—Compare Floating Point Values
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D8 /2
FCOM m32fp
Valid
Valid
Compare ST(0) with m32fp.
DC /2
FCOM m64fp
Valid
Valid
Compare ST(0) with m64fp.
D8 D0+i
FCOM ST(i)
Valid
Valid
Compare ST(0) with ST(i).
D8 D1
FCOM
Valid
Valid
Compare ST(0) with ST(1).
D8 /3
FCOMP m32fp
Valid
Valid
Compare ST(0) with m32fp and pop register stack.
DC /3
FCOMP m64fp
Valid
Valid
Compare ST(0) with m64fp and pop register stack.
D8 D8+i
FCOMP ST(i)
Valid
Valid
Compare ST(0) with ST(i) and pop register stack.
D8 D9
FCOMP
Valid
Valid
Compare ST(0) with ST(1) and pop register stack.
DE D9
FCOMPP
Valid
Valid
Compare ST(0) with ST(1) and pop register stack
twice.
Description
Compares the contents of register ST(0) and source value and sets condition code flags C0, C2, and C3 in the FPU
status word according to the results (see the table below). The source operand can be a data register or a memory
location. If no source operand is given, the value in ST(0) is compared with the value in ST(1). The sign of zero is
ignored, so that –0.0 is equal to +0.0.
Table 3-21. FCOM/FCOMP/FCOMPP Results
Condition
C3
C2
C0
ST(0) > SRC
0
0
0
ST(0) < SRC
0
0
1
ST(0) = SRC
1
0
0
Unordered*
1
1
1
NOTES:
* Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.
This instruction checks the class of the numbers being compared (see “FXAM—Examine Floating-Point” in this
chapter). If either operand is a NaN or is in an unsupported format, an invalid-arithmetic-operand exception (#IA)
is raised and, if the exception is masked, the condition flags are set to “unordered.” If the invalid-arithmeticoperand exception is unmasked, the condition code flags are not set.
The FCOMP instruction pops the register stack following the comparison operation and the FCOMPP instruction
pops the register stack twice following the comparison operation. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The FCOM instructions perform the same operation as the FUCOM instructions. The only difference is how they
handle QNaN operands. The FCOM instructions raise an invalid-arithmetic-operand exception (#IA) when either or
both of the operands is a NaN value or is in an unsupported format. The FUCOM instructions perform the same
operation as the FCOM instructions, except that they do not generate an invalid-arithmetic-operand exception for
QNaNs.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
FCOM/FCOMP/FCOMPP—Compare Floating Point Values
Vol. 2A 3-325
INSTRUCTION SET REFERENCE, A-L
Operation
CASE (relation of operands) OF
ST > SRC:
C3, C2, C0 ← 000;
ST < SRC:
C3, C2, C0 ← 001;
ST = SRC:
C3, C2, C0 ← 100;
ESAC;
IF ST(0) or SRC = NaN or unsupported format
THEN
#IA
IF FPUControlWord.IM = 1
THEN
C3, C2, C0 ← 111;
FI;
FI;
IF Instruction = FCOMP
THEN
PopRegisterStack;
FI;
IF Instruction = FCOMPP
THEN
PopRegisterStack;
PopRegisterStack;
FI;
FPU Flags Affected
C1
Set to 0.
C0, C2, C3
See table on previous page.
Floating-Point Exceptions
#IS
#IA
Stack underflow occurred.
One or both operands are NaN values or have unsupported formats.
Register is marked empty.
#D
One or both operands are denormal values.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
FCOM/FCOMP/FCOMPP—Compare Floating Point Values
Vol. 2A 3-327
INSTRUCTION SET REFERENCE, A-L
FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DB F0+i
FCOMI ST, ST(i)
Valid
Valid
Compare ST(0) with ST(i) and set status flags accordingly.
DF F0+i
FCOMIP ST, ST(i)
Valid
Valid
Compare ST(0) with ST(i), set status flags accordingly, and
pop register stack.
DB E8+i
FUCOMI ST, ST(i)
Valid
Valid
Compare ST(0) with ST(i), check for ordered values, and set
status flags accordingly.
DF E8+i
FUCOMIP ST, ST(i)
Valid
Valid
Compare ST(0) with ST(i), check for ordered values, set
status flags accordingly, and pop register stack.
Description
Performs an unordered comparison of the contents of registers ST(0) and ST(i) and sets the status flags ZF, PF, and
CF in the EFLAGS register according to the results (see the table below). The sign of zero is ignored for comparisons, so that –0.0 is equal to +0.0.
Table 3-22. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results
Comparison Results*
ZF
PF
CF
ST0 > ST(i)
0
0
0
ST0 < ST(i)
0
0
1
ST0 = ST(i)
1
0
0
Unordered**
1
1
1
NOTES:
* See the IA-32 Architecture Compatibility section below.
** Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.
An unordered comparison checks the class of the numbers being compared (see “FXAM—Examine Floating-Point”
in this chapter). The FUCOMI/FUCOMIP instructions perform the same operations as the FCOMI/FCOMIP instructions. The only difference is that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operand exception
(#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition
code flags to be set to unordered, but do not cause an exception to be generated. The FCOMI/FCOMIP instructions
raise an invalid-operation exception when either or both of the operands are a NaN value of any kind or are in an
unsupported format.
If the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS
register are set only if the exception is masked.
The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions set the OF, SF and AF flags to zero in the EFLAGS register
(regardless of whether an invalid-operation exception is detected).
The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation. To pop the
register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IA-32 Architecture Compatibility
The FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the IA-32 Architecture in the P6 family
processors and are not available in earlier IA-32 processors.
3-328 Vol. 2A
FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, A-L
Operation
CASE (relation of operands) OF
ST(0) > ST(i):
ZF, PF, CF ← 000;
ST(0) < ST(i):
ZF, PF, CF ← 001;
ST(0) = ST(i):
ZF, PF, CF ← 100;
ESAC;
IF Instruction is FCOMI or FCOMIP
THEN
IF ST(0) or ST(i) = NaN or unsupported format
THEN
#IA
IF FPUControlWord.IM = 1
THEN
ZF, PF, CF ← 111;
FI;
FI;
FI;
IF Instruction is FUCOMI or FUCOMIP
THEN
IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format
THEN
ZF, PF, CF ← 111;
ELSE (* ST(0) or ST(i) is SNaN or unsupported format *)
#IA;
IF FPUControlWord.IM = 1
THEN
ZF, PF, CF ← 111;
FI;
FI;
FI;
IF Instruction is FCOMIP or FUCOMIP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1
Set to 0.
C0, C2, C3
Not affected.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
(FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported
formats.
(FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or
have undefined formats. Detection of a QNaN value does not raise an invalid-operand exception.
FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS
Vol. 2A 3-329
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, A-L
FCOS— Cosine
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 FF
FCOS
Valid
Valid
Replace ST(0) with its approximate cosine.
Description
Computes the approximate cosine of the source operand in register ST(0) and stores the result in ST(0). The
source operand must be given in radians and must be within the range −263 to +263. The following table shows the
results obtained when taking the cosine of various classes of numbers.
Table 3-23. FCOS Results
ST(0) SRC
ST(0) DEST
−∞
*
−F
−1 to +1
−0
+1
+0
+1
+F
− 1 to + 1
+∞
*
NaN
NaN
NOTES:
F Means finite floating-point value.
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.
If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in
register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of
range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range −
263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2π.
However, even within the range -263 to +263, inaccurate results can occur because the finite approximation of π
used internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply
FCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3π/8. See the
sections titled “Approximation of Pi” and “Transcendental Instruction Accuracy” in Chapter 8 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, for a discussion of the proper value to use for π in
performing such reductions.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF |ST(0)| < 263
THEN
C2 ← 0;
ST(0) ← FCOS(ST(0)); // approximation of cosine
ELSE (* Source operand is out-of-range *)
C2 ← 1;
FI;
FCOS— Cosine
Vol. 2A 3-331
INSTRUCTION SET REFERENCE, A-L
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
Undefined if C2 is 1.
C2
Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0.
C0, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
Source operand is an SNaN value, ∞, or unsupported format.
#D
Source is a denormal value.
#P
Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-332 Vol. 2A
FCOS— Cosine
INSTRUCTION SET REFERENCE, A-L
FDECSTP—Decrement Stack-Top Pointer
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 F6
FDECSTP
Valid
Valid
Decrement TOP field in FPU status word.
Description
Subtracts one from the TOP field of the FPU status word (decrements the top-of-stack pointer). If the TOP field
contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the
FPU data registers and tag register are not affected.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF TOP = 0
THEN TOP ← 7;
ELSE TOP ← TOP – 1;
FI;
FPU Flags Affected
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.
Floating-Point Exceptions
None.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
FDECSTP—Decrement Stack-Top Pointer
Vol. 2A 3-333
INSTRUCTION SET REFERENCE, A-L
FDIV/FDIVP/FIDIV—Divide
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D8 /6
FDIV m32fp
Valid
Valid
Divide ST(0) by m32fp and store result in ST(0).
DC /6
FDIV m64fp
Valid
Valid
Divide ST(0) by m64fp and store result in ST(0).
D8 F0+i
FDIV ST(0), ST(i)
Valid
Valid
Divide ST(0) by ST(i) and store result in ST(0).
DC F8+i
FDIV ST(i), ST(0)
Valid
Valid
Divide ST(i) by ST(0) and store result in ST(i).
DE F8+i
FDIVP ST(i), ST(0)
Valid
Valid
Divide ST(i) by ST(0), store result in ST(i), and pop the
register stack.
DE F9
FDIVP
Valid
Valid
Divide ST(1) by ST(0), store result in ST(1), and pop
the register stack.
DA /6
FIDIV m32int
Valid
Valid
Divide ST(0) by m32int and store result in ST(0).
DE /6
FIDIV m16int
Valid
Valid
Divide ST(0) by m16int and store result in ST(0).
Description
Divides the destination operand by the source operand and stores the result in the destination location. The destination operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory
location. Source operands in memory can be in single-precision or double-precision floating-point format, word or
doubleword integer format.
The no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0)
register. The one-operand version divides the contents of the ST(0) register by the contents of a memory location
(either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by
the contents of the ST(i) register or vice versa.
The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)
by 1. The no-operand version of the floating-point divide instructions always results in the register stack being
popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.
The FIDIV instructions convert an integer source operand to double extended-precision floating-point format
before performing the division. When the source operand is an integer 0, it is treated as a +0.
If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of
the appropriate sign is stored in the destination operand.
The following table shows the results obtained when dividing various classes of numbers, assuming that neither
overflow nor underflow occurs.
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INSTRUCTION SET REFERENCE, A-L
Table 3-24. FDIV/FDIVP/FIDIV Results
DEST
SRC
−∞
−F
−0
+0
+F
+∞
NaN
−∞
*
+0
+0
−0
−0
*
NaN
−F
+∞
+F
+0
−0
−F
−∞
NaN
−I
+∞
+F
+0
−0
−F
−∞
NaN
−0
+∞
**
*
*
**
−∞
NaN
+0
−∞
**
*
*
**
+∞
NaN
+I
−∞
−F
−0
+0
+F
+∞
NaN
+F
−∞
−F
−0
+0
+F
+∞
NaN
+∞
*
−0
−0
+0
+0
*
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NOTES:
F Means finite floating-point value.
I Means integer.
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.
** Indicates floating-point zero-divide (#Z) exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF SRC = 0
THEN
#Z;
ELSE
IF Instruction is FIDIV
THEN
DEST ← DEST / ConvertToDoubleExtendedPrecisionFP(SRC);
ELSE (* Source operand is floating-point value *)
DEST ← DEST / SRC;
FI;
FI;
IF Instruction = FDIVP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3
FDIV/FDIVP/FIDIV—Divide
Undefined.
Vol. 2A 3-335
INSTRUCTION SET REFERENCE, A-L
Floating-Point Exceptions
#IS
#IA
Stack underflow occurred.
Operand is an SNaN value or unsupported format.
±∞ / ±∞; ±0 / ±0
#D
Source is a denormal value.
#Z
DEST / ±0, where DEST is not equal to ±0.
#U
Result is too small for destination format.
#O
Result is too large for destination format.
#P
Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-336 Vol. 2A
FDIV/FDIVP/FIDIV—Divide
INSTRUCTION SET REFERENCE, A-L
FDIVR/FDIVRP/FIDIVR—Reverse Divide
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D8 /7
FDIVR m32fp
Valid
Valid
Divide m32fp by ST(0) and store result in ST(0).
DC /7
FDIVR m64fp
Valid
Valid
Divide m64fp by ST(0) and store result in ST(0).
D8 F8+i
FDIVR ST(0), ST(i)
Valid
Valid
Divide ST(i) by ST(0) and store result in ST(0).
DC F0+i
FDIVR ST(i), ST(0)
Valid
Valid
Divide ST(0) by ST(i) and store result in ST(i).
DE F0+i
FDIVRP ST(i), ST(0)
Valid
Valid
Divide ST(0) by ST(i), store result in ST(i), and pop the
register stack.
DE F1
FDIVRP
Valid
Valid
Divide ST(0) by ST(1), store result in ST(1), and pop the
register stack.
DA /7
FIDIVR m32int
Valid
Valid
Divide m32int by ST(0) and store result in ST(0).
DE /7
FIDIVR m16int
Valid
Valid
Divide m16int by ST(0) and store result in ST(0).
Description
Divides the source operand by the destination operand and stores the result in the destination location. The destination operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory
location. Source operands in memory can be in single-precision or double-precision floating-point format, word or
doubleword integer format.
These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to
support more efficient coding.
The no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1)
register. The one-operand version divides the contents of a memory location (either a floating-point or an integer
value) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by
the contents of the ST(0) register or vice versa.
The FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)
by 1. The no-operand version of the floating-point divide instructions always results in the register stack being
popped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP.
The FIDIVR instructions convert an integer source operand to double extended-precision floating-point format
before performing the division.
If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of
the appropriate sign is stored in the destination operand.
The following table shows the results obtained when dividing various classes of numbers, assuming that neither
overflow nor underflow occurs.
FDIVR/FDIVRP/FIDIVR—Reverse Divide
Vol. 2A 3-337
INSTRUCTION SET REFERENCE, A-L
Table 3-25. FDIVR/FDIVRP/FIDIVR Results
DEST
SRC
−∞
−F
−0
+0
+F
+∞
−∞
*
+∞
+∞
−∞
−∞
*
NaN
−F
+0
+F
**
**
−F
−0
NaN
−I
+0
+F
**
**
−F
−0
NaN
−0
+0
+0
*
*
−0
−0
NaN
+0
−0
−0
*
*
+0
+0
NaN
+I
−0
−F
**
**
+F
+0
NaN
NaN
+F
−0
−F
**
**
+F
+0
NaN
+∞
*
−∞
−∞
+∞
+∞
*
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NOTES:
F Means finite floating-point value.
I Means integer.
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.
** Indicates floating-point zero-divide (#Z) exception.
When the source operand is an integer 0, it is treated as a +0. This instruction’s operation is the same in non-64-bit
modes and 64-bit mode.
Operation
IF DEST = 0
THEN
#Z;
ELSE
IF Instruction = FIDIVR
THEN
DEST ← ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;
ELSE (* Source operand is floating-point value *)
DEST ← SRC / DEST;
FI;
FI;
IF Instruction = FDIVRP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3
3-338 Vol. 2A
Undefined.
FDIVR/FDIVRP/FIDIVR—Reverse Divide
INSTRUCTION SET REFERENCE, A-L
Floating-Point Exceptions
#IS
#IA
Stack underflow occurred.
Operand is an SNaN value or unsupported format.
±∞ / ±∞; ±0 / ±0
#D
Source is a denormal value.
#Z
SRC / ±0, where SRC is not equal to ±0.
#U
Result is too small for destination format.
#O
Result is too large for destination format.
#P
Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
FDIVR/FDIVRP/FIDIVR—Reverse Divide
Vol. 2A 3-339
INSTRUCTION SET REFERENCE, A-L
FFREE—Free Floating-Point Register
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DD C0+i
FFREE ST(i)
Valid
Valid
Sets tag for ST(i) to empty.
Description
Sets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU
stack-top pointer (TOP) are not affected.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
TAG(i) ← 11B;
FPU Flags Affected
C0, C1, C2, C3 undefined.
Floating-Point Exceptions
None
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-340 Vol. 2A
FFREE—Free Floating-Point Register
INSTRUCTION SET REFERENCE, A-L
FICOM/FICOMP—Compare Integer
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DE /2
FICOM m16int
Valid
Valid
Compare ST(0) with m16int.
DA /2
FICOM m32int
Valid
Valid
Compare ST(0) with m32int.
DE /3
FICOMP m16int
Valid
Valid
Compare ST(0) with m16int and pop stack register.
DA /3
FICOMP m32int
Valid
Valid
Compare ST(0) with m32int and pop stack register.
Description
Compares the value in ST(0) with an integer source operand and sets the condition code flags C0, C2, and C3 in
the FPU status word according to the results (see table below). The integer value is converted to double extendedprecision floating-point format before the comparison is made.
Table 3-26. FICOM/FICOMP Results
Condition
C3
C2
C0
ST(0) > SRC
0
0
0
ST(0) < SRC
0
0
1
ST(0) = SRC
1
0
0
Unordered
1
1
1
These instructions perform an “unordered comparison.” An unordered comparison also checks the class of the
numbers being compared (see “FXAM—Examine Floating-Point” in this chapter). If either operand is a NaN or is in
an undefined format, the condition flags are set to “unordered.”
The sign of zero is ignored, so that –0.0 ← +0.0.
The FICOMP instructions pop the register stack following the comparison. To pop the register stack, the processor
marks the ST(0) register empty and increments the stack pointer (TOP) by 1.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
CASE (relation of operands) OF
ST(0) > SRC:
C3, C2, C0 ← 000;
ST(0) < SRC:
C3, C2, C0 ← 001;
ST(0) = SRC:
C3, C2, C0 ← 100;
Unordered:
C3, C2, C0 ← 111;
ESAC;
IF Instruction = FICOMP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1
Set to 0.
C0, C2, C3
See table on previous page.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
One or both operands are NaN values or have unsupported formats.
#D
One or both operands are denormal values.
FICOM/FICOMP—Compare Integer
Vol. 2A 3-341
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-342 Vol. 2A
FICOM/FICOMP—Compare Integer
INSTRUCTION SET REFERENCE, A-L
FILD—Load Integer
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DF /0
FILD m16int
Valid
Valid
Push m16int onto the FPU register stack.
DB /0
FILD m32int
Valid
Valid
Push m32int onto the FPU register stack.
DF /5
FILD m64int
Valid
Valid
Push m64int onto the FPU register stack.
Description
Converts the signed-integer source operand into double extended-precision floating-point format and pushes the
value onto the FPU register stack. The source operand can be a word, doubleword, or quadword integer. It is loaded
without rounding errors. The sign of the source operand is preserved.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
TOP ← TOP − 1;
ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC);
FPU Flags Affected
C1
Set to 1 if stack overflow occurred; set to 0 otherwise.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack overflow occurred.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
FILD—Load Integer
Vol. 2A 3-343
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-344 Vol. 2A
FILD—Load Integer
INSTRUCTION SET REFERENCE, A-L
FINCSTP—Increment Stack-Top Pointer
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 F7
FINCSTP
Valid
Valid
Increment the TOP field in the FPU status register.
Description
Adds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a
7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data
registers and tag register are not affected. This operation is not equivalent to popping the stack, because the tag
for the previous top-of-stack register is not marked empty.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF TOP = 7
THEN TOP ← 0;
ELSE TOP ← TOP + 1;
FI;
FPU Flags Affected
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.
Floating-Point Exceptions
None
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
FINCSTP—Increment Stack-Top Pointer
Vol. 2A 3-345
INSTRUCTION SET REFERENCE, A-L
FINIT/FNINIT—Initialize Floating-Point Unit
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
9B DB E3
FINIT
Valid
Valid
Initialize FPU after checking for pending unmasked
floating-point exceptions.
DB E3
FNINIT*
Valid
Valid
Initialize FPU without checking for pending unmasked
floating-point exceptions.
NOTES:
* See IA-32 Architecture Compatibility section below.
Description
Sets the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU
control word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared
(no exception flags set, TOP is set to 0). The data registers in the register stack are left unchanged, but they are all
tagged as empty (11B). Both the instruction and data pointers are cleared.
The FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing
the initialization; the FNINIT instruction does not.
The assembler issues two instructions for the FINIT instruction (an FWAIT instruction followed by an FNINIT
instruction), and the processor executes each of these instructions in separately. If an exception is generated for
either of these instructions, the save EIP points to the instruction that caused the exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IA-32 Architecture Compatibility
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual
circumstances) for an FNINIT instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An
FNINIT instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000
processor.
In the Intel387 math coprocessor, the FINIT/FNINIT instruction does not clear the instruction and data pointers.
This instruction affects only the x87 FPU. It does not affect the XMM and MXCSR registers.
Operation
FPUControlWord ← 037FH;
FPUStatusWord ← 0;
FPUTagWord ← FFFFH;
FPUDataPointer ← 0;
FPUInstructionPointer ← 0;
FPULastInstructionOpcode ← 0;
FPU Flags Affected
C0, C1, C2, C3 set to 0.
Floating-Point Exceptions
None
3-346 Vol. 2A
FINIT/FNINIT—Initialize Floating-Point Unit
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
FINIT/FNINIT—Initialize Floating-Point Unit
Vol. 2A 3-347
INSTRUCTION SET REFERENCE, A-L
FIST/FISTP—Store Integer
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DF /2
FIST m16int
Valid
Valid
Store ST(0) in m16int.
DB /2
FIST m32int
Valid
Valid
Store ST(0) in m32int.
DF /3
FISTP m16int
Valid
Valid
Store ST(0) in m16int and pop register stack.
DB /3
FISTP m32int
Valid
Valid
Store ST(0) in m32int and pop register stack.
DF /7
FISTP m64int
Valid
Valid
Store ST(0) in m64int and pop register stack.
Description
The FIST instruction converts the value in the ST(0) register to a signed integer and stores the result in the destination operand. Values can be stored in word or doubleword integer format. The destination operand specifies the
address where the first byte of the destination value is to be stored.
The FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop
the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The FISTP instruction also stores values in quadword integer format.
The following table shows the results obtained when storing various classes of numbers in integer format.
Table 3-27. FIST/FISTP Results
ST(0)
DEST
− ∞ or Value Too Large for DEST Format
*
F ≤ −1
−I
−1 < F < −0
**
−0
0
+0
0
+0 0.0
0
0
0
ST(0) < 0.0
0
0
1
ST(0) = 0.0
1
0
0
Unordered
1
1
1
This instruction performs an “unordered comparison.” An unordered comparison also checks the class of the
numbers being compared (see “FXAM—Examine Floating-Point” in this chapter). If the value in register ST(0) is a
NaN or is in an undefined format, the condition flags are set to “unordered” and the invalid operation exception is
generated.
The sign of zero is ignored, so that (– 0.0 ← +0.0).
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
CASE (relation of operands) OF
Not comparable: C3, C2, C0 ← 111;
ST(0) > 0.0:
C3, C2, C0 ← 000;
ST(0) < 0.0:
C3, C2, C0 ← 001;
ST(0) = 0.0:
C3, C2, C0 ← 100;
ESAC;
FPU Flags Affected
C1
Set to 0.
C0, C2, C3
See Table 3-40.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
The source operand is a NaN value or is in an unsupported format.
#D
The source operand is a denormal value.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
FTST—TEST
Vol. 2A 3-401
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-402 Vol. 2A
FTST—TEST
INSTRUCTION SET REFERENCE, A-L
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
DD E0+i
FUCOM ST(i)
Valid
Valid
Compare ST(0) with ST(i).
DD E1
FUCOM
Valid
Valid
Compare ST(0) with ST(1).
DD E8+i
FUCOMP ST(i)
Valid
Valid
Compare ST(0) with ST(i) and pop register stack.
DD E9
FUCOMP
Valid
Valid
Compare ST(0) with ST(1) and pop register stack.
DA E9
FUCOMPP
Valid
Valid
Compare ST(0) with ST(1) and pop register stack twice.
Description
Performs an unordered comparison of the contents of register ST(0) and ST(i) and sets condition code flags C0, C2,
and C3 in the FPU status word according to the results (see the table below). If no operand is specified, the
contents of registers ST(0) and ST(1) are compared. The sign of zero is ignored, so that –0.0 is equal to +0.0.
Table 3-41. FUCOM/FUCOMP/FUCOMPP Results
Comparison Results*
C3
C2
C0
ST0 > ST(i)
0
0
0
ST0 < ST(i)
0
0
1
ST0 = ST(i)
1
0
0
Unordered
1
1
1
NOTES:
* Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.
An unordered comparison checks the class of the numbers being compared (see “FXAM—Examine Floating-Point”
in this chapter). The FUCOM/FUCOMP/FUCOMPP instructions perform the same operations as the
FCOM/FCOMP/FCOMPP instructions. The only difference is that the FUCOM/FUCOMP/FUCOMPP instructions raise
the invalid-arithmetic-operand exception (#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be
generated. The FCOM/FCOMP/FCOMPP instructions raise an invalid-operation exception when either or both of the
operands are a NaN value of any kind or are in an unsupported format.
As with the FCOM/FCOMP/FCOMPP instructions, if the operation results in an invalid-arithmetic-operand exception
being raised, the condition code flags are set only if the exception is masked.
The FUCOMP instruction pops the register stack following the comparison operation and the FUCOMPP instruction
pops the register stack twice following the comparison operation. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values
Vol. 2A 3-403
INSTRUCTION SET REFERENCE, A-L
Operation
CASE (relation of operands) OF
ST > SRC:
C3, C2, C0 ← 000;
ST < SRC:
C3, C2, C0 ← 001;
ST = SRC:
C3, C2, C0 ← 100;
ESAC;
IF ST(0) or SRC = QNaN, but not SNaN or unsupported format
THEN
C3, C2, C0 ← 111;
ELSE (* ST(0) or SRC is SNaN or unsupported format *)
#IA;
IF FPUControlWord.IM = 1
THEN
C3, C2, C0 ← 111;
FI;
FI;
IF Instruction = FUCOMP
THEN
PopRegisterStack;
FI;
IF Instruction = FUCOMPP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
C0, C2, C3
See Table 3-41.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
One or both operands are SNaN values or have unsupported formats. Detection of a QNaN
value in and of itself does not raise an invalid-operand exception.
#D
One or both operands are denormal values.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
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FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
Same exceptions as in protected mode.
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values
Vol. 2A 3-405
INSTRUCTION SET REFERENCE, A-L
FXAM—Examine Floating-Point
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 E5
FXAM
Valid
Valid
Classify value or number in ST(0).
Description
Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word
to indicate the class of value or number in the register (see the table below).
Table 3-42. FXAM Results
.
Class
C3
C2
C0
Unsupported
0
0
0
NaN
0
0
1
Normal finite number
0
1
0
Infinity
0
1
1
Zero
1
0
0
Empty
1
0
1
Denormal number
1
1
0
The C1 flag is set to the sign of the value in ST(0), regardless of whether the register is empty or full.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
C1 ← sign bit of ST; (* 0 for positive, 1 for negative *)
CASE (class of value or number in ST(0)) OF
Unsupported:C3, C2, C0 ← 000;
NaN:
C3, C2, C0 ← 001;
Normal:
C3, C2, C0 ← 010;
Infinity:
C3, C2, C0 ← 011;
Zero:
C3, C2, C0 ← 100;
Empty:
C3, C2, C0 ← 101;
Denormal:
C3, C2, C0 ← 110;
ESAC;
FPU Flags Affected
C1
Sign of value in ST(0).
C0, C2, C3
See Table 3-42.
Floating-Point Exceptions
None
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
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FXAM—Examine Floating-Point
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
FXAM—Examine Floating-Point
Vol. 2A 3-407
INSTRUCTION SET REFERENCE, A-L
FXCH—Exchange Register Contents
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 C8+i
FXCH ST(i)
Valid
Valid
Exchange the contents of ST(0) and ST(i).
D9 C9
FXCH
Valid
Valid
Exchange the contents of ST(0) and ST(1).
Description
Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and
ST(1) are exchanged.
This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)],
so that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For
example, the following instruction sequence takes the square root of the third register from the top of the register
stack:
FXCH ST(3);
FSQRT;
FXCH ST(3);
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF (Number-of-operands) is 1
THEN
temp ← ST(0);
ST(0) ← SRC;
SRC ← temp;
ELSE
temp ← ST(0);
ST(0) ← ST(1);
ST(1) ← temp;
FI;
FPU Flags Affected
C1
Set to 0.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
3-408 Vol. 2A
FXCH—Exchange Register Contents
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
FXCH—Exchange Register Contents
Vol. 2A 3-409
INSTRUCTION SET REFERENCE, A-L
FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AE /1
M
Valid
Valid
Restore the x87 FPU, MMX, XMM, and MXCSR
register state from m512byte.
M
Valid
N.E.
Restore the x87 FPU, MMX, XMM, and MXCSR
register state from m512byte.
FXRSTOR m512byte
REX.W+ 0F AE /1
FXRSTOR64 m512byte
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Reloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image specified in
the source operand. This data should have been written to memory previously using the FXSAVE instruction, and
in the same format as required by the operating modes. The first byte of the data should be located on a 16-byte
boundary. There are three distinct layouts of the FXSAVE state map: one for legacy and compatibility mode, a
second format for 64-bit mode FXSAVE/FXRSTOR with REX.W=0, and the third format is for 64-bit mode with
FXSAVE64/FXRSTOR64. Table 3-43 shows the layout of the legacy/compatibility mode state information in memory
and describes the fields in the memory image for the FXRSTOR and FXSAVE instructions. Table 3-46 shows the
layout of the 64-bit mode state information when REX.W is set (FXSAVE64/FXRSTOR64). Table 3-47 shows the
layout of the 64-bit mode state information when REX.W is clear (FXSAVE/FXRSTOR).
The state image referenced with an FXRSTOR instruction must have been saved using an FXSAVE instruction or be
in the same format as required by Table 3-43, Table 3-46, or Table 3-47. Referencing a state image saved with an
FSAVE, FNSAVE instruction or incompatible field layout will result in an incorrect state restoration.
The FXRSTOR instruction does not flush pending x87 FPU exceptions. To check and raise exceptions when loading
x87 FPU state information with the FXRSTOR instruction, use an FWAIT instruction after the FXRSTOR instruction.
If the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may not restore the states of the XMM
and MXCSR registers. This behavior is implementation dependent.
If the MXCSR state contains an unmasked exception with a corresponding status flag also set, loading the register
with the FXRSTOR instruction will not result in a SIMD floating-point error condition being generated. Only the next
occurrence of this unmasked exception will result in the exception being generated.
Bits 16 through 32 of the MXCSR register are defined as reserved and should be set to 0. Attempting to write a 1 in
any of these bits from the saved state image will result in a general protection exception (#GP) being generated.
Bytes 464:511 of an FXSAVE image are available for software use. FXRSTOR ignores the content of bytes 464:511
in an FXSAVE state image.
Operation
IF 64-Bit Mode
THEN
(x87 FPU, MMX, XMM15-XMM0, MXCSR) Load(SRC);
ELSE
(x87 FPU, MMX, XMM7-XMM0, MXCSR) ← Load(SRC);
FI;
x87 FPU and SIMD Floating-Point Exceptions
None.
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FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See alignment check exception [#AC] below.)
For an attempt to set reserved bits in MXCSR.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#NM
If CR0.TS[bit 3] = 1.
If CR0.EM[bit 2] = 1.
#UD
If CPUID.01H:EDX.FXSR[bit 24] = 0.
If instruction is preceded by a LOCK prefix.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
For an attempt to set reserved bits in MXCSR.
#NM
If CR0.TS[bit 3] = 1.
If CR0.EM[bit 2] = 1.
#UD
If CPUID.01H:EDX.FXSR[bit 24] = 0.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
#AC
For unaligned memory reference.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State
Vol. 2A 3-411
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
If memory operand is not aligned on a 16-byte boundary, regardless of segment.
For an attempt to set reserved bits in MXCSR.
#PF(fault-code)
For a page fault.
#NM
If CR0.TS[bit 3] = 1.
If CR0.EM[bit 2] = 1.
#UD
If CPUID.01H:EDX.FXSR[bit 24] = 0.
If instruction is preceded by a LOCK prefix.
#AC
3-412 Vol. 2A
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State
INSTRUCTION SET REFERENCE, A-L
FXSAVE—Save x87 FPU, MMX Technology, and SSE State
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AE /0
M
Valid
Valid
Save the x87 FPU, MMX, XMM, and MXCSR
register state to m512byte.
M
Valid
N.E.
Save the x87 FPU, MMX, XMM, and MXCSR
register state to m512byte.
FXSAVE m512byte
REX.W+ 0F AE /0
FXSAVE64 m512byte
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location specified in the destination operand. The content layout of the 512 byte region depends on whether the
processor is operating in non-64-bit operating modes or 64-bit sub-mode of IA-32e mode.
Bytes 464:511 are available to software use. The processor does not write to bytes 464:511 of an FXSAVE area.
The operation of FXSAVE in non-64-bit modes is described first.
Non-64-Bit Mode Operation
Table 3-43 shows the layout of the state information in memory when the processor is operating in legacy modes.
Table 3-43. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR
Memory Region
15
14
Rsvd
13
12
FCS
MXCSR_MASK
11 10
9
8
7
6
FIP[31:0]
FOP
MXCSR
Rsrvd
5
4
Rsvd
FTW
FDS
3
2
FSW
1
0
FCW
FDP[31:0]
0
16
Reserved
ST0/MM0
32
Reserved
ST1/MM1
48
Reserved
ST2/MM2
64
Reserved
ST3/MM3
80
Reserved
ST4/MM4
96
Reserved
ST5/MM5
112
Reserved
ST6/MM6
128
Reserved
ST7/MM7
144
FXSAVE—Save x87 FPU, MMX Technology, and SSE State
XMM0
160
XMM1
176
XMM2
192
XMM3
208
XMM4
224
XMM5
240
XMM6
256
XMM7
272
Reserved
288
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INSTRUCTION SET REFERENCE, A-L
Table 3-43. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR
Memory Region (Contd.)
15
14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
Reserved
304
Reserved
320
Reserved
336
Reserved
352
Reserved
368
Reserved
384
Reserved
400
Reserved
416
Reserved
432
Reserved
448
Available
464
Available
480
Available
496
The destination operand contains the first byte of the memory image, and it must be aligned on a 16-byte
boundary. A misaligned destination operand will result in a general-protection (#GP) exception being generated (or
in some cases, an alignment check exception [#AC]).
The FXSAVE instruction is used when an operating system needs to perform a context switch or when an exception
handler needs to save and examine the current state of the x87 FPU, MMX technology, and/or XMM and MXCSR
registers.
The fields in Table 3-43 are defined in Table 3-44.
Table 3-44. Field Definitions
Field
Definition
FCW
x87 FPU Control Word (16 bits). See Figure 8-6 in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for the layout of the x87 FPU control word.
FSW
x87 FPU Status Word (16 bits). See Figure 8-4 in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for the layout of the x87 FPU status word.
Abridged FTW
x87 FPU Tag Word (8 bits). The tag information saved here is abridged, as described in the following
paragraphs.
FOP
x87 FPU Opcode (16 bits). The lower 11 bits of this field contain the opcode, upper 5 bits are reserved.
See Figure 8-8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for
the layout of the x87 FPU opcode field.
FIP
x87 FPU Instruction Pointer Offset (64 bits). The contents of this field differ depending on the current
addressing mode (32-bit, 16-bit, or 64-bit) of the processor when the FXSAVE instruction was
executed:
32-bit mode — 32-bit IP offset.
16-bit mode — low 16 bits are IP offset; high 16 bits are reserved.
64-bit mode with REX.W — 64-bit IP offset.
64-bit mode without REX.W — 32-bit IP offset.
See “x87 FPU Instruction and Operand (Data) Pointers” in Chapter 8 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for a description of the x87 FPU instruction
pointer.
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INSTRUCTION SET REFERENCE, A-L
Table 3-44. Field Definitions (Contd.)
Field
Definition
FCS
x87 FPU Instruction Pointer Selector (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the
processor deprecates FCS and FDS, and this field is saved as 0000H.
FDP
x87 FPU Instruction Operand (Data) Pointer Offset (64 bits). The contents of this field differ
depending on the current addressing mode (32-bit, 16-bit, or 64-bit) of the processor when the
FXSAVE instruction was executed:
32-bit mode — 32-bit DP offset.
16-bit mode — low 16 bits are DP offset; high 16 bits are reserved.
64-bit mode with REX.W — 64-bit DP offset.
64-bit mode without REX.W — 32-bit DP offset.
See “x87 FPU Instruction and Operand (Data) Pointers” in Chapter 8 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for a description of the x87 FPU operand
pointer.
FDS
x87 FPU Instruction Operand (Data) Pointer Selector (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit
13] = 1, the processor deprecates FCS and FDS, and this field is saved as 0000H.
MXCSR
MXCSR Register State (32 bits). See Figure 10-3 in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for the layout of the MXCSR register. If the OSFXSR bit in control
register CR4 is not set, the FXSAVE instruction may not save this register. This behavior is
implementation dependent.
MXCSR_
MASK
MXCSR_MASK (32 bits). This mask can be used to adjust values written to the MXCSR register,
ensuring that reserved bits are set to 0. Set the mask bits and flags in MXCSR to the mode of
operation desired for SSE and SSE2 SIMD floating-point instructions. See “Guidelines for Writing to the
MXCSR Register” in Chapter 11 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, for instructions for how to determine and use the MXCSR_MASK value.
ST0/MM0 through
ST7/MM7
x87 FPU or MMX technology registers. These 80-bit fields contain the x87 FPU data registers or the
MMX technology registers, depending on the state of the processor prior to the execution of the
FXSAVE instruction. If the processor had been executing x87 FPU instruction prior to the FXSAVE
instruction, the x87 FPU data registers are saved; if it had been executing MMX instructions (or SSE or
SSE2 instructions that operated on the MMX technology registers), the MMX technology registers are
saved. When the MMX technology registers are saved, the high 16 bits of the field are reserved.
XMM0 through XMM7
XMM registers (128 bits per field). If the OSFXSR bit in control register CR4 is not set, the FXSAVE
instruction may not save these registers. This behavior is implementation dependent.
The FXSAVE instruction saves an abridged version of the x87 FPU tag word in the FTW field (unlike the FSAVE
instruction, which saves the complete tag word). The tag information is saved in physical register order (R0
through R7), rather than in top-of-stack (TOS) order. With the FXSAVE instruction, however, only a single bit (1 for
valid or 0 for empty) is saved for each tag. For example, assume that the tag word is currently set as follows:
R7 R6 R5 R4 R3 R2 R1 R0
11 xx xx xx 11 11 11 11
Here, 11B indicates empty stack elements and “xx” indicates valid (00B), zero (01B), or special (10B).
For this example, the FXSAVE instruction saves only the following 8 bits of information:
R7 R6 R5 R4 R3 R2 R1 R0
0 1 1 1 0 0 0 0
Here, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any empty tag.
The operation of the FXSAVE instruction differs from that of the FSAVE instruction, the as follows:
•
FXSAVE instruction does not check for pending unmasked floating-point exceptions. (The FXSAVE operation in
this regard is similar to the operation of the FNSAVE instruction).
•
After the FXSAVE instruction has saved the state of the x87 FPU, MMX technology, XMM, and MXCSR registers,
the processor retains the contents of the registers. Because of this behavior, the FXSAVE instruction cannot be
FXSAVE—Save x87 FPU, MMX Technology, and SSE State
Vol. 2A 3-415
INSTRUCTION SET REFERENCE, A-L
used by an application program to pass a “clean” x87 FPU state to a procedure, since it retains the current
state. To clean the x87 FPU state, an application must explicitly execute an FINIT instruction after an FXSAVE
instruction to reinitialize the x87 FPU state.
•
The format of the memory image saved with the FXSAVE instruction is the same regardless of the current
addressing mode (32-bit or 16-bit) and operating mode (protected, real address, or system management).
This behavior differs from the FSAVE instructions, where the memory image format is different depending on
the addressing mode and operating mode. Because of the different image formats, the memory image saved
with the FXSAVE instruction cannot be restored correctly with the FRSTOR instruction, and likewise the state
saved with the FSAVE instruction cannot be restored correctly with the FXRSTOR instruction.
The FSAVE format for FTW can be recreated from the FTW valid bits and the stored 80-bit FP data (assuming the
stored data was not the contents of MMX technology registers) using Table 3-45.
Table 3-45. Recreating FSAVE Format
Exponent
all 1’s
Exponent
all 0’s
Fraction
all 0’s
J and M
bits
FTW valid bit
0
0
0
0x
1
Special
10
0
0
0
1x
1
Valid
00
0
0
1
00
1
Special
10
0
0
1
10
1
Valid
00
0
1
0
0x
1
Special
10
0
1
0
1x
1
Special
10
0
1
1
00
1
Zero
01
0
1
1
10
1
Special
10
1
0
0
1x
1
Special
10
1
0
0
1x
1
Special
10
1
0
1
00
1
Special
10
1
0
1
10
1
Special
10
0
Empty
11
For all legal combinations above.
x87 FTW
The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the significand. The M-bit is
defined to be the most significant bit of the fractional portion of the significand (i.e., the bit immediately to the right
of the decimal place).
When the M-bit is the most significant bit of the fractional portion of the significand, it must be 0 if the fraction is all
0’s.
IA-32e Mode Operation
In compatibility sub-mode of IA-32e mode, legacy SSE registers, XMM0 through XMM7, are saved according to the
legacy FXSAVE map. In 64-bit mode, all of the SSE registers, XMM0 through XMM15, are saved. Additionally, there
are two different layouts of the FXSAVE map in 64-bit mode, corresponding to FXSAVE64 (which requires
REX.W=1) and FXSAVE (REX.W=0). In the FXSAVE64 map (Table 3-46), the FPU IP and FPU DP pointers are 64-bit
wide. In the FXSAVE map for 64-bit mode (Table 3-47), the FPU IP and FPU DP pointers are 32-bits.
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INSTRUCTION SET REFERENCE, A-L
Table 3-46. Layout of the 64-bit-mode FXSAVE64 Map
(requires REX.W = 1)
15
14
13
12
11
10
9
FIP
MXCSR_MASK
8
7
6
FOP
MXCSR
5
4
Reserved
FTW
FDP
3
2
FSW
1
0
FCW
0
16
Reserved
ST0/MM0
32
Reserved
ST1/MM1
48
Reserved
ST2/MM2
64
Reserved
ST3/MM3
80
Reserved
ST4/MM4
96
Reserved
ST5/MM5
112
Reserved
ST6/MM6
128
Reserved
ST7/MM7
144
FXSAVE—Save x87 FPU, MMX Technology, and SSE State
XMM0
160
XMM1
176
XMM2
192
XMM3
208
XMM4
224
XMM5
240
XMM6
256
XMM7
272
XMM8
288
XMM9
304
XMM10
320
XMM11
336
XMM12
352
XMM13
368
XMM14
384
XMM15
400
Reserved
416
Reserved
432
Reserved
448
Available
464
Available
480
Available
496
Vol. 2A 3-417
INSTRUCTION SET REFERENCE, A-L
Table 3-47. Layout of the 64-bit-mode FXSAVE Map (REX.W = 0)
15
14
Reserved
13
12
FCS
MXCSR_MASK
3-418 Vol. 2A
11
10
9
8
7
6
FIP[31:0]
FOP
MXCSR
Reserved
5
4
Reserved
FTW
FDS
3
2
FSW
1
0
FCW
FDP[31:0]
0
16
Reserved
ST0/MM0
32
Reserved
ST1/MM1
48
Reserved
ST2/MM2
64
Reserved
ST3/MM3
80
Reserved
ST4/MM4
96
Reserved
ST5/MM5
112
Reserved
ST6/MM6
128
Reserved
ST7/MM7
144
XMM0
160
XMM1
176
XMM2
192
XMM3
208
XMM4
224
XMM5
240
XMM6
256
XMM7
272
XMM8
288
XMM9
304
XMM10
320
XMM11
336
XMM12
352
XMM13
368
XMM14
384
XMM15
400
Reserved
416
Reserved
432
Reserved
448
Available
464
Available
480
Available
496
FXSAVE—Save x87 FPU, MMX Technology, and SSE State
INSTRUCTION SET REFERENCE, A-L
Operation
IF 64-Bit Mode
THEN
IF REX.W = 1
THEN
DEST ← Save64BitPromotedFxsave(x87 FPU, MMX, XMM15-XMM0,
MXCSR);
ELSE
DEST ← Save64BitDefaultFxsave(x87 FPU, MMX, XMM15-XMM0, MXCSR);
FI;
ELSE
DEST ← SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);
FI;
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See the
description of the alignment check exception [#AC] below.)
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#NM
If CR0.TS[bit 3] = 1.
If CR0.EM[bit 2] = 1.
#UD
If CPUID.01H:EDX.FXSR[bit 24] = 0.
#UD
If the LOCK prefix is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NM
If CR0.TS[bit 3] = 1.
If CR0.EM[bit 2] = 1.
#UD
If CPUID.01H:EDX.FXSR[bit 24] = 0.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
#AC
For unaligned memory reference.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
FXSAVE—Save x87 FPU, MMX Technology, and SSE State
Vol. 2A 3-419
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#PF(fault-code)
For a page fault.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:EDX.FXSR[bit 24] = 0.
If CR0.EM[bit 2] = 1.
If the LOCK prefix is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
Implementation Note
The order in which the processor signals general-protection (#GP) and page-fault (#PF) exceptions when they both
occur on an instruction boundary is given in Table 5-2 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B. This order vary for FXSAVE for different processor implementations.
3-420 Vol. 2A
FXSAVE—Save x87 FPU, MMX Technology, and SSE State
INSTRUCTION SET REFERENCE, A-L
FXTRACT—Extract Exponent and Significand
Opcode/
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 F4
Valid
Valid
Separate value in ST(0) into exponent and significand, store
exponent in ST(0), and push the significand onto the register
stack.
FXTRACT
Description
Separates the source value in the ST(0) register into its exponent and significand, stores the exponent in ST(0),
and pushes the significand onto the register stack. Following this operation, the new top-of-stack register ST(0)
contains the value of the original significand expressed as a floating-point value. The sign and significand of this
value are the same as those found in the source operand, and the exponent is 3FFFH (biased value for a true exponent of zero). The ST(1) register contains the value of the original operand’s true (unbiased) exponent expressed
as a floating-point value. (The operation performed by this instruction is a superset of the IEEE-recommended
logb(x) function.)
This instruction and the F2XM1 instruction are useful for performing power and range scaling operations. The
FXTRACT instruction is also useful for converting numbers in double extended-precision floating-point format to
decimal representations (e.g., for printing or displaying).
If the floating-point zero-divide exception (#Z) is masked and the source operand is zero, an exponent value of –
∞ is stored in register ST(1) and 0 with the sign of the source operand is stored in register ST(0).
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
TEMP ← Significand(ST(0));
ST(0) ← Exponent(ST(0));
TOP← TOP − 1;
ST(0) ← TEMP;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow or overflow occurred.
#IA
Source operand is an SNaN value or unsupported format.
#Z
ST(0) operand is ±0.
#D
Source operand is a denormal value.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
FXTRACT—Extract Exponent and Significand
Vol. 2A 3-421
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-422 Vol. 2A
FXTRACT—Extract Exponent and Significand
INSTRUCTION SET REFERENCE, A-L
FYL2X—Compute y ∗ log2x
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 F1
FYL2X
Valid
Valid
Replace ST(1) with (ST(1) ∗ log2ST(0)) and pop the
register stack.
Description
Computes (ST(1) ∗ log2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source
operand in ST(0) must be a non-zero positive number.
The following table shows the results obtained when taking the log of various classes of numbers, assuming that
neither overflow nor underflow occurs.
Table 3-48. FYL2X Results
ST(0)
ST(1)
−∞
−F
±0
+0<+F<+1
−∞
*
*
+∞
+∞
*
−∞
−∞
NaN
−F
*
*
**
+F
−0
−F
−∞
NaN
−0
*
*
*
+0
−0
−0
*
NaN
+0
*
*
*
−0
+0
+0
*
NaN
+F
*
*
**
−F
+0
+F
+∞
NaN
+∞
*
*
∞
−∞
*
+∞
+∞
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
−
+1
+F>+1
+∞
NaN
NOTES:
F Means finite floating-point value.
* Indicates floating-point invalid-operation (#IA) exception.
** Indicates floating-point zero-divide (#Z) exception.
If the divide-by-zero exception is masked and register ST(0) contains ±0, the instruction returns ∞ with a sign that
is the opposite of the sign of the source operand in register ST(1).
The FYL2X instruction is designed with a built-in multiplication to optimize the calculation of logarithms with an
arbitrary positive base (b):
logbx ← (log2b)–1 ∗ log2x
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
ST(1) ← ST(1) ∗ log2ST(0);
PopRegisterStack;
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3
FYL2X—Compute y * log2x
Undefined.
Vol. 2A 3-423
INSTRUCTION SET REFERENCE, A-L
Floating-Point Exceptions
#IS
#IA
Stack underflow occurred.
Either operand is an SNaN or unsupported format.
Source operand in register ST(0) is a negative finite value
(not -0).
#Z
Source operand in register ST(0) is ±0.
#D
Source operand is a denormal value.
#U
Result is too small for destination format.
#O
Result is too large for destination format.
#P
Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-424 Vol. 2A
FYL2X—Compute y * log2x
INSTRUCTION SET REFERENCE, A-L
FYL2XP1—Compute y ∗ log2(x +1)
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 F9
FYL2XP1
Valid
Valid
Replace ST(1) with ST(1) ∗ log2(ST(0) + 1.0) and pop the
register stack.
Description
Computes (ST(1) ∗ log2(ST(0) + 1.0)), stores the result in register ST(1), and pops the FPU register stack. The
source operand in ST(0) must be in the range:
– ( 1 – 2 ⁄ 2 ) )to ( 1 – 2 ⁄ 2 )
The source operand in ST(1) can range from −∞ to +∞. If the ST(0) operand is outside of its acceptable range, the
result is undefined and software should not rely on an exception being generated. Under some circumstances
exceptions may be generated when ST(0) is out of range, but this behavior is implementation specific and not
guaranteed.
The following table shows the results obtained when taking the log epsilon of various classes of numbers, assuming
that underflow does not occur.
Table 3-49. FYL2XP1 Results
ST(0)
ST(1)
−(1 − ( 2 ⁄ 2 )) to −0
-0
+0
+0 to +(1 - ( 2 ⁄ 2 ))
NaN
−∞
+∞
*
*
−∞
NaN
−F
+F
+0
-0
−F
NaN
−0
+0
+0
-0
−0
NaN
+0
−0
−0
+0
+0
NaN
+F
−F
−0
+0
+F
NaN
+∞
−∞
*
*
+∞
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NOTES:
F Means finite floating-point value.
* Indicates floating-point invalid-operation (#IA) exception.
This instruction provides optimal accuracy for values of epsilon [the value in register ST(0)] that are close to 0. For
small epsilon (ε) values, more significant digits can be retained by using the FYL2XP1 instruction than by using
(ε+1) as an argument to the FYL2X instruction. The (ε+1) expression is commonly found in compound interest and
annuity calculations. The result can be simply converted into a value in another logarithm base by including a scale
factor in the ST(1) source operand. The following equation is used to calculate the scale factor for a particular logarithm base, where n is the logarithm base desired for the result of the FYL2XP1 instruction:
scale factor ← logn 2
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
ST(1) ← ST(1) ∗ log2(ST(0) + 1.0);
PopRegisterStack;
FYL2XP1—Compute y * log2(x +1)
Vol. 2A 3-425
INSTRUCTION SET REFERENCE, A-L
FPU Flags Affected
C1
Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3
Undefined.
Floating-Point Exceptions
#IS
Stack underflow occurred.
#IA
Either operand is an SNaN value or unsupported format.
#D
Source operand is a denormal value.
#U
Result is too small for destination format.
#O
Result is too large for destination format.
#P
Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#NM
CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF
If there is a pending x87 FPU exception.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-426 Vol. 2A
FYL2XP1—Compute y * log2(x +1)
INSTRUCTION SET REFERENCE, A-L
HADDPD—Packed Double-FP Horizontal Add
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 7C /r
RM
V/V
SSE3
Horizontal add packed double-precision
floating-point values from xmm2/m128 to
xmm1.
RVM V/V
AVX
Horizontal add packed double-precision
floating-point values from xmm2 and
xmm3/mem.
RVM V/V
AVX
Horizontal add packed double-precision
floating-point values from ymm2 and
ymm3/mem.
HADDPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 7C /r
VHADDPD xmm1,xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 7C /r
VHADDPD ymm1, ymm2, ymm3/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Adds the double-precision floating-point values in the high and low quadwords of the destination operand and
stores the result in the low quadword of the destination operand.
Adds the double-precision floating-point values in the high and low quadwords of the source operand and stores the
result in the high quadword of the destination operand.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
See Figure 3-16 for HADDPD; see Figure 3-17 for VHADDPD.
HADDPD xmm1, xmm2/m128
[127:64]
[63:0]
xmm2
/m128
[127:64]
[63:0]
xmm1
xmm2/m128[63:0] +
xmm2/m128[127:64]
xmm1[63:0] + xmm1[127:64]
Result:
xmm1
[127:64]
[63:0]
OM15993
Figure 3-16. HADDPD—Packed Double-FP Horizontal Add
HADDPD—Packed Double-FP Horizontal Add
Vol. 2A 3-427
INSTRUCTION SET REFERENCE, A-L
SRC1
X3
X2
X1
X0
SRC2
Y3
Y2
Y1
Y0
DEST
Y2 + Y3
X2 + X3
Y0 + Y1
X0 + X1
Figure 3-17. VHADDPD operation
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Operation
HADDPD (128-bit Legacy SSE version)
DEST[63:0] SRC1[127:64] + SRC1[63:0]
DEST[127:64] SRC2[127:64] + SRC2[63:0]
DEST[VLMAX-1:128] (Unmodified)
VHADDPD (VEX.128 encoded version)
DEST[63:0] SRC1[127:64] + SRC1[63:0]
DEST[127:64] SRC2[127:64] + SRC2[63:0]
DEST[VLMAX-1:128] 0
VHADDPD (VEX.256 encoded version)
DEST[63:0] SRC1[127:64] + SRC1[63:0]
DEST[127:64] SRC2[127:64] + SRC2[63:0]
DEST[191:128] SRC1[255:192] + SRC1[191:128]
DEST[255:192] SRC2[255:192] + SRC2[191:128]
Intel C/C++ Compiler Intrinsic Equivalent
VHADDPD: __m256d _mm256_hadd_pd (__m256d a, __m256d b);
HADDPD:
__m128d _mm_hadd_pd (__m128d a, __m128d b);
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a generalprotection exception (#GP) will be generated.
3-428 Vol. 2A
HADDPD—Packed Double-FP Horizontal Add
INSTRUCTION SET REFERENCE, A-L
Numeric Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
See Exceptions Type 2.
HADDPD—Packed Double-FP Horizontal Add
Vol. 2A 3-429
INSTRUCTION SET REFERENCE, A-L
HADDPS—Packed Single-FP Horizontal Add
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
F2 0F 7C /r
RM
V/V
SSE3
Horizontal add packed single-precision
floating-point values from xmm2/m128 to
xmm1.
RVM V/V
AVX
Horizontal add packed single-precision
floating-point values from xmm2 and
xmm3/mem.
RVM V/V
AVX
Horizontal add packed single-precision
floating-point values from ymm2 and
ymm3/mem.
HADDPS xmm1, xmm2/m128
VEX.NDS.128.F2.0F.WIG 7C /r
VHADDPS xmm1, xmm2, xmm3/m128
VEX.NDS.256.F2.0F.WIG 7C /r
VHADDPS ymm1, ymm2, ymm3/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores
the result in the first dword of the destination operand.
Adds single-precision floating-point values in the third and fourth dword of the destination operand and stores the
result in the second dword of the destination operand.
Adds single-precision floating-point values in the first and second dword of the source operand and stores the
result in the third dword of the destination operand.
Adds single-precision floating-point values in the third and fourth dword of the source operand and stores the result
in the fourth dword of the destination operand.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
3-430 Vol. 2A
HADDPS—Packed Single-FP Horizontal Add
INSTRUCTION SET REFERENCE, A-L
See Figure 3-18 for HADDPS; see Figure 3-19 for VHADDPS.
HADDPS xmm1, xmm2/m128
[127:96]
[95:64]
[63:32]
[31:0]
xmm2/
m128
[127:96]
[95:64]
[63:32]
[31:0]
xmm1
xmm2/m128
[95:64] + xmm2/
m128[127:96]
xmm2/m128
[31:0] + xmm2/
m128[63:32]
xmm1[95:64] +
xmm1[127:96]
xmm1[31:0] +
xmm1[63:32]
[127:96]
[95:64]
[63:32]
RESULT:
xmm1
[31:0]
OM15994
Figure 3-18. HADDPS—Packed Single-FP Horizontal Add
SRC1
X7
X6
X5
X4
X3
X2
X1
X0
SRC2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y2+Y3
Y0+Y1
X2+X3
X0+X1
DEST Y6+Y7
Y4+Y5
X6+X7
X4+X5
Figure 3-19. VHADDPS operation
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
HADDPS—Packed Single-FP Horizontal Add
Vol. 2A 3-431
INSTRUCTION SET REFERENCE, A-L
Operation
HADDPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[63:32] + SRC1[31:0]
DEST[63:32] SRC1[127:96] + SRC1[95:64]
DEST[95:64] SRC2[63:32] + SRC2[31:0]
DEST[127:96] SRC2[127:96] + SRC2[95:64]
DEST[VLMAX-1:128] (Unmodified)
VHADDPS (VEX.128 encoded version)
DEST[31:0] SRC1[63:32] + SRC1[31:0]
DEST[63:32] SRC1[127:96] + SRC1[95:64]
DEST[95:64] SRC2[63:32] + SRC2[31:0]
DEST[127:96] SRC2[127:96] + SRC2[95:64]
DEST[VLMAX-1:128] 0
VHADDPS (VEX.256 encoded version)
DEST[31:0] SRC1[63:32] + SRC1[31:0]
DEST[63:32] SRC1[127:96] + SRC1[95:64]
DEST[95:64] SRC2[63:32] + SRC2[31:0]
DEST[127:96] SRC2[127:96] + SRC2[95:64]
DEST[159:128] SRC1[191:160] + SRC1[159:128]
DEST[191:160] SRC1[255:224] + SRC1[223:192]
DEST[223:192] SRC2[191:160] + SRC2[159:128]
DEST[255:224] SRC2[255:224] + SRC2[223:192]
Intel C/C++ Compiler Intrinsic Equivalent
HADDPS:
__m128 _mm_hadd_ps (__m128 a, __m128 b);
VHADDPS:
__m256 _mm256_hadd_ps (__m256 a, __m256 b);
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a generalprotection exception (#GP) will be generated.
Numeric Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
See Exceptions Type 2.
3-432 Vol. 2A
HADDPS—Packed Single-FP Horizontal Add
INSTRUCTION SET REFERENCE, A-L
HLT—Halt
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F4
HLT
NP
Valid
Valid
Halt
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and
SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution. If an
interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer
(CS:EIP) points to the instruction following the HLT instruction.
When a HLT instruction is executed on an Intel 64 or IA-32 processor supporting Intel Hyper-Threading Technology,
only the logical processor that executes the instruction is halted. The other logical processors in the physical
processor remain active, unless they are each individually halted by executing a HLT instruction.
The HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode,
the privilege level of a program or procedure must be 0 to execute the HLT instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
Enter Halt state;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
None.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
HLT—Halt
Vol. 2A 3-433
INSTRUCTION SET REFERENCE, A-L
HSUBPD—Packed Double-FP Horizontal Subtract
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 7D /r
RM
V/V
SSE3
Horizontal subtract packed double-precision
floating-point values from xmm2/m128 to
xmm1.
VEX.NDS.128.66.0F.WIG 7D /r
VHSUBPD xmm1,xmm2, xmm3/m128
RVM V/V
AVX
Horizontal subtract packed double-precision
floating-point values from xmm2 and
xmm3/mem.
VEX.NDS.256.66.0F.WIG 7D /r
VHSUBPD ymm1, ymm2, ymm3/m256
RVM V/V
AVX
Horizontal subtract packed double-precision
floating-point values from ymm2 and
ymm3/mem.
HSUBPD xmm1, xmm2/m128
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
The HSUBPD instruction subtracts horizontally the packed DP FP numbers of both operands.
Subtracts the double-precision floating-point value in the high quadword of the destination operand from the low
quadword of the destination operand and stores the result in the low quadword of the destination operand.
Subtracts the double-precision floating-point value in the high quadword of the source operand from the low quadword of the source operand and stores the result in the high quadword of the destination operand.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
See Figure 3-20 for HSUBPD; see Figure 3-21 for VHSUBPD.
HSUBPD xmm1, xmm2/m128
[127:64]
[63:0]
xmm2
/m128
[127:64]
[63:0]
xmm1
xmm2/m128[63:0] xmm2/m128[127:64]
xmm1[63:0] - xmm1[127:64]
Result:
xmm1
[127:64]
[63:0]
OM15995
Figure 3-20. HSUBPD—Packed Double-FP Horizontal Subtract
3-434 Vol. 2A
HSUBPD—Packed Double-FP Horizontal Subtract
INSTRUCTION SET REFERENCE, A-L
SRC1
X3
X2
X1
X0
SRC2
Y3
Y2
Y1
Y0
DEST
Y2 - Y3
X2 - X3
Y0 - Y1
X0 - X1
Figure 3-21. VHSUBPD operation
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Operation
HSUBPD (128-bit Legacy SSE version)
DEST[63:0] SRC1[63:0] - SRC1[127:64]
DEST[127:64] SRC2[63:0] - SRC2[127:64]
DEST[VLMAX-1:128] (Unmodified)
VHSUBPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] - SRC1[127:64]
DEST[127:64] SRC2[63:0] - SRC2[127:64]
DEST[VLMAX-1:128] 0
VHSUBPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] - SRC1[127:64]
DEST[127:64] SRC2[63:0] - SRC2[127:64]
DEST[191:128] SRC1[191:128] - SRC1[255:192]
DEST[255:192] SRC2[191:128] - SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
HSUBPD:
__m128d _mm_hsub_pd(__m128d a, __m128d b)
VHSUBPD:
__m256d _mm256_hsub_pd (__m256d a, __m256d b);
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a generalprotection exception (#GP) will be generated.
Numeric Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
HSUBPD—Packed Double-FP Horizontal Subtract
Vol. 2A 3-435
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
See Exceptions Type 2.
3-436 Vol. 2A
HSUBPD—Packed Double-FP Horizontal Subtract
INSTRUCTION SET REFERENCE, A-L
HSUBPS—Packed Single-FP Horizontal Subtract
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
F2 0F 7D /r
RM
V/V
SSE3
Horizontal subtract packed single-precision
floating-point values from xmm2/m128 to
xmm1.
RVM V/V
AVX
Horizontal subtract packed single-precision
floating-point values from xmm2 and
xmm3/mem.
RVM V/V
AVX
Horizontal subtract packed single-precision
floating-point values from ymm2 and
ymm3/mem.
HSUBPS xmm1, xmm2/m128
VEX.NDS.128.F2.0F.WIG 7D /r
VHSUBPS xmm1, xmm2, xmm3/m128
VEX.NDS.256.F2.0F.WIG 7D /r
VHSUBPS ymm1, ymm2, ymm3/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Subtracts the single-precision floating-point value in the second dword of the destination operand from the first
dword of the destination operand and stores the result in the first dword of the destination operand.
Subtracts the single-precision floating-point value in the fourth dword of the destination operand from the third
dword of the destination operand and stores the result in the second dword of the destination operand.
Subtracts the single-precision floating-point value in the second dword of the source operand from the first dword
of the source operand and stores the result in the third dword of the destination operand.
Subtracts the single-precision floating-point value in the fourth dword of the source operand from the third dword
of the source operand and stores the result in the fourth dword of the destination operand.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
See Figure 3-22 for HSUBPS; see Figure 3-23 for VHSUBPS.
HSUBPS—Packed Single-FP Horizontal Subtract
Vol. 2A 3-437
INSTRUCTION SET REFERENCE, A-L
HSUBPS xmm1, xmm2/m128
[127:96]
[95:64]
[63:32]
[31:0]
xmm2/
m128
[127:96]
[95:64]
[63:32]
[31:0]
xmm1
xmm2/m128
[95:64] - xmm2/
m128[127:96]
xmm2/m128
[31:0] - xmm2/
m128[63:32]
xmm1[95:64] xmm1[127:96]
xmm1[31:0] xmm1[63:32]
[127:96]
[95:64]
[63:32]
RESULT:
xmm1
[31:0]
OM15996
Figure 3-22. HSUBPS—Packed Single-FP Horizontal Subtract
SRC1
X7
X6
X5
X4
X3
X2
X1
X0
SRC2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y4-Y5
X6-X7
X4-X5
Y2-Y3
Y0-Y1
X2-X3
X0-X1
DEST Y6-Y7
Figure 3-23. VHSUBPS operation
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
3-438 Vol. 2A
HSUBPS—Packed Single-FP Horizontal Subtract
INSTRUCTION SET REFERENCE, A-L
Operation
HSUBPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] - SRC1[63:32]
DEST[63:32] SRC1[95:64] - SRC1[127:96]
DEST[95:64] SRC2[31:0] - SRC2[63:32]
DEST[127:96] SRC2[95:64] - SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VHSUBPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] - SRC1[63:32]
DEST[63:32] SRC1[95:64] - SRC1[127:96]
DEST[95:64] SRC2[31:0] - SRC2[63:32]
DEST[127:96] SRC2[95:64] - SRC2[127:96]
DEST[VLMAX-1:128] 0
VHSUBPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] - SRC1[63:32]
DEST[63:32] SRC1[95:64] - SRC1[127:96]
DEST[95:64] SRC2[31:0] - SRC2[63:32]
DEST[127:96] SRC2[95:64] - SRC2[127:96]
DEST[159:128] SRC1[159:128] - SRC1[191:160]
DEST[191:160] SRC1[223:192] - SRC1[255:224]
DEST[223:192] SRC2[159:128] - SRC2[191:160]
DEST[255:224] SRC2[223:192] - SRC2[255:224]
Intel C/C++ Compiler Intrinsic Equivalent
HSUBPS:
__m128 _mm_hsub_ps(__m128 a, __m128 b);
VHSUBPS: __m256 _mm256_hsub_ps (__m256 a, __m256 b);
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a generalprotection exception (#GP) will be generated.
Numeric Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
See Exceptions Type 2.
HSUBPS—Packed Single-FP Horizontal Subtract
Vol. 2A 3-439
INSTRUCTION SET REFERENCE, A-L
IDIV—Signed Divide
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F6 /7
IDIV r/m8
M
Valid
Valid
Signed divide AX by r/m8, with result stored in:
AL ← Quotient, AH ← Remainder.
REX + F6 /7
IDIV r/m8*
M
Valid
N.E.
Signed divide AX by r/m8, with result stored in
AL ← Quotient, AH ← Remainder.
F7 /7
IDIV r/m16
M
Valid
Valid
Signed divide DX:AX by r/m16, with result
stored in AX ← Quotient, DX ← Remainder.
F7 /7
IDIV r/m32
M
Valid
Valid
Signed divide EDX:EAX by r/m32, with result
stored in EAX ← Quotient, EDX ← Remainder.
REX.W + F7 /7
IDIV r/m64
M
Valid
N.E.
Signed divide RDX:RAX by r/m64, with result
stored in RAX ← Quotient, RDX ← Remainder.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Divides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the source operand (divisor) and stores the
result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a
memory location. The action of this instruction depends on the operand size (dividend/divisor).
Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is
applied, the instruction divides the signed value in RDX:RAX by the source operand. RAX contains a 64-bit
quotient; RDX contains a 64-bit remainder.
See the summary chart at the beginning of this section for encoding data and limits. See Table 3-50.
Table 3-50. IDIV Results
Operand Size
Dividend
Divisor
Quotient
Remainder
Quotient Range
Word/byte
AX
r/m8
AL
AH
−128 to +127
Doubleword/word
DX:AX
r/m16
AX
DX
−32,768 to +32,767
Quadword/doubleword
EDX:EAX
r/m32
EAX
EDX
−231 to 231 − 1
Doublequadword/ quadword
RDX:RAX
r/m64
RAX
RDX
−263 to 263 − 1
3-440 Vol. 2A
IDIV—Signed Divide
INSTRUCTION SET REFERENCE, A-L
Operation
IF SRC = 0
THEN #DE; (* Divide error *)
FI;
IF OperandSize = 8 (* Word/byte operation *)
THEN
temp ← AX / SRC; (* Signed division *)
IF (temp > 7FH) or (temp < 80H)
(* If a positive result is greater than 7FH or a negative result is less than 80H *)
THEN #DE; (* Divide error *)
ELSE
AL ← temp;
AH ← AX SignedModulus SRC;
FI;
ELSE IF OperandSize = 16 (* Doubleword/word operation *)
THEN
temp ← DX:AX / SRC; (* Signed division *)
IF (temp > 7FFFH) or (temp < 8000H)
(* If a positive result is greater than 7FFFH
or a negative result is less than 8000H *)
THEN
#DE; (* Divide error *)
ELSE
AX ← temp;
DX ← DX:AX SignedModulus SRC;
FI;
FI;
ELSE IF OperandSize = 32 (* Quadword/doubleword operation *)
temp ← EDX:EAX / SRC; (* Signed division *)
IF (temp > 7FFFFFFFH) or (temp < 80000000H)
(* If a positive result is greater than 7FFFFFFFH
or a negative result is less than 80000000H *)
THEN
#DE; (* Divide error *)
ELSE
EAX ← temp;
EDX ← EDXE:AX SignedModulus SRC;
FI;
FI;
ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)
temp ← RDX:RAX / SRC; (* Signed division *)
IF (temp > 7FFFFFFFFFFFFFFFH) or (temp < 8000000000000000H)
(* If a positive result is greater than 7FFFFFFFFFFFFFFFH
or a negative result is less than 8000000000000000H *)
THEN
#DE; (* Divide error *)
ELSE
RAX ← temp;
RDX ← RDE:RAX SignedModulus SRC;
FI;
FI;
FI;
IDIV—Signed Divide
Vol. 2A 3-441
INSTRUCTION SET REFERENCE, A-L
Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are undefined.
Protected Mode Exceptions
#DE
If the source operand (divisor) is 0.
The signed result (quotient) is too large for the destination.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#DE
If the source operand (divisor) is 0.
The signed result (quotient) is too large for the destination.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#DE
If the source operand (divisor) is 0.
The signed result (quotient) is too large for the destination.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#DE
If the source operand (divisor) is 0
If the quotient is too large for the designated register.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-442 Vol. 2A
IDIV—Signed Divide
INSTRUCTION SET REFERENCE, A-L
IMUL—Signed Multiply
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F6 /5
IMUL r/m8*
M
Valid
Valid
AX← AL ∗ r/m byte.
F7 /5
IMUL r/m16
M
Valid
Valid
DX:AX ← AX ∗ r/m word.
F7 /5
IMUL r/m32
M
Valid
Valid
EDX:EAX ← EAX ∗ r/m32.
REX.W + F7 /5
IMUL r/m64
M
Valid
N.E.
RDX:RAX ← RAX ∗ r/m64.
0F AF /r
IMUL r16, r/m16
RM
Valid
Valid
word register ← word register ∗ r/m16.
0F AF /r
IMUL r32, r/m32
RM
Valid
Valid
doubleword register ← doubleword register ∗
r/m32.
REX.W + 0F AF /r
IMUL r64, r/m64
RM
Valid
N.E.
Quadword register ← Quadword register ∗
r/m64.
6B /r ib
IMUL r16, r/m16, imm8
RMI
Valid
Valid
word register ← r/m16 ∗ sign-extended
immediate byte.
6B /r ib
IMUL r32, r/m32, imm8
RMI
Valid
Valid
doubleword register ← r/m32 ∗ signextended immediate byte.
REX.W + 6B /r ib
IMUL r64, r/m64, imm8
RMI
Valid
N.E.
Quadword register ← r/m64 ∗ sign-extended
immediate byte.
69 /r iw
IMUL r16, r/m16, imm16
RMI
Valid
Valid
word register ← r/m16 ∗ immediate word.
69 /r id
IMUL r32, r/m32, imm32
RMI
Valid
Valid
doubleword register ← r/m32 ∗ immediate
doubleword.
REX.W + 69 /r id
IMUL r64, r/m64, imm32
RMI
Valid
N.E.
Quadword register ← r/m64 ∗ immediate
doubleword.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r, w)
NA
NA
NA
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8/16/32
NA
Description
Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of
operands.
•
One-operand form — This form is identical to that used by the MUL instruction. Here, the source operand (in
a general-purpose register or memory location) is multiplied by the value in the AL, AX, EAX, or RAX register
(depending on the operand size) and the product (twice the size of the input operand) is stored in the AX,
DX:AX, EDX:EAX, or RDX:RAX registers, respectively.
•
Two-operand form — With this form the destination operand (the first operand) is multiplied by the source
operand (second operand). The destination operand is a general-purpose register and the source operand is an
immediate value, a general-purpose register, or a memory location. The intermediate product (twice the size of
the input operand) is truncated and stored in the destination operand location.
•
Three-operand form — This form requires a destination operand (the first operand) and two source operands
(the second and the third operands). Here, the first source operand (which can be a general-purpose register
or a memory location) is multiplied by the second source operand (an immediate value). The intermediate
product (twice the size of the first source operand) is truncated and stored in the destination operand (a
general-purpose register).
IMUL—Signed Multiply
Vol. 2A 3-443
INSTRUCTION SET REFERENCE, A-L
When an immediate value is used as an operand, it is sign-extended to the length of the destination operand
format.
The CF and OF flags are set when the signed integer value of the intermediate product differs from the sign
extended operand-size-truncated product, otherwise the CF and OF flags are cleared.
The three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length
of the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and
three- operand forms, however, the result is truncated to the length of the destination before it is stored in the
destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits
are lost.
The two- and three-operand forms may also be used with unsigned operands because the lower half of the product
is the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to
determine if the upper half of the result is non-zero.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. Use of REX.W modifies the three
forms of the instruction as follows.
•
One-operand form —The source operand (in a 64-bit general-purpose register or memory location) is
multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers.
•
Two-operand form — The source operand is promoted to 64 bits if it is a register or a memory location. The
destination operand is promoted to 64 bits.
•
Three-operand form — The first source operand (either a register or a memory location) and destination
operand are promoted to 64 bits. If the source operand is an immediate, it is sign extended to 64 bits.
Operation
IF (NumberOfOperands = 1)
THEN IF (OperandSize = 8)
THEN
TMP_XP ← AL ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *);
AX ← TMP_XP[15:0];
IF SignExtend(TMP_XP[7:0]) = TMP_XP
THEN CF ← 0; OF ← 0;
ELSE CF ← 1; OF ← 1; FI;
ELSE IF OperandSize = 16
THEN
TMP_XP ← AX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)
DX:AX ← TMP_XP[31:0];
IF SignExtend(TMP_XP[15:0]) = TMP_XP
THEN CF ← 0; OF ← 0;
ELSE CF ← 1; OF ← 1; FI;
ELSE IF OperandSize = 32
THEN
TMP_XP ← EAX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC*)
EDX:EAX ← TMP_XP[63:0];
IF SignExtend(TMP_XP[31:0]) = TMP_XP
THEN CF ← 0; OF ← 0;
ELSE CF ← 1; OF ← 1; FI;
ELSE (* OperandSize = 64 *)
TMP_XP ← RAX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)
EDX:EAX ← TMP_XP[127:0];
IF SignExtend(TMP_XP[63:0]) = TMP_XP
THEN CF ← 0; OF ← 0;
ELSE CF ← 1; OF ← 1; FI;
FI;
3-444 Vol. 2A
IMUL—Signed Multiply
INSTRUCTION SET REFERENCE, A-L
FI;
ELSE IF (NumberOfOperands = 2)
THEN
TMP_XP ← DEST ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)
DEST ← TruncateToOperandSize(TMP_XP);
IF SignExtend(DEST) ≠ TMP_XP
THEN CF ← 1; OF ← 1;
ELSE CF ← 0; OF ← 0; FI;
ELSE (* NumberOfOperands = 3 *)
TMP_XP ← SRC1 ∗ SRC2 (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC1 *)
DEST ← TruncateToOperandSize(TMP_XP);
IF SignExtend(DEST) ≠ TMP_XP
THEN CF ← 1; OF ← 1;
ELSE CF ← 0; OF ← 0; FI;
FI;
FI;
Flags Affected
For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the
upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and
three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the
destination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and
PF flags are undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL NULL
segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
IMUL—Signed Multiply
Vol. 2A 3-445
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-446 Vol. 2A
IMUL—Signed Multiply
INSTRUCTION SET REFERENCE, A-L
IN—Input from Port
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
E4 ib
IN AL, imm8
I
Valid
Valid
Input byte from imm8 I/O port address into
AL.
E5 ib
IN AX, imm8
I
Valid
Valid
Input word from imm8 I/O port address into
AX.
E5 ib
IN EAX, imm8
I
Valid
Valid
Input dword from imm8 I/O port address into
EAX.
EC
IN AL,DX
NP
Valid
Valid
Input byte from I/O port in DX into AL.
ED
IN AX,DX
NP
Valid
Valid
Input word from I/O port in DX into AX.
ED
IN EAX,DX
NP
Valid
Valid
Input doubleword from I/O port in DX into
EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
I
imm8
NA
NA
NA
NP
NA
NA
NA
NA
Description
Copies the value from the I/O port specified with the second operand (source operand) to the destination operand
(first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be
register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the
DX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte immediate allows I/O port addresses 0 to 255 to be accessed.
When accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port,
the operand-size attribute determines the port size. At the machine code level, I/O instructions are shorter when
accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.
This instruction is only useful for accessing I/O ports located in the processor’s I/O address space. See Chapter 18,
“Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
IF (Any I/O Permission Bit for I/O port being accessed = 1)
THEN (* I/O operation is not allowed *)
#GP(0);
ELSE ( * I/O operation is allowed *)
DEST ← SRC; (* Read from selected I/O port *)
FI;
ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *)
DEST ← SRC; (* Read from selected I/O port *)
FI;
Flags Affected
None
IN—Input from Port
Vol. 2A 3-447
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
#UD
If the LOCK prefix is used.
3-448 Vol. 2A
IN—Input from Port
INSTRUCTION SET REFERENCE, A-L
INC—Increment by 1
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
FE /0
INC r/m8
M
Valid
Valid
Increment r/m byte by 1.
REX + FE /0
INC r/m8*
M
Valid
N.E.
Increment r/m byte by 1.
FF /0
INC r/m16
M
Valid
Valid
Increment r/m word by 1.
FF /0
INC r/m32
M
Valid
Valid
Increment r/m doubleword by 1.
INC r/m64
M
Valid
N.E.
Increment r/m quadword by 1.
REX.W + FF /0
**
40+ rw
INC r16
O
N.E.
Valid
Increment word register by 1.
40+ rd
INC r32
O
N.E.
Valid
Increment doubleword register by 1.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
** 40H through 47H are REX prefixes in 64-bit mode.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r, w)
NA
NA
NA
O
opcode + rd (r, w)
NA
NA
NA
Description
Adds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a
register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.
(Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the
CF flag.)
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, INC r16 and INC r32 are not encodable (because opcodes 40H through 47H are REX prefixes).
Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to
additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.
Operation
DEST ← DEST + 1;
AFlags Affected
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination operand is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
INC—Increment by 1
Vol. 2A 3-449
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-450 Vol. 2A
INC—Increment by 1
INSTRUCTION SET REFERENCE, A-L
INS/INSB/INSW/INSD—Input from Port to String
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
6C
INS m8, DX
NP
Valid
Valid
Input byte from I/O port specified in DX into
memory location specified in ES:(E)DI or RDI.*
6D
INS m16, DX
NP
Valid
Valid
Input word from I/O port specified in DX into
memory location specified in ES:(E)DI or RDI.1
6D
INS m32, DX
NP
Valid
Valid
Input doubleword from I/O port specified in DX
into memory location specified in ES:(E)DI or
RDI.1
6C
INSB
NP
Valid
Valid
Input byte from I/O port specified in DX into
memory location specified with ES:(E)DI or
RDI.1
6D
INSW
NP
Valid
Valid
Input word from I/O port specified in DX into
memory location specified in ES:(E)DI or RDI.1
6D
INSD
NP
Valid
Valid
Input doubleword from I/O port specified in DX
into memory location specified in ES:(E)DI or
RDI.1
NOTES:
* In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit mode, only 32-bit (EDI) and 16-bit (DI)
address sizes are supported.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Copies the data from the I/O port specified with the source operand (second operand) to the destination operand
(first operand). The source operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The
destination operand is a memory location, the address of which is read from either the ES:DI, ES:EDI or the RDI
registers (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The ES segment
cannot be overridden with a segment override prefix.) The size of the I/O port being accessed (that is, the size of
the source and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.
At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands” form and the “nooperands” form. The explicit-operands form (specified with the INS mnemonic) allows the source and destination
operands to be specified explicitly. Here, the source operand must be “DX,” and the destination operand should be
a symbol that indicates the size of the I/O port and the destination address. This explicit-operands form is provided
to allow documentation; however, note that the documentation provided by this form can be misleading. That is,
the destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword),
but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers,
which must be loaded correctly before the INS instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the INS instructions.
Here also DX is assumed by the processor to be the source operand and ES:(E)DI is assumed to be the destination
operand. The size of the I/O port is specified with the choice of mnemonic: INSB (byte), INSW (word), or INSD
(doubleword).
After the byte, word, or doubleword is transfer from the I/O port to the memory location, the DI/EDI/RDI register
is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the
DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI
register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword
operations.
INS/INSB/INSW/INSD—Input from Port to String
Vol. 2A 3-451
INSTRUCTION SET REFERENCE, A-L
The INS, INSB, INSW, and INSD instructions can be preceded by the REP prefix for block input of ECX bytes, words,
or doublewords. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in Chapter 4 of the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for a description of the REP prefix.
These instructions are only useful for accessing I/O ports located in the processor’s I/O address space. See Chapter
18, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more
information on accessing I/O ports in the I/O address space.
In 64-bit mode, default address size is 64 bits, 32 bit address size is supported using the prefix 67H. The address
of the memory destination is specified by RDI or EDI. 16-bit address size is not supported in 64-bit mode. The
operand size is not promoted.
These instructions may read from the I/O port without writing to the memory location if an exception or VM exit
occurs due to the write (e.g. #PF). If this would be problematic, for example because the I/O port read has sideeffects, software should ensure the write to the memory location does not cause an exception or VM exit.
Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
IF (Any I/O Permission Bit for I/O port being accessed = 1)
THEN (* I/O operation is not allowed *)
#GP(0);
ELSE (* I/O operation is allowed *)
DEST ← SRC; (* Read from I/O port *)
FI;
ELSE (Real Mode or Protected Mode with CPL IOPL *)
DEST ← SRC; (* Read from I/O port *)
FI;
Non-64-bit Mode:
IF (Byte transfer)
THEN IF DF = 0
THEN (E)DI ← (E)DI + 1;
ELSE (E)DI ← (E)DI – 1; FI;
ELSE IF (Word transfer)
THEN IF DF = 0
THEN (E)DI ← (E)DI + 2;
ELSE (E)DI ← (E)DI – 2; FI;
ELSE (* Doubleword transfer *)
THEN IF DF = 0
THEN (E)DI ← (E)DI + 4;
ELSE (E)DI ← (E)DI – 4; FI;
FI;
FI;
FI64-bit Mode:
IF (Byte transfer)
THEN IF DF = 0
THEN (E|R)DI ← (E|R)DI + 1;
ELSE (E|R)DI ← (E|R)DI – 1; FI;
ELSE IF (Word transfer)
THEN IF DF = 0
THEN (E)DI ← (E)DI + 2;
ELSE (E)DI ← (E)DI – 2; FI;
ELSE (* Doubleword transfer *)
3-452 Vol. 2A
INS/INSB/INSW/INSD—Input from Port to String
INSTRUCTION SET REFERENCE, A-L
FI;
THEN IF DF = 0
THEN (E|R)DI ← (E|R)DI + 4;
ELSE (E|R)DI ← (E|R)DI – 4; FI;
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
If the destination is located in a non-writable segment.
If an illegal memory operand effective address in the ES segments is given.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
INS/INSB/INSW/INSD—Input from Port to String
Vol. 2A 3-453
INSTRUCTION SET REFERENCE, A-L
INSERTPS—Insert Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0F 3A 21 /r ib
INSERTPS xmm1, xmm2/m32, imm8
VEX.NDS.128.66.0F3A.WIG 21 /r ib
VINSERTPS xmm1, xmm2,
xmm3/m32, imm8
RVMI
V/V
AVX
EVEX.NDS.128.66.0F3A.W0 21 /r ib
VINSERTPS xmm1, xmm2,
xmm3/m32, imm8
T1S
V/V
AVX512F
Description
Insert a single-precision floating-point value selected
by imm8 from xmm2/m32 into xmm1 at the specified
destination element specified by imm8 and zero out
destination elements in xmm1 as indicated in imm8.
Insert a single-precision floating-point value selected
by imm8 from xmm3/m32 and merge with values in
xmm2 at the specified destination element specified
by imm8 and write out the result and zero out
destination elements in xmm1 as indicated in imm8.
Insert a single-precision floating-point value selected
by imm8 from xmm3/m32 and merge with values in
xmm2 at the specified destination element specified
by imm8 and write out the result and zero out
destination elements in xmm1 as indicated in imm8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
(register source form)
Select a single-precision floating-point element from second source as indicated by Count_S bits of the immediate
operand and destination operand it into the first source at the location indicated by the Count_D bits of the immediate operand. Store in the destination and zero out destination elements based on the ZMask bits of the immediate
operand.
(memory source form)
Load a floating-point element from a 32-bit memory location and destination operand it into the first source at the
location indicated by the Count_D bits of the immediate operand. Store in the destination and zero out destination
elements based on the ZMask bits of the immediate operand.
128-bit Legacy SSE version: The first source register is an XMM register. The second source operand is either an
XMM register or a 32-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
VEX.128 and EVEX encoded version: The destination and first source register is an XMM register. The second
source operand is either an XMM register or a 32-bit memory location. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.
If VINSERTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause
an #UD exception.
3-454 Vol. 2A
INSERTPS—Insert Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
Operation
VINSERTPS (VEX.128 and EVEX encoded version)
IF (SRC = REG) THEN COUNT_S imm8[7:6]
ELSE COUNT_S 0
COUNT_D imm8[5:4]
ZMASK imm8[3:0]
CASE (COUNT_S) OF
0: TMP SRC2[31:0]
1: TMP SRC2[63:32]
2: TMP SRC2[95:64]
3: TMP SRC2[127:96]
ESAC;
CASE (COUNT_D) OF
0: TMP2[31:0] TMP
TMP2[127:32] SRC1[127:32]
1: TMP2[63:32] TMP
TMP2[31:0] SRC1[31:0]
TMP2[127:64] SRC1[127:64]
2: TMP2[95:64] TMP
TMP2[63:0] SRC1[63:0]
TMP2[127:96] SRC1[127:96]
3: TMP2[127:96] TMP
TMP2[95:0] SRC1[95:0]
ESAC;
IF (ZMASK[0] = 1) THEN DEST[31:0] 00000000H
ELSE DEST[31:0] TMP2[31:0]
IF (ZMASK[1] = 1) THEN DEST[63:32] 00000000H
ELSE DEST[63:32] TMP2[63:32]
IF (ZMASK[2] = 1) THEN DEST[95:64] 00000000H
ELSE DEST[95:64] TMP2[95:64]
IF (ZMASK[3] = 1) THEN DEST[127:96] 00000000H
ELSE DEST[127:96] TMP2[127:96]
DEST[MAX_VL-1:128] 0
INSERTPS (128-bit Legacy SSE version)
IF (SRC = REG) THEN COUNT_S imm8[7:6]
ELSE COUNT_S 0
COUNT_D imm8[5:4]
ZMASK imm8[3:0]
CASE (COUNT_S) OF
0: TMP SRC[31:0]
1: TMP SRC[63:32]
2: TMP SRC[95:64]
3: TMP SRC[127:96]
ESAC;
CASE (COUNT_D) OF
0: TMP2[31:0] TMP
TMP2[127:32] DEST[127:32]
1: TMP2[63:32] TMP
TMP2[31:0] DEST[31:0]
TMP2[127:64] DEST[127:64]
2: TMP2[95:64] TMP
INSERTPS—Insert Scalar Single-Precision Floating-Point Value
Vol. 2A 3-455
INSTRUCTION SET REFERENCE, A-L
TMP2[63:0] DEST[63:0]
TMP2[127:96] DEST[127:96]
3: TMP2[127:96] TMP
TMP2[95:0] DEST[95:0]
ESAC;
IF (ZMASK[0] = 1) THEN DEST[31:0] 00000000H
ELSE DEST[31:0] TMP2[31:0]
IF (ZMASK[1] = 1) THEN DEST[63:32] 00000000H
ELSE DEST[63:32] TMP2[63:32]
IF (ZMASK[2] = 1) THEN DEST[95:64] 00000000H
ELSE DEST[95:64] TMP2[95:64]
IF (ZMASK[3] = 1) THEN DEST[127:96] 00000000H
ELSE DEST[127:96] TMP2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VINSERTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);
INSETRTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Exceptions Type E9NF.
3-456 Vol. 2A
INSERTPS—Insert Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
INT n/INTO/INT 3—Call to Interrupt Procedure
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
CC
INT 3
NP
Valid
Valid
Interrupt 3—trap to debugger.
CD ib
INT imm8
I
Valid
Valid
Interrupt vector specified by immediate byte.
CE
INTO
NP
Invalid
Valid
Interrupt 4—if overflow flag is 1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
I
imm8
NA
NA
NA
Description
The INT n instruction generates a call to the interrupt or exception handler specified with the destination operand
(see the section titled “Interrupts and Exceptions” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1). The destination operand specifies a vector from 0 to 255, encoded as an 8-bit
unsigned intermediate value. Each vector provides an index to a gate descriptor in the IDT. The first 32 vectors are
reserved by Intel for system use. Some of these vectors are used for internally generated exceptions.
The INT n instruction is the general mnemonic for executing a software-generated call to an interrupt handler. The
INTO instruction is a special mnemonic for calling overflow exception (#OF), exception 4. The overflow interrupt
checks the OF flag in the EFLAGS register and calls the overflow interrupt handler if the OF flag is set to 1. (The
INTO instruction cannot be used in 64-bit mode.)
The INT 3 instruction generates a special one byte opcode (CC) that is intended for calling the debug exception
handler. (This one byte form is valuable because it can be used to replace the first byte of any instruction with a
breakpoint, including other one byte instructions, without over-writing other code). To further support its function
as a debug breakpoint, the interrupt generated with the CC opcode also differs from the regular software interrupts
as follows:
•
Interrupt redirection does not happen when in VME mode; the interrupt is handled by a protected-mode
handler.
•
The virtual-8086 mode IOPL checks do not occur. The interrupt is taken without faulting at any IOPL level.
Note that the “normal” 2-byte opcode for INT 3 (CD03) does not have these special features. Intel and Microsoft
assemblers will not generate the CD03 opcode from any mnemonic, but this opcode can be created by direct
numeric code definition or by self-modifying code.
The action of the INT n instruction (including the INTO and INT 3 instructions) is similar to that of a far call made
with the CALL instruction. The primary difference is that with the INT n instruction, the EFLAGS register is pushed
onto the stack before the return address. (The return address is a far address consisting of the current values of
the CS and EIP registers.) Returns from interrupt procedures are handled with the IRET instruction, which pops the
EFLAGS information and return address from the stack.
The vector specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the
IDT. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure.
In protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate,
or task gate. In real-address mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and
a 2-byte instruction pointer), each of which point directly to a procedure in the selected segment. (Note that in
real-address mode, the IDT is called the interrupt vector table, and its pointers are called interrupt vectors.)
The following decision table indicates which action in the lower portion of the table is taken given the conditions in
the upper portion of the table. Each Y in the lower section of the decision table represents a procedure defined in
the “Operation” section for this instruction (except #GP).
INT n/INTO/INT 3—Call to Interrupt Procedure
Vol. 2A 3-457
INSTRUCTION SET REFERENCE, A-L
Table 3-51. Decision Table
PE
0
1
1
1
1
1
1
1
VM
–
–
–
–
–
0
1
1
IOPL
–
–
–
–
–
–
<3
=3
DPL/CPL
RELATIONSHIP
–
DPL<
CPL
–
DPL>
CPL
DPL=
CPL or C
DPL<
CPL & NC
–
–
INTERRUPT TYPE
–
S/W
–
–
–
–
–
–
GATE TYPE
–
–
Task
Trap or
Interrupt
Trap or
Interrupt
Trap or
Interrupt
Trap or
Interrupt
Trap or
Interrupt
REAL-ADDRESS-MODE
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
PROTECTED-MODE
TRAP-OR-INTERRUPTGATE
INTER-PRIVILEGE-LEVELINTERRUPT
Y
INTRA-PRIVILEGE-LEVELINTERRUPT
Y
INTERRUPT-FROMVIRTUAL-8086-MODE
Y
TASK-GATE
#GP
Y
Y
Y
Y
NOTES:
−
Don't Care.
Y
Yes, action taken.
Blank Action not taken.
When the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If
the IOPL is less than 3, the processor generates a #GP(selector) exception; if the IOPL is 3, the processor executes
a protected mode interrupt to privilege level 0. The interrupt gate's DPL must be set to 3 and the target CPL of the
interrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0.
The interrupt descriptor table register (IDTR) specifies the base linear address and limit of the IDT. The initial base
address value of the IDTR after the processor is powered up or reset is 0.
Operation
The following operational description applies not only to the INT n and INTO instructions, but also to external interrupts, nonmaskable interrupts (NMIs), and exceptions. Some of these events push onto the stack an error code.
The operational description specifies numerous checks whose failure may result in delivery of a nested exception.
In these cases, the original event is not delivered.
The operational description specifies the error code delivered by any nested exception. In some cases, the error
code is specified with a pseudofunction error_code(num,idt,ext), where idt and ext are bit values. The pseudofunction produces an error code as follows: (1) if idt is 0, the error code is (num & FCH) | ext; (2) if idt is 1, the error
code is (num « 3) | 2 | ext.
In many cases, the pseudofunction error_code is invoked with a pseudovariable EXT. The value of EXT depends on
the nature of the event whose delivery encountered a nested exception: if that event is a software interrupt, EXT is
0; otherwise, EXT is 1.
3-458 Vol. 2A
INT n/INTO/INT 3—Call to Interrupt Procedure
INSTRUCTION SET REFERENCE, A-L
IF PE = 0
THEN
GOTO REAL-ADDRESS-MODE;
ELSE (* PE = 1 *)
IF (VM = 1 and IOPL < 3 AND INT n)
THEN
#GP(0); (* Bit 0 of error code is 0 because INT n *)
ELSE (* Protected mode, IA-32e mode, or virtual-8086 mode interrupt *)
IF (IA32_EFER.LMA = 0)
THEN (* Protected mode, or virtual-8086 mode interrupt *)
GOTO PROTECTED-MODE;
ELSE (* IA-32e mode interrupt *)
GOTO IA-32e-MODE;
FI;
FI;
FI;
REAL-ADDRESS-MODE:
IF ((vector_number « 2) + 3) is not within IDT limit
THEN #GP; FI;
IF stack not large enough for a 6-byte return information
THEN #SS; FI;
Push (EFLAGS[15:0]);
IF ← 0; (* Clear interrupt flag *)
TF ← 0; (* Clear trap flag *)
AC ← 0; (* Clear AC flag *)
Push(CS);
Push(IP);
(* No error codes are pushed in real-address mode*)
CS ← IDT(Descriptor (vector_number « 2), selector));
EIP ← IDT(Descriptor (vector_number « 2), offset)); (* 16 bit offset AND 0000FFFFH *)
END;
PROTECTED-MODE:
IF ((vector_number « 3) + 7) is not within IDT limits
or selected IDT descriptor is not an interrupt-, trap-, or task-gate type
THEN #GP(error_code(vector_number,1,EXT)); FI;
(* idt operand to error_code set because vector is used *)
IF software interrupt (* Generated by INT n, INT3, or INTO *)
THEN
IF gate DPL < CPL (* PE = 1, DPL < CPL, software interrupt *)
THEN #GP(error_code(vector_number,1,0)); FI;
(* idt operand to error_code set because vector is used *)
(* ext operand to error_code is 0 because INT n, INT3, or INTO*)
FI;
IF gate not present
THEN #NP(error_code(vector_number,1,EXT)); FI;
(* idt operand to error_code set because vector is used *)
IF task gate (* Specified in the selected interrupt table descriptor *)
THEN GOTO TASK-GATE;
ELSE GOTO TRAP-OR-INTERRUPT-GATE; (* PE = 1, trap/interrupt gate *)
FI;
END;
IA-32e-MODE:
IF INTO and CS.L = 1 (64-bit mode)
THEN #UD;
INT n/INTO/INT 3—Call to Interrupt Procedure
Vol. 2A 3-459
INSTRUCTION SET REFERENCE, A-L
FI;
IF ((vector_number « 4) + 15) is not in IDT limits
or selected IDT descriptor is not an interrupt-, or trap-gate type
THEN #GP(error_code(vector_number,1,EXT));
(* idt operand to error_code set because vector is used *)
FI;
IF software interrupt (* Generated by INT n, INT 3, or INTO *)
THEN
IF gate DPL < CPL (* PE = 1, DPL < CPL, software interrupt *)
THEN #GP(error_code(vector_number,1,0));
(* idt operand to error_code set because vector is used *)
(* ext operand to error_code is 0 because INT n, INT3, or INTO*)
FI;
FI;
IF gate not present
THEN #NP(error_code(vector_number,1,EXT));
(* idt operand to error_code set because vector is used *)
FI;
GOTO TRAP-OR-INTERRUPT-GATE; (* Trap/interrupt gate *)
END;
TASK-GATE: (* PE = 1, task gate *)
Read TSS selector in task gate (IDT descriptor);
IF local/global bit is set to local or index not within GDT limits
THEN #GP(error_code(TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
Access TSS descriptor in GDT;
IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)
THEN #GP(TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
IF TSS not present
THEN #NP(TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
SWITCH-TASKS (with nesting) to TSS;
IF interrupt caused by fault with error code
THEN
IF stack limit does not allow push of error code
THEN #SS(EXT); FI;
Push(error code);
FI;
IF EIP not within code segment limit
THEN #GP(EXT); FI;
END;
TRAP-OR-INTERRUPT-GATE:
Read new code-segment selector for trap or interrupt gate (IDT descriptor);
IF new code-segment selector is NULL
THEN #GP(EXT); FI; (* Error code contains NULL selector *)
IF new code-segment selector is not within its descriptor table limits
THEN #GP(error_code(new code-segment selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
Read descriptor referenced by new code-segment selector;
IF descriptor does not indicate a code segment or new code-segment DPL > CPL
THEN #GP(error_code(new code-segment selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
IF new code-segment descriptor is not present,
3-460 Vol. 2A
INT n/INTO/INT 3—Call to Interrupt Procedure
INSTRUCTION SET REFERENCE, A-L
THEN #NP(error_code(new code-segment selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
IF new code segment is non-conforming with DPL < CPL
THEN
IF VM = 0
THEN
GOTO INTER-PRIVILEGE-LEVEL-INTERRUPT;
(* PE = 1, VM = 0, interrupt or trap gate, nonconforming code segment,
DPL < CPL *)
ELSE (* VM = 1 *)
IF new code-segment DPL ≠ 0
THEN #GP(error_code(new code-segment selector,0,EXT));
(* idt operand to error_code is 0 because selector is used *)
GOTO INTERRUPT-FROM-VIRTUAL-8086-MODE; FI;
(* PE = 1, interrupt or trap gate, DPL < CPL, VM = 1 *)
FI;
ELSE (* PE = 1, interrupt or trap gate, DPL ≥ CPL *)
IF VM = 1
THEN #GP(error_code(new code-segment selector,0,EXT));
(* idt operand to error_code is 0 because selector is used *)
IF new code segment is conforming or new code-segment DPL = CPL
THEN
GOTO INTRA-PRIVILEGE-LEVEL-INTERRUPT;
ELSE (* PE = 1, interrupt or trap gate, nonconforming code segment, DPL > CPL *)
#GP(error_code(new code-segment selector,0,EXT));
(* idt operand to error_code is 0 because selector is used *)
FI;
FI;
END;
INTER-PRIVILEGE-LEVEL-INTERRUPT:
(* PE = 1, interrupt or trap gate, non-conforming code segment, DPL < CPL *)
IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)
THEN
(* Identify stack-segment selector for new privilege level in current TSS *)
IF current TSS is 32-bit
THEN
TSSstackAddress ← (new code-segment DPL « 3) + 4;
IF (TSSstackAddress + 5) > current TSS limit
THEN #TS(error_code(current TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
NewSS ← 2 bytes loaded from (TSS base + TSSstackAddress + 4);
NewESP ← 4 bytes loaded from (TSS base + TSSstackAddress);
ELSE
(* current TSS is 16-bit *)
TSSstackAddress ← (new code-segment DPL « 2) + 2
IF (TSSstackAddress + 3) > current TSS limit
THEN #TS(error_code(current TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
NewSS ← 2 bytes loaded from (TSS base + TSSstackAddress + 2);
NewESP ← 2 bytes loaded from (TSS base + TSSstackAddress);
FI;
IF NewSS is NULL
THEN #TS(EXT); FI;
IF NewSS index is not within its descriptor-table limits
or NewSS RPL ≠ new code-segment DPL
INT n/INTO/INT 3—Call to Interrupt Procedure
Vol. 2A 3-461
INSTRUCTION SET REFERENCE, A-L
THEN #TS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
Read new stack-segment descriptor for NewSS in GDT or LDT;
IF new stack-segment DPL ≠ new code-segment DPL
or new stack-segment Type does not indicate writable data segment
THEN #TS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
IF NewSS is not present
THEN #SS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
ELSE (* IA-32e mode *)
IF IDT-gate IST = 0
THEN TSSstackAddress ← (new code-segment DPL « 3) + 4;
ELSE TSSstackAddress ← (IDT gate IST « 3) + 28;
FI;
IF (TSSstackAddress + 7) > current TSS limit
THEN #TS(error_code(current TSS selector,0,EXT); FI;
(* idt operand to error_code is 0 because selector is used *)
NewRSP ← 8 bytes loaded from (current TSS base + TSSstackAddress);
NewSS ← new code-segment DPL; (* NULL selector with RPL = new CPL *)
FI;
IF IDT gate is 32-bit
THEN
IF new stack does not have room for 24 bytes (error code pushed)
or 20 bytes (no error code pushed)
THEN #SS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
FI
ELSE
IF IDT gate is 16-bit
THEN
IF new stack does not have room for 12 bytes (error code pushed)
or 10 bytes (no error code pushed);
THEN #SS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
ELSE (* 64-bit IDT gate*)
IF StackAddress is non-canonical
THEN #SS(EXT); FI; (* Error code contains NULL selector *)
FI;
FI;
IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)
THEN
IF instruction pointer from IDT gate is not within new code-segment limits
THEN #GP(EXT); FI; (* Error code contains NULL selector *)
ESP ← NewESP;
SS ← NewSS; (* Segment descriptor information also loaded *)
ELSE (* IA-32e mode *)
IF instruction pointer from IDT gate contains a non-canonical address
THEN #GP(EXT); FI; (* Error code contains NULL selector *)
RSP ← NewRSP & FFFFFFFFFFFFFFF0H;
SS ← NewSS;
FI;
IF IDT gate is 32-bit
THEN
3-462 Vol. 2A
INT n/INTO/INT 3—Call to Interrupt Procedure
INSTRUCTION SET REFERENCE, A-L
CS:EIP ← Gate(CS:EIP); (* Segment descriptor information also loaded *)
ELSE
IF IDT gate 16-bit
THEN
CS:IP ← Gate(CS:IP);
(* Segment descriptor information also loaded *)
ELSE (* 64-bit IDT gate *)
CS:RIP ← Gate(CS:RIP);
(* Segment descriptor information also loaded *)
FI;
FI;
IF IDT gate is 32-bit
THEN
Push(far pointer to old stack);
(* Old SS and ESP, 3 words padded to 4 *)
Push(EFLAGS);
Push(far pointer to return instruction);
(* Old CS and EIP, 3 words padded to 4 *)
Push(ErrorCode); (* If needed, 4 bytes *)
ELSE
IF IDT gate 16-bit
THEN
Push(far pointer to old stack);
(* Old SS and SP, 2 words *)
Push(EFLAGS(15-0]);
Push(far pointer to return instruction);
(* Old CS and IP, 2 words *)
Push(ErrorCode); (* If needed, 2 bytes *)
ELSE (* 64-bit IDT gate *)
Push(far pointer to old stack);
(* Old SS and SP, each an 8-byte push *)
Push(RFLAGS); (* 8-byte push *)
Push(far pointer to return instruction);
(* Old CS and RIP, each an 8-byte push *)
Push(ErrorCode); (* If needed, 8-bytes *)
FI;
FI;
CPL ← new code-segment DPL;
CS(RPL) ← CPL;
IF IDT gate is interrupt gate
THEN IF ← 0 (* Interrupt flag set to 0, interrupts disabled *); FI;
TF ← 0;
VM ← 0;
RF ← 0;
NT ← 0;
END;
INTERRUPT-FROM-VIRTUAL-8086-MODE:
(* Identify stack-segment selector for privilege level 0 in current TSS *)
IF current TSS is 32-bit
THEN
IF TSS limit < 9
THEN #TS(error_code(current TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
NewSS ← 2 bytes loaded from (current TSS base + 8);
INT n/INTO/INT 3—Call to Interrupt Procedure
Vol. 2A 3-463
INSTRUCTION SET REFERENCE, A-L
NewESP ← 4 bytes loaded from (current TSS base + 4);
ELSE (* current TSS is 16-bit *)
IF TSS limit < 5
THEN #TS(error_code(current TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
NewSS ← 2 bytes loaded from (current TSS base + 4);
NewESP ← 2 bytes loaded from (current TSS base + 2);
FI;
IF NewSS is NULL
THEN #TS(EXT); FI; (* Error code contains NULL selector *)
IF NewSS index is not within its descriptor table limits
or NewSS RPL ≠ 0
THEN #TS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
Read new stack-segment descriptor for NewSS in GDT or LDT;
IF new stack-segment DPL ≠ 0 or stack segment does not indicate writable data segment
THEN #TS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
IF new stack segment not present
THEN #SS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
IF IDT gate is 32-bit
THEN
IF new stack does not have room for 40 bytes (error code pushed)
or 36 bytes (no error code pushed)
THEN #SS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
ELSE (* IDT gate is 16-bit)
IF new stack does not have room for 20 bytes (error code pushed)
or 18 bytes (no error code pushed)
THEN #SS(error_code(NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
FI;
IF instruction pointer from IDT gate is not within new code-segment limits
THEN #GP(EXT); FI; (* Error code contains NULL selector *)
tempEFLAGS ← EFLAGS;
VM ← 0;
TF ← 0;
RF ← 0;
NT ← 0;
IF service through interrupt gate
THEN IF = 0; FI;
TempSS ← SS;
TempESP ← ESP;
SS ← NewSS;
ESP ← NewESP;
(* Following pushes are 16 bits for 16-bit IDT gates and 32 bits for 32-bit IDT gates;
Segment selector pushes in 32-bit mode are padded to two words *)
Push(GS);
Push(FS);
Push(DS);
Push(ES);
Push(TempSS);
Push(TempESP);
3-464 Vol. 2A
INT n/INTO/INT 3—Call to Interrupt Procedure
INSTRUCTION SET REFERENCE, A-L
Push(TempEFlags);
Push(CS);
Push(EIP);
GS ← 0; (* Segment registers made NULL, invalid for use in protected mode *)
FS ← 0;
DS ← 0;
ES ← 0;
CS:IP ← Gate(CS); (* Segment descriptor information also loaded *)
IF OperandSize = 32
THEN
EIP ← Gate(instruction pointer);
ELSE (* OperandSize is 16 *)
EIP ← Gate(instruction pointer) AND 0000FFFFH;
FI;
(* Start execution of new routine in Protected Mode *)
END;
INTRA-PRIVILEGE-LEVEL-INTERRUPT:
(* PE = 1, DPL = CPL or conforming segment *)
IF IA32_EFER.LMA = 1 (* IA-32e mode *)
IF IDT-descriptor IST ≠ 0
THEN
TSSstackAddress ← (IDT-descriptor IST « 3) + 28;
IF (TSSstackAddress + 7) > TSS limit
THEN #TS(error_code(current TSS selector,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)
NewRSP ← 8 bytes loaded from (current TSS base + TSSstackAddress);
FI;
IF 32-bit gate (* implies IA32_EFER.LMA = 0 *)
THEN
IF current stack does not have room for 16 bytes (error code pushed)
or 12 bytes (no error code pushed)
THEN #SS(EXT); FI; (* Error code contains NULL selector *)
ELSE IF 16-bit gate (* implies IA32_EFER.LMA = 0 *)
IF current stack does not have room for 8 bytes (error code pushed)
or 6 bytes (no error code pushed)
THEN #SS(EXT); FI; (* Error code contains NULL selector *)
ELSE (* IA32_EFER.LMA = 1, 64-bit gate*)
IF NewRSP contains a non-canonical address
THEN #SS(EXT); (* Error code contains NULL selector *)
FI;
FI;
IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)
THEN
IF instruction pointer from IDT gate is not within new code-segment limit
THEN #GP(EXT); FI; (* Error code contains NULL selector *)
ELSE
IF instruction pointer from IDT gate contains a non-canonical address
THEN #GP(EXT); FI; (* Error code contains NULL selector *)
RSP ← NewRSP & FFFFFFFFFFFFFFF0H;
FI;
IF IDT gate is 32-bit (* implies IA32_EFER.LMA = 0 *)
THEN
Push (EFLAGS);
Push (far pointer to return instruction); (* 3 words padded to 4 *)
INT n/INTO/INT 3—Call to Interrupt Procedure
Vol. 2A 3-465
INSTRUCTION SET REFERENCE, A-L
CS:EIP ← Gate(CS:EIP); (* Segment descriptor information also loaded *)
Push (ErrorCode); (* If any *)
ELSE
IF IDT gate is 16-bit (* implies IA32_EFER.LMA = 0 *)
THEN
Push (FLAGS);
Push (far pointer to return location); (* 2 words *)
CS:IP ← Gate(CS:IP);
(* Segment descriptor information also loaded *)
Push (ErrorCode); (* If any *)
ELSE (* IA32_EFER.LMA = 1, 64-bit gate*)
Push(far pointer to old stack);
(* Old SS and SP, each an 8-byte push *)
Push(RFLAGS); (* 8-byte push *)
Push(far pointer to return instruction);
(* Old CS and RIP, each an 8-byte push *)
Push(ErrorCode); (* If needed, 8 bytes *)
CS:RIP ← GATE(CS:RIP);
(* Segment descriptor information also loaded *)
FI;
FI;
CS(RPL) ← CPL;
IF IDT gate is interrupt gate
THEN IF ← 0; FI; (* Interrupt flag set to 0; interrupts disabled *)
TF ← 0;
NT ← 0;
VM ← 0;
RF ← 0;
END;
Flags Affected
The EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags may be cleared, depending on
the mode of operation of the processor when the INT instruction is executed (see the “Operation” section). If the
interrupt uses a task gate, any flags may be set or cleared, controlled by the EFLAGS image in the new task’s TSS.
Protected Mode Exceptions
#GP(error_code)
If the instruction pointer in the IDT or in the interrupt-, trap-, or task gate is beyond the code
segment limits.
If the segment selector in the interrupt-, trap-, or task gate is NULL.
If an interrupt-, trap-, or task gate, code segment, or TSS segment selector index is outside its
descriptor table limits.
If the vector selects a descriptor outside the IDT limits.
If an IDT descriptor is not an interrupt-, trap-, or task-descriptor.
If an interrupt is generated by the INT n, INT 3, or INTO instruction and the DPL of an interrupt-, trap-, or task-descriptor is less than the CPL.
If the segment selector in an interrupt- or trap-gate does not point to a segment descriptor for
a code segment.
If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is busy or not available.
3-466 Vol. 2A
INT n/INTO/INT 3—Call to Interrupt Procedure
INSTRUCTION SET REFERENCE, A-L
#SS(error_code)
If pushing the return address, flags, or error code onto the stack exceeds the bounds of the
stack segment and no stack switch occurs.
If the SS register is being loaded and the segment pointed to is marked not present.
If pushing the return address, flags, error code, or stack segment pointer exceeds the bounds
of the new stack segment when a stack switch occurs.
#NP(error_code)
If code segment, interrupt-, trap-, or task gate, or TSS is not present.
#TS(error_code)
If the RPL of the stack segment selector in the TSS is not equal to the DPL of the code segment
being accessed by the interrupt or trap gate.
If DPL of the stack segment descriptor pointed to by the stack segment selector in the TSS is
not equal to the DPL of the code segment descriptor for the interrupt or trap gate.
If the stack segment selector in the TSS is NULL.
If the stack segment for the TSS is not a writable data segment.
If segment-selector index for stack segment is outside descriptor table limits.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
#AC(EXT)
If alignment checking is enabled, the gate DPL is 3, and a stack push is unaligned.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the interrupt vector number is outside the IDT limits.
#SS
If stack limit violation on push.
If pushing the return address, flags, or error code onto the stack exceeds the bounds of the
stack segment.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(error_code)
(For INT n, INTO, or BOUND instruction) If the IOPL is less than 3 or the DPL of the interrupt, trap-, or task-gate descriptor is not equal to 3.
If the instruction pointer in the IDT or in the interrupt-, trap-, or task gate is beyond the code
segment limits.
If the segment selector in the interrupt-, trap-, or task gate is NULL.
If a interrupt-, trap-, or task gate, code segment, or TSS segment selector index is outside its
descriptor table limits.
If the vector selects a descriptor outside the IDT limits.
If an IDT descriptor is not an interrupt-, trap-, or task-descriptor.
If an interrupt is generated by the INT n instruction and the DPL of an interrupt-, trap-, or
task-descriptor is less than the CPL.
If the segment selector in an interrupt- or trap-gate does not point to a segment descriptor for
a code segment.
If the segment selector for a TSS has its local/global bit set for local.
#SS(error_code)
If the SS register is being loaded and the segment pointed to is marked not present.
If pushing the return address, flags, error code, stack segment pointer, or data segments
exceeds the bounds of the stack segment.
#NP(error_code)
If code segment, interrupt-, trap-, or task gate, or TSS is not present.
INT n/INTO/INT 3—Call to Interrupt Procedure
Vol. 2A 3-467
INSTRUCTION SET REFERENCE, A-L
#TS(error_code)
If the RPL of the stack segment selector in the TSS is not equal to the DPL of the code segment
being accessed by the interrupt or trap gate.
If DPL of the stack segment descriptor for the TSS’s stack segment is not equal to the DPL of
the code segment descriptor for the interrupt or trap gate.
If the stack segment selector in the TSS is NULL.
If the stack segment for the TSS is not a writable data segment.
If segment-selector index for stack segment is outside descriptor table limits.
#PF(fault-code)
If a page fault occurs.
#BP
If the INT 3 instruction is executed.
#OF
If the INTO instruction is executed and the OF flag is set.
#UD
If the LOCK prefix is used.
#AC(EXT)
If alignment checking is enabled, the gate DPL is 3, and a stack push is unaligned.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(error_code)
If the instruction pointer in the 64-bit interrupt gate or 64-bit trap gate is non-canonical.
If the segment selector in the 64-bit interrupt or trap gate is NULL.
If the vector selects a descriptor outside the IDT limits.
If the vector points to a gate which is in non-canonical space.
If the vector points to a descriptor which is not a 64-bit interrupt gate or 64-bit trap gate.
If the descriptor pointed to by the gate selector is outside the descriptor table limit.
If the descriptor pointed to by the gate selector is in non-canonical space.
If the descriptor pointed to by the gate selector is not a code segment.
If the descriptor pointed to by the gate selector doesn’t have the L-bit set, or has both the Lbit and D-bit set.
If the descriptor pointed to by the gate selector has DPL > CPL.
#SS(error_code)
If a push of the old EFLAGS, CS selector, EIP, or error code is in non-canonical space with no
stack switch.
If a push of the old SS selector, ESP, EFLAGS, CS selector, EIP, or error code is in non-canonical
space on a stack switch (either CPL change or no-CPL with IST).
#NP(error_code)
If the 64-bit interrupt-gate, 64-bit trap-gate, or code segment is not present.
#TS(error_code)
If an attempt to load RSP from the TSS causes an access to non-canonical space.
#PF(fault-code)
If a page fault occurs.
If the RSP from the TSS is outside descriptor table limits.
#UD
If the LOCK prefix is used.
#AC(EXT)
If alignment checking is enabled, the gate DPL is 3, and a stack push is unaligned.
3-468 Vol. 2A
INT n/INTO/INT 3—Call to Interrupt Procedure
INSTRUCTION SET REFERENCE, A-L
INVD—Invalidate Internal Caches
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 08
INVD
NP
Valid
Valid
Flush internal caches; initiate flushing of
external caches.
NOTES:
* See the IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Invalidates (flushes) the processor’s internal caches and issues a special-function bus cycle that directs external
caches to also flush themselves. Data held in internal caches is not written back to main memory.
After executing this instruction, the processor does not wait for the external caches to complete their flushing operation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush
signal.
The INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a
program or procedure must be 0 to execute this instruction.
The INVD instruction may be used when the cache is used as temporary memory and the cache contents need to
be invalidated rather than written back to memory. When the cache is used as temporary memory, no external
device should be actively writing data to main memory.
Use this instruction with care. Data cached internally and not written back to main memory will be lost. Note that
any data from an external device to main memory (for example, via a PCIWrite) can be temporarily stored in the
caches; these data can be lost when an INVD instruction is executed. Unless there is a specific requirement or
benefit to flushing caches without writing back modified cache lines (for example, temporary memory, testing, or
fault recovery where cache coherency with main memory is not a concern), software should instead use the
WBINVD instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IA-32 Architecture Compatibility
The INVD instruction is implementation dependent; it may be implemented differently on different families of Intel
64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.
Operation
Flush(InternalCaches);
SignalFlush(ExternalCaches);
Continue (* Continue execution *)
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
INVD—Invalidate Internal Caches
Vol. 2A 3-469
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#GP(0)
The INVD instruction cannot be executed in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-470 Vol. 2A
INVD—Invalidate Internal Caches
INSTRUCTION SET REFERENCE, A-L
INVLPG—Invalidate TLB Entries
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01/7
INVLPG m
M
Valid
Valid
Invalidate TLB entries for page containing m.
NOTES:
* See the IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Invalidates any translation lookaside buffer (TLB) entries specified with the source operand. The source operand is
a memory address. The processor determines the page that contains that address and flushes all TLB entries for
that page.1
The INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL must
be 0 to execute this instruction.
The INVLPG instruction normally flushes TLB entries only for the specified page; however, in some cases, it may
flush more entries, even the entire TLB. The instruction is guaranteed to invalidates only TLB entries associated
with the current PCID. (If PCIDs are disabled — CR4.PCIDE = 0 — the current PCID is 000H.) The instruction also
invalidates any global TLB entries for the specified page, regardless of PCID.
For more details on operations that flush the TLB, see “MOV—Move to/from Control Registers” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2B and Section 4.10.4.1, “Operations that Invalidate
TLBs and Paging-Structure Caches,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A.
This instruction’s operation is the same in all non-64-bit modes. It also operates the same in 64-bit mode, except
if the memory address is in non-canonical form. In this case, INVLPG is the same as a NOP.
IA-32 Architecture Compatibility
The INVLPG instruction is implementation dependent, and its function may be implemented differently on different
families of Intel 64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the
Intel486 processor.
Operation
Invalidate(RelevantTLBEntries);
Continue; (* Continue execution *)
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
Operand is a register.
If the LOCK prefix is used.
1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page
(see Section 4.10.2.3, “Details of TLB Use,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A), the
instruction invalidates all of them.
INVLPG—Invalidate TLB Entries
Vol. 2A 3-471
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#UD
Operand is a register.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
The INVLPG instruction cannot be executed at the virtual-8086 mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
Operand is a register.
If the LOCK prefix is used.
3-472 Vol. 2A
INVLPG—Invalidate TLB Entries
INSTRUCTION SET REFERENCE, A-L
INVPCID—Invalidate Process-Context Identifier
Opcode/Instruction
Op/
En
64/32bit
Mode
CPUID
Feature
Flag
Description
66 0F 38 82 /r
INVPCID r32, m128
RM
NE/V
INVPCID
Invalidates entries in the TLBs and paging-structure
caches based on invalidation type in r32 and descriptor in m128.
66 0F 38 82 /r
INVPCID r64, m128
RM
V/NE
INVPCID
Invalidates entries in the TLBs and paging-structure
caches based on invalidation type in r64 and descriptor in m128.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (R)
ModRM:r/m (R)
NA
NA
Description
Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on processcontext identifier (PCID). (See Section 4.10, “Caching Translation Information,” in Intel 64 and IA-32 Architecture
Software Developer’s Manual, Volume 3A.) Invalidation is based on the INVPCID type specified in the register
operand and the INVPCID descriptor specified in the memory operand.
Outside 64-bit mode, the register operand is always 32 bits, regardless of the value of CS.D. In 64-bit mode the
register operand has 64 bits.
There are four INVPCID types currently defined:
•
Individual-address invalidation: If the INVPCID type is 0, the logical processor invalidates mappings—except
global translations—for the linear address and PCID specified in the INVPCID descriptor.1 In some cases, the
instruction may invalidate global translations or mappings for other linear addresses (or other PCIDs) as well.
•
Single-context invalidation: If the INVPCID type is 1, the logical processor invalidates all mappings—except
global translations—associated with the PCID specified in the INVPCID descriptor. In some cases, the
instruction may invalidate global translations or mappings for other PCIDs as well.
•
All-context invalidation, including global translations: If the INVPCID type is 2, the logical processor invalidates
all mappings—including global translations—associated with any PCID.
•
All-context invalidation: If the INVPCID type is 3, the logical processor invalidates all mappings—except global
translations—associated with any PCID. In some case, the instruction may invalidate global translations as
well.
The INVPCID descriptor comprises 128 bits and consists of a PCID and a linear address as shown in Figure 3-24.
For INVPCID type 0, the processor uses the full 64 bits of the linear address even outside 64-bit mode; the linear
address is not used for other INVPCID types.
127
64 63
Linear Address
12 11
Reserved (must be zero)
0
PCID
Figure 3-24. INVPCID Descriptor
1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page
(see Section 4.10.2.3, “Details of TLB Use,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A), the
instruction invalidates all of them.
INVPCID—Invalidate Process-Context Identifier
Vol. 2A 3-473
INSTRUCTION SET REFERENCE, A-L
If CR4.PCIDE = 0, a logical processor does not cache information for any PCID other than 000H. In this case,
executions with INVPCID types 0 and 1 are allowed only if the PCID specified in the INVPCID descriptor is 000H;
executions with INVPCID types 2 and 3 invalidate mappings only for PCID 000H. Note that CR4.PCIDE must be 0
outside 64-bit mode (see Chapter 4.10.1, “Process-Context Identifiers (PCIDs)‚” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
Operation
INVPCID_TYPE ← value of register operand;
// must be in the range of 0–3
INVPCID_DESC ← value of memory operand;
CASE INVPCID_TYPE OF
0:
// individual-address invalidation
PCID ← INVPCID_DESC[11:0];
L_ADDR ← INVPCID_DESC[127:64];
Invalidate mappings for L_ADDR associated with PCID except global translations;
BREAK;
1:
// single PCID invalidation
PCID ← INVPCID_DESC[11:0];
Invalidate all mappings associated with PCID except global translations;
BREAK;
2:
// all PCID invalidation including global translations
Invalidate all mappings for all PCIDs, including global translations;
BREAK;
3:
// all PCID invalidation retaining global translations
Invalidate all mappings for all PCIDs except global translations;
BREAK;
ESAC;
Intel C/C++ Compiler Intrinsic Equivalent
INVPCID:
void _invpcid(unsigned __int32 type, void * descriptor);
SIMD Floating-Point Exceptions
None
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the source operand is located in an execute-only code segment.
If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.
If bits 63:12 of INVPCID_DESC are not all zero.
If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.
If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.
#PF(fault-code)
If a page fault occurs in accessing the memory operand.
#SS(0)
If the memory operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If if CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.
If the LOCK prefix is used.
3-474 Vol. 2A
INVPCID—Invalidate Process-Context Identifier
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.
If bits 63:12 of INVPCID_DESC are not all zero.
If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.
If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.
#UD
If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
The INVPCID instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is
in a non-canonical form.
If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.
If bits 63:12 of INVPCID_DESC are not all zero.
If CR4.PCIDE=0, INVPCID_TYPE is either 0 or 1, and INVPCID_DESC[11:0] is not zero.
If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.
#PF(fault-code)
If a page fault occurs in accessing the memory operand.
#SS(0)
If the memory destination operand is in the SS segment and the memory address is in a noncanonical form.
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.
INVPCID—Invalidate Process-Context Identifier
Vol. 2A 3-475
INSTRUCTION SET REFERENCE, A-L
IRET/IRETD—Interrupt Return
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
CF
IRET
NP
Valid
Valid
Interrupt return (16-bit operand size).
CF
IRETD
NP
Valid
Valid
Interrupt return (32-bit operand size).
REX.W + CF
IRETQ
NP
Valid
N.E.
Interrupt return (64-bit operand size).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Returns program control from an exception or interrupt handler to a program or procedure that was interrupted by
an exception, an external interrupt, or a software-generated interrupt. These instructions are also used to perform
a return from a nested task. (A nested task is created when a CALL instruction is used to initiate a task switch or
when an interrupt or exception causes a task switch to an interrupt or exception handler.) See the section titled
“Task Linking” in Chapter 7 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
IRET and IRETD are mnemonics for the same opcode. The IRETD mnemonic (interrupt return double) is intended
for use when returning from an interrupt when using the 32-bit operand size; however, most assemblers use the
IRET mnemonic interchangeably for both operand sizes.
In Real-Address Mode, the IRET instruction preforms a far return to the interrupted program or procedure. During
this operation, the processor pops the return instruction pointer, return code segment selector, and EFLAGS image
from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted
program or procedure.
In Protected Mode, the action of the IRET instruction depends on the settings of the NT (nested task) and VM flags
in the EFLAGS register and the VM flag in the EFLAGS image stored on the current stack. Depending on the setting
of these flags, the processor performs the following types of interrupt returns:
•
•
•
•
•
Return from virtual-8086 mode.
Return to virtual-8086 mode.
Intra-privilege level return.
Inter-privilege level return.
Return from nested task (task switch).
If the NT flag (EFLAGS register) is cleared, the IRET instruction performs a far return from the interrupt procedure,
without a task switch. The code segment being returned to must be equally or less privileged than the interrupt
handler routine (as indicated by the RPL field of the code segment selector popped from the stack).
As with a real-address mode interrupt return, the IRET instruction pops the return instruction pointer, return code
segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then
resumes execution of the interrupted program or procedure. If the return is to another privilege level, the IRET
instruction also pops the stack pointer and SS from the stack, before resuming program execution. If the return is
to virtual-8086 mode, the processor also pops the data segment registers from the stack.
If the NT flag is set, the IRET instruction performs a task switch (return) from a nested task (a task called with a
CALL instruction, an interrupt, or an exception) back to the calling or interrupted task. The updated state of the
task executing the IRET instruction is saved in its TSS. If the task is re-entered later, the code that follows the IRET
instruction is executed.
If the NT flag is set and the processor is in IA-32e mode, the IRET instruction causes a general protection exception.
If nonmaskable interrupts (NMIs) are blocked (see Section 6.7.1, “Handling Multiple NMIs” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A), execution of the IRET instruction unblocks NMIs.
3-476 Vol. 2A
IRET/IRETD—Interrupt Return
INSTRUCTION SET REFERENCE, A-L
This unblocking occurs even if the instruction causes a fault. In such a case, NMIs are unmasked before the exception handler is invoked.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.W prefix promotes operation to 64
bits (IRETQ). See the summary chart at the beginning of this section for encoding data and limits.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.
Operation
IF PE = 0
THEN GOTO REAL-ADDRESS-MODE;
ELSIF (IA32_EFER.LMA = 0)
THEN
IF (EFLAGS.VM = 1)
THEN GOTO RETURN-FROM-VIRTUAL-8086-MODE;
ELSE GOTO PROTECTED-MODE;
FI;
ELSE GOTO IA-32e-MODE;
FI;
REAL-ADDRESS-MODE;
IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
tempEFLAGS ← Pop();
EFLAGS ← (tempEFLAGS AND 257FD5H) OR (EFLAGS AND 1A0000H);
ELSE (* OperandSize = 16 *)
EIP ← Pop(); (* 16-bit pop; clear upper 16 bits *)
CS ← Pop(); (* 16-bit pop *)
EFLAGS[15:0] ← Pop();
FI;
END;
RETURN-FROM-VIRTUAL-8086-MODE:
(* Processor is in virtual-8086 mode when IRET is executed and stays in virtual-8086 mode *)
IF IOPL = 3 (* Virtual mode: PE = 1, VM = 1, IOPL = 3 *)
THEN IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
EFLAGS ← Pop();
(* VM, IOPL,VIP and VIF EFLAG bits not modified by pop *)
IF EIP not within CS limit
THEN #GP(0); FI;
ELSE (* OperandSize = 16 *)
EIP ← Pop(); (* 16-bit pop; clear upper 16 bits *)
CS ← Pop(); (* 16-bit pop *)
EFLAGS[15:0] ← Pop(); (* IOPL in EFLAGS not modified by pop *)
IF EIP not within CS limit
THEN #GP(0); FI;
FI;
ELSE
IRET/IRETD—Interrupt Return
Vol. 2A 3-477
INSTRUCTION SET REFERENCE, A-L
#GP(0); (* Trap to virtual-8086 monitor: PE
FI;
END;
= 1, VM = 1, IOPL < 3 *)
PROTECTED-MODE:
IF NT = 1
THEN GOTO TASK-RETURN; (* PE = 1, VM = 0, NT = 1 *)
FI;
IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
tempEFLAGS ← Pop();
ELSE (* OperandSize = 16 *)
EIP ← Pop(); (* 16-bit pop; clear upper bits *)
CS ← Pop(); (* 16-bit pop *)
tempEFLAGS ← Pop(); (* 16-bit pop; clear upper bits *)
FI;
IF tempEFLAGS(VM) = 1 and CPL = 0
THEN GOTO RETURN-TO-VIRTUAL-8086-MODE;
ELSE GOTO PROTECTED-MODE-RETURN;
FI;
TASK-RETURN: (* PE = 1, VM = 0, NT = 1 *)
SWITCH-TASKS (without nesting) to TSS specified in link field of current TSS;
Mark the task just abandoned as NOT BUSY;
IF EIP is not within CS limit
THEN #GP(0); FI;
END;
RETURN-TO-VIRTUAL-8086-MODE:
(* Interrupted procedure was in virtual-8086 mode: PE = 1, CPL=0, VM
IF EIP not within CS limit
THEN #GP(0); FI;
EFLAGS ← tempEFLAGS;
ESP ← Pop();
SS ← Pop(); (* Pop 2 words; throw away high-order word *)
ES ← Pop(); (* Pop 2 words; throw away high-order word *)
DS ← Pop(); (* Pop 2 words; throw away high-order word *)
FS ← Pop(); (* Pop 2 words; throw away high-order word *)
GS ← Pop(); (* Pop 2 words; throw away high-order word *)
CPL ← 3;
(* Resume execution in Virtual-8086 mode *)
END;
= 1 in flag image *)
PROTECTED-MODE-RETURN: (* PE = 1 *)
IF CS(RPL) > CPL
THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;
ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL; FI;
END;
RETURN-TO-OUTER-PRIVILEGE-LEVEL:
IF OperandSize = 32
THEN
3-478 Vol. 2A
IRET/IRETD—Interrupt Return
INSTRUCTION SET REFERENCE, A-L
ESP ← Pop();
SS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
ELSE IF OperandSize = 16
THEN
ESP ← Pop(); (* 16-bit pop; clear upper bits *)
SS ← Pop(); (* 16-bit pop *)
ELSE (* OperandSize = 64 *)
RSP ← Pop();
SS ← Pop(); (* 64-bit pop, high-order 48 bits discarded *)
FI;
IF new mode ≠ 64-Bit Mode
THEN
IF EIP is not within CS limit
THEN #GP(0); FI;
ELSE (* new mode = 64-bit mode *)
IF RIP is non-canonical
THEN #GP(0); FI;
FI;
EFLAGS (CF, PF, AF, ZF, SF, TF, DF, OF, NT) ← tempEFLAGS;
IF OperandSize = 32
THEN EFLAGS(RF, AC, ID) ← tempEFLAGS; FI;
IF CPL ≤ IOPL
THEN EFLAGS(IF) ← tempEFLAGS; FI;
IF CPL = 0
THEN
EFLAGS(IOPL) ← tempEFLAGS;
IF OperandSize = 32
THEN EFLAGS(VM, VIF, VIP) ← tempEFLAGS; FI;
IF OperandSize = 64
THEN EFLAGS(VIF, VIP) ← tempEFLAGS; FI;
FI;
CPL ← CS(RPL);
FOR each SegReg in (ES, FS, GS, and DS)
DO
tempDesc ← descriptor cache for SegReg (* hidden part of segment register *)
IF tempDesc(DPL) < CPL AND tempDesc(Type) is data or non-conforming code
THEN (* Segment register invalid *)
SegReg ← NULL;
FI;
OD;
END;
RETURN-TO-SAME-PRIVILEGE-LEVEL: (* PE = 1, RPL = CPL *)
IF new mode ≠ 64-Bit Mode
THEN
IF EIP is not within CS limit
THEN #GP(0); FI;
ELSE (* new mode = 64-bit mode *)
IF RIP is non-canonical
THEN #GP(0); FI;
FI;
EFLAGS (CF, PF, AF, ZF, SF, TF, DF, OF, NT) ← tempEFLAGS;
IF OperandSize = 32 or OperandSize = 64
THEN EFLAGS(RF, AC, ID) ← tempEFLAGS; FI;
IRET/IRETD—Interrupt Return
Vol. 2A 3-479
INSTRUCTION SET REFERENCE, A-L
IF CPL ≤ IOPL
THEN EFLAGS(IF) ← tempEFLAGS; FI;
IF CPL = 0
THEN (* VM = 0 in flags image *)
EFLAGS(IOPL) ← tempEFLAGS;
IF OperandSize = 32 or OperandSize = 64
THEN EFLAGS(VIF, VIP) ← tempEFLAGS; FI;
FI;
END;
IA-32e-MODE:
IF NT = 1
THEN #GP(0);
ELSE IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop();
tempEFLAGS ← Pop();
ELSE IF OperandSize = 16
THEN
EIP ← Pop(); (* 16-bit pop; clear upper bits *)
CS ← Pop(); (* 16-bit pop *)
tempEFLAGS ← Pop(); (* 16-bit pop; clear upper bits *)
FI;
ELSE (* OperandSize = 64 *)
THEN
RIP ← Pop();
CS ← Pop(); (* 64-bit pop, high-order 48 bits discarded *)
tempRFLAGS ← Pop();
FI;
IF tempCS.RPL > CPL
THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;
ELSE
IF instruction began in 64-Bit Mode
THEN
IF OperandSize = 32
THEN
ESP ← Pop();
SS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
ELSE IF OperandSize = 16
THEN
ESP ← Pop(); (* 16-bit pop; clear upper bits *)
SS ← Pop(); (* 16-bit pop *)
ELSE (* OperandSize = 64 *)
RSP ← Pop();
SS ← Pop(); (* 64-bit pop, high-order 48 bits discarded *)
FI;
FI;
GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL; FI;
END;
3-480 Vol. 2A
IRET/IRETD—Interrupt Return
INSTRUCTION SET REFERENCE, A-L
Flags Affected
All the flags and fields in the EFLAGS register are potentially modified, depending on the mode of operation of the
processor. If performing a return from a nested task to a previous task, the EFLAGS register will be modified
according to the EFLAGS image stored in the previous task’s TSS.
Protected Mode Exceptions
#GP(0)
If the return code or stack segment selector is NULL.
If the return instruction pointer is not within the return code segment limit.
#GP(selector)
If a segment selector index is outside its descriptor table limits.
If the return code segment selector RPL is less than the CPL.
If the DPL of a conforming-code segment is greater than the return code segment selector
RPL.
If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment
selector.
If the stack segment descriptor DPL is not equal to the RPL of the return code segment
selector.
If the stack segment is not a writable data segment.
If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
If the segment descriptor for a code segment does not indicate it is a code segment.
If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is not busy.
If a TSS segment descriptor specifies that the TSS is not available.
#SS(0)
If the top bytes of stack are not within stack limits.
#NP(selector)
If the return code or stack segment is not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference occurs when the CPL is 3 and alignment checking is
enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If the return instruction pointer is not within the return code segment limit.
#SS
If the top bytes of stack are not within stack limits.
Virtual-8086 Mode Exceptions
#GP(0)
If the return instruction pointer is not within the return code segment limit.
IF IOPL not equal to 3.
#PF(fault-code)
If a page fault occurs.
#SS(0)
If the top bytes of stack are not within stack limits.
#AC(0)
If an unaligned memory reference occurs and alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#GP(0)
If EFLAGS.NT[bit 14] = 1.
Other exceptions same as in Protected Mode.
IRET/IRETD—Interrupt Return
Vol. 2A 3-481
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
#GP(0)
If EFLAGS.NT[bit 14] = 1.
If the return code segment selector is NULL.
If the stack segment selector is NULL going back to compatibility mode.
If the stack segment selector is NULL going back to CPL3 64-bit mode.
If a NULL stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bit mode.
If the return instruction pointer is not within the return code segment limit.
If the return instruction pointer is non-canonical.
#GP(Selector)
If a segment selector index is outside its descriptor table limits.
If a segment descriptor memory address is non-canonical.
If the segment descriptor for a code segment does not indicate it is a code segment.
If the proposed new code segment descriptor has both the D-bit and L-bit set.
If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment
selector.
If CPL is greater than the RPL of the code segment selector.
If the DPL of a conforming-code segment is greater than the return code segment selector
RPL.
If the stack segment is not a writable data segment.
If the stack segment descriptor DPL is not equal to the RPL of the return code segment
selector.
If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
#SS(0)
If an attempt to pop a value off the stack violates the SS limit.
If an attempt to pop a value off the stack causes a non-canonical address to be referenced.
#NP(selector)
If the return code or stack segment is not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference occurs when the CPL is 3 and alignment checking is
enabled.
#UD
If the LOCK prefix is used.
3-482 Vol. 2A
IRET/IRETD—Interrupt Return
INSTRUCTION SET REFERENCE, A-L
Jcc—Jump if Condition Is Met
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
77 cb
JA rel8
D
Valid
Valid
73 cb
JAE rel8
D
Valid
Valid
Jump short if above or equal (CF=0).
72 cb
JB rel8
D
Valid
Valid
Jump short if below (CF=1).
76 cb
JBE rel8
D
Valid
Valid
Jump short if below or equal (CF=1 or ZF=1).
72 cb
JC rel8
D
Valid
Valid
Jump short if carry (CF=1).
Jump short if above (CF=0 and ZF=0).
E3 cb
JCXZ rel8
D
N.E.
Valid
Jump short if CX register is 0.
E3 cb
JECXZ rel8
D
Valid
Valid
Jump short if ECX register is 0.
E3 cb
JRCXZ rel8
D
Valid
N.E.
Jump short if RCX register is 0.
74 cb
JE rel8
D
Valid
Valid
Jump short if equal (ZF=1).
7F cb
JG rel8
D
Valid
Valid
Jump short if greater (ZF=0 and SF=OF).
7D cb
JGE rel8
D
Valid
Valid
Jump short if greater or equal (SF=OF).
7C cb
JL rel8
D
Valid
Valid
Jump short if less (SF≠ OF).
7E cb
JLE rel8
D
Valid
Valid
Jump short if less or equal (ZF=1 or SF≠ OF).
76 cb
JNA rel8
D
Valid
Valid
Jump short if not above (CF=1 or ZF=1).
72 cb
JNAE rel8
D
Valid
Valid
Jump short if not above or equal (CF=1).
73 cb
JNB rel8
D
Valid
Valid
Jump short if not below (CF=0).
77 cb
JNBE rel8
D
Valid
Valid
Jump short if not below or equal (CF=0 and
ZF=0).
73 cb
JNC rel8
D
Valid
Valid
Jump short if not carry (CF=0).
75 cb
JNE rel8
D
Valid
Valid
Jump short if not equal (ZF=0).
7E cb
JNG rel8
D
Valid
Valid
Jump short if not greater (ZF=1 or SF≠ OF).
7C cb
JNGE rel8
D
Valid
Valid
Jump short if not greater or equal (SF≠ OF).
7D cb
JNL rel8
D
Valid
Valid
Jump short if not less (SF=OF).
7F cb
JNLE rel8
D
Valid
Valid
Jump short if not less or equal (ZF=0 and
SF=OF).
71 cb
JNO rel8
D
Valid
Valid
Jump short if not overflow (OF=0).
7B cb
JNP rel8
D
Valid
Valid
Jump short if not parity (PF=0).
79 cb
JNS rel8
D
Valid
Valid
Jump short if not sign (SF=0).
75 cb
JNZ rel8
D
Valid
Valid
Jump short if not zero (ZF=0).
70 cb
JO rel8
D
Valid
Valid
Jump short if overflow (OF=1).
7A cb
JP rel8
D
Valid
Valid
Jump short if parity (PF=1).
7A cb
JPE rel8
D
Valid
Valid
Jump short if parity even (PF=1).
7B cb
JPO rel8
D
Valid
Valid
Jump short if parity odd (PF=0).
78 cb
JS rel8
D
Valid
Valid
Jump short if sign (SF=1).
74 cb
JZ rel8
D
Valid
Valid
Jump short if zero (ZF = 1).
0F 87 cw
JA rel16
D
N.S.
Valid
Jump near if above (CF=0 and ZF=0). Not
supported in 64-bit mode.
0F 87 cd
JA rel32
D
Valid
Valid
Jump near if above (CF=0 and ZF=0).
0F 83 cw
JAE rel16
D
N.S.
Valid
Jump near if above or equal (CF=0). Not
supported in 64-bit mode.
Jcc—Jump if Condition Is Met
Vol. 2A 3-483
INSTRUCTION SET REFERENCE, A-L
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 83 cd
JAE rel32
D
Valid
Valid
Jump near if above or equal (CF=0).
0F 82 cw
JB rel16
D
N.S.
Valid
Jump near if below (CF=1). Not supported in
64-bit mode.
0F 82 cd
JB rel32
D
Valid
Valid
Jump near if below (CF=1).
0F 86 cw
JBE rel16
D
N.S.
Valid
Jump near if below or equal (CF=1 or ZF=1).
Not supported in 64-bit mode.
0F 86 cd
JBE rel32
D
Valid
Valid
Jump near if below or equal (CF=1 or ZF=1).
0F 82 cw
JC rel16
D
N.S.
Valid
Jump near if carry (CF=1). Not supported in
64-bit mode.
0F 82 cd
JC rel32
D
Valid
Valid
Jump near if carry (CF=1).
0F 84 cw
JE rel16
D
N.S.
Valid
Jump near if equal (ZF=1). Not supported in
64-bit mode.
0F 84 cd
JE rel32
D
Valid
Valid
Jump near if equal (ZF=1).
0F 84 cw
JZ rel16
D
N.S.
Valid
Jump near if 0 (ZF=1). Not supported in 64-bit
mode.
0F 84 cd
JZ rel32
D
Valid
Valid
Jump near if 0 (ZF=1).
0F 8F cw
JG rel16
D
N.S.
Valid
Jump near if greater (ZF=0 and SF=OF). Not
supported in 64-bit mode.
0F 8F cd
JG rel32
D
Valid
Valid
Jump near if greater (ZF=0 and SF=OF).
0F 8D cw
JGE rel16
D
N.S.
Valid
Jump near if greater or equal (SF=OF). Not
supported in 64-bit mode.
0F 8D cd
JGE rel32
D
Valid
Valid
Jump near if greater or equal (SF=OF).
0F 8C cw
JL rel16
D
N.S.
Valid
Jump near if less (SF≠ OF). Not supported in
64-bit mode.
0F 8C cd
JL rel32
D
Valid
Valid
Jump near if less (SF≠ OF).
0F 8E cw
JLE rel16
D
N.S.
Valid
Jump near if less or equal (ZF=1 or SF≠ OF).
Not supported in 64-bit mode.
0F 8E cd
JLE rel32
D
Valid
Valid
Jump near if less or equal (ZF=1 or SF≠ OF).
0F 86 cw
JNA rel16
D
N.S.
Valid
Jump near if not above (CF=1 or ZF=1). Not
supported in 64-bit mode.
0F 86 cd
JNA rel32
D
Valid
Valid
Jump near if not above (CF=1 or ZF=1).
0F 82 cw
JNAE rel16
D
N.S.
Valid
Jump near if not above or equal (CF=1). Not
supported in 64-bit mode.
0F 82 cd
JNAE rel32
D
Valid
Valid
Jump near if not above or equal (CF=1).
0F 83 cw
JNB rel16
D
N.S.
Valid
Jump near if not below (CF=0). Not supported
in 64-bit mode.
0F 83 cd
JNB rel32
D
Valid
Valid
Jump near if not below (CF=0).
0F 87 cw
JNBE rel16
D
N.S.
Valid
Jump near if not below or equal (CF=0 and
ZF=0). Not supported in 64-bit mode.
0F 87 cd
JNBE rel32
D
Valid
Valid
Jump near if not below or equal (CF=0 and
ZF=0).
0F 83 cw
JNC rel16
D
N.S.
Valid
Jump near if not carry (CF=0). Not supported
in 64-bit mode.
0F 83 cd
JNC rel32
D
Valid
Valid
Jump near if not carry (CF=0).
3-484 Vol. 2A
Jcc—Jump if Condition Is Met
INSTRUCTION SET REFERENCE, A-L
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 85 cw
JNE rel16
D
N.S.
Valid
Jump near if not equal (ZF=0). Not supported
in 64-bit mode.
0F 85 cd
JNE rel32
D
Valid
Valid
Jump near if not equal (ZF=0).
0F 8E cw
JNG rel16
D
N.S.
Valid
Jump near if not greater (ZF=1 or SF≠ OF).
Not supported in 64-bit mode.
0F 8E cd
JNG rel32
D
Valid
Valid
Jump near if not greater (ZF=1 or SF≠ OF).
0F 8C cw
JNGE rel16
D
N.S.
Valid
Jump near if not greater or equal (SF≠ OF).
Not supported in 64-bit mode.
0F 8C cd
JNGE rel32
D
Valid
Valid
Jump near if not greater or equal (SF≠ OF).
0F 8D cw
JNL rel16
D
N.S.
Valid
Jump near if not less (SF=OF). Not supported
in 64-bit mode.
0F 8D cd
JNL rel32
D
Valid
Valid
Jump near if not less (SF=OF).
0F 8F cw
JNLE rel16
D
N.S.
Valid
Jump near if not less or equal (ZF=0 and
SF=OF). Not supported in 64-bit mode.
0F 8F cd
JNLE rel32
D
Valid
Valid
Jump near if not less or equal (ZF=0 and
SF=OF).
0F 81 cw
JNO rel16
D
N.S.
Valid
Jump near if not overflow (OF=0). Not
supported in 64-bit mode.
0F 81 cd
JNO rel32
D
Valid
Valid
Jump near if not overflow (OF=0).
0F 8B cw
JNP rel16
D
N.S.
Valid
Jump near if not parity (PF=0). Not supported
in 64-bit mode.
0F 8B cd
JNP rel32
D
Valid
Valid
Jump near if not parity (PF=0).
0F 89 cw
JNS rel16
D
N.S.
Valid
Jump near if not sign (SF=0). Not supported in
64-bit mode.
0F 89 cd
JNS rel32
D
Valid
Valid
Jump near if not sign (SF=0).
0F 85 cw
JNZ rel16
D
N.S.
Valid
Jump near if not zero (ZF=0). Not supported in
64-bit mode.
0F 85 cd
JNZ rel32
D
Valid
Valid
Jump near if not zero (ZF=0).
0F 80 cw
JO rel16
D
N.S.
Valid
Jump near if overflow (OF=1). Not supported
in 64-bit mode.
0F 80 cd
JO rel32
D
Valid
Valid
Jump near if overflow (OF=1).
0F 8A cw
JP rel16
D
N.S.
Valid
Jump near if parity (PF=1). Not supported in
64-bit mode.
0F 8A cd
JP rel32
D
Valid
Valid
Jump near if parity (PF=1).
0F 8A cw
JPE rel16
D
N.S.
Valid
Jump near if parity even (PF=1). Not
supported in 64-bit mode.
0F 8A cd
JPE rel32
D
Valid
Valid
Jump near if parity even (PF=1).
0F 8B cw
JPO rel16
D
N.S.
Valid
Jump near if parity odd (PF=0). Not supported
in 64-bit mode.
0F 8B cd
JPO rel32
D
Valid
Valid
Jump near if parity odd (PF=0).
0F 88 cw
JS rel16
D
N.S.
Valid
Jump near if sign (SF=1). Not supported in 64bit mode.
Jcc—Jump if Condition Is Met
Vol. 2A 3-485
INSTRUCTION SET REFERENCE, A-L
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 88 cd
JS rel32
D
Valid
Valid
Jump near if sign (SF=1).
0F 84 cw
JZ rel16
D
N.S.
Valid
Jump near if 0 (ZF=1). Not supported in 64-bit
mode.
0F 84 cd
JZ rel32
D
Valid
Valid
Jump near if 0 (ZF=1).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
D
Offset
NA
NA
NA
Description
Checks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags
are in the specified state (condition), performs a jump to the target instruction specified by the destination
operand. A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the
condition is not satisfied, the jump is not performed and execution continues with the instruction following the Jcc
instruction.
The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly
code, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to
the instruction pointer. Instruction coding is most efficient for offsets of –128 to +127. If the operand-size attribute
is 16, the upper two bytes of the EIP register are cleared, resulting in a maximum instruction pointer size of 16 bits.
The conditions for each Jcc mnemonic are given in the “Description” column of the table on the preceding page. The
terms “less” and “greater” are used for comparisons of signed integers and the terms “above” and “below” are used
for unsigned integers.
Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are
defined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or
equal) instruction are alternate mnemonics for the opcode 77H.
The Jcc instruction does not support far jumps (jumps to other code segments). When the target for the conditional
jump is in a different segment, use the opposite condition from the condition being tested for the Jcc instruction,
and then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the
following conditional far jump is illegal:
JZ FARLABEL;
To accomplish this far jump, use the following two instructions:
JNZ BEYOND;
JMP FARLABEL;
BEYOND:
The JRCXZ, JECXZ and JCXZ instructions differ from other Jcc instructions because they do not check status flags.
Instead, they check RCX, ECX or CX for 0. The register checked is determined by the address-size attribute. These
instructions are useful when used at the beginning of a loop that terminates with a conditional loop instruction
(such as LOOPNE). They can be used to prevent an instruction sequence from entering a loop when RCX, ECX or CX
is 0. This would cause the loop to execute 264, 232 or 64K times (not zero times).
All conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cacheability.
In 64-bit mode, operand size is fixed at 64 bits. JMP Short is RIP = RIP + 8-bit offset sign extended to 64 bits. JMP
Near is RIP = RIP + 32-bit offset sign extended to 64-bits.
3-486 Vol. 2A
Jcc—Jump if Condition Is Met
INSTRUCTION SET REFERENCE, A-L
Operation
IF condition
THEN
tempEIP ← EIP + SignExtend(DEST);
IF OperandSize = 16
THEN tempEIP ← tempEIP AND 0000FFFFH;
FI;
IF tempEIP is not within code segment limit
THEN #GP(0);
ELSE EIP ← tempEIP
FI;
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the offset being jumped to is beyond the limits of the CS segment.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH. This condition can occur if a 32-bit address size override
prefix is used.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#UD
If the LOCK prefix is used.
Jcc—Jump if Condition Is Met
Vol. 2A 3-487
INSTRUCTION SET REFERENCE, A-L
JMP—Jump
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
EB cb
JMP rel8
D
Valid
Valid
Jump short, RIP = RIP + 8-bit displacement sign
extended to 64-bits
E9 cw
JMP rel16
D
N.S.
Valid
Jump near, relative, displacement relative to
next instruction. Not supported in 64-bit
mode.
E9 cd
JMP rel32
D
Valid
Valid
Jump near, relative, RIP = RIP + 32-bit
displacement sign extended to 64-bits
FF /4
JMP r/m16
M
N.S.
Valid
Jump near, absolute indirect, address = zeroextended r/m16. Not supported in 64-bit
mode.
FF /4
JMP r/m32
M
N.S.
Valid
Jump near, absolute indirect, address given in
r/m32. Not supported in 64-bit mode.
FF /4
JMP r/m64
M
Valid
N.E.
Jump near, absolute indirect, RIP = 64-Bit
offset from register or memory
EA cd
JMP ptr16:16
D
Inv.
Valid
Jump far, absolute, address given in operand
EA cp
JMP ptr16:32
D
Inv.
Valid
Jump far, absolute, address given in operand
FF /5
JMP m16:16
D
Valid
Valid
Jump far, absolute indirect, address given in
m16:16
FF /5
JMP m16:32
D
Valid
Valid
Jump far, absolute indirect, address given in
m16:32.
REX.W + FF /5
JMP m16:64
D
Valid
N.E.
Jump far, absolute indirect, address given in
m16:64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
D
Offset
NA
NA
NA
M
ModRM:r/m (r)
NA
NA
NA
Description
Transfers program control to a different point in the instruction stream without recording return information. The
destination (target) operand specifies the address of the instruction being jumped to. This operand can be an
immediate value, a general-purpose register, or a memory location.
This instruction can be used to execute four different types of jumps:
•
Near jump—A jump to an instruction within the current code segment (the segment currently pointed to by the
CS register), sometimes referred to as an intrasegment jump.
•
•
Short jump—A near jump where the jump range is limited to –128 to +127 from the current EIP value.
•
Far jump—A jump to an instruction located in a different segment than the current code segment but at the
same privilege level, sometimes referred to as an intersegment jump.
Task switch—A jump to an instruction located in a different task.
A task switch can only be executed in protected mode (see Chapter 7, in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A, for information on performing task switches with the JMP instruction).
Near and Short Jumps. When executing a near jump, the processor jumps to the address (within the current code
segment) that is specified with the target operand. The target operand specifies either an absolute offset (that is
an offset from the base of the code segment) or a relative offset (a signed displacement relative to the current
3-488 Vol. 2A
JMP—Jump
INSTRUCTION SET REFERENCE, A-L
value of the instruction pointer in the EIP register). A near jump to a relative offset of 8-bits (rel8) is referred to as
a short jump. The CS register is not changed on near and short jumps.
An absolute offset is specified indirectly in a general-purpose register or a memory location (r/m16 or r/m32). The
operand-size attribute determines the size of the target operand (16 or 32 bits). Absolute offsets are loaded
directly into the EIP register. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared,
resulting in a maximum instruction pointer size of 16 bits.
A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code
level, it is encoded as a signed 8-, 16-, or 32-bit immediate value. This value is added to the value in the EIP
register. (Here, the EIP register contains the address of the instruction following the JMP instruction). When using
relative offsets, the opcode (for short vs. near jumps) and the operand-size attribute (for near relative jumps)
determines the size of the target operand (8, 16, or 32 bits).
Far Jumps in Real-Address or Virtual-8086 Mode. When executing a far jump in real-address or virtual-8086 mode,
the processor jumps to the code segment and offset specified with the target operand. Here the target operand
specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory
location (m16:16 or m16:32). With the pointer method, the segment and address of the called procedure is
encoded in the instruction, using a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address immediate. With the indirect method, the target operand specifies a memory location that contains a 4-byte (16-bit
operand size) or 6-byte (32-bit operand size) far address. The far address is loaded directly into the CS and EIP
registers. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared.
Far Jumps in Protected Mode. When the processor is operating in protected mode, the JMP instruction can be used
to perform the following three types of far jumps:
•
•
•
A far jump to a conforming or non-conforming code segment.
A far jump through a call gate.
A task switch.
(The JMP instruction cannot be used to perform inter-privilege-level far jumps.)
In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access
rights determine the type of jump to be performed.
If the selected descriptor is for a code segment, a far jump to a code segment at the same privilege level is
performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,
a general-protection exception is generated.) A far jump to the same privilege level in protected mode is very
similar to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far
address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or
m16:32). The operand-size attribute determines the size of the offset (16 or 32 bits) in the far address. The new
code segment selector and its descriptor are loaded into CS register, and the offset from the instruction is loaded
into the EIP register. Note that a call gate (described in the next paragraph) can also be used to perform far call to
a code segment at the same privilege level. Using this mechanism provides an extra level of indirection and is the
preferred method of making jumps between 16-bit and 32-bit code segments.
When executing a far jump through a call gate, the segment selector specified by the target operand identifies the
call gate. (The offset part of the target operand is ignored.) The processor then jumps to the code segment specified in the call gate descriptor and begins executing the instruction at the offset specified in the call gate. No stack
switch occurs. Here again, the target operand can specify the far address of the call gate either directly with a
pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32).
Executing a task switch with the JMP instruction is somewhat similar to executing a jump through a call gate. Here
the target operand specifies the segment selector of the task gate for the task being switched to (and the offset
part of the target operand is ignored). The task gate in turn points to the TSS for the task, which contains the
segment selectors for the task’s code and stack segments. The TSS also contains the EIP value for the next instruction that was to be executed before the task was suspended. This instruction pointer value is loaded into the EIP
register so that the task begins executing again at this next instruction.
The JMP instruction can also specify the segment selector of the TSS directly, which eliminates the indirection of the
task gate. See Chapter 7 in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for
detailed information on the mechanics of a task switch.
JMP—Jump
Vol. 2A 3-489
INSTRUCTION SET REFERENCE, A-L
Note that when you execute at task switch with a JMP instruction, the nested task flag (NT) is not set in the EFLAGS
register and the new TSS’s previous task link field is not loaded with the old task’s TSS selector. A return to the
previous task can thus not be carried out by executing the IRET instruction. Switching tasks with the JMP instruction differs in this regard from the CALL instruction which does set the NT flag and save the previous task link information, allowing a return to the calling task with an IRET instruction.
In 64-Bit Mode — The instruction’s operation size is fixed at 64 bits. If a selector points to a gate, then RIP equals
the 64-bit displacement taken from gate; else RIP equals the zero-extended offset from the far pointer referenced
in the instruction.
See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF near jump
IF 64-bit Mode
THEN
IF near relative jump
THEN
tempRIP ← RIP + DEST; (* RIP is instruction following JMP instruction*)
ELSE (* Near absolute jump *)
tempRIP ← DEST;
FI;
ELSE
IF near relative jump
THEN
tempEIP ← EIP + DEST; (* EIP is instruction following JMP instruction*)
ELSE (* Near absolute jump *)
tempEIP ← DEST;
FI;
FI;
IF (IA32_EFER.LMA = 0 or target mode = Compatibility mode)
and tempEIP outside code segment limit
THEN #GP(0); FI
IF 64-bit mode and tempRIP is not canonical
THEN #GP(0);
FI;
IF OperandSize = 32
THEN
EIP ← tempEIP;
ELSE
IF OperandSize = 16
THEN (* OperandSize = 16 *)
EIP ← tempEIP AND 0000FFFFH;
ELSE (* OperandSize = 64)
RIP ← tempRIP;
FI;
FI;
FI;
IF far jump and (PE = 0 or (PE = 1 AND VM = 1)) (* Real-address or virtual-8086 mode *)
THEN
tempEIP ← DEST(Offset); (* DEST is ptr16:32 or [m16:32] *)
IF tempEIP is beyond code segment limit
THEN #GP(0); FI;
CS ← DEST(segment selector); (* DEST is ptr16:32 or [m16:32] *)
IF OperandSize = 32
3-490 Vol. 2A
JMP—Jump
INSTRUCTION SET REFERENCE, A-L
THEN
EIP ← tempEIP; (* DEST is ptr16:32 or [m16:32] *)
ELSE (* OperandSize = 16 *)
EIP ← tempEIP AND 0000FFFFH; (* Clear upper 16 bits *)
FI;
FI;
IF far jump and (PE = 1 and VM = 0)
(* IA-32e mode or protected mode, not virtual-8086 mode *)
THEN
IF effective address in the CS, DS, ES, FS, GS, or SS segment is illegal
or segment selector in target operand NULL
THEN #GP(0); FI;
IF segment selector index not within descriptor table limits
THEN #GP(new selector); FI;
Read type and access rights of segment descriptor;
IF (EFER.LMA = 0)
THEN
IF segment type is not a conforming or nonconforming code
segment, call gate, task gate, or TSS
THEN #GP(segment selector); FI;
ELSE
IF segment type is not a conforming or nonconforming code segment
call gate
THEN #GP(segment selector); FI;
FI;
Depending on type and access rights:
GO TO CONFORMING-CODE-SEGMENT;
GO TO NONCONFORMING-CODE-SEGMENT;
GO TO CALL-GATE;
GO TO TASK-GATE;
GO TO TASK-STATE-SEGMENT;
ELSE
#GP(segment selector);
FI;
CONFORMING-CODE-SEGMENT:
IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1
THEN GP(new code segment selector); FI;
IF DPL > CPL
THEN #GP(segment selector); FI;
IF segment not present
THEN #NP(segment selector); FI;
tempEIP ← DEST(Offset);
IF OperandSize = 16
THEN tempEIP ← tempEIP AND 0000FFFFH;
FI;
IF (IA32_EFER.LMA = 0 or target mode = Compatibility mode) and
tempEIP outside code segment limit
THEN #GP(0); FI
IF tempEIP is non-canonical
THEN #GP(0); FI;
CS ← DEST[segment selector]; (* Segment descriptor information also loaded *)
CS(RPL) ← CPL
EIP ← tempEIP;
END;
JMP—Jump
Vol. 2A 3-491
INSTRUCTION SET REFERENCE, A-L
NONCONFORMING-CODE-SEGMENT:
IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1
THEN GP(new code segment selector); FI;
IF (RPL > CPL) OR (DPL ≠ CPL)
THEN #GP(code segment selector); FI;
IF segment not present
THEN #NP(segment selector); FI;
tempEIP ← DEST(Offset);
IF OperandSize = 16
THEN tempEIP ← tempEIP AND 0000FFFFH; FI;
IF (IA32_EFER.LMA = 0 OR target mode = Compatibility mode)
and tempEIP outside code segment limit
THEN #GP(0); FI
IF tempEIP is non-canonical THEN #GP(0); FI;
CS ← DEST[segment selector]; (* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
END;
CALL-GATE:
IF call gate DPL < CPL
or call gate DPL < call gate segment-selector RPL
THEN #GP(call gate selector); FI;
IF call gate not present
THEN #NP(call gate selector); FI;
IF call gate code-segment selector is NULL
THEN #GP(0); FI;
IF call gate code-segment selector index outside descriptor table limits
THEN #GP(code segment selector); FI;
Read code segment descriptor;
IF code-segment segment descriptor does not indicate a code segment
or code-segment segment descriptor is conforming and DPL > CPL
or code-segment segment descriptor is non-conforming and DPL ≠ CPL
THEN #GP(code segment selector); FI;
IF IA32_EFER.LMA = 1 and (code-segment descriptor is not a 64-bit code segment
or code-segment segment descriptor has both L-Bit and D-bit set)
THEN #GP(code segment selector); FI;
IF code segment is not present
THEN #NP(code-segment selector); FI;
IF instruction pointer is not within code-segment limit
THEN #GP(0); FI;
tempEIP ← DEST(Offset);
IF GateSize = 16
THEN tempEIP ← tempEIP AND 0000FFFFH; FI;
IF (IA32_EFER.LMA = 0 OR target mode = Compatibility mode) AND tempEIP
outside code segment limit
THEN #GP(0); FI
CS ← DEST[SegmentSelector); (* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
END;
TASK-GATE:
IF task gate DPL < CPL
or task gate DPL < task gate segment-selector RPL
3-492 Vol. 2A
JMP—Jump
INSTRUCTION SET REFERENCE, A-L
THEN #GP(task gate selector); FI;
IF task gate not present
THEN #NP(gate selector); FI;
Read the TSS segment selector in the task-gate descriptor;
IF TSS segment selector local/global bit is set to local
or index not within GDT limits
or TSS descriptor specifies that the TSS is busy
THEN #GP(TSS selector); FI;
IF TSS not present
THEN #NP(TSS selector); FI;
SWITCH-TASKS to TSS;
IF EIP not within code segment limit
THEN #GP(0); FI;
END;
TASK-STATE-SEGMENT:
IF TSS DPL < CPL
or TSS DPL < TSS segment-selector RPL
or TSS descriptor indicates TSS not available
THEN #GP(TSS selector); FI;
IF TSS is not present
THEN #NP(TSS selector); FI;
SWITCH-TASKS to TSS;
IF EIP not within code segment limit
THEN #GP(0); FI;
END;
Flags Affected
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.
Protected Mode Exceptions
#GP(0)
If offset in target operand, call gate, or TSS is beyond the code segment limits.
If the segment selector in the destination operand, call gate, task gate, or TSS is NULL.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#GP(selector)
If the segment selector index is outside descriptor table limits.
If the segment descriptor pointed to by the segment selector in the destination operand is not
for a conforming-code segment, nonconforming-code segment, call gate, task gate, or task
state segment.
If the DPL for a nonconforming-code segment is not equal to the CPL
(When not using a call gate.) If the RPL for the segment’s segment selector is greater than the
CPL.
If the DPL for a conforming-code segment is greater than the CPL.
If the DPL from a call-gate, task-gate, or TSS segment descriptor is less than the CPL or than
the RPL of the call-gate, task-gate, or TSS’s segment selector.
If the segment descriptor for selector in a call gate does not indicate it is a code segment.
If the segment descriptor for the segment selector in a task gate does not indicate an available
TSS.
If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is busy or not available.
#SS(0)
JMP—Jump
If a memory operand effective address is outside the SS segment limit.
Vol. 2A 3-493
INSTRUCTION SET REFERENCE, A-L
#NP (selector)
If the code segment being accessed is not present.
If call gate, task gate, or TSS not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3. (Only occurs when fetching target from memory.)
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the target operand is beyond the code segment limits.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made. (Only occurs
when fetching target from memory.)
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as 64-bit mode exceptions.
64-Bit Mode Exceptions
#GP(0)
If a memory address is non-canonical.
If target offset in destination operand is non-canonical.
If target offset in destination operand is beyond the new code segment limit.
If the segment selector in the destination operand is NULL.
If the code segment selector in the 64-bit gate is NULL.
#GP(selector)
If the code segment or 64-bit call gate is outside descriptor table limits.
If the code segment or 64-bit call gate overlaps non-canonical space.
If the segment descriptor from a 64-bit call gate is in non-canonical space.
If the segment descriptor pointed to by the segment selector in the destination operand is not
for a conforming-code segment, nonconforming-code segment, 64-bit call gate.
If the segment descriptor pointed to by the segment selector in the destination operand is a
code segment, and has both the D-bit and the L-bit set.
If the DPL for a nonconforming-code segment is not equal to the CPL, or the RPL for the
segment’s segment selector is greater than the CPL.
If the DPL for a conforming-code segment is greater than the CPL.
If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.
If the upper type field of a 64-bit call gate is not 0x0.
If the segment selector from a 64-bit call gate is beyond the descriptor table limits.
If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the Lbit set and the D-bit clear.
If the segment descriptor for a segment selector from the 64-bit call gate does not indicate it
is a code segment.
If the code segment is non-conforming and CPL ≠ DPL.
3-494 Vol. 2A
JMP—Jump
INSTRUCTION SET REFERENCE, A-L
If the code segment is confirming and CPL < DPL.
#NP(selector)
If a code segment or 64-bit call gate is not present.
#UD
(64-bit mode only) If a far jump is direct to an absolute address in memory.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
If the LOCK prefix is used.
JMP—Jump
Vol. 2A 3-495
INSTRUCTION SET REFERENCE, A-L
KADDW/KADDB/KADDQ/KADDD—ADD Two Masks
Opcode/
Instruction
Op/En
CPUID
Feature
Flag
AVX512DQ
Description
RVR
64/32
bit Mode
Support
V/V
VEX.L1.0F.W0 4A /r
KADDW k1, k2, k3
VEX.L1.66.0F.W0 4A /r
KADDB k1, k2, k3
VEX.L1.0F.W1 4A /r
KADDQ k1, k2, k3
VEX.L1.66.0F.W1 4A /r
KADDD k1, k2, k3
RVR
V/V
AVX512DQ
Add 8 bits masks in k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Add 64 bits masks in k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Add 32 bits masks in k2 and k3 and place result in k1.
Add 16 bits masks in k2 and k3 and place result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RVR
ModRM:reg (w)
VEX.1vvv (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Adds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.
Operation
KADDW
DEST[15:0] SRC1[15:0] + SRC2[15:0]
DEST[MAX_KL-1:16] 0
KADDB
DEST[7:0] SRC1[7:0] + SRC2[7:0]
DEST[MAX_KL-1:8] 0
KADDQ
DEST[63:0] SRC1[63:0] + SRC2[63:0]
DEST[MAX_KL-1:64] 0
KADDD
DEST[31:0] SRC1[31:0] + SRC2[31:0]
DEST[MAX_KL-1:32] 0
Intel C/C++ Compiler Intrinsic Equivalent
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
3-496 Vol. 2A
KADDW/KADDB/KADDQ/KADDD—ADD Two Masks
INSTRUCTION SET REFERENCE, A-L
KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks
Opcode/
Instruction
Op/En
RVR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
VEX.NDS.L1.0F.W0 41 /r
KANDW k1, k2, k3
VEX.L1.66.0F.W0 41 /r
KANDB k1, k2, k3
VEX.L1.0F.W1 41 /r
KANDQ k1, k2, k3
VEX.L1.66.0F.W1 41 /r
KANDD k1, k2, k3
Description
Bitwise AND 16 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512DQ
Bitwise AND 8 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise AND 64 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise AND 32 bits masks k2 and k3 and place result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RVR
ModRM:reg (w)
VEX.1vvv (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask
k1.
Operation
KANDW
DEST[15:0] SRC1[15:0] BITWISE AND SRC2[15:0]
DEST[MAX_KL-1:16] 0
KANDB
DEST[7:0] SRC1[7:0] BITWISE AND SRC2[7:0]
DEST[MAX_KL-1:8] 0
KANDQ
DEST[63:0] SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64] 0
KANDD
DEST[31:0] SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[MAX_KL-1:32] 0
Intel C/C++ Compiler Intrinsic Equivalent
KANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks
Vol. 2A 3-497
INSTRUCTION SET REFERENCE, A-L
KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks
Opcode/
Instruction
Op/En
RVR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
VEX.NDS.L1.0F.W0 42 /r
KANDNW k1, k2, k3
VEX.L1.66.0F.W0 42 /r
KANDNB k1, k2, k3
VEX.L1.0F.W1 42 /r
KANDNQ k1, k2, k3
VEX.L1.66.0F.W1 42 /r
KANDND k1, k2, k3
Description
RVR
V/V
AVX512DQ
RVR
V/V
AVX512BW
RVR
V/V
AVX512BW
Bitwise AND NOT 16 bits masks k2 and k3 and place result in
k1.
Bitwise AND NOT 8 bits masks k1 and k2 and place result in k1.
Bitwise AND NOT 64 bits masks k2 and k3 and place result in
k1.
Bitwise AND NOT 32 bits masks k2 and k3 and place result in
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RVR
ModRM:reg (w)
VEX.1vvv (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector
mask k1.
Operation
KANDNW
DEST[15:0] (BITWISE NOT SRC1[15:0]) BITWISE AND SRC2[15:0]
DEST[MAX_KL-1:16] 0
KANDNB
DEST[7:0] (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]
DEST[MAX_KL-1:8] 0
KANDNQ
DEST[63:0] (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64] 0
KANDND
DEST[31:0] (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]
DEST[MAX_KL-1:32] 0
Intel C/C++ Compiler Intrinsic Equivalent
KANDNW __mmask16 _mm512_kandn(__mmask16 a, __mmask16 b);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
3-498 Vol. 2A
KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks
INSTRUCTION SET REFERENCE, A-L
KMOVW/KMOVB/KMOVQ/KMOVD—Move from and to Mask Registers
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
VEX.L0.0F.W0 90 /r
KMOVW k1, k2/m16
VEX.L0.66.0F.W0 90 /r
KMOVB k1, k2/m8
VEX.L0.0F.W1 90 /r
KMOVQ k1, k2/m64
VEX.L0.66.0F.W1 90 /r
KMOVD k1, k2/m32
VEX.L0.0F.W0 91 /r
KMOVW m16, k1
VEX.L0.66.0F.W0 91 /r
KMOVB m8, k1
VEX.L0.0F.W1 91 /r
KMOVQ m64, k1
VEX.L0.66.0F.W1 91 /r
KMOVD m32, k1
VEX.L0.0F.W0 92 /r
KMOVW k1, r32
VEX.L0.66.0F.W0 92 /r
KMOVB k1, r32
VEX.L0.F2.0F.W1 92 /r
KMOVQ k1, r64
VEX.L0.F2.0F.W0 92 /r
KMOVD k1, r32
VEX.L0.0F.W0 93 /r
KMOVW r32, k1
VEX.L0.66.0F.W0 93 /r
KMOVB r32, k1
VEX.L0.F2.0F.W1 93 /r
KMOVQ r64, k1
VEX.L0.F2.0F.W0 93 /r
KMOVD r32, k1
Description
Move 16 bits mask from k2/m16 and store the result in k1.
RM
V/V
AVX512DQ
Move 8 bits mask from k2/m8 and store the result in k1.
RM
V/V
AVX512BW
Move 64 bits mask from k2/m64 and store the result in k1.
RM
V/V
AVX512BW
Move 32 bits mask from k2/m32 and store the result in k1.
MR
V/V
AVX512F
Move 16 bits mask from k1 and store the result in m16.
MR
V/V
AVX512DQ
Move 8 bits mask from k1 and store the result in m8.
MR
V/V
AVX512BW
Move 64 bits mask from k1 and store the result in m64.
MR
V/V
AVX512BW
Move 32 bits mask from k1 and store the result in m32.
RR
V/V
AVX512F
Move 16 bits mask from r32 to k1.
RR
V/V
AVX512DQ
Move 8 bits mask from r32 to k1.
RR
V/I
AVX512BW
Move 64 bits mask from r64 to k1.
RR
V/V
AVX512BW
Move 32 bits mask from r32 to k1.
RR
V/V
AVX512F
Move 16 bits mask from k1 to r32.
RR
V/V
AVX512DQ
Move 8 bits mask from k1 to r32.
RR
V/I
AVX512BW
Move 64 bits mask from k1 to r64.
RR
V/V
AVX512BW
Move 32 bits mask from k1 to r32.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
RM
ModRM:reg (w)
ModRM:r/m (r)
MR
ModRM:r/m (w, ModRM:[7:6] must not be 11b)
ModRM:reg (r)
RR
ModRM:reg (w)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Copies values from the source operand (second operand) to the destination operand (first operand). The source
and destination operands can be mask registers, memory location or general purpose. The instruction cannot be
used to transfer data between general purpose registers and or memory locations.
When moving to a mask register, the result is zero extended to MAX_KL size (i.e., 64 bits currently). When moving
to a general-purpose register (GPR), the result is zero-extended to the size of the destination. In 32-bit mode, the
default GPR destination’s size is 32 bits. In 64-bit mode, the default GPR destination’s size is 64 bits. Note that
REX.W cannot be used to modify the size of the general-purpose destination.
KMOVW/KMOVB/KMOVQ/KMOVD—Move from and to Mask Registers
Vol. 2A 3-499
INSTRUCTION SET REFERENCE, A-L
Operation
KMOVW
IF *destination is a memory location*
DEST[15:0] SRC[15:0]
IF *destination is a mask register or a GPR *
DEST ZeroExtension(SRC[15:0])
KMOVB
IF *destination is a memory location*
DEST[7:0] SRC[7:0]
IF *destination is a mask register or a GPR *
DEST ZeroExtension(SRC[7:0])
KMOVQ
IF *destination is a memory location or a GPR*
DEST[63:0] SRC[63:0]
IF *destination is a mask register*
DEST ZeroExtension(SRC[63:0])
KMOVD
IF *destination is a memory location*
DEST[31:0] SRC[31:0]
IF *destination is a mask register or a GPR *
DEST ZeroExtension(SRC[31:0])
Intel C/C++ Compiler Intrinsic Equivalent
KMOVW __mmask16 _mm512_kmov(__mmask16 a);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
Instructions with RR operand encoding See Exceptions Type K20.
Instructions with RM or MR operand encoding See Exceptions Type K21.
3-500 Vol. 2A
KMOVW/KMOVB/KMOVQ/KMOVD—Move from and to Mask Registers
INSTRUCTION SET REFERENCE, A-L
KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register
Opcode/
Instruction
Op/En
CPUID
Feature Flag
Description
RR
64/32
bit Mode
Support
V/V
VEX.L0.0F.W0 44 /r
KNOTW k1, k2
VEX.L0.66.0F.W0 44 /r
KNOTB k1, k2
VEX.L0.0F.W1 44 /r
KNOTQ k1, k2
VEX.L0.66.0F.W1 44 /r
KNOTD k1, k2
AVX512F
Bitwise NOT of 16 bits mask k2.
RR
V/V
AVX512DQ
Bitwise NOT of 8 bits mask k2.
RR
V/V
AVX512BW
Bitwise NOT of 64 bits mask k2.
RR
V/V
AVX512BW
Bitwise NOT of 32 bits mask k2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
RR
ModRM:reg (w)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise NOT of vector mask k2 and writes the result into vector mask k1.
Operation
KNOTW
DEST[15:0] BITWISE NOT SRC[15:0]
DEST[MAX_KL-1:16] 0
KNOTB
DEST[7:0] BITWISE NOT SRC[7:0]
DEST[MAX_KL-1:8] 0
KNOTQ
DEST[63:0] BITWISE NOT SRC[63:0]
DEST[MAX_KL-1:64] 0
KNOTD
DEST[31:0] BITWISE NOT SRC[31:0]
DEST[MAX_KL-1:32] 0
Intel C/C++ Compiler Intrinsic Equivalent
KNOTW __mmask16 _mm512_knot(__mmask16 a);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register
Vol. 2A 3-501
INSTRUCTION SET REFERENCE, A-L
KORW/KORB/KORQ/KORD—Bitwise Logical OR Masks
Opcode/
Instruction
Op/En
RVR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
VEX.NDS.L1.0F.W0 45 /r
KORW k1, k2, k3
VEX.L1.66.0F.W0 45 /r
KORB k1, k2, k3
VEX.L1.0F.W1 45 /r
KORQ k1, k2, k3
VEX.L1.66.0F.W1 45 /r
KORD k1, k2, k3
Description
Bitwise OR 16 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512DQ
Bitwise OR 8 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise OR 64 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise OR 32 bits masks k2 and k3 and place result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RVR
ModRM:reg (w)
VEX.1vvv (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise OR between the vector mask k2 and the vector mask k3, and writes the result into vector mask
k1 (three-operand form).
Operation
KORW
DEST[15:0] SRC1[15:0] BITWISE OR SRC2[15:0]
DEST[MAX_KL-1:16] 0
KORB
DEST[7:0] SRC1[7:0] BITWISE OR SRC2[7:0]
DEST[MAX_KL-1:8] 0
KORQ
DEST[63:0] SRC1[63:0] BITWISE OR SRC2[63:0]
DEST[MAX_KL-1:64] 0
KORD
DEST[31:0] SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[MAX_KL-1:32] 0
Intel C/C++ Compiler Intrinsic Equivalent
KORW __mmask16 _mm512_kor(__mmask16 a, __mmask16 b);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
3-502 Vol. 2A
KORW/KORB/KORQ/KORD—Bitwise Logical OR Masks
INSTRUCTION SET REFERENCE, A-L
KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks And Set Flags
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
AVX512F
Description
RR
64/32
bit Mode
Support
V/V
VEX.L0.0F.W0 98 /r
KORTESTW k1, k2
VEX.L0.66.0F.W0 98 /r
KORTESTB k1, k2
VEX.L0.0F.W1 98 /r
KORTESTQ k1, k2
VEX.L0.66.0F.W1 98 /r
KORTESTD k1, k2
RR
V/V
AVX512DQ
Bitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly.
RR
V/V
AVX512BW
Bitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly.
RR
V/V
AVX512BW
Bitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly.
Bitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
RR
ModRM:reg (w)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise OR between the vector mask register k2, and the vector mask register k1, and sets CF and ZF
based on the operation result.
ZF flag is set if both sources are 0x0. CF is set if, after the OR operation is done, the operation result is all 1’s.
Operation
KORTESTW
TMP[15:0] DEST[15:0] BITWISE OR SRC[15:0]
IF(TMP[15:0]=0)
THEN ZF 1
ELSE ZF 0
FI;
IF(TMP[15:0]=FFFFh)
THEN CF 1
ELSE CF 0
FI;
KORTESTB
TMP[7:0] DEST[7:0] BITWISE OR SRC[7:0]
IF(TMP[7:0]=0)
THEN ZF 1
ELSE ZF 0
FI;
IF(TMP[7:0]==FFh)
THEN CF 1
ELSE CF 0
FI;
KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks And Set Flags
Vol. 2A 3-503
INSTRUCTION SET REFERENCE, A-L
KORTESTQ
TMP[63:0] DEST[63:0] BITWISE OR SRC[63:0]
IF(TMP[63:0]=0)
THEN ZF 1
ELSE ZF 0
FI;
IF(TMP[63:0]==FFFFFFFF_FFFFFFFFh)
THEN CF 1
ELSE CF 0
FI;
KORTESTD
TMP[31:0] DEST[31:0] BITWISE OR SRC[31:0]
IF(TMP[31:0]=0)
THEN ZF 1
ELSE ZF 0
FI;
IF(TMP[31:0]=FFFFFFFFh)
THEN CF 1
ELSE CF 0
FI;
Intel C/C++ Compiler Intrinsic Equivalent
KORTESTW __mmask16 _mm512_kortest[cz](__mmask16 a, __mmask16 b);
Flags Affected
The ZF flag is set if the result of OR-ing both sources is all 0s.
The CF flag is set if the result of OR-ing both sources is all 1s.
The OF, SF, AF, and PF flags are set to 0.
Other Exceptions
See Exceptions Type K20.
3-504 Vol. 2A
KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks And Set Flags
INSTRUCTION SET REFERENCE, A-L
KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers
Opcode/
Instruction
Op/En
CPUID
Feature
Flag
AVX512F
Description
RRI
64/32
bit Mode
Support
V/V
VEX.L0.66.0F3A.W1 32 /r
KSHIFTLW k1, k2, imm8
VEX.L0.66.0F3A.W0 32 /r
KSHIFTLB k1, k2, imm8
VEX.L0.66.0F3A.W1 33 /r
KSHIFTLQ k1, k2, imm8
VEX.L0.66.0F3A.W0 33 /r
KSHIFTLD k1, k2, imm8
RRI
V/V
AVX512DQ
Shift left 8 bits in k2 by immediate and write result in k1.
RRI
V/V
AVX512BW
Shift left 64 bits in k2 by immediate and write result in k1.
RRI
V/V
AVX512BW
Shift left 32 bits in k2 by immediate and write result in k1.
Shift left 16 bits in k2 by immediate and write result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RRI
ModRM:reg (w)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Imm8
Description
Shifts 8/16/32/64 bits in the second operand (source operand) left by the count specified in immediate byte and
place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for
word shift), 31 (for doubleword shift) or 63 (for quadword shift).
Operation
KSHIFTLW
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=15
THEN DEST[15:0] SRC1[15:0] << COUNT;
FI;
KSHIFTLB
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=7
THEN
DEST[7:0] SRC1[7:0] << COUNT;
FI;
KSHIFTLQ
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=63
THEN
DEST[63:0] SRC1[63:0] << COUNT;
FI;
KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers
Vol. 2A 3-505
INSTRUCTION SET REFERENCE, A-L
KSHIFTLD
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=31
THEN
DEST[31:0] SRC1[31:0] << COUNT;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
Compiler auto generates KSHIFTLW when needed.
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
3-506 Vol. 2A
KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers
INSTRUCTION SET REFERENCE, A-L
KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers
Opcode/
Instruction
Op/En
CPUID
Feature
Flag
AVX512F
Description
RRI
64/32
bit Mode
Support
V/V
VEX.L0.66.0F3A.W1 30 /r
KSHIFTRW k1, k2, imm8
VEX.L0.66.0F3A.W0 30 /r
KSHIFTRB k1, k2, imm8
VEX.L0.66.0F3A.W1 31 /r
KSHIFTRQ k1, k2, imm8
VEX.L0.66.0F3A.W0 31 /r
KSHIFTRD k1, k2, imm8
RRI
V/V
AVX512DQ
Shift right 8 bits in k2 by immediate and write result in k1.
RRI
V/V
AVX512BW
Shift right 64 bits in k2 by immediate and write result in k1.
RRI
V/V
AVX512BW
Shift right 32 bits in k2 by immediate and write result in k1.
Shift right 16 bits in k2 by immediate and write result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RRI
ModRM:reg (w)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Imm8
Description
Shifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place
the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are
zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift),
31 (for doubleword shift) or 63 (for quadword shift).
Operation
KSHIFTRW
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=15
THEN DEST[15:0] SRC1[15:0] >> COUNT;
FI;
KSHIFTRB
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=7
THEN
DEST[7:0] SRC1[7:0] >> COUNT;
FI;
KSHIFTRQ
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=63
THEN
DEST[63:0] SRC1[63:0] >> COUNT;
FI;
KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers
Vol. 2A 3-507
INSTRUCTION SET REFERENCE, A-L
KSHIFTRD
COUNT imm8[7:0]
DEST[MAX_KL-1:0] 0
IF COUNT <=31
THEN
DEST[31:0] SRC1[31:0] >> COUNT;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
Compiler auto generates KSHIFTRW when needed.
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
3-508 Vol. 2A
KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers
INSTRUCTION SET REFERENCE, A-L
KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags
Opcode/
Instruction
Op
En
RR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512DQ
VEX.L0.0F.W0 99 /r
KTESTW k1, k2
VEX.L0.66.0F.W0 99 /r
KTESTB k1, k2
VEX.L0.0F.W1 99 /r
KTESTQ k1, k2
VEX.L0.66.0F.W1 99 /r
KTESTD k1, k2
RR
V/V
AVX512DQ
RR
V/V
AVX512BW
RR
V/V
AVX512BW
Description
Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask
register sources.
Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask
register sources.
Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask
register sources.
Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask
register sources.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
RR
ModRM:reg (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise comparison of the bits of the first source operand and corresponding bits in the second source
operand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of
the inverted first source operand with the second source operand produces all zeros the CF is set else the CF is
clear. Only the EFLAGS register is updated.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
KTESTW
TEMP[15:0] SRC2[15:0] AND SRC1[15:0]
IF (TEMP[15:0] = = 0)
THEN ZF 1;
ELSE ZF 0;
FI;
TEMP[15:0] SRC2[15:0] AND NOT SRC1[15:0]
IF (TEMP[15:0] = = 0)
THEN CF 1;
ELSE CF 0;
FI;
AF OF PF SF 0;
KTESTB
TEMP[7:0] SRC2[7:0] AND SRC1[7:0]
IF (TEMP[7:0] = = 0)
THEN ZF 1;
ELSE ZF 0;
FI;
TEMP[7:0] SRC2[7:0] AND NOT SRC1[7:0]
IF (TEMP[7:0] = = 0)
THEN CF 1;
ELSE CF 0;
FI;
AF OF PF SF 0;
KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags
Vol. 2A 3-509
INSTRUCTION SET REFERENCE, A-L
KTESTQ
TEMP[63:0] SRC2[63:0] AND SRC1[63:0]
IF (TEMP[63:0] = = 0)
THEN ZF 1;
ELSE ZF 0;
FI;
TEMP[63:0] SRC2[63:0] AND NOT SRC1[63:0]
IF (TEMP[63:0] = = 0)
THEN CF 1;
ELSE CF 0;
FI;
AF OF PF SF 0;
KTESTD
TEMP[31:0] SRC2[31:0] AND SRC1[31:0]
IF (TEMP[31:0] = = 0)
THEN ZF 1;
ELSE ZF 0;
FI;
TEMP[31:0] SRC2[31:0] AND NOT SRC1[31:0]
IF (TEMP[31:0] = = 0)
THEN CF 1;
ELSE CF 0;
FI;
AF OF PF SF 0;
Intel C/C++ Compiler Intrinsic Equivalent
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
3-510 Vol. 2A
KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags
INSTRUCTION SET REFERENCE, A-L
KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers
Opcode/
Instruction
Op/En
RVR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
VEX.NDS.L1.66.0F.W0 4B /r
KUNPCKBW k1, k2, k3
VEX.NDS.L1.0F.W0 4B /r
KUNPCKWD k1, k2, k3
VEX.NDS.L1.0F.W1 4B /r
KUNPCKDQ k1, k2, k3
Description
RVR
V/V
AVX512BW
RVR
V/V
AVX512BW
Unpack and interleave 8 bits masks in k2 and k3 and write
word result in k1.
Unpack and interleave 16 bits in k2 and k3 and write doubleword result in k1.
Unpack and interleave 32 bits masks in k2 and k3 and write
quadword result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RVR
ModRM:reg (w)
VEX.1vvv (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Unpacks the lower 8/16/32 bits of the second and third operands (source operands) into the low part of the first
operand (destination operand), starting from the low bytes. The result is zero-extended in the destination.
Operation
KUNPCKBW
DEST[7:0] SRC2[7:0]
DEST[15:8] SRC1[7:0]
DEST[MAX_KL-1:16] 0
KUNPCKWD
DEST[15:0] SRC2[15:0]
DEST[31:16] SRC1[15:0]
DEST[MAX_KL-1:32] 0
KUNPCKDQ
DEST[31:0] SRC2[31:0]
DEST[63:32] SRC1[31:0]
DEST[MAX_KL-1:64] 0
Intel C/C++ Compiler Intrinsic Equivalent
KUNPCKBW __mmask16 _mm512_kunpackb(__mmask16 a, __mmask16 b);
KUNPCKDQ __mmask64 _mm512_kunpackd(__mmask64 a, __mmask64 b);
KUNPCKWD __mmask32 _mm512_kunpackw(__mmask32 a, __mmask32 b);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers
Vol. 2A 3-511
INSTRUCTION SET REFERENCE, A-L
KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks
Opcode/
Instruction
Op/En
RVR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
VEX.NDS.L1.0F.W0 46 /r
KXNORW k1, k2, k3
VEX.L1.66.0F.W0 46 /r
KXNORB k1, k2, k3
VEX.L1.0F.W1 46 /r
KXNORQ k1, k2, k3
VEX.L1.66.0F.W1 46 /r
KXNORD k1, k2, k3
Description
Bitwise XNOR 16 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512DQ
Bitwise XNOR 8 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise XNOR 64 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise XNOR 32 bits masks k2 and k3 and place result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RVR
ModRM:reg (w)
VEX.1vvv (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector
mask k1 (three-operand form).
Operation
KXNORW
DEST[15:0] NOT (SRC1[15:0] BITWISE XOR SRC2[15:0])
DEST[MAX_KL-1:16] 0
KXNORB
DEST[7:0] NOT (SRC1[7:0] BITWISE XOR SRC2[7:0])
DEST[MAX_KL-1:8] 0
KXNORQ
DEST[63:0] NOT (SRC1[63:0] BITWISE XOR SRC2[63:0])
DEST[MAX_KL-1:64] 0
KXNORD
DEST[31:0] NOT (SRC1[31:0] BITWISE XOR SRC2[31:0])
DEST[MAX_KL-1:32] 0
Intel C/C++ Compiler Intrinsic Equivalent
KXNORW __mmask16 _mm512_kxnor(__mmask16 a, __mmask16 b);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
3-512 Vol. 2A
KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks
INSTRUCTION SET REFERENCE, A-L
KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks
Opcode/
Instruction
Op/En
RVR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
VEX.NDS.L1.0F.W0 47 /r
KXORW k1, k2, k3
VEX.L1.66.0F.W0 47 /r
KXORB k1, k2, k3
VEX.L1.0F.W1 47 /r
KXORQ k1, k2, k3
VEX.L1.66.0F.W1 47 /r
KXORD k1, k2, k3
Description
Bitwise XOR 16 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512DQ
Bitwise XOR 8 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise XOR 64 bits masks k2 and k3 and place result in k1.
RVR
V/V
AVX512BW
Bitwise XOR 32 bits masks k2 and k3 and place result in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RVR
ModRM:reg (w)
VEX.1vvv (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Description
Performs a bitwise XOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask
k1 (three-operand form).
Operation
KXORW
DEST[15:0] SRC1[15:0] BITWISE XOR SRC2[15:0]
DEST[MAX_KL-1:16] 0
KXORB
DEST[7:0] SRC1[7:0] BITWISE XOR SRC2[7:0]
DEST[MAX_KL-1:8] 0
KXORQ
DEST[63:0] SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[MAX_KL-1:64] 0
KXORD
DEST[31:0] SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[MAX_KL-1:32] 0
Intel C/C++ Compiler Intrinsic Equivalent
KXORW __mmask16 _mm512_kxor(__mmask16 a, __mmask16 b);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type K20.
KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks
Vol. 2A 3-513
INSTRUCTION SET REFERENCE, A-L
LAHF—Load Status Flags into AH Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
9F
LAHF
NP
Invalid*
Valid
Load: AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF).
NOTES:
*Valid in specific steppings. See Description section.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only
if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.
Operation
IF 64-Bit Mode
THEN
IF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1;
THEN AH ← RFLAGS(SF:ZF:0:AF:0:PF:1:CF);
ELSE #UD;
FI;
ELSE
AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF);
FI;
Flags Affected
None. The state of the flags in the EFLAGS register is not affected.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.
If the LOCK prefix is used.
3-514 Vol. 2A
LAHF—Load Status Flags into AH Register
INSTRUCTION SET REFERENCE, A-L
LAR—Load Access Rights Byte
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 02 /r
LAR r16, r16/m16
RM
Valid
Valid
r16 ← access rights referenced by r16/m16
0F 02 /r
LAR reg, r32/m161
RM
Valid
Valid
reg ← access rights referenced by r32/m16
NOTES:
1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Loads the access rights from the segment descriptor specified by the second operand (source operand) into the
first operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a
register or a memory location) contains the segment selector for the segment descriptor being accessed. If the
source operand is a memory address, only 16 bits of data are accessed. The destination operand is a generalpurpose register.
The processor performs access checks as part of the loading process. Once loaded in the destination register, software can perform additional checks on the access rights information.
The access rights for a segment descriptor include fields located in the second doubleword (bytes 4–7) of the
segment descriptor. The following fields are loaded by the LAR instruction:
•
•
•
•
•
•
Bits 7:0 are returned as 0
Bits 11:8 return the segment type.
Bit 12 returns the S flag.
Bits 14:13 return the DPL.
Bit 15 returns the P flag.
The following fields are returned only if the operand size is greater than 16 bits:
— Bits 19:16 are undefined.
— Bit 20 returns the software-available bit in the descriptor.
— Bit 21 returns the L flag.
— Bit 22 returns the D/B flag.
— Bit 23 returns the G flag.
— Bits 31:24 are returned as 0.
This instruction performs the following checks before it loads the access rights in the destination register:
•
•
Checks that the segment selector is not NULL.
•
Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for
(can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in
Table 3-52.
•
If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at
the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment
selector).
Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being
accessed
If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no
access rights are loaded in the destination operand.
LAR—Load Access Rights Byte
Vol. 2A 3-515
INSTRUCTION SET REFERENCE, A-L
The LAR instruction can only be executed in protected mode and IA-32e mode.
Table 3-52. Segment and Gate Types
Type
Protected Mode
Name
IA-32e Mode
Valid
Name
Valid
0
Reserved
No
Reserved
No
1
Available 16-bit TSS
Yes
Reserved
No
2
LDT
Yes
LDT
No
3
Busy 16-bit TSS
Yes
Reserved
No
4
16-bit call gate
Yes
Reserved
No
5
16-bit/32-bit task gate
Yes
Reserved
No
6
16-bit interrupt gate
No
Reserved
No
7
16-bit trap gate
No
Reserved
No
8
Reserved
No
Reserved
No
9
Available 32-bit TSS
Yes
Available 64-bit TSS
Yes
A
Reserved
No
Reserved
No
B
Busy 32-bit TSS
Yes
Busy 64-bit TSS
Yes
C
32-bit call gate
Yes
64-bit call gate
Yes
D
Reserved
No
Reserved
No
E
32-bit interrupt gate
No
64-bit interrupt gate
No
F
32-bit trap gate
No
64-bit trap gate
No
Operation
IF Offset(SRC) > descriptor table limit
THEN
ZF ← 0;
ELSE
SegmentDescriptor ← descriptor referenced by SRC;
IF SegmentDescriptor(Type) ≠ conforming code segment
and (CPL > DPL) or (RPL > DPL)
or SegmentDescriptor(Type) is not valid for instruction
THEN
ZF ← 0;
ELSE
DEST ← access rights from SegmentDescriptor as given in Description section;
ZF ← 1;
FI;
FI;
Flags Affected
The ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.
3-516 Vol. 2A
LAR—Load Access Rights Byte
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and the memory operand effective address is unaligned while
the current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The LAR instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The LAR instruction cannot be executed in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If the memory operand effective address referencing the SS segment is in a non-canonical
form.
#GP(0)
If the memory operand effective address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and the memory operand effective address is unaligned while
the current privilege level is 3.
#UD
If the LOCK prefix is used.
LAR—Load Access Rights Byte
Vol. 2A 3-517
INSTRUCTION SET REFERENCE, A-L
LDDQU—Load Unaligned Integer 128 Bits
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
F2 0F F0 /r
RM
V/V
SSE3
Load unaligned data from mem and return
double quadword in xmm1.
RM
V/V
AVX
Load unaligned packed integer values from
mem to xmm1.
RM
V/V
AVX
Load unaligned packed integer values from
mem to ymm1.
LDDQU xmm1, mem
VEX.128.F2.0F.WIG F0 /r
VLDDQU xmm1, m128
VEX.256.F2.0F.WIG F0 /r
VLDDQU ymm1, m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
The instruction is functionally similar to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is:
32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched
from memory and placed in a destination register (first operand). The source operand need not be aligned on a
32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.
This instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line
boundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use
(V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that
are known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.
Implementation Notes
•
If the source is aligned to a 32/16-byte boundary, based on the implementation, the 32/16 bytes may be
loaded more than once. For that reason, the usage of (V)LDDQU should be avoided when using uncached or
write-combining (WC) memory regions. For uncached or WC memory regions, keep using (V)MOVDQU.
•
This instruction is a replacement for (V)MOVDQU (load) in situations where cache line splits significantly affect
performance. It should not be used in situations where store-load forwarding is performance critical. If
performance of store-load forwarding is critical to the application, use (V)MOVDQA store-load pairs when data
is 256/128-bit aligned or (V)MOVDQU store-load pairs when data is 256/128-bit unaligned.
•
If the memory address is not aligned on 32/16-byte boundary, some implementations may load up to 64/32
bytes and return 32/16 bytes in the destination. Some processor implementations may issue multiple loads to
access the appropriate 32/16 bytes. Developers of multi-threaded or multi-processor software should be aware
that on these processors the loads will be performed in a non-atomic way.
•
If alignment checking is enabled (CR0.AM = 1, RFLAGS.AC = 1, and CPL = 3), an alignment-check exception
(#AC) may or may not be generated (depending on processor implementation) when the memory address is
not aligned on an 8-byte boundary.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
LDDQU (128-bit Legacy SSE version)
DEST[127:0] SRC[127:0]
DEST[VLMAX-1:128] (Unmodified)
3-518 Vol. 2A
LDDQU—Load Unaligned Integer 128 Bits
INSTRUCTION SET REFERENCE, A-L
VLDDQU (VEX.128 encoded version)
DEST[127:0] SRC[127:0]
DEST[VLMAX-1:128] 0
VLDDQU (VEX.256 encoded version)
DEST[255:0] SRC[255:0]
Intel C/C++ Compiler Intrinsic Equivalent
LDDQU:
__m128i _mm_lddqu_si128 (__m128i * p);
VLDDQU: __m256i _mm256_lddqu_si256 (__m256i * p);
Numeric Exceptions
None
Other Exceptions
See Exceptions Type 4;
Note treatment of #AC varies.
LDDQU—Load Unaligned Integer 128 Bits
Vol. 2A 3-519
INSTRUCTION SET REFERENCE, A-L
LDMXCSR—Load MXCSR Register
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
0F AE /2
M
V/V
SSE
Load MXCSR register from m32.
M
V/V
AVX
Load MXCSR register from m32.
LDMXCSR m32
VEX.LZ.0F.WIG AE /2
VLDMXCSR m32
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Loads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location.
See “MXCSR Control and Status Register” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of the MXCSR register and its contents.
The LDMXCSR instruction is typically used in conjunction with the (V)STMXCSR instruction, which stores the
contents of the MXCSR register in memory.
The default MXCSR value at reset is 1F80H.
If a (V)LDMXCSR instruction clears a SIMD floating-point exception mask bit and sets the corresponding exception
flag bit, a SIMD floating-point exception will not be immediately generated. The exception will be generated only
upon the execution of the next instruction that meets both conditions below:
•
•
the instruction must operate on an XMM or YMM register operand,
the instruction causes that particular SIMD floating-point exception to be reported.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
If VLDMXCSR is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an
#UD exception.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
MXCSR ← m32;
C/C++ Compiler Intrinsic Equivalent
_mm_setcsr(unsigned int i)
Numeric Exceptions
None
Other Exceptions
See Exceptions Type 5; additionally
#GP
For an attempt to set reserved bits in MXCSR.
#UD
If VEX.vvvv ≠ 1111B.
3-520 Vol. 2A
LDMXCSR—Load MXCSR Register
INSTRUCTION SET REFERENCE, A-L
LDS/LES/LFS/LGS/LSS—Load Far Pointer
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
C5 /r
LDS r16,m16:16
RM
Invalid
Valid
Load DS:r16 with far pointer from memory.
C5 /r
LDS r32,m16:32
RM
Invalid
Valid
Load DS:r32 with far pointer from memory.
0F B2 /r
LSS r16,m16:16
RM
Valid
Valid
Load SS:r16 with far pointer from memory.
0F B2 /r
LSS r32,m16:32
RM
Valid
Valid
Load SS:r32 with far pointer from memory.
REX + 0F B2 /r
LSS r64,m16:64
RM
Valid
N.E.
Load SS:r64 with far pointer from memory.
C4 /r
LES r16,m16:16
RM
Invalid
Valid
Load ES:r16 with far pointer from memory.
C4 /r
LES r32,m16:32
RM
Invalid
Valid
Load ES:r32 with far pointer from memory.
0F B4 /r
LFS r16,m16:16
RM
Valid
Valid
Load FS:r16 with far pointer from memory.
0F B4 /r
LFS r32,m16:32
RM
Valid
Valid
Load FS:r32 with far pointer from memory.
REX + 0F B4 /r
LFS r64,m16:64
RM
Valid
N.E.
Load FS:r64 with far pointer from memory.
0F B5 /r
LGS r16,m16:16
RM
Valid
Valid
Load GS:r16 with far pointer from memory.
0F B5 /r
LGS r32,m16:32
RM
Valid
Valid
Load GS:r32 with far pointer from memory.
REX + 0F B5 /r
LGS r64,m16:64
RM
Valid
N.E.
Load GS:r64 with far pointer from memory.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Loads a far pointer (segment selector and offset) from the second operand (source operand) into a segment
register and the first operand (destination operand). The source operand specifies a 48-bit or a 32-bit pointer in
memory depending on the current setting of the operand-size attribute (32 bits or 16 bits, respectively). The
instruction opcode and the destination operand specify a segment register/general-purpose register pair. The 16bit segment selector from the source operand is loaded into the segment register specified with the opcode (DS,
SS, ES, FS, or GS). The 32-bit or 16-bit offset is loaded into the register specified with the destination operand.
If one of these instructions is executed in protected mode, additional information from the segment descriptor
pointed to by the segment selector in the source operand is loaded in the hidden part of the selected segment
register.
Also in protected mode, a NULL selector (values 0000 through 0003) can be loaded into DS, ES, FS, or GS registers
without causing a protection exception. (Any subsequent reference to a segment whose corresponding segment
register is loaded with a NULL selector, causes a general-protection exception (#GP) and no memory reference to
the segment occurs.)
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.W promotes
operation to specify a source operand referencing an 80-bit pointer (16-bit selector, 64-bit offset) in memory.
Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). See the summary chart at
the beginning of this section for encoding data and limits.
Operation
64-BIT_MODE
IF SS is loaded
THEN
IF SegmentSelector = NULL and ( (RPL = 3) or
(RPL ≠ 3 and RPL ≠ CPL) )
THEN #GP(0);
ELSE IF descriptor is in non-canonical space
LDS/LES/LFS/LGS/LSS—Load Far Pointer
Vol. 2A 3-521
INSTRUCTION SET REFERENCE, A-L
THEN #GP(0); FI;
ELSE IF Segment selector index is not within descriptor table limits
or segment selector RPL ≠ CPL
or access rights indicate nonwritable data segment
or DPL ≠ CPL
THEN #GP(selector); FI;
ELSE IF Segment marked not present
THEN #SS(selector); FI;
FI;
SS ← SegmentSelector(SRC);
SS ← SegmentDescriptor([SRC]);
ELSE IF attempt to load DS, or ES
THEN #UD;
ELSE IF FS, or GS is loaded with non-NULL segment selector
THEN IF Segment selector index is not within descriptor table limits
or access rights indicate segment neither data nor readable code segment
or segment is data or nonconforming-code segment
and ( RPL > DPL or CPL > DPL)
THEN #GP(selector); FI;
ELSE IF Segment marked not present
THEN #NP(selector); FI;
FI;
SegmentRegister ← SegmentSelector(SRC) ;
SegmentRegister ← SegmentDescriptor([SRC]);
FI;
ELSE IF FS, or GS is loaded with a NULL selector:
THEN
SegmentRegister ← NULLSelector;
SegmentRegister(DescriptorValidBit) ← 0; FI; (* Hidden flag;
not accessible by software *)
FI;
DEST ← Offset(SRC);
PREOTECTED MODE OR COMPATIBILITY MODE;
IF SS is loaded
THEN
IF SegementSelector = NULL
THEN #GP(0);
ELSE IF Segment selector index is not within descriptor table limits
or segment selector RPL ≠ CPL
or access rights indicate nonwritable data segment
or DPL ≠ CPL
THEN #GP(selector); FI;
ELSE IF Segment marked not present
THEN #SS(selector); FI;
FI;
SS ← SegmentSelector(SRC);
SS ← SegmentDescriptor([SRC]);
ELSE IF DS, ES, FS, or GS is loaded with non-NULL segment selector
THEN IF Segment selector index is not within descriptor table limits
or access rights indicate segment neither data nor readable code segment
or segment is data or nonconforming-code segment
and (RPL > DPL or CPL > DPL)
THEN #GP(selector); FI;
3-522 Vol. 2A
LDS/LES/LFS/LGS/LSS—Load Far Pointer
INSTRUCTION SET REFERENCE, A-L
ELSE IF Segment marked not present
THEN #NP(selector); FI;
FI;
SegmentRegister ← SegmentSelector(SRC) AND RPL;
SegmentRegister ← SegmentDescriptor([SRC]);
FI;
ELSE IF DS, ES, FS, or GS is loaded with a NULL selector:
THEN
SegmentRegister ← NULLSelector;
SegmentRegister(DescriptorValidBit) ← 0; FI; (* Hidden flag;
not accessible by software *)
FI;
DEST ← Offset(SRC);
Real-Address or Virtual-8086 Mode
SegmentRegister ← SegmentSelector(SRC); FI;
DEST ← Offset(SRC);
Flags Affected
None
Protected Mode Exceptions
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
If a NULL selector is loaded into the SS register.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#GP(selector)
If the SS register is being loaded and any of the following is true: the segment selector index
is not within the descriptor table limits, the segment selector RPL is not equal to CPL, the
segment is a non-writable data segment, or DPL is not equal to CPL.
If the DS, ES, FS, or GS register is being loaded with a non-NULL segment selector and any of
the following is true: the segment selector index is not within descriptor table limits, the
segment is neither a data nor a readable code segment, or the segment is a data or nonconforming-code segment and both RPL and CPL are greater than DPL.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#SS(selector)
If the SS register is being loaded and the segment is marked not present.
#NP(selector)
If DS, ES, FS, or GS register is being loaded with a non-NULL segment selector and the
segment is marked not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
LDS/LES/LFS/LGS/LSS—Load Far Pointer
Vol. 2A 3-523
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
If a NULL selector is attempted to be loaded into the SS register in compatibility mode.
If a NULL selector is attempted to be loaded into the SS register in CPL3 and 64-bit mode.
If a NULL selector is attempted to be loaded into the SS register in non-CPL3 and 64-bit mode
where its RPL is not equal to CPL.
#GP(Selector)
If the FS, or GS register is being loaded with a non-NULL segment selector and any of the
following is true: the segment selector index is not within descriptor table limits, the memory
address of the descriptor is non-canonical, the segment is neither a data nor a readable code
segment, or the segment is a data or nonconforming-code segment and both RPL and CPL are
greater than DPL.
If the SS register is being loaded and any of the following is true: the segment selector index
is not within the descriptor table limits, the memory address of the descriptor is non-canonical,
the segment selector RPL is not equal to CPL, the segment is a nonwritable data segment, or
DPL is not equal to CPL.
#SS(0)
If a memory operand effective address is non-canonical
#SS(Selector)
If the SS register is being loaded and the segment is marked not present.
#NP(selector)
If FS, or GS register is being loaded with a non-NULL segment selector and the segment is
marked not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
3-524 Vol. 2A
LDS/LES/LFS/LGS/LSS—Load Far Pointer
INSTRUCTION SET REFERENCE, A-L
LEA—Load Effective Address
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
8D /r
LEA r16,m
RM
Valid
Valid
Store effective address for m in register r16.
8D /r
LEA r32,m
RM
Valid
Valid
Store effective address for m in register r32.
REX.W + 8D /r
LEA r64,m
RM
Valid
N.E.
Store effective address for m in register r64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Computes the effective address of the second operand (the source operand) and stores it in the first operand
(destination operand). The source operand is a memory address (offset part) specified with one of the processors
addressing modes; the destination operand is a general-purpose register. The address-size and operand-size attributes affect the action performed by this instruction, as shown in the following table. The operand-size attribute of
the instruction is determined by the chosen register; the address-size attribute is determined by the attribute of
the code segment.
Table 3-53. Non-64-bit Mode LEA Operation with Address and Operand Size Attributes
Operand Size
Address Size
Action Performed
16
16
16-bit effective address is calculated and stored in requested 16-bit register destination.
16
32
32-bit effective address is calculated. The lower 16 bits of the address are stored in the
requested 16-bit register destination.
32
16
16-bit effective address is calculated. The 16-bit address is zero-extended and stored in the
requested 32-bit register destination.
32
32
32-bit effective address is calculated and stored in the requested 32-bit register destination.
Different assemblers may use different algorithms based on the size attribute and symbolic reference of the source
operand.
In 64-bit mode, the instruction’s destination operand is governed by operand size attribute, the default operand
size is 32 bits. Address calculation is governed by address size attribute, the default address size is 64-bits. In 64bit mode, address size of 16 bits is not encodable. See Table 3-54.
Table 3-54. 64-bit Mode LEA Operation with Address and Operand Size Attributes
Operand Size
Address Size
16
32
32-bit effective address is calculated (using 67H prefix). The lower 16 bits of the address are
stored in the requested 16-bit register destination (using 66H prefix).
16
64
64-bit effective address is calculated (default address size). The lower 16 bits of the address
are stored in the requested 16-bit register destination (using 66H prefix).
32
32
32-bit effective address is calculated (using 67H prefix) and stored in the requested 32-bit
register destination.
32
64
64-bit effective address is calculated (default address size) and the lower 32 bits of the
address are stored in the requested 32-bit register destination.
64
32
32-bit effective address is calculated (using 67H prefix), zero-extended to 64-bits, and stored
in the requested 64-bit register destination (using REX.W).
64
64
64-bit effective address is calculated (default address size) and all 64-bits of the address are
stored in the requested 64-bit register destination (using REX.W).
LEA—Load Effective Address
Action Performed
Vol. 2A 3-525
INSTRUCTION SET REFERENCE, A-L
Operation
IF OperandSize = 16 and AddressSize = 16
THEN
DEST ← EffectiveAddress(SRC); (* 16-bit address *)
ELSE IF OperandSize = 16 and AddressSize = 32
THEN
temp ← EffectiveAddress(SRC); (* 32-bit address *)
DEST ← temp[0:15]; (* 16-bit address *)
FI;
ELSE IF OperandSize = 32 and AddressSize = 16
THEN
temp ← EffectiveAddress(SRC); (* 16-bit address *)
DEST ← ZeroExtend(temp); (* 32-bit address *)
FI;
ELSE IF OperandSize = 32 and AddressSize = 32
THEN
DEST ← EffectiveAddress(SRC); (* 32-bit address *)
FI;
ELSE IF OperandSize = 16 and AddressSize = 64
THEN
temp ← EffectiveAddress(SRC); (* 64-bit address *)
DEST ← temp[0:15]; (* 16-bit address *)
FI;
ELSE IF OperandSize = 32 and AddressSize = 64
THEN
temp ← EffectiveAddress(SRC); (* 64-bit address *)
DEST ← temp[0:31]; (* 16-bit address *)
FI;
ELSE IF OperandSize = 64 and AddressSize = 64
THEN
DEST ← EffectiveAddress(SRC); (* 64-bit address *)
FI;
FI;
Flags Affected
None
Protected Mode Exceptions
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-526 Vol. 2A
LEA—Load Effective Address
INSTRUCTION SET REFERENCE, A-L
LEAVE—High Level Procedure Exit
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
C9
LEAVE
NP
Valid
Valid
Set SP to BP, then pop BP.
C9
LEAVE
NP
N.E.
Valid
Set ESP to EBP, then pop EBP.
C9
LEAVE
NP
Valid
N.E.
Set RSP to RBP, then pop RBP.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Releases the stack frame set up by an earlier ENTER instruction. The LEAVE instruction copies the frame pointer (in
the EBP register) into the stack pointer register (ESP), which releases the stack space allocated to the stack frame.
The old frame pointer (the frame pointer for the calling procedure that was saved by the ENTER instruction) is then
popped from the stack into the EBP register, restoring the calling procedure’s stack frame.
A RET instruction is commonly executed following a LEAVE instruction to return program control to the calling
procedure.
See “Procedure Calls for Block-Structured Languages” in Chapter 7 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for detailed information on the use of the ENTER and LEAVE instructions.
In 64-bit mode, the instruction’s default operation size is 64 bits; 32-bit operation cannot be encoded. See the
summary chart at the beginning of this section for encoding data and limits.
Operation
IF StackAddressSize = 32
THEN
ESP ← EBP;
ELSE IF StackAddressSize = 64
THEN RSP ← RBP; FI;
ELSE IF StackAddressSize = 16
THEN SP ← BP; FI;
FI;
IF OperandSize = 32
THEN EBP ← Pop();
ELSE IF OperandSize = 64
THEN RBP ← Pop(); FI;
ELSE IF OperandSize = 16
THEN BP ← Pop(); FI;
FI;
Flags Affected
None
LEAVE—High Level Procedure Exit
Vol. 2A 3-527
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#SS(0)
If the EBP register points to a location that is not within the limits of the current stack
segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If the EBP register points to a location outside of the effective address space from 0 to FFFFH.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the EBP register points to a location outside of the effective address space from 0 to FFFFH.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If the stack address is in a non-canonical form.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-528 Vol. 2A
LEAVE—High Level Procedure Exit
INSTRUCTION SET REFERENCE, A-L
LFENCE—Load Fence
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AE E8
LFENCE
NP
Valid
Valid
Serializes load operations.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruction. Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruction begins execution until LFENCE completes. In particular, an instruction that loads from memory and that
precedes an LFENCE receives data from memory prior to completion of the LFENCE. (An LFENCE that follows an
instruction that stores to memory might complete before the data being stored have become globally visible.)
Instructions following an LFENCE may be fetched from memory before the LFENCE, but they will not execute until
the LFENCE completes.
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as
out-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the
data is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE
instruction provides a performance-efficient way of ensuring load ordering between routines that produce weaklyordered results and routines that consume that data.
Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC,
and WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution.
Thus, it is not ordered with respect to executions of the LFENCE instruction; data can be brought into the caches
speculatively just before, during, or after the execution of an LFENCE instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Specification of the instruction's opcode above indicates a ModR/M byte of E8. For this instruction, the processor
ignores the r/m field of the ModR/M byte. Thus, LFENCE is encoded by any opcode of the form 0F AE Ex, where x is
in the range 8-F.
Operation
Wait_On_Following_Instructions_Until(preceding_instructions_complete);
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_lfence(void)
Exceptions (All Modes of Operation)
#UD
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
LFENCE—Load Fence
Vol. 2A 3-529
INSTRUCTION SET REFERENCE, A-L
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 /2
LGDT m16&32
M
N.E.
Valid
Load m into GDTR.
0F 01 /3
LIDT m16&32
M
N.E.
Valid
Load m into IDTR.
0F 01 /2
LGDT m16&64
M
Valid
N.E.
Load m into GDTR.
0F 01 /3
LIDT m16&64
M
Valid
N.E.
Load m into IDTR.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor
table register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a
linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor
table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute
is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here,
the high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is
filled with zeros.
The LGDT and LIDT instructions are used only in operating-system software; they are not used in application
programs. They are the only instructions that directly load a linear address (that is, not a segment-relative
address) and a limit in protected mode. They are commonly executed in real-address mode to allow processor
initialization prior to switching to protected mode.
In 64-bit mode, the instruction’s operand size is fixed at 8+2 bytes (an 8-byte base and a 2-byte limit). See the
summary chart at the beginning of this section for encoding data and limits.
See “SGDT—Store Global Descriptor Table Register” in Chapter 4, Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B, for information on storing the contents of the GDTR and IDTR.
3-530 Vol. 2A
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register
INSTRUCTION SET REFERENCE, A-L
Operation
IF Instruction is LIDT
THEN
IF OperandSize = 16
THEN
IDTR(Limit) ← SRC[0:15];
IDTR(Base) ← SRC[16:47] AND 00FFFFFFH;
ELSE IF 32-bit Operand Size
THEN
IDTR(Limit) ← SRC[0:15];
IDTR(Base) ← SRC[16:47];
FI;
ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
THEN
IDTR(Limit) ← SRC[0:15];
IDTR(Base) ← SRC[16:79];
FI;
FI;
ELSE (* Instruction is LGDT *)
IF OperandSize = 16
THEN
GDTR(Limit) ← SRC[0:15];
GDTR(Base) ← SRC[16:47] AND 00FFFFFFH;
ELSE IF 32-bit Operand Size
THEN
GDTR(Limit) ← SRC[0:15];
GDTR(Base) ← SRC[16:47];
FI;
ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
THEN
GDTR(Limit) ← SRC[0:15];
GDTR(Base) ← SRC[16:79];
FI;
FI;
FI;
Flags Affected
None
Protected Mode Exceptions
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
If the current privilege level is not 0.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register
Vol. 2A 3-531
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
Virtual-8086 Mode Exceptions
#UD
If source operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
The LGDT and LIDT instructions are not recognized in virtual-8086 mode.
#GP
If the current privilege level is not 0.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the current privilege level is not 0.
If the memory address is in a non-canonical form.
#UD
If source operand is not a memory location.
#PF(fault-code)
If a page fault occurs.
If the LOCK prefix is used.
3-532 Vol. 2A
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register
INSTRUCTION SET REFERENCE, A-L
LLDT—Load Local Descriptor Table Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 00 /2
LLDT r/m16
M
Valid
Valid
Load segment selector r/m16 into LDTR.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source
operand (a general-purpose register or a memory location) contains a segment selector that points to a local
descriptor table (LDT). After the segment selector is loaded in the LDTR, the processor uses the segment selector
to locate the segment descriptor for the LDT in the global descriptor table (GDT). It then loads the segment limit
and base address for the LDT from the segment descriptor into the LDTR. The segment registers DS, ES, SS, FS,
GS, and CS are not affected by this instruction, nor is the LDTR field in the task state segment (TSS) for the current
task.
If bits 2-15 of the source operand are 0, LDTR is marked invalid and the LLDT instruction completes silently.
However, all subsequent references to descriptors in the LDT (except by the LAR, VERR, VERW or LSL instructions)
cause a general protection exception (#GP).
The operand-size attribute has no effect on this instruction.
The LLDT instruction is provided for use in operating-system software; it should not be used in application
programs. This instruction can only be executed in protected mode or 64-bit mode.
In 64-bit mode, the operand size is fixed at 16 bits.
Operation
IF SRC(Offset) > descriptor table limit
THEN #GP(segment selector); FI;
IF segment selector is valid
Read segment descriptor;
IF SegmentDescriptor(Type) ≠ LDT
THEN #GP(segment selector); FI;
IF segment descriptor is not present
THEN #NP(segment selector); FI;
LDTR(SegmentSelector) ← SRC;
LDTR(SegmentDescriptor) ← GDTSegmentDescriptor;
ELSE LDTR ← INVALID
FI;
Flags Affected
None
LLDT—Load Local Descriptor Table Register
Vol. 2A 3-533
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#GP(selector)
If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT
is not a Local Descriptor Table.
Segment selector is beyond GDT limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#NP(selector)
If the LDT descriptor is not present.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The LLDT instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The LLDT instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
#GP(0)
If a memory address referencing the SS segment is in a non-canonical form.
If the current privilege level is not 0.
If the memory address is in a non-canonical form.
#GP(selector)
If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT
is not a Local Descriptor Table.
Segment selector is beyond GDT limit.
#NP(selector)
If the LDT descriptor is not present.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
3-534 Vol. 2A
LLDT—Load Local Descriptor Table Register
INSTRUCTION SET REFERENCE, A-L
LMSW—Load Machine Status Word
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 /6
LMSW r/m16
M
Valid
Valid
Loads r/m16 in machine status word of CR0.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can
be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which
contains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are
not affected. The operand-size attribute has no effect on this instruction.
If the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected
mode. While in protected mode, the LMSW instruction cannot be used to clear the PE flag and force a switch back
to real-address mode.
The LMSW instruction is provided for use in operating-system software; it should not be used in application
programs. In protected or virtual-8086 mode, it can only be executed at CPL 0.
This instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to
run on IA-32 and Intel 64 processors beginning with Intel386 processors should use the MOV (control registers)
instruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0,
allowing a procedure or program to switch between protected and real-address modes.
This instruction is a serializing instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Note that the operand size is fixed
at 16 bits.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.
Operation
CR0[0:3] ← SRC[0:3];
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#UD
If the LOCK prefix is used.
LMSW—Load Machine Status Word
Vol. 2A 3-535
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#GP(0)
The LMSW instruction is not recognized in real-address mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
#GP(0)
If a memory address referencing the SS segment is in a non-canonical form.
If the current privilege level is not 0.
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
3-536 Vol. 2A
LMSW—Load Machine Status Word
INSTRUCTION SET REFERENCE, A-L
LOCK—Assert LOCK# Signal Prefix
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F0
LOCK
NP
Valid
Valid
Asserts LOCK# signal for duration of the
accompanying instruction.
NOTES:
* See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Causes the processor’s LOCK# signal to be asserted during execution of the accompanying instruction (turns the
instruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal ensures that the
processor has exclusive use of any shared memory while the signal is asserted.
In most IA-32 and all Intel 64 processors, locking may occur without the LOCK# signal being asserted. See the “IA32 Architecture Compatibility” section below for more details.
The LOCK prefix can be prepended only to the following instructions and only to those forms of the instructions
where the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B,
CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If the LOCK prefix is used with one of
these instructions and the source operand is a memory operand, an undefined opcode exception (#UD) may be
generated. An undefined opcode exception will also be generated if the LOCK prefix is used with any instruction not
in the above list. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of
the LOCK prefix.
The LOCK prefix is typically used with the BTS instruction to perform a read-modify-write operation on a memory
location in shared memory environment.
The integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed
for arbitrarily misaligned fields.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IA-32 Architecture Compatibility
Beginning with the P6 family processors, when the LOCK prefix is prefixed to an instruction and the memory area
being accessed is cached internally in the processor, the LOCK# signal is generally not asserted. Instead, only the
processor’s cache is locked. Here, the processor’s cache coherency mechanism ensures that the operation is
carried out atomically with regards to memory. See “Effects of a Locked Operation on Internal Processor Caches”
in Chapter 8 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, the for more information on locking of caches.
Operation
AssertLOCK#(DurationOfAccompaningInstruction);
Flags Affected
None
Protected Mode Exceptions
#UD
If the LOCK prefix is used with an instruction not listed: ADD, ADC, AND, BTC, BTR, BTS,
CMPXCHG, CMPXCH8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD,
XCHG.
Other exceptions can be generated by the instruction when the LOCK prefix is applied.
LOCK—Assert LOCK# Signal Prefix
Vol. 2A 3-537
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
3-538 Vol. 2A
LOCK—Assert LOCK# Signal Prefix
INSTRUCTION SET REFERENCE, A-L
LODS/LODSB/LODSW/LODSD/LODSQ—Load String
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
AC
LODS m8
NP
Valid
Valid
For legacy mode, Load byte at address DS:(E)SI
into AL. For 64-bit mode load byte at address
(R)SI into AL.
AD
LODS m16
NP
Valid
Valid
For legacy mode, Load word at address
DS:(E)SI into AX. For 64-bit mode load word at
address (R)SI into AX.
AD
LODS m32
NP
Valid
Valid
For legacy mode, Load dword at address
DS:(E)SI into EAX. For 64-bit mode load dword
at address (R)SI into EAX.
REX.W + AD
LODS m64
NP
Valid
N.E.
Load qword at address (R)SI into RAX.
AC
LODSB
NP
Valid
Valid
For legacy mode, Load byte at address DS:(E)SI
into AL. For 64-bit mode load byte at address
(R)SI into AL.
AD
LODSW
NP
Valid
Valid
For legacy mode, Load word at address
DS:(E)SI into AX. For 64-bit mode load word at
address (R)SI into AX.
AD
LODSD
NP
Valid
Valid
For legacy mode, Load dword at address
DS:(E)SI into EAX. For 64-bit mode load dword
at address (R)SI into EAX.
REX.W + AD
LODSQ
NP
Valid
N.E.
Load qword at address (R)SI into RAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Loads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The
source operand is a memory location, the address of which is read from the DS:ESI or the DS:SI registers
(depending on the address-size attribute of the instruction, 32 or 16, respectively). The DS segment may be overridden with a segment override prefix.
At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands” form and the “nooperands” form. The explicit-operands form (specified with the LODS mnemonic) allows the source operand to be
specified explicitly. Here, the source operand should be a symbol that indicates the size and location of the source
value. The destination operand is then automatically selected to match the size of the source operand (the AL
register for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form
is provided to allow documentation; however, note that the documentation provided by this form can be
misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or
doubleword), but it does not have to specify the correct location. The location is always specified by the DS:(E)SI
registers, which must be loaded correctly before the load string instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the LODS instructions.
Here also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the destination operand. The size of the source and destination operands is selected with the mnemonic: LODSB (byte
loaded into register AL), LODSW (word loaded into AX), or LODSD (doubleword loaded into EAX).
After the byte, word, or doubleword is transferred from the memory location into the AL, AX, or EAX register, the
(E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS
register. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.)
The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for
doubleword operations.
LODS/LODSB/LODSW/LODSD/LODSQ—Load String
Vol. 2A 3-539
INSTRUCTION SET REFERENCE, A-L
In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. LODS/LODSQ load the quadword at address
(R)SI into RAX. The (R)SI register is then incremented or decremented automatically according to the setting of
the DF flag in the EFLAGS register.
The LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP prefix for block loads of ECX bytes,
words, or doublewords. More often, however, these instructions are used within a LOOP construct because further
processing of the data moved into the register is usually necessary before the next transfer can be made. See
“REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for a description of the REP prefix.
Operation
IF AL ← SRC; (* Byte load *)
THEN AL ← SRC; (* Byte load *)
IF DF = 0
THEN (E)SI ← (E)SI + 1;
ELSE (E)SI ← (E)SI – 1;
FI;
ELSE IF AX ← SRC; (* Word load *)
THEN IF DF = 0
THEN (E)SI ← (E)SI + 2;
ELSE (E)SI ← (E)SI – 2;
IF;
FI;
ELSE IF EAX ← SRC; (* Doubleword load *)
THEN IF DF = 0
THEN (E)SI ← (E)SI + 4;
ELSE (E)SI ← (E)SI – 4;
FI;
FI;
ELSE IF RAX ← SRC; (* Quadword load *)
THEN IF DF = 0
THEN (R)SI ← (R)SI + 8;
ELSE (R)SI ← (R)SI – 8;
FI;
FI;
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
3-540 Vol. 2A
LODS/LODSB/LODSW/LODSD/LODSQ—Load String
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
LODS/LODSB/LODSW/LODSD/LODSQ—Load String
Vol. 2A 3-541
INSTRUCTION SET REFERENCE, A-L
LOOP/LOOPcc—Loop According to ECX Counter
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
E2 cb
LOOP rel8
D
Valid
Valid
Decrement count; jump short if count ≠ 0.
E1 cb
LOOPE rel8
D
Valid
Valid
Decrement count; jump short if count ≠ 0 and
ZF = 1.
E0 cb
LOOPNE rel8
D
Valid
Valid
Decrement count; jump short if count ≠ 0 and
ZF = 0.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
D
Offset
NA
NA
NA
Description
Performs a loop operation using the RCX, ECX or CX register as a counter (depending on whether address size is 64
bits, 32 bits, or 16 bits). Note that the LOOP instruction ignores REX.W; but 64-bit address size can be over-ridden
using a 67H prefix.
Each time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is
0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If
the count is not zero, a near jump is performed to the destination (target) operand, which is presumably the
instruction at the beginning of the loop.
The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the IP/EIP/RIP register). This offset is generally specified as a label in assembly code, but at the
machine code level, it is encoded as a signed, 8-bit immediate value, which is added to the instruction pointer.
Offsets of –128 to +127 are allowed with this instruction.
Some forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition for terminating the loop before
the count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction
to indicate the condition being tested for. Here, the LOOPcc instruction itself does not affect the state of the ZF flag;
the ZF flag is changed by other instructions in the loop.
Operation
IF (AddressSize = 32)
THEN Count is ECX;
ELSE IF (AddressSize = 64)
Count is RCX;
ELSE Count is CX;
FI;
Count ← Count – 1;
IF Instruction is not LOOP
THEN
IF (Instruction ← LOOPE) or (Instruction ← LOOPZ)
THEN IF (ZF = 1) and (Count ≠ 0)
THEN BranchCond ← 1;
ELSE BranchCond ← 0;
FI;
ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ)
IF (ZF = 0 ) and (Count ≠ 0)
THEN BranchCond ← 1;
ELSE BranchCond ← 0;
3-542 Vol. 2A
LOOP/LOOPcc—Loop According to ECX Counter
INSTRUCTION SET REFERENCE, A-L
FI;
FI;
ELSE (* Instruction = LOOP *)
IF (Count ≠ 0)
THEN BranchCond ← 1;
ELSE BranchCond ← 0;
FI;
FI;
IF BranchCond = 1
THEN
IF OperandSize = 32
THEN EIP ← EIP + SignExtend(DEST);
ELSE IF OperandSize = 64
THEN RIP ← RIP + SignExtend(DEST);
FI;
ELSE IF OperandSize = 16
THEN EIP ← EIP AND 0000FFFFH;
FI;
FI;
IF OperandSize = (32 or 64)
THEN IF (R/E)IP < CS.Base or (R/E)IP > CS.Limit
#GP; FI;
FI;
FI;
ELSE
Terminate loop and continue program execution at (R/E)IP;
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the offset being jumped to is beyond the limits of the CS segment.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH. This condition can occur if a 32-bit address size override
prefix is used.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the offset being jumped to is in a non-canonical form.
#UD
If the LOCK prefix is used.
LOOP/LOOPcc—Loop According to ECX Counter
Vol. 2A 3-543
INSTRUCTION SET REFERENCE, A-L
LSL—Load Segment Limit
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 03 /r
LSL r16, r16/m16
RM
Valid
Valid
Load: r16 ← segment limit, selector r16/m16.
0F 03 /r
LSL r32, r32/m16*
LSL r64, r32/m16*
RM
Valid
Valid
Load: r32 ← segment limit, selector r32/m16.
RM
Valid
Valid
Load: r64 ← segment limit, selector r32/m16
REX.W + 0F 03 /r
NOTES:
* For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source
operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source
operand (which can be a register or a memory location) contains the segment selector for the segment descriptor
being accessed. The destination operand is a general-purpose register.
The processor performs access checks as part of the loading process. Once loaded in the destination register, software can compare the segment limit with the offset of a pointer.
The segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment
descriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination
operand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the
granularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit
before loading it into the destination operand. The translation is performed by shifting the 20-bit “raw” limit left 12
bits and filling the low-order 12 bits with 1s.
When the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size
is 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are truncated and only the low-order 16 bits
are loaded into the destination operand.
This instruction performs the following checks before it loads the segment limit into the destination register:
•
•
Checks that the segment selector is not NULL.
•
Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for
(can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the
following table.
•
If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor
is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of
the segment selector).
Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being
accessed
If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no
value is loaded in the destination operand.
3-544 Vol. 2A
LSL—Load Segment Limit
INSTRUCTION SET REFERENCE, A-L
Table 3-55. Segment and Gate Descriptor Types
Type
Protected Mode
Name
IA-32e Mode
Valid
Name
Valid
0
Reserved
No
Upper 8 byte of a 16-Byte
descriptor
Yes
1
Available 16-bit TSS
Yes
Reserved
No
2
LDT
Yes
LDT
Yes
3
Busy 16-bit TSS
Yes
Reserved
No
4
16-bit call gate
No
Reserved
No
5
16-bit/32-bit task gate
No
Reserved
No
6
16-bit interrupt gate
No
Reserved
No
7
16-bit trap gate
No
Reserved
No
8
Reserved
No
Reserved
No
9
Available 32-bit TSS
Yes
64-bit TSS
Yes
A
Reserved
No
Reserved
No
B
Busy 32-bit TSS
Yes
Busy 64-bit TSS
Yes
C
32-bit call gate
No
64-bit call gate
No
D
Reserved
No
Reserved
No
E
32-bit interrupt gate
No
64-bit interrupt gate
No
F
32-bit trap gate
No
64-bit trap gate
No
Operation
IF SRC(Offset) > descriptor table limit
THEN ZF ← 0; FI;
Read segment descriptor;
IF SegmentDescriptor(Type) ≠ conforming code segment
and (CPL > DPL) OR (RPL > DPL)
or Segment type is not valid for instruction
THEN
ZF ← 0;
ELSE
temp ← SegmentLimit([SRC]);
IF (G ← 1)
THEN temp ← ShiftLeft(12, temp) OR 00000FFFH;
ELSE IF OperandSize = 32
THEN DEST ← temp; FI;
ELSE IF OperandSize = 64 (* REX.W used *)
THEN DEST (* Zero-extended *) ← temp; FI;
ELSE (* OperandSize = 16 *)
DEST ← temp AND FFFFH;
FI;
FI;
Flags Affected
The ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is set to 0.
LSL—Load Segment Limit
Vol. 2A 3-545
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and the memory operand effective address is unaligned while
the current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The LSL instruction cannot be executed in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The LSL instruction cannot be executed in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If the memory operand effective address referencing the SS segment is in a non-canonical
form.
#GP(0)
If the memory operand effective address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and the memory operand effective address is unaligned while
the current privilege level is 3.
#UD
If the LOCK prefix is used.
3-546 Vol. 2A
LSL—Load Segment Limit
INSTRUCTION SET REFERENCE, A-L
LTR—Load Task Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 00 /3
LTR r/m16
M
Valid
Valid
Load r/m16 into task register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Loads the source operand into the segment selector field of the task register. The source operand (a generalpurpose register or a memory location) contains a segment selector that points to a task state segment (TSS).
After the segment selector is loaded in the task register, the processor uses the segment selector to locate the
segment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base
address for the TSS from the segment descriptor into the task register. The task pointed to by the task register is
marked busy, but a switch to the task does not occur.
The LTR instruction is provided for use in operating-system software; it should not be used in application programs.
It can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish
the first task to be executed.
The operand-size attribute has no effect on this instruction.
In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the
64-bit base.
Operation
IF SRC is a NULL selector
THEN #GP(0);
IF SRC(Offset) > descriptor table limit OR IF SRC(type) ≠ global
THEN #GP(segment selector); FI;
Read segment descriptor;
IF segment descriptor is not for an available TSS
THEN #GP(segment selector); FI;
IF segment descriptor is not present
THEN #NP(segment selector); FI;
TSSsegmentDescriptor(busy) ← 1;
(* Locked read-modify-write operation on the entire descriptor when setting busy flag *)
TaskRegister(SegmentSelector) ← SRC;
TaskRegister(SegmentDescriptor) ← TSSSegmentDescriptor;
Flags Affected
None
LTR—Load Task Register
Vol. 2A 3-547
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the source operand contains a NULL segment selector.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#GP(selector)
If the source selector points to a segment that is not a TSS or to one for a task that is already
busy.
If the selector points to LDT or is beyond the GDT limit.
#NP(selector)
If the TSS is marked not present.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The LTR instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The LTR instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
#GP(0)
If a memory address referencing the SS segment is in a non-canonical form.
If the current privilege level is not 0.
If the memory address is in a non-canonical form.
If the source operand contains a NULL segment selector.
#GP(selector)
If the source selector points to a segment that is not a TSS or to one for a task that is already
busy.
If the selector points to LDT or is beyond the GDT limit.
If the descriptor type of the upper 8-byte of the 16-byte descriptor is non-zero.
#NP(selector)
If the TSS is marked not present.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
3-548 Vol. 2A
LTR—Load Task Register
INSTRUCTION SET REFERENCE, A-L
LZCNT— Count the Number of Leading Zero Bits
Opcode/Instruction
Op/
En
CPUID
Feature
Flag
LZCNT
Description
RM
64/32
-bit
Mode
V/V
F3 0F BD /r
LZCNT r16, r/m16
F3 0F BD /r
LZCNT r32, r/m32
RM
V/V
LZCNT
Count the number of leading zero bits in r/m32, return result in r32.
F3 REX.W 0F BD /r
LZCNT r64, r/m64
RM
V/N.E.
LZCNT
Count the number of leading zero bits in r/m64, return result in r64.
Count the number of leading zero bits in r/m16, return result in r16.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Counts the number of leading most significant zero bits in a source operand (second operand) returning the result
into a destination (first operand).
LZCNT differs from BSR. For example, LZCNT will produce the operand size when the input operand is zero. It
should be noted that on processors that do not support LZCNT, the instruction byte encoding is executed as BSR.
In 64-bit mode 64-bit operand size requires REX.W=1.
Operation
temp ← OperandSize - 1
DEST ← 0
WHILE (temp >= 0) AND (Bit(SRC, temp) = 0)
DO
temp ← temp - 1
DEST ← DEST+ 1
OD
IF DEST = OperandSize
CF ← 1
ELSE
CF ← 0
FI
IF DEST = 0
ZF ← 1
ELSE
ZF ← 0
FI
Flags Affected
ZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set
to 1 if input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.
LZCNT— Count the Number of Leading Zero Bits
Vol. 2A 3-549
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
LZCNT:
unsigned __int32 _lzcnt_u32(unsigned __int32 src);
LZCNT:
unsigned __int64 _lzcnt_u64(unsigned __int64 src);
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
selector.
#SS(0)
For an illegal address in the SS segment.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
For an illegal address in the SS segment.
Virtual 8086 Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
For an illegal address in the SS segment.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-550 Vol. 2A
LZCNT— Count the Number of Leading Zero Bits
CHAPTER 4
INSTRUCTION SET REFERENCE, M-U
4.1
IMM8 CONTROL BYTE OPERATION FOR PCMPESTRI / PCMPESTRM /
PCMPISTRI / PCMPISTRM
The notations introduced in this section are referenced in the reference pages of PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM. The operation of the immediate control byte is common to these four string text processing
instructions of SSE4.2. This section describes the common operations.
4.1.1
General Description
The operation of PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM is defined by the combination of the respective opcode and the interpretation of an immediate control byte that is part of the instruction encoding.
The opcode controls the relationship of input bytes/words to each other (determines whether the inputs terminated
strings or whether lengths are expressed explicitly) as well as the desired output (index or mask).
The Imm8 Control Byte for PCMPESTRM/PCMPESTRI/PCMPISTRM/PCMPISTRI encodes a significant amount of
programmable control over the functionality of those instructions. Some functionality is unique to each instruction
while some is common across some or all of the four instructions. This section describes functionality which is
common across the four instructions.
The arithmetic flags (ZF, CF, SF, OF, AF, PF) are set as a result of these instructions. However, the meanings of the
flags have been overloaded from their typical meanings in order to provide additional information regarding the
relationships of the two inputs.
PCMPxSTRx instructions perform arithmetic comparisons between all possible pairs of bytes or words, one from
each packed input source operand. The boolean results of those comparisons are then aggregated in order to
produce meaningful results. The Imm8 Control Byte is used to affect the interpretation of individual input elements
as well as control the arithmetic comparisons used and the specific aggregation scheme.
Specifically, the Imm8 Control Byte consists of bit fields that control the following attributes:
•
•
Source data format — Byte/word data element granularity, signed or unsigned elements
•
•
Polarity — Specifies intermediate processing to be performed on the intermediate result
Aggregation operation — Encodes the mode of per-element comparison operation and the aggregation of
per-element comparisons into an intermediate result
Output selection — Specifies final operation to produce the output (depending on index or mask) from the
intermediate result
Vol. 2B 4-1
INSTRUCTION SET REFERENCE, M-U
4.1.2
Source Data Format
Table 4-1. Source Data Format
Imm8[1:0]
Meaning
Description
00b
Unsigned bytes
Both 128-bit sources are treated as packed, unsigned bytes.
01b
Unsigned words
Both 128-bit sources are treated as packed, unsigned words.
10b
Signed bytes
Both 128-bit sources are treated as packed, signed bytes.
11b
Signed words
Both 128-bit sources are treated as packed, signed words.
If the Imm8 Control Byte has bit[0] cleared, each source contains 16 packed bytes. If the bit is set each source
contains 8 packed words. If the Imm8 Control Byte has bit[1] cleared, each input contains unsigned data. If the
bit is set each source contains signed data.
4.1.3
Aggregation Operation
Table 4-2. Aggregation Operation
Imm8[3:2]
Mode
Comparison
00b
Equal any
The arithmetic comparison is “equal.”
01b
Ranges
Arithmetic comparison is “greater than or equal” between even indexed bytes/words of reg and
each byte/word of reg/mem.
Arithmetic comparison is “less than or equal” between odd indexed bytes/words of reg and each
byte/word of reg/mem.
(reg/mem[m] >= reg[n] for n = even, reg/mem[m] <= reg[n] for n = odd)
10b
Equal each
The arithmetic comparison is “equal.”
11b
Equal ordered
The arithmetic comparison is “equal.”
All 256 (64) possible comparisons are always performed. The individual Boolean results of those comparisons are
referred by “BoolRes[Reg/Mem element index, Reg element index].” Comparisons evaluating to “True” are represented with a 1, False with a 0 (positive logic). The initial results are then aggregated into a 16-bit (8-bit) intermediate result (IntRes1) using one of the modes described in the table below, as determined by Imm8 Control Byte
bit[3:2].
4-2 Vol. 2B
INSTRUCTION SET REFERENCE, M-U
See Section 4.1.6 for a description of the overrideIfDataInvalid() function used in Table 4-3.
Table 4-3. Aggregation Operation
Mode
Pseudocode
Equal any
UpperBound = imm8[0] ? 7 : 15;
(find characters from a set)
IntRes1 = 0;
For j = 0 to UpperBound, j++
For i = 0 to UpperBound, i++
IntRes1[j] OR= overrideIfDataInvalid(BoolRes[j,i])
Ranges
UpperBound = imm8[0] ? 7 : 15;
(find characters from ranges)
IntRes1 = 0;
For j = 0 to UpperBound, j++
For i = 0 to UpperBound, i+=2
IntRes1[j] OR= (overrideIfDataInvalid(BoolRes[j,i]) AND
overrideIfDataInvalid(BoolRes[j,i+1]))
Equal each
UpperBound = imm8[0] ? 7 : 15;
(string compare)
IntRes1 = 0;
For i = 0 to UpperBound, i++
IntRes1[i] = overrideIfDataInvalid(BoolRes[i,i])
Equal ordered
UpperBound = imm8[0] ? 7 :15;
(substring search)
IntRes1 = imm8[0] ? FFH : FFFFH
For j = 0 to UpperBound, j++
For i = 0 to UpperBound-j, k=j to UpperBound, k++, i++
IntRes1[j] AND= overrideIfDataInvalid(BoolRes[k,i])
4.1.4
Polarity
IntRes1 may then be further modified by performing a 1’s complement, according to the value of the Imm8 Control
Byte bit[4]. Optionally, a mask may be used such that only those IntRes1 bits which correspond to “valid” reg/mem
input elements are complemented (note that the definition of a valid input element is dependant on the specific
opcode and is defined in each opcode’s description). The result of the possible negation is referred to as IntRes2.
Table 4-4. Polarity
Imm8[5:4]
Operation
Description
00b
Positive Polarity (+)
IntRes2 = IntRes1
01b
Negative Polarity (-)
IntRes2 = -1 XOR IntRes1
10b
Masked (+)
IntRes2 = IntRes1
11b
Masked (-)
IntRes2[i] = IntRes1[i] if reg/mem[i] invalid, else = ~IntRes1[i]
Vol. 2B 4-3
INSTRUCTION SET REFERENCE, M-U
4.1.5
Output Selection
Table 4-5. Output Selection
Imm8[6] Operation
Description
0b
Least significant index The index returned to ECX is of the least significant set bit in IntRes2.
1b
Most significant index
The index returned to ECX is of the most significant set bit in IntRes2.
For PCMPESTRI/PCMPISTRI, the Imm8 Control Byte bit[6] is used to determine if the index is of the least significant
or most significant bit of IntRes2.
Table 4-6. Output Selection
Imm8[6]
Operation
Description
0b
Bit mask
IntRes2 is returned as the mask to the least significant bits of XMM0 with zero extension to 128
bits.
1b
Byte/word mask
IntRes2 is expanded into a byte/word mask (based on imm8[1]) and placed in XMM0. The
expansion is performed by replicating each bit into all of the bits of the byte/word of the same
index.
Specifically for PCMPESTRM/PCMPISTRM, the Imm8 Control Byte bit[6] is used to determine if the mask is a 16 (8)
bit mask or a 128 bit byte/word mask.
4.1.6
Valid/Invalid Override of Comparisons
PCMPxSTRx instructions allow for the possibility that an end-of-string (EOS) situation may occur within the 128-bit
packed data value (see the instruction descriptions below for details). Any data elements on either source that are
determined to be past the EOS are considered to be invalid, and the treatment of invalid data within a comparison
pair varies depending on the aggregation function being performed.
In general, the individual comparison result for each element pair BoolRes[i.j] can be forced true or false if one or
more elements in the pair are invalid. See Table 4-7.
Table 4-7. Comparison Result for Each Element Pair BoolRes[i.j]
xmm1
byte/ word
xmm2/ m128
byte/word
Imm8[3:2] = 00b
(equal any)
Imm8[3:2] = 01b
(ranges)
Imm8[3:2] = 10b
(equal each)
Imm8[3:2] = 11b
(equal ordered)
Invalid
Invalid
Force false
Force false
Force true
Force true
Invalid
Valid
Force false
Force false
Force false
Force true
Valid
Invalid
Force false
Force false
Force false
Force false
Valid
Valid
Do not force
Do not force
Do not force
Do not force
4-4 Vol. 2B
INSTRUCTION SET REFERENCE, M-U
4.1.7
Summary of Im8 Control byte
Table 4-8. Summary of Imm8 Control Byte
Imm8
Description
-------0b
128-bit sources treated as 16 packed bytes.
-------1b
128-bit sources treated as 8 packed words.
------0-b
Packed bytes/words are unsigned.
------1-b
Packed bytes/words are signed.
----00--b
Mode is equal any.
----01--b
Mode is ranges.
----10--b
Mode is equal each.
----11--b
Mode is equal ordered.
---0----b
IntRes1 is unmodified.
---1----b
IntRes1 is negated (1’s complement).
--0-----b
Negation of IntRes1 is for all 16 (8) bits.
--1-----b
Negation of IntRes1 is masked by reg/mem validity.
-0------b
Index of the least significant, set, bit is used (regardless of corresponding input element validity).
IntRes2 is returned in least significant bits of XMM0.
-1------b
Index of the most significant, set, bit is used (regardless of corresponding input element validity).
Each bit of IntRes2 is expanded to byte/word.
0-------b
This bit currently has no defined effect, should be 0.
1-------b
This bit currently has no defined effect, should be 0.
Vol. 2B 4-5
INSTRUCTION SET REFERENCE, M-U
4.1.8
Diagram Comparison and Aggregation Process
Figure 4-1. Operation of PCMPSTRx and PCMPESTRx
4.2
COMMON TRANSFORMATION AND PRIMITIVE FUNCTIONS FOR SHA1XXX
AND SHA256XXX
The following primitive functions and transformations are used in the algorithmic descriptions of SHA1 and SHA256
instruction extensions SHA1NEXTE, SHA1RNDS4, SHA1MSG1, SHA1MSG2, SHA256RNDS4, SHA256MSG1 and
SHA256MSG2. The operands of these primitives and transformation are generally 32-bit DWORD integers.
•
f0(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This
function is used in SHA1 round 1 to 20 processing.
f0(B,C,D) (B AND C) XOR ((NOT(B) AND D)
•
f1(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This
function is used in SHA1 round 21 to 40 processing.
f1(B,C,D) B XOR C XOR D
•
f2(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This
function is used in SHA1 round 41 to 60 processing.
f2(B,C,D) (B AND C) XOR (B AND D) XOR (C AND D)
4-6 Vol. 2B
INSTRUCTION SET REFERENCE, M-U
•
f3(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This
function is used in SHA1 round 61 to 80 processing. It is the same as f1().
f3(B,C,D) B XOR C XOR D
•
Ch(): A bit oriented logical operation that derives a new dword from three SHA256 state variables (dword).
Ch(E,F,G) (E AND F) XOR ((NOT E) AND G)
•
Maj(): A bit oriented logical operation that derives a new dword from three SHA256 state variables (dword).
Maj(A,B,C) (A AND B) XOR (A AND C) XOR (B AND C)
ROR is rotate right operation
(A ROR N) A[N-1:0] || A[Width-1:N]
ROL is rotate left operation
(A ROL N) A ROR (Width-N)
SHR is the right shift operation
(A SHR N) ZEROES[N-1:0] || A[Width-1:N]
•
Σ0( ): A bit oriented logical and rotational transformation performed on a dword SHA256 state variable.
Σ0(A) (A ROR 2) XOR (A ROR 13) XOR (A ROR 22)
•
Σ1( ): A bit oriented logical and rotational transformation performed on a dword SHA256 state variable.
Σ1(E) (E ROR 6) XOR (E ROR 11) XOR (E ROR 25)
•
σ0( ): A bit oriented logical and rotational transformation performed on a SHA256 message dword used in the
message scheduling.
σ0(W) (W ROR 7) XOR (W ROR 18) XOR (W SHR 3)
•
σ1( ): A bit oriented logical and rotational transformation performed on a SHA256 message dword used in the
message scheduling.
σ1(W) (W ROR 17) XOR (W ROR 19) XOR (W SHR 10)
•
Ki: SHA1 Constants dependent on immediate i.
K0 = 0x5A827999
K1 = 0x6ED9EBA1
K2 = 0X8F1BBCDC
K3 = 0xCA62C1D6
4.3
INSTRUCTIONS (M-U)
Chapter 4 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (M-U). See also: Chapter 3,
“Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A, and Chapter 5, “Instruction Set Reference, V-Z‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2C.
Vol. 2B 4-7
INSTRUCTION SET REFERENCE, M-U
MASKMOVDQU—Store Selected Bytes of Double Quadword
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F F7 /r
RM
V/V
SSE2
Selectively write bytes from xmm1 to
memory location using the byte mask in
xmm2. The default memory location is
specified by DS:DI/EDI/RDI.
RM
V/V
AVX
Selectively write bytes from xmm1 to
memory location using the byte mask in
xmm2. The default memory location is
specified by DS:DI/EDI/RDI.
MASKMOVDQU xmm1, xmm2
VEX.128.66.0F.WIG F7 /r
VMASKMOVDQU xmm1, xmm2
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
Description
Stores selected bytes from the source operand (first operand) into an 128-bit memory location. The mask operand
(second operand) selects which bytes from the source operand are written to memory. The source and mask operands are XMM registers. The memory location specified by the effective address in the DI/EDI/RDI register (the
default segment register is DS, but this may be overridden with a segment-override prefix). The memory location
does not need to be aligned on a natural boundary. (The size of the store address depends on the address-size
attribute.)
The most significant bit in each byte of the mask operand determines whether the corresponding byte in the source
operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.
The MASKMOVDQU instruction generates a non-temporal hint to the processor to minimize cache pollution. The
non-temporal hint is implemented by using a write combining (WC) memory type protocol (see “Caching of
Temporal vs. Non-Temporal Data” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVDQU
instructions if multiple processors might use different memory types to read/write the destination memory locations.
Behavior with a mask of all 0s is as follows:
•
•
No data will be written to memory.
•
Exceptions associated with addressing memory and page faults may still be signaled (implementation
dependent).
•
If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these
memory types is not guaranteed (that is, is reserved) and is implementation-specific.
Signaling of breakpoints (code or data) is not guaranteed; different processor implementations may signal or
not signal these breakpoints.
The MASKMOVDQU instruction can be used to improve performance of algorithms that need to merge data on a
byte-by-byte basis. MASKMOVDQU should not cause a read for ownership; doing so generates unnecessary bandwidth since data is to be written directly using the byte-mask without allocating old data prior to the store.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
If VMASKMOVDQU is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will
cause an #UD exception.
1.ModRM.MOD = 011B required
4-8 Vol. 2B
MASKMOVDQU—Store Selected Bytes of Double Quadword
INSTRUCTION SET REFERENCE, M-U
Operation
IF (MASK[7] = 1)
THEN DEST[DI/EDI] ← SRC[7:0] ELSE (* Memory location unchanged *); FI;
IF (MASK[15] = 1)
THEN DEST[DI/EDI +1] ← SRC[15:8] ELSE (* Memory location unchanged *); FI;
(* Repeat operation for 3rd through 14th bytes in source operand *)
IF (MASK[127] = 1)
THEN DEST[DI/EDI +15] ← SRC[127:120] ELSE (* Memory location unchanged *); FI;
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_maskmoveu_si128(__m128i d, __m128i n, char * p)
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.L= 1
If VEX.vvvv ≠ 1111B.
MASKMOVDQU—Store Selected Bytes of Double Quadword
Vol. 2B 4-9
INSTRUCTION SET REFERENCE, M-U
MASKMOVQ—Store Selected Bytes of Quadword
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F F7 /r
RM
Valid
Valid
Selectively write bytes from mm1 to memory
location using the byte mask in mm2. The
default memory location is specified by
DS:DI/EDI/RDI.
MASKMOVQ mm1, mm2
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
Description
Stores selected bytes from the source operand (first operand) into a 64-bit memory location. The mask operand
(second operand) selects which bytes from the source operand are written to memory. The source and mask operands are MMX technology registers. The memory location specified by the effective address in the DI/EDI/RDI
register (the default segment register is DS, but this may be overridden with a segment-override prefix). The
memory location does not need to be aligned on a natural boundary. (The size of the store address depends on the
address-size attribute.)
The most significant bit in each byte of the mask operand determines whether the corresponding byte in the source
operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.
The MASKMOVQ instruction generates a non-temporal hint to the processor to minimize cache pollution. The nontemporal hint is implemented by using a write combining (WC) memory type protocol (see “Caching of Temporal
vs. Non-Temporal Data” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVQ instructions if
multiple processors might use different memory types to read/write the destination memory locations.
This instruction causes a transition from x87 FPU to MMX technology state (that is, the x87 FPU top-of-stack pointer
is set to 0 and the x87 FPU tag word is set to all 0s [valid]).
The behavior of the MASKMOVQ instruction with a mask of all 0s is as follows:
•
•
•
No data will be written to memory.
•
•
Signaling of breakpoints (code or data) is not guaranteed (implementation dependent).
Transition from x87 FPU to MMX technology state will occur.
Exceptions associated with addressing memory and page faults may still be signaled (implementation
dependent).
If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these
memory types is not guaranteed (that is, is reserved) and is implementation-specific.
The MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byteby-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is
to be written directly using the byte-mask without allocating old data prior to the store.
In 64-bit mode, the memory address is specified by DS:RDI.
4-10 Vol. 2B
MASKMOVQ—Store Selected Bytes of Quadword
INSTRUCTION SET REFERENCE, M-U
Operation
IF (MASK[7] = 1)
THEN DEST[DI/EDI] ← SRC[7:0] ELSE (* Memory location unchanged *); FI;
IF (MASK[15] = 1)
THEN DEST[DI/EDI +1] ← SRC[15:8] ELSE (* Memory location unchanged *); FI;
(* Repeat operation for 3rd through 6th bytes in source operand *)
IF (MASK[63] = 1)
THEN DEST[DI/EDI +15] ← SRC[63:56] ELSE (* Memory location unchanged *); FI;
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_maskmove_si64(__m64d, __m64n, char * p)
Other Exceptions
See Table 22-8, “Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3A.
MASKMOVQ—Store Selected Bytes of Quadword
Vol. 2B 4-11
INSTRUCTION SET REFERENCE, M-U
MAXPD—Maximum of Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5F /r
MAXPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 5F /r
VMAXPD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 5F /r
VMAXPD ymm1, ymm2, ymm3/m256
Description
RVM
V/V
AVX
RVM
V/V
AVX
EVEX.NDS.128.66.0F.W1 5F /r
VMAXPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F.W1 5F /r
VMAXPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F.W1 5F /r
VMAXPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{sae}
FV
V/V
AVX512F
Return the maximum double-precision floating-point
values between xmm1 and xmm2/m128.
Return the maximum double-precision floating-point
values between xmm2 and xmm3/m128.
Return the maximum packed double-precision
floating-point values between ymm2 and
ymm3/m256.
Return the maximum packed double-precision
floating-point values between xmm2 and
xmm3/m128/m64bcst and store result in xmm1
subject to writemask k1.
Return the maximum packed double-precision
floating-point values between ymm2 and
ymm3/m256/m64bcst and store result in ymm1
subject to writemask k1.
Return the maximum packed double-precision
floating-point values between zmm2 and
zmm3/m512/m64bcst and store result in zmm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed double-precision floating-point values in the first source operand and the
second source operand and returns the maximum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MAXPD can be emulated using a
sequence of instructions, such as a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
4-12 Vol. 2B
MAXPD—Maximum of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
Operation
MAX(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 > SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
VMAXPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] MAX(SRC1[i+63:i], SRC2[63:0])
ELSE
DEST[i+63:i] MAX(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMAXPD (VEX.256 encoded version)
DEST[63:0] MAX(SRC1[63:0], SRC2[63:0])
DEST[127:64] MAX(SRC1[127:64], SRC2[127:64])
DEST[191:128] MAX(SRC1[191:128], SRC2[191:128])
DEST[255:192] MAX(SRC1[255:192], SRC2[255:192])
DEST[MAX_VL-1:256] 0
VMAXPD (VEX.128 encoded version)
DEST[63:0] MAX(SRC1[63:0], SRC2[63:0])
DEST[127:64] MAX(SRC1[127:64], SRC2[127:64])
DEST[MAX_VL-1:128] 0
MAXPD—Maximum of Packed Double-Precision Floating-Point Values
Vol. 2B 4-13
INSTRUCTION SET REFERENCE, M-U
MAXPD (128-bit Legacy SSE version)
DEST[63:0] MAX(DEST[63:0], SRC[63:0])
DEST[127:64] MAX(DEST[127:64], SRC[127:64])
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMAXPD __m512d _mm512_max_pd( __m512d a, __m512d b);
VMAXPD __m512d _mm512_mask_max_pd(__m512d s, __mmask8 k, __m512d a, __m512d b,);
VMAXPD __m512d _mm512_maskz_max_pd( __mmask8 k, __m512d a, __m512d b);
VMAXPD __m512d _mm512_max_round_pd( __m512d a, __m512d b, int);
VMAXPD __m512d _mm512_mask_max_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VMAXPD __m512d _mm512_maskz_max_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMAXPD __m256d _mm256_mask_max_pd(__m5256d s, __mmask8 k, __m256d a, __m256d b);
VMAXPD __m256d _mm256_maskz_max_pd( __mmask8 k, __m256d a, __m256d b);
VMAXPD __m128d _mm_mask_max_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VMAXPD __m128d _mm_maskz_max_pd( __mmask8 k, __m128d a, __m128d b);
VMAXPD __m256d _mm256_max_pd (__m256d a, __m256d b);
(V)MAXPD __m128d _mm_max_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
4-14 Vol. 2B
MAXPD—Maximum of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
MAXPS—Maximum of Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 5F /r
MAXPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 5F /r
VMAXPS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.0F.WIG 5F /r
VMAXPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.0F.W0 5F /r
VMAXPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 5F /r
VMAXPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 5F /r
VMAXPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{sae}
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the maximum single-precision floating-point values
between ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Return the maximum packed single-precision floating-point
values between xmm2 and xmm3/m128/m32bcst and store
result in xmm1 subject to writemask k1.
Return the maximum packed single-precision floating-point
values between ymm2 and ymm3/m256/m32bcst and store
result in ymm1 subject to writemask k1.
Return the maximum packed single-precision floating-point
values between zmm2 and zmm3/m512/m32bcst and store
result in zmm1 subject to writemask k1.
Return the maximum single-precision floating-point values
between xmm1 and xmm2/mem.
Return the maximum single-precision floating-point values
between xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed single-precision floating-point values in the first source operand and the
second source operand and returns the maximum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MAXPS can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
MAXPS—Maximum of Packed Single-Precision Floating-Point Values
Vol. 2B 4-15
INSTRUCTION SET REFERENCE, M-U
Operation
MAX(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 > SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
VMAXPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] MAX(SRC1[i+31:i], SRC2[31:0])
ELSE
DEST[i+31:i] MAX(SRC1[i+31:i], SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMAXPS (VEX.256 encoded version)
DEST[31:0] MAX(SRC1[31:0], SRC2[31:0])
DEST[63:32] MAX(SRC1[63:32], SRC2[63:32])
DEST[95:64] MAX(SRC1[95:64], SRC2[95:64])
DEST[127:96] MAX(SRC1[127:96], SRC2[127:96])
DEST[159:128] MAX(SRC1[159:128], SRC2[159:128])
DEST[191:160] MAX(SRC1[191:160], SRC2[191:160])
DEST[223:192] MAX(SRC1[223:192], SRC2[223:192])
DEST[255:224] MAX(SRC1[255:224], SRC2[255:224])
DEST[MAX_VL-1:256] 0
VMAXPS (VEX.128 encoded version)
DEST[31:0] MAX(SRC1[31:0], SRC2[31:0])
DEST[63:32] MAX(SRC1[63:32], SRC2[63:32])
DEST[95:64] MAX(SRC1[95:64], SRC2[95:64])
DEST[127:96] MAX(SRC1[127:96], SRC2[127:96])
DEST[MAX_VL-1:128] 0
4-16 Vol. 2B
MAXPS—Maximum of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
MAXPS (128-bit Legacy SSE version)
DEST[31:0] MAX(DEST[31:0], SRC[31:0])
DEST[63:32] MAX(DEST[63:32], SRC[63:32])
DEST[95:64] MAX(DEST[95:64], SRC[95:64])
DEST[127:96] MAX(DEST[127:96], SRC[127:96])
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMAXPS __m512 _mm512_max_ps( __m512 a, __m512 b);
VMAXPS __m512 _mm512_mask_max_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VMAXPS __m512 _mm512_maskz_max_ps( __mmask16 k, __m512 a, __m512 b);
VMAXPS __m512 _mm512_max_round_ps( __m512 a, __m512 b, int);
VMAXPS __m512 _mm512_mask_max_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VMAXPS __m512 _mm512_maskz_max_round_ps( __mmask16 k, __m512 a, __m512 b, int);
VMAXPS __m256 _mm256_mask_max_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VMAXPS __m256 _mm256_maskz_max_ps( __mmask8 k, __m256 a, __m256 b);
VMAXPS __m128 _mm_mask_max_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMAXPS __m128 _mm_maskz_max_ps( __mmask8 k, __m128 a, __m128 b);
VMAXPS __m256 _mm256_max_ps (__m256 a, __m256 b);
MAXPS __m128 _mm_max_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
MAXPS—Maximum of Packed Single-Precision Floating-Point Values
Vol. 2B 4-17
INSTRUCTION SET REFERENCE, M-U
MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 5F /r
MAXSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 5F /r
VMAXSD xmm1, xmm2,
xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 5F /r
VMAXSD xmm1 {k1}{z}, xmm2,
xmm3/m64{sae}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Return the maximum scalar double-precision floating-point
value between xmm2/m64 and xmm1.
Return the maximum scalar double-precision floating-point
value between xmm3/m64 and xmm2.
Return the maximum scalar double-precision floating-point
value between xmm3/m64 and xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Compares the low double-precision floating-point values in the first source operand and the second source
operand, and returns the maximum value to the low quadword of the destination operand. The second source
operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM
registers. When the second source operand is a memory operand, only 64 bits are accessed.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a
QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN of either source
operand be returned, the action of MAXSD can be emulated using a sequence of instructions, such as, a comparison
followed by AND, ANDN and OR.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VMAXSD is encoded with VEX.L=0. Encoding VMAXSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
4-18 Vol. 2B
MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Operation
MAX(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 > SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
VMAXSD (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[63:0] MAX(SRC1[63:0], SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VMAXSD (VEX.128 encoded version)
DEST[63:0] MAX(SRC1[63:0], SRC2[63:0])
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
MAXSD (128-bit Legacy SSE version)
DEST[63:0] MAX(DEST[63:0], SRC[63:0])
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMAXSD __m128d _mm_max_round_sd( __m128d a, __m128d b, int);
VMAXSD __m128d _mm_mask_max_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMAXSD __m128d _mm_maskz_max_round_sd( __mmask8 k, __m128d a, __m128d b, int);
MAXSD __m128d _mm_max_sd(__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Invalid (Including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value
Vol. 2B 4-19
INSTRUCTION SET REFERENCE, M-U
MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 5F /r
MAXSS xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 5F /r
VMAXSS xmm1, xmm2,
xmm3/m32
EVEX.NDS.LIG.F3.0F.W0 5F /r
VMAXSS xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Return the maximum scalar single-precision floating-point
value between xmm2/m32 and xmm1.
Return the maximum scalar single-precision floating-point
value between xmm3/m32 and xmm2.
Return the maximum scalar single-precision floating-point
value between xmm3/m32 and xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Compares the low single-precision floating-point values in the first source operand and the second source operand,
and returns the maximum value to the low doubleword of the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a
QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN from either source
operand be returned, the action of MAXSS can be emulated using a sequence of instructions, such as, a comparison
followed by AND, ANDN and OR.
The second source operand can be an XMM register or a 32-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. Bits
(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL:128) of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VMAXSS is encoded with VEX.L=0. Encoding VMAXSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
4-20 Vol. 2B
MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Operation
MAX(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 > SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
VMAXSS (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[31:0] MAX(SRC1[31:0], SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VMAXSS (VEX.128 encoded version)
DEST[31:0] MAX(SRC1[31:0], SRC2[31:0])
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
MAXSS (128-bit Legacy SSE version)
DEST[31:0] MAX(DEST[31:0], SRC[31:0])
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMAXSS __m128 _mm_max_round_ss( __m128 a, __m128 b, int);
VMAXSS __m128 _mm_mask_max_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMAXSS __m128 _mm_maskz_max_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MAXSS __m128 _mm_max_ss(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
Invalid (Including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value
Vol. 2B 4-21
INSTRUCTION SET REFERENCE, M-U
MFENCE—Memory Fence
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AE F0
MFENCE
NP
Valid
Valid
Serializes load and store operations.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior
the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes
the MFENCE instruction in program order becomes globally visible before any load or store instruction that follows
the MFENCE instruction.1 The MFENCE instruction is ordered with respect to all load and store instructions, other
MFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID
instruction). MFENCE does not serialize the instruction stream.
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as
out-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of
data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the
producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store
ordering between routines that produce weakly-ordered results and routines that consume that data.
Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and
WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it
is not ordered with respect to executions of the MFENCE instruction; data can be brought into the caches speculatively just before, during, or after the execution of an MFENCE instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Specification of the instruction's opcode above indicates a ModR/M byte of F0. For this instruction, the processor
ignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded by any opcode of the form 0F AE Fx, where x
is in the range 0-7.
Operation
Wait_On_Following_Loads_And_Stores_Until(preceding_loads_and_stores_globally_visible);
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_mfence(void)
Exceptions (All Modes of Operation)
#UD
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
1. A load instruction is considered to become globally visible when the value to be loaded into its destination register is determined.
4-22 Vol. 2B
MFENCE—Memory Fence
INSTRUCTION SET REFERENCE, M-U
MINPD—Minimum of Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5D /r
MINPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 5D /r
VMINPD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG 5D /r
VMINPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 5D /r
VMINPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 5D /r
VMINPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 5D /r
VMINPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{sae}
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the minimum packed double-precision floating-point
values between ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Return the minimum packed double-precision floating-point
values between xmm2 and xmm3/m128/m64bcst and store
result in xmm1 subject to writemask k1.
Return the minimum packed double-precision floating-point
values between ymm2 and ymm3/m256/m64bcst and store
result in ymm1 subject to writemask k1.
Return the minimum packed double-precision floating-point
values between zmm2 and zmm3/m512/m64bcst and store
result in zmm1 subject to writemask k1.
Return the minimum double-precision floating-point values
between xmm1 and xmm2/mem
Return the minimum double-precision floating-point values
between xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed double-precision floating-point values in the first source operand and the
second source operand and returns the minimum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MINPD can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
MINPD—Minimum of Packed Double-Precision Floating-Point Values
Vol. 2B 4-23
INSTRUCTION SET REFERENCE, M-U
Operation
MIN(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 < SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
VMINPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] MIN(SRC1[i+63:i], SRC2[63:0])
ELSE
DEST[i+63:i] MIN(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMINPD (VEX.256 encoded version)
DEST[63:0] MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] MIN(SRC1[127:64], SRC2[127:64])
DEST[191:128] MIN(SRC1[191:128], SRC2[191:128])
DEST[255:192] MIN(SRC1[255:192], SRC2[255:192])
VMINPD (VEX.128 encoded version)
DEST[63:0] MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] MIN(SRC1[127:64], SRC2[127:64])
DEST[MAX_VL-1:128] 0
MINPD (128-bit Legacy SSE version)
DEST[63:0] MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] MIN(SRC1[127:64], SRC2[127:64])
DEST[MAX_VL-1:128] (Unmodified)
4-24 Vol. 2B
MINPD—Minimum of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VMINPD __m512d _mm512_min_pd( __m512d a, __m512d b);
VMINPD __m512d _mm512_mask_min_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VMINPD __m512d _mm512_maskz_min_pd( __mmask8 k, __m512d a, __m512d b);
VMINPD __m512d _mm512_min_round_pd( __m512d a, __m512d b, int);
VMINPD __m512d _mm512_mask_min_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VMINPD __m512d _mm512_maskz_min_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMINPD __m256d _mm256_mask_min_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VMINPD __m256d _mm256_maskz_min_pd( __mmask8 k, __m256d a, __m256d b);
VMINPD __m128d _mm_mask_min_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VMINPD __m128d _mm_maskz_min_pd( __mmask8 k, __m128d a, __m128d b);
VMINPD __m256d _mm256_min_pd (__m256d a, __m256d b);
MINPD __m128d _mm_min_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
MINPD—Minimum of Packed Double-Precision Floating-Point Values
Vol. 2B 4-25
INSTRUCTION SET REFERENCE, M-U
MINPS—Minimum of Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 5D /r
MINPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 5D /r
VMINPS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.0F.WIG 5D /r
VMINPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.0F.W0 5D /r
VMINPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 5D /r
VMINPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 5D /r
VMINPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{sae}
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the minimum single double-precision floating-point
values between ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Return the minimum packed single-precision floating-point
values between xmm2 and xmm3/m128/m32bcst and store
result in xmm1 subject to writemask k1.
Return the minimum packed single-precision floating-point
values between ymm2 and ymm3/m256/m32bcst and store
result in ymm1 subject to writemask k1.
Return the minimum packed single-precision floating-point
values between zmm2 and zmm3/m512/m32bcst and store
result in zmm1 subject to writemask k1.
Return the minimum single-precision floating-point values
between xmm1 and xmm2/mem.
Return the minimum single-precision floating-point values
between xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed single-precision floating-point values in the first source operand and the
second source operand and returns the minimum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MINPS can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
4-26 Vol. 2B
MINPS—Minimum of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
MIN(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 < SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
VMINPS (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] MIN(SRC1[i+31:i], SRC2[31:0])
ELSE
DEST[i+31:i] MIN(SRC1[i+31:i], SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMINPS (VEX.256 encoded version)
DEST[31:0] MIN(SRC1[31:0], SRC2[31:0])
DEST[63:32] MIN(SRC1[63:32], SRC2[63:32])
DEST[95:64] MIN(SRC1[95:64], SRC2[95:64])
DEST[127:96] MIN(SRC1[127:96], SRC2[127:96])
DEST[159:128] MIN(SRC1[159:128], SRC2[159:128])
DEST[191:160] MIN(SRC1[191:160], SRC2[191:160])
DEST[223:192] MIN(SRC1[223:192], SRC2[223:192])
DEST[255:224] MIN(SRC1[255:224], SRC2[255:224])
VMINPS (VEX.128 encoded version)
DEST[31:0] MIN(SRC1[31:0], SRC2[31:0])
DEST[63:32] MIN(SRC1[63:32], SRC2[63:32])
DEST[95:64] MIN(SRC1[95:64], SRC2[95:64])
DEST[127:96] MIN(SRC1[127:96], SRC2[127:96])
DEST[MAX_VL-1:128] 0
MINPS—Minimum of Packed Single-Precision Floating-Point Values
Vol. 2B 4-27
INSTRUCTION SET REFERENCE, M-U
MINPS (128-bit Legacy SSE version)
DEST[31:0] MIN(SRC1[31:0], SRC2[31:0])
DEST[63:32] MIN(SRC1[63:32], SRC2[63:32])
DEST[95:64] MIN(SRC1[95:64], SRC2[95:64])
DEST[127:96] MIN(SRC1[127:96], SRC2[127:96])
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMINPS __m512 _mm512_min_ps( __m512 a, __m512 b);
VMINPS __m512 _mm512_mask_min_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VMINPS __m512 _mm512_maskz_min_ps( __mmask16 k, __m512 a, __m512 b);
VMINPS __m512 _mm512_min_round_ps( __m512 a, __m512 b, int);
VMINPS __m512 _mm512_mask_min_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VMINPS __m512 _mm512_maskz_min_round_ps( __mmask16 k, __m512 a, __m512 b, int);
VMINPS __m256 _mm256_mask_min_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VMINPS __m256 _mm256_maskz_min_ps( __mmask8 k, __m256 a, __m25 b);
VMINPS __m128 _mm_mask_min_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMINPS __m128 _mm_maskz_min_ps( __mmask8 k, __m128 a, __m128 b);
VMINPS __m256 _mm256_min_ps (__m256 a, __m256 b);
MINPS __m128 _mm_min_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
4-28 Vol. 2B
MINPS—Minimum of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
MINSD—Return Minimum Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 5D /r
MINSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 5D /r
VMINSD xmm1, xmm2, xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 5D /r
VMINSD xmm1 {k1}{z}, xmm2,
xmm3/m64{sae}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Return the minimum scalar double-precision floatingpoint value between xmm2/m64 and xmm1.
Return the minimum scalar double-precision floatingpoint value between xmm3/m64 and xmm2.
Return the minimum scalar double-precision floatingpoint value between xmm3/m64 and xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Compares the low double-precision floating-point values in the first source operand and the second source
operand, and returns the minimum value to the low quadword of the destination operand. When the source
operand is a memory operand, only the 64 bits are accessed.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second source operand is an SNaN, then SNaN is returned unchanged to the destination (that is, a
QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand
(from either the first or second source) be returned, the action of MINSD can be emulated using a sequence of
instructions, such as, a comparison followed by AND, ANDN and OR.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VMINSD is encoded with VEX.L=0. Encoding VMINSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
MINSD—Return Minimum Scalar Double-Precision Floating-Point Value
Vol. 2B 4-29
INSTRUCTION SET REFERENCE, M-U
Operation
MIN(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 < SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
MINSD (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[63:0] MIN(SRC1[63:0], SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
MINSD (VEX.128 encoded version)
DEST[63:0] MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
MINSD (128-bit Legacy SSE version)
DEST[63:0] MIN(SRC1[63:0], SRC2[63:0])
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMINSD __m128d _mm_min_round_sd(__m128d a, __m128d b, int);
VMINSD __m128d _mm_mask_min_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMINSD __m128d _mm_maskz_min_round_sd( __mmask8 k, __m128d a, __m128d b, int);
MINSD __m128d _mm_min_sd(__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
4-30 Vol. 2B
MINSD—Return Minimum Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
MINSS—Return Minimum Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 5D /r
MINSS xmm1,xmm2/m32
VEX.NDS.128.F3.0F.WIG 5D /r
VMINSS xmm1,xmm2, xmm3/m32
EVEX.NDS.LIG.F3.0F.W0 5D /r
VMINSS xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Return the minimum scalar single-precision floatingpoint value between xmm2/m32 and xmm1.
Return the minimum scalar single-precision floatingpoint value between xmm3/m32 and xmm2.
Return the minimum scalar single-precision floatingpoint value between xmm3/m32 and xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Compares the low single-precision floating-point values in the first source operand and the second source operand
and returns the minimum value to the low doubleword of the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN
version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN in either source
operand be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison
followed by AND, ANDN and OR.
The second source operand can be an XMM register or a 32-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by (E)VEX.vvvv. Bits
(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VMINSS is encoded with VEX.L=0. Encoding VMINSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
MINSS—Return Minimum Scalar Single-Precision Floating-Point Value
Vol. 2B 4-31
INSTRUCTION SET REFERENCE, M-U
Operation
MIN(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST SRC2;
ELSE IF (SRC1 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC2 = SNaN) THEN DEST SRC2; FI;
ELSE IF (SRC1 < SRC2) THEN DEST SRC1;
ELSE DEST SRC2;
FI;
}
MINSS (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[31:0] MIN(SRC1[31:0], SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VMINSS (VEX.128 encoded version)
DEST[31:0] MIN(SRC1[31:0], SRC2[31:0])
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
MINSS (128-bit Legacy SSE version)
DEST[31:0] MIN(SRC1[31:0], SRC2[31:0])
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMINSS __m128 _mm_min_round_ss( __m128 a, __m128 b, int);
VMINSS __m128 _mm_mask_min_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMINSS __m128 _mm_maskz_min_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MINSS __m128 _mm_min_ss(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
Invalid (Including QNaN Source Operand), Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
4-32 Vol. 2B
MINSS—Return Minimum Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
MONITOR—Set Up Monitor Address
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 C8
MONITOR
NP
Valid
Valid
Sets up a linear address range to be
monitored by hardware and activates the
monitor. The address range should be a writeback memory caching type. The address is
DS:EAX (DS:RAX in 64-bit mode).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
The MONITOR instruction arms address monitoring hardware using an address specified in EAX (the address range
that the monitoring hardware checks for store operations can be determined by using CPUID). A store to an
address within the specified address range triggers the monitoring hardware. The state of monitor hardware is
used by MWAIT.
The content of EAX is an effective address (in 64-bit mode, RAX is used). By default, the DS segment is used to
create a linear address that is monitored. Segment overrides can be used.
ECX and EDX are also used. They communicate other information to MONITOR. ECX specifies optional extensions.
EDX specifies optional hints; it does not change the architectural behavior of the instruction. For the Pentium 4
processor (family 15, model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by the
processor; undefined extensions in ECX raises a general protection fault.
The address range must use memory of the write-back type. Only write-back memory will correctly trigger the
monitoring hardware. Additional information on determining what address range to use in order to prevent false
wake-ups is described in Chapter 8, “Multiple-Processor Management” of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A.
The MONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruction
is subject to the permission checking and faults associated with a byte load. Like a load, MONITOR sets the A-bit
but not the D-bit in page tables.
CPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,
MONITOR may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode
exception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE
MSR; disabling MONITOR clears the CPUID feature flag and causes execution to generate an invalid-opcode exception.
The instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
MONITOR sets up an address range for the monitor hardware using the content of EAX (RAX in 64-bit mode) as an
effective address and puts the monitor hardware in armed state. Always use memory of the write-back caching
type. A store to the specified address range will trigger the monitor hardware. The content of ECX and EDX are
used to communicate other information to the monitor hardware.
Intel C/C++ Compiler Intrinsic Equivalent
MONITOR:
void _mm_monitor(void const *p, unsigned extensions,unsigned hints)
Numeric Exceptions
None
MONITOR—Set Up Monitor Address
Vol. 2B 4-33
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#GP(0)
If the value in EAX is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If ECX ≠ 0.
#SS(0)
If the value in EAX is outside the SS segment limit.
#PF(fault-code)
For a page fault.
#UD
If CPUID.01H:ECX.MONITOR[bit 3] = 0.
If current privilege level is not 0.
Real Address Mode Exceptions
#GP
If the CS, DS, ES, FS, or GS register is used to access memory and the value in EAX is outside
of the effective address space from 0 to FFFFH.
If ECX ≠ 0.
#SS
If the SS register is used to access memory and the value in EAX is outside of the effective
address space from 0 to FFFFH.
#UD
If CPUID.01H:ECX.MONITOR[bit 3] = 0.
Virtual 8086 Mode Exceptions
#UD
The MONITOR instruction is not recognized in virtual-8086 mode (even if
CPUID.01H:ECX.MONITOR[bit 3] = 1).
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the linear address of the operand in the CS, DS, ES, FS, or GS segment is in a non-canonical
form.
If RCX ≠ 0.
#SS(0)
If the SS register is used to access memory and the value in EAX is in a non-canonical form.
#PF(fault-code)
For a page fault.
#UD
If the current privilege level is not 0.
If CPUID.01H:ECX.MONITOR[bit 3] = 0.
4-34 Vol. 2B
MONITOR—Set Up Monitor Address
INSTRUCTION SET REFERENCE, M-U
MOV—Move
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
88 /r
MOV r/m8,r8
MR
Valid
Valid
Move r8 to r/m8.
REX + 88 /r
MOV r/m8***,r8***
MR
Valid
N.E.
Move r8 to r/m8.
89 /r
MOV r/m16,r16
MR
Valid
Valid
Move r16 to r/m16.
89 /r
MOV r/m32,r32
MR
Valid
Valid
Move r32 to r/m32.
REX.W + 89 /r
MOV r/m64,r64
MR
Valid
N.E.
Move r64 to r/m64.
8A /r
MOV r8,r/m8
RM
Valid
Valid
Move r/m8 to r8.
REX + 8A /r
MOV r8***,r/m8***
RM
Valid
N.E.
Move r/m8 to r8.
8B /r
MOV r16,r/m16
RM
Valid
Valid
Move r/m16 to r16.
8B /r
MOV r32,r/m32
RM
Valid
Valid
Move r/m32 to r32.
REX.W + 8B /r
MOV r64,r/m64
RM
Valid
N.E.
Move r/m64 to r64.
8C /r
MOV r/m16,Sreg**
MR
Valid
Valid
Move segment register to r/m16.
REX.W + 8C /r
MOV r/m64,Sreg**
MR
Valid
Valid
Move zero extended 16-bit segment register
to r/m64.
8E /r
MOV Sreg,r/m16**
RM
Valid
Valid
Move r/m16 to segment register.
REX.W + 8E /r
MOV Sreg,r/m64**
RM
Valid
Valid
Move lower 16 bits of r/m64 to segment
register.
A0
MOV AL,moffs8*
FD
Valid
Valid
Move byte at (seg:offset) to AL.
REX.W + A0
MOV AL,moffs8*
FD
Valid
N.E.
Move byte at (offset) to AL.
A1
MOV AX,moffs16*
FD
Valid
Valid
Move word at (seg:offset) to AX.
A1
MOV EAX,moffs32*
FD
Valid
Valid
Move doubleword at (seg:offset) to EAX.
REX.W + A1
MOV RAX,moffs64*
FD
Valid
N.E.
Move quadword at (offset) to RAX.
A2
MOV moffs8,AL
TD
Valid
Valid
Move AL to (seg:offset).
REX.W + A2
MOV moffs8***,AL
TD
Valid
N.E.
Move AL to (offset).
A3
MOV moffs16*,AX
TD
Valid
Valid
Move AX to (seg:offset).
A3
MOV moffs32*,EAX
TD
Valid
Valid
Move EAX to (seg:offset).
REX.W + A3
MOV moffs64*,RAX
TD
Valid
N.E.
Move RAX to (offset).
B0+ rb ib
MOV r8, imm8
OI
Valid
Valid
Move imm8 to r8.
OI
Valid
N.E.
Move imm8 to r8.
REX + B0+ rb ib
***
MOV r8
, imm8
B8+ rw iw
MOV r16, imm16
OI
Valid
Valid
Move imm16 to r16.
B8+ rd id
MOV r32, imm32
OI
Valid
Valid
Move imm32 to r32.
REX.W + B8+ rd io
MOV r64, imm64
OI
Valid
N.E.
Move imm64 to r64.
C6 /0 ib
MOV r/m8, imm8
MI
Valid
Valid
Move imm8 to r/m8.
REX + C6 /0 ib
MOV r/m8***, imm8
MI
Valid
N.E.
Move imm8 to r/m8.
C7 /0 iw
MOV r/m16, imm16
MI
Valid
Valid
Move imm16 to r/m16.
C7 /0 id
MOV r/m32, imm32
MI
Valid
Valid
Move imm32 to r/m32.
REX.W + C7 /0 id
MOV r/m64, imm32
MI
Valid
N.E.
Move imm32 sign extended to 64-bits to
r/m64.
MOV—Move
Vol. 2B 4-35
INSTRUCTION SET REFERENCE, M-U
NOTES:
* The moffs8, moffs16, moffs32 and moffs64 operands specify a simple offset relative to the segment base, where 8, 16, 32 and 64
refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16, 32 or 64
bits.
** In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction (see the following “Description” section for further information).
***In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FD
AL/AX/EAX/RAX
Moffs
NA
NA
TD
Moffs (w)
AL/AX/EAX/RAX
NA
NA
OI
opcode + rd (w)
imm8/16/32/64
NA
NA
MI
ModRM:r/m (w)
imm8/16/32/64
NA
NA
Description
Copies the second operand (source operand) to the first operand (destination operand). The source operand can be
an immediate value, general-purpose register, segment register, or memory location; the destination register can
be a general-purpose register, segment register, or memory location. Both operands must be the same size, which
can be a byte, a word, a doubleword, or a quadword.
The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode exception (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.
If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid
segment selector. In protected mode, moving a segment selector into a segment register automatically causes the
segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part
of the segment register. While loading this information, the segment selector and segment descriptor information
is validated (see the “Operation” algorithm below). The segment descriptor data is obtained from the GDT or LDT
entry for the specified segment selector.
A NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing
a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment
register is loaded with a NULL value causes a general protection exception (#GP) and no memory reference occurs.
Loading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruction. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP,
stack-pointer value) before an interrupt occurs1. Be aware that the LSS instruction offers a more efficient
method of loading the SS and ESP registers.
When executing MOV Reg, Sreg, the processor copies the content of Sreg to the 16 least significant bits of the
general-purpose register. The upper bits of the destination register are zero for most IA-32 processors (Pentium
1. If a code instruction breakpoint (for debug) is placed on an instruction located immediately after a MOV SS instruction, the breakpoint may not be triggered. However, in a sequence of instructions that load the SS register, only the first instruction in the
sequence is guaranteed to delay an interrupt.
In the following sequence, interrupts may be recognized before MOV ESP, EBP executes:
MOV SS, EDX
MOV SS, EAX
MOV ESP, EBP
4-36 Vol. 2B
MOV—Move
INSTRUCTION SET REFERENCE, M-U
Pro processors and later) and all Intel 64 processors, with the exception that bits 31:16 are undefined for Intel
Quark X1000 processors, Pentium and earlier processors.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
DEST ← SRC;
Loading a segment register while in protected mode results in special checks and actions, as described in the
following listing. These checks are performed on the segment selector and the segment descriptor to which it
points.
IF SS is loaded
THEN
IF segment selector is NULL
THEN #GP(0); FI;
IF segment selector index is outside descriptor table limits
or segment selector's RPL ≠ CPL
or segment is not a writable data segment
or DPL ≠ CPL
THEN #GP(selector); FI;
IF segment not marked present
THEN #SS(selector);
ELSE
SS ← segment selector;
SS ← segment descriptor; FI;
FI;
IF DS, ES, FS, or GS is loaded with non-NULL selector
THEN
IF segment selector index is outside descriptor table limits
or segment is not a data or readable code segment
or ((segment is a data or nonconforming code segment)
or ((RPL > DPL) and (CPL > DPL))
THEN #GP(selector); FI;
IF segment not marked present
THEN #NP(selector);
ELSE
SegmentRegister ← segment selector;
SegmentRegister ← segment descriptor; FI;
FI;
IF DS, ES, FS, or GS is loaded with NULL selector
THEN
SegmentRegister ← segment selector;
SegmentRegister ← segment descriptor;
FI;
Flags Affected
None
MOV—Move
Vol. 2B 4-37
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#GP(0)
If attempt is made to load SS register with NULL segment selector.
If the destination operand is in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#GP(selector)
If segment selector index is outside descriptor table limits.
If the SS register is being loaded and the segment selector's RPL and the segment descriptor’s
DPL are not equal to the CPL.
If the SS register is being loaded and the segment pointed to is a
non-writable data segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or
readable code segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or
nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#SS(selector)
If the SS register is being loaded and the segment pointed to is marked not present.
#NP
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not
present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If attempt is made to load the CS register.
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If attempt is made to load the CS register.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If attempt is made to load the CS register.
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
4-38 Vol. 2B
MOV—Move
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
If an attempt is made to load SS register with NULL segment selector when CPL = 3.
If an attempt is made to load SS register with NULL segment selector when CPL < 3 and CPL
≠ RPL.
#GP(selector)
If segment selector index is outside descriptor table limits.
If the memory access to the descriptor table is non-canonical.
If the SS register is being loaded and the segment selector's RPL and the segment descriptor’s
DPL are not equal to the CPL.
If the SS register is being loaded and the segment pointed to is a nonwritable data segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or
readable code segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or
nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0)
If the stack address is in a non-canonical form.
#SS(selector)
If the SS register is being loaded and the segment pointed to is marked not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If attempt is made to load the CS register.
If the LOCK prefix is used.
MOV—Move
Vol. 2B 4-39
INSTRUCTION SET REFERENCE, M-U
MOV—Move to/from Control Registers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 20/r
MR
N.E.
Valid
Move control register to r32.
MR
Valid
N.E.
Move extended control register to r64.
MR
Valid
N.E.
Move extended CR8 to r64.1
RM
N.E.
Valid
Move r32 to control register.
RM
Valid
N.E.
Move r64 to extended control register.
RM
Valid
N.E.
Move r64 to extended CR8.1
MOV r32, CR0–CR7
0F 20/r
MOV r64, CR0–CR7
REX.R + 0F 20 /0
MOV r64, CR8
0F 22 /r
MOV CR0–CR7, r32
0F 22 /r
MOV CR0–CR7, r64
REX.R + 0F 22 /0
MOV CR8, r64
NOTE:
1. MOV CR* instructions, except for MOV CR8, are serializing instructions. MOV CR8 is not
architecturally defined as a serializing instruction. For more information, see Chapter 8 in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Moves the contents of a control register (CR0, CR2, CR3, CR4, or CR8) to a general-purpose register or the
contents of a general purpose register to a control register. The operand size for these instructions is always 32 bits
in non-64-bit modes, regardless of the operand-size attribute. (See “Control Registers” in Chapter 2 of the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for a detailed description of the flags and
fields in the control registers.) This instruction can be executed only when the current privilege level is 0.
At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read.
The 2 bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.
Attempts to reference CR1, CR5, CR6, CR7, and CR9–CR15 result in undefined opcode (#UD) exceptions.
When loading control registers, programs should not attempt to change the reserved bits; that is, always set
reserved bits to the value previously read. An attempt to change CR4's reserved bits will cause a general protection
fault. Reserved bits in CR0 and CR3 remain clear after any load of those registers; attempts to set them have no
impact. On Pentium 4, Intel Xeon and P6 family processors, CR0.ET remains set after any load of CR0; attempts to
clear this bit have no impact.
In certain cases, these instructions have the side effect of invalidating entries in the TLBs and the paging-structure
caches. See Section 4.10.4.1, “Operations that Invalidate TLBs and Paging-Structure Caches,” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A for details.
The following side effects are implementation-specific for the Pentium 4, Intel Xeon, and P6 processor family: when
modifying PE or PG in register CR0, or PSE or PAE in register CR4, all TLB entries are flushed, including global
entries. Software should not depend on this functionality in all Intel 64 or IA-32 processors.
In 64-bit mode, the instruction’s default operation size is 64 bits. The REX.R prefix must be used to access CR8. Use
of REX.B permits access to additional registers (R8-R15). Use of the REX.W prefix or 66H prefix is ignored. Use of
4-40 Vol. 2B
MOV—Move to/from Control Registers
INSTRUCTION SET REFERENCE, M-U
the REX.R prefix to specify a register other than CR8 causes an invalid-opcode exception. See the summary chart
at the beginning of this section for encoding data and limits.
If CR4.PCIDE = 1, bit 63 of the source operand to MOV to CR3 determines whether the instruction invalidates
entries in the TLBs and the paging-structure caches (see Section 4.10.4.1, “Operations that Invalidate TLBs and
Paging-Structure Caches,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). The
instruction does not modify bit 63 of CR3, which is reserved and always 0.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.
Operation
DEST ← SRC;
Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are undefined.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).
If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write 1 to CR4.PCIDE.
If any of the reserved bits are set in the page-directory pointers table (PDPT) and the loading
of a control register causes the PDPT to be loaded into the processor.
#UD
If the LOCK prefix is used.
If an attempt is made to access CR1, CR5, CR6, or CR7.
Real-Address Mode Exceptions
#GP
If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write 1 to CR4.PCIDE.
If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
when the PE flag is set to 0).
#UD
If the LOCK prefix is used.
If an attempt is made to access CR1, CR5, CR6, or CR7.
Virtual-8086 Mode Exceptions
#GP(0)
These instructions cannot be executed in virtual-8086 mode.
Compatibility Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).
If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] ≠ 000H.
If an attempt is made to clear CR0.PG[bit 31] while CR4.PCIDE = 1.
If an attempt is made to write a 1 to any reserved bit in CR3.
If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].
#UD
If the LOCK prefix is used.
If an attempt is made to access CR1, CR5, CR6, or CR7.
MOV—Move to/from Control Registers
Vol. 2B 4-41
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).
If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] ≠ 000H.
If an attempt is made to clear CR0.PG[bit 31].
If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write a 1 to any reserved bit in CR8.
If an attempt is made to write a 1 to any reserved bit in CR3.
If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].
#UD
If the LOCK prefix is used.
If an attempt is made to access CR1, CR5, CR6, or CR7.
If the REX.R prefix is used to specify a register other than CR8.
4-42 Vol. 2B
MOV—Move to/from Control Registers
INSTRUCTION SET REFERENCE, M-U
MOV—Move to/from Debug Registers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 21/r
MR
N.E.
Valid
Move debug register to r32.
MR
Valid
N.E.
Move extended debug register to r64.
RM
N.E.
Valid
Move r32 to debug register.
RM
Valid
N.E.
Move r64 to extended debug register.
MOV r32, DR0–DR7
0F 21/r
MOV r64, DR0–DR7
0F 23 /r
MOV DR0–DR7, r32
0F 23 /r
MOV DR0–DR7, r64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose
register or vice versa. The operand size for these instructions is always 32 bits in non-64-bit modes, regardless of
the operand-size attribute. (See Section 17.2, “Debug Registers”, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for a detailed description of the flags and fields in the debug registers.)
The instructions must be executed at privilege level 0 or in real-address mode.
When the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a
manner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer
to DR6 and DR7, respectively. When the DE flag in CR4 is set, attempts to reference DR4 and DR5 result in an
undefined opcode (#UD) exception. (The CR4 register was added to the IA-32 Architecture beginning with the
Pentium processor.)
At the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read.
The two bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.
In 64-bit mode, the instruction’s default operation size is 64 bits. Use of the REX.B prefix permits access to additional registers (R8–R15). Use of the REX.W or 66H prefix is ignored. Use of the REX.R prefix causes an invalidopcode exception. See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF ((DE = 1) and (SRC or DEST = DR4 or DR5))
THEN
#UD;
ELSE
DEST ← SRC;
FI;
Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are undefined.
MOV—Move to/from Debug Registers
Vol. 2B 4-43
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or
DR5.
If the LOCK prefix is used.
#DB
If any debug register is accessed while the DR7.GD[bit 13] = 1.
Real-Address Mode Exceptions
#UD
If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or
DR5.
If the LOCK prefix is used.
#DB
If any debug register is accessed while the DR7.GD[bit 13] = 1.
Virtual-8086 Mode Exceptions
#GP(0)
The debug registers cannot be loaded or read when in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If an attempt is made to write a 1 to any of bits 63:32 in DR6.
If an attempt is made to write a 1 to any of bits 63:32 in DR7.
#UD
If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or
DR5.
If the LOCK prefix is used.
If the REX.R prefix is used.
#DB
4-44 Vol. 2B
If any debug register is accessed while the DR7.GD[bit 13] = 1.
MOV—Move to/from Debug Registers
INSTRUCTION SET REFERENCE, M-U
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 28 /r
MOVAPD xmm1, xmm2/m128
66 0F 29 /r
MOVAPD xmm2/m128, xmm1
VEX.128.66.0F.WIG 28 /r
VMOVAPD xmm1, xmm2/m128
VEX.128.66.0F.WIG 29 /r
VMOVAPD xmm2/m128, xmm1
VEX.256.66.0F.WIG 28 /r
VMOVAPD ymm1, ymm2/m256
VEX.256.66.0F.WIG 29 /r
VMOVAPD ymm2/m256, ymm1
EVEX.128.66.0F.W1 28 /r
VMOVAPD xmm1 {k1}{z}, xmm2/m128
MR
V/V
SSE2
RM
V/V
AVX
MR
V/V
AVX
RM
V/V
AVX
MR
V/V
AVX
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 28 /r
VMOVAPD ymm1 {k1}{z}, ymm2/m256
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.512.66.0F.W1 28 /r
VMOVAPD zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512F
EVEX.128.66.0F.W1 29 /r
VMOVAPD xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 29 /r
VMOVAPD ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.512.66.0F.W1 29 /r
VMOVAPD zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512F
Description
Move aligned packed double-precision floatingpoint values from xmm2/mem to xmm1.
Move aligned packed double-precision floatingpoint values from xmm1 to xmm2/mem.
Move aligned packed double-precision floatingpoint values from xmm2/mem to xmm1.
Move aligned packed double-precision floatingpoint values from xmm1 to xmm2/mem.
Move aligned packed double-precision floatingpoint values from ymm2/mem to ymm1.
Move aligned packed double-precision floatingpoint values from ymm1 to ymm2/mem.
Move aligned packed double-precision floatingpoint values from xmm2/m128 to xmm1 using
writemask k1.
Move aligned packed double-precision floatingpoint values from ymm2/m256 to ymm1 using
writemask k1.
Move aligned packed double-precision floatingpoint values from zmm2/m512 to zmm1 using
writemask k1.
Move aligned packed double-precision floatingpoint values from xmm1 to xmm2/m128 using
writemask k1.
Move aligned packed double-precision floatingpoint values from ymm1 to ymm2/m256 using
writemask k1.
Move aligned packed double-precision floatingpoint values from zmm1 to zmm2/m512 using
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values
Vol. 2B 4-45
INSTRUCTION SET REFERENCE, M-U
Description
Moves 2, 4 or 8 double-precision floating-point values from the source operand (second operand) to the destination
operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit, 256bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit or
512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit
versions), 32-byte (256-bit version) or 64-byte (EVEX.512 encoded version) boundary or a general-protection
exception (#GP) will be generated. For EVEX encoded versions, the operand must be aligned to the size of the
memory operand. To move double-precision floating-point values to and from unaligned memory locations, use the
VMOVUPD instruction.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float64
memory location, to store the contents of a ZMM register into a 512-bit float64 memory location, or to move data
between two ZMM registers. When the source or destination operand is a memory operand, the operand must be
aligned on a 64-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision
floating-point values to and from unaligned memory locations, use the VMOVUPD instruction.
VEX.256 and EVEX.256 encoded versions:
Moves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte
boundary or a general-protection exception (#GP) will be generated. To move double-precision floating-point
values to and from unaligned memory locations, use the VMOVUPD instruction.
128-bit versions:
Moves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floatingpoint values to and from unaligned memory locations, use the VMOVUPD instruction.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain
unchanged.
(E)VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination ZMM register destination are zeroed.
Operation
VMOVAPD (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-46 Vol. 2B
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VMOVAPD (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
ELSE *DEST[i+63:i] remains unchanged*
; merging-masking
FI;
ENDFOR;
VMOVAPD (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVAPD (VEX.256 encoded version, load - and register copy)
DEST[255:0] SRC[255:0]
DEST[MAX_VL-1:256] 0
VMOVAPD (VEX.256 encoded version, store-form)
DEST[255:0] SRC[255:0]
VMOVAPD (VEX.128 encoded version, load - and register copy)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] 0
MOVAPD (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)
(V)MOVAPD (128-bit store-form version)
DEST[127:0] SRC[127:0]
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values
Vol. 2B 4-47
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VMOVAPD __m512d _mm512_load_pd( void * m);
VMOVAPD __m512d _mm512_mask_load_pd(__m512d s, __mmask8 k, void * m);
VMOVAPD __m512d _mm512_maskz_load_pd( __mmask8 k, void * m);
VMOVAPD void _mm512_store_pd( void * d, __m512d a);
VMOVAPD void _mm512_mask_store_pd( void * d, __mmask8 k, __m512d a);
VMOVAPD __m256d _mm256_mask_load_pd(__m256d s, __mmask8 k, void * m);
VMOVAPD __m256d _mm256_maskz_load_pd( __mmask8 k, void * m);
VMOVAPD void _mm256_mask_store_pd( void * d, __mmask8 k, __m256d a);
VMOVAPD __m128d _mm_mask_load_pd(__m128d s, __mmask8 k, void * m);
VMOVAPD __m128d _mm_maskz_load_pd( __mmask8 k, void * m);
VMOVAPD void _mm_mask_store_pd( void * d, __mmask8 k, __m128d a);
MOVAPD __m256d _mm256_load_pd (double * p);
MOVAPD void _mm256_store_pd(double * p, __m256d a);
MOVAPD __m128d _mm_load_pd (double * p);
MOVAPD void _mm_store_pd(double * p, __m128d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1.
#UD
4-48 Vol. 2B
If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 28 /r
MOVAPS xmm1, xmm2/m128
0F 29 /r
MOVAPS xmm2/m128, xmm1
VEX.128.0F.WIG 28 /r
VMOVAPS xmm1, xmm2/m128
VEX.128.0F.WIG 29 /r
VMOVAPS xmm2/m128, xmm1
VEX.256.0F.WIG 28 /r
VMOVAPS ymm1, ymm2/m256
VEX.256.0F.WIG 29 /r
VMOVAPS ymm2/m256, ymm1
EVEX.128.0F.W0 28 /r
VMOVAPS xmm1 {k1}{z}, xmm2/m128
MR
V/V
SSE
RM
V/V
AVX
MR
V/V
AVX
RM
V/V
AVX
MR
V/V
AVX
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.256.0F.W0 28 /r
VMOVAPS ymm1 {k1}{z}, ymm2/m256
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.512.0F.W0 28 /r
VMOVAPS zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512F
EVEX.128.0F.W0 29 /r
VMOVAPS xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.256.0F.W0 29 /r
VMOVAPS ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.512.0F.W0 29 /r
VMOVAPS zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512F
Description
Move aligned packed single-precision floating-point
values from xmm2/mem to xmm1.
Move aligned packed single-precision floating-point
values from xmm1 to xmm2/mem.
Move aligned packed single-precision floating-point
values from xmm2/mem to xmm1.
Move aligned packed single-precision floating-point
values from xmm1 to xmm2/mem.
Move aligned packed single-precision floating-point
values from ymm2/mem to ymm1.
Move aligned packed single-precision floating-point
values from ymm1 to ymm2/mem.
Move aligned packed single-precision floating-point
values from xmm2/m128 to xmm1 using
writemask k1.
Move aligned packed single-precision floating-point
values from ymm2/m256 to ymm1 using
writemask k1.
Move aligned packed single-precision floating-point
values from zmm2/m512 to zmm1 using
writemask k1.
Move aligned packed single-precision floating-point
values from xmm1 to xmm2/m128 using
writemask k1.
Move aligned packed single-precision floating-point
values from ymm1 to ymm2/m256 using
writemask k1.
Move aligned packed single-precision floating-point
values from zmm1 to zmm2/m512 using
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Moves 4, 8 or 16 single-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit,
256-bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit
or 512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit
version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512 encoded version) boundary or a generalprotection exception (#GP) will be generated. For EVEX.512 encoded versions, the operand must be aligned to the
size of the memory operand. To move single-precision floating-point values to and from unaligned memory locations, use the VMOVUPS instruction.
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values
Vol. 2B 4-49
INSTRUCTION SET REFERENCE, M-U
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32
memory location, to store the contents of a ZMM register into a float32 memory location, or to move data between
two ZMM registers. When the source or destination operand is a memory operand, the operand must be aligned on
a 64-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floatingpoint values to and from unaligned memory locations, use the VMOVUPS instruction.
VEX.256 and EVEX.256 encoded version:
Moves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte
boundary or a general-protection exception (#GP) will be generated.
128-bit versions:
Moves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floatingpoint values to and from unaligned memory locations, use the VMOVUPS instruction.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain
unchanged.
(E)VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination ZMM register are zeroed.
Operation
VMOVAPS (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVAPS (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
SRC[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR;
4-50 Vol. 2B
; merging-masking
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VMOVAPS (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVAPS (VEX.256 encoded version, load - and register copy)
DEST[255:0] SRC[255:0]
DEST[MAX_VL-1:256] 0
VMOVAPS (VEX.256 encoded version, store-form)
DEST[255:0] SRC[255:0]
VMOVAPS (VEX.128 encoded version, load - and register copy)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] 0
MOVAPS (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)
(V)MOVAPS (128-bit store-form version)
DEST[127:0] SRC[127:0]
Intel C/C++ Compiler Intrinsic Equivalent
VMOVAPS __m512 _mm512_load_ps( void * m);
VMOVAPS __m512 _mm512_mask_load_ps(__m512 s, __mmask16 k, void * m);
VMOVAPS __m512 _mm512_maskz_load_ps( __mmask16 k, void * m);
VMOVAPS void _mm512_store_ps( void * d, __m512 a);
VMOVAPS void _mm512_mask_store_ps( void * d, __mmask16 k, __m512 a);
VMOVAPS __m256 _mm256_mask_load_ps(__m256 a, __mmask8 k, void * s);
VMOVAPS __m256 _mm256_maskz_load_ps( __mmask8 k, void * s);
VMOVAPS void _mm256_mask_store_ps( void * d, __mmask8 k, __m256 a);
VMOVAPS __m128 _mm_mask_load_ps(__m128 a, __mmask8 k, void * s);
VMOVAPS __m128 _mm_maskz_load_ps( __mmask8 k, void * s);
VMOVAPS void _mm_mask_store_ps( void * d, __mmask8 k, __m128 a);
MOVAPS __m256 _mm256_load_ps (float * p);
MOVAPS void _mm256_store_ps(float * p, __m256 a);
MOVAPS __m128 _mm_load_ps (float * p);
MOVAPS void _mm_store_ps(float * p, __m128 a);
SIMD Floating-Point Exceptions
None
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values
Vol. 2B 4-51
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E1.
4-52 Vol. 2B
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
MOVBE—Move Data After Swapping Bytes
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 38 F0 /r
MOVBE r16, m16
RM
Valid
Valid
Reverse byte order in m16 and move to r16.
0F 38 F0 /r
MOVBE r32, m32
RM
Valid
Valid
Reverse byte order in m32 and move to r32.
REX.W + 0F 38 F0 /r
MOVBE r64, m64
RM
Valid
N.E.
Reverse byte order in m64 and move to r64.
0F 38 F1 /r
MOVBE m16, r16
MR
Valid
Valid
Reverse byte order in r16 and move to m16.
0F 38 F1 /r
MOVBE m32, r32
MR
Valid
Valid
Reverse byte order in r32 and move to m32.
REX.W + 0F 38 F1 /r
MOVBE m64, r64
MR
Valid
N.E.
Reverse byte order in r64 and move to m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Performs a byte swap operation on the data copied from the second operand (source operand) and store the result
in the first operand (destination operand). The source operand can be a general-purpose register, or memory location; the destination register can be a general-purpose register, or a memory location; however, both operands can
not be registers, and only one operand can be a memory location. Both operands must be the same size, which can
be a word, a doubleword or quadword.
The MOVBE instruction is provided for swapping the bytes on a read from memory or on a write to memory; thus
providing support for converting little-endian values to big-endian format and vice versa.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
TEMP ← SRC
IF ( OperandSize = 16)
THEN
DEST[7:0] ← TEMP[15:8];
DEST[15:8] ← TEMP[7:0];
ELES IF ( OperandSize = 32)
DEST[7:0] ← TEMP[31:24];
DEST[15:8] ← TEMP[23:16];
DEST[23:16] ← TEMP[15:8];
DEST[31:23] ← TEMP[7:0];
ELSE IF ( OperandSize = 64)
DEST[7:0] ← TEMP[63:56];
DEST[15:8] ← TEMP[55:48];
DEST[23:16] ← TEMP[47:40];
DEST[31:24] ← TEMP[39:32];
DEST[39:32] ← TEMP[31:24];
DEST[47:40] ← TEMP[23:16];
DEST[55:48] ← TEMP[15:8];
DEST[63:56] ← TEMP[7:0];
FI;
MOVBE—Move Data After Swapping Bytes
Vol. 2B 4-53
INSTRUCTION SET REFERENCE, M-U
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the destination operand is in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.MOVBE[bit 22] = 0.
If the LOCK prefix is used.
If REP (F3H) prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If CPUID.01H:ECX.MOVBE[bit 22] = 0.
If the LOCK prefix is used.
If REP (F3H) prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.MOVBE[bit 22] = 0.
If the LOCK prefix is used.
If REP (F3H) prefix is used.
If REPNE (F2H) prefix is used and CPUID.01H:ECX.SSE4_2[bit 20] = 0.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If the stack address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.MOVBE[bit 22] = 0.
If the LOCK prefix is used.
If REP (F3H) prefix is used.
4-54 Vol. 2B
MOVBE—Move Data After Swapping Bytes
INSTRUCTION SET REFERENCE, M-U
MOVD/MOVQ—Move Doubleword/Move Quadword
Opcode/
Instruction
Op/ En
64/32-bit CPUID
Mode
Feature
Flag
Description
0F 6E /r
RM
V/V
MMX
Move doubleword from r/m32 to mm.
RM
V/N.E.
MMX
Move quadword from r/m64 to mm.
MR
V/V
MMX
Move doubleword from mm to r/m32.
MR
V/N.E.
MMX
Move quadword from mm to r/m64.
RM
V/V
SSE2
Move doubleword from r/m32 to xmm.
RM
V/N.E.
SSE2
Move quadword from r/m64 to xmm.
MR
V/V
SSE2
Move doubleword from xmm register to r/m32.
MR
V/N.E.
SSE2
Move quadword from xmm register to r/m64.
RM
V/V
AVX
Move doubleword from r/m32 to xmm1.
RM
V/N.E1.
AVX
Move quadword from r/m64 to xmm1.
MR
V/V
AVX
Move doubleword from xmm1 register to r/m32.
MR
V/N.E1.
AVX
Move quadword from xmm1 register to r/m64.
MOVD mm, r/m32
REX.W + 0F 6E /r
MOVQ mm, r/m64
0F 7E /r
MOVD r/m32, mm
REX.W + 0F 7E /r
MOVQ r/m64, mm
66 0F 6E /r
MOVD xmm, r/m32
66 REX.W 0F 6E /r
MOVQ xmm, r/m64
66 0F 7E /r
MOVD r/m32, xmm
66 REX.W 0F 7E /r
MOVQ r/m64, xmm
VEX.128.66.0F.W0 6E /
VMOVD xmm1, r32/m32
VEX.128.66.0F.W1 6E /r
VMOVQ xmm1, r64/m64
VEX.128.66.0F.W0 7E /r
VMOVD r32/m32, xmm1
VEX.128.66.0F.W1 7E /r
VMOVQ r64/m64, xmm1
EVEX.128.66.0F.W0 6E /r
VMOVD xmm1, r32/m32
T1S-RM V/V
AVX512F
Move doubleword from r/m32 to xmm1.
EVEX.128.66.0F.W1 6E /r
VMOVQ xmm1, r64/m64
T1S-RM V/N.E.1
AVX512F
Move quadword from r/m64 to xmm1.
EVEX.128.66.0F.W0 7E /r
VMOVD r32/m32, xmm1
T1S-MR V/V
AVX512F
Move doubleword from xmm1 register to r/m32.
EVEX.128.66.0F.W1 7E /r
VMOVQ r64/m64, xmm1
T1S-MR V/N.E.1
AVX512F
Move quadword from xmm1 register to r/m64.
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
MOVD/MOVQ—Move Doubleword/Move Quadword
Vol. 2B 4-55
INSTRUCTION SET REFERENCE, M-U
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
T1S-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1S-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Copies a doubleword from the source operand (second operand) to the destination operand (first operand). The
source and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or
32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword of an
MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low
doubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot
be used to transfer data between MMX technology registers, between XMM registers, between general-purpose
registers, or between memory locations.
When the destination operand is an MMX technology register, the source operand is written to the low doubleword
of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the
source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
MOVD/Q with XMM destination:
Moves a dword/qword integer from the source operand and stores it in the low 32/64-bits of the destination XMM
register. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit
memory location.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding YMM destination register remain
unchanged. Qword operation requires the use of REX.W=1.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires
the use of VEX.W=1.
EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires
the use of EVEX.W=1.
MOVD/Q with 32/64 reg/mem destination:
Stores the low dword/qword of the source XMM register to 32/64-bit memory location or general-purpose register.
Qword operation requires the use of REX.W=1, VEX.W=1, or EVEX.W=1.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
If VMOVD or VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will
cause an #UD exception.
Operation
MOVD (when destination operand is MMX technology register)
DEST[31:0] ← SRC;
DEST[63:32] ← 00000000H;
MOVD (when destination operand is XMM register)
DEST[31:0] ← SRC;
DEST[127:32] ← 000000000000000000000000H;
DEST[VLMAX-1:128] (Unmodified)
4-56 Vol. 2B
MOVD/MOVQ—Move Doubleword/Move Quadword
INSTRUCTION SET REFERENCE, M-U
MOVD (when source operand is MMX technology or XMM register)
DEST ← SRC[31:0];
VMOVD (VEX-encoded version when destination is an XMM register)
DEST[31:0] SRC[31:0]
DEST[VLMAX-1:32] 0
MOVQ (when destination operand is XMM register)
DEST[63:0] ← SRC[63:0];
DEST[127:64] ← 0000000000000000H;
DEST[VLMAX-1:128] (Unmodified)
MOVQ (when destination operand is r/m64)
DEST[63:0] ← SRC[63:0];
MOVQ (when source operand is XMM register or r/m64)
DEST ← SRC[63:0];
VMOVQ (VEX-encoded version when destination is an XMM register)
DEST[63:0] SRC[63:0]
DEST[VLMAX-1:64] 0
VMOVD (EVEX-encoded version when destination is an XMM register)
DEST[31:0] SRC[31:0]
DEST[511:32] 0H
VMOVQ (EVEX-encoded version when destination is an XMM register)
DEST[63:0] SRC[63:0]
DEST[511:64] 0H
Intel C/C++ Compiler Intrinsic Equivalent
MOVD:
__m64 _mm_cvtsi32_si64 (int i )
MOVD:
int _mm_cvtsi64_si32 ( __m64m )
MOVD:
__m128i _mm_cvtsi32_si128 (int a)
MOVD:
int _mm_cvtsi128_si32 ( __m128i a)
MOVQ:
__int64 _mm_cvtsi128_si64(__m128i);
MOVQ:
__m128i _mm_cvtsi64_si128(__int64);
VMOVD
__m128i _mm_cvtsi32_si128( int);
VMOVD
int _mm_cvtsi128_si32( __m128i );
VMOVQ
__m128i _mm_cvtsi64_si128 (__int64);
VMOVQ
__int64 _mm_cvtsi128_si64(__m128i );
VMOVQ
__m128i _mm_loadl_epi64( __m128i * s);
VMOVQ
void _mm_storel_epi64( __m128i * d, __m128i s);
Flags Affected
None
SIMD Floating-Point Exceptions
None
MOVD/MOVQ—Move Doubleword/Move Quadword
Vol. 2B 4-57
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5.
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD
If VEX.L = 1.
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
4-58 Vol. 2B
MOVD/MOVQ—Move Doubleword/Move Quadword
INSTRUCTION SET REFERENCE, M-U
MOVDDUP—Replicate Double FP Values
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE3
F2 0F 12 /r
MOVDDUP xmm1, xmm2/m64
VEX.128.F2.0F.WIG 12 /r
VMOVDDUP xmm1, xmm2/m64
VEX.256.F2.0F.WIG 12 /r
VMOVDDUP ymm1, ymm2/m256
RM
V/V
AVX
RM
V/V
AVX
EVEX.128.F2.0F.W1 12 /r
VMOVDDUP xmm1 {k1}{z},
xmm2/m64
EVEX.256.F2.0F.W1 12 /r
VMOVDDUP ymm1 {k1}{z},
ymm2/m256
EVEX.512.F2.0F.W1 12 /r
VMOVDDUP zmm1 {k1}{z},
zmm2/m512
DUP-RM
V/V
AVX512VL
AVX512F
DUP-RM
V/V
AVX512VL
AVX512F
DUP-RM
V/V
AVX512F
Description
Move double-precision floating-point value from
xmm2/m64 and duplicate into xmm1.
Move double-precision floating-point value from
xmm2/m64 and duplicate into xmm1.
Move even index double-precision floating-point
values from ymm2/mem and duplicate each element
into ymm1.
Move double-precision floating-point value from
xmm2/m64 and duplicate each element into xmm1
subject to writemask k1.
Move even index double-precision floating-point
values from ymm2/m256 and duplicate each element
into ymm1 subject to writemask k1.
Move even index double-precision floating-point
values from zmm2/m512 and duplicate each element
into zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
DUP-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
For 256-bit or higher versions: Duplicates even-indexed double-precision floating-point values from the source
operand (the second operand) and into adjacent pair and store to the destination operand (the first operand).
For 128-bit versions: Duplicates the low double-precision floating-point value from the source operand (the second
operand) and store to the destination operand (the first operand).
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register are unchanged. The
source operand is XMM register or a 64-bit memory location.
VEX.128 and EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. The source
operand is XMM register or a 64-bit memory location. The destination is updated conditionally under the writemask
for EVEX version.
VEX.256 and EVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed. The source
operand is YMM register or a 256-bit memory location. The destination is updated conditionally under the
writemask for EVEX version.
EVEX.512 encoded version: The destination is updated according to the writemask. The source operand is ZMM
register or a 512-bit memory location.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
MOVDDUP—Replicate Double FP Values
Vol. 2B 4-59
INSTRUCTION SET REFERENCE, M-U
SRC
X3
X2
X1
X0
DEST
X2
X2
X0
X0
Figure 4-2. VMOVDDUP Operation
Operation
VMOVDDUP (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
TMP_SRC[63:0] SRC[63:0]
TMP_SRC[127:64] SRC[63:0]
IF VL >= 256
TMP_SRC[191:128] SRC[191:128]
TMP_SRC[255:192] SRC[191:128]
FI;
IF VL >= 512
TMP_SRC[319:256] SRC[319:256]
TMP_SRC[383:320] SRC[319:256]
TMP_SRC[477:384] SRC[477:384]
TMP_SRC[511:484] SRC[477:384]
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDDUP (VEX.256 encoded version)
DEST[63:0] SRC[63:0]
DEST[127:64] SRC[63:0]
DEST[191:128] SRC[191:128]
DEST[255:192] SRC[191:128]
DEST[MAX_VL-1:256] 0
VMOVDDUP (VEX.128 encoded version)
DEST[63:0] SRC[63:0]
DEST[127:64] SRC[63:0]
DEST[MAX_VL-1:128] 0
4-60 Vol. 2B
MOVDDUP—Replicate Double FP Values
INSTRUCTION SET REFERENCE, M-U
MOVDDUP (128-bit Legacy SSE version)
DEST[63:0] SRC[63:0]
DEST[127:64] SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMOVDDUP __m512d _mm512_movedup_pd( __m512d a);
VMOVDDUP __m512d _mm512_mask_movedup_pd(__m512d s, __mmask8 k, __m512d a);
VMOVDDUP __m512d _mm512_maskz_movedup_pd( __mmask8 k, __m512d a);
VMOVDDUP __m256d _mm256_mask_movedup_pd(__m256d s, __mmask8 k, __m256d a);
VMOVDDUP __m256d _mm256_maskz_movedup_pd( __mmask8 k, __m256d a);
VMOVDDUP __m128d _mm_mask_movedup_pd(__m128d s, __mmask8 k, __m128d a);
VMOVDDUP __m128d _mm_maskz_movedup_pd( __mmask8 k, __m128d a);
MOVDDUP __m256d _mm256_movedup_pd (__m256d a);
MOVDDUP __m128d _mm_movedup_pd (__m128d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E5NF.
#UD
If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.
MOVDDUP—Replicate Double FP Values
Vol. 2B 4-61
INSTRUCTION SET REFERENCE, M-U
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values
Opcode/
Instruction
Op/En
66 0F 6F /r
MOVDQA xmm1, xmm2/m128
66 0F 7F /r
MOVDQA xmm2/m128, xmm1
VEX.128.66.0F.WIG 6F /r
VMOVDQA xmm1, xmm2/m128
VEX.128.66.0F.WIG 7F /r
VMOVDQA xmm2/m128, xmm1
VEX.256.66.0F.WIG 6F /r
VMOVDQA ymm1, ymm2/m256
VEX.256.66.0F.WIG 7F /r
VMOVDQA ymm2/m256, ymm1
EVEX.128.66.0F.W0 6F /r
VMOVDQA32 xmm1 {k1}{z},
xmm2/m128
EVEX.256.66.0F.W0 6F /r
VMOVDQA32 ymm1 {k1}{z},
ymm2/m256
EVEX.512.66.0F.W0 6F /r
VMOVDQA32 zmm1 {k1}{z},
zmm2/m512
EVEX.128.66.0F.W0 7F /r
VMOVDQA32 xmm2/m128 {k1}{z},
xmm1
EVEX.256.66.0F.W0 7F /r
VMOVDQA32 ymm2/m256 {k1}{z},
ymm1
EVEX.512.66.0F.W0 7F /r
VMOVDQA32 zmm2/m512 {k1}{z},
zmm1
EVEX.128.66.0F.W1 6F /r
VMOVDQA64 xmm1 {k1}{z},
xmm2/m128
EVEX.256.66.0F.W1 6F /r
VMOVDQA64 ymm1 {k1}{z},
ymm2/m256
EVEX.512.66.0F.W1 6F /r
VMOVDQA64 zmm1 {k1}{z},
zmm2/m512
EVEX.128.66.0F.W1 7F /r
VMOVDQA64 xmm2/m128 {k1}{z},
xmm1
EVEX.256.66.0F.W1 7F /r
VMOVDQA64 ymm2/m256 {k1}{z},
ymm1
EVEX.512.66.0F.W1 7F /r
VMOVDQA64 zmm2/m512 {k1}{z},
zmm1
4-62 Vol. 2B
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
Description
MR
V/V
SSE2
RM
V/V
AVX
MR
V/V
AVX
RM
V/V
AVX
MR
V/V
AVX
FVM-RM
V/V
AVX512VL
AVX512F
FVM-RM
V/V
AVX512VL
AVX512F
FVM-RM
V/V
AVX512F
FVM-MR
V/V
AVX512VL
AVX512F
FVM-MR
V/V
AVX512VL
AVX512F
FVM-MR
V/V
AVX512F
FVM-RM
V/V
AVX512VL
AVX512F
Move aligned quadword integer values from
xmm2/m128 to xmm1 using writemask k1.
FVM-RM
V/V
AVX512VL
AVX512F
Move aligned quadword integer values from
ymm2/m256 to ymm1 using writemask k1.
FVM-RM
V/V
AVX512F
Move aligned packed quadword integer values
from zmm2/m512 to zmm1 using writemask k1.
FVM-MR
V/V
AVX512VL
AVX512F
FVM-MR
V/V
AVX512VL
AVX512F
FVM-MR
V/V
AVX512F
Move aligned packed quadword integer values
from xmm1 to xmm2/m128 using writemask
k1.
Move aligned packed quadword integer values
from ymm1 to ymm2/m256 using writemask
k1.
Move aligned packed quadword integer values
from zmm1 to zmm2/m512 using writemask k1.
Move aligned packed integer values from
xmm2/mem to xmm1.
Move aligned packed integer values from xmm1
to xmm2/mem.
Move aligned packed integer values from
xmm2/mem to xmm1.
Move aligned packed integer values from xmm1
to xmm2/mem.
Move aligned packed integer values from
ymm2/mem to ymm1.
Move aligned packed integer values from ymm1
to ymm2/mem.
Move aligned packed doubleword integer values
from xmm2/m128 to xmm1 using writemask
k1.
Move aligned packed doubleword integer values
from ymm2/m256 to ymm1 using writemask
k1.
Move aligned packed doubleword integer values
from zmm2/m512 to zmm1 using writemask k1.
Move aligned packed doubleword integer values
from xmm1 to xmm2/m128 using writemask
k1.
Move aligned packed doubleword integer values
from ymm1 to ymm2/m256 using writemask
k1.
Move aligned packed doubleword integer values
from zmm1 to zmm2/m512 using writemask k1.
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values
INSTRUCTION SET REFERENCE, M-U
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX encoded versions:
Moves 128, 256 or 512 bits of packed doubleword/quadword integer values from the source operand (the second
operand) to the destination operand (the first operand). This instruction can be used to load a vector register from
an int32/int64 memory location, to store the contents of a vector register into an int32/int64 memory location, or
to move data between two ZMM registers. When the source or destination operand is a memory operand, the
operand must be aligned on a 16 (EVEX.128)/32(EVEX.256)/64(EVEX.512)-byte boundary or a general-protection
exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the
VMOVDQU instruction.
The destination operand is updated at 32-bit (VMOVDQA32) or 64-bit (VMOVDQA64) granularity according to the
writemask.
VEX.256 encoded version:
Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the
contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary
or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory
locations, use the VMOVDQU instruction. Bits (MAX_VL-1:256) of the destination register are zeroed.
128-bit versions:
Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the
contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary
or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory
locations, use the VMOVDQU instruction.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain
unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values
Vol. 2B 4-63
INSTRUCTION SET REFERENCE, M-U
Operation
VMOVDQA32 (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQA32 (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR;
VMOVDQA32 (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-64 Vol. 2B
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values
INSTRUCTION SET REFERENCE, M-U
VMOVDQA64 (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQA64 (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE *DEST[i+63:i] remains unchanged*
; merging-masking
FI;
ENDFOR;
VMOVDQA64 (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQA (VEX.256 encoded version, load - and register copy)
DEST[255:0] SRC[255:0]
DEST[MAX_VL-1:256] 0
VMOVDQA (VEX.256 encoded version, store-form)
DEST[255:0] SRC[255:0]
VMOVDQA (VEX.128 encoded version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] 0
VMOVDQA (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values
Vol. 2B 4-65
INSTRUCTION SET REFERENCE, M-U
(V)MOVDQA (128-bit store-form version)
DEST[127:0] SRC[127:0]
Intel C/C++ Compiler Intrinsic Equivalent
VMOVDQA32 __m512i _mm512_load_epi32( void * sa);
VMOVDQA32 __m512i _mm512_mask_load_epi32(__m512i s, __mmask16 k, void * sa);
VMOVDQA32 __m512i _mm512_maskz_load_epi32( __mmask16 k, void * sa);
VMOVDQA32 void _mm512_store_epi32(void * d, __m512i a);
VMOVDQA32 void _mm512_mask_store_epi32(void * d, __mmask16 k, __m512i a);
VMOVDQA32 __m256i _mm256_mask_load_epi32(__m256i s, __mmask8 k, void * sa);
VMOVDQA32 __m256i _mm256_maskz_load_epi32( __mmask8 k, void * sa);
VMOVDQA32 void _mm256_store_epi32(void * d, __m256i a);
VMOVDQA32 void _mm256_mask_store_epi32(void * d, __mmask8 k, __m256i a);
VMOVDQA32 __m128i _mm_mask_load_epi32(__m128i s, __mmask8 k, void * sa);
VMOVDQA32 __m128i _mm_maskz_load_epi32( __mmask8 k, void * sa);
VMOVDQA32 void _mm_store_epi32(void * d, __m128i a);
VMOVDQA32 void _mm_mask_store_epi32(void * d, __mmask8 k, __m128i a);
VMOVDQA64 __m512i _mm512_load_epi64( void * sa);
VMOVDQA64 __m512i _mm512_mask_load_epi64(__m512i s, __mmask8 k, void * sa);
VMOVDQA64 __m512i _mm512_maskz_load_epi64( __mmask8 k, void * sa);
VMOVDQA64 void _mm512_store_epi64(void * d, __m512i a);
VMOVDQA64 void _mm512_mask_store_epi64(void * d, __mmask8 k, __m512i a);
VMOVDQA64 __m256i _mm256_mask_load_epi64(__m256i s, __mmask8 k, void * sa);
VMOVDQA64 __m256i _mm256_maskz_load_epi64( __mmask8 k, void * sa);
VMOVDQA64 void _mm256_store_epi64(void * d, __m256i a);
VMOVDQA64 void _mm256_mask_store_epi64(void * d, __mmask8 k, __m256i a);
VMOVDQA64 __m128i _mm_mask_load_epi64(__m128i s, __mmask8 k, void * sa);
VMOVDQA64 __m128i _mm_maskz_load_epi64( __mmask8 k, void * sa);
VMOVDQA64 void _mm_store_epi64(void * d, __m128i a);
VMOVDQA64 void _mm_mask_store_epi64(void * d, __mmask8 k, __m128i a);
MOVDQA void __m256i _mm256_load_si256 (__m256i * p);
MOVDQA _mm256_store_si256(_m256i *p, __m256i a);
MOVDQA __m128i _mm_load_si128 (__m128i * p);
MOVDQA void _mm_store_si128(__m128i *p, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1.
#UD
4-66 Vol. 2B
If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values
INSTRUCTION SET REFERENCE, M-U
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F3 0F 6F /r
MOVDQU xmm1, xmm2/m128
F3 0F 7F /r
MOVDQU xmm2/m128, xmm1
VEX.128.F3.0F.WIG 6F /r
VMOVDQU xmm1, xmm2/m128
VEX.128.F3.0F.WIG 7F /r
VMOVDQU xmm2/m128, xmm1
VEX.256.F3.0F.WIG 6F /r
VMOVDQU ymm1, ymm2/m256
VEX.256.F3.0F.WIG 7F /r
VMOVDQU ymm2/m256, ymm1
EVEX.128.F2.0F.W0 6F /r
VMOVDQU8 xmm1 {k1}{z}, xmm2/m128
MR
V/V
SSE2
RM
V/V
AVX
MR
V/V
AVX
RM
V/V
AVX
MR
V/V
AVX
FVM-RM
V/V
AVX512VL
AVX512BW
EVEX.256.F2.0F.W0 6F /r
VMOVDQU8 ymm1 {k1}{z}, ymm2/m256
FVM-RM
V/V
AVX512VL
AVX512BW
EVEX.512.F2.0F.W0 6F /r
VMOVDQU8 zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512BW
EVEX.128.F2.0F.W0 7F /r
VMOVDQU8 xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512BW
EVEX.256.F2.0F.W0 7F /r
VMOVDQU8 ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512BW
EVEX.512.F2.0F.W0 7F /r
VMOVDQU8 zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512BW
EVEX.128.F2.0F.W1 6F /r
VMOVDQU16 xmm1 {k1}{z}, xmm2/m128
FVM-RM
V/V
AVX512VL
AVX512BW
EVEX.256.F2.0F.W1 6F /r
VMOVDQU16 ymm1 {k1}{z}, ymm2/m256
FVM-RM
V/V
AVX512VL
AVX512BW
EVEX.512.F2.0F.W1 6F /r
VMOVDQU16 zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512BW
EVEX.128.F2.0F.W1 7F /r
VMOVDQU16 xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512BW
EVEX.256.F2.0F.W1 7F /r
VMOVDQU16 ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512BW
EVEX.512.F2.0F.W1 7F /r
VMOVDQU16 zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512BW
EVEX.128.F3.0F.W0 6F /r
VMOVDQU32 xmm1 {k1}{z},
xmm2/mm128
FVM-RM
V/V
AVX512VL
AVX512F
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
Description
Move unaligned packed integer values from
xmm2/m128 to xmm1.
Move unaligned packed integer values from
xmm1 to xmm2/m128.
Move unaligned packed integer values from
xmm2/m128 to xmm1.
Move unaligned packed integer values from
xmm1 to xmm2/m128.
Move unaligned packed integer values from
ymm2/m256 to ymm1.
Move unaligned packed integer values from
ymm1 to ymm2/m256.
Move unaligned packed byte integer values
from xmm2/m128 to xmm1 using writemask
k1.
Move unaligned packed byte integer values
from ymm2/m256 to ymm1 using writemask
k1.
Move unaligned packed byte integer values
from zmm2/m512 to zmm1 using writemask
k1.
Move unaligned packed byte integer values
from xmm1 to xmm2/m128 using writemask
k1.
Move unaligned packed byte integer values
from ymm1 to ymm2/m256 using writemask
k1.
Move unaligned packed byte integer values
from zmm1 to zmm2/m512 using writemask
k1.
Move unaligned packed word integer values
from xmm2/m128 to xmm1 using writemask
k1.
Move unaligned packed word integer values
from ymm2/m256 to ymm1 using writemask
k1.
Move unaligned packed word integer values
from zmm2/m512 to zmm1 using writemask
k1.
Move unaligned packed word integer values
from xmm1 to xmm2/m128 using writemask
k1.
Move unaligned packed word integer values
from ymm1 to ymm2/m256 using writemask
k1.
Move unaligned packed word integer values
from zmm1 to zmm2/m512 using writemask
k1.
Move unaligned packed doubleword integer
values from xmm2/m128 to xmm1 using
writemask k1.
Vol. 2B 4-67
INSTRUCTION SET REFERENCE, M-U
Opcode/
Instruction
Op/En
FVM-RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.256.F3.0F.W0 6F /r
VMOVDQU32 ymm1 {k1}{z}, ymm2/m256
EVEX.512.F3.0F.W0 6F /r
VMOVDQU32 zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512F
EVEX.128.F3.0F.W0 7F /r
VMOVDQU32 xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F.W0 7F /r
VMOVDQU32 ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F.W0 7F /r
VMOVDQU32 zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512F
EVEX.128.F3.0F.W1 6F /r
VMOVDQU64 xmm1 {k1}{z}, xmm2/m128
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F.W1 6F /r
VMOVDQU64 ymm1 {k1}{z}, ymm2/m256
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F.W1 6F /r
VMOVDQU64 zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512F
EVEX.128.F3.0F.W1 7F /r
VMOVDQU64 xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F.W1 7F /r
VMOVDQU64 ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F.W1 7F /r
VMOVDQU64 zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512F
Description
Move unaligned packed doubleword integer
values from ymm2/m256 to ymm1 using
writemask k1.
Move unaligned packed doubleword integer
values from zmm2/m512 to zmm1 using
writemask k1.
Move unaligned packed doubleword integer
values from xmm1 to xmm2/m128 using
writemask k1.
Move unaligned packed doubleword integer
values from ymm1 to ymm2/m256 using
writemask k1.
Move unaligned packed doubleword integer
values from zmm1 to zmm2/m512 using
writemask k1.
Move unaligned packed quadword integer
values from xmm2/m128 to xmm1 using
writemask k1.
Move unaligned packed quadword integer
values from ymm2/m256 to ymm1 using
writemask k1.
Move unaligned packed quadword integer
values from zmm2/m512 to zmm1 using
writemask k1.
Move unaligned packed quadword integer
values from xmm1 to xmm2/m128 using
writemask k1.
Move unaligned packed quadword integer
values from ymm1 to ymm2/m256 using
writemask k1.
Move unaligned packed quadword integer
values from zmm1 to zmm2/m512 using
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX encoded versions:
Moves 128, 256 or 512 bits of packed byte/word/doubleword/quadword integer values from the source operand
(the second operand) to the destination operand (first operand). This instruction can be used to load a vector
register from a memory location, to store the contents of a vector register into a memory location, or to move data
between two vector registers.
4-68 Vol. 2B
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
INSTRUCTION SET REFERENCE, M-U
The destination operand is updated at 8-bit (VMOVDQU8), 16-bit (VMOVDQU16), 32-bit (VMOVDQU32), or 64-bit
(VMOVDQU64) granularity according to the writemask.
VEX.256 encoded version:
Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the
contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.
Bits (MAX_VL-1:256) of the destination register are zeroed.
128-bit versions:
Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the
contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
When the source or destination operand is a memory operand, the operand may be unaligned to any alignment
without causing a general-protection exception (#GP) to be generated
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.
Operation
VMOVDQU8 (EVEX encoded versions, register-copy form)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SRC[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE DEST[i+7:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU8 (EVEX encoded versions, store-form)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i]
SRC[i+7:i]
ELSE *DEST[i+7:i] remains unchanged*
FI;
ENDFOR;
; merging-masking
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
Vol. 2B 4-69
INSTRUCTION SET REFERENCE, M-U
VMOVDQU8 (EVEX encoded versions, load-form)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SRC[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE DEST[i+7:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU16 (EVEX encoded versions, register-copy form)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE DEST[i+15:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU16 (EVEX encoded versions, store-form)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i]
SRC[i+15:i]
ELSE *DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR;
4-70 Vol. 2B
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
INSTRUCTION SET REFERENCE, M-U
VMOVDQU16 (EVEX encoded versions, load-form)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE DEST[i+15:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU32 (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU32 (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
SRC[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR;
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
Vol. 2B 4-71
INSTRUCTION SET REFERENCE, M-U
VMOVDQU32 (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU64 (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU64 (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE *DEST[i+63:i] remains unchanged*
; merging-masking
FI;
ENDFOR;
4-72 Vol. 2B
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
INSTRUCTION SET REFERENCE, M-U
VMOVDQU64 (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVDQU (VEX.256 encoded version, load - and register copy)
DEST[255:0] SRC[255:0]
DEST[MAX_VL-1:256] 0
VMOVDQU (VEX.256 encoded version, store-form)
DEST[255:0] SRC[255:0]
VMOVDQU (VEX.128 encoded version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] 0
VMOVDQU (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)
(V)MOVDQU (128-bit store-form version)
DEST[127:0] SRC[127:0]
Intel C/C++ Compiler Intrinsic Equivalent
VMOVDQU16 __m512i _mm512_mask_loadu_epi16(__m512i s, __mmask32 k, void * sa);
VMOVDQU16 __m512i _mm512_maskz_loadu_epi16( __mmask32 k, void * sa);
VMOVDQU16 void _mm512_mask_storeu_epi16(void * d, __mmask32 k, __m512i a);
VMOVDQU16 __m256i _mm256_mask_loadu_epi16(__m256i s, __mmask16 k, void * sa);
VMOVDQU16 __m256i _mm256_maskz_loadu_epi16( __mmask16 k, void * sa);
VMOVDQU16 void _mm256_mask_storeu_epi16(void * d, __mmask16 k, __m256i a);
VMOVDQU16 void _mm256_maskz_storeu_epi16(void * d, __mmask16 k);
VMOVDQU16 __m128i _mm_mask_loadu_epi16(__m128i s, __mmask8 k, void * sa);
VMOVDQU16 __m128i _mm_maskz_loadu_epi16( __mmask8 k, void * sa);
VMOVDQU16 void _mm_mask_storeu_epi16(void * d, __mmask8 k, __m128i a);
VMOVDQU32 __m512i _mm512_loadu_epi32( void * sa);
VMOVDQU32 __m512i _mm512_mask_loadu_epi32(__m512i s, __mmask16 k, void * sa);
VMOVDQU32 __m512i _mm512_maskz_loadu_epi32( __mmask16 k, void * sa);
VMOVDQU32 void _mm512_storeu_epi32(void * d, __m512i a);
VMOVDQU32 void _mm512_mask_storeu_epi32(void * d, __mmask16 k, __m512i a);
VMOVDQU32 __m256i _mm256_mask_loadu_epi32(__m256i s, __mmask8 k, void * sa);
VMOVDQU32 __m256i _mm256_maskz_loadu_epi32( __mmask8 k, void * sa);
VMOVDQU32 void _mm256_storeu_epi32(void * d, __m256i a);
VMOVDQU32 void _mm256_mask_storeu_epi32(void * d, __mmask8 k, __m256i a);
VMOVDQU32 __m128i _mm_mask_loadu_epi32(__m128i s, __mmask8 k, void * sa);
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
Vol. 2B 4-73
INSTRUCTION SET REFERENCE, M-U
VMOVDQU32 __m128i _mm_maskz_loadu_epi32( __mmask8 k, void * sa);
VMOVDQU32 void _mm_storeu_epi32(void * d, __m128i a);
VMOVDQU32 void _mm_mask_storeu_epi32(void * d, __mmask8 k, __m128i a);
VMOVDQU64 __m512i _mm512_loadu_epi64( void * sa);
VMOVDQU64 __m512i _mm512_mask_loadu_epi64(__m512i s, __mmask8 k, void * sa);
VMOVDQU64 __m512i _mm512_maskz_loadu_epi64( __mmask8 k, void * sa);
VMOVDQU64 void _mm512_storeu_epi64(void * d, __m512i a);
VMOVDQU64 void _mm512_mask_storeu_epi64(void * d, __mmask8 k, __m512i a);
VMOVDQU64 __m256i _mm256_mask_loadu_epi64(__m256i s, __mmask8 k, void * sa);
VMOVDQU64 __m256i _mm256_maskz_loadu_epi64( __mmask8 k, void * sa);
VMOVDQU64 void _mm256_storeu_epi64(void * d, __m256i a);
VMOVDQU64 void _mm256_mask_storeu_epi64(void * d, __mmask8 k, __m256i a);
VMOVDQU64 __m128i _mm_mask_loadu_epi64(__m128i s, __mmask8 k, void * sa);
VMOVDQU64 __m128i _mm_maskz_loadu_epi64( __mmask8 k, void * sa);
VMOVDQU64 void _mm_storeu_epi64(void * d, __m128i a);
VMOVDQU64 void _mm_mask_storeu_epi64(void * d, __mmask8 k, __m128i a);
VMOVDQU8 __m512i _mm512_mask_loadu_epi8(__m512i s, __mmask64 k, void * sa);
VMOVDQU8 __m512i _mm512_maskz_loadu_epi8( __mmask64 k, void * sa);
VMOVDQU8 void _mm512_mask_storeu_epi8(void * d, __mmask64 k, __m512i a);
VMOVDQU8 __m256i _mm256_mask_loadu_epi8(__m256i s, __mmask32 k, void * sa);
VMOVDQU8 __m256i _mm256_maskz_loadu_epi8( __mmask32 k, void * sa);
VMOVDQU8 void _mm256_mask_storeu_epi8(void * d, __mmask32 k, __m256i a);
VMOVDQU8 void _mm256_maskz_storeu_epi8(void * d, __mmask32 k);
VMOVDQU8 __m128i _mm_mask_loadu_epi8(__m128i s, __mmask16 k, void * sa);
VMOVDQU8 __m128i _mm_maskz_loadu_epi8( __mmask16 k, void * sa);
VMOVDQU8 void _mm_mask_storeu_epi8(void * d, __mmask16 k, __m128i a);
MOVDQU __m256i _mm256_loadu_si256 (__m256i * p);
MOVDQU _mm256_storeu_si256(_m256i *p, __m256i a);
MOVDQU __m128i _mm_loadu_si128 (__m128i * p);
MOVDQU _mm_storeu_si128(__m128i *p, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD
4-74 Vol. 2B
If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
INSTRUCTION SET REFERENCE, M-U
MOVDQ2Q—Move Quadword from XMM to MMX Technology Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F2 0F D6 /r
MOVDQ2Q mm, xmm
RM
Valid
Valid
Move low quadword from xmm to mmx
register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Moves the low quadword from the source operand (second operand) to the destination operand (first operand).
The source operand is an XMM register and the destination operand is an MMX technology register.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST ← SRC[63:0];
Intel C/C++ Compiler Intrinsic Equivalent
MOVDQ2Q:
__m64 _mm_movepi64_pi64 ( __m128i a)
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#NM
#UD
If CR0.TS[bit 3] = 1.
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
#MF
If there is a pending x87 FPU exception.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
MOVDQ2Q—Move Quadword from XMM to MMX Technology Register
Vol. 2B 4-75
INSTRUCTION SET REFERENCE, M-U
MOVHLPS—Move Packed Single-Precision Floating-Point Values High to Low
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 12 /r
MOVHLPS xmm1, xmm2
VEX.NDS.128.0F.WIG 12 /r
VMOVHLPS xmm1, xmm2, xmm3
EVEX.NDS.128.0F.W0 12 /r
VMOVHLPS xmm1, xmm2, xmm3
RVM
V/V
AVX
RVM
V/V
AVX512F
Description
Move two packed single-precision floating-point values
from high quadword of xmm2 to low quadword of xmm1.
Merge two packed single-precision floating-point values
from high quadword of xmm3 and low quadword of xmm2.
Merge two packed single-precision floating-point values
from high quadword of xmm3 and low quadword of xmm2.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction cannot be used for memory to register moves.
128-bit two-argument form:
Moves two packed single-precision floating-point values from the high quadword of the second XMM argument
(second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of
the destination operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register remain
unchanged.
128-bit and EVEX three-argument form
Moves two packed single-precision floating-point values from the high quadword of the third XMM argument (third
operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM
argument (second operand) to the high quadword of the destination (first operand). Bits (MAX_VL-1:128) of the
corresponding destination register are zeroed.
If VMOVHLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L’L= 1 will cause an #UD exception.
Operation
MOVHLPS (128-bit two-argument form)
DEST[63:0] SRC[127:64]
DEST[MAX_VL-1:64] (Unmodified)
VMOVHLPS (128-bit three-argument form - VEX & EVEX)
DEST[63:0] SRC2[127:64]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
None
1. ModRM.MOD = 011B required
4-76 Vol. 2B
MOVHLPS—Move Packed Single-Precision Floating-Point Values High to Low
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7; additionally
#UD
If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E7NM.128.
MOVHLPS—Move Packed Single-Precision Floating-Point Values High to Low
Vol. 2B 4-77
INSTRUCTION SET REFERENCE, M-U
MOVHPD—Move High Packed Double-Precision Floating-Point Value
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 16 /r
MOVHPD xmm1, m64
VEX.NDS.128.66.0F.WIG 16 /r
VMOVHPD xmm2, xmm1, m64
EVEX.NDS.128.66.0F.W1 16 /r
VMOVHPD xmm2, xmm1, m64
66 0F 17 /r
MOVHPD m64, xmm1
VEX.128.66.0F.WIG 17 /r
VMOVHPD m64, xmm1
EVEX.128.66.0F.W1 17 /r
VMOVHPD m64, xmm1
RVM
V/V
AVX
T1S
V/V
AVX512F
MR
V/V
SSE2
MR
V/V
AVX
T1S-MR
V/V
AVX512F
Description
Move double-precision floating-point value from m64
to high quadword of xmm1.
Merge double-precision floating-point value from m64
and the low quadword of xmm1.
Merge double-precision floating-point value from m64
and the low quadword of xmm1.
Move double-precision floating-point value from high
quadword of xmm1 to m64.
Move double-precision floating-point value from high
quadword of xmm1 to m64.
Move double-precision floating-point value from high
quadword of xmm1 to m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
T1S-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves a double-precision floating-point value from the source 64-bit memory operand and stores it in the high 64bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of
the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads a double-precision floating-point value from the source 64-bit memory operand (the third operand) and
stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source
operand (second operand) are copied to the low 64-bits of the destination. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
128-bit store:
Stores a double-precision floating-point value from the high 64-bits of the XMM register source (second operand)
to the 64-bit memory location (first operand).
Note: VMOVHPD (store) (VEX.128.66.0F 17 /r) is legal and has the same behavior as the existing 66 0F 17 store.
For VMOVHPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVHPD is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L’L= 1 will cause an #UD exception.
4-78 Vol. 2B
MOVHPD—Move High Packed Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Operation
MOVHPD (128-bit Legacy SSE load)
DEST[63:0] (Unmodified)
DEST[127:64] SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)
VMOVHPD (VEX.128 & EVEX encoded load)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
DEST[MAX_VL-1:128] 0
VMOVHPD (store)
DEST[63:0] SRC[127:64]
Intel C/C++ Compiler Intrinsic Equivalent
MOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p)
MOVHPD void _mm_storeh_pd (double *p, __m128d a)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD
If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.
MOVHPD—Move High Packed Double-Precision Floating-Point Value
Vol. 2B 4-79
INSTRUCTION SET REFERENCE, M-U
MOVHPS—Move High Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 16 /r
MOVHPS xmm1, m64
VEX.NDS.128.0F.WIG 16 /r
VMOVHPS xmm2, xmm1, m64
EVEX.NDS.128.0F.W0 16 /r
VMOVHPS xmm2, xmm1, m64
0F 17 /r
MOVHPS m64, xmm1
VEX.128.0F.WIG 17 /r
VMOVHPS m64, xmm1
EVEX.128.0F.W0 17 /r
VMOVHPS m64, xmm1
RVM
V/V
AVX
T2
V/V
AVX512F
MR
V/V
SSE
MR
V/V
AVX
T2-MR
V/V
AVX512F
Description
Move two packed single-precision floating-point values
from m64 to high quadword of xmm1.
Merge two packed single-precision floating-point values
from m64 and the low quadword of xmm1.
Merge two packed single-precision floating-point values
from m64 and the low quadword of xmm1.
Move two packed single-precision floating-point values
from high quadword of xmm1 to m64.
Move two packed single-precision floating-point values
from high quadword of xmm1 to m64.
Move two packed single-precision floating-point values
from high quadword of xmm1 to m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
T2
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
T2-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves two packed single-precision floating-point values from the source 64-bit memory operand and stores them
in the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits
(MAX_VL-1:128) of the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads two single-precision floating-point values from the source 64-bit memory operand (the third operand) and
stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source
operand (the second operand) are copied to the lower 64-bits of the destination. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
128-bit store:
Stores two packed single-precision floating-point values from the high 64-bits of the XMM register source (second
operand) to the 64-bit memory location (first operand).
Note: VMOVHPS (store) (VEX.NDS.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store.
For VMOVHPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVHPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L’L= 1 will cause an #UD exception.
4-80 Vol. 2B
MOVHPS—Move High Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
MOVHPS (128-bit Legacy SSE load)
DEST[63:0] (Unmodified)
DEST[127:64] SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)
VMOVHPS (VEX.128 and EVEX encoded load)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
DEST[MAX_VL-1:128] 0
VMOVHPS (store)
DEST[63:0] SRC[127:64]
Intel C/C++ Compiler Intrinsic Equivalent
MOVHPS __m128 _mm_loadh_pi ( __m128 a, __m64 *p)
MOVHPS void _mm_storeh_pi (__m64 *p, __m128 a)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD
If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.
MOVHPS—Move High Packed Single-Precision Floating-Point Values
Vol. 2B 4-81
INSTRUCTION SET REFERENCE, M-U
MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 16 /r
MOVLHPS xmm1, xmm2
VEX.NDS.128.0F.WIG 16 /r
VMOVLHPS xmm1, xmm2, xmm3
EVEX.NDS.128.0F.W0 16 /r
VMOVLHPS xmm1, xmm2, xmm3
RVM
V/V
AVX
RVM
V/V
AVX512F
Description
Move two packed single-precision floating-point values from
low quadword of xmm2 to high quadword of xmm1.
Merge two packed single-precision floating-point values
from low quadword of xmm3 and low quadword of xmm2.
Merge two packed single-precision floating-point values
from low quadword of xmm3 and low quadword of xmm2.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction cannot be used for memory to register moves.
128-bit two-argument form:
Moves two packed single-precision floating-point values from the low quadword of the second XMM argument
(second operand) to the high quadword of the first XMM register (first argument). The low quadword of the destination operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register are unmodified.
128-bit three-argument forms:
Moves two packed single-precision floating-point values from the low quadword of the third XMM argument (third
operand) to the high quadword of the destination (first operand). Copies the low quadword from the second XMM
argument (second operand) to the low quadword of the destination (first operand). Bits (MAX_VL-1:128) of the
corresponding destination register are zeroed.
If VMOVLHPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L’L= 1 will cause an #UD exception.
Operation
MOVLHPS (128-bit two-argument form)
DEST[63:0] (Unmodified)
DEST[127:64] SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)
VMOVLHPS (128-bit three-argument form - VEX & EVEX)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
MOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
None
1. ModRM.MOD = 011B required
4-82 Vol. 2B
MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7; additionally
#UD
If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E7NM.128.
MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High
Vol. 2B 4-83
INSTRUCTION SET REFERENCE, M-U
MOVLPD—Move Low Packed Double-Precision Floating-Point Value
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 12 /r
MOVLPD xmm1, m64
VEX.NDS.128.66.0F.WIG 12 /r
VMOVLPD xmm2, xmm1, m64
EVEX.NDS.128.66.0F.W1 12 /r
VMOVLPD xmm2, xmm1, m64
66 0F 13/r
MOVLPD m64, xmm1
VEX.128.66.0F.WIG 13/r
VMOVLPD m64, xmm1
EVEX.128.66.0F.W1 13/r
VMOVLPD m64, xmm1
RVM
V/V
AVX
T1S
V/V
AVX512F
MR
V/V
SSE2
MR
V/V
AVX
T1S-MR
V/V
AVX512F
Description
Move double-precision floating-point value from m64 to
low quadword of xmm1.
Merge double-precision floating-point value from m64
and the high quadword of xmm1.
Merge double-precision floating-point value from m64
and the high quadword of xmm1.
Move double-precision floating-point value from low
quadword of xmm1 to m64.
Move double-precision floating-point value from low
quadword of xmm1 to m64.
Move double-precision floating-point value from low
quadword of xmm1 to m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:r/m (r)
VEX.vvvv
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
T1S-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves a double-precision floating-point value from the source 64-bit memory operand and stores it in the low 64bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of
the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads a double-precision floating-point value from the source 64-bit memory operand (third operand), merges it
with the upper 64-bits of the first source XMM register (second operand), and stores it in the low 128-bits of the
destination XMM register (first operand). Bits (MAX_VL-1:128) of the corresponding destination register are
zeroed.
128-bit store:
Stores a double-precision floating-point value from the low 64-bits of the XMM register source (second operand) to
the 64-bit memory location (first operand).
Note: VMOVLPD (store) (VEX.128.66.0F 13 /r) is legal and has the same behavior as the existing 66 0F 13 store.
For VMOVLPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVLPD is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L’L= 1 will cause an #UD exception.
Operation
MOVLPD (128-bit Legacy SSE load)
DEST[63:0] SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
VMOVLPD (VEX.128 & EVEX encoded load)
4-84 Vol. 2B
MOVLPD—Move Low Packed Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
DEST[63:0] SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VMOVLPD (store)
DEST[63:0] SRC[63:0]
Intel C/C++ Compiler Intrinsic Equivalent
MOVLPD __m128d _mm_loadl_pd ( __m128d a, double *p)
MOVLPD void _mm_storel_pd (double *p, __m128d a)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD
If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.
MOVLPD—Move Low Packed Double-Precision Floating-Point Value
Vol. 2B 4-85
INSTRUCTION SET REFERENCE, M-U
MOVLPS—Move Low Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 12 /r
MOVLPS xmm1, m64
VEX.NDS.128.0F.WIG 12 /r
VMOVLPS xmm2, xmm1, m64
EVEX.NDS.128.0F.W0 12 /r
VMOVLPS xmm2, xmm1, m64
0F 13/r
MOVLPS m64, xmm1
VEX.128.0F.WIG 13/r
VMOVLPS m64, xmm1
EVEX.128.0F.W0 13/r
VMOVLPS m64, xmm1
RVM
V/V
AVX
T2
V/V
AVX512F
MR
V/V
SSE
MR
V/V
AVX
T2-MR
V/V
AVX512F
Description
Move two packed single-precision floating-point values
from m64 to low quadword of xmm1.
Merge two packed single-precision floating-point values
from m64 and the high quadword of xmm1.
Merge two packed single-precision floating-point values
from m64 and the high quadword of xmm1.
Move two packed single-precision floating-point values
from low quadword of xmm1 to m64.
Move two packed single-precision floating-point values
from low quadword of xmm1 to m64.
Move two packed single-precision floating-point values
from low quadword of xmm1 to m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
T2
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
T2-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves two packed single-precision floating-point values from the source 64-bit memory operand and stores them
in the low 64-bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits
(MAX_VL-1:128) of the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads two packed single-precision floating-point values from the source 64-bit memory operand (the third
operand), merges them with the upper 64-bits of the first source operand (the second operand), and stores them
in the low 128-bits of the destination register (the first operand). Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
128-bit store:
Loads two packed single-precision floating-point values from the low 64-bits of the XMM register source (second
operand) to the 64-bit memory location (first operand).
Note: VMOVLPS (store) (VEX.128.0F 13 /r) is legal and has the same behavior as the existing 0F 13 store. For
VMOVLPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L’L= 1 will cause an #UD exception.
4-86 Vol. 2B
MOVLPS—Move Low Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
MOVLPS (128-bit Legacy SSE load)
DEST[63:0] SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
VMOVLPS (VEX.128 & EVEX encoded load)
DEST[63:0] SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VMOVLPS (store)
DEST[63:0] SRC[63:0]
Intel C/C++ Compiler Intrinsic Equivalent
MOVLPS __m128 _mm_loadl_pi ( __m128 a, __m64 *p)
MOVLPS void _mm_storel_pi (__m64 *p, __m128 a)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD
If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.
MOVLPS—Move Low Packed Single-Precision Floating-Point Values
Vol. 2B 4-87
INSTRUCTION SET REFERENCE, M-U
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 50 /r
RM
V/V
SSE2
Extract 2-bit sign mask from xmm and store in reg. The
upper bits of r32 or r64 are filled with zeros.
RM
V/V
AVX
Extract 2-bit sign mask from xmm2 and store in reg.
The upper bits of r32 or r64 are zeroed.
RM
V/V
AVX
Extract 4-bit sign mask from ymm2 and store in reg.
The upper bits of r32 or r64 are zeroed.
MOVMSKPD reg, xmm
VEX.128.66.0F.WIG 50 /r
VMOVMSKPD reg, xmm2
VEX.256.66.0F.WIG 50 /r
VMOVMSKPD reg, ymm2
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Extracts the sign bits from the packed double-precision floating-point values in the source operand (second
operand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The
source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored
in the 2 low-order bits of the destination operand. Zero-extend the upper bits of the destination.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R
prefix. The default operand size is 64-bit in 64-bit mode.
128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.
VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose
register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
(V)MOVMSKPD (128-bit versions)
DEST[0] SRC[63]
DEST[1] SRC[127]
IF DEST = r32
THEN DEST[31:2] 0;
ELSE DEST[63:2] 0;
FI
VMOVMSKPD (VEX.256 encoded version)
DEST[0] SRC[63]
DEST[1] SRC[127]
DEST[2] SRC[191]
DEST[3] SRC[255]
IF DEST = r32
THEN DEST[31:4] 0;
ELSE DEST[63:4] 0;
FI
4-88 Vol. 2B
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
MOVMSKPD:
int _mm_movemask_pd ( __m128d a)
VMOVMSKPD:
_mm256_movemask_pd(__m256d a)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 7; additionally
#UD
If VEX.vvvv ≠ 1111B.
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask
Vol. 2B 4-89
INSTRUCTION SET REFERENCE, M-U
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
0F 50 /r
RM
V/V
SSE
Extract 4-bit sign mask from xmm and store in reg.
The upper bits of r32 or r64 are filled with zeros.
RM
V/V
AVX
Extract 4-bit sign mask from xmm2 and store in reg.
The upper bits of r32 or r64 are zeroed.
RM
V/V
AVX
Extract 8-bit sign mask from ymm2 and store in reg.
The upper bits of r32 or r64 are zeroed.
MOVMSKPS reg, xmm
VEX.128.0F.WIG 50 /r
VMOVMSKPS reg, xmm2
VEX.256.0F.WIG 50 /r
VMOVMSKPS reg, ymm2
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Extracts the sign bits from the packed single-precision floating-point values in the source operand (second
operand), formats them into a 4- or 8-bit mask, and stores the mask in the destination operand (first operand).
The source operand is an XMM or YMM register, and the destination operand is a general-purpose register. The
mask is stored in the 4 or 8 low-order bits of the destination operand. The upper bits of the destination operand
beyond the mask are filled with zeros.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R
prefix. The default operand size is 64-bit in 64-bit mode.
128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.
VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose
register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
DEST[0] ← SRC[31];
DEST[1] ← SRC[63];
DEST[2] ← SRC[95];
DEST[3] ← SRC[127];
IF DEST = r32
THEN DEST[31:4] ← ZeroExtend;
ELSE DEST[63:4] ← ZeroExtend;
FI;
1. ModRM.MOD = 011B required
4-90 Vol. 2B
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask
INSTRUCTION SET REFERENCE, M-U
(V)MOVMSKPS (128-bit version)
DEST[0] SRC[31]
DEST[1] SRC[63]
DEST[2] SRC[95]
DEST[3] SRC[127]
IF DEST = r32
THEN DEST[31:4] 0;
ELSE DEST[63:4] 0;
FI
VMOVMSKPS (VEX.256 encoded version)
DEST[0] SRC[31]
DEST[1] SRC[63]
DEST[2] SRC[95]
DEST[3] SRC[127]
DEST[4] SRC[159]
DEST[5] SRC[191]
DEST[6] SRC[223]
DEST[7] SRC[255]
IF DEST = r32
THEN DEST[31:8] 0;
ELSE DEST[63:8] 0;
FI
Intel C/C++ Compiler Intrinsic Equivalent
int _mm_movemask_ps(__m128 a)
int _mm256_movemask_ps(__m256 a)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 7; additionally
#UD
If VEX.vvvv ≠ 1111B.
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask
Vol. 2B 4-91
INSTRUCTION SET REFERENCE, M-U
MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint
Opcode/
Instruction
Op /
En
CPUID
Feature Flag
Description
RM
64/32
bit Mode
Support
V/V
66 0F 38 2A /r
MOVNTDQA xmm1, m128
VEX.128.66.0F38.WIG 2A /r
VMOVNTDQA xmm1, m128
VEX.256.66.0F38.WIG 2A /r
VMOVNTDQA ymm1, m256
EVEX.128.66.0F38.W0 2A /r
VMOVNTDQA xmm1, m128
EVEX.256.66.0F38.W0 2A /r
VMOVNTDQA ymm1, m256
EVEX.512.66.0F38.W0 2A /r
VMOVNTDQA zmm1, m512
SSE4_1
RM
V/V
AVX
RM
V/V
AVX2
FVM
V/V
FVM
V/V
FVM
V/V
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Move double quadword from m128 to xmm1 using nontemporal hint if WC memory type.
Move double quadword from m128 to xmm using nontemporal hint if WC memory type.
Move 256-bit data from m256 to ymm using non-temporal
hint if WC memory type.
Move 128-bit data from m128 to xmm using non-temporal
hint if WC memory type.
Move 256-bit data from m256 to ymm using non-temporal
hint if WC memory type.
Move 512-bit data from m512 to zmm using non-temporal
hint if WC memory type.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
MOVNTDQA loads a double quadword from the source operand (second operand) to the destination operand (first
operand) using a non-temporal hint if the memory source is WC (write combining) memory type. For WC memory
type, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an
aligned cache line without filling this data to the cache. Any memory-type aliased lines in the cache will be snooped
and flushed. Subsequent MOVNTDQA reads to unread portions of the WC cache line will receive data from the
temporary internal buffer if data is available. The temporary internal buffer may be flushed by the processor at any
time for any reason, for example:
• A load operation other than a MOVNTDQA which references memory already resident in a temporary internal
buffer.
• A non-WC reference to memory already resident in a temporary internal buffer.
• Interleaving of reads and writes to a single temporary internal buffer.
• Repeated (V)MOVNTDQA loads of a particular 16-byte item in a streaming line.
• Certain micro-architectural conditions including resource shortages, detection of
a mis-speculation condition, and various fault conditions
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when reading the
data from memory. Using this protocol, the processor
does not read the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into
the cache hierarchy. The memory type of the region being read can override the non-temporal hint, if the memory
address specified for the non-temporal read is not a WC memory region. Information on non-temporal reads and
writes can be found in “Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the Intel® 64 and IA-32
Architecture Software Developer’s Manual, Volume 3A.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
a MFENCE instruction should be used in conjunction with MOVNTDQA instructions if multiple processors might use
different memory types for the referenced memory locations or to synchronize reads of a processor with writes by
other agents in the system. A processor’s implementation of the streaming load hint does not override the effective
memory type, but the implementation of the hint is processor dependent. For example, a processor implementa1. ModRM.MOD = 011B required
4-92 Vol. 2B
MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint
INSTRUCTION SET REFERENCE, M-U
tion may choose to ignore the hint and process the instruction as a normal MOVDQA for any memory type. Alternatively, another implementation may optimize cache reads generated by MOVNTDQA on WB memory type to
reduce cache evictions.
The 128-bit (V)MOVNTDQA addresses must be 16-byte aligned or the instruction will cause a #GP.
The 256-bit VMOVNTDQA addresses must be 32-byte aligned or the instruction will cause a #GP.
The 512-bit VMOVNTDQA addresses must be 64-byte aligned or the instruction will cause a #GP.
Operation
MOVNTDQA (128bit- Legacy SSE form)
DEST SRC
DEST[MAX_VL-1:128] (Unmodified)
VMOVNTDQA (VEX.128 and EVEX.128 encoded form)
DEST SRC
DEST[MAX_VL-1:128] 0
VMOVNTDQA (VEX.256 and EVEX.256 encoded forms)
DEST[255:0] SRC[255:0]
DEST[MAX_VL-1:256] 0
VMOVNTDQA (EVEX.512 encoded form)
DEST[511:0] SRC[511:0]
Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTDQA __m512i _mm512_stream_load_si512(void * p);
MOVNTDQA __m128i _mm_stream_load_si128 (__m128i *p);
VMOVNTDQA __m256i _mm_stream_load_si256 (__m256i *p);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1;
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint
Vol. 2B 4-93
INSTRUCTION SET REFERENCE, M-U
MOVNTDQ—Store Packed Integers Using Non-Temporal Hint
Opcode/
Instruction
Op /
En
CPUID
Feature Flag
Description
MR
64/32
bit Mode
Support
V/V
66 0F E7 /r
MOVNTDQ m128, xmm1
VEX.128.66.0F.WIG E7 /r
VMOVNTDQ m128, xmm1
VEX.256.66.0F.WIG E7 /r
VMOVNTDQ m256, ymm1
EVEX.128.66.0F.W0 E7 /r
VMOVNTDQ m128, xmm1
EVEX.256.66.0F.W0 E7 /r
VMOVNTDQ m256, ymm1
EVEX.512.66.0F.W0 E7 /r
VMOVNTDQ m512, zmm1
SSE2
MR
V/V
AVX
MR
V/V
AVX
FVM
V/V
FVM
V/V
FVM
V/V
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Move packed integer values in xmm1 to m128 using nontemporal hint.
Move packed integer values in xmm1 to m128 using nontemporal hint.
Move packed integer values in ymm1 to m256 using nontemporal hint.
Move packed integer values in xmm1 to m128 using nontemporal hint.
Move packed integer values in zmm1 to m256 using nontemporal hint.
Move packed integer values in zmm1 to m512 using nontemporal hint.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Moves the packed integers in the source operand (second operand) to the destination operand (first operand) using
a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM
register, YMM register or ZMM register, which is assumed to contain integer data (packed bytes, words, doublewords, or quadwords). The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory
operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (512-bit
version) boundary otherwise a general-protection exception (#GP) will be generated.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s
Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with VMOVNTDQ instructions if multiple processors might use different memory types to read/write the destination memory locations.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will
#UD.
Operation
VMOVNTDQ(EVEX encoded versions)
VL = 128, 256, 512
DEST[VL-1:0] SRC[VL-1:0]
DEST[MAX_VL-1:VL] 0
1. ModRM.MOD = 011B required
4-94 Vol. 2B
MOVNTDQ—Store Packed Integers Using Non-Temporal Hint
INSTRUCTION SET REFERENCE, M-U
MOVNTDQ (Legacy and VEX versions)
DEST SRC
Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTDQ void _mm512_stream_si512(void * p, __m512i a);
VMOVNTDQ void _mm256_stream_si256 (__m256i * p, __m256i a);
MOVNTDQ void _mm_stream_si128 (__m128i * p, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
MOVNTDQ—Store Packed Integers Using Non-Temporal Hint
Vol. 2B 4-95
INSTRUCTION SET REFERENCE, M-U
MOVNTI—Store Doubleword Using Non-Temporal Hint
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F C3 /r
MOVNTI m32, r32
MR
Valid
Valid
Move doubleword from r32 to m32 using nontemporal hint.
REX.W + 0F C3 /r
MOVNTI m64, r64
MR
Valid
N.E.
Move quadword from r64 to m64 using nontemporal hint.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Moves the doubleword integer in the source operand (second operand) to the destination operand (first operand)
using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is a
general-purpose register. The destination operand is a 32-bit memory location.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTI instructions if multiple processors
might use different memory types to read/write the destination memory locations.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
DEST ← SRC;
Intel C/C++ Compiler Intrinsic Equivalent
MOVNTI:
void _mm_stream_si32 (int *p, int a)
MOVNTI:
void _mm_stream_si64(__int64 *p, __int64 a)
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#UD
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
4-96 Vol. 2B
MOVNTI—Store Doubleword Using Non-Temporal Hint
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#GP
#UD
If any part of the operand lies outside the effective address space from 0 to FFFFH.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#UD
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
MOVNTI—Store Doubleword Using Non-Temporal Hint
Vol. 2B 4-97
INSTRUCTION SET REFERENCE, M-U
MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
Opcode/
Instruction
Op /
En
MR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 2B /r
MOVNTPD m128, xmm1
VEX.128.66.0F.WIG 2B /r
VMOVNTPD m128, xmm1
VEX.256.66.0F.WIG 2B /r
VMOVNTPD m256, ymm1
EVEX.128.66.0F.W1 2B /r
VMOVNTPD m128, xmm1
EVEX.256.66.0F.W1 2B /r
VMOVNTPD m256, ymm1
EVEX.512.66.0F.W1 2B /r
VMOVNTPD m512, zmm1
MR
V/V
AVX
MR
V/V
AVX
FVM
V/V
FVM
V/V
FVM
V/V
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Move packed double-precision values in xmm1 to m128 using
non-temporal hint.
Move packed double-precision values in xmm1 to m128 using
non-temporal hint.
Move packed double-precision values in ymm1 to m256 using
non-temporal hint.
Move packed double-precision values in xmm1 to m128 using
non-temporal hint.
Move packed double-precision values in ymm1 to m256 using
non-temporal hint.
Move packed double-precision values in zmm1 to m512 using
non-temporal hint.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Moves the packed double-precision floating-point values in the source operand (second operand) to the destination
operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The
source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed doubleprecision, floating-pointing data. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The
memory operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte
(EVEX.512 encoded version) boundary otherwise a general-protection exception (#GP) will be generated.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s
Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors
might use different memory types to read/write the destination memory locations.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will
#UD.
Operation
VMOVNTPD (EVEX encoded versions)
VL = 128, 256, 512
DEST[VL-1:0] SRC[VL-1:0]
DEST[MAX_VL-1:VL] 0
1. ModRM.MOD = 011B required
4-98 Vol. 2B
MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
INSTRUCTION SET REFERENCE, M-U
MOVNTPD (Legacy and VEX versions)
DEST SRC
Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTPD void _mm512_stream_pd(double * p, __m512d a);
VMOVNTPD void _mm256_stream_pd (double * p, __m256d a);
MOVNTPD void _mm_stream_pd (double * p, __m128d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
Vol. 2B 4-99
INSTRUCTION SET REFERENCE, M-U
MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
Opcode/
Instruction
Op /
En
MR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 2B /r
MOVNTPS m128, xmm1
VEX.128.0F.WIG 2B /r
VMOVNTPS m128, xmm1
VEX.256.0F.WIG 2B /r
VMOVNTPS m256, ymm1
EVEX.128.0F.W0 2B /r
VMOVNTPS m128, xmm1
EVEX.256.0F.W0 2B /r
VMOVNTPS m256, ymm1
EVEX.512.0F.W0 2B /r
VMOVNTPS m512, zmm1
MR
V/V
AVX
MR
V/V
AVX
FVM
V/V
FVM
V/V
FVM
V/V
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Move packed single-precision values xmm1 to mem using
non-temporal hint.
Move packed single-precision values xmm1 to mem using
non-temporal hint.
Move packed single-precision values ymm1 to mem using
non-temporal hint.
Move packed single-precision values in xmm1 to m128
using non-temporal hint.
Move packed single-precision values in ymm1 to m256
using non-temporal hint.
Move packed single-precision values in zmm1 to m512
using non-temporal hint.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Moves the packed single-precision floating-point values in the source operand (second operand) to the destination
operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The
source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed single-precision, floating-pointing. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory
operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512
encoded version) boundary otherwise a general-protection exception (#GP) will be generated.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s
Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPS instructions if multiple processors
might use different memory types to read/write the destination memory locations.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
Operation
VMOVNTPS (EVEX encoded versions)
VL = 128, 256, 512
DEST[VL-1:0] SRC[VL-1:0]
DEST[MAX_VL-1:VL] 0
1. ModRM.MOD = 011B required
4-100 Vol. 2B
MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
INSTRUCTION SET REFERENCE, M-U
MOVNTPS
DEST SRC
Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTPS void _mm512_stream_ps(float * p, __m512d a);
MOVNTPS void _mm_stream_ps (float * p, __m128d a);
VMOVNTPS void _mm256_stream_ps (float * p, __m256 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE; additionally
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
Vol. 2B 4-101
INSTRUCTION SET REFERENCE, M-U
MOVNTQ—Store of Quadword Using Non-Temporal Hint
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F E7 /r
MOVNTQ m64, mm
MR
Valid
Valid
Move quadword from mm to m64 using nontemporal hint.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Moves the quadword in the source operand (second operand) to the destination operand (first operand) using a
non-temporal hint to minimize cache pollution during the write to memory. The source operand is an MMX technology register, which is assumed to contain packed integer data (packed bytes, words, or doublewords). The
destination operand is a 64-bit memory location.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTQ instructions if multiple processors
might use different memory types to read/write the destination memory locations.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
DEST ← SRC;
Intel C/C++ Compiler Intrinsic Equivalent
MOVNTQ:
void _mm_stream_pi(__m64 * p, __m64 a)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 22-8, “Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3A.
4-102 Vol. 2B
MOVNTQ—Store of Quadword Using Non-Temporal Hint
INSTRUCTION SET REFERENCE, M-U
MOVQ—Move Quadword
Opcode/
Instruction
Op/ En
64/32-bit CPUID
Mode
Feature
Flag
Description
0F 6F /r
RM
V/V
MMX
Move quadword from mm/m64 to mm.
MR
V/V
MMX
Move quadword from mm to mm/m64.
RM
V/V
SSE2
Move quadword from xmm2/mem64 to xmm1.
RM
V/V
AVX
Move quadword from xmm2 to xmm1.
MOVQ mm, mm/m64
0F 7F /r
MOVQ mm/m64, mm
F3 0F 7E /r
MOVQ xmm1, xmm2/m64
VEX.128.F3.0F.WIG 7E /r
VMOVQ xmm1, xmm2/m64
EVEX.128.F3.0F.W1 7E /r
VMOVQ xmm1, xmm2/m64
T1S-RM V/V
AVX512F
Move quadword from xmm2/m64 to xmm1.
66 0F D6 /r
MR
V/V
SSE2
Move quadword from xmm1 to xmm2/mem64.
MR
V/V
AVX
Move quadword from xmm2 register to xmm1/m64.
AVX512F
Move quadword from xmm2 register to xmm1/m64.
MOVQ xmm2/m64, xmm1
VEX.128.66.0F.WIG D6 /r
VMOVQ xmm1/m64, xmm2
EVEX.128.66.0F.W1 D6 /r
VMOVQ xmm1/m64, xmm2
T1S-MR V/V
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
T1S-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1S-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Copies a quadword from the source operand (second operand) to the destination operand (first operand). The
source and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations.
This instruction can be used to move a quadword between two MMX technology registers or between an MMX technology register and a 64-bit memory location, or to move data between two XMM registers or between an XMM
register and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.
When the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM
register, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.
In 64-bit mode and if not encoded using VEX/EVEX, use of the REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
If VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an
#UD exception.
MOVQ—Move Quadword
Vol. 2B 4-103
INSTRUCTION SET REFERENCE, M-U
Operation
MOVQ instruction when operating on MMX technology registers and memory locations:
DEST ← SRC;
MOVQ instruction when source and destination operands are XMM registers:
DEST[63:0] ← SRC[63:0];
DEST[127:64] ← 0000000000000000H;
MOVQ instruction when source operand is XMM register and destination
operand is memory location:
DEST ← SRC[63:0];
MOVQ instruction when source operand is memory location and destination
operand is XMM register:
DEST[63:0] ← SRC;
DEST[127:64] ← 0000000000000000H;
VMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination:
DEST[63:0] ← SRC[63:0]
DEST[VLMAX-1:64] ← 0
VMOVQ (VEX.128.66.0F D6) with XMM register source and destination:
DEST[63:0] ← SRC[63:0]
DEST[VLMAX-1:64] ← 0
VMOVQ (7E - EVEX encoded version) with XMM register source and destination:
DEST[63:0] SRC[63:0]
DEST[MAX_VL-1:64] 0
VMOVQ (D6 - EVEX encoded version) with XMM register source and destination:
DEST[63:0] SRC[63:0]
DEST[MAX_VL-1:64] 0
VMOVQ (7E) with memory source:
DEST[63:0] ← SRC[63:0]
DEST[VLMAX-1:64] ← 0
VMOVQ (7E - EVEX encoded version) with memory source:
DEST[63:0] SRC[63:0]
DEST[:MAX_VL-1:64] 0
VMOVQ (D6) with memory dest:
DEST[63:0] ← SRC2[63:0]
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
VMOVQ __m128i _mm_loadu_si64( void * s);
VMOVQ void _mm_storeu_si64( void * d, __m128i s);
MOVQ
4-104 Vol. 2B
m128i _mm_mov_epi64(__m128i a)
MOVQ—Move Quadword
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 22-8, “Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3B.
MOVQ—Move Quadword
Vol. 2B 4-105
INSTRUCTION SET REFERENCE, M-U
MOVQ2DQ—Move Quadword from MMX Technology to XMM Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F3 0F D6 /r
MOVQ2DQ xmm, mm
RM
Valid
Valid
Move quadword from mmx to low quadword
of xmm.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Moves the quadword from the source operand (second operand) to the low quadword of the destination operand
(first operand). The source operand is an MMX technology register and the destination operand is an XMM register.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[63:0] ← SRC[63:0];
DEST[127:64] ← 00000000000000000H;
Intel C/C++ Compiler Intrinsic Equivalent
MOVQ2DQ:
__128i _mm_movpi64_pi64 ( __m64 a)
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#NM
#UD
If CR0.TS[bit 3] = 1.
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
#MF
If there is a pending x87 FPU exception.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-106 Vol. 2B
MOVQ2DQ—Move Quadword from MMX Technology to XMM Register
INSTRUCTION SET REFERENCE, M-U
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String
\
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
A4
MOVS m8, m8
NP
Valid
Valid
For legacy mode, Move byte from address
DS:(E)SI to ES:(E)DI. For 64-bit mode move
byte from address (R|E)SI to (R|E)DI.
A5
MOVS m16, m16
NP
Valid
Valid
For legacy mode, move word from address
DS:(E)SI to ES:(E)DI. For 64-bit mode move
word at address (R|E)SI to (R|E)DI.
A5
MOVS m32, m32
NP
Valid
Valid
For legacy mode, move dword from address
DS:(E)SI to ES:(E)DI. For 64-bit mode move
dword from address (R|E)SI to (R|E)DI.
REX.W + A5
MOVS m64, m64
NP
Valid
N.E.
Move qword from address (R|E)SI to (R|E)DI.
A4
MOVSB
NP
Valid
Valid
For legacy mode, Move byte from address
DS:(E)SI to ES:(E)DI. For 64-bit mode move
byte from address (R|E)SI to (R|E)DI.
A5
MOVSW
NP
Valid
Valid
For legacy mode, move word from address
DS:(E)SI to ES:(E)DI. For 64-bit mode move
word at address (R|E)SI to (R|E)DI.
A5
MOVSD
NP
Valid
Valid
For legacy mode, move dword from address
DS:(E)SI to ES:(E)DI. For 64-bit mode move
dword from address (R|E)SI to (R|E)DI.
REX.W + A5
MOVSQ
NP
Valid
N.E.
Move qword from address (R|E)SI to (R|E)DI.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Moves the byte, word, or doubleword specified with the second operand (source operand) to the location specified
with the first operand (destination operand). Both the source and destination operands are located in memory. The
address of the source operand is read from the DS:ESI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The address of the destination operand is read from the ES:EDI or
the ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be
overridden with a segment override prefix, but the ES segment cannot be overridden.
At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands” form and the “nooperands” form. The explicit-operands form (specified with the MOVS mnemonic) allows the source and destination
operands to be specified explicitly. Here, the source and destination operands should be symbols that indicate the
size and location of the source value and the destination, respectively. This explicit-operands form is provided to
allow documentation; however, note that the documentation provided by this form can be misleading. That is, the
source and destination operand symbols must specify the correct type (size) of the operands (bytes, words, or
doublewords), but they do not have to specify the correct location. The locations of the source and destination
operands are always specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the
move string instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the MOVS instructions. Here also DS:(E)SI and ES:(E)DI are assumed to be the source and destination operands, respectively. The
size of the source and destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW (word
move), or MOVSD (doubleword move).
After the move operation, the (E)SI and (E)DI registers are incremented or decremented automatically according
to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI and (E)DI register are incre-
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String
Vol. 2B 4-107
INSTRUCTION SET REFERENCE, M-U
mented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or
decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.
NOTE
To improve performance, more recent processors support modifications to the processor’s
operation during the string store operations initiated with MOVS and MOVSB. See Section 7.3.9.3
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for additional
information on fast-string operation.
The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix (see “REP/REPE/REPZ
/REPNE/REPNZ—Repeat String Operation Prefix” for a description of the REP prefix) for block moves of ECX bytes,
words, or doublewords.
In 64-bit mode, the instruction’s default address size is 64 bits, 32-bit address size is supported using the prefix
67H. The 64-bit addresses are specified by RSI and RDI; 32-bit address are specified by ESI and EDI. Use of the
REX.W prefix promotes doubleword operation to 64 bits. See the summary chart at the beginning of this section for
encoding data and limits.
Operation
DEST ← SRC;
Non-64-bit Mode:
IF (Byte move)
THEN IF DF = 0
THEN
(E)SI ← (E)SI + 1;
(E)DI ← (E)DI + 1;
ELSE
(E)SI ← (E)SI – 1;
(E)DI ← (E)DI – 1;
FI;
ELSE IF (Word move)
THEN IF DF = 0
(E)SI ← (E)SI + 2;
(E)DI ← (E)DI + 2;
FI;
ELSE
(E)SI ← (E)SI – 2;
(E)DI ← (E)DI – 2;
FI;
ELSE IF (Doubleword move)
THEN IF DF = 0
(E)SI ← (E)SI + 4;
(E)DI ← (E)DI + 4;
FI;
ELSE
(E)SI ← (E)SI – 4;
(E)DI ← (E)DI – 4;
FI;
FI;
64-bit Mode:
IF (Byte move)
THEN IF DF = 0
THEN
4-108 Vol. 2B
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String
INSTRUCTION SET REFERENCE, M-U
(R|E)SI ← (R|E)SI + 1;
(R|E)DI ← (R|E)DI + 1;
ELSE
(R|E)SI ← (R|E)SI – 1;
(R|E)DI ← (R|E)DI – 1;
FI;
ELSE IF (Word move)
THEN IF DF = 0
(R|E)SI ← (R|E)SI + 2;
(R|E)DI ← (R|E)DI + 2;
FI;
ELSE
(R|E)SI ← (R|E)SI – 2;
(R|E)DI ← (R|E)DI – 2;
FI;
ELSE IF (Doubleword move)
THEN IF DF = 0
(R|E)SI ← (R|E)SI + 4;
(R|E)DI ← (R|E)DI + 4;
FI;
ELSE
(R|E)SI ← (R|E)SI – 4;
(R|E)DI ← (R|E)DI – 4;
FI;
ELSE IF (Quadword move)
THEN IF DF = 0
(R|E)SI ← (R|E)SI + 8;
(R|E)DI ← (R|E)DI + 8;
FI;
ELSE
(R|E)SI ← (R|E)SI – 8;
(R|E)DI ← (R|E)DI – 8;
FI;
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String
Vol. 2B 4-109
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
4-110 Vol. 2B
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String
INSTRUCTION SET REFERENCE, M-U
MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op / En
F2 0F 10 /r
MOVSD xmm1, xmm2
F2 0F 10 /r
MOVSD xmm1, m64
F2 0F 11 /r
MOVSD xmm1/m64, xmm2
VEX.NDS.LIG.F2.0F.WIG 10 /r
VMOVSD xmm1, xmm2, xmm3
VEX.LIG.F2.0F.WIG 10 /r
VMOVSD xmm1, m64
VEX.NDS.LIG.F2.0F.WIG 11 /r
VMOVSD xmm1, xmm2, xmm3
VEX.LIG.F2.0F.WIG 11 /r
VMOVSD m64, xmm1
EVEX.NDS.LIG.F2.0F.W1 10 /r
VMOVSD xmm1 {k1}{z}, xmm2, xmm3
EVEX.LIG.F2.0F.W1 10 /r
VMOVSD xmm1 {k1}{z}, m64
EVEX.NDS.LIG.F2.0F.W1 11 /r
VMOVSD xmm1 {k1}{z}, xmm2, xmm3
EVEX.LIG.F2.0F.W1 11 /r
VMOVSD m64 {k1}, xmm1
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
RM
V/V
SSE2
MR
V/V
SSE2
RVM
V/V
AVX
XM
V/V
AVX
MVR
V/V
AVX
MR
V/V
AVX
RVM
V/V
AVX512F
T1S-RM
V/V
AVX512F
MVR
V/V
AVX512F
T1S-MR
V/V
AVX512F
Description
Move scalar double-precision floating-point value
from xmm2 to xmm1 register.
Load scalar double-precision floating-point value
from m64 to xmm1 register.
Move scalar double-precision floating-point value
from xmm2 register to xmm1/m64.
Merge scalar double-precision floating-point value
from xmm2 and xmm3 to xmm1 register.
Load scalar double-precision floating-point value
from m64 to xmm1 register.
Merge scalar double-precision floating-point value
from xmm2 and xmm3 registers to xmm1.
Store scalar double-precision floating-point value
from xmm1 register to m64.
Merge scalar double-precision floating-point value
from xmm2 and xmm3 registers to xmm1 under
writemask k1.
Load scalar double-precision floating-point value
from m64 to xmm1 register under writemask k1.
Merge scalar double-precision floating-point value
from xmm2 and xmm3 registers to xmm1 under
writemask k1.
Store scalar double-precision floating-point value
from xmm1 register to m64 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
XM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MVR
ModRM:r/m (w)
vvvv (r)
ModRM:reg (r)
NA
T1S-RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
T1S-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value
Vol. 2B 4-111
INSTRUCTION SET REFERENCE, M-U
Description
Moves a scalar double-precision floating-point value from the source operand (second operand) to the destination
operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations.
This instruction can be used to move a double-precision floating-point value to and from the low quadword of an
XMM register and a 64-bit memory location, or to move a double-precision floating-point value between the low
quadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations.
Legacy version: When the source and destination operands are XMM registers, bits MAX_VL:64 of the destination
operand remains unchanged. When the source operand is a memory location and destination operand is an XMM
registers, the quadword at bits 127:64 of the destination operand is cleared to all 0s, bits MAX_VL:128 of the destination operand remains unchanged.
VEX and EVEX encoded register-register syntax: Moves a scalar double-precision floating-point value from the
second source operand (the third operand) to the low quadword element of the destination operand (the first
operand). Bits 127:64 of the destination operand are copied from the first source operand (the second operand).
Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX and EVEX encoded memory store syntax: When the source operand is a memory location and destination
operand is an XMM registers, bits MAX_VL:64 of the destination operand is cleared to all 0s.
EVEX encoded versions: The low quadword of the destination is updated according to the writemask.
Note: For VMOVSD (memory store and load forms), VEX.vvvv and EVEX.vvvv are reserved and must be 1111b,
otherwise instruction will #UD.
Operation
VMOVSD (EVEX.NDS.LIG.F2.0F 10 /r: VMOVSD xmm1, m64 with support for 32 registers)
IF k1[0] or *no writemask*
THEN
DEST[63:0] SRC[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[511:64] 0
VMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD m64, xmm1 with support for 32 registers)
IF k1[0] or *no writemask*
THEN
DEST[63:0] SRC[63:0]
ELSE
*DEST[63:0] remains unchanged*
; merging-masking
FI;
VMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)
IF k1[0] or *no writemask*
THEN
DEST[63:0] SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
4-112 Vol. 2B
MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
MOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)
DEST[63:0] SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
VMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)
DEST[63:0] SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)
DEST[63:0] SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)
DEST[63:0] SRC[63:0]
DEST[MAX_VL-1:64] 0
MOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)
DEST[63:0] SRC[63:0]
MOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)
DEST[63:0] SRC[63:0]
DEST[127:64] 0
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMOVSD __m128d _mm_mask_load_sd(__m128d s, __mmask8 k, double * p);
VMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p);
VMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a);
VMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a);
VMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s);
MOVSD __m128d _mm_load_sd (double *p)
MOVSD void _mm_store_sd (double *p, __m128d a)
MOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E10.
MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value
Vol. 2B 4-113
INSTRUCTION SET REFERENCE, M-U
MOVSHDUP—Replicate Single FP Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE3
F3 0F 16 /r
MOVSHDUP xmm1, xmm2/m128
VEX.128.F3.0F.WIG 16 /r
VMOVSHDUP xmm1, xmm2/m128
VEX.256.F3.0F.WIG 16 /r
VMOVSHDUP ymm1, ymm2/m256
EVEX.128.F3.0F.W0 16 /r
VMOVSHDUP xmm1 {k1}{z},
xmm2/m128
EVEX.256.F3.0F.W0 16 /r
VMOVSHDUP ymm1 {k1}{z},
ymm2/m256
EVEX.512.F3.0F.W0 16 /r
VMOVSHDUP zmm1 {k1}{z},
zmm2/m512
RM
V/V
AVX
RM
V/V
AVX
FVM
V/V
AVX512VL
AVX512F
FVM
V/V
AVX512VL
AVX512F
FVM
V/V
AVX512F
Description
Move odd index single-precision floating-point values from
xmm2/mem and duplicate each element into xmm1.
Move odd index single-precision floating-point values from
xmm2/mem and duplicate each element into xmm1.
Move odd index single-precision floating-point values from
ymm2/mem and duplicate each element into ymm1.
Move odd index single-precision floating-point values from
xmm2/m128 and duplicate each element into xmm1 under
writemask.
Move odd index single-precision floating-point values from
ymm2/m256 and duplicate each element into ymm1 under
writemask.
Move odd index single-precision floating-point values from
zmm2/m512 and duplicate each element into zmm1 under
writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Duplicates odd-indexed single-precision floating-point values from the source operand (the second operand) to
adjacent element pair in the destination operand (the first operand). See Figure 4-3. The source operand is an
XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the destination operand is an XMM, YMM
or ZMM register.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.
VEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.
EVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
SRC
X7
X6
X5
X4
X3
X2
X1
X0
DEST
X7
X7
X5
X5
X3
X3
X1
X1
Figure 4-3. MOVSHDUP Operation
Operation
VMOVSHDUP (EVEX encoded versions)
4-114 Vol. 2B
MOVSHDUP—Replicate Single FP Values
INSTRUCTION SET REFERENCE, M-U
(KL, VL) = (4, 128), (8, 256), (16, 512)
TMP_SRC[31:0] SRC[63:32]
TMP_SRC[63:32] SRC[63:32]
TMP_SRC[95:64] SRC[127:96]
TMP_SRC[127:96] SRC[127:96]
IF VL >= 256
TMP_SRC[159:128] SRC[191:160]
TMP_SRC[191:160] SRC[191:160]
TMP_SRC[223:192] SRC[255:224]
TMP_SRC[255:224] SRC[255:224]
FI;
IF VL >= 512
TMP_SRC[287:256] SRC[319:288]
TMP_SRC[319:288] SRC[319:288]
TMP_SRC[351:320] SRC[383:352]
TMP_SRC[383:352] SRC[383:352]
TMP_SRC[415:384] SRC[447:416]
TMP_SRC[447:416] SRC[447:416]
TMP_SRC[479:448] SRC[511:480]
TMP_SRC[511:480] SRC[511:480]
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVSHDUP (VEX.256 encoded version)
DEST[31:0] SRC[63:32]
DEST[63:32] SRC[63:32]
DEST[95:64] SRC[127:96]
DEST[127:96] SRC[127:96]
DEST[159:128] SRC[191:160]
DEST[191:160] SRC[191:160]
DEST[223:192] SRC[255:224]
DEST[255:224] SRC[255:224]
DEST[MAX_VL-1:256] 0
VMOVSHDUP (VEX.128 encoded version)
DEST[31:0] SRC[63:32]
DEST[63:32] SRC[63:32]
DEST[95:64] SRC[127:96]
DEST[127:96] SRC[127:96]
DEST[MAX_VL-1:128] 0
MOVSHDUP (128-bit Legacy SSE version)
DEST[31:0] SRC[63:32]
MOVSHDUP—Replicate Single FP Values
Vol. 2B 4-115
INSTRUCTION SET REFERENCE, M-U
DEST[63:32] SRC[63:32]
DEST[95:64] SRC[127:96]
DEST[127:96] SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMOVSHDUP __m512 _mm512_movehdup_ps( __m512 a);
VMOVSHDUP __m512 _mm512_mask_movehdup_ps(__m512 s, __mmask16 k, __m512 a);
VMOVSHDUP __m512 _mm512_maskz_movehdup_ps( __mmask16 k, __m512 a);
VMOVSHDUP __m256 _mm256_mask_movehdup_ps(__m256 s, __mmask8 k, __m256 a);
VMOVSHDUP __m256 _mm256_maskz_movehdup_ps( __mmask8 k, __m256 a);
VMOVSHDUP __m128 _mm_mask_movehdup_ps(__m128 s, __mmask8 k, __m128 a);
VMOVSHDUP __m128 _mm_maskz_movehdup_ps( __mmask8 k, __m128 a);
VMOVSHDUP __m256 _mm256_movehdup_ps (__m256 a);
VMOVSHDUP __m128 _mm_movehdup_ps (__m128 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
#UD
4-116 Vol. 2B
If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.
MOVSHDUP—Replicate Single FP Values
INSTRUCTION SET REFERENCE, M-U
MOVSLDUP—Replicate Single FP Values
Opcode/
Instruction
Op /
En
A
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE3
F3 0F 12 /r
MOVSLDUP xmm1, xmm2/m128
VEX.128.F3.0F.WIG 12 /r
VMOVSLDUP xmm1, xmm2/m128
VEX.256.F3.0F.WIG 12 /r
VMOVSLDUP ymm1, ymm2/m256
EVEX.128.F3.0F.W0 12 /r
VMOVSLDUP xmm1 {k1}{z},
xmm2/m128
EVEX.256.F3.0F.W0 12 /r
VMOVSLDUP ymm1 {k1}{z},
ymm2/m256
EVEX.512.F3.0F.W0 12 /r
VMOVSLDUP zmm1 {k1}{z},
zmm2/m512
RM
V/V
AVX
RM
V/V
AVX
FVM
V/V
AVX512VL
AVX512F
FVM
V/V
AVX512VL
AVX512F
FVM
V/V
AVX512F
Description
Move even index single-precision floating-point values from
xmm2/mem and duplicate each element into xmm1.
Move even index single-precision floating-point values from
xmm2/mem and duplicate each element into xmm1.
Move even index single-precision floating-point values from
ymm2/mem and duplicate each element into ymm1.
Move even index single-precision floating-point values from
xmm2/m128 and duplicate each element into xmm1 under
writemask.
Move even index single-precision floating-point values from
ymm2/m256 and duplicate each element into ymm1 under
writemask.
Move even index single-precision floating-point values from
zmm2/m512 and duplicate each element into zmm1 under
writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Duplicates even-indexed single-precision floating-point values from the source operand (the second operand). See
Figure 4-4. The source operand is an XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the
destination operand is an XMM, YMM or ZMM register.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.
VEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.
EVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
SRC
X7
X6
X5
X4
X3
X2
X1
X0
DEST
X6
X6
X4
X4
X2
X2
X0
X0
Figure 4-4. MOVSLDUP Operation
MOVSLDUP—Replicate Single FP Values
Vol. 2B 4-117
INSTRUCTION SET REFERENCE, M-U
Operation
VMOVSLDUP (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
TMP_SRC[31:0] SRC[31:0]
TMP_SRC[63:32] SRC[31:0]
TMP_SRC[95:64] SRC[95:64]
TMP_SRC[127:96] SRC[95:64]
IF VL >= 256
TMP_SRC[159:128] SRC[159:128]
TMP_SRC[191:160] SRC[159:128]
TMP_SRC[223:192] SRC[223:192]
TMP_SRC[255:224] SRC[223:192]
FI;
IF VL >= 512
TMP_SRC[287:256] SRC[287:256]
TMP_SRC[319:288] SRC[287:256]
TMP_SRC[351:320] SRC[351:320]
TMP_SRC[383:352] SRC[351:320]
TMP_SRC[415:384] SRC[415:384]
TMP_SRC[447:416] SRC[415:384]
TMP_SRC[479:448] SRC[479:448]
TMP_SRC[511:480] SRC[479:448]
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVSLDUP (VEX.256 encoded version)
DEST[31:0] SRC[31:0]
DEST[63:32] SRC[31:0]
DEST[95:64] SRC[95:64]
DEST[127:96] SRC[95:64]
DEST[159:128] SRC[159:128]
DEST[191:160] SRC[159:128]
DEST[223:192] SRC[223:192]
DEST[255:224] SRC[223:192]
DEST[MAX_VL-1:256] 0
VMOVSLDUP (VEX.128 encoded version)
DEST[31:0] SRC[31:0]
DEST[63:32] SRC[31:0]
DEST[95:64] SRC[95:64]
DEST[127:96] SRC[95:64]
DEST[MAX_VL-1:128] 0
4-118 Vol. 2B
MOVSLDUP—Replicate Single FP Values
INSTRUCTION SET REFERENCE, M-U
MOVSLDUP (128-bit Legacy SSE version)
DEST[31:0] SRC[31:0]
DEST[63:32] SRC[31:0]
DEST[95:64] SRC[95:64]
DEST[127:96] SRC[95:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMOVSLDUP __m512 _mm512_moveldup_ps( __m512 a);
VMOVSLDUP __m512 _mm512_mask_moveldup_ps(__m512 s, __mmask16 k, __m512 a);
VMOVSLDUP __m512 _mm512_maskz_moveldup_ps( __mmask16 k, __m512 a);
VMOVSLDUP __m256 _mm256_mask_moveldup_ps(__m256 s, __mmask8 k, __m256 a);
VMOVSLDUP __m256 _mm256_maskz_moveldup_ps( __mmask8 k, __m256 a);
VMOVSLDUP __m128 _mm_mask_moveldup_ps(__m128 s, __mmask8 k, __m128 a);
VMOVSLDUP __m128 _mm_maskz_moveldup_ps( __mmask8 k, __m128 a);
VMOVSLDUP __m256 _mm256_moveldup_ps (__m256 a);
VMOVSLDUP __m128 _mm_moveldup_ps (__m128 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
#UD
If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.
MOVSLDUP—Replicate Single FP Values
Vol. 2B 4-119
INSTRUCTION SET REFERENCE, M-U
MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 10 /r
MOVSS xmm1, xmm2
F3 0F 10 /r
MOVSS xmm1, m32
VEX.NDS.LIG.F3.0F.WIG 10 /r
VMOVSS xmm1, xmm2, xmm3
VEX.LIG.F3.0F.WIG 10 /r
VMOVSS xmm1, m32
F3 0F 11 /r
MOVSS xmm2/m32, xmm1
VEX.NDS.LIG.F3.0F.WIG 11 /r
VMOVSS xmm1, xmm2, xmm3
VEX.LIG.F3.0F.WIG 11 /r
VMOVSS m32, xmm1
EVEX.NDS.LIG.F3.0F.W0 10 /r
VMOVSS xmm1 {k1}{z}, xmm2, xmm3
RM
V/V
SSE
RVM
V/V
AVX
XM
V/V
AVX
MR
V/V
SSE
MVR
V/V
AVX
MR
V/V
AVX
RVM
V/V
AVX512F
EVEX.LIG.F3.0F.W0 10 /r
VMOVSS xmm1 {k1}{z}, m32
EVEX.NDS.LIG.F3.0F.W0 11 /r
VMOVSS xmm1 {k1}{z}, xmm2, xmm3
T1S-RM
V/V
AVX512F
MVR
V/V
AVX512F
EVEX.LIG.F3.0F.W0 11 /r
VMOVSS m32 {k1}, xmm1
T1S-MR
V/V
AVX512F
Description
Merge scalar single-precision floating-point value
from xmm2 to xmm1 register.
Load scalar single-precision floating-point value from
m32 to xmm1 register.
Merge scalar single-precision floating-point value
from xmm2 and xmm3 to xmm1 register
Load scalar single-precision floating-point value from
m32 to xmm1 register.
Move scalar single-precision floating-point value
from xmm1 register to xmm2/m32.
Move scalar single-precision floating-point value
from xmm2 and xmm3 to xmm1 register.
Move scalar single-precision floating-point value
from xmm1 register to m32.
Move scalar single-precision floating-point value
from xmm2 and xmm3 to xmm1 register under
writemask k1.
Move scalar single-precision floating-point values
from m32 to xmm1 under writemask k1.
Move scalar single-precision floating-point value
from xmm2 and xmm3 to xmm1 register under
writemask k1.
Move scalar single-precision floating-point values
from xmm1 to m32 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
XM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MVR
ModRM:r/m (w)
vvvv (r)
ModRM:reg (r)
NA
T1S-RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
T1S-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
4-120 Vol. 2B
MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Description
Moves a scalar single-precision floating-point value from the source operand (second operand) to the destination
operand (first operand). The source and destination operands can be XMM registers or 32-bit memory locations.
This instruction can be used to move a single-precision floating-point value to and from the low doubleword of an
XMM register and a 32-bit memory location, or to move a single-precision floating-point value between the low
doublewords of two XMM registers. The instruction cannot be used to transfer data between memory locations.
Legacy version: When the source and destination operands are XMM registers, bits (MAX_VL-1:32) of the corresponding destination register are unmodified. When the source operand is a memory location and destination
operand is an XMM registers, Bits (127:32) of the destination operand is cleared to all 0s, bits MAX_VL:128 of the
destination operand remains unchanged.
VEX and EVEX encoded register-register syntax: Moves a scalar single-precision floating-point value from the
second source operand (the third operand) to the low doubleword element of the destination operand (the first
operand). Bits 127:32 of the destination operand are copied from the first source operand (the second operand).
Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX and EVEX encoded memory load syntax: When the source operand is a memory location and destination
operand is an XMM registers, bits MAX_VL:32 of the destination operand is cleared to all 0s.
EVEX encoded versions: The low doubleword of the destination is updated according to the writemask.
Note: For memory store form instruction “VMOVSS m32, xmm1”, VEX.vvvv is reserved and must be 1111b otherwise instruction will #UD. For memory store form instruction “VMOVSS mv {k1}, xmm1”, EVEX.vvvv is reserved
and must be 1111b otherwise instruction will #UD.
Software should ensure VMOVSS is encoded with VEX.L=0. Encoding VMOVSS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
VMOVSS (EVEX.NDS.LIG.F3.0F.W0 11 /r when the source operand is memory and the destination is an XMM register)
IF k1[0] or *no writemask*
THEN
DEST[31:0] SRC[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[511:32] 0
VMOVSS (EVEX.NDS.LIG.F3.0F.W0 10 /r when the source operand is an XMM register and the destination is memory)
IF k1[0] or *no writemask*
THEN
DEST[31:0] SRC[31:0]
ELSE
*DEST[31:0] remains unchanged*
; merging-masking
FI;
MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value
Vol. 2B 4-121
INSTRUCTION SET REFERENCE, M-U
VMOVSS (EVEX.NDS.LIG.F3.0F.W0 10/11 /r where the source and destination are XMM registers)
IF k1[0] or *no writemask*
THEN
DEST[31:0] SRC2[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
MOVSS (Legacy SSE version when the source and destination operands are both XMM registers)
DEST[31:0] SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)
VMOVSS (VEX.NDS.128.F3.0F 11 /r where the destination is an XMM register)
DEST[31:0] SRC2[31:0]
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VMOVSS (VEX.NDS.128.F3.0F 10 /r where the source and destination are XMM registers)
DEST[31:0] SRC2[31:0]
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VMOVSS (VEX.NDS.128.F3.0F 10 /r when the source operand is memory and the destination is an XMM register)
DEST[31:0] SRC[31:0]
DEST[MAX_VL-1:32] 0
MOVSS/VMOVSS (when the source operand is an XMM register and the destination is memory)
DEST[31:0] SRC[31:0]
MOVSS (Legacy SSE version when the source operand is memory and the destination is an XMM register)
DEST[31:0] SRC[31:0]
DEST[127:32] 0
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMOVSS __m128 _mm_mask_load_ss(__m128 s, __mmask8 k, float * p);
VMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p);
VMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a);
VMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a);
VMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a);
MOVSS __m128 _mm_load_ss(float * p)
MOVSS void_mm_store_ss(float * p, __m128 a)
MOVSS __m128 _mm_move_ss(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
None
4-122 Vol. 2B
MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E10.
MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value
Vol. 2B 4-123
INSTRUCTION SET REFERENCE, M-U
MOVSX/MOVSXD—Move with Sign-Extension
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F BE /r
MOVSX r16, r/m8
RM
Valid
Valid
Move byte to word with sign-extension.
0F BE /r
MOVSX r32, r/m8
RM
Valid
Valid
Move byte to doubleword with signextension.
REX + 0F BE /r
MOVSX r64, r/m8*
RM
Valid
N.E.
Move byte to quadword with sign-extension.
0F BF /r
MOVSX r32, r/m16
RM
Valid
Valid
Move word to doubleword, with signextension.
REX.W + 0F BF /r
MOVSX r64, r/m16
RM
Valid
N.E.
Move word to quadword with sign-extension.
REX.W** + 63 /r
MOVSXD r64, r/m32
RM
Valid
N.E.
Move doubleword to quadword with signextension.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
** The use of MOVSXD without REX.W in 64-bit mode is discouraged, Regular MOV should be used instead of using MOVSXD without
REX.W.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and
sign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). The size of the converted value depends on the operand-size attribute.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
DEST ← SignExtend(SRC);
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
4-124 Vol. 2B
MOVSX/MOVSXD—Move with Sign-Extension
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
MOVSX/MOVSXD—Move with Sign-Extension
Vol. 2B 4-125
INSTRUCTION SET REFERENCE, M-U
MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 10 /r
MOVUPD xmm1, xmm2/m128
66 0F 11 /r
MOVUPD xmm2/m128, xmm1
VEX.128.66.0F.WIG 10 /r
VMOVUPD xmm1, xmm2/m128
VEX.128.66.0F.WIG 11 /r
VMOVUPD xmm2/m128, xmm1
VEX.256.66.0F.WIG 10 /r
VMOVUPD ymm1, ymm2/m256
VEX.256.66.0F.WIG 11 /r
VMOVUPD ymm2/m256, ymm1
EVEX.128.66.0F.W1 10 /r
VMOVUPD xmm1 {k1}{z}, xmm2/m128
MR
V/V
SSE2
RM
V/V
AVX
MR
V/V
AVX
RM
V/V
AVX
MR
V/V
AVX
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.128.66.0F.W1 11 /r
VMOVUPD xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 10 /r
VMOVUPD ymm1 {k1}{z}, ymm2/m256
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 11 /r
VMOVUPD ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.512.66.0F.W1 10 /r
VMOVUPD zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512F
EVEX.512.66.0F.W1 11 /r
VMOVUPD zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512F
Description
Move unaligned packed double-precision floatingpoint from xmm2/mem to xmm1.
Move unaligned packed double-precision floatingpoint from xmm1 to xmm2/mem.
Move unaligned packed double-precision floatingpoint from xmm2/mem to xmm1.
Move unaligned packed double-precision floatingpoint from xmm1 to xmm2/mem.
Move unaligned packed double-precision floatingpoint from ymm2/mem to ymm1.
Move unaligned packed double-precision floatingpoint from ymm1 to ymm2/mem.
Move unaligned packed double-precision floatingpoint from xmm2/m128 to xmm1 using
writemask k1.
Move unaligned packed double-precision floatingpoint from xmm1 to xmm2/m128 using
writemask k1.
Move unaligned packed double-precision floatingpoint from ymm2/m256 to ymm1 using
writemask k1.
Move unaligned packed double-precision floatingpoint from ymm1 to ymm2/m256 using
writemask k1.
Move unaligned packed double-precision floatingpoint values from zmm2/m512 to zmm1 using
writemask k1.
Move unaligned packed double-precision floatingpoint values from zmm1 to zmm2/m512 using
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Note: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a float64 memory
location, to store the contents of a ZMM register into a memory. The destination operand is updated according to
the writemask.
4-126 Vol. 2B
MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VEX.256 encoded version:
Moves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. Bits (MAX_VL-1:256) of the destination register are zeroed.
128-bit versions:
Moves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
When the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte
boundary without causing a general-protection exception (#GP) to be generated
VEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.
Operation
VMOVUPD (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVUPD (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE *DEST[i+63:i] remains unchanged*
; merging-masking
FI;
ENDFOR;
MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values
Vol. 2B 4-127
INSTRUCTION SET REFERENCE, M-U
VMOVUPD (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVUPD (VEX.256 encoded version, load - and register copy)
DEST[255:0] SRC[255:0]
DEST[MAX_VL-1:256] 0
VMOVUPD (VEX.256 encoded version, store-form)
DEST[255:0] SRC[255:0]
VMOVUPD (VEX.128 encoded version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] 0
MOVUPD (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)
(V)MOVUPD (128-bit store-form version)
DEST[127:0] SRC[127:0]
Intel C/C++ Compiler Intrinsic Equivalent
VMOVUPD __m512d _mm512_loadu_pd( void * s);
VMOVUPD __m512d _mm512_mask_loadu_pd(__m512d a, __mmask8 k, void * s);
VMOVUPD __m512d _mm512_maskz_loadu_pd( __mmask8 k, void * s);
VMOVUPD void _mm512_storeu_pd( void * d, __m512d a);
VMOVUPD void _mm512_mask_storeu_pd( void * d, __mmask8 k, __m512d a);
VMOVUPD __m256d _mm256_mask_loadu_pd(__m256d s, __mmask8 k, void * m);
VMOVUPD __m256d _mm256_maskz_loadu_pd( __mmask8 k, void * m);
VMOVUPD void _mm256_mask_storeu_pd( void * d, __mmask8 k, __m256d a);
VMOVUPD __m128d _mm_mask_loadu_pd(__m128d s, __mmask8 k, void * m);
VMOVUPD __m128d _mm_maskz_loadu_pd( __mmask8 k, void * m);
VMOVUPD void _mm_mask_storeu_pd( void * d, __mmask8 k, __m128d a);
MOVUPD __m256d _mm256_loadu_pd (double * p);
MOVUPD void _mm256_storeu_pd( double *p, __m256d a);
MOVUPD __m128d _mm_loadu_pd (double * p);
MOVUPD void _mm_storeu_pd( double *p, __m128d a);
SIMD Floating-Point Exceptions
None
4-128 Vol. 2B
MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
Note treatment of #AC varies; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E4.nb.
MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values
Vol. 2B 4-129
INSTRUCTION SET REFERENCE, M-U
MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op / En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 10 /r
MOVUPS xmm1, xmm2/m128
0F 11 /r
MOVUPS xmm2/m128, xmm1
VEX.128.0F.WIG 10 /r
VMOVUPS xmm1, xmm2/m128
VEX.128.0F 11.WIG /r
VMOVUPS xmm2/m128, xmm1
VEX.256.0F 10.WIG /r
VMOVUPS ymm1, ymm2/m256
VEX.256.0F 11.WIG /r
VMOVUPS ymm2/m256, ymm1
EVEX.128.0F.W0 10 /r
VMOVUPS xmm1 {k1}{z}, xmm2/m128
MR
V/V
SSE
RM
V/V
AVX
MR
V/V
AVX
RM
V/V
AVX
MR
V/V
AVX
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.256.0F.W0 10 /r
VMOVUPS ymm1 {k1}{z}, ymm2/m256
FVM-RM
V/V
AVX512VL
AVX512F
EVEX.512.0F.W0 10 /r
VMOVUPS zmm1 {k1}{z}, zmm2/m512
FVM-RM
V/V
AVX512F
EVEX.128.0F.W0 11 /r
VMOVUPS xmm2/m128 {k1}{z}, xmm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.256.0F.W0 11 /r
VMOVUPS ymm2/m256 {k1}{z}, ymm1
FVM-MR
V/V
AVX512VL
AVX512F
EVEX.512.0F.W0 11 /r
VMOVUPS zmm2/m512 {k1}{z}, zmm1
FVM-MR
V/V
AVX512F
Description
Move unaligned packed single-precision
floating-point from xmm2/mem to xmm1.
Move unaligned packed single-precision
floating-point from xmm1 to xmm2/mem.
Move unaligned packed single-precision
floating-point from xmm2/mem to xmm1.
Move unaligned packed single-precision
floating-point from xmm1 to xmm2/mem.
Move unaligned packed single-precision
floating-point from ymm2/mem to ymm1.
Move unaligned packed single-precision
floating-point from ymm1 to ymm2/mem.
Move unaligned packed single-precision
floating-point values from xmm2/m128 to
xmm1 using writemask k1.
Move unaligned packed single-precision
floating-point values from ymm2/m256 to
ymm1 using writemask k1.
Move unaligned packed single-precision
floating-point values from zmm2/m512 to
zmm1 using writemask k1.
Move unaligned packed single-precision
floating-point values from xmm1 to
xmm2/m128 using writemask k1.
Move unaligned packed single-precision
floating-point values from ymm1 to
ymm2/m256 using writemask k1.
Move unaligned packed single-precision
floating-point values from zmm1 to
zmm2/m512 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
FVM-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM-MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Note: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32
memory location, to store the contents of a ZMM register into memory. The destination operand is updated
according to the writemask.
4-130 Vol. 2B
MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VEX.256 and EVEX.256 encoded versions:
Moves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. Bits (MAX_VL-1:256) of the destination register are zeroed.
128-bit versions:
Moves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
When the source or destination operand is a memory operand, the operand may be unaligned without causing a
general-protection exception (#GP) to be generated.
VEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.
Operation
VMOVUPS (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVUPS (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR;
; merging-masking
MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values
Vol. 2B 4-131
INSTRUCTION SET REFERENCE, M-U
VMOVUPS (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMOVUPS (VEX.256 encoded version, load - and register copy)
DEST[255:0] SRC[255:0]
DEST[MAX_VL-1:256] 0
VMOVUPS (VEX.256 encoded version, store-form)
DEST[255:0] SRC[255:0]
VMOVUPS (VEX.128 encoded version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] 0
MOVUPS (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)
(V)MOVUPS (128-bit store-form version)
DEST[127:0] SRC[127:0]
Intel C/C++ Compiler Intrinsic Equivalent
VMOVUPS __m512 _mm512_loadu_ps( void * s);
VMOVUPS __m512 _mm512_mask_loadu_ps(__m512 a, __mmask16 k, void * s);
VMOVUPS __m512 _mm512_maskz_loadu_ps( __mmask16 k, void * s);
VMOVUPS void _mm512_storeu_ps( void * d, __m512 a);
VMOVUPS void _mm512_mask_storeu_ps( void * d, __mmask8 k, __m512 a);
VMOVUPS __m256 _mm256_mask_loadu_ps(__m256 a, __mmask8 k, void * s);
VMOVUPS __m256 _mm256_maskz_loadu_ps( __mmask8 k, void * s);
VMOVUPS void _mm256_mask_storeu_ps( void * d, __mmask8 k, __m256 a);
VMOVUPS __m128 _mm_mask_loadu_ps(__m128 a, __mmask8 k, void * s);
VMOVUPS __m128 _mm_maskz_loadu_ps( __mmask8 k, void * s);
VMOVUPS void _mm_mask_storeu_ps( void * d, __mmask8 k, __m128 a);
MOVUPS __m256 _mm256_loadu_ps ( float * p);
MOVUPS void _mm256 _storeu_ps( float *p, __m256 a);
MOVUPS __m128 _mm_loadu_ps ( float * p);
MOVUPS void _mm_storeu_ps( float *p, __m128 a);
SIMD Floating-Point Exceptions
None
4-132 Vol. 2B
MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
Note treatment of #AC varies;
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD
If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.
MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values
Vol. 2B 4-133
INSTRUCTION SET REFERENCE, M-U
MOVZX—Move with Zero-Extend
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F B6 /r
MOVZX r16, r/m8
RM
Valid
Valid
Move byte to word with zero-extension.
0F B6 /r
MOVZX r32, r/m8
RM
Valid
Valid
Move byte to doubleword, zero-extension.
REX.W + 0F B6 /r
MOVZX r64, r/m8*
RM
Valid
N.E.
Move byte to quadword, zero-extension.
0F B7 /r
MOVZX r32, r/m16
RM
Valid
Valid
Move word to doubleword, zero-extension.
REX.W + 0F B7 /r
MOVZX r64, r/m16
RM
Valid
N.E.
Move word to quadword, zero-extension.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if the REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and
zero extends the value. The size of the converted value depends on the operand-size attribute.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bit operands. See the summary chart
at the beginning of this section for encoding data and limits.
Operation
DEST ← ZeroExtend(SRC);
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
4-134 Vol. 2B
MOVZX—Move with Zero-Extend
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
MOVZX—Move with Zero-Extend
Vol. 2B 4-135
INSTRUCTION SET REFERENCE, M-U
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A 42 /r ib
RMI
V/V
SSE4_1
Sums absolute 8-bit integer difference of
adjacent groups of 4 byte integers in xmm1
and xmm2/m128 and writes the results in
xmm1. Starting offsets within xmm1 and
xmm2/m128 are determined by imm8.
RVMI V/V
AVX
Sums absolute 8-bit integer difference of
adjacent groups of 4 byte integers in xmm2
and xmm3/m128 and writes the results in
xmm1. Starting offsets within xmm2 and
xmm3/m128 are determined by imm8.
RVMI V/V
AVX2
Sums absolute 8-bit integer difference of
adjacent groups of 4 byte integers in xmm2
and ymm3/m128 and writes the results in
ymm1. Starting offsets within ymm2 and
xmm3/m128 are determined by imm8.
MPSADBW xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 42 /r ib
VMPSADBW xmm1, xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.WIG 42 /r ib
VMPSADBW ymm1, ymm2, ymm3/m256, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
(V)MPSADBW calculates packed word results of sum-absolute-difference (SAD) of unsigned bytes from two blocks
of 32-bit dword elements, using two select fields in the immediate byte to select the offsets of the two blocks within
the first source operand and the second operand. Packed SAD word results are calculated within each 128-bit lane.
Each SAD word result is calculated between a stationary block_2 (whose offset within the second source operand
is selected by a two bit select control, multiplied by 32 bits) and a sliding block_1 at consecutive byte-granular
position within the first source operand. The offset of the first 32-bit block of block_1 is selectable using a one bit
select control, multiplied by 32 bits.
128-bit Legacy SSE version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.
Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source operand
and destination operand are the same. The first source and destination operands are XMM registers. The second
source operand is either an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. Bits 7:3 of the immediate byte are ignored.
VEX.128 encoded version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.
Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source and destination operands are XMM registers. The second source operand is either an XMM register or a 128-bit memory
location. Bits (127:128) of the corresponding YMM register are zeroed. Bits 7:3 of the immediate byte are ignored.
VEX.256 encoded version: The sum-absolute-difference (SAD) operation is repeated 8 times for MPSADW between
the same block_2 (fixed offset within the second source operand) and a variable block_1 (offset is shifted by 8 bits
for each SAD operation) in the first source operand. Each 16-bit result of eight SAD operations between block_2
and block_1 is written to the respective word in the lower 128 bits of the destination operand.
Additionally, VMPSADBW performs another eight SAD operations on block_4 of the second source operand and
block_3 of the first source operand. (Imm8[4:3]*32 + 128) specifies the bit offset of block_4 within the second
source operand. (Imm[5]*32+128) specifies the initial bit offset of the block_3 within the first source operand.
Each 16-bit result of eight SAD operations between block_4 and block_3 is written to the respective word in the
upper 128 bits of the destination operand.
4-136 Vol. 2B
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
INSTRUCTION SET REFERENCE, M-U
The first source operand is a YMM register. The second source register can be a YMM register or a 256-bit memory
location. The destination operand is a YMM register. Bits 7:6 of the immediate byte are ignored.
Note: If VMPSADBW is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will
cause an #UD exception.
Imm[4:3]*32+128
255
224
192
Src2
Abs. Diff.
Src1
128
Imm[5]*32+128
Sum
144
255
128
Destination
Imm[1:0]*32
127
96
Src2
64
Abs. Diff.
0
Imm[2]*32
Src1
Sum
16
127
0
Destination
Figure 4-5. 256-bit VMPSADBW Operation
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
Vol. 2B 4-137
INSTRUCTION SET REFERENCE, M-U
Operation
VMPSADBW (VEX.256 encoded version)
BLK2_OFFSET imm8[1:0]*32
BLK1_OFFSET imm8[2]*32
SRC1_BYTE0 SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
SRC1_BYTE1 SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
SRC1_BYTE2 SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
SRC1_BYTE3 SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
SRC1_BYTE4 SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
SRC1_BYTE5 SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
SRC1_BYTE6 SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
SRC1_BYTE7 SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
SRC1_BYTE8 SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
SRC1_BYTE9 SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
SRC1_BYTE10 SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]
SRC2_BYTE0 SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
SRC2_BYTE1 SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
SRC2_BYTE2 SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
SRC2_BYTE3 SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
TEMP0 ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[15:0] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[31:16] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[47:32] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[63:48] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[79:64] TEMP0 + TEMP1 + TEMP2 + TEMP3
4-138 Vol. 2B
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
INSTRUCTION SET REFERENCE, M-U
TEMP0 ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[95:80] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[111:96] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[127:112] TEMP0 + TEMP1 + TEMP2 + TEMP3
BLK2_OFFSET imm8[4:3]*32 + 128
BLK1_OFFSET imm8[5]*32 + 128
SRC1_BYTE0 SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
SRC1_BYTE1 SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
SRC1_BYTE2 SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
SRC1_BYTE3 SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
SRC1_BYTE4 SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
SRC1_BYTE5 SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
SRC1_BYTE6 SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
SRC1_BYTE7 SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
SRC1_BYTE8 SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
SRC1_BYTE9 SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
SRC1_BYTE10 SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]
SRC2_BYTE0 SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
SRC2_BYTE1 SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
SRC2_BYTE2 SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
SRC2_BYTE3 SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
TEMP0 ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[143:128] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[159:144] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[175:160] TEMP0 + TEMP1 + TEMP2 + TEMP3
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
Vol. 2B 4-139
INSTRUCTION SET REFERENCE, M-U
TEMP0 ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[191:176] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[207:192] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[223:208] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[239:224] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[255:240] TEMP0 + TEMP1 + TEMP2 + TEMP3
VMPSADBW (VEX.128 encoded version)
BLK2_OFFSET imm8[1:0]*32
BLK1_OFFSET imm8[2]*32
SRC1_BYTE0 SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
SRC1_BYTE1 SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
SRC1_BYTE2 SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
SRC1_BYTE3 SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
SRC1_BYTE4 SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
SRC1_BYTE5 SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
SRC1_BYTE6 SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
SRC1_BYTE7 SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
SRC1_BYTE8 SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
SRC1_BYTE9 SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
SRC1_BYTE10 SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]
SRC2_BYTE0 SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
SRC2_BYTE1 SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
SRC2_BYTE2 SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
SRC2_BYTE3 SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
4-140 Vol. 2B
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
INSTRUCTION SET REFERENCE, M-U
TEMP0 ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[15:0] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[31:16] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[47:32] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[63:48] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[79:64] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[95:80] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[111:96] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[127:112] TEMP0 + TEMP1 + TEMP2 + TEMP3
DEST[VLMAX-1:128] 0
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
Vol. 2B 4-141
INSTRUCTION SET REFERENCE, M-U
MPSADBW (128-bit Legacy SSE version)
SRC_OFFSET imm8[1:0]*32
DEST_OFFSET imm8[2]*32
DEST_BYTE0 DEST[DEST_OFFSET+7:DEST_OFFSET]
DEST_BYTE1 DEST[DEST_OFFSET+15:DEST_OFFSET+8]
DEST_BYTE2 DEST[DEST_OFFSET+23:DEST_OFFSET+16]
DEST_BYTE3 DEST[DEST_OFFSET+31:DEST_OFFSET+24]
DEST_BYTE4 DEST[DEST_OFFSET+39:DEST_OFFSET+32]
DEST_BYTE5 DEST[DEST_OFFSET+47:DEST_OFFSET+40]
DEST_BYTE6 DEST[DEST_OFFSET+55:DEST_OFFSET+48]
DEST_BYTE7 DEST[DEST_OFFSET+63:DEST_OFFSET+56]
DEST_BYTE8 DEST[DEST_OFFSET+71:DEST_OFFSET+64]
DEST_BYTE9 DEST[DEST_OFFSET+79:DEST_OFFSET+72]
DEST_BYTE10 DEST[DEST_OFFSET+87:DEST_OFFSET+80]
SRC_BYTE0 SRC[SRC_OFFSET+7:SRC_OFFSET]
SRC_BYTE1 SRC[SRC_OFFSET+15:SRC_OFFSET+8]
SRC_BYTE2 SRC[SRC_OFFSET+23:SRC_OFFSET+16]
SRC_BYTE3 SRC[SRC_OFFSET+31:SRC_OFFSET+24]
TEMP0 ABS( DEST_BYTE0 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE1 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE2 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE3 - SRC_BYTE3)
DEST[15:0] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS( DEST_BYTE1 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE2 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE3 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE4 - SRC_BYTE3)
DEST[31:16] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS( DEST_BYTE2 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE3 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE4 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE5 - SRC_BYTE3)
DEST[47:32] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS( DEST_BYTE3 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE4 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE5 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE6 - SRC_BYTE3)
DEST[63:48] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS( DEST_BYTE4 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE5 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE6 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE7 - SRC_BYTE3)
DEST[79:64] TEMP0 + TEMP1 + TEMP2 + TEMP3
4-142 Vol. 2B
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
INSTRUCTION SET REFERENCE, M-U
TEMP0 ABS( DEST_BYTE5 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE6 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE7 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE8 - SRC_BYTE3)
DEST[95:80] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS( DEST_BYTE6 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE7 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE8 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE9 - SRC_BYTE3)
DEST[111:96] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS( DEST_BYTE7 - SRC_BYTE0)
TEMP1 ABS( DEST_BYTE8 - SRC_BYTE1)
TEMP2 ABS( DEST_BYTE9 - SRC_BYTE2)
TEMP3 ABS( DEST_BYTE10 - SRC_BYTE3)
DEST[127:112] TEMP0 + TEMP1 + TEMP2 + TEMP3
DEST[VLMAX-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
(V)MPSADBW:
__m128i _mm_mpsadbw_epu8 (__m128i s1, __m128i s2, const int mask);
VMPSADBW:
__m256i _mm256_mpsadbw_epu8 (__m256i s1, __m256i s2, const int mask);
Flags Affected
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.L = 1.
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
Vol. 2B 4-143
INSTRUCTION SET REFERENCE, M-U
MUL—Unsigned Multiply
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F6 /4
MUL r/m8
M
Valid
Valid
Unsigned multiply (AX ← AL ∗ r/m8).
REX + F6 /4
MUL r/m8*
M
Valid
N.E.
Unsigned multiply (AX ← AL ∗ r/m8).
F7 /4
MUL r/m16
M
Valid
Valid
Unsigned multiply (DX:AX ← AX ∗ r/m16).
F7 /4
MUL r/m32
M
Valid
Valid
Unsigned multiply (EDX:EAX ← EAX ∗ r/m32).
REX.W + F7 /4
MUL r/m64
M
Valid
N.E.
Unsigned multiply (RDX:RAX ← RAX ∗ r/m64).
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Performs an unsigned multiplication of the first operand (destination operand) and the second operand (source
operand) and stores the result in the destination operand. The destination operand is an implied operand located in
register AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose
register or a memory location. The action of this instruction and the location of the result depends on the opcode
and the operand size as shown in Table 4-9.
The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size),
with the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of
the product are 0, the CF and OF flags are cleared; otherwise, the flags are set.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.
See the summary chart at the beginning of this section for encoding data and limits.
Table 4-9. MUL Results
Operand Size
Source 1
Source 2
Destination
Byte
AL
r/m8
AX
Word
AX
r/m16
DX:AX
Doubleword
EAX
r/m32
EDX:EAX
Quadword
RAX
r/m64
RDX:RAX
4-144 Vol. 2B
MUL—Unsigned Multiply
INSTRUCTION SET REFERENCE, M-U
Operation
IF (Byte operation)
THEN
AX ← AL ∗ SRC;
ELSE (* Word or doubleword operation *)
IF OperandSize = 16
THEN
DX:AX ← AX ∗ SRC;
ELSE IF OperandSize = 32
THEN EDX:EAX ← EAX ∗ SRC; FI;
ELSE (* OperandSize = 64 *)
RDX:RAX ← RAX ∗ SRC;
FI;
FI;
Flags Affected
The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and
PF flags are undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
MUL—Unsigned Multiply
Vol. 2B 4-145
INSTRUCTION SET REFERENCE, M-U
MULPD—Multiply Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 59 /r
MULPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 59 /r
VMULPD xmm1,xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 59 /r
VMULPD ymm1, ymm2, ymm3/m256
EVEX.NDS.128.66.0F.W1 59 /r
VMULPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 59 /r
VMULPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 59 /r
VMULPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Multiply packed double-precision floating-point values
in xmm2/m128 with xmm1 and store result in xmm1.
Multiply packed double-precision floating-point values
in xmm3/m128 with xmm2 and store result in xmm1.
Multiply packed double-precision floating-point values
in ymm3/m256 with ymm2 and store result in ymm1.
Multiply packed double-precision floating-point values
from xmm3/m128/m64bcst to xmm2 and store result
in xmm1.
Multiply packed double-precision floating-point values
from ymm3/m256/m64bcst to ymm2 and store result
in ymm1.
Multiply packed double-precision floating-point values
in zmm3/m512/m64bcst with zmm2 and store result
in zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Multiply packed double-precision floating-point values from the first source operand with corresponding values in
the second source operand, and stores the packed double-precision floating-point results in the destination
operand.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the
corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the destination YMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
4-146 Vol. 2B
MULPD—Multiply Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
VMULPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] SRC1[i+63:i] * SRC2[63:0]
ELSE
DEST[i+63:i] SRC1[i+63:i] * SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMULPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] * SRC2[63:0]
DEST[127:64] SRC1[127:64] * SRC2[127:64]
DEST[191:128] SRC1[191:128] * SRC2[191:128]
DEST[255:192] SRC1[255:192] * SRC2[255:192]
DEST[MAX_VL-1:256] 0;
.
VMULPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] * SRC2[63:0]
DEST[127:64] SRC1[127:64] * SRC2[127:64]
DEST[MAX_VL-1:128] 0
MULPD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] * SRC[63:0]
DEST[127:64] DEST[127:64] * SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
MULPD—Multiply Packed Double-Precision Floating-Point Values
Vol. 2B 4-147
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VMULPD __m512d _mm512_mul_pd( __m512d a, __m512d b);
VMULPD __m512d _mm512_mask_mul_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VMULPD __m512d _mm512_maskz_mul_pd( __mmask8 k, __m512d a, __m512d b);
VMULPD __m512d _mm512_mul_round_pd( __m512d a, __m512d b, int);
VMULPD __m512d _mm512_mask_mul_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VMULPD __m512d _mm512_maskz_mul_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMULPD __m256d _mm256_mul_pd (__m256d a, __m256d b);
MULPD __m128d _mm_mul_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
4-148 Vol. 2B
MULPD—Multiply Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
MULPS—Multiply Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 59 /r
MULPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 59 /r
VMULPS xmm1,xmm2, xmm3/m128
VEX.NDS.256.0F.WIG 59 /r
VMULPS ymm1, ymm2, ymm3/m256
EVEX.NDS.128.0F.W0 59 /r
VMULPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 59 /r
VMULPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 59 /r
VMULPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst {er}
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Multiply packed single-precision floating-point values in
xmm2/m128 with xmm1 and store result in xmm1.
Multiply packed single-precision floating-point values in
xmm3/m128 with xmm2 and store result in xmm1.
Multiply packed single-precision floating-point values in
ymm3/m256 with ymm2 and store result in ymm1.
Multiply packed single-precision floating-point values
from xmm3/m128/m32bcst to xmm2 and store result in
xmm1.
Multiply packed single-precision floating-point values
from ymm3/m256/m32bcst to ymm2 and store result in
ymm1.
Multiply packed single-precision floating-point values in
zmm3/m512/m32bcst with zmm2 and store result in
zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Multiply the packed single-precision floating-point values from the first source operand with the corresponding
values in the second source operand, and stores the packed double-precision floating-point results in the destination operand.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the
corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the destination YMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
MULPS—Multiply Packed Single-Precision Floating-Point Values
Vol. 2B 4-149
INSTRUCTION SET REFERENCE, M-U
Operation
VMULPS (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] SRC1[i+31:i] * SRC2[31:0]
ELSE
DEST[i+31:i] SRC1[i+31:i] * SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VMULPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] * SRC2[31:0]
DEST[63:32] SRC1[63:32] * SRC2[63:32]
DEST[95:64] SRC1[95:64] * SRC2[95:64]
DEST[127:96] SRC1[127:96] * SRC2[127:96]
DEST[159:128] SRC1[159:128] * SRC2[159:128]
DEST[191:160]SRC1[191:160] * SRC2[191:160]
DEST[223:192] SRC1[223:192] * SRC2[223:192]
DEST[255:224] SRC1[255:224] * SRC2[255:224].
DEST[MAX_VL-1:256] 0;
VMULPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] * SRC2[31:0]
DEST[63:32] SRC1[63:32] * SRC2[63:32]
DEST[95:64] SRC1[95:64] * SRC2[95:64]
DEST[127:96] SRC1[127:96] * SRC2[127:96]
DEST[MAX_VL-1:128] 0
MULPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] * SRC2[31:0]
DEST[63:32] SRC1[63:32] * SRC2[63:32]
DEST[95:64] SRC1[95:64] * SRC2[95:64]
DEST[127:96] SRC1[127:96] * SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
4-150 Vol. 2B
MULPS—Multiply Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VMULPS __m512 _mm512_mul_ps( __m512 a, __m512 b);
VMULPS __m512 _mm512_mask_mul_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VMULPS __m512 _mm512_maskz_mul_ps(__mmask16 k, __m512 a, __m512 b);
VMULPS __m512 _mm512_mul_round_ps( __m512 a, __m512 b, int);
VMULPS __m512 _mm512_mask_mul_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VMULPS __m512 _mm512_maskz_mul_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VMULPS __m256 _mm256_mask_mul_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VMULPS __m256 _mm256_maskz_mul_ps(__mmask8 k, __m256 a, __m256 b);
VMULPS __m128 _mm_mask_mul_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMULPS __m128 _mm_maskz_mul_ps(__mmask8 k, __m128 a, __m128 b);
VMULPS __m256 _mm256_mul_ps (__m256 a, __m256 b);
MULPS __m128 _mm_mul_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
MULPS—Multiply Packed Single-Precision Floating-Point Values
Vol. 2B 4-151
INSTRUCTION SET REFERENCE, M-U
MULSD—Multiply Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 59 /r
MULSD xmm1,xmm2/m64
VEX.NDS.128.F2.0F.WIG 59 /r
VMULSD xmm1,xmm2, xmm3/m64
RVM
V/V
AVX
EVEX.NDS.LIG.F2.0F.W1 59 /r
VMULSD xmm1 {k1}{z}, xmm2,
xmm3/m64 {er}
T1S
V/V
AVX512F
Description
Multiply the low double-precision floating-point value in
xmm2/m64 by low double-precision floating-point
value in xmm1.
Multiply the low double-precision floating-point value in
xmm3/m64 by low double-precision floating-point
value in xmm2.
Multiply the low double-precision floating-point value in
xmm3/m64 by low double-precision floating-point
value in xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Multiplies the low double-precision floating-point value in the second source operand by the low double-precision
floating-point value in the first source operand, and stores the double-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source
operand and the destination operands are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL1:64) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The quadword at bits 127:64 of the destination operand is copied from the
same bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VMULSD is encoded with VEX.L=0. Encoding VMULSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
4-152 Vol. 2B
MULSD—Multiply Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Operation
VMULSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] SRC1[63:0] * SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI
FI;
ENDFOR
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VMULSD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] * SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
MULSD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] * SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMULSD __m128d _mm_mask_mul_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VMULSD __m128d _mm_maskz_mul_sd( __mmask8 k, __m128d a, __m128d b);
VMULSD __m128d _mm_mul_round_sd( __m128d a, __m128d b, int);
VMULSD __m128d _mm_mask_mul_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMULSD __m128d _mm_maskz_mul_round_sd( __mmask8 k, __m128d a, __m128d b, int);
MULSD __m128d _mm_mul_sd (__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
MULSD—Multiply Scalar Double-Precision Floating-Point Value
Vol. 2B 4-153
INSTRUCTION SET REFERENCE, M-U
MULSS—Multiply Scalar Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 59 /r
MULSS xmm1,xmm2/m32
VEX.NDS.128.F3.0F.WIG 59 /r
VMULSS xmm1,xmm2, xmm3/m32
RVM
V/V
AVX
EVEX.NDS.LIG.F3.0F.W0 59 /r
VMULSS xmm1 {k1}{z}, xmm2,
xmm3/m32 {er}
T1S
V/V
AVX512F
Description
Multiply the low single-precision floating-point value in
xmm2/m32 by the low single-precision floating-point
value in xmm1.
Multiply the low single-precision floating-point value in
xmm3/m32 by the low single-precision floating-point
value in xmm2.
Multiply the low single-precision floating-point value in
xmm3/m32 by the low single-precision floating-point
value in xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Multiplies the low single-precision floating-point value from the second source operand by the low single-precision
floating-point value in the first source operand, and stores the single-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 32-bit memory location. The first source
operand and the destination operands are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three
high-order doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
4-154 Vol. 2B
MULSS—Multiply Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
VMULSS (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] SRC1[31:0] * SRC2[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI
FI;
ENDFOR
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VMULSS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] * SRC2[31:0]
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
MULSS (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0] * SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);
VMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);
VMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MULSS __m128 _mm_mul_ss(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
Underflow, Overflow, Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
MULSS—Multiply Scalar Single-Precision Floating-Point Values
Vol. 2B 4-155
INSTRUCTION SET REFERENCE, M-U
MULX — Unsigned Multiply Without Affecting Flags
Opcode/
Instruction
Op/
En
RVM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI2
VEX.NDD.LZ.F2.0F38.W0 F6 /r
MULX r32a, r32b, r/m32
VEX.NDD.LZ.F2.0F38.W1 F6 /r
MULX r64a, r64b, r/m64
RVM
V/N.E.
BMI2
Description
Unsigned multiply of r/m32 with EDX without affecting arithmetic
flags.
Unsigned multiply of r/m64 with RDX without affecting arithmetic
flags.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (w)
ModRM:r/m (r)
RDX/EDX is implied 64/32 bits
source
Description
Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand
(the third operand) and stores the low half of the result in the second destination (second operand), the high half
of the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This
enables efficient programming where the software can interleave add with carry operations and multiplications.
If the first and second operand are identical, it will contain the high half of the multiplication result.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
// DEST1: ModRM:reg
// DEST2: VEX.vvvv
IF (OperandSize = 32)
SRC1 ← EDX;
DEST2 ← (SRC1*SRC2)[31:0];
DEST1 ← (SRC1*SRC2)[63:32];
ELSE IF (OperandSize = 64)
SRC1 ← RDX;
DEST2 ← (SRC1*SRC2)[63:0];
DEST1 ← (SRC1*SRC2)[127:64];
FI
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language when possible.
unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);
unsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);
SIMD Floating-Point Exceptions
None
4-156 Vol. 2B
MULX — Unsigned Multiply Without Affecting Flags
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
MULX — Unsigned Multiply Without Affecting Flags
Vol. 2B 4-157
INSTRUCTION SET REFERENCE, M-U
MWAIT—Monitor Wait
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 C9
MWAIT
NP
Valid
Valid
A hint that allow the processor to stop
instruction execution and enter an
implementation-dependent optimized state
until occurrence of a class of events.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
MWAIT instruction provides hints to allow the processor to enter an implementation-dependent optimized state.
There are two principal targeted usages: address-range monitor and advanced power management. Both usages
of MWAIT require the use of the MONITOR instruction.
CPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,
MWAIT may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode
exception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE
MSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate an invalid-opcode exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized
state the processor should enter. The first processors to implement MWAIT supported only the zero value for EAX
and ECX. Later processors allowed setting ECX[0] to enable masked interrupts as break events for MWAIT (see
below). Software can use the CPUID instruction to determine the extensions and hints supported by the processor.
MWAIT for Address Range Monitoring
For address-range monitoring, the MWAIT instruction operates with the MONITOR instruction. The two instructions
allow the definition of an address at which to wait (MONITOR) and a implementation-dependent-optimized operation to commence at the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it can enter
an implementation-dependent-optimized state while waiting for an event or a store operation to the address range
armed by MONITOR.
The following cause the processor to exit the implementation-dependent-optimized state: a store to the address
range armed by the MONITOR instruction, an NMI or SMI, a debug exception, a machine check exception, the
BINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events may also cause
the processor to exit the implementation-dependent-optimized state.
In addition, an external interrupt causes the processor to exit the implementation-dependent-optimized state
either (1) if the interrupt would be delivered to software (e.g., as it would be if HLT had been executed instead of
MWAIT); or (2) if ECX[0] = 1. Software can execute MWAIT with ECX[0] = 1 only if CPUID.05H:ECX[bit 1] = 1.
(Implementation-specific conditions may result in an interrupt causing the processor to exit the implementationdependent-optimized state even if interrupts are masked and ECX[0] = 0.)
Following exit from the implementation-dependent-optimized state, control passes to the instruction following the
MWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before
execution of that instruction. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the
MWAIT instruction following the handling of an SMI.
If the preceding MONITOR instruction did not successfully arm an address range or if the MONITOR instruction has
not been executed prior to executing MWAIT, then the processor will not enter the implementation-dependent-optimized state. Execution will resume at the instruction following the MWAIT.
4-158 Vol. 2B
MWAIT—Monitor Wait
INSTRUCTION SET REFERENCE, M-U
MWAIT for Power Management
MWAIT accepts a hint and optional extension to the processor that it can enter a specified target C state while
waiting for an event or a store operation to the address range armed by MONITOR. Support for MWAIT extensions
for power management is indicated by CPUID.05H:ECX[bit 0] reporting 1.
EAX and ECX are used to communicate the additional information to the MWAIT instruction, such as the kind of
optimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may
contain hints such as the preferred optimized state the processor should enter. Implementation-specific conditions
may cause a processor to ignore the hint and enter a different optimized state. Future processor implementations
may implement several optimized “waiting” states and will select among those states based on the hint argument.
Table 4-10 describes the meaning of ECX and EAX registers for MWAIT extensions.
Table 4-10. MWAIT Extension Register (ECX)
Bits
Description
0
Treat interrupts as break events even if masked (e.g., even if EFLAGS.IF=0). May be set only if
CPUID.05H:ECX[bit 1] = 1.
31: 1
Reserved
Table 4-11. MWAIT Hints Register (EAX)
Bits
Description
3:0
Sub C-state within a C-state, indicated by bits [7:4]
7:4
Target C-state*
Value of 0 means C1; 1 means C2 and so on
Value of 01111B means C0
Note: Target C states for MWAIT extensions are processor-specific C-states, not ACPI C-states
Reserved
31: 8
Note that if MWAIT is used to enter any of the C-states that are numerically higher than C1, a store to the address
range armed by the MONITOR instruction will cause the processor to exit MWAIT only if the store was originated by
other processor agents. A store from non-processor agent might not cause the processor to exit MWAIT in such
cases.
For additional details of MWAIT extensions, see Chapter 14, “Power and Thermal Management,” of Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A.
Operation
(* MWAIT takes the argument in EAX as a hint extension and is architected to take the argument in ECX as an instruction extension
MWAIT EAX, ECX *)
{
WHILE ( (“Monitor Hardware is in armed state”)) {
implementation_dependent_optimized_state(EAX, ECX); }
Set the state of Monitor Hardware as triggered;
}
Intel C/C++ Compiler Intrinsic Equivalent
MWAIT:
void _mm_mwait(unsigned extensions, unsigned hints)
MWAIT—Monitor Wait
Vol. 2B 4-159
INSTRUCTION SET REFERENCE, M-U
Example
MONITOR/MWAIT instruction pair must be coded in the same loop because execution of the MWAIT instruction will
trigger the monitor hardware. It is not a proper usage to execute MONITOR once and then execute MWAIT in a
loop. Setting up MONITOR without executing MWAIT has no adverse effects.
Typically the MONITOR/MWAIT pair is used in a sequence, such as:
EAX = Logical Address(Trigger)
ECX = 0 (*Hints *)
EDX = 0 (* Hints *)
IF ( !trigger_store_happened) {
MONITOR EAX, ECX, EDX
IF ( !trigger_store_happened ) {
MWAIT EAX, ECX
}
}
The above code sequence makes sure that a triggering store does not happen between the first check of the trigger
and the execution of the monitor instruction. Without the second check that triggering store would go un-noticed.
Typical usage of MONITOR and MWAIT would have the above code sequence within a loop.
Numeric Exceptions
None
Protected Mode Exceptions
#GP(0)
If ECX[31:1] ≠ 0.
If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
#UD
If CPUID.01H:ECX.MONITOR[bit 3] = 0.
If current privilege level is not 0.
Real Address Mode Exceptions
#GP
If ECX[31:1] ≠ 0.
If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
#UD
If CPUID.01H:ECX.MONITOR[bit 3] = 0.
Virtual 8086 Mode Exceptions
#UD
The MWAIT instruction is not recognized in virtual-8086 mode (even if
CPUID.01H:ECX.MONITOR[bit 3] = 1).
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If RCX[63:1] ≠ 0.
If RCX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
#UD
If the current privilege level is not 0.
If CPUID.01H:ECX.MONITOR[bit 3] = 0.
4-160 Vol. 2B
MWAIT—Monitor Wait
INSTRUCTION SET REFERENCE, M-U
NEG—Two's Complement Negation
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F6 /3
NEG r/m8
M
Valid
Valid
REX + F6 /3
NEG r/m8*
M
Valid
N.E.
Two's complement negate r/m8.
F7 /3
NEG r/m16
M
Valid
Valid
Two's complement negate r/m16.
F7 /3
NEG r/m32
M
Valid
Valid
Two's complement negate r/m32.
REX.W + F7 /3
NEG r/m64
M
Valid
N.E.
Two's complement negate r/m64.
Two's complement negate r/m8.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r, w)
NA
NA
NA
Description
Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent
to subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory
location.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
IF DEST = 0
THEN CF ← 0;
ELSE CF ← 1;
FI;
DEST ← [– (DEST)]
Flags Affected
The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set
according to the result.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
NEG—Two's Complement Negation
Vol. 2B 4-161
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
4-162 Vol. 2B
NEG—Two's Complement Negation
INSTRUCTION SET REFERENCE, M-U
NOP—No Operation
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
90
NOP
NP
Valid
Valid
One byte no-operation instruction.
0F 1F /0
NOP r/m16
M
Valid
Valid
Multi-byte no-operation instruction.
0F 1F /0
NOP r/m32
M
Valid
Valid
Multi-byte no-operation instruction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
M
ModRM:r/m (r)
NA
NA
NA
Description
This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction
stream but does not impact machine context, except for the EIP register.
The multi-byte form of NOP is available on processors with model encoding:
•
CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B
The multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The
instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.
The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode
exception on processors that do not support the multi-byte NOP instruction.
The memory operand form of the instruction allows software to create a byte sequence of “no operation” as one
instruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and
64-bit mode) are:
Table 4-12. Recommended Multi-Byte Sequence of NOP Instruction
Length
Assembly
Byte Sequence
2 bytes
66 NOP
66 90H
3 bytes
NOP DWORD ptr [EAX]
0F 1F 00H
4 bytes
NOP DWORD ptr [EAX + 00H]
0F 1F 40 00H
5 bytes
NOP DWORD ptr [EAX + EAX*1 + 00H]
0F 1F 44 00 00H
6 bytes
66 NOP DWORD ptr [EAX + EAX*1 + 00H]
66 0F 1F 44 00 00H
7 bytes
NOP DWORD ptr [EAX + 00000000H]
0F 1F 80 00 00 00 00H
8 bytes
NOP DWORD ptr [EAX + EAX*1 + 00000000H]
0F 1F 84 00 00 00 00 00H
9 bytes
66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]
66 0F 1F 84 00 00 00 00 00H
Flags Affected
None
Exceptions (All Operating Modes)
#UD
NOP—No Operation
If the LOCK prefix is used.
Vol. 2B 4-163
INSTRUCTION SET REFERENCE, M-U
NOT—One's Complement Negation
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F6 /2
NOT r/m8
M
Valid
Valid
Reverse each bit of r/m8.
REX + F6 /2
NOT r/m8*
M
Valid
N.E.
Reverse each bit of r/m8.
F7 /2
NOT r/m16
M
Valid
Valid
Reverse each bit of r/m16.
F7 /2
NOT r/m32
M
Valid
Valid
Reverse each bit of r/m32.
REX.W + F7 /2
NOT r/m64
M
Valid
N.E.
Reverse each bit of r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r, w)
NA
NA
NA
Description
Performs a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores
the result in the destination operand location. The destination operand can be a register or a memory location.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← NOT DEST;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
4-164 Vol. 2B
NOT—One's Complement Negation
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
NOT—One's Complement Negation
Vol. 2B 4-165
INSTRUCTION SET REFERENCE, M-U
OR—Logical Inclusive OR
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0C ib
OR AL, imm8
I
Valid
Valid
AL OR imm8.
0D iw
OR AX, imm16
I
Valid
Valid
AX OR imm16.
0D id
OR EAX, imm32
I
Valid
Valid
EAX OR imm32.
REX.W + 0D id
OR RAX, imm32
I
Valid
N.E.
RAX OR imm32 (sign-extended).
80 /1 ib
OR r/m8, imm8
MI
Valid
Valid
r/m8 OR imm8.
REX + 80 /1 ib
OR r/m8*, imm8
MI
Valid
N.E.
r/m8 OR imm8.
81 /1 iw
OR r/m16, imm16
MI
Valid
Valid
r/m16 OR imm16.
81 /1 id
OR r/m32, imm32
MI
Valid
Valid
r/m32 OR imm32.
REX.W + 81 /1 id
OR r/m64, imm32
MI
Valid
N.E.
r/m64 OR imm32 (sign-extended).
83 /1 ib
OR r/m16, imm8
MI
Valid
Valid
r/m16 OR imm8 (sign-extended).
83 /1 ib
OR r/m32, imm8
MI
Valid
Valid
r/m32 OR imm8 (sign-extended).
REX.W + 83 /1 ib
OR r/m64, imm8
MI
Valid
N.E.
r/m64 OR imm8 (sign-extended).
08 /r
OR r/m8, r8
MR
Valid
Valid
r/m8 OR r8.
REX + 08 /r
OR r/m8*, r8*
MR
Valid
N.E.
r/m8 OR r8.
09 /r
OR r/m16, r16
MR
Valid
Valid
r/m16 OR r16.
09 /r
OR r/m32, r32
MR
Valid
Valid
r/m32 OR r32.
REX.W + 09 /r
OR r/m64, r64
MR
Valid
N.E.
r/m64 OR r64.
0A /r
OR r8, r/m8
RM
Valid
Valid
r8 OR r/m8.
REX + 0A /r
OR r8*, r/m8*
RM
Valid
N.E.
r8 OR r/m8.
0B /r
OR r16, r/m16
RM
Valid
Valid
r16 OR r/m16.
0B /r
OR r32, r/m32
RM
Valid
Valid
r32 OR r/m32.
REX.W + 0B /r
OR r64, r/m64
RM
Valid
N.E.
r64 OR r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
I
AL/AX/EAX/RAX
imm8/16/32
NA
NA
MI
ModRM:r/m (r, w)
imm8/16/32
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores
the result in the destination operand location. The source operand can be an immediate, a register, or a memory
location; the destination operand can be a register or a memory location. (However, two memory operands cannot
be used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the
first and second operands are 0; otherwise, each bit is set to 1.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
4-166 Vol. 2B
OR—Logical Inclusive OR
INSTRUCTION SET REFERENCE, M-U
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← DEST OR SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is
undefined.
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
OR—Logical Inclusive OR
Vol. 2B 4-167
INSTRUCTION SET REFERENCE, M-U
ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 56/r
ORPD xmm1, xmm2/m128
VEX.NDS.128.66.0F 56 /r
VORPD xmm1,xmm2, xmm3/m128
VEX.NDS.256.66.0F 56 /r
VORPD ymm1, ymm2, ymm3/m256
EVEX.NDS.128.66.0F.W1 56 /r
VORPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 56 /r
VORPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 56 /r
VORPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Return the bitwise logical OR of packed double-precision
floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical OR of packed double-precision
floating-point values in xmm2 and xmm3/mem.
Return the bitwise logical OR of packed double-precision
floating-point values in ymm2 and ymm3/mem.
Return the bitwise logical OR of packed double-precision
floating-point values in xmm2 and xmm3/m128/m64bcst
subject to writemask k1.
Return the bitwise logical OR of packed double-precision
floating-point values in ymm2 and ymm3/m256/m64bcst
subject to writemask k1.
Return the bitwise logical OR of packed double-precision
floating-point values in zmm2 and zmm3/m512/m64bcst
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical OR of the two, four or eight packed double-precision floating-point values from the first
source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
4-168 Vol. 2B
ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
VORPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] SRC1[i+63:i] BITWISE OR SRC2[63:0]
ELSE
DEST[i+63:i] SRC1[i+63:i] BITWISE OR SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VORPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] BITWISE OR SRC2[63:0]
DEST[127:64] SRC1[127:64] BITWISE OR SRC2[127:64]
DEST[191:128] SRC1[191:128] BITWISE OR SRC2[191:128]
DEST[255:192] SRC1[255:192] BITWISE OR SRC2[255:192]
DEST[MAX_VL-1:256] 0
VORPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] BITWISE OR SRC2[63:0]
DEST[127:64] SRC1[127:64] BITWISE OR SRC2[127:64]
DEST[MAX_VL-1:128] 0
ORPD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] BITWISE OR SRC[63:0]
DEST[127:64] DEST[127:64] BITWISE OR SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VORPD __m512d _mm512_or_pd ( __m512d a, __m512d b);
VORPD __m512d _mm512_mask_or_pd ( __m512d s, __mmask8 k, __m512d a, __m512d b);
VORPD __m512d _mm512_maskz_or_pd (__mmask8 k, __m512d a, __m512d b);
VORPD __m256d _mm256_mask_or_pd (__m256d s, ___mmask8 k, __m256d a, __m256d b);
VORPD __m256d _mm256_maskz_or_pd (__mmask8 k, __m256d a, __m256d b);
VORPD __m128d _mm_mask_or_pd ( __m128d s, __mmask8 k, __m128d a, __m128d b);
VORPD __m128d _mm_maskz_or_pd (__mmask8 k, __m128d a, __m128d b);
VORPD __m256d _mm256_or_pd (__m256d a, __m256d b);
ORPD __m128d _mm_or_pd (__m128d a, __m128d b);
ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values
Vol. 2B 4-169
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
4-170 Vol. 2B
ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 56 /r
ORPS xmm1, xmm2/m128
VEX.NDS.128.0F 56 /r
VORPS xmm1,xmm2, xmm3/m128
VEX.NDS.256.0F 56 /r
VORPS ymm1, ymm2, ymm3/m256
EVEX.NDS.128.0F.W0 56 /r
VORPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 56 /r
VORPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 56 /r
VORPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Return the bitwise logical OR of packed single-precision
floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical OR of packed single-precision
floating-point values in xmm2 and xmm3/mem.
Return the bitwise logical OR of packed single-precision
floating-point values in ymm2 and ymm3/mem.
Return the bitwise logical OR of packed single-precision
floating-point values in xmm2 and xmm3/m128/m32bcst
subject to writemask k1.
Return the bitwise logical OR of packed single-precision
floating-point values in ymm2 and ymm3/m256/m32bcst
subject to writemask k1.
Return the bitwise logical OR of packed single-precision
floating-point values in zmm2 and zmm3/m512/m32bcst
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical OR of the four, eight or sixteen packed single-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values
Vol. 2B 4-171
INSTRUCTION SET REFERENCE, M-U
Operation
VORPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] SRC1[i+31:i] BITWISE OR SRC2[31:0]
ELSE
DEST[i+31:i] SRC1[i+31:i] BITWISE OR SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VORPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[159:128] SRC1[159:128] BITWISE OR SRC2[159:128]
DEST[191:160] SRC1[191:160] BITWISE OR SRC2[191:160]
DEST[223:192] SRC1[223:192] BITWISE OR SRC2[223:192]
DEST[255:224] SRC1[255:224] BITWISE OR SRC2[255:224].
DEST[MAX_VL-1:256] 0
VORPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[MAX_VL-1:128] 0
ORPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
4-172 Vol. 2B
ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VORPS __m512 _mm512_or_ps ( __m512 a, __m512 b);
VORPS __m512 _mm512_mask_or_ps ( __m512 s, __mmask16 k, __m512 a, __m512 b);
VORPS __m512 _mm512_maskz_or_ps (__mmask16 k, __m512 a, __m512 b);
VORPS __m256 _mm256_mask_or_ps (__m256 s, ___mmask8 k, __m256 a, __m256 b);
VORPS __m256 _mm256_maskz_or_ps (__mmask8 k, __m256 a, __m256 b);
VORPS __m128 _mm_mask_or_ps ( __m128 s, __mmask8 k, __m128 a, __m128 b);
VORPS __m128 _mm_maskz_or_ps (__mmask8 k, __m128 a, __m128 b);
VORPS __m256 _mm256_or_ps (__m256 a, __m256 b);
ORPS __m128 _mm_or_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values
Vol. 2B 4-173
INSTRUCTION SET REFERENCE, M-U
OUT—Output to Port
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
E6 ib
OUT imm8, AL
I
Valid
Valid
Output byte in AL to I/O port address imm8.
E7 ib
OUT imm8, AX
I
Valid
Valid
Output word in AX to I/O port address imm8.
E7 ib
OUT imm8, EAX
I
Valid
Valid
Output doubleword in EAX to I/O port address
imm8.
EE
OUT DX, AL
NP
Valid
Valid
Output byte in AL to I/O port address in DX.
EF
OUT DX, AX
NP
Valid
Valid
Output word in AX to I/O port address in DX.
EF
OUT DX, EAX
NP
Valid
Valid
Output doubleword in EAX to I/O port address
in DX.
NOTES:
* See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
I
imm8
NA
NA
NA
NP
NA
NA
NA
NA
Description
Copies the value from the second operand (source operand) to the I/O port specified with the destination operand
(first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being
accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register.
Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source
operand allows I/O ports from 0 to 65,535 to be accessed.
The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size
attribute of the instruction for a 16- or 32-bit I/O port.
At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits
of the port address will be 0.
This instruction is only useful for accessing I/O ports located in the processor’s I/O address space. See Chapter 18,
“Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IA-32 Architecture Compatibility
After executing an OUT instruction, the Pentium® processor ensures that the EWBE# pin has been sampled active
before it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active,
but it will not be executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the
EWBE# pin.
4-174 Vol. 2B
OUT—Output to Port
INSTRUCTION SET REFERENCE, M-U
Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
IF (Any I/O Permission Bit for I/O port being accessed = 1)
THEN (* I/O operation is not allowed *)
#GP(0);
ELSE ( * I/O operation is allowed *)
DEST ← SRC; (* Writes to selected I/O port *)
FI;
ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *)
DEST ← SRC; (* Writes to selected I/O port *)
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as protected mode exceptions.
64-Bit Mode Exceptions
Same as protected mode exceptions.
OUT—Output to Port
Vol. 2B 4-175
INSTRUCTION SET REFERENCE, M-U
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
6E
OUTS DX, m8
NP
Valid
Valid
Output byte from memory location specified
in DS:(E)SI or RSI to I/O port specified in DX**.
6F
OUTS DX, m16
NP
Valid
Valid
Output word from memory location specified
in DS:(E)SI or RSI to I/O port specified in DX**.
6F
OUTS DX, m32
NP
Valid
Valid
Output doubleword from memory location
specified in DS:(E)SI or RSI to I/O port specified
in DX**.
6E
OUTSB
NP
Valid
Valid
Output byte from memory location specified
in DS:(E)SI or RSI to I/O port specified in DX**.
6F
OUTSW
NP
Valid
Valid
Output word from memory location specified
in DS:(E)SI or RSI to I/O port specified in DX**.
6F
OUTSD
NP
Valid
Valid
Output doubleword from memory location
specified in DS:(E)SI or RSI to I/O port specified
in DX**.
NOTES:
* See IA-32 Architecture Compatibility section below.
** In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address sizes are supported. In non-64-bit mode, only 32-bit (ESI) and 16-bit (SI)
address sizes are supported.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Copies data from the source operand (second operand) to the I/O port specified with the destination operand (first
operand). The source operand is a memory location, the address of which is read from either the DS:SI, DS:ESI or
the RSI registers (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The DS
segment may be overridden with a segment override prefix.) The destination operand is an I/O port address (from
0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source
and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the
instruction for a 16- or 32-bit I/O port.
At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands” form and the “nooperands” form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination
operands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O
port and the source address, and the destination operand must be DX. This explicit-operands form is provided to
allow documentation; however, note that the documentation provided by this form can be misleading. That is, the
source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does
not have to specify the correct location. The location is always specified by the DS:(E)SI or RSI registers, which
must be loaded correctly before the OUTS instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the OUTS instructions.
Here also DS:(E)SI is assumed to be the source operand and DX is assumed to be the destination operand. The size
of the I/O port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).
After the byte, word, or doubleword is transferred from the memory location to the I/O port, the SI/ESI/RSI
register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register.
(If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI register is decremented.)
The SI/ESI/RSI register is incremented or decremented by 1 for byte operations, by 2 for word operations, and by
4 for doubleword operations.
4-176 Vol. 2B
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port
INSTRUCTION SET REFERENCE, M-U
The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix for block input of ECX
bytes, words, or doublewords. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in this
chapter for a description of the REP prefix. This instruction is only useful for accessing I/O ports located in the
processor’s I/O address space. See Chapter 18, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.
In 64-bit mode, the default operand size is 32 bits; operand size is not promoted by the use of REX.W. In 64-bit
mode, the default address size is 64 bits, and 64-bit address is specified using RSI by default. 32-bit address using
ESI is support using the prefix 67H, but 16-bit address is not supported in 64-bit mode.
IA-32 Architecture Compatibility
After executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentium processor ensures that the EWBE#
pin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be
prefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the
Pentium processor family has the EWBE# pin.
For the Pentium 4, Intel® Xeon®, and P6 processor family, upon execution of an OUTS, OUTSB, OUTSW, or OUTSD
instruction, the processor will not execute the next instruction until the data phase of the transaction is complete.
Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
IF (Any I/O Permission Bit for I/O port being accessed = 1)
THEN (* I/O operation is not allowed *)
#GP(0);
ELSE (* I/O operation is allowed *)
DEST ← SRC; (* Writes to I/O port *)
FI;
ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL ≤ IOPL *)
DEST ← SRC; (* Writes to I/O port *)
FI;
Byte transfer:
IF 64-bit mode
Then
IF 64-Bit Address Size
THEN
IF DF = 0
THEN RSI ← RSI RSI + 1;
ELSE RSI ← RSI or – 1;
FI;
ELSE (* 32-Bit Address Size *)
IF DF = 0
THEN
ESI ← ESI + 1;
ELSE
ESI ← ESI – 1;
FI;
FI;
ELSE
IF DF = 0
THEN
(E)SI ← (E)SI + 1;
ELSE (E)SI ← (E)SI – 1;
FI;
FI;
Word transfer:
IF 64-bit mode
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port
Vol. 2B 4-177
INSTRUCTION SET REFERENCE, M-U
Then
IF 64-Bit Address Size
THEN
IF DF = 0
THEN RSI ← RSI RSI + 2;
ELSE RSI ← RSI or – 2;
FI;
ELSE (* 32-Bit Address Size *)
IF DF = 0
THEN
ESI ← ESI + 2;
ELSE
ESI ← ESI – 2;
FI;
FI;
ELSE
IF DF = 0
THEN
(E)SI ← (E)SI + 2;
ELSE (E)SI ← (E)SI – 2;
FI;
FI;
Doubleword transfer:
IF 64-bit mode
Then
IF 64-Bit Address Size
THEN
IF DF = 0
THEN RSI ← RSI RSI + 4;
ELSE RSI ← RSI or – 4;
FI;
ELSE (* 32-Bit Address Size *)
IF DF = 0
THEN
ESI ← ESI + 4;
ELSE
ESI ← ESI – 4;
FI;
FI;
ELSE
IF DF = 0
THEN
(E)SI ← (E)SI + 4;
ELSE (E)SI ← (E)SI – 4;
FI;
FI;
Flags Affected
None
4-178 Vol. 2B
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#GP(0)
If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
If a memory operand effective address is outside the limit of the CS, DS, ES, FS, or GS
segment.
If the segment register contains a NULL segment selector.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port
Vol. 2B 4-179
INSTRUCTION SET REFERENCE, M-U
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 1C /r1
RM
V/V
SSSE3
Compute the absolute value of bytes in
mm2/m64 and store UNSIGNED result in mm1.
RM
V/V
SSSE3
Compute the absolute value of bytes in
xmm2/m128 and store UNSIGNED result in
xmm1.
RM
V/V
SSSE3
Compute the absolute value of 16-bit integers
in mm2/m64 and store UNSIGNED result in
mm1.
RM
V/V
SSSE3
Compute the absolute value of 16-bit integers
in xmm2/m128 and store UNSIGNED result in
xmm1.
RM
V/V
SSSE3
Compute the absolute value of 32-bit integers
in mm2/m64 and store UNSIGNED result in
mm1.
RM
V/V
SSSE3
Compute the absolute value of 32-bit integers
in xmm2/m128 and store UNSIGNED result in
xmm1.
RM
V/V
AVX
Compute the absolute value of bytes in
xmm2/m128 and store UNSIGNED result in
xmm1.
RM
V/V
AVX
Compute the absolute value of 16- bit
integers in xmm2/m128 and store UNSIGNED
result in xmm1.
RM
V/V
AVX
Compute the absolute value of 32- bit
integers in xmm2/m128 and store UNSIGNED
result in xmm1.
VEX.256.66.0F38.WIG 1C /r
VPABSB ymm1, ymm2/m256
RM
V/V
AVX2
Compute the absolute value of bytes in
ymm2/m256 and store UNSIGNED result in
ymm1.
VEX.256.66.0F38.WIG 1D /r
RM
V/V
AVX2
Compute the absolute value of 16-bit integers
in ymm2/m256 and store UNSIGNED result in
ymm1.
RM
V/V
AVX2
Compute the absolute value of 32-bit integers
in ymm2/m256 and store UNSIGNED result in
ymm1.
PABSB mm1, mm2/m64
66 0F 38 1C /r
PABSB xmm1, xmm2/m128
0F 38 1D /r1
PABSW mm1, mm2/m64
66 0F 38 1D /r
PABSW xmm1, xmm2/m128
0F 38 1E /r1
PABSD mm1, mm2/m64
66 0F 38 1E /r
PABSD xmm1, xmm2/m128
VEX.128.66.0F38.WIG 1C /r
VPABSB xmm1, xmm2/m128
VEX.128.66.0F38.WIG 1D /r
VPABSW xmm1, xmm2/m128
VEX.128.66.0F38.WIG 1E /r
VPABSD xmm1, xmm2/m128
VPABSW ymm1, ymm2/m256
VEX.256.66.0F38.WIG 1E /r
VPABSD ymm1, ymm2/m256
EVEX.128.66.0F38.WIG 1C /r
VPABSB xmm1 {k1}{z}, xmm2/m128
FVM V/V
AVX512VL Compute the absolute value of bytes in
AVX512BW xmm2/m128 and store UNSIGNED result in
xmm1 using writemask k1.
EVEX.256.66.0F38.WIG 1C /r
VPABSB ymm1 {k1}{z}, ymm2/m256
FVM V/V
AVX512VL Compute the absolute value of bytes in
AVX512BW ymm2/m256 and store UNSIGNED result in
ymm1 using writemask k1.
EVEX.512.66.0F38.WIG 1C /r
VPABSB zmm1 {k1}{z}, zmm2/m512
FVM V/V
AVX512BW Compute the absolute value of bytes in
zmm2/m512 and store UNSIGNED result in
zmm1 using writemask k1.
EVEX.128.66.0F38.WIG 1D /r
VPABSW xmm1 {k1}{z}, xmm2/m128
FVM V/V
AVX512VL Compute the absolute value of 16-bit integers
AVX512BW in xmm2/m128 and store UNSIGNED result in
xmm1 using writemask k1.
4-180 Vol. 2B
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value
INSTRUCTION SET REFERENCE, M-U
EVEX.256.66.0F38.WIG 1D /r
VPABSW ymm1 {k1}{z}, ymm2/m256
FVM V/V
AVX512VL Compute the absolute value of 16-bit integers
AVX512BW in ymm2/m256 and store UNSIGNED result in
ymm1 using writemask k1.
EVEX.512.66.0F38.WIG 1D /r
VPABSW zmm1 {k1}{z}, zmm2/m512
FVM V/V
AVX512BW Compute the absolute value of 16-bit integers
in zmm2/m512 and store UNSIGNED result in
zmm1 using writemask k1.
EVEX.128.66.0F38.W0 1E /r
VPABSD xmm1 {k1}{z}, xmm2/m128/m32bcst
FV
V/V
AVX512VL Compute the absolute value of 32-bit integers
AVX512F
in xmm2/m128/m32bcst and store UNSIGNED
result in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 1E /r
VPABSD ymm1 {k1}{z}, ymm2/m256/m32bcst
FV
V/V
AVX512VL Compute the absolute value of 32-bit integers
AVX512F
in ymm2/m256/m32bcst and store UNSIGNED
result in ymm1 using writemask k1.
VPABSD zmm1 {k1}{z}, zmm2/m512/m32bcst
FV
V/V
AVX512F
EVEX.128.66.0F38.W1 1F /r
VPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcst
FV
V/V
AVX512VL Compute the absolute value of 64-bit integers
AVX512F
in xmm2/m128/m64bcst and store UNSIGNED
result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 1F /r
VPABSQ ymm1 {k1}{z}, ymm2/m256/m64bcst
FV
V/V
AVX512VL Compute the absolute value of 64-bit integers
AVX512F
in ymm2/m256/m64bcst and store UNSIGNED
result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 1F /r
VPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst
FV
V/V
AVX512F
Compute the absolute value of 32-bit integers
in zmm2/m512/m32bcst and store UNSIGNED
result in zmm1 using writemask k1.
Compute the absolute value of 64-bit integers
in zmm2/m512/m64bcst and store UNSIGNED
result in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FVM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
PABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and
stores the UNSIGNED results in the destination operand (the first operand). PABSB operates on signed bytes,
PABSW operates on signed 16-bit words, and PABSD operates on signed 32-bit integers.
EVEX encoded VPABSD/Q: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location,
or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
EVEX encoded VPABSB/W: The source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.
VEX.256 encoded versions: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded versions: The source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value
Vol. 2B 4-181
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The source operand can be an XMM register or an 128-bit memory location. The destination is an XMM register. The upper bits (VL_MAX-1:128) of the corresponding register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
Operation
PABSB with 128 bit operands:
Unsigned DEST[7:0] ABS(SRC[7: 0])
Repeat operation for 2nd through 15th bytes
Unsigned DEST[127:120] ABS(SRC[127:120])
VPABSB with 128 bit operands:
Unsigned DEST[7:0] ABS(SRC[7: 0])
Repeat operation for 2nd through 15th bytes
Unsigned DEST[127:120]ABS(SRC[127:120])
VPABSB with 256 bit operands:
Unsigned DEST[7:0]ABS(SRC[7: 0])
Repeat operation for 2nd through 31st bytes
Unsigned DEST[255:248]ABS(SRC[255:248])
VPABSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN
Unsigned DEST[i+7:i] ABS(SRC[i+7:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PABSW with 128 bit operands:
Unsigned DEST[15:0]ABS(SRC[15:0])
Repeat operation for 2nd through 7th 16-bit words
Unsigned DEST[127:112]ABS(SRC[127:112])
VPABSW with 128 bit operands:
Unsigned DEST[15:0] ABS(SRC[15:0])
Repeat operation for 2nd through 7th 16-bit words
Unsigned DEST[127:112]ABS(SRC[127:112])
VPABSW with 256 bit operands:
Unsigned DEST[15:0]ABS(SRC[15:0])
Repeat operation for 2nd through 15th 16-bit words
Unsigned DEST[255:240] ABS(SRC[255:240])
4-182 Vol. 2B
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value
INSTRUCTION SET REFERENCE, M-U
VPABSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
Unsigned DEST[i+15:i] ABS(SRC[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PABSD with 128 bit operands:
Unsigned DEST[31:0]ABS(SRC[31:0])
Repeat operation for 2nd through 3rd 32-bit double words
Unsigned DEST[127:96]ABS(SRC[127:96])
VPABSD with 128 bit operands:
Unsigned DEST[31:0]ABS(SRC[31:0])
Repeat operation for 2nd through 3rd 32-bit double words
Unsigned DEST[127:96]ABS(SRC[127:96])
VPABSD with 256 bit operands:
Unsigned DEST[31:0] ABS(SRC[31:0])
Repeat operation for 2nd through 7th 32-bit double words
Unsigned DEST[255:224] ABS(SRC[255:224])
VPABSD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
Unsigned DEST[i+31:i] ABS(SRC[31:0])
ELSE
Unsigned DEST[i+31:i] ABS(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value
Vol. 2B 4-183
INSTRUCTION SET REFERENCE, M-U
VPABSQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
Unsigned DEST[i+63:i] ABS(SRC[63:0])
ELSE
Unsigned DEST[i+63:i] ABS(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPABSB__m512i _mm512_abs_epi8 ( __m512i a)
VPABSW__m512i _mm512_abs_epi16 ( __m512i a)
VPABSB__m512i _mm512_mask_abs_epi8 ( __m512i s, __mmask64 m, __m512i a)
VPABSW__m512i _mm512_mask_abs_epi16 ( __m512i s, __mmask32 m, __m512i a)
VPABSB__m512i _mm512_maskz_abs_epi8 (__mmask64 m, __m512i a)
VPABSW__m512i _mm512_maskz_abs_epi16 (__mmask32 m, __m512i a)
VPABSB__m256i _mm256_mask_abs_epi8 (__m256i s, __mmask32 m, __m256i a)
VPABSW__m256i _mm256_mask_abs_epi16 (__m256i s, __mmask16 m, __m256i a)
VPABSB__m256i _mm256_maskz_abs_epi8 (__mmask32 m, __m256i a)
VPABSW__m256i _mm256_maskz_abs_epi16 (__mmask16 m, __m256i a)
VPABSB__m128i _mm_mask_abs_epi8 (__m128i s, __mmask16 m, __m128i a)
VPABSW__m128i _mm_mask_abs_epi16 (__m128i s, __mmask8 m, __m128i a)
VPABSB__m128i _mm_maskz_abs_epi8 (__mmask16 m, __m128i a)
VPABSW__m128i _mm_maskz_abs_epi16 (__mmask8 m, __m128i a)
VPABSD __m256i _mm256_mask_abs_epi32(__m256i s, __mmask8 k, __m256i a);
VPABSD __m256i _mm256_maskz_abs_epi32( __mmask8 k, __m256i a);
VPABSD __m128i _mm_mask_abs_epi32(__m128i s, __mmask8 k, __m128i a);
VPABSD __m128i _mm_maskz_abs_epi32( __mmask8 k, __m128i a);
VPABSD __m512i _mm512_abs_epi32( __m512i a);
VPABSD __m512i _mm512_mask_abs_epi32(__m512i s, __mmask16 k, __m512i a);
VPABSD __m512i _mm512_maskz_abs_epi32( __mmask16 k, __m512i a);
VPABSQ __m512i _mm512_abs_epi64( __m512i a);
VPABSQ __m512i _mm512_mask_abs_epi64(__m512i s, __mmask8 k, __m512i a);
VPABSQ __m512i _mm512_maskz_abs_epi64( __mmask8 k, __m512i a);
VPABSQ __m256i _mm256_mask_abs_epi64(__m256i s, __mmask8 k, __m256i a);
VPABSQ __m256i _mm256_maskz_abs_epi64( __mmask8 k, __m256i a);
VPABSQ __m128i _mm_mask_abs_epi64(__m128i s, __mmask8 k, __m128i a);
VPABSQ __m128i _mm_maskz_abs_epi64( __mmask8 k, __m128i a);
PABSB __m128i _mm_abs_epi8 (__m128i a)
VPABSB __m128i _mm_abs_epi8 (__m128i a)
4-184 Vol. 2B
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value
INSTRUCTION SET REFERENCE, M-U
VPABSB __m256i _mm256_abs_epi8 (__m256i a)
PABSW __m128i _mm_abs_epi16 (__m128i a)
VPABSW __m128i _mm_abs_epi16 (__m128i a)
VPABSW __m256i _mm256_abs_epi16 (__m256i a)
PABSD __m128i _mm_abs_epi32 (__m128i a)
VPABSD __m128i _mm_abs_epi32 (__m128i a)
VPABSD __m256i _mm256_abs_epi32 (__m256i a)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPABSD/Q, see Exceptions Type E4.
EVEX-encoded VPABSB/W, see Exceptions Type E4.nb.
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value
Vol. 2B 4-185
INSTRUCTION SET REFERENCE, M-U
PACKSSWB/PACKSSDW—Pack with Signed Saturation
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Description
Feature Flag
0F 63 /r1
RM
V/V
MMX
Converts 4 packed signed word integers from
mm1 and from mm2/m64 into 8 packed
signed byte integers in mm1 using signed
saturation.
RM
V/V
SSE2
Converts 8 packed signed word integers from
xmm1 and from xxm2/m128 into 16 packed
signed byte integers in xxm1 using signed
saturation.
RM
V/V
MMX
Converts 2 packed signed doubleword
integers from mm1 and from mm2/m64 into 4
packed signed word integers in mm1 using
signed saturation.
RM
V/V
SSE2
Converts 4 packed signed doubleword
integers from xmm1 and from xxm2/m128
into 8 packed signed word integers in xxm1
using signed saturation.
RVM V/V
AVX
Converts 8 packed signed word integers from
xmm2 and from xmm3/m128 into 16 packed
signed byte integers in xmm1 using signed
saturation.
RVM V/V
AVX
Converts 4 packed signed doubleword
integers from xmm2 and from xmm3/m128
into 8 packed signed word integers in xmm1
using signed saturation.
RVM V/V
AVX2
Converts 16 packed signed word integers
from ymm2 and from ymm3/m256 into 32
packed signed byte integers in ymm1 using
signed saturation.
RVM V/V
AVX2
Converts 8 packed signed doubleword
integers from ymm2 and from ymm3/m256
into 16 packed signed word integers in
ymm1using signed saturation.
EVEX.NDS.128.66.0F.WIG 63 /r
VPACKSSWB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Converts packed signed word integers from
xmm2 and from xmm3/m128 into packed
signed byte integers in xmm1 using signed
saturation under writemask k1.
EVEX.NDS.256.66.0F.WIG 63 /r
VPACKSSWB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Converts packed signed word integers from
ymm2 and from ymm3/m256 into packed
signed byte integers in ymm1 using signed
saturation under writemask k1.
EVEX.NDS.512.66.0F.WIG 63 /r
VPACKSSWB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Converts packed signed word integers from
zmm2 and from zmm3/m512 into packed
signed byte integers in zmm1 using signed
saturation under writemask k1.
EVEX.NDS.128.66.0F.W0 6B /r
VPACKSSDW xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
AVX512VL
AVX512BW
Converts packed signed doubleword integers
from xmm2 and from xmm3/m128/m32bcst
into packed signed word integers in xmm1
using signed saturation under writemask k1.
PACKSSWB mm1, mm2/m64
66 0F 63 /r
PACKSSWB xmm1, xmm2/m128
0F 6B /r1
PACKSSDW mm1, mm2/m64
66 0F 6B /r
PACKSSDW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 63 /r
VPACKSSWB xmm1,xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 6B /r
VPACKSSDW xmm1,xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 63 /r
VPACKSSWB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG 6B /r
VPACKSSDW ymm1, ymm2, ymm3/m256
4-186 Vol. 2B
V/V
PACKSSWB/PACKSSDW—Pack with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.256.66.0F.W0 6B /r
VPACKSSDW ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512BW
Converts packed signed doubleword integers
from ymm2 and from ymm3/m256/m32bcst
into packed signed word integers in ymm1
using signed saturation under writemask k1.
EVEX.NDS.512.66.0F.W0 6B /r
VPACKSSDW zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512BW
Converts packed signed doubleword integers
from zmm2 and from zmm3/m512/m32bcst
into packed signed word integers in zmm1
using signed saturation under writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Converts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed
doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow conditions. See Figure 4-6 for an example of the packing operation.
64-Bit SRC
D
64-Bit DEST
C
B
D’
C’
B’
A
A’
64-Bit DEST
Figure 4-6. Operation of the PACKSSDW Instruction Using 64-bit Operands
PACKSSWB converts packed signed word integers in the first and second source operands into packed signed byte
integers using signed saturation to handle overflow conditions beyond the range of signed byte integers. If the
signed doubleword value is beyond the range of an unsigned word (i.e. greater than 7FH or less than 80H), the
saturated signed byte integer value of 7FH or 80H, respectively, is stored in the destination. PACKSSDW converts
packed signed doubleword integers in the first and second source operands into packed signed word integers using
signed saturation to handle overflow conditions beyond 7FFFH and 8000H.
EVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register, updated conditional under the writemask k1.
EVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the
writemask k1.
PACKSSWB/PACKSSDW—Pack with Signed Saturation
Vol. 2B 4-187
INSTRUCTION SET REFERENCE, M-U
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM destination register destination are unmodified.
Operation
PACKSSWB instruction (128-bit Legacy SSE version)
DEST[7:0] SaturateSignedWordToSignedByte (DEST[15:0]);
DEST[15:8] SaturateSignedWordToSignedByte (DEST[31:16]);
DEST[23:16] SaturateSignedWordToSignedByte (DEST[47:32]);
DEST[31:24] SaturateSignedWordToSignedByte (DEST[63:48]);
DEST[39:32] SaturateSignedWordToSignedByte (DEST[79:64]);
DEST[47:40] SaturateSignedWordToSignedByte (DEST[95:80]);
DEST[55:48] SaturateSignedWordToSignedByte (DEST[111:96]);
DEST[63:56] SaturateSignedWordToSignedByte (DEST[127:112]);
DEST[71:64] SaturateSignedWordToSignedByte (SRC[15:0]);
DEST[79:72] SaturateSignedWordToSignedByte (SRC[31:16]);
DEST[87:80] SaturateSignedWordToSignedByte (SRC[47:32]);
DEST[95:88] SaturateSignedWordToSignedByte (SRC[63:48]);
DEST[103:96] SaturateSignedWordToSignedByte (SRC[79:64]);
DEST[111:104] SaturateSignedWordToSignedByte (SRC[95:80]);
DEST[119:112] SaturateSignedWordToSignedByte (SRC[111:96]);
DEST[127:120] SaturateSignedWordToSignedByte (SRC[127:112]);
DEST[MAX_VL-1:128] (Unmodified)
PACKSSDW instruction (128-bit Legacy SSE version)
DEST[15:0] SaturateSignedDwordToSignedWord (DEST[31:0]);
DEST[31:16] SaturateSignedDwordToSignedWord (DEST[63:32]);
DEST[47:32] SaturateSignedDwordToSignedWord (DEST[95:64]);
DEST[63:48] SaturateSignedDwordToSignedWord (DEST[127:96]);
DEST[79:64] SaturateSignedDwordToSignedWord (SRC[31:0]);
DEST[95:80] SaturateSignedDwordToSignedWord (SRC[63:32]);
DEST[111:96] SaturateSignedDwordToSignedWord (SRC[95:64]);
DEST[127:112] SaturateSignedDwordToSignedWord (SRC[127:96]);
DEST[MAX_VL-1:128] (Unmodified)
4-188 Vol. 2B
PACKSSWB/PACKSSDW—Pack with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
VPACKSSWB instruction (VEX.128 encoded version)
DEST[7:0] SaturateSignedWordToSignedByte (SRC1[15:0]);
DEST[15:8] SaturateSignedWordToSignedByte (SRC1[31:16]);
DEST[23:16] SaturateSignedWordToSignedByte (SRC1[47:32]);
DEST[31:24] SaturateSignedWordToSignedByte (SRC1[63:48]);
DEST[39:32] SaturateSignedWordToSignedByte (SRC1[79:64]);
DEST[47:40] SaturateSignedWordToSignedByte (SRC1[95:80]);
DEST[55:48] SaturateSignedWordToSignedByte (SRC1[111:96]);
DEST[63:56] SaturateSignedWordToSignedByte (SRC1[127:112]);
DEST[71:64] SaturateSignedWordToSignedByte (SRC2[15:0]);
DEST[79:72] SaturateSignedWordToSignedByte (SRC2[31:16]);
DEST[87:80] SaturateSignedWordToSignedByte (SRC2[47:32]);
DEST[95:88] SaturateSignedWordToSignedByte (SRC2[63:48]);
DEST[103:96] SaturateSignedWordToSignedByte (SRC2[79:64]);
DEST[111:104] SaturateSignedWordToSignedByte (SRC2[95:80]);
DEST[119:112] SaturateSignedWordToSignedByte (SRC2[111:96]);
DEST[127:120] SaturateSignedWordToSignedByte (SRC2[127:112]);
DEST[MAX_VL-1:128] 0;
VPACKSSDW instruction (VEX.128 encoded version)
DEST[15:0] SaturateSignedDwordToSignedWord (SRC1[31:0]);
DEST[31:16] SaturateSignedDwordToSignedWord (SRC1[63:32]);
DEST[47:32] SaturateSignedDwordToSignedWord (SRC1[95:64]);
DEST[63:48] SaturateSignedDwordToSignedWord (SRC1[127:96]);
DEST[79:64] SaturateSignedDwordToSignedWord (SRC2[31:0]);
DEST[95:80] SaturateSignedDwordToSignedWord (SRC2[63:32]);
DEST[111:96] SaturateSignedDwordToSignedWord (SRC2[95:64]);
DEST[127:112] SaturateSignedDwordToSignedWord (SRC2[127:96]);
DEST[MAX_VL-1:128] 0;
VPACKSSWB instruction (VEX.256 encoded version)
DEST[7:0] SaturateSignedWordToSignedByte (SRC1[15:0]);
DEST[15:8] SaturateSignedWordToSignedByte (SRC1[31:16]);
DEST[23:16] SaturateSignedWordToSignedByte (SRC1[47:32]);
DEST[31:24] SaturateSignedWordToSignedByte (SRC1[63:48]);
DEST[39:32] SaturateSignedWordToSignedByte (SRC1[79:64]);
DEST[47:40] SaturateSignedWordToSignedByte (SRC1[95:80]);
DEST[55:48] SaturateSignedWordToSignedByte (SRC1[111:96]);
DEST[63:56] SaturateSignedWordToSignedByte (SRC1[127:112]);
DEST[71:64] SaturateSignedWordToSignedByte (SRC2[15:0]);
DEST[79:72] SaturateSignedWordToSignedByte (SRC2[31:16]);
DEST[87:80] SaturateSignedWordToSignedByte (SRC2[47:32]);
DEST[95:88] SaturateSignedWordToSignedByte (SRC2[63:48]);
DEST[103:96] SaturateSignedWordToSignedByte (SRC2[79:64]);
DEST[111:104] SaturateSignedWordToSignedByte (SRC2[95:80]);
DEST[119:112] SaturateSignedWordToSignedByte (SRC2[111:96]);
DEST[127:120] SaturateSignedWordToSignedByte (SRC2[127:112]);
DEST[135:128] SaturateSignedWordToSignedByte (SRC1[143:128]);
DEST[143:136] SaturateSignedWordToSignedByte (SRC1[159:144]);
DEST[151:144] SaturateSignedWordToSignedByte (SRC1[175:160]);
DEST[159:152] SaturateSignedWordToSignedByte (SRC1[191:176]);
DEST[167:160] SaturateSignedWordToSignedByte (SRC1[207:192]);
DEST[175:168] SaturateSignedWordToSignedByte (SRC1[223:208]);
DEST[183:176] SaturateSignedWordToSignedByte (SRC1[239:224]);
PACKSSWB/PACKSSDW—Pack with Signed Saturation
Vol. 2B 4-189
INSTRUCTION SET REFERENCE, M-U
DEST[191:184] SaturateSignedWordToSignedByte (SRC1[255:240]);
DEST[199:192] SaturateSignedWordToSignedByte (SRC2[143:128]);
DEST[207:200] SaturateSignedWordToSignedByte (SRC2[159:144]);
DEST[215:208] SaturateSignedWordToSignedByte (SRC2[175:160]);
DEST[223:216] SaturateSignedWordToSignedByte (SRC2[191:176]);
DEST[231:224] SaturateSignedWordToSignedByte (SRC2[207:192]);
DEST[239:232] SaturateSignedWordToSignedByte (SRC2[223:208]);
DEST[247:240] SaturateSignedWordToSignedByte (SRC2[239:224]);
DEST[255:248] SaturateSignedWordToSignedByte (SRC2[255:240]);
DEST[MAX_VL-1:256] 0;
VPACKSSDW instruction (VEX.256 encoded version)
DEST[15:0] SaturateSignedDwordToSignedWord (SRC1[31:0]);
DEST[31:16] SaturateSignedDwordToSignedWord (SRC1[63:32]);
DEST[47:32] SaturateSignedDwordToSignedWord (SRC1[95:64]);
DEST[63:48] SaturateSignedDwordToSignedWord (SRC1[127:96]);
DEST[79:64] SaturateSignedDwordToSignedWord (SRC2[31:0]);
DEST[95:80] SaturateSignedDwordToSignedWord (SRC2[63:32]);
DEST[111:96] SaturateSignedDwordToSignedWord (SRC2[95:64]);
DEST[127:112] SaturateSignedDwordToSignedWord (SRC2[127:96]);
DEST[143:128] SaturateSignedDwordToSignedWord (SRC1[159:128]);
DEST[159:144] SaturateSignedDwordToSignedWord (SRC1[191:160]);
DEST[175:160] SaturateSignedDwordToSignedWord (SRC1[223:192]);
DEST[191:176] SaturateSignedDwordToSignedWord (SRC1[255:224]);
DEST[207:192] SaturateSignedDwordToSignedWord (SRC2[159:128]);
DEST[223:208] SaturateSignedDwordToSignedWord (SRC2[191:160]);
DEST[239:224] SaturateSignedDwordToSignedWord (SRC2[223:192]);
DEST[255:240] SaturateSignedDwordToSignedWord (SRC2[255:224]);
DEST[MAX_VL-1:256] 0;
VPACKSSWB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
TMP_DEST[7:0] SaturateSignedWordToSignedByte (SRC1[15:0]);
TMP_DEST[15:8] SaturateSignedWordToSignedByte (SRC1[31:16]);
TMP_DEST[23:16] SaturateSignedWordToSignedByte (SRC1[47:32]);
TMP_DEST[31:24] SaturateSignedWordToSignedByte (SRC1[63:48]);
TMP_DEST[39:32] SaturateSignedWordToSignedByte (SRC1[79:64]);
TMP_DEST[47:40] SaturateSignedWordToSignedByte (SRC1[95:80]);
TMP_DEST[55:48] SaturateSignedWordToSignedByte (SRC1[111:96]);
TMP_DEST[63:56] SaturateSignedWordToSignedByte (SRC1[127:112]);
TMP_DEST[71:64] SaturateSignedWordToSignedByte (SRC2[15:0]);
TMP_DEST[79:72] SaturateSignedWordToSignedByte (SRC2[31:16]);
TMP_DEST[87:80] SaturateSignedWordToSignedByte (SRC2[47:32]);
TMP_DEST[95:88] SaturateSignedWordToSignedByte (SRC2[63:48]);
TMP_DEST[103:96] SaturateSignedWordToSignedByte (SRC2[79:64]);
TMP_DEST[111:104] SaturateSignedWordToSignedByte (SRC2[95:80]);
TMP_DEST[119:112] SaturateSignedWordToSignedByte (SRC2[111:96]);
TMP_DEST[127:120] SaturateSignedWordToSignedByte (SRC2[127:112]);
IF VL >= 256
TMP_DEST[135:128] SaturateSignedWordToSignedByte (SRC1[143:128]);
TMP_DEST[143:136] SaturateSignedWordToSignedByte (SRC1[159:144]);
TMP_DEST[151:144] SaturateSignedWordToSignedByte (SRC1[175:160]);
TMP_DEST[159:152] SaturateSignedWordToSignedByte (SRC1[191:176]);
TMP_DEST[167:160] SaturateSignedWordToSignedByte (SRC1[207:192]);
4-190 Vol. 2B
PACKSSWB/PACKSSDW—Pack with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
TMP_DEST[175:168] SaturateSignedWordToSignedByte (SRC1[223:208]);
TMP_DEST[183:176] SaturateSignedWordToSignedByte (SRC1[239:224]);
TMP_DEST[191:184] SaturateSignedWordToSignedByte (SRC1[255:240]);
TMP_DEST[199:192] SaturateSignedWordToSignedByte (SRC2[143:128]);
TMP_DEST[207:200] SaturateSignedWordToSignedByte (SRC2[159:144]);
TMP_DEST[215:208] SaturateSignedWordToSignedByte (SRC2[175:160]);
TMP_DEST[223:216] SaturateSignedWordToSignedByte (SRC2[191:176]);
TMP_DEST[231:224] SaturateSignedWordToSignedByte (SRC2[207:192]);
TMP_DEST[239:232] SaturateSignedWordToSignedByte (SRC2[223:208]);
TMP_DEST[247:240] SaturateSignedWordToSignedByte (SRC2[239:224]);
TMP_DEST[255:248] SaturateSignedWordToSignedByte (SRC2[255:240]);
FI;
IF VL >= 512
TMP_DEST[263:256] SaturateSignedWordToSignedByte (SRC1[271:256]);
TMP_DEST[271:264] SaturateSignedWordToSignedByte (SRC1[287:272]);
TMP_DEST[279:272] SaturateSignedWordToSignedByte (SRC1[303:288]);
TMP_DEST[287:280] SaturateSignedWordToSignedByte (SRC1[319:304]);
TMP_DEST[295:288] SaturateSignedWordToSignedByte (SRC1[335:320]);
TMP_DEST[303:296] SaturateSignedWordToSignedByte (SRC1[351:336]);
TMP_DEST[311:304] SaturateSignedWordToSignedByte (SRC1[367:352]);
TMP_DEST[319:312] SaturateSignedWordToSignedByte (SRC1[383:368]);
TMP_DEST[327:320] SaturateSignedWordToSignedByte (SRC2[271:256]);
TMP_DEST[335:328] SaturateSignedWordToSignedByte (SRC2[287:272]);
TMP_DEST[343:336] SaturateSignedWordToSignedByte (SRC2[303:288]);
TMP_DEST[351:344] SaturateSignedWordToSignedByte (SRC2[319:304]);
TMP_DEST[359:352] SaturateSignedWordToSignedByte (SRC2[335:320]);
TMP_DEST[367:360] SaturateSignedWordToSignedByte (SRC2[351:336]);
TMP_DEST[375:368] SaturateSignedWordToSignedByte (SRC2[367:352]);
TMP_DEST[383:376] SaturateSignedWordToSignedByte (SRC2[383:368]);
TMP_DEST[391:384] SaturateSignedWordToSignedByte (SRC1[399:384]);
TMP_DEST[399:392] SaturateSignedWordToSignedByte (SRC1[415:400]);
TMP_DEST[407:400] SaturateSignedWordToSignedByte (SRC1[431:416]);
TMP_DEST[415:408] SaturateSignedWordToSignedByte (SRC1[447:432]);
TMP_DEST[423:416] SaturateSignedWordToSignedByte (SRC1[463:448]);
TMP_DEST[431:424] SaturateSignedWordToSignedByte (SRC1[479:464]);
TMP_DEST[439:432] SaturateSignedWordToSignedByte (SRC1[495:480]);
TMP_DEST[447:440] SaturateSignedWordToSignedByte (SRC1[511:496]);
TMP_DEST[455:448] SaturateSignedWordToSignedByte (SRC2[399:384]);
TMP_DEST[463:456] SaturateSignedWordToSignedByte (SRC2[415:400]);
TMP_DEST[471:464] SaturateSignedWordToSignedByte (SRC2[431:416]);
TMP_DEST[479:472] SaturateSignedWordToSignedByte (SRC2[447:432]);
TMP_DEST[487:480] SaturateSignedWordToSignedByte (SRC2[463:448]);
TMP_DEST[495:488] SaturateSignedWordToSignedByte (SRC2[479:464]);
TMP_DEST[503:496] SaturateSignedWordToSignedByte (SRC2[495:480]);
TMP_DEST[511:504] SaturateSignedWordToSignedByte (SRC2[511:496]);
FI;
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN
DEST[i+7:i] TMP_DEST[i+7:i]
PACKSSWB/PACKSSDW—Pack with Signed Saturation
Vol. 2B 4-191
INSTRUCTION SET REFERENCE, M-U
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPACKSSDW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO ((KL/2) - 1)
i j * 32
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
TMP_SRC2[i+31:i] SRC2[31:0]
ELSE
TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
TMP_DEST[15:0] SaturateSignedDwordToSignedWord (SRC1[31:0]);
TMP_DEST[31:16] SaturateSignedDwordToSignedWord (SRC1[63:32]);
TMP_DEST[47:32] SaturateSignedDwordToSignedWord (SRC1[95:64]);
TMP_DEST[63:48] SaturateSignedDwordToSignedWord (SRC1[127:96]);
TMP_DEST[79:64] SaturateSignedDwordToSignedWord (TMP_SRC2[31:0]);
TMP_DEST[95:80] SaturateSignedDwordToSignedWord (TMP_SRC2[63:32]);
TMP_DEST[111:96] SaturateSignedDwordToSignedWord (TMP_SRC2[95:64]);
TMP_DEST[127:112] SaturateSignedDwordToSignedWord (TMP_SRC2[127:96]);
IF VL >= 256
TMP_DEST[143:128] SaturateSignedDwordToSignedWord (SRC1[159:128]);
TMP_DEST[159:144] SaturateSignedDwordToSignedWord (SRC1[191:160]);
TMP_DEST[175:160] SaturateSignedDwordToSignedWord (SRC1[223:192]);
TMP_DEST[191:176] SaturateSignedDwordToSignedWord (SRC1[255:224]);
TMP_DEST[207:192] SaturateSignedDwordToSignedWord (TMP_SRC2[159:128]);
TMP_DEST[223:208] SaturateSignedDwordToSignedWord (TMP_SRC2[191:160]);
TMP_DEST[239:224] SaturateSignedDwordToSignedWord (TMP_SRC2[223:192]);
TMP_DEST[255:240] SaturateSignedDwordToSignedWord (TMP_SRC2[255:224]);
FI;
IF VL >= 512
TMP_DEST[271:256] SaturateSignedDwordToSignedWord (SRC1[287:256]);
TMP_DEST[287:272] SaturateSignedDwordToSignedWord (SRC1[319:288]);
TMP_DEST[303:288] SaturateSignedDwordToSignedWord (SRC1[351:320]);
TMP_DEST[319:304] SaturateSignedDwordToSignedWord (SRC1[383:352]);
TMP_DEST[335:320] SaturateSignedDwordToSignedWord (TMP_SRC2[287:256]);
TMP_DEST[351:336] SaturateSignedDwordToSignedWord (TMP_SRC2[319:288]);
TMP_DEST[367:352] SaturateSignedDwordToSignedWord (TMP_SRC2[351:320]);
TMP_DEST[383:368] SaturateSignedDwordToSignedWord (TMP_SRC2[383:352]);
TMP_DEST[399:384] SaturateSignedDwordToSignedWord (SRC1[415:384]);
TMP_DEST[415:400] SaturateSignedDwordToSignedWord (SRC1[447:416]);
TMP_DEST[431:416] SaturateSignedDwordToSignedWord (SRC1[479:448]);
4-192 Vol. 2B
PACKSSWB/PACKSSDW—Pack with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
TMP_DEST[447:432] SaturateSignedDwordToSignedWord (SRC1[511:480]);
TMP_DEST[463:448] SaturateSignedDwordToSignedWord (TMP_SRC2[415:384]);
TMP_DEST[479:464] SaturateSignedDwordToSignedWord (TMP_SRC2[447:416]);
TMP_DEST[495:480] SaturateSignedDwordToSignedWord (TMP_SRC2[479:448]);
TMP_DEST[511:496] SaturateSignedDwordToSignedWord (TMP_SRC2[511:480]);
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPACKSSDW__m512i _mm512_packs_epi32(__m512i m1, __m512i m2);
VPACKSSDW__m512i _mm512_mask_packs_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);
VPACKSSDW__m512i _mm512_maskz_packs_epi32( __mmask32 k, __m512i m1, __m512i m2);
VPACKSSDW__m256i _mm256_mask_packs_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);
VPACKSSDW__m256i _mm256_maskz_packs_epi32( __mmask16 k, __m256i m1, __m256i m2);
VPACKSSDW__m128i _mm_mask_packs_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);
VPACKSSDW__m128i _mm_maskz_packs_epi32( __mmask8 k, __m128i m1, __m128i m2);
VPACKSSWB__m512i _mm512_packs_epi16(__m512i m1, __m512i m2);
VPACKSSWB__m512i _mm512_mask_packs_epi16(__m512i s, __mmask32 k, __m512i m1, __m512i m2);
VPACKSSWB__m512i _mm512_maskz_packs_epi16( __mmask32 k, __m512i m1, __m512i m2);
VPACKSSWB__m256i _mm256_mask_packs_epi16( __m256i s, __mmask16 k, __m256i m1, __m256i m2);
VPACKSSWB__m256i _mm256_maskz_packs_epi16( __mmask16 k, __m256i m1, __m256i m2);
VPACKSSWB__m128i _mm_mask_packs_epi16( __m128i s, __mmask8 k, __m128i m1, __m128i m2);
VPACKSSWB__m128i _mm_maskz_packs_epi16( __mmask8 k, __m128i m1, __m128i m2);
PACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)
PACKSSDW __m128i _mm_packs_epi32(__m128i m1, __m128i m2)
VPACKSSWB __m256i _mm256_packs_epi16(__m256i m1, __m256i m2)
VPACKSSDW __m256i _mm256_packs_epi32(__m256i m1, __m256i m2)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPACKSSDW, see Exceptions Type E4NF.
EVEX-encoded VPACKSSWB, see Exceptions Type E4NF.nb.
PACKSSWB/PACKSSDW—Pack with Signed Saturation
Vol. 2B 4-193
INSTRUCTION SET REFERENCE, M-U
PACKUSDW—Pack with Unsigned Saturation
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0F 38 2B /r
PACKUSDW xmm1, xmm2/m128
VEX.NDS.128.66.0F38 2B /r
VPACKUSDW xmm1,xmm2,
xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F38 2B /r
VPACKUSDW ymm1, ymm2,
ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.W0 2B /r
VPACKUSDW xmm1{k1}{z},
xmm2, xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512BW
EVEX.NDS.256.66.0F38.W0 2B /r
FV
V/V
AVX512VL
AVX512BW
EVEX.NDS.512.66.0F38.W0 2B /r
VPACKUSDW zmm1{k1}{z},
zmm2, zmm3/m512/m32bcst
FV
V/V
AVX512BW
Description
Convert 4 packed signed doubleword integers from xmm1
and 4 packed signed doubleword integers from
xmm2/m128 into 8 packed unsigned word integers in
xmm1 using unsigned saturation.
Convert 4 packed signed doubleword integers from xmm2
and 4 packed signed doubleword integers from
xmm3/m128 into 8 packed unsigned word integers in
xmm1 using unsigned saturation.
Convert 8 packed signed doubleword integers from ymm2
and 8 packed signed doubleword integers from
ymm3/m256 into 16 packed unsigned word integers in
ymm1 using unsigned saturation.
Convert packed signed doubleword integers from xmm2
and packed signed doubleword integers from
xmm3/m128/m32bcst into packed unsigned word integers
in xmm1 using unsigned saturation under writemask k1.
Convert packed signed doubleword integers from ymm2
and packed signed doubleword integers from
ymm3/m256/m32bcst into packed unsigned word integers
in ymm1 using unsigned saturation under writemask k1.
Convert packed signed doubleword integers from zmm2
and packed signed doubleword integers from
zmm3/m512/m32bcst into packed unsigned word integers
in zmm1 using unsigned saturation under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Converts packed signed doubleword integers in the first and second source operands into packed unsigned word
integers using unsigned saturation to handle overflow conditions. If the signed doubleword value is beyond the
range of an unsigned word (that is, greater than FFFFH or less than 0000H), the saturated unsigned word integer
value of FFFFH or 0000H, respectively, is stored in the destination.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32bit memory location. The destination operand is a ZMM register, updated conditionally under the writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding destination register destination are unmodified.
4-194 Vol. 2B
PACKUSDW—Pack with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
Operation
PACKUSDW (Legacy SSE instruction)
TMP[15:0] (DEST[31:0] < 0) ? 0 : DEST[15:0];
DEST[15:0] (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] (DEST[63:32] < 0) ? 0 : DEST[47:32];
DEST[31:16] (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] (DEST[95:64] < 0) ? 0 : DEST[79:64];
DEST[47:32] (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] (DEST[127:96] < 0) ? 0 : DEST[111:96];
DEST[63:48] (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] (SRC[31:0] < 0) ? 0 : SRC[15:0];
DEST[79:64] (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] (SRC[63:32] < 0) ? 0 : SRC[47:32];
DEST[95:80] (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] (SRC[95:64] < 0) ? 0 : SRC[79:64];
DEST[111:96] (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] (SRC[127:96] < 0) ? 0 : SRC[111:96];
DEST[127:112] (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
DEST[MAX_VL-1:128] (Unmodified)
PACKUSDW (VEX.128 encoded version)
TMP[15:0] (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] (SRC2[31:0] < 0) ? 0 : SRC2[15:0];
DEST[79:64] (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] (SRC2[63:32] < 0) ? 0 : SRC2[47:32];
DEST[95:80] (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] (SRC2[95:64] < 0) ? 0 : SRC2[79:64];
DEST[111:96] (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] (SRC2[127:96] < 0) ? 0 : SRC2[111:96];
DEST[127:112] (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];
DEST[MAX_VL-1:128] 0;
VPACKUSDW (VEX.256 encoded version)
TMP[15:0] (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] (SRC2[31:0] < 0) ? 0 : SRC2[15:0];
DEST[79:64] (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] (SRC2[63:32] < 0) ? 0 : SRC2[47:32];
DEST[95:80] (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] (SRC2[95:64] < 0) ? 0 : SRC2[79:64];
DEST[111:96] (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
PACKUSDW—Pack with Unsigned Saturation
Vol. 2B 4-195
INSTRUCTION SET REFERENCE, M-U
TMP[127:112] (SRC2[127:96] < 0) ? 0 : SRC2[111:96];
DEST[127:112] (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
TMP[143:128] (SRC1[159:128] < 0) ? 0 : SRC1[143:128];
DEST[143:128] (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;
TMP[159:144] (SRC1[191:160] < 0) ? 0 : SRC1[175:160];
DEST[159:144] (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;
TMP[175:160] (SRC1[223:192] < 0) ? 0 : SRC1[207:192];
DEST[175:160] (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;
TMP[191:176] (SRC1[255:224] < 0) ? 0 : SRC1[239:224];
DEST[191:176] (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;
TMP[207:192] (SRC2[159:128] < 0) ? 0 : SRC2[143:128];
DEST[207:192] (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;
TMP[223:208] (SRC2[191:160] < 0) ? 0 : SRC2[175:160];
DEST[223:208] (SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;
TMP[239:224] (SRC2[223:192] < 0) ? 0 : SRC2[207:192];
DEST[239:224] (SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;
TMP[255:240] (SRC2[255:224] < 0) ? 0 : SRC2[239:224];
DEST[255:240] (SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;
DEST[MAX_VL-1:256] 0;
VPACKUSDW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO ((KL/2) - 1)
i j * 32
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
TMP_SRC2[i+31:i] SRC2[31:0]
ELSE
TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
TMP[15:0] (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] (TMP_SRC2[31:0] < 0) ? 0 : TMP_SRC2[15:0];
DEST[79:64] (TMP_SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] (TMP_SRC2[63:32] < 0) ? 0 : TMP_SRC2[47:32];
DEST[95:80] (TMP_SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] (TMP_SRC2[95:64] < 0) ? 0 : TMP_SRC2[79:64];
DEST[111:96] (TMP_SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] (TMP_SRC2[127:96] < 0) ? 0 : TMP_SRC2[111:96];
DEST[127:112] (TMP_SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
IF VL >= 256
TMP[143:128] (SRC1[159:128] < 0) ? 0 : SRC1[143:128];
DEST[143:128] (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;
TMP[159:144] (SRC1[191:160] < 0) ? 0 : SRC1[175:160];
DEST[159:144] (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;
4-196 Vol. 2B
PACKUSDW—Pack with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
TMP[175:160] (SRC1[223:192] < 0) ? 0 : SRC1[207:192];
DEST[175:160] (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;
TMP[191:176] (SRC1[255:224] < 0) ? 0 : SRC1[239:224];
DEST[191:176] (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;
TMP[207:192] (TMP_SRC2[159:128] < 0) ? 0 : TMP_SRC2[143:128];
DEST[207:192] (TMP_SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;
TMP[223:208] (TMP_SRC2[191:160] < 0) ? 0 : TMP_SRC2[175:160];
DEST[223:208] (TMP_SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;
TMP[239:224] (TMP_SRC2[223:192] < 0) ? 0 : TMP_SRC2[207:192];
DEST[239:224] (TMP_SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;
TMP[255:240] (TMP_SRC2[255:224] < 0) ? 0 : TMP_SRC2[239:224];
DEST[255:240] (TMP_SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;
FI;
IF VL >= 512
TMP[271:256] (SRC1[287:256] < 0) ? 0 : SRC1[271:256];
DEST[271:256] (SRC1[287:256] > FFFFH) ? FFFFH : TMP[271:256] ;
TMP[287:272] (SRC1[319:288] < 0) ? 0 : SRC1[303:288];
DEST[287:272] (SRC1[319:288] > FFFFH) ? FFFFH : TMP[287:272] ;
TMP[303:288] (SRC1[351:320] < 0) ? 0 : SRC1[335:320];
DEST[303:288] (SRC1[351:320] > FFFFH) ? FFFFH : TMP[303:288] ;
TMP[319:304] (SRC1[383:352] < 0) ? 0 : SRC1[367:352];
DEST[319:304] (SRC1[383:352] > FFFFH) ? FFFFH : TMP[319:304] ;
TMP[335:320] (TMP_SRC2[287:256] < 0) ? 0 : TMP_SRC2[271:256];
DEST[335:304] (TMP_SRC2[287:256] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[351:336] (TMP_SRC2[319:288] < 0) ? 0 : TMP_SRC2[303:288];
DEST[351:336] (TMP_SRC2[319:288] > FFFFH) ? FFFFH : TMP[351:336] ;
TMP[367:352] (TMP_SRC2[351:320] < 0) ? 0 : TMP_SRC2[315:320];
DEST[367:352] (TMP_SRC2[351:320] > FFFFH) ? FFFFH : TMP[367:352] ;
TMP[383:368] (TMP_SRC2[383:352] < 0) ? 0 : TMP_SRC2[367:352];
DEST[383:368] (TMP_SRC2[383:352] > FFFFH) ? FFFFH : TMP[383:368] ;
TMP[399:384] (SRC1[415:384] < 0) ? 0 : SRC1[399:384];
DEST[399:384] (SRC1[415:384] > FFFFH) ? FFFFH : TMP[399:384] ;
TMP[415:400] (SRC1[447:416] < 0) ? 0 : SRC1[431:416];
DEST[415:400] (SRC1[447:416] > FFFFH) ? FFFFH : TMP[415:400] ;
TMP[431:416] (SRC1[479:448] < 0) ? 0 : SRC1[463:448];
DEST[431:416] (SRC1[479:448] > FFFFH) ? FFFFH : TMP[431:416] ;
TMP[447:432] (SRC1[511:480] < 0) ? 0 : SRC1[495:480];
DEST[447:432] (SRC1[511:480] > FFFFH) ? FFFFH : TMP[447:432] ;
TMP[463:448] (TMP_SRC2[415:384] < 0) ? 0 : TMP_SRC2[399:384];
DEST[463:448] (TMP_SRC2[415:384] > FFFFH) ? FFFFH : TMP[463:448] ;
TMP[475:464] (TMP_SRC2[447:416] < 0) ? 0 : TMP_SRC2[431:416];
DEST[475:464] (TMP_SRC2[447:416] > FFFFH) ? FFFFH : TMP[475:464] ;
TMP[491:476] (TMP_SRC2[479:448] < 0) ? 0 : TMP_SRC2[463:448];
DEST[491:476] (TMP_SRC2[479:448] > FFFFH) ? FFFFH : TMP[491:476] ;
TMP[511:492] (TMP_SRC2[511:480] < 0) ? 0 : TMP_SRC2[495:480];
DEST[511:492] (TMP_SRC2[511:480] > FFFFH) ? FFFFH : TMP[511:492] ;
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
PACKUSDW—Pack with Unsigned Saturation
Vol. 2B 4-197
INSTRUCTION SET REFERENCE, M-U
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPACKUSDW__m512i _mm512_packus_epi32(__m512i m1, __m512i m2);
VPACKUSDW__m512i _mm512_mask_packus_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);
VPACKUSDW__m512i _mm512_maskz_packus_epi32( __mmask32 k, __m512i m1, __m512i m2);
VPACKUSDW__m256i _mm256_mask_packus_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);
VPACKUSDW__m256i _mm256_maskz_packus_epi32( __mmask16 k, __m256i m1, __m256i m2);
VPACKUSDW__m128i _mm_mask_packus_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);
VPACKUSDW__m128i _mm_maskz_packus_epi32( __mmask8 k, __m128i m1, __m128i m2);
PACKUSDW__m128i _mm_packus_epi32(__m128i m1, __m128i m2);
VPACKUSDW__m256i _mm256_packus_epi32(__m256i m1, __m256i m2);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.
4-198 Vol. 2B
PACKUSDW—Pack with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
PACKUSWB—Pack with Unsigned Saturation
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
Description
CPUID
Feature Flag
0F 67 /r1
RM
V/V
MMX
Converts 4 signed word integers from mm and
4 signed word integers from mm/m64 into 8
unsigned byte integers in mm using unsigned
saturation.
RM
V/V
SSE2
Converts 8 signed word integers from xmm1
and 8 signed word integers from xmm2/m128
into 16 unsigned byte integers in xmm1 using
unsigned saturation.
RVM V/V
AVX
Converts 8 signed word integers from xmm2
and 8 signed word integers from xmm3/m128
into 16 unsigned byte integers in xmm1 using
unsigned saturation.
RVM V/V
AVX2
Converts 16 signed word integers from ymm2
and 16signed word integers from
ymm3/m256 into 32 unsigned byte integers
in ymm1 using unsigned saturation.
EVEX.NDS.128.66.0F.WIG 67 /r
VPACKUSWB xmm1{k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Converts signed word integers from xmm2
and signed word integers from xmm3/m128
into unsigned byte integers in xmm1 using
unsigned saturation under writemask k1.
EVEX.NDS.256.66.0F.WIG 67 /r
VPACKUSWB ymm1{k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Converts signed word integers from ymm2
and signed word integers from ymm3/m256
into unsigned byte integers in ymm1 using
unsigned saturation under writemask k1.
EVEX.NDS.512.66.0F.WIG 67 /r
VPACKUSWB zmm1{k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Converts signed word integers from zmm2
and signed word integers from zmm3/m512
into unsigned byte integers in zmm1 using
unsigned saturation under writemask k1.
PACKUSWB mm, mm/m64
66 0F 67 /r
PACKUSWB xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 67 /r
VPACKUSWB xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 67 /r
VPACKUSWB ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Converts 4, 8, 16 or 32 signed word integers from the destination operand (first operand) and 4, 8, 16 or 32 signed
word integers from the source operand (second operand) into 8, 16, 32 or 64 unsigned byte integers and stores the
result in the destination operand. (See Figure 4-6 for an example of the packing operation.) If a signed word
integer value is beyond the range of an unsigned byte integer (that is, greater than FFH or less than 00H), the saturated unsigned byte integer value of FFH or 00H, respectively, is stored in the destination.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register or a 512-bit memory location. The destination operand is a ZMM register.
PACKUSWB—Pack with Unsigned Saturation
Vol. 2B 4-199
INSTRUCTION SET REFERENCE, M-U
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits
(MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits
(MAX_VL-1:128) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
Operation
PACKUSWB (with 64-bit operands)
DEST[7:0] ← SaturateSignedWordToUnsignedByte DEST[15:0];
DEST[15:8] ← SaturateSignedWordToUnsignedByte DEST[31:16];
DEST[23:16] ← SaturateSignedWordToUnsignedByte DEST[47:32];
DEST[31:24] ← SaturateSignedWordToUnsignedByte DEST[63:48];
DEST[39:32] ← SaturateSignedWordToUnsignedByte SRC[15:0];
DEST[47:40] ← SaturateSignedWordToUnsignedByte SRC[31:16];
DEST[55:48] ← SaturateSignedWordToUnsignedByte SRC[47:32];
DEST[63:56] ← SaturateSignedWordToUnsignedByte SRC[63:48];
PACKUSWB (Legacy SSE instruction)
DEST[7:0]SaturateSignedWordToUnsignedByte (DEST[15:0]);
DEST[15:8] SaturateSignedWordToUnsignedByte (DEST[31:16]);
DEST[23:16] SaturateSignedWordToUnsignedByte (DEST[47:32]);
DEST[31:24] SaturateSignedWordToUnsignedByte (DEST[63:48]);
DEST[39:32] SaturateSignedWordToUnsignedByte (DEST[79:64]);
DEST[47:40] SaturateSignedWordToUnsignedByte (DEST[95:80]);
DEST[55:48] SaturateSignedWordToUnsignedByte (DEST[111:96]);
DEST[63:56] SaturateSignedWordToUnsignedByte (DEST[127:112]);
DEST[71:64] SaturateSignedWordToUnsignedByte (SRC[15:0]);
DEST[79:72] SaturateSignedWordToUnsignedByte (SRC[31:16]);
DEST[87:80] SaturateSignedWordToUnsignedByte (SRC[47:32]);
DEST[95:88] SaturateSignedWordToUnsignedByte (SRC[63:48]);
DEST[103:96] SaturateSignedWordToUnsignedByte (SRC[79:64]);
DEST[111:104] SaturateSignedWordToUnsignedByte (SRC[95:80]);
DEST[119:112] SaturateSignedWordToUnsignedByte (SRC[111:96]);
DEST[127:120] SaturateSignedWordToUnsignedByte (SRC[127:112]);
PACKUSWB (VEX.128 encoded version)
DEST[7:0] SaturateSignedWordToUnsignedByte (SRC1[15:0]);
DEST[15:8] SaturateSignedWordToUnsignedByte (SRC1[31:16]);
DEST[23:16] SaturateSignedWordToUnsignedByte (SRC1[47:32]);
DEST[31:24] SaturateSignedWordToUnsignedByte (SRC1[63:48]);
DEST[39:32] SaturateSignedWordToUnsignedByte (SRC1[79:64]);
DEST[47:40] SaturateSignedWordToUnsignedByte (SRC1[95:80]);
DEST[55:48] SaturateSignedWordToUnsignedByte (SRC1[111:96]);
DEST[63:56] SaturateSignedWordToUnsignedByte (SRC1[127:112]);
DEST[71:64] SaturateSignedWordToUnsignedByte (SRC2[15:0]);
DEST[79:72] SaturateSignedWordToUnsignedByte (SRC2[31:16]);
DEST[87:80] SaturateSignedWordToUnsignedByte (SRC2[47:32]);
DEST[95:88] SaturateSignedWordToUnsignedByte (SRC2[63:48]);
DEST[103:96] SaturateSignedWordToUnsignedByte (SRC2[79:64]);
DEST[111:104] SaturateSignedWordToUnsignedByte (SRC2[95:80]);
4-200 Vol. 2B
PACKUSWB—Pack with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
DEST[119:112] SaturateSignedWordToUnsignedByte (SRC2[111:96]);
DEST[127:120] SaturateSignedWordToUnsignedByte (SRC2[127:112]);
DEST[VLMAX-1:128] 0;
VPACKUSWB (VEX.256 encoded version)
DEST[7:0] SaturateSignedWordToUnsignedByte (SRC1[15:0]);
DEST[15:8] SaturateSignedWordToUnsignedByte (SRC1[31:16]);
DEST[23:16] SaturateSignedWordToUnsignedByte (SRC1[47:32]);
DEST[31:24] SaturateSignedWordToUnsignedByte (SRC1[63:48]);
DEST[39:32] SaturateSignedWordToUnsignedByte (SRC1[79:64]);
DEST[47:40] SaturateSignedWordToUnsignedByte (SRC1[95:80]);
DEST[55:48] SaturateSignedWordToUnsignedByte (SRC1[111:96]);
DEST[63:56] SaturateSignedWordToUnsignedByte (SRC1[127:112]);
DEST[71:64] SaturateSignedWordToUnsignedByte (SRC2[15:0]);
DEST[79:72] SaturateSignedWordToUnsignedByte (SRC2[31:16]);
DEST[87:80] SaturateSignedWordToUnsignedByte (SRC2[47:32]);
DEST[95:88] SaturateSignedWordToUnsignedByte (SRC2[63:48]);
DEST[103:96] SaturateSignedWordToUnsignedByte (SRC2[79:64]);
DEST[111:104] SaturateSignedWordToUnsignedByte (SRC2[95:80]);
DEST[119:112] SaturateSignedWordToUnsignedByte (SRC2[111:96]);
DEST[127:120] SaturateSignedWordToUnsignedByte (SRC2[127:112]);
DEST[135:128] SaturateSignedWordToUnsignedByte (SRC1[143:128]);
DEST[143:136] SaturateSignedWordToUnsignedByte (SRC1[159:144]);
DEST[151:144] SaturateSignedWordToUnsignedByte (SRC1[175:160]);
DEST[159:152] SaturateSignedWordToUnsignedByte (SRC1[191:176]);
DEST[167:160] SaturateSignedWordToUnsignedByte (SRC1[207:192]);
DEST[175:168] SaturateSignedWordToUnsignedByte (SRC1[223:208]);
DEST[183:176] SaturateSignedWordToUnsignedByte (SRC1[239:224]);
DEST[191:184] SaturateSignedWordToUnsignedByte (SRC1[255:240]);
DEST[199:192] SaturateSignedWordToUnsignedByte (SRC2[143:128]);
DEST[207:200] SaturateSignedWordToUnsignedByte (SRC2[159:144]);
DEST[215:208] SaturateSignedWordToUnsignedByte (SRC2[175:160]);
DEST[223:216] SaturateSignedWordToUnsignedByte (SRC2[191:176]);
DEST[231:224] SaturateSignedWordToUnsignedByte (SRC2[207:192]);
DEST[239:232] SaturateSignedWordToUnsignedByte (SRC2[223:208]);
DEST[247:240] SaturateSignedWordToUnsignedByte (SRC2[239:224]);
DEST[255:248] SaturateSignedWordToUnsignedByte (SRC2[255:240]);
VPACKUSWB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
TMP_DEST[7:0] SaturateSignedWordToUnsignedByte (SRC1[15:0]);
TMP_DEST[15:8] SaturateSignedWordToUnsignedByte (SRC1[31:16]);
TMP_DEST[23:16] SaturateSignedWordToUnsignedByte (SRC1[47:32]);
TMP_DEST[31:24] SaturateSignedWordToUnsignedByte (SRC1[63:48]);
TMP_DEST[39:32] SaturateSignedWordToUnsignedByte (SRC1[79:64]);
TMP_DEST[47:40] SaturateSignedWordToUnsignedByte (SRC1[95:80]);
TMP_DEST[55:48] SaturateSignedWordToUnsignedByte (SRC1[111:96]);
TMP_DEST[63:56] SaturateSignedWordToUnsignedByte (SRC1[127:112]);
TMP_DEST[71:64] SaturateSignedWordToUnsignedByte (SRC2[15:0]);
TMP_DEST[79:72] SaturateSignedWordToUnsignedByte (SRC2[31:16]);
TMP_DEST[87:80] SaturateSignedWordToUnsignedByte (SRC2[47:32]);
TMP_DEST[95:88] SaturateSignedWordToUnsignedByte (SRC2[63:48]);
TMP_DEST[103:96] SaturateSignedWordToUnsignedByte (SRC2[79:64]);
TMP_DEST[111:104] SaturateSignedWordToUnsignedByte (SRC2[95:80]);
PACKUSWB—Pack with Unsigned Saturation
Vol. 2B 4-201
INSTRUCTION SET REFERENCE, M-U
TMP_DEST[119:112] SaturateSignedWordToUnsignedByte (SRC2[111:96]);
TMP_DEST[127:120] SaturateSignedWordToUnsignedByte (SRC2[127:112]);
IF VL >= 256
TMP_DEST[135:128] SaturateSignedWordToUnsignedByte (SRC1[143:128]);
TMP_DEST[143:136] SaturateSignedWordToUnsignedByte (SRC1[159:144]);
TMP_DEST[151:144] SaturateSignedWordToUnsignedByte (SRC1[175:160]);
TMP_DEST[159:152] SaturateSignedWordToUnsignedByte (SRC1[191:176]);
TMP_DEST[167:160] SaturateSignedWordToUnsignedByte (SRC1[207:192]);
TMP_DEST[175:168] SaturateSignedWordToUnsignedByte (SRC1[223:208]);
TMP_DEST[183:176] SaturateSignedWordToUnsignedByte (SRC1[239:224]);
TMP_DEST[191:184] SaturateSignedWordToUnsignedByte (SRC1[255:240]);
TMP_DEST[199:192] SaturateSignedWordToUnsignedByte (SRC2[143:128]);
TMP_DEST[207:200] SaturateSignedWordToUnsignedByte (SRC2[159:144]);
TMP_DEST[215:208] SaturateSignedWordToUnsignedByte (SRC2[175:160]);
TMP_DEST[223:216] SaturateSignedWordToUnsignedByte (SRC2[191:176]);
TMP_DEST[231:224] SaturateSignedWordToUnsignedByte (SRC2[207:192]);
TMP_DEST[239:232] SaturateSignedWordToUnsignedByte (SRC2[223:208]);
TMP_DEST[247:240] SaturateSignedWordToUnsignedByte (SRC2[239:224]);
TMP_DEST[255:248] SaturateSignedWordToUnsignedByte (SRC2[255:240]);
FI;
IF VL >= 512
TMP_DEST[263:256] SaturateSignedWordToUnsignedByte (SRC1[271:256]);
TMP_DEST[271:264] SaturateSignedWordToUnsignedByte (SRC1[287:272]);
TMP_DEST[279:272] SaturateSignedWordToUnsignedByte (SRC1[303:288]);
TMP_DEST[287:280] SaturateSignedWordToUnsignedByte (SRC1[319:304]);
TMP_DEST[295:288] SaturateSignedWordToUnsignedByte (SRC1[335:320]);
TMP_DEST[303:296] SaturateSignedWordToUnsignedByte (SRC1[351:336]);
TMP_DEST[311:304] SaturateSignedWordToUnsignedByte (SRC1[367:352]);
TMP_DEST[319:312] SaturateSignedWordToUnsignedByte (SRC1[383:368]);
TMP_DEST[327:320] SaturateSignedWordToUnsignedByte (SRC2[271:256]);
TMP_DEST[335:328] SaturateSignedWordToUnsignedByte (SRC2[287:272]);
TMP_DEST[343:336] SaturateSignedWordToUnsignedByte (SRC2[303:288]);
TMP_DEST[351:344] SaturateSignedWordToUnsignedByte (SRC2[319:304]);
TMP_DEST[359:352] SaturateSignedWordToUnsignedByte (SRC2[335:320]);
TMP_DEST[367:360] SaturateSignedWordToUnsignedByte (SRC2[351:336]);
TMP_DEST[375:368] SaturateSignedWordToUnsignedByte (SRC2[367:352]);
TMP_DEST[383:376] SaturateSignedWordToUnsignedByte (SRC2[383:368]);
TMP_DEST[391:384] SaturateSignedWordToUnsignedByte (SRC1[399:384]);
TMP_DEST[399:392] SaturateSignedWordToUnsignedByte (SRC1[415:400]);
TMP_DEST[407:400] SaturateSignedWordToUnsignedByte (SRC1[431:416]);
TMP_DEST[415:408] SaturateSignedWordToUnsignedByte (SRC1[447:432]);
TMP_DEST[423:416] SaturateSignedWordToUnsignedByte (SRC1[463:448]);
TMP_DEST[431:424] SaturateSignedWordToUnsignedByte (SRC1[479:464]);
TMP_DEST[439:432] SaturateSignedWordToUnsignedByte (SRC1[495:480]);
TMP_DEST[447:440] SaturateSignedWordToUnsignedByte (SRC1[511:496]);
TMP_DEST[455:448] SaturateSignedWordToUnsignedByte (SRC2[399:384]);
TMP_DEST[463:456] SaturateSignedWordToUnsignedByte (SRC2[415:400]);
TMP_DEST[471:464] SaturateSignedWordToUnsignedByte (SRC2[431:416]);
TMP_DEST[479:472] SaturateSignedWordToUnsignedByte (SRC2[447:432]);
TMP_DEST[487:480] SaturateSignedWordToUnsignedByte (SRC2[463:448]);
TMP_DEST[495:488] SaturateSignedWordToUnsignedByte (SRC2[479:464]);
4-202 Vol. 2B
PACKUSWB—Pack with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
TMP_DEST[503:496] SaturateSignedWordToUnsignedByte (SRC2[495:480]);
TMP_DEST[511:504] SaturateSignedWordToUnsignedByte (SRC2[511:496]);
FI;
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN
DEST[i+7:i] TMP_DEST[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPACKUSWB__m512i _mm512_packus_epi16(__m512i m1, __m512i m2);
VPACKUSWB__m512i _mm512_mask_packus_epi16(__m512i s, __mmask64 k, __m512i m1, __m512i m2);
VPACKUSWB__m512i _mm512_maskz_packus_epi16(__mmask64 k, __m512i m1, __m512i m2);
VPACKUSWB__m256i _mm256_mask_packus_epi16(__m256i s, __mmask32 k, __m256i m1, __m256i m2);
VPACKUSWB__m256i _mm256_maskz_packus_epi16(__mmask32 k, __m256i m1, __m256i m2);
VPACKUSWB__m128i _mm_mask_packus_epi16(__m128i s, __mmask16 k, __m128i m1, __m128i m2);
VPACKUSWB__m128i _mm_maskz_packus_epi16(__mmask16 k, __m128i m1, __m128i m2);
PACKUSWB:
__m64 _mm_packs_pu16(__m64 m1, __m64 m2)
(V)PACKUSWB: __m128i _mm_packus_epi16(__m128i m1, __m128i m2)
VPACKUSWB:
__m256i _mm256_packus_epi16(__m256i m1, __m256i m2);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
PACKUSWB—Pack with Unsigned Saturation
Vol. 2B 4-203
INSTRUCTION SET REFERENCE, M-U
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
Opcode/
Instruction
Op /
En
0F FC /r1
PADDB mm, mm/m64
0F FD /r1
PADDW mm, mm/m64
66 0F FC /r
PADDB xmm1, xmm2/m128
66 0F FD /r
PADDW xmm1, xmm2/m128
66 0F FE /r
PADDD xmm1, xmm2/m128
66 0F D4 /r
PADDQ xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG FC /r
VPADDB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG FD /r
VPADDW xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG FE /r
VPADDD xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG D4 /r
VPADDQ xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG FC /r
VPADDB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG FD /r
VPADDW ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG FE /r
VPADDD ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG D4 /r
VPADDQ ymm1, ymm2, ymm3/m256
EVEX.NDS.128.66.0F.WIG FC /r
VPADDB xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.128.66.0F.WIG FD /r
VPADDW xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.128.66.0F.W0 FE /r
VPADDD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.128.66.0F.W1 D4 /r
VPADDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.WIG FC /r
VPADDB ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.256.66.0F.WIG FD /r
VPADDW ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.256.66.0F.W0 FE /r
VPADDD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
4-204 Vol. 2B
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
MMX
Description
Add packed byte integers from mm/m64 and mm.
RM
V/V
MMX
Add packed word integers from mm/m64 and mm.
RM
V/V
SSE2
RM
V/V
SSE2
RM
V/V
SSE2
RM
V/V
SSE2
RVM
V/V
AVX
RVM
V/V
AVX
RVM
V/V
AVX
RVM
V/V
AVX
RVM
V/V
AVX2
RVM
V/V
AVX2
RVM
V/V
AVX2
RVM
V/V
AVX2
FVM
V/V
AVX512VL
AVX512BW
Add packed byte integers from xmm2/m128 and
xmm1.
Add packed word integers from xmm2/m128 and
xmm1.
Add packed doubleword integers from xmm2/m128
and xmm1.
Add packed quadword integers from xmm2/m128
and xmm1.
Add packed byte integers from xmm2, and
xmm3/m128 and store in xmm1.
Add packed word integers from xmm2, xmm3/m128
and store in xmm1.
Add packed doubleword integers from xmm2,
xmm3/m128 and store in xmm1.
Add packed quadword integers from xmm2,
xmm3/m128 and store in xmm1.
Add packed byte integers from ymm2, and
ymm3/m256 and store in ymm1.
Add packed word integers from ymm2, ymm3/m256
and store in ymm1.
Add packed doubleword integers from ymm2,
ymm3/m256 and store in ymm1.
Add packed quadword integers from ymm2,
ymm3/m256 and store in ymm1.
Add packed byte integers from xmm2, and
xmm3/m128 and store in xmm1 using writemask k1.
FVM
V/V
AVX512VL
AVX512BW
Add packed word integers from xmm2, and
xmm3/m128 and store in xmm1 using writemask k1.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FVM
V/V
AVX512VL
AVX512BW
Add packed doubleword integers from xmm2, and
xmm3/m128/m32bcst and store in xmm1 using
writemask k1.
Add packed quadword integers from xmm2, and
xmm3/m128/m64bcst and store in xmm1 using
writemask k1.
Add packed byte integers from ymm2, and
ymm3/m256 and store in ymm1 using writemask k1.
FVM
V/V
AVX512VL
AVX512BW
Add packed word integers from ymm2, and
ymm3/m256 and store in ymm1 using writemask k1.
FV
V/V
AVX512VL
AVX512F
Add packed doubleword integers from ymm2,
ymm3/m256/m32bcst and store in ymm1 using
writemask k1.
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
INSTRUCTION SET REFERENCE, M-U
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.256.66.0F.W1 D4 /r
VPADDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.WIG FC /r
VPADDB zmm1 {k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.512.66.0F.WIG FD /r
VPADDW zmm1 {k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.512.66.0F.W0 FE /r
VPADDD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.512.66.0F.W1 D4 /r
VPADDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
NOTES:
Description
FVM
V/V
AVX512BW
FVM
V/V
AVX512BW
Add packed word integers from zmm2, and
zmm3/m512 and store in zmm1 using writemask k1.
FV
V/V
AVX512F
FV
V/V
AVX512F
Add packed doubleword integers from zmm2,
zmm3/m512/m32bcst and store in zmm1 using
writemask k1.
Add packed quadword integers from zmm2,
zmm3/m512/m64bcst and store in zmm1 using
writemask k1.
Add packed quadword integers from ymm2,
ymm3/m256/m64bcst and store in ymm1 using
writemask k1.
Add packed byte integers from zmm2, and
zmm3/m512 and store in zmm1 using writemask k1.
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD add of the packed integers from the source operand (second operand) and the destination
operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled with wraparound, as described in the following paragraphs.
The PADDB and VPADDB instructions add packed byte integers from the first source operand and second source
operand and store the packed integer results in the destination operand. When an individual result is too large to
be represented in 8 bits (overflow), the result is wrapped around and the low 8 bits are written to the destination
operand (that is, the carry is ignored).
The PADDW and VPADDW instructions add packed word integers from the first source operand and second source
operand and store the packed integer results in the destination operand. When an individual result is too large to
be represented in 16 bits (overflow), the result is wrapped around and the low 16 bits are written to the destination
operand (that is, the carry is ignored).
The PADDD and VPADDD instructions add packed doubleword integers from the first source operand and second
source operand and store the packed integer results in the destination operand. When an individual result is too
large to be represented in 32 bits (overflow), the result is wrapped around and the low 32 bits are written to the
destination operand (that is, the carry is ignored).
The PADDQ and VPADDQ instructions add packed quadword integers from the first source operand and second
source operand and store the packed integer results in the destination operand. When a quadword result is too
large to be represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the
destination operand (that is, the carry is ignored).
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
Vol. 2B 4-205
INSTRUCTION SET REFERENCE, M-U
Note that the (V)PADDB, (V)PADDW, (V)PADDD and (V)PADDQ instructions can operate on either unsigned or
signed (two's complement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of
values operated on.
EVEX encoded VPADDD/Q: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the
writemask.
EVEX encoded VPADDB/W: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register updated according to the writemask.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. the upper bits (MAX_VL-1:256) of the
destination are cleared.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
Operation
PADDB (with 64-bit operands)
DEST[7:0] ← DEST[7:0] + SRC[7:0];
(* Repeat add operation for 2nd through 7th byte *)
DEST[63:56] ← DEST[63:56] + SRC[63:56];
PADDW (with 64-bit operands)
DEST[15:0] ← DEST[15:0] + SRC[15:0];
(* Repeat add operation for 2nd and 3th word *)
DEST[63:48] ← DEST[63:48] + SRC[63:48];
PADDD (with 64-bit operands)
DEST[31:0] ← DEST[31:0] + SRC[31:0];
DEST[63:32] ← DEST[63:32] + SRC[63:32];
PADDQ (with 64-Bit operands)
DEST[63:0] ← DEST[63:0] + SRC[63:0];
PADDB (Legacy SSE instruction)
DEST[7:0]← DEST[7:0] + SRC[7:0];
(* Repeat add operation for 2nd through 15th byte *)
DEST[127:120]← DEST[127:120] + SRC[127:120];
DEST[MAX_VL-1:128] (Unmodified)
PADDW (Legacy SSE instruction)
DEST[15:0] ← DEST[15:0] + SRC[15:0];
(* Repeat add operation for 2nd through 7th word *)
DEST[127:112]← DEST[127:112] + SRC[127:112];
DEST[MAX_VL-1:128] (Unmodified)
PADDD (Legacy SSE instruction)
DEST[31:0]← DEST[31:0] + SRC[31:0];
(* Repeat add operation for 2nd and 3th doubleword *)
DEST[127:96]← DEST[127:96] + SRC[127:96];
4-206 Vol. 2B
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
INSTRUCTION SET REFERENCE, M-U
DEST[MAX_VL-1:128] (Unmodified)
PADDQ (Legacy SSE instruction)
DEST[63:0]← DEST[63:0] + SRC[63:0];
DEST[127:64]← DEST[127:64] + SRC[127:64];
DEST[MAX_VL-1:128] (Unmodified)
VPADDB (VEX.128 encoded instruction)
DEST[7:0]← SRC1[7:0] + SRC2[7:0];
(* Repeat add operation for 2nd through 15th byte *)
DEST[127:120]← SRC1[127:120] + SRC2[127:120];
DEST[MAX_VL-1:128] ← 0;
VPADDW (VEX.128 encoded instruction)
DEST[15:0] ← SRC1[15:0] + SRC2[15:0];
(* Repeat add operation for 2nd through 7th word *)
DEST[127:112]← SRC1[127:112] + SRC2[127:112];
DEST[MAX_VL-1:128] ← 0;
VPADDD (VEX.128 encoded instruction)
DEST[31:0]← SRC1[31:0] + SRC2[31:0];
(* Repeat add operation for 2nd and 3th doubleword *)
DEST[127:96] ← SRC1[127:96] + SRC2[127:96];
DEST[MAX_VL-1:128] ← 0;
VPADDQ (VEX.128 encoded instruction)
DEST[63:0]← SRC1[63:0] + SRC2[63:0];
DEST[127:64] ← SRC1[127:64] + SRC2[127:64];
DEST[MAX_VL-1:128] ← 0;
VPADDB (VEX.256 encoded instruction)
DEST[7:0]← SRC1[7:0] + SRC2[7:0];
(* Repeat add operation for 2nd through 31th byte *)
DEST[255:248]← SRC1[255:248] + SRC2[255:248];
VPADDW (VEX.256 encoded instruction)
DEST[15:0] ← SRC1[15:0] + SRC2[15:0];
(* Repeat add operation for 2nd through 15th word *)
DEST[255:240]← SRC1[255:240] + SRC2[255:240];
VPADDD (VEX.256 encoded instruction)
DEST[31:0]← SRC1[31:0] + SRC2[31:0];
(* Repeat add operation for 2nd and 7th doubleword *)
DEST[255:224] ← SRC1[255:224] + SRC2[255:224];
VPADDQ (VEX.256 encoded instruction)
DEST[63:0]← SRC1[63:0] + SRC2[63:0];
DEST[127:64] ← SRC1[127:64] + SRC2[127:64];
DEST[191:128]← SRC1[191:128] + SRC2[191:128];
DEST[255:192] ← SRC1[255:192] + SRC2[255:192];
VPADDB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
Vol. 2B 4-207
INSTRUCTION SET REFERENCE, M-U
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SRC1[i+7:i] + SRC2[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPADDW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC1[i+15:i] + SRC2[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPADDD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SRC1[i+31:i] + SRC2[31:0]
ELSE DEST[i+31:i] SRC1[i+31:i] + SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPADDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
4-208 Vol. 2B
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
INSTRUCTION SET REFERENCE, M-U
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] SRC1[i+63:i] + SRC2[63:0]
ELSE DEST[i+63:i] SRC1[i+63:i] + SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPADDB__m512i _mm512_add_epi8 ( __m512i a, __m512i b)
VPADDW__m512i _mm512_add_epi16 ( __m512i a, __m512i b)
VPADDB__m512i _mm512_mask_add_epi8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)
VPADDW__m512i _mm512_mask_add_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)
VPADDB__m512i _mm512_maskz_add_epi8 (__mmask64 m, __m512i a, __m512i b)
VPADDW__m512i _mm512_maskz_add_epi16 (__mmask32 m, __m512i a, __m512i b)
VPADDB__m256i _mm256_mask_add_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)
VPADDW__m256i _mm256_mask_add_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)
VPADDB__m256i _mm256_maskz_add_epi8 (__mmask32 m, __m256i a, __m256i b)
VPADDW__m256i _mm256_maskz_add_epi16 (__mmask16 m, __m256i a, __m256i b)
VPADDB__m128i _mm_mask_add_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)
VPADDW__m128i _mm_mask_add_epi16 (__m128i s, __mmask8 m, __m128i a, __m128i b)
VPADDB__m128i _mm_maskz_add_epi8 (__mmask16 m, __m128i a, __m128i b)
VPADDW__m128i _mm_maskz_add_epi16 (__mmask8 m, __m128i a, __m128i b)
VPADDD __m512i _mm512_add_epi32( __m512i a, __m512i b);
VPADDD __m512i _mm512_mask_add_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPADDD __m512i _mm512_maskz_add_epi32( __mmask16 k, __m512i a, __m512i b);
VPADDD __m256i _mm256_mask_add_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPADDD __m256i _mm256_maskz_add_epi32( __mmask8 k, __m256i a, __m256i b);
VPADDD __m128i _mm_mask_add_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPADDD __m128i _mm_maskz_add_epi32( __mmask8 k, __m128i a, __m128i b);
VPADDQ __m512i _mm512_add_epi64( __m512i a, __m512i b);
VPADDQ __m512i _mm512_mask_add_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPADDQ __m512i _mm512_maskz_add_epi64( __mmask8 k, __m512i a, __m512i b);
VPADDQ __m256i _mm256_mask_add_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPADDQ __m256i _mm256_maskz_add_epi64( __mmask8 k, __m256i a, __m256i b);
VPADDQ __m128i _mm_mask_add_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPADDQ __m128i _mm_maskz_add_epi64( __mmask8 k, __m128i a, __m128i b);
PADDB __m128i _mm_add_epi8 (__m128i a,__m128i b );
PADDW __m128i _mm_add_epi16 ( __m128i a, __m128i b);
PADDD __m128i _mm_add_epi32 ( __m128i a, __m128i b);
PADDQ __m128i _mm_add_epi64 ( __m128i a, __m128i b);
VPADDB __m256i _mm256_add_epi8 (__m256ia,__m256i b );
VPADDW __m256i _mm256_add_epi16 ( __m256i a, __m256i b);
VPADDD __m256i _mm256_add_epi32 ( __m256i a, __m256i b);
VPADDQ __m256i _mm256_add_epi64 ( __m256i a, __m256i b);
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
Vol. 2B 4-209
INSTRUCTION SET REFERENCE, M-U
PADDB __m64 _mm_add_pi8(__m64 m1, __m64 m2)
PADDW __m64 _mm_add_pi16(__m64 m1, __m64 m2)
PADDD __m64 _mm_add_pi32(__m64 m1, __m64 m2)
PADDQ __m64 _mm_add_pi64(__m64 m1, __m64 m2)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPADDD/Q, see Exceptions Type E4.
EVEX-encoded VPADDB/W, see Exceptions Type E4.nb.
4-210 Vol. 2B
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers
INSTRUCTION SET REFERENCE, M-U
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F EC /r1
RM
V/V
MMX
Add packed signed byte integers from
mm/m64 and mm and saturate the results.
RM
V/V
SSE2
Add packed signed byte integers from
xmm2/m128 and xmm1 saturate the results.
RM
V/V
MMX
Add packed signed word integers from
mm/m64 and mm and saturate the results.
RM
V/V
SSE2
Add packed signed word integers from
xmm2/m128 and xmm1 and saturate the
results.
PADDSB mm, mm/m64
66 0F EC /r
PADDSB xmm1, xmm2/m128
0F ED /r1
PADDSW mm, mm/m64
66 0F ED /r
PADDSW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG EC /r
VPADDSB xmm1, xmm2, xmm3/m128
RVM V/V
AVX
Add packed signed byte integers from
xmm3/m128 and xmm2 saturate the results.
VEX.NDS.128.66.0F.WIG ED /r
RVM V/V
AVX
Add packed signed word integers from
xmm3/m128 and xmm2 and saturate the
results.
RVM V/V
AVX2
Add packed signed byte integers from ymm2,
and ymm3/m256 and store the saturated
results in ymm1.
RVM V/V
AVX2
Add packed signed word integers from ymm2,
and ymm3/m256 and store the saturated
results in ymm1.
EVEX.NDS.128.66.0F.WIG EC /r
VPADDSB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Add packed signed byte integers from xmm2,
and xmm3/m128 and store the saturated
results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG EC /r
VPADDSB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Add packed signed byte integers from ymm2,
and ymm3/m256 and store the saturated
results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG EC /r
VPADDSB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Add packed signed byte integers from zmm2,
and zmm3/m512 and store the saturated
results in zmm1 under writemask k1.
EVEX.NDS.128.66.0F.WIG ED /r
VPADDSW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Add packed signed word integers from xmm2,
and xmm3/m128 and store the saturated
results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG ED /r
VPADDSW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Add packed signed word integers from ymm2,
and ymm3/m256 and store the saturated
results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG ED /r
VPADDSW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Add packed signed word integers from zmm2,
and zmm3/m512 and store the saturated
results in zmm1 under writemask k1.
VPADDSW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG EC /r
VPADDSB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG ED /r
VPADDSW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation
Vol. 2B 4-211
INSTRUCTION SET REFERENCE, M-U
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD add of the packed signed integers from the source operand (second operand) and the destination
operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled with signed saturation, as described in the following paragraphs.
(V)PADDSB performs a SIMD add of the packed signed integers with saturation from the first source operand and
second source operand and stores the packed integer results in the destination operand. When an individual byte
result is beyond the range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value
of 7FH or 80H, respectively, is written to the destination operand.
(V)PADDSW performs a SIMD add of the packed signed word integers with saturation from the first source operand
and second source operand and stores the packed integer results in the destination operand. When an individual
word result is beyond the range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the saturated value of 7FFFH or 8000H, respectively, is written to the destination operand.
EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an
ZMM/YMM/XMM register or a memory location. The destination operand is an ZMM/YMM/XMM register.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of
the corresponding register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
Operation
PADDSB (with 64-bit operands)
DEST[7:0] ← SaturateToSignedByte(DEST[7:0] + SRC (7:0]);
(* Repeat add operation for 2nd through 7th bytes *)
DEST[63:56] ← SaturateToSignedByte(DEST[63:56] + SRC[63:56] );
PADDSB (with 128-bit operands)
DEST[7:0] ←SaturateToSignedByte (DEST[7:0] + SRC[7:0]);
(* Repeat add operation for 2nd through 14th bytes *)
DEST[127:120] ← SaturateToSignedByte (DEST[111:120] + SRC[127:120]);
VPADDSB (VEX.128 encoded version)
DEST[7:0] SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] SaturateToSignedByte (SRC1[111:120] + SRC2[127:120]);
DEST[VLMAX-1:128] 0
VPADDSB (VEX.256 encoded version)
DEST[7:0] SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);
(* Repeat add operation for 2nd through 31st bytes *)
DEST[255:248] SaturateToSignedByte (SRC1[255:248] + SRC2[255:248]);
4-212 Vol. 2B
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
VPADDSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateToSignedByte (SRC1[i+7:i] + SRC2[i+7:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PADDSW (with 64-bit operands)
DEST[15:0] ← SaturateToSignedWord(DEST[15:0] + SRC[15:0] );
(* Repeat add operation for 2nd and 7th words *)
DEST[63:48] ← SaturateToSignedWord(DEST[63:48] + SRC[63:48] );
PADDSW (with 128-bit operands)
DEST[15:0] ← SaturateToSignedWord (DEST[15:0] + SRC[15:0]);
(* Repeat add operation for 2nd through 7th words *)
DEST[127:112] ← SaturateToSignedWord (DEST[127:112] + SRC[127:112]);
VPADDSW (VEX.128 encoded version)
DEST[15:0] SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] SaturateToSignedWord (SRC1[127:112] + SRC2[127:112]);
DEST[VLMAX-1:128] 0
VPADDSW (VEX.256 encoded version)
DEST[15:0] SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);
(* Repeat add operation for 2nd through 15th words *)
DEST[255:240] SaturateToSignedWord (SRC1[255:240] + SRC2[255:240])
VPADDSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateToSignedWord (SRC1[i+15:i] + SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation
Vol. 2B 4-213
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalents
PADDSB:
__m64 _mm_adds_pi8(__m64 m1, __m64 m2)
(V)PADDSB:
__m128i _mm_adds_epi8 ( __m128i a, __m128i b)
VPADDSB:
__m256i _mm256_adds_epi8 ( __m256i a, __m256i b)
PADDSW:
__m64 _mm_adds_pi16(__m64 m1, __m64 m2)
(V)PADDSW:
__m128i _mm_adds_epi16 ( __m128i a, __m128i b)
VPADDSW:
__m256i _mm256_adds_epi16 ( __m256i a, __m256i b)
VPADDSB__m512i _mm512_adds_epi8 ( __m512i a, __m512i b)
VPADDSW__m512i _mm512_adds_epi16 ( __m512i a, __m512i b)
VPADDSB__m512i _mm512_mask_adds_epi8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)
VPADDSW__m512i _mm512_mask_adds_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)
VPADDSB__m512i _mm512_maskz_adds_epi8 (__mmask64 m, __m512i a, __m512i b)
VPADDSW__m512i _mm512_maskz_adds_epi16 (__mmask32 m, __m512i a, __m512i b)
VPADDSB__m256i _mm256_mask_adds_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)
VPADDSW__m256i _mm256_mask_adds_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)
VPADDSB__m256i _mm256_maskz_adds_epi8 (__mmask32 m, __m256i a, __m256i b)
VPADDSW__m256i _mm256_maskz_adds_epi16 (__mmask16 m, __m256i a, __m256i b)
VPADDSB__m128i _mm_mask_adds_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)
VPADDSW__m128i _mm_mask_adds_epi16 (__m128i s, __mmask8 m, __m128i a, __m128i b)
VPADDSB__m128i _mm_maskz_adds_epi8 (__mmask16 m, __m128i a, __m128i b)
VPADDSW__m128i _mm_maskz_adds_epi16 (__mmask8 m, __m128i a, __m128i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
4-214 Vol. 2B
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Description
Feature Flag
0F DC /r1
RM
V/V
MMX
Add packed unsigned byte integers from
mm/m64 and mm and saturate the results.
RM
V/V
SSE2
Add packed unsigned byte integers from
xmm2/m128 and xmm1 saturate the results.
RM
V/V
MMX
Add packed unsigned word integers from
mm/m64 and mm and saturate the results.
RM
V/V
SSE2
Add packed unsigned word integers from
xmm2/m128 to xmm1 and saturate the
results.
RVM V/V
AVX
Add packed unsigned byte integers from
xmm3/m128 to xmm2 and saturate the
results.
RVM V/V
AVX
Add packed unsigned word integers from
xmm3/m128 to xmm2 and saturate the
results.
VEX.NDS.256.66.0F.WIG DC /r
VPADDUSB ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Add packed unsigned byte integers from
ymm2, and ymm3/m256 and store the
saturated results in ymm1.
VEX.NDS.256.66.0F.WIG DD /r
VPADDUSW ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Add packed unsigned word integers from
ymm2, and ymm3/m256 and store the
saturated results in ymm1.
EVEX.NDS.128.66.0F.WIG DC /r
VPADDUSB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Add packed unsigned byte integers from
xmm2, and xmm3/m128 and store the
saturated results in xmm1 under writemask
k1.
EVEX.NDS.256.66.0F.WIG DC /r
VPADDUSB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Add packed unsigned byte integers from
ymm2, and ymm3/m256 and store the
saturated results in ymm1 under writemask
k1.
EVEX.NDS.512.66.0F.WIG DC /r
VPADDUSB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Add packed unsigned byte integers from
zmm2, and zmm3/m512 and store the
saturated results in zmm1 under writemask
k1.
EVEX.NDS.128.66.0F.WIG DD /r
VPADDUSW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Add packed unsigned word integers from
xmm2, and xmm3/m128 and store the
saturated results in xmm1 under writemask
k1.
EVEX.NDS.256.66.0F.WIG DD /r
VPADDUSW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Add packed unsigned word integers from
ymm2, and ymm3/m256 and store the
saturated results in ymm1 under writemask
k1.
PADDUSB mm, mm/m64
66 0F DC /r
PADDUSB xmm1, xmm2/m128
0F DD /r1
PADDUSW mm, mm/m64
66 0F DD /r
PADDUSW xmm1, xmm2/m128
VEX.NDS.128.660F.WIG DC /r
VPADDUSB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG DD /r
VPADDUSW xmm1, xmm2, xmm3/m128
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation
Vol. 2B 4-215
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.512.66.0F.WIG DD /r
VPADDUSW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Add packed unsigned word integers from
zmm2, and zmm3/m512 and store the
saturated results in zmm1 under writemask
k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD add of the packed unsigned integers from the source operand (second operand) and the destination operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled with unsigned saturation, as described in the following paragraphs.
(V)PADDUSB performs a SIMD add of the packed unsigned integers with saturation from the first source operand
and second source operand and stores the packed integer results in the destination operand. When an individual
byte result is beyond the range of an unsigned byte integer (that is, greater than FFH), the saturated value of FFH
is written to the destination operand.
(V)PADDUSW performs a SIMD add of the packed unsigned word integers with saturation from the first source
operand and second source operand and stores the packed integer results in the destination operand. When an
individual word result is beyond the range of an unsigned word integer (that is, greater than FFFFH), the saturated
value of FFFFH is written to the destination operand.
EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination is an ZMM/YMM/XMM register.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding destination register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
Operation
PADDUSB (with 64-bit operands)
DEST[7:0] ← SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );
(* Repeat add operation for 2nd through 7th bytes *)
DEST[63:56] ← SaturateToUnsignedByte(DEST[63:56] + SRC[63:56]
PADDUSB (with 128-bit operands)
DEST[7:0] ← SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);
(* Repeat add operation for 2nd through 14th bytes *)
DEST[127:120] ← SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]);
4-216 Vol. 2B
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
VPADDUSB (VEX.128 encoded version)
DEST[7:0] SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);
DEST[VLMAX-1:128] 0
VPADDUSB (VEX.256 encoded version)
DEST[7:0] SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
(* Repeat add operation for 2nd through 31st bytes *)
DEST[255:248] SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);
PADDUSW (with 64-bit operands)
DEST[15:0] ← SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );
(* Repeat add operation for 2nd and 3rd words *)
DEST[63:48] ← SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );
PADDUSW (with 128-bit operands)
DEST[15:0] ← SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);
(* Repeat add operation for 2nd through 7th words *)
DEST[127:112] ← SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);
VPADDUSW (VEX.128 encoded version)
DEST[15:0] SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);
DEST[VLMAX-1:128] 0
VPADDUSW (VEX.256 encoded version)
DEST[15:0] SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
(* Repeat add operation for 2nd through 15th words *)
DEST[255:240] SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])
VPADDUSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateToUnsignedByte (SRC1[i+7:i] + SRC2[i+7:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPADDUSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation
Vol. 2B 4-217
INSTRUCTION SET REFERENCE, M-U
THEN DEST[i+15:i] SaturateToUnsignedWord (SRC1[i+15:i] + SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
PADDUSB:
__m64 _mm_adds_pu8(__m64 m1, __m64 m2)
PADDUSW:
__m64 _mm_adds_pu16(__m64 m1, __m64 m2)
(V)PADDUSB:
__m128i _mm_adds_epu8 ( __m128i a, __m128i b)
(V)PADDUSW:
__m128i _mm_adds_epu16 ( __m128i a, __m128i b)
VPADDUSB:
__m256i _mm256_adds_epu8 ( __m256i a, __m256i b)
VPADDUSW:
__m256i _mm256_adds_epu16 ( __m256i a, __m256i b)
VPADDUSB__m512i _mm512_adds_epu8 ( __m512i a, __m512i b)
VPADDUSW__m512i _mm512_adds_epu16 ( __m512i a, __m512i b)
VPADDUSB__m512i _mm512_mask_adds_epu8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)
VPADDUSW__m512i _mm512_mask_adds_epu16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)
VPADDUSB__m512i _mm512_maskz_adds_epu8 (__mmask64 m, __m512i a, __m512i b)
VPADDUSW__m512i _mm512_maskz_adds_epu16 (__mmask32 m, __m512i a, __m512i b)
VPADDUSB__m256i _mm256_mask_adds_epu8 (__m256i s, __mmask32 m, __m256i a, __m256i b)
VPADDUSW__m256i _mm256_mask_adds_epu16 (__m256i s, __mmask16 m, __m256i a, __m256i b)
VPADDUSB__m256i _mm256_maskz_adds_epu8 (__mmask32 m, __m256i a, __m256i b)
VPADDUSW__m256i _mm256_maskz_adds_epu16 (__mmask16 m, __m256i a, __m256i b)
VPADDUSB__m128i _mm_mask_adds_epu8 (__m128i s, __mmask16 m, __m128i a, __m128i b)
VPADDUSW__m128i _mm_mask_adds_epu16 (__m128i s, __mmask8 m, __m128i a, __m128i b)
VPADDUSB__m128i _mm_maskz_adds_epu8 (__mmask16 m, __m128i a, __m128i b)
VPADDUSW__m128i _mm_maskz_adds_epu16 (__mmask8 m, __m128i a, __m128i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
4-218 Vol. 2B
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
PALIGNR — Packed Align Right
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 3A 0F /r ib1
RMI
V/V
SSSE3
Concatenate destination and source operands,
extract byte-aligned result shifted to the right by
constant value in imm8 into mm1.
RMI
V/V
SSSE3
Concatenate destination and source operands,
extract byte-aligned result shifted to the right by
constant value in imm8 into xmm1.
RVMI V/V
AVX
Concatenate xmm2 and xmm3/m128, extract
byte aligned result shifted to the right by
constant value in imm8 and result is stored in
xmm1.
RVMI V/V
AVX2
Concatenate pairs of 16 bytes in ymm2 and
ymm3/m256 into 32-byte intermediate result,
extract byte-aligned, 16-byte result shifted to
the right by constant values in imm8 from each
intermediate result, and two 16-byte results are
stored in ymm1.
EVEX.NDS.128.66.0F3A.WIG 0F /r ib
VPALIGNR xmm1 {k1}{z}, xmm2, xmm3/m128,
imm8
FVM
V/V
AVX512VL Concatenate xmm2 and xmm3/m128 into a 32AVX512BW byte intermediate result, extract byte aligned
result shifted to the right by constant value in
imm8 and result is stored in xmm1.
EVEX.NDS.256.66.0F3A.WIG 0F /r ib
VPALIGNR ymm1 {k1}{z}, ymm2, ymm3/m256,
imm8
FVM
V/V
AVX512VL Concatenate pairs of 16 bytes in ymm2 and
AVX512BW ymm3/m256 into 32-byte intermediate result,
extract byte-aligned, 16-byte result shifted to
the right by constant values in imm8 from each
intermediate result, and two 16-byte results are
stored in ymm1.
EVEX.NDS.512.66.0F3A.WIG 0F /r ib
VPALIGNR zmm1 {k1}{z}, zmm2, zmm3/m512,
imm8
FVM
V/V
AVX512BW Concatenate pairs of 16 bytes in zmm2 and
zmm3/m512 into 32-byte intermediate result,
extract byte-aligned, 16-byte result shifted to
the right by constant values in imm8 from each
intermediate result, and four 16-byte results are
stored in zmm1.
PALIGNR mm1, mm2/m64, imm8
66 0F 3A 0F /r ib
PALIGNR xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 0F /r ib
VPALIGNR xmm1, xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.WIG 0F /r ib
VPALIGNR ymm1, ymm2, ymm3/m256, imm8
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
(V)PALIGNR concatenates the destination operand (the first operand) and the source operand (the second
operand) into an intermediate composite, shifts the composite at byte granularity to the right by a constant immediate, and extracts the right-aligned result into the destination. The first and the second operands can be an MMX,
PALIGNR — Packed Align Right
Vol. 2B 4-219
INSTRUCTION SET REFERENCE, M-U
XMM or a YMM register. The immediate value is considered unsigned. Immediate shift counts larger than the 2L
(i.e. 32 for 128-bit operands, or 16 for 64-bit operands) produce a zero result. Both operands can be MMX registers, XMM registers or YMM registers. When the source operand is a 128-bit memory operand, the operand must
be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
In 64-bit mode and not encoded by VEX/EVEX prefix, use the REX prefix to access additional registers.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
EVEX.512 encoded version: The first source operand is a ZMM register and contains four 16-byte blocks. The
second source operand is a ZMM register or a 512-bit memory location containing four 16-byte block. The destination operand is a ZMM register and contain four 16-byte results. The imm8[7:0] is the common shift count
used for each of the four successive 16-byte block sources. The low 16-byte block of the two source operands
produce the low 16-byte result of the destination operand, the high 16-byte block of the two source operands
produce the high 16-byte result of the destination operand and so on for the blocks in the middle.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register and contains two 16-byte
blocks. The second source operand is a YMM register or a 256-bit memory location containing two 16-byte block.
The destination operand is a YMM register and contain two 16-byte results. The imm8[7:0] is the common shift
count used for the two lower 16-byte block sources and the two upper 16-byte block sources. The low 16-byte
block of the two source operands produce the low 16-byte result of the destination operand, the high 16-byte block
of the two source operands produce the high 16-byte result of the destination operand. The upper bits (MAX_VL1:256) of the corresponding ZMM register destination are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits
(MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.
Concatenation is done with 128-bit data in the first and second source operand for both 128-bit and 256-bit
instructions. The high 128-bits of the intermediate composite 256-bit result came from the 128-bit data from the
first source operand; the low 128-bits of the intermediate result came from the 128-bit data of the second source
operand.
Note: VEX.L must be 0, otherwise the instruction will #UD.
0 127
127
0
SRC1
SRC2
128 255
255
128
SRC1
Imm8[7:0]*8
SRC2
Imm8[7:0]*8
128 127
255
DEST
0
DEST
Figure 4-7. 256-bit VPALIGN Instruction Operation
Operation
PALIGNR (with 64-bit operands)
temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8)
DEST[63:0] = temp1[63:0]
4-220 Vol. 2B
PALIGNR — Packed Align Right
INSTRUCTION SET REFERENCE, M-U
PALIGNR (with 128-bit operands)
temp1[255:0] ((DEST[127:0] << 128) OR SRC[127:0])>>(imm8*8);
DEST[127:0] temp1[127:0]
DEST[VLMAX-1:128] (Unmodified)
VPALIGNR (VEX.128 encoded version)
temp1[255:0] ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8*8);
DEST[127:0] temp1[127:0]
DEST[VLMAX-1:128] 0
VPALIGNR (VEX.256 encoded version)
temp1[255:0] ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8[7:0]*8);
DEST[127:0] temp1[127:0]
temp1[255:0] ((SRC1[255:128] << 128) OR SRC2[255:128])>>(imm8[7:0]*8);
DEST[MAX_VL-1:128] temp1[127:0]
VPALIGNR (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR l 0 TO VL-1 with increments of 128
temp1[255:0] ← ((SRC1[l+127:l] << 128) OR SRC2[l+127:l])>>(imm8[7:0]*8);
TMP_DEST[l+127:l] ← temp1[127:0]
ENDFOR;
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TMP_DEST[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
PALIGNR:
__m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
(V)PALIGNR:
__m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)
VPALIGNR:
__m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int n)
VPALIGNR __m512i _mm512_alignr_epi8 (__m512i a, __m512i b, const int n)
VPALIGNR __m512i _mm512_mask_alignr_epi8 (__m512i s, __mmask64 m, __m512i a, __m512i b, const int n)
VPALIGNR __m512i _mm512_maskz_alignr_epi8 ( __mmask64 m, __m512i a, __m512i b, const int n)
VPALIGNR __m256i _mm256_mask_alignr_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b, const int n)
VPALIGNR __m256i _mm256_maskz_alignr_epi8 (__mmask32 m, __m256i a, __m256i b, const int n)
VPALIGNR __m128i _mm_mask_alignr_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b, const int n)
VPALIGNR __m128i _mm_maskz_alignr_epi8 (__mmask16 m, __m128i a, __m128i b, const int n)
SIMD Floating-Point Exceptions
None.
PALIGNR — Packed Align Right
Vol. 2B 4-221
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
4-222 Vol. 2B
PALIGNR — Packed Align Right
INSTRUCTION SET REFERENCE, M-U
PAND—Logical AND
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
Description
CPUID
Feature Flag
0F DB /r1
RM
V/V
MMX
Bitwise AND mm/m64 and mm.
RM
V/V
SSE2
Bitwise AND of xmm2/m128 and xmm1.
RVM V/V
AVX
Bitwise AND of xmm3/m128 and xmm.
RVM V/V
AVX2
Bitwise AND of ymm2, and ymm3/m256 and
store result in ymm1.
EVEX.NDS.128.66.0F.W0 DB /r
VPANDD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND of packed doubleword integers in
xmm2 and xmm3/m128/m32bcst and store
result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W0 DB /r
VPANDD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND of packed doubleword integers in
ymm2 and ymm3/m256/m32bcst and store
result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W0 DB /r
VPANDD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
Bitwise AND of packed doubleword integers in
zmm2 and zmm3/m512/m32bcst and store
result in zmm1 using writemask k1.
EVEX.NDS.128.66.0F.W1 DB /r
VPANDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND of packed quadword integers in
xmm2 and xmm3/m128/m64bcst and store
result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W1 DB /r
VPANDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND of packed quadword integers in
ymm2 and ymm3/m256/m64bcst and store
result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W1 DB /r
VPANDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Bitwise AND of packed quadword integers in
zmm2 and zmm3/m512/m64bcst and store
result in zmm1 using writemask k1.
PAND mm, mm/m64
66 0F DB /r
PAND xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG DB /r
VPAND xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG DB /r
VPAND ymm1, ymm2, ymm3/.m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND operation on the first source operand and second source operand and stores the
result in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second
operands are 1, otherwise it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
PAND—Logical AND
Vol. 2B 4-223
INSTRUCTION SET REFERENCE, M-U
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1 at 32/64-bit granularity.
VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
Operation
PAND (64-bit operand)
DEST DEST AND SRC
PAND (128-bit Legacy SSE version)
DEST DEST AND SRC
DEST[VLMAX-1:128] (Unmodified)
VPAND (VEX.128 encoded version)
DEST SRC1 AND SRC2
DEST[VLMAX-1:128] 0
VPAND (VEX.256 encoded instruction)
DEST[255:0] (SRC1[255:0] AND SRC2[255:0])
DEST[VLMAX-1:256] 0
VPANDD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SRC1[i+31:i] BITWISE AND SRC2[31:0]
ELSE DEST[i+31:i] SRC1[i+31:i] BITWISE AND SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPANDQ (EVEX encoded versions)
4-224 Vol. 2B
PAND—Logical AND
INSTRUCTION SET REFERENCE, M-U
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] SRC1[i+63:i] BITWISE AND SRC2[63:0]
ELSE DEST[i+63:i] SRC1[i+63:i] BITWISE AND SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);
VPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_and_epi64( __m512i a, __m512i b);
VPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_maskz_and_epi64( __mmask8 k, __m512i a, __m512i b);
VPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);
VPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m256i _mm256_mask_and_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);
PAND: __m64 _mm_and_si64 (__m64 m1, __m64 m2)
(V)PAND:__m128i _mm_and_si128 ( __m128i a, __m128i b)
VPAND:
__m256i _mm256_and_si256 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
PAND—Logical AND
Vol. 2B 4-225
INSTRUCTION SET REFERENCE, M-U
PANDN—Logical AND NOT
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F DF /r1
RM
V/V
MMX
Bitwise AND NOT of mm/m64 and mm.
RM
V/V
SSE2
Bitwise AND NOT of xmm2/m128 and xmm1.
RVM V/V
AVX
Bitwise AND NOT of xmm3/m128 and xmm2.
RVM V/V
AVX2
Bitwise AND NOT of ymm2, and ymm3/m256
and store result in ymm1.
EVEX.NDS.128.66.0F.W0 DF /r
VPANDND xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND NOT of packed doubleword
integers in xmm2 and xmm3/m128/m32bcst
and store result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W0 DF /r
VPANDND ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND NOT of packed doubleword
integers in ymm2 and ymm3/m256/m32bcst
and store result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W0 DF /r
VPANDND zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
Bitwise AND NOT of packed doubleword
integers in zmm2 and zmm3/m512/m32bcst
and store result in zmm1 using writemask k1.
EVEX.NDS.128.66.0F.W1 DF /r
VPANDNQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND NOT of packed quadword
integers in xmm2 and xmm3/m128/m64bcst
and store result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W1 DF /r
VPANDNQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
Bitwise AND NOT of packed quadword
integers in ymm2 and ymm3/m256/m64bcst
and store result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W1 DF /r
VPANDNQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Bitwise AND NOT of packed quadword
integers in zmm2 and zmm3/m512/m64bcst
and store result in zmm1 using writemask k1.
PANDN mm, mm/m64
66 0F DF /r
PANDN xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG DF /r
VPANDN xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG DF /r
VPANDN ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical NOT operation on the first source operand, then performs bitwise AND with second
source operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corresponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
4-226 Vol. 2B
PANDN—Logical AND NOT
INSTRUCTION SET REFERENCE, M-U
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1 at 32/64-bit granularity.
VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
Operation
PANDN (64-bit operand)
DEST NOT(DEST) AND SRC
PANDN (128-bit Legacy SSE version)
DEST NOT(DEST) AND SRC
DEST[VLMAX-1:128] (Unmodified)
VPANDN (VEX.128 encoded version)
DEST NOT(SRC1) AND SRC2
DEST[VLMAX-1:128] 0
VPANDN (VEX.256 encoded instruction)
DEST[255:0] ((NOT SRC1[255:0]) AND SRC2[255:0])
DEST[VLMAX-1:256] 0
VPANDND (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] ((NOT SRC1[i+31:i]) AND SRC2[31:0])
ELSE DEST[i+31:i] ((NOT SRC1[i+31:i]) AND SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPANDNQ (EVEX encoded versions)
PANDN—Logical AND NOT
Vol. 2B 4-227
INSTRUCTION SET REFERENCE, M-U
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] ((NOT SRC1[i+63:i]) AND SRC2[63:0])
ELSE DEST[i+63:i] ((NOT SRC1[i+63:i]) AND SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPANDND __m512i _mm512_andnot_epi32( __m512i a, __m512i b);
VPANDND __m512i _mm512_mask_andnot_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPANDND __m512i _mm512_maskz_andnot_epi32( __mmask16 k, __m512i a, __m512i b);
VPANDND __m256i _mm256_mask_andnot_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDND __m256i _mm256_maskz_andnot_epi32( __mmask8 k, __m256i a, __m256i b);
VPANDND __m128i _mm_mask_andnot_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDND __m128i _mm_maskz_andnot_epi32( __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m512i _mm512_andnot_epi64( __m512i a, __m512i b);
VPANDNQ __m512i _mm512_mask_andnot_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPANDNQ __m512i _mm512_maskz_andnot_epi64( __mmask8 k, __m512i a, __m512i b);
VPANDNQ __m256i _mm256_mask_andnot_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz_andnot_epi64( __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m128i _mm_mask_andnot_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m128i _mm_maskz_andnot_epi64( __mmask8 k, __m128i a, __m128i b);
PANDN: __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)
(V)PANDN:__m128i _mm_andnot_si128 ( __m128i a, __m128i b)
VPANDN:
__m256i _mm256_andnot_si256 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
4-228 Vol. 2B
PANDN—Logical AND NOT
INSTRUCTION SET REFERENCE, M-U
PAUSE—Spin Loop Hint
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F3 90
PAUSE
NP
Valid
Valid
Gives hint to processor that improves
performance of spin-wait loops.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Improves the performance of spin-wait loops. When executing a “spin-wait loop,” processors will suffer a severe
performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE
instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint
to avoid the memory order violation in most situations, which greatly improves processor performance. For this
reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.
An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a
spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of
power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spinwait loop greatly reduces the processor’s power consumption.
This instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors.
In earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon
processors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors.
This instruction does not change the architectural state of the processor (that is, it performs essentially a delaying
no-op operation).
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
Execute_Next_Instruction(DELAY);
Numeric Exceptions
None.
Exceptions (All Operating Modes)
#UD
PAUSE—Spin Loop Hint
If the LOCK prefix is used.
Vol. 2B 4-229
INSTRUCTION SET REFERENCE, M-U
PAVGB/PAVGW—Average Packed Integers
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F E0 /r1
RM
V/V
SSE
Average packed unsigned byte integers from
mm2/m64 and mm1 with rounding.
RM
V/V
SSE2
Average packed unsigned byte integers from
xmm2/m128 and xmm1 with rounding.
RM
V/V
SSE
Average packed unsigned word integers from
mm2/m64 and mm1 with rounding.
RM
V/V
SSE2
Average packed unsigned word integers from
xmm2/m128 and xmm1 with rounding.
RVM V/V
AVX
Average packed unsigned byte integers from
xmm3/m128 and xmm2 with rounding.
RVM V/V
AVX
Average packed unsigned word integers from
xmm3/m128 and xmm2 with rounding.
RVM V/V
AVX2
Average packed unsigned byte integers from
ymm2, and ymm3/m256 with rounding and
store to ymm1.
RVM V/V
AVX2
Average packed unsigned word integers from
ymm2, ymm3/m256 with rounding to ymm1.
EVEX.NDS.128.66.0F.WIG E0 /r
VPAVGB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Average packed unsigned byte integers from
AVX512BW xmm2, and xmm3/m128 with rounding and
store to xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG E0 /r
VPAVGB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Average packed unsigned byte integers from
AVX512BW ymm2, and ymm3/m256 with rounding and
store to ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG E0 /r
VPAVGB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Average packed unsigned byte integers from
zmm2, and zmm3/m512 with rounding and
store to zmm1 under writemask k1.
EVEX.NDS.128.66.0F.WIG E3 /r
VPAVGW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Average packed unsigned word integers from
AVX512BW xmm2, xmm3/m128 with rounding to xmm1
under writemask k1.
EVEX.NDS.256.66.0F.WIG E3 /r
VPAVGW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Average packed unsigned word integers from
AVX512BW ymm2, ymm3/m256 with rounding to ymm1
under writemask k1.
EVEX.NDS.512.66.0F.WIG E3 /r
VPAVGW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Average packed unsigned word integers from
zmm2, zmm3/m512 with rounding to zmm1
under writemask k1.
PAVGB mm1, mm2/m64
66 0F E0, /r
PAVGB xmm1, xmm2/m128
0F E3 /r1
PAVGW mm1, mm2/m64
66 0F E3 /r
PAVGW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG E0 /r
VPAVGB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG E3 /r
VPAVGW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG E0 /r
VPAVGB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG E3 /r
VPAVGW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
4-230 Vol. 2B
PAVGB/PAVGW—Average Packed Integers
INSTRUCTION SET REFERENCE, M-U
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD average of the packed unsigned integers from the source operand (second operand) and the
destination operand (first operand), and stores the results in the destination operand. For each corresponding pair
of data elements in the first and second operands, the elements are added together, a 1 is added to the temporary
sum, and that result is shifted right one bit position.
The (V)PAVGB instruction operates on packed unsigned bytes and the (V)PAVGW instruction operates on packed
unsigned words.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register or a 512-bit memory location. The destination operand is a ZMM register.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits
(MAX_VL-1:128) of the corresponding register destination are zeroed.
Operation
PAVGB (with 64-bit operands)
DEST[7:0] ← (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
(* Repeat operation performed for bytes 2 through 6 *)
DEST[63:56] ← (SRC[63:56] + DEST[63:56] + 1) >> 1;
PAVGW (with 64-bit operands)
DEST[15:0] ← (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
(* Repeat operation performed for words 2 and 3 *)
DEST[63:48] ← (SRC[63:48] + DEST[63:48] + 1) >> 1;
PAVGB (with 128-bit operands)
DEST[7:0] ← (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
(* Repeat operation performed for bytes 2 through 14 *)
DEST[127:120] ← (SRC[127:120] + DEST[127:120] + 1) >> 1;
PAVGW (with 128-bit operands)
DEST[15:0] ← (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
(* Repeat operation performed for words 2 through 6 *)
DEST[127:112] ← (SRC[127:112] + DEST[127:112] + 1) >> 1;
PAVGB/PAVGW—Average Packed Integers
Vol. 2B 4-231
INSTRUCTION SET REFERENCE, M-U
VPAVGB (VEX.128 encoded version)
DEST[7:0] (SRC1[7:0] + SRC2[7:0] + 1) >> 1;
(* Repeat operation performed for bytes 2 through 15 *)
DEST[127:120] (SRC1[127:120] + SRC2[127:120] + 1) >> 1
DEST[VLMAX-1:128] 0
VPAVGW (VEX.128 encoded version)
DEST[15:0] (SRC1[15:0] + SRC2[15:0] + 1) >> 1;
(* Repeat operation performed for 16-bit words 2 through 7 *)
DEST[127:112] (SRC1[127:112] + SRC2[127:112] + 1) >> 1
DEST[VLMAX-1:128] 0
VPAVGB (VEX.256 encoded instruction)
DEST[7:0] (SRC1[7:0] + SRC2[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
(* Repeat operation performed for bytes 2 through 31)
DEST[255:248] (SRC1[255:248] + SRC2[255:248] + 1) >> 1;
VPAVGW (VEX.256 encoded instruction)
DEST[15:0] (SRC1[15:0] + SRC2[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
(* Repeat operation performed for words 2 through 15)
DEST[255:14]) (SRC1[255:240] + SRC2[255:240] + 1) >> 1;
VPAVGB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] (SRC1[i+7:i] + SRC2[i+7:i] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPAVGW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] (SRC1[i+15:i] + SRC2[i+15:i] + 1) >> 1
; (* Temp sum before shifting is 17 bits *)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
4-232 Vol. 2B
PAVGB/PAVGW—Average Packed Integers
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalents
VPAVGB __m512i _mm512_avg_epu8( __m512i a, __m512i b);
VPAVGW __m512i _mm512_avg_epu16( __m512i a, __m512i b);
VPAVGB __m512i _mm512_mask_avg_epu8(__m512i s, __mmask64 m, __m512i a, __m512i b);
VPAVGW __m512i _mm512_mask_avg_epu16(__m512i s, __mmask32 m, __m512i a, __m512i b);
VPAVGB __m512i _mm512_maskz_avg_epu8( __mmask64 m, __m512i a, __m512i b);
VPAVGW __m512i _mm512_maskz_avg_epu16( __mmask32 m, __m512i a, __m512i b);
VPAVGB __m256i _mm256_mask_avg_epu8(__m256i s, __mmask32 m, __m256i a, __m256i b);
VPAVGW __m256i _mm256_mask_avg_epu16(__m256i s, __mmask16 m, __m256i a, __m256i b);
VPAVGB __m256i _mm256_maskz_avg_epu8( __mmask32 m, __m256i a, __m256i b);
VPAVGW __m256i _mm256_maskz_avg_epu16( __mmask16 m, __m256i a, __m256i b);
VPAVGB __m128i _mm_mask_avg_epu8(__m128i s, __mmask16 m, __m128i a, __m128i b);
VPAVGW __m128i _mm_mask_avg_epu16(__m128i s, __mmask8 m, __m128i a, __m128i b);
VPAVGB __m128i _mm_maskz_avg_epu8( __mmask16 m, __m128i a, __m128i b);
VPAVGW __m128i _mm_maskz_avg_epu16( __mmask8 m, __m128i a, __m128i b);
PAVGB: __m64 _mm_avg_pu8 (__m64 a, __m64 b)
PAVGW: __m64 _mm_avg_pu16 (__m64 a, __m64 b)
(V)PAVGB: __m128i _mm_avg_epu8 ( __m128i a, __m128i b)
(V)PAVGW: __m128i _mm_avg_epu16 ( __m128i a, __m128i b)
VPAVGB:
__m256i _mm256_avg_epu8 ( __m256i a, __m256i b)
VPAVGW:
__m256i _mm256_avg_epu16 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
PAVGB/PAVGW—Average Packed Integers
Vol. 2B 4-233
INSTRUCTION SET REFERENCE, M-U
PBLENDVB — Variable Blend Packed Bytes
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 38 10 /r
PBLENDVB xmm1, xmm2/m128,
RM
V/V
SSE4_1
Select byte values from xmm1 and
xmm2/m128 from mask specified in the high
bit of each byte in XMM0 and store the
values into xmm1.
VEX.NDS.128.66.0F3A.W0 4C /r /is4
VPBLENDVB xmm1, xmm2, xmm3/m128, xmm4
RVMR V/V
AVX
Select byte values from xmm2 and
xmm3/m128 using mask bits in the specified
mask register, xmm4, and store the values
into xmm1.
VEX.NDS.256.66.0F3A.W0 4C /r /is4
VPBLENDVB ymm1, ymm2, ymm3/m256, ymm4
RVMR V/V
AVX2
Select byte values from ymm2 and
ymm3/m256 from mask specified in the high
bit of each byte in ymm4 and store the
values into ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
RVMR
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8[7:4]
Description
Conditionally copies byte elements from the source operand (second operand) to the destination operand (first
operand) depending on mask bits defined in the implicit third register argument, XMM0. The mask bits are the most
significant bit in each byte element of the XMM0 register.
If a mask bit is “1", then the corresponding byte element in the source operand is copied to the destination, else
the byte element in the destination operand is left unchanged.
The register assignment of the implicit third operand is defined to be the architectural register XMM0.
128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined
to be the architectural register XMM0. An attempt to execute PBLENDVB with a VEX prefix will cause #UD.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed. VEX.L
must be 0, otherwise the instruction will #UD. VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and the destination operand are YMM registers. The second
source operand is an YMM register or 256-bit memory location. The third source register is an YMM register and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored.
VPBLENDVB permits the mask to be any XMM or YMM register. In contrast, PBLENDVB treats XMM0 implicitly as the
mask and do not support non-destructive destination operation. An attempt to execute PBLENDVB encoded with a
VEX prefix will cause a #UD exception.
Operation
PBLENDVB (128-bit Legacy SSE version)
MASK XMM0
IF (MASK[7] = 1) THEN DEST[7:0] SRC[7:0];
ELSE DEST[7:0] DEST[7:0];
IF (MASK[15] = 1) THEN DEST[15:8] SRC[15:8];
4-234 Vol. 2B
PBLENDVB — Variable Blend Packed Bytes
INSTRUCTION SET REFERENCE, M-U
ELSE DEST[15:8] DEST[15:8];
IF (MASK[23] = 1) THEN DEST[23:16] SRC[23:16]
ELSE DEST[23:16] DEST[23:16];
IF (MASK[31] = 1) THEN DEST[31:24] SRC[31:24]
ELSE DEST[31:24] DEST[31:24];
IF (MASK[39] = 1) THEN DEST[39:32] SRC[39:32]
ELSE DEST[39:32] DEST[39:32];
IF (MASK[47] = 1) THEN DEST[47:40] SRC[47:40]
ELSE DEST[47:40] DEST[47:40];
IF (MASK[55] = 1) THEN DEST[55:48] SRC[55:48]
ELSE DEST[55:48] DEST[55:48];
IF (MASK[63] = 1) THEN DEST[63:56] SRC[63:56]
ELSE DEST[63:56] DEST[63:56];
IF (MASK[71] = 1) THEN DEST[71:64] SRC[71:64]
ELSE DEST[71:64] DEST[71:64];
IF (MASK[79] = 1) THEN DEST[79:72] SRC[79:72]
ELSE DEST[79:72] DEST[79:72];
IF (MASK[87] = 1) THEN DEST[87:80] SRC[87:80]
ELSE DEST[87:80] DEST[87:80];
IF (MASK[95] = 1) THEN DEST[95:88] SRC[95:88]
ELSE DEST[95:88] DEST[95:88];
IF (MASK[103] = 1) THEN DEST[103:96] SRC[103:96]
ELSE DEST[103:96] DEST[103:96];
IF (MASK[111] = 1) THEN DEST[111:104] SRC[111:104]
ELSE DEST[111:104] DEST[111:104];
IF (MASK[119] = 1) THEN DEST[119:112] SRC[119:112]
ELSE DEST[119:112] DEST[119:112];
IF (MASK[127] = 1) THEN DEST[127:120] SRC[127:120]
ELSE DEST[127:120] DEST[127:120])
DEST[VLMAX-1:128] (Unmodified)
VPBLENDVB (VEX.128 encoded version)
MASK SRC3
IF (MASK[7] = 1) THEN DEST[7:0] SRC2[7:0];
ELSE DEST[7:0] SRC1[7:0];
IF (MASK[15] = 1) THEN DEST[15:8] SRC2[15:8];
ELSE DEST[15:8] SRC1[15:8];
IF (MASK[23] = 1) THEN DEST[23:16] SRC2[23:16]
ELSE DEST[23:16] SRC1[23:16];
IF (MASK[31] = 1) THEN DEST[31:24] SRC2[31:24]
ELSE DEST[31:24] SRC1[31:24];
IF (MASK[39] = 1) THEN DEST[39:32] SRC2[39:32]
ELSE DEST[39:32] SRC1[39:32];
IF (MASK[47] = 1) THEN DEST[47:40] SRC2[47:40]
ELSE DEST[47:40] SRC1[47:40];
IF (MASK[55] = 1) THEN DEST[55:48] SRC2[55:48]
ELSE DEST[55:48] SRC1[55:48];
IF (MASK[63] = 1) THEN DEST[63:56] SRC2[63:56]
ELSE DEST[63:56] SRC1[63:56];
IF (MASK[71] = 1) THEN DEST[71:64] SRC2[71:64]
ELSE DEST[71:64] SRC1[71:64];
IF (MASK[79] = 1) THEN DEST[79:72] SRC2[79:72]
ELSE DEST[79:72] SRC1[79:72];
IF (MASK[87] = 1) THEN DEST[87:80] SRC2[87:80]
PBLENDVB — Variable Blend Packed Bytes
Vol. 2B 4-235
INSTRUCTION SET REFERENCE, M-U
ELSE DEST[87:80] SRC1[87:80];
IF (MASK[95] = 1) THEN DEST[95:88] SRC2[95:88]
ELSE DEST[95:88] SRC1[95:88];
IF (MASK[103] = 1) THEN DEST[103:96] SRC2[103:96]
ELSE DEST[103:96] SRC1[103:96];
IF (MASK[111] = 1) THEN DEST[111:104] SRC2[111:104]
ELSE DEST[111:104] SRC1[111:104];
IF (MASK[119] = 1) THEN DEST[119:112] SRC2[119:112]
ELSE DEST[119:112] SRC1[119:112];
IF (MASK[127] = 1) THEN DEST[127:120] SRC2[127:120]
ELSE DEST[127:120] SRC1[127:120])
DEST[VLMAX-1:128] 0
VPBLENDVB (VEX.256 encoded version)
MASK SRC3
IF (MASK[7] == 1) THEN DEST[7:0] SRC2[7:0];
ELSE DEST[7:0] SRC1[7:0];
IF (MASK[15] == 1) THEN DEST[15:8] SRC2[15:8];
ELSE DEST[15:8] SRC1[15:8];
IF (MASK[23] == 1) THEN DEST[23:16] SRC2[23:16]
ELSE DEST[23:16] SRC1[23:16];
IF (MASK[31] == 1) THEN DEST[31:24] SRC2[31:24]
ELSE DEST[31:24] SRC1[31:24];
IF (MASK[39] == 1) THEN DEST[39:32] SRC2[39:32]
ELSE DEST[39:32] SRC1[39:32];
IF (MASK[47] == 1) THEN DEST[47:40] SRC2[47:40]
ELSE DEST[47:40] SRC1[47:40];
IF (MASK[55] == 1) THEN DEST[55:48] SRC2[55:48]
ELSE DEST[55:48] SRC1[55:48];
IF (MASK[63] == 1) THEN DEST[63:56] SRC2[63:56]
ELSE DEST[63:56] SRC1[63:56];
IF (MASK[71] == 1) THEN DEST[71:64] SRC2[71:64]
ELSE DEST[71:64] SRC1[71:64];
IF (MASK[79] == 1) THEN DEST[79:72] SRC2[79:72]
ELSE DEST[79:72] SRC1[79:72];
IF (MASK[87] == 1) THEN DEST[87:80] SRC2[87:80]
ELSE DEST[87:80] SRC1[87:80];
IF (MASK[95] == 1) THEN DEST[95:88] SRC2[95:88]
ELSE DEST[95:88] SRC1[95:88];
IF (MASK[103] == 1) THEN DEST[103:96] SRC2[103:96]
ELSE DEST[103:96] SRC1[103:96];
IF (MASK[111] == 1) THEN DEST[111:104] SRC2[111:104]
ELSE DEST[111:104] SRC1[111:104];
IF (MASK[119] == 1) THEN DEST[119:112] SRC2[119:112]
ELSE DEST[119:112] SRC1[119:112];
IF (MASK[127] == 1) THEN DEST[127:120] SRC2[127:120]
ELSE DEST[127:120] SRC1[127:120])
IF (MASK[135] == 1) THEN DEST[135:128] SRC2[135:128];
ELSE DEST[135:128] SRC1[135:128];
IF (MASK[143] == 1) THEN DEST[143:136] SRC2[143:136];
ELSE DEST[[143:136] SRC1[143:136];
IF (MASK[151] == 1) THEN DEST[151:144] SRC2[151:144]
ELSE DEST[151:144] SRC1[151:144];
IF (MASK[159] == 1) THEN DEST[159:152] SRC2[159:152]
4-236 Vol. 2B
PBLENDVB — Variable Blend Packed Bytes
INSTRUCTION SET REFERENCE, M-U
ELSE DEST[159:152] SRC1[159:152];
IF (MASK[167] == 1) THEN DEST[167:160] SRC2[167:160]
ELSE DEST[167:160] SRC1[167:160];
IF (MASK[175] == 1) THEN DEST[175:168] SRC2[175:168]
ELSE DEST[175:168] SRC1[175:168];
IF (MASK[183] == 1) THEN DEST[183:176] SRC2[183:176]
ELSE DEST[183:176] SRC1[183:176];
IF (MASK[191] == 1) THEN DEST[191:184] SRC2[191:184]
ELSE DEST[191:184] SRC1[191:184];
IF (MASK[199] == 1) THEN DEST[199:192] SRC2[199:192]
ELSE DEST[199:192] SRC1[199:192];
IF (MASK[207] == 1) THEN DEST[207:200] SRC2[207:200]
ELSE DEST[207:200] SRC1[207:200]
IF (MASK[215] == 1) THEN DEST[215:208] SRC2[215:208]
ELSE DEST[215:208] SRC1[215:208];
IF (MASK[223] == 1) THEN DEST[223:216] SRC2[223:216]
ELSE DEST[223:216] SRC1[223:216];
IF (MASK[231] == 1) THEN DEST[231:224] SRC2[231:224]
ELSE DEST[231:224] SRC1[231:224];
IF (MASK[239] == 1) THEN DEST[239:232] SRC2[239:232]
ELSE DEST[239:232] SRC1[239:232];
IF (MASK[247] == 1) THEN DEST[247:240] SRC2[247:240]
ELSE DEST[247:240] SRC1[247:240];
IF (MASK[255] == 1) THEN DEST[255:248] SRC2[255:248]
ELSE DEST[255:248] SRC1[255:248]
Intel C/C++ Compiler Intrinsic Equivalent
(V)PBLENDVB:
__m128i _mm_blendv_epi8 (__m128i v1, __m128i v2, __m128i mask);
VPBLENDVB:
__m256i _mm256_blendv_epi8 (__m256i v1, __m256i v2, __m256i mask);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.W = 1.
PBLENDVB — Variable Blend Packed Bytes
Vol. 2B 4-237
INSTRUCTION SET REFERENCE, M-U
PBLENDW — Blend Packed Words
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 0E /r ib
PBLENDW xmm1, xmm2/m128, imm8
RMI
V/V
SSE4_1
Select words from xmm1 and xmm2/m128
from mask specified in imm8 and store the
values into xmm1.
VEX.NDS.128.66.0F3A.WIG 0E /r ib
VPBLENDW xmm1, xmm2, xmm3/m128, imm8
RVMI V/V
AVX
Select words from xmm2 and xmm3/m128
from mask specified in imm8 and store the
values into xmm1.
VEX.NDS.256.66.0F3A.WIG 0E /r ib
VPBLENDW ymm1, ymm2, ymm3/m256, imm8
RVMI V/V
AVX2
Select words from ymm2 and ymm3/m256
from mask specified in imm8 and store the
values into ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Words from the source operand (second operand) are conditionally written to the destination operand (first
operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask
that determines whether the corresponding word in the destination is copied from the source. If a bit in the mask,
corresponding to a word, is “1", then the word is copied, else the word element in the destination operand is
unchanged.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
Operation
PBLENDW (128-bit Legacy SSE version)
IF (imm8[0] = 1) THEN DEST[15:0] SRC[15:0]
ELSE DEST[15:0] DEST[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] SRC[31:16]
ELSE DEST[31:16] DEST[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] SRC[47:32]
ELSE DEST[47:32] DEST[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] SRC[63:48]
ELSE DEST[63:48] DEST[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] SRC[79:64]
ELSE DEST[79:64] DEST[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] SRC[95:80]
ELSE DEST[95:80] DEST[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] SRC[111:96]
ELSE DEST[111:96] DEST[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] SRC[127:112]
4-238 Vol. 2B
PBLENDW — Blend Packed Words
INSTRUCTION SET REFERENCE, M-U
ELSE DEST[127:112] DEST[127:112]
VPBLENDW (VEX.128 encoded version)
IF (imm8[0] = 1) THEN DEST[15:0] SRC2[15:0]
ELSE DEST[15:0] SRC1[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] SRC2[31:16]
ELSE DEST[31:16] SRC1[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] SRC2[47:32]
ELSE DEST[47:32] SRC1[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] SRC2[63:48]
ELSE DEST[63:48] SRC1[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] SRC2[79:64]
ELSE DEST[79:64] SRC1[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] SRC2[95:80]
ELSE DEST[95:80] SRC1[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] SRC2[111:96]
ELSE DEST[111:96] SRC1[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] SRC2[127:112]
ELSE DEST[127:112] SRC1[127:112]
DEST[VLMAX-1:128] 0
VPBLENDW (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[15:0] SRC2[15:0]
ELSE DEST[15:0] SRC1[15:0]
IF (imm8[1] == 1) THEN DEST[31:16] SRC2[31:16]
ELSE DEST[31:16] SRC1[31:16]
IF (imm8[2] == 1) THEN DEST[47:32] SRC2[47:32]
ELSE DEST[47:32] SRC1[47:32]
IF (imm8[3] == 1) THEN DEST[63:48] SRC2[63:48]
ELSE DEST[63:48] SRC1[63:48]
IF (imm8[4] == 1) THEN DEST[79:64] SRC2[79:64]
ELSE DEST[79:64] SRC1[79:64]
IF (imm8[5] == 1) THEN DEST[95:80] SRC2[95:80]
ELSE DEST[95:80] SRC1[95:80]
IF (imm8[6] == 1) THEN DEST[111:96] SRC2[111:96]
ELSE DEST[111:96] SRC1[111:96]
IF (imm8[7] == 1) THEN DEST[127:112] SRC2[127:112]
ELSE DEST[127:112] SRC1[127:112]
IF (imm8[0] == 1) THEN DEST[143:128] SRC2[143:128]
ELSE DEST[143:128] SRC1[143:128]
IF (imm8[1] == 1) THEN DEST[159:144] SRC2[159:144]
ELSE DEST[159:144] SRC1[159:144]
IF (imm8[2] == 1) THEN DEST[175:160] SRC2[175:160]
ELSE DEST[175:160] SRC1[175:160]
IF (imm8[3] == 1) THEN DEST[191:176] SRC2[191:176]
ELSE DEST[191:176] SRC1[191:176]
IF (imm8[4] == 1) THEN DEST[207:192] SRC2[207:192]
ELSE DEST[207:192] SRC1[207:192]
IF (imm8[5] == 1) THEN DEST[223:208] SRC2[223:208]
ELSE DEST[223:208] SRC1[223:208]
IF (imm8[6] == 1) THEN DEST[239:224] SRC2[239:224]
ELSE DEST[239:224] SRC1[239:224]
IF (imm8[7] == 1) THEN DEST[255:240] SRC2[255:240]
ELSE DEST[255:240] SRC1[255:240]
PBLENDW — Blend Packed Words
Vol. 2B 4-239
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
(V)PBLENDW:
__m128i _mm_blend_epi16 (__m128i v1, __m128i v2, const int mask);
VPBLENDW:
__m256i _mm256_blend_epi16 (__m256i v1, __m256i v2, const int mask)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
4-240 Vol. 2B
If VEX.L = 1 and AVX2 = 0.
PBLENDW — Blend Packed Words
INSTRUCTION SET REFERENCE, M-U
PCLMULQDQ - Carry-Less Multiplication Quadword
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 44 /r ib
PCLMULQDQ xmm1, xmm2/m128, imm8
RMI
V/V
PCLMULQDQ
Carry-less multiplication of one quadword of
xmm1 by one quadword of xmm2/m128,
stores the 128-bit result in xmm1. The immediate is used to determine which quadwords
of xmm1 and xmm2/m128 should be used.
VEX.NDS.128.66.0F3A.WIG 44 /r ib
VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8
RVMI V/V
Both PCLMULQDQ
and AVX
flags
Carry-less multiplication of one quadword of
xmm2 by one quadword of xmm3/m128,
stores the 128-bit result in xmm1. The immediate is used to determine which quadwords
of xmm2 and xmm3/m128 should be used.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Performs a carry-less multiplication of two quadwords, selected from the first source and second source operand
according to the value of the immediate byte. Bits 4 and 0 are used to select which 64-bit half of each operand to
use according to Table 4-13, other bits of the immediate byte are ignored.
Table 4-13. PCLMULQDQ Quadword Selection of Immediate Byte
Imm[4]
Imm[0]
PCLMULQDQ Operation
SRC21[63:0],
0
0
CL_MUL(
SRC1[63:0] )
0
1
CL_MUL( SRC2[63:0], SRC1[127:64] )
1
0
CL_MUL( SRC2[127:64], SRC1[63:0] )
1
1
CL_MUL( SRC2[127:64], SRC1[127:64] )
NOTES:
1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination operand.
The first source operand and the destination operand are the same and must be an XMM register. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged.
Compilers and assemblers may implement the following pseudo-op syntax to simply programming and emit the
required encoding for Imm8.
Table 4-14. Pseudo-Op and PCLMULQDQ Implementation
Pseudo-Op
Imm8 Encoding
PCLMULLQLQDQ xmm1, xmm2
0000_0000B
PCLMULHQLQDQ xmm1, xmm2
0000_0001B
PCLMULLQHQDQ xmm1, xmm2
0001_0000B
PCLMULHQHQDQ xmm1, xmm2
0001_0001B
PCLMULQDQ - Carry-Less Multiplication Quadword
Vol. 2B 4-241
INSTRUCTION SET REFERENCE, M-U
Operation
PCLMULQDQ
IF (Imm8[0] = 0 )
THEN
TEMP1 SRC1 [63:0];
ELSE
TEMP1 SRC1 [127:64];
FI
IF (Imm8[4] = 0 )
THEN
TEMP2 SRC2 [63:0];
ELSE
TEMP2 SRC2 [127:64];
FI
For i = 0 to 63 {
TmpB [ i ] (TEMP1[ 0 ] and TEMP2[ i ]);
For j = 1 to i {
TmpB [ i ] TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])
}
DEST[ i ] TmpB[ i ];
}
For i = 64 to 126 {
TmpB [ i ] 0;
For j = i - 63 to 63 {
TmpB [ i ] TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])
}
DEST[ i ] TmpB[ i ];
}
DEST[127] 0;
DEST[VLMAX-1:128] (Unmodified)
VPCLMULQDQ
IF (Imm8[0] = 0 )
THEN
TEMP1 SRC1 [63:0];
ELSE
TEMP1 SRC1 [127:64];
FI
IF (Imm8[4] = 0 )
THEN
TEMP2 SRC2 [63:0];
ELSE
TEMP2 SRC2 [127:64];
FI
For i = 0 to 63 {
TmpB [ i ] (TEMP1[ 0 ] and TEMP2[ i ]);
For j = 1 to i {
TmpB [i] TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])
}
DEST[i] TmpB[i];
}
For i = 64 to 126 {
TmpB [ i ] 0;
For j = i - 63 to 63 {
4-242 Vol. 2B
PCLMULQDQ - Carry-Less Multiplication Quadword
INSTRUCTION SET REFERENCE, M-U
TmpB [i] TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])
}
DEST[i] TmpB[i];
}
DEST[VLMAX-1:127] 0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)PCLMULQDQ:
__m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4, additionally
#UD
If VEX.L = 1.
PCLMULQDQ - Carry-Less Multiplication Quadword
Vol. 2B 4-243
INSTRUCTION SET REFERENCE, M-U
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 74 /r1
RM
V/V
MMX
Compare packed bytes in mm/m64 and mm
for equality.
RM
V/V
SSE2
Compare packed bytes in xmm2/m128 and
xmm1 for equality.
RM
V/V
MMX
Compare packed words in mm/m64 and mm
for equality.
RM
V/V
SSE2
Compare packed words in xmm2/m128 and
xmm1 for equality.
RM
V/V
MMX
Compare packed doublewords in mm/m64 and
mm for equality.
RM
V/V
SSE2
Compare packed doublewords in xmm2/m128
and xmm1 for equality.
RVM V/V
AVX
Compare packed bytes in xmm3/m128 and
xmm2 for equality.
RVM V/V
AVX
Compare packed words in xmm3/m128 and
xmm2 for equality.
RVM V/V
AVX
Compare packed doublewords in xmm3/m128
and xmm2 for equality.
VEX.NDS.256.66.0F.WIG 74 /r
VPCMPEQB ymm1, ymm2, ymm3 /m256
RVM V/V
AVX2
Compare packed bytes in ymm3/m256 and
ymm2 for equality.
VEX.NDS.256.66.0F.WIG 75 /r
RVM V/V
AVX2
Compare packed words in ymm3/m256 and
ymm2 for equality.
RVM V/V
AVX2
Compare packed doublewords in ymm3/m256
and ymm2 for equality.
EVEX.NDS.128.66.0F.W0 76 /r
VPCMPEQD k1 {k2}, xmm2, xmm3/m128/m32bcst
FV
V/V
AVX512V Compare Equal between int32 vector xmm2
L
and int32 vector xmm3/m128/m32bcst, and
AVX512F set vector mask k1 to reflect the
zero/nonzero status of each element of the
result, under writemask.
EVEX.NDS.256.66.0F.W0 76 /r
VPCMPEQD k1 {k2}, ymm2, ymm3/m256/m32bcst
FV
V/V
AVX512V Compare Equal between int32 vector ymm2
L
and int32 vector ymm3/m256/m32bcst, and
AVX512F set vector mask k1 to reflect the
zero/nonzero status of each element of the
result, under writemask.
EVEX.NDS.512.66.0F.W0 76 /r
VPCMPEQD k1 {k2}, zmm2, zmm3/m512/m32bcst
FV
V/V
AVX512F
Compare Equal between int32 vectors in
zmm2 and zmm3/m512/m32bcst, and set
destination k1 according to the comparison
results under writemask k2.
EVEX.NDS.128.66.0F.WIG 74 /r
VPCMPEQB k1 {k2}, xmm2, xmm3 /m128
FVM V/V
AVX512V
L
AVX512B
W
Compare packed bytes in xmm3/m128 and
xmm2 for equality and set vector mask k1 to
reflect the zero/nonzero status of each
element of the result, under writemask.
PCMPEQB mm, mm/m64
66 0F 74 /r
PCMPEQB xmm1, xmm2/m128
0F 75 /r1
PCMPEQW mm, mm/m64
66 0F 75 /r
PCMPEQW xmm1, xmm2/m128
0F 76 /r1
PCMPEQD mm, mm/m64
66 0F 76 /r
PCMPEQD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 74 /r
VPCMPEQB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 75 /r
VPCMPEQW xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 76 /r
VPCMPEQD xmm1, xmm2, xmm3/m128
VPCMPEQW ymm1, ymm2, ymm3 /m256
VEX.NDS.256.66.0F.WIG 76 /r
VPCMPEQD ymm1, ymm2, ymm3 /m256
4-244 Vol. 2B
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.256.66.0F.WIG 74 /r
VPCMPEQB k1 {k2}, ymm2, ymm3 /m256
FVM V/V
AVX512V
L
AVX512B
W
Compare packed bytes in ymm3/m256 and
ymm2 for equality and set vector mask k1 to
reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.512.66.0F.WIG 74 /r
VPCMPEQB k1 {k2}, zmm2, zmm3 /m512
FVM V/V
AVX512B
W
Compare packed bytes in zmm3/m512 and
zmm2 for equality and set vector mask k1 to
reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.128.66.0F.WIG 75 /r
VPCMPEQW k1 {k2}, xmm2, xmm3 /m128
FVM V/V
AVX512V
L
AVX512B
W
Compare packed words in xmm3/m128 and
xmm2 for equality and set vector mask k1 to
reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.256.66.0F.WIG 75 /r
VPCMPEQW k1 {k2}, ymm2, ymm3 /m256
FVM V/V
AVX512V
L
AVX512B
W
Compare packed words in ymm3/m256 and
ymm2 for equality and set vector mask k1 to
reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.512.66.0F.WIG 75 /r
VPCMPEQW k1 {k2}, zmm2, zmm3 /m512
FVM V/V
AVX512B
W
Compare packed words in zmm3/m512 and
zmm2 for equality and set vector mask k1 to
reflect the zero/nonzero status of each
element of the result, under writemask.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD compare for equality of the packed bytes, words, or doublewords in the destination operand (first
operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data
element in the destination operand is set to all 1s; otherwise, it is set to all 0s.
The (V)PCMPEQB instruction compares the corresponding bytes in the destination and source operands; the
(V)PCMPEQW instruction compares the corresponding words in the destination and source operands; and the
(V)PCMPEQD instruction compares the corresponding doublewords in the destination and source operands.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal
Vol. 2B 4-245
INSTRUCTION SET REFERENCE, M-U
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
EVEX encoded VPCMPEQD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.
EVEX encoded VPCMPEQB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand
(first operand) is a mask register updated according to the writemask k2.
Operation
PCMPEQB (with 64-bit operands)
IF DEST[7:0] = SRC[7:0]
THEN DEST[7:0) ← FFH;
ELSE DEST[7:0] ← 0; FI;
(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
IF DEST[63:56] = SRC[63:56]
THEN DEST[63:56] ← FFH;
ELSE DEST[63:56] ← 0; FI;
COMPARE_BYTES_EQUAL (SRC1, SRC2)
IF SRC1[7:0] = SRC2[7:0]
THEN DEST[7:0] FFH;
ELSE DEST[7:0] 0; FI;
(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
IF SRC1[127:120] = SRC2[127:120]
THEN DEST[127:120] FFH;
ELSE DEST[127:120] 0; FI;
COMPARE_WORDS_EQUAL (SRC1, SRC2)
IF SRC1[15:0] = SRC2[15:0]
THEN DEST[15:0] FFFFH;
ELSE DEST[15:0] 0; FI;
(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
IF SRC1[127:112] = SRC2[127:112]
THEN DEST[127:112] FFFFH;
ELSE DEST[127:112] 0; FI;
COMPARE_DWORDS_EQUAL (SRC1, SRC2)
IF SRC1[31:0] = SRC2[31:0]
THEN DEST[31:0] FFFFFFFFH;
ELSE DEST[31:0] 0; FI;
(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
IF SRC1[127:96] = SRC2[127:96]
THEN DEST[127:96] FFFFFFFFH;
ELSE DEST[127:96] 0; FI;
PCMPEQB (with 128-bit operands)
DEST[127:0] COMPARE_BYTES_EQUAL(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
VPCMPEQB (VEX.128 encoded version)
DEST[127:0] COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])
4-246 Vol. 2B
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal
INSTRUCTION SET REFERENCE, M-U
DEST[VLMAX-1:128] 0
VPCMPEQB (VEX.256 encoded version)
DEST[127:0] COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPEQB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
CMP SRC1[i+7:i] == SRC2[i+7:i];
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
PCMPEQW (with 64-bit operands)
IF DEST[15:0] = SRC[15:0]
THEN DEST[15:0] ← FFFFH;
ELSE DEST[15:0] ← 0; FI;
(* Continue comparison of 2nd and 3rd words in DEST and SRC *)
IF DEST[63:48] = SRC[63:48]
THEN DEST[63:48] ← FFFFH;
ELSE DEST[63:48] ← 0; FI;
PCMPEQW (with 128-bit operands)
DEST[127:0] COMPARE_WORDS_EQUAL(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
VPCMPEQW (VEX.128 encoded version)
DEST[127:0] COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[VLMAX-1:128] 0
VPCMPEQW (VEX.256 encoded version)
DEST[127:0] COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPEQW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
CMP SRC1[i+15:i] == SRC2[i+15:i];
IF CMP = TRUE
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal
Vol. 2B 4-247
INSTRUCTION SET REFERENCE, M-U
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
DEST[j] 0
ELSE
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
; zeroing-masking onlyFI;
PCMPEQD (with 64-bit operands)
IF DEST[31:0] = SRC[31:0]
THEN DEST[31:0] ← FFFFFFFFH;
ELSE DEST[31:0] ← 0; FI;
IF DEST[63:32] = SRC[63:32]
THEN DEST[63:32] ← FFFFFFFFH;
ELSE DEST[63:32] ← 0; FI;
PCMPEQD (with 128-bit operands)
DEST[127:0] COMPARE_DWORDS_EQUAL(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
VPCMPEQD (VEX.128 encoded version)
DEST[127:0] COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[VLMAX-1:128] 0
VPCMPEQD (VEX.256 encoded version)
DEST[127:0] COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPEQD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+31:i] = SRC2[31:0];
ELSE CMP SRC1[i+31:i] = SRC2[i+31:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPCMPEQB __mmask64 _mm512_cmpeq_epi8_mask(__m512i a, __m512i b);
VPCMPEQB __mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i a, __m512i b);
VPCMPEQB __mmask32 _mm256_cmpeq_epi8_mask(__m256i a, __m256i b);
VPCMPEQB __mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i a, __m256i b);
VPCMPEQB __mmask16 _mm_cmpeq_epi8_mask(__m128i a, __m128i b);
VPCMPEQB __mmask16 _mm_mask_cmpeq_epi8_mask(__mmask16 k, __m128i a, __m128i b);
4-248 Vol. 2B
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal
INSTRUCTION SET REFERENCE, M-U
VPCMPEQW __mmask32 _mm512_cmpeq_epi16_mask(__m512i a, __m512i b);
VPCMPEQW __mmask32 _mm512_mask_cmpeq_epi16_mask(__mmask32 k, __m512i a, __m512i b);
VPCMPEQW __mmask16 _mm256_cmpeq_epi16_mask(__m256i a, __m256i b);
VPCMPEQW __mmask16 _mm256_mask_cmpeq_epi16_mask(__mmask16 k, __m256i a, __m256i b);
VPCMPEQW __mmask8 _mm_cmpeq_epi16_mask(__m128i a, __m128i b);
VPCMPEQW __mmask8 _mm_mask_cmpeq_epi16_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPEQD __mmask16 _mm512_cmpeq_epi32_mask( __m512i a, __m512i b);
VPCMPEQD __mmask16 _mm512_mask_cmpeq_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPEQD __mmask8 _mm256_cmpeq_epi32_mask(__m256i a, __m256i b);
VPCMPEQD __mmask8 _mm256_mask_cmpeq_epi32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPEQD __mmask8 _mm_cmpeq_epi32_mask(__m128i a, __m128i b);
VPCMPEQD __mmask8 _mm_mask_cmpeq_epi32_mask(__mmask8 k, __m128i a, __m128i b);
PCMPEQB: __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)
PCMPEQW: __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)
PCMPEQD: __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)
(V)PCMPEQB: __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)
(V)PCMPEQW: __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)
(V)PCMPEQD: __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)
VPCMPEQB:
__m256i _mm256_cmpeq_epi8 ( __m256i a, __m256i b)
VPCMPEQW:
__m256i _mm256_cmpeq_epi16 ( __m256i a, __m256i b)
VPCMPEQD:
__m256i _mm256_cmpeq_epi32 ( __m256i a, __m256i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPEQD, see Exceptions Type E4.
EVEX-encoded VPCMPEQB/W, see Exceptions Type E4.nb.
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal
Vol. 2B 4-249
INSTRUCTION SET REFERENCE, M-U
PCMPEQQ — Compare Packed Qword Data for Equal
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 38 29 /r
PCMPEQQ xmm1, xmm2/m128
RM
V/V
SSE4_1
Compare packed qwords in xmm2/m128 and
xmm1 for equality.
VEX.NDS.128.66.0F38.WIG 29 /r
VPCMPEQQ xmm1, xmm2, xmm3/m128
RVM V/V
AVX
Compare packed quadwords in xmm3/m128
and xmm2 for equality.
VEX.NDS.256.66.0F38.WIG 29 /r
VPCMPEQQ ymm1, ymm2, ymm3 /m256
RVM V/V
AVX2
Compare packed quadwords in ymm3/m256
and ymm2 for equality.
EVEX.NDS.128.66.0F38.W1 29 /r
VPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL Compare Equal between int64 vector xmm2
AVX512F and int64 vector xmm3/m128/m64bcst, and
set vector mask k1 to reflect the zero/nonzero
status of each element of the result, under
writemask.
EVEX.NDS.256.66.0F38.W1 29 /r
VPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL Compare Equal between int64 vector ymm2
AVX512F and int64 vector ymm3/m256/m64bcst, and
set vector mask k1 to reflect the zero/nonzero
status of each element of the result, under
writemask.
EVEX.NDS.512.66.0F38.W1 29 /r
VPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcst
FV
V/V
AVX512F
Compare Equal between int64 vector zmm2
and int64 vector zmm3/m512/m64bcst, and
set vector mask k1 to reflect the zero/nonzero
status of each element of the result, under
writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the
source operand (second operand). If a pair of data elements is equal, the corresponding data element in the destination is set to all 1s; otherwise, it is set to 0s.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
EVEX encoded VPCMPEQQ: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.
4-250 Vol. 2B
PCMPEQQ — Compare Packed Qword Data for Equal
INSTRUCTION SET REFERENCE, M-U
Operation
PCMPEQQ (with 128-bit operands)
IF (DEST[63:0] = SRC[63:0])
THEN DEST[63:0] FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] 0; FI;
IF (DEST[127:64] = SRC[127:64])
THEN DEST[127:64] FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64] 0; FI;
DEST[MAX_VL-1:128] (Unmodified)
COMPARE_QWORDS_EQUAL (SRC1, SRC2)
IF SRC1[63:0] = SRC2[63:0]
THEN DEST[63:0] FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] 0; FI;
IF SRC1[127:64] = SRC2[127:64]
THEN DEST[127:64] FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64] 0; FI;
VPCMPEQQ (VEX.128 encoded version)
DEST[127:0] COMPARE_QWORDS_EQUAL(SRC1,SRC2)
DEST[VLMAX-1:128] 0
VPCMPEQQ (VEX.256 encoded version)
DEST[127:0] COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPEQQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+63:i] = SRC2[63:0];
ELSE CMP SRC1[i+63:i] = SRC2[i+63:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);
VPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);
VPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i a, __m128i b);
(V)PCMPEQQ:
__m128i _mm_cmpeq_epi64(__m128i a, __m128i b);
PCMPEQQ — Compare Packed Qword Data for Equal
Vol. 2B 4-251
INSTRUCTION SET REFERENCE, M-U
VPCMPEQQ:
__m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPEQQ, see Exceptions Type E4.
4-252 Vol. 2B
PCMPEQQ — Compare Packed Qword Data for Equal
INSTRUCTION SET REFERENCE, M-U
PCMPESTRI — Packed Compare Explicit Length Strings, Return Index
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 61 /r imm8
PCMPESTRI xmm1, xmm2/m128, imm8
RMI
V/V
SSE4_2
Perform a packed comparison of string data
with explicit lengths, generating an index, and
storing the result in ECX.
VEX.128.66.0F3A 61 /r ib
VPCMPESTRI xmm1, xmm2/m128, imm8
RMI
V/V
AVX
Perform a packed comparison of string data
with explicit lengths, generating an index, and
storing the result in ECX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r)
ModRM:r/m (r)
imm8
NA
Description
The instruction compares and processes data from two string fragments based on the encoded value in the Imm8
Control Byte (see Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates an index stored to the count register (ECX).
Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second
operand) which contains the data elements of the string (byte or word data). The second value is stored in an input
length register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length represents the number of bytes/words which are valid for the respective xmm/m128 data.
The length of each input is interpreted as being the absolute-value of the value in the length register. The absolutevalue computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value
in the length register is greater than 16 (8) or less than -16 (-8).
The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 (see Section 4.1.4) is returned
in ECX. If no bits are set in IntRes2, ECX is set to 16 (8).
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant information:
CFlag – Reset if IntRes2 is equal to zero, set otherwise
ZFlag – Set if absolute-value of EDX is < 16 (8), reset otherwise
SFlag – Set if absolute-value of EAX is < 16 (8), reset otherwise
OFlag – IntRes2[0]
AFlag – Reset
PFlag – Reset
Effective Operand Size
Operating mode/size
Operand 1
Operand 2
Length 1
Length 2
Result
16 bit
xmm
xmm/m128
EAX
EDX
ECX
32 bit
xmm
xmm/m128
EAX
EDX
ECX
64 bit
xmm
xmm/m128
EAX
EDX
ECX
64 bit + REX.W
xmm
xmm/m128
RAX
RDX
ECX
Intel C/C++ Compiler Intrinsic Equivalent For Returning Index
int
_mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode);
PCMPESTRI — Packed Compare Explicit Length Strings, Return Index
Vol. 2B 4-253
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int
_mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to 16
Byte boundary, and
#UD
If VEX.L = 1.
If VEX.vvvv ≠ 1111B.
4-254 Vol. 2B
PCMPESTRI — Packed Compare Explicit Length Strings, Return Index
INSTRUCTION SET REFERENCE, M-U
PCMPESTRM — Packed Compare Explicit Length Strings, Return Mask
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 60 /r imm8
PCMPESTRM xmm1, xmm2/m128, imm8
RMI
V/V
SSE4_2
Perform a packed comparison of string data
with explicit lengths, generating a mask, and
storing the result in XMM0.
VEX.128.66.0F3A 60 /r ib
VPCMPESTRM xmm1, xmm2/m128, imm8
RMI
V/V
AVX
Perform a packed comparison of string data
with explicit lengths, generating a mask, and
storing the result in XMM0.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r)
ModRM:r/m (r)
imm8
NA
Description
The instruction compares data from two string fragments based on the encoded value in the imm8 contol byte (see
Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates a mask stored to XMM0.
Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second
operand) which contains the data elements of the string (byte or word data). The second value is stored in an input
length register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length represents the number of bytes/words which are valid for the respective xmm/m128 data.
The length of each input is interpreted as being the absolute-value of the value in the length register. The absolutevalue computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value
in the length register is greater than 16 (8) or less than -16 (-8).
The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero
extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant information:
CFlag – Reset if IntRes2 is equal to zero, set otherwise
ZFlag – Set if absolute-value of EDX is < 16 (8), reset otherwise
SFlag – Set if absolute-value of EAX is < 16 (8), reset otherwise
OFlag –IntRes2[0]
AFlag – Reset
PFlag – Reset
Note: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be
1111b, VEX.L must be 0, otherwise the instruction will #UD.
PCMPESTRM — Packed Compare Explicit Length Strings, Return Mask
Vol. 2B 4-255
INSTRUCTION SET REFERENCE, M-U
Effective Operand Size
Operating mode/size
Operand1
Operand 2
Length1
Length2
Result
16 bit
xmm
xmm/m128
EAX
EDX
XMM0
32 bit
xmm
xmm/m128
EAX
EDX
XMM0
64 bit
xmm
xmm/m128
EAX
EDX
XMM0
64 bit + REX.W
xmm
xmm/m128
RAX
RDX
XMM0
Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode);
Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int
_mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);
int
_mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to 16
Byte boundary, and
#UD
If VEX.L = 1.
If VEX.vvvv ≠ 1111B.
4-256 Vol. 2B
PCMPESTRM — Packed Compare Explicit Length Strings, Return Mask
INSTRUCTION SET REFERENCE, M-U
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 64 /r1
RM
V/V
MMX
Compare packed signed byte integers in mm and
mm/m64 for greater than.
RM
V/V
SSE2
Compare packed signed byte integers in xmm1
and xmm2/m128 for greater than.
RM
V/V
MMX
Compare packed signed word integers in mm and
mm/m64 for greater than.
RM
V/V
SSE2
Compare packed signed word integers in xmm1
and xmm2/m128 for greater than.
RM
V/V
MMX
Compare packed signed doubleword integers in
mm and mm/m64 for greater than.
RM
V/V
SSE2
Compare packed signed doubleword integers in
xmm1 and xmm2/m128 for greater than.
RVM V/V
AVX
Compare packed signed byte integers in xmm2
and xmm3/m128 for greater than.
RVM V/V
AVX
Compare packed signed word integers in xmm2
and xmm3/m128 for greater than.
RVM V/V
AVX
Compare packed signed doubleword integers in
xmm2 and xmm3/m128 for greater than.
RVM V/V
AVX2
Compare packed signed byte integers in ymm2
and ymm3/m256 for greater than.
RVM V/V
AVX2
Compare packed signed word integers in ymm2
and ymm3/m256 for greater than.
RVM V/V
AVX2
Compare packed signed doubleword integers in
ymm2 and ymm3/m256 for greater than.
EVEX.NDS.128.66.0F.W0 66 /r
VPCMPGTD k1 {k2}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
Compare Greater between int32 vector xmm2 and
int32 vector xmm3/m128/m32bcst, and set
vector mask k1 to reflect the zero/nonzero status
of each element of the result, under writemask.
EVEX.NDS.256.66.0F.W0 66 /r
VPCMPGTD k1 {k2}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
Compare Greater between int32 vector ymm2 and
int32 vector ymm3/m256/m32bcst, and set
vector mask k1 to reflect the zero/nonzero status
of each element of the result, under writemask.
EVEX.NDS.512.66.0F.W0 66 /r
VPCMPGTD k1 {k2}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
Compare Greater between int32 elements in
zmm2 and zmm3/m512/m32bcst, and set
destination k1 according to the comparison results
under writemask. k2.
EVEX.NDS.128.66.0F.WIG 64 /r
VPCMPGTB k1 {k2}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Compare packed signed byte integers in xmm2
and xmm3/m128 for greater than, and set vector
mask k1 to reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.256.66.0F.WIG 64 /r
VPCMPGTB k1 {k2}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Compare packed signed byte integers in ymm2
and ymm3/m256 for greater than, and set vector
mask k1 to reflect the zero/nonzero status of each
element of the result, under writemask.
PCMPGTB mm, mm/m64
66 0F 64 /r
PCMPGTB xmm1, xmm2/m128
0F 65 /r1
PCMPGTW mm, mm/m64
66 0F 65 /r
PCMPGTW xmm1, xmm2/m128
0F 66 /r1
PCMPGTD mm, mm/m64
66 0F 66 /r
PCMPGTD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 64 /r
VPCMPGTB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 65 /r
VPCMPGTW xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 66 /r
VPCMPGTD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 64 /r
VPCMPGTB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG 65 /r
VPCMPGTW ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG 66 /r
VPCMPGTD ymm1, ymm2, ymm3/m256
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than
Vol. 2B 4-257
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.512.66.0F.WIG 64 /r
VPCMPGTB k1 {k2}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Compare packed signed byte integers in zmm2 and
zmm3/m512 for greater than, and set vector
mask k1 to reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.128.66.0F.WIG 65 /r
VPCMPGTW k1 {k2}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Compare packed signed word integers in xmm2
and xmm3/m128 for greater than, and set vector
mask k1 to reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.256.66.0F.WIG 65 /r
VPCMPGTW k1 {k2}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Compare packed signed word integers in ymm2
and ymm3/m256 for greater than, and set vector
mask k1 to reflect the zero/nonzero status of each
element of the result, under writemask.
EVEX.NDS.512.66.0F.WIG 65 /r
VPCMPGTW k1 {k2}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Compare packed signed word integers in zmm2
and zmm3/m512 for greater than, and set vector
mask k1 to reflect the zero/nonzero status of each
element of the result, under writemask.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs an SIMD signed compare for the greater value of the packed byte, word, or doubleword integers in the
destination operand (first operand) and the source operand (second operand). If a data element in the destination
operand is greater than the corresponding date element in the source operand, the corresponding data element in
the destination operand is set to all 1s; otherwise, it is set to all 0s.
The PCMPGTB instruction compares the corresponding signed byte integers in the destination and source operands; the PCMPGTW instruction compares the corresponding signed word integers in the destination and source
operands; and the PCMPGTD instruction compares the corresponding signed doubleword integers in the destination and source operands.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
register are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
4-258 Vol. 2B
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than
INSTRUCTION SET REFERENCE, M-U
EVEX encoded VPCMPGTD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.
EVEX encoded VPCMPGTB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand
(first operand) is a mask register updated according to the writemask k2.
Operation
PCMPGTB (with 64-bit operands)
IF DEST[7:0] > SRC[7:0]
THEN DEST[7:0) ← FFH;
ELSE DEST[7:0] ← 0; FI;
(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
IF DEST[63:56] > SRC[63:56]
THEN DEST[63:56] ← FFH;
ELSE DEST[63:56] ← 0; FI;
COMPARE_BYTES_GREATER (SRC1, SRC2)
IF SRC1[7:0] > SRC2[7:0]
THEN DEST[7:0] FFH;
ELSE DEST[7:0] 0; FI;
(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
IF SRC1[127:120] > SRC2[127:120]
THEN DEST[127:120] FFH;
ELSE DEST[127:120] 0; FI;
COMPARE_WORDS_GREATER (SRC1, SRC2)
IF SRC1[15:0] > SRC2[15:0]
THEN DEST[15:0] FFFFH;
ELSE DEST[15:0] 0; FI;
(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
IF SRC1[127:112] > SRC2[127:112]
THEN DEST[127:112] FFFFH;
ELSE DEST[127:112] 0; FI;
COMPARE_DWORDS_GREATER (SRC1, SRC2)
IF SRC1[31:0] > SRC2[31:0]
THEN DEST[31:0] FFFFFFFFH;
ELSE DEST[31:0] 0; FI;
(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
IF SRC1[127:96] > SRC2[127:96]
THEN DEST[127:96] FFFFFFFFH;
ELSE DEST[127:96] 0; FI;
PCMPGTB (with 128-bit operands)
DEST[127:0] COMPARE_BYTES_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
VPCMPGTB (VEX.128 encoded version)
DEST[127:0] COMPARE_BYTES_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] 0
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than
Vol. 2B 4-259
INSTRUCTION SET REFERENCE, M-U
VPCMPGTB (VEX.256 encoded version)
DEST[127:0] COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPGTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
CMP SRC1[i+7:i] > SRC2[i+7:i];
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
PCMPGTW (with 64-bit operands)
IF DEST[15:0] > SRC[15:0]
THEN DEST[15:0] ← FFFFH;
ELSE DEST[15:0] ← 0; FI;
(* Continue comparison of 2nd and 3rd words in DEST and SRC *)
IF DEST[63:48] > SRC[63:48]
THEN DEST[63:48] ← FFFFH;
ELSE DEST[63:48] ← 0; FI;
PCMPGTW (with 128-bit operands)
DEST[127:0] COMPARE_WORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
VPCMPGTW (VEX.128 encoded version)
DEST[127:0] COMPARE_WORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] 0
VPCMPGTW (VEX.256 encoded version)
DEST[127:0] COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_WORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPGTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
CMP SRC1[i+15:i] > SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
4-260 Vol. 2B
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than
INSTRUCTION SET REFERENCE, M-U
ELSE
DEST[j] 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
; zeroing-masking onlyFI;
PCMPGTD (with 64-bit operands)
IF DEST[31:0] > SRC[31:0]
THEN DEST[31:0] ← FFFFFFFFH;
ELSE DEST[31:0] ← 0; FI;
IF DEST[63:32] > SRC[63:32]
THEN DEST[63:32] ← FFFFFFFFH;
ELSE DEST[63:32] ← 0; FI;
PCMPGTD (with 128-bit operands)
DEST[127:0] COMPARE_DWORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
VPCMPGTD (VEX.128 encoded version)
DEST[127:0] COMPARE_DWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] 0
VPCMPGTD (VEX.256 encoded version)
DEST[127:0] COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_DWORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPGTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+31:i] > SRC2[31:0];
ELSE CMP SRC1[i+31:i] > SRC2[i+31:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPCMPGTB __mmask64 _mm512_cmpgt_epi8_mask(__m512i a, __m512i b);
VPCMPGTB __mmask64 _mm512_mask_cmpgt_epi8_mask(__mmask64 k, __m512i a, __m512i b);
VPCMPGTB __mmask32 _mm256_cmpgt_epi8_mask(__m256i a, __m256i b);
VPCMPGTB __mmask32 _mm256_mask_cmpgt_epi8_mask(__mmask32 k, __m256i a, __m256i b);
VPCMPGTB __mmask16 _mm_cmpgt_epi8_mask(__m128i a, __m128i b);
VPCMPGTB __mmask16 _mm_mask_cmpgt_epi8_mask(__mmask16 k, __m128i a, __m128i b);
VPCMPGTD __mmask16 _mm512_cmpgt_epi32_mask(__m512i a, __m512i b);
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than
Vol. 2B 4-261
INSTRUCTION SET REFERENCE, M-U
VPCMPGTD __mmask16 _mm512_mask_cmpgt_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPGTD __mmask8 _mm256_cmpgt_epi32_mask(__m256i a, __m256i b);
VPCMPGTD __mmask8 _mm256_mask_cmpgt_epi32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPGTD __mmask8 _mm_cmpgt_epi32_mask(__m128i a, __m128i b);
VPCMPGTD __mmask8 _mm_mask_cmpgt_epi32_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPGTW __mmask32 _mm512_cmpgt_epi16_mask(__m512i a, __m512i b);
VPCMPGTW __mmask32 _mm512_mask_cmpgt_epi16_mask(__mmask32 k, __m512i a, __m512i b);
VPCMPGTW __mmask16 _mm256_cmpgt_epi16_mask(__m256i a, __m256i b);
VPCMPGTW __mmask16 _mm256_mask_cmpgt_epi16_mask(__mmask16 k, __m256i a, __m256i b);
VPCMPGTW __mmask8 _mm_cmpgt_epi16_mask(__m128i a, __m128i b);
VPCMPGTW __mmask8 _mm_mask_cmpgt_epi16_mask(__mmask8 k, __m128i a, __m128i b);
PCMPGTB:__m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
PCMPGTW:__m64 _mm_pcmpgt_pi16 (__m64 m1, __m64 m2)
PCMPGTD:__m64 _mm_pcmpgt_pi32 (__m64 m1, __m64 m2)
(V)PCMPGTB:__m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b)
(V)PCMPGTW:__m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b)
(V)DCMPGTD:__m128i _mm_cmpgt_epi32 ( __m128i a, __m128i b)
VPCMPGTB:
__m256i _mm256_cmpgt_epi8 ( __m256i a, __m256i b)
VPCMPGTW:
__m256i _mm256_cmpgt_epi16 ( __m256i a, __m256i b)
VPCMPGTD:
__m256i _mm256_cmpgt_epi32 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPGTD, see Exceptions Type E4.
EVEX-encoded VPCMPGTB/W, see Exceptions Type E4.nb.
4-262 Vol. 2B
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than
INSTRUCTION SET REFERENCE, M-U
PCMPGTQ — Compare Packed Data for Greater Than
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 38 37 /r
PCMPGTQ xmm1,xmm2/m128
RM
V/V
SSE4_2
Compare packed signed qwords in xmm2/m128
and xmm1 for greater than.
VEX.NDS.128.66.0F38.WIG 37 /r
VPCMPGTQ xmm1, xmm2, xmm3/m128
RVM V/V
AVX
Compare packed signed qwords in xmm2 and
xmm3/m128 for greater than.
VEX.NDS.256.66.0F38.WIG 37 /r
VPCMPGTQ ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Compare packed signed qwords in ymm2 and
ymm3/m256 for greater than.
EVEX.NDS.128.66.0F38.W1 37 /r
VPCMPGTQ k1 {k2}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL Compare Greater between int64 vector xmm2 and
AVX512F int64 vector xmm3/m128/m64bcst, and set
vector mask k1 to reflect the zero/nonzero status
of each element of the result, under writemask.
EVEX.NDS.256.66.0F38.W1 37 /r
VPCMPGTQ k1 {k2}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL Compare Greater between int64 vector ymm2 and
AVX512F int64 vector ymm3/m256/m64bcst, and set
vector mask k1 to reflect the zero/nonzero status
of each element of the result, under writemask.
EVEX.NDS.512.66.0F38.W1 37 /r
FV
VPCMPGTQ k1 {k2}, zmm2, zmm3/m512/m64bcst
V/V
AVX512F
Compare Greater between int64 vector zmm2 and
int64 vector zmm3/m512/m64bcst, and set
vector mask k1 to reflect the zero/nonzero status
of each element of the result, under writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs an SIMD signed compare for the packed quadwords in the destination operand (first operand) and the
source operand (second operand). If the data element in the first (destination) operand is greater than the
corresponding element in the second (source) operand, the corresponding data element in the destination is set
to all 1s; otherwise, it is set to 0s.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
register are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
EVEX encoded VPCMPGTD/Q: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.
PCMPGTQ — Compare Packed Data for Greater Than
Vol. 2B 4-263
INSTRUCTION SET REFERENCE, M-U
Operation
COMPARE_QWORDS_GREATER (SRC1, SRC2)
IF SRC1[63:0] > SRC2[63:0]
THEN DEST[63:0] FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] 0; FI;
IF SRC1[127:64] > SRC2[127:64]
THEN DEST[127:64] FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64] 0; FI;
VPCMPGTQ (VEX.128 encoded version)
DEST[127:0] COMPARE_QWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] 0
VPCMPGTQ (VEX.256 encoded version)
DEST[127:0] COMPARE_QWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] COMPARE_QWORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] 0
VPCMPGTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+63:i] > SRC2[63:0];
ELSE CMP SRC1[i+63:i] > SRC2[i+63:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPGTQ __mmask8 _mm512_cmpgt_epi64_mask( __m512i a, __m512i b);
VPCMPGTQ __mmask8 _mm512_mask_cmpgt_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPGTQ __mmask8 _mm256_cmpgt_epi64_mask( __m256i a, __m256i b);
VPCMPGTQ __mmask8 _mm256_mask_cmpgt_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPGTQ __mmask8 _mm_cmpgt_epi64_mask( __m128i a, __m128i b);
VPCMPGTQ __mmask8 _mm_mask_cmpgt_epi64_mask(__mmask8 k, __m128i a, __m128i b);
(V)PCMPGTQ:
__m128i _mm_cmpgt_epi64(__m128i a, __m128i b)
VPCMPGTQ:
__m256i _mm256_cmpgt_epi64( __m256i a, __m256i b);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
4-264 Vol. 2B
PCMPGTQ — Compare Packed Data for Greater Than
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPGTQ, see Exceptions Type E4.
PCMPGTQ — Compare Packed Data for Greater Than
Vol. 2B 4-265
INSTRUCTION SET REFERENCE, M-U
PCMPISTRI — Packed Compare Implicit Length Strings, Return Index
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 63 /r imm8
PCMPISTRI xmm1, xmm2/m128, imm8
RM
V/V
SSE4_2
Perform a packed comparison of string data
with implicit lengths, generating an index, and
storing the result in ECX.
VEX.128.66.0F3A.WIG 63 /r ib
VPCMPISTRI xmm1, xmm2/m128, imm8
RM
V/V
AVX
Perform a packed comparison of string data
with implicit lengths, generating an index, and
storing the result in ECX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
imm8
NA
Description
The instruction compares data from two strings based on the encoded value in the Imm8 Control Byte (see Section
4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates an
index stored to ECX.
Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which
contains the data elements of the string (byte or word data). Each input byte/word is augmented with a
valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null
byte/word. (The least significant null byte/word is also considered invalid.)
The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 is returned in ECX. If no bits
are set in IntRes2, ECX is set to 16 (8).
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant information:
CFlag – Reset if IntRes2 is equal to zero, set otherwise
ZFlag – Set if any byte/word of xmm2/mem128 is null, reset otherwise
SFlag – Set if any byte/word of xmm1 is null, reset otherwise
OFlag –IntRes2[0]
AFlag – Reset
PFlag – Reset
Note: In VEX.128 encoded version, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD.
Effective Operand Size
Operating mode/size
Operand1
Operand 2
Result
16 bit
xmm
xmm/m128
ECX
32 bit
xmm
xmm/m128
ECX
64 bit
xmm
xmm/m128
ECX
Intel C/C++ Compiler Intrinsic Equivalent For Returning Index
int
_mm_cmpistri (__m128i a, __m128i b, const int mode);
4-266 Vol. 2B
PCMPISTRI — Packed Compare Implicit Length Strings, Return Index
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int
_mm_cmpistra (__m128i a, __m128i b, const int mode);
int
_mm_cmpistrc (__m128i a, __m128i b, const int mode);
int
_mm_cmpistro (__m128i a, __m128i b, const int mode);
int
_mm_cmpistrs (__m128i a, __m128i b, const int mode);
int
_mm_cmpistrz (__m128i a, __m128i b, const int mode);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to
16 Byte boundary, and
#UD
If VEX.L = 1.
If VEX.vvvv ≠ 1111B.
PCMPISTRI — Packed Compare Implicit Length Strings, Return Index
Vol. 2B 4-267
INSTRUCTION SET REFERENCE, M-U
PCMPISTRM — Packed Compare Implicit Length Strings, Return Mask
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 62 /r imm8
PCMPISTRM xmm1, xmm2/m128, imm8
RM
V/V
SSE4_2
Perform a packed comparison of string data
with implicit lengths, generating a mask, and
storing the result in XMM0.
VEX.128.66.0F3A.WIG 62 /r ib
VPCMPISTRM xmm1, xmm2/m128, imm8
RM
V/V
AVX
Perform a packed comparison of string data
with implicit lengths, generating a Mask, and
storing the result in XMM0.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
imm8
NA
Description
The instruction compares data from two strings based on the encoded value in the imm8 byte (see Section 4.1,
“Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”) generating a mask
stored to XMM0.
Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which
contains the data elements of the string (byte or word data). Each input byte/word is augmented with a
valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null
byte/word. (The least significant null byte/word is also considered invalid.)
The comparison and aggregation operation are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero
extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant information:
CFlag – Reset if IntRes2 is equal to zero, set otherwise
ZFlag – Set if any byte/word of xmm2/mem128 is null, reset otherwise
SFlag – Set if any byte/word of xmm1 is null, reset otherwise
OFlag – IntRes2[0]
AFlag – Reset
PFlag – Reset
Note: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be
1111b, VEX.L must be 0, otherwise the instruction will #UD.
Effective Operand Size
Operating mode/size
Operand1
Operand 2
Result
16 bit
xmm
xmm/m128
XMM0
32 bit
xmm
xmm/m128
XMM0
64 bit
xmm
xmm/m128
XMM0
Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask
__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);
4-268 Vol. 2B
PCMPISTRM — Packed Compare Implicit Length Strings, Return Mask
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int
_mm_cmpistra (__m128i a, __m128i b, const int mode);
int
_mm_cmpistrc (__m128i a, __m128i b, const int mode);
int
_mm_cmpistro (__m128i a, __m128i b, const int mode);
int
_mm_cmpistrs (__m128i a, __m128i b, const int mode);
int
_mm_cmpistrz (__m128i a, __m128i b, const int mode);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to
16 Byte boundary, and
#UD
If VEX.L = 1.
If VEX.vvvv ≠ 1111B.
PCMPISTRM — Packed Compare Implicit Length Strings, Return Mask
Vol. 2B 4-269
INSTRUCTION SET REFERENCE, M-U
PDEP — Parallel Bits Deposit
Opcode/
Instruction
Op/
En
RVM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI2
VEX.NDS.LZ.F2.0F38.W0 F5 /r
PDEP r32a, r32b, r/m32
VEX.NDS.LZ.F2.0F38.W1 F5 /r
PDEP r64a, r64b, r/m64
RVM
V/N.E.
BMI2
Description
Parallel deposit of bits from r32b using mask in r/m32, result is written to r32a.
Parallel deposit of bits from r64b using mask in r/m64, result is written to r64a.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
PDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits
in the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits
from the first source operand and deposit them in the destination operand at the corresponding bit locations that
are set in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero.
SRC1
S31 S30 S29 S28 S27
SRC2
0
(mask)
DEST
0
0
0
1
0
0
S3
0
0
S7 S6 S5
1 0
S2
0
1
S4
S3
0
0
S1 0
0
S2 S1
S0
1
0
0
S0
0
0
bit 0
bit 31
Figure 4-8. PDEP Example
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
TEMP ← SRC1;
MASK ← SRC2;
DEST ← 0 ;
m← 0, k← 0;
DO WHILE m< OperandSize
OD
IF MASK[ m] = 1 THEN
DEST[ m] ← TEMP[ k];
k ← k+ 1;
FI
m ← m+ 1;
4-270 Vol. 2B
PDEP — Parallel Bits Deposit
INSTRUCTION SET REFERENCE, M-U
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
PDEP:
unsigned __int32 _pdep_u32(unsigned __int32 src, unsigned __int32 mask);
PDEP:
unsigned __int64 _pdep_u64(unsigned __int64 src, unsigned __int32 mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
PDEP — Parallel Bits Deposit
Vol. 2B 4-271
INSTRUCTION SET REFERENCE, M-U
PEXT — Parallel Bits Extract
Opcode/
Instruction
Op/
En
RVM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI2
VEX.NDS.LZ.F3.0F38.W0 F5 /r
PEXT r32a, r32b, r/m32
VEX.NDS.LZ.F3.0F38.W1 F5 /r
PEXT r64a, r64b, r/m64
RVM
V/N.E.
BMI2
Description
Parallel extract of bits from r32b using mask in r/m32, result is written to r32a.
Parallel extract of bits from r64b using mask in r/m64, result is written to r64a.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
PEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contiguous bits in the first source operand (the second operand) to contiguous low order bit positions in the destination
(the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand
and writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are
zeroed.
SRC1 S S
31 30 S29 S28 S27
SRC2
0
(mask)
DEST
0
0
0
0
0
1
0
0
0
S7 S6 S5
1 0
1
0 0
0
S4
S3
S2 S1
S0
0
0
1
0
0
S28 S7
S5
S2
0
bit 0
bit 31
Figure 4-9. PEXT Example
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
TEMP ← SRC1;
MASK ← SRC2;
DEST ← 0 ;
m← 0, k← 0;
DO WHILE m< OperandSize
IF MASK[ m] = 1 THEN
DEST[ k] ← TEMP[ m];
k ← k+ 1;
FI
4-272 Vol. 2B
PEXT — Parallel Bits Extract
INSTRUCTION SET REFERENCE, M-U
m ← m+ 1;
OD
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
PEXT:
unsigned __int32 _pext_u32(unsigned __int32 src, unsigned __int32 mask);
PEXT:
unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int32 mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
PEXT — Parallel Bits Extract
Vol. 2B 4-273
INSTRUCTION SET REFERENCE, M-U
PEXTRB/PEXTRD/PEXTRQ — Extract Byte/Dword/Qword
Opcode/
Instruction
Op/ En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 14
/r ib
PEXTRB reg/m8, xmm2, imm8
MRI
V/V
SSE4_1
Extract a byte integer value from xmm2 at the
source byte offset specified by imm8 into reg or
m8. The upper bits of r32 or r64 are zeroed.
66 0F 3A 16
/r ib
PEXTRD r/m32, xmm2, imm8
MRI
V/V
SSE4_1
Extract a dword integer value from xmm2 at the
source dword offset specified by imm8 into r/m32.
66 REX.W 0F 3A 16
/r ib
PEXTRQ r/m64, xmm2, imm8
MRI
V/N.E.
SSE4_1
Extract a qword integer value from xmm2 at the
source qword offset specified by imm8 into r/m64.
VEX.128.66.0F3A.W0 14 /r ib
VPEXTRB reg/m8, xmm2, imm8
MRI
V1/V
AVX
Extract a byte integer value from xmm2 at the
source byte offset specified by imm8 into reg or
m8. The upper bits of r64/r32 is filled with zeros.
VEX.128.66.0F3A.W0 16 /r ib
VPEXTRD r32/m32, xmm2, imm8
MRI
V/V
AVX
Extract a dword integer value from xmm2 at the
source dword offset specified by imm8 into
r32/m32.
VEX.128.66.0F3A.W1 16 /r ib
VPEXTRQ r64/m64, xmm2, imm8
MRI
V/i
AVX
Extract a qword integer value from xmm2 at the
source dword offset specified by imm8 into
r64/m64.
EVEX.128.66.0F3A.WIG 14 /r ib
VPEXTRB reg/m8, xmm2, imm8
T1S-MRI V/V
AVX512BW Extract a byte integer value from xmm2 at the
source byte offset specified by imm8 into reg or
m8. The upper bits of r64/r32 is filled with zeros.
EVEX.128.66.0F3A.W0 16 /r ib
VPEXTRD r32/m32, xmm2, imm8
T1S-MRI V/V
AVX512DQ
Extract a dword integer value from xmm2 at the
source dword offset specified by imm8 into
r32/m32.
EVEX.128.66.0F3A.W1 16 /r ib
VPEXTRQ r64/m64, xmm2, imm8
T1S-MRI V/N.E.1
AVX512DQ
Extract a qword integer value from xmm2 at the
source dword offset specified by imm8 into
r64/m64.
NOTES:
1. In 64-bit mode, VEX.W1 is ignored for VPEXTRB (similar to legacy REX.W=1 prefix in PEXTRB).
2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MRI
ModRM:r/m (w)
ModRM:reg (r)
imm8
NA
Description
Extract a byte/dword/qword integer value from the source XMM register at a byte/dword/qword offset determined
from imm8[3:0]. The destination can be a register or byte/dword/qword memory location. If the destination is a
register, the upper bits of the register are zero extended.
In legacy non-VEX encoded version and if the destination operand is a register, the default operand size in 64-bit
mode for PEXTRB/PEXTRD is 64 bits, the bits above the least significant byte/dword data are filled with zeros.
PEXTRQ is not encodable in non-64-bit modes and requires REX.W in 64-bit mode.
4-274 Vol. 2B
PEXTRB/PEXTRD/PEXTRQ — Extract Byte/Dword/Qword
INSTRUCTION SET REFERENCE, M-U
Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L”L must be
0, otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit
mode for VPEXTRB/VPEXTRD is 64 bits, the bits above the least significant byte/word/dword data are filled with
zeros. Attempt to execute VPEXTRQ in non-64-bit mode will cause #UD.
Operation
CASE of
PEXTRB: SEL COUNT[3:0];
TEMP (Src >> SEL*8) AND FFH;
IF (DEST = Mem8)
THEN
Mem8 TEMP[7:0];
ELSE IF (64-Bit Mode and 64-bit register selected)
THEN
R64[7:0] TEMP[7:0];
r64[63:8] ← ZERO_FILL; };
ELSE
R32[7:0] TEMP[7:0];
r32[31:8] ← ZERO_FILL; };
FI;
PEXTRD:SEL COUNT[1:0];
TEMP (Src >> SEL*32) AND FFFF_FFFFH;
DEST TEMP;
PEXTRQ: SEL COUNT[0];
TEMP (Src >> SEL*64);
DEST TEMP;
EASC:
VPEXTRTD/VPEXTRQ
IF (64-Bit Mode and 64-bit dest operand)
THEN
Src_Offset Imm8[0]
r64/m64 (Src >> Src_Offset * 64)
ELSE
Src_Offset Imm8[1:0]
r32/m32 ((Src >> Src_Offset *32) AND 0FFFFFFFFh);
FI
VPEXTRB ( dest=m8)
SRC_Offset Imm8[3:0]
Mem8 (Src >> Src_Offset*8)
VPEXTRB ( dest=reg)
IF (64-Bit Mode )
THEN
SRC_Offset Imm8[3:0]
DEST[7:0] ((Src >> Src_Offset*8) AND 0FFh)
DEST[63:8] ZERO_FILL;
ELSE
SRC_Offset . Imm8[3:0];
DEST[7:0] ((Src >> Src_Offset*8) AND 0FFh);
DEST[31:8] ZERO_FILL;
FI
PEXTRB/PEXTRD/PEXTRQ — Extract Byte/Dword/Qword
Vol. 2B 4-275
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
PEXTRB:
int _mm_extract_epi8 (__m128i src, const int ndx);
PEXTRD:
int _mm_extract_epi32 (__m128i src, const int ndx);
PEXTRQ:
__int64 _mm_extract_epi64 (__m128i src, const int ndx);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD
If VEX.L = 1 or EVEX.L’L > 0.
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
If VPEXTRQ in non-64-bit mode, VEX.W=1.
4-276 Vol. 2B
PEXTRB/PEXTRD/PEXTRQ — Extract Byte/Dword/Qword
INSTRUCTION SET REFERENCE, M-U
PEXTRW—Extract Word
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F C5 /r ib1
RMI
V/V
SSE
Extract the word specified by imm8 from mm
and move it to reg, bits 15-0. The upper bits of
r32 or r64 is zeroed.
RMI
V/V
SSE2
Extract the word specified by imm8 from xmm
and move it to reg, bits 15-0. The upper bits of
r32 or r64 is zeroed.
66 0F 3A 15
/r ib
PEXTRW reg/m16, xmm, imm8
MRI
V/V
SSE4_1
Extract the word specified by imm8 from xmm
and copy it to lowest 16 bits of reg or m16.
Zero-extend the result in the destination, r32
or r64.
VEX.128.66.0F.W0 C5 /r ib
VPEXTRW reg, xmm1, imm8
RMI
V2/V
AVX
Extract the word specified by imm8 from
xmm1 and move it to reg, bits 15:0. Zeroextend the result. The upper bits of r64/r32 is
filled with zeros.
VEX.128.66.0F3A.W0 15 /r ib
VPEXTRW reg/m16, xmm2, imm8
MRI
V/V
AVX
Extract a word integer value from xmm2 at
the source word offset specified by imm8 into
reg or m16. The upper bits of r64/r32 is filled
with zeros.
EVEX.128.66.0F.WIG C5 /r ib
VPEXTRW reg, xmm1, imm8
RMI
V/V
AVX512B
W
Extract the word specified by imm8 from
xmm1 and move it to reg, bits 15:0. Zeroextend the result. The upper bits of r64/r32 is
filled with zeros.
EVEX.128.66.0F3A.WIG 15 /r ib
VPEXTRW reg/m16, xmm2, imm8
T1S- V/V
MRI
AVX512B
W
Extract a word integer value from xmm2 at
the source word offset specified by imm8 into
reg or m16. The upper bits of r64/r32 is filled
with zeros.
PEXTRW reg, mm, imm8
66 0F C5 /r ib
PEXTRW reg, xmm, imm8
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
2. In 64-bit mode, VEX.W1 is ignored for VPEXTRW (similar to legacy REX.W=1 prefix in PEXTRW).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
MRI
ModRM:r/m (w)
ModRM:reg (r)
imm8
NA
Description
Copies the word in the source operand (second operand) specified by the count operand (third operand) to the
destination operand (first operand). The source operand can be an MMX technology register or an XMM register.
The destination operand can be the low word of a general-purpose register or a 16-bit memory address. The count
operand is an 8-bit immediate. When specifying a word location in an MMX technology register, the 2 least-significant bits of the count operand specify the location; for an XMM register, the 3 least-significant bits specify the location. The content of the destination register above bit 16 is cleared (set to all 0s).
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15, R8-15). If the destination operand is a general-purpose register, the default operand size is 64-bits
in 64-bit mode.
PEXTRW—Extract Word
Vol. 2B 4-277
INSTRUCTION SET REFERENCE, M-U
Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L must be 0,
otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit mode
for VPEXTRW is 64 bits, the bits above the least significant byte/word/dword data are filled with zeros.
Operation
IF (DEST = Mem16)
THEN
SEL COUNT[2:0];
TEMP (Src >> SEL*16) AND FFFFH;
Mem16 TEMP[15:0];
ELSE IF (64-Bit Mode and destination is a general-purpose register)
THEN
FOR (PEXTRW instruction with 64-bit source operand)
{ SEL ← COUNT[1:0];
TEMP ← (SRC >> (SEL ∗ 16)) AND FFFFH;
r64[15:0] ← TEMP[15:0];
r64[63:16] ← ZERO_FILL; };
FOR (PEXTRW instruction with 128-bit source operand)
{ SEL ← COUNT[2:0];
TEMP ← (SRC >> (SEL ∗ 16)) AND FFFFH;
r64[15:0] ← TEMP[15:0];
r64[63:16] ← ZERO_FILL; }
ELSE
FOR (PEXTRW instruction with 64-bit source operand)
{ SEL ← COUNT[1:0];
TEMP ← (SRC >> (SEL ∗ 16)) AND FFFFH;
r32[15:0] ← TEMP[15:0];
r32[31:16] ← ZERO_FILL; };
FOR (PEXTRW instruction with 128-bit source operand)
{ SEL ← COUNT[2:0];
TEMP ← (SRC >> (SEL ∗ 16)) AND FFFFH;
r32[15:0] ← TEMP[15:0];
r32[31:16] ← ZERO_FILL; };
FI;
FI;
VPEXTRW ( dest=m16)
SRC_Offset Imm8[2:0]
Mem16 (Src >> Src_Offset*16)
VPEXTRW ( dest=reg)
IF (64-Bit Mode )
THEN
SRC_Offset Imm8[2:0]
DEST[15:0] ((Src >> Src_Offset*16) AND 0FFFFh)
DEST[63:16] ZERO_FILL;
ELSE
SRC_Offset Imm8[2:0]
DEST[15:0] ((Src >> Src_Offset*16) AND 0FFFFh)
DEST[31:16] ZERO_FILL;
FI
4-278 Vol. 2B
PEXTRW—Extract Word
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
PEXTRW:
int _mm_extract_pi16 (__m64 a, int n)
PEXTRW:
int _mm_extract_epi16 ( __m128i a, int imm)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD
If VEX.L = 1 or EVEX.L’L > 0.
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
PEXTRW—Extract Word
Vol. 2B 4-279
INSTRUCTION SET REFERENCE, M-U
PHADDW/PHADDD — Packed Horizontal Add
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 01 /r1
RM
V/V
SSSE3
Add 16-bit integers horizontally, pack to mm1.
RM
V/V
SSSE3
Add 16-bit integers horizontally, pack to
xmm1.
RM
V/V
SSSE3
Add 32-bit integers horizontally, pack to mm1.
RM
V/V
SSSE3
Add 32-bit integers horizontally, pack to
xmm1.
RVM V/V
AVX
Add 16-bit integers horizontally, pack to
xmm1.
RVM V/V
AVX
Add 32-bit integers horizontally, pack to
xmm1.
RVM V/V
AVX2
Add 16-bit signed integers horizontally, pack
to ymm1.
RVM V/V
AVX2
Add 32-bit signed integers horizontally, pack
to ymm1.
PHADDW mm1, mm2/m64
66 0F 38 01 /r
PHADDW xmm1, xmm2/m128
0F 38 02 /r
PHADDD mm1, mm2/m64
66 0F 38 02 /r
PHADDD xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 01 /r
VPHADDW xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F38.WIG 02 /r
VPHADDD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 01 /r
VPHADDW ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F38.WIG 02 /r
VPHADDD ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
(V)PHADDW adds two adjacent 16-bit signed integers horizontally from the source and destination operands and
packs the 16-bit signed results to the destination operand (first operand). (V)PHADDD adds two adjacent 32-bit
signed integers horizontally from the source and destination operands and packs the 32-bit signed results to the
destination operand (first operand). When the source operand is a 128-bit memory operand, the operand must be
aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
Note that these instructions can operate on either unsigned or signed (two’s complement notation) integers;
however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of the values operated on.
Legacy SSE instructions: Both operands can be MMX registers. The second source operand can be an MMX register
or a 64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.
4-280 Vol. 2B
PHADDW/PHADDD — Packed Horizontal Add
INSTRUCTION SET REFERENCE, M-U
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM
register are zeroed.
VEX.256 encoded version: Horizontal addition of two adjacent data elements of the low 16-bytes of the first and
second source operands are packed into the low 16-bytes of the destination operand. Horizontal addition of two
adjacent data elements of the high 16-bytes of the first and second source operands are packed into the high 16bytes of the destination operand. The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.
SRC2 Y7 Y6
Y5 Y4
Y3 Y2
Y1 Y0
X7 X6
X5 X4
X3 X2
X1 X0
S3
S3
S4
S3
S2
S1
S0
S7
255
SRC1
0
Dest
Figure 4-10. 256-bit VPHADDD Instruction Operation
Operation
PHADDW (with 64-bit operands)
mm1[15-0] = mm1[31-16] + mm1[15-0];
mm1[31-16] = mm1[63-48] + mm1[47-32];
mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];
mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];
PHADDW (with 128-bit operands)
xmm1[15-0] = xmm1[31-16] + xmm1[15-0];
xmm1[31-16] = xmm1[63-48] + xmm1[47-32];
xmm1[47-32] = xmm1[95-80] + xmm1[79-64];
xmm1[63-48] = xmm1[127-112] + xmm1[111-96];
xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0];
xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32];
xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64];
xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96];
VPHADDW (VEX.128 encoded version)
DEST[15:0] SRC1[31:16] + SRC1[15:0]
DEST[31:16] SRC1[63:48] + SRC1[47:32]
DEST[47:32] SRC1[95:80] + SRC1[79:64]
DEST[63:48] SRC1[127:112] + SRC1[111:96]
DEST[79:64] SRC2[31:16] + SRC2[15:0]
DEST[95:80] SRC2[63:48] + SRC2[47:32]
DEST[111:96] SRC2[95:80] + SRC2[79:64]
DEST[127:112] SRC2[127:112] + SRC2[111:96]
DEST[VLMAX-1:128] 0
PHADDW/PHADDD — Packed Horizontal Add
Vol. 2B 4-281
INSTRUCTION SET REFERENCE, M-U
VPHADDW (VEX.256 encoded version)
DEST[15:0] SRC1[31:16] + SRC1[15:0]
DEST[31:16] SRC1[63:48] + SRC1[47:32]
DEST[47:32] SRC1[95:80] + SRC1[79:64]
DEST[63:48] SRC1[127:112] + SRC1[111:96]
DEST[79:64] SRC2[31:16] + SRC2[15:0]
DEST[95:80] SRC2[63:48] + SRC2[47:32]
DEST[111:96] SRC2[95:80] + SRC2[79:64]
DEST[127:112] SRC2[127:112] + SRC2[111:96]
DEST[143:128] SRC1[159:144] + SRC1[143:128]
DEST[159:144] SRC1[191:176] + SRC1[175:160]
DEST[175:160] SRC1[223:208] + SRC1[207:192]
DEST[191:176] SRC1[255:240] + SRC1[239:224]
DEST[207:192] SRC2[127:112] + SRC2[143:128]
DEST[223:208] SRC2[159:144] + SRC2[175:160]
DEST[239:224] SRC2[191:176] + SRC2[207:192]
DEST[255:240] SRC2[223:208] + SRC2[239:224]
PHADDD (with 64-bit operands)
mm1[31-0] = mm1[63-32] + mm1[31-0];
mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0];
PHADDD (with 128-bit operands)
xmm1[31-0] = xmm1[63-32] + xmm1[31-0];
xmm1[63-32] = xmm1[127-96] + xmm1[95-64];
xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0];
xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64];
VPHADDD (VEX.128 encoded version)
DEST[31-0] SRC1[63-32] + SRC1[31-0]
DEST[63-32] SRC1[127-96] + SRC1[95-64]
DEST[95-64] SRC2[63-32] + SRC2[31-0]
DEST[127-96] SRC2[127-96] + SRC2[95-64]
DEST[VLMAX-1:128] 0
VPHADDD (VEX.256 encoded version)
DEST[31-0] SRC1[63-32] + SRC1[31-0]
DEST[63-32] SRC1[127-96] + SRC1[95-64]
DEST[95-64] SRC2[63-32] + SRC2[31-0]
DEST[127-96] SRC2[127-96] + SRC2[95-64]
DEST[159-128] SRC1[191-160] + SRC1[159-128]
DEST[191-160] SRC1[255-224] + SRC1[223-192]
DEST[223-192] SRC2[191-160] + SRC2[159-128]
DEST[255-224] SRC2[255-224] + SRC2[223-192]
Intel C/C++ Compiler Intrinsic Equivalents
PHADDW:
__m64 _mm_hadd_pi16 (__m64 a, __m64 b)
PHADDD:
__m64 _mm_hadd_pi32 (__m64 a, __m64 b)
(V)PHADDW:
__m128i _mm_hadd_epi16 (__m128i a, __m128i b)
(V)PHADDD:
__m128i _mm_hadd_epi32 (__m128i a, __m128i b)
VPHADDW:
__m256i _mm256_hadd_epi16 (__m256i a, __m256i b)
VPHADDD:
__m256i _mm256_hadd_epi32 (__m256i a, __m256i b)
4-282 Vol. 2B
PHADDW/PHADDD — Packed Horizontal Add
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.L = 1.
PHADDW/PHADDD — Packed Horizontal Add
Vol. 2B 4-283
INSTRUCTION SET REFERENCE, M-U
PHADDSW — Packed Horizontal Add and Saturate
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 03 /r1
RM
V/V
SSSE3
Add 16-bit signed integers horizontally, pack
saturated integers to mm1.
RM
V/V
SSSE3
Add 16-bit signed integers horizontally, pack
saturated integers to xmm1.
RVM V/V
AVX
Add 16-bit signed integers horizontally, pack
saturated integers to xmm1.
RVM V/V
AVX2
Add 16-bit signed integers horizontally, pack
saturated integers to ymm1.
PHADDSW mm1, mm2/m64
66 0F 38 03 /r
PHADDSW xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 03 /r
VPHADDSW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 03 /r
VPHADDSW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
(V)PHADDSW adds two adjacent signed 16-bit integers horizontally from the source and destination operands and
saturates the signed results; packs the signed, saturated 16-bit results to the destination operand (first operand)
When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a
general-protection exception (#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a
64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.
Operation
PHADDSW (with 64-bit operands)
mm1[15-0] = SaturateToSignedWord((mm1[31-16] + mm1[15-0]);
mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);
mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]);
mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]);
4-284 Vol. 2B
PHADDSW — Packed Horizontal Add and Saturate
INSTRUCTION SET REFERENCE, M-U
PHADDSW (with 128-bit operands)
xmm1[15-0]= SaturateToSignedWord(xmm1[31-16] + xmm1[15-0]);
xmm1[31-16] = SaturateToSignedWord(xmm1[63-48] + xmm1[47-32]);
xmm1[47-32] = SaturateToSignedWord(xmm1[95-80] + xmm1[79-64]);
xmm1[63-48] = SaturateToSignedWord(xmm1[127-112] + xmm1[111-96]);
xmm1[79-64] = SaturateToSignedWord(xmm2/m128[31-16] + xmm2/m128[15-0]);
xmm1[95-80] = SaturateToSignedWord(xmm2/m128[63-48] + xmm2/m128[47-32]);
xmm1[111-96] = SaturateToSignedWord(xmm2/m128[95-80] + xmm2/m128[79-64]);
xmm1[127-112] = SaturateToSignedWord(xmm2/m128[127-112] + xmm2/m128[111-96]);
VPHADDSW (VEX.128 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
DEST[VLMAX-1:128] 0
VPHADDSW (VEX.256 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
DEST[143:128]= SaturateToSignedWord(SRC1[159:144] + SRC1[143:128])
DEST[159:144] = SaturateToSignedWord(SRC1[191:176] + SRC1[175:160])
DEST[175:160] = SaturateToSignedWord( SRC1[223:208] + SRC1[207:192])
DEST[191:176] = SaturateToSignedWord(SRC1[255:240] + SRC1[239:224])
DEST[207:192] = SaturateToSignedWord(SRC2[127:112] + SRC2[143:128])
DEST[223:208] = SaturateToSignedWord(SRC2[159:144] + SRC2[175:160])
DEST[239:224] = SaturateToSignedWord(SRC2[191-160] + SRC2[159-128])
DEST[255:240] = SaturateToSignedWord(SRC2[255:240] + SRC2[239:224])
Intel C/C++ Compiler Intrinsic Equivalent
PHADDSW:
__m64 _mm_hadds_pi16 (__m64 a, __m64 b)
(V)PHADDSW:
__m128i _mm_hadds_epi16 (__m128i a, __m128i b)
VPHADDSW:
__m256i _mm256_hadds_epi16 (__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.L = 1.
PHADDSW — Packed Horizontal Add and Saturate
Vol. 2B 4-285
INSTRUCTION SET REFERENCE, M-U
PHMINPOSUW — Packed Horizontal Word Minimum
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 38 41 /r
PHMINPOSUW xmm1, xmm2/m128
RM
V/V
SSE4_1
Find the minimum unsigned word in
xmm2/m128 and place its value in the low
word of xmm1 and its index in the secondlowest word of xmm1.
VEX.128.66.0F38.WIG 41 /r
VPHMINPOSUW xmm1, xmm2/m128
RM
V/V
AVX
Find the minimum unsigned word in
xmm2/m128 and place its value in the low
word of xmm1 and its index in the secondlowest word of xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Determine the minimum unsigned word value in the source operand (second operand) and place the unsigned
word in the low word (bits 0-15) of the destination operand (first operand). The word index of the minimum value
is stored in bits 16-18 of the destination operand. The remaining upper bits of the destination are set to zero.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv is reserved
and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.
Operation
PHMINPOSUW (128-bit Legacy SSE version)
INDEX 0;
MIN SRC[15:0]
IF (SRC[31:16] < MIN)
THEN INDEX 1; MIN SRC[31:16]; FI;
IF (SRC[47:32] < MIN)
THEN INDEX 2; MIN SRC[47:32]; FI;
* Repeat operation for words 3 through 6
IF (SRC[127:112] < MIN)
THEN INDEX 7; MIN SRC[127:112]; FI;
DEST[15:0] MIN;
DEST[18:16] INDEX;
DEST[127:19] 0000000000000000000000000000H;
4-286 Vol. 2B
PHMINPOSUW — Packed Horizontal Word Minimum
INSTRUCTION SET REFERENCE, M-U
VPHMINPOSUW (VEX.128 encoded version)
INDEX 0
MIN SRC[15:0]
IF (SRC[31:16] < MIN) THEN INDEX 1; MIN SRC[31:16]
IF (SRC[47:32] < MIN) THEN INDEX 2; MIN SRC[47:32]
* Repeat operation for words 3 through 6
IF (SRC[127:112] < MIN) THEN INDEX 7; MIN SRC[127:112]
DEST[15:0] MIN
DEST[18:16] INDEX
DEST[127:19] 0000000000000000000000000000H
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
PHMINPOSUW:
__m128i _mm_minpos_epu16( __m128i packed_words);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.L = 1.
If VEX.vvvv ≠ 1111B.
PHMINPOSUW — Packed Horizontal Word Minimum
Vol. 2B 4-287
INSTRUCTION SET REFERENCE, M-U
PHSUBW/PHSUBD — Packed Horizontal Subtract
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 05 /r1
RM
V/V
SSSE3
Subtract 16-bit signed integers horizontally,
pack to mm1.
RM
V/V
SSSE3
Subtract 16-bit signed integers horizontally,
pack to xmm1.
RM
V/V
SSSE3
Subtract 32-bit signed integers horizontally,
pack to mm1.
RM
V/V
SSSE3
Subtract 32-bit signed integers horizontally,
pack to xmm1.
RVM V/V
AVX
Subtract 16-bit signed integers horizontally,
pack to xmm1.
RVM V/V
AVX
Subtract 32-bit signed integers horizontally,
pack to xmm1.
RVM V/V
AVX2
Subtract 16-bit signed integers horizontally,
pack to ymm1.
RVM V/V
AVX2
Subtract 32-bit signed integers horizontally,
pack to ymm1.
PHSUBW mm1, mm2/m64
66 0F 38 05 /r
PHSUBW xmm1, xmm2/m128
0F 38 06 /r
PHSUBD mm1, mm2/m64
66 0F 38 06 /r
PHSUBD xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 05 /r
VPHSUBW xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F38.WIG 06 /r
VPHSUBD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 05 /r
VPHSUBW ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F38.WIG 06 /r
VPHSUBD ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
(V)PHSUBW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the
most significant word from the least significant word of each pair in the source and destination operands, and packs
the signed 16-bit results to the destination operand (first operand). (V)PHSUBD performs horizontal subtraction on
each adjacent pair of 32-bit signed integers by subtracting the most significant doubleword from the least significant doubleword of each pair, and packs the signed 32-bit result to the destination operand. When the source
operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a
64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
4-288 Vol. 2B
PHSUBW/PHSUBD — Packed Horizontal Subtract
INSTRUCTION SET REFERENCE, M-U
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.
Operation
PHSUBW (with 64-bit operands)
mm1[15-0] = mm1[15-0] - mm1[31-16];
mm1[31-16] = mm1[47-32] - mm1[63-48];
mm1[47-32] = mm2/m64[15-0] - mm2/m64[31-16];
mm1[63-48] = mm2/m64[47-32] - mm2/m64[63-48];
PHSUBW (with 128-bit operands)
xmm1[15-0] = xmm1[15-0] - xmm1[31-16];
xmm1[31-16] = xmm1[47-32] - xmm1[63-48];
xmm1[47-32] = xmm1[79-64] - xmm1[95-80];
xmm1[63-48] = xmm1[111-96] - xmm1[127-112];
xmm1[79-64] = xmm2/m128[15-0] - xmm2/m128[31-16];
xmm1[95-80] = xmm2/m128[47-32] - xmm2/m128[63-48];
xmm1[111-96] = xmm2/m128[79-64] - xmm2/m128[95-80];
xmm1[127-112] = xmm2/m128[111-96] - xmm2/m128[127-112];
VPHSUBW (VEX.128 encoded version)
DEST[15:0] SRC1[15:0] - SRC1[31:16]
DEST[31:16] SRC1[47:32] - SRC1[63:48]
DEST[47:32] SRC1[79:64] - SRC1[95:80]
DEST[63:48] SRC1[111:96] - SRC1[127:112]
DEST[79:64] SRC2[15:0] - SRC2[31:16]
DEST[95:80] SRC2[47:32] - SRC2[63:48]
DEST[111:96] SRC2[79:64] - SRC2[95:80]
DEST[127:112] SRC2[111:96] - SRC2[127:112]
DEST[VLMAX-1:128] 0
VPHSUBW (VEX.256 encoded version)
DEST[15:0] SRC1[15:0] - SRC1[31:16]
DEST[31:16] SRC1[47:32] - SRC1[63:48]
DEST[47:32] SRC1[79:64] - SRC1[95:80]
DEST[63:48] SRC1[111:96] - SRC1[127:112]
DEST[79:64] SRC2[15:0] - SRC2[31:16]
DEST[95:80] SRC2[47:32] - SRC2[63:48]
DEST[111:96] SRC2[79:64] - SRC2[95:80]
DEST[127:112] SRC2[111:96] - SRC2[127:112]
DEST[143:128] SRC1[143:128] - SRC1[159:144]
DEST[159:144] SRC1[175:160] - SRC1[191:176]
DEST[175:160] SRC1[207:192] - SRC1[223:208]
DEST[191:176] SRC1[239:224] - SRC1[255:240]
DEST[207:192] SRC2[143:128] - SRC2[159:144]
DEST[223:208] SRC2[175:160] - SRC2[191:176]
DEST[239:224] SRC2[207:192] - SRC2[223:208]
DEST[255:240] SRC2[239:224] - SRC2[255:240]
PHSUBD (with 64-bit operands)
mm1[31-0] = mm1[31-0] - mm1[63-32];
mm1[63-32] = mm2/m64[31-0] - mm2/m64[63-32];
PHSUBW/PHSUBD — Packed Horizontal Subtract
Vol. 2B 4-289
INSTRUCTION SET REFERENCE, M-U
PHSUBD (with 128-bit operands)
xmm1[31-0] = xmm1[31-0] - xmm1[63-32];
xmm1[63-32] = xmm1[95-64] - xmm1[127-96];
xmm1[95-64] = xmm2/m128[31-0] - xmm2/m128[63-32];
xmm1[127-96] = xmm2/m128[95-64] - xmm2/m128[127-96];
VPHSUBD (VEX.128 encoded version)
DEST[31-0] SRC1[31-0] - SRC1[63-32]
DEST[63-32] SRC1[95-64] - SRC1[127-96]
DEST[95-64] SRC2[31-0] - SRC2[63-32]
DEST[127-96] SRC2[95-64] - SRC2[127-96]
DEST[VLMAX-1:128] 0
VPHSUBD (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] - SRC1[63:32]
DEST[63:32] SRC1[95:64] - SRC1[127:96]
DEST[95:64] SRC2[31:0] - SRC2[63:32]
DEST[127:96] SRC2[95:64] - SRC2[127:96]
DEST[159:128] SRC1[159:128] - SRC1[191:160]
DEST[191:160] SRC1[223:192] - SRC1[255:224]
DEST[223:192] SRC2[159:128] - SRC2[191:160]
DEST[255:224] SRC2[223:192] - SRC2[255:224]
Intel C/C++ Compiler Intrinsic Equivalents
PHSUBW:
__m64 _mm_hsub_pi16 (__m64 a, __m64 b)
PHSUBD:
__m64 _mm_hsub_pi32 (__m64 a, __m64 b)
(V)PHSUBW:
__m128i _mm_hsub_epi16 (__m128i a, __m128i b)
(V)PHSUBD:
__m128i _mm_hsub_epi32 (__m128i a, __m128i b)
VPHSUBW:
__m256i _mm256_hsub_epi16 (__m256i a, __m256i b)
VPHSUBD:
__m256i _mm256_hsub_epi32 (__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
4-290 Vol. 2B
If VEX.L = 1.
PHSUBW/PHSUBD — Packed Horizontal Subtract
INSTRUCTION SET REFERENCE, M-U
PHSUBSW — Packed Horizontal Subtract and Saturate
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 07 /r1
RM
V/V
SSSE3
Subtract 16-bit signed integer horizontally,
pack saturated integers to mm1.
RM
V/V
SSSE3
Subtract 16-bit signed integer horizontally,
pack saturated integers to xmm1.
RVM V/V
AVX
Subtract 16-bit signed integer horizontally,
pack saturated integers to xmm1.
RVM V/V
AVX2
Subtract 16-bit signed integer horizontally,
pack saturated integers to ymm1.
PHSUBSW mm1, mm2/m64
66 0F 38 07 /r
PHSUBSW xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 07 /r
VPHSUBSW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 07 /r
VPHSUBSW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
(V)PHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the
most significant word from the least significant word of each pair in the source and destination operands. The
signed, saturated 16-bit results are packed to the destination operand (first operand). When the source operand is
a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception
(#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or
a 64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.
Operation
PHSUBSW (with 64-bit operands)
mm1[15-0] = SaturateToSignedWord(mm1[15-0] - mm1[31-16]);
mm1[31-16] = SaturateToSignedWord(mm1[47-32] - mm1[63-48]);
mm1[47-32] = SaturateToSignedWord(mm2/m64[15-0] - mm2/m64[31-16]);
mm1[63-48] = SaturateToSignedWord(mm2/m64[47-32] - mm2/m64[63-48]);
PHSUBSW — Packed Horizontal Subtract and Saturate
Vol. 2B 4-291
INSTRUCTION SET REFERENCE, M-U
PHSUBSW (with 128-bit operands)
xmm1[15-0] = SaturateToSignedWord(xmm1[15-0] - xmm1[31-16]);
xmm1[31-16] = SaturateToSignedWord(xmm1[47-32] - xmm1[63-48]);
xmm1[47-32] = SaturateToSignedWord(xmm1[79-64] - xmm1[95-80]);
xmm1[63-48] = SaturateToSignedWord(xmm1[111-96] - xmm1[127-112]);
xmm1[79-64] = SaturateToSignedWord(xmm2/m128[15-0] - xmm2/m128[31-16]);
xmm1[95-80] =SaturateToSignedWord(xmm2/m128[47-32] - xmm2/m128[63-48]);
xmm1[111-96] =SaturateToSignedWord(xmm2/m128[79-64] - xmm2/m128[95-80]);
xmm1[127-112]= SaturateToSignedWord(xmm2/m128[111-96] - xmm2/m128[127-112]);
VPHSUBSW (VEX.128 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])
DEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])
DEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])
DEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])
DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])
DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])
DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])
DEST[VLMAX-1:128] 0
VPHSUBSW (VEX.256 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])
DEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])
DEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])
DEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])
DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])
DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])
DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])
DEST[143:128]= SaturateToSignedWord(SRC1[143:128] - SRC1[159:144])
DEST[159:144] = SaturateToSignedWord(SRC1[175:160] - SRC1[191:176])
DEST[175:160] = SaturateToSignedWord(SRC1[207:192] - SRC1[223:208])
DEST[191:176] = SaturateToSignedWord(SRC1[239:224] - SRC1[255:240])
DEST[207:192] = SaturateToSignedWord(SRC2[143:128] - SRC2[159:144])
DEST[223:208] = SaturateToSignedWord(SRC2[175:160] - SRC2[191:176])
DEST[239:224] = SaturateToSignedWord(SRC2[207:192] - SRC2[223:208])
DEST[255:240] = SaturateToSignedWord(SRC2[239:224] - SRC2[255:240])
Intel C/C++ Compiler Intrinsic Equivalent
PHSUBSW:
__m64 _mm_hsubs_pi16 (__m64 a, __m64 b)
(V)PHSUBSW:
__m128i _mm_hsubs_epi16 (__m128i a, __m128i b)
VPHSUBSW:
__m256i _mm256_hsubs_epi16 (__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
4-292 Vol. 2B
If VEX.L = 1.
PHSUBSW — Packed Horizontal Subtract and Saturate
INSTRUCTION SET REFERENCE, M-U
PINSRB/PINSRD/PINSRQ — Insert Byte/Dword/Qword
Opcode/
Instruction
Op/ En 64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 20 /r ib
PINSRB xmm1, r32/m8, imm8
RMI
V/V
SSE4_1
Insert a byte integer value from r32/m8 into
xmm1 at the destination element in xmm1
specified by imm8.
66 0F 3A 22 /r ib
PINSRD xmm1, r/m32, imm8
RMI
V/V
SSE4_1
Insert a dword integer value from r/m32 into
the xmm1 at the destination element
specified by imm8.
66 REX.W 0F 3A 22 /r ib
PINSRQ xmm1, r/m64, imm8
RMI
V/N. E.
SSE4_1
Insert a qword integer value from r/m64 into
the xmm1 at the destination element
specified by imm8.
VEX.NDS.128.66.0F3A.W0 20 /r ib
VPINSRB xmm1, xmm2, r32/m8, imm8
RVMI
V1/V
AVX
Merge a byte integer value from r32/m8 and
rest from xmm2 into xmm1 at the byte offset
in imm8.
VEX.NDS.128.66.0F3A.W0 22 /r ib
VPINSRD xmm1, xmm2, r/m32, imm8
RVMI
V/V
AVX
Insert a dword integer value from r32/m32
and rest from xmm2 into xmm1 at the dword
offset in imm8.
VEX.NDS.128.66.0F3A.W1 22 /r ib
VPINSRQ xmm1, xmm2, r/m64, imm8
RVMI
V/I
AVX
Insert a qword integer value from r64/m64
and rest from xmm2 into xmm1 at the qword
offset in imm8.
EVEX.NDS.128.66.0F3A.WIG 20 /r ib
VPINSRB xmm1, xmm2, r32/m8, imm8
T1SRVMI
V/V
AVX512BW Merge a byte integer value from r32/m8 and
rest from xmm2 into xmm1 at the byte offset
in imm8.
EVEX.NDS.128.66.0F3A.W0 22 /r ib
VPINSRD xmm1, xmm2, r32/m32, imm8
T1SRVMI
V/V
AVX512DQ
Insert a dword integer value from r32/m32
and rest from xmm2 into xmm1 at the dword
offset in imm8.
EVEX.NDS.128.66.0F3A.W1 22 /r ib
VPINSRQ xmm1, xmm2, r64/m64, imm8
T1SRVMI
V/N.E.1
AVX512DQ
Insert a qword integer value from r64/m64
and rest from xmm2 into xmm1 at the qword
offset in imm8.
NOTES:
1. In 64-bit mode, VEX.W1 is ignored for VPINSRB (similar to legacy REX.W=1 prefix with PINSRB).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
T1S-RVMI
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
Copies a byte/dword/qword from the source operand (second operand) and inserts it in the destination operand
(first operand) at the location specified with the count operand (third operand). (The other elements in the destination register are left untouched.) The source operand can be a general-purpose register or a memory location.
(When the source operand is a general-purpose register, PINSRB copies the low byte of the register.) The destination operand is an XMM register. The count operand is an 8-bit immediate. When specifying a qword[dword, byte]
location in an XMM register, the [2, 4] least-significant bit(s) of the count operand specify the location.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15, R8-15). Use of REX.W permits the use of 64 bit general purpose registers.
PINSRB/PINSRD/PINSRQ — Insert Byte/Dword/Qword
Vol. 2B 4-293
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. VEX.L must be 0, otherwise
the instruction will #UD. Attempt to execute VPINSRQ in non-64-bit mode will cause #UD.
EVEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. EVEX.L’L must be 0, otherwise the instruction will #UD.
Operation
CASE OF
PINSRB: SEL COUNT[3:0];
MASK (0FFH << (SEL * 8));
TEMP (((SRC[7:0] << (SEL *8)) AND MASK);
PINSRD: SEL COUNT[1:0];
MASK (0FFFFFFFFH << (SEL * 32));
TEMP (((SRC << (SEL *32)) AND MASK) ;
PINSRQ: SEL COUNT[0]
MASK (0FFFFFFFFFFFFFFFFH << (SEL * 64));
TEMP (((SRC << (SEL *64)) AND MASK) ;
ESAC;
DEST ((DEST AND NOT MASK) OR TEMP);
VPINSRB (VEX/EVEX encoded version)
SEL imm8[3:0]
DEST[127:0] write_b_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] 0
VPINSRD (VEX/EVEX encoded version)
SEL imm8[1:0]
DEST[127:0] write_d_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] 0
VPINSRQ (VEX/EVEX encoded version)
SEL imm8[0]
DEST[127:0] write_q_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
PINSRB:
__m128i _mm_insert_epi8 (__m128i s1, int s2, const int ndx);
PINSRD:
__m128i _mm_insert_epi32 (__m128i s2, int s, const int ndx);
PINSRQ:
__m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.
4-294 Vol. 2B
PINSRB/PINSRD/PINSRQ — Insert Byte/Dword/Qword
INSTRUCTION SET REFERENCE, M-U
#UD
If VEX.L = 1 or EVEX.L’L > 0.
If VPINSRQ in non-64-bit mode with VEX.W=1.
PINSRB/PINSRD/PINSRQ — Insert Byte/Dword/Qword
Vol. 2B 4-295
INSTRUCTION SET REFERENCE, M-U
PINSRW—Insert Word
Opcode/
Instruction
Op/ En 64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F C4 /r ib1
RMI
V/V
SSE
Insert the low word from r32 or from m16
into mm at the word position specified by
imm8.
RMI
V/V
SSE2
Move the low word of r32 or from m16 into
xmm at the word position specified by imm8.
RVMI
V2/V
AVX
Insert a word integer value from r32/m16
and rest from xmm2 into xmm1 at the word
offset in imm8.
T1SRVMI
V/V
AVX512BW Insert a word integer value from r32/m16 and
rest from xmm2 into xmm1 at the word
offset in imm8.
PINSRW mm, r32/m16, imm8
66 0F C4 /r ib
PINSRW xmm, r32/m16, imm8
VEX.NDS.128.66.0F.W0 C4 /r ib
VPINSRW xmm1, xmm2, r32/m16, imm8
EVEX.NDS.128.66.0F.WIG C4 /r ib
VPINSRW xmm1, xmm2, r32/m16, imm8
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
2. In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
T1S-RVMI
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
Copies a word from the source operand (second operand) and inserts it in the destination operand (first operand)
at the location specified with the count operand (third operand). (The other words in the destination register are
left untouched.) The source operand can be a general-purpose register or a 16-bit memory location. (When the
source operand is a general-purpose register, the low word of the register is copied.) The destination operand can
be an MMX technology register or an XMM register. The count operand is an 8-bit immediate. When specifying a
word location in an MMX technology register, the 2 least-significant bits of the count operand specify the location;
for an XMM register, the 3 least-significant bits specify the location.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15, R8-15).
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.L must be 0, otherwise the instruction will #UD.
EVEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. EVEX.L’L must be 0, otherwise the instruction will #UD.
Operation
PINSRW (with 64-bit source operand)
SEL ← COUNT AND 3H;
CASE (Determine word position) OF
SEL ← 0:
MASK ← 000000000000FFFFH;
4-296 Vol. 2B
PINSRW—Insert Word
INSTRUCTION SET REFERENCE, M-U
SEL ← 1:
MASK ← 00000000FFFF0000H;
SEL ← 2:
MASK ← 0000FFFF00000000H;
SEL ← 3:
MASK ← FFFF000000000000H;
DEST ← (DEST AND NOT MASK) OR (((SRC << (SEL ∗ 16)) AND MASK);
PINSRW (with 128-bit source operand)
SEL ← COUNT AND 7H;
CASE (Determine word position) OF
SEL ← 0:
MASK ← 0000000000000000000000000000FFFFH;
SEL ← 1:
MASK ← 000000000000000000000000FFFF0000H;
SEL ← 2:
MASK ← 00000000000000000000FFFF00000000H;
SEL ← 3:
MASK ← 0000000000000000FFFF000000000000H;
SEL ← 4:
MASK ← 000000000000FFFF0000000000000000H;
SEL ← 5:
MASK ← 00000000FFFF00000000000000000000H;
SEL ← 6:
MASK ← 0000FFFF000000000000000000000000H;
SEL ← 7:
MASK ← FFFF0000000000000000000000000000H;
DEST ← (DEST AND NOT MASK) OR (((SRC << (SEL ∗ 16)) AND MASK);
VPINSRW (VEX/EVEX encoded version)
SEL imm8[2:0]
DEST[127:0] write_w_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
PINSRW:
__m64 _mm_insert_pi16 (__m64 a, int d, int n)
PINSRW:
__m128i _mm_insert_epi16 ( __m128i a, int b, int imm)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD
PINSRW—Insert Word
If VEX.L = 1 or EVEX.L’L > 0.
Vol. 2B 4-297
INSTRUCTION SET REFERENCE, M-U
PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 04 /r1
RM
V/V
SSSE3
Multiply signed and unsigned bytes, add
horizontal pair of signed words, pack
saturated signed-words to mm1.
RM
V/V
SSSE3
Multiply signed and unsigned bytes, add
horizontal pair of signed words, pack
saturated signed-words to xmm1.
RVM V/V
AVX
Multiply signed and unsigned bytes, add
horizontal pair of signed words, pack
saturated signed-words to xmm1.
RVM V/V
AVX2
Multiply signed and unsigned bytes, add
horizontal pair of signed words, pack
saturated signed-words to ymm1.
EVEX.NDS.128.66.0F38.WIG 04 /r
VPMADDUBSW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Multiply signed and unsigned bytes, add
AVX512BW horizontal pair of signed words, pack
saturated signed-words to xmm1 under
writemask k1.
EVEX.NDS.256.66.0F38.WIG 04 /r
VPMADDUBSW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Multiply signed and unsigned bytes, add
AVX512BW horizontal pair of signed words, pack
saturated signed-words to ymm1 under
writemask k1.
EVEX.NDS.512.66.0F38.WIG 04 /r
VPMADDUBSW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Multiply signed and unsigned bytes, add
horizontal pair of signed words, pack
saturated signed-words to zmm1 under
writemask k1.
PMADDUBSW mm1, mm2/m64
66 0F 38 04 /r
PMADDUBSW xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 04 /r
VPMADDUBSW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 04 /r
VPMADDUBSW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corresponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each
adjacent pair of signed words is added and the saturated result is packed to the destination operand. For example,
the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed
word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the
operands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same operation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When
the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a
general-protection exception (#GP) will be generated.
In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15.
4-298 Vol. 2B
PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 and EVEX.128 encoded versions: The first source and destination operands are XMM registers. The
second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 and EVEX.256 encoded versions: The second source operand can be an YMM register or a 256-bit memory
location. The first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding
ZMM register are zeroed.
EVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The
first source and destination operands are ZMM registers.
Operation
PMADDUBSW (with 64 bit operands)
DEST[15-0] = SaturateToSignedWord(SRC[15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);
DEST[31-16] = SaturateToSignedWord(SRC[31-24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);
DEST[47-32] = SaturateToSignedWord(SRC[47-40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);
DEST[63-48] = SaturateToSignedWord(SRC[63-56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);
PMADDUBSW (with 128 bit operands)
DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);
// Repeat operation for 2nd through 7th word
SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]*DEST[127-120]+ SRC[119-112]* DEST[119-112]);
VPMADDUBSW (VEX.128 encoded version)
DEST[15:0] SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
// Repeat operation for 2nd through 7th word
DEST[127:112] SaturateToSignedWord(SRC2[127:120]*SRC1[127:120]+ SRC2[119:112]* SRC1[119:112])
DEST[VLMAX-1:128] 0
VPMADDUBSW (VEX.256 encoded version)
DEST[15:0] SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
// Repeat operation for 2nd through 15th word
DEST[255:240] SaturateToSignedWord(SRC2[255:248]*SRC1[255:248]+ SRC2[247:240]* SRC1[247:240])
DEST[VLMAX-1:256] 0
VPMADDUBSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateToSignedWord(SRC2[i+15:i+8]* SRC1[i+15:i+8] + SRC2[i+7:i]*SRC1[i+7:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes
Vol. 2B 4-299
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalents
VPMADDUBSW __m512i _mm512_mddubs_epi16( __m512i a, __m512i b);
VPMADDUBSW __m512i _mm512_mask_mddubs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMADDUBSW __m512i _mm512_maskz_mddubs_epi16( __mmask32 k, __m512i a, __m512i b);
VPMADDUBSW __m256i _mm256_mask_mddubs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMADDUBSW __m256i _mm256_maskz_mddubs_epi16( __mmask16 k, __m256i a, __m256i b);
VPMADDUBSW __m128i _mm_mask_mddubs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMADDUBSW __m128i _mm_maskz_maddubs_epi16( __mmask8 k, __m128i a, __m128i b);
PMADDUBSW: __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)
(V)PMADDUBSW: __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
VPMADDUBSW:
__m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
4-300 Vol. 2B
PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes
INSTRUCTION SET REFERENCE, M-U
PMADDWD—Multiply and Add Packed Integers
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F F5 /r1
RM
V/V
MMX
Multiply the packed words in mm by the packed
words in mm/m64, add adjacent doubleword
results, and store in mm.
RM
V/V
SSE2
Multiply the packed word integers in xmm1 by
the packed word integers in xmm2/m128, add
adjacent doubleword results, and store in
xmm1.
RVM V/V
AVX
Multiply the packed word integers in xmm2 by
the packed word integers in xmm3/m128, add
adjacent doubleword results, and store in
xmm1.
RVM V/V
AVX2
Multiply the packed word integers in ymm2 by
the packed word integers in ymm3/m256, add
adjacent doubleword results, and store in
ymm1.
EVEX.NDS.128.66.0F.WIG F5 /r
VPMADDWD xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Multiply the packed word integers in xmm2 by
AVX512BW the packed word integers in xmm3/m128, add
adjacent doubleword results, and store in
xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG F5 /r
VPMADDWD ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Multiply the packed word integers in ymm2 by
AVX512BW the packed word integers in ymm3/m256, add
adjacent doubleword results, and store in
ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG F5 /r
VPMADDWD zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Multiply the packed word integers in zmm2 by
the packed word integers in zmm3/m512, add
adjacent doubleword results, and store in
zmm1 under writemask k1.
PMADDWD mm, mm/m64
66 0F F5 /r
PMADDWD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG F5 /r
VPMADDWD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG F5 /r
VPMADDWD ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Multiplies the individual signed words of the destination operand (first operand) by the corresponding signed words
of the source operand (second operand), producing temporary signed, doubleword results. The adjacent doubleword results are then summed and stored in the destination operand. For example, the corresponding low-order
words (15-0) and (31-16) in the source and destination operands are multiplied by one another and the doubleword results are added together and stored in the low doubleword of the destination register (31-0). The same
operation is performed on the other pairs of adjacent words. (Figure 4-11 shows this operation when using 64-bit
operands).
PMADDWD—Multiply and Add Packed Integers
Vol. 2B 4-301
INSTRUCTION SET REFERENCE, M-U
The (V)PMADDWD instruction wraps around only in one situation: when the 2 pairs of words being operated on in
a group are all 8000H. In this case, the result wraps around to 80000000H.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version: The first source and destination operands are MMX registers. The second source operand is an
MMX register or a 64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The
first source and destination operands are ZMM registers.
SRC
DEST
TEMP
X3 ∗ Y3
DEST
X3
Y3
X2
Y2
X2 ∗ Y2
X1
X0
Y1
Y0
X1 ∗ Y1
X0 ∗ Y0
(X3∗Y3) + (X2∗Y2) (X1∗Y1) + (X0∗Y0)
Figure 4-11. PMADDWD Execution Model Using 64-bit Operands
Operation
PMADDWD (with 64-bit operands)
DEST[31:0] ← (DEST[15:0] ∗ SRC[15:0]) + (DEST[31:16] ∗ SRC[31:16]);
DEST[63:32] ← (DEST[47:32] ∗ SRC[47:32]) + (DEST[63:48] ∗ SRC[63:48]);
PMADDWD (with 128-bit operands)
DEST[31:0] ← (DEST[15:0] ∗ SRC[15:0]) + (DEST[31:16] ∗ SRC[31:16]);
DEST[63:32] ← (DEST[47:32] ∗ SRC[47:32]) + (DEST[63:48] ∗ SRC[63:48]);
DEST[95:64] ← (DEST[79:64] ∗ SRC[79:64]) + (DEST[95:80] ∗ SRC[95:80]);
DEST[127:96] ← (DEST[111:96] ∗ SRC[111:96]) + (DEST[127:112] ∗ SRC[127:112]);
VPMADDWD (VEX.128 encoded version)
DEST[31:0] (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])
DEST[63:32] (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])
DEST[95:64] (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])
DEST[127:96] (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])
DEST[VLMAX-1:128] 0
VPMADDWD (VEX.256 encoded version)
DEST[31:0] (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])
DEST[63:32] (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])
DEST[95:64] (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])
DEST[127:96] (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])
4-302 Vol. 2B
PMADDWD—Multiply and Add Packed Integers
INSTRUCTION SET REFERENCE, M-U
DEST[159:128] (SRC1[143:128] * SRC2[143:128]) + (SRC1[159:144] * SRC2[159:144])
DEST[191:160] (SRC1[175:160] * SRC2[175:160]) + (SRC1[191:176] * SRC2[191:176])
DEST[223:192] (SRC1[207:192] * SRC2[207:192]) + (SRC1[223:208] * SRC2[223:208])
DEST[255:224] (SRC1[239:224] * SRC2[239:224]) + (SRC1[255:240] * SRC2[255:240])
DEST[VLMAX-1:256] 0
VPMADDWD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] (SRC2[i+31:i+16]* SRC1[i+31:i+16]) + (SRC2[i+15:i]*SRC1[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMADDWD __m512i _mm512_mdd_epi16( __m512i a, __m512i b);
VPMADDWD __m512i _mm512_mask_mdd_epi16(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMADDWD __m512i _mm512_maskz_mdd_epi16( __mmask16 k, __m512i a, __m512i b);
VPMADDWD __m256i _mm256_mask_mdd_epi16(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMADDWD __m256i _mm256_maskz_mdd_epi16( __mmask8 k, __m256i a, __m256i b);
VPMADDWD __m128i _mm_mask_mdd_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMADDWD __m128i _mm_maskz_madd_epi16( __mmask8 k, __m128i a, __m128i b);
PMADDWD:__m64 _mm_madd_pi16(__m64 m1, __m64 m2)
(V)PMADDWD:__m128i _mm_madd_epi16 ( __m128i a, __m128i b)
VPMADDWD:__m256i _mm256_madd_epi16 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
PMADDWD—Multiply and Add Packed Integers
Vol. 2B 4-303
INSTRUCTION SET REFERENCE, M-U
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
Opcode/
Instruction
Op /
En
CPUID
Feature
Flag
SSE
Description
RM
64/32
bit Mode
Support
V/V
0F EE /r1
PMAXSW mm1, mm2/m64
66 0F 38 3C /r
PMAXSB xmm1, xmm2/m128
RM
V/V
SSE4_1
66 0F EE /r
PMAXSW xmm1, xmm2/m128
RM
V/V
SSE2
66 0F 38 3D /r
PMAXSD xmm1, xmm2/m128
RM
V/V
SSE4_1
VEX.NDS.128.66.0F38.WIG 3C /r
VPMAXSB xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.128.66.0F.WIG EE /r
VPMAXSW xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.128.66.0F38.WIG 3D /r
VPMAXSD xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F38.WIG 3C /r
VPMAXSB ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
VEX.NDS.256.66.0F.WIG EE /r
VPMAXSW ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
VEX.NDS.256.66.0F38.WIG 3D /r
VPMAXSD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.WIG 3C /r
VPMAXSB xmm1{k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.WIG 3C /r
VPMAXSB ymm1{k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.WIG 3C /r
VPMAXSB zmm1{k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F.WIG EE /r
VPMAXSW xmm1{k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F.WIG EE /r
VPMAXSW ymm1{k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F.WIG EE /r
VPMAXSW zmm1{k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38.W0 3D /r
VPMAXSD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FV
V/V
AVX512VL
AVX512F
Compare packed signed byte integers in xmm1 and
xmm2/m128 and store packed maximum values in
xmm1.
Compare packed signed word integers in
xmm2/m128 and xmm1 and stores maximum
packed values in xmm1.
Compare packed signed dword integers in xmm1
and xmm2/m128 and store packed maximum values
in xmm1.
Compare packed signed byte integers in xmm2 and
xmm3/m128 and store packed maximum values in
xmm1.
Compare packed signed word integers in
xmm3/m128 and xmm2 and store packed maximum
values in xmm1.
Compare packed signed dword integers in xmm2
and xmm3/m128 and store packed maximum values
in xmm1.
Compare packed signed byte integers in ymm2 and
ymm3/m256 and store packed maximum values in
ymm1.
Compare packed signed word integers in
ymm3/m256 and ymm2 and store packed maximum
values in ymm1.
Compare packed signed dword integers in ymm2
and ymm3/m256 and store packed maximum values
in ymm1.
Compare packed signed byte integers in xmm2 and
xmm3/m128 and store packed maximum values in
xmm1 under writemask k1.
Compare packed signed byte integers in ymm2 and
ymm3/m256 and store packed maximum values in
ymm1 under writemask k1.
Compare packed signed byte integers in zmm2 and
zmm3/m512 and store packed maximum values in
zmm1 under writemask k1.
Compare packed signed word integers in xmm2 and
xmm3/m128 and store packed maximum values in
xmm1 under writemask k1.
Compare packed signed word integers in ymm2 and
ymm3/m256 and store packed maximum values in
ymm1 under writemask k1.
Compare packed signed word integers in zmm2 and
zmm3/m512 and store packed maximum values in
zmm1 under writemask k1.
Compare packed signed dword integers in xmm2
and xmm3/m128/m32bcst and store packed
maximum values in xmm1 using writemask k1.
4-304 Vol. 2B
Compare signed word integers in mm2/m64 and
mm1 and return maximum values.
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W0 3D /r
VPMAXSD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 3D /r
VPMAXSD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 3D /r
VPMAXSQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 3D /r
VPMAXSQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 3D /r
VPMAXSQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Compare packed signed dword integers in ymm2
and ymm3/m256/m32bcst and store packed
maximum values in ymm1 using writemask k1.
Compare packed signed dword integers in zmm2 and
zmm3/m512/m32bcst and store packed maximum
values in zmm1 using writemask k1.
Compare packed signed qword integers in xmm2
and xmm3/m128/m64bcst and store packed
maximum values in xmm1 using writemask k1.
Compare packed signed qword integers in ymm2
and ymm3/m256/m64bcst and store packed
maximum values in ymm1 using writemask k1.
Compare packed signed qword integers in zmm2 and
zmm3/m512/m64bcst and store packed maximum
values in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed signed byte, word, dword or qword integers in the second source operand
and the first source operand and returns the maximum value for each pair of integers to the destination operand.
Legacy SSE version PMAXSW: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination
register are zeroed.
EVEX encoded VPMAXSD/Q: The first source operand is a ZMM/YMM/XMM register; The second source operand is
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
EVEX encoded VPMAXSB/W: The first source operand is a ZMM/YMM/XMM register; The second source operand is
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.
Operation
PMAXSW (64-bit operands)
IF DEST[15:0] > SRC[15:0]) THEN
DEST[15:0] ← DEST[15:0];
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
Vol. 2B 4-305
INSTRUCTION SET REFERENCE, M-U
ELSE
DEST[15:0] ← SRC[15:0]; FI;
(* Repeat operation for 2nd and 3rd words in source and destination operands *)
IF DEST[63:48] > SRC[63:48]) THEN
DEST[63:48] ← DEST[63:48];
ELSE
DEST[63:48] ← SRC[63:48]; FI;
PMAXSB (128-bit Legacy SSE version)
IF DEST[7:0] >SRC[7:0] THEN
DEST[7:0] DEST[7:0];
ELSE
DEST[7:0] SRC[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF DEST[127:120] >SRC[127:120] THEN
DEST[127:120] DEST[127:120];
ELSE
DEST[127:120] SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMAXSB (VEX.128 encoded version)
IF SRC1[7:0] >SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[7:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF SRC1[127:120] >SRC2[127:120] THEN
DEST[127:120] SRC1[127:120];
ELSE
DEST[127:120] SRC2[127:120]; FI;
DEST[MAX_VL-1:128] 0
VPMAXSB (VEX.256 encoded version)
IF SRC1[7:0] >SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[7:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 31st bytes in source and destination operands *)
IF SRC1[255:248] >SRC2[255:248] THEN
DEST[255:248] SRC1[255:248];
ELSE
DEST[255:248] SRC2[255:248]; FI;
DEST[MAX_VL-1:256] 0
VPMAXSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask* THEN
IF SRC1[i+7:i] > SRC2[i+7:i]
THEN DEST[i+7:i] SRC1[i+7:i];
ELSE DEST[i+7:i] SRC2[i+7:i];
FI;
ELSE
4-306 Vol. 2B
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PMAXSW (128-bit Legacy SSE version)
IF DEST[15:0] >SRC[15:0] THEN
DEST[15:0] DEST[15:0];
ELSE
DEST[15:0] SRC[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:112] >SRC[127:112] THEN
DEST[127:112] DEST[127:112];
ELSE
DEST[127:112] SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMAXSW (VEX.128 encoded version)
IF SRC1[15:0] > SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF SRC1[127:112] >SRC2[127:112] THEN
DEST[127:112] SRC1[127:112];
ELSE
DEST[127:112] SRC2[127:112]; FI;
DEST[MAX_VL-1:128] 0
VPMAXSW (VEX.256 encoded version)
IF SRC1[15:0] > SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 15th words in source and destination operands *)
IF SRC1[255:240] >SRC2[255:240] THEN
DEST[255:240] SRC1[255:240];
ELSE
DEST[255:240] SRC2[255:240]; FI;
DEST[MAX_VL-1:256] 0
VPMAXSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask* THEN
IF SRC1[i+15:i] > SRC2[i+15:i]
THEN DEST[i+15:i] SRC1[i+15:i];
ELSE DEST[i+15:i] SRC2[i+15:i];
FI;
ELSE
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
Vol. 2B 4-307
INSTRUCTION SET REFERENCE, M-U
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PMAXSD (128-bit Legacy SSE version)
IF DEST[31:0] >SRC[31:0] THEN
DEST[31:0] DEST[31:0];
ELSE
DEST[31:0] SRC[31:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:96] >SRC[127:96] THEN
DEST[127:96] DEST[127:96];
ELSE
DEST[127:96] SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMAXSD (VEX.128 encoded version)
IF SRC1[31:0] > SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
IF SRC1[127:96] > SRC2[127:96] THEN
DEST[127:96] SRC1[127:96];
ELSE
DEST[127:96] SRC2[127:96]; FI;
DEST[MAX_VL-1:128] 0
VPMAXSD (VEX.256 encoded version)
IF SRC1[31:0] > SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 7th dwords in source and destination operands *)
IF SRC1[255:224] > SRC2[255:224] THEN
DEST[255:224] SRC1[255:224];
ELSE
DEST[255:224] SRC2[255:224]; FI;
DEST[MAX_VL-1:256] 0
VPMAXSD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+31:i] > SRC2[31:0]
THEN DEST[i+31:i] SRC1[i+31:i];
4-308 Vol. 2B
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
ELSE DEST[i+31:i] SRC2[31:0];
FI;
ELSE
IF SRC1[i+31:i] > SRC2[i+31:i]
THEN DEST[i+31:i] SRC1[i+31:i];
ELSE DEST[i+31:i] SRC2[i+31:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMAXSQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+63:i] > SRC2[63:0]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[63:0];
FI;
ELSE
IF SRC1[i+63:i] > SRC2[i+63:i]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[i+63:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMAXSB __m512i _mm512_max_epi8( __m512i a, __m512i b);
VPMAXSB __m512i _mm512_mask_max_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMAXSB __m512i _mm512_maskz_max_epi8( __mmask64 k, __m512i a, __m512i b);
VPMAXSW __m512i _mm512_max_epi16( __m512i a, __m512i b);
VPMAXSW __m512i _mm512_mask_max_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMAXSW __m512i _mm512_maskz_max_epi16( __mmask32 k, __m512i a, __m512i b);
VPMAXSB __m256i _mm256_mask_max_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMAXSB __m256i _mm256_maskz_max_epi8( __mmask32 k, __m256i a, __m256i b);
VPMAXSW __m256i _mm256_mask_max_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
Vol. 2B 4-309
INSTRUCTION SET REFERENCE, M-U
VPMAXSW __m256i _mm256_maskz_max_epi16( __mmask16 k, __m256i a, __m256i b);
VPMAXSB __m128i _mm_mask_max_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMAXSB __m128i _mm_maskz_max_epi8( __mmask16 k, __m128i a, __m128i b);
VPMAXSW __m128i _mm_mask_max_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSW __m128i _mm_maskz_max_epi16( __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m256i _mm256_mask_max_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMAXSD __m256i _mm256_maskz_max_epi32( __mmask16 k, __m256i a, __m256i b);
VPMAXSQ __m256i _mm256_mask_max_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMAXSQ __m256i _mm256_maskz_max_epi64( __mmask8 k, __m256i a, __m256i b);
VPMAXSD __m128i _mm_mask_max_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m128i _mm_maskz_max_epi32( __mmask8 k, __m128i a, __m128i b);
VPMAXSQ __m128i _mm_mask_max_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m512i _mm512_max_epi32( __m512i a, __m512i b);
VPMAXSD __m512i _mm512_mask_max_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMAXSD __m512i _mm512_maskz_max_epi32( __mmask16 k, __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_max_epi64( __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_mask_max_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_maskz_max_epi64( __mmask8 k, __m512i a, __m512i b);
(V)PMAXSB __m128i _mm_max_epi8 ( __m128i a, __m128i b);
(V)PMAXSW __m128i _mm_max_epi16 ( __m128i a, __m128i b)
(V)PMAXSD __m128i _mm_max_epi32 ( __m128i a, __m128i b);
VPMAXSB __m256i _mm256_max_epi8 ( __m256i a, __m256i b);
VPMAXSW __m256i _mm256_max_epi16 ( __m256i a, __m256i b)
VPMAXSD __m256i _mm256_max_epi32 ( __m256i a, __m256i b);
PMAXSW:__m64 _mm_max_pi16(__m64 a, __m64 b)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPMAXSD/Q, see Exceptions Type E4.
EVEX-encoded VPMAXSB/W, see Exceptions Type E4.nb.
4-310 Vol. 2B
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F DE /r1
PMAXUB mm1, mm2/m64
66 0F DE /r
PMAXUB xmm1, xmm2/m128
RM
V/V
SSE2
66 0F 38 3E/r
PMAXUW xmm1, xmm2/m128
RM
V/V
SSE4_1
VEX.NDS.128.66.0F DE /r
VPMAXUB xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.128.66.0F38 3E/r
VPMAXUW xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F DE /r
VPMAXUB ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
VEX.NDS.256.66.0F38 3E/r
VPMAXUW ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F.WIG DE /r
VPMAXUB xmm1{k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F.WIG DE /r
VPMAXUB ymm1{k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F.WIG DE /r
VPMAXUB zmm1{k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38.WIG 3E /r
VPMAXUW xmm1{k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.WIG 3E /r
VPMAXUW ymm1{k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.WIG 3E /r
VPMAXUW zmm1{k1}{z}, zmm2,
zmm3/m512
NOTES:
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
Description
Compare unsigned byte integers in mm2/m64 and
mm1 and returns maximum values.
Compare packed unsigned byte integers in xmm1
and xmm2/m128 and store packed maximum
values in xmm1.
Compare packed unsigned word integers in
xmm2/m128 and xmm1 and stores maximum
packed values in xmm1.
Compare packed unsigned byte integers in xmm2
and xmm3/m128 and store packed maximum
values in xmm1.
Compare packed unsigned word integers in
xmm3/m128 and xmm2 and store maximum
packed values in xmm1.
Compare packed unsigned byte integers in ymm2
and ymm3/m256 and store packed maximum
values in ymm1.
Compare packed unsigned word integers in
ymm3/m256 and ymm2 and store maximum
packed values in ymm1.
Compare packed unsigned byte integers in xmm2
and xmm3/m128 and store packed maximum
values in xmm1 under writemask k1.
Compare packed unsigned byte integers in ymm2
and ymm3/m256 and store packed maximum
values in ymm1 under writemask k1.
Compare packed unsigned byte integers in zmm2
and zmm3/m512 and store packed maximum
values in zmm1 under writemask k1.
Compare packed unsigned word integers in xmm2
and xmm3/m128 and store packed maximum
values in xmm1 under writemask k1.
Compare packed unsigned word integers in ymm2
and ymm3/m256 and store packed maximum
values in ymm1 under writemask k1.
Compare packed unsigned word integers in zmm2
and zmm3/m512 and store packed maximum
values in zmm1 under writemask k1.
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers
Vol. 2B 4-311
INSTRUCTION SET REFERENCE, M-U
Description
Performs a SIMD compare of the packed unsigned byte, word integers in the second source operand and the first
source operand and returns the maximum value for each pair of integers to the destination operand.
Legacy SSE version PMAXUB: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.
Operation
PMAXUB (64-bit operands)
IF DEST[7:0] > SRC[17:0]) THEN
DEST[7:0] ← DEST[7:0];
ELSE
DEST[7:0] ← SRC[7:0]; FI;
(* Repeat operation for 2nd through 7th bytes in source and destination operands *)
IF DEST[63:56] > SRC[63:56]) THEN
DEST[63:56] ← DEST[63:56];
ELSE
DEST[63:56] ← SRC[63:56]; FI;
PMAXUB (128-bit Legacy SSE version)
IF DEST[7:0] >SRC[7:0] THEN
DEST[7:0] DEST[7:0];
ELSE
DEST[15:0] SRC[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF DEST[127:120] >SRC[127:120] THEN
DEST[127:120] DEST[127:120];
ELSE
DEST[127:120] SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMAXUB (VEX.128 encoded version)
IF SRC1[7:0] >SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[7:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF SRC1[127:120] >SRC2[127:120] THEN
DEST[127:120] SRC1[127:120];
ELSE
DEST[127:120] SRC2[127:120]; FI;
DEST[MAX_VL-1:128] 0
4-312 Vol. 2B
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
VPMAXUB (VEX.256 encoded version)
IF SRC1[7:0] >SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[15:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 31st bytes in source and destination operands *)
IF SRC1[255:248] >SRC2[255:248] THEN
DEST[255:248] SRC1[255:248];
ELSE
DEST[255:248] SRC2[255:248]; FI;
DEST[MAX_VL-1:128] 0
VPMAXUB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask* THEN
IF SRC1[i+7:i] > SRC2[i+7:i]
THEN DEST[i+7:i] SRC1[i+7:i];
ELSE DEST[i+7:i] SRC2[i+7:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PMAXUW (128-bit Legacy SSE version)
IF DEST[15:0] >SRC[15:0] THEN
DEST[15:0] DEST[15:0];
ELSE
DEST[15:0] SRC[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:112] >SRC[127:112] THEN
DEST[127:112] DEST[127:112];
ELSE
DEST[127:112] SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMAXUW (VEX.128 encoded version)
IF SRC1[15:0] > SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF SRC1[127:112] >SRC2[127:112] THEN
DEST[127:112] SRC1[127:112];
ELSE
DEST[127:112] SRC2[127:112]; FI;
DEST[MAX_VL-1:128] 0
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers
Vol. 2B 4-313
INSTRUCTION SET REFERENCE, M-U
VPMAXUW (VEX.256 encoded version)
IF SRC1[15:0] > SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 15th words in source and destination operands *)
IF SRC1[255:240] >SRC2[255:240] THEN
DEST[255:240] SRC1[255:240];
ELSE
DEST[255:240] SRC2[255:240]; FI;
DEST[MAX_VL-1:128] 0
VPMAXUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask* THEN
IF SRC1[i+15:i] > SRC2[i+15:i]
THEN DEST[i+15:i] SRC1[i+15:i];
ELSE DEST[i+15:i] SRC2[i+15:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMAXUB __m512i _mm512_max_epu8( __m512i a, __m512i b);
VPMAXUB __m512i _mm512_mask_max_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMAXUB __m512i _mm512_maskz_max_epu8( __mmask64 k, __m512i a, __m512i b);
VPMAXUW __m512i _mm512_max_epu16( __m512i a, __m512i b);
VPMAXUW __m512i _mm512_mask_max_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMAXUW __m512i _mm512_maskz_max_epu16( __mmask32 k, __m512i a, __m512i b);
VPMAXUB __m256i _mm256_mask_max_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMAXUB __m256i _mm256_maskz_max_epu8( __mmask32 k, __m256i a, __m256i b);
VPMAXUW __m256i _mm256_mask_max_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMAXUW __m256i _mm256_maskz_max_epu16( __mmask16 k, __m256i a, __m256i b);
VPMAXUB __m128i _mm_mask_max_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMAXUB __m128i _mm_maskz_max_epu8( __mmask16 k, __m128i a, __m128i b);
VPMAXUW __m128i _mm_mask_max_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUW __m128i _mm_maskz_max_epu16( __mmask8 k, __m128i a, __m128i b);
(V)PMAXUB __m128i _mm_max_epu8 ( __m128i a, __m128i b);
(V)PMAXUW __m128i _mm_max_epu16 ( __m128i a, __m128i b)
VPMAXUB __m256i _mm256_max_epu8 ( __m256i a, __m256i b);
VPMAXUW __m256i _mm256_max_epu16 ( __m256i a, __m256i b);
PMAXUB: __m64 _mm_max_pu8(__m64 a, __m64 b);
4-314 Vol. 2B
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers
Vol. 2B 4-315
INSTRUCTION SET REFERENCE, M-U
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers
Opcode/
Instruction
Op/
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0F 38 3F /r
PMAXUD xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 3F /r
VPMAXUD xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F38.WIG 3F /r
VPMAXUD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.W0 3F /r
VPMAXUD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 3F /r
VPMAXUD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 3F /r
VPMAXUD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 3F /r
VPMAXUQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 3F /r
VPMAXUQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 3F /r
VPMAXUQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Compare packed unsigned dword integers in xmm1
and xmm2/m128 and store packed maximum values in
xmm1.
Compare packed unsigned dword integers in xmm2
and xmm3/m128 and store packed maximum values in
xmm1.
Compare packed unsigned dword integers in ymm2
and ymm3/m256 and store packed maximum values in
ymm1.
Compare packed unsigned dword integers in xmm2
and xmm3/m128/m32bcst and store packed
maximum values in xmm1 under writemask k1.
Compare packed unsigned dword integers in ymm2
and ymm3/m256/m32bcst and store packed
maximum values in ymm1 under writemask k1.
Compare packed unsigned dword integers in zmm2
and zmm3/m512/m32bcst and store packed maximum
values in zmm1 under writemask k1.
Compare packed unsigned qword integers in xmm2
and xmm3/m128/m64bcst and store packed
maximum values in xmm1 under writemask k1.
Compare packed unsigned qword integers in ymm2
and ymm3/m256/m64bcst and store packed
maximum values in ymm1 under writemask k1.
Compare packed unsigned qword integers in zmm2
and zmm3/m512/m64bcst and store packed maximum
values in zmm1 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed unsigned dword or qword integers in the second source operand and the
first source operand and returns the maximum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register
or 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
4-316 Vol. 2B
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
Operation
PMAXUD (128-bit Legacy SSE version)
IF DEST[31:0] >SRC[31:0] THEN
DEST[31:0] DEST[31:0];
ELSE
DEST[31:0] SRC[31:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:96] >SRC[127:96] THEN
DEST[127:96] DEST[127:96];
ELSE
DEST[127:96] SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMAXUD (VEX.128 encoded version)
IF SRC1[31:0] > SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
IF SRC1[127:96] > SRC2[127:96] THEN
DEST[127:96] SRC1[127:96];
ELSE
DEST[127:96] SRC2[127:96]; FI;
DEST[MAX_VL-1:128] 0
VPMAXUD (VEX.256 encoded version)
IF SRC1[31:0] > SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 7th dwords in source and destination operands *)
IF SRC1[255:224] > SRC2[255:224] THEN
DEST[255:224] SRC1[255:224];
ELSE
DEST[255:224] SRC2[255:224]; FI;
DEST[MAX_VL-1:256] 0
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers
Vol. 2B 4-317
INSTRUCTION SET REFERENCE, M-U
VPMAXUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+31:i] > SRC2[31:0]
THEN DEST[i+31:i] SRC1[i+31:i];
ELSE DEST[i+31:i] SRC2[31:0];
FI;
ELSE
IF SRC1[i+31:i] > SRC2[i+31:i]
THEN DEST[i+31:i] SRC1[i+31:i];
ELSE DEST[i+31:i] SRC2[i+31:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPMAXUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+63:i] > SRC2[63:0]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[63:0];
FI;
ELSE
IF SRC1[i+31:i] > SRC2[i+31:i]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[i+63:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
4-318 Vol. 2B
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VPMAXUD __m512i _mm512_max_epu32( __m512i a, __m512i b);
VPMAXUD __m512i _mm512_mask_max_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMAXUD __m512i _mm512_maskz_max_epu32( __mmask16 k, __m512i a, __m512i b);
VPMAXUQ __m512i _mm512_max_epu64( __m512i a, __m512i b);
VPMAXUQ __m512i _mm512_mask_max_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMAXUQ __m512i _mm512_maskz_max_epu64( __mmask8 k, __m512i a, __m512i b);
VPMAXUD __m256i _mm256_mask_max_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMAXUD __m256i _mm256_maskz_max_epu32( __mmask16 k, __m256i a, __m256i b);
VPMAXUQ __m256i _mm256_mask_max_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMAXUQ __m256i _mm256_maskz_max_epu64( __mmask8 k, __m256i a, __m256i b);
VPMAXUD __m128i _mm_mask_max_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUD __m128i _mm_maskz_max_epu32( __mmask8 k, __m128i a, __m128i b);
VPMAXUQ __m128i _mm_mask_max_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);
(V)PMAXUD __m128i _mm_max_epu32 ( __m128i a, __m128i b);
VPMAXUD __m256i _mm256_max_epu32 ( __m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers
Vol. 2B 4-319
INSTRUCTION SET REFERENCE, M-U
PMINSB/PMINSW—Minimum of Packed Signed Integers
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F EA /r1
PMINSW mm1, mm2/m64
66 0F 38 38 /r
PMINSB xmm1, xmm2/m128
RM
V/V
SSE4_1
RM
V/V
SSE2
RVM
V/V
AVX
VEX.NDS.128.66.0F EA /r
VPMINSW xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F38 38 /r
VPMINSB ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
VEX.NDS.256.66.0F EA /r
VPMINSW ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.WIG 38 /r
VPMINSB xmm1{k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.WIG 38 /r
VPMINSB ymm1{k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.WIG 38 /r
VPMINSB zmm1{k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F.WIG EA /r
VPMINSW xmm1{k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F.WIG EA /r
VPMINSW ymm1{k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F.WIG EA /r
VPMINSW zmm1{k1}{z}, zmm2,
zmm3/m512
NOTES:
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
66 0F EA /r
PMINSW xmm1, xmm2/m128
VEX.NDS.128.66.0F38 38 /r
VPMINSB xmm1, xmm2, xmm3/m128
Description
Compare signed word integers in mm2/m64 and mm1
and return minimum values.
Compare packed signed byte integers in xmm1 and
xmm2/m128 and store packed minimum values in
xmm1.
Compare packed signed word integers in xmm2/m128
and xmm1 and store packed minimum values in xmm1.
Compare packed signed byte integers in xmm2 and
xmm3/m128 and store packed minimum values in
xmm1.
Compare packed signed word integers in xmm3/m128
and xmm2 and return packed minimum values in
xmm1.
Compare packed signed byte integers in ymm2 and
ymm3/m256 and store packed minimum values in
ymm1.
Compare packed signed word integers in ymm3/m256
and ymm2 and return packed minimum values in
ymm1.
Compare packed signed byte integers in xmm2 and
xmm3/m128 and store packed minimum values in
xmm1 under writemask k1.
Compare packed signed byte integers in ymm2 and
ymm3/m256 and store packed minimum values in
ymm1 under writemask k1.
Compare packed signed byte integers in zmm2 and
zmm3/m512 and store packed minimum values in
zmm1 under writemask k1.
Compare packed signed word integers in xmm2 and
xmm3/m128 and store packed minimum values in
xmm1 under writemask k1.
Compare packed signed word integers in ymm2 and
ymm3/m256 and store packed minimum values in
ymm1 under writemask k1.
Compare packed signed word integers in zmm2 and
zmm3/m512 and store packed minimum values in
zmm1 under writemask k1.
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
4-320 Vol. 2B
PMINSB/PMINSW—Minimum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
Description
Performs a SIMD compare of the packed signed byte, word, or dword integers in the second source operand and
the first source operand and returns the minimum value for each pair of integers to the destination operand.
Legacy SSE version PMINSW: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.
Operation
PMINSW (64-bit operands)
IF DEST[15:0] < SRC[15:0] THEN
DEST[15:0] ← DEST[15:0];
ELSE
DEST[15:0] ← SRC[15:0]; FI;
(* Repeat operation for 2nd and 3rd words in source and destination operands *)
IF DEST[63:48] < SRC[63:48] THEN
DEST[63:48] ← DEST[63:48];
ELSE
DEST[63:48] ← SRC[63:48]; FI;
PMINSB (128-bit Legacy SSE version)
IF DEST[7:0] < SRC[7:0] THEN
DEST[7:0] DEST[7:0];
ELSE
DEST[15:0] SRC[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF DEST[127:120] < SRC[127:120] THEN
DEST[127:120] DEST[127:120];
ELSE
DEST[127:120] SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMINSB (VEX.128 encoded version)
IF SRC1[7:0] < SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[7:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF SRC1[127:120] < SRC2[127:120] THEN
DEST[127:120] SRC1[127:120];
ELSE
DEST[127:120] SRC2[127:120]; FI;
DEST[MAX_VL-1:128] 0
PMINSB/PMINSW—Minimum of Packed Signed Integers
Vol. 2B 4-321
INSTRUCTION SET REFERENCE, M-U
VPMINSB (VEX.256 encoded version)
IF SRC1[7:0] < SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[15:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 31st bytes in source and destination operands *)
IF SRC1[255:248] < SRC2[255:248] THEN
DEST[255:248] SRC1[255:248];
ELSE
DEST[255:248] SRC2[255:248]; FI;
DEST[MAX_VL-1:256] 0
VPMINSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask* THEN
IF SRC1[i+7:i] < SRC2[i+7:i]
THEN DEST[i+7:i] SRC1[i+7:i];
ELSE DEST[i+7:i] SRC2[i+7:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PMINSW (128-bit Legacy SSE version)
IF DEST[15:0] < SRC[15:0] THEN
DEST[15:0] DEST[15:0];
ELSE
DEST[15:0] SRC[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:112] < SRC[127:112] THEN
DEST[127:112] DEST[127:112];
ELSE
DEST[127:112] SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMINSW (VEX.128 encoded version)
IF SRC1[15:0] < SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF SRC1[127:112] < SRC2[127:112] THEN
DEST[127:112] SRC1[127:112];
ELSE
DEST[127:112] SRC2[127:112]; FI;
DEST[MAX_VL-1:128] 0
4-322 Vol. 2B
PMINSB/PMINSW—Minimum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
VPMINSW (VEX.256 encoded version)
IF SRC1[15:0] < SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 15th words in source and destination operands *)
IF SRC1[255:240] < SRC2[255:240] THEN
DEST[255:240] SRC1[255:240];
ELSE
DEST[255:240] SRC2[255:240]; FI;
DEST[MAX_VL-1:256] 0
VPMINSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask* THEN
IF SRC1[i+15:i] < SRC2[i+15:i]
THEN DEST[i+15:i] SRC1[i+15:i];
ELSE DEST[i+15:i] SRC2[i+15:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMINSB __m512i _mm512_min_epi8( __m512i a, __m512i b);
VPMINSB __m512i _mm512_mask_min_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMINSB __m512i _mm512_maskz_min_epi8( __mmask64 k, __m512i a, __m512i b);
VPMINSW __m512i _mm512_min_epi16( __m512i a, __m512i b);
VPMINSW __m512i _mm512_mask_min_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMINSW __m512i _mm512_maskz_min_epi16( __mmask32 k, __m512i a, __m512i b);
VPMINSB __m256i _mm256_mask_min_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMINSB __m256i _mm256_maskz_min_epi8( __mmask32 k, __m256i a, __m256i b);
VPMINSW __m256i _mm256_mask_min_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINSW __m256i _mm256_maskz_min_epi16( __mmask16 k, __m256i a, __m256i b);
VPMINSB __m128i _mm_mask_min_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMINSB __m128i _mm_maskz_min_epi8( __mmask16 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_mask_min_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_maskz_min_epi16( __mmask8 k, __m128i a, __m128i b);
(V)PMINSB __m128i _mm_min_epi8 ( __m128i a, __m128i b);
(V)PMINSW __m128i _mm_min_epi16 ( __m128i a, __m128i b)
VPMINSB __m256i _mm256_min_epi8 ( __m256i a, __m256i b);
VPMINSW __m256i _mm256_min_epi16 ( __m256i a, __m256i b)
PMINSW:__m64 _mm_min_pi16 (__m64 a, __m64 b)
PMINSB/PMINSW—Minimum of Packed Signed Integers
Vol. 2B 4-323
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
#MF
4-324 Vol. 2B
(64-bit operations only) If there is a pending x87 FPU exception.
PMINSB/PMINSW—Minimum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
PMINSD/PMINSQ—Minimum of Packed Signed Integers
Opcode/
Instruction
Op/
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0F 38 39 /r
PMINSD xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 39 /r
VPMINSD xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F38.WIG 39 /r
VPMINSD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.W0 39 /r
VPMINSD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 39 /r
VPMINSD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 39 /r
VPMINSD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 39 /r
VPMINSQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 39 /r
VPMINSQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 39 /r
VPMINSQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Compare packed signed dword integers in xmm1 and
xmm2/m128 and store packed minimum values in
xmm1.
Compare packed signed dword integers in xmm2 and
xmm3/m128 and store packed minimum values in
xmm1.
Compare packed signed dword integers in ymm2 and
ymm3/m128 and store packed minimum values in
ymm1.
Compare packed signed dword integers in xmm2 and
xmm3/m128 and store packed minimum values in
xmm1 under writemask k1.
Compare packed signed dword integers in ymm2 and
ymm3/m256 and store packed minimum values in
ymm1 under writemask k1.
Compare packed signed dword integers in zmm2 and
zmm3/m512/m32bcst and store packed minimum
values in zmm1 under writemask k1.
Compare packed signed qword integers in xmm2 and
xmm3/m128 and store packed minimum values in
xmm1 under writemask k1.
Compare packed signed qword integers in ymm2 and
ymm3/m256 and store packed minimum values in
ymm1 under writemask k1.
Compare packed signed qword integers in zmm2 and
zmm3/m512/m64bcst and store packed minimum
values in zmm1 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed signed dword or qword integers in the second source operand and the first
source operand and returns the minimum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination
register are zeroed.
PMINSD/PMINSQ—Minimum of Packed Signed Integers
Vol. 2B 4-325
INSTRUCTION SET REFERENCE, M-U
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
Operation
PMINSD (128-bit Legacy SSE version)
IF DEST[31:0] < SRC[31:0] THEN
DEST[31:0] DEST[31:0];
ELSE
DEST[31:0] SRC[31:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:96] < SRC[127:96] THEN
DEST[127:96] DEST[127:96];
ELSE
DEST[127:96] SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMINSD (VEX.128 encoded version)
IF SRC1[31:0] < SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
IF SRC1[127:96] < SRC2[127:96] THEN
DEST[127:96] SRC1[127:96];
ELSE
DEST[127:96] SRC2[127:96]; FI;
DEST[MAX_VL-1:128] 0
VPMINSD (VEX.256 encoded version)
IF SRC1[31:0] < SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 7th dwords in source and destination operands *)
IF SRC1[255:224] < SRC2[255:224] THEN
DEST[255:224] SRC1[255:224];
ELSE
DEST[255:224] SRC2[255:224]; FI;
DEST[MAX_VL-1:256] 0
4-326 Vol. 2B
PMINSD/PMINSQ—Minimum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
VPMINSD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+31:i] < SRC2[31:0]
THEN DEST[i+31:i] SRC1[i+31:i];
ELSE DEST[i+31:i] SRC2[31:0];
FI;
ELSE
IF SRC1[i+31:i] < SRC2[i+31:i]
THEN DEST[i+31:i] SRC1[i+31:i];
ELSE DEST[i+31:i] SRC2[i+31:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPMINSQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+63:i] < SRC2[63:0]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[63:0];
FI;
ELSE
IF SRC1[i+63:i] < SRC2[i+63:i]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[i+63:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PMINSD/PMINSQ—Minimum of Packed Signed Integers
Vol. 2B 4-327
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VPMINSD __m512i _mm512_min_epi32( __m512i a, __m512i b);
VPMINSD __m512i _mm512_mask_min_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMINSD __m512i _mm512_maskz_min_epi32( __mmask16 k, __m512i a, __m512i b);
VPMINSQ __m512i _mm512_min_epi64( __m512i a, __m512i b);
VPMINSQ __m512i _mm512_mask_min_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMINSQ __m512i _mm512_maskz_min_epi64( __mmask8 k, __m512i a, __m512i b);
VPMINSD __m256i _mm256_mask_min_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINSD __m256i _mm256_maskz_min_epi32( __mmask16 k, __m256i a, __m256i b);
VPMINSQ __m256i _mm256_mask_min_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMINSQ __m256i _mm256_maskz_min_epi64( __mmask8 k, __m256i a, __m256i b);
VPMINSD __m128i _mm_mask_min_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSD __m128i _mm_maskz_min_epi32( __mmask8 k, __m128i a, __m128i b);
VPMINSQ __m128i _mm_mask_min_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);
(V)PMINSD __m128i _mm_min_epi32 ( __m128i a, __m128i b);
VPMINSD __m256i _mm256_min_epi32 (__m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
4-328 Vol. 2B
PMINSD/PMINSQ—Minimum of Packed Signed Integers
INSTRUCTION SET REFERENCE, M-U
PMINUB/PMINUW—Minimum of Packed Unsigned Integers
Opcode/
Instruction
Op /
En
CPUID
Feature
Flag
SSE
Description
RM
64/32
bit Mode
Support
V/V
0F DA /r1
PMINUB mm1, mm2/m64
66 0F DA /r
PMINUB xmm1, xmm2/m128
RM
V/V
SSE2
66 0F 38 3A/r
PMINUW xmm1, xmm2/m128
RM
V/V
SSE4_1
VEX.NDS.128.66.0F DA /r
VPMINUB xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.128.66.0F38 3A/r
VPMINUW xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F DA /r
VPMINUB ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
VEX.NDS.256.66.0F38 3A/r
VPMINUW ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F DA /r
VPMINUB xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F DA /r
VPMINUB ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F DA /r
VPMINUB zmm1 {k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38 3A/r
VPMINUW xmm1{k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38 3A/r
VPMINUW ymm1{k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38 3A/r
VPMINUW zmm1{k1}{z}, zmm2,
zmm3/m512
NOTES:
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
Compare packed unsigned byte integers in xmm1
and xmm2/m128 and store packed minimum values
in xmm1.
Compare packed unsigned word integers in
xmm2/m128 and xmm1 and store packed minimum
values in xmm1.
Compare packed unsigned byte integers in xmm2
and xmm3/m128 and store packed minimum values
in xmm1.
Compare packed unsigned word integers in
xmm3/m128 and xmm2 and return packed
minimum values in xmm1.
Compare packed unsigned byte integers in ymm2
and ymm3/m256 and store packed minimum values
in ymm1.
Compare packed unsigned word integers in
ymm3/m256 and ymm2 and return packed
minimum values in ymm1.
Compare packed unsigned byte integers in xmm2
and xmm3/m128 and store packed minimum values
in xmm1 under writemask k1.
Compare packed unsigned byte integers in ymm2
and ymm3/m256 and store packed minimum values
in ymm1 under writemask k1.
Compare packed unsigned byte integers in zmm2
and zmm3/m512 and store packed minimum values
in zmm1 under writemask k1.
Compare packed unsigned word integers in
xmm3/m128 and xmm2 and return packed
minimum values in xmm1 under writemask k1.
Compare packed unsigned word integers in
ymm3/m256 and ymm2 and return packed
minimum values in ymm1 under writemask k1.
Compare packed unsigned word integers in
zmm3/m512 and zmm2 and return packed
minimum values in zmm1 under writemask k1.
Compare unsigned byte integers in mm2/m64 and
mm1 and returns minimum values.
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
PMINUB/PMINUW—Minimum of Packed Unsigned Integers
Vol. 2B 4-329
INSTRUCTION SET REFERENCE, M-U
Description
Performs a SIMD compare of the packed unsigned byte or word integers in the second source operand and the first
source operand and returns the minimum value for each pair of integers to the destination operand.
Legacy SSE version PMINUB: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.
Operation
PMINUB (for 64-bit operands)
IF DEST[7:0] < SRC[17:0] THEN
DEST[7:0] ← DEST[7:0];
ELSE
DEST[7:0] ← SRC[7:0]; FI;
(* Repeat operation for 2nd through 7th bytes in source and destination operands *)
IF DEST[63:56] < SRC[63:56] THEN
DEST[63:56] ← DEST[63:56];
ELSE
DEST[63:56] ← SRC[63:56]; FI;
PMINUB instruction for 128-bit operands:
IF DEST[7:0] < SRC[7:0] THEN
DEST[7:0] DEST[7:0];
ELSE
DEST[15:0] SRC[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF DEST[127:120] < SRC[127:120] THEN
DEST[127:120] DEST[127:120];
ELSE
DEST[127:120] SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMINUB (VEX.128 encoded version)
IF SRC1[7:0] < SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[7:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF SRC1[127:120] < SRC2[127:120] THEN
DEST[127:120] SRC1[127:120];
ELSE
DEST[127:120] SRC2[127:120]; FI;
DEST[MAX_VL-1:128] 0
4-330 Vol. 2B
PMINUB/PMINUW—Minimum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
VPMINUB (VEX.256 encoded version)
IF SRC1[7:0] < SRC2[7:0] THEN
DEST[7:0] SRC1[7:0];
ELSE
DEST[15:0] SRC2[7:0]; FI;
(* Repeat operation for 2nd through 31st bytes in source and destination operands *)
IF SRC1[255:248] < SRC2[255:248] THEN
DEST[255:248] SRC1[255:248];
ELSE
DEST[255:248] SRC2[255:248]; FI;
DEST[MAX_VL-1:256] 0
VPMINUB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask* THEN
IF SRC1[i+7:i] < SRC2[i+7:i]
THEN DEST[i+7:i] SRC1[i+7:i];
ELSE DEST[i+7:i] SRC2[i+7:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PMINUW instruction for 128-bit operands:
IF DEST[15:0] < SRC[15:0] THEN
DEST[15:0] DEST[15:0];
ELSE
DEST[15:0] SRC[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:112] < SRC[127:112] THEN
DEST[127:112] DEST[127:112];
ELSE
DEST[127:112] SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMINUW (VEX.128 encoded version)
IF SRC1[15:0] < SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF SRC1[127:112] < SRC2[127:112] THEN
DEST[127:112] SRC1[127:112];
ELSE
DEST[127:112] SRC2[127:112]; FI;
DEST[MAX_VL-1:128] 0
PMINUB/PMINUW—Minimum of Packed Unsigned Integers
Vol. 2B 4-331
INSTRUCTION SET REFERENCE, M-U
VPMINUW (VEX.256 encoded version)
IF SRC1[15:0] < SRC2[15:0] THEN
DEST[15:0] SRC1[15:0];
ELSE
DEST[15:0] SRC2[15:0]; FI;
(* Repeat operation for 2nd through 15th words in source and destination operands *)
IF SRC1[255:240] < SRC2[255:240] THEN
DEST[255:240] SRC1[255:240];
ELSE
DEST[255:240] SRC2[255:240]; FI;
DEST[MAX_VL-1:256] 0
VPMINUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask* THEN
IF SRC1[i+15:i] < SRC2[i+15:i]
THEN DEST[i+15:i] SRC1[i+15:i];
ELSE DEST[i+15:i] SRC2[i+15:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMINUB __m512i _mm512_min_epu8( __m512i a, __m512i b);
VPMINUB __m512i _mm512_mask_min_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMINUB __m512i _mm512_maskz_min_epu8( __mmask64 k, __m512i a, __m512i b);
VPMINUW __m512i _mm512_min_epu16( __m512i a, __m512i b);
VPMINUW __m512i _mm512_mask_min_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMINUW __m512i _mm512_maskz_min_epu16( __mmask32 k, __m512i a, __m512i b);
VPMINUB __m256i _mm256_mask_min_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMINUB __m256i _mm256_maskz_min_epu8( __mmask32 k, __m256i a, __m256i b);
VPMINUW __m256i _mm256_mask_min_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINUW __m256i _mm256_maskz_min_epu16( __mmask16 k, __m256i a, __m256i b);
VPMINUB __m128i _mm_mask_min_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMINUB __m128i _mm_maskz_min_epu8( __mmask16 k, __m128i a, __m128i b);
VPMINUW __m128i _mm_mask_min_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUW __m128i _mm_maskz_min_epu16( __mmask8 k, __m128i a, __m128i b);
(V)PMINUB __m128i _mm_min_epu8 ( __m128i a, __m128i b)
(V)PMINUW __m128i _mm_min_epu16 ( __m128i a, __m128i b);
VPMINUB __m256i _mm256_min_epu8 ( __m256i a, __m256i b)
VPMINUW __m256i _mm256_min_epu16 ( __m256i a, __m256i b);
PMINUB: __m64 _m_min_pu8 (__m64 a, __m64 b)
4-332 Vol. 2B
PMINUB/PMINUW—Minimum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
PMINUB/PMINUW—Minimum of Packed Unsigned Integers
Vol. 2B 4-333
INSTRUCTION SET REFERENCE, M-U
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers
Opcode/
Instruction
Op/
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0F 38 3B /r
PMINUD xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 3B /r
VPMINUD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.WIG 3B /r
VPMINUD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W0 3B /r
VPMINUD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 3B /r
VPMINUD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 3B /r
VPMINUD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 3B /r
VPMINUQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 3B /r
VPMINUQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 3B /r
VPMINUQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
RVM
V/V
AVX
RVM
V/V
AVX2
Compare packed unsigned dword integers in ymm2 and
ymm3/m256 and store packed minimum values in ymm1.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Compare packed unsigned dword integers in xmm2 and
xmm3/m128/m32bcst and store packed minimum values
in xmm1 under writemask k1.
Compare packed unsigned dword integers in ymm2 and
ymm3/m256/m32bcst and store packed minimum values
in ymm1 under writemask k1.
Compare packed unsigned dword integers in zmm2 and
zmm3/m512/m32bcst and store packed minimum values
in zmm1 under writemask k1.
Compare packed unsigned qword integers in xmm2 and
xmm3/m128/m64bcst and store packed minimum values
in xmm1 under writemask k1.
Compare packed unsigned qword integers in ymm2 and
ymm3/m256/m64bcst and store packed minimum values
in ymm1 under writemask k1.
Compare packed unsigned qword integers in zmm2 and
zmm3/m512/m64bcst and store packed minimum values
in zmm1 under writemask k1.
Description
Compare packed unsigned dword integers in xmm1 and
xmm2/m128 and store packed minimum values in xmm1.
Compare packed unsigned dword integers in xmm2 and
xmm3/m128 and store packed minimum values in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed unsigned dword/qword integers in the second source operand and the first
source operand and returns the minimum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination
register are zeroed.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
4-334 Vol. 2B
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
Operation
PMINUD (128-bit Legacy SSE version)
PMINUD instruction for 128-bit operands:
IF DEST[31:0] < SRC[31:0] THEN
DEST[31:0] DEST[31:0];
ELSE
DEST[31:0] SRC[31:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)
IF DEST[127:96] < SRC[127:96] THEN
DEST[127:96] DEST[127:96];
ELSE
DEST[127:96] SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)
VPMINUD (VEX.128 encoded version)
VPMINUD instruction for 128-bit operands:
IF SRC1[31:0] < SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
IF SRC1[127:96] < SRC2[127:96] THEN
DEST[127:96] SRC1[127:96];
ELSE
DEST[127:96] SRC2[127:96]; FI;
DEST[MAX_VL-1:128] 0
VPMINUD (VEX.256 encoded version)
VPMINUD instruction for 128-bit operands:
IF SRC1[31:0] < SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 7th dwords in source and destination operands *)
IF SRC1[255:224] < SRC2[255:224] THEN
DEST[255:224] SRC1[255:224];
ELSE
DEST[255:224] SRC2[255:224]; FI;
DEST[MAX_VL-1:256] 0
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers
Vol. 2B 4-335
INSTRUCTION SET REFERENCE, M-U
VPMINUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+31:i] < SRC2[31:0]
THEN DEST[i+31:i] SRC1[i+31:i];
ELSE DEST[i+31:i] SRC2[31:0];
FI;
ELSE
IF SRC1[i+31:i] < SRC2[i+31:i]
THEN DEST[i+31:i] SRC1[i+31:i];
ELSE DEST[i+31:i] SRC2[i+31:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPMINUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
IF SRC1[i+63:i] < SRC2[63:0]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[63:0];
FI;
ELSE
IF SRC1[i+63:i] < SRC2[i+63:i]
THEN DEST[i+63:i] SRC1[i+63:i];
ELSE DEST[i+63:i] SRC2[i+63:i];
FI;
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
4-336 Vol. 2B
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VPMINUD __m512i _mm512_min_epu32( __m512i a, __m512i b);
VPMINUD __m512i _mm512_mask_min_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMINUD __m512i _mm512_maskz_min_epu32( __mmask16 k, __m512i a, __m512i b);
VPMINUQ __m512i _mm512_min_epu64( __m512i a, __m512i b);
VPMINUQ __m512i _mm512_mask_min_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMINUQ __m512i _mm512_maskz_min_epu64( __mmask8 k, __m512i a, __m512i b);
VPMINUD __m256i _mm256_mask_min_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINUD __m256i _mm256_maskz_min_epu32( __mmask16 k, __m256i a, __m256i b);
VPMINUQ __m256i _mm256_mask_min_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMINUQ __m256i _mm256_maskz_min_epu64( __mmask8 k, __m256i a, __m256i b);
VPMINUD __m128i _mm_mask_min_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUD __m128i _mm_maskz_min_epu32( __mmask8 k, __m128i a, __m128i b);
VPMINUQ __m128i _mm_mask_min_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);
(V)PMINUD __m128i _mm_min_epu32 ( __m128i a, __m128i b);
VPMINUD __m256i _mm256_min_epu32 ( __m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers
Vol. 2B 4-337
INSTRUCTION SET REFERENCE, M-U
PMOVMSKB—Move Byte Mask
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F D7 /r1
RM
V/V
SSE
Move a byte mask of mm to reg. The upper
bits of r32 or r64 are zeroed
RM
V/V
SSE2
Move a byte mask of xmm to reg. The upper
bits of r32 or r64 are zeroed
RM
V/V
AVX
Move a byte mask of xmm1 to reg. The upper
bits of r32 or r64 are filled with zeros.
RM
V/V
AVX2
Move a 32-bit mask of ymm1 to reg. The
upper bits of r64 are filled with zeros.
PMOVMSKB reg, mm
66 0F D7 /r
PMOVMSKB reg, xmm
VEX.128.66.0F.WIG D7 /r
VPMOVMSKB reg, xmm1
VEX.256.66.0F.WIG D7 /r
VPMOVMSKB reg, ymm1
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Creates a mask made up of the most significant bit of each byte of the source operand (second operand) and stores
the result in the low byte or word of the destination operand (first operand).
The byte mask is 8 bits for 64-bit source operand, 16 bits for 128-bit source operand and 32 bits for 256-bit source
operand. The destination operand is a general-purpose register.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R
prefix. The default operand size is 64-bit in 64-bit mode.
Legacy SSE version: The source operand is an MMX technology register.
128-bit Legacy SSE version: The source operand is an XMM register.
VEX.128 encoded version: The source operand is an XMM register.
VEX.256 encoded version: The source operand is a YMM register.
Note: VEX.vvvv is reserved and must be 1111b.
Operation
PMOVMSKB (with 64-bit source operand and r32)
r32[0] ← SRC[7];
r32[1] ← SRC[15];
(* Repeat operation for bytes 2 through 6 *)
r32[7] ← SRC[63];
r32[31:8] ← ZERO_FILL;
(V)PMOVMSKB (with 128-bit source operand and r32)
r32[0] ← SRC[7];
r32[1] ← SRC[15];
(* Repeat operation for bytes 2 through 14 *)
r32[15] ← SRC[127];
r32[31:16] ← ZERO_FILL;
4-338 Vol. 2B
PMOVMSKB—Move Byte Mask
INSTRUCTION SET REFERENCE, M-U
VPMOVMSKB (with 256-bit source operand and r32)
r32[0] SRC[7];
r32[1] SRC[15];
(* Repeat operation for bytes 3rd through 31*)
r32[31] SRC[255];
PMOVMSKB (with 64-bit source operand and r64)
r64[0] ← SRC[7];
r64[1] ← SRC[15];
(* Repeat operation for bytes 2 through 6 *)
r64[7] ← SRC[63];
r64[63:8] ← ZERO_FILL;
(V)PMOVMSKB (with 128-bit source operand and r64)
r64[0] ← SRC[7];
r64[1] ← SRC[15];
(* Repeat operation for bytes 2 through 14 *)
r64[15] ← SRC[127];
r64[63:16] ← ZERO_FILL;
VPMOVMSKB (with 256-bit source operand and r64)
r64[0] SRC[7];
r64[1] SRC[15];
(* Repeat operation for bytes 2 through 31*)
r64[31] SRC[255];
r64[63:32] ZERO_FILL;
Intel C/C++ Compiler Intrinsic Equivalent
PMOVMSKB:
int _mm_movemask_pi8(__m64 a)
(V)PMOVMSKB:
int _mm_movemask_epi8 ( __m128i a)
VPMOVMSKB:
int _mm256_movemask_epi8 ( __m256i a)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
See Exceptions Type 7; additionally
#UD
If VEX.vvvv ≠ 1111B.
PMOVMSKB—Move Byte Mask
Vol. 2B 4-339
INSTRUCTION SET REFERENCE, M-U
PMOVSX—Packed Move with Sign Extend
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0f 38 20 /r
PMOVSXBW xmm1, xmm2/m64
66 0f 38 21 /r
PMOVSXBD xmm1, xmm2/m32
66 0f 38 22 /r
PMOVSXBQ xmm1, xmm2/m16
66 0f 38 23/r
PMOVSXWD xmm1, xmm2/m64
66 0f 38 24 /r
PMOVSXWQ xmm1, xmm2/m32
66 0f 38 25 /r
PMOVSXDQ xmm1, xmm2/m64
VEX.128.66.0F38.WIG 20 /r
VPMOVSXBW xmm1, xmm2/m64
VEX.128.66.0F38.WIG 21 /r
VPMOVSXBD xmm1, xmm2/m32
VEX.128.66.0F38.WIG 22 /r
VPMOVSXBQ xmm1, xmm2/m16
VEX.128.66.0F38.WIG 23 /r
VPMOVSXWD xmm1, xmm2/m64
VEX.128.66.0F38.WIG 24 /r
VPMOVSXWQ xmm1, xmm2/m32
VEX.128.66.0F38.WIG 25 /r
VPMOVSXDQ xmm1, xmm2/m64
VEX.256.66.0F38.WIG 20 /r
VPMOVSXBW ymm1, xmm2/m128
VEX.256.66.0F38.WIG 21 /r
VPMOVSXBD ymm1, xmm2/m64
VEX.256.66.0F38.WIG 22 /r
VPMOVSXBQ ymm1, xmm2/m32
VEX.256.66.0F38.WIG 23 /r
VPMOVSXWD ymm1, xmm2/m128
RM
V/V
SSE4_1
RM
V/V
SSE4_1
RM
V/V
SSE4_1
RM
V/V
SSE4_1
RM
V/V
SSE4_1
RM
V/V
AVX
RM
V/V
AVX
RM
V/V
AVX
RM
V/V
AVX
RM
V/V
AVX
RM
V/V
AVX
RM
V/V
AVX2
RM
V/V
AVX2
RM
V/V
AVX2
RM
V/V
AVX2
VEX.256.66.0F38.WIG 24 /r
VPMOVSXWQ ymm1, xmm2/m64
VEX.256.66.0F38.WIG 25 /r
VPMOVSXDQ ymm1, xmm2/m128
RM
V/V
AVX2
RM
V/V
AVX2
EVEX.128.66.0F38.WIG 20 /r
VPMOVSXBW xmm1 {k1}{z},
xmm2/m64
EVEX.256.66.0F38.WIG 20 /r
VPMOVSXBW ymm1 {k1}{z},
xmm2/m128
EVEX.512.66.0F38.WIG 20 /r
VPMOVSXBW zmm1 {k1}{z},
ymm2/m256
EVEX.128.66.0F38.WIG 21 /r
VPMOVSXBD xmm1 {k1}{z},
xmm2/m32
HVM
V/V
AVX512VL
AVX512BW
Sign extend 8 packed 8-bit integers in the low 8 bytes
of xmm2/m64 to 8 packed 16-bit integers in xmm1.
Sign extend 4 packed 8-bit integers in the low 4 bytes
of xmm2/m32 to 4 packed 32-bit integers in xmm1.
Sign extend 2 packed 8-bit integers in the low 2 bytes
of xmm2/m16 to 2 packed 64-bit integers in xmm1.
Sign extend 4 packed 16-bit integers in the low 8 bytes
of xmm2/m64 to 4 packed 32-bit integers in xmm1.
Sign extend 2 packed 16-bit integers in the low 4 bytes
of xmm2/m32 to 2 packed 64-bit integers in xmm1.
Sign extend 2 packed 32-bit integers in the low 8 bytes
of xmm2/m64 to 2 packed 64-bit integers in xmm1.
Sign extend 8 packed 8-bit integers in the low 8 bytes
of xmm2/m64 to 8 packed 16-bit integers in xmm1.
Sign extend 4 packed 8-bit integers in the low 4 bytes
of xmm2/m32 to 4 packed 32-bit integers in xmm1.
Sign extend 2 packed 8-bit integers in the low 2 bytes
of xmm2/m16 to 2 packed 64-bit integers in xmm1.
Sign extend 4 packed 16-bit integers in the low 8 bytes
of xmm2/m64 to 4 packed 32-bit integers in xmm1.
Sign extend 2 packed 16-bit integers in the low 4 bytes
of xmm2/m32 to 2 packed 64-bit integers in xmm1.
Sign extend 2 packed 32-bit integers in the low 8 bytes
of xmm2/m64 to 2 packed 64-bit integers in xmm1.
Sign extend 16 packed 8-bit integers in xmm2/m128 to
16 packed 16-bit integers in ymm1.
Sign extend 8 packed 8-bit integers in the low 8 bytes
of xmm2/m64 to 8 packed 32-bit integers in ymm1.
Sign extend 4 packed 8-bit integers in the low 4 bytes
of xmm2/m32 to 4 packed 64-bit integers in ymm1.
Sign extend 8 packed 16-bit integers in the low 16
bytes of xmm2/m128 to 8 packed 32-bit integers in
ymm1.
Sign extend 4 packed 16-bit integers in the low 8 bytes
of xmm2/m64 to 4 packed 64-bit integers in ymm1.
Sign extend 4 packed 32-bit integers in the low 16
bytes of xmm2/m128 to 4 packed 64-bit integers in
ymm1.
Sign extend 8 packed 8-bit integers in xmm2/m64 to 8
packed 16-bit integers in zmm1.
HVM
V/V
AVX512VL
AVX512BW
Sign extend 16 packed 8-bit integers in xmm2/m128 to
16 packed 16-bit integers in ymm1.
HVM
V/V
AVX512BW
Sign extend 32 packed 8-bit integers in ymm2/m256 to
32 packed 16-bit integers in zmm1.
QVM
V/V
AVX512VL
AVX512F
Sign extend 4 packed 8-bit integers in the low 4 bytes
of xmm2/m32 to 4 packed 32-bit integers in xmm1
subject to writemask k1.
4-340 Vol. 2B
Description
PMOVSX—Packed Move with Sign Extend
INSTRUCTION SET REFERENCE, M-U
Opcode/
Instruction
Op /
En
EVEX.256.66.0F38.WIG 21 /r
VPMOVSXBD ymm1 {k1}{z},
xmm2/m64
EVEX.512.66.0F38.WIG 21 /r
VPMOVSXBD zmm1 {k1}{z},
xmm2/m128
EVEX.128.66.0F38.WIG 22 /r
VPMOVSXBQ xmm1 {k1}{z},
xmm2/m16
EVEX.256.66.0F38.WIG 22 /r
VPMOVSXBQ ymm1 {k1}{z},
xmm2/m32
EVEX.512.66.0F38.WIG 22 /r
VPMOVSXBQ zmm1 {k1}{z},
xmm2/m64
EVEX.128.66.0F38.WIG 23 /r
VPMOVSXWD xmm1 {k1}{z},
xmm2/m64
EVEX.256.66.0F38.WIG 23 /r
VPMOVSXWD ymm1 {k1}{z},
xmm2/m128
EVEX.512.66.0F38.WIG 23 /r
VPMOVSXWD zmm1 {k1}{z},
ymm2/m256
EVEX.128.66.0F38.WIG 24 /r
VPMOVSXWQ xmm1 {k1}{z},
xmm2/m32
EVEX.256.66.0F38.WIG 24 /r
VPMOVSXWQ ymm1 {k1}{z},
xmm2/m64
EVEX.512.66.0F38.WIG 24 /r
VPMOVSXWQ zmm1 {k1}{z},
xmm2/m128
EVEX.128.66.0F38.W0 25 /r
VPMOVSXDQ xmm1 {k1}{z},
xmm2/m64
EVEX.256.66.0F38.W0 25 /r
VPMOVSXDQ ymm1 {k1}{z},
xmm2/m128
EVEX.512.66.0F38.W0 25 /r
VPMOVSXDQ zmm1 {k1}{z},
ymm2/m256
PMOVSX—Packed Move with Sign Extend
QVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
QVM
V/V
AVX512F
OVM
V/V
AVX512VL
AVX512F
OVM
V/V
AVX512VL
AVX512F
OVM
V/V
AVX512F
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512F
QVM
V/V
AVX512VL
AVX512F
QVM
V/V
AVX512VL
AVX512F
QVM
V/V
AVX512F
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512F
Description
Sign extend 8 packed 8-bit integers in the low 8 bytes
of xmm2/m64 to 8 packed 32-bit integers in ymm1
subject to writemask k1.
Sign extend 16 packed 8-bit integers in the low 16
bytes of xmm2/m128 to 16 packed 32-bit integers in
zmm1 subject to writemask k1.
Sign extend 2 packed 8-bit integers in the low 2 bytes
of xmm2/m16 to 2 packed 64-bit integers in xmm1
subject to writemask k1.
Sign extend 4 packed 8-bit integers in the low 4 bytes
of xmm2/m32 to 4 packed 64-bit integers in ymm1
subject to writemask k1.
Sign extend 8 packed 8-bit integers in the low 8 bytes
of xmm2/m64 to 8 packed 64-bit integers in zmm1
subject to writemask k1.
Sign extend 4 packed 16-bit integers in the low 8 bytes
of ymm2/mem to 4 packed 32-bit integers in xmm1
subject to writemask k1.
Sign extend 8 packed 16-bit integers in the low 16
bytes of ymm2/m128 to 8 packed 32-bit integers in
ymm1 subject to writemask k1.
Sign extend 16 packed 16-bit integers in the low 32
bytes of ymm2/m256 to 16 packed 32-bit integers in
zmm1 subject to writemask k1.
Sign extend 2 packed 16-bit integers in the low 4 bytes
of xmm2/m32 to 2 packed 64-bit integers in xmm1
subject to writemask k1.
Sign extend 4 packed 16-bit integers in the low 8 bytes
of xmm2/m64 to 4 packed 64-bit integers in ymm1
subject to writemask k1.
Sign extend 8 packed 16-bit integers in the low 16
bytes of xmm2/m128 to 8 packed 64-bit integers in
zmm1 subject to writemask k1.
Sign extend 2 packed 32-bit integers in the low 8 bytes
of xmm2/m64 to 2 packed 64-bit integers in zmm1
using writemask k1.
Sign extend 4 packed 32-bit integers in the low 16
bytes of xmm2/m128 to 4 packed 64-bit integers in
zmm1 using writemask k1.
Sign extend 8 packed 32-bit integers in the low 32
bytes of ymm2/m256 to 8 packed 64-bit integers in
zmm1 using writemask k1.
Vol. 2B 4-341
INSTRUCTION SET REFERENCE, M-U
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
HVM, QVM, OVM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Legacy and VEX encoded versions: Packed byte, word, or dword integers in the low bytes of the source operand
(second operand) are sign extended to word, dword, or quadword integers and stored in packed signed bytes the
destination operand.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the corresponding destination register are
zeroed.
VEX.256 and EVEX.256 encoded versions: Bits (MAX_VL-1:256) of the corresponding destination register are
zeroed.
EVEX encoded versions: Packed byte, word or dword integers starting from the low bytes of the source operand
(second operand) are sign extended to word, dword or quadword integers and stored to the destination operand
under the writemask. The destination register is XMM, YMM or ZMM Register.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
4-342 Vol. 2B
PMOVSX—Packed Move with Sign Extend
INSTRUCTION SET REFERENCE, M-U
Operation
Packed_Sign_Extend_BYTE_to_WORD(DEST, SRC)
DEST[15:0] SignExtend(SRC[7:0]);
DEST[31:16] SignExtend(SRC[15:8]);
DEST[47:32] SignExtend(SRC[23:16]);
DEST[63:48] SignExtend(SRC[31:24]);
DEST[79:64] SignExtend(SRC[39:32]);
DEST[95:80] SignExtend(SRC[47:40]);
DEST[111:96] SignExtend(SRC[55:48]);
DEST[127:112] SignExtend(SRC[63:56]);
Packed_Sign_Extend_BYTE_to_DWORD(DEST, SRC)
DEST[31:0] SignExtend(SRC[7:0]);
DEST[63:32] SignExtend(SRC[15:8]);
DEST[95:64] SignExtend(SRC[23:16]);
DEST[127:96] SignExtend(SRC[31:24]);
Packed_Sign_Extend_BYTE_to_QWORD(DEST, SRC)
DEST[63:0] SignExtend(SRC[7:0]);
DEST[127:64] SignExtend(SRC[15:8]);
Packed_Sign_Extend_WORD_to_DWORD(DEST, SRC)
DEST[31:0] SignExtend(SRC[15:0]);
DEST[63:32] SignExtend(SRC[31:16]);
DEST[95:64] SignExtend(SRC[47:32]);
DEST[127:96] SignExtend(SRC[63:48]);
Packed_Sign_Extend_WORD_to_QWORD(DEST, SRC)
DEST[63:0] SignExtend(SRC[15:0]);
DEST[127:64] SignExtend(SRC[31:16]);
Packed_Sign_Extend_DWORD_to_QWORD(DEST, SRC)
DEST[63:0] SignExtend(SRC[31:0]);
DEST[127:64] SignExtend(SRC[63:32]);
VPMOVSXBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[383:256], SRC[191:128])
Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[511:384], SRC[255:192])
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TEMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
PMOVSX—Packed Move with Sign Extend
Vol. 2B 4-343
INSTRUCTION SET REFERENCE, M-U
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVSXBD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[383:256], SRC[95:64])
Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TEMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVSXBQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[127:0], SRC[15:0])
IF VL >= 256
Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[255:128], SRC[31:16])
FI;
IF VL >= 512
Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[383:256], SRC[47:32])
Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[511:384], SRC[63:48])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TEMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-344 Vol. 2B
PMOVSX—Packed Move with Sign Extend
INSTRUCTION SET REFERENCE, M-U
VPMOVSXWD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[383:256], SRC[191:128])
Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[511:384], SRC[256:192])
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TEMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVSXWQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[383:256], SRC[95:64])
Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TEMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PMOVSX—Packed Move with Sign Extend
Vol. 2B 4-345
INSTRUCTION SET REFERENCE, M-U
VPMOVSXDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[383:256], SRC[191:128])
Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[511:384], SRC[255:192])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TEMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVSXBW (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] 0
VPMOVSXBD (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] 0
VPMOVSXBQ (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])
Packed_Sign_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])
DEST[MAX_VL-1:256] 0
VPMOVSXWD (VEX.256 encoded version)
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] 0
VPMOVSXWQ (VEX.256 encoded version)
Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] 0
VPMOVSXDQ (VEX.256 encoded version)
Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] 0
4-346 Vol. 2B
PMOVSX—Packed Move with Sign Extend
INSTRUCTION SET REFERENCE, M-U
VPMOVSXBW (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_WORDDEST[127:0], SRC[127:0]()
DEST[MAX_VL-1:128] 0
VPMOVSXBD (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] 0
VPMOVSXBQ (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] 0
VPMOVSXWD (VEX.128 encoded version)
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] 0
VPMOVSXWQ (VEX.128 encoded version)
Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] 0
VPMOVSXDQ (VEX.128 encoded version)
Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] 0
PMOVSXBW
Packed_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
PMOVSXBD
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
PMOVSXBQ
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
PMOVSXWD
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
PMOVSXWQ
Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
PMOVSXDQ
Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VPMOVSXBW __m512i _mm512_cvtepi8_epi16(__m512i a);
VPMOVSXBW __m512i _mm512_mask_cvtepi8_epi16(__m512i a, __mmask32 k, __m512i b);
VPMOVSXBW __m512i _mm512_maskz_cvtepi8_epi16( __mmask32 k, __m512i b);
VPMOVSXBD __m512i _mm512_cvtepi8_epi32(__m512i a);
VPMOVSXBD __m512i _mm512_mask_cvtepi8_epi32(__m512i a, __mmask16 k, __m512i b);
PMOVSX—Packed Move with Sign Extend
Vol. 2B 4-347
INSTRUCTION SET REFERENCE, M-U
VPMOVSXBD __m512i _mm512_maskz_cvtepi8_epi32( __mmask16 k, __m512i b);
VPMOVSXBQ __m512i _mm512_cvtepi8_epi64(__m512i a);
VPMOVSXBQ __m512i _mm512_mask_cvtepi8_epi64(__m512i a, __mmask8 k, __m512i b);
VPMOVSXBQ __m512i _mm512_maskz_cvtepi8_epi64( __mmask8 k, __m512i a);
VPMOVSXDQ __m512i _mm512_cvtepi32_epi64(__m512i a);
VPMOVSXDQ __m512i _mm512_mask_cvtepi32_epi64(__m512i a, __mmask8 k, __m512i b);
VPMOVSXDQ __m512i _mm512_maskz_cvtepi32_epi64( __mmask8 k, __m512i a);
VPMOVSXWD __m512i _mm512_cvtepi16_epi32(__m512i a);
VPMOVSXWD __m512i _mm512_mask_cvtepi16_epi32(__m512i a, __mmask16 k, __m512i b);
VPMOVSXWD __m512i _mm512_maskz_cvtepi16_epi32(__mmask16 k, __m512i a);
VPMOVSXWQ __m512i _mm512_cvtepi16_epi64(__m512i a);
VPMOVSXWQ __m512i _mm512_mask_cvtepi16_epi64(__m512i a, __mmask8 k, __m512i b);
VPMOVSXWQ __m512i _mm512_maskz_cvtepi16_epi64( __mmask8 k, __m512i a);
VPMOVSXBW __m256i _mm256_cvtepi8_epi16(__m256i a);
VPMOVSXBW __m256i _mm256_mask_cvtepi8_epi16(__m256i a, __mmask16 k, __m256i b);
VPMOVSXBW __m256i _mm256_maskz_cvtepi8_epi16( __mmask16 k, __m256i b);
VPMOVSXBD __m256i _mm256_cvtepi8_epi32(__m256i a);
VPMOVSXBD __m256i _mm256_mask_cvtepi8_epi32(__m256i a, __mmask8 k, __m256i b);
VPMOVSXBD __m256i _mm256_maskz_cvtepi8_epi32( __mmask8 k, __m256i b);
VPMOVSXBQ __m256i _mm256_cvtepi8_epi64(__m256i a);
VPMOVSXBQ __m256i _mm256_mask_cvtepi8_epi64(__m256i a, __mmask8 k, __m256i b);
VPMOVSXBQ __m256i _mm256_maskz_cvtepi8_epi64( __mmask8 k, __m256i a);
VPMOVSXDQ __m256i _mm256_cvtepi32_epi64(__m256i a);
VPMOVSXDQ __m256i _mm256_mask_cvtepi32_epi64(__m256i a, __mmask8 k, __m256i b);
VPMOVSXDQ __m256i _mm256_maskz_cvtepi32_epi64( __mmask8 k, __m256i a);
VPMOVSXWD __m256i _mm256_cvtepi16_epi32(__m256i a);
VPMOVSXWD __m256i _mm256_mask_cvtepi16_epi32(__m256i a, __mmask16 k, __m256i b);
VPMOVSXWD __m256i _mm256_maskz_cvtepi16_epi32(__mmask16 k, __m256i a);
VPMOVSXWQ __m256i _mm256_cvtepi16_epi64(__m256i a);
VPMOVSXWQ __m256i _mm256_mask_cvtepi16_epi64(__m256i a, __mmask8 k, __m256i b);
VPMOVSXWQ __m256i _mm256_maskz_cvtepi16_epi64( __mmask8 k, __m256i a);
VPMOVSXBW __m128i _mm_mask_cvtepi8_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSXBW __m128i _mm_maskz_cvtepi8_epi16( __mmask8 k, __m128i b);
VPMOVSXBD __m128i _mm_mask_cvtepi8_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSXBD __m128i _mm_maskz_cvtepi8_epi32( __mmask8 k, __m128i b);
VPMOVSXBQ __m128i _mm_mask_cvtepi8_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVSXBQ __m128i _mm_maskz_cvtepi8_epi64( __mmask8 k, __m128i a);
VPMOVSXDQ __m128i _mm_mask_cvtepi32_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVSXDQ __m128i _mm_maskz_cvtepi32_epi64( __mmask8 k, __m128i a);
VPMOVSXWD __m128i _mm_mask_cvtepi16_epi32(__m128i a, __mmask16 k, __m128i b);
VPMOVSXWD __m128i _mm_maskz_cvtepi16_epi32(__mmask16 k, __m128i a);
VPMOVSXWQ __m128i _mm_mask_cvtepi16_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVSXWQ __m128i _mm_maskz_cvtepi16_epi64( __mmask8 k, __m128i a);
PMOVSXBW __m128i _mm_ cvtepi8_epi16 ( __m128i a);
PMOVSXBD __m128i _mm_ cvtepi8_epi32 ( __m128i a);
PMOVSXBQ __m128i _mm_ cvtepi8_epi64 ( __m128i a);
PMOVSXWD __m128i _mm_ cvtepi16_epi32 ( __m128i a);
PMOVSXWQ __m128i _mm_ cvtepi16_epi64 ( __m128i a);
PMOVSXDQ __m128i _mm_ cvtepi32_epi64 ( __m128i a);
SIMD Floating-Point Exceptions
None
4-348 Vol. 2B
PMOVSX—Packed Move with Sign Extend
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5.
EVEX-encoded instruction, see Exceptions Type E5.
#UD
If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.
PMOVSX—Packed Move with Sign Extend
Vol. 2B 4-349
INSTRUCTION SET REFERENCE, M-U
PMOVZX—Packed Move with Zero Extend
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0f 38 30 /r
PMOVZXBW xmm1, xmm2/m64
66 0f 38 31 /r
PMOVZXBD xmm1, xmm2/m32
RM
V/V
SSE4_1
66 0f 38 32 /r
PMOVZXBQ xmm1, xmm2/m16
RM
V/V
SSE4_1
66 0f 38 33 /r
PMOVZXWD xmm1, xmm2/m64
RM
V/V
SSE4_1
66 0f 38 34 /r
PMOVZXWQ xmm1, xmm2/m32
RM
V/V
SSE4_1
66 0f 38 35 /r
PMOVZXDQ xmm1, xmm2/m64
RM
V/V
SSE4_1
VEX.128.66.0F38.WIG 30 /r
VPMOVZXBW xmm1, xmm2/m64
RM
V/V
AVX
VEX.128.66.0F38.WIG 31 /r
VPMOVZXBD xmm1, xmm2/m32
RM
V/V
AVX
VEX.128.66.0F38.WIG 32 /r
VPMOVZXBQ xmm1, xmm2/m16
RM
V/V
AVX
VEX.128.66.0F38.WIG 33 /r
VPMOVZXWD xmm1, xmm2/m64
RM
V/V
AVX
VEX.128.66.0F38.WIG 34 /r
VPMOVZXWQ xmm1, xmm2/m32
RM
V/V
AVX
VEX.128.66.0F 38.WIG 35 /r
VPMOVZXDQ xmm1, xmm2/m64
RM
V/V
AVX
VEX.256.66.0F38.WIG 30 /r
VPMOVZXBW ymm1, xmm2/m128
VEX.256.66.0F38.WIG 31 /r
VPMOVZXBD ymm1, xmm2/m64
RM
V/V
AVX2
RM
V/V
AVX2
VEX.256.66.0F38.WIG 32 /r
VPMOVZXBQ ymm1, xmm2/m32
RM
V/V
AVX2
VEX.256.66.0F38.WIG 33 /r
VPMOVZXWD ymm1, xmm2/m128
VEX.256.66.0F38.WIG 34 /r
VPMOVZXWQ ymm1, xmm2/m64
RM
V/V
AVX2
RM
V/V
AVX2
RM
V/V
AVX2
VEX.256.66.0F38.WIG 35 /r
VPMOVZXDQ ymm1, xmm2/m128
4-350 Vol. 2B
Description
Zero extend 8 packed 8-bit integers in the low 8
bytes of xmm2/m64 to 8 packed 16-bit integers in
xmm1.
Zero extend 4 packed 8-bit integers in the low 4
bytes of xmm2/m32 to 4 packed 32-bit integers in
xmm1.
Zero extend 2 packed 8-bit integers in the low 2
bytes of xmm2/m16 to 2 packed 64-bit integers in
xmm1.
Zero extend 4 packed 16-bit integers in the low 8
bytes of xmm2/m64 to 4 packed 32-bit integers in
xmm1.
Zero extend 2 packed 16-bit integers in the low 4
bytes of xmm2/m32 to 2 packed 64-bit integers in
xmm1.
Zero extend 2 packed 32-bit integers in the low 8
bytes of xmm2/m64 to 2 packed 64-bit integers in
xmm1.
Zero extend 8 packed 8-bit integers in the low 8
bytes of xmm2/m64 to 8 packed 16-bit integers in
xmm1.
Zero extend 4 packed 8-bit integers in the low 4
bytes of xmm2/m32 to 4 packed 32-bit integers in
xmm1.
Zero extend 2 packed 8-bit integers in the low 2
bytes of xmm2/m16 to 2 packed 64-bit integers in
xmm1.
Zero extend 4 packed 16-bit integers in the low 8
bytes of xmm2/m64 to 4 packed 32-bit integers in
xmm1.
Zero extend 2 packed 16-bit integers in the low 4
bytes of xmm2/m32 to 2 packed 64-bit integers in
xmm1.
Zero extend 2 packed 32-bit integers in the low 8
bytes of xmm2/m64 to 2 packed 64-bit integers in
xmm1.
Zero extend 16 packed 8-bit integers in
xmm2/m128 to 16 packed 16-bit integers in ymm1.
Zero extend 8 packed 8-bit integers in the low 8
bytes of xmm2/m64 to 8 packed 32-bit integers in
ymm1.
Zero extend 4 packed 8-bit integers in the low 4
bytes of xmm2/m32 to 4 packed 64-bit integers in
ymm1.
Zero extend 8 packed 16-bit integers xmm2/m128
to 8 packed 32-bit integers in ymm1.
Zero extend 4 packed 16-bit integers in the low 8
bytes of xmm2/m64 to 4 packed 64-bit integers in
xmm1.
Zero extend 4 packed 32-bit integers in
xmm2/m128 to 4 packed 64-bit integers in ymm1.
PMOVZX—Packed Move with Zero Extend
INSTRUCTION SET REFERENCE, M-U
HVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
HVM
V/V
AVX512VL
AVX512BW
HVM
V/V
AVX512BW
Zero extend 32 packed 8-bit integers in
ymm2/m256 to 32 packed 16-bit integers in zmm1.
QVM
V/V
AVX512VL
AVX512F
EVEX.256.66.0F38.WIG 31 /r
VPMOVZXBD ymm1 {k1}{z}, xmm2/m64
QVM
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.WIG 31 /r
VPMOVZXBD zmm1 {k1}{z},
xmm2/m128
EVEX.128.66.0F38.WIG 32 /r
VPMOVZXBQ xmm1 {k1}{z}, xmm2/m16
QVM
V/V
AVX512F
OVM
V/V
AVX512VL
AVX512F
EVEX.256.66.0F38.WIG 32 /r
VPMOVZXBQ ymm1 {k1}{z}, xmm2/m32
OVM
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.WIG 32 /r
VPMOVZXBQ zmm1 {k1}{z}, xmm2/m64
OVM
V/V
AVX512F
EVEX.128.66.0F38.WIG 33 /r
VPMOVZXWD xmm1 {k1}{z}, xmm2/m64
HVM
V/V
AVX512VL
AVX512F
EVEX.256.66.0F38.WIG 33 /r
VPMOVZXWD ymm1 {k1}{z},
xmm2/m128
EVEX.512.66.0F38.WIG 33 /r
VPMOVZXWD zmm1 {k1}{z},
ymm2/m256
EVEX.128.66.0F38.WIG 34 /r
VPMOVZXWQ xmm1 {k1}{z}, xmm2/m32
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512F
QVM
V/V
AVX512VL
AVX512F
EVEX.256.66.0F38.WIG 34 /r
VPMOVZXWQ ymm1 {k1}{z}, xmm2/m64
QVM
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.WIG 34 /r
VPMOVZXWQ zmm1 {k1}{z},
xmm2/m128
QVM
V/V
AVX512F
Zero extend 4 packed 8-bit integers in the low 4
bytes of xmm2/m32 to 4 packed 32-bit integers in
xmm1 subject to writemask k1.
Zero extend 8 packed 8-bit integers in the low 8
bytes of xmm2/m64 to 8 packed 32-bit integers in
ymm1 subject to writemask k1.
Zero extend 16 packed 8-bit integers in
xmm2/m128 to 16 packed 32-bit integers in zmm1
subject to writemask k1.
Zero extend 2 packed 8-bit integers in the low 2
bytes of xmm2/m16 to 2 packed 64-bit integers in
xmm1 subject to writemask k1.
Zero extend 4 packed 8-bit integers in the low 4
bytes of xmm2/m32 to 4 packed 64-bit integers in
ymm1 subject to writemask k1.
Zero extend 8 packed 8-bit integers in the low 8
bytes of xmm2/m64 to 8 packed 64-bit integers in
zmm1 subject to writemask k1.
Zero extend 4 packed 16-bit integers in the low 8
bytes of xmm2/m64 to 4 packed 32-bit integers in
xmm1 subject to writemask k1.
Zero extend 8 packed 16-bit integers in
xmm2/m128 to 8 packed 32-bit integers in zmm1
subject to writemask k1.
Zero extend 16 packed 16-bit integers in
ymm2/m256 to 16 packed 32-bit integers in zmm1
subject to writemask k1.
Zero extend 2 packed 16-bit integers in the low 4
bytes of xmm2/m32 to 2 packed 64-bit integers in
xmm1 subject to writemask k1.
Zero extend 4 packed 16-bit integers in the low 8
bytes of xmm2/m64 to 4 packed 64-bit integers in
ymm1 subject to writemask k1.
Zero extend 8 packed 16-bit integers in
xmm2/m128 to 8 packed 64-bit integers in zmm1
subject to writemask k1.
Opcode/
Instruction
Op /
En
EVEX.128.66.0F38 30.WIG /r
VPMOVZXBW xmm1 {k1}{z}, xmm2/m64
EVEX.256.66.0F38.WIG 30 /r
VPMOVZXBW ymm1 {k1}{z},
xmm2/m128
EVEX.512.66.0F38.WIG 30 /r
VPMOVZXBW zmm1 {k1}{z},
ymm2/m256
EVEX.128.66.0F38.WIG 31 /r
VPMOVZXBD xmm1 {k1}{z}, xmm2/m32
PMOVZX—Packed Move with Zero Extend
Description
Zero extend 8 packed 8-bit integers in the low 8
bytes of xmm2/m64 to 8 packed 16-bit integers in
xmm1.
Zero extend 16 packed 8-bit integers in
xmm2/m128 to 16 packed 16-bit integers in ymm1.
Vol. 2B 4-351
INSTRUCTION SET REFERENCE, M-U
Opcode/
Instruction
Op /
En
HVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W0 35 /r
VPMOVZXDQ xmm1 {k1}{z}, xmm2/m64
EVEX.256.66.0F38.W0 35 /r
VPMOVZXDQ ymm1 {k1}{z},
xmm2/m128
EVEX.512.66.0F38.W0 35 /r
VPMOVZXDQ zmm1 {k1}{z},
ymm2/m256
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512F
Description
Zero extend 2 packed 32-bit integers in the low 8
bytes of xmm2/m64 to 2 packed 64-bit integers in
zmm1 using writemask k1.
Zero extend 4 packed 32-bit integers in
xmm2/m128 to 4 packed 64-bit integers in zmm1
using writemask k1.
Zero extend 8 packed 32-bit integers in
ymm2/m256 to 8 packed 64-bit integers in zmm1
using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
HVM, QVM, OVM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Legacy, VEX and EVEX encoded versions: Packed byte, word, or dword integers starting from the low bytes of the
source operand (second operand) are zero extended to word, dword, or quadword integers and stored in packed
signed bytes the destination operand.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 encoded version: Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: Packed dword integers starting from the low bytes of the source operand (second
operand) are zero extended to quadword integers and stored to the destination operand under the writemask.The
destination register is XMM, YMM or ZMM Register.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
Operation
Packed_Zero_Extend_BYTE_to_WORD(DEST, SRC)
DEST[15:0] ZeroExtend(SRC[7:0]);
DEST[31:16] ZeroExtend(SRC[15:8]);
DEST[47:32] ZeroExtend(SRC[23:16]);
DEST[63:48] ZeroExtend(SRC[31:24]);
DEST[79:64] ZeroExtend(SRC[39:32]);
DEST[95:80] ZeroExtend(SRC[47:40]);
DEST[111:96] ZeroExtend(SRC[55:48]);
DEST[127:112] ZeroExtend(SRC[63:56]);
Packed_Zero_Extend_BYTE_to_DWORD(DEST, SRC)
DEST[31:0] ZeroExtend(SRC[7:0]);
DEST[63:32] ZeroExtend(SRC[15:8]);
DEST[95:64] ZeroExtend(SRC[23:16]);
DEST[127:96] ZeroExtend(SRC[31:24]);
Packed_Zero_Extend_BYTE_to_QWORD(DEST, SRC)
DEST[63:0] ZeroExtend(SRC[7:0]);
DEST[127:64] ZeroExtend(SRC[15:8]);
4-352 Vol. 2B
PMOVZX—Packed Move with Zero Extend
INSTRUCTION SET REFERENCE, M-U
Packed_Zero_Extend_WORD_to_DWORD(DEST, SRC)
DEST[31:0] ZeroExtend(SRC[15:0]);
DEST[63:32] ZeroExtend(SRC[31:16]);
DEST[95:64] ZeroExtend(SRC[47:32]);
DEST[127:96] ZeroExtend(SRC[63:48]);
Packed_Zero_Extend_WORD_to_QWORD(DEST, SRC)
DEST[63:0] ZeroExtend(SRC[15:0]);
DEST[127:64] ZeroExtend(SRC[31:16]);
Packed_Zero_Extend_DWORD_to_QWORD(DEST, SRC)
DEST[63:0] ZeroExtend(SRC[31:0]);
DEST[127:64] ZeroExtend(SRC[63:32]);
VPMOVZXBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[383:256], SRC[191:128])
Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[511:384], SRC[255:192])
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TEMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVZXBD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[383:256], SRC[95:64])
Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TEMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
PMOVZX—Packed Move with Zero Extend
Vol. 2B 4-353
INSTRUCTION SET REFERENCE, M-U
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVZXBQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[127:0], SRC[15:0])
IF VL >= 256
Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[255:128], SRC[31:16])
FI;
IF VL >= 512
Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[383:256], SRC[47:32])
Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[511:384], SRC[63:48])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TEMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVZXWD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[383:256], SRC[191:128])
Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[511:384], SRC[256:192])
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TEMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
4-354 Vol. 2B
PMOVZX—Packed Move with Zero Extend
INSTRUCTION SET REFERENCE, M-U
DEST[MAX_VL-1:VL] 0
VPMOVZXWQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[383:256], SRC[95:64])
Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TEMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVZXDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[383:256], SRC[191:128])
Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[511:384], SRC[255:192])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TEMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVZXBW (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] 0
PMOVZX—Packed Move with Zero Extend
Vol. 2B 4-355
INSTRUCTION SET REFERENCE, M-U
VPMOVZXBD (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] 0
VPMOVZXBQ (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])
Packed_Zero_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])
DEST[MAX_VL-1:256] 0
VPMOVZXWD (VEX.256 encoded version)
Packed_Zero_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] 0
VPMOVZXWQ (VEX.256 encoded version)
Packed_Zero_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] 0
VPMOVZXDQ (VEX.256 encoded version)
Packed_Zero_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] 0
VPMOVZXBW (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_WORD()
DEST[MAX_VL-1:128] 0
VPMOVZXBD (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_DWORD()
DEST[MAX_VL-1:128] 0
VPMOVZXBQ (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_QWORD()
DEST[MAX_VL-1:128] 0
VPMOVZXWD (VEX.128 encoded version)
Packed_Zero_Extend_WORD_to_DWORD()
DEST[MAX_VL-1:128] 0
VPMOVZXWQ (VEX.128 encoded version)
Packed_Zero_Extend_WORD_to_QWORD()
DEST[MAX_VL-1:128] 0
VPMOVZXDQ (VEX.128 encoded version)
Packed_Zero_Extend_DWORD_to_QWORD()
DEST[MAX_VL-1:128] 0
PMOVZXBW
Packed_Zero_Extend_BYTE_to_WORD()
DEST[MAX_VL-1:128] (Unmodified)
4-356 Vol. 2B
PMOVZX—Packed Move with Zero Extend
INSTRUCTION SET REFERENCE, M-U
PMOVZXBD
Packed_Zero_Extend_BYTE_to_DWORD()
DEST[MAX_VL-1:128] (Unmodified)
PMOVZXBQ
Packed_Zero_Extend_BYTE_to_QWORD()
DEST[MAX_VL-1:128] (Unmodified)
PMOVZXWD
Packed_Zero_Extend_WORD_to_DWORD()
DEST[MAX_VL-1:128] (Unmodified)
PMOVZXWQ
Packed_Zero_Extend_WORD_to_QWORD()
DEST[MAX_VL-1:128] (Unmodified)
PMOVZXDQ
Packed_Zero_Extend_DWORD_to_QWORD()
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VPMOVZXBW __m512i _mm512_cvtepu8_epi16(__m256i a);
VPMOVZXBW __m512i _mm512_mask_cvtepu8_epi16(__m512i a, __mmask32 k, __m256i b);
VPMOVZXBW __m512i _mm512_maskz_cvtepu8_epi16( __mmask32 k, __m256i b);
VPMOVZXBD __m512i _mm512_cvtepu8_epi32(__m128i a);
VPMOVZXBD __m512i _mm512_mask_cvtepu8_epi32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXBD __m512i _mm512_maskz_cvtepu8_epi32( __mmask16 k, __m128i b);
VPMOVZXBQ __m512i _mm512_cvtepu8_epi64(__m128i a);
VPMOVZXBQ __m512i _mm512_mask_cvtepu8_epi64(__m512i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m512i _mm512_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m512i _mm512_cvtepu32_epi64(__m256i a);
VPMOVZXDQ __m512i _mm512_mask_cvtepu32_epi64(__m512i a, __mmask8 k, __m256i b);
VPMOVZXDQ __m512i _mm512_maskz_cvtepu32_epi64( __mmask8 k, __m256i a);
VPMOVZXWD __m512i _mm512_cvtepu16_epi32(__m128i a);
VPMOVZXWD __m512i _mm512_mask_cvtepu16_epi32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXWD __m512i _mm512_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);
VPMOVZXWQ __m512i _mm512_cvtepu16_epi64(__m256i a);
VPMOVZXWQ __m512i _mm512_mask_cvtepu16_epi64(__m512i a, __mmask8 k, __m256i b);
VPMOVZXWQ __m512i _mm512_maskz_cvtepu16_epi64( __mmask8 k, __m256i a);
VPMOVZXBW __m256i _mm256_cvtepu8_epi16(__m256i a);
VPMOVZXBW __m256i _mm256_mask_cvtepu8_epi16(__m256i a, __mmask16 k, __m128i b);
VPMOVZXBW __m256i _mm256_maskz_cvtepu8_epi16( __mmask16 k, __m128i b);
VPMOVZXBD __m256i _mm256_cvtepu8_epi32(__m128i a);
VPMOVZXBD __m256i _mm256_mask_cvtepu8_epi32(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBD __m256i _mm256_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_cvtepu8_epi64(__m128i a);
VPMOVZXBQ __m256i _mm256_mask_cvtepu8_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m256i _mm256_cvtepu32_epi64(__m128i a);
VPMOVZXDQ __m256i _mm256_mask_cvtepu32_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXDQ __m256i _mm256_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m256i _mm256_cvtepu16_epi32(__m128i a);
VPMOVZXWD __m256i _mm256_mask_cvtepu16_epi32(__m256i a, __mmask16 k, __m128i b);
VPMOVZXWD __m256i _mm256_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);
PMOVZX—Packed Move with Zero Extend
Vol. 2B 4-357
INSTRUCTION SET REFERENCE, M-U
VPMOVZXWQ __m256i _mm256_cvtepu16_epi64(__m128i a);
VPMOVZXWQ __m256i _mm256_mask_cvtepu16_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXWQ __m256i _mm256_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);
VPMOVZXBW __m128i _mm_mask_cvtepu8_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBW __m128i _mm_maskz_cvtepu8_epi16( __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_mask_cvtepu8_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_mask_cvtepu8_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m128i _mm_mask_cvtepu32_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXDQ __m128i _mm_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m128i _mm_mask_cvtepu16_epi32(__m128i a, __mmask16 k, __m128i b);
VPMOVZXWD __m128i _mm_maskz_cvtepu16_epi32(__mmask8 k, __m128i a);
VPMOVZXWQ __m128i _mm_mask_cvtepu16_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXWQ __m128i _mm_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);
PMOVZXBW __m128i _mm_ cvtepu8_epi16 ( __m128i a);
PMOVZXBD __m128i _mm_ cvtepu8_epi32 ( __m128i a);
PMOVZXBQ __m128i _mm_ cvtepu8_epi64 ( __m128i a);
PMOVZXWD __m128i _mm_ cvtepu16_epi32 ( __m128i a);
PMOVZXWQ __m128i _mm_ cvtepu16_epi64 ( __m128i a);
PMOVZXDQ __m128i _mm_ cvtepu32_epi64 ( __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5.
EVEX-encoded instruction, see Exceptions Type E5.
#UD
4-358 Vol. 2B
If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.
PMOVZX—Packed Move with Zero Extend
INSTRUCTION SET REFERENCE, M-U
PMULDQ—Multiply Packed Doubleword Integers
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0F 38 28 /r
PMULDQ xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 28 /r
VPMULDQ xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.WIG 28 /r
VPMULDQ ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W1 28 /r
VPMULDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
RVM
V/V
AVX
RVM
V/V
AVX2
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W1 28 /r
VPMULDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F38.W1 28 /r
VPMULDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Description
Multiply packed signed doubleword integers in xmm1 by
packed signed doubleword integers in xmm2/m128, and
store the quadword results in xmm1.
Multiply packed signed doubleword integers in xmm2 by
packed signed doubleword integers in xmm3/m128, and
store the quadword results in xmm1.
Multiply packed signed doubleword integers in ymm2 by
packed signed doubleword integers in ymm3/m256, and
store the quadword results in ymm1.
Multiply packed signed doubleword integers in xmm2 by
packed signed doubleword integers in
xmm3/m128/m64bcst, and store the quadword results in
xmm1 using writemask k1.
Multiply packed signed doubleword integers in ymm2 by
packed signed doubleword integers in
ymm3/m256/m64bcst, and store the quadword results in
ymm1 using writemask k1.
Multiply packed signed doubleword integers in zmm2 by
packed signed doubleword integers in
zmm3/m512/m64bcst, and store the quadword results in
zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Multiplies packed signed doubleword integers in the even-numbered (zero-based reference) elements of the first
source operand with the packed signed doubleword integers in the corresponding elements of the second source
operand and stores packed signed quadword results in the destination operand.
128-bit Legacy SSE version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e. the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are
fetched from memory, but only the first and third doublewords are used in the computation. The first source
operand and the destination XMM operand is the same. The second source operand can be an XMM register or 128bit memory location. Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e., the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are
fetched from memory, but only the first and third doublewords are used in the computation.The first source
operand and the destination operand are XMM registers. The second source operand can be an XMM register or
128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 encoded version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e. the first, 3rd, 5th, 7th doubleword element. For 256-bit memory operands, 256 bits are
fetched from memory, but only the four even-numbered doublewords are used in the computation. The first source
operand and the destination operand are YMM registers. The second source operand can be a YMM register or 256bit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.
PMULDQ—Multiply Packed Doubleword Integers
Vol. 2B 4-359
INSTRUCTION SET REFERENCE, M-U
EVEX encoded version: The input signed doubleword integers are taken from the even-numbered elements of the
source operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64bit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64bit granularity.
Operation
VPMULDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[31:0])
ELSE DEST[i+63:i] SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMULDQ (VEX.256 encoded version)
DEST[63:0] SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])
DEST[127:64] SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])
DEST[191:128] SignExtend64( SRC1[159:128]) * SignExtend64( SRC2[159:128])
DEST[255:192] SignExtend64( SRC1[223:192]) * SignExtend64( SRC2[223:192])
DEST[MAX_VL-1:256] 0
VPMULDQ (VEX.128 encoded version)
DEST[63:0] SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])
DEST[127:64] SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])
DEST[MAX_VL-1:128] 0
PMULDQ (128-bit Legacy SSE version)
DEST[63:0] SignExtend64( DEST[31:0]) * SignExtend64( SRC[31:0])
DEST[127:64] SignExtend64( DEST[95:64]) * SignExtend64( SRC[95:64])
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VPMULDQ __m512i _mm512_mul_epi32(__m512i a, __m512i b);
VPMULDQ __m512i _mm512_mask_mul_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULDQ __m512i _mm512_maskz_mul_epi32( __mmask8 k, __m512i a, __m512i b);
VPMULDQ __m256i _mm256_mask_mul_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULDQ __m256i _mm256_mask_mul_epi32( __mmask8 k, __m256i a, __m256i b);
VPMULDQ __m128i _mm_mask_mul_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULDQ __m128i _mm_mask_mul_epi32( __mmask8 k, __m128i a, __m128i b);
(V)PMULDQ __m128i _mm_mul_epi32( __m128i a, __m128i b);
VPMULDQ __m256i _mm256_mul_epi32( __m256i a, __m256i b);
4-360 Vol. 2B
PMULDQ—Multiply Packed Doubleword Integers
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
PMULDQ—Multiply Packed Doubleword Integers
Vol. 2B 4-361
INSTRUCTION SET REFERENCE, M-U
PMULHRSW — Packed Multiply High with Round and Scale
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 0B /r1
RM
V/V
SSSE3
Multiply 16-bit signed words, scale and round
signed doublewords, pack high 16 bits to
mm1.
RM
V/V
SSSE3
Multiply 16-bit signed words, scale and round
signed doublewords, pack high 16 bits to
xmm1.
RVM V/V
AVX
Multiply 16-bit signed words, scale and round
signed doublewords, pack high 16 bits to
xmm1.
RVM V/V
AVX2
Multiply 16-bit signed words, scale and round
signed doublewords, pack high 16 bits to
ymm1.
EVEX.NDS.128.66.0F38.WIG 0B /r
VPMULHRSW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Multiply 16-bit signed words, scale and round
AVX512BW signed doublewords, pack high 16 bits to
xmm1 under writemask k1.
EVEX.NDS.256.66.0F38.WIG 0B /r
VPMULHRSW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Multiply 16-bit signed words, scale and round
AVX512BW signed doublewords, pack high 16 bits to
ymm1 under writemask k1.
EVEX.NDS.512.66.0F38.WIG 0B /r
VPMULHRSW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Multiply 16-bit signed words, scale and round
signed doublewords, pack high 16 bits to
zmm1 under writemask k1.
PMULHRSW mm1, mm2/m64
66 0F 38 0B /r
PMULHRSW xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 0B /r
VPMULHRSW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 0B /r
VPMULHRSW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
PMULHRSW multiplies vertically each signed 16-bit integer from the destination operand (first operand) with the
corresponding signed 16-bit integer of the source operand (second operand), producing intermediate, signed 32bit integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always
performed by adding 1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by
selecting the 16 bits immediately to the right of the most significant bit of each 18-bit intermediate result and
packed to the destination operand.
When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a
general-protection exception (#GP) will be generated.
In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.
Legacy SSE version 64-bit operand: Both operands can be MMX registers. The second source operand is an MMX
register or a 64-bit memory location.
4-362 Vol. 2B
PMULHRSW — Packed Multiply High with Round and Scale
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Operation
PMULHRSW (with 64-bit operands)
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;
temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;
DEST[15:0] = temp0[16:1];
DEST[31:16] = temp1[16:1];
DEST[47:32] = temp2[16:1];
DEST[63:48] = temp3[16:1];
PMULHRSW (with 128-bit operand)
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;
temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;
temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;
temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1;
temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1;
temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1;
DEST[15:0] = temp0[16:1];
DEST[31:16] = temp1[16:1];
DEST[47:32] = temp2[16:1];
DEST[63:48] = temp3[16:1];
DEST[79:64] = temp4[16:1];
DEST[95:80] = temp5[16:1];
DEST[111:96] = temp6[16:1];
DEST[127:112] = temp7[16:1];
VPMULHRSW (VEX.128 encoded version)
temp0[31:0] INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
DEST[15:0] temp0[16:1]
DEST[31:16] temp1[16:1]
DEST[47:32] temp2[16:1]
PMULHRSW — Packed Multiply High with Round and Scale
Vol. 2B 4-363
INSTRUCTION SET REFERENCE, M-U
DEST[63:48] temp3[16:1]
DEST[79:64] temp4[16:1]
DEST[95:80] temp5[16:1]
DEST[111:96] temp6[16:1]
DEST[127:112] temp7[16:1]
DEST[VLMAX-1:128] 0
VPMULHRSW (VEX.256 encoded version)
temp0[31:0] INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
temp8[31:0] INT32 ((SRC1[143:128] * SRC2[143:128]) >>14) + 1
temp9[31:0] INT32 ((SRC1[159:144] * SRC2[159:144]) >>14) + 1
temp10[31:0] INT32 ((SRC1[75:160] * SRC2[175:160]) >>14) + 1
temp11[31:0] INT32 ((SRC1[191:176] * SRC2[191:176]) >>14) + 1
temp12[31:0] INT32 ((SRC1[207:192] * SRC2[207:192]) >>14) + 1
temp13[31:0] INT32 ((SRC1[223:208] * SRC2[223:208]) >>14) + 1
temp14[31:0] INT32 ((SRC1[239:224] * SRC2[239:224]) >>14) + 1
temp15[31:0] INT32 ((SRC1[255:240] * SRC2[255:240) >>14) + 1
DEST[15:0] temp0[16:1]
DEST[31:16] temp1[16:1]
DEST[47:32] temp2[16:1]
DEST[63:48] temp3[16:1]
DEST[79:64] temp4[16:1]
DEST[95:80] temp5[16:1]
DEST[111:96] temp6[16:1]
DEST[127:112] temp7[16:1]
DEST[143:128] temp8[16:1]
DEST[159:144] temp9[16:1]
DEST[175:160] temp10[16:1]
DEST[191:176] temp11[16:1]
DEST[207:192] temp12[16:1]
DEST[223:208] temp13[16:1]
DEST[239:224] temp14[16:1]
DEST[255:240] temp15[16:1]
DEST[MAX_VL-1:256] 0
VPMULHRSW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] ((SRC1[i+15:i] * SRC2[i+15:i]) >>14) + 1
DEST[i+15:i] tmp[16:1]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
4-364 Vol. 2B
PMULHRSW — Packed Multiply High with Round and Scale
INSTRUCTION SET REFERENCE, M-U
ELSE *zeroing-masking*
DEST[i+15:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPMULHRSW __m512i _mm512_mulhrs_epi16(__m512i a, __m512i b);
VPMULHRSW __m512i _mm512_mask_mulhrs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHRSW __m512i _mm512_maskz_mulhrs_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULHRSW __m256i _mm256_mask_mulhrs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHRSW __m256i _mm256_maskz_mulhrs_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULHRSW __m128i _mm_mask_mulhrs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHRSW __m128i _mm_maskz_mulhrs_epi16( __mmask8 k, __m128i a, __m128i b);
PMULHRSW: __m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)
(V)PMULHRSW: __m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
VPMULHRSW:__m256i _mm256_mulhrs_epi16 (__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
PMULHRSW — Packed Multiply High with Round and Scale
Vol. 2B 4-365
INSTRUCTION SET REFERENCE, M-U
PMULHUW—Multiply Packed Unsigned Integers and Store High Result
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F E4 /r1
RM
V/V
SSE
Multiply the packed unsigned word integers in
mm1 register and mm2/m64, and store the
high 16 bits of the results in mm1.
RM
V/V
SSE2
Multiply the packed unsigned word integers in
xmm1 and xmm2/m128, and store the high
16 bits of the results in xmm1.
RVM V/V
AVX
Multiply the packed unsigned word integers in
xmm2 and xmm3/m128, and store the high
16 bits of the results in xmm1.
RVM V/V
AVX2
Multiply the packed unsigned word integers in
ymm2 and ymm3/m256, and store the high
16 bits of the results in ymm1.
EVEX.NDS.128.66.0F.WIG E4 /r
VPMULHUW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Multiply the packed unsigned word integers in
AVX512BW xmm2 and xmm3/m128, and store the high
16 bits of the results in xmm1 under
writemask k1.
EVEX.NDS.256.66.0F.WIG E4 /r
VPMULHUW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Multiply the packed unsigned word integers in
AVX512BW ymm2 and ymm3/m256, and store the high
16 bits of the results in ymm1 under
writemask k1.
EVEX.NDS.512.66.0F.WIG E4 /r
VPMULHUW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Multiply the packed unsigned word integers in
zmm2 and zmm3/m512, and store the high 16
bits of the results in zmm1 under writemask
k1.
PMULHUW mm1, mm2/m64
66 0F E4 /r
PMULHUW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG E4 /r
VPMULHUW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG E4 /r
VPMULHUW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD unsigned multiply of the packed unsigned word integers in the destination operand (first operand)
and the source operand (second operand), and stores the high 16 bits of each 32-bit intermediate results in the
destination operand. (Figure 4-12 shows this operation when using 64-bit operands.)
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
4-366 Vol. 2B
PMULHUW—Multiply Packed Unsigned Integers and Store High Result
INSTRUCTION SET REFERENCE, M-U
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
SRC
DEST
TEMP
Z3 = X3 ∗ Y3
DEST
X3
Y3
X2
Y2
Z2 = X2 ∗ Y2
X1
Y1
X0
Y0
Z1 = X1 ∗ Y1
Z0 = X0 ∗ Y0
Z3[31:16] Z2[31:16] Z1[31:16] Z0[31:16]
Figure 4-12. PMULHUW and PMULHW Instruction Operation Using 64-bit Operands
Operation
PMULHUW (with 64-bit operands)
TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48];
DEST[15:0] ←
TEMP0[31:16];
DEST[31:16] ← TEMP1[31:16];
DEST[47:32] ← TEMP2[31:16];
DEST[63:48] ← TEMP3[31:16];
PMULHUW (with 128-bit operands)
TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48];
TEMP4[31:0] ← DEST[79:64] ∗ SRC[79:64];
TEMP5[31:0] ← DEST[95:80] ∗ SRC[95:80];
TEMP6[31:0] ← DEST[111:96] ∗ SRC[111:96];
TEMP7[31:0] ← DEST[127:112] ∗ SRC[127:112];
DEST[15:0] ←
TEMP0[31:16];
DEST[31:16] ← TEMP1[31:16];
DEST[47:32] ← TEMP2[31:16];
DEST[63:48] ← TEMP3[31:16];
DEST[79:64] ← TEMP4[31:16];
DEST[95:80] ← TEMP5[31:16];
DEST[111:96] ← TEMP6[31:16];
DEST[127:112] ← TEMP7[31:16];
VPMULHUW (VEX.128 encoded version)
TEMP0[31:0] SRC1[15:0] * SRC2[15:0]
PMULHUW—Multiply Packed Unsigned Integers and Store High Result
Vol. 2B 4-367
INSTRUCTION SET REFERENCE, M-U
TEMP1[31:0] SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] SRC1[127:112] * SRC2[127:112]
DEST[15:0] TEMP0[31:16]
DEST[31:16] TEMP1[31:16]
DEST[47:32] TEMP2[31:16]
DEST[63:48] TEMP3[31:16]
DEST[79:64] TEMP4[31:16]
DEST[95:80] TEMP5[31:16]
DEST[111:96] TEMP6[31:16]
DEST[127:112] TEMP7[31:16]
DEST[VLMAX-1:128] 0
PMULHUW (VEX.256 encoded version)
TEMP0[31:0] SRC1[15:0] * SRC2[15:0]
TEMP1[31:0] SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] SRC1[255:240] * SRC2[255:240]
DEST[15:0] TEMP0[31:16]
DEST[31:16] TEMP1[31:16]
DEST[47:32] TEMP2[31:16]
DEST[63:48] TEMP3[31:16]
DEST[79:64] TEMP4[31:16]
DEST[95:80] TEMP5[31:16]
DEST[111:96] TEMP6[31:16]
DEST[127:112] TEMP7[31:16]
DEST[143:128] TEMP8[31:16]
DEST[159:144] TEMP9[31:16]
DEST[175:160] TEMP10[31:16]
DEST[191:176] TEMP11[31:16]
DEST[207:192] TEMP12[31:16]
DEST[223:208] TEMP13[31:16]
DEST[239:224] TEMP14[31:16]
DEST[255:240] TEMP15[31:16]
DEST[MAX_VL-1:256] 0
PMULHUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
4-368 Vol. 2B
PMULHUW—Multiply Packed Unsigned Integers and Store High Result
INSTRUCTION SET REFERENCE, M-U
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] SRC1[i+15:i] * SRC2[i+15:i]
DEST[i+15:i] tmp[31:16]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMULHUW __m512i _mm512_mulhi_epu16(__m512i a, __m512i b);
VPMULHUW __m512i _mm512_mask_mulhi_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m512i _mm512_maskz_mulhi_epu16( __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m256i _mm256_mask_mulhi_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m256i _mm256_maskz_mulhi_epu16( __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m128i _mm_mask_mulhi_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHUW __m128i _mm_maskz_mulhi_epu16( __mmask8 k, __m128i a, __m128i b);
PMULHUW:__m64 _mm_mulhi_pu16(__m64 a, __m64 b)
(V)PMULHUW:__m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)
VPMULHUW:__m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
PMULHUW—Multiply Packed Unsigned Integers and Store High Result
Vol. 2B 4-369
INSTRUCTION SET REFERENCE, M-U
PMULHW—Multiply Packed Signed Integers and Store High Result
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F E5 /r1
RM
V/V
MMX
Multiply the packed signed word integers in mm1
register and mm2/m64, and store the high 16
bits of the results in mm1.
RM
V/V
SSE2
Multiply the packed signed word integers in
xmm1 and xmm2/m128, and store the high 16
bits of the results in xmm1.
RVM V/V
AVX
Multiply the packed signed word integers in
xmm2 and xmm3/m128, and store the high 16
bits of the results in xmm1.
RVM V/V
AVX2
Multiply the packed signed word integers in
ymm2 and ymm3/m256, and store the high 16
bits of the results in ymm1.
EVEX.NDS.128.66.0F.WIG E5 /r
VPMULHW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Multiply the packed signed word integers in
xmm2 and xmm3/m128, and store the high 16
bits of the results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG E5 /r
VPMULHW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Multiply the packed signed word integers in
ymm2 and ymm3/m256, and store the high 16
bits of the results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG E5 /r
VPMULHW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW
Multiply the packed signed word integers in
zmm2 and zmm3/m512, and store the high 16
bits of the results in zmm1 under writemask k1.
PMULHW mm, mm/m64
66 0F E5 /r
PMULHW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG E5 /r
VPMULHW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG E5 /r
VPMULHW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and
the source operand (second operand), and stores the high 16 bits of each intermediate 32-bit result in the destination operand. (Figure 4-12 shows this operation when using 64-bit operands.)
n 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.
4-370 Vol. 2B
PMULHW—Multiply Packed Signed Integers and Store High Result
INSTRUCTION SET REFERENCE, M-U
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Operation
PMULHW (with 64-bit operands)
TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48];
DEST[15:0] ←
TEMP0[31:16];
DEST[31:16] ← TEMP1[31:16];
DEST[47:32] ← TEMP2[31:16];
DEST[63:48] ← TEMP3[31:16];
PMULHW (with 128-bit operands)
TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48];
TEMP4[31:0] ← DEST[79:64] ∗ SRC[79:64];
TEMP5[31:0] ← DEST[95:80] ∗ SRC[95:80];
TEMP6[31:0] ← DEST[111:96] ∗ SRC[111:96];
TEMP7[31:0] ← DEST[127:112] ∗ SRC[127:112];
DEST[15:0] ←
TEMP0[31:16];
DEST[31:16] ← TEMP1[31:16];
DEST[47:32] ← TEMP2[31:16];
DEST[63:48] ← TEMP3[31:16];
DEST[79:64] ← TEMP4[31:16];
DEST[95:80] ← TEMP5[31:16];
DEST[111:96] ← TEMP6[31:16];
DEST[127:112] ← TEMP7[31:16];
VPMULHW (VEX.128 encoded version)
TEMP0[31:0] SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] SRC1[127:112] * SRC2[127:112]
DEST[15:0] TEMP0[31:16]
DEST[31:16] TEMP1[31:16]
DEST[47:32] TEMP2[31:16]
DEST[63:48] TEMP3[31:16]
DEST[79:64] TEMP4[31:16]
DEST[95:80] TEMP5[31:16]
DEST[111:96] TEMP6[31:16]
DEST[127:112] TEMP7[31:16]
DEST[VLMAX-1:128] 0
PMULHW—Multiply Packed Signed Integers and Store High Result
Vol. 2B 4-371
INSTRUCTION SET REFERENCE, M-U
PMULHW (VEX.256 encoded version)
TEMP0[31:0] SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] SRC1[255:240] * SRC2[255:240]
DEST[15:0] TEMP0[31:16]
DEST[31:16] TEMP1[31:16]
DEST[47:32] TEMP2[31:16]
DEST[63:48] TEMP3[31:16]
DEST[79:64] TEMP4[31:16]
DEST[95:80] TEMP5[31:16]
DEST[111:96] TEMP6[31:16]
DEST[127:112] TEMP7[31:16]
DEST[143:128] TEMP8[31:16]
DEST[159:144] TEMP9[31:16]
DEST[175:160] TEMP10[31:16]
DEST[191:176] TEMP11[31:16]
DEST[207:192] TEMP12[31:16]
DEST[223:208] TEMP13[31:16]
DEST[239:224] TEMP14[31:16]
DEST[255:240] TEMP15[31:16]
DEST[VLMAX-1:256] 0
PMULHW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] SRC1[i+15:i] * SRC2[i+15:i]
DEST[i+15:i] tmp[31:16]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-372 Vol. 2B
PMULHW—Multiply Packed Signed Integers and Store High Result
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VPMULHW __m512i _mm512_mulhi_epi16(__m512i a, __m512i b);
VPMULHW __m512i _mm512_mask_mulhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHW __m512i _mm512_maskz_mulhi_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULHW __m256i _mm256_mask_mulhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHW __m256i _mm256_maskz_mulhi_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULHW __m128i _mm_mask_mulhi_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHW __m128i _mm_maskz_mulhi_epi16( __mmask8 k, __m128i a, __m128i b);
PMULHW:__m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2)
(V)PMULHW:__m128i _mm_mulhi_epi16 ( __m128i a, __m128i b)
VPMULHW:__m256i _mm256_mulhi_epi16 ( __m256i a, __m256i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
PMULHW—Multiply Packed Signed Integers and Store High Result
Vol. 2B 4-373
INSTRUCTION SET REFERENCE, M-U
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result
Opcode/
Instruction
Op/
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE4_1
66 0F 38 40 /r
PMULLD xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 40 /r
VPMULLD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.WIG 40 /r
VPMULLD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W0 40 /r
VPMULLD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 40 /r
VPMULLD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 40 /r
VPMULLD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 40 /r
VPMULLQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 40 /r
VPMULLQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 40 /r
VPMULLQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
RVM
V/V
AVX
RVM
V/V
AVX2
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Multiply the packed dword signed integers in xmm1 and
xmm2/m128 and store the low 32 bits of each product in
xmm1.
Multiply the packed dword signed integers in xmm2 and
xmm3/m128 and store the low 32 bits of each product in
xmm1.
Multiply the packed dword signed integers in ymm2 and
ymm3/m256 and store the low 32 bits of each product in
ymm1.
Multiply the packed dword signed integers in xmm2 and
xmm3/m128/m32bcst and store the low 32 bits of each
product in xmm1 under writemask k1.
Multiply the packed dword signed integers in ymm2 and
ymm3/m256/m32bcst and store the low 32 bits of each
product in ymm1 under writemask k1.
Multiply the packed dword signed integers in zmm2 and
zmm3/m512/m32bcst and store the low 32 bits of each
product in zmm1 under writemask k1.
Multiply the packed qword signed integers in xmm2 and
xmm3/m128/m64bcst and store the low 64 bits of each
product in xmm1 under writemask k1.
Multiply the packed qword signed integers in ymm2 and
ymm3/m256/m64bcst and store the low 64 bits of each
product in ymm1 under writemask k1.
Multiply the packed qword signed integers in zmm2 and
zmm3/m512/m64bcst and store the low 64 bits of each
product in zmm1 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source
operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit
intermediate results are stored to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register
or 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.
4-374 Vol. 2B
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result
INSTRUCTION SET REFERENCE, M-U
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
Operation
VPMULLQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN Temp[127:0] SRC1[i+63:i] * SRC2[63:0]
ELSE Temp[127:0] SRC1[i+63:i] * SRC2[i+63:i]
FI;
DEST[i+63:i] Temp[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMULLD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN Temp[63:0] SRC1[i+31:i] * SRC2[31:0]
ELSE Temp[63:0] SRC1[i+31:i] * SRC2[i+31:i]
FI;
DEST[i+31:i] Temp[31:0]
ELSE
IF *merging-masking*
; merging-masking
*DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result
Vol. 2B 4-375
INSTRUCTION SET REFERENCE, M-U
VPMULLD (VEX.256 encoded version)
Temp0[63:0] SRC1[31:0] * SRC2[31:0]
Temp1[63:0] SRC1[63:32] * SRC2[63:32]
Temp2[63:0] SRC1[95:64] * SRC2[95:64]
Temp3[63:0] SRC1[127:96] * SRC2[127:96]
Temp4[63:0] SRC1[159:128] * SRC2[159:128]
Temp5[63:0] SRC1[191:160] * SRC2[191:160]
Temp6[63:0] SRC1[223:192] * SRC2[223:192]
Temp7[63:0] SRC1[255:224] * SRC2[255:224]
DEST[31:0] Temp0[31:0]
DEST[63:32] Temp1[31:0]
DEST[95:64] Temp2[31:0]
DEST[127:96] Temp3[31:0]
DEST[159:128] Temp4[31:0]
DEST[191:160] Temp5[31:0]
DEST[223:192] Temp6[31:0]
DEST[255:224] Temp7[31:0]
DEST[MAX_VL-1:256] 0
VPMULLD (VEX.128 encoded version)
Temp0[63:0] SRC1[31:0] * SRC2[31:0]
Temp1[63:0] SRC1[63:32] * SRC2[63:32]
Temp2[63:0] SRC1[95:64] * SRC2[95:64]
Temp3[63:0] SRC1[127:96] * SRC2[127:96]
DEST[31:0] Temp0[31:0]
DEST[63:32] Temp1[31:0]
DEST[95:64] Temp2[31:0]
DEST[127:96] Temp3[31:0]
DEST[MAX_VL-1:128] 0
PMULLD (128-bit Legacy SSE version)
Temp0[63:0] DEST[31:0] * SRC[31:0]
Temp1[63:0] DEST[63:32] * SRC[63:32]
Temp2[63:0] DEST[95:64] * SRC[95:64]
Temp3[63:0] DEST[127:96] * SRC[127:96]
DEST[31:0] Temp0[31:0]
DEST[63:32] Temp1[31:0]
DEST[95:64] Temp2[31:0]
DEST[127:96] Temp3[31:0]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);
VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);
VPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);
VPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);
VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);
PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);
VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);
VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
4-376 Vol. 2B
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result
INSTRUCTION SET REFERENCE, M-U
VPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);
VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);
VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);
VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result
Vol. 2B 4-377
INSTRUCTION SET REFERENCE, M-U
PMULLW—Multiply Packed Signed Integers and Store Low Result
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F D5 /r1
RM
V/V
MMX
Multiply the packed signed word integers in
mm1 register and mm2/m64, and store the low
16 bits of the results in mm1.
RM
V/V
SSE2
Multiply the packed signed word integers in
xmm1 and xmm2/m128, and store the low 16
bits of the results in xmm1.
RVM V/V
AVX
Multiply the packed dword signed integers in
xmm2 and xmm3/m128 and store the low 32
bits of each product in xmm1.
RVM V/V
AVX2
Multiply the packed signed word integers in
ymm2 and ymm3/m256, and store the low 16
bits of the results in ymm1.
EVEX.NDS.128.66.0F.WIG D5 /r
VPMULLW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Multiply the packed signed word integers in
AVX512BW xmm2 and xmm3/m128, and store the low 16
bits of the results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG D5 /r
VPMULLW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Multiply the packed signed word integers in
AVX512BW ymm2 and ymm3/m256, and store the low 16
bits of the results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG D5 /r
VPMULLW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Multiply the packed signed word integers in
zmm2 and zmm3/m512, and store the low 16
bits of the results in zmm1 under writemask k1.
PMULLW mm, mm/m64
66 0F D5 /r
PMULLW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG D5 /r
VPMULLW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG D5 /r
VPMULLW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and
the source operand (second operand), and stores the low 16 bits of each intermediate 32-bit result in the destination operand. (Figure 4-12 shows this operation when using 64-bit operands.)
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.
4-378 Vol. 2B
PMULLW—Multiply Packed Signed Integers and Store Low Result
INSTRUCTION SET REFERENCE, M-U
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.
SRC
DEST
TEMP
Z3 = X3 ∗ Y3
DEST
X3
Y3
X2
X1
Y2
Y1
Z2 = X2 ∗ Y2
Z3[15:0]
Z2[15:0]
X0
Y0
Z1 = X1 ∗ Y1
Z1[15:0]
Z0 = X0 ∗ Y0
Z0[15:0]
Figure 4-13. PMULLU Instruction Operation Using 64-bit Operands
Operation
PMULLW (with 64-bit operands)
TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48];
DEST[15:0] ←
TEMP0[15:0];
DEST[31:16] ← TEMP1[15:0];
DEST[47:32] ← TEMP2[15:0];
DEST[63:48] ← TEMP3[15:0];
PMULLW (with 128-bit operands)
TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48];
TEMP4[31:0] ← DEST[79:64] ∗ SRC[79:64];
TEMP5[31:0] ← DEST[95:80] ∗ SRC[95:80];
TEMP6[31:0] ← DEST[111:96] ∗ SRC[111:96];
TEMP7[31:0] ← DEST[127:112] ∗ SRC[127:112];
DEST[15:0] ←
TEMP0[15:0];
DEST[31:16] ← TEMP1[15:0];
DEST[47:32] ← TEMP2[15:0];
DEST[63:48] ← TEMP3[15:0];
DEST[79:64] ← TEMP4[15:0];
DEST[95:80] ← TEMP5[15:0];
DEST[111:96] ← TEMP6[15:0];
DEST[127:112] ← TEMP7[15:0];
DEST[VLMAX-1:256] 0
PMULLW—Multiply Packed Signed Integers and Store Low Result
Vol. 2B 4-379
INSTRUCTION SET REFERENCE, M-U
VPMULLW (VEX.128 encoded version)
Temp0[31:0] SRC1[15:0] * SRC2[15:0]
Temp1[31:0] SRC1[31:16] * SRC2[31:16]
Temp2[31:0] SRC1[47:32] * SRC2[47:32]
Temp3[31:0] SRC1[63:48] * SRC2[63:48]
Temp4[31:0] SRC1[79:64] * SRC2[79:64]
Temp5[31:0] SRC1[95:80] * SRC2[95:80]
Temp6[31:0] SRC1[111:96] * SRC2[111:96]
Temp7[31:0] SRC1[127:112] * SRC2[127:112]
DEST[15:0] Temp0[15:0]
DEST[31:16] Temp1[15:0]
DEST[47:32] Temp2[15:0]
DEST[63:48] Temp3[15:0]
DEST[79:64] Temp4[15:0]
DEST[95:80] Temp5[15:0]
DEST[111:96] Temp6[15:0]
DEST[127:112] Temp7[15:0]
DEST[VLMAX-1:128] 0
PMULLW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] SRC1[i+15:i] * SRC2[i+15:i]
DEST[i+15:i] temp[15:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMULLW __m512i _mm512_mullo_epi16(__m512i a, __m512i b);
VPMULLW __m512i _mm512_mask_mullo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULLW __m512i _mm512_maskz_mullo_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULLW __m256i _mm256_mask_mullo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULLW __m256i _mm256_maskz_mullo_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULLW __m128i _mm_mask_mullo_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLW __m128i _mm_maskz_mullo_epi16( __mmask8 k, __m128i a, __m128i b);
PMULLW: __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)
(V)PMULLW: __m128i _mm_mullo_epi16 ( __m128i a, __m128i b)
VPMULLW:__m256i _mm256_mullo_epi16 ( __m256i a, __m256i b);
Flags Affected
None.
4-380 Vol. 2B
PMULLW—Multiply Packed Signed Integers and Store Low Result
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
PMULLW—Multiply Packed Signed Integers and Store Low Result
Vol. 2B 4-381
INSTRUCTION SET REFERENCE, M-U
PMULUDQ—Multiply Packed Unsigned Doubleword Integers
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F F4 /r1
RM
V/V
SSE2
Multiply unsigned doubleword integer in mm1 by
unsigned doubleword integer in mm2/m64, and
store the quadword result in mm1.
RM
V/V
SSE2
Multiply packed unsigned doubleword integers in
xmm1 by packed unsigned doubleword integers
in xmm2/m128, and store the quadword results
in xmm1.
RVM V/V
AVX
Multiply packed unsigned doubleword integers in
xmm2 by packed unsigned doubleword integers
in xmm3/m128, and store the quadword results
in xmm1.
RVM V/V
AVX2
Multiply packed unsigned doubleword integers in
ymm2 by packed unsigned doubleword integers
in ymm3/m256, and store the quadword results
in ymm1.
EVEX.NDS.128.66.0F.W1 F4 /r
VPMULUDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
Multiply packed unsigned doubleword integers in
xmm2 by packed unsigned doubleword integers
in xmm3/m128/m64bcst, and store the
quadword results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.W1 F4 /r
VPMULUDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
Multiply packed unsigned doubleword integers in
ymm2 by packed unsigned doubleword integers
in ymm3/m256/m64bcst, and store the
quadword results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.W1 F4 /r
VPMULUDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Multiply packed unsigned doubleword integers in
zmm2 by packed unsigned doubleword integers
in zmm3/m512/m64bcst, and store the
quadword results in zmm1 under writemask k1.
PMULUDQ mm1, mm2/m64
66 0F F4 /r
PMULUDQ xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG F4 /r
VPMULUDQ xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG F4 /r
VPMULUDQ ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Multiplies the first operand (destination operand) by the second operand (source operand) and stores the result in
the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an unsigned doubleword integer stored in the low
doubleword of an MMX technology register or a 64-bit memory location. The destination operand can be an
unsigned doubleword integer stored in the low doubleword an MMX technology register. The result is an unsigned
4-382 Vol. 2B
PMULUDQ—Multiply Packed Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, M-U
quadword integer stored in the destination an MMX technology register. When a quadword result is too large to be
represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the destination
element (that is, the carry is ignored).
For 64-bit memory operands, 64 bits are fetched from memory, but only the low doubleword is used in the computation.
128-bit Legacy SSE version: The second source operand is two packed unsigned doubleword integers stored in the
first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,
128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first
source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM
register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is two packed unsigned doubleword integers stored in the
first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,
128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first
source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM
register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (VLMAX1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand is four packed unsigned doubleword integers stored in the
first (low), third, fifth and seventh doublewords of a YMM register or a 256-bit memory location. For 256-bit
memory operands, 256 bits are fetched from memory, but only the first, third, fifth and seventh doublewords are
used in the computation. The first source operand is four packed unsigned doubleword integers stored in the first,
third, fifth and seventh doublewords of an YMM register. The destination contains four packed unaligned quadword
integers stored in an YMM register.
EVEX encoded version: The input unsigned doubleword integers are taken from the even-numbered elements of
the source operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64bit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64bit granularity.
Operation
PMULUDQ (with 64-Bit operands)
DEST[63:0] ← DEST[31:0] ∗ SRC[31:0];
PMULUDQ (with 128-Bit operands)
DEST[63:0] ← DEST[31:0] ∗ SRC[31:0];
DEST[127:64] ← DEST[95:64] ∗ SRC[95:64];
VPMULUDQ (VEX.128 encoded version)
DEST[63:0] SRC1[31:0] * SRC2[31:0]
DEST[127:64] SRC1[95:64] * SRC2[95:64]
DEST[VLMAX-1:128] 0
VPMULUDQ (VEX.256 encoded version)
DEST[63:0] SRC1[31:0] * SRC2[31:0]
DEST[127:64] SRC1[95:64] * SRC2[95:64
DEST[191:128] SRC1[159:128] * SRC2[159:128]
DEST[255:192] SRC1[223:192] * SRC2[223:192]
DEST[VLMAX-1:256] 0
VPMULUDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
PMULUDQ—Multiply Packed Unsigned Doubleword Integers
Vol. 2B 4-383
INSTRUCTION SET REFERENCE, M-U
THEN DEST[i+63:i] ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[31:0] )
ELSE DEST[i+63:i] ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[i+31:i] )
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMULUDQ __m512i _mm512_mul_epu32(__m512i a, __m512i b);
VPMULUDQ __m512i _mm512_mask_mul_epu32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULUDQ __m512i _mm512_maskz_mul_epu32( __mmask8 k, __m512i a, __m512i b);
VPMULUDQ __m256i _mm256_mask_mul_epu32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULUDQ __m256i _mm256_maskz_mul_epu32( __mmask8 k, __m256i a, __m256i b);
VPMULUDQ __m128i _mm_mask_mul_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULUDQ __m128i _mm_maskz_mul_epu32( __mmask8 k, __m128i a, __m128i b);
PMULUDQ:__m64 _mm_mul_su32 (__m64 a, __m64 b)
(V)PMULUDQ:__m128i _mm_mul_epu32 ( __m128i a, __m128i b)
VPMULUDQ:__m256i _mm256_mul_epu32( __m256i a, __m256i b);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
4-384 Vol. 2B
PMULUDQ—Multiply Packed Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, M-U
POP—Pop a Value from the Stack
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
8F /0
POP r/m16
M
Valid
Valid
Pop top of stack into m16; increment stack
pointer.
8F /0
POP r/m32
M
N.E.
Valid
Pop top of stack into m32; increment stack
pointer.
8F /0
POP r/m64
M
Valid
N.E.
Pop top of stack into m64; increment stack
pointer. Cannot encode 32-bit operand size.
58+ rw
POP r16
O
Valid
Valid
Pop top of stack into r16; increment stack
pointer.
58+ rd
POP r32
O
N.E.
Valid
Pop top of stack into r32; increment stack
pointer.
58+ rd
POP r64
O
Valid
N.E.
Pop top of stack into r64; increment stack
pointer. Cannot encode 32-bit operand size.
1F
POP DS
NP
Invalid
Valid
Pop top of stack into DS; increment stack
pointer.
07
POP ES
NP
Invalid
Valid
Pop top of stack into ES; increment stack
pointer.
17
POP SS
NP
Invalid
Valid
Pop top of stack into SS; increment stack
pointer.
0F A1
POP FS
NP
Valid
Valid
Pop top of stack into FS; increment stack
pointer by 16 bits.
0F A1
POP FS
NP
N.E.
Valid
Pop top of stack into FS; increment stack
pointer by 32 bits.
0F A1
POP FS
NP
Valid
N.E.
Pop top of stack into FS; increment stack
pointer by 64 bits.
0F A9
POP GS
NP
Valid
Valid
Pop top of stack into GS; increment stack
pointer by 16 bits.
0F A9
POP GS
NP
N.E.
Valid
Pop top of stack into GS; increment stack
pointer by 32 bits.
0F A9
POP GS
NP
Valid
N.E.
Pop top of stack into GS; increment stack
pointer by 64 bits.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
O
opcode + rd (w)
NA
NA
NA
NP
NA
NA
NA
NA
Description
Loads the value from the top of the stack to the location specified with the destination operand (or explicit opcode)
and then increments the stack pointer. The destination operand can be a general-purpose register, memory location, or segment register.
Address and operand sizes are determined and used as follows:
•
Address size. The D flag in the current code-segment descriptor determines the default address size; it may be
overridden by an instruction prefix (67H).
POP—Pop a Value from the Stack
Vol. 2B 4-385
INSTRUCTION SET REFERENCE, M-U
The address size is used only when writing to a destination operand in memory.
•
Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may
be overridden by instruction prefixes (66H or REX.W).
The operand size (16, 32, or 64 bits) determines the amount by which the stack pointer is incremented (2, 4
or 8).
•
Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the
size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.
The stack-address size determines the width of the stack pointer when reading from the stack in memory and
when incrementing the stack pointer. (As stated above, the amount by which the stack pointer is incremented
is determined by the operand size.)
If the destination operand is one of the segment registers DS, ES, FS, GS, or SS, the value loaded into the register
must be a valid segment selector. In protected mode, popping a segment selector into a segment register automatically causes the descriptor information associated with that segment selector to be loaded into the hidden
(shadow) part of the segment register and causes the selector and the descriptor information to be validated (see
the “Operation” section below).
A NULL value (0000-0003) may be popped into the DS, ES, FS, or GS register without causing a general protection
fault. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded
with a NULL value causes a general protection exception (#GP). In this situation, no memory reference occurs and
the saved value of the segment register is NULL.
The POP instruction cannot pop a value into the CS register. To load the CS register from the stack, use the RET
instruction.
If the ESP register is used as a base register for addressing a destination operand in memory, the POP instruction
computes the effective address of the operand after it increments the ESP register. For the case of a 16-bit stack
where ESP wraps to 0H as a result of the POP instruction, the resulting location of the memory write is processorfamily-specific.
The POP ESP instruction increments the stack pointer (ESP) before data at the old top of stack is written into the
destination.
A POP SS instruction inhibits all interrupts, including the NMI interrupt, until after execution of the next instruction.
This action allows sequential execution of POP SS and MOV ESP, EBP instructions without the danger of having an
invalid stack during an interrupt1. However, use of the LSS instruction is the preferred method of loading the SS
and ESP registers.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). When in
64-bit mode, POPs using 32-bit operands are not encodable and POPs to DS, ES, SS are not valid. See the summary
chart at the beginning of this section for encoding data and limits.
Operation
IF StackAddrSize = 32
THEN
IF OperandSize = 32
THEN
DEST ← SS:ESP; (* Copy a doubleword *)
ESP ← ESP + 4;
ELSE (* OperandSize = 16*)
DEST ← SS:ESP; (* Copy a word *)
1. If a code instruction breakpoint (for debug) is placed on an instruction located immediately after a POP SS instruction, the breakpoint
may not be triggered. However, in a sequence of instructions that POP the SS register, only the first instruction in the sequence is
guaranteed to delay an interrupt.
In the following sequence, interrupts may be recognized before POP ESP executes:
POP SS
POP SS
POP ESP
4-386 Vol. 2B
POP—Pop a Value from the Stack
INSTRUCTION SET REFERENCE, M-U
ESP ← ESP + 2;
FI;
ELSE IF StackAddrSize = 64
THEN
IF OperandSize = 64
THEN
DEST ← SS:RSP; (* Copy quadword *)
RSP ← RSP + 8;
ELSE (* OperandSize = 16*)
DEST ← SS:RSP; (* Copy a word *)
RSP ← RSP + 2;
FI;
FI;
ELSE StackAddrSize = 16
THEN
IF OperandSize = 16
THEN
DEST ← SS:SP; (* Copy a word *)
SP ← SP + 2;
ELSE (* OperandSize = 32 *)
DEST ← SS:SP; (* Copy a doubleword *)
SP ← SP + 4;
FI;
FI;
Loading a segment register while in protected mode results in special actions, as described in the following listing.
These checks are performed on the segment selector and the segment descriptor it points to.
64-BIT_MODE
IF FS, or GS is loaded with non-NULL selector;
THEN
IF segment selector index is outside descriptor table limits
OR segment is not a data or readable code segment
OR ((segment is a data or nonconforming code segment)
AND (both RPL and CPL > DPL))
THEN #GP(selector);
IF segment not marked present
THEN #NP(selector);
ELSE
SegmentRegister ← segment selector;
SegmentRegister ← segment descriptor;
FI;
FI;
IF FS, or GS is loaded with a NULL selector;
THEN
SegmentRegister ← segment selector;
SegmentRegister ← segment descriptor;
FI;
PREOTECTED MODE OR COMPATIBILITY MODE;
IF SS is loaded;
POP—Pop a Value from the Stack
Vol. 2B 4-387
INSTRUCTION SET REFERENCE, M-U
THEN
IF segment selector is NULL
THEN #GP(0);
FI;
IF segment selector index is outside descriptor table limits
or segment selector's RPL ≠ CPL
or segment is not a writable data segment
or DPL ≠ CPL
THEN #GP(selector);
FI;
IF segment not marked present
THEN #SS(selector);
ELSE
SS ← segment selector;
SS ← segment descriptor;
FI;
FI;
IF DS, ES, FS, or GS is loaded with non-NULL selector;
THEN
IF segment selector index is outside descriptor table limits
or segment is not a data or readable code segment
or ((segment is a data or nonconforming code segment)
and (both RPL and CPL > DPL))
THEN #GP(selector);
FI;
IF segment not marked present
THEN #NP(selector);
ELSE
SegmentRegister ← segment selector;
SegmentRegister ← segment descriptor;
FI;
FI;
IF DS, ES, FS, or GS is loaded with a NULL selector
THEN
SegmentRegister ← segment selector;
SegmentRegister ← segment descriptor;
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If attempt is made to load SS register with NULL segment selector.
If the destination operand is in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#GP(selector)
If segment selector index is outside descriptor table limits.
If the SS register is being loaded and the segment selector's RPL and the segment descriptor’s
DPL are not equal to the CPL.
4-388 Vol. 2B
POP—Pop a Value from the Stack
INSTRUCTION SET REFERENCE, M-U
If the SS register is being loaded and the segment pointed to is a
non-writable data segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or
readable code segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or
nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0)
If the current top of stack is not within the stack segment.
If a memory operand effective address is outside the SS segment limit.
#SS(selector)
If the SS register is being loaded and the segment pointed to is marked not present.
#NP
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not
present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If the stack address is in a non-canonical form.
#GP(selector)
If the descriptor is outside the descriptor table limit.
If the FS or GS register is being loaded and the segment pointed to is not a data or readable
code segment.
If the FS or GS register is being loaded and the segment pointed to is a data or nonconforming
code segment, but both the RPL and the CPL are greater than the DPL.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#PF(fault-code)
If a page fault occurs.
#NP
If the FS or GS register is being loaded and the segment pointed to is marked not present.
#UD
If the LOCK prefix is used.
POP—Pop a Value from the Stack
Vol. 2B 4-389
INSTRUCTION SET REFERENCE, M-U
POPA/POPAD—Pop All General-Purpose Registers
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
61
POPA
NP
Invalid
Valid
Pop DI, SI, BP, BX, DX, CX, and AX.
61
POPAD
NP
Invalid
Valid
Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers. The registers are
loaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX (if the operand-size attribute is 32) and DI,
SI, BP, BX, DX, CX, and AX (if the operand-size attribute is 16). (These instructions reverse the operation of the
PUSHA/PUSHAD instructions.) The value on the stack for the ESP or SP register is ignored. Instead, the ESP or SP
register is incremented after each register is loaded.
The POPA (pop all) and POPAD (pop all double) mnemonics reference the same opcode. The POPA instruction is
intended for use when the operand-size attribute is 16 and the POPAD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used
(using the operand-size override prefix [66H] if necessary). Others may treat these mnemonics as synonyms
(POPA/POPAD) and use the current setting of the operand-size attribute to determine the size of values to be
popped from the stack, regardless of the mnemonic used. (The D flag in the current code segment’s segment
descriptor determines the operand-size attribute.)
This instruction executes as described in non-64-bit modes. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
IF OperandSize = 32 (* Instruction = POPAD *)
THEN
EDI ← Pop();
ESI ← Pop();
EBP ← Pop();
Increment ESP by 4; (* Skip next 4 bytes of stack *)
EBX ← Pop();
EDX ← Pop();
ECX ← Pop();
EAX ← Pop();
ELSE (* OperandSize = 16, instruction = POPA *)
DI ← Pop();
SI ← Pop();
BP ← Pop();
Increment ESP by 2; (* Skip next 2 bytes of stack *)
BX ← Pop();
DX ← Pop();
CX ← Pop();
AX ← Pop();
FI;
FI;
4-390 Vol. 2B
POPA/POPAD—Pop All General-Purpose Registers
INSTRUCTION SET REFERENCE, M-U
Flags Affected
None.
Protected Mode Exceptions
#SS(0)
If the starting or ending stack address is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#SS
If the starting or ending stack address is not within the stack segment.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#SS(0)
If the starting or ending stack address is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
POPA/POPAD—Pop All General-Purpose Registers
Vol. 2B 4-391
INSTRUCTION SET REFERENCE, M-U
POPCNT — Return the Count of Number of Bits Set to 1
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F3 0F B8 /r
POPCNT r16, r/m16
RM
Valid
Valid
POPCNT on r/m16
F3 0F B8 /r
POPCNT r32, r/m32
RM
Valid
Valid
POPCNT on r/m32
F3 REX.W 0F B8 /r
POPCNT r64, r/m64
RM
Valid
N.E.
POPCNT on r/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
This instruction calculates the number of bits set to 1 in the second operand (source) and returns the count in the
first operand (a destination register).
Operation
Count = 0;
For (i=0; i < OperandSize; i++)
{
IF (SRC[ i] = 1) // i’th bit
THEN Count++; FI;
}
DEST Count;
Flags Affected
OF, SF, ZF, AF, CF, PF are all cleared. ZF is set if SRC = 0, otherwise ZF is cleared.
Intel C/C++ Compiler Intrinsic Equivalent
POPCNT:
int _mm_popcnt_u32(unsigned int a);
POPCNT:
int64_t _mm_popcnt_u64(unsigned __int64 a);
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
If LOCK prefix is used.
Real-Address Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
If LOCK prefix is used.
4-392 Vol. 2B
POPCNT — Return the Count of Number of Bits Set to 1
INSTRUCTION SET REFERENCE, M-U
Virtual 8086 Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
If LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
If LOCK prefix is used.
POPCNT — Return the Count of Number of Bits Set to 1
Vol. 2B 4-393
INSTRUCTION SET REFERENCE, M-U
POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
9D
POPF
NP
Valid
Valid
Pop top of stack into lower 16 bits of EFLAGS.
9D
POPFD
NP
N.E.
Valid
Pop top of stack into EFLAGS.
9D
POPFQ
NP
Valid
N.E.
Pop top of stack and zero-extend into RFLAGS.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the
value in the EFLAGS register, or pops a word from the top of the stack (if the operand-size attribute is 16) and
stores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). These instructions reverse the
operation of the PUSHF/PUSHFD instructions.
The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction
is intended for use when the operand-size attribute is 16; the POPFD instruction is intended for use when the
operand-size attribute is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD.
Others may treat the mnemonics as synonyms (POPF/POPFD) and use the setting of the operand-size attribute to
determine the size of values to pop from the stack.
The effect of POPF/POPFD on the EFLAGS register changes, depending on the mode of operation. See the Table
4-15 and key below for details.
When operating in protected, compatibility, or 64-bit mode at privilege level 0 (or in real-address mode, the equivalent to privilege level 0), all non-reserved flags in the EFLAGS register except RF1, VIP, VIF, and VM may be modified. VIP, VIF and VM remain unaffected.
When operating in protected, compatibility, or 64-bit mode with a privilege level greater than 0, but less than or
equal to IOPL, all flags can be modified except the IOPL field and RF1, IF, VIP, VIF, and VM; these remain unaffected.
The AC and ID flags can only be modified if the operand-size attribute is 32. The interrupt flag (IF) is altered only
when executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insufficient privilege, an exception does not occur but privileged bits do not change.
When operating in virtual-8086 mode (EFLAGS.VM = 1) without the virtual-8086 mode extensions (CR4.VME = 0),
the POPF/POPFD instructions can be used only if IOPL = 3; otherwise, a general-protection exception (#GP) occurs.
If the virtual-8086 mode extensions are enabled (CR4.VME = 1), POPF (but not POPFD) can be executed in virtual8086 mode with IOPL < 3.
In 64-bit mode, the mnemonic assigned is POPFQ (note that the 32-bit operand is not encodable). POPFQ pops 64
bits from the stack. Reserved bits of RFLAGS (including the upper 32 bits of RFLAGS) are not affected.
See Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about the EFLAGS registers.
1. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clears RF as it begins to execute.
4-394 Vol. 2B
POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register
INSTRUCTION SET REFERENCE, M-U
Table 4-15. Effect of POPF/POPFD on the EFLAGS Register
Flags
Mode
Operand
Size
CPL
Real-Address
Mode (CR0.PE
= 0)
16
0
32
0
Protected,
Compatibility,
and 64-Bit
Modes
16
IOPL
21
20
19
18
17
16
14
13:12
11
10
9
8
7
6
4
2
0
ID
VIP
VIF
AC
VM
RF
NT
IOPL
OF
DF
IF
TF
SF
ZF
AF
PF
CF
0-3
N
N
N
N
N
0
S
S
S
S
S
S
S
S
S
S
S
0-3
S
N
N
S
N
0
S
S
S
S
S
S
S
S
S
S
S
0
0-3
N
N
N
N
N
0
S
S
S
S
S
S
S
S
S
S
S
16
1-3
0 *)
IF OperandSize = 32
THEN
IF CPL > IOPL
THEN
EFLAGS ← Pop(); (* 32-bit pop *)
(* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified;
IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
ELSE
EFLAGS ← Pop(); (* 32-bit pop *)
(* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified;
IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
FI;
ELSE IF (Operandsize = 64)
IF CPL > IOPL
THEN
RFLAGS ← Pop(); (* 64-bit pop *)
(* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified;
IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
ELSE
RFLAGS ← Pop(); (* 64-bit pop *)
(* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified;
IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
FI;
ELSE (* OperandSize = 16 *)
EFLAGS[15:0] ← Pop(); (* 16-bit pop *)
(* All non-reserved bits except IOPL can be modified; IOPL and all
reserved bits are unaffected. *)
FI;
FI;
ELSE IF CR4.VME = 1 (* In Virtual-8086 Mode with VME Enabled *)
IF IOPL = 3
THEN IF OperandSize = 32
THEN
EFLAGS ← Pop();
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
VIP, VIF, VM, IOPL and all reserved bits are unaffected. RF is cleared. *)
ELSE
EFLAGS[15:0] ← Pop(); FI;
(* All non-reserved bits except IOPL can be modified;
IOPL and all reserved bits are unaffected. *)
FI;
ELSE (* IOPL < 3 *)
IF (Operandsize = 32)
THEN
#GP(0); (* Trap to virtual-8086 monitor. *)
ELSE (* Operandsize = 16 *)
tempFLAGS ← Pop();
IF EFLAGS.VIP = 1 AND tempFLAGS[9] = 1
THEN #GP(0);
ELSE
4-396 Vol. 2B
POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register
INSTRUCTION SET REFERENCE, M-U
EFLAGS.VIF ← tempFLAGS[9];
EFLAGS[15:0] ← tempFLAGS;
(* All non-reserved bits except IOPL and IF can be modified;
IOPL, IF, and all reserved bits are unaffected. *)
FI;
FI;
FI;
ELSE (* In Virtual-8086 Mode *)
IF IOPL = 3
THEN IF OperandSize = 32
THEN
EFLAGS ← Pop();
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
VIP, VIF, VM, IOPL and all reserved bits are unaffected. RF is cleared. *)
ELSE
EFLAGS[15:0] ← Pop(); FI;
(* All non-reserved bits except IOPL can be modified;
IOPL and all reserved bits are unaffected. *)
ELSE (* IOPL < 3 *)
#GP(0); (* Trap to virtual-8086 monitor. *)
FI;
FI;
FI;
Flags Affected
All flags may be affected; see the Operation section for details.
Protected Mode Exceptions
#SS(0)
If the top of stack is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#SS
If the top of stack is not within the stack segment.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the I/O privilege level is less than 3.
If an attempt is made to execute the POPF/POPFD instruction with an operand-size override
prefix.
#SS(0)
If the top of stack is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register
Vol. 2B 4-397
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If the stack address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
4-398 Vol. 2B
POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register
INSTRUCTION SET REFERENCE, M-U
POR—Bitwise Logical OR
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F EB /r1
RM
V/V
MMX
Bitwise OR of mm/m64 and mm.
RM
V/V
SSE2
Bitwise OR of xmm2/m128 and xmm1.
RVM V/V
AVX
Bitwise OR of xmm2/m128 and xmm3.
RVM V/V
AVX2
Bitwise OR of ymm2/m256 and ymm3.
EVEX.NDS.128.66.0F.W0 EB /r
VPORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
Bitwise OR of packed doubleword integers in
xmm2 and xmm3/m128/m32bcst using
writemask k1.
EVEX.NDS.256.66.0F.W0 EB /r
VPORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
Bitwise OR of packed doubleword integers in
ymm2 and ymm3/m256/m32bcst using
writemask k1.
EVEX.NDS.512.66.0F.W0 EB /r
VPORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst
FV
V/V
AVX512F
Bitwise OR of packed doubleword integers in
zmm2 and zmm3/m512/m32bcst using
writemask k1.
EVEX.NDS.128.66.0F.W1 EB /r
VPORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
Bitwise OR of packed quadword integers in
xmm2 and xmm3/m128/m64bcst using
writemask k1.
EVEX.NDS.256.66.0F.W1 EB /r
VPORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
Bitwise OR of packed quadword integers in
ymm2 and ymm3/m256/m64bcst using
writemask k1.
EVEX.NDS.512.66.0F.W1 EB /r
VPORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst
FV
V/V
AVX512F
Bitwise OR of packed quadword integers in
zmm2 and zmm3/m512/m64bcst using
writemask k1.
POR mm, mm/m64
66 0F EB /r
POR xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG EB /r
VPOR xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG EB /r
VPOR ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand (first
operand) and stores the result in the destination operand. Each bit of the result is set to 1 if either or both of the
corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
POR—Bitwise Logical OR
Vol. 2B 4-399
INSTRUCTION SET REFERENCE, M-U
Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand is an MMX technology register.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source and destination operands can be XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source and destination operands can be XMM registers. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first
source and destination operands can be YMM registers.
EVEX encoded version: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1 at 32/64-bit granularity.
Operation
POR (64-bit operand)
DEST DEST OR SRC
POR (128-bit Legacy SSE version)
DEST DEST OR SRC
DEST[VLMAX-1:128] (Unmodified)
VPOR (VEX.128 encoded version)
DEST SRC1 OR SRC2
DEST[VLMAX-1:128] 0
VPOR (VEX.256 encoded version)
DEST SRC1 OR SRC2
DEST[VLMAX-1:256] 0
VPORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SRC1[i+31:i] BITWISE OR SRC2[31:0]
ELSE DEST[i+31:i] SRC1[i+31:i] BITWISE OR SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
*DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
4-400 Vol. 2B
POR—Bitwise Logical OR
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VPORD __m512i _mm512_or_epi32(__m512i a, __m512i b);
VPORD __m512i _mm512_mask_or_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPORD __m512i _mm512_maskz_or_epi32( __mmask16 k, __m512i a, __m512i b);
VPORD __m256i _mm256_or_epi32(__m256i a, __m256i b);
VPORD __m256i _mm256_mask_or_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b,);
VPORD __m256i _mm256_maskz_or_epi32( __mmask8 k, __m256i a, __m256i b);
VPORD __m128i _mm_or_epi32(__m128i a, __m128i b);
VPORD __m128i _mm_mask_or_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPORD __m128i _mm_maskz_or_epi32( __mmask8 k, __m128i a, __m128i b);
VPORQ __m512i _mm512_or_epi64(__m512i a, __m512i b);
VPORQ __m512i _mm512_mask_or_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPORQ __m512i _mm512_maskz_or_epi64(__mmask8 k, __m512i a, __m512i b);
VPORQ __m256i _mm256_or_epi64(__m256i a, int imm);
VPORQ __m256i _mm256_mask_or_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPORQ __m256i _mm256_maskz_or_epi64( __mmask8 k, __m256i a, __m256i b);
VPORQ __m128i _mm_or_epi64(__m128i a, __m128i b);
VPORQ __m128i _mm_mask_or_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPORQ __m128i _mm_maskz_or_epi64( __mmask8 k, __m128i a, __m128i b);
POR __m64 _mm_or_si64(__m64 m1, __m64 m2)
(V)POR: __m128i _mm_or_si128(__m128i m1, __m128i m2)
VPOR: __m256i _mm256_or_si256 ( __m256i a, __m256i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
POR—Bitwise Logical OR
Vol. 2B 4-401
INSTRUCTION SET REFERENCE, M-U
PREFETCHh—Prefetch Data Into Caches
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 18 /1
PREFETCHT0 m8
M
Valid
Valid
Move data from m8 closer to the processor
using T0 hint.
0F 18 /2
PREFETCHT1 m8
M
Valid
Valid
Move data from m8 closer to the processor
using T1 hint.
0F 18 /3
PREFETCHT2 m8
M
Valid
Valid
Move data from m8 closer to the processor
using T2 hint.
0F 18 /0
PREFETCHNTA m8
M
Valid
Valid
Move data from m8 closer to the processor
using NTA hint.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Fetches the line of data from memory that contains the byte specified with the source operand to a location in the
cache hierarchy specified by a locality hint:
•
•
•
T0 (temporal data)—prefetch data into all levels of the cache hierarchy.
•
NTA (non-temporal data with respect to all cache levels)—prefetch data into non-temporal cache structure and
into a location close to the processor, minimizing cache pollution.
T1 (temporal data with respect to first level cache misses)—prefetch data into level 2 cache and higher.
T2 (temporal data with respect to second level cache misses)—prefetch data into level 3 cache and higher, or
an implementation-specific choice.
The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction
using bits 3 through 5 of the ModR/M byte.)
If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement
occurs. Prefetches from uncacheable or WC memory are ignored.
The PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor in anticipation of future use.
The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,
however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are
described in Section 7.4 of Intel® 64 and IA-32 Architectures Optimization Reference Manual.
It should be noted that processors are free to speculatively fetch and cache data from system memory regions that
are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A
PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur
at any time and is not tied to instruction execution, a PREFETCHh instruction is not ordered with respect to the
fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHh instruction is also
unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHh instructions, or any other
general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
FETCH (m8);
4-402 Vol. 2B
PREFETCHh—Prefetch Data Into Caches
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_prefetch(char *p, int i)
The argument “*p” gives the address of the byte (and corresponding cache line) to be prefetched. The value “i”
gives a constant (_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, or _MM_HINT_NTA) that specifies the type of
prefetch operation to be performed.
Numeric Exceptions
None.
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
PREFETCHh—Prefetch Data Into Caches
Vol. 2B 4-403
INSTRUCTION SET REFERENCE, M-U
PREFETCHW—Prefetch Data into Caches in Anticipation of a Write
Opcode/
Instruction
Op/
En
0F 0D /1
PREFETCHW m8
A
64/32 bit
Mode
Support
V/V
CPUID
Feature
Flag
PRFCHW
Description
Move data from m8 closer to the processor in anticipation of a
write.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Fetches the cache line of data from memory that contains the byte specified with the source operand to a location
in the 1st or 2nd level cache and invalidates other cached instances of the line.
The source operand is a byte memory location. If the line selected is already present in the lowest level cache and
is already in an exclusively owned state, no data movement occurs. Prefetches from non-writeback memory are
ignored.
The PREFETCHW instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor and invalidates other cached copies in anticipation of the line being written to
in the future.
The characteristic of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,
however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are
described in Section 7.4 of Intel® 64 and IA-32 Architectures Optimization Reference Manual.
It should be noted that processors are free to speculatively fetch and cache data with exclusive ownership from
system memory regions that permit such accesses (that is, the WB memory type). A PREFETCHW instruction is
considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not
tied to instruction execution, a PREFETCHW instruction is not ordered with respect to the fence instructions
(MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHW instruction is also unordered with
respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHW instructions, or any other general instruction
It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
Operation
FETCH_WITH_EXCLUSIVE_OWNERSHIP (m8);
Flags Affected
All flags are affected
C/C++ Compiler Intrinsic Equivalent
void _m_prefetchw( void * );
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
4-404 Vol. 2B
If the LOCK prefix is used.
PREFETCHW—Prefetch Data into Caches in Anticipation of a Write
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
PREFETCHW—Prefetch Data into Caches in Anticipation of a Write
Vol. 2B 4-405
INSTRUCTION SET REFERENCE, M-U
PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint
Opcode/
Instruction
Op/
En
0F 0D /2
PREFETCHWT1 m8
M
64/32 bit
Mode
Support
V/V
CPUID Feature
Flag
Description
PREFETCHWT1
Move data from m8 closer to the processor using T1 hint
with intent to write.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Fetches the line of data from memory that contains the byte specified with the source operand to a location in the
cache hierarchy specified by an intent to write hint (so that data is brought into ‘Exclusive’ state via a request for
ownership) and a locality hint:
• T1 (temporal data with respect to first level cache)—prefetch data into the second level cache.
The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction
using bits 3 through 5 of the ModR/M byte. Use of any ModR/M value other than the specified ones will lead to
unpredictable behavior.)
If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement
occurs. Prefetches from uncacheable or WC memory are ignored.
The PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor in anticipation of future use.
The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,
however, be a minimum of 32 bytes.
It should be noted that processors are free to speculatively fetch and cache data from system memory regions that
are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A
PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur
at any time and is not tied to instruction execution, a PREFETCHh instruction is not ordered with respect to the
fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHh instruction is also
unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHh instructions, or any other
general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request
for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.
Prefetch (m8, Level = 1, EXCLUSIVE=1);
Flags Affected
All flags are affected
C/C++ Compiler Intrinsic Equivalent
void _mm_prefetch( char const *, int hint= _MM_HINT_ET1);
Protected Mode Exceptions
#UD
4-406 Vol. 2B
If the LOCK prefix is used.
PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint
Vol. 2B 4-407
INSTRUCTION SET REFERENCE, M-U
PSADBW—Compute Sum of Absolute Differences
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID Feature Description
Flag
0F F6 /r1
RM
V/V
SSE
Computes the absolute differences of the
packed unsigned byte integers from mm2
/m64 and mm1; differences are then summed
to produce an unsigned word integer result.
RM
V/V
SSE2
Computes the absolute differences of the
packed unsigned byte integers from xmm2
/m128 and xmm1; the 8 low differences and 8
high differences are then summed separately
to produce two unsigned word integer results.
RVM V/V
AVX
Computes the absolute differences of the
packed unsigned byte integers from xmm3
/m128 and xmm2; the 8 low differences and 8
high differences are then summed separately
to produce two unsigned word integer results.
RVM V/V
AVX2
Computes the absolute differences of the
packed unsigned byte integers from ymm3
/m256 and ymm2; then each consecutive 8
differences are summed separately to produce
four unsigned word integer results.
EVEX.NDS.128.66.0F.WIG F6 /r
VPSADBW xmm1, xmm2, xmm3/m128
FVM V/V
AVX512VL
AVX512BW
Computes the absolute differences of the
packed unsigned byte integers from xmm3
/m128 and xmm2; then each consecutive 8
differences are summed separately to produce
four unsigned word integer results.
EVEX.NDS.256.66.0F.WIG F6 /r
VPSADBW ymm1, ymm2, ymm3/m256
FVM V/V
AVX512VL
AVX512BW
Computes the absolute differences of the
packed unsigned byte integers from ymm3
/m256 and ymm2; then each consecutive 8
differences are summed separately to produce
four unsigned word integer results.
EVEX.NDS.512.66.0F.WIG F6 /r
VPSADBW zmm1, zmm2, zmm3/m512
FVM V/V
AVX512BW
Computes the absolute differences of the
packed unsigned byte integers from zmm3
/m512 and zmm2; then each consecutive 8
differences are summed separately to produce
four unsigned word integer results.
PSADBW mm1, mm2/m64
66 0F F6 /r
PSADBW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG F6 /r
VPSADBW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG F6 /r
VPSADBW ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Computes the absolute value of the difference of 8 unsigned byte integers from the source operand (second
4-408 Vol. 2B
PSADBW—Compute Sum of Absolute Differences
INSTRUCTION SET REFERENCE, M-U
operand) and from the destination operand (first operand). These 8 differences are then summed to produce an
unsigned word integer result that is stored in the destination operand. Figure 4-14 shows the operation of the
PSADBW instruction when using 64-bit operands.
When operating on 64-bit operands, the word integer result is stored in the low word of the destination operand,
and the remaining bytes in the destination operand are cleared to all 0s.
When operating on 128-bit operands, two packed results are computed. Here, the 8 low-order bytes of the source
and destination operands are operated on to produce a word result that is stored in the low word of the destination
operand, and the 8 high-order bytes are operated on to produce a word result that is stored in bits 64 through 79
of the destination operand. The remaining bytes of the destination operand are cleared.
For 256-bit version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of
the destination register and the fourth group of 8 differences are summed to produce an unsigned word in
bits[207:192] of the destination register. The remaining words of the destination are set to 0.
For 512-bit version, the fifth group result is stored in bits [271:256] of the destination. The result from the sixth
group is stored in bits [335:320]. The results for the seventh and eighth group are stored respectively in bits
[399:384] and bits [463:447], respectively. The remaining bits in the destination are set to 0.
In 64-bit mode and not encoded by VEX/EVEX prefix, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).
Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM
destination register remain unchanged.
VEX.128 and EVEX.128 encoded versions: The first source operand and destination register are XMM registers. The
second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
VEX.256 and EVEX.256 encoded versions: The first source operand and destination register are YMM registers. The
second source operand is an YMM register or a 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The first source operand and destination register are ZMM registers. The second
source operand is a ZMM register or a 512-bit memory location.
SRC
X7
X6
X5
X4
X3
X2
X1
X0
DEST
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
TEMP
DEST
ABS(X7:Y7) ABS(X6:Y6) ABS(X5:Y5) ABS(X4:Y4) ABS(X3:Y3) ABS(X2:Y2) ABS(X1:Y1) ABS(X0:Y0)
00H
00H
00H
00H
00H
00H
SUM(TEMP7...TEMP0)
Figure 4-14. PSADBW Instruction Operation Using 64-bit Operands
Operation
VPSADBW (EVEX encoded versions)
VL = 128, 256, 512
TEMP0 ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 1 through 15 *)
TEMP15 ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] SUM(TEMP0:TEMP7)
DEST[63:16] 000000000000H
PSADBW—Compute Sum of Absolute Differences
Vol. 2B 4-409
INSTRUCTION SET REFERENCE, M-U
DEST[79:64] SUM(TEMP8:TEMP15)
DEST[127:80] 00000000000H
IF VL >= 256
(* Repeat operation for bytes 16 through 31*)
TEMP31 ABS(SRC1[255:248] - SRC2[255:248])
DEST[143:128] SUM(TEMP16:TEMP23)
DEST[191:144] 000000000000H
DEST[207:192] SUM(TEMP24:TEMP31)
DEST[223:208] 00000000000H
FI;
IF VL >= 512
(* Repeat operation for bytes 32 through 63*)
TEMP63 ABS(SRC1[511:504] - SRC2[511:504])
DEST[271:256] SUM(TEMP0:TEMP7)
DEST[319:272] 000000000000H
DEST[335:320] SUM(TEMP8:TEMP15)
DEST[383:336] 00000000000H
DEST[399:384] SUM(TEMP16:TEMP23)
DEST[447:400] 000000000000H
DEST[463:448] SUM(TEMP24:TEMP31)
DEST[511:464] 00000000000H
FI;
DEST[MAX_VL-1:VL] 0
VPSADBW (VEX.256 encoded version)
TEMP0 ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 30*)
TEMP31 ABS(SRC1[255:248] - SRC2[255:248])
DEST[15:0] SUM(TEMP0:TEMP7)
DEST[63:16] 000000000000H
DEST[79:64] SUM(TEMP8:TEMP15)
DEST[127:80] 00000000000H
DEST[143:128] SUM(TEMP16:TEMP23)
DEST[191:144] 000000000000H
DEST[207:192] SUM(TEMP24:TEMP31)
DEST[223:208] 00000000000H
DEST[MAX_VL-1:256] 0
4-410 Vol. 2B
PSADBW—Compute Sum of Absolute Differences
INSTRUCTION SET REFERENCE, M-U
VPSADBW (VEX.128 encoded version)
TEMP0 ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] SUM(TEMP0:TEMP7)
DEST[63:16] 000000000000H
DEST[79:64] SUM(TEMP8:TEMP15)
DEST[127:80] 00000000000H
DEST[MAX_VL-1:128] 0
PSADBW (128-bit Legacy SSE version)
TEMP0 ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 ABS(DEST[127:120] - SRC[127:120])
DEST[15:0] SUM(TEMP0:TEMP7)
DEST[63:16] 000000000000H
DEST[79:64] SUM(TEMP8:TEMP15)
DEST[127:80] 00000000000
DEST[MAX_VL-1:128] (Unmodified)
PSADBW (64-bit operand)
TEMP0 ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 6 *)
TEMP7 ABS(DEST[63:56] - SRC[63:56])
DEST[15:0] SUM(TEMP0:TEMP7)
DEST[63:16] 000000000000H
Intel C/C++ Compiler Intrinsic Equivalent
VPSADBW __m512i _mm512_sad_epu8( __m512i a, __m512i b)
PSADBW:__m64 _mm_sad_pu8(__m64 a,__m64 b)
(V)PSADBW:__m128i _mm_sad_epu8(__m128i a, __m128i b)
VPSADBW:__m256i _mm256_sad_epu8( __m256i a, __m256i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
PSADBW—Compute Sum of Absolute Differences
Vol. 2B 4-411
INSTRUCTION SET REFERENCE, M-U
PSHUFB — Packed Shuffle Bytes
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 00 /r1
RM
V/V
SSSE3
Shuffle bytes in mm1 according to contents of
mm2/m64.
RM
V/V
SSSE3
Shuffle bytes in xmm1 according to contents of
xmm2/m128.
RVM V/V
AVX
Shuffle bytes in xmm2 according to contents of
xmm3/m128.
RVM V/V
AVX2
Shuffle bytes in ymm2 according to contents of
ymm3/m256.
EVEX.NDS.128.66.0F38.WIG 00 /r
VPSHUFB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Shuffle bytes in xmm2 according to contents of
AVX512BW xmm3/m128 under write mask k1.
EVEX.NDS.256.66.0F38.WIG 00 /r
VPSHUFB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Shuffle bytes in ymm2 according to contents of
AVX512BW ymm3/m256 under write mask k1.
EVEX.NDS.512.66.0F38.WIG 00 /r
VPSHUFB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Shuffle bytes in zmm2 according to contents of
zmm3/m512 under write mask k1.
PSHUFB mm1, mm2/m64
66 0F 38 00 /r
PSHUFB xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 00 /r
VPSHUFB xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 00 /r
VPSHUFB ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
PSHUFB performs in-place shuffles of bytes in the destination operand (the first operand) according to the shuffle
control mask in the source operand (the second operand). The instruction permutes the data in the destination
operand, leaving the shuffle mask unaffected. If the most significant bit (bit[7]) of each byte of the shuffle control
mask is set, then constant zero is written in the result byte. Each byte in the shuffle control mask forms an index
to permute the corresponding byte in the destination operand. The value of each index is the least significant 4 bits
(128-bit operation) or 3 bits (64-bit operation) of the shuffle control byte. When the source operand is a 128-bit
memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will
be generated.
In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.
Legacy SSE version 64-bit operand: Both operands can be MMX registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The destination operand is the first operand, the first source operand is the second
operand, the second source operand is the third operand. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: Bits (255:128) of the destination YMM register stores the 16-byte shuffle result of the
upper 16 bytes of the first source operand, using the upper 16-bytes of the second source operand as control mask.
4-412 Vol. 2B
PSHUFB — Packed Shuffle Bytes
INSTRUCTION SET REFERENCE, M-U
The value of each index is for the high 128-bit lane is the least significant 4 bits of the respective shuffle control
byte. The index value selects a source data element within each 128-bit lane.
EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.
EVEX and VEX encoded version: Four/two in-lane 128-bit shuffles.
Operation
PSHUFB (with 64 bit operands)
TEMP ← DEST
for i = 0 to 7 {
if (SRC[(i * 8)+7] = 1 ) then
DEST[(i*8)+7...(i*8)+0] ← 0;
else
index[2..0] ← SRC[(i*8)+2 .. (i*8)+0];
DEST[(i*8)+7...(i*8)+0] ← TEMP[(index*8+7)..(index*8+0)];
endif;
}
PSHUFB (with 128 bit operands)
TEMP ← DEST
for i = 0 to 15 {
if (SRC[(i * 8)+7] = 1 ) then
DEST[(i*8)+7..(i*8)+0] ← 0;
else
index[3..0] ← SRC[(i*8)+3 .. (i*8)+0];
DEST[(i*8)+7..(i*8)+0] ← TEMP[(index*8+7)..(index*8+0)];
endif
}
VPSHUFB (VEX.128 encoded version)
for i = 0 to 15 {
if (SRC2[(i * 8)+7] = 1) then
DEST[(i*8)+7..(i*8)+0] 0;
else
index[3..0] SRC2[(i*8)+3 .. (i*8)+0];
DEST[(i*8)+7..(i*8)+0] SRC1[(index*8+7)..(index*8+0)];
endif
}
DEST[VLMAX-1:128] 0
VPSHUFB (VEX.256 encoded version)
for i = 0 to 15 {
if (SRC2[(i * 8)+7] == 1 ) then
DEST[(i*8)+7..(i*8)+0] 0;
else
index[3..0] SRC2[(i*8)+3 .. (i*8)+0];
DEST[(i*8)+7..(i*8)+0] SRC1[(index*8+7)..(index*8+0)];
endif
if (SRC2[128 + (i * 8)+7] == 1 ) then
DEST[128 + (i*8)+7..(i*8)+0] 0;
else
index[3..0] SRC2[128 + (i*8)+3 .. (i*8)+0];
DEST[128 + (i*8)+7..(i*8)+0] SRC1[128 + (index*8+7)..(index*8+0)];
PSHUFB — Packed Shuffle Bytes
Vol. 2B 4-413
INSTRUCTION SET REFERENCE, M-U
endif
}
VPSHUFB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
jmask (KL-1) & ~0xF
FOR j = 0 TO KL-1
IF kl[ i ] or no_masking
index src.byte[ j ];
IF index & 0x80
Dest.byte[ j ] 0;
ELSE
index (index & 0xF) + (j & jmask);
Dest.byte[ j ] src.byte[ index ];
ELSE if zeroing
Dest.byte[ j ] 0;
DEST[MAX_VL-1:VL] 0;
// 0x00, 0x10, 0x30 depending on the VL
// dest
// 16-element in-lane lookup
MM2
07H
07H
FFH
80H
01H
00H
00H
00H
02H
02H
FFH
01H
01H
01H
MM1
04H
01H
07H
03H
MM1
04H
04H
00H
00H
FFH
01H
Figure 4-15. PSHUFB with 64-Bit Operands
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFB __m512i _mm512_shuffle_epi8(__m512i a, __m512i b);
VPSHUFB __m512i _mm512_mask_shuffle_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m512i _mm512_maskz_shuffle_epi8( __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m256i _mm256_mask_shuffle_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m256i _mm256_maskz_shuffle_epi8( __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m128i _mm_mask_shuffle_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSHUFB __m128i _mm_maskz_shuffle_epi8( __mmask16 k, __m128i a, __m128i b);
PSHUFB: __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
(V)PSHUFB: __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
VPSHUFB:__m256i _mm256_shuffle_epi8(__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
4-414 Vol. 2B
PSHUFB — Packed Shuffle Bytes
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
PSHUFB — Packed Shuffle Bytes
Vol. 2B 4-415
INSTRUCTION SET REFERENCE, M-U
PSHUFD—Shuffle Packed Doublewords
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 70 /r ib
RMI
V/V
SSE2
Shuffle the doublewords in xmm2/m128 based on
the encoding in imm8 and store the result in xmm1.
RMI
V/V
AVX
Shuffle the doublewords in xmm2/m128 based on
the encoding in imm8 and store the result in xmm1.
RMI
V/V
AVX2
Shuffle the doublewords in ymm2/m256 based on
the encoding in imm8 and store the result in ymm1.
EVEX.128.66.0F.W0 70 /r ib
VPSHUFD xmm1 {k1}{z}, xmm2/m128/m32bcst,
imm8
FV
V/V
AVX512VL Shuffle the doublewords in xmm2/m128/m32bcst
AVX512F based on the encoding in imm8 and store the result
in xmm1 using writemask k1.
EVEX.256.66.0F.W0 70 /r ib
VPSHUFD ymm1 {k1}{z}, ymm2/m256/m32bcst,
imm8
FV
V/V
AVX512VL Shuffle the doublewords in ymm2/m256/m32bcst
AVX512F based on the encoding in imm8 and store the result
in ymm1 using writemask k1.
EVEX.512.66.0F.W0 70 /r ib
VPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst,
imm8
FV
V/V
AVX512F
PSHUFD xmm1, xmm2/m128, imm8
VEX.128.66.0F.WIG 70 /r ib
VPSHUFD xmm1, xmm2/m128, imm8
VEX.256.66.0F.WIG 70 /r ib
VPSHUFD ymm1, ymm2/m256, imm8
Shuffle the doublewords in zmm2/m512/m32bcst
based on the encoding in imm8 and store the result
in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Copies doublewords from source operand (second operand) and inserts them in the destination operand (first
operand) at the locations selected with the order operand (third operand). Figure 4-16 shows the operation of the
256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects
the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination
operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high
128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand
(see the field encoding in Figure 4-16) determines which doubleword element (from the respective 128-bit lane) of
the source operand will be copied to doubleword 0 of the destination operand.
For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a
128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate.
Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword
location in the destination operand.
4-416 Vol. 2B
PSHUFD—Shuffle Packed Doublewords
INSTRUCTION SET REFERENCE, M-U
SRC
DEST
X7
Y7
Encoding
of Fields in
ORDER
Operand
X6
Y6
00B - X4
01B - X5
10B - X6
11B - X7
X5
Y5
X4
Y4
X3
X2
X1
X0
Y3
Y2
Y1
Y0
ORDER
7 6 5 4 3 2 1
0
Encoding
of Fields in
ORDER
Operand
00B - X0
01B - X1
10B - X2
11B - X3
Figure 4-16. 256-bit VPSHUFD Instruction Operation
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM
register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source
operand to be copied to more than one doubleword location in the destination operand.
In 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
VEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destination operand is an YMM register. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed. Bits (2551:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the immediate byte as the order operand.
EVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
Each 128-bit lane of the destination stores the shuffled results of the respective lane of the source operand using
the immediate byte as the order operand.
Note: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFD (128-bit Legacy SSE version)
DEST[31:0] (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] (Unmodified)
VPSHUFD (VEX.128 encoded version)
DEST[31:0] (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] 0
PSHUFD—Shuffle Packed Doublewords
Vol. 2B 4-417
INSTRUCTION SET REFERENCE, M-U
VPSHUFD (VEX.256 encoded version)
DEST[31:0] (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
DEST[159:128] (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
DEST[191:160] (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
DEST[223:192] (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
DEST[255:224] (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:256] 0
VPSHUFD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+31:i] SRC[31:0]
ELSE TMP_SRC[i+31:i] SRC[i+31:i]
FI;
ENDFOR;
IF VL >= 128
TMP_DEST[31:0] (TMP_SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[63:32] (TMP_SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[95:64] (TMP_SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[127:96] (TMP_SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
FI;
IF VL >= 256
TMP_DEST[159:128] (TMP_SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[191:160] (TMP_SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[223:192] (TMP_SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[255:224] (TMP_SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
FI;
IF VL >= 512
TMP_DEST[287:256] (TMP_SRC[383:256] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[319:288] (TMP_SRC[383:256] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[351:320] (TMP_SRC[383:256] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[383:352] (TMP_SRC[383:256] >> (ORDER[7:6] * 32))[31:0];
TMP_DEST[415:384] (TMP_SRC[511:384] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[447:416] (TMP_SRC[511:384] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[479:448] (TMP_SRC[511:384] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[511:480] (TMP_SRC[511:384] >> (ORDER[7:6] * 32))[31:0];
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
4-418 Vol. 2B
PSHUFD—Shuffle Packed Doublewords
INSTRUCTION SET REFERENCE, M-U
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );
VPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );
VPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );
VPSHUFD __m128i _mm_mask_shuffle_epi32(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );
(V)PSHUFD:__m128i _mm_shuffle_epi32(__m128i a, int n)
VPSHUFD:__m256i _mm256_shuffle_epi32(__m256i a, const int n)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD
If VEX.vvvv ≠ 1111B or EVEX.vvvv ≠ 1111B.
PSHUFD—Shuffle Packed Doublewords
Vol. 2B 4-419
INSTRUCTION SET REFERENCE, M-U
PSHUFHW—Shuffle Packed High Words
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
F3 0F 70 /r ib
RMI
V/V
SSE2
Shuffle the high words in xmm2/m128 based
on the encoding in imm8 and store the result in
xmm1.
RMI
V/V
AVX
Shuffle the high words in xmm2/m128 based
on the encoding in imm8 and store the result in
xmm1.
RMI
V/V
AVX2
Shuffle the high words in ymm2/m256 based
on the encoding in imm8 and store the result in
ymm1.
PSHUFHW xmm1, xmm2/m128, imm8
VEX.128.F3.0F.WIG 70 /r ib
VPSHUFHW xmm1, xmm2/m128, imm8
VEX.256.F3.0F.WIG 70 /r ib
VPSHUFHW ymm1, ymm2/m256, imm8
EVEX.128.F3.0F.WIG 70 /r ib
VPSHUFHW xmm1 {k1}{z}, xmm2/m128, imm8
FVM V/V
AVX512VL Shuffle the high words in xmm2/m128 based
AVX512BW on the encoding in imm8 and store the result in
xmm1 under write mask k1.
EVEX.256.F3.0F.WIG 70 /r ib
VPSHUFHW ymm1 {k1}{z}, ymm2/m256, imm8
FVM V/V
AVX512VL Shuffle the high words in ymm2/m256 based
AVX512BW on the encoding in imm8 and store the result in
ymm1 under write mask k1.
EVEX.512.F3.0F.WIG 70 /r ib
VPSHUFHW zmm1 {k1}{z}, zmm2/m512, imm8
FVM V/V
AVX512BW Shuffle the high words in zmm2/m512 based
on the encoding in imm8 and store the result in
zmm1 under write mask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
FVM
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Copies words from the high quadword of a 128-bit lane of the source operand and inserts them in the high quadword of the destination operand at word locations (of the respective lane) selected with the immediate operand.
This 256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illustrated in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate
operand selects the contents of one word location in the high quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3, 4) from the high quadword of the source
operand to be copied to the destination operand. The low quadword of the source operand is copied to the low
quadword of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the high quadword of the source operand to be copied to more than one
word location in the high quadword of the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM
register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv is
reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register
or a 256-bit memory location.
4-420 Vol. 2B
PSHUFHW—Shuffle Packed High Words
INSTRUCTION SET REFERENCE, M-U
EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.
Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFHW (128-bit Legacy SSE version)
DEST[63:0] SRC[63:0]
DEST[79:64] (SRC >> (imm[1:0] *16))[79:64]
DEST[95:80] (SRC >> (imm[3:2] * 16))[79:64]
DEST[111:96] (SRC >> (imm[5:4] * 16))[79:64]
DEST[127:112] (SRC >> (imm[7:6] * 16))[79:64]
DEST[VLMAX-1:128] (Unmodified)
VPSHUFHW (VEX.128 encoded version)
DEST[63:0] SRC1[63:0]
DEST[79:64] (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[VLMAX-1:128] 0
VPSHUFHW (VEX.256 encoded version)
DEST[63:0] SRC1[63:0]
DEST[79:64] (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[191:128] SRC1[191:128]
DEST[207192] (SRC1 >> (imm[1:0] *16))[207:192]
DEST[223:208] (SRC1 >> (imm[3:2] * 16))[207:192]
DEST[239:224] (SRC1 >> (imm[5:4] * 16))[207:192]
DEST[255:240] (SRC1 >> (imm[7:6] * 16))[207:192]
DEST[VLMAX-1:256] 0
VPSHUFHW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL >= 128
TMP_DEST[63:0] SRC1[63:0]
TMP_DEST[79:64] (SRC1 >> (imm[1:0] *16))[79:64]
TMP_DEST[95:80] (SRC1 >> (imm[3:2] * 16))[79:64]
TMP_DEST[111:96] (SRC1 >> (imm[5:4] * 16))[79:64]
TMP_DEST[127:112] (SRC1 >> (imm[7:6] * 16))[79:64]
FI;
IF VL >= 256
TMP_DEST[191:128] SRC1[191:128]
TMP_DEST[207:192] (SRC1 >> (imm[1:0] *16))[207:192]
TMP_DEST[223:208] (SRC1 >> (imm[3:2] * 16))[207:192]
TMP_DEST[239:224] (SRC1 >> (imm[5:4] * 16))[207:192]
TMP_DEST[255:240] (SRC1 >> (imm[7:6] * 16))[207:192]
FI;
IF VL >= 512
TMP_DEST[319:256] SRC1[319:256]
TMP_DEST[335:320] (SRC1 >> (imm[1:0] *16))[335:320]
PSHUFHW—Shuffle Packed High Words
Vol. 2B 4-421
INSTRUCTION SET REFERENCE, M-U
TMP_DEST[351:336] (SRC1 >> (imm[3:2] * 16))[335:320]
TMP_DEST[367:352] (SRC1 >> (imm[5:4] * 16))[335:320]
TMP_DEST[383:368] (SRC1 >> (imm[7:6] * 16))[335:320]
TMP_DEST[447:384] SRC1[447:384]
TMP_DEST[463:448] (SRC1 >> (imm[1:0] *16))[463:448]
TMP_DEST[479:464] (SRC1 >> (imm[3:2] * 16))[463:448]
TMP_DEST[495:480] (SRC1 >> (imm[5:4] * 16))[463:448]
TMP_DEST[511:496] (SRC1 >> (imm[7:6] * 16))[463:448]
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i];
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFHW __m512i _mm512_shufflehi_epi16(__m512i a, int n);
VPSHUFHW __m512i _mm512_mask_shufflehi_epi16(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFHW __m512i _mm512_maskz_shufflehi_epi16( __mmask16 k, __m512i a, int n );
VPSHUFHW __m256i _mm256_mask_shufflehi_epi16(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFHW __m256i _mm256_maskz_shufflehi_epi16( __mmask8 k, __m256i a, int n );
VPSHUFHW __m128i _mm_mask_shufflehi_epi16(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFHW __m128i _mm_maskz_shufflehi_epi16( __mmask8 k, __m128i a, int n );
(V)PSHUFHW:__m128i _mm_shufflehi_epi16(__m128i a, int n)
VPSHUFHW:__m256i _mm256_shufflehi_epi16(__m256i a, const int n)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb
#UD
4-422 Vol. 2B
If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.
PSHUFHW—Shuffle Packed High Words
INSTRUCTION SET REFERENCE, M-U
PSHUFLW—Shuffle Packed Low Words
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
F2 0F 70 /r ib
RMI
V/V
SSE2
Shuffle the low words in xmm2/m128 based on
the encoding in imm8 and store the result in
xmm1.
RMI
V/V
AVX
Shuffle the low words in xmm2/m128 based on
the encoding in imm8 and store the result in
xmm1.
RMI
V/V
AVX2
Shuffle the low words in ymm2/m256 based on
the encoding in imm8 and store the result in
ymm1.
PSHUFLW xmm1, xmm2/m128, imm8
VEX.128.F2.0F.WIG 70 /r ib
VPSHUFLW xmm1, xmm2/m128, imm8
VEX.256.F2.0F.WIG 70 /r ib
VPSHUFLW ymm1, ymm2/m256, imm8
EVEX.128.F2.0F.WIG 70 /r ib
VPSHUFLW xmm1 {k1}{z}, xmm2/m128, imm8
FVM V/V
AVX512VL Shuffle the low words in xmm2/m128 based on
AVX512BW the encoding in imm8 and store the result in
xmm1 under write mask k1.
EVEX.256.F2.0F.WIG 70 /r ib
VPSHUFLW ymm1 {k1}{z}, ymm2/m256, imm8
FVM V/V
AVX512VL Shuffle the low words in ymm2/m256 based on
AVX512BW the encoding in imm8 and store the result in
ymm1 under write mask k1.
EVEX.512.F2.0F.WIG 70 /r ib
VPSHUFLW zmm1 {k1}{z}, zmm2/m512, imm8
FVM V/V
AVX512BW Shuffle the low words in zmm2/m512 based on
the encoding in imm8 and store the result in
zmm1 under write mask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
FVM
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Copies words from the low quadword of a 128-bit lane of the source operand and inserts them in the low quadword
of the destination operand at word locations (of the respective lane) selected with the immediate operand. The
256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illustrated
in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate
operand selects the contents of one word location in the low quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3) from the low quadword of the source operand
to be copied to the destination operand. The high quadword of the source operand is copied to the high quadword
of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the low quadword of the source operand to be copied to more than one
word location in the low quadword of the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM
register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register
or a 256-bit memory location.
EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.
PSHUFLW—Shuffle Packed Low Words
Vol. 2B 4-423
INSTRUCTION SET REFERENCE, M-U
Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFLW (128-bit Legacy SSE version)
DEST[15:0] (SRC >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VPSHUFLW (VEX.128 encoded version)
DEST[15:0] (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC[127:64]
DEST[VLMAX-1:128] 0
VPSHUFLW (VEX.256 encoded version)
DEST[15:0] (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC1[127:64]
DEST[143:128] (SRC1 >> (imm[1:0] *16))[143:128]
DEST[159:144] (SRC1 >> (imm[3:2] * 16))[143:128]
DEST[175:160] (SRC1 >> (imm[5:4] * 16))[143:128]
DEST[191:176] (SRC1 >> (imm[7:6] * 16))[143:128]
DEST[255:192] SRC1[255:192]
DEST[VLMAX-1:256] 0
VPSHUFLW (EVEX.U1.512 encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL >= 128
TMP_DEST[15:0] (SRC1 >> (imm[1:0] *16))[15:0]
TMP_DEST[31:16] (SRC1 >> (imm[3:2] * 16))[15:0]
TMP_DEST[47:32] (SRC1 >> (imm[5:4] * 16))[15:0]
TMP_DEST[63:48] (SRC1 >> (imm[7:6] * 16))[15:0]
TMP_DEST[127:64] SRC1[127:64]
FI;
IF VL >= 256
TMP_DEST[143:128] (SRC1 >> (imm[1:0] *16))[143:128]
TMP_DEST[159:144] (SRC1 >> (imm[3:2] * 16))[143:128]
TMP_DEST[175:160] (SRC1 >> (imm[5:4] * 16))[143:128]
TMP_DEST[191:176] (SRC1 >> (imm[7:6] * 16))[143:128]
TMP_DEST[255:192] SRC1[255:192]
FI;
IF VL >= 512
TMP_DEST[271:256] (SRC1 >> (imm[1:0] *16))[271:256]
TMP_DEST[287:272] (SRC1 >> (imm[3:2] * 16))[271:256]
TMP_DEST[303:288] (SRC1 >> (imm[5:4] * 16))[271:256]
TMP_DEST[319:304] (SRC1 >> (imm[7:6] * 16))[271:256]
TMP_DEST[383:320] SRC1[383:320]
4-424 Vol. 2B
PSHUFLW—Shuffle Packed Low Words
INSTRUCTION SET REFERENCE, M-U
TMP_DEST[399:384] (SRC1 >> (imm[1:0] *16))[399:384]
TMP_DEST[415:400] (SRC1 >> (imm[3:2] * 16))[399:384]
TMP_DEST[431:416] (SRC1 >> (imm[5:4] * 16))[399:384]
TMP_DEST[447:432] (SRC1 >> (imm[7:6] * 16))[399:384]
TMP_DEST[511:448] SRC1[511:448]
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i];
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFLW __m512i _mm512_shufflelo_epi16(__m512i a, int n);
VPSHUFLW __m512i _mm512_mask_shufflelo_epi16(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFLW __m512i _mm512_maskz_shufflelo_epi16( __mmask16 k, __m512i a, int n );
VPSHUFLW __m256i _mm256_mask_shufflelo_epi16(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFLW __m256i _mm256_maskz_shufflelo_epi16( __mmask8 k, __m256i a, int n );
VPSHUFLW __m128i _mm_mask_shufflelo_epi16(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFLW __m128i _mm_maskz_shufflelo_epi16( __mmask8 k, __m128i a, int n );
(V)PSHUFLW:__m128i _mm_shufflelo_epi16(__m128i a, int n)
VPSHUFLW:__m256i _mm256_shufflelo_epi16(__m256i a, const int n)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb
#UD
If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.
PSHUFLW—Shuffle Packed Low Words
Vol. 2B 4-425
INSTRUCTION SET REFERENCE, M-U
PSHUFW—Shuffle Packed Words
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 70 /r ib
RMI
Valid
Valid
Shuffle the words in mm2/m64 based on the
encoding in imm8 and store the result in mm1.
PSHUFW mm1, mm2/m64, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
Description
Copies words from the source operand (second operand) and inserts them in the destination operand (first
operand) at word locations selected with the order operand (third operand). This operation is similar to the operation used by the PSHUFD instruction, which is illustrated in Figure 4-16. For the PSHUFW instruction, each 2-bit
field in the order operand selects the contents of one word location in the destination operand. The encodings of the
order operand fields select words from the source operand to be copied to the destination operand.
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
MMX technology register. The order operand is an 8-bit immediate. Note that this instruction permits a word in the
source operand to be copied to more than one word location in the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
Operation
DEST[15:0] ← (SRC >> (ORDER[1:0] * 16))[15:0];
DEST[31:16] ← (SRC >> (ORDER[3:2] * 16))[15:0];
DEST[47:32] ← (SRC >> (ORDER[5:4] * 16))[15:0];
DEST[63:48] ← (SRC >> (ORDER[7:6] * 16))[15:0];
Intel C/C++ Compiler Intrinsic Equivalent
PSHUFW:
__m64 _mm_shuffle_pi16(__m64 a, int n)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
See Table 22-7, “Exception Conditions for SIMD/MMX Instructions with Memory Reference,” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A.
4-426 Vol. 2B
PSHUFW—Shuffle Packed Words
INSTRUCTION SET REFERENCE, M-U
PSIGNB/PSIGNW/PSIGND — Packed SIGN
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 38 08 /r1
RM
V/V
SSSE3
Negate/zero/preserve packed byte integers in
mm1 depending on the corresponding sign in
mm2/m64.
RM
V/V
SSSE3
Negate/zero/preserve packed byte integers in
xmm1 depending on the corresponding sign in
xmm2/m128.
RM
V/V
SSSE3
Negate/zero/preserve packed word integers
in mm1 depending on the corresponding sign
in mm2/m128.
RM
V/V
SSSE3
Negate/zero/preserve packed word integers
in xmm1 depending on the corresponding sign
in xmm2/m128.
RM
V/V
SSSE3
Negate/zero/preserve packed doubleword
integers in mm1 depending on the
corresponding sign in mm2/m128.
RM
V/V
SSSE3
Negate/zero/preserve packed doubleword
integers in xmm1 depending on the
corresponding sign in xmm2/m128.
RVM V/V
AVX
Negate/zero/preserve packed byte integers in
xmm2 depending on the corresponding sign in
xmm3/m128.
RVM V/V
AVX
Negate/zero/preserve packed word integers
in xmm2 depending on the corresponding sign
in xmm3/m128.
RVM V/V
AVX
Negate/zero/preserve packed doubleword
integers in xmm2 depending on the
corresponding sign in xmm3/m128.
RVM V/V
AVX2
Negate packed byte integers in ymm2 if the
corresponding sign in ymm3/m256 is less
than zero.
RVM V/V
AVX2
Negate packed 16-bit integers in ymm2 if the
corresponding sign in ymm3/m256 is less
than zero.
RVM V/V
AVX2
Negate packed doubleword integers in ymm2
if the corresponding sign in ymm3/m256 is
less than zero.
PSIGNB mm1, mm2/m64
66 0F 38 08 /r
PSIGNB xmm1, xmm2/m128
0F 38 09 /r1
PSIGNW mm1, mm2/m64
66 0F 38 09 /r
PSIGNW xmm1, xmm2/m128
0F 38 0A /r1
PSIGND mm1, mm2/m64
66 0F 38 0A /r
PSIGND xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 08 /r
VPSIGNB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F38.WIG 09 /r
VPSIGNW xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F38.WIG 0A /r
VPSIGND xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.WIG 08 /r
VPSIGNB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F38.WIG 09 /r
VPSIGNW ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F38.WIG 0A /r
VPSIGND ymm1, ymm2, ymm3/m256
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
PSIGNB/PSIGNW/PSIGND — Packed SIGN
Vol. 2B 4-427
INSTRUCTION SET REFERENCE, M-U
Description
(V)PSIGNB/(V)PSIGNW/(V)PSIGND negates each data element of the destination operand (the first operand) if the
signed integer value of the corresponding data element in the source operand (the second operand) is less than
zero. If the signed integer value of a data element in the source operand is positive, the corresponding data
element in the destination operand is unchanged. If a data element in the source operand is zero, the corresponding data element in the destination operand is set to zero.
(V)PSIGNB operates on signed bytes. (V)PSIGNW operates on 16-bit signed words. (V)PSIGND operates on signed
32-bit integers. When the source operand is a 128bit memory operand, the operand must be aligned on a 16-byte
boundary or a general-protection exception (#GP) will be generated.
Legacy SSE instructions: Both operands can be MMX registers. In 64-bit mode, use the REX prefix to access additional registers.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise instructions will #UD.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand is an YMM register or a 256-bit memory location.
Operation
PSIGNB (with 64 bit operands)
IF (SRC[7:0] < 0 )
DEST[7:0] ← Neg(DEST[7:0])
ELSEIF (SRC[7:0] = 0 )
DEST[7:0] ← 0
ELSEIF (SRC[7:0] > 0 )
DEST[7:0] ← DEST[7:0]
Repeat operation for 2nd through 7th bytes
IF (SRC[63:56] < 0 )
DEST[63:56] ← Neg(DEST[63:56])
ELSEIF (SRC[63:56] = 0 )
DEST[63:56] ← 0
ELSEIF (SRC[63:56] > 0 )
DEST[63:56] ← DEST[63:56]
PSIGNB (with 128 bit operands)
IF (SRC[7:0] < 0 )
DEST[7:0] ← Neg(DEST[7:0])
ELSEIF (SRC[7:0] = 0 )
DEST[7:0] ← 0
ELSEIF (SRC[7:0] > 0 )
DEST[7:0] ← DEST[7:0]
Repeat operation for 2nd through 15th bytes
IF (SRC[127:120] < 0 )
DEST[127:120] ← Neg(DEST[127:120])
ELSEIF (SRC[127:120] = 0 )
DEST[127:120] ← 0
ELSEIF (SRC[127:120] > 0 )
DEST[127:120] ← DEST[127:120]
4-428 Vol. 2B
PSIGNB/PSIGNW/PSIGND — Packed SIGN
INSTRUCTION SET REFERENCE, M-U
VPSIGNB (VEX.128 encoded version)
DEST[127:0] BYTE_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] 0
VPSIGNB (VEX.256 encoded version)
DEST[255:0] BYTE_SIGN_256b(SRC1, SRC2)
PSIGNW (with 64 bit operands)
IF (SRC[15:0] < 0 )
DEST[15:0] ← Neg(DEST[15:0])
ELSEIF (SRC[15:0] = 0 )
DEST[15:0] ← 0
ELSEIF (SRC[15:0] > 0 )
DEST[15:0] ← DEST[15:0]
Repeat operation for 2nd through 3rd words
IF (SRC[63:48] < 0 )
DEST[63:48] ← Neg(DEST[63:48])
ELSEIF (SRC[63:48] = 0 )
DEST[63:48] ← 0
ELSEIF (SRC[63:48] > 0 )
DEST[63:48] ← DEST[63:48]
PSIGNW (with 128 bit operands)
IF (SRC[15:0] < 0 )
DEST[15:0] ← Neg(DEST[15:0])
ELSEIF (SRC[15:0] = 0 )
DEST[15:0] ← 0
ELSEIF (SRC[15:0] > 0 )
DEST[15:0] ← DEST[15:0]
Repeat operation for 2nd through 7th words
IF (SRC[127:112] < 0 )
DEST[127:112] ← Neg(DEST[127:112])
ELSEIF (SRC[127:112] = 0 )
DEST[127:112] ← 0
ELSEIF (SRC[127:112] > 0 )
DEST[127:112] ← DEST[127:112]
VPSIGNW (VEX.128 encoded version)
DEST[127:0] WORD_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] 0
VPSIGNW (VEX.256 encoded version)
DEST[255:0] WORD_SIGN(SRC1, SRC2)
PSIGND (with 64 bit operands)
IF (SRC[31:0] < 0 )
DEST[31:0] ← Neg(DEST[31:0])
ELSEIF (SRC[31:0] = 0 )
DEST[31:0] ← 0
ELSEIF (SRC[31:0] > 0 )
DEST[31:0] ← DEST[31:0]
IF (SRC[63:32] < 0 )
DEST[63:32] ← Neg(DEST[63:32])
ELSEIF (SRC[63:32] = 0 )
DEST[63:32] ← 0
PSIGNB/PSIGNW/PSIGND — Packed SIGN
Vol. 2B 4-429
INSTRUCTION SET REFERENCE, M-U
ELSEIF (SRC[63:32] > 0 )
DEST[63:32] ← DEST[63:32]
PSIGND (with 128 bit operands)
IF (SRC[31:0] < 0 )
DEST[31:0] ← Neg(DEST[31:0])
ELSEIF (SRC[31:0] = 0 )
DEST[31:0] ← 0
ELSEIF (SRC[31:0] > 0 )
DEST[31:0] ← DEST[31:0]
Repeat operation for 2nd through 3rd double words
IF (SRC[127:96] < 0 )
DEST[127:96] ← Neg(DEST[127:96])
ELSEIF (SRC[127:96] = 0 )
DEST[127:96] ← 0
ELSEIF (SRC[127:96] > 0 )
DEST[127:96] ← DEST[127:96]
VPSIGND (VEX.128 encoded version)
DEST[127:0] DWORD_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] 0
VPSIGND (VEX.256 encoded version)
DEST[255:0] DWORD_SIGN(SRC1, SRC2)
Intel C/C++ Compiler Intrinsic Equivalent
PSIGNB:
__m64 _mm_sign_pi8 (__m64 a, __m64 b)
(V)PSIGNB:
__m128i _mm_sign_epi8 (__m128i a, __m128i b)
VPSIGNB:
__m256i _mm256_sign_epi8 (__m256i a, __m256i b)
PSIGNW:
__m64 _mm_sign_pi16 (__m64 a, __m64 b)
(V)PSIGNW:
__m128i _mm_sign_epi16 (__m128i a, __m128i b)
VPSIGNW:
__m256i _mm256_sign_epi16 (__m256i a, __m256i b)
PSIGND:
__m64 _mm_sign_pi32 (__m64 a, __m64 b)
(V)PSIGND:
__m128i _mm_sign_epi32 (__m128i a, __m128i b)
VPSIGND:
__m256i _mm256_sign_epi32 (__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
4-430 Vol. 2B
If VEX.L = 1.
PSIGNB/PSIGNW/PSIGND — Packed SIGN
INSTRUCTION SET REFERENCE, M-U
PSLLDQ—Shift Double Quadword Left Logical
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 73 /7 ib
MI
V/V
SSE2
Shift xmm1 left by imm8 bytes while shifting
in 0s.
VMI
V/V
AVX
Shift xmm2 left by imm8 bytes while shifting
in 0s and store result in xmm1.
VMI
V/V
AVX2
Shift ymm2 left by imm8 bytes while shifting
in 0s and store result in ymm1.
PSLLDQ xmm1, imm8
VEX.NDD.128.66.0F.WIG 73 /7 ib
VPSLLDQ xmm1, xmm2, imm8
VEX.NDD.256.66.0F.WIG 73 /7 ib
VPSLLDQ ymm1, ymm2, imm8
EVEX.NDD.128.66.0F.WIG 73 /7 ib
VPSLLDQ xmm1,xmm2/ m128, imm8
FVMI V/V
AVX512VL Shift xmm2/m128 left by imm8 bytes while
AVX512BW shifting in 0s and store result in xmm1.
EVEX.NDD.256.66.0F.WIG 73 /7 ib
VPSLLDQ ymm1, ymm2/m256, imm8
FVMI V/V
AVX512VL Shift ymm2/m256 left by imm8 bytes while
AVX512BW shifting in 0s and store result in ymm1.
EVEX.NDD.512.66.0F.WIG 73 /7 ib
VPSLLDQ zmm1, zmm2/m512, imm8
FVMI V/V
AVX512BW Shift zmm2/m512 left by imm8 bytes while
shifting in 0s and store result in zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MI
ModRM:r/m (r, w)
imm8
NA
NA
VMI
VEX.vvvv (w)
ModRM:r/m (r)
imm8
NA
FVMI
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
Description
Shifts the destination operand (first operand) to the left by the number of bytes specified in the count operand
(second operand). The empty low-order bytes are cleared (set to all 0s). If the value specified by the count
operand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.
128-bit Legacy SSE version: The source and destination operands are the same. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The source and destination operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed.
VEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits
(MAX_VL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and
high 128-bit lanes.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.
Operation
VPSLLDQ (EVEX.U1.512 encoded version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST[127:0] SRC[127:0] << (TEMP * 8)
DEST[255:128] SRC[255:128] << (TEMP * 8)
DEST[383:256] SRC[383:256] << (TEMP * 8)
DEST[511:384] SRC[511:384] << (TEMP * 8)
DEST[MAX_VL-1:512] 0
PSLLDQ—Shift Double Quadword Left Logical
Vol. 2B 4-431
INSTRUCTION SET REFERENCE, M-U
VPSLLDQ (VEX.256 and EVEX.256 encoded version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST[127:0] SRC[127:0] << (TEMP * 8)
DEST[255:128] SRC[255:128] << (TEMP * 8)
DEST[MAX_VL-1:256] 0
VPSLLDQ (VEX.128 and EVEX.128 encoded version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST SRC << (TEMP * 8)
DEST[MAX_VL-1:128] 0
PSLLDQ(128-bit Legacy SSE version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST DEST << (TEMP * 8)
DEST[VLMAX-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
(V)PSLLDQ:__m128i _mm_slli_si128 ( __m128i a, int imm)
VPSLLDQ:__m256i _mm256_slli_si256 ( __m256i a, const int imm)
VPSLLDQ __m512i _mm512_bslli_epi128 ( __m512i a, const int imm)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
4-432 Vol. 2B
PSLLDQ—Shift Double Quadword Left Logical
INSTRUCTION SET REFERENCE, M-U
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F F1 /r1
RM
V/V
MMX
Shift words in mm left mm/m64 while shifting in
0s.
RM
V/V
SSE2
Shift words in xmm1 left by xmm2/m128 while
shifting in 0s.
MI
V/V
MMX
Shift words in mm left by imm8 while shifting in
0s.
MI
V/V
SSE2
Shift words in xmm1 left by imm8 while shifting
in 0s.
RM
V/V
MMX
Shift doublewords in mm left by mm/m64 while
shifting in 0s.
RM
V/V
SSE2
Shift doublewords in xmm1 left by xmm2/m128
while shifting in 0s.
MI
V/V
MMX
Shift doublewords in mm left by imm8 while
shifting in 0s.
MI
V/V
SSE2
Shift doublewords in xmm1 left by imm8 while
shifting in 0s.
RM
V/V
MMX
Shift quadword in mm left by mm/m64 while
shifting in 0s.
RM
V/V
SSE2
Shift quadwords in xmm1 left by xmm2/m128
while shifting in 0s.
MI
V/V
MMX
Shift quadword in mm left by imm8 while
shifting in 0s.
MI
V/V
SSE2
Shift quadwords in xmm1 left by imm8 while
shifting in 0s.
RVM
V/V
AVX
Shift words in xmm2 left by amount specified in
xmm3/m128 while shifting in 0s.
VMI
V/V
AVX
Shift words in xmm2 left by imm8 while shifting
in 0s.
RVM
V/V
AVX
Shift doublewords in xmm2 left by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX
Shift doublewords in xmm2 left by imm8 while
shifting in 0s.
RVM
V/V
AVX
Shift quadwords in xmm2 left by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX
Shift quadwords in xmm2 left by imm8 while
shifting in 0s.
RVM
V/V
AVX2
Shift words in ymm2 left by amount specified in
xmm3/m128 while shifting in 0s.
VMI
V/V
AVX2
Shift words in ymm2 left by imm8 while shifting
in 0s.
PSLLW mm, mm/m64
66 0F F1 /r
PSLLW xmm1, xmm2/m128
0F 71 /6 ib
PSLLW mm1, imm8
66 0F 71 /6 ib
PSLLW xmm1, imm8
0F F2 /r1
PSLLD mm, mm/m64
66 0F F2 /r
PSLLD xmm1, xmm2/m128
0F 72 /6 ib1
PSLLD mm, imm8
66 0F 72 /6 ib
PSLLD xmm1, imm8
0F F3 /r1
PSLLQ mm, mm/m64
66 0F F3 /r
PSLLQ xmm1, xmm2/m128
0F 73 /6 ib1
PSLLQ mm, imm8
66 0F 73 /6 ib
PSLLQ xmm1, imm8
VEX.NDS.128.66.0F.WIG F1 /r
VPSLLW xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 71 /6 ib
VPSLLW xmm1, xmm2, imm8
VEX.NDS.128.66.0F.WIG F2 /r
VPSLLD xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 72 /6 ib
VPSLLD xmm1, xmm2, imm8
VEX.NDS.128.66.0F.WIG F3 /r
VPSLLQ xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 73 /6 ib
VPSLLQ xmm1, xmm2, imm8
VEX.NDS.256.66.0F.WIG F1 /r
VPSLLW ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 71 /6 ib
VPSLLW ymm1, ymm2, imm8
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
Vol. 2B 4-433
INSTRUCTION SET REFERENCE, M-U
VEX.NDS.256.66.0F.WIG F2 /r
RVM
V/V
AVX2
Shift doublewords in ymm2 left by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX2
Shift doublewords in ymm2 left by imm8 while
shifting in 0s.
RVM
V/V
AVX2
Shift quadwords in ymm2 left by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX2
Shift quadwords in ymm2 left by imm8 while
shifting in 0s.
VPSLLD ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 72 /6 ib
VPSLLD ymm1, ymm2, imm8
VEX.NDS.256.66.0F.WIG F3 /r
VPSLLQ ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 73 /6 ib
VPSLLQ ymm1, ymm2, imm8
EVEX.NDS.128.66.0F.WIG F1 /r
VPSLLW xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL Shift words in xmm2 left by amount specified in
AVX512BW xmm3/m128 while shifting in 0s using
writemask k1.
EVEX.NDS.256.66.0F.WIG F1 /r
VPSLLW ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL Shift words in ymm2 left by amount specified in
AVX512BW xmm3/m128 while shifting in 0s using
writemask k1.
EVEX.NDS.512.66.0F.WIG F1 /r
VPSLLW zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512BW Shift words in zmm2 left by amount specified in
xmm3/m128 while shifting in 0s using
writemask k1.
EVEX.NDD.128.66.0F.WIG 71 /6 ib
VPSLLW xmm1 {k1}{z}, xmm2/m128, imm8
FVMI
V/V
AVX512VL Shift words in xmm2/m128 left by imm8 while
AVX512BW shifting in 0s using writemask k1.
EVEX.NDD.256.66.0F.WIG 71 /6 ib
VPSLLW ymm1 {k1}{z}, ymm2/m256, imm8
FVMI
V/V
AVX512VL Shift words in ymm2/m256 left by imm8 while
AVX512BW shifting in 0s using writemask k1.
EVEX.NDD.512.66.0F.WIG 71 /6 ib
VPSLLW zmm1 {k1}{z}, zmm2/m512, imm8
FVMI
V/V
AVX512BW Shift words in zmm2/m512 left by imm8 while
shifting in 0 using writemask k1.
EVEX.NDS.128.66.0F.W0 F2 /r
VPSLLD xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift doublewords in xmm2 left by amount
specified in xmm3/m128 while shifting in 0s
under writemask k1.
EVEX.NDS.256.66.0F.W0 F2 /r
VPSLLD ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift doublewords in ymm2 left by amount
specified in xmm3/m128 while shifting in 0s
under writemask k1.
EVEX.NDS.512.66.0F.W0 F2 /r
VPSLLD zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512F
Shift doublewords in zmm2 left by amount
specified in xmm3/m128 while shifting in 0s
under writemask k1.
EVEX.NDD.128.66.0F.W0 72 /6 ib
VPSLLD xmm1 {k1}{z}, xmm2/m128/m32bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift doublewords in xmm2/m128/m32bcst left
by imm8 while shifting in 0s using writemask k1.
EVEX.NDD.256.66.0F.W0 72 /6 ib
VPSLLD ymm1 {k1}{z}, ymm2/m256/m32bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift doublewords in ymm2/m256/m32bcst left
by imm8 while shifting in 0s using writemask k1.
EVEX.NDD.512.66.0F.W0 72 /6 ib
VPSLLD zmm1 {k1}{z}, zmm2/m512/m32bcst,
imm8
FVI
V/V
AVX512F
Shift doublewords in zmm2/m512/m32bcst left
by imm8 while shifting in 0s using writemask k1.
EVEX.NDS.128.66.0F.W1 F3 /r
VPSLLQ xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift quadwords in xmm2 left by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
EVEX.NDS.256.66.0F.W1 F3 /r
VPSLLQ ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift quadwords in ymm2 left by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
EVEX.NDS.512.66.0F.W1 F3 /r
VPSLLQ zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512F
Shift quadwords in zmm2 left by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
4-434 Vol. 2B
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, M-U
EVEX.NDD.128.66.0F.W1 73 /6 ib
VPSLLQ xmm1 {k1}{z}, xmm2/m128/m64bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift quadwords in xmm2/m128/m64bcst left
by imm8 while shifting in 0s using writemask k1.
EVEX.NDD.256.66.0F.W1 73 /6 ib
VPSLLQ ymm1 {k1}{z}, ymm2/m256/m64bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift quadwords in ymm2/m256/m64bcst left
by imm8 while shifting in 0s using writemask k1.
EVEX.NDD.512.66.0F.W1 73 /6 ib
VPSLLQ zmm1 {k1}{z}, zmm2/m512/m64bcst,
imm8
FVI
V/V
AVX512F
Shift quadwords in zmm2/m512/m64bcst left
by imm8 while shifting in 0s using writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
VMI
VEX.vvvv (w)
ModRM:r/m (r)
imm8
NA
FVMI
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
FVI
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
M128
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first
operand) to the left by the number of bits specified in the count operand (second operand). As the bits in the data
elements are shifted left, the empty low-order bits are cleared (set to 0). If the value specified by the count
operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand
is set to all 0s. Figure 4-17 gives an example of shifting words in a 64-bit operand.
Pre-Shift
DEST
X3
X2
X3 << COUNT
X2 << COUNT
X1
X0
Shift Left
with Zero
Extension
Post-Shift
DEST
X1 << COUNT X0 << COUNT
Figure 4-17. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand
The (V)PSLLW instruction shifts each of the words in the destination operand to the left by the number of bits specified in the count operand; the (V)PSLLD instruction shifts each of the doublewords in the destination operand; and
the (V)PSLLQ instruction shifts the quadword (or quadwords) in the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count
operand can be either an MMX technology register or an 64-bit memory location.
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
Vol. 2B 4-435
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of
the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register
or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded
but the upper 64 bits are ignored.
VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are
ignored.
VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location. The count operand can come either from an XMM register or a memory location or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count
operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a
memory location (the variable count version). For the immediate count version, the source operand (the second
operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,
the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.
Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination
register, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.
Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /6, or EVEX.128.66.0F 71-73 /6),
VEX.vvvv/EVEX.vvvv encodes the destination register.
Operation
PSLLW (with 64-bit operand)
IF (COUNT > 15)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST[15:0] ← ZeroExtend(DEST[15:0] << COUNT);
(* Repeat shift operation for 2nd and 3rd words *)
DEST[63:48] ← ZeroExtend(DEST[63:48] << COUNT);
FI;
PSLLD (with 64-bit operand)
IF (COUNT > 31)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST[31:0] ← ZeroExtend(DEST[31:0] << COUNT);
DEST[63:32] ← ZeroExtend(DEST[63:32] << COUNT);
FI;
PSLLQ (with 64-bit operand)
IF (COUNT > 63)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST ← ZeroExtend(DEST << COUNT);
FI;
LOGICAL_LEFT_SHIFT_WORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
4-436 Vol. 2B
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, M-U
DEST[127:0] 00000000000000000000000000000000H
ELSE
DEST[15:0] ZeroExtend(SRC[15:0] << COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[127:112] ZeroExtend(SRC[127:112] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_DWORDS1(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
DEST[31:0] 0
ELSE
DEST[31:0] ZeroExtend(SRC[31:0] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_DWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
DEST[127:0] 00000000000000000000000000000000H
ELSE
DEST[31:0] ZeroExtend(SRC[31:0] << COUNT);
(* Repeat shift operation for 2nd through 3rd words *)
DEST[127:96] ZeroExtend(SRC[127:96] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_QWORDS1(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
DEST[63:0] 0
ELSE
DEST[63:0] ZeroExtend(SRC[63:0] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_QWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
DEST[127:0] 00000000000000000000000000000000H
ELSE
DEST[63:0] ZeroExtend(SRC[63:0] << COUNT);
DEST[127:64] ZeroExtend(SRC[127:64] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
DEST[127:0] 00000000000000000000000000000000H
DEST[255:128] 00000000000000000000000000000000H
ELSE
DEST[15:0] ZeroExtend(SRC[15:0] << COUNT);
(* Repeat shift operation for 2nd through 15th words *)
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
Vol. 2B 4-437
INSTRUCTION SET REFERENCE, M-U
DEST[255:240] ZeroExtend(SRC[255:240] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
DEST[127:0] 00000000000000000000000000000000H
DEST[255:128] 00000000000000000000000000000000H
ELSE
DEST[31:0] ZeroExtend(SRC[31:0] << COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[255:224] ZeroExtend(SRC[255:224] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
DEST[127:0] 00000000000000000000000000000000H
DEST[255:128] 00000000000000000000000000000000H
ELSE
DEST[63:0] ZeroExtend(SRC[63:0] << COUNT);
DEST[127:64] ZeroExtend(SRC[127:64] << COUNT)
DEST[191:128] ZeroExtend(SRC[191:128] << COUNT);
DEST[255:192] ZeroExtend(SRC[255:192] << COUNT);
FI;
VPSLLW (EVEX versions, xmm/m128)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[127:0] LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-438 Vol. 2B
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, M-U
VPSLLW (EVEX versions, imm8)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[127:0] LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
TMP_DEST[511:256] LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSLLW (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0;
VPSLLW (ymm, imm8) - VEX.256 encoding
DEST[255:0] LOGICAL_LEFT_SHIFT_WORD_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0;
VPSLLW (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] LOGICAL_LEFT_SHIFT_WORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSLLW (xmm, imm8) - VEX.128 encoding
DEST[127:0] LOGICAL_LEFT_SHIFT_WORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
Vol. 2B 4-439
INSTRUCTION SET REFERENCE, M-U
PSLLW (xmm, xmm, xmm/m128)
DEST[127:0] LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSLLW (xmm, imm8)
DEST[127:0] LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
VPSLLD (EVEX versions, imm8)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[31:0], imm8)
ELSE DEST[i+31:i] LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSLLD (EVEX versions, xmm/m128)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
TMP_DEST[127:0] LOGICAL_LEFT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-440 Vol. 2B
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, M-U
VPSLLD (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0;
VPSLLD (ymm, imm8) - VEX.256 encoding
DEST[255:0] LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0;
VPSLLD (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSLLD (xmm, imm8) - VEX.128 encoding
DEST[127:0] LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSLLD (xmm, xmm, xmm/m128)
DEST[127:0] LOGICAL_LEFT_SHIFT_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSLLD (xmm, imm8)
DEST[127:0] LOGICAL_LEFT_SHIFT_DWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
VPSLLQ (EVEX versions, imm8)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[63:0], imm8)
ELSE DEST[i+63:i] LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
VPSLLQ (EVEX versions, xmm/m128)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF VL = 128
TMP_DEST[127:0] LOGICAL_LEFT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)
FI;
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
Vol. 2B 4-441
INSTRUCTION SET REFERENCE, M-U
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSLLQ (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0;
VPSLLQ (ymm, imm8) - VEX.256 encoding
DEST[255:0] LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0;
VPSLLQ (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] LOGICAL_LEFT_SHIFT_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSLLQ (xmm, imm8) - VEX.128 encoding
DEST[127:0] LOGICAL_LEFT_SHIFT_QWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSLLQ (xmm, xmm, xmm/m128)
DEST[127:0] LOGICAL_LEFT_SHIFT_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSLLQ (xmm, imm8)
DEST[127:0] LOGICAL_LEFT_SHIFT_QWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalents
VPSLLD __m512i _mm512_slli_epi32(__m512i a, unsigned int imm);
VPSLLD __m512i _mm512_mask_slli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);
VPSLLD __m512i _mm512_maskz_slli_epi32( __mmask16 k, __m512i a, unsigned int imm);
VPSLLD __m256i _mm256_mask_slli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSLLD __m256i _mm256_maskz_slli_epi32( __mmask8 k, __m256i a, unsigned int imm);
VPSLLD __m128i _mm_mask_slli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSLLD __m128i _mm_maskz_slli_epi32( __mmask8 k, __m128i a, unsigned int imm);
VPSLLD __m512i _mm512_sll_epi32(__m512i a, __m128i cnt);
VPSLLD __m512i _mm512_mask_sll_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSLLD __m512i _mm512_maskz_sll_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSLLD __m256i _mm256_mask_sll_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSLLD __m256i _mm256_maskz_sll_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSLLD __m128i _mm_mask_sll_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLD __m128i _mm_maskz_sll_epi32( __mmask8 k, __m128i a, __m128i cnt);
4-442 Vol. 2B
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, M-U
VPSLLQ __m512i _mm512_mask_slli_epi64(__m512i a, unsigned int imm);
VPSLLQ __m512i _mm512_mask_slli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);
VPSLLQ __m512i _mm512_maskz_slli_epi64( __mmask8 k, __m512i a, unsigned int imm);
VPSLLQ __m256i _mm256_mask_slli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSLLQ __m256i _mm256_maskz_slli_epi64( __mmask8 k, __m256i a, unsigned int imm);
VPSLLQ __m128i _mm_mask_slli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSLLQ __m128i _mm_maskz_slli_epi64( __mmask8 k, __m128i a, unsigned int imm);
VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i a, __m128i cnt);
VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);
VPSLLQ __m512i _mm512_maskz_sll_epi64( __mmask8 k, __m512i a, __m128i cnt);
VPSLLQ __m256i _mm256_mask_sll_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSLLQ __m256i _mm256_maskz_sll_epi64( __mmask8 k, __m256i a, __m128i cnt);
VPSLLQ __m128i _mm_mask_sll_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLQ __m128i _mm_maskz_sll_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSLLW __m512i _mm512_slli_epi16(__m512i a, unsigned int imm);
VPSLLW __m512i _mm512_mask_slli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);
VPSLLW __m512i _mm512_maskz_slli_epi16( __mmask32 k, __m512i a, unsigned int imm);
VPSLLW __m256i _mm256_mask_sllii_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
VPSLLW __m256i _mm256_maskz_slli_epi16( __mmask16 k, __m256i a, unsigned int imm);
VPSLLW __m128i _mm_mask_slli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSLLW __m128i _mm_maskz_slli_epi16( __mmask8 k, __m128i a, unsigned int imm);
VPSLLW __m512i _mm512_sll_epi16(__m512i a, __m128i cnt);
VPSLLW __m512i _mm512_mask_sll_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);
VPSLLW __m512i _mm512_maskz_sll_epi16( __mmask32 k, __m512i a, __m128i cnt);
VPSLLW __m256i _mm256_mask_sll_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);
VPSLLW __m256i _mm256_maskz_sll_epi16( __mmask16 k, __m256i a, __m128i cnt);
VPSLLW __m128i _mm_mask_sll_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLW __m128i _mm_maskz_sll_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSLLW:__m64 _mm_slli_pi16 (__m64 m, int count)
PSLLW:__m64 _mm_sll_pi16(__m64 m, __m64 count)
(V)PSLLW:__m128i _mm_slli_pi16(__m64 m, int count)
(V)PSLLW:__m128i _mm_slli_pi16(__m128i m, __m128i count)
VPSLLW:__m256i _mm256_slli_epi16 (__m256i m, int count)
VPSLLW:__m256i _mm256_sll_epi16 (__m256i m, __m128i count)
PSLLD:__m64 _mm_slli_pi32(__m64 m, int count)
PSLLD:__m64 _mm_sll_pi32(__m64 m, __m64 count)
(V)PSLLD:__m128i _mm_slli_epi32(__m128i m, int count)
(V)PSLLD:__m128i _mm_sll_epi32(__m128i m, __m128i count)
VPSLLD:__m256i _mm256_slli_epi32 (__m256i m, int count)
VPSLLD:__m256i _mm256_sll_epi32 (__m256i m, __m128i count)
PSLLQ:__m64 _mm_slli_si64(__m64 m, int count)
PSLLQ:__m64 _mm_sll_si64(__m64 m, __m64 count)
(V)PSLLQ:__m128i _mm_slli_epi64(__m128i m, int count)
(V)PSLLQ:__m128i _mm_sll_epi64(__m128i m, __m128i count)
VPSLLQ:__m256i _mm256_slli_epi64 (__m256i m, int count)
VPSLLQ:__m256i _mm256_sll_epi64 (__m256i m, __m128i count)
Flags Affected
None.
Numeric Exceptions
None.
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
Vol. 2B 4-443
INSTRUCTION SET REFERENCE, M-U
Other Exceptions
VEX-encoded instructions:
Syntax with RM/RVM operand encoding, see Exceptions Type 4.
Syntax with MI/VMI operand encoding, see Exceptions Type 7.
EVEX-encoded VPSLLW, see Exceptions Type E4NF.nb.
EVEX-encoded VPSLLD/Q:
Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.
Syntax with FVI operand encoding, see Exceptions Type E4.
4-444 Vol. 2B
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, M-U
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F E1 /r1
RM
V/V
MMX
Shift words in mm right by mm/m64 while shifting
in sign bits.
RM
V/V
SSE2
Shift words in xmm1 right by xmm2/m128 while
shifting in sign bits.
MI
V/V
MMX
Shift words in mm right by imm8 while shifting in
sign bits
MI
V/V
SSE2
Shift words in xmm1 right by imm8 while shifting
in sign bits
RM
V/V
MMX
Shift doublewords in mm right by mm/m64 while
shifting in sign bits.
RM
V/V
SSE2
Shift doubleword in xmm1 right by xmm2 /m128
while shifting in sign bits.
MI
V/V
MMX
Shift doublewords in mm right by imm8 while
shifting in sign bits.
MI
V/V
SSE2
Shift doublewords in xmm1 right by imm8 while
shifting in sign bits.
RVM
V/V
AVX
Shift words in xmm2 right by amount specified in
xmm3/m128 while shifting in sign bits.
VMI
V/V
AVX
Shift words in xmm2 right by imm8 while shifting
in sign bits.
RVM
V/V
AVX
Shift doublewords in xmm2 right by amount
specified in xmm3/m128 while shifting in sign
bits.
VMI
V/V
AVX
Shift doublewords in xmm2 right by imm8 while
shifting in sign bits.
RVM
V/V
AVX2
Shift words in ymm2 right by amount specified in
xmm3/m128 while shifting in sign bits.
VMI
V/V
AVX2
Shift words in ymm2 right by imm8 while shifting
in sign bits.
RVM
V/V
AVX2
Shift doublewords in ymm2 right by amount
specified in xmm3/m128 while shifting in sign
bits.
VMI
V/V
AVX2
Shift doublewords in ymm2 right by imm8 while
shifting in sign bits.
PSRAW mm, mm/m64
66 0F E1 /r
PSRAW xmm1, xmm2/m128
0F 71 /4 ib1
PSRAW mm, imm8
66 0F 71 /4 ib
PSRAW xmm1, imm8
0F E2 /r1
PSRAD mm, mm/m64
66 0F E2 /r
PSRAD xmm1, xmm2/m128
0F 72 /4 ib1
PSRAD mm, imm8
66 0F 72 /4 ib
PSRAD xmm1, imm8
VEX.NDS.128.66.0F.WIG E1 /r
VPSRAW xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 71 /4 ib
VPSRAW xmm1, xmm2, imm8
VEX.NDS.128.66.0F.WIG E2 /r
VPSRAD xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 72 /4 ib
VPSRAD xmm1, xmm2, imm8
VEX.NDS.256.66.0F.WIG E1 /r
VPSRAW ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 71 /4 ib
VPSRAW ymm1, ymm2, imm8
VEX.NDS.256.66.0F.WIG E2 /r
VPSRAD ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 72 /4 ib
VPSRAD ymm1, ymm2, imm8
EVEX.NDS.128.66.0F.WIG E1 /r
VPSRAW xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL Shift words in xmm2 right by amount specified in
AVX512BW xmm3/m128 while shifting in sign bits using
writemask k1.
EVEX.NDS.256.66.0F.WIG E1 /r
VPSRAW ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL Shift words in ymm2 right by amount specified in
AVX512BW xmm3/m128 while shifting in sign bits using
writemask k1.
EVEX.NDS.512.66.0F.WIG E1 /r
VPSRAW zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512BW Shift words in zmm2 right by amount specified in
xmm3/m128 while shifting in sign bits using
writemask k1.
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
Vol. 2B 4-445
INSTRUCTION SET REFERENCE, M-U
EVEX.NDD.128.66.0F.WIG 71 /4 ib
VPSRAW xmm1 {k1}{z}, xmm2/m128, imm8
FVMI
V/V
AVX512VL Shift words in xmm2/m128 right by imm8 while
AVX512BW shifting in sign bits using writemask k1.
EVEX.NDD.256.66.0F.WIG 71 /4 ib
VPSRAW ymm1 {k1}{z}, ymm2/m256, imm8
FVMI
V/V
AVX512VL Shift words in ymm2/m256 right by imm8 while
AVX512BW shifting in sign bits using writemask k1.
EVEX.NDD.512.66.0F.WIG 71 /4 ib
VPSRAW zmm1 {k1}{z}, zmm2/m512, imm8
FVMI
V/V
AVX512BW Shift words in zmm2/m512 right by imm8 while
shifting in sign bits using writemask k1.
EVEX.NDS.128.66.0F.W0 E2 /r
VPSRAD xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift doublewords in xmm2 right by amount
specified in xmm3/m128 while shifting in sign bits
using writemask k1.
EVEX.NDS.256.66.0F.W0 E2 /r
VPSRAD ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift doublewords in ymm2 right by amount
specified in xmm3/m128 while shifting in sign bits
using writemask k1.
EVEX.NDS.512.66.0F.W0 E2 /r
VPSRAD zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512F
Shift doublewords in zmm2 right by amount
specified in xmm3/m128 while shifting in sign bits
using writemask k1.
EVEX.NDD.128.66.0F.W0 72 /4 ib
VPSRAD xmm1 {k1}{z}, xmm2/m128/m32bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift doublewords in xmm2/m128/m32bcst right
by imm8 while shifting in sign bits using
writemask k1.
EVEX.NDD.256.66.0F.W0 72 /4 ib
VPSRAD ymm1 {k1}{z}, ymm2/m256/m32bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift doublewords in ymm2/m256/m32bcst right
by imm8 while shifting in sign bits using
writemask k1.
EVEX.NDD.512.66.0F.W0 72 /4 ib
VPSRAD zmm1 {k1}{z}, zmm2/m512/m32bcst,
imm8
FVI
V/V
AVX512F
Shift doublewords in zmm2/m512/m32bcst right
by imm8 while shifting in sign bits using
writemask k1.
EVEX.NDS.128.66.0F.W1 E2 /r
VPSRAQ xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift quadwords in xmm2 right by amount
specified in xmm3/m128 while shifting in sign bits
using writemask k1.
EVEX.NDS.256.66.0F.W1 E2 /r
VPSRAQ ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift quadwords in ymm2 right by amount
specified in xmm3/m128 while shifting in sign bits
using writemask k1.
EVEX.NDS.512.66.0F.W1 E2 /r
VPSRAQ zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512F
Shift quadwords in zmm2 right by amount
specified in xmm3/m128 while shifting in sign bits
using writemask k1.
EVEX.NDD.128.66.0F.W1 72 /4 ib
VPSRAQ xmm1 {k1}{z}, xmm2/m128/m64bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift quadwords in xmm2/m128/m64bcst right by
imm8 while shifting in sign bits using writemask
k1.
EVEX.NDD.256.66.0F.W1 72 /4 ib
VPSRAQ ymm1 {k1}{z}, ymm2/m256/m64bcst,
imm8
FVI
V/V
AVX512VL
AVX512F
Shift quadwords in ymm2/m256/m64bcst right by
imm8 while shifting in sign bits using writemask
k1.
EVEX.NDD.512.66.0F.W1 72 /4 ib
VPSRAQ zmm1 {k1}{z}, zmm2/m512/m64bcst,
imm8
FVI
V/V
AVX512F
Shift quadwords in zmm2/m512/m64bcst right by
imm8 while shifting in sign bits using writemask
k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
4-446 Vol. 2B
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
INSTRUCTION SET REFERENCE, M-U
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
VMI
VEX.vvvv (w)
ModRM:r/m (r)
imm8
NA
FVMI
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
FVI
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
M128
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Shifts the bits in the individual data elements (words, doublewords or quadwords) in the destination operand (first
operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data
elements are shifted right, the empty high-order bits are filled with the initial value of the sign bit of the data
element. If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for
quadwords), each destination data element is filled with the initial value of the sign bit of the element. (Figure 4-18
gives an example of shifting words in a 64-bit operand.)
Pre-Shift
DEST
X3
X2
X3 >> COUNT
X2 >> COUNT
X1
X0
Shift Right
with Sign
Extension
Post-Shift
DEST
X1 >> COUNT X0 >> COUNT
Figure 4-18. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand
Note that only the first 64-bits of a 128-bit count operand are checked to compute the count. If the second source
operand is a memory address, 128 bits are loaded.
The (V)PSRAW instruction shifts each of the words in the destination operand to the right by the number of bits
specified in the count operand, and the (V)PSRAD instruction shifts each of the doublewords in the destination
operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count
operand can be either an MMX technology register or an 64-bit memory location.
128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of
the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register
or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded
but the upper 64 bits are ignored.
VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are
ignored.
VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location. The count operand can come either from an XMM register or a memory location or an 8-bit
immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
Vol. 2B 4-447
INSTRUCTION SET REFERENCE, M-U
EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count
operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a
memory location (the variable count version). For the immediate count version, the source operand (the second
operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,
the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.
Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination
register, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.
Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /4, EVEX.128.66.0F 71-73 /4),
VEX.vvvv/EVEX.vvvv encodes the destination register.
Operation
PSRAW (with 64-bit operand)
IF (COUNT > 15)
THEN COUNT ← 16;
FI;
DEST[15:0] ← SignExtend(DEST[15:0] >> COUNT);
(* Repeat shift operation for 2nd and 3rd words *)
DEST[63:48] ← SignExtend(DEST[63:48] >> COUNT);
PSRAD (with 64-bit operand)
IF (COUNT > 31)
THEN COUNT ← 32;
FI;
DEST[31:0] ← SignExtend(DEST[31:0] >> COUNT);
DEST[63:32] ← SignExtend(DEST[63:32] >> COUNT);
ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
DEST[31:0] SignBit
ELSE
DEST[31:0] SignExtend(SRC[31:0] >> COUNT);
FI;
ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
DEST[63:0] SignBit
ELSE
DEST[63:0] SignExtend(SRC[63:0] >> COUNT);
FI;
ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
COUNT 16;
FI;
DEST[15:0] SignExtend(SRC[15:0] >> COUNT);
(* Repeat shift operation for 2nd through 15th words *)
DEST[255:240] SignExtend(SRC[255:240] >> COUNT);
4-448 Vol. 2B
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
INSTRUCTION SET REFERENCE, M-U
ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
COUNT 32;
FI;
DEST[31:0] SignExtend(SRC[31:0] >> COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[255:224] SignExtend(SRC[255:224] >> COUNT);
ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC, VL)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
COUNT 64;
FI;
DEST[63:0] SignExtend(SRC[63:0] >> COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[VL-1:VL-64] SignExtend(SRC[VL-1:VL-64] >> COUNT);
; VL: 128b, 256b or 512b
ARITHMETIC_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
COUNT 16;
FI;
DEST[15:0] SignExtend(SRC[15:0] >> COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[127:112] SignExtend(SRC[127:112] >> COUNT);
ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
COUNT 32;
FI;
DEST[31:0] SignExtend(SRC[31:0] >> COUNT);
(* Repeat shift operation for 2nd through 3rd words *)
DEST[127:96] SignExtend(SRC[127:96] >> COUNT);
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
Vol. 2B 4-449
INSTRUCTION SET REFERENCE, M-U
VPSRAW (EVEX versions, xmm/m128)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[127:0] ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRAW (EVEX versions, imm8)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[127:0] ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
FI;
IF VL = 256
TMP_DEST[255:0] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
FI;
IF VL = 512
TMP_DEST[255:0] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
TMP_DEST[511:256] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-450 Vol. 2B
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
INSTRUCTION SET REFERENCE, M-U
VPSRAW (ymm, ymm, xmm/m128) - VEX
DEST[255:0] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPSRAW (ymm, imm8) - VEX
DEST[255:0] ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0
VPSRAW (xmm, xmm, xmm/m128) - VEX
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSRAW (xmm, imm8) - VEX
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSRAW (xmm, xmm, xmm/m128)
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSRAW (xmm, imm8)
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
VPSRAD (EVEX versions, imm8)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)
ELSE DEST[i+31:i] ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRAD (EVEX versions, xmm/m128)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
TMP_DEST[127:0] ARITHMETIC_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
Vol. 2B 4-451
INSTRUCTION SET REFERENCE, M-U
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRAD (ymm, ymm, xmm/m128) - VEX
DEST[255:0] ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPSRAD (ymm, imm8) - VEX
DEST[255:0] ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0
VPSRAD (xmm, xmm, xmm/m128) - VEX
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSRAD (xmm, imm8) - VEX
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSRAD (xmm, xmm, xmm/m128)
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSRAD (xmm, imm8)
DEST[127:0] ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
VPSRAQ (EVEX versions, imm8)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)
ELSE DEST[i+63:i] ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
4-452 Vol. 2B
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
INSTRUCTION SET REFERENCE, M-U
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRAQ (EVEX versions, xmm/m128)
(KL, VL) = (2, 128), (4, 256), (8, 512)
TMP_DEST[VL-1:0] ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC1[VL-1:0], SRC2, VL)
FOR j 0 TO 7
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPSRAD __m512i _mm512_srai_epi32(__m512i a, unsigned int imm);
VPSRAD __m512i _mm512_mask_srai_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);
VPSRAD __m512i _mm512_maskz_srai_epi32( __mmask16 k, __m512i a, unsigned int imm);
VPSRAD __m256i _mm256_mask_srai_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRAD __m256i _mm256_maskz_srai_epi32( __mmask8 k, __m256i a, unsigned int imm);
VPSRAD __m128i _mm_mask_srai_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRAD __m128i _mm_maskz_srai_epi32( __mmask8 k, __m128i a, unsigned int imm);
VPSRAD __m512i _mm512_sra_epi32(__m512i a, __m128i cnt);
VPSRAD __m512i _mm512_mask_sra_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSRAD __m512i _mm512_maskz_sra_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSRAD __m256i _mm256_mask_sra_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAD __m256i _mm256_maskz_sra_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSRAD __m128i _mm_mask_sra_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAD __m128i _mm_maskz_sra_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRAQ __m512i _mm512_srai_epi64(__m512i a, unsigned int imm);
VPSRAQ __m512i _mm512_mask_srai_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm)
VPSRAQ __m512i _mm512_maskz_srai_epi64( __mmask8 k, __m512i a, unsigned int imm)
VPSRAQ __m256i _mm256_mask_srai_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRAQ __m256i _mm256_maskz_srai_epi64( __mmask8 k, __m256i a, unsigned int imm);
VPSRAQ __m128i _mm_mask_srai_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRAQ __m128i _mm_maskz_srai_epi64( __mmask8 k, __m128i a, unsigned int imm);
VPSRAQ __m512i _mm512_sra_epi64(__m512i a, __m128i cnt);
VPSRAQ __m512i _mm512_mask_sra_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt)
VPSRAQ __m512i _mm512_maskz_sra_epi64( __mmask8 k, __m512i a, __m128i cnt)
VPSRAQ __m256i _mm256_mask_sra_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAQ __m256i _mm256_maskz_sra_epi64( __mmask8 k, __m256i a, __m128i cnt);
VPSRAQ __m128i _mm_mask_sra_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAQ __m128i _mm_maskz_sra_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRAW __m512i _mm512_srai_epi16(__m512i a, unsigned int imm);
VPSRAW __m512i _mm512_mask_srai_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
Vol. 2B 4-453
INSTRUCTION SET REFERENCE, M-U
VPSRAW __m512i _mm512_maskz_srai_epi16( __mmask32 k, __m512i a, unsigned int imm);
VPSRAW __m256i _mm256_mask_srai_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
VPSRAW __m256i _mm256_maskz_srai_epi16( __mmask16 k, __m256i a, unsigned int imm);
VPSRAW __m128i _mm_mask_srai_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRAW __m128i _mm_maskz_srai_epi16( __mmask8 k, __m128i a, unsigned int imm);
VPSRAW __m512i _mm512_sra_epi16(__m512i a, __m128i cnt);
VPSRAW __m512i _mm512_mask_sra_epi16(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSRAW __m512i _mm512_maskz_sra_epi16( __mmask16 k, __m512i a, __m128i cnt);
VPSRAW __m256i _mm256_mask_sra_epi16(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAW __m256i _mm256_maskz_sra_epi16( __mmask8 k, __m256i a, __m128i cnt);
VPSRAW __m128i _mm_mask_sra_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAW __m128i _mm_maskz_sra_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSRAW:__m64 _mm_srai_pi16 (__m64 m, int count)
PSRAW:__m64 _mm_sra_pi16 (__m64 m, __m64 count)
(V)PSRAW:__m128i _mm_srai_epi16(__m128i m, int count)
(V)PSRAW:__m128i _mm_sra_epi16(__m128i m, __m128i count)
VPSRAW:__m256i _mm256_srai_epi16 (__m256i m, int count)
VPSRAW:__m256i _mm256_sra_epi16 (__m256i m, __m128i count)
PSRAD:__m64 _mm_srai_pi32 (__m64 m, int count)
PSRAD:__m64 _mm_sra_pi32 (__m64 m, __m64 count)
(V)PSRAD:__m128i _mm_srai_epi32 (__m128i m, int count)
(V)PSRAD:__m128i _mm_sra_epi32 (__m128i m, __m128i count)
VPSRAD:__m256i _mm256_srai_epi32 (__m256i m, int count)
VPSRAD:__m256i _mm256_sra_epi32 (__m256i m, __m128i count)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
VEX-encoded instructions:
Syntax with RM/RVM operand encoding, see Exceptions Type 4.
Syntax with MI/VMI operand encoding, see Exceptions Type 7.
EVEX-encoded VPSRAW, see Exceptions Type E4NF.nb.
EVEX-encoded VPSRAD/Q:
Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.
Syntax with FVI operand encoding, see Exceptions Type E4.
4-454 Vol. 2B
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic
INSTRUCTION SET REFERENCE, M-U
PSRLDQ—Shift Double Quadword Right Logical
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 73 /3 ib
MI
V/V
SSE2
Shift xmm1 right by imm8 while shifting in 0s.
VMI
V/V
AVX
Shift xmm2 right by imm8 bytes while shifting in
0s.
VMI
V/V
AVX2
Shift ymm1 right by imm8 bytes while shifting in
0s.
EVEX.NDD.128.66.0F.WIG 73 /3 ib
VPSRLDQ xmm1, xmm2/m128, imm8
FVM
V/V
AVX512VL Shift xmm2/m128 right by imm8 bytes while
AVX512BW shifting in 0s and store result in xmm1.
EVEX.NDD.256.66.0F.WIG 73 /3 ib
VPSRLDQ ymm1, ymm2/m256, imm8
FVM
V/V
AVX512VL Shift ymm2/m256 right by imm8 bytes while
AVX512BW shifting in 0s and store result in ymm1.
EVEX.NDD.512.66.0F.WIG 73 /3 ib
VPSRLDQ zmm1, zmm2/m512, imm8
FVM
V/V
AVX512BW Shift zmm2/m512 right by imm8 bytes while
shifting in 0s and store result in zmm1.
PSRLDQ xmm1, imm8
VEX.NDD.128.66.0F.WIG 73 /3 ib
VPSRLDQ xmm1, xmm2, imm8
VEX.NDD.256.66.0F.WIG 73 /3 ib
VPSRLDQ ymm1, ymm2, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MI
ModRM:r/m (r, w)
imm8
NA
NA
VMI
VEX.vvvv (w)
ModRM:r/m (r)
imm8
NA
FVM
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
Description
Shifts the destination operand (first operand) to the right by the number of bytes specified in the count operand
(second operand). The empty high-order bytes are cleared (set to all 0s). If the value specified by the count
operand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The source and destination operands are the same. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The source and destination operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed.
VEX.256 encoded version: The source operand is a YMM register. The destination operand is a YMM register. The
count operand applies to both the low and high 128-bit lanes.
VEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits
(MAX_VL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and
high 128-bit lanes.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.
Note: VEX.vvvv/EVEX.vvvv encodes the destination register.
PSRLDQ—Shift Double Quadword Right Logical
Vol. 2B 4-455
INSTRUCTION SET REFERENCE, M-U
Operation
VPSRLDQ (EVEX.512 encoded version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST[127:0] SRC[127:0] >> (TEMP * 8)
DEST[255:128] SRC[255:128] >> (TEMP * 8)
DEST[383:256] SRC[383:256] >> (TEMP * 8)
DEST[511:384] SRC[511:384] >> (TEMP * 8)
DEST[MAX_VL-1:512] 0;
VPSRLDQ (VEX.256 and EVEX.256 encoded version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST[127:0] SRC[127:0] >> (TEMP * 8)
DEST[255:128] SRC[255:128] >> (TEMP * 8)
DEST[MAX_VL-1:256] 0;
VPSRLDQ (VEX.128 and EVEX.128 encoded version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST SRC >> (TEMP * 8)
DEST[MAX_VL-1:128] 0;
PSRLDQ(128-bit Legacy SSE version)
TEMP COUNT
IF (TEMP > 15) THEN TEMP 16; FI
DEST DEST >> (TEMP * 8)
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalents
(V)PSRLDQ __m128i _mm_srli_si128 ( __m128i a, int imm)
VPSRLDQ __m256i _mm256_bsrli_epi128 ( __m256i, const int)
VPSRLDQ __m512i _mm512_bsrli_epi128 ( __m512i, int)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
4-456 Vol. 2B
PSRLDQ—Shift Double Quadword Right Logical
INSTRUCTION SET REFERENCE, M-U
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F D1 /r1
RM
V/V
MMX
Shift words in mm right by amount specified in
mm/m64 while shifting in 0s.
RM
V/V
SSE2
Shift words in xmm1 right by amount
specified in xmm2/m128 while shifting in 0s.
MI
V/V
MMX
Shift words in mm right by imm8 while shifting
in 0s.
MI
V/V
SSE2
Shift words in xmm1 right by imm8 while
shifting in 0s.
RM
V/V
MMX
Shift doublewords in mm right by amount
specified in mm/m64 while shifting in 0s.
RM
V/V
SSE2
Shift doublewords in xmm1 right by amount
specified in xmm2 /m128 while shifting in 0s.
MI
V/V
MMX
Shift doublewords in mm right by imm8 while
shifting in 0s.
MI
V/V
SSE2
Shift doublewords in xmm1 right by imm8
while shifting in 0s.
RM
V/V
MMX
Shift mm right by amount specified in
mm/m64 while shifting in 0s.
RM
V/V
SSE2
Shift quadwords in xmm1 right by amount
specified in xmm2/m128 while shifting in 0s.
MI
V/V
MMX
Shift mm right by imm8 while shifting in 0s.
MI
V/V
SSE2
Shift quadwords in xmm1 right by imm8 while
shifting in 0s.
RVM
V/V
AVX
Shift words in xmm2 right by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX
Shift words in xmm2 right by imm8 while
shifting in 0s.
RVM
V/V
AVX
Shift doublewords in xmm2 right by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX
Shift doublewords in xmm2 right by imm8
while shifting in 0s.
RVM
V/V
AVX
Shift quadwords in xmm2 right by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX
Shift quadwords in xmm2 right by imm8 while
shifting in 0s.
RVM
V/V
AVX2
Shift words in ymm2 right by amount specified
in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX2
Shift words in ymm2 right by imm8 while
shifting in 0s.
PSRLW mm, mm/m64
66 0F D1 /r
PSRLW xmm1, xmm2/m128
0F 71 /2 ib1
PSRLW mm, imm8
66 0F 71 /2 ib
PSRLW xmm1, imm8
0F D2 /r1
PSRLD mm, mm/m64
66 0F D2 /r
PSRLD xmm1, xmm2/m128
0F 72 /2 ib1
PSRLD mm, imm8
66 0F 72 /2 ib
PSRLD xmm1, imm8
0F D3 /r1
PSRLQ mm, mm/m64
66 0F D3 /r
PSRLQ xmm1, xmm2/m128
0F 73 /2 ib1
PSRLQ mm, imm8
66 0F 73 /2 ib
PSRLQ xmm1, imm8
VEX.NDS.128.66.0F.WIG D1 /r
VPSRLW xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 71 /2 ib
VPSRLW xmm1, xmm2, imm8
VEX.NDS.128.66.0F.WIG D2 /r
VPSRLD xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 72 /2 ib
VPSRLD xmm1, xmm2, imm8
VEX.NDS.128.66.0F.WIG D3 /r
VPSRLQ xmm1, xmm2, xmm3/m128
VEX.NDD.128.66.0F.WIG 73 /2 ib
VPSRLQ xmm1, xmm2, imm8
VEX.NDS.256.66.0F.WIG D1 /r
VPSRLW ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 71 /2 ib
VPSRLW ymm1, ymm2, imm8
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Vol. 2B 4-457
INSTRUCTION SET REFERENCE, M-U
VEX.NDS.256.66.0F.WIG D2 /r
RVM
V/V
AVX2
Shift doublewords in ymm2 right by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX2
Shift doublewords in ymm2 right by imm8
while shifting in 0s.
RVM
V/V
AVX2
Shift quadwords in ymm2 right by amount
specified in xmm3/m128 while shifting in 0s.
VMI
V/V
AVX2
Shift quadwords in ymm2 right by imm8 while
shifting in 0s.
VPSRLD ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 72 /2 ib
VPSRLD ymm1, ymm2, imm8
VEX.NDS.256.66.0F.WIG D3 /r
VPSRLQ ymm1, ymm2, xmm3/m128
VEX.NDD.256.66.0F.WIG 73 /2 ib
VPSRLQ ymm1, ymm2, imm8
EVEX.NDS.128.66.0F.WIG D1 /r
VPSRLW xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL
AVX512BW
Shift words in xmm2 right by amount specified
in xmm3/m128 while shifting in 0s using
writemask k1.
EVEX.NDS.256.66.0F.WIG D1 /r
VPSRLW ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL
AVX512BW
Shift words in ymm2 right by amount specified
in xmm3/m128 while shifting in 0s using
writemask k1.
EVEX.NDS.512.66.0F.WIG D1 /r
VPSRLW zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512BW
Shift words in zmm2 right by amount specified
in xmm3/m128 while shifting in 0s using
writemask k1.
EVEX.NDD.128.66.0F.WIG 71 /2 ib
VPSRLW xmm1 {k1}{z}, xmm2/m128, imm8
FVM
V/V
AVX512VL
AVX512BW
Shift words in xmm2/m128 right by imm8
while shifting in 0s using writemask k1.
EVEX.NDD.256.66.0F.WIG 71 /2 ib
VPSRLW ymm1 {k1}{z}, ymm2/m256, imm8
FVM
V/V
AVX512VL
AVX512BW
Shift words in ymm2/m256 right by imm8
while shifting in 0s using writemask k1.
EVEX.NDD.512.66.0F.WIG 71 /2 ib
VPSRLW zmm1 {k1}{z}, zmm2/m512, imm8
FVM
V/V
AVX512BW
Shift words in zmm2/m512 right by imm8
while shifting in 0s using writemask k1.
EVEX.NDS.128.66.0F.W0 D2 /r
VPSRLD xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift doublewords in xmm2 right by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
EVEX.NDS.256.66.0F.W0 D2 /r
VPSRLD ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift doublewords in ymm2 right by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
EVEX.NDS.512.66.0F.W0 D2 /r
VPSRLD zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512F
Shift doublewords in zmm2 right by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
EVEX.NDD.128.66.0F.W0 72 /2 ib
VPSRLD xmm1 {k1}{z}, xmm2/m128/m32bcst,
imm8
FV
V/V
AVX512VL
AVX512F
Shift doublewords in xmm2/m128/m32bcst
right by imm8 while shifting in 0s using
writemask k1.
EVEX.NDD.256.66.0F.W0 72 /2 ib
VPSRLD ymm1 {k1}{z}, ymm2/m256/m32bcst,
imm8
FV
V/V
AVX512VL
AVX512F
Shift doublewords in ymm2/m256/m32bcst
right by imm8 while shifting in 0s using
writemask k1.
EVEX.NDD.512.66.0F.W0 72 /2 ib
VPSRLD zmm1 {k1}{z}, zmm2/m512/m32bcst,
imm8
FVI
V/V
AVX512F
Shift doublewords in zmm2/m512/m32bcst
right by imm8 while shifting in 0s using
writemask k1.
EVEX.NDS.128.66.0F.W1 D3 /r
VPSRLQ xmm1 {k1}{z}, xmm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift quadwords in xmm2 right by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
EVEX.NDS.256.66.0F.W1 D3 /r
VPSRLQ ymm1 {k1}{z}, ymm2, xmm3/m128
M128 V/V
AVX512VL
AVX512F
Shift quadwords in ymm2 right by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
EVEX.NDS.512.66.0F.W1 D3 /r
VPSRLQ zmm1 {k1}{z}, zmm2, xmm3/m128
M128 V/V
AVX512F
Shift quadwords in zmm2 right by amount
specified in xmm3/m128 while shifting in 0s
using writemask k1.
4-458 Vol. 2B
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, M-U
EVEX.NDD.128.66.0F.W1 73 /2 ib
VPSRLQ xmm1 {k1}{z}, xmm2/m128/m64bcst,
imm8
FV
V/V
AVX512VL
AVX512F
Shift quadwords in xmm2/m128/m64bcst
right by imm8 while shifting in 0s using
writemask k1.
EVEX.NDD.256.66.0F.W1 73 /2 ib
VPSRLQ ymm1 {k1}{z}, ymm2/m256/m64bcst,
imm8
FV
V/V
AVX512VL
AVX512F
Shift quadwords in ymm2/m256/m64bcst
right by imm8 while shifting in 0s using
writemask k1.
EVEX.NDD.512.66.0F.W1 73 /2 ib
VPSRLQ zmm1 {k1}{z}, zmm2/m512/m64bcst,
imm8
FVI
V/V
AVX512F
Shift quadwords in zmm2/m512/m64bcst
right by imm8 while shifting in 0s using
writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
VMI
VEX.vvvv (w)
ModRM:r/m (r)
imm8
NA
FVM
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
FVI
EVEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
M128
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first
operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data
elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count
operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand
is set to all 0s. Figure 4-19 gives an example of shifting words in a 64-bit operand.
Note that only the low 64-bits of a 128-bit count operand are checked to compute the count.
Pre-Shift
DEST
X3
X2
X3 >> COUNT
X2 >> COUNT
X1
X0
Shift Right
with Zero
Extension
Post-Shift
DEST
X1 >> COUNT X0 >> COUNT
Figure 4-19. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand
The (V)PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits
specified in the count operand; the (V)PSRLD instruction shifts each of the doublewords in the destination operand;
and the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instruction 64-bit operand: The destination operand is an MMX technology register; the count operand
can be either an MMX technology register or an 64-bit memory location.
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Vol. 2B 4-459
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The destination operand is an XMM register; the count operand can be either an XMM
register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits
are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged.
VEX.128 encoded version: The destination operand is an XMM register; the count operand can be either an XMM
register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits
are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location. The count operand can come either from an XMM register or a memory location or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count
operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a
memory location (the variable count version). For the immediate count version, the source operand (the second
operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,
the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.
Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination
register, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.
Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /2, or EVEX.128.66.0F 71-73 /2),
VEX.vvvv/EVEX.vvvv encodes the destination register.
Operation
PSRLW (with 64-bit operand)
IF (COUNT > 15)
THEN
DEST[64:0] ← 0000000000000000H
ELSE
DEST[15:0] ← ZeroExtend(DEST[15:0] >> COUNT);
(* Repeat shift operation for 2nd and 3rd words *)
DEST[63:48] ← ZeroExtend(DEST[63:48] >> COUNT);
FI;
PSRLD (with 64-bit operand)
IF (COUNT > 31)
THEN
DEST[64:0] ← 0000000000000000H
ELSE
DEST[31:0] ← ZeroExtend(DEST[31:0] >> COUNT);
DEST[63:32] ← ZeroExtend(DEST[63:32] >> COUNT);
FI;
PSRLQ (with 64-bit operand)
IF (COUNT > 63)
THEN
DEST[64:0] ← 0000000000000000H
ELSE
DEST ← ZeroExtend(DEST >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
DEST[31:0] 0
ELSE
4-460 Vol. 2B
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, M-U
DEST[31:0] ZeroExtend(SRC[31:0] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
DEST[63:0] 0
ELSE
DEST[63:0] ZeroExtend(SRC[63:0] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
DEST[255:0] 0
ELSE
DEST[15:0] ZeroExtend(SRC[15:0] >> COUNT);
(* Repeat shift operation for 2nd through 15th words *)
DEST[255:240] ZeroExtend(SRC[255:240] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
DEST[127:0] 00000000000000000000000000000000H
ELSE
DEST[15:0] ZeroExtend(SRC[15:0] >> COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[127:112] ZeroExtend(SRC[127:112] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
DEST[255:0] 0
ELSE
DEST[31:0] ZeroExtend(SRC[31:0] >> COUNT);
(* Repeat shift operation for 2nd through 3rd words *)
DEST[255:224] ZeroExtend(SRC[255:224] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
DEST[127:0] 00000000000000000000000000000000H
ELSE
DEST[31:0] ZeroExtend(SRC[31:0] >> COUNT);
(* Repeat shift operation for 2nd through 3rd words *)
DEST[127:96] ZeroExtend(SRC[127:96] >> COUNT);
FI;
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Vol. 2B 4-461
INSTRUCTION SET REFERENCE, M-U
LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
DEST[255:0] 0
ELSE
DEST[63:0] ZeroExtend(SRC[63:0] >> COUNT);
DEST[127:64] ZeroExtend(SRC[127:64] >> COUNT);
DEST[191:128] ZeroExtend(SRC[191:128] >> COUNT);
DEST[255:192] ZeroExtend(SRC[255:192] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
DEST[127:0] 00000000000000000000000000000000H
ELSE
DEST[63:0] ZeroExtend(SRC[63:0] >> COUNT);
DEST[127:64] ZeroExtend(SRC[127:64] >> COUNT);
FI;
4-462 Vol. 2B
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, M-U
VPSRLW (EVEX versions, xmm/m128)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[127:0] LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRLW (EVEX versions, imm8)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[127:0] LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
TMP_DEST[511:256] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Vol. 2B 4-463
INSTRUCTION SET REFERENCE, M-U
VPSRLW (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0;
VPSRLW (ymm, imm8) - VEX.256 encoding
DEST[255:0] LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0;
VPSRLW (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSRLW (xmm, imm8) - VEX.128 encoding
DEST[127:0] LOGICAL_RIGHT_SHIFT_WORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSRLW (xmm, xmm, xmm/m128)
DEST[127:0] LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSRLW (xmm, imm8)
DEST[127:0] LOGICAL_RIGHT_SHIFT_WORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
VPSRLD (EVEX versions, xmm/m128)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
TMP_DEST[127:0] LOGICAL_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-464 Vol. 2B
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, M-U
VPSRLD (EVEX versions, imm8)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)
ELSE DEST[i+31:i] LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRLD (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0;
VPSRLD (ymm, imm8) - VEX.256 encoding
DEST[255:0] LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0;
VPSRLD (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSRLD (xmm, imm8) - VEX.128 encoding
DEST[127:0] LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSRLD (xmm, xmm, xmm/m128)
DEST[127:0] LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSRLD (xmm, imm8)
DEST[127:0] LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Vol. 2B 4-465
INSTRUCTION SET REFERENCE, M-U
VPSRLQ (EVEX versions, xmm/m128)
(KL, VL) = (2, 128), (4, 256), (8, 512)
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)
IF VL = 128
TMP_DEST[127:0] LOGICAL_RIGHT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
TMP_DEST[255:0] LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRLQ (EVEX versions, imm8)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)
ELSE DEST[i+63:i] LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSRLQ (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0;
VPSRLQ (ymm, imm8) - VEX.256 encoding
DEST[255:0] LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] 0;
4-466 Vol. 2B
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, M-U
VPSRLQ (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPSRLQ (xmm, imm8) - VEX.128 encoding
DEST[127:0] LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] 0
PSRLQ (xmm, xmm, xmm/m128)
DEST[127:0] LOGICAL_RIGHT_SHIFT_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
PSRLQ (xmm, imm8)
DEST[127:0] LOGICAL_RIGHT_SHIFT_QWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalents
VPSRLD __m512i _mm512_srli_epi32(__m512i a, unsigned int imm);
VPSRLD __m512i _mm512_mask_srli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);
VPSRLD __m512i _mm512_maskz_srli_epi32( __mmask16 k, __m512i a, unsigned int imm);
VPSRLD __m256i _mm256_mask_srli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRLD __m256i _mm256_maskz_srli_epi32( __mmask8 k, __m256i a, unsigned int imm);
VPSRLD __m128i _mm_mask_srli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRLD __m128i _mm_maskz_srli_epi32( __mmask8 k, __m128i a, unsigned int imm);
VPSRLD __m512i _mm512_srl_epi32(__m512i a, __m128i cnt);
VPSRLD __m512i _mm512_mask_srl_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSRLD __m512i _mm512_maskz_srl_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSRLD __m256i _mm256_mask_srl_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRLD __m256i _mm256_maskz_srl_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSRLD __m128i _mm_mask_srl_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLD __m128i _mm_maskz_srl_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRLQ __m512i _mm512_srli_epi64(__m512i a, unsigned int imm);
VPSRLQ __m512i _mm512_mask_srli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);
VPSRLQ __m512i _mm512_mask_srli_epi64( __mmask8 k, __m512i a, unsigned int imm);
VPSRLQ __m256i _mm256_mask_srli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRLQ __m256i _mm256_maskz_srli_epi64( __mmask8 k, __m256i a, unsigned int imm);
VPSRLQ __m128i _mm_mask_srli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRLQ __m128i _mm_maskz_srli_epi64( __mmask8 k, __m128i a, unsigned int imm);
VPSRLQ __m512i _mm512_srl_epi64(__m512i a, __m128i cnt);
VPSRLQ __m512i _mm512_mask_srl_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);
VPSRLQ __m512i _mm512_mask_srl_epi64( __mmask8 k, __m512i a, __m128i cnt);
VPSRLQ __m256i _mm256_mask_srl_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRLQ __m256i _mm256_maskz_srl_epi64( __mmask8 k, __m256i a, __m128i cnt);
VPSRLQ __m128i _mm_mask_srl_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLQ __m128i _mm_maskz_srl_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRLW __m512i _mm512_srli_epi16(__m512i a, unsigned int imm);
VPSRLW __m512i _mm512_mask_srli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);
VPSRLW __m512i _mm512_maskz_srli_epi16( __mmask32 k, __m512i a, unsigned int imm);
VPSRLW __m256i _mm256_mask_srlii_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
VPSRLW __m256i _mm256_maskz_srli_epi16( __mmask16 k, __m256i a, unsigned int imm);
VPSRLW __m128i _mm_mask_srli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRLW __m128i _mm_maskz_srli_epi16( __mmask8 k, __m128i a, unsigned int imm);
VPSRLW __m512i _mm512_srl_epi16(__m512i a, __m128i cnt);
VPSRLW __m512i _mm512_mask_srl_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Vol. 2B 4-467
INSTRUCTION SET REFERENCE, M-U
VPSRLW __m512i _mm512_maskz_srl_epi16( __mmask32 k, __m512i a, __m128i cnt);
VPSRLW __m256i _mm256_mask_srl_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);
VPSRLW __m256i _mm256_maskz_srl_epi16( __mmask8 k, __mmask16 a, __m128i cnt);
VPSRLW __m128i _mm_mask_srl_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLW __m128i _mm_maskz_srl_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSRLW:__m64 _mm_srli_pi16(__m64 m, int count)
PSRLW:__m64 _mm_srl_pi16 (__m64 m, __m64 count)
(V)PSRLW:__m128i _mm_srli_epi16 (__m128i m, int count)
(V)PSRLW:__m128i _mm_srl_epi16 (__m128i m, __m128i count)
VPSRLW:__m256i _mm256_srli_epi16 (__m256i m, int count)
VPSRLW:__m256i _mm256_srl_epi16 (__m256i m, __m128i count)
PSRLD:__m64 _mm_srli_pi32 (__m64 m, int count)
PSRLD:__m64 _mm_srl_pi32 (__m64 m, __m64 count)
(V)PSRLD:__m128i _mm_srli_epi32 (__m128i m, int count)
(V)PSRLD:__m128i _mm_srl_epi32 (__m128i m, __m128i count)
VPSRLD:__m256i _mm256_srli_epi32 (__m256i m, int count)
VPSRLD:__m256i _mm256_srl_epi32 (__m256i m, __m128i count)
PSRLQ:__m64 _mm_srli_si64 (__m64 m, int count)
PSRLQ:__m64 _mm_srl_si64 (__m64 m, __m64 count)
(V)PSRLQ:__m128i _mm_srli_epi64 (__m128i m, int count)
(V)PSRLQ:__m128i _mm_srl_epi64 (__m128i m, __m128i count)
VPSRLQ:__m256i _mm256_srli_epi64 (__m256i m, int count)
VPSRLQ:__m256i _mm256_srl_epi64 (__m256i m, __m128i count)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
VEX-encoded instructions:
Syntax with RM/RVM operand encoding, see Exceptions Type 4.
Syntax with MI/VMI operand encoding, see Exceptions Type 7.
EVEX-encoded VPSRLW, see Exceptions Type E4NF.nb.
EVEX-encoded VPSRLD/Q:
Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.
Syntax with FVI operand encoding, see Exceptions Type E4.
4-468 Vol. 2B
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, M-U
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F F8 /r1
RM
V/V
MMX
Subtract packed byte integers in mm/m64
from packed byte integers in mm.
RM
V/V
SSE2
Subtract packed byte integers in xmm2/m128
from packed byte integers in xmm1.
RM
V/V
MMX
Subtract packed word integers in mm/m64
from packed word integers in mm.
RM
V/V
SSE2
Subtract packed word integers in
xmm2/m128 from packed word integers in
xmm1.
RM
V/V
MMX
Subtract packed doubleword integers in
mm/m64 from packed doubleword integers in
mm.
RM
V/V
SSE2
Subtract packed doubleword integers in
xmm2/mem128 from packed doubleword
integers in xmm1.
PSUBB mm, mm/m64
66 0F F8 /r
PSUBB xmm1, xmm2/m128
0F F9 /r1
PSUBW mm, mm/m64
66 0F F9 /r
PSUBW xmm1, xmm2/m128
0F FA /r1
PSUBD mm, mm/m64
66 0F FA /r
PSUBD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG F8 /r
VPSUBB xmm1, xmm2, xmm3/m128
RVM V/V
AVX
Subtract packed byte integers in xmm3/m128
from xmm2.
VEX.NDS.128.66.0F.WIG F9 /r
RVM V/V
AVX
Subtract packed word integers in
xmm3/m128 from xmm2.
VEX.NDS.128.66.0F.WIG FA /r
VPSUBD xmm1, xmm2, xmm3/m128
RVM V/V
AVX
Subtract packed doubleword integers in
xmm3/m128 from xmm2.
VEX.NDS.256.66.0F.WIG F8 /r
VPSUBB ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Subtract packed byte integers in ymm3/m256
from ymm2.
VEX.NDS.256.66.0F.WIG F9 /r
VPSUBW ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Subtract packed word integers in
ymm3/m256 from ymm2.
VEX.NDS.256.66.0F.WIG FA /r
VPSUBD ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Subtract packed doubleword integers in
ymm3/m256 from ymm2.
EVEX.NDS.128.66.0F.WIG F8 /r
VPSUBB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Subtract packed byte integers in xmm3/m128
AVX512BW from xmm2 and store in xmm1 using
writemask k1.
EVEX.NDS.256.66.0F.WIG F8 /r
VPSUBB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Subtract packed byte integers in ymm3/m256
AVX512BW from ymm2 and store in ymm1 using
writemask k1.
EVEX.NDS.512.66.0F.WIG F8 /r
VPSUBB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Subtract packed byte integers in zmm3/m512
from zmm2 and store in zmm1 using
writemask k1.
EVEX.NDS.128.66.0F.WIG F9 /r
VPSUBW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Subtract packed word integers in
AVX512BW xmm3/m128 from xmm2 and store in xmm1
using writemask k1.
EVEX.NDS.256.66.0F.WIG F9 /r
VPSUBW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Subtract packed word integers in
AVX512BW ymm3/m256 from ymm2 and store in ymm1
using writemask k1.
EVEX.NDS.512.66.0F.WIG F9 /r
VPSUBW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Subtract packed word integers in
zmm3/m512 from zmm2 and store in zmm1
using writemask k1.
VPSUBW xmm1, xmm2, xmm3/m128
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
Vol. 2B 4-469
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.128.66.0F.W0 FA /r
FV
VPSUBD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst
V/V
AVX512VL
AVX512F
Subtract packed doubleword integers in
xmm3/m128/m32bcst from xmm2 and store
in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W0 FA /r
FV
VPSUBD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst
V/V
AVX512VL
AVX512F
Subtract packed doubleword integers in
ymm3/m256/m32bcst from ymm2 and store
in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W0 FA /r
VPSUBD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst
V/V
AVX512F
Subtract packed doubleword integers in
zmm3/m512/m32bcst from zmm2 and store
in zmm1 using writemask k1
FV
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed integers
of the destination operand (first operand), and stores the packed integer results in the destination operand. See
Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of
a SIMD operation. Overflow is handled with wraparound, as described in the following paragraphs.
The (V)PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small to be
represented in a byte, the result is wrapped around and the low 8 bits are written to the destination element.
The (V)PSUBW instruction subtracts packed word integers. When an individual result is too large or too small to be
represented in a word, the result is wrapped around and the low 16 bits are written to the destination element.
The (V)PSUBD instruction subtracts packed doubleword integers. When an individual result is too large or too small
to be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination
element.
Note that the (V)PSUBB, (V)PSUBW, and (V)PSUBD instructions can operate on either unsigned or signed (two's
complement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow
and/or a carry. To prevent undetected overflow conditions, software must control the ranges of values upon which
it operates.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source
operand can be either an MMX technology register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
4-470 Vol. 2B
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
INSTRUCTION SET REFERENCE, M-U
VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded VPSUBD: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and
destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.
EVEX encoded VPSUBB/W: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.
Operation
PSUBB (with 64-bit operands)
DEST[7:0] ← DEST[7:0] − SRC[7:0];
(* Repeat subtract operation for 2nd through 7th byte *)
DEST[63:56] ← DEST[63:56] − SRC[63:56];
PSUBW (with 64-bit operands)
DEST[15:0] ← DEST[15:0] − SRC[15:0];
(* Repeat subtract operation for 2nd and 3rd word *)
DEST[63:48] ← DEST[63:48] − SRC[63:48];
PSUBD (with 64-bit operands)
DEST[31:0] ← DEST[31:0] − SRC[31:0];
DEST[63:32] ← DEST[63:32] − SRC[63:32];
PSUBD (with 128-bit operands)
DEST[31:0] ← DEST[31:0] − SRC[31:0];
(* Repeat subtract operation for 2nd and 3rd doubleword *)
DEST[127:96] ← DEST[127:96] − SRC[127:96];
VPSUBB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SRC1[i+7:i] - SRC2[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPSUBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC1[i+15:i] - SRC2[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
Vol. 2B 4-471
INSTRUCTION SET REFERENCE, M-U
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] = 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPSUBD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SRC1[i+31:i] - SRC2[31:0]
ELSE DEST[i+31:i] SRC1[i+31:i] - SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPSUBB (VEX.256 encoded version)
DEST[7:0] SRC1[7:0]-SRC2[7:0]
DEST[15:8] SRC1[15:8]-SRC2[15:8]
DEST[23:16] SRC1[23:16]-SRC2[23:16]
DEST[31:24] SRC1[31:24]-SRC2[31:24]
DEST[39:32] SRC1[39:32]-SRC2[39:32]
DEST[47:40] SRC1[47:40]-SRC2[47:40]
DEST[55:48] SRC1[55:48]-SRC2[55:48]
DEST[63:56] SRC1[63:56]-SRC2[63:56]
DEST[71:64] SRC1[71:64]-SRC2[71:64]
DEST[79:72] SRC1[79:72]-SRC2[79:72]
DEST[87:80] SRC1[87:80]-SRC2[87:80]
DEST[95:88] SRC1[95:88]-SRC2[95:88]
DEST[103:96] SRC1[103:96]-SRC2[103:96]
DEST[111:104] SRC1[111:104]-SRC2[111:104]
DEST[119:112] SRC1[119:112]-SRC2[119:112]
DEST[127:120] SRC1[127:120]-SRC2[127:120]
DEST[135:128] SRC1[135:128]-SRC2[135:128]
DEST[143:136] SRC1[143:136]-SRC2[143:136]
DEST[151:144] SRC1[151:144]-SRC2[151:144]
DEST[159:152] SRC1[159:152]-SRC2[159:152]
DEST[167:160] SRC1[167:160]-SRC2[167:160]
DEST[175:168] SRC1[175:168]-SRC2[175:168]
DEST[183:176] SRC1[183:176]-SRC2[183:176]
DEST[191:184] SRC1[191:184]-SRC2[191:184]
DEST[199:192] SRC1[199:192]-SRC2[199:192]
DEST[207:200] SRC1[207:200]-SRC2[207:200]
4-472 Vol. 2B
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
INSTRUCTION SET REFERENCE, M-U
DEST[215:208] SRC1[215:208]-SRC2[215:208]
DEST[223:216] SRC1[223:216]-SRC2[223:216]
DEST[231:224] SRC1[231:224]-SRC2[231:224]
DEST[239:232] SRC1[239:232]-SRC2[239:232]
DEST[247:240] SRC1[247:240]-SRC2[247:240]
DEST[255:248] SRC1[255:248]-SRC2[255:248]
DEST[MAX_VL-1:256] 0
VPSUBB (VEX.128 encoded version)
DEST[7:0] SRC1[7:0]-SRC2[7:0]
DEST[15:8] SRC1[15:8]-SRC2[15:8]
DEST[23:16] SRC1[23:16]-SRC2[23:16]
DEST[31:24] SRC1[31:24]-SRC2[31:24]
DEST[39:32] SRC1[39:32]-SRC2[39:32]
DEST[47:40] SRC1[47:40]-SRC2[47:40]
DEST[55:48] SRC1[55:48]-SRC2[55:48]
DEST[63:56] SRC1[63:56]-SRC2[63:56]
DEST[71:64] SRC1[71:64]-SRC2[71:64]
DEST[79:72] SRC1[79:72]-SRC2[79:72]
DEST[87:80] SRC1[87:80]-SRC2[87:80]
DEST[95:88] SRC1[95:88]-SRC2[95:88]
DEST[103:96] SRC1[103:96]-SRC2[103:96]
DEST[111:104] SRC1[111:104]-SRC2[111:104]
DEST[119:112] SRC1[119:112]-SRC2[119:112]
DEST[127:120] SRC1[127:120]-SRC2[127:120]
DEST[MAX_VL-1:128] 0
PSUBB (128-bit Legacy SSE version)
DEST[7:0] DEST[7:0]-SRC[7:0]
DEST[15:8] DEST[15:8]-SRC[15:8]
DEST[23:16] DEST[23:16]-SRC[23:16]
DEST[31:24] DEST[31:24]-SRC[31:24]
DEST[39:32] DEST[39:32]-SRC[39:32]
DEST[47:40] DEST[47:40]-SRC[47:40]
DEST[55:48] DEST[55:48]-SRC[55:48]
DEST[63:56] DEST[63:56]-SRC[63:56]
DEST[71:64] DEST[71:64]-SRC[71:64]
DEST[79:72] DEST[79:72]-SRC[79:72]
DEST[87:80] DEST[87:80]-SRC[87:80]
DEST[95:88] DEST[95:88]-SRC[95:88]
DEST[103:96] DEST[103:96]-SRC[103:96]
DEST[111:104] DEST[111:104]-SRC[111:104]
DEST[119:112] DEST[119:112]-SRC[119:112]
DEST[127:120] DEST[127:120]-SRC[127:120]
DEST[MAX_VL-1:128] (Unmodified)
VPSUBW (VEX.256 encoded version)
DEST[15:0] SRC1[15:0]-SRC2[15:0]
DEST[31:16] SRC1[31:16]-SRC2[31:16]
DEST[47:32] SRC1[47:32]-SRC2[47:32]
DEST[63:48] SRC1[63:48]-SRC2[63:48]
DEST[79:64] SRC1[79:64]-SRC2[79:64]
DEST[95:80] SRC1[95:80]-SRC2[95:80]
DEST[111:96] SRC1[111:96]-SRC2[111:96]
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
Vol. 2B 4-473
INSTRUCTION SET REFERENCE, M-U
DEST[127:112] SRC1[127:112]-SRC2[127:112]
DEST[143:128] SRC1[143:128]-SRC2[143:128]
DEST[159:144] SRC1[159:144]-SRC2[159:144]
DEST[175:160] SRC1[175:160]-SRC2[175:160]
DEST[191:176] SRC1[191:176]-SRC2[191:176]
DEST[207:192] SRC1207:192]-SRC2[207:192]
DEST[223:208] SRC1[223:208]-SRC2[223:208]
DEST[239:224] SRC1[239:224]-SRC2[239:224]
DEST[255:240] SRC1[255:240]-SRC2[255:240]
DEST[MAX_VL-1:256] 0
VPSUBW (VEX.128 encoded version)
DEST[15:0] SRC1[15:0]-SRC2[15:0]
DEST[31:16] SRC1[31:16]-SRC2[31:16]
DEST[47:32] SRC1[47:32]-SRC2[47:32]
DEST[63:48] SRC1[63:48]-SRC2[63:48]
DEST[79:64] SRC1[79:64]-SRC2[79:64]
DEST[95:80] SRC1[95:80]-SRC2[95:80]
DEST[111:96] SRC1[111:96]-SRC2[111:96]
DEST[127:112] SRC1[127:112]-SRC2[127:112]
DEST[MAX_VL-1:128] 0
PSUBW (128-bit Legacy SSE version)
DEST[15:0] DEST[15:0]-SRC[15:0]
DEST[31:16] DEST[31:16]-SRC[31:16]
DEST[47:32] DEST[47:32]-SRC[47:32]
DEST[63:48] DEST[63:48]-SRC[63:48]
DEST[79:64] DEST[79:64]-SRC[79:64]
DEST[95:80] DEST[95:80]-SRC[95:80]
DEST[111:96] DEST[111:96]-SRC[111:96]
DEST[127:112] DEST[127:112]-SRC[127:112]
DEST[MAX_VL-1:128] (Unmodified)
VPSUBD (VEX.256 encoded version)
DEST[31:0] SRC1[31:0]-SRC2[31:0]
DEST[63:32] SRC1[63:32]-SRC2[63:32]
DEST[95:64] SRC1[95:64]-SRC2[95:64]
DEST[127:96] SRC1[127:96]-SRC2[127:96]
DEST[159:128] SRC1[159:128]-SRC2[159:128]
DEST[191:160] SRC1[191:160]-SRC2[191:160]
DEST[223:192] SRC1[223:192]-SRC2[223:192]
DEST[255:224] SRC1[255:224]-SRC2[255:224]
DEST[MAX_VL-1:256] 0
VPSUBD (VEX.128 encoded version)
DEST[31:0] SRC1[31:0]-SRC2[31:0]
DEST[63:32] SRC1[63:32]-SRC2[63:32]
DEST[95:64] SRC1[95:64]-SRC2[95:64]
DEST[127:96] SRC1[127:96]-SRC2[127:96]
DEST[MAX_VL-1:128] 0
PSUBD (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0]-SRC[31:0]
DEST[63:32] DEST[63:32]-SRC[63:32]
4-474 Vol. 2B
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
INSTRUCTION SET REFERENCE, M-U
DEST[95:64] DEST[95:64]-SRC[95:64]
DEST[127:96] DEST[127:96]-SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalents
VPSUBB __m512i _mm512_sub_epi8(__m512i a, __m512i b);
VPSUBB __m512i _mm512_mask_sub_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSUBB __m512i _mm512_maskz_sub_epi8( __mmask64 k, __m512i a, __m512i b);
VPSUBB __m256i _mm256_mask_sub_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSUBB __m256i _mm256_maskz_sub_epi8( __mmask32 k, __m256i a, __m256i b);
VPSUBB __m128i _mm_mask_sub_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSUBB __m128i _mm_maskz_sub_epi8( __mmask16 k, __m128i a, __m128i b);
VPSUBW __m512i _mm512_sub_epi16(__m512i a, __m512i b);
VPSUBW __m512i _mm512_mask_sub_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPSUBW __m512i _mm512_maskz_sub_epi16( __mmask32 k, __m512i a, __m512i b);
VPSUBW __m256i _mm256_mask_sub_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPSUBW __m256i _mm256_maskz_sub_epi16( __mmask16 k, __m256i a, __m256i b);
VPSUBW __m128i _mm_mask_sub_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBW __m128i _mm_maskz_sub_epi16( __mmask8 k, __m128i a, __m128i b);
VPSUBD __m512i _mm512_sub_epi32(__m512i a, __m512i b);
VPSUBD __m512i _mm512_mask_sub_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPSUBD __m512i _mm512_maskz_sub_epi32( __mmask16 k, __m512i a, __m512i b);
VPSUBD __m256i _mm256_mask_sub_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPSUBD __m256i _mm256_maskz_sub_epi32( __mmask8 k, __m256i a, __m256i b);
VPSUBD __m128i _mm_mask_sub_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBD __m128i _mm_maskz_sub_epi32( __mmask8 k, __m128i a, __m128i b);
PSUBB:__m64 _mm_sub_pi8(__m64 m1, __m64 m2)
(V)PSUBB:__m128i _mm_sub_epi8 ( __m128i a, __m128i b)
VPSUBB:__m256i _mm256_sub_epi8 ( __m256i a, __m256i b)
PSUBW:__m64 _mm_sub_pi16(__m64 m1, __m64 m2)
(V)PSUBW:__m128i _mm_sub_epi16 ( __m128i a, __m128i b)
VPSUBW:__m256i _mm256_sub_epi16 ( __m256i a, __m256i b)
PSUBD:__m64 _mm_sub_pi32(__m64 m1, __m64 m2)
(V)PSUBD:__m128i _mm_sub_epi32 ( __m128i a, __m128i b)
VPSUBD:__m256i _mm256_sub_epi32 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPSUBD, see Exceptions Type E4.
EVEX-encoded VPSUBB/W, see Exceptions Type E4.nb.
PSUBB/PSUBW/PSUBD—Subtract Packed Integers
Vol. 2B 4-475
INSTRUCTION SET REFERENCE, M-U
PSUBQ—Subtract Packed Quadword Integers
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F FB /r1
RM
V/V
SSE2
Subtract quadword integer in mm1 from mm2
/m64.
RM
V/V
SSE2
Subtract packed quadword integers in xmm1
from xmm2 /m128.
RVM V/V
AVX
Subtract packed quadword integers in
xmm3/m128 from xmm2.
RVM V/V
AVX2
Subtract packed quadword integers in
ymm3/m256 from ymm2.
PSUBQ mm1, mm2/m64
66 0F FB /r
PSUBQ xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG FB/r
VPSUBQ xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG FB /r
VPSUBQ ymm1, ymm2, ymm3/m256
EVEX.NDS.128.66.0F.W1 FB /r
FV
VPSUBQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst
V/V
AVX512VL Subtract packed quadword integers in
AVX512F
xmm3/m128/m64bcst from xmm2 and store
in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W1 FB /r
FV
VPSUBQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
V/V
AVX512VL Subtract packed quadword integers in
AVX512F
ymm3/m256/m64bcst from ymm2 and store
in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W1 FB/r
FV
VPSUBQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst
V/V
AVX512F
Subtract packed quadword integers in
zmm3/m512/m64bcst from zmm2 and store
in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result
in the destination operand. When packed quadword operands are used, a SIMD subtract is performed. When a
quadword result is too large to be represented in 64 bits (overflow), the result is wrapped around and the low 64
bits are written to the destination element (that is, the carry is ignored).
Note that the (V)PSUBQ instruction can operate on either unsigned or signed (two’s complement notation) integers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected
overflow conditions, software must control the ranges of the values upon which it operates.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be a quadword integer stored in an MMX technology
register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
4-476 Vol. 2B
PSUBQ—Subtract Packed Quadword Integers
INSTRUCTION SET REFERENCE, M-U
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded VPSUBQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and
destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.
Operation
PSUBQ (with 64-Bit operands)
DEST[63:0] ← DEST[63:0] − SRC[63:0];
PSUBQ (with 128-Bit operands)
DEST[63:0] ← DEST[63:0] − SRC[63:0];
DEST[127:64] ← DEST[127:64] − SRC[127:64];
VPSUBQ (VEX.128 encoded version)
DEST[63:0] SRC1[63:0]-SRC2[63:0]
DEST[127:64] SRC1[127:64]-SRC2[127:64]
DEST[VLMAX-1:128] 0
VPSUBQ (VEX.256 encoded version)
DEST[63:0] SRC1[63:0]-SRC2[63:0]
DEST[127:64] SRC1[127:64]-SRC2[127:64]
DEST[191:128] SRC1[191:128]-SRC2[191:128]
DEST[255:192] SRC1[255:192]-SRC2[255:192]
DEST[VLMAX-1:256] 0
VPSUBQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] SRC1[i+63:i] - SRC2[63:0]
ELSE DEST[i+63:i] SRC1[i+63:i] - SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPSUBQ __m512i _mm512_sub_epi64(__m512i a, __m512i b);
VPSUBQ __m512i _mm512_mask_sub_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPSUBQ __m512i _mm512_maskz_sub_epi64( __mmask8 k, __m512i a, __m512i b);
VPSUBQ __m256i _mm256_mask_sub_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
PSUBQ—Subtract Packed Quadword Integers
Vol. 2B 4-477
INSTRUCTION SET REFERENCE, M-U
VPSUBQ __m256i _mm256_maskz_sub_epi64( __mmask8 k, __m256i a, __m256i b);
VPSUBQ __m128i _mm_mask_sub_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBQ __m128i _mm_maskz_sub_epi64( __mmask8 k, __m128i a, __m128i b);
PSUBQ:__m64 _mm_sub_si64(__m64 m1, __m64 m2)
(V)PSUBQ:__m128i _mm_sub_epi64(__m128i m1, __m128i m2)
VPSUBQ:__m256i _mm256_sub_epi64(__m256i m1, __m256i m2)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPSUBQ, see Exceptions Type E4.
4-478 Vol. 2B
PSUBQ—Subtract Packed Quadword Integers
INSTRUCTION SET REFERENCE, M-U
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F E8 /r1
RM
V/V
MMX
Subtract signed packed bytes in mm/m64 from
signed packed bytes in mm and saturate results.
RM
V/V
SSE2
Subtract packed signed byte integers in
xmm2/m128 from packed signed byte integers
in xmm1 and saturate results.
RM
V/V
MMX
Subtract signed packed words in mm/m64 from
signed packed words in mm and saturate
results.
RM
V/V
SSE2
Subtract packed signed word integers in
xmm2/m128 from packed signed word integers
in xmm1 and saturate results.
RVM V/V
AVX
Subtract packed signed byte integers in
xmm3/m128 from packed signed byte integers
in xmm2 and saturate results.
RVM V/V
AVX
Subtract packed signed word integers in
xmm3/m128 from packed signed word integers
in xmm2 and saturate results.
RVM V/V
AVX2
Subtract packed signed byte integers in
ymm3/m256 from packed signed byte integers
in ymm2 and saturate results.
RVM V/V
AVX2
Subtract packed signed word integers in
ymm3/m256 from packed signed word integers
in ymm2 and saturate results.
EVEX.NDS.128.66.0F.WIG E8 /r
VPSUBSB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Subtract packed signed byte integers in
AVX512BW xmm3/m128 from packed signed byte integers
in xmm2 and saturate results and store in
xmm1 using writemask k1.
EVEX.NDS.256.66.0F.WIG E8 /r
VPSUBSB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Subtract packed signed byte integers in
AVX512BW ymm3/m256 from packed signed byte integers
in ymm2 and saturate results and store in
ymm1 using writemask k1.
EVEX.NDS.512.66.0F.WIG E8 /r
VPSUBSB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Subtract packed signed byte integers in
zmm3/m512 from packed signed byte integers
in zmm2 and saturate results and store in zmm1
using writemask k1.
EVEX.NDS.128.66.0F.WIG E9 /r
VPSUBSW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Subtract packed signed word integers in
AVX512BW xmm3/m128 from packed signed word integers
in xmm2 and saturate results and store in
xmm1 using writemask k1.
EVEX.NDS.256.66.0F.WIG E9 /r
VPSUBSW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Subtract packed signed word integers in
AVX512BW ymm3/m256 from packed signed word integers
in ymm2 and saturate results and store in
ymm1 using writemask k1.
PSUBSB mm, mm/m64
66 0F E8 /r
PSUBSB xmm1, xmm2/m128
0F E9 /r1
PSUBSW mm, mm/m64
66 0F E9 /r
PSUBSW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG E8 /r
VPSUBSB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG E9 /r
VPSUBSW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG E8 /r
VPSUBSB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG E9 /r
VPSUBSW ymm1, ymm2, ymm3/m256
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation
Vol. 2B 4-479
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.512.66.0F.WIG E9 /r
VPSUBSW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Subtract packed signed word integers in
zmm3/m512 from packed signed word integers
in zmm2 and saturate results and store in zmm1
using writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD subtract of the packed signed integers of the source operand (second operand) from the packed
signed integers of the destination operand (first operand), and stores the packed integer results in the destination
operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an
illustration of a SIMD operation. Overflow is handled with signed saturation, as described in the following paragraphs.
The (V)PSUBSB instruction subtracts packed signed byte integers. When an individual byte result is beyond the
range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value of 7FH or 80H,
respectively, is written to the destination operand.
The (V)PSUBSW instruction subtracts packed signed word integers. When an individual word result is beyond the
range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the saturated value of 7FFFH or
8000H, respectively, is written to the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source
operand can be either an MMX technology register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.
Operation
PSUBSB (with 64-bit operands)
DEST[7:0] ← SaturateToSignedByte (DEST[7:0] − SRC (7:0]);
(* Repeat subtract operation for 2nd through 7th bytes *)
DEST[63:56] ← SaturateToSignedByte (DEST[63:56] − SRC[63:56] );
4-480 Vol. 2B
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
PSUBSW (with 64-bit operands)
DEST[15:0] ← SaturateToSignedWord (DEST[15:0] − SRC[15:0] );
(* Repeat subtract operation for 2nd and 7th words *)
DEST[63:48] ← SaturateToSignedWord (DEST[63:48] − SRC[63:48] );
VPSUBSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
i j * 8;
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateToSignedByte (SRC1[i+7:i] - SRC2[i+7:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0;
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPSUBSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateToSignedWord (SRC1[i+15:i] - SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0;
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
VPSUBSB (VEX.256 encoded version)
DEST[7:0] SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31th bytes *)
DEST[255:248] SaturateToSignedByte (SRC1[255:248] - SRC2[255:248]);
DEST[MAX_VL-1:256] 0;
VPSUBSB (VEX.128 encoded version)
DEST[7:0] SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] SaturateToSignedByte (SRC1[127:120] - SRC2[127:120]);
DEST[MAX_VL-1:128] 0;
PSUBSB (128-bit Legacy SSE Version)
DEST[7:0] SaturateToSignedByte (DEST[7:0] - SRC[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] SaturateToSignedByte (DEST[127:120] - SRC[127:120]);
DEST[MAX_VL-1:128] (Unmodified);
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation
Vol. 2B 4-481
INSTRUCTION SET REFERENCE, M-U
VPSUBSW (VEX.256 encoded version)
DEST[15:0] SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 15th words *)
DEST[255:240] SaturateToSignedWord (SRC1[255:240] - SRC2[255:240]);
DEST[MAX_VL-1:256] 0;
VPSUBSW (VEX.128 encoded version)
DEST[15:0] SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] SaturateToSignedWord (SRC1[127:112] - SRC2[127:112]);
DEST[MAX_VL-1:128] 0;
PSUBSW (128-bit Legacy SSE Version)
DEST[15:0] SaturateToSignedWord (DEST[15:0] - SRC[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] SaturateToSignedWord (DEST[127:112] - SRC[127:112]);
DEST[MAX_VL-1:128] (Unmodified);
Intel C/C++ Compiler Intrinsic Equivalents
VPSUBSB __m512i _mm512_subs_epi8(__m512i a, __m512i b);
VPSUBSB __m512i _mm512_mask_subs_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSUBSB __m512i _mm512_maskz_subs_epi8( __mmask64 k, __m512i a, __m512i b);
VPSUBSB __m256i _mm256_mask_subs_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSUBSB __m256i _mm256_maskz_subs_epi8( __mmask32 k, __m256i a, __m256i b);
VPSUBSB __m128i _mm_mask_subs_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSUBSB __m128i _mm_maskz_subs_epi8( __mmask16 k, __m128i a, __m128i b);
VPSUBSW __m512i _mm512_subs_epi16(__m512i a, __m512i b);
VPSUBSW __m512i _mm512_mask_subs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPSUBSW __m512i _mm512_maskz_subs_epi16( __mmask32 k, __m512i a, __m512i b);
VPSUBSW __m256i _mm256_mask_subs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPSUBSW __m256i _mm256_maskz_subs_epi16( __mmask16 k, __m256i a, __m256i b);
VPSUBSW __m128i _mm_mask_subs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBSW __m128i _mm_maskz_subs_epi16( __mmask8 k, __m128i a, __m128i b);
PSUBSB:__m64 _mm_subs_pi8(__m64 m1, __m64 m2)
(V)PSUBSB:__m128i _mm_subs_epi8(__m128i m1, __m128i m2)
VPSUBSB:__m256i _mm256_subs_epi8(__m256i m1, __m256i m2)
PSUBSW:__m64 _mm_subs_pi16(__m64 m1, __m64 m2)
(V)PSUBSW:__m128i _mm_subs_epi16(__m128i m1, __m128i m2)
VPSUBSW:__m256i _mm256_subs_epi16(__m256i m1, __m256i m2)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
4-482 Vol. 2B
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation
INSTRUCTION SET REFERENCE, M-U
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F D8 /r1
RM
V/V
MMX
Subtract unsigned packed bytes in mm/m64
from unsigned packed bytes in mm and
saturate result.
RM
V/V
SSE2
Subtract packed unsigned byte integers in
xmm2/m128 from packed unsigned byte
integers in xmm1 and saturate result.
RM
V/V
MMX
Subtract unsigned packed words in mm/m64
from unsigned packed words in mm and
saturate result.
RM
V/V
SSE2
Subtract packed unsigned word integers in
xmm2/m128 from packed unsigned word
integers in xmm1 and saturate result.
RVM V/V
AVX
Subtract packed unsigned byte integers in
xmm3/m128 from packed unsigned byte
integers in xmm2 and saturate result.
RVM V/V
AVX
Subtract packed unsigned word integers in
xmm3/m128 from packed unsigned word
integers in xmm2 and saturate result.
RVM V/V
AVX2
Subtract packed unsigned byte integers in
ymm3/m256 from packed unsigned byte
integers in ymm2 and saturate result.
RVM V/V
AVX2
Subtract packed unsigned word integers in
ymm3/m256 from packed unsigned word
integers in ymm2 and saturate result.
EVEX.NDS.128.66.0F.WIG D8 /r
VPSUBUSB xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Subtract packed unsigned byte integers in
AVX512BW xmm3/m128 from packed unsigned byte
integers in xmm2, saturate results and store
in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.WIG D8 /r
VPSUBUSB ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Subtract packed unsigned byte integers in
AVX512BW ymm3/m256 from packed unsigned byte
integers in ymm2, saturate results and store
in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.WIG D8 /r
VPSUBUSB zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Subtract packed unsigned byte integers in
zmm3/m512 from packed unsigned byte
integers in zmm2, saturate results and store
in zmm1 using writemask k1.
EVEX.NDS.128.66.0F.WIG D9 /r
VPSUBUSW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Subtract packed unsigned word integers in
AVX512BW xmm3/m128 from packed unsigned word
integers in xmm2 and saturate results and
store in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.WIG D9 /r
VPSUBUSW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Subtract packed unsigned word integers in
AVX512BW ymm3/m256 from packed unsigned word
integers in ymm2, saturate results and store
in ymm1 using writemask k1.
PSUBUSB mm, mm/m64
66 0F D8 /r
PSUBUSB xmm1, xmm2/m128
0F D9 /r1
PSUBUSW mm, mm/m64
66 0F D9 /r
PSUBUSW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG D8 /r
VPSUBUSB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG D9 /r
VPSUBUSW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG D8 /r
VPSUBUSB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG D9 /r
VPSUBUSW ymm1, ymm2, ymm3/m256
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation
Vol. 2B 4-483
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.512.66.0F.WIG D9 /r
VPSUBUSW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Subtract packed unsigned word integers in
zmm3/m512 from packed unsigned word
integers in zmm2, saturate results and store
in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD subtract of the packed unsigned integers of the source operand (second operand) from the
packed unsigned integers of the destination operand (first operand), and stores the packed unsigned integer
results in the destination operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with unsigned saturation, as
described in the following paragraphs.
These instructions can operate on either 64-bit or 128-bit operands.
The (V)PSUBUSB instruction subtracts packed unsigned byte integers. When an individual byte result is less than
zero, the saturated value of 00H is written to the destination operand.
The (V)PSUBUSW instruction subtracts packed unsigned word integers. When an individual word result is less than
zero, the saturated value of 0000H is written to the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source
operand can be either an MMX technology register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.
Operation
PSUBUSB (with 64-bit operands)
DEST[7:0] ← SaturateToUnsignedByte (DEST[7:0] − SRC (7:0] );
(* Repeat add operation for 2nd through 7th bytes *)
DEST[63:56] ← SaturateToUnsignedByte (DEST[63:56] − SRC[63:56];
4-484 Vol. 2B
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
PSUBUSW (with 64-bit operands)
DEST[15:0] ← SaturateToUnsignedWord (DEST[15:0] − SRC[15:0] );
(* Repeat add operation for 2nd and 3rd words *)
DEST[63:48] ← SaturateToUnsignedWord (DEST[63:48] − SRC[63:48] );
VPSUBUSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
i j * 8;
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateToUnsignedByte (SRC1[i+7:i] - SRC2[i+7:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0;
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
VPSUBUSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16;
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateToUnsignedWord (SRC1[i+15:i] - SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0;
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
VPSUBUSB (VEX.256 encoded version)
DEST[7:0] SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31st bytes *)
DEST[255:148] SaturateToUnsignedByte (SRC1[255:248] - SRC2[255:248]);
DEST[MAX_VL-1:256] 0;
VPSUBUSB (VEX.128 encoded version)
DEST[7:0] SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] SaturateToUnsignedByte (SRC1[127:120] - SRC2[127:120]);
DEST[MAX_VL-1:128] 0
PSUBUSB (128-bit Legacy SSE Version)
DEST[7:0] SaturateToUnsignedByte (DEST[7:0] - SRC[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] SaturateToUnsignedByte (DEST[127:120] - SRC[127:120]);
DEST[MAX_VL-1:128] (Unmodified)
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation
Vol. 2B 4-485
INSTRUCTION SET REFERENCE, M-U
VPSUBUSW (VEX.256 encoded version)
DEST[15:0] SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 15th words *)
DEST[255:240] SaturateToUnsignedWord (SRC1[255:240] - SRC2[255:240]);
DEST[MAX_VL-1:256] 0;
VPSUBUSW (VEX.128 encoded version)
DEST[15:0] SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] SaturateToUnsignedWord (SRC1[127:112] - SRC2[127:112]);
DEST[MAX_VL-1:128] 0
PSUBUSW (128-bit Legacy SSE Version)
DEST[15:0] SaturateToUnsignedWord (DEST[15:0] - SRC[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] SaturateToUnsignedWord (DEST[127:112] - SRC[127:112]);
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalents
VPSUBUSB __m512i _mm512_subs_epu8(__m512i a, __m512i b);
VPSUBUSB __m512i _mm512_mask_subs_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSUBUSB __m512i _mm512_maskz_subs_epu8( __mmask64 k, __m512i a, __m512i b);
VPSUBUSB __m256i _mm256_mask_subs_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSUBUSB __m256i _mm256_maskz_subs_epu8( __mmask32 k, __m256i a, __m256i b);
VPSUBUSB __m128i _mm_mask_subs_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSUBUSB __m128i _mm_maskz_subs_epu8( __mmask16 k, __m128i a, __m128i b);
VPSUBUSW __m512i _mm512_subs_epu16(__m512i a, __m512i b);
VPSUBUSW __m512i _mm512_mask_subs_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPSUBUSW __m512i _mm512_maskz_subs_epu16( __mmask32 k, __m512i a, __m512i b);
VPSUBUSW __m256i _mm256_mask_subs_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPSUBUSW __m256i _mm256_maskz_subs_epu16( __mmask16 k, __m256i a, __m256i b);
VPSUBUSW __m128i _mm_mask_subs_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBUSW __m128i _mm_maskz_subs_epu16( __mmask8 k, __m128i a, __m128i b);
PSUBUSB:__m64 _mm_subs_pu8(__m64 m1, __m64 m2)
(V)PSUBUSB:__m128i _mm_subs_epu8(__m128i m1, __m128i m2)
VPSUBUSB:__m256i _mm256_subs_epu8(__m256i m1, __m256i m2)
PSUBUSW:__m64 _mm_subs_pu16(__m64 m1, __m64 m2)
(V)PSUBUSW:__m128i _mm_subs_epu16(__m128i m1, __m128i m2)
VPSUBUSW:__m256i _mm256_subs_epu16(__m256i m1, __m256i m2)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
4-486 Vol. 2B
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation
INSTRUCTION SET REFERENCE, M-U
PTEST- Logical Compare
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 38 17 /r
PTEST xmm1, xmm2/m128
RM
V/V
SSE4_1
Set ZF if xmm2/m128 AND xmm1 result is all
0s. Set CF if xmm2/m128 AND NOT xmm1
result is all 0s.
VEX.128.66.0F38.WIG 17 /r
VPTEST xmm1, xmm2/m128
RM
V/V
AVX
Set ZF and CF depending on bitwise AND and
ANDN of sources.
VEX.256.66.0F38.WIG 17 /r
VPTEST ymm1, ymm2/m256
RM
V/V
AVX
Set ZF and CF depending on bitwise AND and
ANDN of sources.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
Description
PTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise AND of the first source operand (first
operand) and the second source operand (second operand). VPTEST sets the CF flag if all bits in the result are 0 of
the bitwise AND of the second source operand (second operand) and the logical NOT of the destination operand.
The first source register is specified by the ModR/M reg field.
128-bit versions: The first source register is an XMM register. The second source register can be an XMM register
or a 128-bit memory location. The destination register is not modified.
VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM
register or a 256-bit memory location. The destination register is not modified.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
(V)PTEST (128-bit version)
IF (SRC[127:0] BITWISE AND DEST[127:0] = 0)
THEN ZF 1;
ELSE ZF 0;
IF (SRC[127:0] BITWISE AND NOT DEST[127:0] = 0)
THEN CF 1;
ELSE CF 0;
DEST (unmodified)
AF OF PF SF 0;
VPTEST (VEX.256 encoded version)
IF (SRC[255:0] BITWISE AND DEST[255:0] = 0) THEN ZF 1;
ELSE ZF 0;
IF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF 1;
ELSE CF 0;
DEST (unmodified)
AF OF PF SF 0;
PTEST- Logical Compare
Vol. 2B 4-487
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
PTEST
int _mm_testz_si128 (__m128i s1, __m128i s2);
int _mm_testc_si128 (__m128i s1, __m128i s2);
int _mm_testnzc_si128 (__m128i s1, __m128i s2);
VPTEST
int _mm256_testz_si256 (__m256i s1, __m256i s2);
int _mm256_testc_si256 (__m256i s1, __m256i s2);
int _mm256_testnzc_si256 (__m256i s1, __m256i s2);
int _mm_testz_si128 (__m128i s1, __m128i s2);
int _mm_testc_si128 (__m128i s1, __m128i s2);
int _mm_testnzc_si128 (__m128i s1, __m128i s2);
Flags Affected
The 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
4-488 Vol. 2B
If VEX.vvvv ≠ 1111B.
PTEST- Logical Compare
INSTRUCTION SET REFERENCE, M-U
PTWRITE - Write Data to a Processor Trace Packet
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
F3 REX.W 0F AE /4
PTWRITE r64/m64
RM
V/N.E
Reads the data from r64/m64 to encod into a
PTW packet if dependencies are met (see
details below).
F3 0F AE /4
PTWRITE r32/m32
RM
V/V
Reads the data from r32/m32 to encode into a
PTW packet if dependencies are met (see
details below).
CPUID
Feature
Flag
Description
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:rm (r)
NA
NA
NA
Description
This instruction reads data in the source operand and sends it to the Intel Processor Trace hardware to be encoded
in a PTW packet if TriggerEn, ContextEn, FilterEn, and PTWEn are all set to 1. For more details on these values, see
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, Section 36.2.3, “Power Event
Tracing”. The size of data is 64-bit if using REX.W in 64-bit mode, otherwise 32-bits of data are copied from the
source operand.
Note: The instruction will #UD if prefix 66H is used.
Operation
IF (IA32_RTIT_STATUS.TriggerEn & IA32_RTIT_STATUS.ContextEn & IA32_RTIT_STATUS.FilterEn & IA32_RTIT_CTL.PTWEn) = 1
PTW.PayloadBytes ← Encoded payload size;
PTW.IP ← IA32_RTIT_CTL.FUPonPTW
IF IA32_RTIT_CTL.FUPonPTW = 1
Insert FUP packet with IP of PTWRITE;
FI;
FI;
Flags Affected
None.
Other Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
If LOCK prefix is used.
If 66H prefix is used.
PTWRITE - Write Data to a Processor Trace Packet
Vol. 2B 4-489
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
If LOCK prefix is used.
If 66H prefix is used.
Virtual 8086 Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
If LOCK prefix is used.
If 66H prefix is used.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
If LOCK prefix is used.
If 66H prefix is used.
4-490 Vol. 2B
PTWRITE - Write Data to a Processor Trace Packet
INSTRUCTION SET REFERENCE, M-U
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 68 /r1
RM
V/V
MMX
Unpack and interleave high-order bytes from
mm and mm/m64 into mm.
RM
V/V
SSE2
Unpack and interleave high-order bytes from
xmm1 and xmm2/m128 into xmm1.
RM
V/V
MMX
Unpack and interleave high-order words from
mm and mm/m64 into mm.
RM
V/V
SSE2
Unpack and interleave high-order words from
xmm1 and xmm2/m128 into xmm1.
RM
V/V
MMX
Unpack and interleave high-order
doublewords from mm and mm/m64 into mm.
RM
V/V
SSE2
Unpack and interleave high-order
doublewords from xmm1 and xmm2/m128
into xmm1.
RM
V/V
SSE2
Unpack and interleave high-order quadwords
from xmm1 and xmm2/m128 into xmm1.
RVM V/V
AVX
Interleave high-order bytes from xmm2 and
xmm3/m128 into xmm1.
RVM V/V
AVX
Interleave high-order words from xmm2 and
xmm3/m128 into xmm1.
RVM V/V
AVX
Interleave high-order doublewords from
xmm2 and xmm3/m128 into xmm1.
VEX.NDS.128.66.0F.WIG 6D/r
VPUNPCKHQDQ xmm1, xmm2, xmm3/m128
RVM V/V
AVX
Interleave high-order quadword from xmm2
and xmm3/m128 into xmm1 register.
VEX.NDS.256.66.0F.WIG 68 /r
VPUNPCKHBW ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Interleave high-order bytes from ymm2 and
ymm3/m256 into ymm1 register.
VEX.NDS.256.66.0F.WIG 69 /r
VPUNPCKHWD ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Interleave high-order words from ymm2 and
ymm3/m256 into ymm1 register.
VEX.NDS.256.66.0F.WIG 6A /r
VPUNPCKHDQ ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Interleave high-order doublewords from
ymm2 and ymm3/m256 into ymm1 register.
VEX.NDS.256.66.0F.WIG 6D /r
VPUNPCKHQDQ ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Interleave high-order quadword from ymm2
and ymm3/m256 into ymm1 register.
EVEX.NDS.128.66.0F.WIG 68 /r
VPUNPCKHBW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Interleave high-order bytes from xmm2 and
AVX512BW xmm3/m128 into xmm1 register using k1
write mask.
EVEX.NDS.128.66.0F.WIG 69 /r
VPUNPCKHWD xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Interleave high-order words from xmm2 and
AVX512BW xmm3/m128 into xmm1 register using k1
write mask.
EVEX.NDS.128.66.0F.W0 6A /r
VPUNPCKHDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
Interleave high-order doublewords from
xmm2 and xmm3/m128/m32bcst into xmm1
register using k1 write mask.
EVEX.NDS.128.66.0F.W1 6D /r
VPUNPCKHQDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
Interleave high-order quadword from xmm2
and xmm3/m128/m64bcst into xmm1
register using k1 write mask.
PUNPCKHBW mm, mm/m64
66 0F 68 /r
PUNPCKHBW xmm1, xmm2/m128
0F 69 /r1
PUNPCKHWD mm, mm/m64
66 0F 69 /r
PUNPCKHWD xmm1, xmm2/m128
0F 6A /r1
PUNPCKHDQ mm, mm/m64
66 0F 6A /r
PUNPCKHDQ xmm1, xmm2/m128
66 0F 6D /r
PUNPCKHQDQ xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 68/r
VPUNPCKHBW xmm1,xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 69/r
VPUNPCKHWD xmm1,xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 6A/r
VPUNPCKHDQ xmm1, xmm2, xmm3/m128
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
Vol. 2B 4-491
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.256.66.0F.WIG 68 /r
VPUNPCKHBW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Interleave high-order bytes from ymm2 and
AVX512BW ymm3/m256 into ymm1 register using k1
write mask.
EVEX.NDS.256.66.0F.WIG 69 /r
VPUNPCKHWD ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Interleave high-order words from ymm2 and
AVX512BW ymm3/m256 into ymm1 register using k1
write mask.
EVEX.NDS.256.66.0F.W0 6A /r
VPUNPCKHDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
Interleave high-order doublewords from
ymm2 and ymm3/m256/m32bcst into ymm1
register using k1 write mask.
EVEX.NDS.256.66.0F.W1 6D /r
VPUNPCKHQDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
Interleave high-order quadword from ymm2
and ymm3/m256/m64bcst into ymm1
register using k1 write mask.
EVEX.NDS.512.66.0F.WIG 68/r
VPUNPCKHBW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Interleave high-order bytes from zmm2 and
zmm3/m512 into zmm1 register.
EVEX.NDS.512.66.0F.WIG 69/r
VPUNPCKHWD zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Interleave high-order words from zmm2 and
zmm3/m512 into zmm1 register.
EVEX.NDS.512.66.0F.W0 6A /r
VPUNPCKHDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
Interleave high-order doublewords from
zmm2 and zmm3/m512/m32bcst into zmm1
register using k1 write mask.
EVEX.NDS.512.66.0F.W1 6D /r
VPUNPCKHQDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Interleave high-order quadword from zmm2
and zmm3/m512/m64bcst into zmm1 register
using k1 write mask.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Unpacks and interleaves the high-order data elements (bytes, words, doublewords, or quadwords) of the destination operand (first operand) and source operand (second operand) into the destination operand. Figure 4-20 shows
the unpack operation for bytes in 64-bit operands. The low-order data elements are ignored.
4-492 Vol. 2B
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
INSTRUCTION SET REFERENCE, M-U
SRC Y7 Y6
Y5 Y4
Y3 Y2
Y1 Y0
DEST Y7 X7 Y6
X6 Y5
X5 Y4
X7 X6
X5 X4
X3 X2
X1 X0 DEST
X4
Figure 4-20. PUNPCKHBW Instruction Operation Using 64-bit Operands
31
255
SRC Y7 Y6
Y5 Y4
Y3 Y2
0
Y1 Y0
255
31 0
X7 X6
X5 X4
X3 X2
255
DEST Y7 X7 Y6
X1 X0
0
X6 Y3
X3 Y2
X2
Figure 4-21. 256-bit VPUNPCKHDQ Instruction Operation
When the source data comes from a 64-bit memory operand, the full 64-bit operand is accessed from memory, but
the instruction uses only the high-order 32 bits. When the source data comes from a 128-bit memory operand, an
implementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal
segment checking will still be enforced.
The (V)PUNPCKHBW instruction interleaves the high-order bytes of the source and destination operands, the
(V)PUNPCKHWD instruction interleaves the high-order words of the source and destination operands, the
(V)PUNPCKHDQ instruction interleaves the high-order doubleword (or doublewords) of the source and destination
operands, and the (V)PUNPCKHQDQ instruction interleaves the high-order quadwords of the source and destination operands.
These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and
quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand
contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data
elements from the original value in the destination operand. For example, with the (V)PUNPCKHBW instruction the
high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKHWD
instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers.
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
Vol. 2B 4-493
INSTRUCTION SET REFERENCE, M-U
EVEX encoded VPUNPCKHDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source
operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with
writemask k1.
EVEX encoded VPUNPCKHWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination
is conditionally updated with writemask k1.
Operation
PUNPCKHBW instruction with 64-bit operands:
DEST[7:0] ← DEST[39:32];
DEST[15:8] ← SRC[39:32];
DEST[23:16] ← DEST[47:40];
DEST[31:24] ← SRC[47:40];
DEST[39:32] ← DEST[55:48];
DEST[47:40] ← SRC[55:48];
DEST[55:48] ← DEST[63:56];
DEST[63:56] ← SRC[63:56];
PUNPCKHW instruction with 64-bit operands:
DEST[15:0] ← DEST[47:32];
DEST[31:16] ← SRC[47:32];
DEST[47:32] ← DEST[63:48];
DEST[63:48] ← SRC[63:48];
PUNPCKHDQ instruction with 64-bit operands:
DEST[31:0] ← DEST[63:32];
DEST[63:32] ← SRC[63:32];
INTERLEAVE_HIGH_BYTES_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_HIGH_BYTES_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] INTERLEAVE_HIGH_BYTES_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_HIGH_BYTES_256b (SRC1, SRC2)
DEST[7:0] SRC1[71:64]
DEST[15:8] SRC2[71:64]
DEST[23:16] SRC1[79:72]
DEST[31:24] SRC2[79:72]
DEST[39:32] SRC1[87:80]
DEST[47:40] SRC2[87:80]
DEST[55:48] SRC1[95:88]
DEST[63:56] SRC2[95:88]
DEST[71:64] SRC1[103:96]
DEST[79:72] SRC2[103:96]
DEST[87:80] SRC1[111:104]
DEST[95:88] SRC2[111:104]
DEST[103:96] SRC1[119:112]
DEST[111:104] SRC2[119:112]
DEST[119:112] SRC1[127:120]
DEST[127:120] SRC2[127:120]
DEST[135:128] SRC1[199:192]
DEST[143:136] SRC2[199:192]
DEST[151:144] SRC1[207:200]
DEST[159:152] SRC2[207:200]
4-494 Vol. 2B
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
INSTRUCTION SET REFERENCE, M-U
DEST[167:160] SRC1[215:208]
DEST[175:168] SRC2[215:208]
DEST[183:176] SRC1[223:216]
DEST[191:184] SRC2[223:216]
DEST[199:192] SRC1[231:224]
DEST[207:200] SRC2[231:224]
DEST[215:208] SRC1[239:232]
DEST[223:216] SRC2[239:232]
DEST[231:224] SRC1[247:240]
DEST[239:232] SRC2[247:240]
DEST[247:240] SRC1[255:248]
DEST[255:248] SRC2[255:248]
INTERLEAVE_HIGH_BYTES (SRC1, SRC2)
DEST[7:0] SRC1[71:64]
DEST[15:8] SRC2[71:64]
DEST[23:16] SRC1[79:72]
DEST[31:24] SRC2[79:72]
DEST[39:32] SRC1[87:80]
DEST[47:40] SRC2[87:80]
DEST[55:48] SRC1[95:88]
DEST[63:56] SRC2[95:88]
DEST[71:64] SRC1[103:96]
DEST[79:72] SRC2[103:96]
DEST[87:80] SRC1[111:104]
DEST[95:88] SRC2[111:104]
DEST[103:96] SRC1[119:112]
DEST[111:104] SRC2[119:112]
DEST[119:112] SRC1[127:120]
DEST[127:120] SRC2[127:120]
INTERLEAVE_HIGH_WORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_HIGH_WORDS_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] INTERLEAVE_HIGH_WORDS_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)
DEST[15:0] SRC1[79:64]
DEST[31:16] SRC2[79:64]
DEST[47:32] SRC1[95:80]
DEST[63:48] SRC2[95:80]
DEST[79:64] SRC1[111:96]
DEST[95:80] SRC2[111:96]
DEST[111:96] SRC1[127:112]
DEST[127:112] SRC2[127:112]
DEST[143:128] SRC1[207:192]
DEST[159:144] SRC2[207:192]
DEST[175:160] SRC1[223:208]
DEST[191:176] SRC2[223:208]
DEST[207:192] SRC1[239:224]
DEST[223:208] SRC2[239:224]
DEST[239:224] SRC1[255:240]
DEST[255:240] SRC2[255:240]
INTERLEAVE_HIGH_WORDS (SRC1, SRC2)
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
Vol. 2B 4-495
INSTRUCTION SET REFERENCE, M-U
DEST[15:0] SRC1[79:64]
DEST[31:16] SRC2[79:64]
DEST[47:32] SRC1[95:80]
DEST[63:48] SRC2[95:80]
DEST[79:64] SRC1[111:96]
DEST[95:80] SRC2[111:96]
DEST[111:96] SRC1[127:112]
DEST[127:112] SRC2[127:112]
INTERLEAVE_HIGH_DWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_HIGH_DWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] INTERLEAVE_HIGH_DWORDS_256b(SRC1[511:256], SRC2[511:256])
INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)
DEST[31:0] SRC1[95:64]
DEST[63:32] SRC2[95:64]
DEST[95:64] SRC1[127:96]
DEST[127:96] SRC2[127:96]
DEST[159:128] SRC1[223:192]
DEST[191:160] SRC2[223:192]
DEST[223:192] SRC1[255:224]
DEST[255:224] SRC2[255:224]
INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)
DEST[31:0] SRC1[95:64]
DEST[63:32] SRC2[95:64]
DEST[95:64] SRC1[127:96]
DEST[127:96] SRC2[127:96]
INTERLEAVE_HIGH_QWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_HIGH_QWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] INTERLEAVE_HIGH_QWORDS_256b(SRC1[511:256], SRC2[511:256])
INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)
DEST[63:0] SRC1[127:64]
DEST[127:64] SRC2[127:64]
DEST[191:128] SRC1[255:192]
DEST[255:192] SRC2[255:192]
INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)
DEST[63:0] SRC1[127:64]
DEST[127:64] SRC2[127:64]
PUNPCKHBW (128-bit Legacy SSE Version)
DEST[127:0] INTERLEAVE_HIGH_BYTES(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKHBW (VEX.128 encoded version)
DEST[127:0] INTERLEAVE_HIGH_BYTES(SRC1, SRC2)
DEST[511:127] 0
VPUNPCKHBW (VEX.256 encoded version)
DEST[255:0] INTERLEAVE_HIGH_BYTES_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
4-496 Vol. 2B
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
INSTRUCTION SET REFERENCE, M-U
VPUNPCKHBW (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TMP_DEST[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PUNPCKHWD (128-bit Legacy SSE Version)
DEST[127:0] INTERLEAVE_HIGH_WORDS(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKHWD (VEX.128 encoded version)
DEST[127:0] INTERLEAVE_HIGH_WORDS(SRC1, SRC2)
DEST[511:127] 0
VPUNPCKHWD (VEX.256 encoded version)
DEST[255:0] INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPUNPCKHWD (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
Vol. 2B 4-497
INSTRUCTION SET REFERENCE, M-U
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PUNPCKHDQ (128-bit Legacy SSE Version)
DEST[127:0] INTERLEAVE_HIGH_DWORDS(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKHDQ (VEX.128 encoded version)
DEST[127:0] INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)
DEST[511:127] 0
VPUNPCKHDQ (VEX.256 encoded version)
DEST[255:0] INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPUNPCKHDQ (EVEX.512 encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] SRC2[31:0]
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
4-498 Vol. 2B
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
INSTRUCTION SET REFERENCE, M-U
PUNPCKHQDQ (128-bit Legacy SSE Version)
DEST[127:0] INTERLEAVE_HIGH_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
VPUNPCKHQDQ (VEX.128 encoded version)
DEST[127:0] INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPUNPCKHQDQ (VEX.256 encoded version)
DEST[255:0] INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPUNPCKHQDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] SRC2[63:0]
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i]
FI;
ENDFOR;
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_HIGH_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPUNPCKHBW __m512i _mm512_unpackhi_epi8(__m512i a, __m512i b);
VPUNPCKHBW __m512i _mm512_mask_unpackhi_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPUNPCKHBW __m512i _mm512_maskz_unpackhi_epi8( __mmask64 k, __m512i a, __m512i b);
VPUNPCKHBW __m256i _mm256_mask_unpackhi_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPUNPCKHBW __m256i _mm256_maskz_unpackhi_epi8( __mmask32 k, __m256i a, __m256i b);
VPUNPCKHBW __m128i _mm_mask_unpackhi_epi8(v s, __mmask16 k, __m128i a, __m128i b);
VPUNPCKHBW __m128i _mm_maskz_unpackhi_epi8( __mmask16 k, __m128i a, __m128i b);
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
Vol. 2B 4-499
INSTRUCTION SET REFERENCE, M-U
VPUNPCKHWD __m512i _mm512_unpackhi_epi16(__m512i a, __m512i b);
VPUNPCKHWD __m512i _mm512_mask_unpackhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPUNPCKHWD __m512i _mm512_maskz_unpackhi_epi16( __mmask32 k, __m512i a, __m512i b);
VPUNPCKHWD __m256i _mm256_mask_unpackhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPUNPCKHWD __m256i _mm256_maskz_unpackhi_epi16( __mmask16 k, __m256i a, __m256i b);
VPUNPCKHWD __m128i _mm_mask_unpackhi_epi16(v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKHWD __m128i _mm_maskz_unpackhi_epi16( __mmask8 k, __m128i a, __m128i b);
VPUNPCKHDQ __m512i _mm512_unpackhi_epi32(__m512i a, __m512i b);
VPUNPCKHDQ __m512i _mm512_mask_unpackhi_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPUNPCKHDQ __m512i _mm512_maskz_unpackhi_epi32( __mmask16 k, __m512i a, __m512i b);
VPUNPCKHDQ __m256i _mm256_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m256i _mm256_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m128i _mm_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m128i _mm_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m512i _mm512_unpackhi_epi64(__m512i a, __m512i b);
VPUNPCKHQDQ __m512i _mm512_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m512i _mm512_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m256i _mm256_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m256i _mm256_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m128i _mm_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m128i _mm_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);
PUNPCKHBW:__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)
(V)PUNPCKHBW:__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)
VPUNPCKHBW:__m256i _mm256_unpackhi_epi8(__m256i m1, __m256i m2)
PUNPCKHWD:__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)
(V)PUNPCKHWD:__m128i _mm_unpackhi_epi16(__m128i m1,__m128i m2)
VPUNPCKHWD:__m256i _mm256_unpackhi_epi16(__m256i m1,__m256i m2)
PUNPCKHDQ:__m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)
(V)PUNPCKHDQ:__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)
VPUNPCKHDQ:__m256i _mm256_unpackhi_epi32(__m256i m1, __m256i m2)
(V)PUNPCKHQDQ:__m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b)
VPUNPCKHQDQ:__m256i _mm256_unpackhi_epi64 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPUNPCKHQDQ/QDQ, see Exceptions Type E4NF.
EVEX-encoded VPUNPCKHBW/WD, see Exceptions Type E4NF.nb.
4-500 Vol. 2B
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data
INSTRUCTION SET REFERENCE, M-U
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 60 /r1
RM
V/V
MMX
Interleave low-order bytes from mm and
mm/m32 into mm.
RM
V/V
SSE2
Interleave low-order bytes from xmm1 and
xmm2/m128 into xmm1.
RM
V/V
MMX
Interleave low-order words from mm and
mm/m32 into mm.
RM
V/V
SSE2
Interleave low-order words from xmm1 and
xmm2/m128 into xmm1.
RM
V/V
MMX
Interleave low-order doublewords from mm
and mm/m32 into mm.
RM
V/V
SSE2
Interleave low-order doublewords from xmm1
and xmm2/m128 into xmm1.
RM
V/V
SSE2
Interleave low-order quadword from xmm1
and xmm2/m128 into xmm1 register.
RVM V/V
AVX
Interleave low-order bytes from xmm2 and
xmm3/m128 into xmm1.
RVM V/V
AVX
Interleave low-order words from xmm2 and
xmm3/m128 into xmm1.
RVM V/V
AVX
Interleave low-order doublewords from xmm2
and xmm3/m128 into xmm1.
RVM V/V
AVX
Interleave low-order quadword from xmm2
and xmm3/m128 into xmm1 register.
RVM V/V
AVX2
Interleave low-order bytes from ymm2 and
ymm3/m256 into ymm1 register.
RVM V/V
AVX2
Interleave low-order words from ymm2 and
ymm3/m256 into ymm1 register.
RVM V/V
AVX2
Interleave low-order doublewords from ymm2
and ymm3/m256 into ymm1 register.
RVM V/V
AVX2
Interleave low-order quadword from ymm2
and ymm3/m256 into ymm1 register.
EVEX.NDS.128.66.0F.WIG 60 /r
VPUNPCKLBW xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Interleave low-order bytes from xmm2 and
AVX512BW xmm3/m128 into xmm1 register subject to
write mask k1.
EVEX.NDS.128.66.0F.WIG 61 /r
VPUNPCKLWD xmm1 {k1}{z}, xmm2, xmm3/m128
FVM V/V
AVX512VL Interleave low-order words from xmm2 and
AVX512BW xmm3/m128 into xmm1 register subject to
write mask k1.
EVEX.NDS.128.66.0F.W0 62 /r
VPUNPCKLDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL Interleave low-order doublewords from xmm2
AVX512F
and xmm3/m128/m32bcst into xmm1
register subject to write mask k1.
EVEX.NDS.128.66.0F.W1 6C /r
VPUNPCKLQDQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL Interleave low-order quadword from zmm2
AVX512F
and zmm3/m512/m64bcst into zmm1
register subject to write mask k1.
PUNPCKLBW mm, mm/m32
66 0F 60 /r
PUNPCKLBW xmm1, xmm2/m128
0F 61 /r1
PUNPCKLWD mm, mm/m32
66 0F 61 /r
PUNPCKLWD xmm1, xmm2/m128
0F 62 /r1
PUNPCKLDQ mm, mm/m32
66 0F 62 /r
PUNPCKLDQ xmm1, xmm2/m128
66 0F 6C /r
PUNPCKLQDQ xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 60/r
VPUNPCKLBW xmm1,xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 61/r
VPUNPCKLWD xmm1,xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 62/r
VPUNPCKLDQ xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F.WIG 6C/r
VPUNPCKLQDQ xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 60 /r
VPUNPCKLBW ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG 61 /r
VPUNPCKLWD ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG 62 /r
VPUNPCKLDQ ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F.WIG 6C /r
VPUNPCKLQDQ ymm1, ymm2, ymm3/m256
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
Vol. 2B 4-501
INSTRUCTION SET REFERENCE, M-U
EVEX.NDS.256.66.0F.WIG 60 /r
VPUNPCKLBW ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Interleave low-order bytes from ymm2 and
AVX512BW ymm3/m256 into ymm1 register subject to
write mask k1.
EVEX.NDS.256.66.0F.WIG 61 /r
VPUNPCKLWD ymm1 {k1}{z}, ymm2, ymm3/m256
FVM V/V
AVX512VL Interleave low-order words from ymm2 and
AVX512BW ymm3/m256 into ymm1 register subject to
write mask k1.
EVEX.NDS.256.66.0F.W0 62 /r
VPUNPCKLDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL Interleave low-order doublewords from ymm2
AVX512F
and ymm3/m256/m32bcst into ymm1
register subject to write mask k1.
EVEX.NDS.256.66.0F.W1 6C /r
VPUNPCKLQDQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL Interleave low-order quadword from ymm2
AVX512F
and ymm3/m256/m64bcst into ymm1
register subject to write mask k1.
EVEX.NDS.512.66.0F.WIG 60/r
VPUNPCKLBW zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Interleave low-order bytes from zmm2 and
zmm3/m512 into zmm1 register subject to
write mask k1.
EVEX.NDS.512.66.0F.WIG 61/r
VPUNPCKLWD zmm1 {k1}{z}, zmm2, zmm3/m512
FVM V/V
AVX512BW Interleave low-order words from zmm2 and
zmm3/m512 into zmm1 register subject to
write mask k1.
EVEX.NDS.512.66.0F.W0 62 /r
VPUNPCKLDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
Interleave low-order doublewords from zmm2
and zmm3/m512/m32bcst into zmm1
register subject to write mask k1.
EVEX.NDS.512.66.0F.W1 6C /r
VPUNPCKLQDQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Interleave low-order quadword from zmm2
and zmm3/m512/m64bcst into zmm1
register subject to write mask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords) of the destination operand (first operand) and source operand (second operand) into the destination operand. (Figure 4-22
shows the unpack operation for bytes in 64-bit operands.). The high-order data elements are ignored.
4-502 Vol. 2B
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
INSTRUCTION SET REFERENCE, M-U
SRC Y7 Y6
Y5 Y4
Y3 Y2
X7 X6
Y1 Y0
DEST Y3 X3 Y2
X5 X4
X2 Y1
X3 X2
X1 Y0
X1 X0 DEST
X0
Figure 4-22. PUNPCKLBW Instruction Operation Using 64-bit Operands
31
255
SRC Y7 Y6
Y5 Y4
Y3 Y2
0
Y1 Y0
255
31 0
X7 X6
X5 X4
X3 X2
255
DEST Y5 X5 Y4
X1 X0
0
X4 Y1
X1 Y0
X0
Figure 4-23. 256-bit VPUNPCKLDQ Instruction Operation
When the source data comes from a 128-bit memory operand, an implementation may fetch only the appropriate
64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.
The (V)PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the
(V)PUNPCKLWD instruction interleaves the low-order words of the source and destination operands, the
(V)PUNPCKLDQ instruction interleaves the low-order doubleword (or doublewords) of the source and destination
operands, and the (V)PUNPCKLQDQ instruction interleaves the low-order quadwords of the source and destination
operands.
These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and
quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand
contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data
elements from the original value in the destination operand. For example, with the (V)PUNPCKLBW instruction the
high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKLWD
instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 32-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
Vol. 2B 4-503
INSTRUCTION SET REFERENCE, M-U
EVEX encoded VPUNPCKLDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source
operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with
writemask k1.
EVEX encoded VPUNPCKLWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination
is conditionally updated with writemask k1.
Operation
PUNPCKLBW instruction with 64-bit operands:
DEST[63:56] ← SRC[31:24];
DEST[55:48] ← DEST[31:24];
DEST[47:40] ← SRC[23:16];
DEST[39:32] ← DEST[23:16];
DEST[31:24] ← SRC[15:8];
DEST[23:16] ← DEST[15:8];
DEST[15:8] ← SRC[7:0];
DEST[7:0] ← DEST[7:0];
PUNPCKLWD instruction with 64-bit operands:
DEST[63:48] ← SRC[31:16];
DEST[47:32] ← DEST[31:16];
DEST[31:16] ← SRC[15:0];
DEST[15:0] ← DEST[15:0];
PUNPCKLDQ instruction with 64-bit operands:
DEST[63:32] ← SRC[31:0];
DEST[31:0] ← DEST[31:0];
INTERLEAVE_BYTES_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_BYTES_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] INTERLEAVE_BYTES_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_BYTES_256b (SRC1, SRC2)
DEST[7:0] SRC1[7:0]
DEST[15:8] SRC2[7:0]
DEST[23:16] SRC1[15:8]
DEST[31:24] SRC2[15:8]
DEST[39:32] SRC1[23:16]
DEST[47:40] SRC2[23:16]
DEST[55:48] SRC1[31:24]
DEST[63:56] SRC2[31:24]
DEST[71:64] SRC1[39:32]
DEST[79:72] SRC2[39:32]
DEST[87:80] SRC1[47:40]
DEST[95:88] SRC2[47:40]
DEST[103:96] SRC1[55:48]
DEST[111:104] SRC2[55:48]
DEST[119:112] SRC1[63:56]
DEST[127:120] SRC2[63:56]
DEST[135:128] SRC1[135:128]
DEST[143:136] SRC2[135:128]
DEST[151:144] SRC1[143:136]
DEST[159:152] SRC2[143:136]
DEST[167:160] SRC1[151:144]
4-504 Vol. 2B
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
INSTRUCTION SET REFERENCE, M-U
DEST[175:168] SRC2[151:144]
DEST[183:176] SRC1[159:152]
DEST[191:184] SRC2[159:152]
DEST[199:192] SRC1[167:160]
DEST[207:200] SRC2[167:160]
DEST[215:208] SRC1[175:168]
DEST[223:216] SRC2[175:168]
DEST[231:224] SRC1[183:176]
DEST[239:232] SRC2[183:176]
DEST[247:240] SRC1[191:184]
DEST[255:248] SRC2[191:184]
INTERLEAVE_BYTES (SRC1, SRC2)
DEST[7:0] SRC1[7:0]
DEST[15:8] SRC2[7:0]
DEST[23:16] SRC2[15:8]
DEST[31:24] SRC2[15:8]
DEST[39:32] SRC1[23:16]
DEST[47:40] SRC2[23:16]
DEST[55:48] SRC1[31:24]
DEST[63:56] SRC2[31:24]
DEST[71:64] SRC1[39:32]
DEST[79:72] SRC2[39:32]
DEST[87:80] SRC1[47:40]
DEST[95:88] SRC2[47:40]
DEST[103:96] SRC1[55:48]
DEST[111:104] SRC2[55:48]
DEST[119:112] SRC1[63:56]
DEST[127:120] SRC2[63:56]
INTERLEAVE_WORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_WORDS_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] INTERLEAVE_WORDS_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[15:0] SRC1[15:0]
DEST[31:16] SRC2[15:0]
DEST[47:32] SRC1[31:16]
DEST[63:48] SRC2[31:16]
DEST[79:64] SRC1[47:32]
DEST[95:80] SRC2[47:32]
DEST[111:96] SRC1[63:48]
DEST[127:112] SRC2[63:48]
DEST[143:128] SRC1[143:128]
DEST[159:144] SRC2[143:128]
DEST[175:160] SRC1[159:144]
DEST[191:176] SRC2[159:144]
DEST[207:192] SRC1[175:160]
DEST[223:208] SRC2[175:160]
DEST[239:224] SRC1[191:176]
DEST[255:240] SRC2[191:176]
INTERLEAVE_WORDS (SRC1, SRC2)
DEST[15:0] SRC1[15:0]
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
Vol. 2B 4-505
INSTRUCTION SET REFERENCE, M-U
DEST[31:16] SRC2[15:0]
DEST[47:32] SRC1[31:16]
DEST[63:48] SRC2[31:16]
DEST[79:64] SRC1[47:32]
DEST[95:80] SRC2[47:32]
DEST[111:96] SRC1[63:48]
DEST[127:112] SRC2[63:48]
INTERLEAVE_DWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_DWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] INTERLEAVE_DWORDS_256b(SRC1[511:256], SRC2[511:256])
INTERLEAVE_DWORDS_256b(SRC1, SRC2)
DEST[31:0] SRC1[31:0]
DEST[63:32] SRC2[31:0]
DEST[95:64] SRC1[63:32]
DEST[127:96] SRC2[63:32]
DEST[159:128] SRC1[159:128]
DEST[191:160] SRC2[159:128]
DEST[223:192] SRC1[191:160]
DEST[255:224] SRC2[191:160]
INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[31:0] SRC1[31:0]
DEST[63:32] SRC2[31:0]
DEST[95:64] SRC1[63:32]
DEST[127:96] SRC2[63:32]
INTERLEAVE_QWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] INTERLEAVE_QWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] INTERLEAVE_QWORDS_256b(SRC1[511:256], SRC2[511:256])
INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
DEST[191:128] SRC1[191:128]
DEST[255:192] SRC2[191:128]
INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
PUNPCKLBW
DEST[127:0] INTERLEAVE_BYTES(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKLBW (VEX.128 encoded instruction)
DEST[127:0] INTERLEAVE_BYTES(SRC1, SRC2)
DEST[511:127] 0
VPUNPCKLBW (VEX.256 encoded instruction)
DEST[255:0] INTERLEAVE_BYTES_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
4-506 Vol. 2B
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
INSTRUCTION SET REFERENCE, M-U
VPUNPCKLBW (EVEX.512 encoded instruction)
(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TMP_DEST[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
DEST[511:0] INTERLEAVE_BYTES_512b(SRC1, SRC2)
PUNPCKLWD
DEST[127:0] INTERLEAVE_WORDS(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKLWD (VEX.128 encoded instruction)
DEST[127:0] INTERLEAVE_WORDS(SRC1, SRC2)
DEST[511:127] 0
VPUNPCKLWD (VEX.256 encoded instruction)
DEST[255:0] INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPUNPCKLWD (EVEX.512 encoded instruction)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
Vol. 2B 4-507
INSTRUCTION SET REFERENCE, M-U
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
DEST[511:0] INTERLEAVE_WORDS_512b(SRC1, SRC2)
PUNPCKLDQ
DEST[127:0] INTERLEAVE_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
VPUNPCKLDQ (VEX.128 encoded instruction)
DEST[127:0] INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPUNPCKLDQ (VEX.256 encoded instruction)
DEST[255:0] INTERLEAVE_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPUNPCKLDQ (EVEX encoded instructions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] SRC2[31:0]
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
4-508 Vol. 2B
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
INSTRUCTION SET REFERENCE, M-U
ENDFOR
DEST511:0] INTERLEAVE_DWORDS_512b(SRC1, SRC2)
DEST[MAX_VL-1:VL] 0
PUNPCKLQDQ
DEST[127:0] INTERLEAVE_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)
VPUNPCKLQDQ (VEX.128 encoded instruction)
DEST[127:0] INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] 0
VPUNPCKLQDQ (VEX.256 encoded instruction)
DEST[255:0] INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] 0
VPUNPCKLQDQ (EVEX encoded instructions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] SRC2[63:0]
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i]
FI;
ENDFOR;
IF VL = 128
TMP_DEST[VL-1:0] INTERLEAVE_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
TMP_DEST[VL-1:0] INTERLEAVE_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
TMP_DEST[VL-1:0] INTERLEAVE_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPUNPCKLBW __m512i _mm512_unpacklo_epi8(__m512i a, __m512i b);
VPUNPCKLBW __m512i _mm512_mask_unpacklo_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPUNPCKLBW __m512i _mm512_maskz_unpacklo_epi8( __mmask64 k, __m512i a, __m512i b);
VPUNPCKLBW __m256i _mm256_mask_unpacklo_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
Vol. 2B 4-509
INSTRUCTION SET REFERENCE, M-U
VPUNPCKLBW __m256i _mm256_maskz_unpacklo_epi8( __mmask32 k, __m256i a, __m256i b);
VPUNPCKLBW __m128i _mm_mask_unpacklo_epi8(v s, __mmask16 k, __m128i a, __m128i b);
VPUNPCKLBW __m128i _mm_maskz_unpacklo_epi8( __mmask16 k, __m128i a, __m128i b);
VPUNPCKLWD __m512i _mm512_unpacklo_epi16(__m512i a, __m512i b);
VPUNPCKLWD __m512i _mm512_mask_unpacklo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPUNPCKLWD __m512i _mm512_maskz_unpacklo_epi16( __mmask32 k, __m512i a, __m512i b);
VPUNPCKLWD __m256i _mm256_mask_unpacklo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPUNPCKLWD __m256i _mm256_maskz_unpacklo_epi16( __mmask16 k, __m256i a, __m256i b);
VPUNPCKLWD __m128i _mm_mask_unpacklo_epi16(v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLWD __m128i _mm_maskz_unpacklo_epi16( __mmask8 k, __m128i a, __m128i b);
VPUNPCKLDQ __m512i _mm512_unpacklo_epi32(__m512i a, __m512i b);
VPUNPCKLDQ __m512i _mm512_mask_unpacklo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPUNPCKLDQ __m512i _mm512_maskz_unpacklo_epi32( __mmask16 k, __m512i a, __m512i b);
VPUNPCKLDQ __m256i _mm256_mask_unpacklo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPUNPCKLDQ __m256i _mm256_maskz_unpacklo_epi32( __mmask8 k, __m256i a, __m256i b);
VPUNPCKLDQ __m128i _mm_mask_unpacklo_epi32(v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLDQ __m128i _mm_maskz_unpacklo_epi32( __mmask8 k, __m128i a, __m128i b);
VPUNPCKLQDQ __m512i _mm512_unpacklo_epi64(__m512i a, __m512i b);
VPUNPCKLQDQ __m512i _mm512_mask_unpacklo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKLQDQ __m512i _mm512_maskz_unpacklo_epi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKLQDQ __m256i _mm256_mask_unpacklo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPUNPCKLQDQ __m256i _mm256_maskz_unpacklo_epi64( __mmask8 k, __m256i a, __m256i b);
VPUNPCKLQDQ __m128i _mm_mask_unpacklo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLQDQ __m128i _mm_maskz_unpacklo_epi64( __mmask8 k, __m128i a, __m128i b);
PUNPCKLBW:__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)
(V)PUNPCKLBW:__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)
VPUNPCKLBW:__m256i _mm256_unpacklo_epi8 (__m256i m1, __m256i m2)
PUNPCKLWD:__m64 _mm_unpacklo_pi16 (__m64 m1, __m64 m2)
(V)PUNPCKLWD:__m128i _mm_unpacklo_epi16 (__m128i m1, __m128i m2)
VPUNPCKLWD:__m256i _mm256_unpacklo_epi16 (__m256i m1, __m256i m2)
PUNPCKLDQ:__m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2)
(V)PUNPCKLDQ:__m128i _mm_unpacklo_epi32 (__m128i m1, __m128i m2)
VPUNPCKLDQ:__m256i _mm256_unpacklo_epi32 (__m256i m1, __m256i m2)
(V)PUNPCKLQDQ:__m128i _mm_unpacklo_epi64 (__m128i m1, __m128i m2)
VPUNPCKLQDQ:__m256i _mm256_unpacklo_epi64 (__m256i m1, __m256i m2)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPUNPCKLDQ/QDQ, see Exceptions Type E4NF.
EVEX-encoded VPUNPCKLBW/WD, see Exceptions Type E4NF.nb.
4-510 Vol. 2B
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data
INSTRUCTION SET REFERENCE, M-U
PUSH—Push Word, Doubleword or Quadword Onto the Stack
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
FF /6
PUSH r/m16
M
Valid
Valid
Push r/m16.
FF /6
PUSH r/m32
M
N.E.
Valid
Push r/m32.
FF /6
PUSH r/m64
M
Valid
N.E.
Push r/m64.
50+rw
PUSH r16
O
Valid
Valid
Push r16.
50+rd
PUSH r32
O
N.E.
Valid
Push r32.
50+rd
PUSH r64
O
Valid
N.E.
Push r64.
6A ib
PUSH imm8
I
Valid
Valid
Push imm8.
68 iw
PUSH imm16
I
Valid
Valid
Push imm16.
68 id
PUSH imm32
I
Valid
Valid
Push imm32.
0E
PUSH CS
NP
Invalid
Valid
Push CS.
16
PUSH SS
NP
Invalid
Valid
Push SS.
1E
PUSH DS
NP
Invalid
Valid
Push DS.
06
PUSH ES
NP
Invalid
Valid
Push ES.
0F A0
PUSH FS
NP
Valid
Valid
Push FS.
0F A8
PUSH GS
NP
Valid
Valid
Push GS.
NOTES:
* See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
O
opcode + rd (r)
NA
NA
NA
I
imm8/16/32
NA
NA
NA
NP
NA
NA
NA
NA
Description
Decrements the stack pointer and then stores the source operand on the top of the stack. Address and operand
sizes are determined and used as follows:
•
Address size. The D flag in the current code-segment descriptor determines the default address size; it may be
overridden by an instruction prefix (67H).
The address size is used only when referencing a source operand in memory.
•
Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may
be overridden by instruction prefixes (66H or REX.W).
The operand size (16, 32, or 64 bits) determines the amount by which the stack pointer is decremented (2, 4
or 8).
If the source operand is an immediate of size less than the operand size, a sign-extended value is pushed on
the stack. If the source operand is a segment register (16 bits) and the operand size is 64-bits, a zeroextended value is pushed on the stack; if the operand size is 32-bits, either a zero-extended value is pushed
on the stack or the segment selector is written on the stack using a 16-bit move. For the last case, all recent
Core and Atom processors perform a 16-bit move, leaving the upper portion of the stack location unmodified.
•
Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the
size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.
PUSH—Push Word, Doubleword or Quadword Onto the Stack
Vol. 2B 4-511
INSTRUCTION SET REFERENCE, M-U
The stack-address size determines the width of the stack pointer when writing to the stack in memory and
when decrementing the stack pointer. (As stated above, the amount by which the stack pointer is
decremented is determined by the operand size.)
If the operand size is less than the stack-address size, the PUSH instruction may result in a misaligned stack
pointer (a stack pointer that is not aligned on a doubleword or quadword boundary).
The PUSH ESP instruction pushes the value of the ESP register as it existed before the instruction was executed. If
a PUSH instruction uses a memory operand in which the ESP register is used for computing the operand address,
the address of the operand is computed before the ESP register is decremented.
If the ESP or SP register is 1 when the PUSH instruction is executed in real-address mode, a stack-fault exception
(#SS) is generated (because the limit of the stack segment is violated). Its delivery encounters a second stackfault exception (for the same reason), causing generation of a double-fault exception (#DF). Delivery of the
double-fault exception encounters a third stack-fault exception, and the logical processor enters shutdown mode.
See the discussion of the double-fault exception in Chapter 6 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A.
IA-32 Architecture Compatibility
For IA-32 processors from the Intel 286 on, the PUSH ESP instruction pushes the value of the ESP register as it
existed before the instruction was executed. (This is also true for Intel 64 architecture, real-address and virtual8086 modes of IA-32 architecture.) For the Intel® 8086 processor, the PUSH SP instruction pushes the new value
of the SP register (that is the value after it has been decremented by 2).
Operation
(* See Description section for possible sign-extension or zero-extension of source operand and for *)
(* a case in which the size of the memory store may be smaller than the instruction’s operand size *)
IF StackAddrSize = 64
THEN
IF OperandSize = 64
THEN
RSP ← RSP – 8;
Memory[SS:RSP] ← SRC;
(* push quadword *)
ELSE IF OperandSize = 32
THEN
RSP ← RSP – 4;
Memory[SS:RSP] ← SRC;
(* push dword *)
ELSE (* OperandSize = 16 *)
RSP ← RSP – 2;
Memory[SS:RSP] ← SRC;
(* push word *)
FI;
ELSE IF StackAddrSize = 32
THEN
IF OperandSize = 64
THEN
ESP ← ESP – 8;
Memory[SS:ESP] ← SRC;
ELSE IF OperandSize = 32
THEN
ESP ← ESP – 4;
Memory[SS:ESP] ← SRC;
ELSE (* OperandSize = 16 *)
ESP ← ESP – 2;
Memory[SS:ESP] ← SRC;
FI;
ELSE (* StackAddrSize = 16 *)
4-512 Vol. 2B
(* push quadword *)
(* push dword *)
(* push word *)
PUSH—Push Word, Doubleword or Quadword Onto the Stack
INSTRUCTION SET REFERENCE, M-U
IF OperandSize = 32
THEN
SP ← SP – 4;
Memory[SS:SP] ← SRC;
ELSE (* OperandSize = 16 *)
SP ← SP – 2;
Memory[SS:SP] ← SRC;
FI;
(* push dword *)
(* push word *)
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
#SS
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand effective address is outside the SS segment limit.
If the new value of the SP or ESP register is outside the stack segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If the stack address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
If the PUSH is of CS, SS, DS, or ES.
PUSH—Push Word, Doubleword or Quadword Onto the Stack
Vol. 2B 4-513
INSTRUCTION SET REFERENCE, M-U
PUSHA/PUSHAD—Push All General-Purpose Registers
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
60
PUSHA
NP
Invalid
Valid
Push AX, CX, DX, BX, original SP, BP, SI, and DI.
60
PUSHAD
NP
Invalid
Valid
Push EAX, ECX, EDX, EBX, original ESP, EBP,
ESI, and EDI.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Pushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the
following order: EAX, ECX, EDX, EBX, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute
is 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). These instructions perform the reverse operation of the POPA/POPAD instructions. The value pushed for the ESP or SP register
is its value before prior to pushing the first register (see the “Operation” section below).
The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same opcode. The PUSHA instruction is intended for use when the operand-size attribute is 16 and the PUSHAD instruction for when the operandsize attribute is 32. Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when
PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting
of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the
mnemonic used.
In the real-address mode, if the ESP or SP register is 1, 3, or 5 when PUSHA/PUSHAD executes: an #SS exception
is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates a
#DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-bit Mode
THEN #UD
FI;
IF OperandSize = 32 (* PUSHAD instruction *)
THEN
Temp ← (ESP);
Push(EAX);
Push(ECX);
Push(EDX);
Push(EBX);
Push(Temp);
Push(EBP);
Push(ESI);
Push(EDI);
ELSE (* OperandSize = 16, PUSHA instruction *)
Temp ← (SP);
Push(AX);
Push(CX);
Push(DX);
4-514 Vol. 2B
PUSHA/PUSHAD—Push All General-Purpose Registers
INSTRUCTION SET REFERENCE, M-U
Push(BX);
Push(Temp);
Push(BP);
Push(SI);
Push(DI);
FI;
Flags Affected
None.
Protected Mode Exceptions
#SS(0)
If the starting or ending stack address is outside the stack segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If the ESP or SP register contains 7, 9, 11, 13, or 15.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the ESP or SP register contains 7, 9, 11, 13, or 15.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
PUSHA/PUSHAD—Push All General-Purpose Registers
Vol. 2B 4-515
INSTRUCTION SET REFERENCE, M-U
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
9C
PUSHF
NP
Valid
Valid
Push lower 16 bits of EFLAGS.
9C
PUSHFD
NP
N.E.
Valid
Push EFLAGS.
9C
PUSHFQ
NP
Valid
N.E.
Push RFLAGS.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Decrements the stack pointer by 4 (if the current operand-size attribute is 32) and pushes the entire contents of
the EFLAGS register onto the stack, or decrements the stack pointer by 2 (if the operand-size attribute is 16) and
pushes the lower 16 bits of the EFLAGS register (that is, the FLAGS register) onto the stack. These instructions
reverse the operation of the POPF/POPFD instructions.
When copying the entire EFLAGS register to the stack, the VM and RF flags (bits 16 and 17) are not copied; instead,
the values for these flags are cleared in the EFLAGS image stored on the stack. See Chapter 3 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about the EFLAGS register.
The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the same opcode. The PUSHF
instruction is intended for use when the operand-size attribute is 16 and the PUSHFD instruction for when the
operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHF is used and to 32
when PUSHFD is used. Others may treat these mnemonics as synonyms (PUSHF/PUSHFD) and use the current
setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the
mnemonic used.
In 64-bit mode, the instruction’s default operation is to decrement the stack pointer (RSP) by 8 and pushes RFLAGS
on the stack. 16-bit operation is supported using the operand size override prefix 66H. 32-bit operand size cannot
be encoded in this mode. When copying RFLAGS to the stack, the VM and RF flags (bits 16 and 17) are not copied;
instead, values for these flags are cleared in the RFLAGS image stored on the stack.
When in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3, the PUSHF/PUSHFD instruction causes
a general protection exception (#GP).
In the real-address mode, if the ESP or SP register is 1 when PUSHF/PUSHFD instruction executes: an #SS exception is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates
a #DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A.
Operation
IF (PE = 0) or (PE = 1 and ((VM = 0) or (VM = 1 and IOPL = 3)))
(* Real-Address Mode, Protected mode, or Virtual-8086 mode with IOPL equal to 3 *)
THEN
IF OperandSize = 32
THEN
push (EFLAGS AND 00FCFFFFH);
(* VM and RF EFLAG bits are cleared in image stored on the stack *)
ELSE
push (EFLAGS); (* Lower 16 bits only *)
FI;
ELSE IF 64-bit MODE (* In 64-bit Mode *)
IF OperandSize = 64
4-516 Vol. 2B
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack
INSTRUCTION SET REFERENCE, M-U
THEN
push (RFLAGS AND 00000000_00FCFFFFH);
(* VM and RF RFLAG bits are cleared in image stored on the stack; *)
ELSE
push (EFLAGS); (* Lower 16 bits only *)
FI;
ELSE (* In Virtual-8086 Mode with IOPL less than 3 *)
#GP(0); (* Trap to virtual-8086 monitor *)
FI;
Flags Affected
None.
Protected Mode Exceptions
#SS(0)
If the new value of the ESP register is outside the stack segment boundary.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the I/O privilege level is less than 3.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If the stack address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack
Vol. 2B 4-517
INSTRUCTION SET REFERENCE, M-U
PXOR—Logical Exclusive OR
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F EF /r1
RM
V/V
MMX
Bitwise XOR of mm/m64 and mm.
RM
V/V
SSE2
Bitwise XOR of xmm2/m128 and xmm1.
PXOR mm, mm/m64
66 0F EF /r
PXOR xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG EF /r
VPXOR xmm1, xmm2, xmm3/m128
RVM V/V
AVX
Bitwise XOR of xmm3/m128 and xmm2.
VEX.NDS.256.66.0F.WIG EF /r
VPXOR ymm1, ymm2, ymm3/m256
RVM V/V
AVX2
Bitwise XOR of ymm3/m256 and ymm2.
EVEX.NDS.128.66.0F.W0 EF /r
FV
VPXORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst
V/V
AVX512VL Bitwise XOR of packed doubleword integers in
AVX512F xmm2 and xmm3/m128 using writemask k1.
EVEX.NDS.256.66.0F.W0 EF /r
FV
VPXORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst
V/V
AVX512VL Bitwise XOR of packed doubleword integers in
AVX512F ymm2 and ymm3/m256 using writemask k1.
EVEX.NDS.512.66.0F.W0 EF /r
FV
VPXORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst
V/V
AVX512F
EVEX.NDS.128.66.0F.W1 EF /r
VPXORQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL Bitwise XOR of packed quadword integers in
AVX512F xmm2 and xmm3/m128 using writemask k1.
EVEX.NDS.256.66.0F.W1 EF /r
FV
VPXORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
V/V
AVX512VL Bitwise XOR of packed quadword integers in
AVX512F ymm2 and ymm3/m256 using writemask k1.
EVEX.NDS.512.66.0F.W1 EF /r
FV
VPXORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst
V/V
AVX512F
Bitwise XOR of packed doubleword integers in
zmm2 and zmm3/m512/m32bcst using
writemask k1.
Bitwise XOR of packed quadword integers in
zmm2 and zmm3/m512/m64bcst using
writemask k1.
NOTES:
1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand. Each bit of the result is 1 if the corresponding bits of the two operands are different; each bit is 0 if the corresponding bits of the operands are the same.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions 64-bit operand: The source operand can be an MMX technology register or a 64-bit
memory location. The destination operand is an MMX technology register.
4-518 Vol. 2B
PXOR—Logical Exclusive OR
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding register destination are zeroed.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
Operation
PXOR (64-bit operand)
DEST DEST XOR SRC
PXOR (128-bit Legacy SSE version)
DEST DEST XOR SRC
DEST[VLMAX-1:128] (Unmodified)
VPXOR (VEX.128 encoded version)
DEST SRC1 XOR SRC2
DEST[VLMAX-1:128] 0
VPXOR (VEX.256 encoded version)
DEST SRC1 XOR SRC2
DEST[VLMAX-1:256] 0
VPXORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SRC1[i+31:i] BITWISE XOR SRC2[31:0]
ELSE DEST[i+31:i] SRC1[i+31:i] BITWISE XOR SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
PXOR—Logical Exclusive OR
Vol. 2B 4-519
INSTRUCTION SET REFERENCE, M-U
VPXORQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] SRC1[i+63:i] BITWISE XOR SRC2[63:0]
ELSE DEST[i+63:i] SRC1[i+63:i] BITWISE XOR SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPXORD __m512i _mm512_xor_epi32(__m512i a, __m512i b)
VPXORD __m512i _mm512_mask_xor_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b)
VPXORD __m512i _mm512_maskz_xor_epi32( __mmask16 m, __m512i a, __m512i b)
VPXORD __m256i _mm256_xor_epi32(__m256i a, __m256i b)
VPXORD __m256i _mm256_mask_xor_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b)
VPXORD __m256i _mm256_maskz_xor_epi32( __mmask8 m, __m256i a, __m256i b)
VPXORD __m128i _mm_xor_epi32(__m128i a, __m128i b)
VPXORD __m128i _mm_mask_xor_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b)
VPXORD __m128i _mm_maskz_xor_epi32( __mmask16 m, __m128i a, __m128i b)
VPXORQ __m512i _mm512_xor_epi64( __m512i a, __m512i b);
VPXORQ __m512i _mm512_mask_xor_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b);
VPXORQ __m512i _mm512_maskz_xor_epi64(__mmask8 m, __m512i a, __m512i b);
VPXORQ __m256i _mm256_xor_epi64( __m256i a, __m256i b);
VPXORQ __m256i _mm256_mask_xor_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b);
VPXORQ __m256i _mm256_maskz_xor_epi64(__mmask8 m, __m256i a, __m256i b);
VPXORQ __m128i _mm_xor_epi64( __m128i a, __m128i b);
VPXORQ __m128i _mm_mask_xor_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b);
VPXORQ __m128i _mm_maskz_xor_epi64(__mmask8 m, __m128i a, __m128i b);
PXOR:__m64 _mm_xor_si64 (__m64 m1, __m64 m2)
(V)PXOR:__m128i _mm_xor_si128 ( __m128i a, __m128i b)
VPXOR:__m256i _mm256_xor_si256 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
4-520 Vol. 2B
PXOR—Logical Exclusive OR
INSTRUCTION SET REFERENCE, M-U
RCL/RCR/ROL/ROR—Rotate
Opcode**
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
D0 /2
RCL r/m8, 1
M1
Valid
Valid
Rotate 9 bits (CF, r/m8) left once.
REX + D0 /2
RCL r/m8*, 1
M1
Valid
N.E.
Rotate 9 bits (CF, r/m8) left once.
D2 /2
RCL r/m8, CL
MC
Valid
Valid
Rotate 9 bits (CF, r/m8) left CL times.
REX + D2 /2
RCL r/m8*, CL
MC
Valid
N.E.
Rotate 9 bits (CF, r/m8) left CL times.
C0 /2 ib
RCL r/m8, imm8
MI
Valid
Valid
Rotate 9 bits (CF, r/m8) left imm8 times.
REX + C0 /2 ib
RCL r/m8*, imm8
MI
Valid
N.E.
Rotate 9 bits (CF, r/m8) left imm8 times.
D1 /2
RCL r/m16, 1
M1
Valid
Valid
Rotate 17 bits (CF, r/m16) left once.
D3 /2
RCL r/m16, CL
MC
Valid
Valid
Rotate 17 bits (CF, r/m16) left CL times.
C1 /2 ib
RCL r/m16, imm8
MI
Valid
Valid
Rotate 17 bits (CF, r/m16) left imm8 times.
D1 /2
RCL r/m32, 1
M1
Valid
Valid
Rotate 33 bits (CF, r/m32) left once.
REX.W + D1 /2
RCL r/m64, 1
M1
Valid
N.E.
Rotate 65 bits (CF, r/m64) left once. Uses a 6
bit count.
D3 /2
RCL r/m32, CL
MC
Valid
Valid
Rotate 33 bits (CF, r/m32) left CL times.
REX.W + D3 /2
RCL r/m64, CL
MC
Valid
N.E.
Rotate 65 bits (CF, r/m64) left CL times. Uses a
6 bit count.
C1 /2 ib
RCL r/m32, imm8
MI
Valid
Valid
Rotate 33 bits (CF, r/m32) left imm8 times.
REX.W + C1 /2 ib
RCL r/m64, imm8
MI
Valid
N.E.
Rotate 65 bits (CF, r/m64) left imm8 times.
Uses a 6 bit count.
D0 /3
RCR r/m8, 1
M1
Valid
Valid
Rotate 9 bits (CF, r/m8) right once.
REX + D0 /3
RCR r/m8*, 1
M1
Valid
N.E.
Rotate 9 bits (CF, r/m8) right once.
D2 /3
RCR r/m8, CL
MC
Valid
Valid
Rotate 9 bits (CF, r/m8) right CL times.
REX + D2 /3
RCR r/m8*, CL
MC
Valid
N.E.
Rotate 9 bits (CF, r/m8) right CL times.
C0 /3 ib
RCR r/m8, imm8
MI
Valid
Valid
Rotate 9 bits (CF, r/m8) right imm8 times.
REX + C0 /3 ib
RCR r/m8*, imm8
MI
Valid
N.E.
Rotate 9 bits (CF, r/m8) right imm8 times.
D1 /3
RCR r/m16, 1
M1
Valid
Valid
Rotate 17 bits (CF, r/m16) right once.
D3 /3
RCR r/m16, CL
MC
Valid
Valid
Rotate 17 bits (CF, r/m16) right CL times.
C1 /3 ib
RCR r/m16, imm8
MI
Valid
Valid
Rotate 17 bits (CF, r/m16) right imm8 times.
D1 /3
RCR r/m32, 1
M1
Valid
Valid
Rotate 33 bits (CF, r/m32) right once. Uses a 6
bit count.
REX.W + D1 /3
RCR r/m64, 1
M1
Valid
N.E.
Rotate 65 bits (CF, r/m64) right once. Uses a 6
bit count.
D3 /3
RCR r/m32, CL
MC
Valid
Valid
Rotate 33 bits (CF, r/m32) right CL times.
REX.W + D3 /3
RCR r/m64, CL
MC
Valid
N.E.
Rotate 65 bits (CF, r/m64) right CL times. Uses
a 6 bit count.
C1 /3 ib
RCR r/m32, imm8
MI
Valid
Valid
Rotate 33 bits (CF, r/m32) right imm8 times.
REX.W + C1 /3 ib
RCR r/m64, imm8
MI
Valid
N.E.
Rotate 65 bits (CF, r/m64) right imm8 times.
Uses a 6 bit count.
D0 /0
ROL r/m8, 1
M1
Valid
Valid
Rotate 8 bits r/m8 left once.
REX + D0 /0
ROL r/m8*, 1
M1
Valid
N.E.
Rotate 8 bits r/m8 left once
D2 /0
ROL r/m8, CL
MC
Valid
Valid
Rotate 8 bits r/m8 left CL times.
REX + D2 /0
ROL r/m8*, CL
MC
Valid
N.E.
Rotate 8 bits r/m8 left CL times.
C0 /0 ib
ROL r/m8, imm8
MI
Valid
Valid
Rotate 8 bits r/m8 left imm8 times.
RCL/RCR/ROL/ROR—Rotate
Vol. 2B 4-521
INSTRUCTION SET REFERENCE, M-U
Opcode**
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
REX + C0 /0 ib
ROL r/m8*, imm8
MI
Valid
N.E.
Rotate 8 bits r/m8 left imm8 times.
D1 /0
ROL r/m16, 1
M1
Valid
Valid
Rotate 16 bits r/m16 left once.
D3 /0
ROL r/m16, CL
MC
Valid
Valid
Rotate 16 bits r/m16 left CL times.
C1 /0 ib
ROL r/m16, imm8
MI
Valid
Valid
Rotate 16 bits r/m16 left imm8 times.
D1 /0
ROL r/m32, 1
M1
Valid
Valid
Rotate 32 bits r/m32 left once.
REX.W + D1 /0
ROL r/m64, 1
M1
Valid
N.E.
Rotate 64 bits r/m64 left once. Uses a 6 bit
count.
D3 /0
ROL r/m32, CL
MC
Valid
Valid
Rotate 32 bits r/m32 left CL times.
REX.W + D3 /0
ROL r/m64, CL
MC
Valid
N.E.
Rotate 64 bits r/m64 left CL times. Uses a 6
bit count.
C1 /0 ib
ROL r/m32, imm8
MI
Valid
Valid
Rotate 32 bits r/m32 left imm8 times.
REX.W + C1 /0 ib
ROL r/m64, imm8
MI
Valid
N.E.
Rotate 64 bits r/m64 left imm8 times. Uses a
6 bit count.
D0 /1
ROR r/m8, 1
M1
Valid
Valid
Rotate 8 bits r/m8 right once.
REX + D0 /1
ROR r/m8*, 1
M1
Valid
N.E.
Rotate 8 bits r/m8 right once.
D2 /1
ROR r/m8, CL
MC
Valid
Valid
Rotate 8 bits r/m8 right CL times.
REX + D2 /1
ROR r/m8*, CL
MC
Valid
N.E.
Rotate 8 bits r/m8 right CL times.
C0 /1 ib
ROR r/m8, imm8
MI
Valid
Valid
Rotate 8 bits r/m16 right imm8 times.
REX + C0 /1 ib
ROR r/m8*, imm8
MI
Valid
N.E.
Rotate 8 bits r/m16 right imm8 times.
D1 /1
ROR r/m16, 1
M1
Valid
Valid
Rotate 16 bits r/m16 right once.
D3 /1
ROR r/m16, CL
MC
Valid
Valid
Rotate 16 bits r/m16 right CL times.
C1 /1 ib
ROR r/m16, imm8
MI
Valid
Valid
Rotate 16 bits r/m16 right imm8 times.
D1 /1
ROR r/m32, 1
M1
Valid
Valid
Rotate 32 bits r/m32 right once.
REX.W + D1 /1
ROR r/m64, 1
M1
Valid
N.E.
Rotate 64 bits r/m64 right once. Uses a 6 bit
count.
D3 /1
ROR r/m32, CL
MC
Valid
Valid
Rotate 32 bits r/m32 right CL times.
REX.W + D3 /1
ROR r/m64, CL
MC
Valid
N.E.
Rotate 64 bits r/m64 right CL times. Uses a 6
bit count.
C1 /1 ib
ROR r/m32, imm8
MI
Valid
Valid
Rotate 32 bits r/m32 right imm8 times.
REX.W + C1 /1 ib
ROR r/m64, imm8
MI
Valid
N.E.
Rotate 64 bits r/m64 right imm8 times. Uses a
6 bit count.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
** See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M1
ModRM:r/m (w)
1
NA
NA
MC
ModRM:r/m (w)
CL
NA
NA
MI
ModRM:r/m (w)
imm8
NA
NA
4-522 Vol. 2B
RCL/RCR/ROL/ROR—Rotate
INSTRUCTION SET REFERENCE, M-U
Description
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in
the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W = 1).
The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit
positions, except for the most-significant bit, which is rotated to the least-significant bit location. The rotate right
(ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except
for the least-significant bit, which is rotated to the most-significant bit location.
The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the
least-significant bit and shifts the most-significant bit into the CF flag. The RCR instruction shifts the CF flag into
the most-significant bit and shifts the least-significant bit into the CF flag. For the ROL and ROR instructions, the
original value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from
one end to the other.
The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except RCL and RCR instructions
only: a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR
of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the
exclusive OR of the two most-significant bits of the result.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Use of
REX.W promotes the first operand to 64 bits and causes the count operand to become a 6-bit counter.
IA-32 Architecture Compatibility
The 8086 does not mask the rotation count. However, all other IA-32 processors (starting with the Intel 286
processor) do mask the rotation count to 5 bits, resulting in a maximum count of 31. This masking is done in all
operating modes (including the virtual-8086 mode) to reduce the maximum execution time of the instructions.
Operation
(* RCL and RCR instructions *)
SIZE ← OperandSize;
CASE (determine count) OF
SIZE ← 8:
tempCOUNT ← (COUNT AND 1FH) MOD 9;
SIZE ← 16: tempCOUNT ← (COUNT AND 1FH) MOD 17;
SIZE ← 32: tempCOUNT ← COUNT AND 1FH;
SIZE ← 64: tempCOUNT ← COUNT AND 3FH;
ESAC;
(* RCL instruction operation *)
WHILE (tempCOUNT ≠ 0)
DO
tempCF ← MSB(DEST);
DEST ← (DEST ∗ 2) + CF;
CF ← tempCF;
tempCOUNT ← tempCOUNT – 1;
OD;
ELIHW;
IF (COUNT & COUNTMASK) = 1
THEN OF ← MSB(DEST) XOR CF;
ELSE OF is undefined;
FI;
RCL/RCR/ROL/ROR—Rotate
Vol. 2B 4-523
INSTRUCTION SET REFERENCE, M-U
(* RCR instruction operation *)
IF (COUNT & COUNTMASK) = 1
THEN OF ← MSB(DEST) XOR CF;
ELSE OF is undefined;
FI;
WHILE (tempCOUNT ≠ 0)
DO
tempCF ← LSB(SRC);
DEST ← (DEST / 2) + (CF * 2SIZE);
CF ← tempCF;
tempCOUNT ← tempCOUNT – 1;
OD;
(* ROL and ROR instructions *)
IF OperandSize = 64
THEN COUNTMASK = 3FH;
ELSE COUNTMASK = 1FH;
FI;
(* ROL instruction operation *)
tempCOUNT ← (COUNT & COUNTMASK) MOD SIZE
WHILE (tempCOUNT ≠ 0)
DO
tempCF ← MSB(DEST);
DEST ← (DEST ∗ 2) + tempCF;
tempCOUNT ← tempCOUNT – 1;
OD;
ELIHW;
IF (COUNT & COUNTMASK) ≠ 0
THEN CF ← LSB(DEST);
FI;
IF (COUNT & COUNTMASK) = 1
THEN OF ← MSB(DEST) XOR CF;
ELSE OF is undefined;
FI;
(* ROR instruction operation *)
tempCOUNT ← (COUNT & COUNTMASK) MOD SIZE
WHILE (tempCOUNT ≠ 0)
DO
tempCF ← LSB(SRC);
DEST ← (DEST / 2) + (tempCF ∗ 2SIZE);
tempCOUNT ← tempCOUNT – 1;
OD;
ELIHW;
IF (COUNT & COUNTMASK) ≠ 0
THEN CF ← MSB(DEST);
FI;
IF (COUNT & COUNTMASK) = 1
THEN OF ← MSB(DEST) XOR MSB − 1(DEST);
ELSE OF is undefined;
FI;
4-524 Vol. 2B
RCL/RCR/ROL/ROR—Rotate
INSTRUCTION SET REFERENCE, M-U
Flags Affected
If the masked count is 0, the flags are not affected. If the masked count is 1, then the OF flag is affected, otherwise
(masked count is greater than 1) the OF flag is undefined. The CF flag is affected when the masked count is nonzero. The SF, ZF, AF, and PF flags are always unaffected.
Protected Mode Exceptions
#GP(0)
If the source operand is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
#GP(0)
If a memory address referencing the SS segment is in a non-canonical form.
If the source operand is located in a nonwritable segment.
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
RCL/RCR/ROL/ROR—Rotate
Vol. 2B 4-525
INSTRUCTION SET REFERENCE, M-U
RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point Values
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 53 /r
RM
V/V
SSE
Computes the approximate reciprocals of the
packed single-precision floating-point values
in xmm2/m128 and stores the results in
xmm1.
RM
V/V
AVX
Computes the approximate reciprocals of
packed single-precision values in xmm2/mem
and stores the results in xmm1.
RM
V/V
AVX
Computes the approximate reciprocals of
packed single-precision values in ymm2/mem
and stores the results in ymm1.
RCPPS xmm1, xmm2/m128
VEX.128.0F.WIG 53 /r
VRCPPS xmm1, xmm2/m128
VEX.256.0F.WIG 53 /r
VRCPPS ymm1, ymm2/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Performs a SIMD computation of the approximate reciprocals of the four packed single-precision floating-point
values in the source operand (second operand) stores the packed single-precision floating-point results in the
destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination
operand is an XMM register. See Figure 10-5 in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, for an illustration of a SIMD single-precision floating-point operation.
The relative error for this approximation is:
|Relative Error| ≤ 1.5 ∗ 2−12
The RCPPS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a
0.0, an ∞ of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign).
Tiny results (see Section 4.9.1.5, “Numeric Underflow Exception (#U)” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1) are always flushed to 0.0, with the sign of the operand. (Input values greater
than or equal to |1.11111111110100000000000B∗2125| are guaranteed to not produce tiny results; input values
less than or equal to |1.00000000000110000000001B*2126| are guaranteed to produce tiny results, which are in
turn flushed to 0.0; and input values in between this range may or may not produce tiny results, depending on the
implementation.) When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN
is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
4-526 Vol. 2B
RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
RCPPS (128-bit Legacy SSE version)
DEST[31:0] APPROXIMATE(1/SRC[31:0])
DEST[63:32] APPROXIMATE(1/SRC[63:32])
DEST[95:64] APPROXIMATE(1/SRC[95:64])
DEST[127:96] APPROXIMATE(1/SRC[127:96])
DEST[VLMAX-1:128] (Unmodified)
VRCPPS (VEX.128 encoded version)
DEST[31:0] APPROXIMATE(1/SRC[31:0])
DEST[63:32] APPROXIMATE(1/SRC[63:32])
DEST[95:64] APPROXIMATE(1/SRC[95:64])
DEST[127:96] APPROXIMATE(1/SRC[127:96])
DEST[VLMAX-1:128] 0
VRCPPS (VEX.256 encoded version)
DEST[31:0] APPROXIMATE(1/SRC[31:0])
DEST[63:32] APPROXIMATE(1/SRC[63:32])
DEST[95:64] APPROXIMATE(1/SRC[95:64])
DEST[127:96] APPROXIMATE(1/SRC[127:96])
DEST[159:128] APPROXIMATE(1/SRC[159:128])
DEST[191:160] APPROXIMATE(1/SRC[191:160])
DEST[223:192] APPROXIMATE(1/SRC[223:192])
DEST[255:224] APPROXIMATE(1/SRC[255:224])
Intel C/C++ Compiler Intrinsic Equivalent
RCCPS:
__m128 _mm_rcp_ps(__m128 a)
RCPPS:
__m256 _mm256_rcp_ps (__m256 a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.vvvv ≠ 1111B.
RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point Values
Vol. 2B 4-527
INSTRUCTION SET REFERENCE, M-U
RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
F3 0F 53 /r
RM
V/V
SSE
Computes the approximate reciprocal of the
scalar single-precision floating-point value in
xmm2/m32 and stores the result in xmm1.
RVM V/V
AVX
Computes the approximate reciprocal of the
scalar single-precision floating-point value in
xmm3/m32 and stores the result in xmm1.
Also, upper single precision floating-point
values (bits[127:32]) from xmm2 are copied to
xmm1[127:32].
RCPSS xmm1, xmm2/m32
VEX.NDS.LIG.F3.0F.WIG 53 /r
VRCPSS xmm1, xmm2, xmm3/m32
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Computes of an approximate reciprocal of the low single-precision floating-point value in the source operand
(second operand) and stores the single-precision floating-point result in the destination operand. The source
operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The
three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a scalar single-precision floatingpoint operation.
The relative error for this approximation is:
|Relative Error| ≤ 1.5 ∗ 2−12
The RCPSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a
0.0, an ∞ of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign).
Tiny results (see Section 4.9.1.5, “Numeric Underflow Exception (#U)” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1) are always flushed to 0.0, with the sign of the operand. (Input values greater
than or equal to |1.11111111110100000000000B∗2125| are guaranteed to not produce tiny results; input values
less than or equal to |1.00000000000110000000001B*2126| are guaranteed to produce tiny results, which are in
turn flushed to 0.0; and input values in between this range may or may not produce tiny results, depending on the
implementation.) When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN
is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Operation
RCPSS (128-bit Legacy SSE version)
DEST[31:0] APPROXIMATE(1/SRC[31:0])
DEST[VLMAX-1:32] (Unmodified)
4-528 Vol. 2B
RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VRCPSS (VEX.128 encoded version)
DEST[31:0] APPROXIMATE(1/SRC2[31:0])
DEST[127:32] SRC1[127:32]
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
RCPSS:
__m128 _mm_rcp_ss(__m128 a)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 5.
RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values
Vol. 2B 4-529
INSTRUCTION SET REFERENCE, M-U
RDFSBASE/RDGSBASE—Read FS/GS Segment Base
Opcode/
Instruction
Op/
En
64/32bit
Mode
CPUID Feature Flag
Description
F3 0F AE /0
RDFSBASE r32
M
V/I
FSGSBASE
Load the 32-bit destination register with the FS
base address.
F3 REX.W 0F AE /0
RDFSBASE r64
M
V/I
FSGSBASE
Load the 64-bit destination register with the FS
base address.
F3 0F AE /1
RDGSBASE r32
M
V/I
FSGSBASE
Load the 32-bit destination register with the GS
base address.
F3 REX.W 0F AE /1
RDGSBASE r64
M
V/I
FSGSBASE
Load the 64-bit destination register with the GS
base address.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Loads the general-purpose register indicated by the modR/M:r/m field with the FS or GS segment base address.
The destination operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the
operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source base
address (for FS or GS) are ignored and upper 32 bits of the destination register are cleared.
This instruction is supported only in 64-bit mode.
Operation
DEST ← FS/GS segment base address;
Flags Affected
None
C/C++ Compiler Intrinsic Equivalent
RDFSBASE:
unsigned int _readfsbase_u32(void );
RDFSBASE:
unsigned __int64 _readfsbase_u64(void );
RDGSBASE:
unsigned int _readgsbase_u32(void );
RDGSBASE:
unsigned __int64 _readgsbase_u64(void );
Protected Mode Exceptions
#UD
The RDFSBASE and RDGSBASE instructions are not recognized in protected mode.
Real-Address Mode Exceptions
#UD
The RDFSBASE and RDGSBASE instructions are not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The RDFSBASE and RDGSBASE instructions are not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
4-530 Vol. 2B
The RDFSBASE and RDGSBASE instructions are not recognized in compatibility mode.
RDFSBASE/RDGSBASE—Read FS/GS Segment Base
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CR4.FSGSBASE[bit 16] = 0.
If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0.
RDFSBASE/RDGSBASE—Read FS/GS Segment Base
Vol. 2B 4-531
INSTRUCTION SET REFERENCE, M-U
RDMSR—Read from Model Specific Register
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 32
RDMSR
NP
Valid
Valid
Read MSR specified by ECX into EDX:EAX.
NOTES:
* See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Reads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX.
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register
is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On
processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If
fewer than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit
locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection
exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a
general protection exception.
The MSRs control functions for testability, execution tracing, performance-monitoring, and machine check errors.
Chapter 35, “Model-Specific Registers (MSRs),” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C, lists all the MSRs that can be read with this instruction and their addresses. Note that each
processor family has its own set of MSRs.
The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before
using this instruction.
IA-32 Architecture Compatibility
The MSRs and the ability to read them with the RDMSR instruction were introduced into the IA-32 Architecture with
the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor
results in an invalid opcode exception #UD.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.
Operation
EDX:EAX ← MSR[ECX];
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the value in ECX specifies a reserved or unimplemented MSR address.
#UD
4-532 Vol. 2B
If the LOCK prefix is used.
RDMSR—Read from Model Specific Register
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#GP
If the value in ECX specifies a reserved or unimplemented MSR address.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
The RDMSR instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
RDMSR—Read from Model Specific Register
Vol. 2B 4-533
INSTRUCTION SET REFERENCE, M-U
RDPID—Read Processor ID
Opcode/
Instruction
Op/
En
64/32bit
Mode
CPUID
Description
Feature Flag
F3 0F C7 /7
RDPID r32
M
N.E./V
RDPID
Read IA32_TSC_AUX into r32.
F3 0F C7 /7
RDPID r64
M
V/N.E.
RDPID
Read IA32_TSC_AUX into r64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Reads the value of the IA32_TSC_AUX MSR (address C0000103H) into the destination register. The value of CS.D
and operand-size prefixes (66H and REX.W) do not affect the behavior of the RDPID instruction.
Operation
DEST ← IA32_TSC_AUX
Flags Affected
None.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If the F2 prefix is used.
If CPUID.7H.0:ECX.RDPID[bit 22] = 0.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-534 Vol. 2B
RDPID—Read Processor ID
INSTRUCTION SET REFERENCE, M-U
RDPKRU—Read Protection Key Rights for User Pages
Opcode*
Instruction
Op/
En
64/32bit
Mode
Support
CPUID
Feature
Flag
Description
0F 01 EE
RDPKRU
NP
V/V
OSPKE
Reads PKRU into EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Reads the value of PKRU into EAX and clears EDX. ECX must be 0 when RDPKRU is executed; otherwise, a generalprotection exception (#GP) occurs.
RDPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can
discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].
On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX are ignored and the high-order
32-bits of RDX and RAX are cleared.
Operation
IF (ECX = 0)
THEN
EAX ← PKRU;
EDX ← 0;
ELSE #GP(0);
FI;
Flags Affected
None.
C/C++ Compiler Intrinsic Equivalent
RDPKRU:
uint32_t _rdpkru_u32(void);
Protected Mode Exceptions
#GP(0)
#UD
If ECX
≠0
If the LOCK prefix is used.
If CR4.PKE = 0.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
RDPKRU—Read Protection Key Rights for User Pages
Vol. 2B 4-535
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-536 Vol. 2B
RDPKRU—Read Protection Key Rights for User Pages
INSTRUCTION SET REFERENCE, M-U
RDPMC—Read Performance-Monitoring Counters
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 33
RDPMC
NP
Valid
Valid
Read performance-monitoring counter
specified by ECX into EDX:EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
The EAX register is loaded with the low-order 32 bits. The EDX register is loaded with the supported high-order bits
of the counter. The number of high-order bits loaded into EDX is implementation specific on processors that do no
support architectural performance monitoring. The width of fixed-function and general-purpose performance counters on processors supporting architectural performance monitoring are reported by CPUID 0AH leaf. See below for
the treatment of the EDX register for “fast” reads.
The ECX register specifies the counter type (if the processor supports architectural performance monitoring) and
counter index. Counter type is specified in ECX[30] to select one of two type of performance counters. If the
processor does not support architectural performance monitoring, ECX[30:0] specifies the counter index; otherwise ECX[29:0] specifies the index relative to the base of each counter type. ECX[31] selects “fast” read mode if
supported. The two counter types are:
•
General-purpose or special-purpose performance counters are specified with ECX[30] = 0: The number of
general-purpose performance counters on processor supporting architectural performance monitoring are
reported by CPUID 0AH leaf. The number of general-purpose counters is model specific if the processor does
not support architectural performance monitoring, see Chapter 18, “Performance Monitoring” of Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B. Special-purpose counters are available only in
selected processor members, see Table 4-16.
•
Fixed-function performance counter are specified with ECX[30] = 1. The number fixed-function performance
counters is enumerated by CPUID 0AH leaf. See Chapter 30 of Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3B. This counter type is selected if ECX[30] is set.
The width of fixed-function performance counters and general-purpose performance counters on processor
supporting architectural performance monitoring are reported by CPUID 0AH leaf. The width of general-purpose
performance counters are 40-bits for processors that do not support architectural performance monitoring counters. The width of special-purpose performance counters are implementation specific.
Table 4-16 lists valid indices of the general-purpose and special-purpose performance counters according to the
DisplayFamily_DisplayModel values of CPUID encoding for each processor family (see CPUID instruction in Chapter
3, “Instruction Set Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A).
Table 4-16. Valid General and Special Purpose Performance Counter Index Range for RDPMC
Processor Family
DisplayFamily_DisplayModel/
Other Signatures
Valid PMC Index
Range
General-purpose
Counters
P6
06H_01H, 06H_03H, 06H_05H,
06H_06H, 06H_07H, 06H_08H,
06H_0AH, 06H_0BH
0, 1
0, 1
Processors Based on Intel NetBurst
microarchitecture (No L3)
0FH_00H, 0FH_01H, 0FH_02H,
0FH_03H, 0FH_04H, 0FH_06H
≥ 0 and ≤ 17
≥ 0 and ≤ 17
Pentium M processors
06H_09H, 06H_0DH
0, 1
0, 1
Processors Based on Intel NetBurst
microarchitecture (No L3)
0FH_03H, 0FH_04H) and (L3 is
present)
≥ 0 and ≤ 25
≥ 0 and ≤ 17
RDPMC—Read Performance-Monitoring Counters
Vol. 2B 4-537
INSTRUCTION SET REFERENCE, M-U
Table 4-16. Valid General and Special Purpose Performance Counter Index Range for RDPMC (Contd.)
Processor Family
DisplayFamily_DisplayModel/
Other Signatures
Valid PMC Index
Range
General-purpose
Counters
Intel® Core™ Solo and Intel® Core™ Duo
processors, Dual-core Intel® Xeon®
processor LV
06H_0EH
0, 1
0, 1
Intel® Core™2 Duo processor, Intel Xeon
processor 3000, 5100, 5300, 7300 Series general-purpose PMC
06H_0FH
0, 1
0, 1
Intel® Core™2 Duo processor family, Intel
Xeon processor 3100, 3300, 5200, 5400
series - general-purpose PMC
06H_17H
0, 1
0, 1
Intel Xeon processors 7400 series
(06H_1DH)
≥ 0 and ≤ 9
0, 1
06H_1CH, 06_26H, 06_27H,
06_35H, 06_36H
0, 1
0, 1
Intel® Atom™ processors based on
Silvermont or Airmont microarchitectures
06H_37H, 06_4AH, 06_4DH,
06_5AH, 06_5DH, 06_4CH
0, 1
0, 1
Next Generation Intel® Atom™ processors
based on Goldmont microarchitecture
06H_5CH, 06_5FH
0-3
0-3
Intel® processors based on the Nehalem,
Westmere microarchitectures
06H_1AH, 06H_1EH, 06H_1FH,
06_25H, 06_2CH, 06H_2EH,
06_2FH
0-3
0-3
Intel® processors based on the Sandy
Bridge, Ivy Bridge microarchitecture
06H_2AH, 06H_2DH, 06H_3AH,
06H_3EH
0-3 (0-7 if
HyperThreading is off)
0-3 (0-7 if
HyperThreading is off)
Intel® processors based on the Haswell,
Broadwell, SkyLake microarchitectures
06H_3CH, 06H_45H, 06H_46H,
06H_3FH, 06_3DH, 06_47H,
4FH, 06_56H, 06_4EH, 06_5EH
0-3 (0-7 if
HyperThreading is off)
0-3 (0-7 if
HyperThreading is off)
45 nm and 32 nm Intel
®
Atom™ processors
Processors based on Intel NetBurst microarchitecture support “fast” (32-bit) and “slow” (40-bit) reads on the first
18 performance counters. Selected this option using ECX[31]. If bit 31 is set, RDPMC reads only the low 32 bits of
the selected performance counter. If bit 31 is clear, all 40 bits are read. A 32-bit result is returned in EAX and EDX
is set to 0. A 32-bit read executes faster on these processors than a full 40-bit read.
On processors based on Intel NetBurst microarchitecture with L3, performance counters with indices 18-25 are 32bit counters. EDX is cleared after executing RDPMC for these counters.
In Intel Core 2 processor family, Intel Xeon processor 3000, 5100, 5300 and 7400 series, the fixed-function performance counters are 40-bits wide; they can be accessed by RDMPC with ECX between from 4000_0000H and
4000_0002H.
On Intel Xeon processor 7400 series, there are eight 32-bit special-purpose counters addressable with indices 2-9,
ECX[30]=0.
When in protected or virtual 8086 mode, the performance-monitoring counters enabled (PCE) flag in register CR4
restricts the use of the RDPMC instruction as follows. When the PCE flag is set, the RDPMC instruction can be
executed at any privilege level; when the flag is clear, the instruction can only be executed at privilege level 0.
(When in real-address mode, the RDPMC instruction is always enabled.)
The performance-monitoring counters can also be read with the RDMSR instruction, when executing at privilege
level 0.
The performance-monitoring counters are event counters that can be programmed to count events such as the
number of instructions decoded, number of interrupts received, or number of cache loads. Chapter 19, “Performance Monitoring Events,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, lists
the events that can be counted for various processors in the Intel 64 and IA-32 architecture families.
The RDPMC instruction is not a serializing instruction; that is, it does not imply that all the events caused by the
preceding instructions have been completed or that events caused by subsequent instructions have not begun. If
4-538 Vol. 2B
RDPMC—Read Performance-Monitoring Counters
INSTRUCTION SET REFERENCE, M-U
an exact event count is desired, software must insert a serializing instruction (such as the CPUID instruction)
before and/or after the RDPMC instruction.
Performing back-to-back fast reads are not guaranteed to be monotonic. To guarantee monotonicity on back-toback reads, a serializing instruction must be placed between the two RDPMC instructions.
The RDPMC instruction can execute in 16-bit addressing mode or virtual-8086 mode; however, the full contents of
the ECX register are used to select the counter, and the event count is stored in the full EAX and EDX registers. The
RDPMC instruction was introduced into the IA-32 Architecture in the Pentium Pro processor and the Pentium
processor with MMX technology. The earlier Pentium processors have performance-monitoring counters, but they
must be read with the RDMSR instruction.
Operation
(* Intel processors that support architectural performance monitoring *)
Most significant counter bit (MSCB) = 47
IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)
EAX ← IA32_FIXED_CTR(ECX)[30:0];
EDX ← IA32_FIXED_CTR(ECX)[MSCB:32];
ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)
EAX ← PMC(ECX[30:0])[31:0];
EDX ← PMC(ECX[30:0])[MSCB:32];
ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
#GP(0);
FI;
(* Intel Core 2 Duo processor family and Intel Xeon processor 3000, 5100, 5300, 7400 series*)
Most significant counter bit (MSCB) = 39
IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)
EAX ← IA32_FIXED_CTR(ECX)[30:0];
EDX ← IA32_FIXED_CTR(ECX)[MSCB:32];
ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)
EAX ← PMC(ECX[30:0])[31:0];
EDX ← PMC(ECX[30:0])[MSCB:32];
ELSE IF (ECX[30] = 0 and ECX[29:0] in valid special-purpose counter range)
EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)
ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
#GP(0);
FI;
(* P6 family processors and Pentium processor with MMX technology *)
IF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
THEN
EAX ← PMC(ECX)[31:0];
EDX ← PMC(ECX)[39:32];
ELSE (* ECX is not 0 or 1 or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
#GP(0);
FI;
(* Processors based on Intel NetBurst microarchitecture *)
IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
THEN IF (ECX[30:0] = 0:17)
THEN IF ECX[31] = 0
RDPMC—Read Performance-Monitoring Counters
Vol. 2B 4-539
INSTRUCTION SET REFERENCE, M-U
THEN
EAX ← PMC(ECX[30:0])[31:0]; (* 40-bit read *)
EDX ← PMC(ECX[30:0])[39:32];
ELSE (* ECX[31] = 1*)
THEN
EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)
EDX ← 0;
FI;
ELSE IF (*64-bit Intel processor based on Intel NetBurst microarchitecture with L3 *)
THEN IF (ECX[30:0] = 18:25 )
EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)
EDX ← 0;
FI;
ELSE (* Invalid PMC index in ECX[30:0], see Table 4-19. *)
GP(0);
FI;
ELSE (* CR4.PCE = 0 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
#GP(0);
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0 and the PCE flag in the CR4 register is clear.
If an invalid performance counter index is specified (see Table 4-16).
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If an invalid performance counter index is specified (see Table 4-16).
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the PCE flag in the CR4 register is clear.
If an invalid performance counter index is specified (see Table 4-16).
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0 and the PCE flag in the CR4 register is clear.
If an invalid performance counter index is specified (see Table 4-16).
#UD
4-540 Vol. 2B
If the LOCK prefix is used.
RDPMC—Read Performance-Monitoring Counters
INSTRUCTION SET REFERENCE, M-U
RDRAND—Read Random Number
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F C7 /6
M
V/V
RDRAND
Read a 16-bit random number and store in the
destination register.
M
V/V
RDRAND
Read a 32-bit random number and store in the
destination register.
M
V/I
RDRAND
Read a 64-bit random number and store in the
destination register.
RDRAND r16
0F C7 /6
RDRAND r32
REX.W + 0F C7 /6
RDRAND r64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Loads a hardware generated random value and store it in the destination register. The size of the random value is
determined by the destination register size and operating mode. The Carry Flag indicates whether a random value
is available at the time the instruction is executed. CF=1 indicates that the data in the destination is valid. Otherwise CF=0 and the data in the destination operand will be returned as zeros for the specified width. All other flags
are forced to 0 in either situation. Software must check the state of CF=1 for determining if a valid random value
has been returned, otherwise it is expected to loop and retry execution of RDRAND (see Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, Section 7.3.17, “Random Number Generator Instructions”).
This instruction is available at all privilege levels.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.B permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit operands. See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF HW_RND_GEN.ready = 1
THEN
CASE of
osize is 64: DEST[63:0] ← HW_RND_GEN.data;
osize is 32: DEST[31:0] ← HW_RND_GEN.data;
osize is 16: DEST[15:0] ← HW_RND_GEN.data;
ESAC
CF ← 1;
ELSE
CASE of
osize is 64: DEST[63:0] ← 0;
osize is 32: DEST[31:0] ← 0;
osize is 16: DEST[15:0] ← 0;
ESAC
CF ← 0;
FI
OF, SF, ZF, AF, PF ← 0;
Flags Affected
The CF flag is set according to the result (see the “Operation” section above). The OF, SF, ZF, AF, and PF flags are
set to 0.
RDRAND—Read Random Number
Vol. 2B 4-541
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
RDRAND:
int _rdrand16_step( unsigned short * );
RDRAND:
int _rdrand32_step( unsigned int * );
RDRAND:
int _rdrand64_step( unsigned __int64 *);
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If the F2H or F3H prefix is used.
If CPUID.01H:ECX.RDRAND[bit 30] = 0.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-542 Vol. 2B
RDRAND—Read Random Number
INSTRUCTION SET REFERENCE, M-U
RDSEED—Read Random SEED
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
RDSEED
Description
M
64/32
bit Mode
Support
V/V
0F C7 /7
RDSEED r16
0F C7 /7
RDSEED r32
M
V/V
RDSEED
Read a 32-bit NIST SP800-90B & C compliant random value and
store in the destination register.
REX.W + 0F C7 /7
RDSEED r64
M
V/I
RDSEED
Read a 64-bit NIST SP800-90B & C compliant random value and
store in the destination register.
Read a 16-bit NIST SP800-90B & C compliant random value and
store in the destination register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Loads a hardware generated random value and store it in the destination register. The random value is generated
from an Enhanced NRBG (Non Deterministic Random Bit Generator) that is compliant to NIST SP800-90B and NIST
SP800-90C in the XOR construction mode. The size of the random value is determined by the destination register
size and operating mode. The Carry Flag indicates whether a random value is available at the time the instruction
is executed. CF=1 indicates that the data in the destination is valid. Otherwise CF=0 and the data in the destination
operand will be returned as zeros for the specified width. All other flags are forced to 0 in either situation. Software
must check the state of CF=1 for determining if a valid random seed value has been returned, otherwise it is
expected to loop and retry execution of RDSEED (see Section 1.2).
The RDSEED instruction is available at all privilege levels. The RDSEED instruction executes normally either inside
or outside a transaction region.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.B permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit operands. See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF HW_NRND_GEN.ready = 1
THEN
CASE of
osize is 64: DEST[63:0] ← HW_NRND_GEN.data;
osize is 32: DEST[31:0] ← HW_NRND_GEN.data;
osize is 16: DEST[15:0] ← HW_NRND_GEN.data;
ESAC;
CF ← 1;
ELSE
CASE of
osize is 64: DEST[63:0] ← 0;
osize is 32: DEST[31:0] ← 0;
osize is 16: DEST[15:0] ← 0;
ESAC;
CF ← 0;
FI;
OF, SF, ZF, AF, PF ← 0;
RDSEED—Read Random SEED
Vol. 2B 4-543
INSTRUCTION SET REFERENCE, M-U
Flags Affected
The CF flag is set according to the result (see the "Operation" section above). The OF, SF, ZF, AF, and PF flags
are set to 0.
C/C++ Compiler Intrinsic Equivalent
RDSEED int _rdseed16_step( unsigned short * );
RDSEED int _rdseed32_step( unsigned int * );
RDSEED int _rdseed64_step( unsigned __int64 *);
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If the F2H or F3H prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If the F2H or F3H prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If the F2H or F3H prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
If the F2H or F3H prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If the F2H or F3H prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.
4-544 Vol. 2B
RDSEED—Read Random SEED
INSTRUCTION SET REFERENCE, M-U
RDTSC—Read Time-Stamp Counter
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 31
RDTSC
NP
Valid
Valid
Read time-stamp counter into EDX:EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Reads the current value of the processor’s time-stamp counter (a 64-bit MSR) into the EDX:EAX registers. The EDX
register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits.
(On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.)
The processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever
the processor is reset. See “Time Stamp Counter” in Chapter 17 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3B, for specific details of the time stamp counter behavior.
The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSC instruction as follows. When the
flag is clear, the RDTSC instruction can be executed at any privilege level; when the flag is set, the instruction can
only be executed at privilege level 0.
The time-stamp counter can also be read with the RDMSR instruction, when executing at privilege level 0.
The RDTSC instruction is not a serializing instruction. It does not necessarily wait until all previous instructions
have been executed before reading the counter. Similarly, subsequent instructions may begin execution before the
read operation is performed. If software requires RDTSC to be executed only after all previous instructions have
completed locally, it can either use RDTSCP (if the processor supports that instruction) or execute the sequence
LFENCE;RDTSC.
This instruction was introduced by the Pentium processor.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.
Operation
IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
THEN EDX:EAX ← TimeStampCounter;
ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
#GP(0);
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the TSD flag in register CR4 is set and the CPL is greater than 0.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
RDTSC—Read Time-Stamp Counter
Vol. 2B 4-545
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#GP(0)
If the TSD flag in register CR4 is set.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-546 Vol. 2B
RDTSC—Read Time-Stamp Counter
INSTRUCTION SET REFERENCE, M-U
RDTSCP—Read Time-Stamp Counter and Processor ID
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 F9
RDTSCP
NP
Valid
Valid
Read 64-bit time-stamp counter and
IA32_TSC_AUX value into EDX:EAX and ECX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Reads the current value of the processor’s time-stamp counter (a 64-bit MSR) into the EDX:EAX registers and also
reads the value of the IA32_TSC_AUX MSR (address C0000103H) into the ECX register. The EDX register is loaded
with the high-order 32 bits of the IA32_TSC MSR; the EAX register is loaded with the low-order 32 bits of the
IA32_TSC MSR; and the ECX register is loaded with the low-order 32-bits of IA32_TSC_AUX MSR. On processors
that support the Intel 64 architecture, the high-order 32 bits of each of RAX, RDX, and RCX are cleared.
The processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever
the processor is reset. See “Time Stamp Counter” in Chapter 17 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3B, for specific details of the time stamp counter behavior.
The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSCP instruction as follows. When the
flag is clear, the RDTSCP instruction can be executed at any privilege level; when the flag is set, the instruction can
only be executed at privilege level 0.
The RDTSCP instruction waits until all previous instructions have been executed before reading the counter.
However, subsequent instructions may begin execution before the read operation is performed.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.
Operation
IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
THEN
EDX:EAX ← TimeStampCounter;
ECX ← IA32_TSC_AUX[31:0];
ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
#GP(0);
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the TSD flag in register CR4 is set and the CPL is greater than 0.
#UD
If the LOCK prefix is used.
If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.
RDTSCP—Read Time-Stamp Counter and Processor ID
Vol. 2B 4-547
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#GP(0)
#UD
If the TSD flag in register CR4 is set.
If the LOCK prefix is used.
If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-548 Vol. 2B
RDTSCP—Read Time-Stamp Counter and Processor ID
INSTRUCTION SET REFERENCE, M-U
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F3 6C
REP INS m8, DX
NP
Valid
Valid
Input (E)CX bytes from port DX into ES:[(E)DI].
F3 6C
REP INS m8, DX
NP
Valid
N.E.
Input RCX bytes from port DX into [RDI].
F3 6D
REP INS m16, DX
NP
Valid
Valid
Input (E)CX words from port DX into ES:[(E)DI.]
F3 6D
REP INS m32, DX
NP
Valid
Valid
Input (E)CX doublewords from port DX into
ES:[(E)DI].
F3 6D
REP INS r/m32, DX
NP
Valid
N.E.
Input RCX default size from port DX into [RDI].
F3 A4
REP MOVS m8, m8
NP
Valid
Valid
Move (E)CX bytes from DS:[(E)SI] to ES:[(E)DI].
F3 REX.W A4
REP MOVS m8, m8
NP
Valid
N.E.
Move RCX bytes from [RSI] to [RDI].
F3 A5
REP MOVS m16, m16
NP
Valid
Valid
Move (E)CX words from DS:[(E)SI] to ES:[(E)DI].
F3 A5
REP MOVS m32, m32
NP
Valid
Valid
Move (E)CX doublewords from DS:[(E)SI] to
ES:[(E)DI].
F3 REX.W A5
REP MOVS m64, m64
NP
Valid
N.E.
Move RCX quadwords from [RSI] to [RDI].
F3 6E
REP OUTS DX, r/m8
NP
Valid
Valid
Output (E)CX bytes from DS:[(E)SI] to port DX.
F3 REX.W 6E
REP OUTS DX, r/m8*
NP
Valid
N.E.
Output RCX bytes from [RSI] to port DX.
F3 6F
REP OUTS DX, r/m16
NP
Valid
Valid
Output (E)CX words from DS:[(E)SI] to port DX.
F3 6F
REP OUTS DX, r/m32
NP
Valid
Valid
Output (E)CX doublewords from DS:[(E)SI] to
port DX.
F3 REX.W 6F
REP OUTS DX, r/m32
NP
Valid
N.E.
Output RCX default size from [RSI] to port DX.
F3 AC
REP LODS AL
NP
Valid
Valid
Load (E)CX bytes from DS:[(E)SI] to AL.
F3 REX.W AC
REP LODS AL
NP
Valid
N.E.
Load RCX bytes from [RSI] to AL.
F3 AD
REP LODS AX
NP
Valid
Valid
Load (E)CX words from DS:[(E)SI] to AX.
F3 AD
REP LODS EAX
NP
Valid
Valid
Load (E)CX doublewords from DS:[(E)SI] to
EAX.
F3 REX.W AD
REP LODS RAX
NP
Valid
N.E.
Load RCX quadwords from [RSI] to RAX.
F3 AA
REP STOS m8
NP
Valid
Valid
Fill (E)CX bytes at ES:[(E)DI] with AL.
F3 REX.W AA
REP STOS m8
NP
Valid
N.E.
Fill RCX bytes at [RDI] with AL.
F3 AB
REP STOS m16
NP
Valid
Valid
Fill (E)CX words at ES:[(E)DI] with AX.
F3 AB
REP STOS m32
NP
Valid
Valid
Fill (E)CX doublewords at ES:[(E)DI] with EAX.
F3 REX.W AB
REP STOS m64
NP
Valid
N.E.
Fill RCX quadwords at [RDI] with RAX.
F3 A6
REPE CMPS m8, m8
NP
Valid
Valid
Find nonmatching bytes in ES:[(E)DI] and
DS:[(E)SI].
F3 REX.W A6
REPE CMPS m8, m8
NP
Valid
N.E.
Find non-matching bytes in [RDI] and [RSI].
F3 A7
REPE CMPS m16, m16
NP
Valid
Valid
Find nonmatching words in ES:[(E)DI] and
DS:[(E)SI].
F3 A7
REPE CMPS m32, m32
NP
Valid
Valid
Find nonmatching doublewords in ES:[(E)DI]
and DS:[(E)SI].
F3 REX.W A7
REPE CMPS m64, m64
NP
Valid
N.E.
Find non-matching quadwords in [RDI] and
[RSI].
F3 AE
REPE SCAS m8
NP
Valid
Valid
Find non-AL byte starting at ES:[(E)DI].
F3 REX.W AE
REPE SCAS m8
NP
Valid
N.E.
Find non-AL byte starting at [RDI].
F3 AF
REPE SCAS m16
NP
Valid
Valid
Find non-AX word starting at ES:[(E)DI].
F3 AF
REPE SCAS m32
NP
Valid
Valid
Find non-EAX doubleword starting at
ES:[(E)DI].
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix
Vol. 2B 4-549
INSTRUCTION SET REFERENCE, M-U
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F3 REX.W AF
REPE SCAS m64
NP
Valid
N.E.
Find non-RAX quadword starting at [RDI].
F2 A6
REPNE CMPS m8, m8
NP
Valid
Valid
Find matching bytes in ES:[(E)DI] and DS:[(E)SI].
F2 REX.W A6
REPNE CMPS m8, m8
NP
Valid
N.E.
Find matching bytes in [RDI] and [RSI].
F2 A7
REPNE CMPS m16, m16
NP
Valid
Valid
Find matching words in ES:[(E)DI] and
DS:[(E)SI].
F2 A7
REPNE CMPS m32, m32
NP
Valid
Valid
Find matching doublewords in ES:[(E)DI] and
DS:[(E)SI].
F2 REX.W A7
REPNE CMPS m64, m64
NP
Valid
N.E.
Find matching doublewords in [RDI] and [RSI].
F2 AE
REPNE SCAS m8
NP
Valid
Valid
Find AL, starting at ES:[(E)DI].
F2 REX.W AE
REPNE SCAS m8
NP
Valid
N.E.
Find AL, starting at [RDI].
F2 AF
REPNE SCAS m16
NP
Valid
Valid
Find AX, starting at ES:[(E)DI].
F2 AF
REPNE SCAS m32
NP
Valid
Valid
Find EAX, starting at ES:[(E)DI].
F2 REX.W AF
REPNE SCAS m64
NP
Valid
N.E.
Find RAX, starting at [RDI].
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Repeats a string instruction the number of times specified in the count register or until the indicated condition of
the ZF flag is no longer met. The REP (repeat), REPE (repeat while equal), REPNE (repeat while not equal), REPZ
(repeat while zero), and REPNZ (repeat while not zero) mnemonics are prefixes that can be added to one of the
string instructions. The REP prefix can be added to the INS, OUTS, MOVS, LODS, and STOS instructions, and the
REPE, REPNE, REPZ, and REPNZ prefixes can be added to the CMPS and SCAS instructions. (The REPZ and REPNZ
prefixes are synonymous forms of the REPE and REPNE prefixes, respectively.) The F3H prefix is defined for the
following instructions and undefined for the rest:
•
•
F3H as REP/REPE/REPZ for string and input/output instruction.
F3H is a mandatory prefix for POPCNT, LZCNT, and ADOX.
The REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP
instruction or another looping construct. All of these repeat prefixes cause the associated instruction to be repeated
until the count in register is decremented to 0. See Table 4-17.
Table 4-17. Repeat Prefixes
Repeat Prefix
Termination Condition 1*
Termination Condition 2
REP
RCX or (E)CX = 0
None
REPE/REPZ
RCX or (E)CX = 0
ZF = 0
REPNE/REPNZ
RCX or (E)CX = 0
ZF = 1
NOTES:
* Count register is CX, ECX or RCX by default, depending on attributes of the operating modes.
4-550 Vol. 2B
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix
INSTRUCTION SET REFERENCE, M-U
The REPE, REPNE, REPZ, and REPNZ prefixes also check the state of the ZF flag after each iteration and terminate
the repeat loop if the ZF flag is not in the specified state. When both termination conditions are tested, the cause
of a repeat termination can be determined either by testing the count register with a JECXZ instruction or by
testing the ZF flag (with a JZ, JNZ, or JNE instruction).
When the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require initialization because both
the CMPS and SCAS instructions affect the ZF flag according to the results of the comparisons they make.
A repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the
registers is preserved to allow the string operation to be resumed upon a return from the exception or interrupt
handler. The source and destination registers point to the next string elements to be operated on, the EIP register
points to the string instruction, and the ECX register has the value it held following the last successful iteration of
the instruction. This mechanism allows long string operations to proceed without affecting the interrupt response
time of the system.
When a fault occurs during the execution of a CMPS or SCAS instruction that is prefixed with REPE or REPNE, the
EFLAGS value is restored to the state prior to the execution of the instruction. Since the SCAS and CMPS instructions do not use EFLAGS as an input, the processor can resume the instruction after the page fault handler.
Use the REP INS and REP OUTS instructions with caution. Not all I/O ports can handle the rate at which these
instructions execute. Note that a REP STOS instruction is the fastest way to initialize a large block of memory.
In 64-bit mode, the operand size of the count register is associated with the address size attribute. Thus the default
count register is RCX; REX.W has no effect on the address size and the count register. In 64-bit mode, if 67H is
used to override address size attribute, the count register is ECX and any implicit source/destination operand will
use the corresponding 32-bit index register. See the summary chart at the beginning of this section for encoding
data and limits.
REP INS may read from the I/O port without writing to the memory location if an exception or VM exit occurs due
to the write (e.g. #PF). If this would be problematic, for example because the I/O port read has side-effects, software should ensure the write to the memory location does not cause an exception or VM exit.
Operation
IF AddressSize = 16
THEN
Use CX for CountReg;
Implicit Source/Dest operand for memory use of SI/DI;
ELSE IF AddressSize = 64
THEN Use RCX for CountReg;
Implicit Source/Dest operand for memory use of RSI/RDI;
ELSE
Use ECX for CountReg;
Implicit Source/Dest operand for memory use of ESI/EDI;
FI;
WHILE CountReg ≠ 0
DO
Service pending interrupts (if any);
Execute associated string instruction;
CountReg ← (CountReg – 1);
IF CountReg = 0
THEN exit WHILE loop; FI;
IF (Repeat prefix is REPZ or REPE) and (ZF = 0)
or (Repeat prefix is REPNZ or REPNE) and (ZF = 1)
THEN exit WHILE loop; FI;
OD;
Flags Affected
None; however, the CMPS and SCAS instructions do set the status flags in the EFLAGS register.
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix
Vol. 2B 4-551
INSTRUCTION SET REFERENCE, M-U
Exceptions (All Operating Modes)
Exceptions may be generated by an instruction associated with the prefix.
64-Bit Mode Exceptions
#GP(0)
4-552 Vol. 2B
If the memory address is in a non-canonical form.
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix
INSTRUCTION SET REFERENCE, M-U
RET—Return from Procedure
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
C3
RET
NP
Valid
Valid
Near return to calling procedure.
CB
RET
NP
Valid
Valid
Far return to calling procedure.
C2 iw
RET imm16
I
Valid
Valid
Near return to calling procedure and pop
imm16 bytes from stack.
CA iw
RET imm16
I
Valid
Valid
Far return to calling procedure and pop imm16
bytes from stack.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
I
imm16
NA
NA
NA
Description
Transfers program control to a return address located on the top of the stack. The address is usually placed on the
stack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.
The optional source operand specifies the number of stack bytes to be released after the return address is popped;
the default is none. This operand can be used to release parameters from the stack that were passed to the called
procedure and are no longer needed. It must be used when the CALL instruction used to switch to a new procedure
uses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET
instruction must specify the same number of bytes as is specified in the word count field of the call gate.
The RET instruction can be used to execute three different types of returns:
•
Near return — A return to a calling procedure within the current code segment (the segment currently pointed
to by the CS register), sometimes referred to as an intrasegment return.
•
Far return — A return to a calling procedure located in a different segment than the current code segment,
sometimes referred to as an intersegment return.
•
Inter-privilege-level far return — A far return to a different privilege level than that of the currently
executing program or procedure.
The inter-privilege-level return type can only be executed in protected mode. See the section titled “Calling Procedures Using Call and RET” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, for detailed information on near, far, and inter-privilege-level returns.
When executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack
into the EIP register and begins program execution at the new instruction pointer. The CS register is unchanged.
When executing a far return, the processor pops the return instruction pointer from the top of the stack into the EIP
register, then pops the segment selector from the top of the stack into the CS register. The processor then begins
program execution in the new code segment at the new instruction pointer.
The mechanics of an inter-privilege-level far return are similar to an intersegment return, except that the
processor examines the privilege levels and access rights of the code and stack segments being returned to determine if the control transfer is allowed to be made. The DS, ES, FS, and GS segment registers are cleared by the RET
instruction during an inter-privilege-level return if they refer to segments that are not allowed to be accessed at the
new privilege level. Since a stack switch also occurs on an inter-privilege level return, the ESP and SS registers are
loaded from the stack.
If parameters are passed to the called procedure during an inter-privilege level call, the optional source operand
must be used with the RET instruction to release the parameters on the return. Here, the parameters are released
both from the called procedure’s stack and the calling procedure’s stack (that is, the stack being returned to).
In 64-bit mode, the default operation size of this instruction is the stack-address size, i.e. 64 bits. This applies to
near returns, not far returns; the default operation size of far returns is 32 bits.
RET—Return from Procedure
Vol. 2B 4-553
INSTRUCTION SET REFERENCE, M-U
Operation
(* Near return *)
IF instruction = near return
THEN;
IF OperandSize = 32
THEN
IF top 4 bytes of stack not within stack limits
THEN #SS(0); FI;
EIP ← Pop();
ELSE
IF OperandSize = 64
THEN
IF top 8 bytes of stack not within stack limits
THEN #SS(0); FI;
RIP ← Pop();
ELSE (* OperandSize = 16 *)
IF top 2 bytes of stack not within stack limits
THEN #SS(0); FI;
tempEIP ← Pop();
tempEIP ← tempEIP AND 0000FFFFH;
IF tempEIP not within code segment limits
THEN #GP(0); FI;
EIP ← tempEIP;
FI;
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE
IF StackAddressSize = 64
THEN
RSP ← RSP + SRC;
ELSE (* StackAddressSize = 16 *)
SP ← SP + SRC;
FI;
FI;
FI;
FI;
(* Real-address mode or virtual-8086 mode *)
IF ((PE = 0) or (PE = 1 AND VM = 1)) and instruction = far return
THEN
IF OperandSize = 32
THEN
IF top 8 bytes of stack not within stack limits
THEN #SS(0); FI;
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
ELSE (* OperandSize = 16 *)
IF top 4 bytes of stack not within stack limits
THEN #SS(0); FI;
4-554 Vol. 2B
RET—Return from Procedure
INSTRUCTION SET REFERENCE, M-U
tempEIP ← Pop();
tempEIP ← tempEIP AND 0000FFFFH;
IF tempEIP not within code segment limits
THEN #GP(0); FI;
EIP ← tempEIP;
CS ← Pop(); (* 16-bit pop *)
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
SP ← SP + (SRC AND FFFFH);
FI;
FI;
(* Protected mode, not virtual-8086 mode *)
IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 0) and instruction = far return
THEN
IF OperandSize = 32
THEN
IF second doubleword on stack is not within stack limits
THEN #SS(0); FI;
ELSE (* OperandSize = 16 *)
IF second word on stack is not within stack limits
THEN #SS(0); FI;
FI;
IF return code segment selector is NULL
THEN #GP(0); FI;
IF return code segment selector addresses descriptor beyond descriptor table limit
THEN #GP(selector); FI;
Obtain descriptor to which return code segment selector points from descriptor table;
IF return code segment descriptor is not a code segment
THEN #GP(selector); FI;
IF return code segment selector RPL < CPL
THEN #GP(selector); FI;
IF return code segment descriptor is conforming
and return code segment DPL > return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is non-conforming and return code
segment DPL ≠ return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is not present
THEN #NP(selector); FI:
IF return code segment selector RPL > CPL
THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;
ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL;
FI;
FI;
RETURN-SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI;
IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
RET—Return from Procedure
Vol. 2B 4-555
INSTRUCTION SET REFERENCE, M-U
ELSE (* OperandSize = 16 *)
EIP ← Pop();
EIP ← EIP AND 0000FFFFH;
CS ← Pop(); (* 16-bit pop *)
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP ← SP + SRC;
FI;
FI;
RETURN-TO-OUTER-PRIVILEGE-LEVEL:
IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
THEN #SS(0); FI;
Read return segment selector;
IF stack segment selector is NULL
THEN #GP(0); FI;
IF return stack segment selector index is not within its descriptor table limits
THEN #GP(selector); FI;
Read segment descriptor pointed to by return segment selector;
IF stack segment selector RPL ≠ RPL of the return code segment selector
or stack segment is not a writable data segment
or stack segment descriptor DPL ≠ RPL of the return code segment selector
THEN #GP(selector); FI;
IF stack segment not present
THEN #SS(StackSegmentSelector); FI;
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI;
CPL ← ReturnCodeSegmentSelector(RPL);
IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded; segment descriptor loaded *)
CS(RPL) ← CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure’s stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP ← SP + SRC;
FI;
FI;
tempESP ← Pop();
tempSS ← Pop(); (* 32-bit pop, high-order 16 bits discarded; seg. descriptor loaded *)
ESP ← tempESP;
SS ← tempSS;
ELSE (* OperandSize = 16 *)
EIP ← Pop();
4-556 Vol. 2B
RET—Return from Procedure
INSTRUCTION SET REFERENCE, M-U
FI;
EIP ← EIP AND 0000FFFFH;
CS ← Pop(); (* 16-bit pop; segment descriptor loaded *)
CS(RPL) ← CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure’s stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP ← SP + SRC;
FI;
FI;
tempESP ← Pop();
tempSS ← Pop(); (* 16-bit pop; segment descriptor loaded *)
ESP ← tempESP;
SS ← tempSS;
FOR each of segment register (ES, FS, GS, and DS)
DO
IF segment register points to data or non-conforming code segment
and CPL > segment descriptor DPL (* DPL in hidden part of segment register *)
THEN SegmentSelector ← 0; (* Segment selector invalid *)
FI;
OD;
IF instruction has immediate operand
THEN (* Release parameters from calling procedure’s stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP ← SP + SRC;
FI;
FI;
(* IA-32e Mode *)
IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 1) and instruction = far return
THEN
IF OperandSize = 32
THEN
IF second doubleword on stack is not within stack limits
THEN #SS(0); FI;
IF first or second doubleword on stack is not in canonical space
THEN #SS(0); FI;
ELSE
IF OperandSize = 16
THEN
IF second word on stack is not within stack limits
THEN #SS(0); FI;
IF first or second word on stack is not in canonical space
THEN #SS(0); FI;
ELSE (* OperandSize = 64 *)
IF first or second quadword on stack is not in canonical space
RET—Return from Procedure
Vol. 2B 4-557
INSTRUCTION SET REFERENCE, M-U
THEN #SS(0); FI;
FI
FI;
IF return code segment selector is NULL
THEN GP(0); FI;
IF return code segment selector addresses descriptor beyond descriptor table limit
THEN GP(selector); FI;
IF return code segment selector addresses descriptor in non-canonical space
THEN GP(selector); FI;
Obtain descriptor to which return code segment selector points from descriptor table;
IF return code segment descriptor is not a code segment
THEN #GP(selector); FI;
IF return code segment descriptor has L-bit = 1 and D-bit = 1
THEN #GP(selector); FI;
IF return code segment selector RPL < CPL
THEN #GP(selector); FI;
IF return code segment descriptor is conforming
and return code segment DPL > return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is non-conforming
and return code segment DPL ≠ return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is not present
THEN #NP(selector); FI:
IF return code segment selector RPL > CPL
THEN GOTO IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL;
ELSE GOTO IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL;
FI;
FI;
IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI;
IF the return instruction pointer is not within canonical address space
THEN #GP(0); FI;
IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded *)
ELSE
IF OperandSize = 16
THEN
EIP ← Pop();
EIP ← EIP AND 0000FFFFH;
CS ← Pop(); (* 16-bit pop *)
ELSE (* OperandSize = 64 *)
RIP ← Pop();
CS ← Pop(); (* 64-bit pop, high-order 48 bits discarded *)
FI;
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
IF StackAddressSize = 32
THEN
4-558 Vol. 2B
RET—Return from Procedure
INSTRUCTION SET REFERENCE, M-U
ESP ← ESP + SRC;
ELSE
IF StackAddressSize = 16
THEN
SP ← SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP ← RSP + SRC;
FI;
FI;
FI;
IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL:
IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
THEN #SS(0); FI;
IF top (16 + SRC) bytes of stack are not in canonical address space (OperandSize = 32)
or top (8 + SRC) bytes of stack are not in canonical address space (OperandSize = 16)
or top (32 + SRC) bytes of stack are not in canonical address space (OperandSize = 64)
THEN #SS(0); FI;
Read return stack segment selector;
IF stack segment selector is NULL
THEN
IF new CS descriptor L-bit = 0
THEN #GP(selector);
IF stack segment selector RPL = 3
THEN #GP(selector);
FI;
IF return stack segment descriptor is not within descriptor table limits
THEN #GP(selector); FI;
IF return stack segment descriptor is in non-canonical address space
THEN #GP(selector); FI;
Read segment descriptor pointed to by return segment selector;
IF stack segment selector RPL ≠ RPL of the return code segment selector
or stack segment is not a writable data segment
or stack segment descriptor DPL ≠ RPL of the return code segment selector
THEN #GP(selector); FI;
IF stack segment not present
THEN #SS(StackSegmentSelector); FI;
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI:
IF the return instruction pointer is not within canonical address space
THEN #GP(0); FI;
CPL ← ReturnCodeSegmentSelector(RPL);
IF OperandSize = 32
THEN
EIP ← Pop();
CS ← Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
CS(RPL) ← CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure’s stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE
RET—Return from Procedure
Vol. 2B 4-559
INSTRUCTION SET REFERENCE, M-U
IF StackAddressSize = 16
THEN
SP ← SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP ← RSP + SRC;
FI;
FI;
FI;
tempESP ← Pop();
tempSS ← Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
ESP ← tempESP;
SS ← tempSS;
ELSE
IF OperandSize = 16
THEN
EIP ← Pop();
EIP ← EIP AND 0000FFFFH;
CS ← Pop(); (* 16-bit pop; segment descriptor loaded *)
CS(RPL) ← CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure’s stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE
IF StackAddressSize = 16
THEN
SP ← SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP ← RSP + SRC;
FI;
FI;
FI;
tempESP ← Pop();
tempSS ← Pop(); (* 16-bit pop; segment descriptor loaded *)
ESP ← tempESP;
SS ← tempSS;
ELSE (* OperandSize = 64 *)
RIP ← Pop();
CS ← Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. descriptor loaded *)
CS(RPL) ← CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure’s stack *)
RSP ← RSP + SRC;
FI;
tempESP ← Pop();
tempSS ← Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. desc. loaded *)
ESP ← tempESP;
SS ← tempSS;
FI;
FI;
FOR each of segment register (ES, FS, GS, and DS)
DO
4-560 Vol. 2B
RET—Return from Procedure
INSTRUCTION SET REFERENCE, M-U
IF segment register points to data or non-conforming code segment
and CPL > segment descriptor DPL; (* DPL in hidden part of segment register *)
THEN SegmentSelector ← 0; (* SegmentSelector invalid *)
FI;
OD;
IF instruction has immediate operand
THEN (* Release parameters from calling procedure’s stack *)
IF StackAddressSize = 32
THEN
ESP ← ESP + SRC;
ELSE
IF StackAddressSize = 16
THEN
SP ← SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP ← RSP + SRC;
FI;
FI;
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the return code or stack segment selector NULL.
If the return instruction pointer is not within the return code segment limit
#GP(selector)
If the RPL of the return code segment selector is less then the CPL.
If the return code or stack segment selector index is not within its descriptor table limits.
If the return code segment descriptor does not indicate a code segment.
If the return code segment is non-conforming and the segment selector’s DPL is not equal to
the RPL of the code segment’s segment selector
If the return code segment is conforming and the segment selector’s DPL greater than the RPL
of the code segment’s segment selector
If the stack segment is not a writable data segment.
If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
If the stack segment descriptor DPL is not equal to the RPL of the return code segment
selector.
#SS(0)
If the top bytes of stack are not within stack limits.
If the return stack segment is not present.
#NP(selector)
If the return code segment is not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory access occurs when the CPL is 3 and alignment checking is enabled.
Real-Address Mode Exceptions
#GP
If the return instruction pointer is not within the return code segment limit
#SS
If the top bytes of stack are not within stack limits.
Virtual-8086 Mode Exceptions
#GP(0)
If the return instruction pointer is not within the return code segment limit
RET—Return from Procedure
Vol. 2B 4-561
INSTRUCTION SET REFERENCE, M-U
#SS(0)
If the top bytes of stack are not within stack limits.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory access occurs when alignment checking is enabled.
Compatibility Mode Exceptions
Same as 64-bit mode exceptions.
64-Bit Mode Exceptions
#GP(0)
If the return instruction pointer is non-canonical.
If the return instruction pointer is not within the return code segment limit.
If the stack segment selector is NULL going back to compatibility mode.
If the stack segment selector is NULL going back to CPL3 64-bit mode.
If a NULL stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bit mode.
If the return code segment selector is NULL.
#GP(selector)
If the proposed segment descriptor for a code segment does not indicate it is a code segment.
If the proposed new code segment descriptor has both the D-bit and L-bit set.
If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment
selector.
If CPL is greater than the RPL of the code segment selector.
If the DPL of a conforming-code segment is greater than the return code segment selector
RPL.
If a segment selector index is outside its descriptor table limits.
If a segment descriptor memory address is non-canonical.
If the stack segment is not a writable data segment.
If the stack segment descriptor DPL is not equal to the RPL of the return code segment
selector.
If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
#SS(0)
If an attempt to pop a value off the stack violates the SS limit.
If an attempt to pop a value off the stack causes a non-canonical address to be referenced.
#NP(selector)
If the return code or stack segment is not present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
4-562 Vol. 2B
RET—Return from Procedure
INSTRUCTION SET REFERENCE, M-U
RORX — Rotate Right Logical Without Affecting Flags
Opcode/
Instruction
Op/
En
RMI
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI2
VEX.LZ.F2.0F3A.W0 F0 /r ib
RORX r32, r/m32, imm8
VEX.LZ.F2.0F3A.W1 F0 /r ib
RORX r64, r/m64, imm8
RMI
V/N.E.
BMI2
Description
Rotate 32-bit r/m32 right imm8 times without affecting arithmetic
flags.
Rotate 64-bit r/m64 right imm8 times without affecting arithmetic
flags.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Rotates the bits of second operand right by the count value specified in imm8 without affecting arithmetic flags.
The RORX instruction does not read or write the arithmetic flags.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
IF (OperandSize = 32)
y ← imm8 AND 1FH;
DEST ← (SRC >> y) | (SRC << (32-y));
ELSEIF (OperandSize = 64 )
y ← imm8 AND 3FH;
DEST ← (SRC >> y) | (SRC << (64-y));
ENDIF
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
RORX — Rotate Right Logical Without Affecting Flags
Vol. 2B 4-563
INSTRUCTION SET REFERENCE, M-U
ROUNDPD — Round Packed Double Precision Floating-Point Values
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 09 /r ib
ROUNDPD xmm1, xmm2/m128, imm8
RMI
V/V
SSE4_1
Round packed double precision floating-point
values in xmm2/m128 and place the result in
xmm1. The rounding mode is determined by
imm8.
VEX.128.66.0F3A.WIG 09 /r ib
VROUNDPD xmm1, xmm2/m128, imm8
RMI
V/V
AVX
Round packed double-precision floating-point
values in xmm2/m128 and place the result in
xmm1. The rounding mode is determined by
imm8.
VEX.256.66.0F3A.WIG 09 /r ib
VROUNDPD ymm1, ymm2/m256, imm8
RMI
V/V
AVX
Round packed double-precision floating-point
values in ymm2/m256 and place the result in
ymm1. The rounding mode is determined by
imm8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
Description
Round the 2 double-precision floating-point values in the source operand (second operand) using the rounding
mode specified in the immediate operand (third operand) and place the results in the destination operand (first
operand). The rounding process rounds each input floating-point value to an integer value and returns the integer
result as a double-precision floating-point value.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM
register destination are unmodified.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
4-564 Vol. 2B
ROUNDPD — Round Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
8
3 2 1 0
Reserved
P — Precision Mask; 0: normal, 1: inexact
RS — Rounding select; 1: MXCSR.RC, 0: Imm8.RC
RC — Rounding mode
Figure 4-24. Bit Control Fields of Immediate Byte for ROUNDxx Instruction
Table 4-18. Rounding Modes and Encoding of Rounding Control (RC) Field
Rounding
Mode
RC Field
Setting
Description
Round to
nearest (even)
00B
Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is
the even value (i.e., the integer value with the least-significant bit of zero).
Round down
(toward −∞)
01B
Rounded result is closest to but no greater than the infinitely precise result.
Round up
(toward +∞)
10B
Rounded result is closest to but no less than the infinitely precise result.
Round toward 11B
zero (Truncate)
Rounded result is closest to but no greater in absolute value than the infinitely precise result.
Operation
IF (imm[2] = ‘1)
THEN
// rounding mode is determined by MXCSR.RC
DEST[63:0] ConvertDPFPToInteger_M(SRC[63:0]);
DEST[127:64] ConvertDPFPToInteger_M(SRC[127:64]);
ELSE
// rounding mode is determined by IMM8.RC
DEST[63:0] ConvertDPFPToInteger_Imm(SRC[63:0]);
DEST[127:64] ConvertDPFPToInteger_Imm(SRC[127:64]);
FI
ROUNDPD (128-bit Legacy SSE version)
DEST[63:0] RoundToInteger(SRC[63:0]], ROUND_CONTROL)
DEST[127:64] RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[VLMAX-1:128] (Unmodified)
VROUNDPD (VEX.128 encoded version)
DEST[63:0] RoundToInteger(SRC[63:0]], ROUND_CONTROL)
DEST[127:64] RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[VLMAX-1:128] 0
VROUNDPD (VEX.256 encoded version)
DEST[63:0] RoundToInteger(SRC[63:0], ROUND_CONTROL)
DEST[127:64] RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[191:128] RoundToInteger(SRC[191:128]], ROUND_CONTROL)
DEST[255:192] RoundToInteger(SRC[255:192] ], ROUND_CONTROL)
ROUNDPD — Round Packed Double Precision Floating-Point Values
Vol. 2B 4-565
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
__m128 _mm_round_pd(__m128d s1, int iRoundMode);
__m128 _mm_floor_pd(__m128d s1);
__m128 _mm_ceil_pd(__m128d s1)
__m256 _mm256_round_pd(__m256d s1, int iRoundMode);
__m256 _mm256_floor_pd(__m256d s1);
__m256 _mm256_ceil_pd(__m256d s1)
SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = ‘0; if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision exception is not signaled.)
Note that Denormal is not signaled by ROUNDPD.
Other Exceptions
See Exceptions Type 2; additionally
#UD
4-566 Vol. 2B
If VEX.vvvv ≠ 1111B.
ROUNDPD — Round Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
ROUNDPS — Round Packed Single Precision Floating-Point Values
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 08
/r ib
ROUNDPS xmm1, xmm2/m128, imm8
RMI
V/V
SSE4_1
Round packed single precision floating-point
values in xmm2/m128 and place the result in
xmm1. The rounding mode is determined by
imm8.
VEX.128.66.0F3A.WIG 08 /r ib
VROUNDPS xmm1, xmm2/m128, imm8
RMI
V/V
AVX
Round packed single-precision floating-point
values in xmm2/m128 and place the result in
xmm1. The rounding mode is determined by
imm8.
VEX.256.66.0F3A.WIG 08 /r ib
VROUNDPS ymm1, ymm2/m256, imm8
RMI
V/V
AVX
Round packed single-precision floating-point
values in ymm2/m256 and place the result in
ymm1. The rounding mode is determined by
imm8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
Description
Round the 4 single-precision floating-point values in the source operand (second operand) using the rounding
mode specified in the immediate operand (third operand) and place the results in the destination operand (first
operand). The rounding process rounds each input floating-point value to an integer value and returns the integer
result as a single-precision floating-point value.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM
register destination are unmodified.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
ROUNDPS — Round Packed Single Precision Floating-Point Values
Vol. 2B 4-567
INSTRUCTION SET REFERENCE, M-U
Operation
IF (imm[2] = ‘1)
THEN
// rounding mode is determined by MXCSR.RC
DEST[31:0] ConvertSPFPToInteger_M(SRC[31:0]);
DEST[63:32] ConvertSPFPToInteger_M(SRC[63:32]);
DEST[95:64] ConvertSPFPToInteger_M(SRC[95:64]);
DEST[127:96] ConvertSPFPToInteger_M(SRC[127:96]);
ELSE
// rounding mode is determined by IMM8.RC
DEST[31:0] ConvertSPFPToInteger_Imm(SRC[31:0]);
DEST[63:32] ConvertSPFPToInteger_Imm(SRC[63:32]);
DEST[95:64] ConvertSPFPToInteger_Imm(SRC[95:64]);
DEST[127:96] ConvertSPFPToInteger_Imm(SRC[127:96]);
FI;
ROUNDPS(128-bit Legacy SSE version)
DEST[31:0] RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[VLMAX-1:128] (Unmodified)
VROUNDPS (VEX.128 encoded version)
DEST[31:0] RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[VLMAX-1:128] 0
VROUNDPS (VEX.256 encoded version)
DEST[31:0] RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[159:128] RoundToInteger(SRC[159:128]], ROUND_CONTROL)
DEST[191:160] RoundToInteger(SRC[191:160]], ROUND_CONTROL)
DEST[223:192] RoundToInteger(SRC[223:192] ], ROUND_CONTROL)
DEST[255:224] RoundToInteger(SRC[255:224] ], ROUND_CONTROL)
Intel C/C++ Compiler Intrinsic Equivalent
__m128 _mm_round_ps(__m128 s1, int iRoundMode);
__m128 _mm_floor_ps(__m128 s1);
__m128 _mm_ceil_ps(__m128 s1)
__m256 _mm256_round_ps(__m256 s1, int iRoundMode);
__m256 _mm256_floor_ps(__m256 s1);
__m256 _mm256_ceil_ps(__m256 s1)
4-568 Vol. 2B
ROUNDPS — Round Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = ‘0; if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision exception is not signaled.)
Note that Denormal is not signaled by ROUNDPS.
Other Exceptions
See Exceptions Type 2; additionally
#UD
If VEX.vvvv ≠ 1111B.
ROUNDPS — Round Packed Single Precision Floating-Point Values
Vol. 2B 4-569
INSTRUCTION SET REFERENCE, M-U
ROUNDSD — Round Scalar Double Precision Floating-Point Values
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 0B /r ib
ROUNDSD xmm1, xmm2/m64, imm8
RMI
V/V
SSE4_1
Round the low packed double precision
floating-point value in xmm2/m64 and place
the result in xmm1. The rounding mode is
determined by imm8.
VEX.NDS.LIG.66.0F3A.WIG 0B /r ib
VROUNDSD xmm1, xmm2, xmm3/m64, imm8
RVMI V/V
AVX
Round the low packed double precision
floating-point value in xmm3/m64 and place
the result in xmm1. The rounding mode is
determined by imm8. Upper packed double
precision floating-point value (bits[127:64])
from xmm2 is copied to xmm1[127:64].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Round the DP FP value in the lower qword of the source operand (second operand) using the rounding mode specified in the immediate operand (third operand) and place the result in the destination operand (first operand). The
rounding process rounds a double-precision floating-point input to an integer value and returns the integer result
as a double precision floating-point value in the lowest position. The upper double precision floating-point value in
the destination is retained.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX1:64) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Operation
IF (imm[2] = ‘1)
THEN
// rounding mode is determined by MXCSR.RC
DEST[63:0] ConvertDPFPToInteger_M(SRC[63:0]);
ELSE
// rounding mode is determined by IMM8.RC
DEST[63:0] ConvertDPFPToInteger_Imm(SRC[63:0]);
FI;
DEST[127:63] remains unchanged ;
ROUNDSD (128-bit Legacy SSE version)
DEST[63:0] RoundToInteger(SRC[63:0], ROUND_CONTROL)
DEST[VLMAX-1:64] (Unmodified)
4-570 Vol. 2B
ROUNDSD — Round Scalar Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VROUNDSD (VEX.128 encoded version)
DEST[63:0] RoundToInteger(SRC2[63:0], ROUND_CONTROL)
DEST[127:64] SRC1[127:64]
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
ROUNDSD:
__m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode);
__m128d mm_floor_sd(__m128d dst, __m128d s1);
__m128d mm_ceil_sd(__m128d dst, __m128d s1);
SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = ‘0; if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision exception is not signaled.)
Note that Denormal is not signaled by ROUNDSD.
Other Exceptions
See Exceptions Type 3.
ROUNDSD — Round Scalar Double Precision Floating-Point Values
Vol. 2B 4-571
INSTRUCTION SET REFERENCE, M-U
ROUNDSS — Round Scalar Single Precision Floating-Point Values
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
66 0F 3A 0A /r ib
ROUNDSS xmm1, xmm2/m32, imm8
RMI
V/V
SSE4_1
Round the low packed single precision
floating-point value in xmm2/m32 and place
the result in xmm1. The rounding mode is
determined by imm8.
VEX.NDS.LIG.66.0F3A.WIG 0A /r ib
VROUNDSS xmm1, xmm2, xmm3/m32, imm8
RVMI V/V
AVX
Round the low packed single precision
floating-point value in xmm3/m32 and place
the result in xmm1. The rounding mode is
determined by imm8. Also, upper packed
single precision floating-point values
(bits[127:32]) from xmm2 are copied to
xmm1[127:32].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Round the single-precision floating-point value in the lowest dword of the source operand (second operand) using
the rounding mode specified in the immediate operand (third operand) and place the result in the destination
operand (first operand). The rounding process rounds a single-precision floating-point input to an integer value and
returns the result as a single-precision floating-point value in the lowest position. The upper three single-precision
floating-point values in the destination are retained.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Operation
IF (imm[2] = ‘1)
THEN
// rounding mode is determined by MXCSR.RC
DEST[31:0] ConvertSPFPToInteger_M(SRC[31:0]);
ELSE
// rounding mode is determined by IMM8.RC
DEST[31:0] ConvertSPFPToInteger_Imm(SRC[31:0]);
FI;
DEST[127:32] remains unchanged ;
ROUNDSS (128-bit Legacy SSE version)
DEST[31:0] RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[VLMAX-1:32] (Unmodified)
4-572 Vol. 2B
ROUNDSS — Round Scalar Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VROUNDSS (VEX.128 encoded version)
DEST[31:0] RoundToInteger(SRC2[31:0], ROUND_CONTROL)
DEST[127:32] SRC1[127:32]
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
ROUNDSS:
__m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode);
__m128 mm_floor_ss(__m128 dst, __m128 s1);
__m128 mm_ceil_ss(__m128 dst, __m128 s1);
SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = ‘0; if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision exception is not signaled.)
Note that Denormal is not signaled by ROUNDSS.
Other Exceptions
See Exceptions Type 3.
ROUNDSS — Round Scalar Single Precision Floating-Point Values
Vol. 2B 4-573
INSTRUCTION SET REFERENCE, M-U
RSM—Resume from System Management Mode
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AA
RSM
NP
Valid
Valid
Resume operation of interrupted program.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Returns program control from system management mode (SMM) to the application program or operating-system
procedure that was interrupted when the processor received an SMM interrupt. The processor’s state is restored
from the dump created upon entering SMM. If the processor detects invalid state information during state restoration, it enters the shutdown state. The following invalid information can cause a shutdown:
•
•
•
Any reserved bit of CR4 is set to 1.
Any illegal combination of bits in CR0, such as (PG=1 and PE=0) or (NW=1 and CD=0).
(Intel Pentium and Intel486™ processors only.) The value stored in the state dump base field is not a 32-KByte
aligned address.
The contents of the model-specific registers are not affected by a return from SMM.
The SMM state map used by RSM supports resuming processor context for non-64-bit modes and 64-bit mode.
See Chapter 34, “System Management Mode,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C, for more information about SMM and the behavior of the RSM instruction.
Operation
ReturnFromSMM;
IF (IA-32e mode supported) or (CPUID DisplayFamily_DisplayModel = 06H_0CH )
THEN
ProcessorState ← Restore(SMMDump(IA-32e SMM STATE MAP));
Else
ProcessorState ← Restore(SMMDump(Non-32-Bit-Mode SMM STATE MAP));
FI
Flags Affected
All.
Protected Mode Exceptions
#UD
If an attempt is made to execute this instruction when the processor is not in SMM.
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
4-574 Vol. 2B
RSM—Resume from System Management Mode
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
Same exceptions as in protected mode.
RSM—Resume from System Management Mode
Vol. 2B 4-575
INSTRUCTION SET REFERENCE, M-U
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point
Values
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 52 /r
RM
V/V
SSE
Computes the approximate reciprocals of the
square roots of the packed single-precision
floating-point values in xmm2/m128 and
stores the results in xmm1.
RM
V/V
AVX
Computes the approximate reciprocals of the
square roots of packed single-precision values
in xmm2/mem and stores the results in xmm1.
RM
V/V
AVX
Computes the approximate reciprocals of the
square roots of packed single-precision values
in ymm2/mem and stores the results in ymm1.
RSQRTPS xmm1, xmm2/m128
VEX.128.0F.WIG 52 /r
VRSQRTPS xmm1, xmm2/m128
VEX.256.0F.WIG 52 /r
VRSQRTPS ymm1, ymm2/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Performs a SIMD computation of the approximate reciprocals of the square roots of the four packed single-precision floating-point values in the source operand (second operand) and stores the packed single-precision floatingpoint results in the destination operand. The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. See Figure 10-5 in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for an illustration of a SIMD single-precision floating-point operation.
The relative error for this approximation is:
|Relative Error| ≤ 1.5 ∗ 2−12
The RSQRTPS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is
a 0.0, an ∞ of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same
sign). When a source value is a negative value (other than −0.0), a floating-point indefinite is returned. When a
source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
4-576 Vol. 2B
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
RSQRTPS (128-bit Legacy SSE version)
DEST[31:0] APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[VLMAX-1:128] (Unmodified)
VRSQRTPS (VEX.128 encoded version)
DEST[31:0] APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[VLMAX-1:128] 0
VRSQRTPS (VEX.256 encoded version)
DEST[31:0] APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[159:128] APPROXIMATE(1/SQRT(SRC2[159:128]))
DEST[191:160] APPROXIMATE(1/SQRT(SRC2[191:160]))
DEST[223:192] APPROXIMATE(1/SQRT(SRC2[223:192]))
DEST[255:224] APPROXIMATE(1/SQRT(SRC2[255:224]))
Intel C/C++ Compiler Intrinsic Equivalent
RSQRTPS:
__m128 _mm_rsqrt_ps(__m128 a)
RSQRTPS:
__m256 _mm256_rsqrt_ps (__m256 a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.vvvv ≠ 1111B.
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values
Vol. 2B 4-577
INSTRUCTION SET REFERENCE, M-U
RSQRTSS—Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
F3 0F 52 /r
RM
V/V
SSE
Computes the approximate reciprocal of the
square root of the low single-precision
floating-point value in xmm2/m32 and stores
the results in xmm1.
RVM V/V
AVX
Computes the approximate reciprocal of the
square root of the low single precision
floating-point value in xmm3/m32 and stores
the results in xmm1. Also, upper single
precision floating-point values (bits[127:32])
from xmm2 are copied to xmm1[127:32].
RSQRTSS xmm1, xmm2/m32
VEX.NDS.LIG.F3.0F.WIG 52 /r
VRSQRTSS xmm1, xmm2, xmm3/m32
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Computes an approximate reciprocal of the square root of the low single-precision floating-point value in the
source operand (second operand) stores the single-precision floating-point result in the destination operand. The
source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register.
The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a scalar single-precision
floating-point operation.
The relative error for this approximation is:
|Relative Error| ≤ 1.5 ∗ 2−12
The RSQRTSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is
a 0.0, an ∞ of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same
sign). When a source value is a negative value (other than −0.0), a floating-point indefinite is returned. When a
source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Operation
RSQRTSS (128-bit Legacy SSE version)
DEST[31:0] APPROXIMATE(1/SQRT(SRC2[31:0]))
DEST[VLMAX-1:32] (Unmodified)
VRSQRTSS (VEX.128 encoded version)
DEST[31:0] APPROXIMATE(1/SQRT(SRC2[31:0]))
DEST[127:32] SRC1[127:32]
DEST[VLMAX-1:128] 0
4-578 Vol. 2B
RSQRTSS—Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
RSQRTSS:
__m128 _mm_rsqrt_ss(__m128 a)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 5.
RSQRTSS—Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value
Vol. 2B 4-579
INSTRUCTION SET REFERENCE, M-U
SAHF—Store AH into Flags
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
9E
SAHF
NP
Invalid*
Valid
Loads SF, ZF, AF, PF, and CF from AH into
EFLAGS register.
NOTES:
* Valid in specific steppings. See Description section.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH
register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved
bits (1, 3, and 5) in the EFLAGS register remain as shown in the “Operation” section below.
This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only
if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.
Operation
IF IA-64 Mode
THEN
IF CPUID.80000001H.ECX[0] = 1;
THEN
RFLAGS(SF:ZF:0:AF:0:PF:1:CF) ← AH;
ELSE
#UD;
FI
ELSE
EFLAGS(SF:ZF:0:AF:0:PF:1:CF) ← AH;
FI;
Flags Affected
The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register
are unaffected, with the values remaining 1, 0, and 0, respectively.
Protected Mode Exceptions
None.
Real-Address Mode Exceptions
None.
Virtual-8086 Mode Exceptions
None.
Compatibility Mode Exceptions
None.
4-580 Vol. 2B
SAHF—Store AH into Flags
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#UD
If CPUID.80000001H.ECX[0] = 0.
If the LOCK prefix is used.
SAHF—Store AH into Flags
Vol. 2B 4-581
INSTRUCTION SET REFERENCE, M-U
SAL/SAR/SHL/SHR—Shift
Opcode***
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
D0 /4
SAL r/m8, 1
M1
Valid
Valid
Multiply r/m8 by 2, once.
REX + D0 /4
SAL r/m8**, 1
M1
Valid
N.E.
Multiply r/m8 by 2, once.
D2 /4
SAL r/m8, CL
MC
Valid
Valid
Multiply r/m8 by 2, CL times.
REX + D2 /4
SAL r/m8**, CL
MC
Valid
N.E.
Multiply r/m8 by 2, CL times.
C0 /4 ib
SAL r/m8, imm8
MI
Valid
Valid
Multiply r/m8 by 2, imm8 times.
REX + C0 /4 ib
SAL r/m8**, imm8
MI
Valid
N.E.
Multiply r/m8 by 2, imm8 times.
D1 /4
SAL r/m16, 1
M1
Valid
Valid
Multiply r/m16 by 2, once.
D3 /4
SAL r/m16, CL
MC
Valid
Valid
Multiply r/m16 by 2, CL times.
C1 /4 ib
SAL r/m16, imm8
MI
Valid
Valid
Multiply r/m16 by 2, imm8 times.
D1 /4
SAL r/m32, 1
M1
Valid
Valid
Multiply r/m32 by 2, once.
REX.W + D1 /4
SAL r/m64, 1
M1
Valid
N.E.
Multiply r/m64 by 2, once.
D3 /4
SAL r/m32, CL
MC
Valid
Valid
Multiply r/m32 by 2, CL times.
REX.W + D3 /4
SAL r/m64, CL
MC
Valid
N.E.
Multiply r/m64 by 2, CL times.
C1 /4 ib
SAL r/m32, imm8
MI
Valid
Valid
Multiply r/m32 by 2, imm8 times.
REX.W + C1 /4 ib
SAL r/m64, imm8
MI
Valid
N.E.
Multiply r/m64 by 2, imm8 times.
D0 /7
SAR r/m8, 1
M1
Valid
Valid
Signed divide* r/m8 by 2, once.
REX + D0 /7
SAR r/m8**, 1
M1
Valid
N.E.
Signed divide* r/m8 by 2, once.
D2 /7
SAR r/m8, CL
MC
Valid
Valid
Signed divide* r/m8 by 2, CL times.
REX + D2 /7
SAR r/m8**, CL
MC
Valid
N.E.
Signed divide* r/m8 by 2, CL times.
C0 /7 ib
SAR r/m8, imm8
MI
Valid
Valid
Signed divide* r/m8 by 2, imm8 time.
REX + C0 /7 ib
SAR r/m8**, imm8
MI
Valid
N.E.
Signed divide* r/m8 by 2, imm8 times.
D1 /7
SAR r/m16,1
M1
Valid
Valid
Signed divide* r/m16 by 2, once.
D3 /7
SAR r/m16, CL
MC
Valid
Valid
Signed divide* r/m16 by 2, CL times.
C1 /7 ib
SAR r/m16, imm8
MI
Valid
Valid
Signed divide* r/m16 by 2, imm8 times.
D1 /7
SAR r/m32, 1
M1
Valid
Valid
Signed divide* r/m32 by 2, once.
REX.W + D1 /7
SAR r/m64, 1
M1
Valid
N.E.
Signed divide* r/m64 by 2, once.
D3 /7
SAR r/m32, CL
MC
Valid
Valid
Signed divide* r/m32 by 2, CL times.
REX.W + D3 /7
SAR r/m64, CL
MC
Valid
N.E.
Signed divide* r/m64 by 2, CL times.
C1 /7 ib
SAR r/m32, imm8
MI
Valid
Valid
Signed divide* r/m32 by 2, imm8 times.
REX.W + C1 /7 ib
SAR r/m64, imm8
MI
Valid
N.E.
Signed divide* r/m64 by 2, imm8 times
D0 /4
SHL r/m8, 1
M1
Valid
Valid
Multiply r/m8 by 2, once.
REX + D0 /4
SHL r/m8**, 1
M1
Valid
N.E.
Multiply r/m8 by 2, once.
D2 /4
SHL r/m8, CL
MC
Valid
Valid
Multiply r/m8 by 2, CL times.
REX + D2 /4
SHL r/m8**, CL
MC
Valid
N.E.
Multiply r/m8 by 2, CL times.
C0 /4 ib
SHL r/m8, imm8
MI
Valid
Valid
Multiply r/m8 by 2, imm8 times.
REX + C0 /4 ib
SHL r/m8**, imm8
MI
Valid
N.E.
Multiply r/m8 by 2, imm8 times.
D1 /4
SHL r/m16,1
M1
Valid
Valid
Multiply r/m16 by 2, once.
D3 /4
SHL r/m16, CL
MC
Valid
Valid
Multiply r/m16 by 2, CL times.
C1 /4 ib
SHL r/m16, imm8
MI
Valid
Valid
Multiply r/m16 by 2, imm8 times.
D1 /4
SHL r/m32,1
M1
Valid
Valid
Multiply r/m32 by 2, once.
4-582 Vol. 2B
SAL/SAR/SHL/SHR—Shift
INSTRUCTION SET REFERENCE, M-U
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
REX.W + D1 /4
SHL r/m64,1
M1
Valid
N.E.
Multiply r/m64 by 2, once.
D3 /4
SHL r/m32, CL
MC
Valid
Valid
Multiply r/m32 by 2, CL times.
REX.W + D3 /4
SHL r/m64, CL
MC
Valid
N.E.
Multiply r/m64 by 2, CL times.
C1 /4 ib
SHL r/m32, imm8
MI
Valid
Valid
Multiply r/m32 by 2, imm8 times.
REX.W + C1 /4 ib
SHL r/m64, imm8
MI
Valid
N.E.
Multiply r/m64 by 2, imm8 times.
D0 /5
SHR r/m8,1
M1
Valid
Valid
Unsigned divide r/m8 by 2, once.
REX + D0 /5
SHR r/m8**, 1
M1
Valid
N.E.
Unsigned divide r/m8 by 2, once.
D2 /5
SHR r/m8, CL
MC
Valid
Valid
Unsigned divide r/m8 by 2, CL times.
REX + D2 /5
SHR r/m8**, CL
MC
Valid
N.E.
Unsigned divide r/m8 by 2, CL times.
C0 /5 ib
SHR r/m8, imm8
MI
Valid
Valid
Unsigned divide r/m8 by 2, imm8 times.
REX + C0 /5 ib
SHR r/m8**, imm8
MI
Valid
N.E.
Unsigned divide r/m8 by 2, imm8 times.
D1 /5
SHR r/m16, 1
M1
Valid
Valid
Unsigned divide r/m16 by 2, once.
D3 /5
SHR r/m16, CL
MC
Valid
Valid
Unsigned divide r/m16 by 2, CL times
C1 /5 ib
SHR r/m16, imm8
MI
Valid
Valid
Unsigned divide r/m16 by 2, imm8 times.
D1 /5
SHR r/m32, 1
M1
Valid
Valid
Unsigned divide r/m32 by 2, once.
REX.W + D1 /5
SHR r/m64, 1
M1
Valid
N.E.
Unsigned divide r/m64 by 2, once.
D3 /5
SHR r/m32, CL
MC
Valid
Valid
Unsigned divide r/m32 by 2, CL times.
REX.W + D3 /5
SHR r/m64, CL
MC
Valid
N.E.
Unsigned divide r/m64 by 2, CL times.
C1 /5 ib
SHR r/m32, imm8
MI
Valid
Valid
Unsigned divide r/m32 by 2, imm8 times.
REX.W + C1 /5 ib
SHR r/m64, imm8
MI
Valid
N.E.
Unsigned divide r/m64 by 2, imm8 times.
NOTES:
* Not the same form of division as IDIV; rounding is toward negative infinity.
** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
***See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M1
ModRM:r/m (r, w)
1
NA
NA
MC
ModRM:r/m (r, w)
CL
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
Description
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF
flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination
operand.
The destination operand can be a register or a memory location. The count operand can be an immediate value or
the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is
limited to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding is provided for a count of 1.
The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the
bits in the destination operand to the left (toward more significant bit locations). For each shift count, the most
significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see
Figure 7-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
SAL/SAR/SHL/SHR—Shift
Vol. 2B 4-583
INSTRUCTION SET REFERENCE, M-U
The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to
the right (toward less significant bit locations). For each shift count, the least significant bit of the destination
operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction
type. The SHR instruction clears the most significant bit (see Figure 7-8 in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond
to the sign (most significant bit) of the original value in the destination operand. In effect, the SAR instruction fills
the empty bit position’s shifted value with the sign of the unshifted value (see Figure 7-9 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1).
The SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination
operand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides
the value by 2.
Using the SAR instruction to perform a division operation does not produce the same result as the IDIV instruction.
The quotient from the IDIV instruction is rounded toward zero, whereas the “quotient” of the SAR instruction is
rounded toward negative infinity. This difference is apparent only for negative numbers. For example, when the
IDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to
shift -9 right by two bits, the result is -3 and the “remainder” is +3; however, the SAR instruction stores only the
most significant bit of the remainder (in the CF flag).
The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is set to 0 if the most-significant bit of the
result is the same as the CF flag (that is, the top two bits of the original operand were the same); otherwise, it is
set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set
to the most-significant bit of the original operand.
In 64-bit mode, the instruction’s default operation size is 32 bits and the mask width for CL is 5 bits. Using a REX
prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W
promotes operation to 64-bits and sets the mask width for CL to 6 bits. See the summary chart at the beginning of
this section for encoding data and limits.
IA-32 Architecture Compatibility
The 8086 does not mask the shift count. However, all other IA-32 processors (starting with the Intel 286 processor)
do mask the shift count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes
(including the virtual-8086 mode) to reduce the maximum execution time of the instructions.
Operation
IF 64-Bit Mode and using REX.W
THEN
countMASK ← 3FH;
ELSE
countMASK ← 1FH;
FI
tempCOUNT ← (COUNT AND countMASK);
tempDEST ← DEST;
WHILE (tempCOUNT ≠ 0)
DO
IF instruction is SAL or SHL
THEN
CF ← MSB(DEST);
ELSE (* Instruction is SAR or SHR *)
CF ← LSB(DEST);
FI;
IF instruction is SAL or SHL
THEN
DEST ← DEST ∗ 2;
ELSE
IF instruction is SAR
4-584 Vol. 2B
SAL/SAR/SHL/SHR—Shift
INSTRUCTION SET REFERENCE, M-U
THEN
DEST ← DEST / 2; (* Signed divide, rounding toward negative infinity *)
ELSE (* Instruction is SHR *)
DEST ← DEST / 2 ; (* Unsigned divide *)
OD;
FI;
FI;
tempCOUNT ← tempCOUNT – 1;
(* Determine overflow for the various instructions *)
IF (COUNT and countMASK) = 1
THEN
IF instruction is SAL or SHL
THEN
OF ← MSB(DEST) XOR CF;
ELSE
IF instruction is SAR
THEN
OF ← 0;
ELSE (* Instruction is SHR *)
OF ← MSB(tempDEST);
FI;
FI;
ELSE IF (COUNT AND countMASK) = 0
THEN
All flags unchanged;
ELSE (* COUNT not 1 or 0 *)
OF ← undefined;
FI;
FI;
Flags Affected
The CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR
instructions where the count is greater than or equal to the size (in bits) of the destination operand. The OF flag is
affected only for 1-bit shifts (see “Description” above); otherwise, it is undefined. The SF, ZF, and PF flags are set
according to the result. If the count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
SAL/SAR/SHL/SHR—Shift
Vol. 2B 4-585
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
4-586 Vol. 2B
SAL/SAR/SHL/SHR—Shift
INSTRUCTION SET REFERENCE, M-U
SARX/SHLX/SHRX — Shift Without Affecting Flags
Opcode/
Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI2
VEX.NDS.LZ.F3.0F38.W0 F7 /r
SARX r32a, r/m32, r32b
VEX.NDS.LZ.66.0F38.W0 F7 /r
SHLX r32a, r/m32, r32b
VEX.NDS.LZ.F2.0F38.W0 F7 /r
SHRX r32a, r/m32, r32b
VEX.NDS.LZ.F3.0F38.W1 F7 /r
SARX r64a, r/m64, r64b
VEX.NDS.LZ.66.0F38.W1 F7 /r
SHLX r64a, r/m64, r64b
VEX.NDS.LZ.F2.0F38.W1 F7 /r
SHRX r64a, r/m64, r64b
Description
Shift r/m32 arithmetically right with count specified in r32b.
RMV
V/V
BMI2
Shift r/m32 logically left with count specified in r32b.
RMV
V/V
BMI2
Shift r/m32 logically right with count specified in r32b.
RMV
V/N.E.
BMI2
Shift r/m64 arithmetically right with count specified in r64b.
RMV
V/N.E.
BMI2
Shift r/m64 logically left with count specified in r64b.
RMV
V/N.E.
BMI2
Shift r/m64 logically right with count specified in r64b.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (w)
ModRM:r/m (r)
VEX.vvvv (r)
NA
Description
Shifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in
the second source operand (the third operand). The result is written to the destination operand (the first operand).
The shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand
to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit)
while shifting.
The logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit locations).
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.
SARX,SHRX, and SHLX instructions do not update flags.
Operation
TEMP ← SRC1;
IF VEX.W1 and CS.L = 1
THEN
countMASK ←3FH;
ELSE
countMASK ←1FH;
FI
COUNT ← (SRC2 AND countMASK)
DEST[OperandSize -1] = TEMP[OperandSize -1];
DO WHILE (COUNT ≠ 0)
IF instruction is SHLX
THEN
DEST[] ← DEST *2;
SARX/SHLX/SHRX — Shift Without Affecting Flags
Vol. 2B 4-587
INSTRUCTION SET REFERENCE, M-U
ELSE IF instruction is SHRX
THEN
DEST[] ← DEST /2; //unsigned divide
ELSE
// SARX
DEST[] ← DEST /2; // signed divide, round toward negative infinity
OD
FI;
COUNT ← COUNT - 1;
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
4-588 Vol. 2B
If VEX.W = 1.
SARX/SHLX/SHRX — Shift Without Affecting Flags
INSTRUCTION SET REFERENCE, M-U
SBB—Integer Subtraction with Borrow
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
1C ib
SBB AL, imm8
I
Valid
Valid
Subtract with borrow imm8 from AL.
1D iw
SBB AX, imm16
I
Valid
Valid
Subtract with borrow imm16 from AX.
1D id
SBB EAX, imm32
I
Valid
Valid
Subtract with borrow imm32 from EAX.
REX.W + 1D id
SBB RAX, imm32
I
Valid
N.E.
Subtract with borrow sign-extended imm.32
to 64-bits from RAX.
80 /3 ib
SBB r/m8, imm8
MI
Valid
Valid
Subtract with borrow imm8 from r/m8.
REX + 80 /3 ib
SBB r/m8*, imm8
MI
Valid
N.E.
Subtract with borrow imm8 from r/m8.
81 /3 iw
SBB r/m16, imm16
MI
Valid
Valid
Subtract with borrow imm16 from r/m16.
81 /3 id
SBB r/m32, imm32
MI
Valid
Valid
Subtract with borrow imm32 from r/m32.
REX.W + 81 /3 id
SBB r/m64, imm32
MI
Valid
N.E.
Subtract with borrow sign-extended imm32 to
64-bits from r/m64.
83 /3 ib
SBB r/m16, imm8
MI
Valid
Valid
Subtract with borrow sign-extended imm8
from r/m16.
83 /3 ib
SBB r/m32, imm8
MI
Valid
Valid
Subtract with borrow sign-extended imm8
from r/m32.
REX.W + 83 /3 ib
SBB r/m64, imm8
MI
Valid
N.E.
Subtract with borrow sign-extended imm8
from r/m64.
18 /r
SBB r/m8, r8
MR
Valid
Valid
Subtract with borrow r8 from r/m8.
REX + 18 /r
SBB r/m8*, r8
MR
Valid
N.E.
Subtract with borrow r8 from r/m8.
19 /r
SBB r/m16, r16
MR
Valid
Valid
Subtract with borrow r16 from r/m16.
19 /r
SBB r/m32, r32
MR
Valid
Valid
Subtract with borrow r32 from r/m32.
REX.W + 19 /r
SBB r/m64, r64
MR
Valid
N.E.
Subtract with borrow r64 from r/m64.
1A /r
SBB r8, r/m8
RM
Valid
Valid
Subtract with borrow r/m8 from r8.
REX + 1A /r
SBB r8*, r/m8*
RM
Valid
N.E.
Subtract with borrow r/m8 from r8.
1B /r
SBB r16, r/m16
RM
Valid
Valid
Subtract with borrow r/m16 from r16.
1B /r
SBB r32, r/m32
RM
Valid
Valid
Subtract with borrow r/m32 from r32.
REX.W + 1B /r
SBB r64, r/m64
RM
Valid
N.E.
Subtract with borrow r/m64 from r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
I
AL/AX/EAX/RAX
imm8/16/32
NA
NA
MI
ModRM:r/m (w)
imm8/16/32
NA
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
SBB—Integer Subtraction with Borrow
Vol. 2B 4-589
INSTRUCTION SET REFERENCE, M-U
Description
Adds the source operand (second operand) and the carry (CF) flag, and subtracts the result from the destination
operand (first operand). The result of the subtraction is stored in the destination operand. The destination operand
can be a register or a memory location; the source operand can be an immediate, a register, or a memory location.
(However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a borrow
from a previous subtraction.
When an immediate value is used as an operand, it is sign-extended to the length of the destination operand
format.
The SBB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates
the result for both data types and sets the OF and CF flags to indicate a borrow in the signed or unsigned result,
respectively. The SF flag indicates the sign of the signed result.
The SBB instruction is usually executed as part of a multibyte or multiword subtraction in which a SUB instruction
is followed by a SBB instruction.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← (DEST – (SRC + CF));
Intel C/C++ Compiler Intrinsic Equivalent
SBB:
extern unsigned char _subborrow_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *diff_out);
SBB:
extern unsigned char _subborrow_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short
*diff_out);
SBB:
extern unsigned char _subborrow_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *diff_out);
SBB:
extern unsigned char _subborrow_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned
__int64 *diff_out);
Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
4-590 Vol. 2B
SBB—Integer Subtraction with Borrow
INSTRUCTION SET REFERENCE, M-U
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
SBB—Integer Subtraction with Borrow
Vol. 2B 4-591
INSTRUCTION SET REFERENCE, M-U
SCAS/SCASB/SCASW/SCASD—Scan String
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
AE
SCAS m8
NP
Valid
Valid
Compare AL with byte at ES:(E)DI or RDI, then
set status flags.*
AF
SCAS m16
NP
Valid
Valid
Compare AX with word at ES:(E)DI or RDI, then
set status flags.*
AF
SCAS m32
NP
Valid
Valid
Compare EAX with doubleword at ES(E)DI or
RDI then set status flags.*
REX.W + AF
SCAS m64
NP
Valid
N.E.
Compare RAX with quadword at RDI or EDI
then set status flags.
AE
SCASB
NP
Valid
Valid
Compare AL with byte at ES:(E)DI or RDI then
set status flags.*
AF
SCASW
NP
Valid
Valid
Compare AX with word at ES:(E)DI or RDI then
set status flags.*
AF
SCASD
NP
Valid
Valid
Compare EAX with doubleword at ES:(E)DI or
RDI then set status flags.*
REX.W + AF
SCASQ
NP
Valid
N.E.
Compare RAX with quadword at RDI or EDI
then set status flags.
NOTES:
* In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit mode, only 32-bit (EDI) and 16-bit (DI)
address sizes are supported.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
In non-64-bit modes and in default 64-bit mode: this instruction compares a byte, word, doubleword or quadword
specified using a memory operand with the value in AL, AX, or EAX. It then sets status flags in EFLAGS recording
the results. The memory operand address is read from ES:(E)DI register (depending on the address-size attribute
of the instruction and the current operational mode). Note that ES cannot be overridden with a segment override
prefix.
At the assembly-code level, two forms of this instruction are allowed. The explicit-operand form and the no-operands form. The explicit-operand form (specified using the SCAS mnemonic) allows a memory operand to be specified explicitly. The memory operand must be a symbol that indicates the size and location of the operand value. The
register operand is then automatically selected to match the size of the memory operand (AL register for byte
comparisons, AX for word comparisons, EAX for doubleword comparisons). The explicit-operand form is provided
to allow documentation. Note that the documentation provided by this form can be misleading. That is, the
memory operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword) but it
does not have to specify the correct location. The location is always specified by ES:(E)DI.
The no-operands form of the instruction uses a short form of SCAS. Again, ES:(E)DI is assumed to be the memory
operand and AL, AX, or EAX is assumed to be the register operand. The size of operands is selected by the
mnemonic: SCASB (byte comparison), SCASW (word comparison), or SCASD (doubleword comparison).
After the comparison, the (E)DI register is incremented or decremented automatically according to the setting of
the DF flag in the EFLAGS register. If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI
register is decremented. The register is incremented or decremented by 1 for byte operations, by 2 for word operations, and by 4 for doubleword operations.
SCAS, SCASB, SCASW, SCASD, and SCASQ can be preceded by the REP prefix for block comparisons of ECX bytes,
words, doublewords, or quadwords. Often, however, these instructions will be used in a LOOP construct that takes
4-592 Vol. 2B
SCAS/SCASB/SCASW/SCASD—Scan String
INSTRUCTION SET REFERENCE, M-U
some action based on the setting of status flags. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation
Prefix” in this chapter for a description of the REP prefix.
In 64-bit mode, the instruction’s default address size is 64-bits, 32-bit address size is supported using the prefix
67H. Using a REX prefix in the form of REX.W promotes operation on doubleword operand to 64 bits. The 64-bit nooperand mnemonic is SCASQ. Address of the memory operand is specified in either RDI or EDI, and
AL/AX/EAX/RAX may be used as the register operand. After a comparison, the destination register is incremented
or decremented by the current operand size (depending on the value of the DF flag). See the summary chart at the
beginning of this section for encoding data and limits.
Operation
Non-64-bit Mode:
IF (Byte comparison)
THEN
temp ← AL − SRC;
SetStatusFlags(temp);
THEN IF DF = 0
THEN (E)DI ← (E)DI + 1;
ELSE (E)DI ← (E)DI – 1; FI;
ELSE IF (Word comparison)
THEN
temp ← AX − SRC;
SetStatusFlags(temp);
IF DF = 0
THEN (E)DI ← (E)DI + 2;
ELSE (E)DI ← (E)DI – 2; FI;
FI;
ELSE IF (Doubleword comparison)
THEN
temp ← EAX – SRC;
SetStatusFlags(temp);
IF DF = 0
THEN (E)DI ← (E)DI + 4;
ELSE (E)DI ← (E)DI – 4; FI;
FI;
FI;
64-bit Mode:
IF (Byte cmparison)
THEN
temp ← AL − SRC;
SetStatusFlags(temp);
THEN IF DF = 0
THEN (R|E)DI ← (R|E)DI + 1;
ELSE (R|E)DI ← (R|E)DI – 1; FI;
ELSE IF (Word comparison)
THEN
temp ← AX − SRC;
SetStatusFlags(temp);
IF DF = 0
THEN (R|E)DI ← (R|E)DI + 2;
ELSE (R|E)DI ← (R|E)DI – 2; FI;
FI;
SCAS/SCASB/SCASW/SCASD—Scan String
Vol. 2B 4-593
INSTRUCTION SET REFERENCE, M-U
ELSE IF (Doubleword comparison)
THEN
temp ← EAX – SRC;
SetStatusFlags(temp);
IF DF = 0
THEN (R|E)DI ← (R|E)DI + 4;
ELSE (R|E)DI ← (R|E)DI – 4; FI;
FI;
ELSE IF (Quadword comparison using REX.W )
THEN
temp ← RAX − SRC;
SetStatusFlags(temp);
IF DF = 0
THEN (R|E)DI ← (R|E)DI + 8;
ELSE (R|E)DI ← (R|E)DI – 8;
FI;
FI;
F
Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result of the comparison.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the limit of the ES segment.
If the ES register contains a NULL segment selector.
If an illegal memory operand effective address in the ES segment is given.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
4-594 Vol. 2B
SCAS/SCASB/SCASW/SCASD—Scan String
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
SCAS/SCASB/SCASW/SCASD—Scan String
Vol. 2B 4-595
INSTRUCTION SET REFERENCE, M-U
SETcc—Set Byte on Condition
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 97
SETA r/m8
M
Valid
Valid
Set byte if above (CF=0 and ZF=0).
REX + 0F 97
SETA r/m8*
M
Valid
N.E.
Set byte if above (CF=0 and ZF=0).
0F 93
SETAE r/m8
M
Valid
Valid
Set byte if above or equal (CF=0).
REX + 0F 93
SETAE r/m8*
M
Valid
N.E.
Set byte if above or equal (CF=0).
0F 92
SETB r/m8
M
Valid
Valid
Set byte if below (CF=1).
REX + 0F 92
SETB r/m8*
M
Valid
N.E.
Set byte if below (CF=1).
0F 96
SETBE r/m8
M
Valid
Valid
Set byte if below or equal (CF=1 or ZF=1).
REX + 0F 96
SETBE r/m8*
M
Valid
N.E.
Set byte if below or equal (CF=1 or ZF=1).
0F 92
SETC r/m8
M
Valid
Valid
Set byte if carry (CF=1).
REX + 0F 92
SETC r/m8*
M
Valid
N.E.
Set byte if carry (CF=1).
0F 94
SETE r/m8
M
Valid
Valid
Set byte if equal (ZF=1).
REX + 0F 94
SETE r/m8*
M
Valid
N.E.
Set byte if equal (ZF=1).
0F 9F
SETG r/m8
M
Valid
Valid
Set byte if greater (ZF=0 and SF=OF).
REX + 0F 9F
SETG r/m8*
M
Valid
N.E.
Set byte if greater (ZF=0 and SF=OF).
0F 9D
SETGE r/m8
M
Valid
Valid
Set byte if greater or equal (SF=OF).
REX + 0F 9D
SETGE r/m8*
M
Valid
N.E.
Set byte if greater or equal (SF=OF).
0F 9C
SETL r/m8
M
Valid
Valid
Set byte if less (SF≠ OF).
REX + 0F 9C
SETL r/m8*
M
Valid
N.E.
Set byte if less (SF≠ OF).
0F 9E
SETLE r/m8
M
Valid
Valid
Set byte if less or equal (ZF=1 or SF≠ OF).
REX + 0F 9E
SETLE r/m8*
M
Valid
N.E.
Set byte if less or equal (ZF=1 or SF≠ OF).
0F 96
SETNA r/m8
M
Valid
Valid
Set byte if not above (CF=1 or ZF=1).
REX + 0F 96
SETNA r/m8*
M
Valid
N.E.
Set byte if not above (CF=1 or ZF=1).
0F 92
SETNAE r/m8
M
Valid
Valid
Set byte if not above or equal (CF=1).
REX + 0F 92
SETNAE r/m8*
M
Valid
N.E.
Set byte if not above or equal (CF=1).
0F 93
SETNB r/m8
M
Valid
Valid
Set byte if not below (CF=0).
REX + 0F 93
SETNB r/m8*
M
Valid
N.E.
Set byte if not below (CF=0).
0F 97
SETNBE r/m8
M
Valid
Valid
Set byte if not below or equal (CF=0 and
ZF=0).
REX + 0F 97
SETNBE r/m8*
M
Valid
N.E.
Set byte if not below or equal (CF=0 and
ZF=0).
0F 93
SETNC r/m8
M
Valid
Valid
Set byte if not carry (CF=0).
REX + 0F 93
SETNC r/m8*
M
Valid
N.E.
Set byte if not carry (CF=0).
0F 95
SETNE r/m8
M
Valid
Valid
Set byte if not equal (ZF=0).
REX + 0F 95
SETNE r/m8*
M
Valid
N.E.
Set byte if not equal (ZF=0).
0F 9E
SETNG r/m8
M
Valid
Valid
Set byte if not greater (ZF=1 or SF≠ OF)
REX + 0F 9E
SETNG r/m8*
M
Valid
N.E.
Set byte if not greater (ZF=1 or SF≠ OF).
0F 9C
SETNGE r/m8
M
Valid
Valid
Set byte if not greater or equal (SF≠ OF).
REX + 0F 9C
SETNGE r/m8*
M
Valid
N.E.
Set byte if not greater or equal (SF≠ OF).
0F 9D
SETNL r/m8
M
Valid
Valid
Set byte if not less (SF=OF).
REX + 0F 9D
SETNL r/m8*
M
Valid
N.E.
Set byte if not less (SF=OF).
0F 9F
SETNLE r/m8
M
Valid
Valid
Set byte if not less or equal (ZF=0 and SF=OF).
4-596 Vol. 2B
SETcc—Set Byte on Condition
INSTRUCTION SET REFERENCE, M-U
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
REX + 0F 9F
SETNLE r/m8*
M
Valid
N.E.
Set byte if not less or equal (ZF=0 and SF=OF).
0F 91
SETNO r/m8
M
Valid
Valid
Set byte if not overflow (OF=0).
REX + 0F 91
SETNO r/m8*
M
Valid
N.E.
Set byte if not overflow (OF=0).
0F 9B
SETNP r/m8
M
Valid
Valid
Set byte if not parity (PF=0).
REX + 0F 9B
SETNP r/m8*
M
Valid
N.E.
Set byte if not parity (PF=0).
0F 99
SETNS r/m8
M
Valid
Valid
Set byte if not sign (SF=0).
REX + 0F 99
SETNS r/m8*
M
Valid
N.E.
Set byte if not sign (SF=0).
0F 95
SETNZ r/m8
M
Valid
Valid
Set byte if not zero (ZF=0).
REX + 0F 95
SETNZ r/m8*
M
Valid
N.E.
Set byte if not zero (ZF=0).
0F 90
SETO r/m8
M
Valid
Valid
Set byte if overflow (OF=1)
REX + 0F 90
SETO r/m8*
M
Valid
N.E.
Set byte if overflow (OF=1).
0F 9A
SETP r/m8
M
Valid
Valid
Set byte if parity (PF=1).
REX + 0F 9A
SETP r/m8*
M
Valid
N.E.
Set byte if parity (PF=1).
0F 9A
SETPE r/m8
M
Valid
Valid
Set byte if parity even (PF=1).
REX + 0F 9A
SETPE r/m8*
M
Valid
N.E.
Set byte if parity even (PF=1).
0F 9B
SETPO r/m8
M
Valid
Valid
Set byte if parity odd (PF=0).
REX + 0F 9B
SETPO r/m8*
M
Valid
N.E.
Set byte if parity odd (PF=0).
0F 98
SETS r/m8
M
Valid
Valid
Set byte if sign (SF=1).
REX + 0F 98
SETS r/m8*
M
Valid
N.E.
Set byte if sign (SF=1).
0F 94
SETZ r/m8
M
Valid
Valid
Set byte if zero (ZF=1).
REX + 0F 94
SETZ r/m8*
M
Valid
N.E.
Set byte if zero (ZF=1).
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the
EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix
(cc) indicates the condition being tested for.
The terms “above” and “below” are associated with the CF flag and refer to the relationship between two unsigned
integer values. The terms “greater” and “less” are associated with the SF and OF flags and refer to the relationship
between two signed integer values.
Many of the SETcc instruction opcodes have alternate mnemonics. For example, SETG (set byte if greater) and
SETNLE (set if not less or equal) have the same opcode and test for the same condition: ZF equals 0 and SF equals
OF. These alternate mnemonics are provided to make code more intelligible. Appendix B, “EFLAGS Condition
Codes,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, shows the alternate
mnemonics for various test conditions.
Some languages represent a logical one as an integer with all bits set. This representation can be obtained by
choosing the logically opposite condition for the SETcc instruction, then decrementing the result. For example, to
test for overflow, use the SETNO instruction, then decrement the result.
SETcc—Set Byte on Condition
Vol. 2B 4-597
INSTRUCTION SET REFERENCE, M-U
In IA-64 mode, the operand size is fixed at 8 bits. Use of REX prefix enable uniform addressing to additional byte
registers. Otherwise, this instruction’s operation is the same as in legacy mode and compatibility mode.
Operation
IF condition
THEN DEST ← 1;
ELSE DEST ← 0;
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
4-598 Vol. 2B
SETcc—Set Byte on Condition
INSTRUCTION SET REFERENCE, M-U
SFENCE—Store Fence
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AE F8
SFENCE
NP
Valid
Valid
Serializes store operations.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Performs a serializing operation on all store-to-memory instructions that were issued prior the SFENCE instruction.
This serializing operation guarantees that every store instruction that precedes the SFENCE instruction in program
order becomes globally visible before any store instruction that follows the SFENCE instruction. The SFENCE
instruction is ordered with respect to store instructions, other SFENCE instructions, any LFENCE and MFENCE
instructions, and any serializing instructions (such as the CPUID instruction). It is not ordered with respect to load
instructions.
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as
out-of-order issue, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or
knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data.
The SFENCE instruction provides a performance-efficient way of ensuring store ordering between routines that
produce weakly-ordered results and routines that consume this data.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Specification of the instruction's opcode above indicates a ModR/M byte of F8. For this instruction, the processor
ignores the r/m field of the ModR/M byte. Thus, SFENCE is encoded by any opcode of the form 0F AE Fx, where x
is in the range 8-F.
Operation
Wait_On_Following_Stores_Until(preceding_stores_globally_visible);
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_sfence(void)
Exceptions (All Operating Modes)
#UD
If CPUID.01H:EDX.SSE[bit 25] = 0.
If the LOCK prefix is used.
SFENCE—Store Fence
Vol. 2B 4-599
INSTRUCTION SET REFERENCE, M-U
SGDT—Store Global Descriptor Table Register
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 /0
SGDT m
M
Valid
Valid
Store GDTR to m.
NOTES:
* See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Stores the content of the global descriptor table register (GDTR) in the destination operand. The destination
operand specifies a memory location.
In legacy or compatibility mode, the destination operand is a 6-byte memory location. If the operand-size attribute
is 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address is stored in bytes 3-5, and byte 6 is zerofilled. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the low 2 bytes of the
memory location and the 32-bit base address is stored in the high 4 bytes.
In IA-32e mode, the operand size is fixed at 8+2 bytes. The instruction stores an 8-byte base and a 2-byte limit.
SGDT is useful only by operating-system software. However, it can be used in application programs without causing
an exception to be generated if CR4.UMIP = 0. See “LGDT/LIDT—Load Global/Interrupt Descriptor Table Register”
in Chapter 3, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for information on
loading the GDTR and IDTR.
IA-32 Architecture Compatibility
The 16-bit form of the SGDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The
Intel 286 processor fills these bits with 1s; processor generations later than the Intel 286 processor fill these bits
with 0s.
Operation
IF instruction is SGDT
IF OperandSize = 16
THEN
DEST[0:15] ← GDTR(Limit);
DEST[16:39] ← GDTR(Base); (* 24 bits of base address stored *)
DEST[40:47] ← 0;
ELSE IF (32-bit Operand Size)
DEST[0:15] ← GDTR(Limit);
DEST[16:47] ← GDTR(Base); (* Full 32-bit base address stored *)
FI;
ELSE (* 64-bit Operand Size *)
DEST[0:15] ← GDTR(Limit);
DEST[16:79] ← GDTR(Base); (* Full 64-bit base address stored *)
FI;
FI;
Flags Affected
None.
4-600 Vol. 2B
SGDT—Store Global Descriptor Table Register
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#UD
If the destination operand is a register.
If the LOCK prefix is used.
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If CR4.UMIP = 1 and CPL > 0.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
Real-Address Mode Exceptions
#UD
If the destination operand is a register.
If the LOCK prefix is used.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
Virtual-8086 Mode Exceptions
#UD
If the destination operand is a register.
If the LOCK prefix is used.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If CR4.UMIP = 1.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
#UD
If a memory address referencing the SS segment is in a non-canonical form.
If the destination operand is a register.
If the LOCK prefix is used.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
If CR4.UMIP = 1 and CPL > 0.
SGDT—Store Global Descriptor Table Register
Vol. 2B 4-601
INSTRUCTION SET REFERENCE, M-U
SHA1RNDS4—Perform Four Rounds of SHA1 Operation
Opcode/
Instruction
Op/En
0F 3A CC /r ib
SHA1RNDS4 xmm1,
xmm2/m128, imm8
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SHA
Description
Performs four rounds of SHA1 operation operating on SHA1 state
(A,B,C,D) from xmm1, with a pre-computed sum of the next 4
round message dwords and state variable E from xmm2/m128.
The immediate byte controls logic functions and round constants.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
Description
The SHA1RNDS4 instruction performs four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from the
first operand (which is a source operand and the destination operand) and some pre-computed sum of the next 4
round message dwords, and state variable E from the second operand (a source operand). The updated SHA1 state
(A,B,C,D) after four rounds of processing is stored in the destination operand.
Operation
SHA1RNDS4
The function f() and Constant K are dependent on the value of the immediate.
IF ( imm8[1:0] = 0 )
THEN f() f0(), K K0;
ELSE IF ( imm8[1:0] = 1 )
THEN f() f1(), K K1;
ELSE IF ( imm8[1:0] = 2 )
THEN f() f2(), K K2;
ELSE IF ( imm8[1:0] = 3 )
THEN f() f3(), K K3;
FI;
A SRC1[127:96];
B SRC1[95:64];
C SRC1[63:32];
D SRC1[31:0];
W0E SRC2[127:96];
W1 SRC2[95:64];
W2 SRC2[63:32];
W3 SRC2[31:0];
Round i = 0 operation:
A_1 f (B, C, D) + (A ROL 5) +W0E +K;
B_1 A;
C_1 B ROL 30;
D_1 C;
E_1 D;
FOR i = 1 to 3
A_(i +1) f (B_i, C_i, D_i) + (A_i ROL 5) +Wi+ E_i +K;
B_(i +1) A_i;
4-602 Vol. 2B
SHA1RNDS4—Perform Four Rounds of SHA1 Operation
INSTRUCTION SET REFERENCE, M-U
C_(i +1) B_i ROL 30;
D_(i +1) C_i;
E_(i +1) D_i;
ENDFOR
DEST[127:96] A_4;
DEST[95:64] B_4;
DEST[63:32] C_4;
DEST[31:0] D_4;
Intel C/C++ Compiler Intrinsic Equivalent
SHA1RNDS4: __m128i _mm_sha1rnds4_epu32(__m128i, __m128i, const int);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
SHA1RNDS4—Perform Four Rounds of SHA1 Operation
Vol. 2B 4-603
INSTRUCTION SET REFERENCE, M-U
SHA1NEXTE—Calculate SHA1 State Variable E after Four Rounds
Opcode/
Instruction
Op/En
0F 38 C8 /r
SHA1NEXTE xmm1,
xmm2/m128
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SHA
Description
Calculates SHA1 state variable E after four rounds of operation
from the current SHA1 state variable A in xmm1. The calculated
value of the SHA1 state variable E is added to the scheduled
dwords in xmm2/m128, and stored with some of the scheduled
dwords in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
Description
The SHA1NEXTE calculates the SHA1 state variable E after four rounds of operation from the current SHA1 state
variable A in the destination operand. The calculated value of the SHA1 state variable E is added to the source
operand, which contains the scheduled dwords.
Operation
SHA1NEXTE
TMP (SRC1[127:96] ROL 30);
DEST[127:96] SRC2[127:96] + TMP;
DEST[95:64] SRC2[95:64];
DEST[63:32] SRC2[63:32];
DEST[31:0] SRC2[31:0];
Intel C/C++ Compiler Intrinsic Equivalent
SHA1NEXTE: __m128i _mm_sha1nexte_epu32(__m128i, __m128i);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
4-604 Vol. 2B
SHA1NEXTE—Calculate SHA1 State Variable E after Four Rounds
INSTRUCTION SET REFERENCE, M-U
SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords
Opcode/
Instruction
Op/En
0F 38 C9 /r
SHA1MSG1 xmm1,
xmm2/m128
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SHA
Description
Performs an intermediate calculation for the next four SHA1
message dwords using previous message dwords from xmm1 and
xmm2/m128, storing the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
Description
The SHA1MSG1 instruction is one of two SHA1 message scheduling instructions. The instruction performs an intermediate calculation for the next four SHA1 message dwords.
Operation
SHA1MSG1
W0 SRC1[127:96] ;
W1 SRC1[95:64] ;
W2 SRC1[63: 32] ;
W3 SRC1[31: 0] ;
W4 SRC2[127:96] ;
W5 SRC2[95:64] ;
DEST[127:96] W2 XOR W0;
DEST[95:64] W3 XOR W1;
DEST[63:32] W4 XOR W2;
DEST[31:0] W5 XOR W3;
Intel C/C++ Compiler Intrinsic Equivalent
SHA1MSG1: __m128i _mm_sha1msg1_epu32(__m128i, __m128i);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords
Vol. 2B 4-605
INSTRUCTION SET REFERENCE, M-U
SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords
Opcode/
Instruction
Op/En
0F 38 CA /r
SHA1MSG2 xmm1,
xmm2/m128
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SHA
Description
Performs the final calculation for the next four SHA1 message
dwords using intermediate results from xmm1 and the previous
message dwords from xmm2/m128, storing the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
Description
The SHA1MSG2 instruction is one of two SHA1 message scheduling instructions. The instruction performs the final
calculation to derive the next four SHA1 message dwords.
Operation
SHA1MSG2
W13 SRC2[95:64] ;
W14 SRC2[63: 32] ;
W15 SRC2[31: 0] ;
W16 (SRC1[127:96] XOR W13 ) ROL 1;
W17 (SRC1[95:64] XOR W14) ROL 1;
W18 (SRC1[63: 32] XOR W15) ROL 1;
W19 (SRC1[31: 0] XOR W16) ROL 1;
DEST[127:96] W16;
DEST[95:64] W17;
DEST[63:32] W18;
DEST[31:0] W19;
Intel C/C++ Compiler Intrinsic Equivalent
SHA1MSG2: __m128i _mm_sha1msg2_epu32(__m128i, __m128i);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
4-606 Vol. 2B
SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords
INSTRUCTION SET REFERENCE, M-U
SHA256RNDS2—Perform Two Rounds of SHA256 Operation
Opcode/
Instruction
Op/En
0F 38 CB /r
SHA256RNDS2 xmm1,
xmm2/m128,
RM0
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SHA
Description
Perform 2 rounds of SHA256 operation using an initial SHA256
state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from
xmm2/m128, and a pre-computed sum of the next 2 round message dwords and the corresponding round constants from the
implicit operand XMM0, storing the updated SHA256 state
(A,B,E,F) result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Implicit XMM0 (r)
Description
The SHA256RNDS2 instruction performs 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H)
from the first operand, an initial SHA256 state (A,B,E,F) from the second operand, and a pre-computed sum of the
next 2 round message dwords and the corresponding round constants from the implicit operand xmm0. Note that
only the two lower dwords of XMM0 are used by the instruction.
The updated SHA256 state (A,B,E,F) is written to the first operand, and the second operand can be used as the
updated state (C,D,G,H) in later rounds.
Operation
SHA256RNDS2
A_0 SRC2[127:96];
B_0 SRC2[95:64];
C_0 SRC1[127:96];
D_0 SRC1[95:64];
E_0 SRC2[63:32];
F_0 SRC2[31:0];
G_0 SRC1[63:32];
H_0 SRC1[31:0];
WK0 XMM0[31: 0];
WK1 XMM0[63: 32];
FOR i = 0 to 1
A_(i +1) Ch (E_i, F_i, G_i) +Σ1( E_i) +WKi+ H_i + Maj(A_i , B_i, C_i) +Σ0( A_i);
B_(i +1) A_i;
C_(i +1) B_i ;
D_(i +1) C_i;
E_(i +1) Ch (E_i, F_i, G_i) +Σ1( E_i) +WKi+ H_i + D_i;
F_(i +1) E_i ;
G_(i +1) F_i;
H_(i +1) G_i;
ENDFOR
DEST[127:96] A_2;
DEST[95:64] B_2;
DEST[63:32] E_2;
DEST[31:0] F_2;
SHA256RNDS2—Perform Two Rounds of SHA256 Operation
Vol. 2B 4-607
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
SHA256RNDS2: __m128i _mm_sha256rnds2_epu32(__m128i, __m128i, __m128i);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
4-608 Vol. 2B
SHA256RNDS2—Perform Two Rounds of SHA256 Operation
INSTRUCTION SET REFERENCE, M-U
SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message
Dwords
Opcode/
Instruction
Op/En
0F 38 CC /r
SHA256MSG1 xmm1,
xmm2/m128
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SHA
Description
Performs an intermediate calculation for the next four SHA256
message dwords using previous message dwords from xmm1 and
xmm2/m128, storing the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
Description
The SHA256MSG1 instruction is one of two SHA256 message scheduling instructions. The instruction performs an
intermediate calculation for the next four SHA256 message dwords.
Operation
SHA256MSG1
W4 SRC2[31: 0] ;
W3 SRC1[127:96] ;
W2 SRC1[95:64] ;
W1 SRC1[63: 32] ;
W0 SRC1[31: 0] ;
DEST[127:96] W3 + σ0( W4);
DEST[95:64] W2 + σ0( W3);
DEST[63:32] W1 + σ0( W2);
DEST[31:0] W0 + σ0( W1);
Intel C/C++ Compiler Intrinsic Equivalent
SHA256MSG1: __m128i _mm_sha256msg1_epu32(__m128i, __m128i);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords
Vol. 2B 4-609
INSTRUCTION SET REFERENCE, M-U
SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords
Opcode/
Instruction
Op/En
0F 38 CD /r
SHA256MSG2 xmm1,
xmm2/m128
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SHA
Description
Performs the final calculation for the next four SHA256 message
dwords using previous message dwords from xmm1 and
xmm2/m128, storing the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
Description
The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the
final calculation for the next four SHA256 message dwords.
Operation
SHA256MSG2
W14 SRC2[95:64] ;
W15 SRC2[127:96] ;
W16 SRC1[31: 0] + σ1( W14) ;
W17 SRC1[63: 32] + σ1( W15) ;
W18 SRC1[95: 64] + σ1( W16) ;
W19 SRC1[127: 96] + σ1( W17) ;
DEST[127:96] W19 ;
DEST[95:64] W18 ;
DEST[63:32] W17 ;
DEST[31:0] W16;
Intel C/C++ Compiler Intrinsic Equivalent
SHA256MSG2 : __m128i _mm_sha256msg2_epu32(__m128i, __m128i);
Flags Affected
None
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
4-610 Vol. 2B
SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords
INSTRUCTION SET REFERENCE, M-U
SHLD—Double Precision Shift Left
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F A4 /r ib
SHLD r/m16, r16, imm8
MRI
Valid
Valid
Shift r/m16 to left imm8 places while shifting
bits from r16 in from the right.
0F A5 /r
SHLD r/m16, r16, CL
MRC Valid
Valid
Shift r/m16 to left CL places while shifting bits
from r16 in from the right.
0F A4 /r ib
SHLD r/m32, r32, imm8
MRI
Valid
Valid
Shift r/m32 to left imm8 places while shifting
bits from r32 in from the right.
REX.W + 0F A4 /r ib
SHLD r/m64, r64, imm8
MRI
Valid
N.E.
Shift r/m64 to left imm8 places while shifting
bits from r64 in from the right.
0F A5 /r
SHLD r/m32, r32, CL
MRC Valid
Valid
Shift r/m32 to left CL places while shifting bits
from r32 in from the right.
REX.W + 0F A5 /r
SHLD r/m64, r64, CL
MRC Valid
N.E.
Shift r/m64 to left CL places while shifting
bits from r64 in from the right.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MRI
ModRM:r/m (w)
ModRM:reg (r)
imm8
NA
MRC
ModRM:r/m (w)
ModRM:reg (r)
CL
NA
Description
The SHLD instruction is used for multi-precision shifts of 64 bits or more.
The instruction shifts the first operand (destination operand) to the left the number of bits specified by the third
operand (count operand). The second operand (source operand) provides bits to shift in from the right (starting
with bit 0 of the destination operand).
The destination operand can be a register or a memory location; the source operand is a register. The count
operand is an unsigned integer that can be stored in an immediate byte or in the CL register. If the count operand
is CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode; only
bits 0 through 4 of the count are used. This masks the count to a value between 0 and 31. If a count is greater than
the operand size, the result is undefined.
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit
shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not
affected.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits
(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and
limits.
Operation
IF (In 64-Bit Mode and REX.W = 1)
THEN COUNT ← COUNT MOD 64;
ELSE COUNT ← COUNT MOD 32;
FI
SIZE ← OperandSize;
IF COUNT = 0
THEN
No operation;
ELSE
SHLD—Double Precision Shift Left
Vol. 2B 4-611
INSTRUCTION SET REFERENCE, M-U
IF COUNT > SIZE
THEN (* Bad parameters *)
DEST is undefined;
CF, OF, SF, ZF, AF, PF are undefined;
ELSE (* Perform the shift *)
CF ← BIT[DEST, SIZE – COUNT];
(* Last bit shifted out on exit *)
FOR i ← SIZE – 1 DOWN TO COUNT
DO
Bit(DEST, i) ← Bit(DEST, i – COUNT);
OD;
FOR i ← COUNT – 1 DOWN TO 0
DO
BIT[DEST, i] ← BIT[SRC, i – COUNT + SIZE];
OD;
FI;
FI;
Flags Affected
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF,
and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred;
otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags
are undefined.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
4-612 Vol. 2B
SHLD—Double Precision Shift Left
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
SHLD—Double Precision Shift Left
Vol. 2B 4-613
INSTRUCTION SET REFERENCE, M-U
SHRD—Double Precision Shift Right
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AC /r ib
SHRD r/m16, r16, imm8
MRI
Valid
Valid
Shift r/m16 to right imm8 places while
shifting bits from r16 in from the left.
0F AD /r
SHRD r/m16, r16, CL
MRC Valid
Valid
Shift r/m16 to right CL places while shifting
bits from r16 in from the left.
0F AC /r ib
SHRD r/m32, r32, imm8
MRI
Valid
Valid
Shift r/m32 to right imm8 places while
shifting bits from r32 in from the left.
REX.W + 0F AC /r ib
SHRD r/m64, r64, imm8
MRI
Valid
N.E.
Shift r/m64 to right imm8 places while
shifting bits from r64 in from the left.
0F AD /r
SHRD r/m32, r32, CL
MRC Valid
Valid
Shift r/m32 to right CL places while shifting
bits from r32 in from the left.
REX.W + 0F AD /r
SHRD r/m64, r64, CL
MRC Valid
N.E.
Shift r/m64 to right CL places while shifting
bits from r64 in from the left.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MRI
ModRM:r/m (w)
ModRM:reg (r)
imm8
NA
MRC
ModRM:r/m (w)
ModRM:reg (r)
CL
NA
Description
The SHRD instruction is useful for multi-precision shifts of 64 bits or more.
The instruction shifts the first operand (destination operand) to the right the number of bits specified by the third
operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with
the most significant bit of the destination operand).
The destination operand can be a register or a memory location; the source operand is a register. The count
operand is an unsigned integer that can be stored in an immediate byte or the CL register. If the count operand is
CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode, the
width of the count mask is 5 bits. Only bits 0 through 4 of the count register are used (masking the count to a value
between 0 and 31). If the count is greater than the operand size, the result is undefined.
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit
shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not
affected.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits
(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and
limits.
Operation
IF (In 64-Bit Mode and REX.W = 1)
THEN COUNT ← COUNT MOD 64;
ELSE COUNT ← COUNT MOD 32;
FI
SIZE ← OperandSize;
IF COUNT = 0
THEN
No operation;
ELSE
4-614 Vol. 2B
SHRD—Double Precision Shift Right
INSTRUCTION SET REFERENCE, M-U
IF COUNT > SIZE
THEN (* Bad parameters *)
DEST is undefined;
CF, OF, SF, ZF, AF, PF are undefined;
ELSE (* Perform the shift *)
CF ← BIT[DEST, COUNT – 1]; (* Last bit shifted out on exit *)
FOR i ← 0 TO SIZE – 1 – COUNT
DO
BIT[DEST, i] ← BIT[DEST, i + COUNT];
OD;
FOR i ← SIZE – COUNT TO SIZE – 1
DO
BIT[DEST,i] ← BIT[SRC, i + COUNT – SIZE];
OD;
FI;
FI;
Flags Affected
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF,
ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change
occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag
is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the
flags are undefined.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
SHRD—Double Precision Shift Right
Vol. 2B 4-615
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
4-616 Vol. 2B
SHRD—Double Precision Shift Right
INSTRUCTION SET REFERENCE, M-U
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F C6 /r ib
SHUFPD xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F.WIG C6 /r ib
VSHUFPD xmm1, xmm2, xmm3/m128,
imm8
RVMI
V/V
AVX
VEX.NDS.256.66.0F.WIG C6 /r ib
VSHUFPD ymm1, ymm2, ymm3/m256,
imm8
RVMI
V/V
AVX
EVEX.NDS.128.66.0F.W1 C6 /r ib
VSHUFPD xmm1{k1}{z}, xmm2,
xmm3/m128/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F.W1 C6 /r ib
VSHUFPD ymm1{k1}{z}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F.W1 C6 /r ib
VSHUFPD zmm1{k1}{z}, zmm2,
zmm3/m512/m64bcst, imm8
FV
V/V
AVX512F
Description
Shuffle two pairs of double-precision floating-point
values from xmm1 and xmm2/m128 using imm8 to
select from each pair, interleaved result is stored in
xmm1.
Shuffle two pairs of double-precision floating-point
values from xmm2 and xmm3/m128 using imm8 to
select from each pair, interleaved result is stored in
xmm1.
Shuffle four pairs of double-precision floating-point
values from ymm2 and ymm3/m256 using imm8 to
select from each pair, interleaved result is stored in
xmm1.
Shuffle two paris of double-precision floating-point
values from xmm2 and xmm3/m128/m64bcst using
imm8 to select from each pair. store interleaved
results in xmm1 subject to writemask k1.
Shuffle four paris of double-precision floating-point
values from ymm2 and ymm3/m256/m64bcst using
imm8 to select from each pair. store interleaved
results in ymm1 subject to writemask k1.
Shuffle eight paris of double-precision floating-point
values from zmm2 and zmm3/m512/m64bcst using
imm8 to select from each pair. store interleaved
results in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
Imm8
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
Selects a double-precision floating-point value of an input pair using a bit control and move to a designated
element of the destination operand. The low-to-high order of double-precision element of the destination operand
is interleaved between the first source operand and the second source operand at the granularity of input pair of
128 bits. Each bit in the imm8 byte, starting from bit 0, is the select control of the corresponding element of the
destination to received the shuffled result of an input pair.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
64-bit memory location The destination operand is a ZMM/YMM/XMM register updated according to the writemask.
The select controls are the lower 8/4/2 bits of the imm8 byte.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The select controls are the bit 3:0
of the imm8 byte, imm8[7:4) are ignored.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed. The select controls are the bit 1:0 of the imm8 byte,
imm8[7:2) are ignored.
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
Vol. 2B 4-617
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination operand and the first source operand is the same and is an XMM register. The upper bits (MAX_VL-1:128) of
the corresponding ZMM register destination are unmodified. The select controls are the bit 1:0 of the imm8 byte,
imm8[7:2) are ignored.
SRC1
X3
X2
X1
X0
SRC2
Y3
Y2
Y1
Y0
DEST
Y2 or Y3
X2 or X3
Y0 or Y1
X0 or X1
Figure 4-25. 256-bit VSHUFPD Operation of Four Pairs of DP FP Values
Operation
VSHUFPD (EVEX encoded versions when SRC2 is a vector register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF IMM0[0] = 0
THEN TMP_DEST[63:0] SRC1[63:0]
ELSE TMP_DEST[63:0] SRC1[127:64] FI;
IF IMM0[1] = 0
THEN TMP_DEST[127:64] SRC2[63:0]
ELSE TMP_DEST[127:64] SRC2[127:64] FI;
IF VL >= 256
IF IMM0[2] = 0
THEN TMP_DEST[191:128] SRC1[191:128]
ELSE TMP_DEST[191:128] SRC1[255:192] FI;
IF IMM0[3] = 0
THEN TMP_DEST[255:192] SRC2[191:128]
ELSE TMP_DEST[255:192] SRC2[255:192] FI;
FI;
IF VL >= 512
IF IMM0[4] = 0
THEN TMP_DEST[319:256] SRC1[319:256]
ELSE TMP_DEST[319:256] SRC1[383:320] FI;
IF IMM0[5] = 0
THEN TMP_DEST[383:320] SRC2[319:256]
ELSE TMP_DEST[383:320] SRC2[383:320] FI;
IF IMM0[6] = 0
THEN TMP_DEST[447:384] SRC1[447:384]
ELSE TMP_DEST[447:384] SRC1[511:448] FI;
IF IMM0[7] = 0
THEN TMP_DEST[511:448] SRC2[447:384]
ELSE TMP_DEST[511:448] SRC2[511:448] FI;
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
4-618 Vol. 2B
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSHUFPD (EVEX encoded versions when SRC2 is memory)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1)
THEN TMP_SRC2[i+63:i] SRC2[63:0]
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i]
FI;
ENDFOR;
IF IMM0[0] = 0
THEN TMP_DEST[63:0] SRC1[63:0]
ELSE TMP_DEST[63:0] SRC1[127:64] FI;
IF IMM0[1] = 0
THEN TMP_DEST[127:64] TMP_SRC2[63:0]
ELSE TMP_DEST[127:64] TMP_SRC2[127:64] FI;
IF VL >= 256
IF IMM0[2] = 0
THEN TMP_DEST[191:128] SRC1[191:128]
ELSE TMP_DEST[191:128] SRC1[255:192] FI;
IF IMM0[3] = 0
THEN TMP_DEST[255:192] TMP_SRC2[191:128]
ELSE TMP_DEST[255:192] TMP_SRC2[255:192] FI;
FI;
IF VL >= 512
IF IMM0[4] = 0
THEN TMP_DEST[319:256] SRC1[319:256]
ELSE TMP_DEST[319:256] SRC1[383:320] FI;
IF IMM0[5] = 0
THEN TMP_DEST[383:320] TMP_SRC2[319:256]
ELSE TMP_DEST[383:320] TMP_SRC2[383:320] FI;
IF IMM0[6] = 0
THEN TMP_DEST[447:384] SRC1[447:384]
ELSE TMP_DEST[447:384] SRC1[511:448] FI;
IF IMM0[7] = 0
THEN TMP_DEST[511:448] TMP_SRC2[447:384]
ELSE TMP_DEST[511:448] TMP_SRC2[511:448] FI;
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
Vol. 2B 4-619
INSTRUCTION SET REFERENCE, M-U
ELSE *zeroing-masking*
DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSHUFPD (VEX.256 encoded version)
IF IMM0[0] = 0
THEN DEST[63:0] SRC1[63:0]
ELSE DEST[63:0] SRC1[127:64] FI;
IF IMM0[1] = 0
THEN DEST[127:64] SRC2[63:0]
ELSE DEST[127:64] SRC2[127:64] FI;
IF IMM0[2] = 0
THEN DEST[191:128] SRC1[191:128]
ELSE DEST[191:128] SRC1[255:192] FI;
IF IMM0[3] = 0
THEN DEST[255:192] SRC2[191:128]
ELSE DEST[255:192] SRC2[255:192] FI;
DEST[MAX_VL-1:256] (Unmodified)
VSHUFPD (VEX.128 encoded version)
IF IMM0[0] = 0
THEN DEST[63:0] SRC1[63:0]
ELSE DEST[63:0] SRC1[127:64] FI;
IF IMM0[1] = 0
THEN DEST[127:64] SRC2[63:0]
ELSE DEST[127:64] SRC2[127:64] FI;
DEST[MAX_VL-1:128] 0
VSHUFPD (128-bit Legacy SSE version)
IF IMM0[0] = 0
THEN DEST[63:0] SRC1[63:0]
ELSE DEST[63:0] SRC1[127:64] FI;
IF IMM0[1] = 0
THEN DEST[127:64] SRC2[63:0]
ELSE DEST[127:64] SRC2[127:64] FI;
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSHUFPD __m512d _mm512_shuffle_pd(__m512d a, __m512d b, int imm);
VSHUFPD __m512d _mm512_mask_shuffle_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFPD __m512d _mm512_maskz_shuffle_pd( __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFPD __m256d _mm256_shuffle_pd (__m256d a, __m256d b, const int select);
VSHUFPD __m256d _mm256_mask_shuffle_pd(__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);
VSHUFPD __m256d _mm256_maskz_shuffle_pd( __mmask8 k, __m256d a, __m256d b, int imm);
SHUFPD __m128d _mm_shuffle_pd (__m128d a, __m128d b, const int select);
VSHUFPD __m128d _mm_mask_shuffle_pd(__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VSHUFPD __m128d _mm_maskz_shuffle_pd( __mmask8 k, __m128d a, __m128d b, int imm);
4-620 Vol. 2B
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
Vol. 2B 4-621
INSTRUCTION SET REFERENCE, M-U
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F C6 /r ib
SHUFPS xmm1, xmm3/m128, imm8
VEX.NDS.128.0F.WIG C6 /r ib
VSHUFPS xmm1, xmm2,
xmm3/m128, imm8
VEX.NDS.256.0F.WIG C6 /r ib
VSHUFPS ymm1, ymm2,
ymm3/m256, imm8
EVEX.NDS.128.0F.W0 C6 /r ib
VSHUFPS xmm1{k1}{z}, xmm2,
xmm3/m128/m32bcst, imm8
RVMI
V/V
AVX
RVMI
V/V
AVX
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.0F.W0 C6 /r ib
VSHUFPS ymm1{k1}{z}, ymm2,
ymm3/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.0F.W0 C6 /r ib
VSHUFPS zmm1{k1}{z}, zmm2,
zmm3/m512/m32bcst, imm8
FV
V/V
AVX512F
Description
Select from quadruplet of single-precision floatingpoint values in xmm1 and xmm2/m128 using imm8,
interleaved result pairs are stored in xmm1.
Select from quadruplet of single-precision floatingpoint values in xmm1 and xmm2/m128 using imm8,
interleaved result pairs are stored in xmm1.
Select from quadruplet of single-precision floatingpoint values in ymm2 and ymm3/m256 using imm8,
interleaved result pairs are stored in ymm1.
Select from quadruplet of single-precision floatingpoint values in xmm1 and xmm2/m128 using imm8,
interleaved result pairs are stored in xmm1, subject to
writemask k1.
Select from quadruplet of single-precision floatingpoint values in ymm2 and ymm3/m256 using imm8,
interleaved result pairs are stored in ymm1, subject to
writemask k1.
Select from quadruplet of single-precision floatingpoint values in zmm2 and zmm3/m512 using imm8,
interleaved result pairs are stored in zmm1, subject to
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
Imm8
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
Selects a single-precision floating-point value of an input quadruplet using a two-bit control and move to a designated element of the destination operand. Each 64-bit element-pair of a 128-bit lane of the destination operand is
interleaved between the corresponding lane of the first source operand and the second source operand at the granularity 128 bits. Each two bits in the imm8 byte, starting from bit 0, is the select control of the corresponding
element of a 128-bit lane of the destination to received the shuffled result of an input quadruplet. The two lower
elements of a 128-bit lane in the destination receives shuffle results from the quadruple of the first source operand.
The next two elements of the destination receives shuffle results from the quadruple of the second source operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.
Imm8[7:0] provides 4 select controls for each applicable 128-bit lane of the destination.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. Imm8[7:0] provides 4 select
controls for the high and low 128-bit of the destination.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed. Imm8[7:0] provides 4 select controls for each element
of the destination.
4-622 Vol. 2B
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
128-bit Legacy SSE version: The source can be an XMM register or an 128-bit memory location. The destination is
not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM
register destination are unmodified. Imm8[7:0] provides 4 select controls for each element of the destination.
SRC1
X7
X6
X5
X4
X3
X2
X1
X0
SRC2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y3 ..Y0
X3 .. X0
X3 .. X0
DEST Y7 .. Y4
Y7 .. Y4
X7 .. X4
X7 .. X4 Y3 ..Y0
Figure 4-26. 256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved Result
Operation
Select4(SRC, control) {
CASE (control[1:0]) OF
0: TMP SRC[31:0];
1: TMP SRC[63:32];
2: TMP SRC[95:64];
3: TMP SRC[127:96];
ESAC;
RETURN TMP
}
VPSHUFPS (EVEX encoded versions when SRC2 is a vector register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
TMP_DEST[31:0] Select4(SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] Select4(SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] Select4(SRC2[127:0], imm8[5:4]);
TMP_DEST[127:96] Select4(SRC2[127:0], imm8[7:6]);
IF VL >= 256
TMP_DEST[159:128] Select4(SRC1[255:128], imm8[1:0]);
TMP_DEST[191:160] Select4(SRC1[255:128], imm8[3:2]);
TMP_DEST[223:192] Select4(SRC2[255:128], imm8[5:4]);
TMP_DEST[255:224] Select4(SRC2[255:128], imm8[7:6]);
FI;
IF VL >= 512
TMP_DEST[287:256] Select4(SRC1[383:256], imm8[1:0]);
TMP_DEST[319:288] Select4(SRC1[383:256], imm8[3:2]);
TMP_DEST[351:320] Select4(SRC2[383:256], imm8[5:4]);
TMP_DEST[383:352] Select4(SRC2[383:256], imm8[7:6]);
TMP_DEST[415:384] Select4(SRC1[511:384], imm8[1:0]);
TMP_DEST[447:416] Select4(SRC1[511:384], imm8[3:2]);
TMP_DEST[479:448] Select4(SRC2[511:384], imm8[5:4]);
TMP_DEST[511:480] Select4(SRC2[511:384], imm8[7:6]);
FI;
FOR j 0 TO KL-1
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values
Vol. 2B 4-623
INSTRUCTION SET REFERENCE, M-U
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPSHUFPS (EVEX encoded versions when SRC2 is memory)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1)
THEN TMP_SRC2[i+31:i] SRC2[31:0]
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
TMP_DEST[31:0] Select4(SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] Select4(SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] Select4(TMP_SRC2[127:0], imm8[5:4]);
TMP_DEST[127:96] Select4(TMP_SRC2[127:0], imm8[7:6]);
IF VL >= 256
TMP_DEST[159:128] Select4(SRC1[255:128], imm8[1:0]);
TMP_DEST[191:160] Select4(SRC1[255:128], imm8[3:2]);
TMP_DEST[223:192] Select4(TMP_SRC2[255:128], imm8[5:4]);
TMP_DEST[255:224] Select4(TMP_SRC2[255:128], imm8[7:6]);
FI;
IF VL >= 512
TMP_DEST[287:256] Select4(SRC1[383:256], imm8[1:0]);
TMP_DEST[319:288] Select4(SRC1[383:256], imm8[3:2]);
TMP_DEST[351:320] Select4(TMP_SRC2[383:256], imm8[5:4]);
TMP_DEST[383:352] Select4(TMP_SRC2[383:256], imm8[7:6]);
TMP_DEST[415:384] Select4(SRC1[511:384], imm8[1:0]);
TMP_DEST[447:416] Select4(SRC1[511:384], imm8[3:2]);
TMP_DEST[479:448] Select4(TMP_SRC2[511:384], imm8[5:4]);
TMP_DEST[511:480] Select4(TMP_SRC2[511:384], imm8[7:6]);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
4-624 Vol. 2B
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
DEST[MAX_VL-1:VL] 0
VSHUFPS (VEX.256 encoded version)
DEST[31:0] Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] Select4(SRC2[127:0], imm8[7:6]);
DEST[159:128] Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] Select4(SRC2[255:128], imm8[5:4]);
DEST[255:224] Select4(SRC2[255:128], imm8[7:6]);
DEST[MAX_VL-1:256] 0
VSHUFPS (VEX.128 encoded version)
DEST[31:0] Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] Select4(SRC2[127:0], imm8[7:6]);
DEST[MAX_VL-1:128] 0
SHUFPS (128-bit Legacy SSE version)
DEST[31:0] Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] Select4(SRC2[127:0], imm8[7:6]);
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSHUFPS __m512 _mm512_shuffle_ps(__m512 a, __m512 b, int imm);
VSHUFPS __m512 _mm512_mask_shuffle_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFPS __m512 _mm512_maskz_shuffle_ps(__mmask16 k, __m512 a, __m512 b, int imm);
VSHUFPS __m256 _mm256_shuffle_ps (__m256 a, __m256 b, const int select);
VSHUFPS __m256 _mm256_mask_shuffle_ps(__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);
VSHUFPS __m256 _mm256_maskz_shuffle_ps(__mmask8 k, __m256 a, __m256 b, int imm);
SHUFPS __m128 _mm_shuffle_ps (__m128 a, __m128 b, const int select);
VSHUFPS __m128 _mm_mask_shuffle_ps(__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VSHUFPS __m128 _mm_maskz_shuffle_ps(__mmask8 k, __m128 a, __m128 b, int imm);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values
Vol. 2B 4-625
INSTRUCTION SET REFERENCE, M-U
SIDT—Store Interrupt Descriptor Table Register
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 /1
SIDT m
M
Valid
Valid
Store IDTR to m.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Stores the content the interrupt descriptor table register (IDTR) in the destination operand. The destination
operand specifies a 6-byte memory location.
In non-64-bit modes, if the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the low
2 bytes of the memory location and the 32-bit base address is stored in the high 4 bytes. If the operand-size attribute is 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address is stored in the third, fourth, and
fifth byte, with the sixth byte filled with 0s.
In 64-bit mode, the operand size fixed at 8+2 bytes. The instruction stores 8-byte base and 2-byte limit values.
SIDT is only useful in operating-system software; however, it can be used in application programs without causing
an exception to be generated if CR4.UMIP = 0. See “LGDT/LIDT—Load Global/Interrupt Descriptor Table Register”
in Chapter 3, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for information on
loading the GDTR and IDTR.
IA-32 Architecture Compatibility
The 16-bit form of SIDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The Intel
286 processor fills these bits with 1s; processor generations later than the Intel 286 processor fill these bits with
0s.
Operation
IF instruction is SIDT
THEN
IF OperandSize = 16
THEN
DEST[0:15] ← IDTR(Limit);
DEST[16:39] ← IDTR(Base); (* 24 bits of base address stored; *)
DEST[40:47] ← 0;
ELSE IF (32-bit Operand Size)
DEST[0:15] ← IDTR(Limit);
DEST[16:47] ← IDTR(Base); FI; (* Full 32-bit base address stored *)
ELSE (* 64-bit Operand Size *)
DEST[0:15] ← IDTR(Limit);
DEST[16:79] ← IDTR(Base); (* Full 64-bit base address stored *)
FI;
FI;
Flags Affected
None.
4-626 Vol. 2B
SIDT—Store Interrupt Descriptor Table Register
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If CR4.UMIP = 1 and CPL > 0.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If CR4.UMIP = 1.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
#UD
If a memory address referencing the SS segment is in a non-canonical form.
If the destination operand is a register.
If the LOCK prefix is used.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
If CR4.UMIP = 1 and CPL > 0.
SIDT—Store Interrupt Descriptor Table Register
Vol. 2B 4-627
INSTRUCTION SET REFERENCE, M-U
SLDT—Store Local Descriptor Table Register
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 00 /0
SLDT r/m16
M
Valid
Valid
Stores segment selector from LDTR in r/m16.
REX.W + 0F 00 /0
SLDT r64/m16
M
Valid
Valid
Stores segment selector from LDTR in
r64/m16.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Stores the segment selector from the local descriptor table register (LDTR) in the destination operand. The destination operand can be a general-purpose register or a memory location. The segment selector stored with this
instruction points to the segment descriptor (located in the GDT) for the current LDT. This instruction can only be
executed in protected mode.
Outside IA-32e mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into
the low-order 16 bits of the register. The high-order 16 bits of the register are cleared for the Pentium 4, Intel Xeon,
and P6 family processors. They are undefined for Pentium, Intel486, and Intel386 processors. When the destination operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of
the operand size.
In compatibility mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into
the low-order 16 bits of the register. The high-order 16 bits of the register are cleared. When the destination
operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of the
operand size.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). The
behavior of SLDT with a 64-bit register is to zero-extend the 16-bit selector and store it in the register. If the destination is memory and operand size is 64, SLDT will write the 16-bit selector to memory as a 16-bit quantity,
regardless of the operand size.
Operation
DEST ← LDTR(SegmentSelector);
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If CR4.UMIP = 1 and CPL > 0.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD
If the LOCK prefix is used.
4-628 Vol. 2B
SLDT—Store Local Descriptor Table Register
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#UD
The SLDT instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The SLDT instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
If CR4.UMIP = 1 and CPL > 0.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD
If the LOCK prefix is used.
SLDT—Store Local Descriptor Table Register
Vol. 2B 4-629
INSTRUCTION SET REFERENCE, M-U
SMSW—Store Machine Status Word
Opcode*
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 /4
SMSW r/m16
M
Valid
Valid
Store machine status word to r/m16.
0F 01 /4
SMSW r32/m16
M
Valid
Valid
Store machine status word in low-order 16
bits of r32/m16; high-order 16 bits of r32 are
undefined.
REX.W + 0F 01 /4
SMSW r64/m16
M
Valid
Valid
Store machine status word in low-order 16
bits of r64/m16; high-order 16 bits of r32 are
undefined.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Stores the machine status word (bits 0 through 15 of control register CR0) into the destination operand. The destination operand can be a general-purpose register or a memory location.
In non-64-bit modes, when the destination operand is a 32-bit register, the low-order 16 bits of register CR0 are
copied into the low-order 16 bits of the register and the high-order 16 bits are undefined. When the destination
operand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity,
regardless of the operand size.
In 64-bit mode, the behavior of the SMSW instruction is defined by the following examples:
•
•
•
•
•
•
SMSW r16 operand size 16, store CR0[15:0] in r16
SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32
SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64
SMSW m16 operand size 16, store CR0[15:0] in m16
SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)
SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)
SMSW is only useful in operating-system software. However, it is not a privileged instruction and can be used in
application programs if CR4.UMIP = 0. It is provided for compatibility with the Intel 286 processor. Programs and
procedures intended to run on IA-32 and Intel 64 processors beginning with the Intel386 processors should use the
MOV CR instruction to load the machine status word.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.
Operation
DEST ← CR0[15:0];
(* Machine status word *)
Flags Affected
None.
4-630 Vol. 2B
SMSW—Store Machine Status Word
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If CR4.UMIP = 1 and CPL > 0.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If CR4.UMIP = 1.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
If CR4.UMIP = 1 and CPL > 0.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD
If the LOCK prefix is used.
SMSW—Store Machine Status Word
Vol. 2B 4-631
INSTRUCTION SET REFERENCE, M-U
SQRTPD—Square Root of Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 51 /r
SQRTPD xmm1, xmm2/m128
VEX.128.66.0F.WIG 51 /r
VSQRTPD xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.66.0F.WIG 51 /r
VSQRTPD ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.66.0F.W1 51 /r
VSQRTPD xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.66.0F.W1 51 /r
VSQRTPD ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.66.0F.W1 51 /r
VSQRTPD zmm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Computes Square Roots of the packed double-precision
floating-point values in xmm2/m128 and stores the result
in xmm1.
Computes Square Roots of the packed double-precision
floating-point values in xmm2/m128 and stores the result
in xmm1.
Computes Square Roots of the packed double-precision
floating-point values in ymm2/m256 and stores the result
in ymm1.
Computes Square Roots of the packed double-precision
floating-point values in xmm2/m128/m64bcst and stores
the result in xmm1 subject to writemask k1.
Computes Square Roots of the packed double-precision
floating-point values in ymm2/m256/m64bcst and stores
the result in ymm1 subject to writemask k1.
Computes Square Roots of the packed double-precision
floating-point values in zmm2/m512/m64bcst and stores
the result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Performs a SIMD computation of the square roots of the two, four or eight packed double-precision floating-point
values in the source operand (the second operand) stores the packed double-precision floating-point results in the
destination operand (the first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM
register destination are unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
4-632 Vol. 2B
SQRTPD—Square Root of Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
VSQRTPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+63:i] SQRT(SRC[63:0])
ELSE DEST[i+63:i] SQRT(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSQRTPD (VEX.256 encoded version)
DEST[63:0] SQRT(SRC[63:0])
DEST[127:64] SQRT(SRC[127:64])
DEST[191:128] SQRT(SRC[191:128])
DEST[255:192] SQRT(SRC[255:192])
DEST[MAX_VL-1:256] 0
.
VSQRTPD (VEX.128 encoded version)
DEST[63:0] SQRT(SRC[63:0])
DEST[127:64] SQRT(SRC[127:64])
DEST[MAX_VL-1:128] 0
SQRTPD (128-bit Legacy SSE version)
DEST[63:0] SQRT(SRC[63:0])
DEST[127:64] SQRT(SRC[127:64])
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSQRTPD __m512d _mm512_sqrt_round_pd(__m512d a, int r);
VSQRTPD __m512d _mm512_mask_sqrt_round_pd(__m512d s, __mmask8 k, __m512d a, int r);
VSQRTPD __m512d _mm512_maskz_sqrt_round_pd( __mmask8 k, __m512d a, int r);
VSQRTPD __m256d _mm256_sqrt_pd (__m256d a);
VSQRTPD __m256d _mm256_mask_sqrt_pd(__m256d s, __mmask8 k, __m256d a, int r);
VSQRTPD __m256d _mm256_maskz_sqrt_pd( __mmask8 k, __m256d a, int r);
SQRTPD __m128d _mm_sqrt_pd (__m128d a);
VSQRTPD __m128d _mm_mask_sqrt_pd(__m128d s, __mmask8 k, __m128d a, int r);
VSQRTPD __m128d _mm_maskz_sqrt_pd( __mmask8 k, __m128d a, int r);
SQRTPD—Square Root of Double-Precision Floating-Point Values
Vol. 2B 4-633
INSTRUCTION SET REFERENCE, M-U
SIMD Floating-Point Exceptions
Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E2.
#UD
4-634 Vol. 2B
If EVEX.vvvv != 1111B.
SQRTPD—Square Root of Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
SQRTPS—Square Root of Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 51 /r
SQRTPS xmm1, xmm2/m128
VEX.128.0F.WIG 51 /r
VSQRTPS xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.0F.WIG 51/r
VSQRTPS ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.0F.W0 51 /r
VSQRTPS xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.0F.W0 51 /r
VSQRTPS ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.0F.W0 51/r
VSQRTPS zmm1 {k1}{z},
zmm2/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Computes Square Roots of the packed single-precision
floating-point values in xmm2/m128 and stores the result in
xmm1.
Computes Square Roots of the packed single-precision
floating-point values in xmm2/m128 and stores the result in
xmm1.
Computes Square Roots of the packed single-precision
floating-point values in ymm2/m256 and stores the result in
ymm1.
Computes Square Roots of the packed single-precision
floating-point values in xmm2/m128/m32bcst and stores
the result in xmm1 subject to writemask k1.
Computes Square Roots of the packed single-precision
floating-point values in ymm2/m256/m32bcst and stores
the result in ymm1 subject to writemask k1.
Computes Square Roots of the packed single-precision
floating-point values in zmm2/m512/m32bcst and stores
the result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Performs a SIMD computation of the square roots of the four, eight or sixteen packed single-precision floating-point
values in the source operand (second operand) stores the packed single-precision floating-point results in the
destination operand.
EVEX.512 encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location
or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM
register destination are unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
SQRTPS—Square Root of Single-Precision Floating-Point Values
Vol. 2B 4-635
INSTRUCTION SET REFERENCE, M-U
Operation
VSQRTPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+31:i] SQRT(SRC[31:0])
ELSE DEST[i+31:i] SQRT(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSQRTPS (VEX.256 encoded version)
DEST[31:0] SQRT(SRC[31:0])
DEST[63:32] SQRT(SRC[63:32])
DEST[95:64] SQRT(SRC[95:64])
DEST[127:96] SQRT(SRC[127:96])
DEST[159:128] SQRT(SRC[159:128])
DEST[191:160] SQRT(SRC[191:160])
DEST[223:192] SQRT(SRC[223:192])
DEST[255:224] SQRT(SRC[255:224])
VSQRTPS (VEX.128 encoded version)
DEST[31:0] SQRT(SRC[31:0])
DEST[63:32] SQRT(SRC[63:32])
DEST[95:64] SQRT(SRC[95:64])
DEST[127:96] SQRT(SRC[127:96])
DEST[MAX_VL-1:128] 0
SQRTPS (128-bit Legacy SSE version)
DEST[31:0] SQRT(SRC[31:0])
DEST[63:32] SQRT(SRC[63:32])
DEST[95:64] SQRT(SRC[95:64])
DEST[127:96] SQRT(SRC[127:96])
DEST[MAX_VL-1:128] (Unmodified)
4-636 Vol. 2B
SQRTPS—Square Root of Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VSQRTPS __m512 _mm512_sqrt_round_ps(__m512 a, int r);
VSQRTPS __m512 _mm512_mask_sqrt_round_ps(__m512 s, __mmask16 k, __m512 a, int r);
VSQRTPS __m512 _mm512_maskz_sqrt_round_ps( __mmask16 k, __m512 a, int r);
VSQRTPS __m256 _mm256_sqrt_ps (__m256 a);
VSQRTPS __m256 _mm256_mask_sqrt_ps(__m256 s, __mmask8 k, __m256 a, int r);
VSQRTPS __m256 _mm256_maskz_sqrt_ps( __mmask8 k, __m256 a, int r);
SQRTPS __m128 _mm_sqrt_ps (__m128 a);
VSQRTPS __m128 _mm_mask_sqrt_ps(__m128 s, __mmask8 k, __m128 a, int r);
VSQRTPS __m128 _mm_maskz_sqrt_ps( __mmask8 k, __m128 a, int r);
SIMD Floating-Point Exceptions
Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E2.
#UD
If EVEX.vvvv != 1111B.
SQRTPS—Square Root of Single-Precision Floating-Point Values
Vol. 2B 4-637
INSTRUCTION SET REFERENCE, M-U
SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
F2 0F 51/r
SQRTSD xmm1,xmm2/m64
VEX.NDS.128.F2.0F.WIG 51/r
VSQRTSD xmm1,xmm2,
xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 51/r
VSQRTSD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Computes square root of the low double-precision floatingpoint value in xmm2/m64 and stores the results in xmm1.
Computes square root of the low double-precision floatingpoint value in xmm3/m64 and stores the results in xmm1.
Also, upper double-precision floating-point value
(bits[127:64]) from xmm2 is copied to xmm1[127:64].
Computes square root of the low double-precision floatingpoint value in xmm3/m64 and stores the results in xmm1
under writemask k1. Also, upper double-precision floatingpoint value (bits[127:64]) from xmm2 is copied to
xmm1[127:64].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Computes the square root of the low double-precision floating-point value in the second source operand and stores
the double-precision floating-point result in the destination operand. The second source operand can be an XMM
register or a 64-bit memory location. The first source and destination operands are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at
bits 127:64 of the destination operand remains unchanged. Bits (MAX_VL-1:64) of the corresponding destination
register remain unchanged.
VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding
bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
4-638 Vol. 2B
SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Operation
VSQRTSD (EVEX encoded version)
IF (EVEX.b = 1) AND (SRC2 *is register*)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] SQRT(SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VSQRTSD (VEX.128 encoded version)
DEST[63:0] SQRT(SRC2[63:0])
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
SQRTSD (128-bit Legacy SSE version)
DEST[63:0] SQRT(SRC[63:0])
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);
VSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);
VSQRTSD __m128d _mm_maskz_sqrt_round_sd(__mmask8 k, __m128d a, __m128d b, int r);
SQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value
Vol. 2B 4-639
INSTRUCTION SET REFERENCE, M-U
SQRTSS—Compute Square Root of Scalar Single-Precision Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 51 /r
SQRTSS xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 51 /r
VSQRTSS xmm1, xmm2,
xmm3/m32
RVM
V/V
AVX
EVEX.NDS.LIG.F3.0F.W0 51 /r
VSQRTSS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
T1S
V/V
AVX512F
Description
Computes square root of the low single-precision floating-point
value in xmm2/m32 and stores the results in xmm1.
Computes square root of the low single-precision floating-point
value in xmm3/m32 and stores the results in xmm1. Also,
upper single-precision floating-point values (bits[127:32]) from
xmm2 are copied to xmm1[127:32].
Computes square root of the low single-precision floating-point
value in xmm3/m32 and stores the results in xmm1 under
writemask k1. Also, upper single-precision floating-point values
(bits[127:32]) from xmm2 are copied to xmm1[127:32].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Computes the square root of the low single-precision floating-point value in the second source operand and stores
the single-precision floating-point result in the destination operand. The second source operand can be an XMM
register or a 32-bit memory location. The first source and destination operands is an XMM register.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 and EVEX encoded versions: Bits 127:32 of the destination operand are copied from the corresponding
bits of the first source operand. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VSQRTSS is encoded with VEX.L=0. Encoding VSQRTSS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
4-640 Vol. 2B
SQRTSS—Compute Square Root of Scalar Single-Precision Value
INSTRUCTION SET REFERENCE, M-U
Operation
VSQRTSS (EVEX encoded version)
IF (EVEX.b = 1) AND (SRC2 *is register*)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] SQRT(SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI;
FI;
DEST[127:31] SRC1[127:31]
DEST[MAX_VL-1:128] 0
VSQRTSS (VEX.128 encoded version)
DEST[31:0] SQRT(SRC2[31:0])
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
SQRTSS (128-bit Legacy SSE version)
DEST[31:0] SQRT(SRC2[31:0])
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSQRTSS __m128 _mm_sqrt_round_ss(__m128 a, __m128 b, int r);
VSQRTSS __m128 _mm_mask_sqrt_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int r);
VSQRTSS __m128 _mm_maskz_sqrt_round_ss( __mmask8 k, __m128 a, __m128 b, int r);
SQRTSS __m128 _mm_sqrt_ss(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision, Denormal
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
SQRTSS—Compute Square Root of Scalar Single-Precision Value
Vol. 2B 4-641
INSTRUCTION SET REFERENCE, M-U
STAC—Set AC Flag in EFLAGS Register
Opcode/
Instruction
Op /
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 01 CB
NP
V/V
SMAP
Set the AC flag in the EFLAGS register.
STAC
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Sets the AC flag bit in EFLAGS register. This may enable alignment checking of user-mode data accesses. This
allows explicit supervisor-mode data accesses to user-mode pages even if the SMAP bit is set in the CR4 register.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute STAC when
CPL > 0 cause #UD.
Operation
EFLAGS.AC ← 1;
Flags Affected
AC set. Other flags are unaffected.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
Virtual-8086 Mode Exceptions
#UD
The STAC instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
4-642 Vol. 2B
STAC—Set AC Flag in EFLAGS Register
INSTRUCTION SET REFERENCE, M-U
STC—Set Carry Flag
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F9
STC
NP
Valid
Valid
Set CF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Sets the CF flag in the EFLAGS register. Operation is the same in all modes.
Operation
CF ← 1;
Flags Affected
The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
STC—Set Carry Flag
If the LOCK prefix is used.
Vol. 2B 4-643
INSTRUCTION SET REFERENCE, M-U
STD—Set Direction Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
FD
STD
NP
Valid
Valid
Set DF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index registers (ESI and/or EDI). Operation is the same in all modes.
Operation
DF ← 1;
Flags Affected
The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
4-644 Vol. 2B
If the LOCK prefix is used.
STD—Set Direction Flag
INSTRUCTION SET REFERENCE, M-U
STI—Set Interrupt Flag
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
FB
STI
NP
Valid
Valid
Set interrupt flag; external, maskable
interrupts enabled at the end of the next
instruction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
If protected-mode virtual interrupts are not enabled, STI sets the interrupt flag (IF) in the EFLAGS register. After
the IF flag is set, the processor begins responding to external, maskable interrupts after the next instruction is
executed. The delayed effect of this instruction is provided to allow interrupts to be enabled just before returning
from a procedure (or subroutine). For instance, if an STI instruction is followed by an RET instruction, the RET
instruction is allowed to execute before external interrupts are recognized1. If the STI instruction is followed by a
CLI instruction (which clears the IF flag), the effect of the STI instruction is negated.
The IF flag and the STI and CLI instructions do not prohibit the generation of exceptions and NMI interrupts. NMI
interrupts (and SMIs) may be blocked for one macroinstruction following an STI.
When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; STI sets the VIF flag in the
EFLAGS register, leaving IF unaffected.
Table 4-19 indicates the action of the STI instruction depending on the processor’s mode of operation and the
CPL/IOPL settings of the running program or procedure.
Operation is the same in all modes.
Table 4-19. Decision Table for STI Results
CR0.PE
EFLAGS.VM
EFLAGS.IOPL
CS.CPL
CR4.PVI
EFLAGS.VIP
CR4.VME
STI Result
0
X
X
X
X
X
X
IF = 1
1
0
≥ CPL
X
X
X
X
IF = 1
1
0
< CPL
3
1
X
X
VIF = 1
1
0
< CPL
<3
X
X
X
GP Fault
1
0
< CPL
X
0
X
X
GP Fault
1
0
< CPL
X
X
1
X
GP Fault
1
1
3
X
X
X
X
IF = 1
1
1
<3
X
X
0
1
VIF = 1
1
1
<3
X
X
1
X
GP Fault
1
1
<3
X
X
X
0
GP Fault
NOTES:
X = This setting has no impact.
1. The STI instruction delays recognition of interrupts only if it is executed with EFLAGS.IF = 0. In a sequence of STI instructions, only
the first instruction in the sequence is guaranteed to delay interrupts.
In the following instruction sequence, interrupts may be recognized before RET executes:
STI
STI
RET
STI—Set Interrupt Flag
Vol. 2B 4-645
INSTRUCTION SET REFERENCE, M-U
Operation
IF PE = 0 (* Executing in real-address mode *)
THEN
IF ← 1; (* Set Interrupt Flag *)
ELSE (* Executing in protected mode or virtual-8086 mode *)
IF VM = 0 (* Executing in protected mode*)
THEN
IF IOPL ≥ CPL
THEN
IF ← 1; (* Set Interrupt Flag *)
ELSE
IF (IOPL < CPL) and (CPL = 3) and (PVI = 1)
THEN
VIF ← 1; (* Set Virtual Interrupt Flag *)
ELSE
#GP(0);
FI;
FI;
ELSE (* Executing in Virtual-8086 mode *)
IF IOPL = 3
THEN
IF ← 1; (* Set Interrupt Flag *)
ELSE
IF ((IOPL < 3) and (VIP = 0) and (VME = 1))
THEN
VIF ← 1; (* Set Virtual Interrupt Flag *)
ELSE
#GP(0); (* Trap to virtual-8086 monitor *)
FI;)
FI;
FI;
FI;
Flags Affected
The IF flag is set to 1; or the VIF flag is set to 1. Other flags are unaffected.
Protected Mode Exceptions
#GP(0)
If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-646 Vol. 2B
STI—Set Interrupt Flag
INSTRUCTION SET REFERENCE, M-U
STMXCSR—Store MXCSR Register State
Opcode*/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F AE /3
M
V/V
SSE
Store contents of MXCSR register to m32.
M
V/V
AVX
Store contents of MXCSR register to m32.
STMXCSR m32
VEX.LZ.0F.WIG AE /3
VSTMXCSR m32
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Stores the contents of the MXCSR control and status register to the destination operand. The destination operand
is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
VEX.L must be 0, otherwise instructions will #UD.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
m32 ← MXCSR;
Intel C/C++ Compiler Intrinsic Equivalent
_mm_getcsr(void)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 5; additionally
#UD
If VEX.L= 1,
If VEX.vvvv ≠ 1111B.
STMXCSR—Store MXCSR Register State
Vol. 2B 4-647
INSTRUCTION SET REFERENCE, M-U
STOS/STOSB/STOSW/STOSD/STOSQ—Store String
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
AA
STOS m8
NA
Valid
Valid
For legacy mode, store AL at address ES:(E)DI;
For 64-bit mode store AL at address RDI or
EDI.
AB
STOS m16
NA
Valid
Valid
For legacy mode, store AX at address ES:(E)DI;
For 64-bit mode store AX at address RDI or
EDI.
AB
STOS m32
NA
Valid
Valid
For legacy mode, store EAX at address
ES:(E)DI; For 64-bit mode store EAX at address
RDI or EDI.
REX.W + AB
STOS m64
NA
Valid
N.E.
Store RAX at address RDI or EDI.
AA
STOSB
NA
Valid
Valid
For legacy mode, store AL at address ES:(E)DI;
For 64-bit mode store AL at address RDI or
EDI.
AB
STOSW
NA
Valid
Valid
For legacy mode, store AX at address ES:(E)DI;
For 64-bit mode store AX at address RDI or
EDI.
AB
STOSD
NA
Valid
Valid
For legacy mode, store EAX at address
ES:(E)DI; For 64-bit mode store EAX at address
RDI or EDI.
REX.W + AB
STOSQ
NA
Valid
N.E.
Store RAX at address RDI or EDI.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NA
NA
NA
NA
NA
Description
In non-64-bit and default 64-bit mode; stores a byte, word, or doubleword from the AL, AX, or EAX register
(respectively) into the destination operand. The destination operand is a memory location, the address of which is
read from either the ES:EDI or ES:DI register (depending on the address-size attribute of the instruction and the
mode of operation). The ES segment cannot be overridden with a segment override prefix.
At the assembly-code level, two forms of the instruction are allowed: the “explicit-operands” form and the “nooperands” form. The explicit-operands form (specified with the STOS mnemonic) allows the destination operand to
be specified explicitly. Here, the destination operand should be a symbol that indicates the size and location of the
destination value. The source operand is then automatically selected to match the size of the destination operand
(the AL register for byte operands, AX for word operands, EAX for doubleword operands). The explicit-operands
form is provided to allow documentation; however, note that the documentation provided by this form can be
misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte,
word, or doubleword), but it does not have to specify the correct location. The location is always specified by the
ES:(E)DI register. These must be loaded correctly before the store string instruction is executed.
The no-operands form provides “short forms” of the byte, word, doubleword, and quadword versions of the STOS
instructions. Here also ES:(E)DI is assumed to be the destination operand and AL, AX, or EAX is assumed to be the
source operand. The size of the destination and source operands is selected by the mnemonic: STOSB (byte read
from register AL), STOSW (word from AX), STOSD (doubleword from EAX).
After the byte, word, or doubleword is transferred from the register to the memory location, the (E)DI register is
incremented or decremented according to the setting of the DF flag in the EFLAGS register. If the DF flag is 0, the
register is incremented; if the DF flag is 1, the register is decremented (the register is incremented or decremented
by 1 for byte operations, by 2 for word operations, by 4 for doubleword operations).
4-648 Vol. 2B
STOS/STOSB/STOSW/STOSD/STOSQ—Store String
INSTRUCTION SET REFERENCE, M-U
NOTE: To improve performance, more recent processors support modifications to the processor’s operation during
the string store operations initiated with STOS and STOSB. See Section 7.3.9.3 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for additional information on fast-string operation.
In 64-bit mode, the default address size is 64 bits, 32-bit address size is supported using the prefix 67H. Using a
REX prefix in the form of REX.W promotes operation on doubleword operand to 64 bits. The promoted no-operand
mnemonic is STOSQ. STOSQ (and its explicit operands variant) store a quadword from the RAX register into the
destination addressed by RDI or EDI. See the summary chart at the beginning of this section for encoding data and
limits.
The STOS, STOSB, STOSW, STOSD, STOSQ instructions can be preceded by the REP prefix for block loads of ECX
bytes, words, or doublewords. More often, however, these instructions are used within a LOOP construct because
data needs to be moved into the AL, AX, or EAX register before it can be stored. See “REP/REPE/REPZ
/REPNE/REPNZ—Repeat String Operation Prefix” in this chapter for a description of the REP prefix.
Operation
Non-64-bit Mode:
IF (Byte store)
THEN
DEST ← AL;
THEN IF DF = 0
THEN (E)DI ← (E)DI + 1;
ELSE (E)DI ← (E)DI – 1;
FI;
ELSE IF (Word store)
THEN
DEST ← AX;
THEN IF DF = 0
THEN (E)DI ← (E)DI + 2;
ELSE (E)DI ← (E)DI – 2;
FI;
FI;
ELSE IF (Doubleword store)
THEN
DEST ← EAX;
THEN IF DF = 0
THEN (E)DI ← (E)DI + 4;
ELSE (E)DI ← (E)DI – 4;
FI;
FI;
FI;
64-bit Mode:
IF (Byte store)
THEN
DEST ← AL;
THEN IF DF = 0
THEN (R|E)DI ← (R|E)DI + 1;
ELSE (R|E)DI ← (R|E)DI – 1;
FI;
ELSE IF (Word store)
THEN
DEST ← AX;
STOS/STOSB/STOSW/STOSD/STOSQ—Store String
Vol. 2B 4-649
INSTRUCTION SET REFERENCE, M-U
THEN IF DF = 0
THEN (R|E)DI ← (R|E)DI + 2;
ELSE (R|E)DI ← (R|E)DI – 2;
FI;
FI;
ELSE IF (Doubleword store)
THEN
DEST ← EAX;
THEN IF DF = 0
THEN (R|E)DI ← (R|E)DI + 4;
ELSE (R|E)DI ← (R|E)DI – 4;
FI;
FI;
ELSE IF (Quadword store using REX.W )
THEN
DEST ← RAX;
THEN IF DF = 0
THEN (R|E)DI ← (R|E)DI + 8;
ELSE (R|E)DI ← (R|E)DI – 8;
FI;
FI;
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the limit of the ES segment.
If the ES register contains a NULL segment selector.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the ES segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the ES segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
4-650 Vol. 2B
If the memory address is in a non-canonical form.
STOS/STOSB/STOSW/STOSD/STOSQ—Store String
INSTRUCTION SET REFERENCE, M-U
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
STOS/STOSB/STOSW/STOSD/STOSQ—Store String
Vol. 2B 4-651
INSTRUCTION SET REFERENCE, M-U
STR—Store Task Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 00 /1
STR r/m16
M
Valid
Valid
Stores segment selector from TR in r/m16.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be
a general-purpose register or a memory location. The segment selector stored with this instruction points to the
task state segment (TSS) for the currently running task.
When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the
register and the upper 16 bits of the register are cleared. When the destination operand is a memory location, the
segment selector is written to memory as a 16-bit quantity, regardless of operand size.
In 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits. In register stores, the 2byte TR is zero extended if stored to a 64-bit register.
The STR instruction is useful only in operating-system software. It can only be executed in protected mode.
Operation
DEST ← TR(SegmentSelector);
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the destination is a memory operand that is located in a non-writable segment or if the
effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If CR4.UMIP = 1 and CPL > 0.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The STR instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The STR instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
4-652 Vol. 2B
STR—Store Task Register
INSTRUCTION SET REFERENCE, M-U
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
If CR4.UMIP = 1 and CPL > 0.
#SS(0)
If the stack address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
STR—Store Task Register
Vol. 2B 4-653
INSTRUCTION SET REFERENCE, M-U
SUB—Subtract
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
2C ib
SUB AL, imm8
I
Valid
Valid
Subtract imm8 from AL.
2D iw
SUB AX, imm16
I
Valid
Valid
Subtract imm16 from AX.
2D id
SUB EAX, imm32
I
Valid
Valid
Subtract imm32 from EAX.
REX.W + 2D id
SUB RAX, imm32
I
Valid
N.E.
Subtract imm32 sign-extended to 64-bits
from RAX.
80 /5 ib
SUB r/m8, imm8
MI
Valid
Valid
Subtract imm8 from r/m8.
REX + 80 /5 ib
SUB r/m8*, imm8
MI
Valid
N.E.
Subtract imm8 from r/m8.
81 /5 iw
SUB r/m16, imm16
MI
Valid
Valid
Subtract imm16 from r/m16.
81 /5 id
SUB r/m32, imm32
MI
Valid
Valid
Subtract imm32 from r/m32.
REX.W + 81 /5 id
SUB r/m64, imm32
MI
Valid
N.E.
Subtract imm32 sign-extended to 64-bits
from r/m64.
83 /5 ib
SUB r/m16, imm8
MI
Valid
Valid
Subtract sign-extended imm8 from r/m16.
83 /5 ib
SUB r/m32, imm8
MI
Valid
Valid
Subtract sign-extended imm8 from r/m32.
REX.W + 83 /5 ib
SUB r/m64, imm8
MI
Valid
N.E.
Subtract sign-extended imm8 from r/m64.
28 /r
SUB r/m8, r8
MR
Valid
Valid
Subtract r8 from r/m8.
REX + 28 /r
SUB r/m8*, r8*
MR
Valid
N.E.
Subtract r8 from r/m8.
29 /r
SUB r/m16, r16
MR
Valid
Valid
Subtract r16 from r/m16.
29 /r
SUB r/m32, r32
MR
Valid
Valid
Subtract r32 from r/m32.
REX.W + 29 /r
SUB r/m64, r64
MR
Valid
N.E.
Subtract r64 from r/m64.
2A /r
SUB r8, r/m8
RM
Valid
Valid
Subtract r/m8 from r8.
REX + 2A /r
SUB r8*, r/m8*
RM
Valid
N.E.
Subtract r/m8 from r8.
2B /r
SUB r16, r/m16
RM
Valid
Valid
Subtract r/m16 from r16.
2B /r
SUB r32, r/m32
RM
Valid
Valid
Subtract r/m32 from r32.
REX.W + 2B /r
SUB r64, r/m64
RM
Valid
N.E.
Subtract r/m64 from r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
I
AL/AX/EAX/RAX
imm8/26/32
NA
NA
MI
ModRM:r/m (r, w)
imm8/26/32
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result
in the destination operand. The destination operand can be a register or a memory location; the source operand
can be an immediate, register, or memory location. (However, two memory operands cannot be used in one
instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination
operand format.
4-654 Vol. 2B
SUB—Subtract
INSTRUCTION SET REFERENCE, M-U
The SUB instruction performs integer subtraction. It evaluates the result for both signed and unsigned integer
operands and sets the OF and CF flags to indicate an overflow in the signed or unsigned result, respectively. The SF
flag indicates the sign of the signed result.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
Operation
DEST ← (DEST – SRC);
Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
SUB—Subtract
Vol. 2B 4-655
INSTRUCTION SET REFERENCE, M-U
SUBPD—Subtract Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op/
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5C /r
SUBPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 5C /r
VSUBPD xmm1,xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG 5C /r
VSUBPD ymm1, ymm2, ymm3/m256
EVEX.NDS.128.66.0F.W1 5C /r
VSUBPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 5C /r
VSUBPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 5C /r
VSUBPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Subtract packed double-precision floating-point values
in xmm2/mem from xmm1 and store result in xmm1.
Subtract packed double-precision floating-point values
in xmm3/mem from xmm2 and store result in xmm1.
Subtract packed double-precision floating-point values
in ymm3/mem from ymm2 and store result in ymm1.
Subtract packed double-precision floating-point values
from xmm3/m128/m64bcst to xmm2 and store result
in xmm1 with writemask k1.
Subtract packed double-precision floating-point values
from ymm3/m256/m64bcst to ymm2 and store result
in ymm1 with writemask k1.
Subtract packed double-precision floating-point values
from zmm3/m512/m64bcst to zmm2 and store result in
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD subtract of the two, four or eight packed double-precision floating-point values of the second
Source operand from the first Source operand, and stores the packed double-precision floating-point results in the
destination operand.
VEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory
location. The first source operand and destination operands are XMM registers. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory
location. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit
vector broadcasted from a 64-bit memory location. The first source operand and destination operands are ZMM
registers. The destination operand is conditionally updated according to the writemask.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
4-656 Vol. 2B
SUBPD—Subtract Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
VSUBPD (EVEX encoded versions) when src2 operand is a vector register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC1[i+63:i] - SRC2[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSUBPD (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i] SRC1[i+63:i] - SRC2[63:0];
ELSE
EST[i+63:i] SRC1[i+63:i] - SRC2[i+63:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSUBPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] - SRC2[63:0]
DEST[127:64] SRC1[127:64] - SRC2[127:64]
DEST[191:128] SRC1[191:128] - SRC2[191:128]
DEST[255:192] SRC1[255:192] - SRC2[255:192]
DEST[MAX_VL-1:256] 0
SUBPD—Subtract Packed Double-Precision Floating-Point Values
Vol. 2B 4-657
INSTRUCTION SET REFERENCE, M-U
VSUBPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] - SRC2[63:0]
DEST[127:64] SRC1[127:64] - SRC2[127:64]
DEST[MAX_VL-1:128] 0
SUBPD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] - SRC[63:0]
DEST[127:64] DEST[127:64] - SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSUBPD __m512d _mm512_sub_pd (__m512d a, __m512d b);
VSUBPD __m512d _mm512_mask_sub_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VSUBPD __m512d _mm512_maskz_sub_pd (__mmask8 k, __m512d a, __m512d b);
VSUBPD __m512d _mm512_sub_round_pd (__m512d a, __m512d b, int);
VSUBPD __m512d _mm512_mask_sub_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VSUBPD __m512d _mm512_maskz_sub_round_pd (__mmask8 k, __m512d a, __m512d b, int);
VSUBPD __m256d _mm256_sub_pd (__m256d a, __m256d b);
VSUBPD __m256d _mm256_mask_sub_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VSUBPD __m256d _mm256_maskz_sub_pd (__mmask8 k, __m256d a, __m256d b);
SUBPD __m128d _mm_sub_pd (__m128d a, __m128d b);
VSUBPD __m128d _mm_mask_sub_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VSUBPD __m128d _mm_maskz_sub_pd (__mmask8 k, __m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
4-658 Vol. 2B
SUBPD—Subtract Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
SUBPS—Subtract Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op/
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 5C /r
SUBPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 5C /r
VSUBPS xmm1,xmm2, xmm3/m128
VEX.NDS.256.0F.WIG 5C /r
VSUBPS ymm1, ymm2, ymm3/m256
EVEX.NDS.128.0F.W0 5C /r
VSUBPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 5C /r
VSUBPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 5C /r
VSUBPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{er}
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Subtract packed single-precision floating-point values
in xmm2/mem from xmm1 and store result in xmm1.
Subtract packed single-precision floating-point values
in xmm3/mem from xmm2 and stores result in xmm1.
Subtract packed single-precision floating-point values
in ymm3/mem from ymm2 and stores result in ymm1.
Subtract packed single-precision floating-point values
from xmm3/m128/m32bcst to xmm2 and stores
result in xmm1 with writemask k1.
Subtract packed single-precision floating-point values
from ymm3/m256/m32bcst to ymm2 and stores
result in ymm1 with writemask k1.
Subtract packed single-precision floating-point values
in zmm3/m512/m32bcst from zmm2 and stores result
in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD subtract of the packed single-precision floating-point values in the second Source operand from
the First Source operand, and stores the packed single-precision floating-point results in the destination operand.
VEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory
location. The first source operand and destination operands are XMM registers. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory
location. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit
vector broadcasted from a 32-bit memory location. The first source operand and destination operands are ZMM
registers. The destination operand is conditionally updated according to the writemask.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
SUBPS—Subtract Packed Single-Precision Floating-Point Values
Vol. 2B 4-659
INSTRUCTION SET REFERENCE, M-U
Operation
VSUBPS (EVEX encoded versions) when src2 operand is a vector register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC1[i+31:i] - SRC2[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VSUBPS (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (4, 128), (8, 256),(16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] SRC1[i+31:i] - SRC2[31:0];
ELSE
DEST[i+31:i] SRC1[i+31:i] - SRC2[i+31:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VSUBPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] - SRC2[31:0]
DEST[63:32] SRC1[63:32] - SRC2[63:32]
DEST[95:64] SRC1[95:64] - SRC2[95:64]
DEST[127:96] SRC1[127:96] - SRC2[127:96]
DEST[159:128] SRC1[159:128] - SRC2[159:128]
DEST[191:160] SRC1[191:160] - SRC2[191:160]
DEST[223:192] SRC1[223:192] - SRC2[223:192]
DEST[255:224] SRC1[255:224] - SRC2[255:224].
DEST[MAX_VL-1:256] 0
4-660 Vol. 2B
SUBPS—Subtract Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
VSUBPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] - SRC2[31:0]
DEST[63:32] SRC1[63:32] - SRC2[63:32]
DEST[95:64] SRC1[95:64] - SRC2[95:64]
DEST[127:96] SRC1[127:96] - SRC2[127:96]
DEST[MAX_VL-1:128] 0
SUBPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] - SRC2[31:0]
DEST[63:32] SRC1[63:32] - SRC2[63:32]
DEST[95:64] SRC1[95:64] - SRC2[95:64]
DEST[127:96] SRC1[127:96] - SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSUBPS __m512 _mm512_sub_ps (__m512 a, __m512 b);
VSUBPS __m512 _mm512_mask_sub_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VSUBPS __m512 _mm512_maskz_sub_ps (__mmask16 k, __m512 a, __m512 b);
VSUBPS __m512 _mm512_sub_round_ps (__m512 a, __m512 b, int);
VSUBPS __m512 _mm512_mask_sub_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VSUBPS __m512 _mm512_maskz_sub_round_ps (__mmask16 k, __m512 a, __m512 b, int);
VSUBPS __m256 _mm256_sub_ps (__m256 a, __m256 b);
VSUBPS __m256 _mm256_mask_sub_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VSUBPS __m256 _mm256_maskz_sub_ps (__mmask16 k, __m256 a, __m256 b);
SUBPS __m128 _mm_sub_ps (__m128 a, __m128 b);
VSUBPS __m128 _mm_mask_sub_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VSUBPS __m128 _mm_maskz_sub_ps (__mmask16 k, __m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
SUBPS—Subtract Packed Single-Precision Floating-Point Values
Vol. 2B 4-661
INSTRUCTION SET REFERENCE, M-U
SUBSD—Subtract Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 5C /r
SUBSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 5C /r
VSUBSD xmm1,xmm2, xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 5C /r
VSUBSD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Subtract the low double-precision floating-point value in
xmm2/m64 from xmm1 and store the result in xmm1.
Subtract the low double-precision floating-point value in
xmm3/m64 from xmm2 and store the result in xmm1.
Subtract the low double-precision floating-point value in
xmm3/m64 from xmm2 and store the result in xmm1
under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Subtract the low double-precision floating-point value in the second source operand from the first source operand
and stores the double-precision floating-point result in the low quadword of the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VSUBSD is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
4-662 Vol. 2B
SUBSD—Subtract Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Operation
VSUBSD (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] SRC1[63:0] - SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VSUBSD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] - SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
SUBSD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] - SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSUBSD __m128d _mm_mask_sub_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VSUBSD __m128d _mm_maskz_sub_sd (__mmask8 k, __m128d a, __m128d b);
VSUBSD __m128d _mm_sub_round_sd (__m128d a, __m128d b, int);
VSUBSD __m128d _mm_mask_sub_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VSUBSD __m128d _mm_maskz_sub_round_sd (__mmask8 k, __m128d a, __m128d b, int);
SUBSD __m128d _mm_sub_sd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
SUBSD—Subtract Scalar Double-Precision Floating-Point Value
Vol. 2B 4-663
INSTRUCTION SET REFERENCE, M-U
SUBSS—Subtract Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 5C /r
SUBSS xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 5C /r
VSUBSS xmm1,xmm2, xmm3/m32
EVEX.NDS.LIG.F3.0F.W0 5C /r
VSUBSS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Subtract the low single-precision floating-point value in
xmm2/m32 from xmm1 and store the result in xmm1.
Subtract the low single-precision floating-point value in
xmm3/m32 from xmm2 and store the result in xmm1.
Subtract the low single-precision floating-point value in
xmm3/m32 from xmm2 and store the result in xmm1
under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Subtract the low single-precision floating-point value from the second source operand and the first source operand
and store the double-precision floating-point result in the low doubleword of the destination operand.
The second source operand can be an XMM register or a 32-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:32) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VSUBSS is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
4-664 Vol. 2B
SUBSS—Subtract Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, M-U
Operation
VSUBSS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] SRC1[31:0] - SRC2[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VSUBSS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] - SRC2[31:0]
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
SUBSS (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0] - SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSUBSS __m128 _mm_mask_sub_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_maskz_sub_ss (__mmask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_sub_round_ss (__m128 a, __m128 b, int);
VSUBSS __m128 _mm_mask_sub_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSUBSS __m128 _mm_maskz_sub_round_ss (__mmask8 k, __m128 a, __m128 b, int);
SUBSS __m128 _mm_sub_ss (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
SUBSS—Subtract Scalar Single-Precision Floating-Point Value
Vol. 2B 4-665
INSTRUCTION SET REFERENCE, M-U
SWAPGS—Swap GS Base Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 F8
SWAPGS
NP
Valid
Invalid
Exchanges the current GS base register value
with the value contained in MSR address
C0000102H.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
SWAPGS exchanges the current GS base register value with the value contained in MSR address C0000102H
(IA32_KERNEL_GS_BASE). The SWAPGS instruction is a privileged instruction intended for use by system software.
When using SYSCALL to implement system calls, there is no kernel stack at the OS entry point. Neither is there a
straightforward method to obtain a pointer to kernel structures from which the kernel stack pointer could be read.
Thus, the kernel cannot save general purpose registers or reference memory.
By design, SWAPGS does not require any general purpose registers or memory operands. No registers need to be
saved before using the instruction. SWAPGS exchanges the CPL 0 data pointer from the IA32_KERNEL_GS_BASE
MSR with the GS base register. The kernel can then use the GS prefix on normal memory references to access
kernel data structures. Similarly, when the OS kernel is entered using an interrupt or exception (where the kernel
stack is already set up), SWAPGS can be used to quickly get a pointer to the kernel data structures.
The IA32_KERNEL_GS_BASE MSR itself is only accessible using RDMSR/WRMSR instructions. Those instructions
are only accessible at privilege level 0. The WRMSR instruction ensures that the IA32_KERNEL_GS_BASE MSR
contains a canonical address.
Operation
IF CS.L ≠ 1 (* Not in 64-Bit Mode *)
THEN
#UD; FI;
IF CPL ≠ 0
THEN #GP(0); FI;
tmp ← GS.base;
GS.base ← IA32_KERNEL_GS_BASE;
IA32_KERNEL_GS_BASE ← tmp;
Flags Affected
None
Protected Mode Exceptions
#UD
If Mode
≠ 64-Bit.
Real-Address Mode Exceptions
#UD
If Mode
≠ 64-Bit.
Virtual-8086 Mode Exceptions
#UD
4-666 Vol. 2B
If Mode
≠ 64-Bit.
SWAPGS—Swap GS Base Register
INSTRUCTION SET REFERENCE, M-U
Compatibility Mode Exceptions
#UD
If Mode
≠ 64-Bit.
64-Bit Mode Exceptions
#GP(0)
If CPL
≠ 0.
If the LOCK prefix is used.
SWAPGS—Swap GS Base Register
Vol. 2B 4-667
INSTRUCTION SET REFERENCE, M-U
SYSCALL—Fast System Call
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 05
SYSCALL
NP
Valid
Invalid
Fast call to privilege level 0 system
procedures.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
SYSCALL invokes an OS system-call handler at privilege level 0. It does so by loading RIP from the IA32_LSTAR
MSR (after saving the address of the instruction following SYSCALL into RCX). (The WRMSR instruction ensures
that the IA32_LSTAR MSR always contain a canonical address.)
SYSCALL also saves RFLAGS into R11 and then masks RFLAGS using the IA32_FMASK MSR (MSR address
C0000084H); specifically, the processor clears in RFLAGS every bit corresponding to a bit that is set in the
IA32_FMASK MSR.
SYSCALL loads the CS and SS selectors with values derived from bits 47:32 of the IA32_STAR MSR. However, the
CS and SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors.
Instead, the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the fixed values loaded into the descriptor caches; the SYSCALL instruction does not ensure this
correspondence.
The SYSCALL instruction does not save the stack pointer (RSP). If the OS system-call handler will change the stack
pointer, it is the responsibility of software to save the previous value of the stack pointer. This might be done prior
to executing SYSCALL, with software restoring the stack pointer with the instruction following SYSCALL (which will
be executed after SYSRET). Alternatively, the OS system-call handler may save the stack pointer and restore it
before executing SYSRET.
Operation
IF (CS.L ≠ 1 ) or (IA32_EFER.LMA ≠ 1) or (IA32_EFER.SCE ≠ 1)
(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)
THEN #UD;
FI;
RCX ← RIP;
(* Will contain address of next instruction *)
RIP ← IA32_LSTAR;
R11 ← RFLAGS;
RFLAGS ← RFLAGS AND NOT(IA32_FMASK);
CS.Selector ← IA32_STAR[47:32] AND FFFCH (* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)
CS.Base ← 0;
(* Flat segment *)
CS.Limit ← FFFFFH;
(* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type ← 11;
(* Execute/read code, accessed *)
CS.S ← 1;
CS.DPL ← 0;
CS.P ← 1;
CS.L ← 1;
(* Entry is to 64-bit mode *)
CS.D ← 0;
(* Required if CS.L = 1 *)
CS.G ← 1;
(* 4-KByte granularity *)
CPL ← 0;
4-668 Vol. 2B
SYSCALL—Fast System Call
INSTRUCTION SET REFERENCE, M-U
SS.Selector ← IA32_STAR[47:32] + 8;
(* Set rest of SS to a fixed value *)
SS.Base ← 0;
SS.Limit ← FFFFFH;
SS.Type ← 3;
SS.S ← 1;
SS.DPL ← 0;
SS.P ← 1;
SS.B ← 1;
SS.G ← 1;
(* SS just above CS *)
(* Flat segment *)
(* With 4-KByte granularity, implies a 4-GByte limit *)
(* Read/write data, accessed *)
(* 32-bit stack segment *)
(* 4-KByte granularity *)
Flags Affected
All.
Protected Mode Exceptions
#UD
The SYSCALL instruction is not recognized in protected mode.
Real-Address Mode Exceptions
#UD
The SYSCALL instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The SYSCALL instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The SYSCALL instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#UD
If IA32_EFER.SCE = 0.
If the LOCK prefix is used.
SYSCALL—Fast System Call
Vol. 2B 4-669
INSTRUCTION SET REFERENCE, M-U
SYSENTER—Fast System Call
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 34
SYSENTER
NP
Valid
Valid
Fast call to privilege level 0 system
procedures.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Executes a fast call to a level 0 system procedure or routine. SYSENTER is a companion instruction to SYSEXIT. The
instruction is optimized to provide the maximum performance for system calls from user code running at privilege
level 3 to operating system or executive procedures running at privilege level 0.
When executed in IA-32e mode, the SYSENTER instruction transitions the logical processor to 64-bit mode; otherwise, the logical processor remains in protected mode.
Prior to executing the SYSENTER instruction, software must specify the privilege level 0 code segment and code
entry point, and the privilege level 0 stack segment and stack pointer by writing values to the following MSRs:
•
IA32_SYSENTER_CS (MSR address 174H) — The lower 16 bits of this MSR are the segment selector for the
privilege level 0 code segment. This value is also used to determine the segment selector of the privilege level
0 stack segment (see the Operation section). This value cannot indicate a null selector.
•
IA32_SYSENTER_EIP (MSR address 176H) — The value of this MSR is loaded into RIP (thus, this value
references the first instruction of the selected operating procedure or routine). In protected mode, only
bits 31:0 are loaded.
•
IA32_SYSENTER_ESP (MSR address 175H) — The value of this MSR is loaded into RSP (thus, this value
contains the stack pointer for the privilege level 0 stack). This value cannot represent a non-canonical address.
In protected mode, only bits 31:0 are loaded.
These MSRs can be read from and written to using RDMSR/WRMSR. The WRMSR instruction ensures that the
IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs always contain canonical addresses.
While SYSENTER loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS MSR, the CS and
SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. Instead,
the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of
OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the
fixed values loaded into the descriptor caches; the SYSENTER instruction does not ensure this correspondence.
The SYSENTER instruction can be invoked from all operating modes except real-address mode.
The SYSENTER and SYSEXIT instructions are companion instructions, but they do not constitute a call/return pair.
When executing a SYSENTER instruction, the processor does not save state information for the user code (e.g., the
instruction pointer), and neither the SYSENTER nor the SYSEXIT instruction supports passing parameters on the
stack.
To use the SYSENTER and SYSEXIT instructions as companion instructions for transitions between privilege level 3
code and privilege level 0 operating system procedures, the following conventions must be followed:
•
The segment descriptors for the privilege level 0 code and stack segments and for the privilege level 3 code and
stack segments must be contiguous in a descriptor table. This convention allows the processor to compute the
segment selectors from the value entered in the SYSENTER_CS_MSR MSR.
•
The fast system call “stub” routines executed by user code (typically in shared libraries or DLLs) must save the
required return IP and processor state information if a return to the calling procedure is required. Likewise, the
operating system or executive procedures called with SYSENTER instructions must have access to and use this
saved return and state information when returning to the user code.
4-670 Vol. 2B
SYSENTER—Fast System Call
INSTRUCTION SET REFERENCE, M-U
The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor.
The availability of these instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature
flag returned to the EDX register by the CPUID instruction. An operating system that qualifies the SEP flag must
also qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually
present. For example:
IF CPUID SEP bit is set
THEN IF (Family = 6) and (Model < 3) and (Stepping < 3)
THEN
SYSENTER/SYSEXIT_Not_Supported; FI;
ELSE
SYSENTER/SYSEXIT_Supported; FI;
FI;
When the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP
flag as set, but does not support the SYSENTER/SYSEXIT instructions.
Operation
IF CR0.PE = 0 OR IA32_SYSENTER_CS[15:2] = 0 THEN #GP(0); FI;
RFLAGS.VM ← 0;
(* Ensures protected mode execution *)
RFLAGS.IF ← 0;
(* Mask interrupts *)
IF in IA-32e mode
THEN
RSP ← IA32_SYSENTER_ESP;
RIP ← IA32_SYSENTER_EIP;
ELSE
ESP ← IA32_SYSENTER_ESP[31:0];
EIP ← IA32_SYSENTER_EIP[31:0];
FI;
CS.Selector ← IA32_SYSENTER_CS[15:0] AND FFFCH;
(* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)
CS.Base ← 0;
(* Flat segment *)
CS.Limit ← FFFFFH;
(* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type ← 11;
(* Execute/read code, accessed *)
CS.S ← 1;
CS.DPL ← 0;
CS.P ← 1;
IF in IA-32e mode
THEN
CS.L ← 1;
(* Entry is to 64-bit mode *)
CS.D ← 0;
(* Required if CS.L = 1 *)
ELSE
CS.L ← 0;
CS.D ← 1;
(* 32-bit code segment*)
FI;
CS.G ← 1;
(* 4-KByte granularity *)
CPL ← 0;
SS.Selector ← CS.Selector + 8;
(* Set rest of SS to a fixed value *)
SS.Base ← 0;
SS.Limit ← FFFFFH;
SS.Type ← 3;
SYSENTER—Fast System Call
(* SS just above CS *)
(* Flat segment *)
(* With 4-KByte granularity, implies a 4-GByte limit *)
(* Read/write data, accessed *)
Vol. 2B 4-671
INSTRUCTION SET REFERENCE, M-U
SS.S ← 1;
SS.DPL ← 0;
SS.P ← 1;
SS.B ← 1;
SS.G ← 1;
(* 32-bit stack segment*)
(* 4-KByte granularity *)
Flags Affected
VM, IF (see Operation above)
Protected Mode Exceptions
#GP(0)
If IA32_SYSENTER_CS[15:2] = 0.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
The SYSENTER instruction is not recognized in real-address mode.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
4-672 Vol. 2B
SYSENTER—Fast System Call
INSTRUCTION SET REFERENCE, M-U
SYSEXIT—Fast Return from Fast System Call
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 35
SYSEXIT
NP
Valid
Valid
Fast return to privilege level 3 user code.
REX.W + 0F 35
SYSEXIT
NP
Valid
Valid
Fast return to 64-bit mode privilege level 3
user code.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Executes a fast return to privilege level 3 user code. SYSEXIT is a companion instruction to the SYSENTER instruction. The instruction is optimized to provide the maximum performance for returns from system procedures
executing at protections levels 0 to user procedures executing at protection level 3. It must be executed from code
executing at privilege level 0.
With a 64-bit operand size, SYSEXIT remains in 64-bit mode; otherwise, it either enters compatibility mode (if the
logical processor is in IA-32e mode) or remains in protected mode (if it is not).
Prior to executing SYSEXIT, software must specify the privilege level 3 code segment and code entry point, and the
privilege level 3 stack segment and stack pointer by writing values into the following MSR and general-purpose
registers:
•
IA32_SYSENTER_CS (MSR address 174H) — Contains a 32-bit value that is used to determine the segment
selectors for the privilege level 3 code and stack segments (see the Operation section)
•
RDX — The canonical address in this register is loaded into RIP (thus, this value references the first instruction
to be executed in the user code). If the return is not to 64-bit mode, only bits 31:0 are loaded.
•
ECX — The canonical address in this register is loaded into RSP (thus, this value contains the stack pointer for
the privilege level 3 stack). If the return is not to 64-bit mode, only bits 31:0 are loaded.
The IA32_SYSENTER_CS MSR can be read from and written to using RDMSR and WRMSR.
While SYSEXIT loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS MSR, the CS and
SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. Instead,
the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of
OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the
fixed values loaded into the descriptor caches; the SYSEXIT instruction does not ensure this correspondence.
The SYSEXIT instruction can be invoked from all operating modes except real-address mode and virtual-8086
mode.
The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor.
The availability of these instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature
flag returned to the EDX register by the CPUID instruction. An operating system that qualifies the SEP flag must
also qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually
present. For example:
IF CPUID SEP bit is set
THEN IF (Family = 6) and (Model < 3) and (Stepping < 3)
THEN
SYSENTER/SYSEXIT_Not_Supported; FI;
ELSE
SYSENTER/SYSEXIT_Supported; FI;
FI;
When the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP
flag as set, but does not support the SYSENTER/SYSEXIT instructions.
SYSEXIT—Fast Return from Fast System Call
Vol. 2B 4-673
INSTRUCTION SET REFERENCE, M-U
Operation
IF IA32_SYSENTER_CS[15:2] = 0 OR CR0.PE = 0 OR CPL ≠ 0 THEN #GP(0); FI;
IF operand size is 64-bit
THEN
(* Return to 64-bit mode *)
RSP ← RCX;
RIP ← RDX;
ELSE
(* Return to protected mode or compatibility mode *)
RSP ← ECX;
RIP ← EDX;
FI;
IF operand size is 64-bit
(* Operating system provides CS; RPL forced to 3 *)
THEN CS.Selector ← IA32_SYSENTER_CS[15:0] + 32;
ELSE CS.Selector ← IA32_SYSENTER_CS[15:0] + 16;
FI;
CS.Selector ← CS.Selector OR 3;
(* RPL forced to 3 *)
(* Set rest of CS to a fixed value *)
CS.Base ← 0;
(* Flat segment *)
CS.Limit ← FFFFFH;
(* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type ← 11;
(* Execute/read code, accessed *)
CS.S ← 1;
CS.DPL ← 3;
CS.P ← 1;
IF operand size is 64-bit
THEN
(* return to 64-bit mode *)
CS.L ← 1;
(* 64-bit code segment *)
CS.D ← 0;
(* Required if CS.L = 1 *)
ELSE
(* return to protected mode or compatibility mode *)
CS.L ← 0;
CS.D ← 1;
(* 32-bit code segment*)
FI;
CS.G ← 1;
(* 4-KByte granularity *)
CPL ← 3;
SS.Selector ← CS.Selector + 8;
(* Set rest of SS to a fixed value *)
SS.Base ← 0;
SS.Limit ← FFFFFH;
SS.Type ← 3;
SS.S ← 1;
SS.DPL ← 3;
SS.P ← 1;
SS.B ← 1;
SS.G ← 1;
(* SS just above CS *)
(* Flat segment *)
(* With 4-KByte granularity, implies a 4-GByte limit *)
(* Read/write data, accessed *)
(* 32-bit stack segment*)
(* 4-KByte granularity *)
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If IA32_SYSENTER_CS[15:2] = 0.
If CPL
#UD
4-674 Vol. 2B
≠ 0.
If the LOCK prefix is used.
SYSEXIT—Fast Return from Fast System Call
INSTRUCTION SET REFERENCE, M-U
Real-Address Mode Exceptions
#GP
The SYSEXIT instruction is not recognized in real-address mode.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
The SYSEXIT instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If IA32_SYSENTER_CS = 0.
If CPL
≠ 0.
If RCX or RDX contains a non-canonical address.
#UD
If the LOCK prefix is used.
SYSEXIT—Fast Return from Fast System Call
Vol. 2B 4-675
INSTRUCTION SET REFERENCE, M-U
SYSRET—Return From Fast System Call
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 07
SYSRET
NP
Valid
Invalid
Return to compatibility mode from fast
system call
REX.W + 0F 07
SYSRET
NP
Valid
Invalid
Return to 64-bit mode from fast system call
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
SYSRET is a companion instruction to the SYSCALL instruction. It returns from an OS system-call handler to user
code at privilege level 3. It does so by loading RIP from RCX and loading RFLAGS from R11.1 With a 64-bit operand
size, SYSRET remains in 64-bit mode; otherwise, it enters compatibility mode and only the low 32 bits of the registers are loaded.
SYSRET loads the CS and SS selectors with values derived from bits 63:48 of the IA32_STAR MSR. However, the
CS and SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors.
Instead, the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the fixed values loaded into the descriptor caches; the SYSRET instruction does not ensure this
correspondence.
The SYSRET instruction does not modify the stack pointer (ESP or RSP). For that reason, it is necessary for software
to switch to the user stack. The OS may load the user stack pointer (if it was saved after SYSCALL) before executing
SYSRET; alternatively, user code may load the stack pointer (if it was saved before SYSCALL) after receiving control
from SYSRET.
If the OS loads the stack pointer before executing SYSRET, it must ensure that the handler of any interrupt or
exception delivered between restoring the stack pointer and successful execution of SYSRET is not invoked with the
user stack. It can do so using approaches such as the following:
•
External interrupts. The OS can prevent an external interrupt from being delivered by clearing EFLAGS.IF
before loading the user stack pointer.
•
Nonmaskable interrupts (NMIs). The OS can ensure that the NMI handler is invoked with the correct stack by
using the interrupt stack table (IST) mechanism for gate 2 (NMI) in the IDT (see Section 6.14.5, “Interrupt
Stack Table,” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
•
General-protection exceptions (#GP). The SYSRET instruction generates #GP(0) if the value of RCX is not
canonical. The OS can address this possibility using one or more of the following approaches:
— Confirming that the value of RCX is canonical before executing SYSRET.
— Using paging to ensure that the SYSCALL instruction will never save a non-canonical value into RCX.
— Using the IST mechanism for gate 13 (#GP) in the IDT.
Operation
IF (CS.L ≠ 1 ) or (IA32_EFER.LMA ≠ 1) or (IA32_EFER.SCE ≠ 1)
(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)
THEN #UD; FI;
IF (CPL ≠ 0) OR (RCX is not canonical) THEN #GP(0); FI;
1. Regardless of the value of R11, the RF and VM flags are always 0 in RFLAGS after execution of SYSRET. In addition, all reserved bits
in RFLAGS retain the fixed values.
4-676 Vol. 2B
SYSRET—Return From Fast System Call
INSTRUCTION SET REFERENCE, M-U
IF (operand size is 64-bit)
THEN (* Return to 64-Bit Mode *)
RIP ← RCX;
ELSE (* Return to Compatibility Mode *)
RIP ← ECX;
FI;
RFLAGS ← (R11 & 3C7FD7H) | 2;
(* Clear RF, VM, reserved bits; set bit 2 *)
IF (operand size is 64-bit)
THEN CS.Selector ← IA32_STAR[63:48]+16;
ELSE CS.Selector ← IA32_STAR[63:48];
FI;
CS.Selector ← CS.Selector OR 3;
(* RPL forced to 3 *)
(* Set rest of CS to a fixed value *)
CS.Base ← 0;
(* Flat segment *)
CS.Limit ← FFFFFH;
(* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type ← 11;
(* Execute/read code, accessed *)
CS.S ← 1;
CS.DPL ← 3;
CS.P ← 1;
IF (operand size is 64-bit)
THEN (* Return to 64-Bit Mode *)
CS.L ← 1;
(* 64-bit code segment *)
CS.D ← 0;
(* Required if CS.L = 1 *)
ELSE (* Return to Compatibility Mode *)
CS.L ← 0;
(* Compatibility mode *)
CS.D ← 1;
(* 32-bit code segment *)
FI;
CS.G ← 1;
(* 4-KByte granularity *)
CPL ← 3;
SS.Selector ← (IA32_STAR[63:48]+8) OR 3;
(* Set rest of SS to a fixed value *)
SS.Base ← 0;
SS.Limit ← FFFFFH;
SS.Type ← 3;
SS.S ← 1;
SS.DPL ← 3;
SS.P ← 1;
SS.B ← 1;
SS.G ← 1;
(* RPL forced to 3 *)
(* Flat segment *)
(* With 4-KByte granularity, implies a 4-GByte limit *)
(* Read/write data, accessed *)
(* 32-bit stack segment*)
(* 4-KByte granularity *)
Flags Affected
All.
Protected Mode Exceptions
#UD
The SYSRET instruction is not recognized in protected mode.
Real-Address Mode Exceptions
#UD
The SYSRET instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The SYSRET instruction is not recognized in virtual-8086 mode.
SYSRET—Return From Fast System Call
Vol. 2B 4-677
INSTRUCTION SET REFERENCE, M-U
Compatibility Mode Exceptions
#UD
The SYSRET instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#UD
If IA32_EFER.SCE = 0.
If the LOCK prefix is used.
#GP(0)
If CPL
≠ 0.
If RCX contains a non-canonical address.
4-678 Vol. 2B
SYSRET—Return From Fast System Call
INSTRUCTION SET REFERENCE, M-U
TEST—Logical Compare
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
A8 ib
TEST AL, imm8
I
Valid
Valid
AND imm8 with AL; set SF, ZF, PF according to
result.
A9 iw
TEST AX, imm16
I
Valid
Valid
AND imm16 with AX; set SF, ZF, PF according
to result.
A9 id
TEST EAX, imm32
I
Valid
Valid
AND imm32 with EAX; set SF, ZF, PF according
to result.
REX.W + A9 id
TEST RAX, imm32
I
Valid
N.E.
AND imm32 sign-extended to 64-bits with
RAX; set SF, ZF, PF according to result.
F6 /0 ib
TEST r/m8, imm8
MI
Valid
Valid
AND imm8 with r/m8; set SF, ZF, PF according
to result.
REX + F6 /0 ib
TEST r/m8*, imm8
MI
Valid
N.E.
AND imm8 with r/m8; set SF, ZF, PF according
to result.
F7 /0 iw
TEST r/m16, imm16
MI
Valid
Valid
AND imm16 with r/m16; set SF, ZF, PF
according to result.
F7 /0 id
TEST r/m32, imm32
MI
Valid
Valid
AND imm32 with r/m32; set SF, ZF, PF
according to result.
REX.W + F7 /0 id
TEST r/m64, imm32
MI
Valid
N.E.
AND imm32 sign-extended to 64-bits with
r/m64; set SF, ZF, PF according to result.
84 /r
TEST r/m8, r8
MR
Valid
Valid
AND r8 with r/m8; set SF, ZF, PF according to
result.
REX + 84 /r
TEST r/m8*, r8*
MR
Valid
N.E.
AND r8 with r/m8; set SF, ZF, PF according to
result.
85 /r
TEST r/m16, r16
MR
Valid
Valid
AND r16 with r/m16; set SF, ZF, PF according
to result.
85 /r
TEST r/m32, r32
MR
Valid
Valid
AND r32 with r/m32; set SF, ZF, PF according
to result.
REX.W + 85 /r
TEST r/m64, r64
MR
Valid
N.E.
AND r64 with r/m64; set SF, ZF, PF according
to result.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
I
AL/AX/EAX/RAX
imm8/16/32
NA
NA
MI
ModRM:r/m (r)
imm8/16/32
NA
NA
MR
ModRM:r/m (r)
ModRM:reg (r)
NA
NA
Description
Computes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand)
and sets the SF, ZF, and PF status flags according to the result. The result is then discarded.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a
REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.
TEST—Logical Compare
Vol. 2B 4-679
INSTRUCTION SET REFERENCE, M-U
Operation
TEMP ← SRC1 AND SRC2;
SF ← MSB(TEMP);
IF TEMP = 0
THEN ZF ← 1;
ELSE ZF ← 0;
FI:
PF ← BitwiseXNOR(TEMP[0:7]);
CF ← 0;
OF ← 0;
(* AF is undefined *)
Flags Affected
The OF and CF flags are set to 0. The SF, ZF, and PF flags are set according to the result (see the “Operation” section
above). The state of the AF flag is undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
4-680 Vol. 2B
TEST—Logical Compare
INSTRUCTION SET REFERENCE, M-U
TZCNT — Count the Number of Trailing Zero Bits
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
BMI1
Description
RM
64/32
-bit
Mode
V/V
F3 0F BC /r
TZCNT r16, r/m16
F3 0F BC /r
TZCNT r32, r/m32
F3 REX.W 0F BC /r
TZCNT r64, r/m64
RM
V/V
BMI1
Count the number of trailing zero bits in r/m32, return result in r32.
RM
V/N.E.
BMI1
Count the number of trailing zero bits in r/m64, return result in r64.
Count the number of trailing zero bits in r/m16, return result in r16.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
A
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
TZCNT counts the number of trailing least significant zero bits in source operand (second operand) and returns the
result in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference
between TZCNT and BSF instruction is that TZCNT provides operand size as output when source operand is zero
while in the case of BSF instruction, if source operand is zero, the content of destination operand are undefined. On
processors that do not support TZCNT, the instruction byte encoding is executed as BSF.
Operation
temp ← 0
DEST ← 0
DO WHILE ( (temp < OperandSize) and (SRC[ temp] = 0) )
OD
temp ← temp +1
DEST ← DEST+ 1
IF DEST = OperandSize
CF ← 1
ELSE
CF ← 0
FI
IF DEST = 0
ZF ← 1
ELSE
ZF ← 0
FI
Flags Affected
ZF is set to 1 in case of zero output (least significant bit of the source is set), and to 0 otherwise, CF is set to 1 if
the input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
TZCNT:
unsigned __int32 _tzcnt_u32(unsigned __int32 src);
TZCNT:
unsigned __int64 _tzcnt_u64(unsigned __int64 src);
TZCNT — Count the Number of Trailing Zero Bits
Vol. 2B 4-681
INSTRUCTION SET REFERENCE, M-U
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
selector.
#SS(0)
For an illegal address in the SS segment.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
For an illegal address in the SS segment.
Virtual 8086 Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
For an illegal address in the SS segment.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
4-682 Vol. 2B
TZCNT — Count the Number of Trailing Zero Bits
INSTRUCTION SET REFERENCE, M-U
UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 2E /r
UCOMISD xmm1, xmm2/m64
VEX.128.66.0F.WIG 2E /r
VUCOMISD xmm1, xmm2/m64
RM
V/V
AVX
EVEX.LIG.66.0F.W1 2E /r
VUCOMISD xmm1, xmm2/m64{sae}
T1S
V/V
AVX512F
Description
Compare low double-precision floating-point values in
xmm1 and xmm2/mem64 and set the EFLAGS flags
accordingly.
Compare low double-precision floating-point values in
xmm1 and xmm2/mem64 and set the EFLAGS flags
accordingly.
Compare low double-precision floating-point values in
xmm1 and xmm2/m64 and set the EFLAGS flags
accordingly.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Performs an unordered compare of the double-precision floating-point values in the low quadwords of operand 1
(first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according
to the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set
to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory
location.
The UCOMISD instruction differs from the COMISD instruction in that it signals a SIMD floating-point invalid operation exception (#I) only when a source operand is an SNaN. The COMISD instruction signals an invalid numeric
exception only if a source operand is either an SNaN or a QNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
(V)UCOMISD (all versions)
RESULT UnorderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF 111;
GREATER_THAN: ZF,PF,CF 000;
LESS_THAN: ZF,PF,CF 001;
EQUAL: ZF,PF,CF 100;
ESAC;
OF, AF, SF 0; }
UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS
Vol. 2B 4-683
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VUCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);
UCOMISD int _mm_ucomieq_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomilt_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomile_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomigt_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomige_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomineq_sd(__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Invalid (if SNaN operands), Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
4-684 Vol. 2B
UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, M-U
UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 2E /r
UCOMISS xmm1, xmm2/m32
VEX.128.0F.WIG 2E /r
VUCOMISS xmm1, xmm2/m32
RM
V/V
AVX
EVEX.LIG.0F.W0 2E /r
VUCOMISS xmm1, xmm2/m32{sae}
T1S
V/V
AVX512F
Description
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Compares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and
operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.
The UCOMISS instruction differs from the COMISS instruction in that it signals a SIMD floating-point invalid operation exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid numeric exception when a source operand is either a QNaN or SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
(V)UCOMISS (all versions)
RESULT UnorderedCompare(DEST[31:0] <> SRC[31:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF 111;
GREATER_THAN: ZF,PF,CF 000;
LESS_THAN: ZF,PF,CF 001;
EQUAL: ZF,PF,CF 100;
ESAC;
OF, AF, SF 0; }
UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
Vol. 2B 4-685
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VUCOMISS
UCOMISS
UCOMISS
UCOMISS
UCOMISS
UCOMISS
UCOMISS
int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);
int _mm_ucomieq_ss(__m128 a, __m128 b);
int _mm_ucomilt_ss(__m128 a, __m128 b);
int _mm_ucomile_ss(__m128 a, __m128 b);
int _mm_ucomigt_ss(__m128 a, __m128 b);
int _mm_ucomige_ss(__m128 a, __m128 b);
int _mm_ucomineq_ss(__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Invalid (if SNaN Operands), Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
4-686 Vol. 2B
UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, M-U
UD2—Undefined Instruction
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 0B
UD2
NP
Valid
Valid
Raise invalid opcode exception.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an
invalid opcode exception. The opcode for this instruction is reserved for this purpose.
Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory.
Even though it is the execution of the UD2 instruction that causes the invalid opcode exception, the instruction
pointer saved by delivery of the exception references the UD2 instruction (and not the following instruction).
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
#UD (* Generates invalid opcode exception *);
Flags Affected
None.
Exceptions (All Operating Modes)
#UD
Raises an invalid opcode exception in all operating modes.
UD2—Undefined Instruction
Vol. 2B 4-687
INSTRUCTION SET REFERENCE, M-U
UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values
Op /
En
Opcode/
Instruction
66 0F 15 /r
UNPCKHPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 15 /r
VUNPCKHPD xmm1,xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG 15 /r
VUNPCKHPD ymm1,ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 15 /r
VUNPCKHPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 15 /r
VUNPCKHPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 15 /r
VUNPCKHPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
RM
RVM
Description
Unpacks and Interleaves double-precision floating-point
values from high quadwords of xmm1 and
xmm2/m128.
Unpacks and Interleaves double-precision floating-point
values from high quadwords of xmm2 and
xmm3/m128.
Unpacks and Interleaves double-precision floating-point
values from high quadwords of ymm2 and
ymm3/m256.
Unpacks and Interleaves double precision floating-point
values from high quadwords of xmm2 and
xmm3/m128/m64bcst subject to writemask k1.
Unpacks and Interleaves double precision floating-point
values from high quadwords of ymm2 and
ymm3/m256/m64bcst subject to writemask k1.
Unpacks and Interleaves double-precision floating-point
values from high quadwords of zmm2 and
zmm3/m512/m64bcst subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs an interleaved unpack of the high double-precision floating-point values from the first source operand and
the second source operand. See Figure 4-15 in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2B.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.
4-688 Vol. 2B
UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
VUNPCKHPD (EVEX encoded versions when SRC2 is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF VL >= 128
TMP_DEST[63:0] SRC1[127:64]
TMP_DEST[127:64] SRC2[127:64]
FI;
IF VL >= 256
TMP_DEST[191:128] SRC1[255:192]
TMP_DEST[255:192] SRC2[255:192]
FI;
IF VL >= 512
TMP_DEST[319:256] SRC1[383:320]
TMP_DEST[383:320] SRC2[383:320]
TMP_DEST[447:384] SRC1[511:448]
TMP_DEST[511:448] SRC2[511:448]
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values
Vol. 2B 4-689
INSTRUCTION SET REFERENCE, M-U
VUNPCKHPD (EVEX encoded version when SRC2 is memory)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1)
THEN TMP_SRC2[i+63:i] SRC2[63:0]
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i]
FI;
ENDFOR;
IF VL >= 128
TMP_DEST[63:0] SRC1[127:64]
TMP_DEST[127:64] TMP_SRC2[127:64]
FI;
IF VL >= 256
TMP_DEST[191:128] SRC1[255:192]
TMP_DEST[255:192] TMP_SRC2[255:192]
FI;
IF VL >= 512
TMP_DEST[319:256] SRC1[383:320]
TMP_DEST[383:320] TMP_SRC2[383:320]
TMP_DEST[447:384] SRC1[511:448]
TMP_DEST[511:448] TMP_SRC2[511:448]
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VUNPCKHPD (VEX.256 encoded version)
DEST[63:0] SRC1[127:64]
DEST[127:64] SRC2[127:64]
DEST[191:128]SRC1[255:192]
DEST[255:192]SRC2[255:192]
DEST[MAX_VL-1:256] 0
VUNPCKHPD (VEX.128 encoded version)
DEST[63:0] SRC1[127:64]
DEST[127:64] SRC2[127:64]
DEST[MAX_VL-1:128] 0
UNPCKHPD (128-bit Legacy SSE version)
DEST[63:0] SRC1[127:64]
DEST[127:64] SRC2[127:64]
DEST[MAX_VL-1:128] (Unmodified)
4-690 Vol. 2B
UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKHPD __m512d _mm512_unpackhi_pd( __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_mask_unpackhi_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_maskz_unpackhi_pd(__mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m256d _mm256_unpackhi_pd(__m256d a, __m256d b)
VUNPCKHPD __m256d _mm256_mask_unpackhi_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VUNPCKHPD __m256d _mm256_maskz_unpackhi_pd(__mmask8 k, __m256d a, __m256d b);
UNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)
VUNPCKHPD __m128d _mm_mask_unpackhi_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VUNPCKHPD __m128d _mm_maskz_unpackhi_pd(__mmask8 k, __m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.
UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values
Vol. 2B 4-691
INSTRUCTION SET REFERENCE, M-U
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
V/V
AVX
RVM
V/V
AVX
Unpacks and Interleaves single-precision floating-point
values from high quadwords of ymm2 and ymm3/m256.
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.0F.W0 15 /r
VUNPCKHPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.0F.W0 15 /r
VUNPCKHPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
Unpacks and Interleaves single-precision floating-point
values from high quadwords of xmm2 and
xmm3/m128/m32bcst and write result to xmm1 subject to
writemask k1.
Unpacks and Interleaves single-precision floating-point
values from high quadwords of ymm2 and
ymm3/m256/m32bcst and write result to ymm1 subject to
writemask k1.
Unpacks and Interleaves single-precision floating-point
values from high quadwords of zmm2 and
zmm3/m512/m32bcst and write result to zmm1 subject to
writemask k1.
0F 15 /r
UNPCKHPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 15 /r
VUNPCKHPS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.0F.WIG 15 /r
VUNPCKHPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.0F.W0 15 /r
VUNPCKHPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
RM
RVM
Description
Unpacks and Interleaves single-precision floating-point
values from high quadwords of xmm1 and xmm2/m128.
Unpacks and Interleaves single-precision floating-point
values from high quadwords of xmm2 and xmm3/m128.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs an interleaved unpack of the high single-precision floating-point values from the first source operand and
the second source operand.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers.
4-692 Vol. 2B
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
SRC1
X7
X6
X5
X4
X3
X2
X1
X0
SRC2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
DEST
Y7
X7
Y6
X6
Y3
X3
Y2
X2
Figure 4-27. VUNPCKHPS Operation
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.
Operation
VUNPCKHPS (EVEX encoded version when SRC2 is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL >= 128
TMP_DEST[31:0] SRC1[95:64]
TMP_DEST[63:32] SRC2[95:64]
TMP_DEST[95:64] SRC1[127:96]
TMP_DEST[127:96] SRC2[127:96]
FI;
IF VL >= 256
TMP_DEST[159:128] SRC1[223:192]
TMP_DEST[191:160] SRC2[223:192]
TMP_DEST[223:192] SRC1[255:224]
TMP_DEST[255:224] SRC2[255:224]
FI;
IF VL >= 512
TMP_DEST[287:256] SRC1[351:320]
TMP_DEST[319:288] SRC2[351:320]
TMP_DEST[351:320] SRC1[383:352]
TMP_DEST[383:352] SRC2[383:352]
TMP_DEST[415:384] SRC1[479:448]
TMP_DEST[447:416] SRC2[479:448]
TMP_DEST[479:448] SRC1[511:480]
TMP_DEST[511:480] SRC2[511:480]
FI;
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values
Vol. 2B 4-693
INSTRUCTION SET REFERENCE, M-U
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VUNPCKHPS (EVEX encoded version when SRC2 is memory)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1)
THEN TMP_SRC2[i+31:i] SRC2[31:0]
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
IF VL >= 128
TMP_DEST[31:0] SRC1[95:64]
TMP_DEST[63:32] TMP_SRC2[95:64]
TMP_DEST[95:64] SRC1[127:96]
TMP_DEST[127:96] TMP_SRC2[127:96]
FI;
IF VL >= 256
TMP_DEST[159:128] SRC1[223:192]
TMP_DEST[191:160] TMP_SRC2[223:192]
TMP_DEST[223:192] SRC1[255:224]
TMP_DEST[255:224] TMP_SRC2[255:224]
FI;
IF VL >= 512
TMP_DEST[287:256] SRC1[351:320]
TMP_DEST[319:288] TMP_SRC2[351:320]
TMP_DEST[351:320] SRC1[383:352]
TMP_DEST[383:352] TMP_SRC2[383:352]
TMP_DEST[415:384] SRC1[479:448]
TMP_DEST[447:416] TMP_SRC2[479:448]
TMP_DEST[479:448] SRC1[511:480]
TMP_DEST[511:480] TMP_SRC2[511:480]
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
4-694 Vol. 2B
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VUNPCKHPS (VEX.256 encoded version)
DEST[31:0] SRC1[95:64]
DEST[63:32] SRC2[95:64]
DEST[95:64] SRC1[127:96]
DEST[127:96] SRC2[127:96]
DEST[159:128] SRC1[223:192]
DEST[191:160] SRC2[223:192]
DEST[223:192] SRC1[255:224]
DEST[255:224] SRC2[255:224]
DEST[MAX_VL-1:256] 0
VUNPCKHPS (VEX.128 encoded version)
DEST[31:0] SRC1[95:64]
DEST[63:32] SRC2[95:64]
DEST[95:64] SRC1[127:96]
DEST[127:96] SRC2[127:96]
DEST[MAX_VL-1:128] 0
UNPCKHPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[95:64]
DEST[63:32] SRC2[95:64]
DEST[95:64] SRC1[127:96]
DEST[127:96] SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKHPS __m512 _mm512_unpackhi_ps( __m512 a, __m512 b);
VUNPCKHPS __m512 _mm512_mask_unpackhi_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VUNPCKHPS __m512 _mm512_maskz_unpackhi_ps(__mmask16 k, __m512 a, __m512 b);
VUNPCKHPS __m256 _mm256_unpackhi_ps (__m256 a, __m256 b);
VUNPCKHPS __m256 _mm256_mask_unpackhi_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VUNPCKHPS __m256 _mm256_maskz_unpackhi_ps(__mmask8 k, __m256 a, __m256 b);
UNPCKHPS __m128 _mm_unpackhi_ps (__m128 a, __m128 b);
VUNPCKHPS __m128 _mm_mask_unpackhi_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VUNPCKHPS __m128 _mm_maskz_unpackhi_ps(__mmask8 k, __m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values
Vol. 2B 4-695
INSTRUCTION SET REFERENCE, M-U
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
66 0F 14 /r
UNPCKLPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 14 /r
VUNPCKLPD xmm1,xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG 14 /r
VUNPCKLPD ymm1,ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 14 /r
VUNPCKLPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 14 /r
VUNPCKLPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 14 /r
VUNPCKLPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
V/V
AVX
RVM
V/V
AVX
Unpacks and Interleaves double-precision floating-point
values from low quadwords of ymm2 and ymm3/m256.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Unpacks and Interleaves double precision floating-point
values from low quadwords of xmm2 and
xmm3/m128/m64bcst subject to write mask k1.
Unpacks and Interleaves double precision floating-point
values from low quadwords of ymm2 and
ymm3/m256/m64bcst subject to write mask k1.
Unpacks and Interleaves double-precision floating-point
values from low quadwords of zmm2 and
zmm3/m512/m64bcst subject to write mask k1.
RM
RVM
Description
Unpacks and Interleaves double-precision floating-point
values from low quadwords of xmm1 and xmm2/m128.
Unpacks and Interleaves double-precision floating-point
values from low quadwords of xmm2 and xmm3/m128.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs an interleaved unpack of the low double-precision floating-point values from the first source operand and
the second source operand.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.
4-696 Vol. 2B
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Operation
VUNPCKLPD (EVEX encoded versions when SRC2 is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF VL >= 128
TMP_DEST[63:0] SRC1[63:0]
TMP_DEST[127:64] SRC2[63:0]
FI;
IF VL >= 256
TMP_DEST[191:128] SRC1[191:128]
TMP_DEST[255:192] SRC2[191:128]
FI;
IF VL >= 512
TMP_DEST[319:256] SRC1[319:256]
TMP_DEST[383:320] SRC2[319:256]
TMP_DEST[447:384] SRC1[447:384]
TMP_DEST[511:448] SRC2[447:384]
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values
Vol. 2B 4-697
INSTRUCTION SET REFERENCE, M-U
VUNPCKLPD (EVEX encoded version when SRC2 is memory)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1)
THEN TMP_SRC2[i+63:i] SRC2[63:0]
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i]
FI;
ENDFOR;
IF VL >= 128
TMP_DEST[63:0] SRC1[63:0]
TMP_DEST[127:64] TMP_SRC2[63:0]
FI;
IF VL >= 256
TMP_DEST[191:128] SRC1[191:128]
TMP_DEST[255:192] TMP_SRC2[191:128]
FI;
IF VL >= 512
TMP_DEST[319:256] SRC1[319:256]
TMP_DEST[383:320] TMP_SRC2[319:256]
TMP_DEST[447:384] SRC1[447:384]
TMP_DEST[511:448] TMP_SRC2[447:384]
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VUNPCKLPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
DEST[191:128] SRC1[191:128]
DEST[255:192] SRC2[191:128]
DEST[MAX_VL-1:256] 0
VUNPCKLPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
DEST[MAX_VL-1:128] 0
UNPCKLPD (128-bit Legacy SSE version)
DEST[63:0] SRC1[63:0]
DEST[127:64] SRC2[63:0]
DEST[MAX_VL-1:128] (Unmodified)
4-698 Vol. 2B
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKLPD __m512d _mm512_unpacklo_pd( __m512d a, __m512d b);
VUNPCKLPD __m512d _mm512_mask_unpacklo_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VUNPCKLPD __m512d _mm512_maskz_unpacklo_pd(__mmask8 k, __m512d a, __m512d b);
VUNPCKLPD __m256d _mm256_unpacklo_pd(__m256d a, __m256d b)
VUNPCKLPD __m256d _mm256_mask_unpacklo_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VUNPCKLPD __m256d _mm256_maskz_unpacklo_pd(__mmask8 k, __m256d a, __m256d b);
UNPCKLPD __m128d _mm_unpacklo_pd(__m128d a, __m128d b)
VUNPCKLPD __m128d _mm_mask_unpacklo_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VUNPCKLPD __m128d _mm_maskz_unpacklo_pd(__mmask8 k, __m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values
Vol. 2B 4-699
INSTRUCTION SET REFERENCE, M-U
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
0F 14 /r
UNPCKLPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 14 /r
VUNPCKLPS xmm1,xmm2,
xmm3/m128
VEX.NDS.256.0F.WIG 14 /r
VUNPCKLPS
ymm1,ymm2,ymm3/m256
EVEX.NDS.128.0F.W0 14 /r
VUNPCKLPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 14 /r
VUNPCKLPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 14 /r
VUNPCKLPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
V/V
AVX
RVM
V/V
AVX
Unpacks and Interleaves single-precision floating-point
values from low quadwords of ymm2 and ymm3/m256.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Unpacks and Interleaves single-precision floating-point
values from low quadwords of xmm2 and xmm3/mem and
write result to xmm1 subject to write mask k1.
Unpacks and Interleaves single-precision floating-point
values from low quadwords of ymm2 and ymm3/mem and
write result to ymm1 subject to write mask k1.
Unpacks and Interleaves single-precision floating-point
values from low quadwords of zmm2 and
zmm3/m512/m32bcst and write result to zmm1 subject
to write mask k1.
RM
RVM
Description
Unpacks and Interleaves single-precision floating-point
values from low quadwords of xmm1 and xmm2/m128.
Unpacks and Interleaves single-precision floating-point
values from low quadwords of xmm2 and xmm3/m128.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs an interleaved unpack of the low single-precision floating-point values from the first source operand and
the second source operand.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
4-700 Vol. 2B
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
SRC1
X7
X6
X5
X4
X3
X2
X1
X0
SRC2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
DEST
Y5
X5
Y4
X4
Y1
X1
Y0
X0
Figure 4-28. VUNPCKLPS Operation
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.
Operation
VUNPCKLPS (EVEX encoded version when SRC2 is a ZMM register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL >= 128
TMP_DEST[31:0] SRC1[31:0]
TMP_DEST[63:32] SRC2[31:0]
TMP_DEST[95:64] SRC1[63:32]
TMP_DEST[127:96] SRC2[63:32]
FI;
IF VL >= 256
TMP_DEST[159:128] SRC1[159:128]
TMP_DEST[191:160] SRC2[159:128]
TMP_DEST[223:192] SRC1[191:160]
TMP_DEST[255:224] SRC2[191:160]
FI;
IF VL >= 512
TMP_DEST[287:256] SRC1[287:256]
TMP_DEST[319:288] SRC2[287:256]
TMP_DEST[351:320] SRC1[319:288]
TMP_DEST[383:352] SRC2[319:288]
TMP_DEST[415:384] SRC1[415:384]
TMP_DEST[447:416] SRC2[415:384]
TMP_DEST[479:448] SRC1[447:416]
TMP_DEST[511:480] SRC2[447:416]
FI;
FOR j 0 TO KL-1
i j * 32
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values
Vol. 2B 4-701
INSTRUCTION SET REFERENCE, M-U
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VUNPCKLPS (EVEX encoded version when SRC2 is memory)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 31
IF (EVEX.b = 1)
THEN TMP_SRC2[i+31:i] SRC2[31:0]
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
IF VL >= 128
TMP_DEST[31:0] SRC1[31:0]
TMP_DEST[63:32] TMP_SRC2[31:0]
TMP_DEST[95:64] SRC1[63:32]
TMP_DEST[127:96] TMP_SRC2[63:32]
FI;
IF VL >= 256
TMP_DEST[159:128] SRC1[159:128]
TMP_DEST[191:160] TMP_SRC2[159:128]
TMP_DEST[223:192] SRC1[191:160]
TMP_DEST[255:224] TMP_SRC2[191:160]
FI;
IF VL >= 512
TMP_DEST[287:256] SRC1[287:256]
TMP_DEST[319:288] TMP_SRC2[287:256]
TMP_DEST[351:320] SRC1[319:288]
TMP_DEST[383:352] TMP_SRC2[319:288]
TMP_DEST[415:384] SRC1[415:384]
TMP_DEST[447:416] TMP_SRC2[415:384]
TMP_DEST[479:448] SRC1[447:416]
TMP_DEST[511:480] TMP_SRC2[447:416]
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
4-702 Vol. 2B
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, M-U
ENDFOR
DEST[MAX_VL-1:VL] 0
UNPCKLPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0]
DEST[63:32] SRC2[31:0]
DEST[95:64] SRC1[63:32]
DEST[127:96] SRC2[63:32]
DEST[159:128] SRC1[159:128]
DEST[191:160] SRC2[159:128]
DEST[223:192] SRC1[191:160]
DEST[255:224] SRC2[191:160]
DEST[MAX_VL-1:256] 0
VUNPCKLPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0]
DEST[63:32] SRC2[31:0]
DEST[95:64] SRC1[63:32]
DEST[127:96] SRC2[63:32]
DEST[MAX_VL-1:128] 0
UNPCKLPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0]
DEST[63:32] SRC2[31:0]
DEST[95:64] SRC1[63:32]
DEST[127:96] SRC2[63:32]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKLPS __m512 _mm512_unpacklo_ps(__m512 a, __m512 b);
VUNPCKLPS __m512 _mm512_mask_unpacklo_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VUNPCKLPS __m512 _mm512_maskz_unpacklo_ps(__mmask16 k, __m512 a, __m512 b);
VUNPCKLPS __m256 _mm256_unpacklo_ps (__m256 a, __m256 b);
VUNPCKLPS __m256 _mm256_mask_unpacklo_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VUNPCKLPS __m256 _mm256_maskz_unpacklo_ps(__mmask8 k, __m256 a, __m256 b);
UNPCKLPS __m128 _mm_unpacklo_ps (__m128 a, __m128 b);
VUNPCKLPS __m128 _mm_mask_unpacklo_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VUNPCKLPS __m128 _mm_maskz_unpacklo_ps(__mmask8 k, __m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values
Vol. 2B 4-703
INSTRUCTION SET REFERENCE, M-U
4-704 Vol. 2B
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values
CHAPTER 5
INSTRUCTION SET REFERENCE, V-Z
5.1
TERNARY BIT VECTOR LOGIC TABLE
VPTERNLOGD/VPTERNLOGQ instructions operate on dword/qword elements and take three bit vectors of the
respective input data elements to form a set of 32/64 indices, where each 3-bit value provides an index into an 8bit lookup table represented by the imm8 byte of the instruction. The 256 possible values of the imm8 byte is
constructed as a 16x16 boolean logic table. The 16 rows of the table uses the lower 4 bits of imm8 as row index.
The 16 columns are referenced by imm8[7:4]. The 16 columns of the table are present in two halves, with 8
columns shown in Table 5-10 for the column index value between 0:7, followed by Table 5-11 showing the 8
columns corresponding to column index 8:15. This section presents the two-halves of the 256-entry table using a
short-hand notation representing simple or compound boolean logic expressions with three input bit source data.
The three input bit source data will be denoted with the capital letters: A, B, C; where A represents a bit from the
first source operand (also the destination operand), B and C represent a bit from the 2nd and 3rd source operands.
Each map entry takes the form of a logic expression consisting of one of more component expressions. Each
component expression consists of either a unary or binary boolean operator and associated operands. Each binary
boolean operator is expressed in lowercase letters, and operands concatenated after the logic operator. The unary
operator ‘not’ is expressed using ‘!’. Additionally, the conditional expression “A?B:C” expresses a result returning B
if A is set, returning C otherwise.
A binary boolean operator is followed by two operands, e.g. andAB. For a compound binary expression that contain
commutative components and comprising the same logic operator, the 2nd logic operator is omitted and three
operands can be concatenated in sequence, e.g. andABC. When the 2nd operand of the first binary boolean expression comes from the result of another boolean expression, the 2nd boolean expression is concatenated after the
uppercase operand of the first logic expression, e.g. norBnandAC. When the result is independent of an operand,
that operand is omitted in the logic expression, e.g. zeros or norCB.
The 3-input expression “majorABC” returns 0 if two or more input bits are 0, returns 1 if two or more input bits are
1. The 3-input expression “minorABC” returns 1 if two or more input bits are 0, returns 0 if two or more input bits
are 1.
The building-block bit logic functions used in Table 5-10 and Table 5-11 include;
•
•
•
•
•
Constants: TRUE (1), FALSE (0);
Unary function: Not (!);
Binary functions: and, nand, or, nor, xor, xnor;
Conditional function: Select (?:);
Tertiary functions: major, minor.
Vol. 2C 5-1
INSTRUCTION SET REFERENCE, V-Z
Table 5-10. Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations
:
Imm
[7:4]
[3:0]
0H
1H
2H
3H
4H
5H
6H
7H
00H
FALSE
andAnorBC
norBnandAC
andA!B
norCnandBA
andA!C
andAxorBC
andAnandBC
01H
norABC
norCB
norBxorAC
A?!B:norBC
norCxorBA
A?!C:norBC
A?xorBC:norB A?nandBC:no
C
rBC
02H
andCnorBA
norBxnorAC
andC!B
norBnorAC
C?norBA:and
BA
C?norBA:A
C?!B:andBA
C?!B:A
03H
norBA
norBandAC
C?!B:norBA
!B
C?norBA:xnor A?!C:!B
BA
A?xorBC:!B
A?nandBC:!B
04H
andBnorAC
norCxnorBA
B?norAC:and
AC
B?norAC:A
andB!C
norCnorBA
B?!C:andAC
B?!C:A
05H
norCA
norCandBA
B?norAC:xnor A?!B:!C
AC
B?!C:norAC
!C
A?xorBC:!C
A?nandBC:!C
06H
norAxnorBC
A?norBC:xorB B?norAC:C
C
xorBorAC
C?norBA:B
xorCorBA
xorCB
B?!C:orAC
07H
norAandBC
minorABC
C?!B:!A
nandBorAC
B?!C:!A
nandCorBA
A?xorBC:nan
dBC
nandCB
08H
norAnandBC
A?norBC:and
BC
andCxorBA
A?!B:andBC
andBxorAC
A?!C:andBC
A?xorBC:and
BC
xorAandBC
09H
norAxorBC
A?norBC:xnor C?xorBA:norB A?!B:xnorBC
BC
A
B?xorAC:norA A?!C:xnorBC
C
xnorABC
A?nandBC:xn
orBC
0AH
andC!A
A?norBC:C
andCnandBA
A?!B:C
C?!A:andBA
xorCA
xorCandBA
A?nandBC:C
0BH
C?!A:norBA
C?!A:!B
C?nandBA:no
rBA
C?nandBA:!B
B?xorAC:!A
B?xorAC:nan
dAC
C?nandBA:xn
orBA
nandBxnorAC
0CH
andB!A
A?norBC:B
B?!A:andAC
xorBA
andBnandAC
A?!C:B
xorBandAC
A?nandBC:B
0DH
B?!A:norAC
B?!A:!C
B?!A:xnorAC
C?xorBA:nan
dBA
B?nandAC:no
rAC
B?nandAC:!C
B?nandAC:xn
orAC
nandCxnorBA
0EH
norAnorBC
xorAorBC
B?!A:C
A?!B:orBC
C?!A:B
A?!C:orBC
B?nandAC:C
A?nandBC:or
BC
0FH
!A
nandAorBC
C?nandBA:!A
nandBA
B?nandAC:!A
nandCA
nandAxnorBC nandABC
Table 5-11 shows the half of 256-entry map corresponding to column index values 8:15.
5-2 Vol. 2C
INSTRUCTION SET REFERENCE, V-Z
Table 5-11. Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations
:
Imm
[7:4]
[3:0]
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
00H
andABC
andAxnorBC
andCA
B?andAC:A
andBA
C?andBA:A
andAorBC
A
01H
A?andBC:nor
BC
B?andAC:!C
A?C:norBC
C?A:!B
A?B:norBC
B?A:!C
xnorAorBC
orAnorBC
02H
andCxnorBA
B?andAC:xor
AC
B?andAC:C
B?andAC:orA
C
C?xnorBA:an
dBA
B?A:xorAC
B?A:C
B?A:orAC
03H
A?andBC:!B
xnorBandAC
A?C:!B
nandBnandA
C
xnorBA
B?A:nandAC
A?orBC:!B
orA!B
04H
andBxnorAC
C?andBA:xor
BA
B?xnorAC:an
dAC
B?xnorAC:A
C?andBA:B
C?andBA:orB
A
C?A:B
C?A:orBA
05H
A?andBC:!C
xnorCandBA
xnorCA
C?A:nandBA
A?B:!C
nandCnandB
A
A?orBC:!C
orA!C
06H
A?andBC:xor
BC
xorABC
A?C:xorBC
B?xnorAC:orA A?B:xorBC
C
C?xnorBA:orB A?orBC:xorBC orAxorBC
A
07H
xnorAandBC
A?xnorBC:na
ndBC
A?C:nandBC
nandBxorAC
A?B:nandBC
nandCxorBA
A?orBCnandB orAnandBC
C
08H
andCB
A?xnorBC:an
dBC
andCorAB
B?C:A
andBorAC
C?B:A
majorABC
09H
B?C:norAC
xnorCB
xnorCorBA
C?orBA:!B
xnorBorAC
B?orAC:!C
A?orBC:xnorB orAxnorBC
C
0AH
A?andBC:C
A?xnorBC:C
C
B?C:orAC
A?B:C
B?orAC:xorAC orCandBA
orCA
0BH
B?C:!A
B?C:nandAC
orCnorBA
orC!B
B?orAC:!A
B?orAC:nand
AC
orCxnorBA
nandBnorAC
0CH
A?andBC:B
A?xnorBC:B
A?C:B
C?orBA:xorBA B
C?B:orBA
orBandAC
orBA
0DH
C?B!A
C?B:nandBA
C?orBA:!A
C?orBA:nand
BA
orBnorAC
orB!C
orBxnorAC
nandCnorBA
0EH
A?andBC:orB
C
A?xnorBC:orB A?C:orBC
C
orCxorBA
A?B:orBC
orBxorAC
orCB
orABC
0FH
nandAnandB
C
nandAxorBC
orCnandBA
orB!A
orBnandAC
nandAnorBC
TRUE
orC!A
orAandBC
Table 5-10 and Table 5-11 translate each of the possible value of the imm8 byte to a Boolean expression. These
tables can also be used by software to translate Boolean expressions to numerical constants to form the imm8
value needed to construct the VPTERNLOG syntax. There is a unique set of three byte constants (F0H, CCH, AAH)
that can be used for this purpose as input operands in conjunction with the Boolean expressions defined in those
tables. The reverse mapping can be expressed as:
Result_imm8 = Table_Lookup_Entry( 0F0H, 0CCH, 0AAH)
Table_Lookup_Entry is the Boolean expression defined in Table 5-10 and Table 5-11.
Vol. 2C 5-3
INSTRUCTION SET REFERENCE, V-Z
5.2
INSTRUCTIONS (V-Z)
Chapter 5 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (V-Z). See also: Chapter 3,
“Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A, and Chapter 4, “Instruction Set Reference, M-U‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
5-4 Vol. 2C
INSTRUCTION SET REFERENCE, V-Z
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F3A.W0 03 /r ib
VALIGND xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst, imm8
EVEX.NDS.128.66.0F3A.W1 03 /r ib
VALIGNQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F3A.W0 03 /r ib
VALIGND ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F3A.W1 03 /r ib
VALIGNQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F3A.W0 03 /r ib
VALIGND zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst, imm8
FV
V/V
AVX512F
EVEX.NDS.512.66.0F3A.W1 03 /r ib
VALIGNQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst, imm8
FV
V/V
AVX512F
Description
Shift right and merge vectors xmm2 and
xmm3/m128/m32bcst with double-word granularity
using imm8 as number of elements to shift, and store the
final result in xmm1, under writemask.
Shift right and merge vectors xmm2 and
xmm3/m128/m64bcst with quad-word granularity using
imm8 as number of elements to shift, and store the final
result in xmm1, under writemask.
Shift right and merge vectors ymm2 and
ymm3/m256/m32bcst with double-word granularity
using imm8 as number of elements to shift, and store the
final result in ymm1, under writemask.
Shift right and merge vectors ymm2 and
ymm3/m256/m64bcst with quad-word granularity using
imm8 as number of elements to shift, and store the final
result in ymm1, under writemask.
Shift right and merge vectors zmm2 and
zmm3/m512/m32bcst with double-word granularity
using imm8 as number of elements to shift, and store the
final result in zmm1, under writemask.
Shift right and merge vectors zmm2 and
zmm3/m512/m64bcst with quad-word granularity using
imm8 as number of elements to shift, and store the final
result in zmm1, under writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Concatenates and shifts right doubleword/quadword elements of the first source operand (the second operand)
and the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low
512/256/128-bit of the intermediate vector is written to the destination operand (the first operand) using the
writemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted
from a 32/64-bit memory location.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous
values (merging-masking) or are set to 0 (zeroing-masking).
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors
Vol. 2C 5-5
INSTRUCTION SET REFERENCE, V-Z
Operation
VALIGND (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (SRC2 *is memory*) (AND EVEX.b = 1)
THEN
FOR j 0 TO KL-1
i j * 32
src[i+31:i] SRC2[31:0]
ENDFOR;
ELSE src SRC2
FI
; Concatenate sources
tmp[VL-1:0] src[VL-1:0]
tmp[2VL-1:VL] SRC1[VL-1:0]
; Shift right doubleword elements
IF VL = 128
THEN SHIFT = imm8[1:0]
ELSE
IF VL = 256
THEN SHIFT = imm8[2:0]
ELSE SHIFT = imm8[3:0]
FI
FI;
tmp[2VL-1:0] tmp[2VL-1:0] >> (32*SHIFT)
; Apply writemask
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] tmp[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
5-6 Vol. 2C
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors
INSTRUCTION SET REFERENCE, V-Z
VALIGNQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256),(8, 512)
IF (SRC2 *is memory*) (AND EVEX.b = 1)
THEN
FOR j 0 TO KL-1
i j * 64
src[i+63:i] SRC2[63:0]
ENDFOR;
ELSE src SRC2
FI
; Concatenate sources
tmp[VL-1:0] src[VL-1:0]
tmp[2VL-1:VL] SRC1[VL-1:0]
; Shift right quadword elements
IF VL = 128
THEN SHIFT = imm8[0]
ELSE
IF VL = 256
THEN SHIFT = imm8[1:0]
ELSE SHIFT = imm8[2:0]
FI
FI;
tmp[2VL-1:0] tmp[2VL-1:0] >> (64*SHIFT)
; Apply writemask
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] tmp[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors
Vol. 2C 5-7
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VALIGND __m512i _mm512_alignr_epi32( __m512i a, __m512i b, int cnt);
VALIGND __m512i _mm512_mask_alignr_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b, int cnt);
VALIGND __m512i _mm512_maskz_alignr_epi32( __mmask16 k, __m512i a, __m512i b, int cnt);
VALIGND __m256i _mm256_mask_alignr_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGND __m256i _mm256_maskz_alignr_epi32( __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGND __m128i _mm_mask_alignr_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGND __m128i _mm_maskz_alignr_epi32( __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGNQ __m512i _mm512_alignr_epi64( __m512i a, __m512i b, int cnt);
VALIGNQ __m512i _mm512_mask_alignr_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b, int cnt);
VALIGNQ __m512i _mm512_maskz_alignr_epi64( __mmask8 k, __m512i a, __m512i b, int cnt);
VALIGNQ __m256i _mm256_mask_alignr_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGNQ __m256i _mm256_maskz_alignr_epi64( __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGNQ __m128i _mm_mask_alignr_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGNQ __m128i _mm_maskz_alignr_epi64( __mmask8 k, __m128i a, __m128i b, int cnt);
Exceptions
See Exceptions Type E4NF.
5-8 Vol. 2C
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors
INSTRUCTION SET REFERENCE, V-Z
VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W1 65 /r
VBLENDMPD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 65 /r
VBLENDMPD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 65 /r
VBLENDMPD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst
EVEX.NDS.128.66.0F38.W0 65 /r
VBLENDMPS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 65 /r
VBLENDMPS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 65 /r
VBLENDMPS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Blend double-precision vector xmm2 and double-precision
vector xmm3/m128/m64bcst and store the result in xmm1,
under control mask.
Blend double-precision vector ymm2 and double-precision
vector ymm3/m256/m64bcst and store the result in ymm1,
under control mask.
Blend double-precision vector zmm2 and double-precision
vector zmm3/m512/m64bcst and store the result in zmm1,
under control mask.
Blend single-precision vector xmm2 and single-precision
vector xmm3/m128/m32bcst and store the result in xmm1,
under control mask.
Blend single-precision vector ymm2 and single-precision
vector ymm3/m256/m32bcst and store the result in ymm1,
under control mask.
Blend single-precision vector zmm2 and single-precision
vector zmm3/m512/m32bcst using k1 as select control and
store the result in zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs an element-by-element blending between float64/float32 elements in the first source operand (the
second operand) with the elements in the second source operand (the third operand) using an opmask register as
select control. The blended result is written to the destination register.
The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64bit memory location.
The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element
selector: every element of the destination is conditionally selected between first source or second source using the
value of the related mask bit (0 for first source operand, 1 for second source operand).
If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.
VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control
Vol. 2C 5-9
INSTRUCTION SET REFERENCE, V-Z
Operation
VBLENDMPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no controlmask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] SRC2[63:0]
ELSE
DEST[i+63:i] SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+63:i] SRC1[i+63:i]
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBLENDMPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no controlmask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] SRC2[31:0]
ELSE
DEST[i+31:i] SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+31:i] SRC1[i+31:i]
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-10 Vol. 2C
VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VBLENDMPD __m512d _mm512_mask_blend_pd(__mmask8 k, __m512d a, __m512d b);
VBLENDMPD __m256d _mm256_mask_blend_pd(__mmask8 k, __m256d a, __m256d b);
VBLENDMPD __m128d _mm_mask_blend_pd(__mmask8 k, __m128d a, __m128d b);
VBLENDMPS __m512 _mm512_mask_blend_ps(__mmask16 k, __m512 a, __m512 b);
VBLENDMPS __m256 _mm256_mask_blend_ps(__mmask8 k, __m256 a, __m256 b);
VBLENDMPS __m128 _mm_mask_blend_ps(__mmask8 k, __m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.
VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control
Vol. 2C 5-11
INSTRUCTION SET REFERENCE, V-Z
VBROADCAST—Load with Broadcast Floating-Point Data
Opcode/
Instruction
Op /
En
VEX.128.66.0F38.W0 18 /r
VBROADCASTSS xmm1, m32
VEX.256.66.0F38.W0 18 /r
VBROADCASTSS ymm1, m32
VEX.256.66.0F38.W0 19 /r
VBROADCASTSD ymm1, m64
VEX.256.66.0F38.W0 1A /r
VBROADCASTF128 ymm1, m128
EVEX.256.66.0F38.W1 19 /r
VBROADCASTSD ymm1 {k1}{z},
xmm2/m64
EVEX.512.66.0F38.W1 19 /r
VBROADCASTSD zmm1 {k1}{z},
xmm2/m64
EVEX.256.66.0F38.W0 19 /r
VBROADCASTF32X2 ymm1 {k1}{z},
xmm2/m64
EVEX.512.66.0F38.W0 19 /r
VBROADCASTF32X2 zmm1 {k1}{z},
xmm2/m64
EVEX.128.66.0F38.W0 18 /r
VBROADCASTSS xmm1 {k1}{z},
xmm2/m32
EVEX.256.66.0F38.W0 18 /r
VBROADCASTSS ymm1 {k1}{z},
xmm2/m32
EVEX.512.66.0F38.W0 18 /r
VBROADCASTSS zmm1 {k1}{z},
xmm2/m32
EVEX.256.66.0F38.W0 1A /r
VBROADCASTF32X4 ymm1 {k1}{z},
m128
EVEX.512.66.0F38.W0 1A /r
VBROADCASTF32X4 zmm1 {k1}{z},
m128
EVEX.256.66.0F38.W1 1A /r
VBROADCASTF64X2 ymm1 {k1}{z},
m128
EVEX.512.66.0F38.W1 1A /r
VBROADCASTF64X2 zmm1 {k1}{z},
m128
EVEX.512.66.0F38.W0 1B /r
VBROADCASTF32X8 zmm1 {k1}{z},
m256
EVEX.512.66.0F38.W1 1B /r
VBROADCASTF64X4 zmm1 {k1}{z},
m256
5-12 Vol. 2C
CPUID
Feature
Flag
Description
RM
64/32
bit
Mode
Support
V/V
AVX
RM
V/V
AVX
RM
V/V
AVX
RM
V/V
AVX
T1S
V/V
AVX512VL
AVX512F
T1S
V/V
AVX512F
T2
V/V
AVX512VL
AVX512DQ
T2
V/V
AVX512DQ
T1S
V/V
AVX512VL
AVX512F
T1S
V/V
AVX512VL
AVX512F
T1S
V/V
AVX512F
T4
V/V
AVX512VL
AVX512F
Broadcast single-precision floating-point element in
mem to four locations in xmm1.
Broadcast single-precision floating-point element in
mem to eight locations in ymm1.
Broadcast double-precision floating-point element in
mem to four locations in ymm1.
Broadcast 128 bits of floating-point data in mem to
low and high 128-bits in ymm1.
Broadcast low double-precision floating-point element
in xmm2/m64 to four locations in ymm1 using
writemask k1.
Broadcast low double-precision floating-point element
in xmm2/m64 to eight locations in zmm1 using
writemask k1.
Broadcast two single-precision floating-point elements
in xmm2/m64 to locations in ymm1 using writemask
k1.
Broadcast two single-precision floating-point elements
in xmm2/m64 to locations in zmm1 using writemask
k1.
Broadcast low single-precision floating-point element
in xmm2/m32 to all locations in xmm1 using
writemask k1.
Broadcast low single-precision floating-point element
in xmm2/m32 to all locations in ymm1 using
writemask k1.
Broadcast low single-precision floating-point element
in xmm2/m32 to all locations in zmm1 using
writemask k1.
Broadcast 128 bits of 4 single-precision floating-point
data in mem to locations in ymm1 using writemask k1.
T4
V/V
AVX512F
Broadcast 128 bits of 4 single-precision floating-point
data in mem to locations in zmm1 using writemask k1.
T2
V/V
AVX512VL
AVX512DQ
Broadcast 128 bits of 2 double-precision floating-point
data in mem to locations in ymm1 using writemask k1.
T2
V/V
AVX512DQ
Broadcast 128 bits of 2 double-precision floating-point
data in mem to locations in zmm1 using writemask k1.
T8
V/V
AVX512DQ
Broadcast 256 bits of 8 single-precision floating-point
data in mem to locations in zmm1 using writemask k1.
T4
V/V
AVX512F
Broadcast 256 bits of 4 double-precision floating-point
data in mem to locations in zmm1 using writemask k1.
VBROADCAST—Load with Broadcast Floating-Point Data
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1S, T2, T4, T8
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
VBROADCASTSD/VBROADCASTSS/VBROADCASTF128 load floating-point values as one tuple from the source
operand (second operand) in memory and broadcast to all elements of the destination operand (first operand).
VEX256-encoded versions: The destination operand is a YMM register. The source operand is either a 32-bit,
64-bit, or 128-bit memory location. Register source encodings are reserved and will #UD. Bits (MAX_VL1:256) of the destination register are zeroed.
EVEX-encoded versions: The destination operand is a ZMM/YMM/XMM register and updated according to the
writemask k1. The source operand is either a 32-bit, 64-bit memory location or the low
doubleword/quadword element of an XMM register.
VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2/VBROADCASTF32X8/VBROADCASTF64X4 load
floating-point values as tuples from the source operand (the second operand) in memory or register and broadcast
to all elements of the destination operand (the first operand). The destination operand is a YMM/ZMM register
updated according to the writemask k1. The source operand is either a register or 64-bit/128-bit/256-bit memory
location.
VBROADCASTSD and VBROADCASTF128,F32x4 and F64x2 are only supported as 256-bit and 512-bit wide
versions and up. VBROADCASTSS is supported in 128-bit, 256-bit and 512-bit wide versions. F32x8 and F64x4 are
only supported as 512-bit wide versions.
VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF32X8 have 32-bit granularity. VBROADCASTF64X2 and
VBROADCASTF64X4 have 64-bit granularity.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
If VBROADCASTSD or VBROADCASTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded
with VEX.L= 0 will cause an #UD exception.
X0
m32
DEST
X0
X0
X0
X0
X0
X0
X0
X0
Figure 5-1. VBROADCASTSS Operation (VEX.256 encoded version)
X0
m32
DEST
0
0
0
0
X0
X0
X0
X0
Figure 5-2. VBROADCASTSS Operation (VEX.128-bit version)
VBROADCAST—Load with Broadcast Floating-Point Data
Vol. 2C 5-13
INSTRUCTION SET REFERENCE, V-Z
m64
DEST
X0
X0
X0
X0
X0
Figure 5-3. VBROADCASTSD Operation (VEX.256-bit version)
m128
DEST
X0
X0
X0
Figure 5-4. VBROADCASTF128 Operation (VEX.256-bit version)
m256
DEST
X0
X0
X0
Figure 5-5. VBROADCASTF64X4 Operation (512-bit version with writemask all 1s)
Operation
VBROADCASTSS (128 bit version VEX and legacy)
temp SRC[31:0]
DEST[31:0] temp
DEST[63:32] temp
DEST[95:64] temp
DEST[127:96] temp
DEST[MAX_VL-1:128] 0
5-14 Vol. 2C
VBROADCAST—Load with Broadcast Floating-Point Data
INSTRUCTION SET REFERENCE, V-Z
VBROADCASTSS (VEX.256 encoded version)
temp SRC[31:0]
DEST[31:0] temp
DEST[63:32] temp
DEST[95:64] temp
DEST[127:96] temp
DEST[159:128] temp
DEST[191:160] temp
DEST[223:192] temp
DEST[255:224] temp
DEST[MAX_VL-1:256] 0
VBROADCASTSS (EVEX encoded versions)
(KL, VL) (4, 128), (8, 256),= (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCASTSD (VEX.256 encoded version)
temp SRC[63:0]
DEST[63:0] temp
DEST[127:64] temp
DEST[191:128] temp
DEST[255:192] temp
DEST[MAX_VL-1:256] 0
VBROADCASTSD (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCAST—Load with Broadcast Floating-Point Data
Vol. 2C 5-15
INSTRUCTION SET REFERENCE, V-Z
VBROADCASTF32x2 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
n (j mod 2) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCASTF128 (VEX.256 encoded version)
temp SRC[127:0]
DEST[127:0] temp
DEST[255:128] temp
DEST[MAX_VL-1:256] 0
VBROADCASTF32X4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j 0 TO KL-1
i j* 32
n (j modulo 4) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-16 Vol. 2C
VBROADCAST—Load with Broadcast Floating-Point Data
INSTRUCTION SET REFERENCE, V-Z
VBROADCASTF64X2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
n (j modulo 2) * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[n+63:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI
FI;
ENDFOR;
VBROADCASTF32X8 (EVEX.U1.512 encoded version)
FOR j 0 TO 15
i j * 32
n (j modulo 8) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCASTF64X4 (EVEX.512 encoded version)
FOR j 0 TO 7
i j * 64
n (j modulo 4) * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[n+63:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCAST—Load with Broadcast Floating-Point Data
Vol. 2C 5-17
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VBROADCASTF32x2 __m512 _mm512_broadcast_f32x2( __m128 a);
VBROADCASTF32x2 __m512 _mm512_mask_broadcast_f32x2(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x2 __m512 _mm512_maskz_broadcast_f32x2( __mmask16 k, __m128 a);
VBROADCASTF32x2 __m256 _mm256_broadcast_f32x2( __m128 a);
VBROADCASTF32x2 __m256 _mm256_mask_broadcast_f32x2(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x2 __m256 _mm256_maskz_broadcast_f32x2( __mmask8 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_broadcast_f32x4( __m128 a);
VBROADCASTF32x4 __m512 _mm512_mask_broadcast_f32x4(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_maskz_broadcast_f32x4( __mmask16 k, __m128 a);
VBROADCASTF32x4 __m256 _mm256_broadcast_f32x4( __m128 a);
VBROADCASTF32x4 __m256 _mm256_mask_broadcast_f32x4(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x4 __m256 _mm256_maskz_broadcast_f32x4( __mmask8 k, __m128 a);
VBROADCASTF32x8 __m512 _mm512_broadcast_f32x8( __m256 a);
VBROADCASTF32x8 __m512 _mm512_mask_broadcast_f32x8(__m512 s, __mmask16 k, __m256 a);
VBROADCASTF32x8 __m512 _mm512_maskz_broadcast_f32x8( __mmask16 k, __m256 a);
VBROADCASTF64x2 __m512d _mm512_broadcast_f64x2( __m128d a);
VBROADCASTF64x2 __m512d _mm512_mask_broadcast_f64x2(__m512d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m512d _mm512_maskz_broadcast_f64x2( __mmask8 k, __m128d a);
VBROADCASTF64x2 __m256d _mm256_broadcast_f64x2( __m128d a);
VBROADCASTF64x2 __m256d _mm256_mask_broadcast_f64x2(__m256d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m256d _mm256_maskz_broadcast_f64x2( __mmask8 k, __m128d a);
VBROADCASTF64x4 __m512d _mm512_broadcast_f64x4( __m256d a);
VBROADCASTF64x4 __m512d _mm512_mask_broadcast_f64x4(__m512d s, __mmask8 k, __m256d a);
VBROADCASTF64x4 __m512d _mm512_maskz_broadcast_f64x4( __mmask8 k, __m256d a);
VBROADCASTSD __m512d _mm512_broadcastsd_pd( __m128d a);
VBROADCASTSD __m512d _mm512_mask_broadcastsd_pd(__m512d s, __mmask8 k, __m128d a);
VBROADCASTSD __m512d _mm512_maskz_broadcastsd_pd(__mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_broadcastsd_pd(__m128d a);
VBROADCASTSD __m256d _mm256_mask_broadcastsd_pd(__m256d s, __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_maskz_broadcastsd_pd( __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_broadcast_sd(double *a);
VBROADCASTSS __m512 _mm512_broadcastss_ps( __m128 a);
VBROADCASTSS __m512 _mm512_mask_broadcastss_ps(__m512 s, __mmask16 k, __m128 a);
VBROADCASTSS __m512 _mm512_maskz_broadcastss_ps( __mmask16 k, __m128 a);
VBROADCASTSS __m256 _mm256_broadcastss_ps(__m128 a);
VBROADCASTSS __m256 _mm256_mask_broadcast_ss(__m256 s, __mmask8 k, __m128 a);
VBROADCASTSS __m256 _mm256_maskz_broadcast_ss( __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_broadcastss_ps(__m128 a);
VBROADCASTSS __m128 _mm_mask_broadcast_ss(__m128 s, __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_maskz_broadcast_ss( __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_broadcast_ss(float *a);
VBROADCASTSS __m256 _mm256_broadcast_ss(float *a);
VBROADCASTF128 __m256 _mm256_broadcast_ps(__m128 * a);
VBROADCASTF128 __m256d _mm256_broadcast_pd(__m128d * a);
Exceptions
VEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, see Exceptions Type E6.
#UD
If VEX.L = 0 for VBROADCASTSD or VBROADCASTF128.
If EVEX.L’L = 0 for VBROADCASTSD/VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2.
If EVEX.L’L < 10b for VBROADCASTF32X8/VBROADCASTF64X4.
5-18 Vol. 2C
VBROADCAST—Load with Broadcast Floating-Point Data
INSTRUCTION SET REFERENCE, V-Z
VPBROADCASTM—Broadcast Mask to Vector Register
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
AVX512VL
AVX512CD
Description
RM
64/32
bit Mode
Support
V/V
EVEX.128.F3.0F38.W1 2A /r
VPBROADCASTMB2Q xmm1, k1
EVEX.256.F3.0F38.W1 2A /r
VPBROADCASTMB2Q ymm1, k1
RM
V/V
AVX512VL
AVX512CD
Broadcast low byte value in k1 to four locations in ymm1.
EVEX.512.F3.0F38.W1 2A /r
VPBROADCASTMB2Q zmm1, k1
RM
V/V
AVX512CD
Broadcast low byte value in k1 to eight locations in zmm1.
EVEX.128.F3.0F38.W0 3A /r
VPBROADCASTMW2D xmm1, k1
RM
V/V
AVX512VL
AVX512CD
Broadcast low word value in k1 to four locations in xmm1.
EVEX.256.F3.0F38.W0 3A /r
VPBROADCASTMW2D ymm1, k1
RM
V/V
AVX512VL
AVX512CD
Broadcast low word value in k1 to eight locations in ymm1.
EVEX.512.F3.0F38.W0 3A /r
VPBROADCASTMW2D zmm1, k1
RM
V/V
AVX512CD
Broadcast low word value in k1 to sixteen locations in
zmm1.
Broadcast low byte value in k1 to two locations in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Broadcasts the zero-extended 64/32 bit value of the low byte/word of the source operand (the second operand) to
each 64/32 bit element of the destination operand (the first operand). The source operand is an opmask register.
The destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPBROADCASTMB2Q
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j*64
DEST[i+63:i] ZeroExtend(SRC[7:0])
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTMW2D
(KL, VL) = (4, 128), (8, 256),(16, 512)
FOR j 0 TO KL-1
i j*32
DEST[i+31:i] ZeroExtend(SRC[15:0])
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTM—Broadcast Mask to Vector Register
Vol. 2C 5-19
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTMB2Q __m512i _mm512_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);
VPBROADCASTMB2Q __m256i _mm256_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);
VPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6NF.
5-20 Vol. 2C
VPBROADCASTM—Broadcast Mask to Vector Register
INSTRUCTION SET REFERENCE, V-Z
VCOMPRESSPD—Store Sparse Packed Double-Precision Floating-Point Values into Dense
Memory
Opcode/
Instruction
Op /
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W1 8A /r
VCOMPRESSPD xmm1/m128 {k1}{z},
xmm2
EVEX.256.66.0F38.W1 8A /r
VCOMPRESSPD ymm1/m256 {k1}{z},
ymm2
EVEX.512.66.0F38.W1 8A /r
VCOMPRESSPD zmm1/m512 {k1}{z},
zmm2
T1S
V/V
AVX512VL
AVX512F
T1S
V/V
AVX512F
Description
Compress packed double-precision floating-point
values from xmm2 to xmm1/m128 using writemask
k1.
Compress packed double-precision floating-point
values from ymm2 to ymm1/m256 using writemask
k1.
Compress packed double-precision floating-point
values from zmm2 using control mask k1 to
zmm1/m512.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Compress (store) up to 8 double-precision floating-point values from the source operand (the second operand) as
a contiguous vector to the destination operand (the first operand) The source operand is a ZMM/YMM/XMM register,
the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VCOMPRESSPD (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE 64
k0
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] SRC[i+63:i]
k k + SIZE
FI;
ENDFOR
VCOMPRESSPD—Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory
Vol. 2C 5-21
INSTRUCTION SET REFERENCE, V-Z
VCOMPRESSPD (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE 64
k0
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] SRC[i+63:i]
k k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] ← 0
FI
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPD __m512d _mm512_mask_compress_pd( __m512d s, __mmask8 k, __m512d a);
VCOMPRESSPD __m512d _mm512_maskz_compress_pd( __mmask8 k, __m512d a);
VCOMPRESSPD void _mm512_mask_compressstoreu_pd( void * d, __mmask8 k, __m512d a);
VCOMPRESSPD __m256d _mm256_mask_compress_pd( __m256d s, __mmask8 k, __m256d a);
VCOMPRESSPD __m256d _mm256_maskz_compress_pd( __mmask8 k, __m256d a);
VCOMPRESSPD void _mm256_mask_compressstoreu_pd( void * d, __mmask8 k, __m256d a);
VCOMPRESSPD __m128d _mm_mask_compress_pd( __m128d s, __mmask8 k, __m128d a);
VCOMPRESSPD __m128d _mm_maskz_compress_pd( __mmask8 k, __m128d a);
VCOMPRESSPD void _mm_mask_compressstoreu_pd( void * d, __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb.
#UD
5-22 Vol. 2C
If EVEX.vvvv != 1111B.
VCOMPRESSPD—Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory
INSTRUCTION SET REFERENCE, V-Z
VCOMPRESSPS—Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory
Opcode/
Instruction
Op /
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W0 8A /r
VCOMPRESSPS xmm1/m128 {k1}{z},
xmm2
EVEX.256.66.0F38.W0 8A /r
VCOMPRESSPS ymm1/m256 {k1}{z},
ymm2
EVEX.512.66.0F38.W0 8A /r
VCOMPRESSPS zmm1/m512 {k1}{z},
zmm2
T1S
V/V
AVX512VL
AVX512F
T1S
V/V
AVX512F
Description
Compress packed single-precision floating-point
values from xmm2 to xmm1/m128 using writemask
k1.
Compress packed single-precision floating-point
values from ymm2 to ymm1/m256 using writemask
k1.
Compress packed single-precision floating-point
values from zmm2 using control mask k1 to
zmm1/m512.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Compress (stores) up to 16 single-precision floating-point values from the source operand (the second operand) to
the destination operand (the first operand). The source operand is a ZMM/YMM/XMM register, the destination
operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (a partial vector or possibly non-contiguous if less than 16
active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to
the destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VCOMPRESSPS (EVEX encoded versions) store form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE 32
k0
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] SRC[i+31:i]
k k + SIZE
FI;
ENDFOR;
VCOMPRESSPS—Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory
Vol. 2C 5-23
INSTRUCTION SET REFERENCE, V-Z
VCOMPRESSPS (EVEX encoded versions) reg-reg form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE 32
k0
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] SRC[i+31:i]
k k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] 0
FI
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPS __m512 _mm512_mask_compress_ps( __m512 s, __mmask16 k, __m512 a);
VCOMPRESSPS __m512 _mm512_maskz_compress_ps( __mmask16 k, __m512 a);
VCOMPRESSPS void _mm512_mask_compressstoreu_ps( void * d, __mmask16 k, __m512 a);
VCOMPRESSPS __m256 _mm256_mask_compress_ps( __m256 s, __mmask8 k, __m256 a);
VCOMPRESSPS __m256 _mm256_maskz_compress_ps( __mmask8 k, __m256 a);
VCOMPRESSPS void _mm256_mask_compressstoreu_ps( void * d, __mmask8 k, __m256 a);
VCOMPRESSPS __m128 _mm_mask_compress_ps( __m128 s, __mmask8 k, __m128 a);
VCOMPRESSPS __m128 _mm_maskz_compress_ps( __mmask8 k, __m128 a);
VCOMPRESSPS void _mm_mask_compressstoreu_ps( void * d, __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb.
#UD
5-24 Vol. 2C
If EVEX.vvvv != 1111B.
VCOMPRESSPS—Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory
INSTRUCTION SET REFERENCE, V-Z
VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword
Integers
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F.W1 7B /r
VCVTPD2QQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.66.0F.W1 7B /r
VCVTPD2QQ ymm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.66.0F.W1 7B /r
VCVTPD2QQ zmm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Convert two packed double-precision floating-point values from
xmm2/m128/m64bcst to two packed quadword integers in
xmm1 with writemask k1.
Convert four packed double-precision floating-point values from
ymm2/m256/m64bcst to four packed quadword integers in
ymm1 with writemask k1.
Convert eight packed double-precision floating-point values
from zmm2/m512/m64bcst to eight packed quadword integers
in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed double-precision floating-point values in the source operand (second operand) to packed quadword integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C 5-25
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTPD2QQ (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPD2QQ (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[63:0])
ELSE
DEST[i+63:i] Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-26 Vol. 2C
VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2QQ __m512i _mm512_cvtpd_epi64( __m512d a);
VCVTPD2QQ __m512i _mm512_mask_cvtpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_maskz_cvtpd_epi64( __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_cvt_roundpd_epi64( __m512d a, int r);
VCVTPD2QQ __m512i _mm512_mask_cvt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m512i _mm512_maskz_cvt_roundpd_epi64( __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m256i _mm256_mask_cvtpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2QQ __m256i _mm256_maskz_cvtpd_epi64( __mmask8 k, __m256d a);
VCVTPD2QQ __m128i _mm_mask_cvtpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2QQ __m128i _mm_maskz_cvtpd_epi64( __mmask8 k, __m128d a);
VCVTPD2QQ __m256i _mm256_cvtpd_epi64 (__m256d src)
VCVTPD2QQ __m128i _mm_cvtpd_epi64 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD
If EVEX.vvvv != 1111B.
VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C 5-27
INSTRUCTION SET REFERENCE, V-Z
VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned
Doubleword Integers
Opcode
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.0F.W1 79 /r
VCVTPD2UDQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.0F.W1 79 /r
VCVTPD2UDQ xmm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.0F.W1 79 /r
VCVTPD2UDQ ymm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point
values in xmm2/m128/m64bcst to two unsigned
doubleword integers in xmm1 subject to writemask k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four unsigned
doubleword integers in xmm1 subject to writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight unsigned
doubleword integers in ymm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed double-precision floating-point values in the source operand (the second operand) to packed
unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1. The upper bits (MAX_VL-1:256) of the corresponding destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-28 Vol. 2C
VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTPD2UDQ (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
VCVTPD2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0])
ELSE
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C 5-29
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a);
VCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_maskz_cvtpd_epu32( __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_cvt_roundpd_epu32( __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_maskz_cvt_roundpd_epu32( __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm256_maskz_cvtpd_epu32( __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
5-30 Vol. 2C
If EVEX.vvvv != 1111B.
VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, V-Z
VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned
Quadword Integers
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F.W1 79 /r
VCVTPD2UQQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.66.0F.W1 79 /r
VCVTPD2UQQ ymm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.66.0F.W1 79 /r
VCVTPD2UQQ zmm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Convert two packed double-precision floating-point values from
xmm2/mem to two packed unsigned quadword integers in
xmm1 with writemask k1.
Convert fourth packed double-precision floating-point values
from ymm2/mem to four packed unsigned quadword integers
in ymm1 with writemask k1.
Convert eight packed double-precision floating-point values
from zmm2/mem to eight packed unsigned quadword integers
in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed double-precision floating-point values in the source operand (second operand) to packed
unsigned quadword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C 5-31
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTPD2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPD2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[63:0])
ELSE
DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-32 Vol. 2C
VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UQQ __m512i _mm512_cvtpd_epu64( __m512d a);
VCVTPD2UQQ __m512i _mm512_mask_cvtpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_maskz_cvtpd_epu64( __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_cvt_roundpd_epu64( __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_mask_cvt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_maskz_cvt_roundpd_epu64( __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m256i _mm256_mask_cvtpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2UQQ __m256i _mm256_maskz_cvtpd_epu64( __mmask8 k, __m256d a);
VCVTPD2UQQ __m128i _mm_mask_cvtpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UQQ __m128i _mm_maskz_cvtpd_epu64( __mmask8 k, __m128d a);
VCVTPD2UQQ __m256i _mm256_cvtpd_epu64 (__m256d src)
VCVTPD2UQQ __m128i _mm_cvtpd_epu64 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD
If EVEX.vvvv != 1111B.
VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C 5-33
INSTRUCTION SET REFERENCE, V-Z
VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
F16C
VEX.128.66.0F38.W0 13 /r
VCVTPH2PS xmm1, xmm2/m64
Description
VEX.256.66.0F38.W0 13 /r
VCVTPH2PS ymm1, xmm2/m128
RM
V/V
F16C
EVEX.128.66.0F38.W0 13 /r
VCVTPH2PS xmm1 {k1}{z}, xmm2/m64
HVM
V/V
AVX512VL
AVX512F
EVEX.256.66.0F38.W0 13 /r
VCVTPH2PS ymm1 {k1}{z},
xmm2/m128
EVEX.512.66.0F38.W0 13 /r
VCVTPH2PS zmm1 {k1}{z},
ymm2/m256 {sae}
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512F
Convert four packed half precision (16-bit) floatingpoint values in xmm2/m64 to packed single-precision
floating-point value in xmm1.
Convert eight packed half precision (16-bit) floatingpoint values in xmm2/m128 to packed singleprecision floating-point value in ymm1.
Convert four packed half precision (16-bit) floatingpoint values in xmm2/m64 to packed single-precision
floating-point values in xmm1.
Convert eight packed half precision (16-bit) floatingpoint values in xmm2/m128 to packed singleprecision floating-point values in ymm1.
Convert sixteen packed half precision (16-bit)
floating-point values in ymm2/m256 to packed
single-precision floating-point values in zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
HVM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed half precision (16-bits) floating-point values in the low-order bits of the source operand (the
second operand) to packed single-precision floating-point values and writes the converted values into the destination operand (the first operand).
If case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it
0. No denormal exception is reported on MXCSR.
VEX.128 version: The source operand is a XMM register or 64-bit memory location. The destination operand is a
XMM register. The upper bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 version: The source operand is a XMM register or 128-bit memory location. The destination operand is a
YMM register. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit
memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
The diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single precision (in 128 bits) FP values.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
5-34 Vol. 2C
VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values
INSTRUCTION SET REFERENCE, V-Z
VCVTPH2PS xmm1, xmm2/mem64, imm8
127
96
95
64
63
48
47
VH3
convert
127
31
16
15
0
xmm2/mem64
VH1
VH0
convert
convert
convert
96
VS3
32
VH2
95
64
63
VS2
32
VS1
31
0
VS0
xmm1
Figure 5-6. VCVTPH2PS (128-bit Version)
Operation
vCvt_h2s(SRC1[15:0])
{
RETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);
}
VCVTPH2PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
k j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
vCvt_h2s(SRC[k+15:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPH2PS (VEX.256 encoded version)
DEST[31:0] vCvt_h2s(SRC1[15:0]);
DEST[63:32] vCvt_h2s(SRC1[31:16]);
DEST[95:64] vCvt_h2s(SRC1[47:32]);
DEST[127:96] vCvt_h2s(SRC1[63:48]);
DEST[159:128] vCvt_h2s(SRC1[79:64]);
DEST[191:160] vCvt_h2s(SRC1[95:80]);
DEST[223:192] vCvt_h2s(SRC1[111:96]);
DEST[255:224] vCvt_h2s(SRC1[127:112]);
DEST[MAX_VL-1:256] 0
VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values
Vol. 2C 5-35
INSTRUCTION SET REFERENCE, V-Z
VCVTPH2PS (VEX.128 encoded version)
DEST[31:0] vCvt_h2s(SRC1[15:0]);
DEST[63:32] vCvt_h2s(SRC1[31:16]);
DEST[95:64] vCvt_h2s(SRC1[47:32]);
DEST[127:96] vCvt_h2s(SRC1[63:48]);
DEST[MAX_VL-1:128] 0
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2PS __m512 _mm512_cvtph_ps( __m256i a);
VCVTPH2PS __m512 _mm512_mask_cvtph_ps(__m512 s, __mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_maskz_cvtph_ps(__mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_cvt_roundph_ps( __m256i a, int sae);
VCVTPH2PS __m512 _mm512_mask_cvt_roundph_ps(__m512 s, __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m512 _mm512_maskz_cvt_roundph_ps( __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m256 _mm256_mask_cvtph_ps(__m256 s, __mmask8 k, __m128i a);
VCVTPH2PS __m256 _mm256_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_mask_cvtph_ps(__m128 s, __mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_cvtph_ps ( __m128i m1);
VCVTPH2PS __m256 _mm256_cvtph_ps ( __m128i m1)
SIMD Floating-Point Exceptions
Invalid
Other Exceptions
VEX-encoded instructions, see Exceptions Type 11 (do not report #AC);
EVEX-encoded instructions, see Exceptions Type E11.
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
5-36 Vol. 2C
VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values
INSTRUCTION SET REFERENCE, V-Z
VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value
Opcode/
Instruction
Op /
En
MRI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
F16C
VEX.128.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m64, xmm2,
imm8
VEX.256.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m128, ymm2,
imm8
EVEX.128.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m64 {k1}{z},
xmm2, imm8
EVEX.256.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m128 {k1}{z},
ymm2, imm8
EVEX.512.66.0F3A.W0 1D /r ib
VCVTPS2PH ymm1/m256 {k1}{z},
zmm2{sae}, imm8
MRI
V/V
F16C
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512VL
AVX512F
HVM
V/V
AVX512F
Description
Convert four packed single-precision floating-point values
in xmm2 to packed half-precision (16-bit) floating-point
values in xmm1/m64. Imm8 provides rounding controls.
Convert eight packed single-precision floating-point values
in ymm2 to packed half-precision (16-bit) floating-point
values in xmm1/m128. Imm8 provides rounding controls.
Convert four packed single-precision floating-point values
in xmm2 to packed half-precision (16-bit) floating-point
values in xmm1/m64. Imm8 provides rounding controls.
Convert eight packed single-precision floating-point values
in ymm2 to packed half-precision (16-bit) floating-point
values in xmm1/m128. Imm8 provides rounding controls.
Convert sixteen packed single-precision floating-point
values in zmm2 to packed half-precision (16-bit) floatingpoint values in ymm1/m256. Imm8 provides rounding
controls.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MRI
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
HVM
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
Description
Convert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point
values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).
Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is
denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception
will be raised with DE, UE and PE set.
127
127
96
VCVTPS2PH xmm1/mem64, xmm2, imm8
95
64
63
VS3
VS2
VS1
convert
convert
convert
96
95
64
63
32
0
VS0
xmm2
convert
48 47
VH3
31
32 31
VH2
16 15
VH1
0
VH0
xmm1/mem64
Figure 5-7. VCVTPS2PH (128-bit Version)
The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC
field are listed in Table 5-12.
VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value
Vol. 2C 5-37
INSTRUCTION SET REFERENCE, V-Z
Table 5-12. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions
Bits
Imm[1:0]
Imm[2]
Imm[7:3]
Field Name/value
Description
RC=00B
Round to nearest even
RC=01B
Round down
RC=10B
Round up
RC=11B
Truncate
MS1=0
Use imm[1:0] for rounding
MS1=1
Use MXCSR.RC for rounding
Ignored
Ignored by processor
Comment
If Imm[2] = 0
Ignore MXCSR.RC
VEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit
memory location. If the destination operand is a register then the upper bits (MAX_VL-1:64) of corresponding
register are zeroed.
VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit
memory location. If the destination operand is a register, the upper bits (MAX_VL-1:128) of the corresponding
destination register are zeroed.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a
YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask
k1. Bits (MAX_VL-1:256/128/64) of the corresponding destination register are zeroed.
Operation
vCvt_s2h(SRC1[31:0])
{
IF Imm[2] = 0
THEN ; using Imm[1:0] for rounding control, see Table 5-12
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);
ELSE ; using MXCSR.RC for rounding control
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);
FI;
}
VCVTPS2PH (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i]
vCvt_s2h(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
5-38 Vol. 2C
VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value
INSTRUCTION SET REFERENCE, V-Z
VCVTPS2PH (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i]
vCvt_s2h(SRC[k+31:k])
ELSE
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VCVTPS2PH (VEX.256 encoded version)
DEST[15:0] vCvt_s2h(SRC1[31:0]);
DEST[31:16] vCvt_s2h(SRC1[63:32]);
DEST[47:32] vCvt_s2h(SRC1[95:64]);
DEST[63:48] vCvt_s2h(SRC1[127:96]);
DEST[79:64] vCvt_s2h(SRC1[159:128]);
DEST[95:80] vCvt_s2h(SRC1[191:160]);
DEST[111:96] vCvt_s2h(SRC1[223:192]);
DEST[127:112] vCvt_s2h(SRC1[255:224]);
DEST[MAX_VL-1:128] 0
VCVTPS2PH (VEX.128 encoded version)
DEST[15:0] vCvt_s2h(SRC1[31:0]);
DEST[31:16] vCvt_s2h(SRC1[63:32]);
DEST[47:32] vCvt_s2h(SRC1[95:64]);
DEST[63:48] vCvt_s2h(SRC1[127:96]);
DEST[MAX_VL-1:64] 0
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);
VCVTPS2PH __m256i _mm512_mask_cvtps_ph(__m256i s, __mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_maskz_cvtps_ph(__mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_cvt_roundps_ph(__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m256i s, __mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm_mask_cvtps_ph(__m128i s, __mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_maskz_cvtps_ph(__mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_cvtps_ph ( __m128 m1, const int imm);
VCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);
VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value
Vol. 2C 5-39
INSTRUCTION SET REFERENCE, V-Z
Other Exceptions
VEX-encoded instructions, see Exceptions Type 11 (do not report #AC);
EVEX-encoded instructions, see Exceptions Type E11.
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
5-40 Vol. 2C
VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value
INSTRUCTION SET REFERENCE, V-Z
VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned
Doubleword Integer Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.0F.W0 79 /r
VCVTPS2UDQ xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.0F.W0 79 /r
VCVTPS2UDQ ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.0F.W0 79 /r
VCVTPS2UDQ zmm1 {k1}{z},
zmm2/m512/m32bcst{er}
FV
V/V
AVX512F
Description
Convert four packed single precision floating-point
values from xmm2/m128/m32bcst to four packed
unsigned doubleword values in xmm1 subject to
writemask k1.
Convert eight packed single precision floating-point
values from ymm2/m256/m32bcst to eight packed
unsigned doubleword values in ymm1 subject to
writemask k1.
Convert sixteen packed single-precision floating-point
values from zmm2/m512/m32bcst to sixteen packed
unsigned doubleword values in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts sixteen packed single-precision floating-point values in the source operand to sixteen unsigned doubleword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Vol. 2C 5-41
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTPS2UDQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPS2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0])
ELSE
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-42 Vol. 2C
VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UDQ __m512i _mm512_cvtps_epu32( __m512 a);
VCVTPS2UDQ __m512i _mm512_mask_cvtps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_maskz_cvtps_epu32( __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_cvt_roundps_epu32( __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_mask_cvt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_maskz_cvt_roundps_epu32( __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m256i _mm256_cvtps_epu32( __m256d a);
VCVTPS2UDQ __m256i _mm256_mask_cvtps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UDQ __m256i _mm256_maskz_cvtps_epu32( __mmask8 k, __m256 a);
VCVTPS2UDQ __m128i _mm_cvtps_epu32( __m128 a);
VCVTPS2UDQ __m128i _mm_mask_cvtps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UDQ __m128i _mm_maskz_cvtps_epu32( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
If EVEX.vvvv != 1111B.
VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Vol. 2C 5-43
INSTRUCTION SET REFERENCE, V-Z
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed
Quadword Integer Values
Opcode/
Instruction
Op /
En
HV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F.W0 7B /r
VCVTPS2QQ xmm1 {k1}{z},
xmm2/m64/m32bcst
EVEX.256.66.0F.W0 7B /r
VCVTPS2QQ ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.66.0F.W0 7B /r
VCVTPS2QQ zmm1 {k1}{z},
ymm2/m256/m32bcst{er}
HV
V/V
AVX512VL
AVX512DQ
HV
V/V
AVX512DQ
Description
Convert two packed single precision floating-point values from
xmm2/m64/m32bcst to two packed signed quadword values in
xmm1 subject to writemask k1.
Convert four packed single precision floating-point values from
xmm2/m128/m32bcst to four packed signed quadword values
in ymm1 subject to writemask k1.
Convert eight packed single precision floating-point values from
ymm2/m256/m32bcst to eight packed signed quadword values
in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts eight packed single-precision floating-point values in the source operand to eight signed quadword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-44 Vol. 2C
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTPS2QQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPS2QQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Single_Precision_To_QuadInteger(SRC[31:0])
ELSE
DEST[i+63:i]
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
Vol. 2C 5-45
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);
VCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);
VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);
VCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);
VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);
VCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3
#UD
5-46 Vol. 2C
If EVEX.vvvv != 1111B.
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
INSTRUCTION SET REFERENCE, V-Z
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned
Quadword Integer Values
Opcode/
Instruction
Op /
En
HV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F.W0 79 /r
VCVTPS2UQQ xmm1 {k1}{z},
xmm2/m64/m32bcst
EVEX.256.66.0F.W0 79 /r
VCVTPS2UQQ ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.66.0F.W0 79 /r
VCVTPS2UQQ zmm1 {k1}{z},
ymm2/m256/m32bcst{er}
HV
V/V
AVX512VL
AVX512DQ
HV
V/V
AVX512DQ
Description
Convert two packed single precision floating-point values from
zmm2/m64/m32bcst to two packed unsigned quadword values
in zmm1 subject to writemask k1.
Convert four packed single precision floating-point values from
xmm2/m128/m32bcst to four packed unsigned quadword
values in ymm1 subject to writemask k1.
Convert eight packed single precision floating-point values from
ymm2/m256/m32bcst to eight packed unsigned quadword
values in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts up to eight packed single-precision floating-point values in the source operand to unsigned quadword
integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C 5-47
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTPS2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTPS2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Single_Precision_To_UQuadInteger(SRC[31:0])
ELSE
DEST[i+63:i]
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-48 Vol. 2C
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UQQ __m512i _mm512_cvtps_epu64( __m512 a);
VCVTPS2UQQ __m512i _mm512_mask_cvtps_epu64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_maskz_cvtps_epu64( __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_cvt_roundps_epu64( __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_mask_cvt_roundps_epu64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_maskz_cvt_roundps_epu64( __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m256i _mm256_cvtps_epu64( __m256 a);
VCVTPS2UQQ __m256i _mm256_mask_cvtps_epu64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UQQ __m256i _mm256_maskz_cvtps_epu64( __mmask8 k, __m256 a);
VCVTPS2UQQ __m128i _mm_cvtps_epu64( __m128 a);
VCVTPS2UQQ __m128i _mm_mask_cvtps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UQQ __m128i _mm_maskz_cvtps_epu64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3
#UD
If EVEX.vvvv != 1111B.
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C 5-49
INSTRUCTION SET REFERENCE, V-Z
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point
Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.F3.0F.W1 E6 /r
VCVTQQ2PD xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.F3.0F.W1 E6 /r
VCVTQQ2PD ymm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.F3.0F.W1 E6 /r
VCVTQQ2PD zmm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Convert two packed quadword integers from
xmm2/m128/m64bcst to packed double-precision floatingpoint values in xmm1 with writemask k1.
Convert four packed quadword integers from
ymm2/m256/m64bcst to packed double-precision floatingpoint values in ymm1 with writemask k1.
Convert eight packed quadword integers from
zmm2/m512/m64bcst to eight packed double-precision
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed quadword integers in the source operand (second operand) to packed double-precision floatingpoint values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTQQ2PD (EVEX2 encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-50 Vol. 2C
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VCVTQQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+63:i]
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PD __m512d _mm512_cvtepi64_pd( __m512i a);
VCVTQQ2PD __m512d _mm512_mask_cvtepi64_pd( __m512d s, __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_maskz_cvtepi64_pd( __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_cvt_roundepi64_pd( __m512i a, int r);
VCVTQQ2PD __m512d _mm512_mask_cvt_roundepi_ps( __m512d s, __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m512d _mm512_maskz_cvt_roundepi64_pd( __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m256d _mm256_mask_cvtepi64_pd( __m256d s, __mmask8 k, __m256i a);
VCVTQQ2PD __m256d _mm256_maskz_cvtepi64_pd( __mmask8 k, __m256i a);
VCVTQQ2PD __m128d _mm_mask_cvtepi64_pd( __m128d s, __mmask8 k, __m128i a);
VCVTQQ2PD __m128d _mm_maskz_cvtepi64_pd( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD
If EVEX.vvvv != 1111B.
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values
Vol. 2C 5-51
INSTRUCTION SET REFERENCE, V-Z
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point
Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.0F.W1 5B /r
VCVTQQ2PS xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.0F.W1 5B /r
VCVTQQ2PS xmm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.0F.W1 5B /r
VCVTQQ2PS ymm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Convert two packed quadword integers from xmm2/mem to
packed single-precision floating-point values in xmm1 with
writemask k1.
Convert four packed quadword integers from ymm2/mem to
packed single-precision floating-point values in xmm1 with
writemask k1.
Convert eight packed quadword integers from zmm2/mem to
eight packed single-precision floating-point values in ymm1 with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed quadword integers in the source operand (second operand) to packed single-precision floatingpoint values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a YMM/XMM/XMM (lower 64 bits) register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTQQ2PS (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[k+31:k]
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[k+31:k] remains unchanged*
ELSE
; zeroing-masking
DEST[k+31:k] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
5-52 Vol. 2C
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VCVTQQ2PS (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[k+31:k]
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[k+31:k]
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[k+31:k] remains unchanged*
ELSE
; zeroing-masking
DEST[k+31:k] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PS __m256 _mm512_cvtepi64_ps( __m512i a);
VCVTQQ2PS __m256 _mm512_mask_cvtepi64_ps( __m256 s, __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_maskz_cvtepi64_ps( __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_cvt_roundepi64_ps( __m512i a, int r);
VCVTQQ2PS __m256 _mm512_mask_cvt_roundepi_ps( __m256 s, __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m256 _mm512_maskz_cvt_roundepi64_ps( __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m128 _mm256_cvtepi64_ps( __m256i a);
VCVTQQ2PS __m128 _mm256_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm256_maskz_cvtepi64_ps( __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm_cvtepi64_ps( __m128i a);
VCVTQQ2PS __m128 _mm_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m128i a);
VCVTQQ2PS __m128 _mm_maskz_cvtepi64_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD
If EVEX.vvvv != 1111B.
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values
Vol. 2C 5-53
INSTRUCTION SET REFERENCE, V-Z
VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword
Integer
Opcode/
Instruction
Op /
En
T1F
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.LIG.F2.0F.W0 79 /r
VCVTSD2USI r32, xmm1/m64{er}
EVEX.LIG.F2.0F.W1 79 /r
VCVTSD2USI r64, xmm1/m64{er}
T1F
V/N.E.1
AVX512F
Description
Convert one double-precision floating-point value from
xmm1/m64 to one unsigned doubleword integer r32.
Convert one double-precision floating-point value from
xmm1/m64 to one unsigned quadword integer zeroextended into r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a double-precision floating-point value in the source operand (the second operand) to an unsigned
doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or
a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an
XMM register, the double-precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is
returned, where w represents the number of bits in the destination format.
Operation
VCVTSD2USI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
ELSE
DEST[31:0] Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
FI
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);
VCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);
VCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);
VCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.
5-54 Vol. 2C
VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer
INSTRUCTION SET REFERENCE, V-Z
VCVTSS2USI—Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword
Integer
Opcode/
Instruction
Op /
En
T1F
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.LIG.F3.0F.W0 79 /r
VCVTSS2USI r32, xmm1/m32{er}
EVEX.LIG.F3.0F.W1 79 /r
VCVTSS2USI r64, xmm1/m32{er}
T1F
V/N.E.1
AVX512F
Description
Convert one single-precision floating-point value from
xmm1/m32 to one unsigned doubleword integer in r32.
Convert one single-precision floating-point value from
xmm1/m32 to one unsigned quadword integer in r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a single-precision floating-point value in the source operand (the second operand) to an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first
operand). The source operand can be an XMM register or a memory location. The destination operand is a generalpurpose register. When the source operand is an XMM register, the single-precision floating-point value is
contained in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is
returned, where w represents the number of bits in the destination format.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTSS2USI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
ELSE
DEST[31:0] Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2USI unsigned _mm_cvtss_u32( __m128 a);
VCVTSS2USI unsigned _mm_cvt_roundss_u32( __m128 a, int r);
VCVTSS2USI unsigned __int64 _mm_cvtss_u64( __m128 a);
VCVTSS2USI unsigned __int64 _mm_cvt_roundss_u64( __m128 a, int r);
VCVTSS2USI—Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer
Vol. 2C 5-55
INSTRUCTION SET REFERENCE, V-Z
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.
5-56 Vol. 2C
VCVTSS2USI—Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer
INSTRUCTION SET REFERENCE, V-Z
VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Quadword Integers
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F.W1 7A /r
VCVTTPD2QQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.66.0F.W1 7A /r
VCVTTPD2QQ ymm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.66.0F.W1 7A /r
VCVTTPD2QQ zmm1 {k1}{z},
zmm2/m512/m64bcst{sae}
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Convert two packed double-precision floating-point values from
zmm2/m128/m64bcst to two packed quadword integers in
zmm1 using truncation with writemask k1.
Convert four packed double-precision floating-point values
from ymm2/m256/m64bcst to four packed quadword integers
in ymm1 using truncation with writemask k1.
Convert eight packed double-precision floating-point values
from zmm2/m512 to eight packed quadword integers in zmm1
using truncation with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation packed double-precision floating-point values in the source operand (second operand) to
packed quadword integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits
in the destination format) is returned.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2QQ (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C 5-57
INSTRUCTION SET REFERENCE, V-Z
VCVTTPD2QQ (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0])
ELSE
DEST[i+63:i] Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2QQ __m512i _mm512_cvttpd_epi64( __m512d a);
VCVTTPD2QQ __m512i _mm512_mask_cvttpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_maskz_cvttpd_epi64( __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_cvtt_roundpd_epi64( __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_mask_cvtt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_maskz_cvtt_roundpd_epi64( __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m256i _mm256_mask_cvttpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2QQ __m256i _mm256_maskz_cvttpd_epi64( __mmask8 k, __m256d a);
VCVTTPD2QQ __m128i _mm_mask_cvttpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2QQ __m128i _mm_maskz_cvttpd_epi64( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
5-58 Vol. 2C
If EVEX.vvvv != 1111B.
VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers
INSTRUCTION SET REFERENCE, V-Z
VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Unsigned Doubleword Integers
Opcode
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.0F.W1 78 /r
VCVTTPD2UDQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.0F.W1 78 02 /r
VCVTTPD2UDQ xmm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.0F.W1 78 /r
VCVTTPD2UDQ ymm1 {k1}{z},
zmm2/m512/m64bcst{sae}
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point values
in xmm2/m128/m64bcst to two unsigned doubleword
integers in xmm1 using truncation subject to writemask
k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four unsigned
doubleword integers in xmm1 using truncation subject to
writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight unsigned
doubleword integers in ymm1 using truncation subject to
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation packed double-precision floating-point values in the source operand (the second operand)
to packed unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of
bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register
conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of the corresponding destination are
zeroed.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C 5-59
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTTPD2UDQ (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (2, 128), (4, 256),(8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
VCVTTPD2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256),(8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0])
ELSE
DEST[i+31:i]
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
5-60 Vol. 2C
VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2UDQ __m256i _mm512_cvttpd_epu32( __m512d a);
VCVTTPD2UDQ __m256i _mm512_mask_cvttpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_maskz_cvttpd_epu32( __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_cvtt_roundpd_epu32( __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_mask_cvtt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_maskz_cvtt_roundpd_epu32( __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m128i _mm256_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm256_maskz_cvttpd_epu32( __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UDQ __m128i _mm_maskz_cvttpd_epu32( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
If EVEX.vvvv != 1111B.
VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C 5-61
INSTRUCTION SET REFERENCE, V-Z
VCVTTPD2UQQ—Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Unsigned Quadword Integers
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F.W1 78 /r
VCVTTPD2UQQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.66.0F.W1 78 /r
VCVTTPD2UQQ ymm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512DQ
EVEX.512.66.0F.W1 78 /r
VCVTTPD2UQQ zmm1 {k1}{z},
zmm2/m512/m64bcst{sae}
FV
V/V
AVX512DQ
Description
Convert two packed double-precision floating-point values
from xmm2/m128/m64bcst to two packed unsigned
quadword integers in xmm1 using truncation with
writemask k1.
Convert four packed double-precision floating-point values
from ymm2/m256/m64bcst to four packed unsigned
quadword integers in ymm1 using truncation with
writemask k1.
Convert eight packed double-precision floating-point values
from zmm2/mem to eight packed unsigned quadword
integers in zmm1 using truncation with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation packed double-precision floating-point values in the source operand (second operand) to
packed unsigned quadword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of
bits in the destination format.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-62 Vol. 2C
VCVTTPD2UQQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
INSTRUCTION SET REFERENCE, V-Z
VCVTTPD2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[63:0])
ELSE
DEST[i+63:i]
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2UQQ _mm[_mask[z]]_cvtt[_round]pd_epu64
VCVTTPD2UQQ __m512i _mm512_cvttpd_epu64( __m512d a);
VCVTTPD2UQQ __m512i _mm512_mask_cvttpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_maskz_cvttpd_epu64( __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_cvtt_roundpd_epu64( __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_mask_cvtt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_maskz_cvtt_roundpd_epu64( __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m256i _mm256_mask_cvttpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2UQQ __m256i _mm256_maskz_cvttpd_epu64( __mmask8 k, __m256d a);
VCVTTPD2UQQ __m128i _mm_mask_cvttpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UQQ __m128i _mm_maskz_cvttpd_epu64( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
If EVEX.vvvv != 1111B.
VCVTTPD2UQQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C 5-63
INSTRUCTION SET REFERENCE, V-Z
VCVTTPS2UDQ—Convert with Truncation Packed Single-Precision Floating-Point Values to
Packed Unsigned Doubleword Integer Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.0F.W0 78 /r
VCVTTPS2UDQ xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.0F.W0 78 /r
VCVTTPS2UDQ ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.0F.W0 78 /r
VCVTTPS2UDQ zmm1 {k1}{z},
zmm2/m512/m32bcst{sae}
FV
V/V
AVX512F
Description
Convert four packed single precision floating-point
values from xmm2/m128/m32bcst to four packed
unsigned doubleword values in xmm1 using
truncation subject to writemask k1.
Convert eight packed single precision floating-point
values from ymm2/m256/m32bcst to eight packed
unsigned doubleword values in ymm1 using
truncation subject to writemask k1.
Convert sixteen packed single-precision floatingpoint values from zmm2/m512/m32bcst to sixteen
packed unsigned doubleword values in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation packed single-precision floating-point values in the source operand to sixteen unsigned
doubleword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR.
If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised,
and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the
destination format.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or
a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2UDQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-64 Vol. 2C
VCVTTPS2UDQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Val-
INSTRUCTION SET REFERENCE, V-Z
VCVTTPS2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0])
ELSE
DEST[i+31:i]
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UDQ __m512i _mm512_cvttps_epu32( __m512 a);
VCVTTPS2UDQ __m512i _mm512_mask_cvttps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_maskz_cvttps_epu32( __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_cvtt_roundps_epu32( __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_mask_cvtt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_maskz_cvtt_roundps_epu32( __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m256i _mm256_mask_cvttps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2UDQ __m256i _mm256_maskz_cvttps_epu32( __mmask8 k, __m256 a);
VCVTTPS2UDQ __m128i _mm_mask_cvttps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UDQ __m128i _mm_maskz_cvttps_epu32( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2UDQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Val-
Vol. 2C 5-65
INSTRUCTION SET REFERENCE, V-Z
VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to
Packed Singed Quadword Integer Values
Opcode/
Instruction
Op /
En
HV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F.W0 7A /r
VCVTTPS2QQ xmm1 {k1}{z},
xmm2/m64/m32bcst
EVEX.256.66.0F.W0 7A /r
VCVTTPS2QQ ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.66.0F.W0 7A /r
VCVTTPS2QQ zmm1 {k1}{z},
ymm2/m256/m32bcst{sae}
HV
V/V
AVX512VL
AVX512DQ
HV
V/V
AVX512DQ
Description
Convert two packed single precision floating-point values from
xmm2/m64/m32bcst to two packed signed quadword values in
xmm1 using truncation subject to writemask k1.
Convert four packed single precision floating-point values from
xmm2/m128/m32bcst to four packed signed quadword values
in ymm1 using truncation subject to writemask k1.
Convert eight packed single precision floating-point values from
ymm2/m256/m32bcst to eight packed signed quadword values
in zmm1 using truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation packed single-precision floating-point values in the source operand to eight signed quadword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits
in the destination format) is returned.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2QQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-66 Vol. 2C
VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
INSTRUCTION SET REFERENCE, V-Z
VCVTTPS2QQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0])
ELSE
DEST[i+63:i]
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2QQ __m512i _mm512_cvttps_epi64( __m256 a);
VCVTTPS2QQ __m512i _mm512_mask_cvttps_epi64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_maskz_cvttps_epi64( __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_cvtt_roundps_epi64( __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_mask_cvtt_roundps_epi64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_maskz_cvtt_roundps_epi64( __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m256i _mm256_mask_cvttps_epi64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m256i _mm256_maskz_cvttps_epi64( __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_mask_cvttps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_maskz_cvttps_epi64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3.
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
Vol. 2C 5-67
INSTRUCTION SET REFERENCE, V-Z
VCVTTPS2UQQ—Convert with Truncation Packed Single Precision Floating-Point Values to
Packed Unsigned Quadword Integer Values
Opcode/
Instruction
Op /
En
EVEX.128.66.0F.W0 78 /r
VCVTTPS2UQQ xmm1 {k1}{z},
xmm2/m64/m32bcst
EVEX.256.66.0F.W0 78 /r
VCVTTPS2UQQ ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.66.0F.W0 78 /r
VCVTTPS2UQQ zmm1 {k1}{z},
ymm2/m256/m32bcst{sae}
HV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
HV
V/V
AVX512VL
AVX512DQ
HV
V/V
AVX512DQ
Description
Convert two packed single precision floating-point values
from xmm2/m64/m32bcst to two packed unsigned quadword
values in xmm1 using truncation subject to writemask k1.
Convert four packed single precision floating-point values
from xmm2/m128/m32bcst to four packed unsigned
quadword values in ymm1 using truncation subject to
writemask k1.
Convert eight packed single precision floating-point values
from ymm2/m256/m32bcst to eight packed unsigned
quadword values in zmm1 using truncation subject to
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation up to eight packed single-precision floating-point values in the source operand to
unsigned quadword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of
bits in the destination format.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-68 Vol. 2C
VCVTTPS2UQQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
INSTRUCTION SET REFERENCE, V-Z
VCVTTPS2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[31:0])
ELSE
DEST[i+63:i]
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UQQ _mm[_mask[z]]_cvtt[_round]ps_epu64
VCVTTPS2UQQ __m512i _mm512_cvttps_epu64( __m256 a);
VCVTTPS2UQQ __m512i _mm512_mask_cvttps_epu64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_maskz_cvttps_epu64( __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_cvtt_roundps_epu64( __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_mask_cvtt_roundps_epu64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_maskz_cvtt_roundps_epu64( __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m256i _mm256_mask_cvttps_epu64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m256i _mm256_maskz_cvttps_epu64( __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_mask_cvttps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_maskz_cvttps_epu64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3.
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2UQQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C 5-69
INSTRUCTION SET REFERENCE, V-Z
VCVTTSD2USI—Convert with Truncation Scalar Double-Precision Floating-Point Value to
Unsigned Integer
Opcode/
Instruction
Op /
En
T1F
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.LIG.F2.0F.W0 78 /r
VCVTTSD2USI r32, xmm1/m64{sae}
EVEX.LIG.F2.0F.W1 78 /r
VCVTTSD2USI r64, xmm1/m64{sae}
T1F
V/N.E.1
AVX512F
Description
Convert one double-precision floating-point value from
xmm1/m64 to one unsigned doubleword integer r32
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one unsigned quadword integer zeroextended into r64 using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation a double-precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination
operand is a general-purpose register. When the source operand is an XMM register, the double-precision floatingpoint value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of
bits in the destination format.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Operation
VCVTTSD2USI (EVEX encoded version)
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
ELSE
DEST[31:0] Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
FI
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2USI unsigned int _mm_cvttsd_u32(__m128d);
VCVTTSD2USI unsigned int _mm_cvtt_roundsd_u32(__m128d, int sae);
VCVTTSD2USI unsigned __int64 _mm_cvttsd_u64(__m128d);
VCVTTSD2USI unsigned __int64 _mm_cvtt_roundsd_u64(__m128d, int sae);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.
5-70 Vol. 2C
VCVTTSD2USI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer
INSTRUCTION SET REFERENCE, V-Z
VCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to
Unsigned Integer
Opcode/
Instruction
Op /
En
T1F
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.LIG.F3.0F.W0 78 /r
VCVTTSS2USI r32, xmm1/m32{sae}
EVEX.LIG.F3.0F.W1 78 /r
VCVTTSS2USI r64, xmm1/m32{sae}
T1F
V/N.E.1
AVX512F
Description
Convert one single-precision floating-point value from
xmm1/m32 to one unsigned doubleword integer in
r32 using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one unsigned quadword integer in r64
using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts with truncation a single-precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a memory location. The destination operand is
a general-purpose register. When the source operand is an XMM register, the single-precision floating-point value
is contained in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of
bits in the destination format.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
VCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer
Vol. 2C 5-71
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTTSS2USI (EVEX encoded version)
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
ELSE
DEST[31:0] Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSS2USI unsigned int _mm_cvttss_u32( __m128 a);
VCVTTSS2USI unsigned int _mm_cvtt_roundss_u32( __m128 a, int sae);
VCVTTSS2USI unsigned __int64 _mm_cvttss_u64( __m128 a);
VCVTTSS2USI unsigned __int64 _mm_cvtt_roundss_u64( __m128 a, int sae);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.
5-72 Vol. 2C
VCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer
INSTRUCTION SET REFERENCE, V-Z
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
EVEX.128.F3.0F.W0 7A /r
VCVTUDQ2PD xmm1 {k1}{z},
xmm2/m64/m32bcst
EVEX.256.F3.0F.W0 7A /r
VCVTUDQ2PD ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.F3.0F.W0 7A /r
VCVTUDQ2PD zmm1 {k1}{z},
ymm2/m256/m32bcst
HV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
HV
V/V
AVX512VL
AVX512F
HV
V/V
AVX512F
Description
Convert two packed unsigned doubleword integers
from ymm2/m64/m32bcst to packed double-precision
floating-point values in zmm1 with writemask k1.
Convert four packed unsigned doubleword integers
from xmm2/m128/m32bcst to packed doubleprecision floating-point values in zmm1 with
writemask k1.
Convert eight packed unsigned doubleword integers
from ymm2/m256/m32bcst to eight packed doubleprecision floating-point values in zmm1 with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed unsigned doubleword integers in the source operand (second operand) to packed double-precision floating-point values in the destination operand (first operand).
The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a
256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Attempt to encode this instruction with EVEX embedded rounding is ignored.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUDQ2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values
Vol. 2C 5-73
INSTRUCTION SET REFERENCE, V-Z
VCVTUDQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+63:i]
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);
VCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);
VCVTUDQ2PD __m512d _mm512_maskz_cvtepu32_pd( __mmask8 k, __m256i a);
VCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m256d _mm256_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m128d _mm_mask_cvtepu32_pd( __m128d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E5.
#UD
5-74 Vol. 2C
If EVEX.vvvv != 1111B.
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.F2.0F.W0 7A /r
VCVTUDQ2PS xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.F2.0F.W0 7A /r
VCVTUDQ2PS ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.F2.0F.W0 7A /r
VCVTUDQ2PS zmm1 {k1}{z},
zmm2/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert four packed unsigned doubleword integers from
xmm2/m128/m32bcst to packed single-precision
floating-point values in xmm1 with writemask k1.
Convert eight packed unsigned doubleword integers
from ymm2/m256/m32bcst to packed single-precision
floating-point values in zmm1 with writemask k1.
Convert sixteen packed unsigned doubleword integers
from zmm2/m512/m32bcst to sixteen packed singleprecision floating-point values in zmm1 with writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed unsigned doubleword integers in the source operand (second operand) to single-precision
floating-point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUDQ2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values
Vol. 2C 5-75
INSTRUCTION SET REFERENCE, V-Z
VCVTUDQ2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+31:i]
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PS __m512 _mm512_cvtepu32_ps( __m512i a);
VCVTUDQ2PS __m512 _mm512_mask_cvtepu32_ps( __m512 s, __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_maskz_cvtepu32_ps( __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_cvt_roundepu32_ps( __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_mask_cvt_roundepu32_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_maskz_cvt_roundepu32_ps( __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m256 _mm256_cvtepu32_ps( __m256i a);
VCVTUDQ2PS __m256 _mm256_mask_cvtepu32_ps( __m256 s, __mmask8 k, __m256i a);
VCVTUDQ2PS __m256 _mm256_maskz_cvtepu32_ps( __mmask8 k, __m256i a);
VCVTUDQ2PS __m128 _mm_cvtepu32_ps( __m128i a);
VCVTUDQ2PS __m128 _mm_mask_cvtepu32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTUDQ2PS __m128 _mm_maskz_cvtepu32_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
5-76 Vol. 2C
If EVEX.vvvv != 1111B.
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.F3.0F.W1 7A /r
VCVTUQQ2PD xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.F3.0F.W1 7A /r
VCVTUQQ2PD ymm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.F3.0F.W1 7A /r
VCVTUQQ2PD zmm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Convert two packed unsigned quadword integers from
xmm2/m128/m64bcst to two packed double-precision
floating-point values in xmm1 with writemask k1.
Convert four packed unsigned quadword integers from
ymm2/m256/m64bcst to packed double-precision floatingpoint values in ymm1 with writemask k1.
Convert eight packed unsigned quadword integers from
zmm2/m512/m64bcst to eight packed double-precision
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed unsigned quadword integers in the source operand (second operand) to packed double-precision
floating-point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUQQ2PD (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values
Vol. 2C 5-77
INSTRUCTION SET REFERENCE, V-Z
VCVTUQQ2PD (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i]
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+63:i]
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PD __m512d _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PD __m512d _mm512_mask_cvtepu64_ps( __m512d s, __mmask8 k, __m512i a);
VCVTUQQ2PD __m512d _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);
VCVTUQQ2PD __m512d _mm512_cvt_roundepu64_ps( __m512i a, int r);
VCVTUQQ2PD __m512d _mm512_mask_cvt_roundepu64_ps( __m512d s, __mmask8 k, __m512i a, int r);
VCVTUQQ2PD __m512d _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);
VCVTUQQ2PD __m256d _mm256_cvtepu64_ps( __m256i a);
VCVTUQQ2PD __m256d _mm256_mask_cvtepu64_ps( __m256d s, __mmask8 k, __m256i a);
VCVTUQQ2PD __m256d _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);
VCVTUQQ2PD __m128d _mm_cvtepu64_ps( __m128i a);
VCVTUQQ2PD __m128d _mm_mask_cvtepu64_ps( __m128d s, __mmask8 k, __m128i a);
VCVTUQQ2PD __m128d _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
5-78 Vol. 2C
If EVEX.vvvv != 1111B.
VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.F2.0F.W1 7A /r
VCVTUQQ2PS xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.F2.0F.W1 7A /r
VCVTUQQ2PS xmm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.F2.0F.W1 7A /r
VCVTUQQ2PS ymm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Convert two packed unsigned quadword integers from
xmm2/m128/m64bcst to packed single-precision floatingpoint values in zmm1 with writemask k1.
Convert four packed unsigned quadword integers from
ymm2/m256/m64bcst to packed single-precision floatingpoint values in xmm1 with writemask k1.
Convert eight packed unsigned quadword integers from
zmm2/m512/m64bcst to eight packed single-precision
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed unsigned quadword integers in the source operand (second operand) to single-precision floatingpoint values in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUQQ2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values
Vol. 2C 5-79
INSTRUCTION SET REFERENCE, V-Z
VCVTUQQ2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+31:i]
Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PS __m256 _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PS __m256 _mm512_mask_cvtepu64_ps( __m256 s, __mmask8 k, __m512i a);
VCVTUQQ2PS __m256 _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);
VCVTUQQ2PS __m256 _mm512_cvt_roundepu64_ps( __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_mask_cvt_roundepu64_ps( __m256 s, __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m128 _mm256_cvtepu64_ps( __m256i a);
VCVTUQQ2PS __m128 _mm256_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m256i a);
VCVTUQQ2PS __m128 _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);
VCVTUQQ2PS __m128 _mm_cvtepu64_ps( __m128i a);
VCVTUQQ2PS __m128 _mm_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m128i a);
VCVTUQQ2PS __m128 _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD
5-80 Vol. 2C
If EVEX.vvvv != 1111B.
VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VCVTUSI2SD—Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.NDS.LIG.F2.0F.W0 7B /r
VCVTUSI2SD xmm1, xmm2, r/m32
EVEX.NDS.LIG.F2.0F.W1 7B /r
VCVTUSI2SD xmm1, xmm2, r/m64{er}
T1S
V/N.E.1
AVX512F
Description
Convert one unsigned doubleword integer from
r/m32 to one double-precision floating-point value in
xmm1.
Convert one unsigned quadword integer from r/m64
to one double-precision floating-point value in xmm1.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the second
source operand to a double-precision floating-point value in the destination operand. The result is stored in the low
quadword of the destination operand. When conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.
EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.
Operation
VCVTUSI2SD (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0] Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0] Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VCVTUSI2SD—Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value
Vol. 2C 5-81
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SD __m128d _mm_cvtu32_sd( __m128d s, unsigned a);
VCVTUSI2SD __m128d _mm_cvtu64_sd( __m128d s, unsigned __int64 a);
VCVTUSI2SD __m128d _mm_cvt_roundu64_sd( __m128d s, unsigned __int64 a, int r);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
See Exceptions Type E3NF if W1, else type E10NF.
5-82 Vol. 2C
VCVTUSI2SD—Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, V-Z
VCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.NDS.LIG.F3.0F.W0 7B /r
VCVTUSI2SS xmm1, xmm2, r/m32{er}
EVEX.NDS.LIG.F3.0F.W1 7B /r
VCVTUSI2SS xmm1, xmm2, r/m64{er}
T1S
V/N.E.1
AVX512F
Description
Convert one signed doubleword integer from r/m32 to
one single-precision floating-point value in xmm1.
Convert one signed quadword integer from r/m64 to
one single-precision floating-point value in xmm1.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the source
operand (second operand) to a single-precision floating-point value in the destination operand (first operand). The
source operand can be a general-purpose register or a memory location. The destination operand is an XMM
register. The result is stored in the low doubleword of the destination operand. When a conversion is inexact, the
value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding
control bits.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.
VCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value
Vol. 2C 5-83
INSTRUCTION SET REFERENCE, V-Z
Operation
VCVTUSI2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0] Convert_UInteger_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SS __m128 _mm_cvtu32_ss( __m128 s, unsigned a);
VCVTUSI2SS __m128 _mm_cvt_roundu32_ss( __m128 s, unsigned a, int r);
VCVTUSI2SS __m128 _mm_cvtu64_ss( __m128 s, unsigned __int64 a);
VCVTUSI2SS __m128 _mm_cvt_roundu64_ss( __m128 s, unsigned __int64 a, int r);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
See Exceptions Type E3NF.
5-84 Vol. 2C
VCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, V-Z
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
Opcode/
Instruction
Op /
En
FVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
EVEX.NDS.128.66.0F3A.W0 42 /r ib
VDBPSADBW xmm1 {k1}{z}, xmm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W0 42 /r ib
VDBPSADBW ymm1 {k1}{z}, ymm2,
ymm3/m256, imm8
FVM
V/V
AVX512VL
AVX512BW
EVEX.NDS.512.66.0F3A.W0 42 /r ib
VDBPSADBW zmm1 {k1}{z}, zmm2,
zmm3/m512, imm8
FVM
V/V
AVX512BW
Description
Compute packed SAD word results of unsigned bytes in
dword block from xmm2 with unsigned bytes of dword
blocks transformed from xmm3/m128 using the shuffle
controls in imm8. Results are written to xmm1 under the
writemask k1.
Compute packed SAD word results of unsigned bytes in
dword block from ymm2 with unsigned bytes of dword
blocks transformed from ymm3/m256 using the shuffle
controls in imm8. Results are written to ymm1 under the
writemask k1.
Compute packed SAD word results of unsigned bytes in
dword block from zmm2 with unsigned bytes of dword
blocks transformed from zmm3/m512 using the shuffle
controls in imm8. Results are written to zmm1 under the
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Compute packed SAD (sum of absolute differences) word results of unsigned bytes from two 32-bit dword
elements. Packed SAD word results are calculated in multiples of qword superblocks, producing 4 SAD word results
in each 64-bit superblock of the destination register.
Within each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as
follows:
•
The lower two word results are calculated each from the SAD operation between a sliding dword element within
a qword superblock from an intermediate vector with a stationary dword element in the corresponding qword
superblock of the first source operand. The intermediate vector, see “Tmp1” in Figure 5-8, is constructed from
the second source operand the imm8 byte as shuffle control to select dword elements within a 128-bit lane of
the second source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte
offset 0 and 1 within the superblock, respectively. The stationary dword element in the qword superblock from
the first source operand is located at byte offset 0.
•
The next two word results are calculated each from the SAD operation between a sliding dword element within
a qword superblock from the intermediate vector Tmp1 with a second stationary dword element in the corresponding qword superblock of the first source operand. The two sliding dword elements in a qword superblock
of Tmp1 are located at byte offset 2and 3 within the superblock, respectively. The stationary dword element in
the qword superblock from the first source operand is located at byte offset 4.
•
The intermediate vector is constructed in 128-bits lanes. Within each 128-bit lane, each dword element of the
intermediate vector is selected by a two-bit field within the imm8 byte on the corresponding 128-bits of the
second source operand. The imm8 byte serves as dword shuffle control within each 128-bit lanes of the intermediate vector and the second source operand, similarly to PSHUFD.
The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or
a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1 at
16-bit word granularity.
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
Vol. 2C 5-85
INSTRUCTION SET REFERENCE, V-Z
127+128*n
128-bit Lane of Src2
95+128*n
DW3
63+128*n
31+128*n
00B: DW0
01B: DW1
10B: DW2
11B: DW3
imm8 shuffle control
7
127+128*n
5
95+128*n
3
128*n
DW0
DW1
DW2
1
0
63+128*n
31+128*n
128*n
128-bit Lane of Tmp1
Tmp1 qword superblock
55
47
39
31 24
39
31
23
15 8
31
23
15
7
Tmp1 sliding dword
Tmp1 sliding dword
63
55
47
39 32
_
_
_
_
abs
abs
abs
abs
+
Src1 stationary dword 0
Src1 stationary dword 1
47
39
31
_
_
_
_
abs
abs
abs
abs
+
23 16
31
23
15
7
0
31
23
15
7
0
Tmp1 sliding dword
63
55
47
39 32
_
_
_
_
abs
abs
abs
abs
Src1 stationary dword 1
Tmp1 sliding dword
+
63
47
0
31
15
_
_
_
_
abs
abs
abs
abs
+
Src1 stationary dword 0
0
Destination qword superblock
Figure 5-8. 64-bit Super Block of SAD Operation in VDBPSADBW
5-86 Vol. 2C
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
INSTRUCTION SET REFERENCE, V-Z
Operation
VDBPSADBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
Selection of quadruplets:
FOR I = 0 to VL step 128
TMP1[I+31:I] select (SRC2[I+127: I], imm8[1:0])
TMP1[I+63: I+32] select (SRC2[I+127: I], imm8[3:2])
TMP1[I+95: I+64] select (SRC2[I+127: I], imm8[5:4])
TMP1[I+127: I+96] select (SRC2[I+127: I], imm8[7:6])
END FOR
SAD of quadruplets:
FOR I =0 to VL step 64
TMP_DEST[I+15:I] ABS(SRC1[I+7: I] - TMP1[I+7: I]) +
ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) +
ABS(SRC1[I+23: I+16]- TMP1[I+23: I+16]) +
ABS(SRC1[I+31: I+24]- TMP1[I+31: I+24])
TMP_DEST[I+31: I+16] ABS(SRC1[I+7: I] - TMP1[I+15: I+8]) +
ABS(SRC1[I+15: I+8]- TMP1[I+23: I+16]) +
ABS(SRC1[I+23: I+16]- TMP1[I+31: I+24]) +
ABS(SRC1[I+31: I+24]- TMP1[I+39: I+32])
TMP_DEST[I+47: I+32] ABS(SRC1[I+39: I+32] - TMP1[I+23: I+16]) +
ABS(SRC1[I+47: I+40]- TMP1[I+31: I+24]) +
ABS(SRC1[I+55: I+48]- TMP1[I+39: I+32]) +
ABS(SRC1[I+63: I+56]- TMP1[I+47: I+40])
TMP_DEST[I+63: I+48] ABS(SRC1[I+39: I+32] - TMP1[I+31: I+24]) +
ABS(SRC1[I+47: I+40] - TMP1[I+39: I+32]) +
ABS(SRC1[I+55: I+48] - TMP1[I+47: I+40]) +
ABS(SRC1[I+63: I+56] - TMP1[I+55: I+48])
ENDFOR
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TMP_DEST[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
Vol. 2C 5-87
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VDBPSADBW __m512i _mm512_dbsad_epu8(__m512i a, __m512i b);
VDBPSADBW __m512i _mm512_mask_dbsad_epu8(__m512i s, __mmask32 m, __m512i a, __m512i b);
VDBPSADBW __m512i _mm512_maskz_dbsad_epu8(__mmask32 m, __m512i a, __m512i b);
VDBPSADBW __m256i _mm256_dbsad_epu8(__m256i a, __m256i b);
VDBPSADBW __m256i _mm256_mask_dbsad_epu8(__m256i s, __mmask16 m, __m256i a, __m256i b);
VDBPSADBW __m256i _mm256_maskz_dbsad_epu8(__mmask16 m, __m256i a, __m256i b);
VDBPSADBW __m128i _mm_dbsad_epu8(__m128i a, __m128i b);
VDBPSADBW __m128i _mm_mask_dbsad_epu8(__m128i s, __mmask8 m, __m128i a, __m128i b);
VDBPSADBW __m128i _mm_maskz_dbsad_epu8(__mmask8 m, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4NF.nb.
5-88 Vol. 2C
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
INSTRUCTION SET REFERENCE, V-Z
VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory
Opcode/
Instruction
Op /
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W1 88 /r
VEXPANDPD xmm1 {k1}{z},
xmm2/m128
EVEX.256.66.0F38.W1 88 /r
VEXPANDPD ymm1 {k1}{z}, ymm2/m256
EVEX.512.66.0F38.W1 88 /r
VEXPANDPD zmm1 {k1}{z}, zmm2/m512
T1S
V/V
T1S
V/V
AVX512VL
AVX512F
AVX512F
Description
Expand packed double-precision floating-point values
from xmm2/m128 to xmm1 using writemask k1.
Expand packed double-precision floating-point values
from ymm2/m256 to ymm1 using writemask k1.
Expand packed double-precision floating-point values
from zmm2/m512 to zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Expand (load) up to 8/4/2, contiguous, double-precision floating-point values of the input vector in the source
operand (the second operand) to sparse elements in the destination operand (the first operand) selected by the
writemask k1.
The destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a
512/256/128-bit memory location.
The input vector starts from the lowest element in the source operand. The writemask register k1 selects the destination elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VEXPANDPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
k0
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+63:i] SRC[k+63:k];
k k + 64
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory
Vol. 2C 5-89
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VEXPANDPD __m512d _mm512_mask_expand_pd( __m512d s, __mmask8 k, __m512d a);
VEXPANDPD __m512d _mm512_maskz_expand_pd( __mmask8 k, __m512d a);
VEXPANDPD __m512d _mm512_mask_expandloadu_pd( __m512d s, __mmask8 k, void * a);
VEXPANDPD __m512d _mm512_maskz_expandloadu_pd( __mmask8 k, void * a);
VEXPANDPD __m256d _mm256_mask_expand_pd( __m256d s, __mmask8 k, __m256d a);
VEXPANDPD __m256d _mm256_maskz_expand_pd( __mmask8 k, __m256d a);
VEXPANDPD __m256d _mm256_mask_expandloadu_pd( __m256d s, __mmask8 k, void * a);
VEXPANDPD __m256d _mm256_maskz_expandloadu_pd( __mmask8 k, void * a);
VEXPANDPD __m128d _mm_mask_expand_pd( __m128d s, __mmask8 k, __m128d a);
VEXPANDPD __m128d _mm_maskz_expand_pd( __mmask8 k, __m128d a);
VEXPANDPD __m128d _mm_mask_expandloadu_pd( __m128d s, __mmask8 k, void * a);
VEXPANDPD __m128d _mm_maskz_expandloadu_pd( __mmask8 k, void * a);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.nb.
#UD
5-90 Vol. 2C
If EVEX.vvvv != 1111B.
VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory
INSTRUCTION SET REFERENCE, V-Z
VEXPANDPS—Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory
Opcode/
Instruction
Op /
En
EVEX.128.66.0F38.W0 88 /r
VEXPANDPS xmm1 {k1}{z}, xmm2/m128
EVEX.256.66.0F38.W0 88 /r
VEXPANDPS ymm1 {k1}{z}, ymm2/m256
EVEX.512.66.0F38.W0 88 /r
VEXPANDPS zmm1 {k1}{z}, zmm2/m512
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Expand packed single-precision floating-point values
from xmm2/m128 to xmm1 using writemask k1.
Expand packed single-precision floating-point values
from ymm2/m256 to ymm1 using writemask k1.
Expand packed single-precision floating-point values
from zmm2/m512 to zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Expand (load) up to 16/8/4, contiguous, single-precision floating-point values of the input vector in the source
operand (the second operand) to sparse elements of the destination operand (the first operand) selected by the
writemask k1.
The destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a
512/256/128-bit memory location.
The input vector starts from the lowest element in the source operand. The writemask k1 selects the destination
elements (a partial vector or sparse elements if less than 16 elements) to be replaced by the ascending elements
in the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed,
depending on EVEX.z.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VEXPANDPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
k0
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] SRC[k+31:k];
k k + 32
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VEXPANDPS—Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory
Vol. 2C 5-91
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VEXPANDPS __m512 _mm512_mask_expand_ps( __m512 s, __mmask16 k, __m512 a);
VEXPANDPS __m512 _mm512_maskz_expand_ps( __mmask16 k, __m512 a);
VEXPANDPS __m512 _mm512_mask_expandloadu_ps( __m512 s, __mmask16 k, void * a);
VEXPANDPS __m512 _mm512_maskz_expandloadu_ps( __mmask16 k, void * a);
VEXPANDPD __m256 _mm256_mask_expand_ps( __m256 s, __mmask8 k, __m256 a);
VEXPANDPD __m256 _mm256_maskz_expand_ps( __mmask8 k, __m256 a);
VEXPANDPD __m256 _mm256_mask_expandloadu_ps( __m256 s, __mmask8 k, void * a);
VEXPANDPD __m256 _mm256_maskz_expandloadu_ps( __mmask8 k, void * a);
VEXPANDPD __m128 _mm_mask_expand_ps( __m128 s, __mmask8 k, __m128 a);
VEXPANDPD __m128 _mm_maskz_expand_ps( __mmask8 k, __m128 a);
VEXPANDPD __m128 _mm_mask_expandloadu_ps( __m128 s, __mmask8 k, void * a);
VEXPANDPD __m128 _mm_maskz_expandloadu_ps( __mmask8 k, void * a);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.nb.
#UD
5-92 Vol. 2C
If EVEX.vvvv != 1111B.
VEXPANDPS—Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory
INSTRUCTION SET REFERENCE, V-Z
VERR/VERW—Verify a Segment for Reading or Writing
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 00 /4
VERR r/m16
M
Valid
Valid
Set ZF=1 if segment specified with r/m16 can
be read.
0F 00 /5
VERW r/m16
M
Valid
Valid
Set ZF=1 if segment specified with r/m16 can
be written.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable
(VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that
contains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or
writable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable.
This check cannot be performed on system segments.
To set the ZF flag, the following conditions must be met:
•
•
•
•
•
•
The segment selector is not NULL.
The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).
The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).
For the VERR instruction, the segment must be readable.
For the VERW instruction, the segment must be a writable data segment.
If the segment is not a conforming code segment, the segment’s DPL must be greater than or equal to (have
less or the same privilege as) both the CPL and the segment selector's RPL.
The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS
register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a
protection exception, enabling the software to anticipate possible segment access problems.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode. The operand size is fixed at 16 bits.
Operation
IF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))
THEN ZF ← 0; FI;
Read segment descriptor;
IF SegmentDescriptor(DescriptorType) = 0 (* System segment *)
or (SegmentDescriptor(Type) ≠ conforming code segment)
and (CPL > DPL) or (RPL > DPL)
THEN
ZF ← 0;
ELSE
IF ((Instruction = VERR) and (Segment readable))
or ((Instruction = VERW) and (Segment writable))
THEN
ZF ← 1;
FI;
FI;
VERR/VERW—Verify a Segment for Reading or Writing
Vol. 2C 5-93
INSTRUCTION SET REFERENCE, V-Z
Flags Affected
The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is set to 0.
Protected Mode Exceptions
The only exceptions generated for these instructions are those related to illegal addressing of the source operand.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The VERR and VERW instructions are not recognized in real-address mode.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
The VERR and VERW instructions are not recognized in virtual-8086 mode.
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
5-94 Vol. 2C
VERR/VERW—Verify a Segment for Reading or Writing
INSTRUCTION SET REFERENCE, V-Z
VEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point
Values with Less Than 2^-23 Relative Error
Opcode/
Instruction
Op /
En
EVEX.512.66.0F38.W1 C8 /r
VEXP2PD zmm1 {k1}{z},
zmm2/m512/m64bcst {sae}
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes approximations to the exponential 2^x (with less
than 2^-23 of maximum relative error) of the packed doubleprecision floating-point values from zmm2/m512/m64bcst and
stores the floating-point result in zmm1with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Computes the approximate base-2 exponential evaluation of the double-precision floating-point values in the
source operand (the second operand) and stores the results to the destination operand (the first operand) using
the writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VEXP2PD
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+63:i] EXP2_23_DP(SRC[63:0])
ELSE DEST[i+63:i] EXP2_23_DP(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI;
FI;
ENDFOR;
VEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative
Vol. 2C 5-95
INSTRUCTION SET REFERENCE, V-Z
Table 5-13. Special Values Behavior
Source Input
Result
Comments
NaN
QNaN(src)
If (SRC = SNaN) then #I
+∞
+∞
+/-0
1.0f
-∞
+0.0f
Integral value N
2^ (N)
Exact result
Exact result
Intel C/C++ Compiler Intrinsic Equivalent
VEXP2PD __m512d _mm512_exp2a23_round_pd (__m512d a, int sae);
VEXP2PD __m512d _mm512_mask_exp2a23_round_pd (__m512d a, __mmask8 m, __m512d b, int sae);
VEXP2PD __m512d _mm512_maskz_exp2a23_round_pd ( __mmask8 m, __m512d b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Overflow
Other Exceptions
See Exceptions Type E2.
5-96 Vol. 2C
VEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Er-
INSTRUCTION SET REFERENCE, V-Z
VEXP2PS—Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point
Values with Less Than 2^-23 Relative Error
Opcode/
Instruction
Op /
En
EVEX.512.66.0F38.W0 C8 /r
VEXP2PS zmm1 {k1}{z},
zmm2/m512/m32bcst {sae}
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes approximations to the exponential 2^x (with less
than 2^-23 of maximum relative error) of the packed singleprecision floating-point values from zmm2/m512/m32bcst and
stores the floating-point result in zmm1with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Computes the approximate base-2 exponential evaluation of the single-precision floating-point values in the
source operand (the second operand) and store the results in the destination operand (the first operand) using the
writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VEXP2PS
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+31:i] EXP2_23_SP(SRC[31:0])
ELSE DEST[i+31:i] EXP2_23_SP(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR;
VEXP2PS—Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Er-
Vol. 2C 5-97
INSTRUCTION SET REFERENCE, V-Z
Table 5-14. Special Values Behavior
Source Input
Result
Comments
NaN
QNaN(src)
If (SRC = SNaN) then #I
+∞
+∞
+/-0
1.0f
-∞
+0.0f
Integral value N
2^ (N)
Exact result
Exact result
Intel C/C++ Compiler Intrinsic Equivalent
VEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);
VEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);
VEXP2PS __m512 _mm512_maskz_exp2a23_round_ps (__mmask16 m, __m512 b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Overflow
Other Exceptions
See Exceptions Type E2.
5-98 Vol. 2C
VEXP2PS—Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Er-
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extr
act Packed Floating-Point Values
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX
VEX.256.66.0F3A.W0 19 /r ib
VEXTRACTF128 xmm1/m128, ymm2,
imm8
EVEX.256.66.0F3A.W0 19 /r ib
VEXTRACTF32X4 xmm1/m128 {k1}{z},
ymm2, imm8
EVEX.512.66.0F3A.W0 19 /r ib
VEXTRACTF32x4 xmm1/m128 {k1}{z},
zmm2, imm8
EVEX.256.66.0F3A.W1 19 /r ib
VEXTRACTF64X2 xmm1/m128 {k1}{z},
ymm2, imm8
EVEX.512.66.0F3A.W1 19 /r ib
VEXTRACTF64X2 xmm1/m128 {k1}{z},
zmm2, imm8
EVEX.512.66.0F3A.W0 1B /r ib
VEXTRACTF32X8 ymm1/m256 {k1}{z},
zmm2, imm8
EVEX.512.66.0F3A.W1 1B /r ib
VEXTRACTF64x4 ymm1/m256 {k1}{z},
zmm2, imm8
T4
V/V
AVX512VL
AVX512F
T4
V/V
AVX512F
T2
V/V
AVX512VL
AVX512DQ
T2
V/V
AVX512DQ
T8
V/V
AVX512DQ
T4
V/V
AVX512F
Description
Extract 128 bits of packed floating-point values
from ymm2 and store results in xmm1/m128.
Extract 128 bits of packed single-precision floatingpoint values from ymm2 and store results in
xmm1/m128 subject to writemask k1.
Extract 128 bits of packed single-precision floatingpoint values from zmm2 and store results in
xmm1/m128 subject to writemask k1.
Extract 128 bits of packed double-precision
floating-point values from ymm2 and store results
in xmm1/m128 subject to writemask k1.
Extract 128 bits of packed double-precision
floating-point values from zmm2 and store results
in xmm1/m128 subject to writemask k1.
Extract 256 bits of packed single-precision floatingpoint values from zmm2 and store results in
ymm1/m256 subject to writemask k1.
Extract 256 bits of packed double-precision
floating-point values from zmm2 and store results
in ymm1/m256 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
T2, T4, T8
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
Description
VEXTRACTF128/VEXTRACTF32x4 and VEXTRACTF64x2 extract 128-bits of single-precision floating-point values
from the source operand (the second operand) and store to the low 128-bit of the destination operand (the first
operand). The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or
imm8[1:0] as the multiply factor. The destination may be either a vector register or an 128-bit memory location.
VEXTRACTF32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the
writemask.
VEXTRACTF32x8 and VEXTRACTF64x4 extract 256-bits of double-precision floating-point values from the source
operand (second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit
data extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply
factor The destination may be either a vector register or a 256-bit memory location.
VEXTRACTF64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the
writemask.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The high 6 bits of the immediate are ignored.
If VEXTRACTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point Values
Vol. 2C 5-99
INSTRUCTION SET REFERENCE, V-Z
Operation
VEXTRACTF32x4 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
FI;
FOR j 0 TO 3
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:128] 0
5-100 Vol. 2C
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTF32x4 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
FI;
FOR j 0 TO 3
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR
; merging-masking
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point Values
Vol. 2C 5-101
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTF64x2 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
FI;
FOR j 0 TO 1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:128] 0
5-102 Vol. 2C
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTF64x2 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
FI;
FOR j 0 TO 1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE *DEST[i+63:i] remains unchanged*
FI;
ENDFOR
; merging-masking
VEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 7
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:256] 0
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point Values
Vol. 2C 5-103
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is memory
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 7
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR
; merging-masking
VEXTRACTF64x4 (EVEX.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 3
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:256] 0
VEXTRACTF64x4 (EVEX.512 encoded version) when destination is memory
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 3
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
; merging-masking
*DEST[i+63:i] remains unchanged*
FI;
ENDFOR
5-104 Vol. 2C
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTF128 (memory destination form)
CASE (imm8[0]) OF
0: DEST[127:0] SRC1[127:0]
1: DEST[127:0] SRC1[255:128]
ESAC.
VEXTRACTF128 (register destination form)
CASE (imm8[0]) OF
0: DEST[127:0] SRC1[127:0]
1: DEST[127:0] SRC1[255:128]
ESAC.
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VEXTRACTF32x4 __m128 _mm512_extractf32x4_ps(__m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm512_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm512_maskz_extractf32x4_ps( __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_extractf32x4_ps(__m256 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m256 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_maskz_extractf32x4_ps( __mmask8 k, __m256 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_extractf32x8_ps(__m512 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_mask_extractf32x8_ps(__m256 s, __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_maskz_extractf32x8_ps( __mmask8 k, __m512 a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_extractf64x2_pd(__m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_maskz_extractf64x2_pd( __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_extractf64x2_pd(__m256d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m256d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_maskz_extractf64x2_pd( __mmask8 k, __m256d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_extractf64x4_pd( __m512d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_mask_extractf64x4_pd(__m256d s, __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_maskz_extractf64x4_pd( __mmask8 k, __m512d a, const int nidx);
VEXTRACTF128 __m128 _mm256_extractf128_ps (__m256 a, int offset);
VEXTRACTF128 __m128d _mm256_extractf128_pd (__m256d a, int offset);
VEXTRACTF128 __m128i_mm256_extractf128_si256(__m256i a, int offset);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, see Exceptions Type E6NF.
#UD
IF VEX.L = 0.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point Values
Vol. 2C 5-105
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract
packed Integer Values
Opcode/
Instruction
Op /
En
CPUID
Feature
Flag
AVX2
Description
RMI
64/32
bit Mode
Support
V/V
VEX.256.66.0F3A.W0 39 /r ib
VEXTRACTI128 xmm1/m128, ymm2,
imm8
EVEX.256.66.0F3A.W0 39 /r ib
VEXTRACTI32X4 xmm1/m128 {k1}{z},
ymm2, imm8
EVEX.512.66.0F3A.W0 39 /r ib
VEXTRACTI32x4 xmm1/m128 {k1}{z},
zmm2, imm8
EVEX.256.66.0F3A.W1 39 /r ib
VEXTRACTI64X2 xmm1/m128 {k1}{z},
ymm2, imm8
EVEX.512.66.0F3A.W1 39 /r ib
VEXTRACTI64X2 xmm1/m128 {k1}{z},
zmm2, imm8
EVEX.512.66.0F3A.W0 3B /r ib
VEXTRACTI32X8 ymm1/m256 {k1}{z},
zmm2, imm8
EVEX.512.66.0F3A.W1 3B /r ib
VEXTRACTI64x4 ymm1/m256 {k1}{z},
zmm2, imm8
T4
V/V
AVX512VL
AVX512F
T4
V/V
AVX512F
T2
V/V
AVX512VL
AVX512DQ
T2
V/V
AVX512DQ
T8
V/V
AVX512DQ
T4
V/V
AVX512F
Extract 128 bits of double-word integer values
from ymm2 and store results in xmm1/m128
subject to writemask k1.
Extract 128 bits of double-word integer values
from zmm2 and store results in xmm1/m128
subject to writemask k1.
Extract 128 bits of quad-word integer values from
ymm2 and store results in xmm1/m128 subject to
writemask k1.
Extract 128 bits of quad-word integer values from
zmm2 and store results in xmm1/m128 subject to
writemask k1.
Extract 256 bits of double-word integer values
from zmm2 and store results in ymm1/m256
subject to writemask k1.
Extract 256 bits of quad-word integer values from
zmm2 and store results in ymm1/m256 subject to
writemask k1.
Extract 128 bits of integer data from ymm2 and
store results in xmm1/m128.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
T2, T4, T8
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
Description
VEXTRACTI128/VEXTRACTI32x4 and VEXTRACTI64x2 extract 128-bits of doubleword integer values from the
source operand (the second operand) and store to the low 128-bit of the destination operand (the first operand).
The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or imm8[1:0] as
the multiply factor. The destination may be either a vector register or an 128-bit memory location.
VEXTRACTI32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the
writemask.
VEXTRACTI64x2: The low 128-bit of the destination operand is updated at 64-bit granularity according to the
writemask.
VEXTRACTI32x8 and VEXTRACTI64x4 extract 256-bits of quadword integer values from the source operand (the
second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit data
extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply factor
The destination may be either a vector register or a 256-bit memory location.
VEXTRACTI32x8: The low 256-bit of the destination operand is updated at 32-bit granularity according to the
writemask.
5-106 Vol. 2C
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTI64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the
writemask.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The high 7 bits (6 bits in EVEX.512) of the immediate are ignored.
If VEXTRACTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.
Operation
VEXTRACTI32x4 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
FI;
FOR j 0 TO 3
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:128] 0
VEXTRACTI32x4 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values
Vol. 2C 5-107
INSTRUCTION SET REFERENCE, V-Z
FI;
FOR j 0 TO 3
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR
; merging-masking
VEXTRACTI64x2 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
FI;
FOR j 0 TO 1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:128] 0
5-108 Vol. 2C
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTI64x2 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC1[127:0]
1: TMP_DEST[127:0] SRC1[255:128]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC1[127:0]
01: TMP_DEST[127:0] SRC1[255:128]
10: TMP_DEST[127:0] SRC1[383:256]
11: TMP_DEST[127:0] SRC1[511:384]
ESAC.
FI;
FOR j 0 TO 1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE *DEST[i+63:i] remains unchanged*
FI;
ENDFOR
; merging-masking
VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 7
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:256] 0
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values
Vol. 2C 5-109
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is memory
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 7
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR
; merging-masking
VEXTRACTI64x4 (EVEX.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 3
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:256] 0
VEXTRACTI64x4 (EVEX.512 encoded version) when destination is memory
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC1[255:0]
1: TMP_DEST[255:0] SRC1[511:256]
ESAC.
FOR j 0 TO 3
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE *DEST[i+63:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-110 Vol. 2C
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values
INSTRUCTION SET REFERENCE, V-Z
VEXTRACTI128 (memory destination form)
CASE (imm8[0]) OF
0: DEST[127:0] SRC1[127:0]
1: DEST[127:0] SRC1[255:128]
ESAC.
VEXTRACTI128 (register destination form)
CASE (imm8[0]) OF
0: DEST[127:0] SRC1[127:0]
1: DEST[127:0] SRC1[255:128]
ESAC.
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VEXTRACTI32x4 __m128i _mm512_extracti32x4_epi32(__m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm512_mask_extracti32x4_epi32(__m128i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm512_maskz_extracti32x4_epi32( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm256_extracti32x4_epi32(__m256i a, const int nidx);
VEXTRACTI32x4 __m128i _mm256_mask_extracti32x4_epi32(__m128i s, __mmask8 k, __m256i a, const int nidx);
VEXTRACTI32x4 __m128i _mm256_maskz_extracti32x4_epi32( __mmask8 k, __m256i a, const int nidx);
VEXTRACTI32x8 __m256i _mm512_extracti32x8_epi32(__m512i a, const int nidx);
VEXTRACTI32x8 __m256i _mm512_mask_extracti32x8_epi32(__m256i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x8 __m256i _mm512_maskz_extracti32x8_epi32( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm512_extracti64x2_epi64(__m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm512_mask_extracti64x2_epi64(__m128i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm512_maskz_extracti64x2_epi64( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm256_extracti64x2_epi64(__m256i a, const int nidx);
VEXTRACTI64x2 __m128i _mm256_mask_extracti64x2_epi64(__m128i s, __mmask8 k, __m256i a, const int nidx);
VEXTRACTI64x2 __m128i _mm256_maskz_extracti64x2_epi64( __mmask8 k, __m256i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_extracti64x4_epi64(__m512i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_mask_extracti64x4_epi64(__m256i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_maskz_extracti64x4_epi64( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI128 __m128i _mm256_extracti128_si256(__m256i a, int offset);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, see Exceptions Type E6NF.
#UD
IF VEX.L = 0.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values
Vol. 2C 5-111
INSTRUCTION SET REFERENCE, V-Z
VFIXUPIMMPD—Fix Up Special Packed Float64 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F3A.W1 54 /r ib
VFIXUPIMMPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst, imm8
EVEX.NDS.256.66.0F3A.W1 54 /r ib
VFIXUPIMMPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst, imm8
EVEX.NDS.512.66.0F3A.W1 54 /r ib
VFIXUPIMMPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{sae}, imm8
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Fix up special numbers in float64 vector xmm1, float64
vector xmm2 and int64 vector xmm3/m128/m64bcst
and store the result in xmm1, under writemask.
Fix up special numbers in float64 vector ymm1, float64
vector ymm2 and int64 vector ymm3/m256/m64bcst
and store the result in ymm1, under writemask.
Fix up elements of float64 vector in zmm2 using int64
vector table in zmm3/m512/m64bcst, combine with
preserved elements from zmm1, and store the result in
zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (r, w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Perform fix-up of quad-word elements encoded in double-precision floating-point format in the first source operand
(the second operand) using a 32-bit, two-level look-up table specified in the corresponding quadword element of
the second source operand (the third operand) with exception reporting specifier imm8. The elements that are
fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table
response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from
the first source operand and the preserved element in the first operand are combined as the final results in the
destination operand (the first operand).
The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64bit memory location.
The two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source
so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incorrect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in the destination with the corresponding bit clear in k1 retain their
previous values or are set to 0.
5-112 Vol. 2C
VFIXUPIMMPD—Fix Up Special Packed Float64 Values
INSTRUCTION SET REFERENCE, V-Z
Operation
enum TOKEN_TYPE
{
QNAN_TOKEN 0,
SNAN_TOKEN 1,
ZERO_VALUE_TOKEN 2,
POS_ONE_VALUE_TOKEN 3,
NEG_INF_TOKEN 4,
POS_INF_TOKEN 5,
NEG_VALUE_TOKEN 6,
POS_VALUE_TOKEN 7
}
FIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){
tsrc[63:0] ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]
CASE(tsrc[63:0] of TOKEN_TYPE) {
QNAN_TOKEN: j 0;
SNAN_TOKEN: j 1;
ZERO_VALUE_TOKEN: j 2;
POS_ONE_VALUE_TOKEN: j 3;
NEG_INF_TOKEN: j 4;
POS_INF_TOKEN: j 5;
NEG_VALUE_TOKEN: j 6;
POS_VALUE_TOKEN: j 7;
}
; end source special CASE(tsrc…)
; The required response from src3 table is extracted
token_response[3:0] = tbl3[3+4*j:4*j];
CASE(token_response[3:0]) {
0000: dest[63:0] dest[63:0] ;
; preserve content of DEST
0001: dest[63:0] tsrc[63:0];
; pass through src1 normal input value, denormal as zero
0010: dest[63:0] QNaN(tsrc[63:0]);
0011: dest[63:0] QNAN_Indefinite;
0100: dest[63:0] -INF;
0101: dest[63:0] +INF;
0110: dest[63:0] tsrc.sign? –INF : +INF;
0111: dest[63:0] -0;
1000: dest[63:0] +0;
1001: dest[63:0] -1;
1010: dest[63:0] +1;
1011: dest[63:0] ½;
1100: dest[63:0] 90.0;
1101: dest[63:0] PI/2;
1110: dest[63:0] MAX_FLOAT;
1111: dest[63:0] -MAX_FLOAT;
}
; end of token_response CASE
VFIXUPIMMPD—Fix Up Special Packed Float64 Values
Vol. 2C 5-113
INSTRUCTION SET REFERENCE, V-Z
}
; The required fault reporting from imm8 is extracted
; TOKENs are mutually exclusive and TOKENs priority defines the order.
; Multiple faults related to a single token can occur simultaneously.
IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
; end fault reporting
return dest[63:0];
; end of FIXUPIMM_DP()
VFIXUPIMMPD
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[63:0], imm8 [7:0])
ELSE
DEST[i+63:i] FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[i+63:i], imm8 [7:0])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-114 Vol. 2C
VFIXUPIMMPD—Fix Up Special Packed Float64 Values
INSTRUCTION SET REFERENCE, V-Z
Immediate Control Description:
7 6 5 4 3 2 1 0
+ INF
- VE
- INF
SNaN
ONE
ONE
ZERO
ZERO
#IE
#IE
#IE
#IE
#IE
#ZE
#IE
#ZE
Figure 5-9. VFIXUPIMMPD Immediate Control Description
Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMPD __m512d _mm512_fixupimm_pd( __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_mask_fixupimm_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_pd( __mmask8 k, __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_fixupimm_round_pd( __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m512d _mm512_mask_fixupimm_round_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_round_pd( __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m256d _mm256_fixupimm_pd( __m256d a, __m256i tbl, int imm);
VFIXUPIMMPD __m256d _mm256_mask_fixupimm_pd(__m256d s, __mmask8 k, __m256d a, __m256i tbl, int imm);
VFIXUPIMMPD __m256d _mm256_maskz_fixupimm_pd( __mmask8 k, __m256d a, __m256i tbl, int imm);
VFIXUPIMMPD __m128d _mm_fixupimm_pd( __m128d a, __m128i tbl, int imm);
VFIXUPIMMPD __m128d _mm_mask_fixupimm_pd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMPD __m128d _mm_maskz_fixupimm_pd( __mmask8 k, __m128d a, __m128i tbl, int imm);
SIMD Floating-Point Exceptions
Zero, Invalid
Other Exceptions
See Exceptions Type E2.
VFIXUPIMMPD—Fix Up Special Packed Float64 Values
Vol. 2C 5-115
INSTRUCTION SET REFERENCE, V-Z
VFIXUPIMMPS—Fix Up Special Packed Float32 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F3A.W0 54 /r
VFIXUPIMMPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst, imm8
EVEX.NDS.256.66.0F3A.W0 54 /r
VFIXUPIMMPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst, imm8
EVEX.NDS.512.66.0F3A.W0 54 /r ib
VFIXUPIMMPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{sae}, imm8
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Fix up special numbers in float32 vector xmm1, float32
vector xmm2 and int32 vector xmm3/m128/m32bcst
and store the result in xmm1, under writemask.
Fix up special numbers in float32 vector ymm1, float32
vector ymm2 and int32 vector ymm3/m256/m32bcst
and store the result in ymm1, under writemask.
Fix up elements of float32 vector in zmm2 using int32
vector table in zmm3/m512/m32bcst, combine with
preserved elements from zmm1, and store the result in
zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (r, w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Perform fix-up of doubleword elements encoded in single-precision floating-point format in the first source operand
(the second operand) using a 32-bit, two-level look-up table specified in the corresponding doubleword element of
the second source operand (the third operand) with exception reporting specifier imm8. The elements that are
fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table
response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from
the first source operand and the preserved element in the first operand are combined as the final results in the
destination operand (the first operand).
The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64bit memory location.
The two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source
so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incorrect result. To deal with this, VFIXUPIMMPS can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.
5-116 Vol. 2C
VFIXUPIMMPS—Fix Up Special Packed Float32 Values
INSTRUCTION SET REFERENCE, V-Z
Operation
enum TOKEN_TYPE
{
QNAN_TOKEN 0,
SNAN_TOKEN 1,
ZERO_VALUE_TOKEN 2,
POS_ONE_VALUE_TOKEN 3,
NEG_INF_TOKEN 4,
POS_INF_TOKEN 5,
NEG_VALUE_TOKEN 6,
POS_VALUE_TOKEN 7
}
FIXUPIMM_SP ( dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){
tsrc[31:0] ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]
CASE(tsrc[63:0] of TOKEN_TYPE) {
QNAN_TOKEN: j 0;
SNAN_TOKEN: j 1;
ZERO_VALUE_TOKEN: j 2;
POS_ONE_VALUE_TOKEN: j 3;
NEG_INF_TOKEN: j 4;
POS_INF_TOKEN: j 5;
NEG_VALUE_TOKEN: j 6;
POS_VALUE_TOKEN: j 7;
}
; end source special CASE(tsrc…)
; The required response from src3 table is extracted
token_response[3:0] = tbl3[3+4*j:4*j];
CASE(token_response[3:0]) {
0000: dest[31:0] dest[31:0];
; preserve content of DEST
0001: dest[31:0] tsrc[31:0];
; pass through src1 normal input value, denormal as zero
0010: dest[31:0] QNaN(tsrc[31:0]);
0011: dest[31:0] QNAN_Indefinite;
0100: dest[31:0] -INF;
0101: dest[31:0] +INF;
0110: dest[31:0] tsrc.sign? –INF : +INF;
0111: dest[31:0] -0;
1000: dest[31:0] +0;
1001: dest[31:0] -1;
1010: dest[31:0] +1;
1011: dest[31:0] ½;
1100: dest[31:0] 90.0;
1101: dest[31:0] PI/2;
1110: dest[31:0] MAX_FLOAT;
1111: dest[31:0] -MAX_FLOAT;
}
; end of token_response CASE
VFIXUPIMMPS—Fix Up Special Packed Float32 Values
Vol. 2C 5-117
INSTRUCTION SET REFERENCE, V-Z
}
; The required fault reporting from imm8 is extracted
; TOKENs are mutually exclusive and TOKENs priority defines the order.
; Multiple faults related to a single token can occur simultaneously.
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
; end fault reporting
return dest[31:0];
; end of FIXUPIMM_SP()
VFIXUPIMMPS (EVEX)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[31:0], imm8 [7:0])
ELSE
DEST[i+31:i] FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[i+31:i], imm8 [7:0])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
; zeroing-masking
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-118 Vol. 2C
VFIXUPIMMPS—Fix Up Special Packed Float32 Values
INSTRUCTION SET REFERENCE, V-Z
Immediate Control Description:
7 6 5 4 3 2 1 0
+ INF
- VE
- INF
SNaN
ONE
ONE
ZERO
ZERO
#IE
#IE
#IE
#IE
#IE
#ZE
#IE
#ZE
Figure 5-10. VFIXUPIMMPS Immediate Control Description
Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMPS __m512 _mm512_fixupimm_ps( __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_mask_fixupimm_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_ps( __mmask16 k, __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_fixupimm_round_ps( __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m512 _mm512_mask_fixupimm_round_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_round_ps( __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m256 _mm256_fixupimm_ps( __m256 a, __m256i tbl, int imm);
VFIXUPIMMPS __m256 _mm256_mask_fixupimm_ps(__m256 s, __mmask8 k, __m256 a, __m256i tbl, int imm);
VFIXUPIMMPS __m256 _mm256_maskz_fixupimm_ps( __mmask8 k, __m256 a, __m256i tbl, int imm);
VFIXUPIMMPS __m128 _mm_fixupimm_ps( __m128 a, __m128i tbl, int imm);
VFIXUPIMMPS __m128 _mm_mask_fixupimm_ps(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm);
VFIXUPIMMPS __m128 _mm_maskz_fixupimm_ps( __mmask8 k, __m128 a, __m128i tbl, int imm);
SIMD Floating-Point Exceptions
Zero, Invalid
Other Exceptions
See Exceptions Type E2.
VFIXUPIMMPS—Fix Up Special Packed Float32 Values
Vol. 2C 5-119
INSTRUCTION SET REFERENCE, V-Z
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W1 55 /r ib
VFIXUPIMMSD xmm1 {k1}{z},
xmm2, xmm3/m64{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Fix up a float64 number in the low quadword element of
xmm2 using scalar int32 table in xmm3/m64 and store the
result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (r, w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Perform a fix-up of the low quadword element encoded in double-precision floating-point format in the first source
operand (the second operand) using a 32-bit, two-level look-up table specified in the low quadword element of the
second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-up is
selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action of
0000b preserves the corresponding element of the first operand. The fixed-up element from the first source
operand or the preserved element in the first operand becomes the low quadword element of the destination
operand (the first operand). Bits 127:64 of the destination operand is copied from the corresponding bits of the first
source operand. The destination and first source operands are XMM registers. The second source operand can be a
XMM register or a 64- bit memory location.
The two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source
so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incorrect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.
Operation
enum TOKEN_TYPE
{
QNAN_TOKEN 0,
SNAN_TOKEN 1,
ZERO_VALUE_TOKEN 2,
POS_ONE_VALUE_TOKEN 3,
NEG_INF_TOKEN 4,
POS_INF_TOKEN 5,
NEG_VALUE_TOKEN 6,
POS_VALUE_TOKEN 7
}
5-120 Vol. 2C
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value
INSTRUCTION SET REFERENCE, V-Z
FIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){
tsrc[63:0] ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]
CASE(tsrc[63:0] of TOKEN_TYPE) {
QNAN_TOKEN: j 0;
SNAN_TOKEN: j 1;
ZERO_VALUE_TOKEN: j 2;
POS_ONE_VALUE_TOKEN: j 3;
NEG_INF_TOKEN: j 4;
POS_INF_TOKEN: j 5;
NEG_VALUE_TOKEN: j 6;
POS_VALUE_TOKEN: j 7;
}
; end source special CASE(tsrc…)
; The required response from src3 table is extracted
token_response[3:0] = tbl3[3+4*j:4*j];
CASE(token_response[3:0]) {
0000: dest[63:0] dest[63:0]
; preserve content of DEST
0001: dest[63:0] tsrc[63:0];
; pass through src1 normal input value, denormal as zero
0010: dest[63:0] QNaN(tsrc[63:0]);
0011: dest[63:0] QNAN_Indefinite;
0100:dest[63:0] -INF;
0101: dest[63:0] +INF;
0110: dest[63:0] tsrc.sign? –INF : +INF;
0111: dest[63:0] -0;
1000: dest[63:0] +0;
1001: dest[63:0] -1;
1010: dest[63:0] +1;
1011: dest[63:0] ½;
1100: dest[63:0] 90.0;
1101: dest[63:0] PI/2;
1110: dest[63:0] MAX_FLOAT;
1111: dest[63:0] -MAX_FLOAT;
}
; end of token_response CASE
}
; The required fault reporting from imm8 is extracted
; TOKENs are mutually exclusive and TOKENs priority defines the order.
; Multiple faults related to a single token can occur simultaneously.
IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
; end fault reporting
return dest[63:0];
; end of FIXUPIMM_DP()
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value
Vol. 2C 5-121
INSTRUCTION SET REFERENCE, V-Z
VFIXUPIMMSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[63:0] FIXUPIMM_DP(DEST[63:0], SRC1[63:0], SRC2[63:0], imm8 [7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE DEST[63:0] 0
; zeroing-masking
FI
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Immediate Control Description:
7 6 5 4 3 2 1 0
+ INF
- VE
- INF
SNaN
ONE
ONE
ZERO
ZERO
#IE
#IE
#IE
#IE
#IE
#ZE
#IE
#ZE
Figure 5-11. VFIXUPIMMSD Immediate Control Description
Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMSD __m128d _mm_fixupimm_sd( __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_mask_fixupimm_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_maskz_fixupimm_sd( __mmask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_fixupimm_round_sd( __m128d a, __m128i tbl, int imm, int sae);
VFIXUPIMMSD __m128d _mm_mask_fixupimm_round_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);
VFIXUPIMMSD __m128d _mm_maskz_fixupimm_round_sd( __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);
SIMD Floating-Point Exceptions
Zero, Invalid
Other Exceptions
See Exceptions Type E3.
5-122 Vol. 2C
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value
INSTRUCTION SET REFERENCE, V-Z
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W0 55 /r ib
VFIXUPIMMSS xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Fix up a float32 number in the low doubleword element
in xmm2 using scalar int32 table in xmm3/m32 and store
the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (r, w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Perform a fix-up of the low doubleword element encoded in single-precision floating-point format in the first source
operand (the second operand) using a 32-bit, two-level look-up table specified in the low doubleword element of
the second source operand (the third operand) with exception reporting specifier imm8. The element that is fixedup is selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action
of 0000b preserves the corresponding element of the first operand. The fixed-up element from the first source
operand or the preserved element in the first operand becomes the low doubleword element of the destination
operand (the first operand) Bits 127:32 of the destination operand is copied from the corresponding bits of the first
source operand. The destination and first source operands are XMM registers. The second source operand can be a
XMM register or a 32-bit memory location.
The two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one
source so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incorrect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.
Operation
enum TOKEN_TYPE
{
QNAN_TOKEN 0,
SNAN_TOKEN 1,
ZERO_VALUE_TOKEN 2,
POS_ONE_VALUE_TOKEN 3,
NEG_INF_TOKEN 4,
POS_INF_TOKEN 5,
NEG_VALUE_TOKEN 6,
POS_VALUE_TOKEN 7
}
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value
Vol. 2C 5-123
INSTRUCTION SET REFERENCE, V-Z
FIXUPIMM_SP (dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){
tsrc[31:0] ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]
CASE(tsrc[63:0] of TOKEN_TYPE) {
QNAN_TOKEN: j 0;
SNAN_TOKEN: j 1;
ZERO_VALUE_TOKEN: j 2;
POS_ONE_VALUE_TOKEN: j 3;
NEG_INF_TOKEN: j 4;
POS_INF_TOKEN: j 5;
NEG_VALUE_TOKEN: j 6;
POS_VALUE_TOKEN: j = 7;
}
; end source special CASE(tsrc…)
; The required response from src3 table is extracted
token_response[3:0] = tbl3[3+4*j:4*j];
CASE(token_response[3:0]) {
0000: dest[31:0] dest[31:0];
; preserve content of DEST
0001: dest[31:0] tsrc[31:0];
; pass through src1 normal input value, denormal as zero
0010: dest[31:0] QNaN(tsrc[31:0]);
0011: dest[31:0] QNAN_Indefinite;
0100: dest[31:0] -INF;
0101: dest[31:0] +INF;
0110: dest[31:0] tsrc.sign? –INF : +INF;
0111: dest[31:0] -0;
1000: dest[31:0] +0;
1001: dest[31:0] -1;
1010: dest[31:0] +1;
1011: dest[31:0] ½;
1100: dest[31:0] 90.0;
1101: dest[31:0] PI/2;
1110: dest[31:0] MAX_FLOAT;
1111: dest[31:0] -MAX_FLOAT;
}
; end of token_response CASE
}
; The required fault reporting from imm8 is extracted
; TOKENs are mutually exclusive and TOKENs priority defines the order.
; Multiple faults related to a single token can occur simultaneously.
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
; end fault reporting
return dest[31:0];
; end of FIXUPIMM_SP()
5-124 Vol. 2C
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value
INSTRUCTION SET REFERENCE, V-Z
VFIXUPIMMSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[31:0] FIXUPIMM_SP(DEST[31:0], SRC1[31:0], SRC2[31:0], imm8 [7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE DEST[31:0] 0
; zeroing-masking
FI
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
Immediate Control Description:
7 6 5 4 3 2 1 0
+ INF
- VE
- INF
SNaN
ONE
ONE
ZERO
ZERO
#IE
#IE
#IE
#IE
#IE
#ZE
#IE
#ZE
Figure 5-12. VFIXUPIMMSS Immediate Control Description
Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMSS __m128 _mm_fixupimm_ss( __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_mask_fixupimm_ss(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_maskz_fixupimm_ss( __mmask8 k, __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_fixupimm_round_ss( __m128 a, __m128i tbl, int imm, int sae);
VFIXUPIMMSS __m128 _mm_mask_fixupimm_round_ss(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);
VFIXUPIMMSS __m128 _mm_maskz_fixupimm_round_ss( __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);
SIMD Floating-Point Exceptions
Zero, Invalid
Other Exceptions
See Exceptions Type E3.
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value
Vol. 2C 5-125
INSTRUCTION SET REFERENCE, V-Z
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed DoublePrecision Floating-Point Values
Opcode/
Instruction
Op/
En
VEX.NDS.128.66.0F38.W1 98 /r
VFMADD132PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 A8 /r
VFMADD213PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 B8 /r
VFMADD231PD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W1 98 /r
VFMADD132PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 A8 /r
VFMADD213PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 B8 /r
VFMADD231PD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W1 98 /r
VFMADD132PD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.128.66.0F38.W1 A8 /r
VFMADD213PD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.128.66.0F38.W1 B8 /r
VFMADD231PD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 98 /r
VFMADD132PD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.256.66.0F38.W1 A8 /r
VFMADD213PD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.256.66.0F38.W1 B8 /r
VFMADD231PD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 98 /r
VFMADD132PD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 A8 /r
VFMADD213PD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 B8 /r
VFMADD231PD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
5-126 Vol. 2C
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
Description
Multiply packed double-precision floating-point
values from xmm1 and xmm3/mem, add to xmm2
and put result in xmm1.
Multiply packed double-precision floating-point
values from xmm1 and xmm2, add to xmm3/mem
and put result in xmm1.
Multiply packed double-precision floating-point
values from xmm2 and xmm3/mem, add to xmm1
and put result in xmm1.
Multiply packed double-precision floating-point
values from ymm1 and ymm3/mem, add to ymm2
and put result in ymm1.
Multiply packed double-precision floating-point
values from ymm1 and ymm2, add to ymm3/mem
and put result in ymm1.
Multiply packed double-precision floating-point
values from ymm2 and ymm3/mem, add to ymm1
and put result in ymm1.
Multiply packed double-precision floating-point
values from xmm1 and xmm3/m128/m64bcst, add
to xmm2 and put result in xmm1.
Multiply packed double-precision floating-point
values from xmm1 and xmm2, add to
xmm3/m128/m64bcst and put result in xmm1.
Multiply packed double-precision floating-point
values from xmm2 and xmm3/m128/m64bcst, add
to xmm1 and put result in xmm1.
Multiply packed double-precision floating-point
values from ymm1 and ymm3/m256/m64bcst, add
to ymm2 and put result in ymm1.
Multiply packed double-precision floating-point
values from ymm1 and ymm2, add to
ymm3/m256/m64bcst and put result in ymm1.
Multiply packed double-precision floating-point
values from ymm2 and ymm3/m256/m64bcst, add
to ymm1 and put result in ymm1.
Multiply packed double-precision floating-point
values from zmm1 and zmm3/m512/m64bcst, add
to zmm2 and put result in zmm1.
Multiply packed double-precision floating-point
values from zmm1 and zmm2, add to
zmm3/m512/m64bcst and put result in zmm1.
Multiply packed double-precision floating-point
values from zmm2 and zmm3/m512/m64bcst, add
to zmm1 and put result in zmm1.
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a set of SIMD multiply-add computation on packed double-precision floating-point values using three
source operands and writes the multiply-add results in the destination operand. The destination operand is also the
first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD
register or a memory location.
VFMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source
operand to the two, four or eight packed double-precision floating-point values in the third source operand, adds
the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in
the second source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
VFMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand,
adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point
values in the third source operand, performs rounding and stores the resulting two, four or eight packed doubleprecision floating-point values to the destination operand (first source operand).
VFMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand, adds the
infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the
first source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in
reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a
ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The
destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values
Vol. 2C 5-127
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFMADD132PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] + SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMADD213PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] + SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMADD231PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] + DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
5-128 Vol. 2C
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values
Vol. 2C 5-129
INSTRUCTION SET REFERENCE, V-Z
VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-130 Vol. 2C
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values
Vol. 2C 5-131
INSTRUCTION SET REFERENCE, V-Z
VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxPD __m512d _mm512_fmadd_pd(__m512d a, __m512d b, __m512d c);
VFMADDxxxPD __m512d _mm512_fmadd_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_mask_fmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMADDxxxPD __m512d _mm512_maskz_fmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMADDxxxPD __m512d _mm512_mask3_fmadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMADDxxxPD __m512d _mm512_mask_fmadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_maskz_fmadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_mask3_fmadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMADDxxxPD __m256d _mm256_mask_fmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMADDxxxPD __m256d _mm256_maskz_fmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMADDxxxPD __m256d _mm256_mask3_fmadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMADDxxxPD __m128d _mm_mask_fmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMADDxxxPD __m128d _mm_maskz_fmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMADDxxxPD __m128d _mm_mask3_fmadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMADDxxxPD __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);
VFMADDxxxPD __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
5-132 Vol. 2C
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed SinglePrecision Floating-Point Values
Opcode/
Instruction
Op/
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.NDS.128.66.0F38.W0 98 /r
VFMADD132PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 A8 /r
VFMADD213PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 B8 /r
VFMADD231PS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W0 98 /r
VFMADD132PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W0 A8 /r
VFMADD213PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.0 B8 /r
VFMADD231PS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W0 98 /r
VFMADD132PS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 A8 /r
VFMADD213PS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 B8 /r
VFMADD231PS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 98 /r
VFMADD132PS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 A8 /r
VFMADD213PS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 B8 /r
VFMADD231PS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 98 /r
VFMADD132PS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 A8 /r
VFMADD213PS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 B8 /r
VFMADD231PS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{er}
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
Description
Multiply packed single-precision floating-point values
from xmm1 and xmm3/mem, add to xmm2 and put
result in xmm1.
Multiply packed single-precision floating-point values
from xmm1 and xmm2, add to xmm3/mem and put
result in xmm1.
Multiply packed single-precision floating-point values
from xmm2 and xmm3/mem, add to xmm1 and put
result in xmm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm3/mem, add to ymm2 and put
result in ymm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm2, add to ymm3/mem and put
result in ymm1.
Multiply packed single-precision floating-point values
from ymm2 and ymm3/mem, add to ymm1 and put
result in ymm1.
Multiply packed single-precision floating-point values
from xmm1 and xmm3/m128/m32bcst, add to
xmm2 and put result in xmm1.
Multiply packed single-precision floating-point values
from xmm1 and xmm2, add to
xmm3/m128/m32bcst and put result in xmm1.
Multiply packed single-precision floating-point values
from xmm2 and xmm3/m128/m32bcst, add to
xmm1 and put result in xmm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm3/m256/m32bcst, add to
ymm2 and put result in ymm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm2, add to
ymm3/m256/m32bcst and put result in ymm1.
Multiply packed single-precision floating-point values
from ymm2 and ymm3/m256/m32bcst, add to
ymm1 and put result in ymm1.
Multiply packed single-precision floating-point values
from zmm1 and zmm3/m512/m32bcst, add to
zmm2 and put result in zmm1.
Multiply packed single-precision floating-point values
from zmm1 and zmm2, add to
zmm3/m512/m32bcst and put result in zmm1.
Multiply packed single-precision floating-point values
from zmm2 and zmm3/m512/m32bcst, add to
zmm1 and put result in zmm1.
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values
Vol. 2C 5-133
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a set of SIMD multiply-add computation on packed single-precision floating-point values using three
source operands and writes the multiply-add results in the destination operand. The destination operand is also the
first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD
register or a memory location.
VFMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision
floating-point values in the second source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision
floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision
floating-point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen
packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in
reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a
ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The
destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
5-134 Vol. 2C
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFMADD132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 4
ELSEIF (VEX.256)
MAXNUM 8
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMADD213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 4
ELSEIF (VEX.256)
MAXNUM 8
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] + SRC3[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMADD231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 4
ELSEIF (VEX.256)
MAXNUM 8
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values
Vol. 2C 5-135
INSTRUCTION SET REFERENCE, V-Z
VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-136 Vol. 2C
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values
Vol. 2C 5-137
INSTRUCTION SET REFERENCE, V-Z
VFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-138 Vol. 2C
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxPS __m512 _mm512_fmadd_ps(__m512 a, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_fmadd_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMADDxxxPS __m512 _mm512_mask_fmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_maskz_fmadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_mask3_fmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMADDxxxPS __m512 _mm512_mask_fmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMADDxxxPS __m512 _mm512_maskz_fmadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMADDxxxPS __m512 _mm512_mask3_fmadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMADDxxxPS __m256 _mm256_mask_fmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMADDxxxPS __m256 _mm256_maskz_fmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMADDxxxPS __m256 _mm256_mask3_fmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMADDxxxPS __m128 _mm_mask_fmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMADDxxxPS __m128 _mm_maskz_fmadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMADDxxxPS __m128 _mm_mask3_fmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDxxxPS __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c);
VFMADDxxxPS __m256 _mm256_fmadd_ps (__m256 a, __m256 b, __m256 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values
Vol. 2C 5-139
INSTRUCTION SET REFERENCE, V-Z
VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar DoublePrecision Floating-Point Values
Opcode/
Instruction
Op/
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W1 99 /r
VFMADD132SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 A9 /r
VFMADD213SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 B9 /r
VFMADD231SD xmm1, xmm2,
xmm3/m64
EVEX.DDS.LIG.66.0F38.W1 99 /r
VFMADD132SD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 A9 /r
VFMADD213SD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 B9 /r
VFMADD231SD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar double-precision floating-point value
from xmm1 and xmm3/m64, add to xmm2 and put
result in xmm1.
Multiply scalar double-precision floating-point value
from xmm1 and xmm2, add to xmm3/m64 and put
result in xmm1.
Multiply scalar double-precision floating-point value
from xmm2 and xmm3/m64, add to xmm1 and put
result in xmm1.
Multiply scalar double-precision floating-point value
from xmm1 and xmm3/m64, add to xmm2 and put
result in xmm1.
Multiply scalar double-precision floating-point value
from xmm1 and xmm2, add to xmm3/m64 and put
result in xmm1.
Multiply scalar double-precision floating-point value
from xmm2 and xmm3/m64, add to xmm1 and put
result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD multiply-add computation on the low double-precision floating-point values using three source
operands and writes the multiply-add result in the destination operand. The destination operand is also the first
source operand. The first and second operand are XMM registers. The third source operand can be an XMM register
or a 64-bit memory location.
VFMADD132SD: Multiplies the low double-precision floating-point value from the first source operand to the low
double-precision floating-point value in the third source operand, adds the infinite precision intermediate result to
the low double-precision floating-point values in the second source operand, performs rounding and stores the
resulting double-precision floating-point value to the destination operand (first source operand).
VFMADD213SD: Multiplies the low double-precision floating-point value from the second source operand to the low
double-precision floating-point value in the first source operand, adds the infinite precision intermediate result to
the low double-precision floating-point value in the third source operand, performs rounding and stores the
resulting double-precision floating-point value to the destination operand (first source operand).
VFMADD231SD: Multiplies the low double-precision floating-point value from the second source to the low doubleprecision floating-point value in the third source operand, adds the infinite precision intermediate result to the low
double-precision floating-point value in the first source operand, performs rounding and stores the resulting
double-precision floating-point value to the destination operand (first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination is updated according to the writemask.
5-140 Vol. 2C
VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
Vol. 2C 5-141
INSTRUCTION SET REFERENCE, V-Z
VFMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFMADD132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] MAX_VL-1:128RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
DEST[127:63] DEST[127:63]
DEST[MAX_VL-1:128] 0
VFMADD213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
DEST[127:63] DEST[127:63]
DEST[MAX_VL-1:128] 0
VFMADD231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
DEST[127:63] DEST[127:63]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxSD __m128d _mm_fmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_mask_fmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMADDxxxSD __m128d _mm_maskz_fmadd_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMADDxxxSD __m128d _mm_mask3_fmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMADDxxxSD __m128d _mm_mask_fmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_maskz_fmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_mask3_fmadd_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFMADDxxxSD __m128d _mm_fmadd_sd (__m128d a, __m128d b, __m128d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
5-142 Vol. 2C
VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W0 99 /r
VFMADD132SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 A9 /r
VFMADD213SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 B9 /r
VFMADD231SS xmm1, xmm2,
xmm3/m32
EVEX.DDS.LIG.66.0F38.W0 99 /r
VFMADD132SS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 A9 /r
VFMADD213SS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 B9 /r
VFMADD231SS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar single-precision floating-point value
from xmm1 and xmm3/m32, add to xmm2 and put
result in xmm1.
Multiply scalar single-precision floating-point value
from xmm1 and xmm2, add to xmm3/m32 and put
result in xmm1.
Multiply scalar single-precision floating-point value
from xmm2 and xmm3/m32, add to xmm1 and put
result in xmm1.
Multiply scalar single-precision floating-point value
from xmm1 and xmm3/m32, add to xmm2 and put
result in xmm1.
Multiply scalar single-precision floating-point value
from xmm1 and xmm2, add to xmm3/m32 and put
result in xmm1.
Multiply scalar single-precision floating-point value
from xmm2 and xmm3/m32, add to xmm1 and put
result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD multiply-add computation on single-precision floating-point values using three source operands
and writes the multiply-add results in the destination operand. The destination operand is also the first source
operand. The first and second operands are XMM registers. The third source operand can be a XMM register or a
32-bit memory location.
VFMADD132SS: Multiplies the low single-precision floating-point value from the first source operand to the low
single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to
the low single-precision floating-point value in the second source operand, performs rounding and stores the
resulting single-precision floating-point value to the destination operand (first source operand).
VFMADD213SS: Multiplies the low single-precision floating-point value from the second source operand to the low
single-precision floating-point value in the first source operand, adds the infinite precision intermediate result to
the low single-precision floating-point value in the third source operand, performs rounding and stores the
resulting single-precision floating-point value to the destination operand (first source operand).
VFMADD231SS: Multiplies the low single-precision floating-point value from the second source operand to the low
single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to
the low single-precision floating-point value in the first source operand, performs rounding and stores the resulting
single-precision floating-point value to the destination operand (first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
Vol. 2C 5-143
INSTRUCTION SET REFERENCE, V-Z
EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(DEST[31:0]*SRC3[31:0] + SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(SRC2[31:0]*DEST[31:0] + SRC3[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
5-144 Vol. 2C
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(SRC2[31:0]*SRC3[31:0] + DEST[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0]] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMADD132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] + SRC2[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMADD213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] + SRC3[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMADD231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] + DEST[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxSS __m128 _mm_fmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask_fmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_maskz_fmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_mask3_fmadd_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDxxxSS __m128 _mm_mask_fmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_maskz_fmadd_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask3_fmadd_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFMADDxxxSS __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
Vol. 2C 5-145
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating
Add/Subtract of Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.128.66.0F38.W1 96 /r
VFMADDSUB132PD xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W1 A6 /r
VFMADDSUB213PD xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W1 B6 /r
VFMADDSUB231PD xmm1, xmm2,
xmm3/m128
VEX.DDS.256.66.0F38.W1 96 /r
VFMADDSUB132PD ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W1 A6 /r
VFMADDSUB213PD ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W1 B6 /r
VFMADDSUB231PD ymm1, ymm2,
ymm3/m256
EVEX.DDS.128.66.0F38.W1 A6 /r
VFMADDSUB213PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.128.66.0F38.W1 B6 /r
VFMADDSUB231PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.128.66.0F38.W1 96 /r
VFMADDSUB132PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W1 A6 /r
VFMADDSUB213PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W1 B6 /r
VFMADDSUB231PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W1 96 /r
VFMADDSUB132PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
5-146 Vol. 2C
Description
Multiply packed double-precision floating-point values
from xmm1 and xmm3/mem, add/subtract elements in
xmm2 and put result in xmm1.
Multiply packed double-precision floating-point values
from xmm1 and xmm2, add/subtract elements in
xmm3/mem and put result in xmm1.
Multiply packed double-precision floating-point values
from xmm2 and xmm3/mem, add/subtract elements in
xmm1 and put result in xmm1.
Multiply packed double-precision floating-point values
from ymm1 and ymm3/mem, add/subtract elements in
ymm2 and put result in ymm1.
Multiply packed double-precision floating-point values
from ymm1 and ymm2, add/subtract elements in
ymm3/mem and put result in ymm1.
Multiply packed double-precision floating-point values
from ymm2 and ymm3/mem, add/subtract elements in
ymm1 and put result in ymm1.
Multiply packed double-precision floating-point values
from xmm1 and xmm2, add/subtract elements in
xmm3/m128/m64bcst and put result in xmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from xmm2 and xmm3/m128/m64bcst, add/subtract
elements in xmm1 and put result in xmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from xmm1 and xmm3/m128/m64bcst, add/subtract
elements in xmm2 and put result in xmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from ymm1 and ymm2, add/subtract elements in
ymm3/m256/m64bcst and put result in ymm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from ymm2 and ymm3/m256/m64bcst, add/subtract
elements in ymm1 and put result in ymm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from ymm1 and ymm3/m256/m64bcst, add/subtract
elements in ymm2 and put result in ymm1 subject to
writemask k1.
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.DDS.512.66.0F38.W1 A6 /r
VFMADDSUB213PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.DDS.512.66.0F38.W1 B6 /r
VFMADDSUB231PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
FV
V/V
AVX512F
EVEX.DDS.512.66.0F38.W1 96 /r
VFMADDSUB132PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
FV
V/V
AVX512F
Description
Multiply packed double-precision floating-point values
from zmm1and zmm2, add/subtract elements in
zmm3/m512/m64bcst and put result in zmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from zmm2 and zmm3/m512/m64bcst, add/subtract
elements in zmm1 and put result in zmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from zmm1 and zmm3/m512/m64bcst, add/subtract
elements in zmm2 and put result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFMADDSUB132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first
source operand to the two or four packed double-precision floating-point values in the third source operand. From
the infinite precision intermediate result, adds the odd double-precision floating-point elements and subtracts the
even double-precision floating-point values in the second source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
VFMADDSUB213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the first source operand.
From the infinite precision intermediate result, adds the odd double-precision floating-point elements and
subtracts the even double-precision floating-point values in the third source operand, performs rounding and
stores the resulting two or four packed double-precision floating-point values to the destination operand (first
source operand).
VFMADDSUB231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the third source
operand. From the infinite precision intermediate result, adds the odd double-precision floating-point elements and
subtracts the even double-precision floating-point values in the first source operand, performs rounding and stores
the resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
Vol. 2C 5-147
INSTRUCTION SET REFERENCE, V-Z
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFMADDSUB132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
DEST[191:128] RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] - SRC2[191:128])
DEST[255:192] RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] + SRC2[255:192]
FI
VFMADDSUB213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] - SRC3[191:128])
DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] + SRC3[255:192]
FI
VFMADDSUB231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] - DEST[191:128])
DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] + DEST[255:192]
FI
5-148 Vol. 2C
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+63:i]
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
ELSE DEST[i+63:i]
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
Vol. 2C 5-149
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-150 Vol. 2C
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
ELSE DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
Vol. 2C 5-151
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-152 Vol. 2C
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
ELSE DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
Vol. 2C 5-153
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-154 Vol. 2C
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VFMADDSUBxxxPD __m512d _mm512_fmaddsub_pd(__m512d a, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_fmaddsub_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMADDSUBxxxPD __m256d _mm256_mask_fmaddsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMADDSUBxxxPD __m256d _mm256_maskz_fmaddsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMADDSUBxxxPD __m256d _mm256_mask3_fmaddsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMADDSUBxxxPD __m128d _mm_mask_fmaddsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMADDSUBxxxPD __m128d _mm_maskz_fmaddsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMADDSUBxxxPD __m128d _mm_mask3_fmaddsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMADDSUBxxxPD __m128d _mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c);
VFMADDSUBxxxPD __m256d _mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision
Vol. 2C 5-155
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating
Add/Subtract of Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.128.66.0F38.W0 96 /r
VFMADDSUB132PS xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W0 A6 /r
VFMADDSUB213PS xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W0 B6 /r
VFMADDSUB231PS xmm1, xmm2,
xmm3/m128
VEX.DDS.256.66.0F38.W0 96 /r
VFMADDSUB132PS ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W0 A6 /r
VFMADDSUB213PS ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W0 B6 /r
VFMADDSUB231PS ymm1, ymm2,
ymm3/m256
EVEX.DDS.128.66.0F38.W0 A6 /r
VFMADDSUB213PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.128.66.0F38.W0 B6 /r
VFMADDSUB231PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.DDS.128.66.0F38.W0 96 /r
VFMADDSUB132PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.DDS.256.66.0F38.W0 A6 /r
VFMADDSUB213PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W0 B6 /r
VFMADDSUB231PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.DDS.256.66.0F38.W0 96 /r
VFMADDSUB132PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.DDS.512.66.0F38.W0 A6 /r
VFMADDSUB213PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
EVEX.DDS.512.66.0F38.W0 B6 /r
VFMADDSUB231PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.DDS.512.66.0F38.W0 96 /r
VFMADDSUB132PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
FV
V/V
AVX512F
FV
V/V
AVX512F
5-156 Vol. 2C
Description
Multiply packed single-precision floating-point values from
xmm1 and xmm3/mem, add/subtract elements in xmm2
and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, add/subtract elements in xmm3/mem
and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/mem, add/subtract elements in xmm1
and put result in xmm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/mem, add/subtract elements in ymm2
and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, add/subtract elements in ymm3/mem
and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/mem, add/subtract elements in ymm1
and put result in ymm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, add/subtract elements in
xmm3/m128/m32bcst and put result in xmm1 subject to
writemask k1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/m128/m32bcst, add/subtract elements
in xmm1 and put result in xmm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
xmm1 and xmm3/m128/m32bcst, add/subtract elements
in zmm2 and put result in xmm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, add/subtract elements in
ymm3/m256/m32bcst and put result in ymm1 subject to
writemask k1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/m256/m32bcst, add/subtract elements
in ymm1 and put result in ymm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/m256/m32bcst, add/subtract elements
in ymm2 and put result in ymm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
zmm1 and zmm2, add/subtract elements in
zmm3/m512/m32bcst and put result in zmm1 subject to
writemask k1.
Multiply packed single-precision floating-point values from
zmm2 and zmm3/m512/m32bcst, add/subtract elements
in zmm1 and put result in zmm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
zmm1 and zmm3/m512/m32bcst, add/subtract elements
in zmm2 and put result in zmm1 subject to writemask k1.
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFMADDSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the corresponding packed single-precision floating-point values in the third source operand.
From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts
the even single-precision floating-point values in the second source operand, performs rounding and stores the
resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMADDSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the first source
operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and
subtracts the even single-precision floating-point values in the third source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMADDSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the third source
operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and
subtracts the even single-precision floating-point values in the first source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
Vol. 2C 5-157
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFMADDSUB132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM -1{
n 64*i;
DEST[n+31:n] RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])
DEST[n+63:n+32] RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] + SRC2[n+63:n+32])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMADDSUB213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM -1{
n 64*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])
DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] + SRC3[n+63:n+32])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
5-158 Vol. 2C
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM -1{
n 64*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] + DEST[n+63:n+32])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) (4, 128), (8, 256),= (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+31:i]
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
ELSE DEST[i+31:i]
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
Vol. 2C 5-159
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-160 Vol. 2C
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
ELSE DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
FI;
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
Vol. 2C 5-161
INSTRUCTION SET REFERENCE, V-Z
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
ELSE DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-162 Vol. 2C
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
Vol. 2C 5-163
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VFMADDSUBxxxPS __m512 _mm512_fmaddsub_ps(__m512 a, __m512 b, __m512 c);
VFMADDSUBxxxPS __m512 _mm512_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMADDSUBxxxPS __m256 _mm256_mask_fmaddsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMADDSUBxxxPS __m256 _mm256_maskz_fmaddsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMADDSUBxxxPS __m256 _mm256_mask3_fmaddsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMADDSUBxxxPS __m128 _mm_mask_fmaddsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMADDSUBxxxPS __m128 _mm_maskz_fmaddsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMADDSUBxxxPS __m128 _mm_mask3_fmaddsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDSUBxxxPS __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);
VFMADDSUBxxxPS __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
5-164 Vol. 2C
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating
Subtract/Add of Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.128.66.0F38.W1 97 /r
VFMSUBADD132PD xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W1 A7 /r
VFMSUBADD213PD xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W1 B7 /r
VFMSUBADD231PD xmm1, xmm2,
xmm3/m128
VEX.DDS.256.66.0F38.W1 97 /r
VFMSUBADD132PD ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W1 A7 /r
VFMSUBADD213PD ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W1 B7 /r
VFMSUBADD231PD ymm1, ymm2,
ymm3/m256
EVEX.DDS.128.66.0F38.W1 97 /r
VFMSUBADD132PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.128.66.0F38.W1 A7 /r
VFMSUBADD213PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.128.66.0F38.W1 B7 /r
VFMSUBADD231PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W1 97 /r
VFMSUBADD132PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W1 A7 /r
VFMSUBADD213PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W1 B7 /r
VFMSUBADD231PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
Description
Multiply packed double-precision floating-point values
from xmm1 and xmm3/mem, subtract/add elements
in xmm2 and put result in xmm1.
Multiply packed double-precision floating-point values
from xmm1 and xmm2, subtract/add elements in
xmm3/mem and put result in xmm1.
Multiply packed double-precision floating-point values
from xmm2 and xmm3/mem, subtract/add elements
in xmm1 and put result in xmm1.
Multiply packed double-precision floating-point values
from ymm1 and ymm3/mem, subtract/add elements
in ymm2 and put result in ymm1.
Multiply packed double-precision floating-point values
from ymm1 and ymm2, subtract/add elements in
ymm3/mem and put result in ymm1.
Multiply packed double-precision floating-point values
from ymm2 and ymm3/mem, subtract/add elements
in ymm1 and put result in ymm1.
Multiply packed double-precision floating-point values
from xmm1 and xmm3/m128/m64bcst, subtract/add
elements in xmm2 and put result in xmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from xmm1 and xmm2, subtract/add elements in
xmm3/m128/m64bcst and put result in xmm1
subject to writemask k1.
Multiply packed double-precision floating-point values
from xmm2 and xmm3/m128/m64bcst, subtract/add
elements in xmm1 and put result in xmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from ymm1 and ymm3/m256/m64bcst, subtract/add
elements in ymm2 and put result in ymm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from ymm1 and ymm2, subtract/add elements in
ymm3/m256/m64bcst and put result in ymm1
subject to writemask k1.
Multiply packed double-precision floating-point values
from ymm2 and ymm3/m256/m64bcst, subtract/add
elements in ymm1 and put result in ymm1 subject to
writemask k1.
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
Vol. 2C 5-165
INSTRUCTION SET REFERENCE, V-Z
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
EVEX.DDS.512.66.0F38.W1 97 /r
VFMSUBADD132PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.DDS.512.66.0F38.W1 A7 /r
VFMSUBADD213PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
FV
V/V
AVX512F
EVEX.DDS.512.66.0F38.W1 B7 /r
VFMSUBADD231PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
FV
V/V
AVX512F
Description
Multiply packed double-precision floating-point values
from zmm1 and zmm3/m512/m64bcst, subtract/add
elements in zmm2 and put result in zmm1 subject to
writemask k1.
Multiply packed double-precision floating-point values
from zmm1 and zmm2, subtract/add elements in
zmm3/m512/m64bcst and put result in zmm1 subject
to writemask k1.
Multiply packed double-precision floating-point values
from zmm2 and zmm3/m512/m64bcst, subtract/add
elements in zmm1 and put result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFMSUBADD132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first
source operand to the two or four packed double-precision floating-point values in the third source operand. From
the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the
even double-precision floating-point values in the second source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
VFMSUBADD213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the first source operand.
From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and
adds the even double-precision floating-point values in the third source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
VFMSUBADD231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the third source operand.
From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and
adds the even double-precision floating-point values in the first source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is conditionally updated with write mask k1.
5-166 Vol. 2C
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFMSUBADD132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])
DEST[191:128] RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] + SRC2[191:128])
DEST[255:192] RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] - SRC2[255:192]
FI
VFMSUBADD213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])
DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] + SRC3[191:128])
DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] - SRC3[255:192]
FI
VFMSUBADD231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])
DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] + DEST[191:128])
DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] - DEST[255:192]
FI
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
Vol. 2C 5-167
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+63:i]
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
ELSE DEST[i+63:i]
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-168 Vol. 2C
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
Vol. 2C 5-169
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
ELSE DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-170 Vol. 2C
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
Vol. 2C 5-171
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
ELSE DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-172 Vol. 2C
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
Vol. 2C 5-173
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBADDxxxPD __m512d _mm512_fmsubadd_pd(__m512d a, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_fmsubadd_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_mask_fmsubadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMSUBADDxxxPD __m512d _mm512_mask_fmsubadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMSUBADDxxxPD __m256d _mm256_mask_fmsubadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMSUBADDxxxPD __m256d _mm256_maskz_fmsubadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMSUBADDxxxPD __m256d _mm256_mask3_fmsubadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMSUBADDxxxPD __m128d _mm_mask_fmsubadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBADDxxxPD __m128d _mm_maskz_fmsubadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMSUBADDxxxPD __m128d _mm_mask3_fmsubadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBADDxxxPD __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);
VFMSUBADDxxxPD __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
5-174 Vol. 2C
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating
Subtract/Add of Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.128.66.0F38.W0 97 /r
VFMSUBADD132PS xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W0 A7 /r
VFMSUBADD213PS xmm1, xmm2,
xmm3/m128
VEX.DDS.128.66.0F38.W0 B7 /r
VFMSUBADD231PS xmm1, xmm2,
xmm3/m128
VEX.DDS.256.66.0F38.W0 97 /r
VFMSUBADD132PS ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W0 A7 /r
VFMSUBADD213PS ymm1, ymm2,
ymm3/m256
VEX.DDS.256.66.0F38.W0 B7 /r
VFMSUBADD231PS ymm1, ymm2,
ymm3/m256
EVEX.DDS.128.66.0F38.W0 97 /r
VFMSUBADD132PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.DDS.128.66.0F38.W0 A7 /r
VFMSUBADD213PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.128.66.0F38.W0 B7 /r
VFMSUBADD231PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.DDS.256.66.0F38.W0 97 /r
VFMSUBADD132PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.DDS.256.66.0F38.W0 A7 /r
VFMSUBADD213PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W0 B7 /r
VFMSUBADD231PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.DDS.512.66.0F38.W0 97 /r
VFMSUBADD132PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.DDS.512.66.0F38.W0 A7 /r
VFMSUBADD213PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
EVEX.DDS.512.66.0F38.W0 B7 /r
VFMSUBADD231PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
FV
V/V
AVX512F
Description
Multiply packed single-precision floating-point values from
xmm1 and xmm3/mem, subtract/add elements in xmm2
and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, subtract/add elements in xmm3/mem
and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/mem, subtract/add elements in xmm1
and put result in xmm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/mem, subtract/add elements in ymm2
and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, subtract/add elements in ymm3/mem
and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/mem, subtract/add elements in ymm1
and put result in ymm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm3/m128/m32bcst, subtract/add elements
in xmm2 and put result in xmm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, subtract/add elements in
xmm3/m128/m32bcst and put result in xmm1 subject to
writemask k1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/m128/m32bcst, subtract/add elements
in xmm1 and put result in xmm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/m256/m32bcst, subtract/add elements
in ymm2 and put result in ymm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, subtract/add elements in
ymm3/m256/m32bcst and put result in ymm1 subject to
writemask k1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/m256/m32bcst, subtract/add elements
in ymm1 and put result in ymm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
zmm1 and zmm3/m512/m32bcst, subtract/add elements
in zmm2 and put result in zmm1 subject to writemask k1.
Multiply packed single-precision floating-point values from
zmm1 and zmm2, subtract/add elements in
zmm3/m512/m32bcst and put result in zmm1 subject to
writemask k1.
Multiply packed single-precision floating-point values from
zmm2 and zmm3/m512/m32bcst, subtract/add elements
in zmm1 and put result in zmm1 subject to writemask k1.
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
Vol. 2C 5-175
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFMSUBADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the corresponding packed single-precision floating-point values in the third source operand.
From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements and adds
the even single-precision floating-point values in the second source operand, performs rounding and stores the
resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMSUBADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the first source
operand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements
and adds the even single-precision floating-point values in the third source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMSUBADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the third source
operand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements
and adds the even single-precision floating-point values in the first source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
5-176 Vol. 2C
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFMSUBADD132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM -1{
n 64*i;
DEST[n+31:n] RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
DEST[n+63:n+32] RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] -SRC2[n+63:n+32])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUBADD213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM -1{
n 64*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] +SRC3[n+31:n])
DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] -SRC3[n+63:n+32])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUBADD231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM -1{
n 64*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] -DEST[n+63:n+32])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
Vol. 2C 5-177
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+31:i]
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
ELSE DEST[i+31:i]
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-178 Vol. 2C
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
Vol. 2C 5-179
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
ELSE DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-180 Vol. 2C
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
Vol. 2C 5-181
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
ELSE DEST[i+31:i]
RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-182 Vol. 2C
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF j *is even*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
FI;
ELSE
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
FI;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
Vol. 2C 5-183
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBADDxxxPS __m512 _mm512_fmsubadd_ps(__m512 a, __m512 b, __m512 c);
VFMSUBADDxxxPS __m512 _mm512_fmsubadd_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMSUBADDxxxPS __m256 _mm256_mask_fmsubadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMSUBADDxxxPS __m256 _mm256_maskz_fmsubadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMSUBADDxxxPS __m256 _mm256_mask3_fmsubadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMSUBADDxxxPS __m128 _mm_mask_fmsubadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMSUBADDxxxPS __m128 _mm_maskz_fmsubadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBADDxxxPS __m128 _mm_mask3_fmsubadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBADDxxxPS __m128 _mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c);
VFMSUBADDxxxPS __m256 _mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
5-184 Vol. 2C
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision
INSTRUCTION SET REFERENCE, V-Z
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed DoublePrecision Floating-Point Values
Opcode/
Instruction
Op/
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.NDS.128.66.0F38.W1 9A /r
VFMSUB132PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 AA /r
VFMSUB213PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 BA /r
VFMSUB231PD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W1 9A /r
VFMSUB132PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 AA /r
VFMSUB213PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 BA /r
VFMSUB231PD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W1 9A /r
VFMSUB132PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
EVEX.NDS.128.66.0F38.W1 AA /r
VFMSUB213PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
EVEX.NDS.128.66.0F38.W1 BA /r
VFMSUB231PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 9A /r
VFMSUB132PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
EVEX.NDS.256.66.0F38.W1 AA /r
VFMSUB213PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
EVEX.NDS.256.66.0F38.W1 BA /r
VFMSUB231PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 9A /r
VFMSUB132PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 AA /r
VFMSUB213PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 BA /r
VFMSUB231PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
Description
Multiply packed double-precision floating-point values
from xmm1 and xmm3/mem, subtract xmm2 and put
result in xmm1.
Multiply packed double-precision floating-point values
from xmm1 and xmm2, subtract xmm3/mem and put
result in xmm1.
Multiply packed double-precision floating-point values
from xmm2 and xmm3/mem, subtract xmm1 and put
result in xmm1.
Multiply packed double-precision floating-point values
from ymm1 and ymm3/mem, subtract ymm2 and put
result in ymm1.
Multiply packed double-precision floating-point values
from ymm1 and ymm2, subtract ymm3/mem and put
result in ymm1.
Multiply packed double-precision floating-point values
from ymm2 and ymm3/mem, subtract ymm1 and put
result in ymm1.S
Multiply packed double-precision floating-point values
from xmm1 and xmm3/m128/m64bcst, subtract xmm2
and put result in xmm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from xmm1 and xmm2, subtract xmm3/m128/m64bcst
and put result in xmm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from xmm2 and xmm3/m128/m64bcst, subtract xmm1
and put result in xmm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from ymm1 and ymm3/m256/m64bcst, subtract ymm2
and put result in ymm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from ymm1 and ymm2, subtract ymm3/m256/m64bcst
and put result in ymm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from ymm2 and ymm3/m256/m64bcst, subtract ymm1
and put result in ymm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from zmm1 and zmm3/m512/m64bcst, subtract zmm2
and put result in zmm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from zmm1 and zmm2, subtract zmm3/m512/m64bcst
and put result in zmm1 subject to writemask k1.
Multiply packed double-precision floating-point values
from zmm2 and zmm3/m512/m64bcst, subtract zmm1
and put result in zmm1 subject to writemask k1.
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
Vol. 2C 5-185
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a set of SIMD multiply-subtract computation on packed double-precision floating-point values using three
source operands and writes the multiply-subtract results in the destination operand. The destination operand is
also the first source operand. The second operand must be a SIMD register. The third source operand can be a
SIMD register or a memory location.
VFMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source
operand to the two, four or eight packed double-precision floating-point values in the third source operand. From
the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point
values in the second source operand, performs rounding and stores the resulting two, four or eight packed doubleprecision floating-point values to the destination operand (first source operand).
VFMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand.
From the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floatingpoint values in the third source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
VFMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand. From the
infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point values
in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
5-186 Vol. 2C
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFMSUB132PD DEST, SRC2, SRC3 (VEX encoded versions)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] - SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUB213PD DEST, SRC2, SRC3 (VEX encoded versions)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] - SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUB231PD DEST, SRC2, SRC3 (VEX encoded versions)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] - DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
Vol. 2C 5-187
INSTRUCTION SET REFERENCE, V-Z
VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-188 Vol. 2C
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
Vol. 2C 5-189
INSTRUCTION SET REFERENCE, V-Z
VFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])
+31:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-190 Vol. 2C
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxPD __m512d _mm512_fmsub_pd(__m512d a, __m512d b, __m512d c);
VFMSUBxxxPD __m512d _mm512_fmsub_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_mask_fmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMSUBxxxPD __m512d _mm512_maskz_fmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMSUBxxxPD __m512d _mm512_mask3_fmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMSUBxxxPD __m512d _mm512_mask_fmsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_maskz_fmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_mask3_fmsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMSUBxxxPD __m256d _mm256_mask_fmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMSUBxxxPD __m256d _mm256_maskz_fmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMSUBxxxPD __m256d _mm256_mask3_fmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMSUBxxxPD __m128d _mm_mask_fmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBxxxPD __m128d _mm_maskz_fmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMSUBxxxPD __m128d _mm_mask3_fmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBxxxPD __m128d _mm_fmsub_pd (__m128d a, __m128d b, __m128d c);
VFMSUBxxxPD __m256d _mm256_fmsub_pd (__m256d a, __m256d b, __m256d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
Vol. 2C 5-191
INSTRUCTION SET REFERENCE, V-Z
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed SinglePrecision Floating-Point Values
Opcode/
Instruction
Op/E
n
VEX.NDS.128.66.0F38.W0 9A /r
VFMSUB132PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 AA /r
VFMSUB213PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 BA /r
VFMSUB231PS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W0 9A /r
VFMSUB132PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W0 AA /r
VFMSUB213PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.0 BA /r
VFMSUB231PS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W0 9A /r
VFMSUB132PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 AA /r
VFMSUB213PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 BA /r
VFMSUB231PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 9A /r
VFMSUB132PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 AA /r
VFMSUB213PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 BA /r
VFMSUB231PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 9A /r
VFMSUB132PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 AA /r
VFMSUB213PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 BA /r
VFMSUB231PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
5-192 Vol. 2C
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
Description
Multiply packed single-precision floating-point values
from xmm1 and xmm3/mem, subtract xmm2 and put
result in xmm1.
Multiply packed single-precision floating-point values
from xmm1 and xmm2, subtract xmm3/mem and put
result in xmm1.
Multiply packed single-precision floating-point values
from xmm2 and xmm3/mem, subtract xmm1 and put
result in xmm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm3/mem, subtract ymm2 and put
result in ymm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm2, subtract ymm3/mem and put
result in ymm1.
Multiply packed single-precision floating-point values
from ymm2 and ymm3/mem, subtract ymm1 and put
result in ymm1.
Multiply packed single-precision floating-point values
from xmm1 and xmm3/m128/m32bcst, subtract
xmm2 and put result in xmm1.
Multiply packed single-precision floating-point values
from xmm1 and xmm2, subtract
xmm3/m128/m32bcst and put result in xmm1.
Multiply packed single-precision floating-point values
from xmm2 and xmm3/m128/m32bcst, subtract
xmm1 and put result in xmm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm3/m256/m32bcst, subtract
ymm2 and put result in ymm1.
Multiply packed single-precision floating-point values
from ymm1 and ymm2, subtract
ymm3/m256/m32bcst and put result in ymm1.
Multiply packed single-precision floating-point values
from ymm2 and ymm3/m256/m32bcst, subtract
ymm1 and put result in ymm1.
Multiply packed single-precision floating-point values
from zmm1 and zmm3/m512/m32bcst, subtract zmm2
and put result in zmm1.
Multiply packed single-precision floating-point values
from zmm1 and zmm2, subtract zmm3/m512/m32bcst
and put result in zmm1.
Multiply packed single-precision floating-point values
from zmm2 and zmm3/m512/m32bcst, subtract zmm1
and put result in zmm1.
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a set of SIMD multiply-subtract computation on packed single-precision floating-point values using three
source operands and writes the multiply-subtract results in the destination operand. The destination operand is
also the first source operand. The second operand must be a SIMD register. The third source operand can be a
SIMD register or a memory location.
VFMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision
floating-point values in the second source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision
floating-point values in the third source operand, performs rounding and stores the resulting four, eight or sixteen
packed single-precision floating-point values to the destination operand (first source operand).
VFMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From
the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision floating-point
values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed singleprecision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
Vol. 2C 5-193
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
5-194 Vol. 2C
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
Vol. 2C 5-195
INSTRUCTION SET REFERENCE, V-Z
VFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-196 Vol. 2C
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
Vol. 2C 5-197
INSTRUCTION SET REFERENCE, V-Z
VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxPS __m512 _mm512_fmsub_ps(__m512 a, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_fmsub_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_mask_fmsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_maskz_fmsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_mask3_fmsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMSUBxxxPS __m512 _mm512_mask_fmsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_maskz_fmsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_mask3_fmsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMSUBxxxPS __m256 _mm256_mask_fmsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMSUBxxxPS __m256 _mm256_maskz_fmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMSUBxxxPS __m256 _mm256_mask3_fmsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMSUBxxxPS __m128 _mm_mask_fmsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMSUBxxxPS __m128 _mm_maskz_fmsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBxxxPS __m128 _mm_mask3_fmsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBxxxPS __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c);
VFMSUBxxxPS __m256 _mm256_fmsub_ps (__m256 a, __m256 b, __m256 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
5-198 Vol. 2C
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar DoublePrecision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W1 9B /r
VFMSUB132SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 AB /r
VFMSUB213SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 BB /r
VFMSUB231SD xmm1, xmm2,
xmm3/m64
EVEX.DDS.LIG.66.0F38.W1 9B /r
VFMSUB132SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 AB /r
VFMSUB213SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 BB /r
VFMSUB231SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar double-precision floating-point value from
xmm1 and xmm3/m64, subtract xmm2 and put result in
xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm2, subtract xmm3/m64 and put result in
xmm1.
Multiply scalar double-precision floating-point value from
xmm2 and xmm3/m64, subtract xmm1 and put result in
xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm3/m64, subtract xmm2 and put result in
xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm2, subtract xmm3/m64 and put result in
xmm1.
Multiply scalar double-precision floating-point value from
xmm2 and xmm3/m64, subtract xmm1 and put result in
xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD multiply-subtract computation on the low packed double-precision floating-point values using
three source operands and writes the multiply-subtract result in the destination operand. The destination operand
is also the first source operand. The second operand must be a XMM register. The third source operand can be a
XMM register or a 64-bit memory location.
VFMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to
the low packed double-precision floating-point value in the third source operand. From the infinite precision intermediate result, subtracts the low packed double-precision floating-point values in the second source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand to
the low packed double-precision floating-point value in the first source operand. From the infinite precision intermediate result, subtracts the low packed double-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low
packed double-precision floating-point value in the third source operand. From the infinite precision intermediate
result, subtracts the low packed double-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
Vol. 2C 5-199
INSTRUCTION SET REFERENCE, V-Z
EVEX encoded version: The low quadword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
5-200 Vol. 2C
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxSD __m128d _mm_fmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_mask_fmsub_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBxxxSD __m128d _mm_maskz_fmsub_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMSUBxxxSD __m128d _mm_mask3_fmsub_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBxxxSD __m128d _mm_mask_fmsub_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_maskz_fmsub_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_mask3_fmsub_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFMSUBxxxSD __m128d _mm_fmsub_sd (__m128d a, __m128d b, __m128d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
Vol. 2C 5-201
INSTRUCTION SET REFERENCE, V-Z
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar SinglePrecision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W0 9B /r
VFMSUB132SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 AB /r
VFMSUB213SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 BB /r
VFMSUB231SS xmm1, xmm2,
xmm3/m32
EVEX.DDS.LIG.66.0F38.W0 9B /r
VFMSUB132SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 AB /r
VFMSUB213SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 BB /r
VFMSUB231SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar single-precision floating-point value from
xmm1 and xmm3/m32, subtract xmm2 and put result in
xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm2, subtract xmm3/m32 and put result in
xmm1.
Multiply scalar single-precision floating-point value from
xmm2 and xmm3/m32, subtract xmm1 and put result in
xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm3/m32, subtract xmm2 and put result in
xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm2, subtract xmm3/m32 and put result in
xmm1.
Multiply scalar single-precision floating-point value from
xmm2 and xmm3/m32, subtract xmm1 and put result in
xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD multiply-subtract computation on the low packed single-precision floating-point values using
three source operands and writes the multiply-subtract result in the destination operand. The destination operand
is also the first source operand. The second operand must be a XMM register. The third source operand can be a
XMM register or a 32-bit memory location.
VFMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to the
low packed single-precision floating-point value in the third source operand. From the infinite precision intermediate result, subtracts the low packed single-precision floating-point values in the second source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to
the low packed single-precision floating-point value in the first source operand. From the infinite precision intermediate result, subtracts the low packed single-precision floating-point value in the third source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low
packed single-precision floating-point value in the third source operand. From the infinite precision intermediate
result, subtracts the low packed single-precision floating-point value in the first source operand, performs rounding
and stores the resulting packed single-precision floating-point value to the destination operand (first source
operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
5-202 Vol. 2C
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(DEST[31:0]*SRC3[31:0] - SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(SRC2[31:0]*DEST[31:0] - SRC3[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
Vol. 2C 5-203
INSTRUCTION SET REFERENCE, V-Z
VFMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(SRC2[31:0]*SRC3[63:0] - DEST[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] - SRC2[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] - SRC3[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] - DEST[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxSS __m128 _mm_fmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFMSUBxxxSS __m128 _mm_mask_fmsub_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMSUBxxxSS __m128 _mm_maskz_fmsub_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBxxxSS __m128 _mm_mask3_fmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBxxxSS __m128 _mm_mask_fmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFMSUBxxxSS __m128 _mm_maskz_fmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFMSUBxxxSS __m128 _mm_mask3_fmsub_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFMSUBxxxSS __m128 _mm_fmsub_ss (__m128 a, __m128 b, __m128 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
5-204 Vol. 2C
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed
Double-Precision Floating-Point Values
Opcode/
Instruction
Op/
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.NDS.128.66.0F38.W1 9C /r
VFNMADD132PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 AC /r
VFNMADD213PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 BC /r
VFNMADD231PD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W1 9C /r
VFNMADD132PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 AC /r
VFNMADD213PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 BC /r
VFNMADD231PD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W1 9C /r
VFNMADD132PD xmm0 {k1}{z},
xmm1, xmm2/m128/m64bcst
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W1 AC /r
VFNMADD213PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
EVEX.NDS.128.66.0F38.W1 BC /r
VFNMADD231PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W1 9C /r
VFNMADD132PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W1 AC /r
VFNMADD213PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
EVEX.NDS.256.66.0F38.W1 BC /r
VFNMADD231PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
EVEX.NDS.512.66.0F38.W1 9C /r
VFNMADD132PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 AC /r
VFNMADD213PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 BC /r
VFNMADD231PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
Description
Multiply packed double-precision floating-point values from
xmm1 and xmm3/mem, negate the multiplication result
and add to xmm2 and put result in xmm1.
Multiply packed double-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and add
to xmm3/mem and put result in xmm1.
Multiply packed double-precision floating-point values from
xmm2 and xmm3/mem, negate the multiplication result
and add to xmm1 and put result in xmm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm3/mem, negate the multiplication result and
add to ymm2 and put result in ymm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and add
to ymm3/mem and put result in ymm1.
Multiply packed double-precision floating-point values from
ymm2 and ymm3/mem, negate the multiplication result and
add to ymm1 and put result in ymm1.
Multiply packed double-precision floating-point values from
xmm1 and xmm3/m128/m64bcst, negate the
multiplication result and add to xmm2 and put result in
xmm1.
Multiply packed double-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and add
to xmm3/m128/m64bcst and put result in xmm1.
Multiply packed double-precision floating-point values from
xmm2 and xmm3/m128/m64bcst, negate the
multiplication result and add to xmm1 and put result in
xmm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm3/m256/m64bcst, negate the
multiplication result and add to ymm2 and put result in
ymm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and add
to ymm3/m256/m64bcst and put result in ymm1.
Multiply packed double-precision floating-point values from
ymm2 and ymm3/m256/m64bcst, negate the
multiplication result and add to ymm1 and put result in
ymm1.
Multiply packed double-precision floating-point values from
zmm1 and zmm3/m512/m64bcst, negate the multiplication
result and add to zmm2 and put result in zmm1.
Multiply packed double-precision floating-point values from
zmm1 and zmm2, negate the multiplication result and add
to zmm3/m512/m64bcst and put result in zmm1.
Multiply packed double-precision floating-point values from
zmm2 and zmm3/m512/m64bcst, negate the multiplication
result and add to zmm1 and put result in zmm1.
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Val-
Vol. 2C 5-205
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first
source operand to the two, four or eight packed double-precision floating-point values in the third source operand,
adds the negated infinite precision intermediate result to the two, four or eight packed double-precision floatingpoint values in the second source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
VFNMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand,
adds the negated infinite precision intermediate result to the two, four or eight packed double-precision floatingpoint values in the third source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
VFNMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand, the
negated infinite precision intermediate result to the two, four or eight packed double-precision floating-point values
in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
5-206 Vol. 2C
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFNMADD132PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(-(DEST[n+63:n]*SRC3[n+63:n]) + SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMADD213PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(-(SRC2[n+63:n]*DEST[n+63:n]) + SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMADD231PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR(-(SRC2[n+63:n]*SRC3[n+63:n]) + DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Val-
Vol. 2C 5-207
INSTRUCTION SET REFERENCE, V-Z
VFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) + SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-208 Vol. 2C
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[63:0])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Val-
Vol. 2C 5-209
INSTRUCTION SET REFERENCE, V-Z
VFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) + DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-210 Vol. 2C
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxPD __m512d _mm512_fnmadd_pd(__m512d a, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_fnmadd_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_mask_fnmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_maskz_fnmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_mask3_fnmadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFNMADDxxxPD __m512d _mm512_mask_fnmadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_maskz_fnmadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_mask3_fnmadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFNMADDxxxPD __m256d _mm256_mask_fnmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFNMADDxxxPD __m256d _mm256_maskz_fnmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFNMADDxxxPD __m256d _mm256_mask3_fnmadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFNMADDxxxPD __m128d _mm_mask_fnmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMADDxxxPD __m128d _mm_maskz_fnmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMADDxxxPD __m128d _mm_mask3_fnmadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMADDxxxPD __m128d _mm_fnmadd_pd (__m128d a, __m128d b, __m128d c);
VFNMADDxxxPD __m256d _mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Val-
Vol. 2C 5-211
INSTRUCTION SET REFERENCE, V-Z
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed
Single-Precision Floating-Point Values
Opcode/
Instruction
Op/
En
VEX.NDS.128.66.0F38.W0 9C /r
VFNMADD132PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 AC /r
VFNMADD213PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 BC /r
VFNMADD231PS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W0 9C /r
VFNMADD132PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W0 AC /r
VFNMADD213PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.0 BC /r
VFNMADD231PS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W0 9C /r
VFNMADD132PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 AC /r
VFNMADD213PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 BC /r
VFNMADD231PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 9C /r
VFNMADD132PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 AC /r
VFNMADD213PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 BC /r
VFNMADD231PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 9C /r
VFNMADD132PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 AC /r
VFNMADD213PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 BC /r
VFNMADD231PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
5-212 Vol. 2C
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
Description
Multiply packed single-precision floating-point values from
xmm1 and xmm3/mem, negate the multiplication result
and add to xmm2 and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and add
to xmm3/mem and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/mem, negate the multiplication result
and add to xmm1 and put result in xmm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/mem, negate the multiplication result
and add to ymm2 and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and add
to ymm3/mem and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/mem, negate the multiplication result and
add to ymm1 and put result in ymm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm3/m128/m32bcst, negate the multiplication
result and add to xmm2 and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and add
to xmm3/m128/m32bcst and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/m128/m32bcst, negate the multiplication
result and add to xmm1 and put result in xmm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/m256/m32bcst, negate the multiplication
result and add to ymm2 and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and add
to ymm3/m256/m32bcst and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/m256/m32bcst, negate the multiplication
result and add to ymm1 and put result in ymm1.
Multiply packed single-precision floating-point values from
zmm1 and zmm3/m512/m32bcst, negate the multiplication
result and add to zmm2 and put result in zmm1.
Multiply packed single-precision floating-point values from
zmm1 and zmm2, negate the multiplication result and add
to zmm3/m512/m32bcst and put result in zmm1.
Multiply packed single-precision floating-point values from
zmm2 and zmm3/m512/m32bcst, negate the multiplication
result and add to zmm1 and put result in zmm1.
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-precision floating-point values in the second source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-precision floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-precision floating-point values in the first source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFNMADD132PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(- (DEST[n+31:n]*SRC3[n+31:n]) + SRC2[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
Vol. 2C 5-213
INSTRUCTION SET REFERENCE, V-Z
VFNMADD213PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(- (SRC2[n+31:n]*DEST[n+31:n]) + SRC3[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMADD231PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR(- (SRC2[n+31:n]*SRC3[n+31:n]) + DEST[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-214 Vol. 2C
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) + SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
Vol. 2C 5-215
INSTRUCTION SET REFERENCE, V-Z
VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[31:0])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-216 Vol. 2C
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) + DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxPS __m512 _mm512_fnmadd_ps(__m512 a, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_mask_fnmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFNMADDxxxPS __m512 _mm512_mask_fnmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFNMADDxxxPS __m256 _mm256_mask_fnmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFNMADDxxxPS __m256 _mm256_maskz_fnmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFNMADDxxxPS __m256 _mm256_mask3_fnmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFNMADDxxxPS __m128 _mm_mask_fnmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMADDxxxPS __m128 _mm_maskz_fnmadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMADDxxxPS __m128 _mm_mask3_fnmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMADDxxxPS __m128 _mm_fnmadd_ps (__m128 a, __m128 b, __m128 c);
VFNMADDxxxPS __m256 _mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
Vol. 2C 5-217
INSTRUCTION SET REFERENCE, V-Z
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar
Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W1 9D /r
VFNMADD132SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 AD /r
VFNMADD213SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 BD /r
VFNMADD231SD xmm1, xmm2,
xmm3/m64
EVEX.DDS.LIG.66.0F38.W1 9D /r
VFNMADD132SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 AD /r
VFNMADD213SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 BD /r
VFNMADD231SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar double-precision floating-point value from
xmm1 and xmm3/mem, negate the multiplication result and
add to xmm2 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and add to
xmm3/mem and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm2 and xmm3/mem, negate the multiplication result and
add to xmm1 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm3/m64, negate the multiplication result and
add to xmm2 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and add to
xmm3/m64 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm2 and xmm3/m64, negate the multiplication result and
add to xmm1 and put result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMADD132SD: Multiplies the low packed double-precision floating-point value from the first source operand to
the low packed double-precision floating-point value in the third source operand, adds the negated infinite precision intermediate result to the low packed double-precision floating-point values in the second source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFNMADD213SD: Multiplies the low packed double-precision floating-point value from the second source operand
to the low packed double-precision floating-point value in the first source operand, adds the negated infinite precision intermediate result to the low packed double-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFNMADD231SD: Multiplies the low packed double-precision floating-point value from the second source to the low
packed double-precision floating-point value in the third source operand, adds the negated infinite precision intermediate result to the low packed double-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
5-218 Vol. 2C
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
EVEX encoded version: The low quadword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFNMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(-(DEST[63:0]*SRC3[63:0]) + SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(-(SRC2[63:0]*DEST[63:0]) + SRC3[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
Vol. 2C 5-219
INSTRUCTION SET REFERENCE, V-Z
VFNMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) + DEST[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMADD132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) + SRC2[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMADD213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) + SRC3[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMADD231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) + DEST[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxSD __m128d _mm_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_mask_fnmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMADDxxxSD __m128d _mm_maskz_fnmadd_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMADDxxxSD __m128d _mm_mask3_fnmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMADDxxxSD __m128d _mm_mask_fnmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_maskz_fnmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_mask3_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFNMADDxxxSD __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
5-220 Vol. 2C
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar
Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W0 9D /r
VFNMADD132SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 AD /r
VFNMADD213SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 BD /r
VFNMADD231SS xmm1, xmm2,
xmm3/m32
EVEX.DDS.LIG.66.0F38.W0 9D /r
VFNMADD132SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 AD /r
VFNMADD213SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 BD /r
VFNMADD231SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar single-precision floating-point value from
xmm1 and xmm3/m32, negate the multiplication result
and add to xmm2 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and
add to xmm3/m32 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm2 and xmm3/m32, negate the multiplication result
and add to xmm1 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm3/m32, negate the multiplication result
and add to xmm2 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and
add to xmm3/m32 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm2 and xmm3/m32, negate the multiplication result
and add to xmm1 and put result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMADD132SS: Multiplies the low packed single-precision floating-point value from the first source operand to
the low packed single-precision floating-point value in the third source operand, adds the negated infinite precision
intermediate result to the low packed single-precision floating-point value in the second source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFNMADD213SS: Multiplies the low packed single-precision floating-point value from the second source operand
to the low packed single-precision floating-point value in the first source operand, adds the negated infinite precision intermediate result to the low packed single-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed single-precision floating-point value to the destination operand
(first source operand).
VFNMADD231SS: Multiplies the low packed single-precision floating-point value from the second source operand
to the low packed single-precision floating-point value in the third source operand, adds the negated infinite precision intermediate result to the low packed single-precision floating-point value in the first source operand,
performs rounding and stores the resulting packed single-precision floating-point value to the destination operand
(first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
Vol. 2C 5-221
INSTRUCTION SET REFERENCE, V-Z
EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).
VFNMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(-(DEST[31:0]*SRC3[31:0]) + SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(-(SRC2[31:0]*DEST[31:0]) + SRC3[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
5-222 Vol. 2C
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VFNMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) + DEST[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMADD132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) + SRC2[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMADD213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) + SRC3[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMADD231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) + DEST[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxSS __m128 _mm_fnmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_mask_fnmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMADDxxxSS __m128 _mm_maskz_fnmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMADDxxxSS __m128 _mm_mask3_fnmadd_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMADDxxxSS __m128 _mm_mask_fnmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_maskz_fnmadd_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_mask3_fnmadd_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFNMADDxxxSS __m128 _mm_fnmadd_ss (__m128 a, __m128 b, __m128 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
Vol. 2C 5-223
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of
Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op/
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.NDS.128.66.0F38.W1 9E /r
VFNMSUB132PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 AE /r
VFNMSUB213PD xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W1 BE /r
VFNMSUB231PD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W1 9E /r
VFNMSUB132PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 AE /r
VFNMSUB213PD ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W1 BE /r
VFNMSUB231PD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W1 9E /r
VFNMSUB132PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W1 AE /r
VFNMSUB213PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
EVEX.NDS.128.66.0F38.W1 BE /r
VFNMSUB231PD xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W1 9E /r
VFNMSUB132PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W1 AE /r
VFNMSUB213PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
EVEX.NDS.256.66.0F38.W1 BE /r
VFNMSUB231PD ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
EVEX.NDS.512.66.0F38.W1 9E /r
VFNMSUB132PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 AE /r
VFNMSUB213PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
EVEX.NDS.512.66.0F38.W1 BE /r
VFNMSUB231PD zmm1 {k1}{z},
zmm2, zmm3/m512/m64bcst{er}
5-224 Vol. 2C
Description
Multiply packed double-precision floating-point values from
xmm1 and xmm3/mem, negate the multiplication result
and subtract xmm2 and put result in xmm1.
Multiply packed double-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/mem and put result in xmm1.
Multiply packed double-precision floating-point values from
xmm2 and xmm3/mem, negate the multiplication result
and subtract xmm1 and put result in xmm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm3/mem, negate the multiplication result and
subtract ymm2 and put result in ymm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and
subtract ymm3/mem and put result in ymm1.
Multiply packed double-precision floating-point values from
ymm2 and ymm3/mem, negate the multiplication result and
subtract ymm1 and put result in ymm1.
Multiply packed double-precision floating-point values from
xmm1 and xmm3/m128/m64bcst, negate the
multiplication result and subtract xmm2 and put result in
xmm1.
Multiply packed double-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/m128/m64bcst and put result in xmm1.
Multiply packed double-precision floating-point values from
xmm2 and xmm3/m128/m64bcst, negate the
multiplication result and subtract xmm1 and put result in
xmm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm3/m256/m64bcst, negate the
multiplication result and subtract ymm2 and put result in
ymm1.
Multiply packed double-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and
subtract ymm3/m256/m64bcst and put result in ymm1.
Multiply packed double-precision floating-point values from
ymm2 and ymm3/m256/m64bcst, negate the
multiplication result and subtract ymm1 and put result in
ymm1.
Multiply packed double-precision floating-point values from
zmm1 and zmm3/m512/m64bcst, negate the multiplication
result and subtract zmm2 and put result in zmm1.
Multiply packed double-precision floating-point values from
zmm1 and zmm2, negate the multiplication result and
subtract zmm3/m512/m64bcst and put result in zmm1.
Multiply packed double-precision floating-point values from
zmm2 and zmm3/m512/m64bcst, negate the multiplication
result and subtract zmm1 and put result in zmm1.
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first
source operand to the two, four or eight packed double-precision floating-point values in the third source operand.
From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision
floating-point values in the second source operand, performs rounding and stores the resulting two, four or eight
packed double-precision floating-point values to the destination operand (first source operand).
VFNMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand.
From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision
floating-point values in the third source operand, performs rounding and stores the resulting two, four or eight
packed double-precision floating-point values to the destination operand (first source operand).
VFNMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand. From
negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floatingpoint values in the first source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFNMSUB132PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR( - (DEST[n+63:n]*SRC3[n+63:n]) - SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point
Vol. 2C 5-225
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB213PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR( - (SRC2[n+63:n]*DEST[n+63:n]) - SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMSUB231PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 64*i;
DEST[n+63:n] RoundFPControl_MXCSR( - (SRC2[n+63:n]*SRC3[n+63:n]) - DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-226 Vol. 2C
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) - SRC2[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point
Vol. 2C 5-227
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[63:0])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-228 Vol. 2C
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) - DEST[i+63:i])
ELSE
DEST[i+63:i]
RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxPD __m512d _mm512_fnmsub_pd(__m512d a, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFNMSUBxxxPD __m256d _mm256_mask_fnmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFNMSUBxxxPD __m256d _mm256_maskz_fnmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFNMSUBxxxPD __m256d _mm256_mask3_fnmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFNMSUBxxxPD __m128d _mm_mask_fnmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMSUBxxxPD __m128d _mm_maskz_fnmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMSUBxxxPD __m128d _mm_mask3_fnmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMSUBxxxPD __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);
VFNMSUBxxxPD __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point
Vol. 2C 5-229
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of
Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op/
En
VEX.NDS.128.66.0F38.W0 9E /r
VFNMSUB132PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 AE /r
VFNMSUB213PS xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.W0 BE /r
VFNMSUB231PS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.W0 9E /r
VFNMSUB132PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.W0 AE /r
VFNMSUB213PS ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.0 BE /r
VFNMSUB231PS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F38.W0 9E /r
VFNMSUB132PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 AE /r
VFNMSUB213PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.128.66.0F38.W0 BE /r
VFNMSUB231PS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 9E /r
VFNMSUB132PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 AE /r
VFNMSUB213PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.256.66.0F38.W0 BE /r
VFNMSUB231PS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 9E /r
VFNMSUB132PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 AE /r
VFNMSUB213PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
EVEX.NDS.512.66.0F38.W0 BE /r
VFNMSUB231PS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst{er}
5-230 Vol. 2C
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
RVM
V/V
FMA
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512F
Description
Multiply packed single-precision floating-point values from
xmm1 and xmm3/mem, negate the multiplication result and
subtract xmm2 and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/mem and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/mem, negate the multiplication result and
subtract xmm1 and put result in xmm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/mem, negate the multiplication result and
subtract ymm2 and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and
subtract ymm3/mem and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/mem, negate the multiplication result and
subtract ymm1 and put result in ymm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm3/m128/m32bcst, negate the multiplication
result and subtract xmm2 and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/m128/m32bcst and put result in xmm1.
Multiply packed single-precision floating-point values from
xmm2 and xmm3/m128/m32bcst, negate the multiplication
result subtract add to xmm1 and put result in xmm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm3/m256/m32bcst, negate the multiplication
result and subtract ymm2 and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm1 and ymm2, negate the multiplication result and
subtract ymm3/m256/m32bcst and put result in ymm1.
Multiply packed single-precision floating-point values from
ymm2 and ymm3/m256/m32bcst, negate the multiplication
result subtract add to ymm1 and put result in ymm1.
Multiply packed single-precision floating-point values from
zmm1 and zmm3/m512/m32bcst, negate the multiplication
result and subtract zmm2 and put result in zmm1.
Multiply packed single-precision floating-point values from
zmm1 and zmm2, negate the multiplication result and
subtract zmm3/m512/m32bcst and put result in zmm1.
Multiply packed single-precision floating-point values from
zmm2 and zmm3/m512/m32bcst, negate the multiplication
result subtract add to zmm1 and put result in zmm1.
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Val-
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed singleprecision floating-point values in the second source operand, performs rounding and stores the resulting four, eight
or sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed singleprecision floating-point values in the third source operand, performs rounding and stores the resulting four, eight
or sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From
negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-precision floatingpoint values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed
single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFNMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR( - (DEST[n+31:n]*SRC3[n+31:n]) - SRC2[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Val-
Vol. 2C 5-231
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR( - (SRC2[n+31:n]*DEST[n+31:n]) - SRC3[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
MAXNUM 2
ELSEIF (VEX.256)
MAXNUM 4
FI
For i = 0 to MAXNUM-1 {
n 32*i;
DEST[n+31:n] RoundFPControl_MXCSR( - (SRC2[n+31:n]*SRC3[n+31:n]) - DEST[n+31:n])
}
IF (VEX.128) THEN
DEST[MAX_VL-1:128] 0
ELSEIF (VEX.256)
DEST[MAX_VL-1:256] 0
FI
VFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-232 Vol. 2C
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Val-
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) - SRC2[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Val-
Vol. 2C 5-233
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[31:0])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
5-234 Vol. 2C
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Val-
INSTRUCTION SET REFERENCE, V-Z
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) - DEST[i+31:i])
ELSE
DEST[i+31:i]
RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxPS __m512 _mm512_fnmsub_ps(__m512 a, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_fnmsub_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_mask_fnmsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFNMSUBxxxPS __m512 _mm512_mask_fnmsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFNMSUBxxxPS __m256 _mm256_mask_fnmsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFNMSUBxxxPS __m256 _mm256_maskz_fnmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFNMSUBxxxPS __m256 _mm256_mask3_fnmsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFNMSUBxxxPS __m128 _mm_mask_fnmsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMSUBxxxPS __m128 _mm_maskz_fnmsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMSUBxxxPS __m128 _mm_mask3_fnmsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMSUBxxxPS __m128 _mm_fnmsub_ps (__m128 a, __m128 b, __m128 c);
VFNMSUBxxxPS __m256 _mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Val-
Vol. 2C 5-235
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of
Scalar Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W1 9F /r
VFNMSUB132SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 AF /r
VFNMSUB213SD xmm1, xmm2,
xmm3/m64
VEX.DDS.LIG.66.0F38.W1 BF /r
VFNMSUB231SD xmm1, xmm2,
xmm3/m64
EVEX.DDS.LIG.66.0F38.W1 9F /r
VFNMSUB132SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 AF /r
VFNMSUB213SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
EVEX.DDS.LIG.66.0F38.W1 BF /r
VFNMSUB231SD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar double-precision floating-point value from
xmm1 and xmm3/mem, negate the multiplication result and
subtract xmm2 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/mem and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm2 and xmm3/mem, negate the multiplication result and
subtract xmm1 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm3/m64, negate the multiplication result and
subtract xmm2 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/m64 and put result in xmm1.
Multiply scalar double-precision floating-point value from
xmm2 and xmm3/m64, negate the multiplication result and
subtract xmm1 and put result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to
the low packed double-precision floating-point value in the third source operand. From negated infinite precision
intermediate result, subtracts the low double-precision floating-point value in the second source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VFNMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand
to the low packed double-precision floating-point value in the first source operand. From negated infinite precision
intermediate result, subtracts the low double-precision floating-point value in the third source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VFNMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low
packed double-precision floating-point value in the third source operand. From negated infinite precision intermediate result, subtracts the low double-precision floating-point value in the first source operand, performs rounding
and stores the resulting packed double-precision floating-point value to the destination operand (first source
operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
5-236 Vol. 2C
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Val-
INSTRUCTION SET REFERENCE, V-Z
EVEX encoded version: The low quadword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFNMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(-(DEST[63:0]*SRC3[63:0]) - SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(-(SRC2[63:0]*DEST[63:0]) - SRC3[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Val-
Vol. 2C 5-237
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) - DEST[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) - SRC2[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) - SRC3[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
VFNMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) - DEST[63:0])
DEST[127:64] DEST[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxSD __m128d _mm_fnmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_mask_fnmsub_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMSUBxxxSD __m128d _mm_maskz_fnmsub_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMSUBxxxSD __m128d _mm_mask3_fnmsub_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMSUBxxxSD __m128d _mm_mask_fnmsub_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_maskz_fnmsub_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_mask3_fnmsub_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFNMSUBxxxSD __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
5-238 Vol. 2C
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Val-
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of
Scalar Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
FMA
VEX.DDS.LIG.66.0F38.W0 9F /r
VFNMSUB132SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 AF /r
VFNMSUB213SS xmm1, xmm2,
xmm3/m32
VEX.DDS.LIG.66.0F38.W0 BF /r
VFNMSUB231SS xmm1, xmm2,
xmm3/m32
EVEX.DDS.LIG.66.0F38.W0 9F /r
VFNMSUB132SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 AF /r
VFNMSUB213SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
EVEX.DDS.LIG.66.0F38.W0 BF /r
VFNMSUB231SS xmm1 {k1}{z},
xmm2, xmm3/m32{er}
RVM
V/V
FMA
RVM
V/V
FMA
T1S
V/V
AVX512F
T1S
V/V
AVX512F
T1S
V/V
AVX512F
Description
Multiply scalar single-precision floating-point value from
xmm1 and xmm3/m32, negate the multiplication result and
subtract xmm2 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/m32 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm2 and xmm3/m32, negate the multiplication result and
subtract xmm1 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm3/m32, negate the multiplication result and
subtract xmm2 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm1 and xmm2, negate the multiplication result and
subtract xmm3/m32 and put result in xmm1.
Multiply scalar single-precision floating-point value from
xmm2 and xmm3/m32, negate the multiplication result and
subtract xmm1 and put result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
T1S
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
VFNMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to
the low packed single-precision floating-point value in the third source operand. From negated infinite precision
intermediate result, the low single-precision floating-point value in the second source operand, performs rounding
and stores the resulting packed single-precision floating-point value to the destination operand (first source
operand).
VFNMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to
the low packed single-precision floating-point value in the first source operand. From negated infinite precision
intermediate result, the low single-precision floating-point value in the third source operand, performs rounding
and stores the resulting packed single-precision floating-point value to the destination operand (first source
operand).
VFNMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low
packed single-precision floating-point value in the third source operand. From negated infinite precision intermediate result, the low single-precision floating-point value in the first source operand, performs rounding and stores
the resulting packed single-precision floating-point value to the destination operand (first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Val-
Vol. 2C 5-239
INSTRUCTION SET REFERENCE, V-Z
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).
VFNMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(-(DEST[31:0]*SRC3[31:0]) - SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(-(SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
5-240 Vol. 2C
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Val-
INSTRUCTION SET REFERENCE, V-Z
VFNMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) - DEST[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) - SRC2[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
VFNMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) - DEST[31:0])
DEST[127:32] DEST[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxSS __m128 _mm_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_mask_fnmsub_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMSUBxxxSS __m128 _mm_mask_fnmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFNMSUBxxxSS __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Val-
Vol. 2C 5-241
INSTRUCTION SET REFERENCE, V-Z
VFPCLASSPD—Tests Types Of a Packed Float64 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F3A.W1 66 /r ib
VFPCLASSPD k2 {k1},
xmm2/m128/m64bcst, imm8
EVEX.256.66.0F3A.W1 66 /r ib
VFPCLASSPD k2 {k1},
ymm2/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512DQ
EVEX.512.66.0F3A.W1 66 /r ib
VFPCLASSPD k2 {k1},
zmm2/m512/m64bcst, imm8
FV
V/V
AVX512DQ
Description
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
The FPCLASSPD instruction checks the packed double precision floating point values for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the
input data element is classified against. The classified results of all specified categories of an input value are ORed
together to form the final boolean result for the input element. The result of each element is written to the corresponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:8/4/2] of the destination are
cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-15.
7
SNaN
6
Neg. Finite
5
Denormal
4
Neg. INF
3
+INF
2
1
Neg. 0
+0
0
QNaN
Figure 5-13. Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS
Table 5-15. Classifier Operations for VFPCLASSPD/SD/PS/SS
Bits
Imm8[0]
Imm8[1]
Imm8[2]
Imm8[3]
Imm8[4]
Imm8[5]
Imm8[6]
Imm8[7]
Category
QNAN
PosZero
NegZero
PosINF
NegINF
Denormal
Negative
SNAN
Classifier
Checks for
QNaN
Checks for
+0
Checks for 0
Checks for
+INF
Checks for INF
Checks for
Denormal
Checks for
Negative finite
Checks for
SNaN
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-242 Vol. 2C
VFPCLASSPD—Tests Types Of a Packed Float64 Values
INSTRUCTION SET REFERENCE, V-Z
Operation
CheckFPClassDP (tsrc[63:0], imm8[7:0]){
//* Start checking the source operand for special type *//
NegNum tsrc[63];
IF (tsrc[62:52]=07FFh) Then ExpAllOnes 1; FI;
IF (tsrc[62:52]=0h) Then ExpAllZeros 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros 1;
ELSIF (tsrc[51:0]=0h) Then
MantAllZeros 1;
FI;
ZeroNumber ExpAllZeros AND MantAllZeros
SignalingBit tsrc[51];
sNaN_res ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
qNaN_res ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
Pzero_res NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
Nzero_res NegNum AND ExpAllZeros AND MantAllZeros;; // -0
PInf_res NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
NInf_res NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
Denorm_res ExpAllZeros AND NOT(MantAllZeros);; // denorm
FinNeg_res NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
Return bResult;
} //* end of CheckFPClassDP() *//
VFPCLASSPD (EVEX Encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC *is memory*)
THEN
DEST[j] CheckFPClassDP(SRC1[63:0], imm8[7:0]);
ELSE
DEST[j] CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);
FI;
ELSE DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VFPCLASSPD—Tests Types Of a Packed Float64 Values
Vol. 2C 5-243
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSPD __mmask8 _mm512_fpclass_pd_mask( __m512d a, int c);
VFPCLASSPD __mmask8 _mm512_mask_fpclass_pd_mask( __mmask8 m, __m512d a, int c)
VFPCLASSPD __mmask8 _mm256_fpclass_pd_mask( __m256d a, int c)
VFPCLASSPD __mmask8 _mm256_mask_fpclass_pd_mask( __mmask8 m, __m256d a, int c)
VFPCLASSPD __mmask8 _mm_fpclass_pd_mask( __m128d a, int c)
VFPCLASSPD __mmask8 _mm_mask_fpclass_pd_mask( __mmask8 m, __m128d a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4
#UD
5-244 Vol. 2C
If EVEX.vvvv != 1111B.
VFPCLASSPD—Tests Types Of a Packed Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VFPCLASSPS—Tests Types Of a Packed Float32 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F3A.W0 66 /r ib
VFPCLASSPS k2 {k1},
xmm2/m128/m32bcst, imm8
EVEX.256.66.0F3A.W0 66 /r ib
VFPCLASSPS k2 {k1},
ymm2/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512DQ
EVEX.512.66.0F3A.W0 66 /r ib
VFPCLASSPS k2 {k1},
zmm2/m512/m32bcst, imm8
FV
V/V
AVX512DQ
Description
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
The FPCLASSPS instruction checks the packed single-precision floating point values for special categories, specified
by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input
data element is classified against. The classified results of all specified categories of an input value are ORed
together to form the final boolean result for the input element. The result of each element is written to the corresponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:16/8/4] of the destination are
cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-15.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 32-bit memory location.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){
//* Start checking the source operand for special type *//
NegNum tsrc[31];
IF (tsrc[30:23]=0FFh) Then ExpAllOnes 1; FI;
IF (tsrc[30:23]=0h) Then ExpAllZeros 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros 1;
ELSIF (tsrc[22:0]=0h) Then
MantAllZeros 1;
FI;
ZeroNumber= ExpAllZeros AND MantAllZeros
SignalingBit= tsrc[22];
sNaN_res ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
qNaN_res ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
Pzero_res NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
VFPCLASSPS—Tests Types Of a Packed Float32 Values
Vol. 2C 5-245
INSTRUCTION SET REFERENCE, V-Z
Nzero_res NegNum AND ExpAllZeros AND MantAllZeros;; // -0
PInf_res NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
NInf_res NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
Denorm_res ExpAllZeros AND NOT(MantAllZeros);; // denorm
FinNeg_res NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
Return bResult;
} //* end of CheckSPClassSP() *//
VFPCLASSPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC *is memory*)
THEN
DEST[j] CheckFPClassDP(SRC1[31:0], imm8[7:0]);
ELSE
DEST[j] CheckFPClassDP(SRC1[i+31:i], imm8[7:0]);
FI;
ELSE DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSPS __mmask16 _mm512_fpclass_ps_mask( __m512 a, int c);
VFPCLASSPS __mmask16 _mm512_mask_fpclass_ps_mask( __mmask16 m, __m512 a, int c)
VFPCLASSPS __mmask8 _mm256_fpclass_ps_mask( __m256 a, int c)
VFPCLASSPS __mmask8 _mm256_mask_fpclass_ps_mask( __mmask8 m, __m256 a, int c)
VFPCLASSPS __mmask8 _mm_fpclass_ps_mask( __m128 a, int c)
VFPCLASSPS __mmask8 _mm_mask_fpclass_ps_mask( __mmask8 m, __m128 a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4
#UD
5-246 Vol. 2C
If EVEX.vvvv != 1111B.
VFPCLASSPS—Tests Types Of a Packed Float32 Values
INSTRUCTION SET REFERENCE, V-Z
VFPCLASSSD—Tests Types Of a Scalar Float64 Values
Opcode/
Instruction
Op /
En
EVEX.LIG.66.0F3A.W1 67 /r ib
VFPCLASSSD k2 {k1},
xmm2/m64, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512DQ
Description
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
The FPCLASSSD instruction checks the low double precision floating point value in the source operand for special
categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point
values that the input data element is classified against. The classified results of all specified categories of an input
value are ORed together to form the final boolean result for the input element. The result is written to the low bit
in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-15.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
CheckFPClassDP (tsrc[63:0], imm8[7:0]){
NegNum tsrc[63];
IF (tsrc[62:52]=07FFh) Then ExpAllOnes 1; FI;
IF (tsrc[62:52]=0h) Then ExpAllZeros 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros 1;
ELSIF (tsrc[51:0]=0h) Then
MantAllZeros 1;
FI;
ZeroNumber ExpAllZeros AND MantAllZeros
SignalingBit tsrc[51];
sNaN_res ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
qNaN_res ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
Pzero_res NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
Nzero_res NegNum AND ExpAllZeros AND MantAllZeros;; // -0
PInf_res NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
NInf_res NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
Denorm_res ExpAllZeros AND NOT(MantAllZeros);; // denorm
FinNeg_res NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
Return bResult;
} //* end of CheckFPClassDP() *//
VFPCLASSSD—Tests Types Of a Scalar Float64 Values
Vol. 2C 5-247
INSTRUCTION SET REFERENCE, V-Z
VFPCLASSSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[0]
CheckFPClassDP(SRC1[63:0], imm8[7:0])
ELSE DEST[0] 0
; zeroing-masking only
FI;
DEST[MAX_KL-1:1] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSD __mmask8 _mm_fpclass_sd_mask( __m128d a, int c)
VFPCLASSSD __mmask8 _mm_mask_fpclass_sd_mask( __mmask8 m, __m128d a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E6
#UD
5-248 Vol. 2C
If EVEX.vvvv != 1111B.
VFPCLASSSD—Tests Types Of a Scalar Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VFPCLASSSS—Tests Types Of a Scalar Float32 Values
Opcode/
Instruction
Op /
En
EVEX.LIG.66.0F3A.W0 67 /r
VFPCLASSSS k2 {k1},
xmm2/m32, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512DQ
Description
Tests the input for the following categories: NaN, +0, -0,
+Infinity, -Infinity, denormal, finite negative. The immediate
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
The FPCLASSSS instruction checks the low single-precision floating point value in the source operand for special
categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point
values that the input data element is classified against. The classified results of all specified categories of an input
value are ORed together to form the final boolean result for the input element. The result is written to the low bit
in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-15.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VFPCLASSSS—Tests Types Of a Scalar Float32 Values
Vol. 2C 5-249
INSTRUCTION SET REFERENCE, V-Z
Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){
//* Start checking the source operand for special type *//
NegNum tsrc[31];
IF (tsrc[30:23]=0FFh) Then ExpAllOnes 1; FI;
IF (tsrc[30:23]=0h) Then ExpAllZeros 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros 1;
ELSIF (tsrc[22:0]=0h) Then
MantAllZeros 1;
FI;
ZeroNumber= ExpAllZeros AND MantAllZeros
SignalingBit= tsrc[22];
sNaN_res ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
qNaN_res ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
Pzero_res NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
Nzero_res NegNum AND ExpAllZeros AND MantAllZeros;; // -0
PInf_res NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
NInf_res NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
Denorm_res ExpAllZeros AND NOT(MantAllZeros);; // denorm
FinNeg_res NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
Return bResult;
} //* end of CheckSPClassSP() *//
VFPCLASSSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[0]
CheckFPClassSP(SRC1[31:0], imm8[7:0])
ELSE DEST[0] 0
; zeroing-masking only
FI;
DEST[MAX_KL-1:1] 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSS __mmask8 _mm_fpclass_ss_mask( __m128 a, int c)
VFPCLASSSS __mmask8 _mm_mask_fpclass_ss_mask( __mmask8 m, __m128 a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E6
#UD
5-250 Vol. 2C
If EVEX.vvvv != 1111B.
VFPCLASSSS—Tests Types Of a Scalar Float32 Values
INSTRUCTION SET REFERENCE, V-Z
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
Opcode/
Instruction
Op/
En
RMV
64/3
2-bit
Mode
V/V
CPUID
Feature
Flag
AVX2
VEX.DDS.128.66.0F38.W1 92 /r
VGATHERDPD xmm1, vm32x, xmm2
Description
VEX.DDS.128.66.0F38.W1 93 /r
VGATHERQPD xmm1, vm64x, xmm2
RMV
V/V
AVX2
Using qword indices specified in vm64x, gather double-precision FP values from memory conditioned on mask specified by xmm2. Conditionally gathered elements are merged
into xmm1.
VEX.DDS.256.66.0F38.W1 92 /r
VGATHERDPD ymm1, vm32x, ymm2
RMV
V/V
AVX2
Using dword indices specified in vm32x, gather double-precision FP values from memory conditioned on mask specified by ymm2. Conditionally gathered elements are merged
into ymm1.
VEX.DDS.256.66.0F38.W1 93 /r
VGATHERQPD ymm1, vm64y, ymm2
RMV
V/V
AVX2
Using qword indices specified in vm64y, gather double-precision FP values from memory conditioned on mask specified by ymm2. Conditionally gathered elements are merged
into ymm1.
Using dword indices specified in vm32x, gather double-precision FP values from memory conditioned on mask specified by xmm2. Conditionally gathered elements are merged
into xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
VEX.vvvv (r, w)
NA
Description
The instruction conditionally loads up to 2 or 4 double-precision floating-point values from memory addresses
specified by the memory operand (the second operand) and using qword indices. The memory operand uses the
VSIB form of the SIB byte to specify a general purpose register operand as the common base, a vector register for
an array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is specified by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 doubleprecision floating-point values from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
Vol. 2C 5-251
INSTRUCTION SET REFERENCE, V-Z
VEX.128 version: The instruction will gather two double-precision floating-point values. For dword indices, only the
lower two indices in the vector index register are used.
VEX.256 version: The instruction will gather four double-precision floating-point values. For dword indices, only
the lower four indices in the vector index register are used.
Note that:
•
•
If any pair of the index, mask, or destination registers are the same, this instruction results a #UD fault.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
•
Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
•
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
This instruction will cause a #UD if the address size attribute is 16-bit.
This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
5-252 Vol. 2C
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
Operation
DEST SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK SRC3;
VGATHERDPD (VEX.128 version)
FOR j 0 to 1
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 1
k j * 32;
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63: i] 0;
ENDFOR
MASK[VLMAX-1:128] 0;
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
VGATHERQPD (VEX.128 version)
FOR j 0 to 1
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 1
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits this instruction
FI;
MASK[i +63: i] 0;
ENDFOR
MASK[VLMAX-1:128] 0;
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
Vol. 2C 5-253
INSTRUCTION SET REFERENCE, V-Z
VGATHERQPD (VEX.256 version)
FOR j 0 to 3
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 3
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63: i] 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)
VGATHERDPD (VEX.256 version)
FOR j 0 to 3
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 3
k j * 32;
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)
5-254 Vol. 2C
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPD: __m128d _mm_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m128d _mm_mask_i32gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int
scale);
VGATHERDPD: __m256d _mm256_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m256d _mm256_mask_i32gather_pd (__m256d src, double const * base, __m128i index, __m256d mask, const int
scale);
VGATHERQPD: __m128d _mm_i64gather_pd (double const * base, __m128i index, const int scale);
VGATHERQPD: __m128d _mm_mask_i64gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int
scale);
VGATHERQPD: __m256d _mm256_i64gather_pd (double const * base, __m256i index, const int scale);
VGATHERQPD: __m256d _mm256_mask_i64gather_pd (__m256d src, double const * base, __m256i index, __m256d mask, const int
scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 12.
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
Vol. 2C 5-255
INSTRUCTION SET REFERENCE, V-Z
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices
Opcode/
Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
AVX2
VEX.DDS.128.66.0F38.W0 92 /r
VGATHERDPS xmm1, vm32x, xmm2
Description
VEX.DDS.128.66.0F38.W0 93 /r
VGATHERQPS xmm1, vm64x, xmm2
RMV
V/V
AVX2
Using qword indices specified in vm64x, gather single-precision FP values from memory conditioned on mask specified
by xmm2. Conditionally gathered elements are merged into
xmm1.
VEX.DDS.256.66.0F38.W0 92 /r
VGATHERDPS ymm1, vm32y, ymm2
RMV
V/V
AVX2
Using dword indices specified in vm32y, gather single-precision FP values from memory conditioned on mask specified
by ymm2. Conditionally gathered elements are merged into
ymm1.
VEX.DDS.256.66.0F38.W0 93 /r
VGATHERQPS xmm1, vm64y, xmm2
RMV
V/V
AVX2
Using qword indices specified in vm64y, gather single-precision FP values from memory conditioned on mask specified
by xmm2. Conditionally gathered elements are merged into
xmm1.
Using dword indices specified in vm32x, gather single-precision FP values from memory conditioned on mask specified
by xmm2. Conditionally gathered elements are merged into
xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
A
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
VEX.vvvv (r, w)
NA
Description
The instruction conditionally loads up to 4 or 8 single-precision floating-point values from memory addresses specified by the memory operand (the second operand) and using dword indices. The memory operand uses the VSIB
form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an
array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is specified by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using qword indices, the instruction conditionally loads up to 2 or 4 single-precision floating-point values from the
VSIB addressing memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits
of the destination register are zero’ed with qword indices.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
5-256 Vol. 2C
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VEX.128 version: For dword indices, the instruction will gather four single-precision floating-point values. For
qword indices, the instruction will gather two values and zeroes the upper 64 bits of the destination.
VEX.256 version: For dword indices, the instruction will gather eight single-precision floating-point values. For
qword indices, the instruction will gather four values and zeroes the upper 128 bits of the destination.
Note that:
•
•
If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
•
Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
•
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
This instruction will cause a #UD if the address size attribute is 16-bit.
This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices
Vol. 2C 5-257
INSTRUCTION SET REFERENCE, V-Z
Operation
DEST SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK SRC3;
VGATHERDPS (VEX.128 version)
FOR j 0 to 3
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
MASK[VLMAX-1:128] 0;
FOR j 0 to 3
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
VGATHERQPS (VEX.128 version)
FOR j 0 to 3
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
MASK[VLMAX-1:128] 0;
FOR j 0 to 1
k j * 64;
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
MASK[127:64] 0;
DEST[VLMAX-1:64] 0;
(non-masked elements of the mask register have the content of respective element cleared)
5-258 Vol. 2C
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VGATHERDPS (VEX.256 version)
FOR j 0 to 7
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
FOR j 0 to 7
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)
VGATHERQPS (VEX.256 version)
FOR j 0 to 7
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
FOR j 0 to 3
k j * 64;
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
MASK[VLMAX-1:128] 0;
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices
Vol. 2C 5-259
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPS:
__m128 _mm_i32gather_ps (float const * base, __m128i index, const int scale);
VGATHERDPS:
__m128 _mm_mask_i32gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERDPS:
__m256 _mm256_i32gather_ps (float const * base, __m256i index, const int scale);
VGATHERDPS:
scale);
__m256 _mm256_mask_i32gather_ps (__m256 src, float const * base, __m256i index, __m256 mask, const int
VGATHERQPS:
__m128 _mm_i64gather_ps (float const * base, __m128i index, const int scale);
VGATHERQPS:
__m128 _mm_mask_i64gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERQPS:
__m128 _mm256_i64gather_ps (float const * base, __m256i index, const int scale);
VGATHERQPS:
scale);
__m128 _mm256_mask_i64gather_ps (__m128 src, float const * base, __m256i index, __m128 mask, const int
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 12
5-260 Vol. 2C
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword
Opcode/
Instruction
Op/
En
EVEX.128.66.0F38.W0 92 /vsib
VGATHERDPS xmm1 {k1}, vm32x
EVEX.256.66.0F38.W0 92 /vsib
VGATHERDPS ymm1 {k1}, vm32y
EVEX.512.66.0F38.W0 92 /vsib
VGATHERDPS zmm1 {k1}, vm32z
EVEX.128.66.0F38.W1 92 /vsib
VGATHERDPD xmm1 {k1},
vm32x
EVEX.256.66.0F38.W1 92 /vsib
VGATHERDPD ymm1 {k1},
vm32x
EVEX.512.66.0F38.W1 92 /vsib
VGATHERDPD zmm1 {k1}, vm32y
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
T1S
V/V
T1S
V/V
T1S
V/V
AVX512VL
AVX512F
Using signed dword indices, gather single-precision floatingpoint values from memory using k1 as completion mask.
Using signed dword indices, gather single-precision floatingpoint values from memory using k1 as completion mask.
Using signed dword indices, gather single-precision floatingpoint values from memory using k1 as completion mask.
Using signed dword indices, gather float64 vector into
float64 vector xmm1 using k1 as completion mask.
T1S
V/V
AVX512VL
AVX512F
Using signed dword indices, gather float64 vector into
float64 vector ymm1 using k1 as completion mask.
T1S
V/V
AVX512F
Using signed dword indices, gather float64 vector into
float64 vector zmm1 using k1 as completion mask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
Description
A set of single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR
and index vector V_INDEX with scale SCALE are gathered. The result is written into a vector register. The elements
are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only
be loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of
the destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it
triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the right most one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
•
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
•
Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword
Vol. 2C 5-261
INSTRUCTION SET REFERENCE, V-Z
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
VGATHERDPS (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j]
THEN DEST[i+31:i]
MEM[BASE_ADDR +
SignExtend(VINDEX[i+31:i]) * SCALE + DISP]
k1[j] 0
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL] 0
VGATHERDPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j]
THEN DEST[i+63:i] MEM[BASE_ADDR +
SignExtend(VINDEX[k+31:k]) * SCALE + DISP]
k1[j] 0
ELSE *DEST[i+63:i] remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL] 0
5-262 Vol. 2C
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPD __m512d _mm512_i32gather_pd( __m256i vdx, void * base, int scale);
VGATHERDPD __m512d _mm512_mask_i32gather_pd(__m512d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERDPD __m256d _mm256_mmask_i32gather_pd(__m256d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPD __m128d _mm_mmask_i32gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_i32gather_ps( __m512i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_mask_i32gather_ps(__m512 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERDPS __m256 _mm256_mmask_i32gather_ps(__m256 s, __mmask8 k, __m256i vdx, void * base, int scale);
GATHERDPS __m128 _mm_mmask_i32gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12.
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword
Vol. 2C 5-263
INSTRUCTION SET REFERENCE, V-Z
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
Opcode/
Instruction
Op/
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512PF
EVEX.512.66.0F38.W0 C6 /1 /vsib
VGATHERPF0DPS vm32z {k1}
EVEX.512.66.0F38.W0 C7 /1 /vsib
VGATHERPF0QPS vm64z {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C6 /1 /vsib
VGATHERPF0DPD vm32y {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C7 /1 /vsib
VGATHERPF0QPD vm64z {k1}
T1S
V/V
AVX512PF
Description
Using signed dword indices, prefetch sparse byte
memory locations containing single-precision data
using opmask k1 and T0 hint.
Using signed qword indices, prefetch sparse byte
memory locations containing single-precision data
using opmask k1 and T0 hint.
Using signed dword indices, prefetch sparse byte
memory locations containing double-precision data
using opmask k1 and T0 hint.
Using signed qword indices, prefetch sparse byte
memory locations containing double-precision data
using opmask k1 and T0 hint.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
NA
Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T0):
• T0 (temporal data)—prefetch data into the first level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruction will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.
5-264 Vol. 2C
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
INSTRUCTION SET REFERENCE, V-Z
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request
for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.
VGATHERPF0DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0QPS (EVEX encoded version)
(KL, VL) = (8, 256)
FOR j 0 TO KL-1
i j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
Vol. 2C 5-265
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERPF0DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF0DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);
VGATHERPF0QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF0QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12NP.
5-266 Vol. 2C
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
INSTRUCTION SET REFERENCE, V-Z
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
Opcode/
Instruction
Op/
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512PF
EVEX.512.66.0F38.W0 C6 /2 /vsib
VGATHERPF1DPS vm32z {k1}
EVEX.512.66.0F38.W0 C7 /2 /vsib
VGATHERPF1QPS vm64z {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C6 /2 /vsib
VGATHERPF1DPD vm32y {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C7 /2 /vsib
VGATHERPF1QPD vm64z {k1}
T1S
V/V
AVX512PF
Description
Using signed dword indices, prefetch sparse byte
memory locations containing single-precision data using
opmask k1 and T1 hint.
Using signed qword indices, prefetch sparse byte
memory locations containing single-precision data using
opmask k1 and T1 hint.
Using signed dword indices, prefetch sparse byte
memory locations containing double-precision data using
opmask k1 and T1 hint.
Using signed qword indices, prefetch sparse byte
memory locations containing double-precision data using
opmask k1 and T1 hint.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
NA
Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T1):
• T1 (temporal data)—prefetch data into the second level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruction will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
Vol. 2C 5-267
INSTRUCTION SET REFERENCE, V-Z
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request
for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.
VGATHERPF1DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
VGATHERPF1DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
VGATHERPF1QPS (EVEX encoded version)
(KL, VL) = (8, 256)
FOR j 0 TO KL-1
i j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
VGATHERPF1QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
5-268 Vol. 2C
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERPF1DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF1DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);
VGATHERPF1QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF1QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12NP.
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
Vol. 2C 5-269
INSTRUCTION SET REFERENCE, V-Z
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
Opcode/
Instruction
Op/
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W0 93 /vsib
VGATHERQPS xmm1 {k1}, vm64x
EVEX.256.66.0F38.W0 93 /vsib
VGATHERQPS xmm1 {k1}, vm64y
T1S
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.W0 93 /vsib
VGATHERQPS ymm1 {k1}, vm64z
T1S
V/V
AVX512F
EVEX.128.66.0F38.W1 93 /vsib
VGATHERQPD xmm1 {k1}, vm64x
EVEX.256.66.0F38.W1 93 /vsib
VGATHERQPD ymm1 {k1}, vm64y
EVEX.512.66.0F38.W1 93 /vsib
VGATHERQPD zmm1 {k1}, vm64z
T1S
V/V
T1S
V/V
T1S
V/V
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Using signed qword indices, gather single-precision
floating-point values from memory using k1 as completion
mask.
Using signed qword indices, gather single-precision
floating-point values from memory using k1 as completion
mask.
Using signed qword indices, gather single-precision
floating-point values from memory using k1 as completion
mask.
Using signed qword indices, gather float64 vector into
float64 vector xmm1 using k1 as completion mask.
Using signed qword indices, gather float64 vector into
float64 vector ymm1 using k1 as completion mask.
Using signed qword indices, gather float64 vector into
float64 vector zmm1 using k1 as completion mask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
Description
A set of 8 single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR
and index vector V_INDEX with scale SCALE are gathered. The result is written into vector a register. The elements
are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be
loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of the
destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
•
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
5-270 Vol. 2C
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
INSTRUCTION SET REFERENCE, V-Z
•
Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits
are ignored.
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
VGATHERQPS (EVEX encoded version)
(KL, VL) = (2, 64), (4, 128), (8, 256)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]
MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]
k1[j] 0
ELSE *DEST[i+31:i] remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL/2] 0
VGATHERQPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]
k1[j] 0
ELSE *DEST[i+63:i] remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL] 0
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
Vol. 2C 5-271
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERQPD __m512d _mm512_i64gather_pd( __m512i vdx, void * base, int scale);
VGATHERQPD __m512d _mm512_mask_i64gather_pd(__m512d s, __mmask8 k, __m512i vdx, void * base, int scale);
VGATHERQPD __m256d _mm256_mask_i64gather_pd(__m256d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPD __m128d _mm_mask_i64gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_i64gather_ps( __m512i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_mask_i64gather_ps(__m256 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERQPS __m128 _mm256_mask_i64gather_ps(__m128 s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPS __m128 _mm_mask_i64gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12.
5-272 Vol. 2C
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword
Indices
Opcode/
Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
AVX2
VEX.DDS.128.66.0F38.W0 90 /r
VPGATHERDD xmm1, vm32x, xmm2
VEX.DDS.128.66.0F38.W0 91 /r
VPGATHERQD xmm1, vm64x, xmm2
RMV
V/V
AVX2
VEX.DDS.256.66.0F38.W0 90 /r
VPGATHERDD ymm1, vm32y, ymm2
RMV
V/V
AVX2
VEX.DDS.256.66.0F38.W0 91 /r
VPGATHERQD xmm1, vm64y, xmm2
RMV
V/V
AVX2
Description
Using dword indices specified in vm32x, gather dword values from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into
xmm1.
Using qword indices specified in vm64x, gather dword values from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into
xmm1.
Using dword indices specified in vm32y, gather dword
from memory conditioned on mask specified by ymm2.
Conditionally gathered elements are merged into ymm1.
Using qword indices specified in vm64y, gather dword values from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into
xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
VEX.vvvv (r, w)
NA
Description
The instruction conditionally loads up to 4 or 8 dword values from memory addresses specified by the memory
operand (the second operand) and using dword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register for an array of indices relative
to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is specified by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using qword indices, the instruction conditionally loads up to 2 or 4 qword values from the VSIB addressing
memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits of the destination register are zero’ed with qword indices.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: For dword indices, the instruction will gather four dword values. For qword indices, the instruction will gather two values and zeroes the upper 64 bits of the destination.
VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword Indices
Vol. 2C 5-273
INSTRUCTION SET REFERENCE, V-Z
VEX.256 version: For dword indices, the instruction will gather eight dword values. For qword indices, the instruction will gather four values and zeroes the upper 128 bits of the destination.
Note that:
•
•
If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
•
Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
•
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
This instruction will cause a #UD if the address size attribute is 16-bit.
This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
Operation
DEST SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK SRC3;
VPGATHERDD (VEX.128 version)
FOR j 0 to 3
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
MASK[VLMAX-1:128] 0;
FOR j 0 to 3
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
5-274 Vol. 2C
VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VPGATHERQD (VEX.128 version)
FOR j 0 to 3
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
MASK[VLMAX-1:128] 0;
FOR j 0 to 1
k j * 64;
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
MASK[127:64] 0;
DEST[VLMAX-1:64] 0;
(non-masked elements of the mask register have the content of respective element cleared)
VPGATHERDD (VEX.256 version)
FOR j 0 to 7
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
FOR j 0 to 7
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)
VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword Indices
Vol. 2C 5-275
INSTRUCTION SET REFERENCE, V-Z
VPGATHERQD (VEX.256 version)
FOR j 0 to 7
i j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] 0;
FI;
ENDFOR
FOR j 0 to 3
k j * 64;
i j * 32;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] 0;
ENDFOR
MASK[VLMAX-1:128] 0;
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDD: __m128i _mm_i32gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERDD: __m128i _mm_mask_i32gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);
VPGATHERDD: __m256i _mm256_i32gather_epi32 ( int const * base, __m256i index, const int scale);
VPGATHERDD: __m256i _mm256_mask_i32gather_epi32 (__m256i src, int const * base, __m256i index, __m256i mask, const int
scale);
VPGATHERQD: __m128i _mm_i64gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERQD: __m128i _mm_mask_i64gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);
VPGATHERQD: __m128i _mm256_i64gather_epi32 (int const * base, __m256i index, const int scale);
VPGATHERQD: __m128i _mm256_mask_i64gather_epi32 (__m128i src, int const * base, __m256i index, __m128i mask, const int
scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 12.
5-276 Vol. 2C
VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword with Signed Dword Indices
Opcode/
Instruction
Op/
En
EVEX.128.66.0F38.W0 90 /vsib
VPGATHERDD xmm1 {k1}, vm32x
EVEX.256.66.0F38.W0 90 /vsib
VPGATHERDD ymm1 {k1}, vm32y
EVEX.512.66.0F38.W0 90 /vsib
VPGATHERDD zmm1 {k1}, vm32z
EVEX.128.66.0F38.W1 90 /vsib
VPGATHERDQ xmm1 {k1}, vm32x
EVEX.256.66.0F38.W1 90 /vsib
VPGATHERDQ ymm1 {k1}, vm32x
EVEX.512.66.0F38.W1 90 /vsib
VPGATHERDQ zmm1 {k1}, vm32y
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Using signed dword indices, gather dword values from
memory using writemask k1 for merging-masking.
Using signed dword indices, gather dword values from
memory using writemask k1 for merging-masking.
Using signed dword indices, gather dword values from
memory using writemask k1 for merging-masking.
Using signed dword indices, gather quadword values from
memory using writemask k1 for merging-masking.
Using signed dword indices, gather quadword values from
memory using writemask k1 for merging-masking.
Using signed dword indices, gather quadword values from
memory using writemask k1 for merging-masking.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
Description
A set of 16 or 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector
VINDEX with scale SCALE are gathered. The result is written into vector zmm1. The elements are specified via the
VSIB (i.e., the index register is a zmm, holding packed indices). Elements will only be loaded if their corresponding
mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination register (zmm1)
is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
•
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
•
Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
Not valid with 16-bit effective addresses. Will deliver a #UD fault.
These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword with Signed Dword Indices
Vol. 2C 5-277
INSTRUCTION SET REFERENCE, V-Z
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
VPGATHERDD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j]
THEN DEST[i+31:i] MEM[BASE_ADDR +
SignExtend(VINDEX[i+31:i]) * SCALE + DISP]), 1)
k1[j] 0
ELSE *DEST[i+31:i] remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL] 0
VPGATHERDQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j]
THEN DEST[i+63:i]
MEM[BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP])
k1[j] 0
ELSE *DEST[i+63:i] remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL] 0
5-278 Vol. 2C
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword with Signed Dword Indices
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDD __m512i _mm512_i32gather_epi32( __m512i vdx, void * base, int scale);
VPGATHERDD __m512i _mm512_mask_i32gather_epi32(__m512i s, __mmask16 k, __m512i vdx, void * base, int scale);
VPGATHERDD __m256i _mm256_mmask_i32gather_epi32(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERDD __m128i _mm_mmask_i32gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_i32logather_epi64( __m256i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_mask_i32logather_epi64(__m512i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERDQ __m256i _mm256_mmask_i32logather_epi64(__m256i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m128i _mm_mmask_i32gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12.
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword with Signed Dword Indices
Vol. 2C 5-279
INSTRUCTION SET REFERENCE, V-Z
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword
Indices
Opcode/
Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
AVX2
VEX.DDS.128.66.0F38.W1 90 /r
VPGATHERDQ xmm1, vm32x, xmm2
VEX.DDS.128.66.0F38.W1 91 /r
VPGATHERQQ xmm1, vm64x, xmm2
RMV
V/V
AVX2
VEX.DDS.256.66.0F38.W1 90 /r
VPGATHERDQ ymm1, vm32x, ymm2
RMV
V/V
AVX2
VEX.DDS.256.66.0F38.W1 91 /r
VPGATHERQQ ymm1, vm64y, ymm2
RMV
V/V
AVX2
Description
Using dword indices specified in vm32x, gather qword values from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into
xmm1.
Using qword indices specified in vm64x, gather qword values from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into
xmm1.
Using dword indices specified in vm32x, gather qword values from memory conditioned on mask specified by
ymm2. Conditionally gathered elements are merged into
ymm1.
Using qword indices specified in vm64y, gather qword values from memory conditioned on mask specified by
ymm2. Conditionally gathered elements are merged into
ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
A
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
VEX.vvvv (r, w)
NA
Description
The instruction conditionally loads up to 2 or 4 qword values from memory addresses specified by the memory
operand (the second operand) and using qword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register for an array of indices relative
to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is specified by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 qword
values from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: The instruction will gather two qword values. For dword indices, only the lower two indices in the
vector index register are used.
5-280 Vol. 2C
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VEX.256 version: The instruction will gather four qword values. For dword indices, only the lower four indices in
the vector index register are used.
Note that:
•
•
If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
•
Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
•
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
This instruction will cause a #UD if the address size attribute is 16-bit.
This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices
Vol. 2C 5-281
INSTRUCTION SET REFERENCE, V-Z
Operation
DEST SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK SRC3;
VPGATHERDQ (VEX.128 version)
FOR j 0 to 1
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 1
k j * 32;
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] 0;
ENDFOR
MASK[VLMAX-1:128] 0;
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
VPGATHERQQ (VEX.128 version)
FOR j 0 to 1
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 1
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] 0;
ENDFOR
MASK[VLMAX-1:128] 0;
DEST[VLMAX-1:128] 0;
(non-masked elements of the mask register have the content of respective element cleared)
5-282 Vol. 2C
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VPGATHERQQ (VEX.256 version)
FOR j 0 to 3
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 3
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)
VPGATHERDQ (VEX.256 version)
FOR j 0 to 3
i j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] 0;
FI;
ENDFOR
FOR j 0 to 3
k j * 32;
i j * 64;
DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices
Vol. 2C 5-283
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDQ: __m128i _mm_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERDQ: __m128i _mm_mask_i32gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int
scale);
VPGATHERDQ: __m256i _mm256_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERDQ: __m256i _mm256_mask_i32gather_epi64 (__m256i src, __int64 const * base, __m128i index, __m256i mask, const
int scale);
VPGATHERQQ: __m128i _mm_i64gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERQQ: __m128i _mm_mask_i64gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int
scale);
VPGATHERQQ: __m256i _mm256_i64gather_epi64 __(int64 const * base, __m256i index, const int scale);
VPGATHERQQ: __m256i _mm256_mask_i64gather_epi64 (__m256i src, __int64 const * base, __m256i index, __m256i mask, const
int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 12.
5-284 Vol. 2C
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V-Z
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
Opcode/
Instruction
Op/
En
EVEX.128.66.0F38.W0 91 /vsib
VPGATHERQD xmm1 {k1}, vm64x
EVEX.256.66.0F38.W0 91 /vsib
VPGATHERQD xmm1 {k1}, vm64y
EVEX.512.66.0F38.W0 91 /vsib
VPGATHERQD ymm1 {k1}, vm64z
EVEX.128.66.0F38.W1 91 /vsib
VPGATHERQQ xmm1 {k1}, vm64x
EVEX.256.66.0F38.W1 91 /vsib
VPGATHERQQ ymm1 {k1}, vm64y
EVEX.512.66.0F38.W1 91 /vsib
VPGATHERQQ zmm1 {k1}, vm64z
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Using signed qword indices, gather dword values from
memory using writemask k1 for merging-masking.
Using signed qword indices, gather dword values from
memory using writemask k1 for merging-masking.
Using signed qword indices, gather dword values from
memory using writemask k1 for merging-masking.
Using signed qword indices, gather quadword values from
memory using writemask k1 for merging-masking.
Using signed qword indices, gather quadword values from
memory using writemask k1 for merging-masking.
Using signed qword indices, gather quadword values from
memory using writemask k1 for merging-masking.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
Description
A set of 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector
VINDEX with scale SCALE are gathered. The result is written into a vector register. The elements are specified via
the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be loaded if their
corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination
register is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
•
The values may be read from memory in any order. Memory ordering with other instructions follows the Intel64 memory-ordering model.
•
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
•
Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
Vol. 2C 5-285
INSTRUCTION SET REFERENCE, V-Z
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
Not valid with 16-bit effective addresses. Will deliver a #UD fault.
These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
VPGATHERQD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j]
THEN DEST[i+31:i] MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]), 1)
k1[j] 0
ELSE *DEST[i+31:i] remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL/2] 0
VPGATHERQQ (EVEX encoded version)
(KL, VL) = (2, 64), (4, 128), (8, 256)
FOR j 0 TO KL-1
i j * 64
IF k1[j]
THEN DEST[i+63:i]
MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP])
k1[j] 0
ELSE *DEST[i+63:i] remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
DEST[MAX_VL-1:VL] 0
5-286 Vol. 2C
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERQD __m256i _mm512_i64gather_epi32(__m512i vdx, void * base, int scale);
VPGATHERQD __m256i _mm512_mask_i64gather_epi32lo(__m256i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQD __m128i _mm256_mask_i64gather_epi32lo(__m128i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQD __m128i _mm_mask_i64gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_i64gather_epi64( __m512i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_mask_i64gather_epi64(__m512i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQQ __m256i _mm256_mask_i64gather_epi64(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQQ __m128i _mm_mask_i64gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12.
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
Vol. 2C 5-287
INSTRUCTION SET REFERENCE, V-Z
VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values
Opcode/
Instruction
Op/
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W1 42 /r
VGETEXPPD xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.66.0F38.W1 42 /r
VGETEXPPD ymm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.W1 42 /r
VGETEXPPD zmm1 {k1}{z},
zmm2/m512/m64bcst{sae}
FV
V/V
AVX512F
Description
Convert the exponent of packed double-precision floating-point
values in the source operand to DP FP results representing
unbiased integer exponents and stores the results in the
destination register.
Convert the exponent of packed double-precision floating-point
values in the source operand to DP FP results representing
unbiased integer exponents and stores the results in the
destination register.
Convert the exponent of packed double-precision floating-point
values in the source operand to DP FP results representing
unbiased integer exponents and stores the results in the
destination under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Extracts the biased exponents from the normalized DP FP representation of each qword data element of the source
operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input
data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to doubleprecision FP value and written to the corresponding qword elements of the destination operand (the first operand)
as DP FP numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 64-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal representation). Special cases of input values are listed in Table 5-16.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for the greatest integer not exceeding real number x.
Table 5-16. VGETEXPPD/SD Special Cases
5-288 Vol. 2C
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
No Exceptions
0 < |src1| < INF
floor(log2(|src1|))
| src1| = +INF
+INF
| src1| = 0
-INF
VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values
INSTRUCTION SET REFERENCE, V-Z
Operation
NormalizeExpTinyDPFP(SRC[63:0])
{
// Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.
Src.Jbit 0;
Dst.exp 1;
Dst.fraction SRC[51:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit Dst.fraction[51];
// Get the fraction MSB
Dst.fraction Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction 0;
// zero out fraction bits
Dst.sign 1;
// Return negative sign
TMP[63:0] MXCSR.DAZ? 0 : (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction) ;
Return (TMP[63:0]);
}
ConvertExpDPFP(SRC[63:0])
{
Src.sign 0;
// Zero out sign bit
Src.exp SRC[62:52];
Src.fraction SRC[51:0];
// Check for NaN
IF (SRC = NaN)
{
IF ( SRC = SNAN ) SET IE;
Return QNAN(SRC);
}
// Check for +INF
IF (SRC = +INF) Return (SRC);
// check if zero operand
IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
}
ELSE
// check if denormal operand (notice that MXCSR.DAZ = 0)
{
IF ((Src.exp = 0) AND (Src.fraction != 0))
{
TMP[63:0] NormalizeExpTinyDPFP(SRC[63:0]) ;
// Get Normalized Exponent
Set #DE
}
ELSE
// exponent value is correct
{
Dst.fraction 0;
// zero out fraction bits
TMP[63:0] (Src.sign << 63) OR (Src.exp << 52) OR (Src.fraction) ;
}
TMP SAR(TMP, 52) ;
// Shift Arithmetic Right
TMP TMP – 1023;
// Subtract Bias
Return CvtI2D(TMP) ;
// Convert INT to Double-Precision FP number
}
}
VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values
Vol. 2C 5-289
INSTRUCTION SET REFERENCE, V-Z
VGETEXPPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+63:i]
ConvertExpDPFP(SRC[63:0])
ELSE
DEST[i+63:i]
ConvertExpDPFP(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPD __m512d _mm512_getexp_pd(__m512d a);
VGETEXPPD __m512d _mm512_mask_getexp_pd(__m512d s, __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_maskz_getexp_pd( __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_getexp_round_pd(__m512d a, int sae);
VGETEXPPD __m512d _mm512_mask_getexp_round_pd(__m512d s, __mmask8 k, __m512d a, int sae);
VGETEXPPD __m512d _mm512_maskz_getexp_round_pd( __mmask8 k, __m512d a, int sae);
VGETEXPPD __m256d _mm256_getexp_pd(__m256d a);
VGETEXPPD __m256d _mm256_mask_getexp_pd(__m256d s, __mmask8 k, __m256d a);
VGETEXPPD __m256d _mm256_maskz_getexp_pd( __mmask8 k, __m256d a);
VGETEXPPD __m128d _mm_getexp_pd(__m128d a);
VGETEXPPD __m128d _mm_mask_getexp_pd(__m128d s, __mmask8 k, __m128d a);
VGETEXPPD __m128d _mm_maskz_getexp_pd( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E2.
#UD
5-290 Vol. 2C
If EVEX.vvvv != 1111B.
VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values
INSTRUCTION SET REFERENCE, V-Z
VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values
Opcode/
Instruction
Op/
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W0 42 /r
VGETEXPPS xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.66.0F38.W0 42 /r
VGETEXPPS ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.W0 42 /r
VGETEXPPS zmm1 {k1}{z},
zmm2/m512/m32bcst{sae}
FV
V/V
AVX512F
Description
Convert the exponent of packed single-precision floating-point
values in the source operand to SP FP results representing
unbiased integer exponents and stores the results in the
destination register.
Convert the exponent of packed single-precision floating-point
values in the source operand to SP FP results representing
unbiased integer exponents and stores the results in the
destination register.
Convert the exponent of packed single-precision floating-point
values in the source operand to SP FP results representing
unbiased integer exponents and stores the results in the
destination register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Extracts the biased exponents from the normalized SP FP representation of each dword element of the source
operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input
data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to single-precision FP value and written to the corresponding dword elements of the destination operand (the first operand) as SP
FP numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 32-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal representation). Special cases of input values are listed in Table 5-17.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
FP exceptions.
Table 5-17. VGETEXPPS/SS Special Cases
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
No Exceptions
0 < |src1| < INF
floor(log2(|src1|))
| src1| = +INF
+INF
| src1| = 0
-INF
VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values
Vol. 2C 5-291
INSTRUCTION SET REFERENCE, V-Z
Figure 5-14 illustrates the VGETEXPPS functionality on input values with normalized representation.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
exp
Fraction
s
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Src = 2^1
SAR Src, 23 = 080h
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
-Bias
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1
Tmp - Bias = 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Cvt_PI2PS(01h) = 2^0
0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-14. VGETEXPPS Functionality On Normal Input values
Operation
NormalizeExpTinySPFP(SRC[31:0])
{
// Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.
Src.Jbit 0;
Dst.exp 1;
Dst.fraction SRC[22:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit Dst.fraction[22];
// Get the fraction MSB
Dst.fraction Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction 0;
// zero out fraction bits
Dst.sign 1;
// Return negative sign
TMP[31:0] MXCSR.DAZ? 0 : (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction) ;
Return (TMP[31:0]);
}
ConvertExpSPFP(SRC[31:0])
{
Src.sign 0;
// Zero out sign bit
Src.exp SRC[30:23];
Src.fraction SRC[22:0];
// Check for NaN
IF (SRC = NaN)
{
IF ( SRC = SNAN ) SET IE;
Return QNAN(SRC);
}
// Check for +INF
IF (SRC = +INF) Return (SRC);
// check if zero operand
IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
}
ELSE
// check if denormal operand (notice that MXCSR.DAZ = 0)
{
5-292 Vol. 2C
VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values
INSTRUCTION SET REFERENCE, V-Z
IF ((Src.exp = 0) AND (Src.fraction != 0))
{
TMP[31:0] NormalizeExpTinySPFP(SRC[31:0]) ;
// Get Normalized Exponent
Set #DE
}
ELSE
// exponent value is correct
{
Dst.fraction 0;
// zero out fraction bits
TMP[31:0] (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction) ;
}
TMP SAR(TMP, 23) ;
// Shift Arithmetic Right
TMP TMP – 127;
// Subtract Bias
Return CvtI2D(TMP) ;
// Convert INT to Single-Precision FP number
}
}
VGETEXPPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+31:i]
ConvertExpSPFP(SRC[31:0])
ELSE
DEST[i+31:i]
ConvertExpSPFP(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values
Vol. 2C 5-293
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPS __m512 _mm512_getexp_ps( __m512 a);
VGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);
VGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);
VGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);
VGETEXPPS __m256 _mm256_getexp_ps(__m256 a);
VGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);
VGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);
VGETEXPPS __m128 _mm_getexp_ps(__m128 a);
VGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);
VGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E2.
#UD
5-294 Vol. 2C
If EVEX.vvvv != 1111B.
VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values
INSTRUCTION SET REFERENCE, V-Z
VGETEXPSD—Convert Exponents of Scalar DP FP Values to DP FP Value
Opcode/
Instruction
Op/
En
EVEX.NDS.LIG.66.0F38.W1 43 /r
VGETEXPSD xmm1 {k1}{z},
xmm2, xmm3/m64{sae}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Convert the biased exponent (bits 62:52) of the low doubleprecision floating-point value in xmm3/m64 to a DP FP value
representing unbiased integer exponent. Stores the result to
the low 64-bit of xmm1 under the writemask k1 and merge
with the other elements of xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Extracts the biased exponent from the normalized DP FP representation of the low qword data element of the
source operand (the third operand) as unbiased signed integer value, or convert the denormal representation of
input data to unbiased negative integer values. The integer value of the unbiased exponent is converted to doubleprecision FP value and written to the destination operand (the first operand) as DP FP numbers. Bits (127:64) of
the XMM register destination are copied from corresponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float64 memory location.
The low quadword element of the destination operand is conditionally updated with writemask k1.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal representation). Special cases of input values are listed in Table 5-16.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Operation
// NormalizeExpTinyDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD
// ConvertExpDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD
VGETEXPSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[63:0]
ConvertExpDPFP(SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VGETEXPSD—Convert Exponents of Scalar DP FP Values to DP FP Value
Vol. 2C 5-295
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSD __m128d _mm_getexp_sd( __m128d a, __m128d b);
VGETEXPSD __m128d _mm_mask_getexp_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_maskz_getexp_sd( __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_getexp_round_sd( __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_mask_getexp_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_maskz_getexp_round_sd( __mmask8 k, __m128d a, __m128d b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E3.
5-296 Vol. 2C
VGETEXPSD—Convert Exponents of Scalar DP FP Values to DP FP Value
INSTRUCTION SET REFERENCE, V-Z
VGETEXPSS—Convert Exponents of Scalar SP FP Values to SP FP Value
Opcode/
Instruction
Op/
En
EVEX.NDS.LIG.66.0F38.W0 43 /r
VGETEXPSS xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Convert the biased exponent (bits 30:23) of the low singleprecision floating-point value in xmm3/m32 to a SP FP
value representing unbiased integer exponent. Stores the
result to xmm1 under the writemask k1 and merge with the
other elements of xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Extracts the biased exponent from the normalized SP FP representation of the low doubleword data element of the
source operand (the third operand) as unbiased signed integer value, or convert the denormal representation of
input data to unbiased negative integer values. The integer value of the unbiased exponent is converted to singleprecision FP value and written to the destination operand (the first operand) as SP FP numbers. Bits (127:32) of
the XMM register destination are copied from corresponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float32 memory location.
The the low doubleword element of the destination operand is conditionally updated with writemask k1.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal representation). Special cases of input values are listed in Table 5-17.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
FP exceptions.
Operation
// NormalizeExpTinySPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS
// ConvertExpSPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS
VGETEXPSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[31:0]
ConvertExpDPFP(SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI
FI;
ENDFOR
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VGETEXPSS—Convert Exponents of Scalar SP FP Values to SP FP Value
Vol. 2C 5-297
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSS __m128 _mm_getexp_ss( __m128 a, __m128 b);
VGETEXPSS __m128 _mm_mask_getexp_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_maskz_getexp_ss( __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_getexp_round_ss( __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_mask_getexp_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_maskz_getexp_round_ss( __mmask8 k, __m128 a, __m128 b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E3.
5-298 Vol. 2C
VGETEXPSS—Convert Exponents of Scalar SP FP Values to SP FP Value
INSTRUCTION SET REFERENCE, V-Z
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector
Opcode/
Instruction
Op/
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F3A.W1 26 /r ib
VGETMANTPD xmm1 {k1}{z},
xmm2/m128/m64bcst, imm8
EVEX.256.66.0F3A.W1 26 /r ib
VGETMANTPD ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F3A.W1 26 /r ib
VGETMANTPD zmm1 {k1}{z},
zmm2/m512/m64bcst{sae},
imm8
FV
V/V
AVX512F
Description
Get Normalized Mantissa from float64 vector
xmm2/m128/m64bcst and store the result in xmm1, using
imm8 for sign control and mantissa interval normalization,
under writemask.
Get Normalized Mantissa from float64 vector
ymm2/m256/m64bcst and store the result in ymm1, using
imm8 for sign control and mantissa interval normalization,
under writemask.
Get Normalized Mantissa from float64 vector
zmm2/m512/m64bcst and store the result in zmm1, using
imm8 for sign control and mantissa interval normalization,
under writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVI
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Convert double-precision floating values in the source operand (the second operand) to DP FP values with the
mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are
written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by
interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64bit memory location.
7
imm8
6
5
4
Must Be Zero
3
2
Sign Control (SC)
1
0
Normaiization Interval
Imm8[1:0] = 00b : Interval is [ 1, 2)
Imm8[3:2] = 00b : sign(SRC)
Imm8[1:0] = 01b : Interval is [1/2, 2)
Imm8[3:2] = 01b : 0
Imm8[1:0] = 10b : Interval is [ 1/2, 1)
Imm8[3] = 1b : qNan_Indefinite if sign(SRC) != 0, regardless of imm8[2].
Imm8[1:0] = 11b : Interval is [3/4, 3/2)
Figure 5-15. Imm8 Controls for VGETMANTPD/SD/PS/SS
For each input DP FP value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector
Vol. 2C 5-299
INSTRUCTION SET REFERENCE, V-Z
If interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in
Figure 5-15.
Each converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b; otherwise instructions will #UD.
Table 5-18. GetMant() Special Float Values Behavior
5-300 Vol. 2C
Input
Result
Exceptions / Comments
NaN
QNaN(SRC)
Ignore interv
If (SRC = SNaN) then #IE
+∞
1.0
Ignore interv
+0
1.0
Ignore interv
-0
IF (SC[0]) THEN +1.0
ELSE -1.0
Ignore interv
-∞
IF (SC[1]) THEN {QNaN_Indefinite}
ELSE {
IF (SC[0]) THEN +1.0
ELSE -1.0
Ignore interv
If (SC[1]) then #IE
negative
SC[1] ? QNaN_Indefinite : Getmant(SRC)
If (SC[1]) then #IE
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector
INSTRUCTION SET REFERENCE, V-Z
Operation
GetNormalizeMantissaDP(SRC[63:0], SignCtrl[1:0], Interv[1:0])
{
// Extracting the SRC sign, exponent and mantissa fields
Dst.sign SignCtrl[0] ? 0 : Src[63];
// Get sign bit
Dst.exp SRC[62:52]; ; Get original exponent value
Dst.fraction SRC[51:0];; Get original fraction value
ZeroOperand (Dst.exp = 0) AND (Dst.fraction = 0);
DenormOperand (Dst.exp = 0h) AND (Dst.fraction != 0);
InfiniteOperand (Dst.exp = 07FFh) AND (Dst.fraction = 0);
NaNOperand (Dst.exp = 07FFh) AND (Dst.fraction != 0);
// Check for NAN operand
IF (NaNOperand)
{
IF (SRC = SNaN) {Set #IE;}
Return QNAN(SRC);
}
// Check for Zero and Infinite operands
IF ((ZeroOperand) OR (InfiniteOperand)
{
Dst.exp 03FFh;
// Override exponent with BIAS
Return ((Dst.sign<<63) | (Dst.exp<<52) | (Dst.fraction));
}
// Check for negative operand (including -0.0)
IF ((Src[63] = 1) AND SignCtrl[1])
{
Set #IE;
Return QNaN_Indefinite;
}
// Checking for denormal operands
IF (DenormOperand)
{
IF (MXCSR.DAZ=1) Dst.fraction 0;// Zero out fraction
ELSE
{
// Jbit is the hidden integral bit. Zero in case of denormal operand.
Src.Jbit 0;
// Zero Src Jbit
Dst.exp 03FFh;
// Override exponent with BIAS
WHILE (Src.Jbit = 0) {
// normalize mantissa
Src.Jbit Dst.fraction[51];
// Get the fraction MSB
Dst.fraction (Dst.fraction << 1);
// Start normalizing the mantissa
Dst.exp-- ;
// Adjust the exponent
}
SET #DE;
// Set DE bit
}
}
// At this point, Dst.fraction is normalized.
// Checking for exponent response
Unbiased.exp Dst.exp – 03FFh;
// subtract the bias from exponent
IsOddExp Unbiased.exp[0];
// recognized unbiased ODD exponent
SignalingBit Dst.fraction[51];
CASE (interv[1:0])
00: Dst.exp 03FFh;
// This is the bias
01: Dst.exp (IsOddExp) ? 03FEh : 03FFh;
// either bias-1, or bias
10: Dst.exp 03FEh;
// bias-1
11: Dst.exp (SignalingBit) ? 03FEh : 03FFh;
// either bias-1, or bias
ESCA
// At this point Dst.exp has the correct result. Form the final destination
DEST[63:0] (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction);
Return (DEST);
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector
Vol. 2C 5-301
INSTRUCTION SET REFERENCE, V-Z
}
SignCtrl[1:0] IMM8[3:2];
Interv[1:0] IMM8[1:0];
VGETMANTPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+63:i] GetNormalizedMantissaDP(SRC[63:0], sc, interv)
ELSE
DEST[i+63:i] GetNormalizedMantissaDP(SRC[i+63:i], sc, interv)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPD __m512d _mm512_getmant_pd( __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_mask_getmant_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_maskz_getmant_pd( __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_getmant_round_pd( __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_mask_getmant_round_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_maskz_getmant_round_pd( __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m256d _mm256_getmant_pd( __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_mask_getmant_pd(__m256d s, __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_maskz_getmant_pd( __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_getmant_pd( __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_mask_getmant_pd(__m128d s, __mmask8 k, __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_maskz_getmant_pd( __mmask8 k, __m128d a, enum intv, enum sgn);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Exceptions Type E2.
#UD
5-302 Vol. 2C
If EVEX.vvvv != 1111B.
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector
INSTRUCTION SET REFERENCE, V-Z
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector
Opcode/
Instruction
Op/
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F3A.W0 26 /r ib
VGETMANTPS xmm1 {k1}{z},
xmm2/m128/m32bcst, imm8
EVEX.256.66.0F3A.W0 26 /r ib
VGETMANTPS ymm1 {k1}{z},
ymm2/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F3A.W0 26 /r ib
VGETMANTPS zmm1 {k1}{z},
zmm2/m512/m32bcst{sae},
imm8
FV
V/V
AVX512F
Description
Get normalized mantissa from float32 vector
xmm2/m128/m32bcst and store the result in xmm1, using
imm8 for sign control and mantissa interval normalization,
under writemask.
Get normalized mantissa from float32 vector
ymm2/m256/m32bcst and store the result in ymm1, using
imm8 for sign control and mantissa interval normalization,
under writemask.
Get normalized mantissa from float32 vector
zmm2/m512/m32bcst and store the result in zmm1, using
imm8 for sign control and mantissa interval normalization,
under writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVI
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Convert single-precision floating values in the source operand (the second operand) to SP FP values with the
mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are
written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by
interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32bit memory location.
For each input SP FP value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.
if interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown
in Figure 5-15.
Each converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector
Vol. 2C 5-303
INSTRUCTION SET REFERENCE, V-Z
Operation
GetNormalizeMantissaSP(SRC[31:0] , SignCtrl[1:0], Interv[1:0])
{
// Extracting the SRC sign, exponent and mantissa fields
Dst.sign SignCtrl[0] ? 0 : Src[31];
// Get sign bit
Dst.exp SRC[30:23]; ; Get original exponent value
Dst.fraction SRC[22:0];; Get original fraction value
ZeroOperand (Dst.exp = 0) AND (Dst.fraction = 0);
DenormOperand (Dst.exp = 0h) AND (Dst.fraction != 0);
InfiniteOperand (Dst.exp = 0FFh) AND (Dst.fraction = 0);
NaNOperand (Dst.exp = 0FFh) AND (Dst.fraction != 0);
// Check for NAN operand
IF (NaNOperand)
{
IF (SRC = SNaN) {Set #IE;}
Return QNAN(SRC);
}
// Check for Zero and Infinite operands
IF ((ZeroOperand) OR (InfiniteOperand)
{
Dst.exp 07Fh;
// Override exponent with BIAS
Return ((Dst.sign<<31) | (Dst.exp<<23) | (Dst.fraction));
}
// Check for negative operand (including -0.0)
IF ((Src[31] = 1) AND SignCtrl[1])
{
Set #IE;
Return QNaN_Indefinite;
}
// Checking for denormal operands
IF (DenormOperand)
{
IF (MXCSR.DAZ=1) Dst.fraction 0;// Zero out fraction
ELSE
{
// Jbit is the hidden integral bit. Zero in case of denormal operand.
Src.Jbit 0;
// Zero Src Jbit
Dst.exp 07Fh;
// Override exponent with BIAS
WHILE (Src.Jbit = 0) {
// normalize mantissa
Src.Jbit Dst.fraction[22];
// Get the fraction MSB
Dst.fraction (Dst.fraction << 1);
// Start normalizing the mantissa
Dst.exp-- ;
// Adjust the exponent
}
SET #DE;
// Set DE bit
}
}
// At this point, Dst.fraction is normalized.
// Checking for exponent response
Unbiased.exp Dst.exp – 07Fh;
// subtract the bias from exponent
IsOddExp Unbiased.exp[0];
// recognized unbiased ODD exponent
SignalingBit Dst.fraction[22];
CASE (interv[1:0])
00: Dst.exp 07Fh;
// This is the bias
01: Dst.exp (IsOddExp) ? 07Eh : 07Fh;
// either bias-1, or bias
10: Dst.exp 07Eh;
// bias-1
11: Dst.exp (SignalingBit) ? 07Eh : 07Fh;
// either bias-1, or bias
ESCA
// Form the final destination
DEST[31:0] (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction);
5-304 Vol. 2C
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector
INSTRUCTION SET REFERENCE, V-Z
Return (DEST);
}
SignCtrl[1:0] IMM8[3:2];
Interv[1:0] IMM8[1:0];
VGETMANTPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+31:i] GetNormalizedMantissaSP(SRC[31:0], sc, interv)
ELSE
DEST[i+31:i] GetNormalizedMantissaSP(SRC[i+31:i], sc, interv)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn;
VGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Exceptions Type E2.
#UD
If EVEX.vvvv != 1111B.
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector
Vol. 2C 5-305
INSTRUCTION SET REFERENCE, V-Z
VGETMANTSD—Extract Float64 of Normalized Mantissas from Float64 Scalar
Opcode/
Instruction
Op/
En
EVEX.NDS.LIG.66.0F3A.W1 27 /r ib
VGETMANTSD xmm1 {k1}{z}, xmm2,
xmm3/m64{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Extract the normalized mantissa of the low float64
element in xmm3/m64 using imm8 for sign control and
mantissa interval normalization. Store the mantissa to
xmm1 under the writemask k1 and merge with the
other elements of xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Convert the double-precision floating values in the low quadword element of the second source operand (the third
operand) to DP FP value with the mantissa normalization and sign control specified by the imm8 byte, see
Figure 5-15. The converted result is written to the low quadword element of the destination operand (the first
operand) using writemask k1. Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control
(sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.
If interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in
Figure 5-15.
The converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous
values.
5-306 Vol. 2C
VGETMANTSD—Extract Float64 of Normalized Mantissas from Float64 Scalar
INSTRUCTION SET REFERENCE, V-Z
Operation
// GetNormalizeMantissaDP(SRC[63:0], SignCtrl[1:0], Interv[1:0]) is defined in the operation section of VGETMANTPD
SignCtrl[1:0] IMM8[3:2];
Interv[1:0] IMM8[1:0];
VGETMANTSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[63:0]
GetNormalizedMantissaDP(SRC2[63:0], sc, interv)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Exceptions Type E3.
VGETMANTSD—Extract Float64 of Normalized Mantissas from Float64 Scalar
Vol. 2C 5-307
INSTRUCTION SET REFERENCE, V-Z
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa from Float32 Vector
Opcode/
Instruction
Op/
En
EVEX.NDS.LIG.66.0F3A.W0 27 /r ib
VGETMANTSS xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Extract the normalized mantissa from the low float32
element of xmm3/m32 using imm8 for sign control and
mantissa interval normalization, store the mantissa to
xmm1 under the writemask k1 and merge with the
other elements of xmm2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Convert the single-precision floating values in the low doubleword element of the second source operand (the third
operand) to SP FP value with the mantissa normalization and sign control specified by the imm8 byte, see
Figure 5-15. The converted result is written to the low doubleword element of the destination operand (the first
operand) using writemask k1. Bits (127:32) of the XMM register destination are copied from corresponding
bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control
(sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.
if interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown
in Figure 5-15.
The converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous
values.
5-308 Vol. 2C
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa from Float32 Vector
INSTRUCTION SET REFERENCE, V-Z
Operation
// GetNormalizeMantissaSP(SRC[31:0], SignCtrl[1:0], Interv[1:0]) is defined in the operation section of VGETMANTPD
SignCtrl[1:0] IMM8[3:2];
Interv[1:0] IMM8[1:0];
VGETMANTSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[31:0]
GetNormalizedMantissaSP(SRC2[31:0], sc, interv)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI
FI;
DEST[127:32] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_mask_getmant_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Exceptions Type E3.
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa from Float32 Vector
Vol. 2C 5-309
INSTRUCTION SET REFERENCE, V-Z
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed
Floating-Point Values
Opcode/
Instruction
Op /
En
RVMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX
VEX.NDS.256.66.0F3A.W0 18 /r ib
VINSERTF128 ymm1, ymm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W0 18 /r ib
VINSERTF32X4 ymm1 {k1}{z}, ymm2,
xmm3/m128, imm8
EVEX.NDS.512.66.0F3A.W0 18 /r ib
VINSERTF32X4 zmm1 {k1}{z}, zmm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W1 18 /r ib
VINSERTF64X2 ymm1 {k1}{z}, ymm2,
xmm3/m128, imm8
EVEX.NDS.512.66.0F3A.W1 18 /r ib
VINSERTF64X2 zmm1 {k1}{z}, zmm2,
xmm3/m128, imm8
EVEX.NDS.512.66.0F3A.W0 1A /r ib
VINSERTF32X8 zmm1 {k1}{z}, zmm2,
ymm3/m256, imm8
EVEX.NDS.512.66.0F3A.W1 1A /r ib
VINSERTF64X4 zmm1 {k1}{z}, zmm2,
ymm3/m256, imm8
T4
V/V
AVX512VL
AVX512F
T4
V/V
AVX512F
T2
V/V
AVX512VL
AVX512DQ
T2
V/V
AVX512DQ
T8
V/V
AVX512DQ
T4
V/V
AVX512F
Description
Insert 128 bits of packed floating-point values from
xmm3/m128 and the remaining values from ymm2
into ymm1.
Insert 128 bits of packed single-precision floatingpoint values from xmm3/m128 and the remaining
values from ymm2 into ymm1 under writemask k1.
Insert 128 bits of packed single-precision floatingpoint values from xmm3/m128 and the remaining
values from zmm2 into zmm1 under writemask k1.
Insert 128 bits of packed double-precision floatingpoint values from xmm3/m128 and the remaining
values from ymm2 into ymm1 under writemask k1.
Insert 128 bits of packed double-precision floatingpoint values from xmm3/m128 and the remaining
values from zmm2 into zmm1 under writemask k1.
Insert 256 bits of packed single-precision floatingpoint values from ymm3/m256 and the remaining
values from zmm2 into zmm1 under writemask k1.
Insert 256 bits of packed double-precision floatingpoint values from ymm3/m256 and the remaining
values from zmm2 into zmm1 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
T2, T4, T8
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
VINSERTF128/VINSERTF32x4 and VINSERTF64x2 insert 128-bits of packed floating-point values from the second
source operand (the third operand) into the destination operand (the first operand) at an 128-bit granularity offset
multiplied by imm8[0] (256-bit) or imm8[1:0]. The remaining portions of the destination operand are copied from
the corresponding fields of the first source operand (the second operand). The second source operand can be either
an XMM register or a 128-bit memory location. The destination and first source operands are vector registers.
VINSERTF32x4: The destination operand is a ZMM/YMM register and updated at 32-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF64x2: The destination operand is a ZMM/YMM register and updated at 64-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF32x8 and VINSERTF64x4 inserts 256-bits of packed floating-point values from the second source operand
(the third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by
imm8[0]. The remaining portions of the destination are copied from the corresponding fields of the first source
operand (the second operand). The second source operand can be either an YMM register or a 256-bit memory
location. The high 7 bits of the immediate are ignored. The destination operand is a ZMM register and updated at
32/64-bit granularity according to the writemask.
5-310 Vol. 2C
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Operation
VINSERTF32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC2[127:0]
1: TMP_DEST[255:128] SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC2[127:0]
01: TMP_DEST[255:128] SRC2[127:0]
10: TMP_DEST[383:256] SRC2[127:0]
11: TMP_DEST[511:384] SRC2[127:0]
ESAC.
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VINSERTF64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC2[127:0]
1: TMP_DEST[255:128] SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC2[127:0]
01: TMP_DEST[255:128] SRC2[127:0]
10: TMP_DEST[383:256] SRC2[127:0]
11: TMP_DEST[511:384] SRC2[127:0]
ESAC.
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
Vol. 2C 5-311
INSTRUCTION SET REFERENCE, V-Z
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VINSERTF32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC2[255:0]
1: TMP_DEST[511:256] SRC2[255:0]
ESAC.
FOR j 0 TO 15
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VINSERTF64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC2[255:0]
1: TMP_DEST[511:256] SRC2[255:0]
ESAC.
FOR j 0 TO 7
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-312 Vol. 2C
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VINSERTF128 (VEX encoded version)
TEMP[255:0] SRC1[255:0]
CASE (imm8[0]) OF
0: TEMP[127:0] SRC2[127:0]
1: TEMP[255:128] SRC2[127:0]
ESAC
DEST TEMP
Intel C/C++ Compiler Intrinsic Equivalent
VINSERTF32x4 __m512 _mm512_insertf32x4( __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_mask_insertf32x4(__m512 s, __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_maskz_insertf32x4( __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_insertf32x4( __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_mask_insertf32x4(__m256 s, __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_maskz_insertf32x4( __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x8 __m512 _mm512_insertf32x8( __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_mask_insertf32x8(__m512 s, __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_maskz_insertf32x8( __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF64x2 __m512d _mm512_insertf64x2( __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_mask_insertf64x2(__m512d s, __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_maskz_insertf64x2( __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_insertf64x2( __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_mask_insertf64x2(__m256d s, __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_maskz_insertf64x2( __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x4 __m512d _mm512_insertf64x4( __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_mask_insertf64x4(__m512d s, __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_maskz_insertf64x4( __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF128 __m256 _mm256_insertf128_ps (__m256 a, __m128 b, int offset);
VINSERTF128 __m256d _mm256_insertf128_pd (__m256d a, __m128d b, int offset);
VINSERTF128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Exceptions Type 6; additionally
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Exceptions Type E6NF.
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
Vol. 2C 5-313
INSTRUCTION SET REFERENCE, V-Z
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed
Integer Values
Opcode/
Instruction
Op /
En
CPUID
Feature
Flag
AVX2
Description
RVMI
64/32
bit Mode
Support
V/V
VEX.NDS.256.66.0F3A.W0 38 /r ib
VINSERTI128 ymm1, ymm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W0 38 /r ib
VINSERTI32X4 ymm1 {k1}{z}, ymm2,
xmm3/m128, imm8
EVEX.NDS.512.66.0F3A.W0 38 /r ib
VINSERTI32X4 zmm1 {k1}{z}, zmm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W1 38 /r ib
VINSERTI64X2 ymm1 {k1}{z}, ymm2,
xmm3/m128, imm8
EVEX.NDS.512.66.0F3A.W1 38 /r ib
VINSERTI64X2 zmm1 {k1}{z}, zmm2,
xmm3/m128, imm8
EVEX.NDS.512.66.0F3A.W0 3A /r ib
VINSERTI32X8 zmm1 {k1}{z}, zmm2,
ymm3/m256, imm8
EVEX.NDS.512.66.0F3A.W1 3A /r ib
VINSERTI64X4 zmm1 {k1}{z}, zmm2,
ymm3/m256, imm8
T4
V/V
AVX512VL
AVX512F
T4
V/V
AVX512F
T2
V/V
AVX512VL
AVX512DQ
T2
V/V
AVX512DQ
T8
V/V
AVX512DQ
T4
V/V
AVX512F
Insert 128 bits of packed doubleword integer values
from xmm3/m128 and the remaining values from
ymm2 into ymm1 under writemask k1.
Insert 128 bits of packed doubleword integer values
from xmm3/m128 and the remaining values from
zmm2 into zmm1 under writemask k1.
Insert 128 bits of packed quadword integer values
from xmm3/m128 and the remaining values from
ymm2 into ymm1 under writemask k1.
Insert 128 bits of packed quadword integer values
from xmm3/m128 and the remaining values from
zmm2 into zmm1 under writemask k1.
Insert 256 bits of packed doubleword integer values
from ymm3/m256 and the remaining values from
zmm2 into zmm1 under writemask k1.
Insert 256 bits of packed quadword integer values
from ymm3/m256 and the remaining values from
zmm2 into zmm1 under writemask k1.
Insert 128 bits of integer data from xmm3/m128 and
the remaining values from ymm2 into ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
T2, T4, T8
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
VINSERTI32x4 and VINSERTI64x2 inserts 128-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at an 128-bit granular offset multiplied by imm8[0]
(256-bit) or imm8[1:0]. The remaining portions of the destination are copied from the corresponding fields of the
first source operand (the second operand). The second source operand can be either an XMM register or a 128-bit
memory location. The high 6/7bits of the immediate are ignored. The destination operand is a ZMM/YMM register
and updated at 32 and 64-bit granularity according to the writemask.
VINSERTI32x8 and VINSERTI64x4 inserts 256-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by imm8[0].
The remaining portions of the destination are copied from the corresponding fields of the first source operand (the
second operand). The second source operand can be either an YMM register or a 256-bit memory location. The
upper bits of the immediate are ignored. The destination operand is a ZMM register and updated at 32 and 64-bit
granularity according to the writemask.
VINSERTI128 inserts 128-bits of packed integer data from the second source operand (the third operand) into the
destination operand (the first operand) at a 128-bit granular offset multiplied by imm8[0]. The remaining portions
of the destination are copied from the corresponding fields of the first source operand (the second operand). The
second source operand can be either an XMM register or a 128-bit memory location. The high 7 bits of the immediate are ignored. VEX.L must be 1, otherwise attempt to execute this instruction with VEX.L=0 will cause #UD.
5-314 Vol. 2C
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
INSTRUCTION SET REFERENCE, V-Z
Operation
VINSERTI32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC2[127:0]
1: TMP_DEST[255:128] SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC2[127:0]
01: TMP_DEST[255:128] SRC2[127:0]
10: TMP_DEST[383:256] SRC2[127:0]
11: TMP_DEST[511:384] SRC2[127:0]
ESAC.
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VINSERTI64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] SRC2[127:0]
1: TMP_DEST[255:128] SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] SRC2[127:0]
01: TMP_DEST[255:128] SRC2[127:0]
10: TMP_DEST[383:256] SRC2[127:0]
11: TMP_DEST[511:384] SRC2[127:0]
ESAC.
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
Vol. 2C 5-315
INSTRUCTION SET REFERENCE, V-Z
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VINSERTI32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC2[255:0]
1: TMP_DEST[511:256] SRC2[255:0]
ESAC.
FOR j 0 TO 15
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VINSERTI64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] SRC2[255:0]
1: TMP_DEST[511:256] SRC2[255:0]
ESAC.
FOR j 0 TO 7
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-316 Vol. 2C
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
INSTRUCTION SET REFERENCE, V-Z
VINSERTI128
TEMP[255:0] SRC1[255:0]
CASE (imm8[0]) OF
0: TEMP[127:0] SRC2[127:0]
1: TEMP[255:128] SRC2[127:0]
ESAC
DEST TEMP
Intel C/C++ Compiler Intrinsic Equivalent
VINSERTI32x4 _mm512i _inserti32x4( __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _mask_inserti32x4(__m512i s, __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _maskz_inserti32x4( __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_inserti32x4( __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_mask_inserti32x4(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_maskz_inserti32x4( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x8 __m512i _mm512_inserti32x8( __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_mask_inserti32x8(__m512i s, __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_maskz_inserti32x8( __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI64x2 __m512i _mm512_inserti64x2( __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_mask_inserti64x2(__m512i s, __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_maskz_inserti64x2( __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_inserti64x2( __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_mask_inserti64x2(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_maskz_inserti64x2( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x4 _mm512_inserti64x4( __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_mask_inserti64x4(__m512i s, __mmask8 k, __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_maskz_inserti64x4( __mmask m, __m512i a, __m256i b, int imm);
VINSERTI128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Exceptions Type 6; additionally
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Exceptions Type E6NF.
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
Vol. 2C 5-317
INSTRUCTION SET REFERENCE, V-Z
VMASKMOV—Conditional SIMD Packed Loads and Stores
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
VEX.NDS.128.66.0F38.W0 2C /r
RVM V/V
AVX
Conditionally load packed single-precision values from
m128 using mask in xmm2 and store in xmm1.
RVM V/V
AVX
Conditionally load packed single-precision values from
m256 using mask in ymm2 and store in ymm1.
RVM V/V
AVX
Conditionally load packed double-precision values from
m128 using mask in xmm2 and store in xmm1.
RVM V/V
AVX
Conditionally load packed double-precision values from
m256 using mask in ymm2 and store in ymm1.
MVR V/V
AVX
Conditionally store packed single-precision values from
xmm2 using mask in xmm1.
MVR V/V
AVX
Conditionally store packed single-precision values from
ymm2 using mask in ymm1.
MVR V/V
AVX
Conditionally store packed double-precision values from
xmm2 using mask in xmm1.
MVR V/V
AVX
Conditionally store packed double-precision values from
ymm2 using mask in ymm1.
VMASKMOVPS xmm1, xmm2, m128
VEX.NDS.256.66.0F38.W0 2C /r
VMASKMOVPS ymm1, ymm2, m256
VEX.NDS.128.66.0F38.W0 2D /r
VMASKMOVPD xmm1, xmm2, m128
VEX.NDS.256.66.0F38.W0 2D /r
VMASKMOVPD ymm1, ymm2, m256
VEX.NDS.128.66.0F38.W0 2E /r
VMASKMOVPS m128, xmm1, xmm2
VEX.NDS.256.66.0F38.W0 2E /r
VMASKMOVPS m256, ymm1, ymm2
VEX.NDS.128.66.0F38.W0 2F /r
VMASKMOVPD m128, xmm1, xmm2
VEX.NDS.256.66.0F38.W0 2F /r
VMASKMOVPD m256, ymm1, ymm2
Description
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
MVR
ModRM:r/m (w)
VEX.vvvv (r)
ModRM:reg (r)
NA
Description
Conditionally moves packed data elements from the second source operand into the corresponding data element of
the destination operand, depending on the mask bits associated with each data element. The mask bits are specified in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instruction. The destination operand is
a memory address for the store form of these instructions. The other operands are both XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.
VMASKMOV should not be used to access memory mapped I/O and un-cached memory as the access and the
ordering of the individual loads or stores it does is implementation specific.
5-318 Vol. 2C
VMASKMOV—Conditional SIMD Packed Loads and Stores
INSTRUCTION SET REFERENCE, V-Z
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an implementation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.
Operation
VMASKMOVPS -128-bit load
DEST[31:0] IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[VLMAX-1:128] 0
VMASKMOVPS - 256-bit load
DEST[31:0] IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VMASKMOVPD - 128-bit load
DEST[63:0] IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[VLMAX-1:128] 0
VMASKMOVPD - 256-bit load
DEST[63:0] IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VMASKMOVPS - 128-bit store
IF (SRC1[31]) DEST[31:0] SRC2[31:0]
IF (SRC1[63]) DEST[63:32] SRC2[63:32]
IF (SRC1[95]) DEST[95:64] SRC2[95:64]
IF (SRC1[127]) DEST[127:96] SRC2[127:96]
VMASKMOVPS - 256-bit store
IF (SRC1[31]) DEST[31:0] SRC2[31:0]
IF (SRC1[63]) DEST[63:32] SRC2[63:32]
IF (SRC1[95]) DEST[95:64] SRC2[95:64]
IF (SRC1[127]) DEST[127:96] SRC2[127:96]
IF (SRC1[159]) DEST[159:128] SRC2[159:128]
IF (SRC1[191]) DEST[191:160] SRC2[191:160]
IF (SRC1[223]) DEST[223:192] SRC2[223:192]
IF (SRC1[255]) DEST[255:224] SRC2[255:224]
VMASKMOV—Conditional SIMD Packed Loads and Stores
Vol. 2C 5-319
INSTRUCTION SET REFERENCE, V-Z
VMASKMOVPD - 128-bit store
IF (SRC1[63]) DEST[63:0] SRC2[63:0]
IF (SRC1[127]) DEST[127:64] SRC2[127:64]
VMASKMOVPD - 256-bit store
IF (SRC1[63]) DEST[63:0] SRC2[63:0]
IF (SRC1[127]) DEST[127:64] SRC2[127:64]
IF (SRC1[191]) DEST[191:128] SRC2[191:128]
IF (SRC1[255]) DEST[255:192] SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
__m256 _mm256_maskload_ps(float const *a, __m256i mask)
void _mm256_maskstore_ps(float *a, __m256i mask, __m256 b)
__m256d _mm256_maskload_pd(double *a, __m256i mask);
void _mm256_maskstore_pd(double *a, __m256i mask, __m256d b);
__m128 _mm128_maskload_ps(float const *a, __m128i mask)
void _mm128_maskstore_ps(float *a, __m128i mask, __m128 b)
__m128d _mm128_maskload_pd(double *a, __m128i mask);
void _mm128_maskstore_pd(double *a, __m128i mask, __m128d b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 6 (No AC# reported for any mask bit combinations);
additionally
#UD
5-320 Vol. 2C
If VEX.W = 1.
VMASKMOV—Conditional SIMD Packed Loads and Stores
INSTRUCTION SET REFERENCE, V-Z
VPBLENDD — Blend Packed Dwords
Opcode/
Instruction
Op/
En
RVMI
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
AVX2
VEX.NDS.128.66.0F3A.W0 02 /r ib
VPBLENDD xmm1, xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.W0 02 /r ib
VPBLENDD ymm1, ymm2, ymm3/m256, imm8
RVMI
V/V
AVX2
Description
Select dwords from xmm2 and xmm3/m128 from
mask specified in imm8 and store the values into
xmm1.
Select dwords from ymm2 and ymm3/m256 from
mask specified in imm8 and store the values into
ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
Description
Dword elements from the source operand (second operand) are conditionally written to the destination operand
(first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a
mask that determines whether the corresponding word in the destination is copied from the source. If a bit in the
mask, corresponding to a word, is “1", then the word is copied, else the word is unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
Operation
VPBLENDD (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] SRC2[31:0]
ELSE DEST[31:0] SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] SRC2[63:32]
ELSE DEST[63:32] SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] SRC2[95:64]
ELSE DEST[95:64] SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] SRC2[127:96]
ELSE DEST[127:96] SRC1[127:96]
IF (imm8[4] == 1) THEN DEST[159:128] SRC2[159:128]
ELSE DEST[159:128] SRC1[159:128]
IF (imm8[5] == 1) THEN DEST[191:160] SRC2[191:160]
ELSE DEST[191:160] SRC1[191:160]
IF (imm8[6] == 1) THEN DEST[223:192] SRC2[223:192]
ELSE DEST[223:192] SRC1[223:192]
IF (imm8[7] == 1) THEN DEST[255:224] SRC2[255:224]
ELSE DEST[255:224] SRC1[255:224]
VPBLENDD — Blend Packed Dwords
Vol. 2C 5-321
INSTRUCTION SET REFERENCE, V-Z
VPBLENDD (VEX.128 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] SRC2[31:0]
ELSE DEST[31:0] SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] SRC2[63:32]
ELSE DEST[63:32] SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] SRC2[95:64]
ELSE DEST[95:64] SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] SRC2[127:96]
ELSE DEST[127:96] SRC1[127:96]
DEST[VLMAX-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDD:
__m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask)
VPBLENDD:
__m256i _mm256_blend_epi32 (__m256i v1, __m256i v2, const int mask)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
5-322 Vol. 2C
If VEX.W = 1.
VPBLENDD — Blend Packed Dwords
INSTRUCTION SET REFERENCE, V-Z
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
Opcode/
Instruction
Op /
En
FVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
EVEX.NDS.128.66.0F38.W0 66 /r
VPBLENDMB xmm1 {k1}{z},
xmm2, xmm3/m128
EVEX.NDS.256.66.0F38.W0 66 /r
VPBLENDMB ymm1 {k1}{z},
ymm2, ymm3/m256
EVEX.NDS.512.66.0F38.W0 66 /r
VPBLENDMB zmm1 {k1}{z},
zmm2, zmm3/m512
EVEX.NDS.128.66.0F38.W1 66 /r
VPBLENDMW xmm1 {k1}{z},
xmm2, xmm3/m128
EVEX.NDS.256.66.0F38.W1 66 /r
VPBLENDMW ymm1 {k1}{z},
ymm2, ymm3/m256
EVEX.NDS.512.66.0F38.W1 66 /r
VPBLENDMW zmm1 {k1}{z},
zmm2, zmm3/m512
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
Description
Blend byte integer vector xmm2 and byte vector
xmm3/m128 and store the result in xmm1, under control
mask.
Blend byte integer vector ymm2 and byte vector
ymm3/m256 and store the result in ymm1, under control
mask.
Blend byte integer vector zmm2 and byte vector
zmm3/m512 and store the result in zmm1, under control
mask.
Blend word integer vector xmm2 and word vector
xmm3/m128 and store the result in xmm1, under control
mask.
Blend word integer vector ymm2 and word vector
ymm3/m256 and store the result in ymm1, under control
mask.
Blend word integer vector zmm2 and word vector
zmm3/m512 and store the result in zmm1, under control
mask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs an element-by-element blending of byte/word elements between the first source operand byte vector
register and the second source operand byte vector from memory or register, using the instruction mask as
selector. The result is written into the destination byte vector register.
The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit memory location.
The mask is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every
element of the destination is conditionally selected between first source or second source using the value of the
related mask bit (0 for first source, 1 for second source).
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
Vol. 2C 5-323
INSTRUCTION SET REFERENCE, V-Z
Operation
VPBLENDMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SRC2[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+7:i] SRC1[i+7:i]
ELSE
; zeroing-masking
DEST[i+7:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0;
VPBLENDMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC2[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+15:i] SRC1[i+15:i]
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDMB __m512i _mm512_mask_blend_epi8(__mmask64 m, __m512i a, __m512i b);
VPBLENDMB __m256i _mm256_mask_blend_epi8(__mmask32 m, __m256i a, __m256i b);
VPBLENDMB __m128i _mm_mask_blend_epi8(__mmask16 m, __m128i a, __m128i b);
VPBLENDMW __m512i _mm512_mask_blend_epi16(__mmask32 m, __m512i a, __m512i b);
VPBLENDMW __m256i _mm256_mask_blend_epi16(__mmask16 m, __m256i a, __m256i b);
VPBLENDMW __m128i _mm_mask_blend_epi16(__mmask8 m, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.
5-324 Vol. 2C
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
INSTRUCTION SET REFERENCE, V-Z
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W0 64 /r
VPBLENDMD xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 64 /r
VPBLENDMD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 64 /r
VPBLENDMD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 64 /r
VPBLENDMQ xmm1 {k1}{z},
xmm2, xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 64 /r
VPBLENDMQ ymm1 {k1}{z},
ymm2, ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 64 /r
VPBLENDMQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Blend doubleword integer vector xmm2 and doubleword
vector xmm3/m128/m32bcst and store the result in
xmm1, under control mask.
Blend doubleword integer vector ymm2 and doubleword
vector ymm3/m256/m32bcst and store the result in
ymm1, under control mask.
Blend doubleword integer vector zmm2 and doubleword
vector zmm3/m512/m32bcst and store the result in
zmm1, under control mask.
Blend quadword integer vector xmm2 and quadword
vector xmm3/m128/m64bcst and store the result in
xmm1, under control mask.
Blend quadword integer vector ymm2 and quadword
vector ymm3/m256/m64bcst and store the result in
ymm1, under control mask.
Blend quadword integer vector zmm2 and quadword
vector zmm3/m512/m64bcst and store the result in
zmm1, under control mask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs an element-by-element blending of dword/qword elements between the first source operand (the second
operand) and the elements of the second source operand (the third operand) using an opmask register as select
control. The blended result is written into the destination.
The destination and first source operands are ZMM registers. The second source operand can be a ZMM register, a
512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location.
The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element
selector: every element of the destination is conditionally selected between first source or second source using the
value of the related mask bit (0 for the first source operand, 1 for the second source operand).
If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
Vol. 2C 5-325
INSTRUCTION SET REFERENCE, V-Z
Operation
VPBLENDMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no controlmask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] SRC2[31:0]
ELSE
DEST[i+31:i] SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+31:i] SRC1[i+31:i]
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0;
VPBLENDMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no controlmask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] SRC2[31:0]
ELSE
DEST[i+31:i] SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+31:i] SRC1[i+31:i]
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-326 Vol. 2C
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDMD __m512i _mm512_mask_blend_epi32(__mmask16 k, __m512i a, __m512i b);
VPBLENDMD __m256i _mm256_mask_blend_epi32(__mmask8 m, __m256i a, __m256i b);
VPBLENDMD __m128i _mm_mask_blend_epi32(__mmask8 m, __m128i a, __m128i b);
VPBLENDMQ __m512i _mm512_mask_blend_epi64(__mmask8 k, __m512i a, __m512i b);
VPBLENDMQ __m256i _mm256_mask_blend_epi64(__mmask8 m, __m256i a, __m256i b);
VPBLENDMQ __m128i _mm_mask_blend_epi64(__mmask8 m, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
Vol. 2C 5-327
INSTRUCTION SET REFERENCE, V-Z
VPBROADCASTB/W/D/Q—Load with Broadcast Integer Data from General Purpose Register
Opcode/
Instruction
Op /
En
EVEX.128.66.0F38.W0 7A /r
VPBROADCASTB xmm1 {k1}{z}, reg
EVEX.256.66.0F38.W0 7A /r
VPBROADCASTB ymm1 {k1}{z}, reg
EVEX.512.66.0F38.W0 7A /r
VPBROADCASTB zmm1 {k1}{z}, reg
EVEX.128.66.0F38.W0 7B /r
VPBROADCASTW xmm1 {k1}{z}, reg
EVEX.256.66.0F38.W0 7B /r
VPBROADCASTW ymm1 {k1}{z}, reg
EVEX.512.66.0F38.W0 7B /r
VPBROADCASTW zmm1 {k1}{z}, reg
EVEX.128.66.0F38.W0 7C /r
VPBROADCASTD xmm1 {k1}{z}, r32
EVEX.256.66.0F38.W0 7C /r
VPBROADCASTD ymm1 {k1}{z}, r32
EVEX.512.66.0F38.W0 7C /r
VPBROADCASTD zmm1 {k1}{z}, r32
EVEX.128.66.0F38.W1 7C /r
VPBROADCASTQ xmm1 {k1}{z}, r64
EVEX.256.66.0F38.W1 7C /r
VPBROADCASTQ ymm1 {k1}{z}, r64
EVEX.512.66.0F38.W1 7C /r
VPBROADCASTQ zmm1 {k1}{z}, r64
T1S
64/32
bit
Mode
Support
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/N.E.1
T1S
V/N.E.1
T1S
V/N.E.1
CPUID
Feature
Flag
Description
AVX512VL
AVX512BW
AVX512VL
AVX512BW
AVX512BW
Broadcast an 8-bit value from a GPR to all bytes in the
128-bit destination subject to writemask k1.
Broadcast an 8-bit value from a GPR to all bytes in the
256-bit destination subject to writemask k1.
Broadcast an 8-bit value from a GPR to all bytes in the
512-bit destination subject to writemask k1.
Broadcast a 16-bit value from a GPR to all words in the
128-bit destination subject to writemask k1.
Broadcast a 16-bit value from a GPR to all words in the
256-bit destination subject to writemask k1.
Broadcast a 16-bit value from a GPR to all words in the
512-bit destination subject to writemask k1.
Broadcast a 32-bit value from a GPR to all double-words
in the 128-bit destination subject to writemask k1.
Broadcast a 32-bit value from a GPR to all double-words
in the 256-bit destination subject to writemask k1.
Broadcast a 32-bit value from a GPR to all double-words
in the 512-bit destination subject to writemask k1.
Broadcast a 64-bit value from a GPR to all quad-words in
the 128-bit destination subject to writemask k1.
Broadcast a 64-bit value from a GPR to all quad-words in
the 256-bit destination subject to writemask k1.
Broadcast a 64-bit value from a GPR to all quad-words in
the 512-bit destination subject to writemask k1.
AVX512VL
AVX512BW
AVX512VL
AVX512BW
AVX512BW
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
NOTES:
1. EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Broadcasts a 8-bit, 16-bit, 32-bit or 64-bit value from a general-purpose register (the second operand) to all the
locations in the destination vector register (the first operand) using the writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-328 Vol. 2C
VPBROADCASTB/W/D/Q—Load with Broadcast Integer Data from General Purpose Register
INSTRUCTION SET REFERENCE, V-Z
Operation
VPBROADCASTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
i j * 8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SRC[7:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC[15:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTB/W/D/Q—Load with Broadcast Integer Data from General Purpose Register
Vol. 2C 5-329
INSTRUCTION SET REFERENCE, V-Z
VPBROADCASTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTB __m512i _mm512_mask_set1_epi8(__m512i s, __mmask64 k, int a);
VPBROADCASTB __m512i _mm512_maskz_set1_epi8( __mmask64 k, int a);
VPBROADCASTB __m256i _mm256_mask_set1_epi8(__m256i s, __mmask32 k, int a);
VPBROADCASTB __m256i _mm256_maskz_set1_epi8( __mmask32 k, int a);
VPBROADCASTB __m128i _mm_mask_set1_epi8(__m128i s, __mmask16 k, int a);
VPBROADCASTB __m128i _mm_maskz_set1_epi8( __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_mask_set1_epi32(__m512i s, __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_maskz_set1_epi32( __mmask16 k, int a);
VPBROADCASTD __m256i _mm256_mask_set1_epi32(__m256i s, __mmask8 k, int a);
VPBROADCASTD __m256i _mm256_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTD __m128i _mm_mask_set1_epi32(__m128i s, __mmask8 k, int a);
VPBROADCASTD __m128i _mm_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTQ __m512i _mm512_mask_set1_epi64(__m512i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m512i _mm512_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_mask_set1_epi64(__m256i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_mask_set1_epi64(__m128i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTW __m512i _mm512_mask_set1_epi16(__m512i s, __mmask32 k, int a);
VPBROADCASTW __m512i _mm512_maskz_set1_epi16( __mmask32 k, int a);
VPBROADCASTW __m256i _mm256_mask_set1_epi16(__m256i s, __mmask16 k, int a);
VPBROADCASTW __m256i _mm256_maskz_set1_epi16( __mmask16 k, int a);
VPBROADCASTW __m128i _mm_mask_set1_epi16(__m128i s, __mmask8 k, int a);
VPBROADCASTW __m128i _mm_maskz_set1_epi16( __mmask8 k, int a);
Exceptions
EVEX-encoded instructions, see Exceptions Type E7NM.
#UD
5-330 Vol. 2C
If EVEX.vvvv != 1111B.
VPBROADCASTB/W/D/Q—Load with Broadcast Integer Data from General Purpose Register
INSTRUCTION SET REFERENCE, V-Z
VPBROADCAST—Load Integer and Broadcast
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
VEX.128.66.0F38.W0 78 /r
VPBROADCASTB xmm1, xmm2/m8
VEX.256.66.0F38.W0 78 /r
VPBROADCASTB ymm1, xmm2/m8
EVEX.128.66.0F38.W0 78 /r
VPBROADCASTB xmm1{k1}{z}, xmm2/m8
EVEX.256.66.0F38.W0 78 /r
VPBROADCASTB ymm1{k1}{z}, xmm2/m8
EVEX.512.66.0F38.W0 78 /r
VPBROADCASTB zmm1{k1}{z}, xmm2/m8
RM
V/V
AVX2
T1S
V/V
T1S
V/V
T1S
V/V
AVX512VL
AVX512BW
AVX512VL
AVX512BW
AVX512BW
VEX.128.66.0F38.W0 79 /r
VPBROADCASTW xmm1, xmm2/m16
VEX.256.66.0F38.W0 79 /r
VPBROADCASTW ymm1, xmm2/m16
EVEX.128.66.0F38.W0 79 /r
VPBROADCASTW xmm1{k1}{z}, xmm2/m16
RM
V/V
AVX2
RM
V/V
AVX2
T1S
V/V
AVX512VL
AVX512BW
EVEX.256.66.0F38.W0 79 /r
VPBROADCASTW ymm1{k1}{z}, xmm2/m16
T1S
V/V
AVX512VL
AVX512BW
EVEX.512.66.0F38.W0 79 /r
VPBROADCASTW zmm1{k1}{z}, xmm2/m16
T1S
V/V
AVX512BW
VEX.128.66.0F38.W0 58 /r
VPBROADCASTD xmm1, xmm2/m32
VEX.256.66.0F38.W0 58 /r
VPBROADCASTD ymm1, xmm2/m32
EVEX.128.66.0F38.W0 58 /r
VPBROADCASTD xmm1 {k1}{z}, xmm2/m32
RM
V/V
AVX2
RM
V/V
AVX2
T1S
V/V
AVX512VL
AVX512F
EVEX.256.66.0F38.W0 58 /r
VPBROADCASTD ymm1 {k1}{z}, xmm2/m32
T1S
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.W0 58 /r
VPBROADCASTD zmm1 {k1}{z}, xmm2/m32
T1S
V/V
AVX512F
VEX.128.66.0F38.W0 59 /r
VPBROADCASTQ xmm1, xmm2/m64
VEX.256.66.0F38.W0 59 /r
VPBROADCASTQ ymm1, xmm2/m64
EVEX.128.66.0F38.W1 59 /r
VPBROADCASTQ xmm1 {k1}{z}, xmm2/m64
EVEX.256.66.0F38.W1 59 /r
VPBROADCASTQ ymm1 {k1}{z}, xmm2/m64
EVEX.512.66.0F38.W1 59 /r
VPBROADCASTQ zmm1 {k1}{z}, xmm2/m64
EVEX.128.66.0F38.W0 59 /r
VBROADCASTI32x2 xmm1 {k1}{z}, xmm2/m64
RM
V/V
AVX2
RM
V/V
AVX2
T1S
V/V
T1S
V/V
T1S
V/V
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
T2
V/V
VPBROADCAST—Load Integer and Broadcast
AVX512VL
AVX512DQ
Description
Broadcast a byte integer in the source operand
to sixteen locations in xmm1.
Broadcast a byte integer in the source operand
to thirty-two locations in ymm1.
Broadcast a byte integer in the source operand
to locations in xmm1 subject to writemask k1.
Broadcast a byte integer in the source operand
to locations in ymm1 subject to writemask k1.
Broadcast a byte integer in the source operand
to 64 locations in zmm1 subject to writemask
k1.
Broadcast a word integer in the source
operand to eight locations in xmm1.
Broadcast a word integer in the source
operand to sixteen locations in ymm1.
Broadcast a word integer in the source
operand to locations in xmm1 subject to
writemask k1.
Broadcast a word integer in the source
operand to locations in ymm1 subject to
writemask k1.
Broadcast a word integer in the source
operand to 32 locations in zmm1 subject to
writemask k1.
Broadcast a dword integer in the source
operand to four locations in xmm1.
Broadcast a dword integer in the source
operand to eight locations in ymm1.
Broadcast a dword integer in the source
operand to locations in xmm1 subject to
writemask k1.
Broadcast a dword integer in the source
operand to locations in ymm1 subject to
writemask k1.
Broadcast a dword integer in the source
operand to locations in zmm1 subject to
writemask k1.
Broadcast a qword element in source operand
to two locations in xmm1.
Broadcast a qword element in source operand
to four locations in ymm1.
Broadcast a qword element in source operand
to locations in xmm1 subject to writemask k1.
Broadcast a qword element in source operand
to locations in ymm1 subject to writemask k1.
Broadcast a qword element in source operand
to locations in zmm1 subject to writemask k1.
Broadcast two dword elements in source
operand to locations in xmm1 subject to
writemask k1.
Vol. 2C 5-331
INSTRUCTION SET REFERENCE, V-Z
Opcode/
Instruction
Op /
En
T2
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.256.66.0F38.W0 59 /r
VBROADCASTI32x2 ymm1 {k1}{z}, xmm2/m64
EVEX.512.66.0F38.W0 59 /r
VBROADCASTI32x2 zmm1 {k1}{z}, xmm2/m64
T2
V/V
AVX512DQ
VEX.256.66.0F38.W0 5A /r
VBROADCASTI128 ymm1, m128
EVEX.256.66.0F38.W0 5A /r
VBROADCASTI32X4 ymm1 {k1}{z}, m128
RM
V/V
AVX2
T4
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.W0 5A /r
VBROADCASTI32X4 zmm1 {k1}{z}, m128
T4
V/V
AVX512F
EVEX.256.66.0F38.W1 5A /r
VBROADCASTI64X2 ymm1 {k1}{z}, m128
T2
V/V
AVX512VL
AVX512DQ
EVEX.512.66.0F38.W1 5A /r
VBROADCASTI64X2 zmm1 {k1}{z}, m128
T2
V/V
AVX512DQ
EVEX.512.66.0F38.W0 5B /r
VBROADCASTI32X8 zmm1 {k1}{z}, m256
T8
V/V
AVX512DQ
EVEX.512.66.0F38.W1 5B /r
VBROADCASTI64X4 zmm1 {k1}{z}, m256
T4
V/V
AVX512F
Description
Broadcast two dword elements in source
operand to locations in ymm1 subject to
writemask k1.
Broadcast two dword elements in source
operand to locations in zmm1 subject to
writemask k1.
Broadcast 128 bits of integer data in mem to
low and high 128-bits in ymm1.
Broadcast 128 bits of 4 doubleword integer
data in mem to locations in ymm1 using
writemask k1.
Broadcast 128 bits of 4 doubleword integer
data in mem to locations in zmm1 using
writemask k1.
Broadcast 128 bits of 2 quadword integer data
in mem to locations in ymm1 using writemask
k1.
Broadcast 128 bits of 2 quadword integer data
in mem to locations in zmm1 using writemask
k1.
Broadcast 256 bits of 8 doubleword integer
data in mem to locations in zmm1 using
writemask k1.
Broadcast 256 bits of 4 quadword integer data
in mem to locations in zmm1 using writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1S, T2, T4, T8
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Load integer data from the source operand (the second operand) and broadcast to all elements of the destination
operand (the first operand).
VEX256-encoded VPBROADCASTB/W/D/Q: The source operand is 8-bit, 16-bit, 32-bit, 64-bit memory location or
the low 8-bit, 16-bit 32-bit, 64-bit data in an XMM register. The destination operand is a YMM register.
VPBROADCASTI128 support the source operand of 128-bit memory location. Register source encodings for
VPBROADCASTI128 is reserved and will #UD. Bits (MAX_VL-1:256) of the destination register are zeroed.
EVEX-encoded VPBROADCASTD/Q: The source operand is a 32-bit, 64-bit memory location or the low 32-bit, 64bit data in an XMM register. The destination operand is a ZMM/YMM/XMM register and updated according to the
writemask k1.
VPBROADCASTI32X4 and VPBROADCASTI64X4: The destination operand is a ZMM register and updated according
to the writemask k1. The source operand is 128-bit or 256-bit memory location. Register source encodings for
VBROADCASTI32X4 and VBROADCASTI64X4 are reserved and will #UD.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
If VPBROADCASTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.
5-332 Vol. 2C
VPBROADCAST—Load Integer and Broadcast
INSTRUCTION SET REFERENCE, V-Z
X0
m32
DEST
X0
X0
X0
X0
X0
X0
X0
X0
Figure 5-16. VPBROADCASTD Operation (VEX.256 encoded version)
X0
m32
DEST
0
0
0
0
X0
X0
X0
X0
Figure 5-17. VPBROADCASTD Operation (128-bit version)
m64
DEST
X0
X0
X0
X0
X0
Figure 5-18. VPBROADCASTQ Operation (256-bit version)
m128
DEST
X0
X0
X0
Figure 5-19. VBROADCASTI128 Operation (256-bit version)
VPBROADCAST—Load Integer and Broadcast
Vol. 2C 5-333
INSTRUCTION SET REFERENCE, V-Z
m256
DEST
X0
X0
X0
Figure 5-20. VBROADCASTI256 Operation (512-bit version)
Operation
VPBROADCASTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
i j * 8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SRC[7:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC[15:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTD (128 bit version)
temp SRC[31:0]
DEST[31:0] temp
DEST[63:32] temp
DEST[95:64] temp
DEST[127:96] temp
DEST[MAX_VL-1:128] 0
5-334 Vol. 2C
VPBROADCAST—Load Integer and Broadcast
INSTRUCTION SET REFERENCE, V-Z
VPBROADCASTD (VEX.256 encoded version)
temp SRC[31:0]
DEST[31:0] temp
DEST[63:32] temp
DEST[95:64] temp
DEST[127:96] temp
DEST[159:128] temp
DEST[191:160] temp
DEST[223:192] temp
DEST[255:224] temp
DEST[MAX_VL-1:256] 0
VPBROADCASTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPBROADCASTQ (VEX.256 encoded version)
temp SRC[63:0]
DEST[63:0] temp
DEST[127:64] temp
DEST[191:128] temp
DEST[255:192] temp
DEST[MAX_VL-1:256] 0
VPBROADCASTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCASTI32x2 (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
VPBROADCAST—Load Integer and Broadcast
Vol. 2C 5-335
INSTRUCTION SET REFERENCE, V-Z
FOR j 0 TO KL-1
i j * 32
n (j mod 2) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCASTI128 (VEX.256 encoded version)
temp SRC[127:0]
DEST[127:0] temp
DEST[255:128] temp
DEST[MAX_VL-1:256] 0
VBROADCASTI32X4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j 0 TO KL-1
i j* 32
n (j modulo 4) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCASTI64X2 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 64
n (j modulo 2) * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[n+63:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI
FI;
ENDFOR;
5-336 Vol. 2C
VPBROADCAST—Load Integer and Broadcast
INSTRUCTION SET REFERENCE, V-Z
VBROADCASTI32X8 (EVEX.U1.512 encoded version)
FOR j 0 TO 15
i j * 32
n (j modulo 8) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VBROADCASTI64X4 (EVEX.512 encoded version)
FOR j 0 TO 7
i j * 64
n (j modulo 4) * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] SRC[n+63:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTB __m512i _mm512_broadcastb_epi8( __m128i a);
VPBROADCASTB __m512i _mm512_mask_broadcastb_epi8(__m512i s, __mmask64 k, __m128i a);
VPBROADCASTB __m512i _mm512_maskz_broadcastb_epi8( __mmask64 k, __m128i a);
VPBROADCASTB __m256i _mm256_broadcastb_epi8(__m128i a);
VPBROADCASTB __m256i _mm256_mask_broadcastb_epi8(__m256i s, __mmask32 k, __m128i a);
VPBROADCASTB __m256i _mm256_maskz_broadcastb_epi8( __mmask32 k, __m128i a);
VPBROADCASTB __m128i _mm_mask_broadcastb_epi8(__m128i s, __mmask16 k, __m128i a);
VPBROADCASTB __m128i _mm_maskz_broadcastb_epi8( __mmask16 k, __m128i a);
VPBROADCASTB __m128i _mm_broadcastb_epi8(__m128i a);
VPBROADCASTD __m512i _mm512_broadcastd_epi32( __m128i a);
VPBROADCASTD __m512i _mm512_mask_broadcastd_epi32(__m512i s, __mmask16 k, __m128i a);
VPBROADCASTD __m512i _mm512_maskz_broadcastd_epi32( __mmask16 k, __m128i a);
VPBROADCASTD __m256i _mm256_broadcastd_epi32( __m128i a);
VPBROADCASTD __m256i _mm256_mask_broadcastd_epi32(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTD __m256i _mm256_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_broadcastd_epi32(__m128i a);
VPBROADCASTD __m128i _mm_mask_broadcastd_epi32(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_broadcastq_epi64( __m128i a);
VPBROADCASTQ __m512i _mm512_mask_broadcastq_epi64(__m512i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCAST—Load Integer and Broadcast
Vol. 2C 5-337
INSTRUCTION SET REFERENCE, V-Z
VPBROADCASTQ __m256i _mm256_broadcastq_epi64(__m128i a);
VPBROADCASTQ __m256i _mm256_mask_broadcastq_epi64(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m256i _mm256_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_broadcastq_epi64(__m128i a);
VPBROADCASTQ __m128i _mm_mask_broadcastq_epi64(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCASTW __m512i _mm512_broadcastw_epi16(__m128i a);
VPBROADCASTW __m512i _mm512_mask_broadcastw_epi16(__m512i s, __mmask32 k, __m128i a);
VPBROADCASTW __m512i _mm512_maskz_broadcastw_epi16( __mmask32 k, __m128i a);
VPBROADCASTW __m256i _mm256_broadcastw_epi16(__m128i a);
VPBROADCASTW __m256i _mm256_mask_broadcastw_epi16(__m256i s, __mmask16 k, __m128i a);
VPBROADCASTW __m256i _mm256_maskz_broadcastw_epi16( __mmask16 k, __m128i a);
VPBROADCASTW __m128i _mm_broadcastw_epi16(__m128i a);
VPBROADCASTW __m128i _mm_mask_broadcastw_epi16(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTW __m128i _mm_maskz_broadcastw_epi16( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_broadcast_i32x2( __m128i a);
VBROADCASTI32x2 __m512i _mm512_mask_broadcast_i32x2(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_maskz_broadcast_i32x2( __mmask16 k, __m128i a);
VBROADCASTI32x2 __m256i _mm256_broadcast_i32x2( __m128i a);
VBROADCASTI32x2 __m256i _mm256_mask_broadcast_i32x2(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI32x2 __m256i _mm256_maskz_broadcast_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_broadcastq_i32x2(__m128i a);
VBROADCASTI32x2 __m128i _mm_mask_broadcastq_i32x2(__m128i s, __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_maskz_broadcastq_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_broadcast_i32x4( __m128i a);
VBROADCASTI32x4 __m512i _mm512_mask_broadcast_i32x4(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_maskz_broadcast_i32x4( __mmask16 k, __m128i a);
VBROADCASTI32x4 __m256i _mm256_broadcast_i32x4( __m128i a);
VBROADCASTI32x4 __m256i _mm256_mask_broadcast_i32x4(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI32x4 __m256i _mm256_maskz_broadcast_i32x4( __mmask8 k, __m128i a);
VBROADCASTI32x8 __m512i _mm512_broadcast_i32x8( __m256i a);
VBROADCASTI32x8 __m512i _mm512_mask_broadcast_i32x8(__m512i s, __mmask16 k, __m256i a);
VBROADCASTI32x8 __m512i _mm512_maskz_broadcast_i32x8( __mmask16 k, __m256i a);
VBROADCASTI64x2 __m512i _mm512_broadcast_i64x2( __m128i a);
VBROADCASTI64x2 __m512i _mm512_mask_broadcast_i64x2(__m512i s, __mmask8 k, __m128i a);
VBROADCASTI64x2 __m512i _mm512_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x2 __m256i _mm256_broadcast_i64x2( __m128i a);
VBROADCASTI64x2 __m256i _mm256_mask_broadcast_i64x2(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI64x2 __m256i _mm256_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x4 __m512i _mm512_broadcast_i64x4( __m256i a);
VBROADCASTI64x4 __m512i _mm512_mask_broadcast_i64x4(__m512i s, __mmask8 k, __m256i a);
VBROADCASTI64x4 __m512i _mm512_maskz_broadcast_i64x4( __mmask8 k, __m256i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, syntax with reg/mem operand, see Exceptions Type E6.
#UD
If VEX.L = 0 for VPBROADCASTQ, VPBROADCASTI128.
If EVEX.L’L = 0 for VBROADCASTI32X4/VBROADCASTI64X2.
If EVEX.L’L < 10b for VBROADCASTI32X8/VBROADCASTI64X4.
5-338 Vol. 2C
VPBROADCAST—Load Integer and Broadcast
INSTRUCTION SET REFERENCE, V-Z
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
Opcode/
Instruction
Op/
En
FVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
EVEX.NDS.128.66.0F3A.W0 3F /r ib
VPCMPB k1 {k2}, xmm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W0 3F /r ib
FVM
V/V
VPCMPB k1 {k2}, ymm2,
ymm3/m256, imm8
EVEX.NDS.512.66.0F3A.W0 3F /r ib
VPCMPB k1 {k2}, zmm2,
zmm3/m512, imm8
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
EVEX.NDS.128.66.0F3A.W0 3E /r ib
FVM
V/V
VPCMPUB k1 {k2}, xmm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W0 3E /r ib
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
VPCMPUB k1 {k2}, ymm2,
ymm3/m256, imm8
EVEX.NDS.512.66.0F3A.W0 3E /r ib
VPCMPUB k1 {k2}, zmm2,
zmm3/m512, imm8
Description
Compare packed signed byte values in xmm3/m128 and
xmm2 using bits 2:0 of imm8 as a comparison predicate
with writemask k2 and leave the result in mask register
k1.
Compare packed signed byte values in ymm3/m256 and
ymm2 using bits 2:0 of imm8 as a comparison predicate
with writemask k2 and leave the result in mask register
k1.
Compare packed signed byte values in zmm3/m512 and
zmm2 using bits 2:0 of imm8 as a comparison predicate
with writemask k2 and leave the result in mask register
k1.
Compare packed unsigned byte values in xmm3/m128
and xmm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in mask
register k1.
Compare packed unsigned byte values in ymm3/m256
and ymm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in mask
register k1.
Compare packed unsigned byte values in zmm3/m512
and zmm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in mask
register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVM
ModRM:reg (w)
vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed byte values in the second source operand and the first source operand and
returns the results of the comparison to the mask destination operand. The comparison predicate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in the two source operands.
The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPB performs a comparison between pairs of signed byte values.
VPCMPUB performs a comparison between pairs of unsigned byte values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask
register k1. Up to 64/32/16 comparisons are performed with results written to the destination operand under the
writemask k2.
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
Vol. 2C 5-339
INSTRUCTION SET REFERENCE, V-Z
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-19.
Table 5-19. Pseudo-Op and VPCMP* Implementation
:
Pseudo-Op
PCMPM Implementation
VPCMPEQ* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 0
VPCMPLT* reg1, reg2, reg3
VPCMP*reg1, reg2, reg3, 1
VPCMPLE* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 2
VPCMPNEQ* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 4
VPPCMPNLT* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 5
VPCMPNLE* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 6
Operation
CASE (COMPARISON PREDICATE) OF
0: OP EQ;
1: OP LT;
2: OP LE;
3: OP FALSE;
4: OP NEQ ;
5: OP NLT;
6: OP NLE;
7: OP TRUE;
ESAC;
VPCMPB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k2[j] OR *no writemask*
THEN
CMP SRC1[i+7:i] OP SRC2[i+7:i];
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
5-340 Vol. 2C
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
INSTRUCTION SET REFERENCE, V-Z
VPCMPUB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k2[j] OR *no writemask*
THEN
CMP SRC1[i+7:i] OP SRC2[i+7:i];
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPB __mmask64 _mm512_cmp_epi8_mask( __m512i a, __m512i b, int cmp);
VPCMPB __mmask64 _mm512_mask_cmp_epi8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPB __mmask32 _mm256_cmp_epi8_mask( __m256i a, __m256i b, int cmp);
VPCMPB __mmask32 _mm256_mask_cmp_epi8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPB __mmask16 _mm_cmp_epi8_mask( __m128i a, __m128i b, int cmp);
VPCMPB __mmask16 _mm_mask_cmp_epi8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
VPCMPB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m512i a, __m512i b);
VPCMPB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask64 m, __m512i a, __m512i b);
VPCMPB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m256i a, __m256i b);
VPCMPB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask32 m, __m256i a, __m256i b);
VPCMPB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m128i a, __m128i b);
VPCMPB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask16 m, __m128i a, __m128i b);
VPCMPUB __mmask64 _mm512_cmp_epu8_mask( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp_epu8_mask( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp_epu8_mask( __m128i a, __m128i b, int cmp);
VPCMPUB __mmask16 _mm_mask_cmp_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
VPCMPUB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m128i a, __m128i b, int cmp);
VPCMPUB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
Vol. 2C 5-341
INSTRUCTION SET REFERENCE, V-Z
VPCMPD/VPCMPUD—Compare Packed Integer Values into Mask
Opcode/
Instruction
Op/
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F3A.W0 1F /r ib
VPCMPD k1 {k2}, xmm2,
xmm3/m128/m32bcst, imm8
EVEX.NDS.256.66.0F3A.W0 1F /r ib
VPCMPD k1 {k2}, ymm2,
ymm3/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F3A.W0 1F /r ib
VPCMPD k1 {k2}, zmm2,
zmm3/m512/m32bcst, imm8
FV
V/V
AVX512F
EVEX.NDS.128.66.0F3A.W0 1E /r ib
VPCMPUD k1 {k2}, xmm2,
xmm3/m128/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F3A.W0 1E /r ib
VPCMPUD k1 {k2}, ymm2,
ymm3/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F3A.W0 1E /r ib
VPCMPUD k1 {k2}, zmm2,
zmm3/m512/m32bcst, imm8
FV
V/V
AVX512F
Description
Compare packed signed doubleword integer values in
xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed signed doubleword integer values in
ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed signed doubleword integer values in
zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8
as a comparison predicate. The comparison results are
written to the destination k1 under writemask k2.
Compare packed unsigned doubleword integer values in
xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed unsigned doubleword integer values in
ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed unsigned doubleword integer values in
zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8
as a comparison predicate. The comparison results are
written to the destination k1 under writemask k2.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
Performs a SIMD compare of the packed integer values in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source operands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPD/VPCMPUD performs a comparison between pairs of signed/unsigned doubleword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand (first operand) is a mask register k1. Up to 16/8/4 comparisons are
performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-19.
5-342 Vol. 2C
VPCMPD/VPCMPUD—Compare Packed Integer Values into Mask
INSTRUCTION SET REFERENCE, V-Z
Operation
CASE (COMPARISON PREDICATE) OF
0: OP EQ;
1: OP LT;
2: OP LE;
3: OP FALSE;
4: OP NEQ;
5: OP NLT;
6: OP NLE;
7: OP TRUE;
ESAC;
VPCMPD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+31:i] OP SRC2[31:0];
ELSE CMP SRC1[i+31:i] OP SRC2[i+31:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPCMPUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+31:i] OP SRC2[31:0];
ELSE CMP SRC1[i+31:i] OP SRC2[i+31:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPCMPD/VPCMPUD—Compare Packed Integer Values into Mask
Vol. 2C 5-343
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPD __mmask16 _mm512_cmp_epi32_mask( __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_mask_cmp_epi32_mask(__mmask16 k, __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m512i a, __m512i b);
VPCMPD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_cmp_epu32_mask( __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_mask_cmp_epu32_mask(__mmask16 k, __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPD __mmask8 _mm256_cmp_epi32_mask( __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_mask_cmp_epi32_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m256i a, __m256i b);
VPCMPD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPUD __mmask8 _mm256_cmp_epu32_mask( __m256i a, __m256i b, int imm);
VPCMPUD __mmask8 _mm256_mask_cmp_epu32_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPUD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m256i a, __m256i b);
VPCMPUD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPD __mmask8 _mm_cmp_epi32_mask( __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_mask_cmp_epi32_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m128i a, __m128i b);
VPCMPD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_cmp_epu32_mask( __m128i a, __m128i b, int imm);
VPCMPUD __mmask8 _mm_mask_cmp_epu32_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPUD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.
5-344 Vol. 2C
VPCMPD/VPCMPUD—Compare Packed Integer Values into Mask
INSTRUCTION SET REFERENCE, V-Z
VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask
Opcode/
Instruction
Op/
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F3A.W1 1F /r ib
VPCMPQ k1 {k2}, xmm2,
xmm3/m128/m64bcst, imm8
EVEX.NDS.256.66.0F3A.W1 1F /r ib
VPCMPQ k1 {k2}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F3A.W1 1F /r ib
VPCMPQ k1 {k2}, zmm2,
zmm3/m512/m64bcst, imm8
FV
V/V
AVX512F
EVEX.NDS.128.66.0F3A.W1 1E /r ib
VPCMPUQ k1 {k2}, xmm2,
xmm3/m128/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F3A.W1 1E /r ib
VPCMPUQ k1 {k2}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F3A.W1 1E /r ib
VPCMPUQ k1 {k2}, zmm2,
zmm3/m512/m64bcst, imm8
FV
V/V
AVX512F
Description
Compare packed signed quadword integer values in
xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed signed quadword integer values in
ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed signed quadword integer values in
zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed unsigned quadword integer values in
xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed unsigned quadword integer values in
ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Compare packed unsigned quadword integer values in
zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
Performs a SIMD compare of the packed integer values in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source operands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPQ/VPCMPUQ performs a comparison between pairs of signed/unsigned quadword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand (first operand) is a mask register k1. Up to 8/4/2 comparisons are
performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-19.
VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask
Vol. 2C 5-345
INSTRUCTION SET REFERENCE, V-Z
Operation
CASE (COMPARISON PREDICATE) OF
0: OP EQ;
1: OP LT;
2: OP LE;
3: OP FALSE;
4: OP NEQ;
5: OP NLT;
6: OP NLE;
7: OP TRUE;
ESAC;
VPCMPQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+63:i] OP SRC2[63:0];
ELSE CMP SRC1[i+63:i] OP SRC2[i+63:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPCMPUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP SRC1[i+63:i] OP SRC2[63:0];
ELSE CMP SRC1[i+63:i] OP SRC2[i+63:i];
FI;
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
5-346 Vol. 2C
VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPQ __mmask8 _mm512_cmp_epi64_mask( __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_mask_cmp_epi64_mask(__mmask8 k, __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m512i a, __m512i b);
VPCMPQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_cmp_epu64_mask( __m512i a, __m512i b, int imm);
VPCMPUQ __mmask8 _mm512_mask_cmp_epu64_mask(__mmask8 k, __m512i a, __m512i b, int imm);
VPCMPUQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPQ __mmask8 _mm256_cmp_epi64_mask( __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_mask_cmp_epi64_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m256i a, __m256i b);
VPCMPQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_cmp_epu64_mask( __m256i a, __m256i b, int imm);
VPCMPUQ __mmask8 _mm256_mask_cmp_epu64_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPUQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPQ __mmask8 _mm_cmp_epi64_mask( __m128i a, __m128i b, int imm);
VPCMPQ __mmask8 _mm_mask_cmp_epi64_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m128i a, __m128i b);
VPCMPQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_cmp_epu64_mask( __m128i a, __m128i b, int imm);
VPCMPUQ __mmask8 _mm_mask_cmp_epu64_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPUQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.
VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask
Vol. 2C 5-347
INSTRUCTION SET REFERENCE, V-Z
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
Opcode/
Instruction
Op/
En
FVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
EVEX.NDS.128.66.0F3A.W1 3F /r ib
VPCMPW k1 {k2}, xmm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W1 3F /r ib
FVM
V/V
VPCMPW k1 {k2}, ymm2,
ymm3/m256, imm8
EVEX.NDS.512.66.0F3A.W1 3F /r ib
VPCMPW k1 {k2}, zmm2,
zmm3/m512, imm8
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
EVEX.NDS.128.66.0F3A.W1 3E /r ib
FVM
V/V
VPCMPUW k1 {k2}, xmm2,
xmm3/m128, imm8
EVEX.NDS.256.66.0F3A.W1 3E /r ib
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
VPCMPUW k1 {k2}, ymm2,
ymm3/m256, imm8
VPCMPUW k1 {k2}, zmm2,
zmm3/m512, imm8
Description
Compare packed signed word integers in xmm3/m128
and xmm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in
mask register k1.
Compare packed signed word integers in ymm3/m256
and ymm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in
mask register k1.
Compare packed signed word integers in zmm3/m512
and zmm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in
mask register k1.
Compare packed unsigned word integers in xmm3/m128
and xmm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in
mask register k1.
Compare packed unsigned word integers in ymm3/m256
and ymm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in
mask register k1.
Compare packed unsigned word integers in zmm3/m512
and zmm2 using bits 2:0 of imm8 as a comparison
predicate with writemask k2 and leave the result in
mask register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVM
ModRM:reg (w)
vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a SIMD compare of the packed integer word in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source operands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPW performs a comparison between pairs of signed word values.
VPCMPUW performs a comparison between pairs of unsigned word values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask
register k1. Up to 32/16/8 comparisons are performed with results written to the destination operand under the
writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-19.
5-348 Vol. 2C
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
INSTRUCTION SET REFERENCE, V-Z
Operation
CASE (COMPARISON PREDICATE) OF
0: OP EQ;
1: OP LT;
2: OP LE;
3: OP FALSE;
4: OP NEQ ;
5: OP NLT;
6: OP NLE;
7: OP TRUE;
ESAC;
VPCMPW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k2[j] OR *no writemask*
THEN
ICMP SRC1[i+15:i] OP SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPCMPUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k2[j] OR *no writemask*
THEN
CMP SRC1[i+15:i] OP SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] 1;
ELSE DEST[j] 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
Vol. 2C 5-349
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPW __mmask32 _mm512_cmp_epi16_mask( __m512i a, __m512i b, int cmp);
VPCMPW __mmask32 _mm512_mask_cmp_epi16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPW __mmask16 _mm256_cmp_epi16_mask( __m256i a, __m256i b, int cmp);
VPCMPW __mmask16 _mm256_mask_cmp_epi16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPW __mmask8 _mm_cmp_epi16_mask( __m128i a, __m128i b, int cmp);
VPCMPW __mmask8 _mm_mask_cmp_epi16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
VPCMPW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m512i a, __m512i b);
VPCMPW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask32 m, __m512i a, __m512i b);
VPCMPW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m256i a, __m256i b);
VPCMPW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask16 m, __m256i a, __m256i b);
VPCMPW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m128i a, __m128i b);
VPCMPW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask8 m, __m128i a, __m128i b);
VPCMPUW __mmask32 _mm512_cmp_epu16_mask( __m512i a, __m512i b, int cmp);
VPCMPUW __mmask32 _mm512_mask_cmp_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPUW __mmask16 _mm256_cmp_epu16_mask( __m256i a, __m256i b, int cmp);
VPCMPUW __mmask16 _mm256_mask_cmp_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPUW __mmask8 _mm_cmp_epu16_mask( __m128i a, __m128i b, int cmp);
VPCMPUW __mmask8 _mm_mask_cmp_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
VPCMPUW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m512i a, __m512i b, int cmp);
VPCMPUW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPUW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m256i a, __m256i b, int cmp);
VPCMPUW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPUW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m128i a, __m128i b, int cmp);
VPCMPUW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
5-350 Vol. 2C
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
INSTRUCTION SET REFERENCE, V-Z
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values into Dense Memory/Register
Opcode/
Instruction
Op/
En
EVEX.128.66.0F38.W0 8B /r
VPCOMPRESSD xmm1/m128 {k1}{z}, xmm2
EVEX.256.66.0F38.W0 8B /r
VPCOMPRESSD ymm1/m256 {k1}{z}, ymm2
EVEX.512.66.0F38.W0 8B /r
VPCOMPRESSD zmm1/m512 {k1}{z}, zmm2
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Compress packed doubleword integer values from
xmm2 to xmm1/m128 using controlmask k1.
Compress packed doubleword integer values from
ymm2 to ymm1/m256 using controlmask k1.
Compress packed doubleword integer values from
zmm2 to zmm1/m512 using controlmask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Compress (store) up to 16/8/4 doubleword integer values from the source operand (second operand) to the destination operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 16 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPCOMPRESSD (EVEX encoded versions) store form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE 32
k0
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] SRC[i+31:i]
k k + SIZE
FI;
ENDFOR;
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values into Dense Memory/Register
Vol. 2C 5-351
INSTRUCTION SET REFERENCE, V-Z
VPCOMPRESSD (EVEX encoded versions) reg-reg form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE 32
k0
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] SRC[i+31:i]
k k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] ← 0
FI
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSD __m512i _mm512_mask_compress_epi32(__m512i s, __mmask16 c, __m512i a);
VPCOMPRESSD __m512i _mm512_maskz_compress_epi32( __mmask16 c, __m512i a);
VPCOMPRESSD void _mm512_mask_compressstoreu_epi32(void * a, __mmask16 c, __m512i s);
VPCOMPRESSD __m256i _mm256_mask_compress_epi32(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSD __m256i _mm256_maskz_compress_epi32( __mmask8 c, __m256i a);
VPCOMPRESSD void _mm256_mask_compressstoreu_epi32(void * a, __mmask8 c, __m256i s);
VPCOMPRESSD __m128i _mm_mask_compress_epi32(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSD __m128i _mm_maskz_compress_epi32( __mmask8 c, __m128i a);
VPCOMPRESSD void _mm_mask_compressstoreu_epi32(void * a, __mmask8 c, __m128i s);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
5-352 Vol. 2C
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values into Dense Memory/Register
INSTRUCTION SET REFERENCE, V-Z
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values into Dense Memory/Register
Opcode/
Instruction
Op/
En
EVEX.128.66.0F38.W1 8B /r
VPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2
EVEX.256.66.0F38.W1 8B /r
VPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2
EVEX.512.66.0F38.W1 8B /r
VPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Compress packed quadword integer values from
xmm2 to xmm1/m128 using controlmask k1.
Compress packed quadword integer values from
ymm2 to ymm1/m256 using controlmask k1.
Compress packed quadword integer values from
zmm2 to zmm1/m512 using controlmask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Compress (stores) up to 8/4/2 quadword integer values from the source operand (second operand) to the destination operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPCOMPRESSQ (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE 64
k0
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] SRC[i+63:i]
k k + SIZE
FI;
ENFOR
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values into Dense Memory/Register
Vol. 2C 5-353
INSTRUCTION SET REFERENCE, V-Z
VPCOMPRESSQ (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE 64
k0
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] SRC[i+63:i]
k k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] ← 0
FI
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSQ __m512i _mm512_mask_compress_epi64(__m512i s, __mmask8 c, __m512i a);
VPCOMPRESSQ __m512i _mm512_maskz_compress_epi64( __mmask8 c, __m512i a);
VPCOMPRESSQ void _mm512_mask_compressstoreu_epi64(void * a, __mmask8 c, __m512i s);
VPCOMPRESSQ __m256i _mm256_mask_compress_epi64(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSQ __m256i _mm256_maskz_compress_epi64( __mmask8 c, __m256i a);
VPCOMPRESSQ void _mm256_mask_compressstoreu_epi64(void * a, __mmask8 c, __m256i s);
VPCOMPRESSQ __m128i _mm_mask_compress_epi64(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSQ __m128i _mm_maskz_compress_epi64( __mmask8 c, __m128i a);
VPCOMPRESSQ void _mm_mask_compressstoreu_epi64(void * a, __mmask8 c, __m128i s);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
5-354 Vol. 2C
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values into Dense Memory/Register
INSTRUCTION SET REFERENCE, V-Z
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense
Memory/ Register
Opcode/
Instruction
Op/
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512CD
EVEX.128.66.0F38.W0 C4 /r
VPCONFLICTD xmm1 {k1}{z},
xmm2/m128/m32bcst
Description
Detect duplicate double-word values in
xmm2/m128/m32bcst using writemask k1.
EVEX.256.66.0F38.W0 C4 /r
VPCONFLICTD ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512CD
Detect duplicate double-word values in
ymm2/m256/m32bcst using writemask k1.
EVEX.512.66.0F38.W0 C4 /r
VPCONFLICTD zmm1 {k1}{z},
zmm2/m512/m32bcst
FV
V/V
AVX512CD
Detect duplicate double-word values in
zmm2/m512/m32bcst using writemask k1.
EVEX.128.66.0F38.W1 C4 /r
VPCONFLICTQ xmm1 {k1}{z},
xmm2/m128/m64bcst
FV
V/V
AVX512VL
AVX512CD
Detect duplicate quad-word values in
xmm2/m128/m64bcst using writemask k1.
EVEX.256.66.0F38.W1 C4 /r
VPCONFLICTQ ymm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512CD
Detect duplicate quad-word values in
ymm2/m256/m64bcst using writemask k1.
EVEX.512.66.0F38.W1 C4 /r
VPCONFLICTQ zmm1 {k1}{z},
zmm2/m512/m64bcst
FV
V/V
AVX512CD
Detect duplicate quad-word values in
zmm2/m512/m64bcst using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Test each dword/qword element of the source operand (the second operand) for equality with all other elements in
the source operand closer to the least significant element. Each element’s comparison results form a bit vector,
which is then zero extended and written to the destination according to the writemask.
EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated
using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated
using writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated
using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register
Vol. 2C 5-355
INSTRUCTION SET REFERENCE, V-Z
Operation
VPCONFLICTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j*32
IF MaskBit(j) OR *no writemask*THEN
FOR k 0 TO j-1
m k*32
IF ((SRC[i+31:i] = SRC[m+31:m])) THEN
DEST[i+k] 1
ELSE
DEST[i+k] 0
FI
ENDFOR
DEST[i+31:i+j] 0
ELSE
IF *merging-masking* THEN
*DEST[i+31:i] remains unchanged*
ELSE
DEST[i+31:i] 0
FI
FI
ENDFOR
DEST[MAX_VL-1:VL] ← 0
VPCONFLICTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j*64
IF MaskBit(j) OR *no writemask*THEN
FOR k 0 TO j-1
m k*64
IF ((SRC[i+63:i] = SRC[m+63:m])) THEN
DEST[i+k] 1
ELSE
DEST[i+k] 0
FI
ENDFOR
DEST[i+63:i+j] 0
ELSE
IF *merging-masking* THEN
*DEST[i+63:i] remains unchanged*
ELSE
DEST[i+63:i] 0
FI
FI
ENDFOR
DEST[MAX_VL-1:VL] 0
5-356 Vol. 2C
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);
VPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);
VPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);
VPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);
VPCONFLICTQ __m512i _mm512_mask_conflict_epi64(__m512i s, __mmask8 m, __m512i a);
VPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);
VPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);
VPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);
VPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);
VPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);
VPCONFLICTQ __m256i _mm256_mask_conflict_epi64(__m256i s, __mmask8 m, __m256i a);
VPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);
VPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);
VPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);
VPCONFLICTQ __m128i _mm_mask_conflict_epi64(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_maskz_conflict_epi64(__mmask8 m, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register
Vol. 2C 5-357
INSTRUCTION SET REFERENCE, V-Z
VPERM2F128 — Permute Floating-Point Values
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
VEX.NDS.256.66.0F3A.W0 06 /r ib
VPERM2F128 ymm1, ymm2, ymm3/m256, imm8
RVMI V/V
CPUID
Feature
Flag
Description
AVX
Permute 128-bit floating-point fields in ymm2
and ymm3/mem using controls from imm8 and
store result in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Permute 128 bit floating-point-containing fields from the first source operand (second operand) and second source
operand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first
operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit
memory location, and the destination operand is a YMM register.
SRC2
Y1
Y0
SRC1
X1
X0
DEST
X0, X1, Y0, or Y1
X0, X1, Y0, or Y1
Figure 5-21. VPERM2F128 Operation
Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second
destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.
5-358 Vol. 2C
VPERM2F128 — Permute Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Operation
VPERM2F128
CASE IMM8[1:0] of
0: DEST[127:0] SRC1[127:0]
1: DEST[127:0] SRC1[255:128]
2: DEST[127:0] SRC2[127:0]
3: DEST[127:0] SRC2[255:128]
ESAC
CASE IMM8[5:4] of
0: DEST[255:128] SRC1[127:0]
1: DEST[255:128] SRC1[255:128]
2: DEST[255:128] SRC2[127:0]
3: DEST[255:128] SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] 0
FI
IF (imm8[7])
DEST[VLMAX-1:128] 0
FI
Intel C/C++ Compiler Intrinsic Equivalent
VPERM2F128:
__m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)
VPERM2F128:
__m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)
VPERM2F128:
__m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 6; additionally
#UD
If VEX.L = 0
If VEX.W = 1.
VPERM2F128 — Permute Floating-Point Values
Vol. 2C 5-359
INSTRUCTION SET REFERENCE, V-Z
VPERM2I128 — Permute Integer Values
Opcode/
Instruction
Op/
En
VEX.NDS.256.66.0F3A.W0 46 /r ib
VPERM2I128 ymm1, ymm2, ymm3/m256, imm8
RVMI
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
AVX2
Description
Permute 128-bit integer data in ymm2 and
ymm3/mem using controls from imm8 and
store result in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
Description
Permute 128 bit integer data from the first source operand (second operand) and second source operand (third
operand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first
source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and
the destination operand is a YMM register.
SRC2
Y1
Y0
SRC1
X1
X0
DEST
X0, X1, Y0, or Y1
X0, X1, Y0, or Y1
Figure 5-22. VPERM2I128 Operation
Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second
destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.
5-360 Vol. 2C
VPERM2I128 — Permute Integer Values
INSTRUCTION SET REFERENCE, V-Z
Operation
VPERM2I128
CASE IMM8[1:0] of
0: DEST[127:0] SRC1[127:0]
1: DEST[127:0] SRC1[255:128]
2: DEST[127:0] SRC2[127:0]
3: DEST[127:0] SRC2[255:128]
ESAC
CASE IMM8[5:4] of
0: DEST[255:128] SRC1[127:0]
1: DEST[255:128] SRC1[255:128]
2: DEST[255:128] SRC2[127:0]
3: DEST[255:128] SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] 0
FI
IF (imm8[7])
DEST[255:128] 0
FI
Intel C/C++ Compiler Intrinsic Equivalent
VPERM2I128: __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, int control)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 6; additionally
#UD
If VEX.L = 0,
If VEX.W = 1.
VPERM2I128 — Permute Integer Values
Vol. 2C 5-361
INSTRUCTION SET REFERENCE, V-Z
VPERMD/VPERMW—Permute Packed Doublewords/Words Elements
Opcode/
Instruction
Op /
En
VEX.NDS.256.66.0F38.W0 36 /r
VPERMD ymm1, ymm2, ymm3/m256
EVEX.NDS.256.66.0F38.W0 36 /r
VPERMD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 36 /r
VPERMD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 8D /r
VPERMW xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.W1 8D /r
VPERMW ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.W1 8D /r
VPERMW zmm1 {k1}{z}, zmm2,
zmm3/m512
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
Permute word integers in ymm3/m256 using indexes
in ymm2 and store the result in ymm1 using writemask
k1.
FVM
V/V
AVX512BW
Permute word integers in zmm3/m512 using indexes
in zmm2 and store the result in zmm1 using writemask
k1.
Description
Permute doublewords in ymm3/m256 using indices in
ymm2 and store the result in ymm1.
Permute doublewords in ymm3/m256/m32bcst using
indexes in ymm2 and store the result in ymm1 using
writemask k1.
Permute doublewords in zmm3/m512/m32bcst using
indices in zmm2 and store the result in zmm1 using
writemask k1.
Permute word integers in xmm3/m128 using indexes
in xmm2 and store the result in xmm1 using writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
Description
Copies doublewords (or words) from the second source operand (the third operand) to the destination operand (the
first operand) according to the indices in the first source operand (the second operand). Note that this instruction
permits a doubleword (word) in the source operand to be copied to more than one location in the destination
operand.
VEX.256 encoded VPERMD: The first and second operands are YMM registers, the third operand can be a YMM
register or memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded VPERMD: The first and second operands are ZMM/YMM registers, the third operand can be a
ZMM/YMM register, a 512/256-bit memory location or a 512/256-bit vector broadcasted from a 32-bit memory
location. The elements in the destination are updated using the writemask k1.
VPERMW: first and second operands are ZMM/YMM/XMM registers, the third operand can be a ZMM/YMM/XMM
register, or a 512/256/128-bit memory location. The destination is updated using the writemask k1.
EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
5-362 Vol. 2C
VPERMD/VPERMW—Permute Packed Doublewords/Words Elements
INSTRUCTION SET REFERENCE, V-Z
Operation
VPERMD (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
IF VL = 256 THEN n 2; FI;
IF VL = 512 THEN n 3; FI;
FOR j 0 TO KL-1
i j * 32
id 32*SRC1[i+n:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SRC2[31:0];
ELSE DEST[i+31:i] SRC2[id+31:id];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMD (VEX.256 encoded version)
DEST[31:0] (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
DEST[MAX_VL-1:256] 0
VPERMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128 THEN n 2; FI;
IF VL = 256 THEN n 3; FI;
IF VL = 512 THEN n 4; FI;
FOR j 0 TO KL-1
i j * 16
id 16*SRC1[i+n:i]
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SRC2[id+15:id]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMD/VPERMW—Permute Packed Doublewords/Words Elements
Vol. 2C 5-363
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPERMD __m512i _mm512_permutexvar_epi32( __m512i idx, __m512i a);
VPERMD __m512i _mm512_mask_permutexvar_epi32(__m512i s, __mmask16 k, __m512i idx, __m512i a);
VPERMD __m512i _mm512_maskz_permutexvar_epi32( __mmask16 k, __m512i idx, __m512i a);
VPERMD __m256i _mm256_permutexvar_epi32( __m256i idx, __m256i a);
VPERMD __m256i _mm256_mask_permutexvar_epi32(__m256i s, __mmask8 k, __m256i idx, __m256i a);
VPERMD __m256i _mm256_maskz_permutexvar_epi32( __mmask8 k, __m256i idx, __m256i a);
VPERMW __m512i _mm512_permutexvar_epi16( __m512i idx, __m512i a);
VPERMW __m512i _mm512_mask_permutexvar_epi16(__m512i s, __mmask32 k, __m512i idx, __m512i a);
VPERMW __m512i _mm512_maskz_permutexvar_epi16( __mmask32 k, __m512i idx, __m512i a);
VPERMW __m256i _mm256_permutexvar_epi16( __m256i idx, __m256i a);
VPERMW __m256i _mm256_mask_permutexvar_epi16(__m256i s, __mmask16 k, __m256i idx, __m256i a);
VPERMW __m256i _mm256_maskz_permutexvar_epi16( __mmask16 k, __m256i idx, __m256i a);
VPERMW __m128i _mm_permutexvar_epi16( __m128i idx, __m128i a);
VPERMW __m128i _mm_mask_permutexvar_epi16(__m128i s, __mmask8 k, __m128i idx, __m128i a);
VPERMW __m128i _mm_maskz_permutexvar_epi16( __mmask8 k, __m128i idx, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPERMD, see Exceptions Type E4NF.
EVEX-encoded VPERMW, see Exceptions Type E4NF.nb.
#UD
If VEX.L = 0.
If EVEX.L’L = 0 for VPERMD.
5-364 Vol. 2C
VPERMD/VPERMW—Permute Packed Doublewords/Words Elements
INSTRUCTION SET REFERENCE, V-Z
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
Opcode/
Instruction
Op /
En
FVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
EVEX.DDS.128.66.0F38.W1 75 /r
VPERMI2W xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.DDS.256.66.0F38.W1 75 /r
VPERMI2W ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.DDS.512.66.0F38.W1 75 /r
VPERMI2W zmm1 {k1}{z}, zmm2,
zmm3/m512
EVEX.DDS.128.66.0F38.W0 76 /r
VPERMI2D xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W0 76 /r
VPERMI2D ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.512.66.0F38.W0 76 /r
VPERMI2D zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
EVEX.DDS.128.66.0F38.W1 76 /r
VPERMI2Q xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W1 76 /r
VPERMI2Q ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.512.66.0F38.W1 76 /r
VPERMI2Q zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
EVEX.DDS.128.66.0F38.W0 77 /r
VPERMI2PS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F38.W0 77 /r
VPERMI2PS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.512.66.0F38.W0 77 /r
VPERMI2PS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
Description
Permute word integers from two tables in
xmm3/m128 and xmm2 using indexes in xmm1 and
store the result in xmm1 using writemask k1.
Permute word integers from two tables in
ymm3/m256 and ymm2 using indexes in ymm1 and
store the result in ymm1 using writemask k1.
Permute word integers from two tables in
zmm3/m512 and zmm2 using indexes in zmm1 and
store the result in zmm1 using writemask k1.
Permute double-words from two tables in
xmm3/m128/m32bcst and xmm2 using indexes in
xmm1 and store the result in xmm1 using writemask
k1.
Permute double-words from two tables in
ymm3/m256/m32bcst and ymm2 using indexes in
ymm1 and store the result in ymm1 using writemask
k1.
Permute double-words from two tables in
zmm3/m512/m32bcst and zmm2 using indices in
zmm1 and store the result in zmm1 using writemask
k1.
Permute quad-words from two tables in
xmm3/m128/m64bcst and xmm2 using indexes in
xmm1 and store the result in xmm1 using writemask
k1.
Permute quad-words from two tables in
ymm3/m256/m64bcst and ymm2 using indexes in
ymm1 and store the result in ymm1 using writemask
k1.
Permute quad-words from two tables in
zmm3/m512/m64bcst and zmm2 using indices in
zmm1 and store the result in zmm1 using writemask
k1.
Permute single-precision FP values from two tables in
xmm3/m128/m32bcst and xmm2 using indexes in
xmm1 and store the result in xmm1 using writemask
k1.
Permute single-precision FP values from two tables in
ymm3/m256/m32bcst and ymm2 using indexes in
ymm1 and store the result in ymm1 using writemask
k1.
Permute single-precision FP values from two tables in
zmm3/m512/m32bcst and zmm2 using indices in
zmm1 and store the result in zmm1 using writemask
k1.
Vol. 2C 5-365
INSTRUCTION SET REFERENCE, V-Z
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.DDS.128.66.0F38.W1 77 /r
VPERMI2PD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.DDS.256.66.0F38.W1 77 /r
VPERMI2PD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.512.66.0F38.W1 77 /r
VPERMI2PD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Description
Permute double-precision FP values from two tables in
xmm3/m128/m64bcst and xmm2 using indexes in
xmm1 and store the result in xmm1 using writemask
k1.
Permute double-precision FP values from two tables in
ymm3/m256/m64bcst and ymm2 using indexes in
ymm1 and store the result in ymm1 using writemask
k1.
Permute double-precision FP values from two tables in
zmm3/m512/m64bcst and zmm2 using indices in
zmm1 and store the result in zmm1 using writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVM
ModRM:reg (r,w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Permutes 16-bit/32-bit/64-bit values in the second operand (the first source operand) and the third operand (the
second source operand) using indices in the first operand to select elements from the second and third operands.
The selected elements are written to the destination operand (the first operand) according to the writemask k1.
The first and second operands are ZMM/YMM/XMM registers. The first operand contains input indices to select
elements from the two input tables in the 2nd and 3rd operands. The first operand is also the destination of the
result.
D/Q/PS/PD element versions: The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. Broadcast from the
low 32/64-bit memory location is performed if EVEX.b and the id bit for table selection are set (selecting table_2).
Dword/PS versions: The id bit for table selection is bit 4/3/2, depending on VL=512, 256, 128. Bits
[3:0]/[2:0]/[1:0] of each element in the input index vector select an element within the two source operands, If
the id bit is 0, table_1 (the first source) is selected; otherwise the second source operand is selected.
Qword/PD versions: The id bit for table selection is bit 3/2/1, and bits [2:0]/[1:0] /bit 0 selects element within each
input table.
Word element versions: The second source operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit
memory location. The id bit for table selection is bit 5/4/3, and bits [4:0]/[3:0]/[2:0] selects element within each
input table.
Note that these instructions permit a 16-bit/32-bit/64-bit value in the source operands to be copied to more than
one location in the destination operand. Note also that in this case, the same table can be reused for example for a
second iteration, while the index elements are overwritten.
Bits (MAX_VL-1:256/128) of the destination are zeroed for VL=256,128.
5-366 Vol. 2C
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
INSTRUCTION SET REFERENCE, V-Z
Operation
VPERMI2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
id 2
FI;
IF VL = 256
id 3
FI;
IF VL = 512
id 4
FI;
TMP_DEST DEST
FOR j 0 TO KL-1
i j * 16
off 16*TMP_DEST[i+id:i]
IF k1[j] OR *no writemask*
THEN
DEST[i+15:i]=TMP_DEST[i+id+1] ? SRC2[off+15:off]
: SRC1[off+15:off]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMI2D/VPERMI2PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
id 1
FI;
IF VL = 256
id 2
FI;
IF VL = 512
id 3
FI;
TMP_DEST DEST
FOR j 0 TO KL-1
i j * 32
off 32*TMP_DEST[i+id:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] TMP_DEST[i+id+1] ? SRC2[31:0]
: SRC1[off+31:off]
ELSE
DEST[i+31:i] TMP_DEST[i+id+1] ? SRC2[off+31:off]
: SRC1[off+31:off]
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
Vol. 2C 5-367
INSTRUCTION SET REFERENCE, V-Z
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMI2Q/VPERMI2PD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8 512)
IF VL = 128
id 0
FI;
IF VL = 256
id 1
FI;
IF VL = 512
id 2
FI;
TMP_DEST DEST
FOR j 0 TO KL-1
i j * 64
off 64*TMP_DEST[i+id:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] TMP_DEST[i+id+1] ? SRC2[63:0]
: SRC1[off+63:off]
ELSE
DEST[i+63:i] TMP_DEST[i+id+1] ? SRC2[off+63:off]
: SRC1[off+63:off]
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-368 Vol. 2C
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPERMI2D __m512i _mm512_permutex2var_epi32(__m512i a, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask_permutex2var_epi32(__m512i a, __mmask16 k, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask2_permutex2var_epi32(__m512i a, __m512i idx, __mmask16 k, __m512i b);
VPERMI2D __m512i _mm512_maskz_permutex2var_epi32(__mmask16 k, __m512i a, __m512i idx, __m512i b);
VPERMI __m256i _mm256_permutex2var_epi32(__m256i a, __m256i idx, __m256i b);
VPERMI2D __m256i _mm256_mask_permutex2var_epi32(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMI2D __m256i _mm256_mask2_permutex2var_epi32(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2D __m256i _mm256_maskz_permutex2var_epi32(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMI2D __m128i _mm_permutex2var_epi32(__m128i a, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask_permutex2var_epi32(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask2_permutex2var_epi32(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2D __m128i _mm_maskz_permutex2var_epi32(__mmask8 k, __m128i a, __m128i idx, __m128i b);
VPERMI2PD __m512d _mm512_permutex2var_pd(__m512d a, __m512i idx, __m512d b);
VPERMI2PD __m512d _mm512_mask_permutex2var_pd(__m512d a, __mmask8 k, __m512i idx, __m512d b);
VPERMI2PD __m512d _mm512_mask2_permutex2var_pd(__m512d a, __m512i idx, __mmask8 k, __m512d b);
VPERMI2PD __m512d _mm512_maskz_permutex2var_pd(__mmask8 k, __m512d a, __m512i idx, __m512d b);
VPERMI2PD __m256d _mm256_permutex2var_pd(__m256d a, __m256i idx, __m256d b);
VPERMI2PD __m256d _mm256_mask_permutex2var_pd(__m256d a, __mmask8 k, __m256i idx, __m256d b);
VPERMI2PD __m256d _mm256_mask2_permutex2var_pd(__m256d a, __m256i idx, __mmask8 k, __m256d b);
VPERMI2PD __m256d _mm256_maskz_permutex2var_pd(__mmask8 k, __m256d a, __m256i idx, __m256d b);
VPERMI2PD __m128d _mm_permutex2var_pd(__m128d a, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask_permutex2var_pd(__m128d a, __mmask8 k, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask2_permutex2var_pd(__m128d a, __m128i idx, __mmask8 k, __m128d b);
VPERMI2PD __m128d _mm_maskz_permutex2var_pd(__mmask8 k, __m128d a, __m128i idx, __m128d b);
VPERMI2PS __m512 _mm512_permutex2var_ps(__m512 a, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask_permutex2var_ps(__m512 a, __mmask16 k, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask2_permutex2var_ps(__m512 a, __m512i idx, __mmask16 k, __m512 b);
VPERMI2PS __m512 _mm512_maskz_permutex2var_ps(__mmask16 k, __m512 a, __m512i idx, __m512 b);
VPERMI2PS __m256 _mm256_permutex2var_ps(__m256 a, __m256i idx, __m256 b);
VPERMI2PS __m256 _mm256_mask_permutex2var_ps(__m256 a, __mmask8 k, __m256i idx, __m256 b);
VPERMI2PS __m256 _mm256_mask2_permutex2var_ps(__m256 a, __m256i idx, __mmask8 k, __m256 b);
VPERMI2PS __m256 _mm256_maskz_permutex2var_ps(__mmask8 k, __m256 a, __m256i idx, __m256 b);
VPERMI2PS __m128 _mm_permutex2var_ps(__m128 a, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask_permutex2var_ps(__m128 a, __mmask8 k, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask2_permutex2var_ps(__m128 a, __m128i idx, __mmask8 k, __m128 b);
VPERMI2PS __m128 _mm_maskz_permutex2var_ps(__mmask8 k, __m128 a, __m128i idx, __m128 b);
VPERMI2Q __m512i _mm512_permutex2var_epi64(__m512i a, __m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask_permutex2var_epi64(__m512i a, __mmask8 k, __m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask2_permutex2var_epi64(__m512i a, __m512i idx, __mmask8 k, __m512i b);
VPERMI2Q __m512i _mm512_maskz_permutex2var_epi64(__mmask8 k, __m512i a, __m512i idx, __m512i b);
VPERMI2Q __m256i _mm256_permutex2var_epi64(__m256i a, __m256i idx, __m256i b);
VPERMI2Q __m256i _mm256_mask_permutex2var_epi64(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMI2Q __m256i _mm256_mask2_permutex2var_epi64(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2Q __m256i _mm256_maskz_permutex2var_epi64(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMI2Q __m128i _mm_permutex2var_epi64(__m128i a, __m128i idx, __m128i b);
VPERMI2Q __m128i _mm_mask_permutex2var_epi64(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2Q __m128i _mm_mask2_permutex2var_epi64(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2Q __m128i _mm_maskz_permutex2var_epi64(__mmask8 k, __m128i a, __m128i idx, __m128i b);
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
Vol. 2C 5-369
INSTRUCTION SET REFERENCE, V-Z
VPERMI2W __m512i _mm512_permutex2var_epi16(__m512i a, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask_permutex2var_epi16(__m512i a, __mmask32 k, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask2_permutex2var_epi16(__m512i a, __m512i idx, __mmask32 k, __m512i b);
VPERMI2W __m512i _mm512_maskz_permutex2var_epi16(__mmask32 k, __m512i a, __m512i idx, __m512i b);
VPERMI2W __m256i _mm256_permutex2var_epi16(__m256i a, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask_permutex2var_epi16(__m256i a, __mmask16 k, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask2_permutex2var_epi16(__m256i a, __m256i idx, __mmask16 k, __m256i b);
VPERMI2W __m256i _mm256_maskz_permutex2var_epi16(__mmask16 k, __m256i a, __m256i idx, __m256i b);
VPERMI2W __m128i _mm_permutex2var_epi16(__m128i a, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask_permutex2var_epi16(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask2_permutex2var_epi16(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2W __m128i _mm_maskz_permutex2var_epi16(__mmask8 k, __m128i a, __m128i idx, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VPERMI2D/Q/PS/PD: See Exceptions Type E4NF.
VPERMI2W: See Exceptions Type E4NF.nb.
5-370 Vol. 2C
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
INSTRUCTION SET REFERENCE, V-Z
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values
Opcode/
Instruction
Op / En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX
VEX.NDS.128.66.0F38.W0 0D /r
VPERMILPD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F38.W0 0D /r
VPERMILPD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX
EVEX.NDS.128.66.0F38.W1 0D /r
VPERMILPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 0D /r
VPERMILPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 0D /r
VPERMILPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
VEX.128.66.0F3A.W0 05 /r ib
VPERMILPD xmm1, xmm2/m128, imm8
VEX.256.66.0F3A.W0 05 /r ib
VPERMILPD ymm1, ymm2/m256, imm8
EVEX.128.66.0F3A.W1 05 /r ib
VPERMILPD xmm1 {k1}{z},
xmm2/m128/m64bcst, imm8
EVEX.256.66.0F3A.W1 05 /r ib
VPERMILPD ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
EVEX.512.66.0F3A.W1 05 /r ib
VPERMILPD zmm1 {k1}{z},
zmm2/m512/m64bcst, imm8
FV-RVM
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512F
RM
V/V
AVX
RM
V/V
AVX
FV-RM
V/V
AVX512VL
AVX512F
FV-RM
V/V
AVX512VL
AVX512F
FV-RM
V/V
AVX512F
Description
Permute double-precision floating-point values in
xmm2 using controls from xmm3/m128 and store
result in xmm1.
Permute double-precision floating-point values in
ymm2 using controls from ymm3/m256 and store
result in ymm1.
Permute double-precision floating-point values in
xmm2 using control from xmm3/m128/m64bcst
and store the result in xmm1 using writemask k1.
Permute double-precision floating-point values in
ymm2 using control from ymm3/m256/m64bcst
and store the result in ymm1 using writemask k1.
Permute double-precision floating-point values in
zmm2 using control from zmm3/m512/m64bcst
and store the result in zmm1 using writemask k1.
Permute double-precision floating-point values in
xmm2/m128 using controls from imm8.
Permute double-precision floating-point values in
ymm2/m256 using controls from imm8.
Permute double-precision floating-point values in
xmm2/m128/m64bcst using controls from imm8
and store the result in xmm1 using writemask k1.
Permute double-precision floating-point values in
ymm2/m256/m64bcst using controls from imm8
and store the result in ymm1 using writemask k1.
Permute double-precision floating-point values in
zmm2/m512/m64bcst using controls from imm8
and store the result in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values
Vol. 2C 5-371
INSTRUCTION SET REFERENCE, V-Z
Description
(variable control version)
Permute pairs of double-precision floating-point values in the first source operand (second operand), each using a
1-bit control field residing in the corresponding quadword element of the second source operand (third operand).
Permuted results are stored in the destination operand (first operand).
The control bits are located at bit 0 of each quadword element (see Figure 5-24). Each control determines which of
the source element in an input pair is selected for the destination element. Each pair of source elements must lie in
the same 128-bit region as the destination.
EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are
written to the destination under the writemask.
SRC1
X3
X2
X1
X0
DEST
X2..X3
X2..X3
X0..X1
X0..X1
Figure 5-23. VPERMILPD Operation
VEX.256 encoded version: Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
Bit
Control Field 4
...
66
ignored
65
sel
63
Control Field 2
2
ignored
1
sel
ignored
sel
ignored
ignored
127
ignored
194 193
255
Control Field1
Figure 5-24. VPERMILPD Shuffle Control
(immediate control version)
Permute pairs of double-precision floating-point values in the first source operand (second operand), each pair
using a 1-bit control field in the imm8 byte. Each element in the destination operand (first operand) use a separate
control bit of the imm8 byte.
VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination
operand is a YMM/XMM register. Imm8 byte provides the lower 4/2 bit as permute control fields.
EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are written to
the destination under the writemask. Imm8 byte provides the lower 8/4/2 bit as permute control fields.
Note: For the imm8 versions, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will
#UD.
5-372 Vol. 2C
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Operation
VPERMILPD (EVEX immediate versions)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN TMP_SRC1[i+63:i] SRC1[63:0];
ELSE TMP_SRC1[i+63:i] SRC1[i+63:i];
FI;
ENDFOR;
IF (imm8[0] = 0) THEN TMP_DEST[63:0] SRC1[63:0]; FI;
IF (imm8[0] = 1) THEN TMP_DEST[63:0] TMP_SRC1[127:64]; FI;
IF (imm8[1] = 0) THEN TMP_DEST[127:64] TMP_SRC1[63:0]; FI;
IF (imm8[1] = 1) THEN TMP_DEST[127:64] TMP_SRC1[127:64]; FI;
IF VL >= 256
IF (imm8[2] = 0) THEN TMP_DEST[191:128] TMP_SRC1[191:128]; FI;
IF (imm8[2] = 1) THEN TMP_DEST[191:128] TMP_SRC1[255:192]; FI;
IF (imm8[3] = 0) THEN TMP_DEST[255:192] TMP_SRC1[191:128]; FI;
IF (imm8[3] = 1) THEN TMP_DEST[255:192] TMP_SRC1[255:192]; FI;
FI;
IF VL >= 512
IF (imm8[4] = 0) THEN TMP_DEST[319:256] TMP_SRC1[319:256]; FI;
IF (imm8[4] = 1) THEN TMP_DEST[319:256] TMP_SRC1[383:320]; FI;
IF (imm8[5] = 0) THEN TMP_DEST[383:320] TMP_SRC1[319:256]; FI;
IF (imm8[5] = 1) THEN TMP_DEST[383:320] TMP_SRC1[383:320]; FI;
IF (imm8[6] = 0) THEN TMP_DEST[447:384] TMP_SRC1[447:384]; FI;
IF (imm8[6] = 1) THEN TMP_DEST[447:384] TMP_SRC1[511:448]; FI;
IF (imm8[7] = 0) THEN TMP_DEST[511:448] TMP_SRC1[447:384]; FI;
IF (imm8[7] = 1) THEN TMP_DEST[511:448] TMP_SRC1[511:448]; FI;
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMILPD (256-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0]SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0]SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64]SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64]SRC1[127:64]
IF (imm8[2] = 0) THEN DEST[191:128]SRC1[191:128]
IF (imm8[2] = 1) THEN DEST[191:128]SRC1[255:192]
IF (imm8[3] = 0) THEN DEST[255:192]SRC1[191:128]
IF (imm8[3] = 1) THEN DEST[255:192]SRC1[255:192]
DEST[MAX_VL-1:256]0
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values
Vol. 2C 5-373
INSTRUCTION SET REFERENCE, V-Z
VPERMILPD (128-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0]SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0]SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64]SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64]SRC1[127:64]
DEST[MAX_VL-1:128]0
VPERMILPD (EVEX variable versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] SRC2[63:0];
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i];
FI;
ENDFOR;
IF (TMP_SRC2[1] = 0) THEN TMP_DEST[63:0] SRC1[63:0]; FI;
IF (TMP_SRC2[1] = 1) THEN TMP_DEST[63:0] SRC1[127:64]; FI;
IF (TMP_SRC2[65] = 0) THEN TMP_DEST[127:64] SRC1[63:0]; FI;
IF (TMP_SRC2[65] = 1) THEN TMP_DEST[127:64] SRC1[127:64]; FI;
IF VL >= 256
IF (TMP_SRC2[129] = 0) THEN TMP_DEST[191:128] SRC1[191:128]; FI;
IF (TMP_SRC2[129] = 1) THEN TMP_DEST[191:128] SRC1[255:192]; FI;
IF (TMP_SRC2[193] = 0) THEN TMP_DEST[255:192] SRC1[191:128]; FI;
IF (TMP_SRC2[193] = 1) THEN TMP_DEST[255:192] SRC1[255:192]; FI;
FI;
IF VL >= 512
IF (TMP_SRC2[257] = 0) THEN TMP_DEST[319:256] SRC1[319:256]; FI;
IF (TMP_SRC2[257] = 1) THEN TMP_DEST[319:256] SRC1[383:320]; FI;
IF (TMP_SRC2[321] = 0) THEN TMP_DEST[383:320] SRC1[319:256]; FI;
IF (TMP_SRC2[321] = 1) THEN TMP_DEST[383:320] SRC1[383:320]; FI;
IF (TMP_SRC2[385] = 0) THEN TMP_DEST[447:384] SRC1[447:384]; FI;
IF (TMP_SRC2[385] = 1) THEN TMP_DEST[447:384] SRC1[511:448]; FI;
IF (TMP_SRC2[449] = 0) THEN TMP_DEST[511:448] SRC1[447:384]; FI;
IF (TMP_SRC2[449] = 1) THEN TMP_DEST[511:448] SRC1[511:448]; FI;
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-374 Vol. 2C
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VPERMILPD (256-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0]SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0]SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64]SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64]SRC1[127:64]
IF (SRC2[129] = 0) THEN DEST[191:128]SRC1[191:128]
IF (SRC2[129] = 1) THEN DEST[191:128]SRC1[255:192]
IF (SRC2[193] = 0) THEN DEST[255:192]SRC1[191:128]
IF (SRC2[193] = 1) THEN DEST[255:192]SRC1[255:192]
DEST[MAX_VL-1:256]0
VPERMILPD (128-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0]SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0]SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64]SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64]SRC1[127:64]
DEST[MAX_VL-1:128]0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMILPD __m512d _mm512_permute_pd( __m512d a, int imm);
VPERMILPD __m512d _mm512_mask_permute_pd(__m512d s, __mmask8 k, __m512d a, int imm);
VPERMILPD __m512d _mm512_maskz_permute_pd( __mmask8 k, __m512d a, int imm);
VPERMILPD __m256d _mm256_mask_permute_pd(__m256d s, __mmask8 k, __m256d a, int imm);
VPERMILPD __m256d _mm256_maskz_permute_pd( __mmask8 k, __m256d a, int imm);
VPERMILPD __m128d _mm_mask_permute_pd(__m128d s, __mmask8 k, __m128d a, int imm);
VPERMILPD __m128d _mm_maskz_permute_pd( __mmask8 k, __m128d a, int imm);
VPERMILPD __m512d _mm512_permutevar_pd( __m512i i, __m512d a);
VPERMILPD __m512d _mm512_mask_permutevar_pd(__m512d s, __mmask8 k, __m512i i, __m512d a);
VPERMILPD __m512d _mm512_maskz_permutevar_pd( __mmask8 k, __m512i i, __m512d a);
VPERMILPD __m256d _mm256_mask_permutevar_pd(__m256d s, __mmask8 k, __m256d i, __m256d a);
VPERMILPD __m256d _mm256_maskz_permutevar_pd( __mmask8 k, __m256d i, __m256d a);
VPERMILPD __m128d _mm_mask_permutevar_pd(__m128d s, __mmask8 k, __m128d i, __m128d a);
VPERMILPD __m128d _mm_maskz_permutevar_pd( __mmask8 k, __m128d i, __m128d a);
VPERMILPD __m128d _mm_permute_pd (__m128d a, int control)
VPERMILPD __m256d _mm256_permute_pd (__m256d a, int control)
VPERMILPD __m128d _mm_permutevar_pd (__m128d a, __m128i control);
VPERMILPD __m256d _mm256_permutevar_pd (__m256d a, __m256i control);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD
If VEX.W = 1.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD
If either (E)VEX.vvvv != 1111B and with imm8.
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values
Vol. 2C 5-375
INSTRUCTION SET REFERENCE, V-Z
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
Opcode/
Instruction
Op / En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX
VEX.NDS.128.66.0F38.W0 0C /r
VPERMILPS xmm1, xmm2, xmm3/m128
VEX.128.66.0F3A.W0 04 /r ib
VPERMILPS xmm1, xmm2/m128, imm8
RM
V/V
AVX
VEX.NDS.256.66.0F38.W0 0C /r
VPERMILPS ymm1, ymm2, ymm3/m256
RVM
V/V
AVX
VEX.256.66.0F3A.W0 04 /r ib
VPERMILPS ymm1, ymm2/m256, imm8
RM
V/V
AVX
EVEX.NDS.128.66.0F38.W0 0C /r
VPERMILPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 0C /r
VPERMILPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 0C /r
VPERMILPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.128.66.0F3A.W0 04 /r ib
VPERMILPS xmm1 {k1}{z},
xmm2/m128/m32bcst, imm8
EVEX.256.66.0F3A.W0 04 /r ib
VPERMILPS ymm1 {k1}{z},
ymm2/m256/m32bcst, imm8
EVEX.512.66.0F3A.W0 04 /r
ibVPERMILPS zmm1 {k1}{z},
zmm2/m512/m32bcst, imm8
FV-RVM
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512F
FV-RM
V/V
AVX512VL
AVX512F
FV-RM
V/V
AVX512VL
AVX512F
FV-RM
V/V
AVX512F
Description
Permute single-precision floating-point values in
xmm2 using controls from xmm3/m128 and
store result in xmm1.
Permute single-precision floating-point values in
xmm2/m128 using controls from imm8 and store
result in xmm1.
Permute single-precision floating-point values in
ymm2 using controls from ymm3/m256 and
store result in ymm1.
Permute single-precision floating-point values in
ymm2/m256 using controls from imm8 and store
result in ymm1.
Permute single-precision floating-point values
xmm2 using control from xmm3/m128/m32bcst
and store the result in xmm1 using writemask k1.
Permute single-precision floating-point values
ymm2 using control from ymm3/m256/m32bcst
and store the result in ymm1 using writemask k1.
Permute single-precision floating-point values
zmm2 using control from zmm3/m512/m32bcst
and store the result in zmm1 using writemask k1.
Permute single-precision floating-point values
xmm2/m128/m32bcst using controls from imm8
and store the result in xmm1 using writemask k1.
Permute single-precision floating-point values
ymm2/m256/m32bcst using controls from imm8
and store the result in ymm1 using writemask k1.
Permute single-precision floating-point values
zmm2/m512/m32bcst using controls from imm8
and store the result in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV-RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
5-376 Vol. 2C
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
Description
(variable control version)
Permute quadruples of single-precision floating-point values in the first source operand (second operand), each
quadruplet using a 2-bit control field in the corresponding dword element of the second source operand. Permuted
results are stored in the destination operand (first operand).
The 2-bit control fields are located at the low two bits of each dword element (see Figure 5-26). Each control determines which of the source element in an input quadruple is selected for the destination element. Each quadruple of
source elements must lie in the same 128-bit region as the destination.
EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are
written to the destination under the writemask.
SRC1
X7
X6
DEST X7 .. X4
X5
X7 .. X4
X7 .. X4
X4
X3
X7 .. X4 X3 ..X0
X2
X1
X0
X3 ..X0
X3 .. X0
X3 .. X0
Figure 5-25. VPERMILPS Operation
Bit
226 225 224
255
ignored
sel
Control Field 7
63
...
34
ignored
33 32
31
sel
Control Field 2
1
ignored
0
sel
Control Field 1
Figure 5-26. VPERMILPS Shuffle Control
(immediate control version)
Permute quadruples of single-precision floating-point values in the first source operand (second operand), each
quadruplet using a 2-bit control field in the imm8 byte. Each 128-bit lane in the destination operand (first operand)
use the four control fields of the same imm8 byte.
VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination
operand is a YMM/XMM register.
EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are written to
the destination under the writemask.
Note: For the imm8 version, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will
#UD.
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
Vol. 2C 5-377
INSTRUCTION SET REFERENCE, V-Z
Operation
Select4(SRC, control) {
CASE (control[1:0]) OF
0: TMP SRC[31:0];
1: TMP SRC[63:32];
2: TMP SRC[95:64];
3: TMP SRC[127:96];
ESAC;
RETURN TMP
}
VPERMILPS (EVEX immediate versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN TMP_SRC1[i+31:i] SRC1[31:0];
ELSE TMP_SRC1[i+31:i] SRC1[i+31:i];
FI;
ENDFOR;
TMP_DEST[31:0] Select4(TMP_SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] Select4(TMP_SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] Select4(TMP_SRC1[127:0], imm8[5:4]);
TMP_DEST[127:96] Select4(TMP_SRC1[127:0], imm8[7:6]); FI;
IF VL >= 256
TMP_DEST[159:128] Select4(TMP_SRC1[255:128], imm8[1:0]); FI;
TMP_DEST[191:160] Select4(TMP_SRC1[255:128], imm8[3:2]); FI;
TMP_DEST[223:192] Select4(TMP_SRC1[255:128], imm8[5:4]); FI;
TMP_DEST[255:224] Select4(TMP_SRC1[255:128], imm8[7:6]); FI;
FI;
IF VL >= 512
TMP_DEST[287:256] Select4(TMP_SRC1[383:256], imm8[1:0]); FI;
TMP_DEST[319:288] Select4(TMP_SRC1[383:256], imm8[3:2]); FI;
TMP_DEST[351:320] Select4(TMP_SRC1[383:256], imm8[5:4]); FI;
TMP_DEST[383:352] Select4(TMP_SRC1[383:256], imm8[7:6]); FI;
TMP_DEST[415:384] Select4(TMP_SRC1[511:384], imm8[1:0]); FI;
TMP_DEST[447:416] Select4(TMP_SRC1[511:384], imm8[3:2]); FI;
TMP_DEST[479:448] Select4(TMP_SRC1[511:384], imm8[5:4]); FI;
TMP_DEST[511:480] Select4(TMP_SRC1[511:384], imm8[7:6]); FI;
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-378 Vol. 2C
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VPERMILPS (256-bit immediate version)
DEST[31:0] Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] Select4(SRC1[127:0], imm8[7:6]);
DEST[159:128] Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] Select4(SRC1[255:128], imm8[5:4]);
DEST[255:224] Select4(SRC1[255:128], imm8[7:6]);
VPERMILPS (128-bit immediate version)
DEST[31:0] Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] Select4(SRC1[127:0], imm8[7:6]);
DEST[MAX_VL-1:128]0
VPERMILPS (EVEX variable versions)
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] SRC2[31:0];
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i];
FI;
ENDFOR;
TMP_DEST[31:0] Select4(SRC1[127:0], TMP_SRC2[1:0]);
TMP_DEST[63:32] Select4(SRC1[127:0], TMP_SRC2[33:32]);
TMP_DEST[95:64] Select4(SRC1[127:0], TMP_SRC2[65:64]);
TMP_DEST[127:96] Select4(SRC1[127:0], TMP_SRC2[97:96]);
IF VL >= 256
TMP_DEST[159:128] Select4(SRC1[255:128], TMP_SRC2[129:128]);
TMP_DEST[191:160] Select4(SRC1[255:128], TMP_SRC2[161:160]);
TMP_DEST[223:192] Select4(SRC1[255:128], TMP_SRC2[193:192]);
TMP_DEST[255:224] Select4(SRC1[255:128], TMP_SRC2[225:224]);
FI;
IF VL >= 512
TMP_DEST[287:256] Select4(SRC1[383:256], TMP_SRC2[257:256]);
TMP_DEST[319:288] Select4(SRC1[383:256], TMP_SRC2[289:288]);
TMP_DEST[351:320] Select4(SRC1[383:256], TMP_SRC2[321:320]);
TMP_DEST[383:352] Select4(SRC1[383:256], TMP_SRC2[353:352]);
TMP_DEST[415:384] Select4(SRC1[511:384], TMP_SRC2[385:384]);
TMP_DEST[447:416] Select4(SRC1[511:384], TMP_SRC2[417:416]);
TMP_DEST[479:448] Select4(SRC1[511:384], TMP_SRC2[449:448]);
TMP_DEST[511:480] Select4(SRC1[511:384], TMP_SRC2[481:480]);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
;zeroing-masking
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
Vol. 2C 5-379
INSTRUCTION SET REFERENCE, V-Z
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMILPS (256-bit variable version)
DEST[31:0] Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] Select4(SRC1[127:0], SRC2[97:96]);
DEST[159:128] Select4(SRC1[255:128], SRC2[129:128]);
DEST[191:160] Select4(SRC1[255:128], SRC2[161:160]);
DEST[223:192] Select4(SRC1[255:128], SRC2[193:192]);
DEST[255:224] Select4(SRC1[255:128], SRC2[225:224]);
DEST[MAX_VL-1:256]0
VPERMILPS (128-bit variable version)
DEST[31:0] Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] Select4(SRC1[127:0], SRC2[97:96]);
DEST[MAX_VL-1:128]0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMILPS __m512 _mm512_permute_ps( __m512 a, int imm);
VPERMILPS __m512 _mm512_mask_permute_ps(__m512 s, __mmask16 k, __m512 a, int imm);
VPERMILPS __m512 _mm512_maskz_permute_ps( __mmask16 k, __m512 a, int imm);
VPERMILPS __m256 _mm256_mask_permute_ps(__m256 s, __mmask8 k, __m256 a, int imm);
VPERMILPS __m256 _mm256_maskz_permute_ps( __mmask8 k, __m256 a, int imm);
VPERMILPS __m128 _mm_mask_permute_ps(__m128 s, __mmask8 k, __m128 a, int imm);
VPERMILPS __m128 _mm_maskz_permute_ps( __mmask8 k, __m128 a, int imm);
VPERMILPS __m512 _mm512_permutevar_ps( __m512i i, __m512 a);
VPERMILPS __m512 _mm512_mask_permutevar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m512 _mm512_maskz_permutevar_ps( __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m256 _mm256_mask_permutevar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m256 _mm256_maskz_permutevar_ps( __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m128 _mm_mask_permutevar_ps(__m128 s, __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_maskz_permutevar_ps( __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_permute_ps (__m128 a, int control);
VPERMILPS __m256 _mm256_permute_ps (__m256 a, int control);
VPERMILPS __m128 _mm_permutevar_ps (__m128 a, __m128i control);
VPERMILPS __m256 _mm256_permutevar_ps (__m256 a, __m256i control);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
#UD
If VEX.W = 1.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD
5-380 Vol. 2C
If either (E)VEX.vvvv != 1111B and with imm8.
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VPERMPD—Permute Double-Precision Floating-Point Elements
Opcode/
Instruction
Op / En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
VEX.256.66.0F3A.W1 01 /r ib
VPERMPD ymm1, ymm2/m256, imm8
EVEX.256.66.0F3A.W1 01 /r ib
VPERMPD ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
EVEX.512.66.0F3A.W1 01 /r ib
VPERMPD zmm1 {k1}{z},
zmm2/m512/m64bcst, imm8
EVEX.NDS.256.66.0F38.W1 16 /r
VPERMPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 16 /r
VPERMPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV-RM
V/V
AVX512VL
AVX512F
FV-RMI
V/V
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512F
Description
Permute double-precision floating-point elements in
ymm2/m256 using indices in imm8 and store the
result in ymm1.
Permute double-precision floating-point elements in
ymm2/m256/m64bcst using indexes in imm8 and
store the result in ymm1 subject to writemask k1.
Permute double-precision floating-point elements in
zmm2/m512/m64bcst using indices in imm8 and
store the result in zmm1 subject to writemask k1.
Permute double-precision floating-point elements in
ymm3/m256/m64bcst using indexes in ymm2 and
store the result in ymm1 subject to writemask k1.
Permute double-precision floating-point elements in
zmm3/m512/m64bcst using indices in zmm2 and
store the result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
FV-RMI
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
The imm8 version: Copies quadword elements of double-precision floating-point values from the source operand
(the second operand) to the destination operand (the first operand) according to the indices specified by the immediate operand (the third operand). Each two-bit value in the immediate byte selects a qword element in the source
operand.
VEX version: The source operand can be a YMM register or a memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
In EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8
bits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The
source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location.
The imm8 versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The vector control version: Copies quadword elements of double-precision floating-point values from the second
source operand (the third operand) to the destination operand (the first operand) according to the indices in the
first source operand (the second operand). The first 3 bits of each 64 bit element in the index operand selects
which quadword in the second source operand to copy. The first and second operands are ZMM registers, the third
operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory
location. The elements in the destination are updated using the writemask k1.
Note that this instruction permits a qword in the source operand to be copied to multiple locations in the destination operand.
If VPERMPD is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an
#UD exception.
VPERMPD—Permute Double-Precision Floating-Point Elements
Vol. 2C 5-381
INSTRUCTION SET REFERENCE, V-Z
Operation
VPERMPD (EVEX - imm8 control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+63:i] SRC[63:0];
ELSE TMP_SRC[i+63:i] SRC[i+63:i];
FI;
ENDFOR;
TMP_DEST[63:0] (TMP_SRC[256:0] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[127:64] (TMP_SRC[256:0] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[191:128] (TMP_SRC[256:0] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[255:192] (TMP_SRC[256:0] >> (IMM8[7:6] * 64))[63:0];
IF VL >= 512
TMP_DEST[319:256] (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[383:320] (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[447:384] (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[511:448] (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMPD (EVEX - vector control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] SRC2[63:0];
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i];
FI;
ENDFOR;
IF VL = 256
TMP_DEST[63:0] (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];
TMP_DEST[127:64] (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];
TMP_DEST[191:128] (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];
TMP_DEST[255:192] (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];
FI;
IF VL = 512
TMP_DEST[63:0] (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];
5-382 Vol. 2C
VPERMPD—Permute Double-Precision Floating-Point Elements
INSTRUCTION SET REFERENCE, V-Z
TMP_DEST[127:64] (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];
TMP_DEST[191:128] (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];
TMP_DEST[255:192] (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];
TMP_DEST[319:256] (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];
TMP_DEST[383:320] (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];
TMP_DEST[447:384] (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];
TMP_DEST[511:448] (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMPD (VEX.256 encoded version)
DEST[63:0] (SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] (SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] (SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] (SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
DEST[MAX_VL-1:256] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMPD __m512d _mm512_permutex_pd( __m512d a, int imm);
VPERMPD __m512d _mm512_mask_permutex_pd(__m512d s, __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_maskz_permutex_pd( __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_permutexvar_pd( __m512i i, __m512d a);
VPERMPD __m512d _mm512_mask_permutexvar_pd(__m512d s, __mmask16 k, __m512i i, __m512d a);
VPERMPD __m512d _mm512_maskz_permutexvar_pd( __mmask16 k, __m512i i, __m512d a);
VPERMPD __m256d _mm256_permutex_epi64( __m256d a, int imm);
VPERMPD __m256d _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_maskz_permutex_epi64( __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_permutexvar_epi64( __m256i i, __m256d a);
VPERMPD __m256d _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i i, __m256d a);
VPERMPD __m256d _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i i, __m256d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD
If VEX.L = 0.
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD
If encoded with EVEX.128.
If EVEX.vvvv != 1111B and with imm8.
VPERMPD—Permute Double-Precision Floating-Point Elements
Vol. 2C 5-383
INSTRUCTION SET REFERENCE, V-Z
VPERMPS—Permute Single-Precision Floating-Point Elements
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
VEX.256.66.0F38.W0 16 /r
VPERMPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.256.66.0F38.W0 16 /r
VPERMPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 16 /r
VPERMPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Permute single-precision floating-point elements in
ymm3/m256 using indices in ymm2 and store the result in
ymm1.
Permute single-precision floating-point elements in
ymm3/m256/m32bcst using indexes in ymm2 and store
the result in ymm1 subject to write mask k1.
Permute single-precision floating-point values in
zmm3/m512/m32bcst using indices in zmm2 and store the
result in zmm1 subject to write mask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Copies doubleword elements of single-precision floating-point values from the second source operand (the third
operand) to the destination operand (the first operand) according to the indices in the first source operand (the
second operand). Note that this instruction permits a doubleword in the source operand to be copied to more than
one location in the destination operand.
VEX.256 versions: The first and second operands are YMM registers, the third operand can be a YMM register or
memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded version: The first and second operands are ZMM registers, the third operand can be a ZMM register,
a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The elements in the
destination are updated using the writemask k1.
If VPERMPS is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an
#UD exception.
Operation
VPERMPS (EVEX forms)
(KL, VL) (8, 256),= (16, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] SRC2[31:0];
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i];
FI;
ENDFOR;
IF VL = 256
TMP_DEST[31:0] (TMP_SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
TMP_DEST[63:32] (TMP_SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
TMP_DEST[95:64] (TMP_SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
TMP_DEST[127:96] (TMP_SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
TMP_DEST[159:128] (TMP_SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
TMP_DEST[191:160] (TMP_SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
TMP_DEST[223:192] (TMP_SRC2[255:0] >> (SRC1[193:192] * 32))[31:0];
TMP_DEST[255:224] (TMP_SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
5-384 Vol. 2C
VPERMPS—Permute Single-Precision Floating-Point Elements
INSTRUCTION SET REFERENCE, V-Z
FI;
IF VL = 512
TMP_DEST[31:0] (TMP_SRC2[511:0] >> (SRC1[3:0] * 32))[31:0];
TMP_DEST[63:32] (TMP_SRC2[511:0] >> (SRC1[35:32] * 32))[31:0];
TMP_DEST[95:64] (TMP_SRC2[511:0] >> (SRC1[67:64] * 32))[31:0];
TMP_DEST[127:96] (TMP_SRC2[511:0] >> (SRC1[99:96] * 32))[31:0];
TMP_DEST[159:128] (TMP_SRC2[511:0] >> (SRC1[131:128] * 32))[31:0];
TMP_DEST[191:160] (TMP_SRC2[511:0] >> (SRC1[163:160] * 32))[31:0];
TMP_DEST[223:192] (TMP_SRC2[511:0] >> (SRC1[195:192] * 32))[31:0];
TMP_DEST[255:224] (TMP_SRC2[511:0] >> (SRC1[227:224] * 32))[31:0];
TMP_DEST[287:256] (TMP_SRC2[511:0] >> (SRC1[259:256] * 32))[31:0];
TMP_DEST[319:288] (TMP_SRC2[511:0] >> (SRC1[291:288] * 32))[31:0];
TMP_DEST[351:320] (TMP_SRC2[511:0] >> (SRC1[323:320] * 32))[31:0];
TMP_DEST[383:352] (TMP_SRC2[511:0] >> (SRC1[355:352] * 32))[31:0];
TMP_DEST[415:384] (TMP_SRC2[511:0] >> (SRC1[387:384] * 32))[31:0];
TMP_DEST[447:416] (TMP_SRC2[511:0] >> (SRC1[419:416] * 32))[31:0];
TMP_DEST[479:448] (TMP_SRC2[511:0] >> (SRC1[451:448] * 32))[31:0];
TMP_DEST[511:480] (TMP_SRC2[511:0] >> (SRC1[483:480] * 32))[31:0];
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMPS (VEX.256 encoded version)
DEST[31:0] (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
DEST[MAX_VL-1:256] 0
VPERMPS—Permute Single-Precision Floating-Point Elements
Vol. 2C 5-385
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPERMPS __m512 _mm512_permutexvar_ps(__m512i i, __m512 a);
VPERMPS __m512 _mm512_mask_permutexvar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);
VPERMPS __m512 _mm512_maskz_permutexvar_ps( __mmask16 k, __m512i i, __m512 a);
VPERMPS __m256 _mm256_permutexvar_ps(__m256 i, __m256 a);
VPERMPS __m256 _mm256_mask_permutexvar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);
VPERMPS __m256 _mm256_maskz_permutexvar_ps( __mmask8 k, __m256 i, __m256 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Exceptions Type E4NF.
5-386 Vol. 2C
VPERMPS—Permute Single-Precision Floating-Point Elements
INSTRUCTION SET REFERENCE, V-Z
VPERMQ—Qwords Element Permutation
Opcode/
Instruction
Op / En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
VEX.256.66.0F3A.W1 00 /r ib
VPERMQ ymm1, ymm2/m256, imm8
EVEX.256.66.0F3A.W1 00 /r ib
VPERMQ ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
EVEX.512.66.0F3A.W1 00 /r ib
VPERMQ zmm1 {k1}{z},
zmm2/m512/m64bcst, imm8
EVEX.NDS.256.66.0F38.W1 36 /r
VPERMQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 36 /r
VPERMQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
Description
FV-RM
V/V
AVX512VL
AVX512F
FV-RMI
V/V
AVX512F
Permute qwords in zmm2/m512/m64bcst using
indices in imm8 and store the result in zmm1.
FV-RVM
V/V
AVX512VL
AVX512F
Permute qwords in ymm3/m256/m64bcst using
indexes in ymm2 and store the result in ymm1.
FV-RVM
V/V
AVX512F
Permute qwords in zmm3/m512/m64bcst using
indices in zmm2 and store the result in zmm1.
Permute qwords in ymm2/m256 using indices in
imm8 and store the result in ymm1.
Permute qwords in ymm2/m256/m64bcst using
indexes in imm8 and store the result in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
FV-RMI
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
The imm8 version: Copies quadwords from the source operand (the second operand) to the destination operand
(the first operand) according to the indices specified by the immediate operand (the third operand). Each two-bit
value in the immediate byte selects a qword element in the source operand.
VEX version: The source operand can be a YMM register or a memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
In EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8
bits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The
source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location.
Immediate control versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will
#UD.
The vector control version: Copies quadwords from the second source operand (the third operand) to the destination operand (the first operand) according to the indices in the first source operand (the second operand). The first
3 bits of each 64 bit element in the index operand selects which quadword in the second source operand to copy.
The first and second operands are ZMM registers, the third operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The elements in the destination are updated
using the writemask k1.
Note that this instruction permits a qword in the source operand to be copied to multiple locations in the destination operand.
If VPERMPQ is encoded with VEX.L= 0 or EVEX.128, an attempt to execute the instruction will cause an #UD exception.
VPERMQ—Qwords Element Permutation
Vol. 2C 5-387
INSTRUCTION SET REFERENCE, V-Z
Operation
VPERMQ (EVEX - imm8 control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+63:i] SRC[63:0];
ELSE TMP_SRC[i+63:i] SRC[i+63:i];
FI;
ENDFOR;
TMP_DEST[63:0] (TMP_SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[127:64] (TMP_SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[191:128] (TMP_SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[255:192] (TMP_SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
IF VL >= 512
TMP_DEST[319:256] (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[383:320] (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[447:384] (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[511:448] (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMQ (EVEX - vector control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] SRC2[63:0];
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i];
FI;
ENDFOR;
IF VL = 256
TMP_DEST[63:0] (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];
TMP_DEST[127:64] (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];
TMP_DEST[191:128] (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];
TMP_DEST[255:192] (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];
FI;
IF VL = 512
TMP_DEST[63:0] (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];
TMP_DEST[127:64] (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];
TMP_DEST[191:128] (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];
TMP_DEST[255:192] (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];
5-388 Vol. 2C
VPERMQ—Qwords Element Permutation
INSTRUCTION SET REFERENCE, V-Z
TMP_DEST[319:256] (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];
TMP_DEST[383:320] (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];
TMP_DEST[447:384] (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];
TMP_DEST[511:448] (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPERMQ (VEX.256 encoded version)
DEST[63:0] (SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] (SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] (SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] (SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
DEST[MAX_VL-1:256] 0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMQ __m512i _mm512_permutex_epi64( __m512i a, int imm);
VPERMQ __m512i _mm512_mask_permutex_epi64(__m512i s, __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_maskz_permutex_epi64( __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_permutexvar_epi64( __m512i a, __m512i b);
VPERMQ __m512i _mm512_mask_permutexvar_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPERMQ __m512i _mm512_maskz_permutexvar_epi64( __mmask8 k, __m512i a, __m512i b);
VPERMQ __m256i _mm256_permutex_epi64( __m256i a, int imm);
VPERMQ __m256i _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_maskz_permutex_epi64( __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_permutexvar_epi64( __m256i a, __m256i b);
VPERMQ __m256i _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPERMQ __m256i _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD
If VEX.L = 0.
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD
If encoded with EVEX.128.
If EVEX.vvvv != 1111B and with imm8.
VPERMQ—Qwords Element Permutation
Vol. 2C 5-389
INSTRUCTION SET REFERENCE, V-Z
VPEXPANDD—Load Sparse Packed Doubleword Integer Values from Dense Memory / Register
Opcode/
Instruction
Op/
En
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W0 89 /r
VPEXPANDD xmm1 {k1}{z},
xmm2/m128
EVEX.256.66.0F38.W0 89 /r
VPEXPANDD ymm1 {k1}{z},
ymm2/m256
EVEX.512.66.0F38.W0 89 /r
VPEXPANDD zmm1 {k1}{z},
zmm2/m512
Description
Expand packed double-word integer values from
xmm2/m128 to xmm1 using writemask k1.
T1S
V/V
AVX512VL
AVX512F
Expand packed double-word integer values from
ymm2/m256 to ymm1 using writemask k1.
T1S
V/V
AVX512F
Expand packed double-word integer values from
zmm2/m512 to zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Expand (load) up to 16 contiguous doubleword integer values of the input vector in the source operand (the second
operand) to sparse elements in the destination operand (the first operand), selected by the writemask k1. The
destination operand is a ZMM register, the source operand can be a ZMM register or memory location.
The input vector starts from the lowest element in the source operand. The opmask register k1 selects the destination elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPEXPANDD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
k0
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] SRC[k+31:k];
k k + 32
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-390 Vol. 2C
VPEXPANDD—Load Sparse Packed Doubleword Integer Values from Dense Memory / Register
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPEXPANDD __m512i _mm512_mask_expandloadu_epi32(__m512i s, __mmask16 k, void * a);
VPEXPANDD __m512i _mm512_maskz_expandloadu_epi32( __mmask16 k, void * a);
VPEXPANDD __m512i _mm512_mask_expand_epi32(__m512i s, __mmask16 k, __m512i a);
VPEXPANDD __m512i _mm512_maskz_expand_epi32( __mmask16 k, __m512i a);
VPEXPANDD __m256i _mm256_mask_expandloadu_epi32(__m256i s, __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_maskz_expandloadu_epi32( __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_mask_expand_epi32(__m256i s, __mmask8 k, __m256i a);
VPEXPANDD __m256i _mm256_maskz_expand_epi32( __mmask8 k, __m256i a);
VPEXPANDD __m128i _mm_mask_expandloadu_epi32(__m128i s, __mmask8 k, void * a);
VPEXPANDD __m128i _mm_maskz_expandloadu_epi32( __mmask8 k, void * a);
VPEXPANDD __m128i _mm_mask_expand_epi32(__m128i s, __mmask8 k, __m128i a);
VPEXPANDD __m128i _mm_maskz_expand_epi32( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD
If EVEX.vvvv != 1111B.
VPEXPANDD—Load Sparse Packed Doubleword Integer Values from Dense Memory / Register
Vol. 2C 5-391
INSTRUCTION SET REFERENCE, V-Z
VPEXPANDQ—Load Sparse Packed Quadword Integer Values from Dense Memory / Register
Opcode/
Instruction
Op/
En
EVEX.128.66.0F38.W1 89 /r
VPEXPANDQ xmm1 {k1}{z}, xmm2/m128
EVEX.256.66.0F38.W1 89 /r
VPEXPANDQ ymm1 {k1}{z}, ymm2/m256
EVEX.512.66.0F38.W1 89 /r
VPEXPANDQ zmm1 {k1}{z}, zmm2/m512
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Expand packed quad-word integer values from
xmm2/m128 to xmm1 using writemask k1.
Expand packed quad-word integer values from
ymm2/m256 to ymm1 using writemask k1.
Expand packed quad-word integer values from
zmm2/m512 to zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Expand (load) up to 8 quadword integer values from the source operand (the second operand) to sparse elements
in the destination operand (the first operand), selected by the writemask k1. The destination operand is a ZMM
register, the source operand can be a ZMM register or memory location.
The input vector starts from the lowest element in the source operand. The opmask register k1 selects the destination elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPEXPANDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
k0
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+63:i] SRC[k+63:k];
k k + 64
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-392 Vol. 2C
VPEXPANDQ—Load Sparse Packed Quadword Integer Values from Dense Memory / Register
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPEXPANDQ __m512i _mm512_mask_expandloadu_epi64(__m512i s, __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_mask_expand_epi64(__m512i s, __mmask8 k, __m512i a);
VPEXPANDQ __m512i _mm512_maskz_expand_epi64( __mmask8 k, __m512i a);
VPEXPANDQ __m256i _mm256_mask_expandloadu_epi64(__m256i s, __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_mask_expand_epi64(__m256i s, __mmask8 k, __m256i a);
VPEXPANDQ __m256i _mm256_maskz_expand_epi64( __mmask8 k, __m256i a);
VPEXPANDQ __m128i _mm_mask_expandloadu_epi64(__m128i s, __mmask8 k, void * a);
VPEXPANDQ __m128i _mm_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m128i _mm_mask_expand_epi64(__m128i s, __mmask8 k, __m128i a);
VPEXPANDQ __m128i _mm_maskz_expand_epi64( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD
If EVEX.vvvv != 1111B.
VPEXPANDQ—Load Sparse Packed Quadword Integer Values from Dense Memory / Register
Vol. 2C 5-393
INSTRUCTION SET REFERENCE, V-Z
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
AVX512VL
AVX512CD
Description
FV
64/32
bit Mode
Support
V/V
EVEX.128.66.0F38.W0 44 /r
VPLZCNTD xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.66.0F38.W0 44 /r
VPLZCNTD ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512CD
Count the number of leading zero bits in each dword
element of ymm2/m256/m32bcst using writemask k1.
EVEX.512.66.0F38.W0 44 /r
VPLZCNTD zmm1 {k1}{z},
zmm2/m512/m32bcst
FV
V/V
AVX512CD
Count the number of leading zero bits in each dword
element of zmm2/m512/m32bcst using writemask k1.
EVEX.128.66.0F38.W1 44 /r
VPLZCNTQ xmm1 {k1}{z},
xmm2/m128/m64bcst
FV
V/V
AVX512VL
AVX512CD
Count the number of leading zero bits in each qword
element of xmm2/m128/m64bcst using writemask k1.
EVEX.256.66.0F38.W1 44 /r
VPLZCNTQ ymm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512CD
Count the number of leading zero bits in each qword
element of ymm2/m256/m64bcst using writemask k1.
EVEX.512.66.0F38.W1 44 /r
VPLZCNTQ zmm1 {k1}{z},
zmm2/m512/m64bcst
FV
V/V
AVX512CD
Count the number of leading zero bits in each qword
element of zmm2/m512/m64bcst using writemask k1.
Count the number of leading zero bits in each dword
element of xmm2/m128/m32bcst using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Counts the number of leading most significant zero bits in each dword or qword element of the source operand (the
second operand) and stores the results in the destination register (the first operand) according to the writemask.
If an element is zero, the result for that element is the operand size of the element.
EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated
using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated
using writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated
using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-394 Vol. 2C
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
INSTRUCTION SET REFERENCE, V-Z
Operation
VPLZCNTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j*32
IF MaskBit(j) OR *no writemask*
THEN
temp 32
DEST[i+31:i] 0
WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
DO
temp temp – 1
DEST[i+31:i] DEST[i+31:i] + 1
OD
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] 0
FI
FI
ENDFOR
DEST[MAX_VL-1:VL] 0
VPLZCNTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j*64
IF MaskBit(j) OR *no writemask*
THEN
temp 64
DEST[i+63:i] 0
WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
DO
temp temp – 1
DEST[i+63:i] DEST[i+63:i] + 1
OD
ELSE
IF *merging-masking*
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] 0
FI
FI
ENDFOR
DEST[MAX_VL-1:VL] 0
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
Vol. 2C 5-395
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPLZCNTD __m512i _mm512_lzcnt_epi32(__m512i a);
VPLZCNTD __m512i _mm512_mask_lzcnt_epi32(__m512i s, __mmask16 m, __m512i a);
VPLZCNTD __m512i _mm512_maskz_lzcnt_epi32( __mmask16 m, __m512i a);
VPLZCNTQ __m512i _mm512_lzcnt_epi64(__m512i a);
VPLZCNTQ __m512i _mm512_mask_lzcnt_epi64(__m512i s, __mmask8 m, __m512i a);
VPLZCNTQ __m512i _mm512_maskz_lzcnt_epi64(__mmask8 m, __m512i a);
VPLZCNTD __m256i _mm256_lzcnt_epi32(__m256i a);
VPLZCNTD __m256i _mm256_mask_lzcnt_epi32(__m256i s, __mmask8 m, __m256i a);
VPLZCNTD __m256i _mm256_maskz_lzcnt_epi32( __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_lzcnt_epi64(__m256i a);
VPLZCNTQ __m256i _mm256_mask_lzcnt_epi64(__m256i s, __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_maskz_lzcnt_epi64(__mmask8 m, __m256i a);
VPLZCNTD __m128i _mm_lzcnt_epi32(__m128i a);
VPLZCNTD __m128i _mm_mask_lzcnt_epi32(__m128i s, __mmask8 m, __m128i a);
VPLZCNTD __m128i _mm_maskz_lzcnt_epi32( __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_lzcnt_epi64(__m128i a);
VPLZCNTQ __m128i _mm_mask_lzcnt_epi64(__m128i s, __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_maskz_lzcnt_epi64(__mmask8 m, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.
5-396 Vol. 2C
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
INSTRUCTION SET REFERENCE, V-Z
VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores
Opcode/
Instruction
Op/
En
RVM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
AVX2
VEX.NDS.128.66.0F38.W0 8C /rVPMASKMOVD xmm1, xmm2, m128
VEX.NDS.256.66.0F38.W0 8C /r
VPMASKMOVD ymm1, ymm2, m256
VEX.NDS.128.66.0F38.W1 8C /r
VPMASKMOVQ xmm1, xmm2, m128
VEX.NDS.256.66.0F38.W1 8C /r
VPMASKMOVQ ymm1, ymm2, m256
VEX.NDS.128.66.0F38.W0 8E /r
VPMASKMOVD m128, xmm1, xmm2
VEX.NDS.256.66.0F38.W0 8E /r
VPMASKMOVD m256, ymm1, ymm2
VEX.NDS.128.66.0F38.W1 8E /r
VPMASKMOVQ m128, xmm1, xmm2
VEX.NDS.256.66.0F38.W1 8E /r
VPMASKMOVQ m256, ymm1, ymm2
RVM
V/V
AVX2
RVM
V/V
AVX2
RVM
V/V
AVX2
MVR
V/V
AVX2
MVR
V/V
AVX2
MVR
V/V
AVX2
MVR
V/V
AVX2
Description
Conditionally load dword values from m128 using mask
in xmm2 and store in xmm1.
Conditionally load dword values from m256 using mask
in ymm2 and store in ymm1.
Conditionally load qword values from m128 using mask
in xmm2 and store in xmm1.
Conditionally load qword values from m256 using mask
in ymm2 and store in ymm1.
Conditionally store dword values from xmm2 using
mask in xmm1.
Conditionally store dword values from ymm2 using
mask in ymm1.
Conditionally store qword values from xmm2 using
mask in xmm1.
Conditionally store qword values from ymm2 using
mask in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
MVR
ModRM:r/m (w)
VEX.vvvv
ModRM:reg (r)
NA
Description
Conditionally moves packed data elements from the second source operand into the corresponding data element
of the destination operand, depending on the mask bits associated with each data element. The mask bits are
specified in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instructions. The destination operand
is a memory address for the store form of these instructions. The other operands are either XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.
VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores
Vol. 2C 5-397
INSTRUCTION SET REFERENCE, V-Z
VMASKMOV should not be used to access memory mapped I/O as the ordering of the individual loads or stores it
does is implementation specific.
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an implementation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.
Operation
VPMASKMOVD - 256-bit load
DEST[31:0] IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VPMASKMOVD -128-bit load
DEST[31:0] IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[VLMAX-1:128] 0
VPMASKMOVQ - 256-bit load
DEST[63:0] IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VPMASKMOVQ - 128-bit load
DEST[63:0] IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[VLMAX-1:128] 0
VPMASKMOVD - 256-bit store
IF (SRC1[31]) DEST[31:0] SRC2[31:0]
IF (SRC1[63]) DEST[63:32] SRC2[63:32]
IF (SRC1[95]) DEST[95:64] SRC2[95:64]
IF (SRC1[127]) DEST[127:96] SRC2[127:96]
IF (SRC1[159]) DEST[159:128] SRC2[159:128]
IF (SRC1[191]) DEST[191:160] SRC2[191:160]
IF (SRC1[223]) DEST[223:192] SRC2[223:192]
IF (SRC1[255]) DEST[255:224] SRC2[255:224]
5-398 Vol. 2C
VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores
INSTRUCTION SET REFERENCE, V-Z
VPMASKMOVD - 128-bit store
IF (SRC1[31]) DEST[31:0] SRC2[31:0]
IF (SRC1[63]) DEST[63:32] SRC2[63:32]
IF (SRC1[95]) DEST[95:64] SRC2[95:64]
IF (SRC1[127]) DEST[127:96] SRC2[127:96]
VPMASKMOVQ - 256-bit store
IF (SRC1[63]) DEST[63:0] SRC2[63:0]
IF (SRC1[127]) DEST[127:64] SRC2[127:64]
IF (SRC1[191]) DEST[191:128] SRC2[191:128]
IF (SRC1[255]) DEST[255:192] SRC2[255:192]
VPMASKMOVQ - 128-bit store
IF (SRC1[63]) DEST[63:0] SRC2[63:0]
IF (SRC1[127]) DEST[127:64] SRC2[127:64]
Intel C/C++ Compiler Intrinsic Equivalent
VPMASKMOVD: __m256i _mm256_maskload_epi32(int const *a, __m256i mask)
VPMASKMOVD: void _mm256_maskstore_epi32(int *a, __m256i mask, __m256i b)
VPMASKMOVQ: __m256i _mm256_maskload_epi64(__int64 const *a, __m256i mask);
VPMASKMOVQ: void _mm256_maskstore_epi64(__int64 *a, __m256i mask, __m256d b);
VPMASKMOVD: __m128i _mm_maskload_epi32(int const *a, __m128i mask)
VPMASKMOVD: void _mm_maskstore_epi32(int *a, __m128i mask, __m128 b)
VPMASKMOVQ: __m128i _mm_maskload_epi64(__int cont *a, __m128i mask);
VPMASKMOVQ: void _mm_maskstore_epi64(__int64 *a, __m128i mask, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 6 (No AC# reported for any mask bit combinations).
VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores
Vol. 2C 5-399
INSTRUCTION SET REFERENCE, V-Z
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector
Register
Opcode/
Instruction
Op/
En
EVEX.128.F3.0F38.W0 28 /r
VPMOVM2B xmm1, k1
EVEX.256.F3.0F38.W0 28 /r
VPMOVM2B ymm1, k1
EVEX.512.F3.0F38.W0 28 /r
VPMOVM2B zmm1, k1
EVEX.128.F3.0F38.W1 28 /r
VPMOVM2W xmm1, k1
EVEX.256.F3.0F38.W1 28 /r
VPMOVM2W ymm1, k1
EVEX.512.F3.0F38.W1 28 /r
VPMOVM2W zmm1, k1
EVEX.128.F3.0F38.W0 38 /r
VPMOVM2D xmm1, k1
EVEX.256.F3.0F38.W0 38 /r
VPMOVM2D ymm1, k1
EVEX.512.F3.0F38.W0 38 /r
VPMOVM2D zmm1, k1
EVEX.128.F3.0F38.W1 38 /r
VPMOVM2Q xmm1, k1
EVEX.256.F3.0F38.W1 38 /r
VPMOVM2Q ymm1, k1
EVEX.512.F3.0F38.W1 38 /r
VPMOVM2Q zmm1, k1
RM
64/32
bit Mode
Support
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
AVX512VL
AVX512BW
AVX512BW
AVX512VL
AVX512BW
AVX512VL
AVX512BW
AVX512BW
AVX512VL
AVX512DQ
AVX512VL
AVX512DQ
AVX512DQ
AVX512VL
AVX512DQ
AVX512VL
AVX512DQ
AVX512DQ
Description
Sets each byte in XMM1 to all 1’s or all 0’s based on the value
of the corresponding bit in k1.
Sets each byte in YMM1 to all 1’s or all 0’s based on the value
of the corresponding bit in k1.
Sets each byte in ZMM1 to all 1’s or all 0’s based on the value
of the corresponding bit in k1.
Sets each word in XMM1 to all 1’s or all 0’s based on the value
of the corresponding bit in k1.
Sets each word in YMM1 to all 1’s or all 0’s based on the value
of the corresponding bit in k1.
Sets each word in ZMM1 to all 1’s or all 0’s based on the value
of the corresponding bit in k1.
Sets each doubleword in XMM1 to all 1’s or all 0’s based on the
value of the corresponding bit in k1.
Sets each doubleword in YMM1 to all 1’s or all 0’s based on the
value of the corresponding bit in k1.
Sets each doubleword in ZMM1 to all 1’s or all 0’s based on the
value of the corresponding bit in k1.
Sets each quadword in XMM1 to all 1’s or all 0’s based on the
value of the corresponding bit in k1.
Sets each quadword in YMM1 to all 1’s or all 0’s based on the
value of the corresponding bit in k1.
Sets each quadword in ZMM1 to all 1’s or all 0’s based on the
value of the corresponding bit in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a mask register to a vector register. Each element in the destination register is set to all 1’s or all 0’s
depending on the value of the corresponding bit in the source mask register.
The source operand is a mask register. The destination operand is a ZMM/YMM/XMM register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-400 Vol. 2C
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVM2B (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF SRC[j]
THEN
DEST[i+7:i] -1
ELSE
DEST[i+7:i] 0
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVM2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF SRC[j]
THEN
DEST[i+15:i] -1
ELSE
DEST[i+15:i] 0
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVM2D (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF SRC[j]
THEN
DEST[i+31:i] -1
ELSE
DEST[i+31:i] 0
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVM2Q (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF SRC[j]
THEN
DEST[i+63:i] -1
ELSE
DEST[i+63:i] 0
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register
Vol. 2C 5-401
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );
VPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );
VPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );
VPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );
VPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );
VPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );
VPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );
VPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );
VPMOVM2B __m128i _mm_movm_epi8(__mmask16 );
VPMOVM2D __m128i _mm_movm_epi32(__mmask8 );
VPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );
VPMOVM2W __m128i _mm_movm_epi16(__mmask8 );
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E7NM
#UD
5-402 Vol. 2C
If EVEX.vvvv != 1111B.
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register
INSTRUCTION SET REFERENCE, V-Z
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
Opcode/
Instruction
Op/
En
EVEX.128.F3.0F38.W0 29 /r
VPMOVB2M k1, xmm1
EVEX.256.F3.0F38.W0 29 /r
VPMOVB2M k1, ymm1
EVEX.512.F3.0F38.W0 29 /r
VPMOVB2M k1, zmm1
EVEX.128.F3.0F38.W1 29 /r
VPMOVW2M k1, xmm1
EVEX.256.F3.0F38.W1 29 /r
VPMOVW2M k1, ymm1
EVEX.512.F3.0F38.W1 29 /r
VPMOVW2M k1, zmm1
EVEX.128.F3.0F38.W0 39 /r
VPMOVD2M k1, xmm1
EVEX.256.F3.0F38.W0 39 /r
VPMOVD2M k1, ymm1
EVEX.512.F3.0F38.W0 39 /r
VPMOVD2M k1, zmm1
EVEX.128.F3.0F38.W1 39 /r
VPMOVQ2M k1, xmm1
EVEX.256.F3.0F38.W1 39 /r
VPMOVQ2M k1, ymm1
EVEX.512.F3.0F38.W1 39 /r
VPMOVQ2M k1, zmm1
RM
64/32
bit Mode
Support
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
RM
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
AVX512VL
AVX512BW
AVX512BW
AVX512VL
AVX512BW
AVX512VL
AVX512BW
AVX512BW
AVX512VL
AVX512DQ
AVX512VL
AVX512DQ
AVX512DQ
AVX512VL
AVX512DQ
AVX512VL
AVX512DQ
AVX512DQ
Description
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding byte in XMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding byte in YMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding byte in ZMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding word in XMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding word in YMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding word in ZMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding doubleword in XMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding doubleword in YMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding doubleword in ZMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding quadword in XMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding quadword in YMM1.
Sets each bit in k1 to 1 or 0 based on the value of the most
significant bit of the corresponding quadword in ZMM1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on
the value of most significant bit of the corresponding element in the source register.
The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
Vol. 2C 5-403
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVB2M (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF SRC[i+7]
THEN
DEST[j] 1
ELSE
DEST[j] 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPMOVW2M (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF SRC[i+15]
THEN
DEST[j] 1
ELSE
DEST[j] 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPMOVD2M (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF SRC[i+31]
THEN
DEST[j] 1
ELSE
DEST[j] 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPMOVQ2M (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF SRC[i+63]
THEN
DEST[j] 1
ELSE
DEST[j] 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
5-404 Vol. 2C
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );
VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );
VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );
VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );
VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );
VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );
VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );
VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );
VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );
VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );
VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E7NM
#UD
If EVEX.vvvv != 1111B.
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
Vol. 2C 5-405
INSTRUCTION SET REFERENCE, V-Z
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
Opcode/
Instruction
Op /
En
OVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 32 /r
VPMOVQB xmm1/m16 {k1}{z}, xmm2
EVEX.128.F3.0F38.W0 22 /r
VPMOVSQB xmm1/m16 {k1}{z}, xmm2
OVM
V/V
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 12 /r
VPMOVUSQB xmm1/m16 {k1}{z}, xmm2
OVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 32 /r
VPMOVQB xmm1/m32 {k1}{z}, ymm2
OVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 22 /r
VPMOVSQB xmm1/m32 {k1}{z}, ymm2
OVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 12 /r
VPMOVUSQB xmm1/m32 {k1}{z}, ymm2
OVM
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F38.W0 32 /r
VPMOVQB xmm1/m64 {k1}{z}, zmm2
OVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 22 /r
VPMOVSQB xmm1/m64 {k1}{z}, zmm2
OVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 12 /r
VPMOVUSQB xmm1/m64 {k1}{z}, zmm2
OVM
V/V
AVX512F
Description
Converts 2 packed quad-word integers from xmm2
into 2 packed byte integers in xmm1/m16 with
truncation under writemask k1.
Converts 2 packed signed quad-word integers from
xmm2 into 2 packed signed byte integers in
xmm1/m16 using signed saturation under writemask
k1.
Converts 2 packed unsigned quad-word integers
from xmm2 into 2 packed unsigned byte integers in
xmm1/m16 using unsigned saturation under
writemask k1.
Converts 4 packed quad-word integers from ymm2
into 4 packed byte integers in xmm1/m32 with
truncation under writemask k1.
Converts 4 packed signed quad-word integers from
ymm2 into 4 packed signed byte integers in
xmm1/m32 using signed saturation under writemask
k1.
Converts 4 packed unsigned quad-word integers
from ymm2 into 4 packed unsigned byte integers in
xmm1/m32 using unsigned saturation under
writemask k1.
Converts 8 packed quad-word integers from zmm2
into 8 packed byte integers in xmm1/m64 with
truncation under writemask k1.
Converts 8 packed signed quad-word integers from
zmm2 into 8 packed signed byte integers in
xmm1/m64 using signed saturation under writemask
k1.
Converts 8 packed unsigned quad-word integers
from zmm2 into 8 packed unsigned byte integers in
xmm1/m64 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
OVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
VPMOVQB down converts 64-bit integer elements in the source operand (the second operand) into packed byte
elements using truncation. VPMOVSQB converts signed 64-bit integers into packed signed bytes using signed saturation. VPMOVUSQB convert unsigned quad-word values into unsigned byte values using unsigned saturation. The
source operand is a vector register. The destination operand is an XMM register or a memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-1:64) of the
destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-406 Vol. 2C
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
ij*8
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TruncateQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/8] 0;
VPMOVQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
ij*8
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TruncateQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
ij*8
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateSignedQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/8] 0;
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
Vol. 2C 5-407
INSTRUCTION SET REFERENCE, V-Z
VPMOVSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
ij*8
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateSignedQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
ij*8
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateUnsignedQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/8] 0;
VPMOVUSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
ij*8
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateUnsignedQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-408 Vol. 2C
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQB __m128i _mm512_cvtepi64_epi8( __m512i a);
VPMOVQB __m128i _mm512_mask_cvtepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVQB __m128i _mm512_maskz_cvtepi64_epi8( __mmask8 k, __m512i a);
VPMOVQB void _mm512_mask_cvtepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_cvtsepi64_epi8( __m512i a);
VPMOVSQB __m128i _mm512_mask_cvtsepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_maskz_cvtsepi64_epi8( __mmask8 k, __m512i a);
VPMOVSQB void _mm512_mask_cvtsepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_cvtusepi64_epi8( __m512i a);
VPMOVUSQB __m128i _mm512_mask_cvtusepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_maskz_cvtusepi64_epi8( __mmask8 k, __m512i a);
VPMOVUSQB void _mm512_mask_cvtusepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm256_cvtusepi64_epi8(__m256i a);
VPMOVUSQB __m128i _mm256_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm256_maskz_cvtusepi64_epi8( __mmask8 k, __m256i b);
VPMOVUSQB void _mm256_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm_cvtusepi64_epi8(__m128i a);
VPMOVUSQB __m128i _mm_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQB __m128i _mm_maskz_cvtusepi64_epi8( __mmask8 k, __m128i b);
VPMOVUSQB void _mm_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm256_cvtsepi64_epi8(__m256i a);
VPMOVSQB __m128i _mm256_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm256_maskz_cvtsepi64_epi8( __mmask8 k, __m256i b);
VPMOVSQB void _mm256_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm_cvtsepi64_epi8(__m128i a);
VPMOVSQB __m128i _mm_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm_maskz_cvtsepi64_epi8( __mmask8 k, __m128i b);
VPMOVSQB void _mm_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVQB __m128i _mm256_cvtepi64_epi8(__m256i a);
VPMOVQB __m128i _mm256_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVQB __m128i _mm256_maskz_cvtepi64_epi8( __mmask8 k, __m256i b);
VPMOVQB void _mm256_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVQB __m128i _mm_cvtepi64_epi8(__m128i a);
VPMOVQB __m128i _mm_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVQB __m128i _mm_maskz_cvtepi64_epi8( __mmask8 k, __m128i b);
VPMOVQB void _mm_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD
If EVEX.vvvv != 1111B.
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
Vol. 2C 5-409
INSTRUCTION SET REFERENCE, V-Z
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
Opcode/
Instruction
Op /
En
QVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 34 /r
VPMOVQW xmm1/m32 {k1}{z}, xmm2
EVEX.128.F3.0F38.W0 24 /r
VPMOVSQW xmm1/m32 {k1}{z}, xmm2
QVM
V/V
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 14 /r
VPMOVUSQW xmm1/m32 {k1}{z}, xmm2
QVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 34 /r
VPMOVQW xmm1/m64 {k1}{z}, ymm2
QVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 24 /r
VPMOVSQW xmm1/m64 {k1}{z}, ymm2
QVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 14 /r
VPMOVUSQW xmm1/m64 {k1}{z}, ymm2
QVM
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F38.W0 34 /r
VPMOVQW xmm1/m128 {k1}{z}, zmm2
QVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 24 /r
VPMOVSQW xmm1/m128 {k1}{z}, zmm2
QVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 14 /r
VPMOVUSQW xmm1/m128 {k1}{z},
zmm2
QVM
V/V
AVX512F
Description
Converts 2 packed quad-word integers from xmm2
into 2 packed word integers in xmm1/m32 with
truncation under writemask k1.
Converts 8 packed signed quad-word integers from
zmm2 into 8 packed signed word integers in
xmm1/m32 using signed saturation under writemask
k1.
Converts 2 packed unsigned quad-word integers from
xmm2 into 2 packed unsigned word integers in
xmm1/m32 using unsigned saturation under
writemask k1.
Converts 4 packed quad-word integers from ymm2
into 4 packed word integers in xmm1/m64 with
truncation under writemask k1.
Converts 4 packed signed quad-word integers from
ymm2 into 4 packed signed word integers in
xmm1/m64 using signed saturation under writemask
k1.
Converts 4 packed unsigned quad-word integers from
ymm2 into 4 packed unsigned word integers in
xmm1/m64 using unsigned saturation under
writemask k1.
Converts 8 packed quad-word integers from zmm2
into 8 packed word integers in xmm1/m128 with
truncation under writemask k1.
Converts 8 packed signed quad-word integers from
zmm2 into 8 packed signed word integers in
xmm1/m128 using signed saturation under
writemask k1.
Converts 8 packed unsigned quad-word integers from
zmm2 into 8 packed unsigned word integers in
xmm1/m128 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
QVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation.
VPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAX_VL1:128/64/32) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-410 Vol. 2C
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 16
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TruncateQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/4] 0;
VPMOVQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 16
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TruncateQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VPMOVSQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 16
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateSignedQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/4] 0;
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
Vol. 2C 5-411
INSTRUCTION SET REFERENCE, V-Z
VPMOVSQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 16
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateSignedQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VPMOVUSQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 16
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateUnsignedQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/4] 0;
VPMOVUSQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 16
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateUnsignedQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
5-412 Vol. 2C
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);
VPMOVQW __m128i _mm512_mask_cvtepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVQW __m128i _mm512_maskz_cvtepi64_epi16( __mmask8 k, __m512i a);
VPMOVQW void _mm512_mask_cvtepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);
VPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);
VPMOVSQW void _mm512_mask_cvtsepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);
VPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);
VPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD
If EVEX.vvvv != 1111B.
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
Vol. 2C 5-413
INSTRUCTION SET REFERENCE, V-Z
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
Opcode/
Instruction
Op /
En
A
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 35 /r
VPMOVQD xmm1/m128 {k1}{z}, xmm2
EVEX.128.F3.0F38.W0 25 /r
VPMOVSQD xmm1/m64 {k1}{z}, xmm2
A
V/V
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 15 /r
VPMOVUSQD xmm1/m64 {k1}{z}, xmm2
A
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 35 /r
VPMOVQD xmm1/m128 {k1}{z}, ymm2
A
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 25 /r
VPMOVSQD xmm1/m128 {k1}{z}, ymm2
A
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 15 /r
VPMOVUSQD xmm1/m128 {k1}{z}, ymm2
A
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F38.W0 35 /r
VPMOVQD ymm1/m256 {k1}{z}, zmm2
HVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 25 /r
VPMOVSQD ymm1/m256 {k1}{z}, zmm2
HVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 15 /r
VPMOVUSQD ymm1/m256 {k1}{z}, zmm2
HVM
V/V
AVX512F
Description
Converts 2 packed quad-word integers from xmm2
into 2 packed double-word integers in xmm1/m128
with truncation subject to writemask k1.
Converts 2 packed signed quad-word integers from
xmm2 into 2 packed signed double-word integers
in xmm1/m64 using signed saturation subject to
writemask k1.
Converts 2 packed unsigned quad-word integers
from xmm2 into 2 packed unsigned double-word
integers in xmm1/m64 using unsigned saturation
subject to writemask k1.
Converts 4 packed quad-word integers from ymm2
into 4 packed double-word integers in xmm1/m128
with truncation subject to writemask k1.
Converts 4 packed signed quad-word integers from
ymm2 into 4 packed signed double-word integers in
xmm1/m128 using signed saturation subject to
writemask k1.
Converts 4 packed unsigned quad-word integers
from ymm2 into 4 packed unsigned double-word
integers in xmm1/m128 using unsigned saturation
subject to writemask k1.
Converts 8 packed quad-word integers from zmm2
into 8 packed double-word integers in ymm1/m256
with truncation subject to writemask k1.
Converts 8 packed signed quad-word integers from
zmm2 into 8 packed signed double-word integers in
ymm1/m256 using signed saturation subject to
writemask k1.
Converts 8 packed unsigned quad-word integers
from zmm2 into 8 packed unsigned double-word
integers in ymm1/m256 using unsigned saturation
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed doublewords using truncation. VPMOVSQW converts signed 64-bit integers into packed signed doublewords using signed
saturation. VPMOVUSQW convert unsigned quad-word values into unsigned double-word values using unsigned
saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted doubleword elements are written to the destination operand (the first operand) from the leastsignificant doubleword. Doubleword elements of the destination operand are updated according to the writemask.
Bits (MAX_VL-1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-414 Vol. 2C
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TruncateQuadWordToDWord (SRC[m+63:m])
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TruncateQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SaturateSignedQuadWordToDWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
Vol. 2C 5-415
INSTRUCTION SET REFERENCE, V-Z
VPMOVSQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SaturateSignedQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVUSQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
m j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-416 Vol. 2C
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQD __m256i _mm512_cvtepi64_epi32( __m512i a);
VPMOVQD __m256i _mm512_mask_cvtepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVQD __m256i _mm512_maskz_cvtepi64_epi32( __mmask8 k, __m512i a);
VPMOVQD void _mm512_mask_cvtepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_cvtsepi64_epi32( __m512i a);
VPMOVSQD __m256i _mm512_mask_cvtsepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_maskz_cvtsepi64_epi32( __mmask8 k, __m512i a);
VPMOVSQD void _mm512_mask_cvtsepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_cvtusepi64_epi32( __m512i a);
VPMOVUSQD __m256i _mm512_mask_cvtusepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_maskz_cvtusepi64_epi32( __mmask8 k, __m512i a);
VPMOVUSQD void _mm512_mask_cvtusepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD
If EVEX.vvvv != 1111B.
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
Vol. 2C 5-417
INSTRUCTION SET REFERENCE, V-Z
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
Opcode/
Instruction
Op /
En
QVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 31 /r
VPMOVDB xmm1/m32 {k1}{z}, xmm2
EVEX.128.F3.0F38.W0 21 /r
VPMOVSDB xmm1/m32 {k1}{z}, xmm2
QVM
V/V
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 11 /r
VPMOVUSDB xmm1/m32 {k1}{z},
xmm2
QVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 31 /r
VPMOVDB xmm1/m64 {k1}{z}, ymm2
QVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 21 /r
VPMOVSDB xmm1/m64 {k1}{z}, ymm2
QVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 11 /r
VPMOVUSDB xmm1/m64 {k1}{z}, ymm2
QVM
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F38.W0 31 /r
VPMOVDB xmm1/m128 {k1}{z}, zmm2
QVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 21 /r
VPMOVSDB xmm1/m128 {k1}{z}, zmm2
QVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 11 /r
VPMOVUSDB xmm1/m128 {k1}{z},
zmm2
QVM
V/V
AVX512F
Description
Converts 4 packed double-word integers from xmm2
into 4 packed byte integers in xmm1/m32 with
truncation under writemask k1.
Converts 4 packed signed double-word integers from
xmm2 into 4 packed signed byte integers in
xmm1/m32 using signed saturation under writemask
k1.
Converts 4 packed unsigned double-word integers
from xmm2 into 4 packed unsigned byte integers in
xmm1/m32 using unsigned saturation under
writemask k1.
Converts 8 packed double-word integers from ymm2
into 8 packed byte integers in xmm1/m64 with
truncation under writemask k1.
Converts 8 packed signed double-word integers from
ymm2 into 8 packed signed byte integers in
xmm1/m64 using signed saturation under writemask
k1.
Converts 8 packed unsigned double-word integers
from ymm2 into 8 packed unsigned byte integers in
xmm1/m64 using unsigned saturation under
writemask k1.
Converts 16 packed double-word integers from zmm2
into 16 packed byte integers in xmm1/m128 with
truncation under writemask k1.
Converts 16 packed signed double-word integers
from zmm2 into 16 packed signed byte integers in
xmm1/m128 using signed saturation under
writemask k1.
Converts 16 packed unsigned double-word integers
from zmm2 into 16 packed unsigned byte integers in
xmm1/m128 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
QVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
VPMOVDB down converts 32-bit integer elements in the source operand (the second operand) into packed bytes
using truncation. VPMOVSDB converts signed 32-bit integers into packed signed bytes using signed saturation.
VPMOVUSDB convert unsigned double-word values into unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL1:128/64/32) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-418 Vol. 2C
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
ij*8
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TruncateDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/4] 0;
VPMOVDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
ij*8
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TruncateDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
ij*8
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateSignedDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/4] 0;
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
Vol. 2C 5-419
INSTRUCTION SET REFERENCE, V-Z
VPMOVSDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
ij*8
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateSignedDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
ij*8
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/4] 0;
VPMOVUSDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
ij*8
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-420 Vol. 2C
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDB __m128i _mm512_cvtepi32_epi8( __m512i a);
VPMOVDB __m128i _mm512_mask_cvtepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVDB __m128i _mm512_maskz_cvtepi32_epi8( __mmask16 k, __m512i a);
VPMOVDB void _mm512_mask_cvtepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_cvtsepi32_epi8( __m512i a);
VPMOVSDB __m128i _mm512_mask_cvtsepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_maskz_cvtsepi32_epi8( __mmask16 k, __m512i a);
VPMOVSDB void _mm512_mask_cvtsepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_cvtusepi32_epi8( __m512i a);
VPMOVUSDB __m128i _mm512_mask_cvtusepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_maskz_cvtusepi32_epi8( __mmask16 k, __m512i a);
VPMOVUSDB void _mm512_mask_cvtusepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm256_cvtusepi32_epi8(__m256i a);
VPMOVUSDB __m128i _mm256_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm256_maskz_cvtusepi32_epi8( __mmask8 k, __m256i b);
VPMOVUSDB void _mm256_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm_cvtusepi32_epi8(__m128i a);
VPMOVUSDB __m128i _mm_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDB __m128i _mm_maskz_cvtusepi32_epi8( __mmask8 k, __m128i b);
VPMOVUSDB void _mm_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm256_cvtsepi32_epi8(__m256i a);
VPMOVSDB __m128i _mm256_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm256_maskz_cvtsepi32_epi8( __mmask8 k, __m256i b);
VPMOVSDB void _mm256_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm_cvtsepi32_epi8(__m128i a);
VPMOVSDB __m128i _mm_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm_maskz_cvtsepi32_epi8( __mmask8 k, __m128i b);
VPMOVSDB void _mm_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVDB __m128i _mm256_cvtepi32_epi8(__m256i a);
VPMOVDB __m128i _mm256_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVDB __m128i _mm256_maskz_cvtepi32_epi8( __mmask8 k, __m256i b);
VPMOVDB void _mm256_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVDB __m128i _mm_cvtepi32_epi8(__m128i a);
VPMOVDB __m128i _mm_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVDB __m128i _mm_maskz_cvtepi32_epi8( __mmask8 k, __m128i b);
VPMOVDB void _mm_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD
If EVEX.vvvv != 1111B.
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
Vol. 2C 5-421
INSTRUCTION SET REFERENCE, V-Z
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
Opcode/
Instruction
Op /
En
HVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 33 /r
VPMOVDW xmm1/m64 {k1}{z}, xmm2
EVEX.128.F3.0F38.W0 23 /r
VPMOVSDW xmm1/m64 {k1}{z}, xmm2
HVM
V/V
AVX512VL
AVX512F
EVEX.128.F3.0F38.W0 13 /r
VPMOVUSDW xmm1/m64 {k1}{z}, xmm2
HVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 33 /r
VPMOVDW xmm1/m128 {k1}{z}, ymm2
HVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 23 /r
VPMOVSDW xmm1/m128 {k1}{z}, ymm2
HVM
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F38.W0 13 /r
VPMOVUSDW xmm1/m128 {k1}{z},
ymm2
HVM
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F38.W0 33 /r
VPMOVDW ymm1/m256 {k1}{z}, zmm2
HVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 23 /r
VPMOVSDW ymm1/m256 {k1}{z}, zmm2
HVM
V/V
AVX512F
EVEX.512.F3.0F38.W0 13 /r
VPMOVUSDW ymm1/m256 {k1}{z},
zmm2
HVM
V/V
AVX512F
Description
Converts 4 packed double-word integers from
xmm2 into 4 packed word integers in xmm1/m64
with truncation under writemask k1.
Converts 4 packed signed double-word integers
from xmm2 into 4 packed signed word integers in
ymm1/m64 using signed saturation under
writemask k1.
Converts 4 packed unsigned double-word integers
from xmm2 into 4 packed unsigned word integers
in xmm1/m64 using unsigned saturation under
writemask k1.
Converts 8 packed double-word integers from
ymm2 into 8 packed word integers in xmm1/m128
with truncation under writemask k1.
Converts 8 packed signed double-word integers
from ymm2 into 8 packed signed word integers in
xmm1/m128 using signed saturation under
writemask k1.
Converts 8 packed unsigned double-word integers
from ymm2 into 8 packed unsigned word integers
in xmm1/m128 using unsigned saturation under
writemask k1.
Converts 16 packed double-word integers from
zmm2 into 16 packed word integers in
ymm1/m256 with truncation under writemask k1.
Converts 16 packed signed double-word integers
from zmm2 into 16 packed signed word integers in
ymm1/m256 using signed saturation under
writemask k1.
Converts 16 packed unsigned double-word integers
from zmm2 into 16 packed unsigned word integers
in ymm1/m256 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
VPMOVDW down converts 32-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSDW converts signed 32-bit integers into packed signed words using signed saturation.
VPMOVUSDW convert unsigned double-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAX_VL1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-422 Vol. 2C
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TruncateDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] TruncateDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VPMOVSDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateSignedDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
Vol. 2C 5-423
INSTRUCTION SET REFERENCE, V-Z
VPMOVSDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateSignedDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VPMOVUSDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVUSDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 16
m j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
5-424 Vol. 2C
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDW __m256i _mm512_cvtepi32_epi16( __m512i a);
VPMOVDW __m256i _mm512_mask_cvtepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVDW __m256i _mm512_maskz_cvtepi32_epi16( __mmask16 k, __m512i a);
VPMOVDW void _mm512_mask_cvtepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_cvtsepi32_epi16( __m512i a);
VPMOVSDW __m256i _mm512_mask_cvtsepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_maskz_cvtsepi32_epi16( __mmask16 k, __m512i a);
VPMOVSDW void _mm512_mask_cvtsepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_cvtusepi32_epi16 __m512i a);
VPMOVUSDW __m256i _mm512_mask_cvtusepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_maskz_cvtusepi32_epi16( __mmask16 k, __m512i a);
VPMOVUSDW void _mm512_mask_cvtusepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m128i _mm256_cvtusepi32_epi16(__m256i a);
VPMOVUSDW __m128i _mm256_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm256_maskz_cvtusepi32_epi16( __mmask8 k, __m256i b);
VPMOVUSDW void _mm256_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm_cvtusepi32_epi16(__m128i a);
VPMOVUSDW __m128i _mm_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDW __m128i _mm_maskz_cvtusepi32_epi16( __mmask8 k, __m128i b);
VPMOVUSDW void _mm_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm256_cvtsepi32_epi16(__m256i a);
VPMOVSDW __m128i _mm256_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm256_maskz_cvtsepi32_epi16( __mmask8 k, __m256i b);
VPMOVSDW void _mm256_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm_cvtsepi32_epi16(__m128i a);
VPMOVSDW __m128i _mm_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm_maskz_cvtsepi32_epi16( __mmask8 k, __m128i b);
VPMOVSDW void _mm_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVDW __m128i _mm256_cvtepi32_epi16(__m256i a);
VPMOVDW __m128i _mm256_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVDW __m128i _mm256_maskz_cvtepi32_epi16( __mmask8 k, __m256i b);
VPMOVDW void _mm256_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVDW __m128i _mm_cvtepi32_epi16(__m128i a);
VPMOVDW __m128i _mm_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVDW __m128i _mm_maskz_cvtepi32_epi16( __mmask8 k, __m128i b);
VPMOVDW void _mm_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD
If EVEX.vvvv != 1111B.
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
Vol. 2C 5-425
INSTRUCTION SET REFERENCE, V-Z
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
Opcode/
Instruction
Op /
En
HVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
EVEX.128.F3.0F38.W0 30 /r
VPMOVWB xmm1/m64 {k1}{z}, xmm2
EVEX.128.F3.0F38.W0 20 /r
VPMOVSWB xmm1/m64 {k1}{z},
xmm2
EVEX.128.F3.0F38.W0 10 /r
VPMOVUSWB xmm1/m64 {k1}{z},
xmm2
EVEX.256.F3.0F38.W0 30 /r
VPMOVWB xmm1/m128 {k1}{z},
ymm2
EVEX.256.F3.0F38.W0 20 /r
VPMOVSWB xmm1/m128 {k1}{z},
ymm2
EVEX.256.F3.0F38.W0 10 /r
VPMOVUSWB xmm1/m128 {k1}{z},
ymm2
EVEX.512.F3.0F38.W0 30 /r
VPMOVWB ymm1/m256 {k1}{z},
zmm2
EVEX.512.F3.0F38.W0 20 /r
VPMOVSWB ymm1/m256 {k1}{z},
zmm2
EVEX.512.F3.0F38.W0 10 /r
VPMOVUSWB ymm1/m256 {k1}{z},
zmm2
HVM
V/V
AVX512VL
AVX512BW
HVM
V/V
AVX512VL
AVX512BW
HVM
V/V
AVX512VL
AVX512BW
HVM
V/V
AVX512VL
AVX512BW
HVM
V/V
AVX512VL
AVX512BW
HVM
V/V
AVX512BW
HVM
V/V
AVX512BW
HVM
V/V
AVX512BW
Description
Converts 8 packed word integers from xmm2 into 8
packed bytes in xmm1/m64 with truncation under
writemask k1.
Converts 8 packed signed word integers from xmm2
into 8 packed signed bytes in xmm1/m64 using
signed saturation under writemask k1.
Converts 8 packed unsigned word integers from
xmm2 into 8 packed unsigned bytes in 8mm1/m64
using unsigned saturation under writemask k1.
Converts 16 packed word integers from ymm2 into
16 packed bytes in xmm1/m128 with truncation
under writemask k1.
Converts 16 packed signed word integers from ymm2
into 16 packed signed bytes in xmm1/m128 using
signed saturation under writemask k1.
Converts 16 packed unsigned word integers from
ymm2 into 16 packed unsigned bytes in xmm1/m128
using unsigned saturation under writemask k1.
Converts 32 packed word integers from zmm2 into
32 packed bytes in ymm1/m256 with truncation
under writemask k1.
Converts 32 packed signed word integers from zmm2
into 32 packed signed bytes in ymm1/m256 using
signed saturation under writemask k1.
Converts 32 packed unsigned word integers from
zmm2 into 32 packed unsigned bytes in ymm1/m256
using unsigned saturation under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
HVM
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
VPMOVWB down converts 16-bit integers into packed bytes using truncation. VPMOVSWB converts signed 16-bit
integers into packed signed bytes using signed saturation. VPMOVUSWB convert unsigned word values into
unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL1:256/128/64) of the register destination are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-426 Vol. 2C
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
INSTRUCTION SET REFERENCE, V-Z
Operation
VPMOVWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO Kl-1
ij*8
m j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TruncateWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO Kl-1
ij*8
m j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] TruncateWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO Kl-1
ij*8
m j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateSignedWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
Vol. 2C 5-427
INSTRUCTION SET REFERENCE, V-Z
VPMOVSWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO Kl-1
ij*8
m j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateSignedWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO Kl-1
ij*8
m j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateUnsignedWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2] 0;
VPMOVUSWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO Kl-1
ij*8
m j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] SaturateUnsignedWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-428 Vol. 2C
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVUSWB __m256i _mm512_cvtusepi16_epi8(__m512i a);
VPMOVUSWB __m256i _mm512_mask_cvtusepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVUSWB __m256i _mm512_maskz_cvtusepi16_epi8( __mmask32 k, __m512i b);
VPMOVUSWB void _mm512_mask_cvtusepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_cvtsepi16_epi8(__m512i a);
VPMOVSWB __m256i _mm512_mask_cvtsepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_maskz_cvtsepi16_epi8( __mmask32 k, __m512i b);
VPMOVSWB void _mm512_mask_cvtsepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_cvtepi16_epi8(__m512i a);
VPMOVWB __m256i _mm512_mask_cvtepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_maskz_cvtepi16_epi8( __mmask32 k, __m512i b);
VPMOVWB void _mm512_mask_cvtepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVUSWB __m128i _mm256_cvtusepi16_epi8(__m256i a);
VPMOVUSWB __m128i _mm256_mask_cvtusepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm256_maskz_cvtusepi16_epi8( __mmask16 k, __m256i b);
VPMOVUSWB void _mm256_mask_cvtusepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm_cvtusepi16_epi8(__m128i a);
VPMOVUSWB __m128i _mm_mask_cvtusepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSWB __m128i _mm_maskz_cvtusepi16_epi8( __mmask8 k, __m128i b);
VPMOVUSWB void _mm_mask_cvtusepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm256_cvtsepi16_epi8(__m256i a);
VPMOVSWB __m128i _mm256_mask_cvtsepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm256_maskz_cvtsepi16_epi8( __mmask16 k, __m256i b);
VPMOVSWB void _mm256_mask_cvtsepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm_cvtsepi16_epi8(__m128i a);
VPMOVSWB __m128i _mm_mask_cvtsepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm_maskz_cvtsepi16_epi8( __mmask8 k, __m128i b);
VPMOVSWB void _mm_mask_cvtsepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVWB __m128i _mm256_cvtepi16_epi8(__m256i a);
VPMOVWB __m128i _mm256_mask_cvtepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVWB __m128i _mm256_maskz_cvtepi16_epi8( __mmask16 k, __m256i b);
VPMOVWB void _mm256_mask_cvtepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVWB __m128i _mm_cvtepi16_epi8(__m128i a);
VPMOVWB __m128i _mm_mask_cvtepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVWB __m128i _mm_maskz_cvtepi16_epi8( __mmask8 k, __m128i b);
VPMOVWB void _mm_mask_cvtepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6NF
#UD
If EVEX.vvvv != 1111B.
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
Vol. 2C 5-429
INSTRUCTION SET REFERENCE, V-Z
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left
Opcode/
Instruction
Op / En
FV-RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W0 15 /r
VPROLVD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDD.128.66.0F.W0 72 /1 ib
VPROLD xmm1 {k1}{z},
xmm2/m128/m32bcst, imm8
EVEX.NDS.128.66.0F38.W1 15 /r
VPROLVQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDD.128.66.0F.W1 72 /1 ib
VPROLQ xmm1 {k1}{z},
xmm2/m128/m64bcst, imm8
EVEX.NDS.256.66.0F38.W0 15 /r
VPROLVD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDD.256.66.0F.W0 72 /1 ib
VPROLD ymm1 {k1}{z},
ymm2/m256/m32bcst, imm8
EVEX.NDS.256.66.0F38.W1 15 /r
VPROLVQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDD.256.66.0F.W1 72 /1 ib
VPROLQ ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
EVEX.NDS.512.66.0F38.W0 15 /r
VPROLVD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512F
EVEX.NDD.512.66.0F.W0 72 /1 ib
VPROLD zmm1 {k1}{z},
zmm2/m512/m32bcst, imm8
EVEX.NDS.512.66.0F38.W1 15 /r
VPROLVQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
EVEX.NDD.512.66.0F.W1 72 /1 ib
VPROLQ zmm1 {k1}{z},
zmm2/m512/m64bcst, imm8
FV-VMI
V/V
AVX512F
FV-RVM
V/V
AVX512F
FV-VMI
V/V
AVX512F
Description
Rotate doublewords in xmm2 left by count in the
corresponding element of xmm3/m128/m32bcst.
Result written to xmm1 under writemask k1.
Rotate doublewords in xmm2/m128/m32bcst left
by imm8. Result written to xmm1 using
writemask k1.
Rotate quadwords in xmm2 left by count in the
corresponding element of xmm3/m128/m64bcst.
Result written to xmm1 under writemask k1.
Rotate quadwords in xmm2/m128/m64bcst left
by imm8. Result written to xmm1 using
writemask k1.
Rotate doublewords in ymm2 left by count in the
corresponding element of ymm3/m256/m32bcst.
Result written to ymm1 under writemask k1.
Rotate doublewords in ymm2/m256/m32bcst left
by imm8. Result written to ymm1 using
writemask k1.
Rotate quadwords in ymm2 left by count in the
corresponding element of ymm3/m256/m64bcst.
Result written to ymm1 under writemask k1.
Rotate quadwords in ymm2/m256/m64bcst left
by imm8. Result written to ymm1 using
writemask k1.
Rotate left of doublewords in zmm2 by count in
the corresponding element of
zmm3/m512/m32bcst. Result written to zmm1
using writemask k1.
Rotate left of doublewords in
zmm3/m512/m32bcst by imm8. Result written to
zmm1 using writemask k1.
Rotate quadwords in zmm2 left by count in the
corresponding element of zmm3/m512/m64bcst.
Result written to zmm1under writemask k1.
Rotate quadwords in zmm2/m512/m64bcst left
by imm8. Result written to zmm1 using
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV-VMI
VEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
5-430 Vol. 2C
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left
INSTRUCTION SET REFERENCE, V-Z
Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the left
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.
Operation
LEFT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC modulo 32;
DEST[31:0] (SRC << COUNT) | (SRC >> (32 - COUNT));
LEFT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC modulo 64;
DEST[63:0] (SRC << COUNT) | (SRC >> (64 - COUNT));
VPROLD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] LEFT_ROTATE_DWORDS(SRC1[31:0], imm8)
ELSE DEST[i+31:i] LEFT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left
Vol. 2C 5-431
INSTRUCTION SET REFERENCE, V-Z
VPROLVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPROLQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] LEFT_ROTATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] LEFT_ROTATE_QWORDS(SRC1[i+63:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-432 Vol. 2C
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left
INSTRUCTION SET REFERENCE, V-Z
VPROLVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left
Vol. 2C 5-433
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPROLD __m512i _mm512_rol_epi32(__m512i a, int imm);
VPROLD __m512i _mm512_mask_rol_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPROLD __m512i _mm512_maskz_rol_epi32( __mmask16 k, __m512i a, int imm);
VPROLD __m256i _mm256_rol_epi32(__m256i a, int imm);
VPROLD __m256i _mm256_mask_rol_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLD __m256i _mm256_maskz_rol_epi32( __mmask8 k, __m256i a, int imm);
VPROLD __m128i _mm_rol_epi32(__m128i a, int imm);
VPROLD __m128i _mm_mask_rol_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLD __m128i _mm_maskz_rol_epi32( __mmask8 k, __m128i a, int imm);
VPROLQ __m512i _mm512_rol_epi64(__m512i a, int imm);
VPROLQ __m512i _mm512_mask_rol_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPROLQ __m512i _mm512_maskz_rol_epi64(__mmask8 k, __m512i a, int imm);
VPROLQ __m256i _mm256_rol_epi64(__m256i a, int imm);
VPROLQ __m256i _mm256_mask_rol_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLQ __m256i _mm256_maskz_rol_epi64( __mmask8 k, __m256i a, int imm);
VPROLQ __m128i _mm_rol_epi64(__m128i a, int imm);
VPROLQ __m128i _mm_mask_rol_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLQ __m128i _mm_maskz_rol_epi64( __mmask8 k, __m128i a, int imm);
VPROLVD __m512i _mm512_rolv_epi32(__m512i a, __m512i cnt);
VPROLVD __m512i _mm512_mask_rolv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPROLVD __m512i _mm512_maskz_rolv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPROLVD __m256i _mm256_rolv_epi32(__m256i a, __m256i cnt);
VPROLVD __m256i _mm256_mask_rolv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVD __m256i _mm256_maskz_rolv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPROLVD __m128i _mm_rolv_epi32(__m128i a, __m128i cnt);
VPROLVD __m128i _mm_mask_rolv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVD __m128i _mm_maskz_rolv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPROLVQ __m512i _mm512_rolv_epi64(__m512i a, __m512i cnt);
VPROLVQ __m512i _mm512_mask_rolv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPROLVQ __m512i _mm512_maskz_rolv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPROLVQ __m256i _mm256_rolv_epi64(__m256i a, __m256i cnt);
VPROLVQ __m256i _mm256_mask_rolv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVQ __m256i _mm256_maskz_rolv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPROLVQ __m128i _mm_rolv_epi64(__m128i a, __m128i cnt);
VPROLVQ __m128i _mm_mask_rolv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVQ __m128i _mm_maskz_rolv_epi64(__mmask8 k, __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.
5-434 Vol. 2C
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left
INSTRUCTION SET REFERENCE, V-Z
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right
Opcode/
Instruction
Op / En
FV-RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W0 14 /r
VPRORVD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDD.128.66.0F.W0 72 /0 ib
VPRORD xmm1 {k1}{z},
xmm2/m128/m32bcst, imm8
EVEX.NDS.128.66.0F38.W1 14 /r
VPRORVQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDD.128.66.0F.W1 72 /0 ib
VPRORQ xmm1 {k1}{z},
xmm2/m128/m64bcst, imm8
EVEX.NDS.256.66.0F38.W0 14 /r
VPRORVD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
EVEX.NDD.256.66.0F.W0 72 /0 ib
VPRORD ymm1 {k1}{z},
ymm2/m256/m32bcst, imm8
EVEX.NDS.256.66.0F38.W1 14 /r
VPRORVQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDD.256.66.0F.W1 72 /0 ib
VPRORQ ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
EVEX.NDS.512.66.0F38.W0 14 /r
VPRORVD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512VL
AVX512F
FV-VMI
V/V
AVX512VL
AVX512F
FV-RVM
V/V
AVX512F
EVEX.NDD.512.66.0F.W0 72 /0 ib
VPRORD zmm1 {k1}{z},
zmm2/m512/m32bcst, imm8
EVEX.NDS.512.66.0F38.W1 14 /r
VPRORVQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
EVEX.NDD.512.66.0F.W1 72 /0 ib
VPRORQ zmm1 {k1}{z},
zmm2/m512/m64bcst, imm8
FV-VMI
V/V
AVX512F
FV-RVM
V/V
AVX512F
FV-VMI
V/V
AVX512F
Description
Rotate doublewords in xmm2 right by count in
the corresponding element of
xmm3/m128/m32bcst, store result using
writemask k1.
Rotate doublewords in xmm2/m128/m32bcst
right by imm8, store result using writemask k1.
Rotate quadwords in xmm2 right by count in the
corresponding element of xmm3/m128/m64bcst,
store result using writemask k1.
Rotate quadwords in xmm2/m128/m64bcst right
by imm8, store result using writemask k1.
Rotate doublewords in ymm2 right by count in
the corresponding element of
ymm3/m256/m32bcst, store using result
writemask k1.
Rotate doublewords in ymm2/m256/m32bcst
right by imm8, store result using writemask k1.
Rotate quadwords in ymm2 right by count in the
corresponding element of ymm3/m256/m64bcst,
store result using writemask k1.
Rotate quadwords in ymm2/m256/m64bcst right
by imm8, store result using writemask k1.
Rotate doublewords in zmm2 right by count in
the corresponding element of
zmm3/m512/m32bcst, store result using
writemask k1.
Rotate doublewords in zmm2/m512/m32bcst
right by imm8, store result using writemask k1.
Rotate quadwords in zmm2 right by count in the
corresponding element of zmm3/m512/m64bcst,
store result using writemask k1.
Rotate quadwords in zmm2/m512/m64bcst right
by imm8, store result using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV-VMI
VEX.vvvv (w)
ModRM:r/m (R)
Imm8
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right
Vol. 2C 5-435
INSTRUCTION SET REFERENCE, V-Z
Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the right
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.
Operation
RIGHT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC modulo 32;
DEST[31:0] (SRC >> COUNT) | (SRC << (32 - COUNT));
RIGHT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT COUNT_SRC modulo 64;
DEST[63:0] (SRC >> COUNT) | (SRC << (64 - COUNT));
VPRORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] RIGHT_ROTATE_DWORDS( SRC1[31:0], imm8)
ELSE DEST[i+31:i] RIGHT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-436 Vol. 2C
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right
INSTRUCTION SET REFERENCE, V-Z
VPRORVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VPRORQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] RIGHT_ROTATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] RIGHT_ROTATE_QWORDS(SRC1[i+63:i], imm8])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right
Vol. 2C 5-437
INSTRUCTION SET REFERENCE, V-Z
VPRORVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-438 Vol. 2C
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPRORD __m512i _mm512_ror_epi32(__m512i a, int imm);
VPRORD __m512i _mm512_mask_ror_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPRORD __m512i _mm512_maskz_ror_epi32( __mmask16 k, __m512i a, int imm);
VPRORD __m256i _mm256_ror_epi32(__m256i a, int imm);
VPRORD __m256i _mm256_mask_ror_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORD __m256i _mm256_maskz_ror_epi32( __mmask8 k, __m256i a, int imm);
VPRORD __m128i _mm_ror_epi32(__m128i a, int imm);
VPRORD __m128i _mm_mask_ror_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORD __m128i _mm_maskz_ror_epi32( __mmask8 k, __m128i a, int imm);
VPRORQ __m512i _mm512_ror_epi64(__m512i a, int imm);
VPRORQ __m512i _mm512_mask_ror_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPRORQ __m512i _mm512_maskz_ror_epi64(__mmask8 k, __m512i a, int imm);
VPRORQ __m256i _mm256_ror_epi64(__m256i a, int imm);
VPRORQ __m256i _mm256_mask_ror_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORQ __m256i _mm256_maskz_ror_epi64( __mmask8 k, __m256i a, int imm);
VPRORQ __m128i _mm_ror_epi64(__m128i a, int imm);
VPRORQ __m128i _mm_mask_ror_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORQ __m128i _mm_maskz_ror_epi64( __mmask8 k, __m128i a, int imm);
VPRORVD __m512i _mm512_rorv_epi32(__m512i a, __m512i cnt);
VPRORVD __m512i _mm512_mask_rorv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPRORVD __m512i _mm512_maskz_rorv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPRORVD __m256i _mm256_rorv_epi32(__m256i a, __m256i cnt);
VPRORVD __m256i _mm256_mask_rorv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVD __m256i _mm256_maskz_rorv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPRORVD __m128i _mm_rorv_epi32(__m128i a, __m128i cnt);
VPRORVD __m128i _mm_mask_rorv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVD __m128i _mm_maskz_rorv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPRORVQ __m512i _mm512_rorv_epi64(__m512i a, __m512i cnt);
VPRORVQ __m512i _mm512_mask_rorv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPRORVQ __m512i _mm512_maskz_rorv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPRORVQ __m256i _mm256_rorv_epi64(__m256i a, __m256i cnt);
VPRORVQ __m256i _mm256_mask_rorv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVQ __m256i _mm256_maskz_rorv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPRORVQ __m128i _mm_rorv_epi64(__m128i a, __m128i cnt);
VPRORVQ __m128i _mm_mask_rorv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVQ __m128i _mm_maskz_rorv_epi64(__mmask8 k, __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right
Vol. 2C 5-439
INSTRUCTION SET REFERENCE, V-Z
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed
Qword with Signed Dword, Signed Qword Indices
Opcode/
Instruction
Op/
En
EVEX.128.66.0F38.W0 A0 /vsib
VPSCATTERDD vm32x {k1}, xmm1
EVEX.256.66.0F38.W0 A0 /vsib
VPSCATTERDD vm32y {k1}, ymm1
EVEX.512.66.0F38.W0 A0 /vsib
VPSCATTERDD vm32z {k1}, zmm1
EVEX.128.66.0F38.W1 A0 /vsib
VPSCATTERDQ vm32x {k1}, xmm1
EVEX.256.66.0F38.W1 A0 /vsib
VPSCATTERDQ vm32x {k1}, ymm1
EVEX.512.66.0F38.W1 A0 /vsib
VPSCATTERDQ vm32y {k1}, zmm1
EVEX.128.66.0F38.W0 A1 /vsib
VPSCATTERQD vm64x {k1}, xmm1
EVEX.256.66.0F38.W0 A1 /vsib
VPSCATTERQD vm64y {k1}, xmm1
EVEX.512.66.0F38.W0 A1 /vsib
VPSCATTERQD vm64z {k1}, ymm1
EVEX.128.66.0F38.W1 A1 /vsib
VPSCATTERQQ vm64x {k1}, xmm1
EVEX.256.66.0F38.W1 A1 /vsib
VPSCATTERQQ vm64y {k1}, ymm1
EVEX.512.66.0F38.W1 A1 /vsib
VPSCATTERQQ vm64z {k1}, zmm1
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Using signed dword indices, scatter dword values to
memory using writemask k1.
Using signed dword indices, scatter dword values to
memory using writemask k1.
Using signed dword indices, scatter dword values to
memory using writemask k1.
Using signed dword indices, scatter qword values to
memory using writemask k1.
Using signed dword indices, scatter qword values to
memory using writemask k1.
Using signed dword indices, scatter qword values to
memory using writemask k1.
Using signed qword indices, scatter dword values to
memory using writemask k1.
Using signed qword indices, scatter dword values to
memory using writemask k1.
Using signed qword indices, scatter dword values to
memory using writemask k1.
Using signed qword indices, scatter qword values to
memory using writemask k1.
Using signed qword indices, scatter qword values to
memory using writemask k1.
Using signed qword indices, scatter qword values to
memory using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
ModRM:reg (r)
NA
NA
Description
Stores up to 16 elements (8 elements for qword indices) in doubleword vector or 8 elements in quadword vector to
the memory locations pointed by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The
elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements
will only be stored if their corresponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register are partially updated. If any traps or interrupts are pending from already scattered
elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.
Note that:
•
Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to
MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not
overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory
ordering model. Note that this does not account for non-overlapping indices that map into the same physical
address locations.
5-440 Vol. 2C
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
INSTRUCTION SET REFERENCE, V-Z
•
•
If two or more destination indices completely overlap, the “earlier” write(s) may be skipped.
•
Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination ZMM will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
Not valid with 16-bit effective addresses. Will deliver a #UD fault.
If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before
the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this
instruction, the new instruction will be executed, and the scatter will not complete.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits
are ignored.
The instruction will #UD fault if the k0 mask register is specified.
The instruction will #UD fault if EVEX.Z = 1.
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C 5-441
INSTRUCTION SET REFERENCE, V-Z
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
5-442 Vol. 2C
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
INSTRUCTION SET REFERENCE, V-Z
VPSCATTERDD (EVEX encoded versions)
(KL, VL)= (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] SRC[i+31:i]
k1[j] 0
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VPSCATTERDQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] SRC[i+63:i]
k1[j] 0
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VPSCATTERQD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] SRC[i+31:i]
k1[j] 0
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VPSCATTERQQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[j+63:j]) * SCALE + DISP] SRC[i+63:i]
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C 5-443
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPSCATTERDD void _mm512_i32scatter_epi32(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_i32scatter_epi32(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_i32scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDD void _mm512_mask_i32scatter_epi32(void * base, __mmask16 k, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_mask_i32scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_mask_i32scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_i32scatter_epi64(void * base, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_i32scatter_epi64(void * base, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_i32scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_mask_i32scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_i64scatter_epi32(void * base, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_i64scatter_epi32(void * base, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_i64scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_mask_i64scatter_epi32(void * base, __mmask8 k, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_mask_i64scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_mask_i64scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERQQ void _mm512_i64scatter_epi64(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_i64scatter_epi64(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_i64scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQQ void _mm512_mask_i64scatter_epi64(void * base, __mmask8 k, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_mask_i64scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_mask_i64scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12.
5-444 Vol. 2C
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
INSTRUCTION SET REFERENCE, V-Z
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
VEX.NDS.128.66.0F38.W0 47 /r
VPSLLVD xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F38.W1 47 /r
VPSLLVQ xmm1, xmm2, xmm3/m128
RVM
V/V
AVX2
VEX.NDS.256.66.0F38.W0 47 /r
VPSLLVD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
VEX.NDS.256.66.0F38.W1 47 /r
VPSLLVQ ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.W1 12 /r
VPSLLVW xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.W1 12 /r
VPSLLVW ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.W1 12 /r
VPSLLVW zmm1 {k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38.W0 47 /r
VPSLLVD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 47 /r
VPSLLVD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 47 /r
VPSLLVD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 47 /r
VPSLLVQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 47 /r
VPSLLVQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 47 /r
VPSLLVQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Shift doublewords in xmm2 left by amount specified in
the corresponding element of xmm3/m128 while
shifting in 0s.
Shift quadwords in xmm2 left by amount specified in
the corresponding element of xmm3/m128 while
shifting in 0s.
Shift doublewords in ymm2 left by amount specified in
the corresponding element of ymm3/m256 while
shifting in 0s.
Shift quadwords in ymm2 left by amount specified in
the corresponding element of ymm3/m256 while
shifting in 0s.
Shift words in xmm2 left by amount specified in the
corresponding element of xmm3/m128 while shifting
in 0s using writemask k1.
Shift words in ymm2 left by amount specified in the
corresponding element of ymm3/m256 while shifting
in 0s using writemask k1.
Shift words in zmm2 left by amount specified in the
corresponding element of zmm3/m512 while shifting
in 0s using writemask k1.
Shift doublewords in xmm2 left by amount specified in
the corresponding element of xmm3/m128/m32bcst
while shifting in 0s using writemask k1.
Shift doublewords in ymm2 left by amount specified in
the corresponding element of ymm3/m256/m32bcst
while shifting in 0s using writemask k1.
Shift doublewords in zmm2 left by amount specified in
the corresponding element of zmm3/m512/m32bcst
while shifting in 0s using writemask k1.
Shift quadwords in xmm2 left by amount specified in
the corresponding element of xmm3/m128/m64bcst
while shifting in 0s using writemask k1.
Shift quadwords in ymm2 left by amount specified in
the corresponding element of ymm3/m256/m64bcst
while shifting in 0s using writemask k1.
Shift quadwords in zmm2 left by amount specified in
the corresponding element of zmm3/m512/m64bcst
while shifting in 0s using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
Vol. 2C 5-445
INSTRUCTION SET REFERENCE, V-Z
Description
Shifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the
left by the count value of respective data elements in the second source operand. As the bits in the data elements
are shifted left, the empty low-order bits are cleared (set to 0).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSLLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.
EVEX encoded VPSLLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is conditionally updated with writemask k1.
Operation
VPSLLVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] ZeroExtend(SRC1[i+15:i] << SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
5-446 Vol. 2C
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
INSTRUCTION SET REFERENCE, V-Z
VPSLLVD (VEX.128 version)
COUNT_0 SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 SRC2[100 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] ZeroExtend(SRC1[127:96] << COUNT_3);
ELSE
DEST[127:96] 0;
DEST[MAX_VL-1:128] 0;
VPSLLVD (VEX.256 version)
COUNT_0 SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 SRC2[228 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] 0;
(* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] ZeroExtend(SRC1[255:224] << COUNT_7);
ELSE
DEST[255:224] 0;
DEST[MAX_VL-1:256] 0;
VPSLLVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] ZeroExtend(SRC1[i+31:i] << SRC2[31:0])
ELSE DEST[i+31:i] ZeroExtend(SRC1[i+31:i] << SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
Vol. 2C 5-447
INSTRUCTION SET REFERENCE, V-Z
VPSLLVQ (VEX.128 version)
COUNT_0 SRC2[63 : 0];
COUNT_1 SRC2[127 : 64];
IF COUNT_0 < 64THEN
DEST[63:0] ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] 0;
IF COUNT_1 < 64 THEN
DEST[127:64] ZeroExtend(SRC1[127:64] << COUNT_1);
ELSE
DEST[127:96] 0;
DEST[MAX_VL-1:128] 0;
VPSLLVQ (VEX.256 version)
COUNT_0 SRC2[63 : 0];
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 SRC2[197 : 192];
IF COUNT_0 < 64THEN
DEST[63:0] ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
DEST[255:192] ZeroExtend(SRC1[255:192] << COUNT_3);
ELSE
DEST[255:192] 0;
DEST[MAX_VL-1:256] 0;
VPSLLVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] ZeroExtend(SRC1[i+63:i] << SRC2[63:0])
ELSE DEST[i+63:i] ZeroExtend(SRC1[i+63:i] << SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
5-448 Vol. 2C
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPSLLVW __m512i _mm512_sllv_epi16(__m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_mask_sllv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_maskz_sllv_epi16( __mmask32 k, __m512i a, __m512i cnt);
VPSLLVW __m256i _mm256_mask_sllv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);
VPSLLVW __m256i _mm256_maskz_sllv_epi16( __mmask16 k, __m256i a, __m256i cnt);
VPSLLVW __m128i _mm_mask_sllv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVW __m128i _mm_maskz_sllv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m512i _mm512_sllv_epi32(__m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_mask_sllv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_maskz_sllv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m256i _mm256_mask_sllv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVQ __m512i _mm512_sllv_epi64(__m512i a, __m512i cnt);
VPSLLVQ __m512i _mm512_mask_sllv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);
VPSLLVQ __m512i _mm512_maskz_sllv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPSLLVD __m256i _mm256_mask_sllv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m256i _mm256_sllv_epi32 (__m256i m, __m256i count)
VPSLLVQ __m256i _mm256_sllv_epi64 (__m256i m, __m256i count)
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded VPSLLVD/VPSLLVQ, see Exceptions Type E4.
EVEX-encoded VPSLLVW, see Exceptions Type E4.nb.
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
Vol. 2C 5-449
INSTRUCTION SET REFERENCE, V-Z
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
Opcode/
Instruction
Op/
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
VEX.NDS.128.66.0F38.W0 46 /r
VPSRAVD xmm1, xmm2, xmm3/m128
Description
VEX.NDS.256.66.0F38.W0 46 /r
VPSRAVD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.W1 11 /r
VPSRAVW xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.W1 11 /r
VPSRAVW ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.W1 11 /r
VPSRAVW zmm1 {k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38.W0 46 /r
VPSRAVD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W0 46 /r
VPSRAVD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F38.W0 46 /r
VPSRAVD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
EVEX.NDS.128.66.0F38.W1 46 /r
VPSRAVQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W1 46 /r
VPSRAVQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F38.W1 46 /r
VPSRAVQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Shift doublewords in xmm2 right by amount specified
in the corresponding element of xmm3/m128 while
shifting in sign bits.
Shift doublewords in ymm2 right by amount specified
in the corresponding element of ymm3/m256 while
shifting in sign bits.
Shift words in xmm2 right by amount specified in the
corresponding element of xmm3/m128 while shifting
in sign bits using writemask k1.
Shift words in ymm2 right by amount specified in the
corresponding element of ymm3/m256 while shifting
in sign bits using writemask k1.
Shift words in zmm2 right by amount specified in the
corresponding element of zmm3/m512 while shifting
in sign bits using writemask k1.
Shift doublewords in xmm2 right by amount specified
in the corresponding element of
xmm3/m128/m32bcst while shifting in sign bits
using writemask k1.
Shift doublewords in ymm2 right by amount specified
in the corresponding element of
ymm3/m256/m32bcst while shifting in sign bits
using writemask k1.
Shift doublewords in zmm2 right by amount specified
in the corresponding element of
zmm3/m512/m32bcst while shifting in sign bits using
writemask k1.
Shift quadwords in xmm2 right by amount specified
in the corresponding element of
xmm3/m128/m64bcst while shifting in sign bits
using writemask k1.
Shift quadwords in ymm2 right by amount specified
in the corresponding element of
ymm3/m256/m64bcst while shifting in sign bits
using writemask k1.
Shift quadwords in zmm2 right by amount specified in
the corresponding element of zmm3/m512/m64bcst
while shifting in sign bits using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
5-450 Vol. 2C
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
INSTRUCTION SET REFERENCE, V-Z
Description
Shifts the bits in the individual data elements (word/doublewords/quadword) in the first source operand (the
second operand) to the right by the number of bits specified in the count value of respective data elements in the
second source operand (the third operand). As the bits in the data elements are shifted right, the empty high-order
bits are set to the MSB (sign extension).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for words),
31 (for doublewords), or 63 (for a quadword), then the destination data element are filled with the corresponding
sign bit of the source element.
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 16 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding destination register are
zeroed.
EVEX.512/256/128 encoded VPSRAVD/W: The destination and first source operands are ZMM/YMM/XMM registers.
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a
512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated
with writemask k1.
EVEX.512/256/128 encoded VPSRAVQ: The destination and first source operands are ZMM/YMM/XMM registers.
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination
is conditionally updated with writemask k1.
Operation
VPSRAVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
COUNT SRC2[i+3:i]
IF COUNT < 16
THEN
DEST[i+15:i] SignExtend(SRC1[i+15:i] >> COUNT)
ELSE
FOR k 0 TO 15
DEST[i+k] SRC1[i+15]
ENDFOR;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
Vol. 2C 5-451
INSTRUCTION SET REFERENCE, V-Z
VPSRAVD (VEX.128 version)
COUNT_0 SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 SRC2[100 : 96];
DEST[31:0] SignExtend(SRC1[31:0] >> COUNT_0);
(* Repeat shift operation for 2nd through 4th dwords *)
DEST[127:96] SignExtend(SRC1[127:96] >> COUNT_3);
DEST[MAX_VL-1:128] 0;
VPSRAVD (VEX.256 version)
COUNT_0 SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 8th dwords of SRC2*)
COUNT_7 SRC2[228 : 224];
DEST[31:0] SignExtend(SRC1[31:0] >> COUNT_0);
(* Repeat shift operation for 2nd through 7th dwords *)
DEST[255:224] SignExtend(SRC1[255:224] >> COUNT_7);
DEST[MAX_VL-1:256] 0;
VPSRAVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
COUNT SRC2[4:0]
IF COUNT < 32
THEN
DEST[i+31:i] SignExtend(SRC1[i+31:i] >> COUNT)
ELSE
FOR k 0 TO 31
DEST[i+k] SRC1[i+31]
ENDFOR;
FI
ELSE
COUNT SRC2[i+4:i]
IF COUNT < 32
THEN
DEST[i+31:i] SignExtend(SRC1[i+31:i] >> COUNT)
ELSE
FOR k 0 TO 31
DEST[i+k] SRC1[i+31]
ENDFOR;
FI
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
5-452 Vol. 2C
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
INSTRUCTION SET REFERENCE, V-Z
VPSRAVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
COUNT SRC2[5:0]
IF COUNT < 64
THEN
DEST[i+63:i] SignExtend(SRC1[i+63:i] >> COUNT)
ELSE
FOR k 0 TO 63
DEST[i+k] SRC1[i+63]
ENDFOR;
FI
ELSE
COUNT SRC2[i+5:i]
IF COUNT < 64
THEN
DEST[i+63:i] SignExtend(SRC1[i+63:i] >> COUNT)
ELSE
FOR k 0 TO 63
DEST[i+k] SRC1[i+63]
ENDFOR;
FI
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
Vol. 2C 5-453
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPSRAVD __m512i _mm512_srav_epi32(__m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_mask_srav_epi32(__m512i s, __mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_maskz_srav_epi32(__mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m256i _mm256_srav_epi32(__m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_mask_srav_epi32(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_maskz_srav_epi32(__mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m128i _mm_srav_epi32(__m128i a, __m128i cnt);
VPSRAVD __m128i _mm_mask_srav_epi32(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m512i _mm512_srav_epi64(__m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_mask_srav_epi64(__m512i s, __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_maskz_srav_epi64( __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m256i _mm256_srav_epi64(__m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_mask_srav_epi64(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_maskz_srav_epi64( __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m128i _mm_srav_epi64(__m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_mask_srav_epi64(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_maskz_srav_epi64( __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m512i _mm512_srav_epi16(__m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_mask_srav_epi16(__m512i s, __mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_maskz_srav_epi16(__mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m256i _mm256_srav_epi16(__m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_mask_srav_epi16(__m256i s, __mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_maskz_srav_epi16(__mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m128i _mm_srav_epi16(__m128i a, __m128i cnt);
VPSRAVW __m128i _mm_mask_srav_epi16(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m256i _mm256_srav_epi32 (__m256i m, __m256i count)
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
5-454 Vol. 2C
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
INSTRUCTION SET REFERENCE, V-Z
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
Opcode/
Instruction
Op /
En
RVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX2
VEX.NDS.128.66.0F38.W0 45 /r
VPSRLVD xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F38.W1 45 /r
VPSRLVQ xmm1, xmm2, xmm3/m128
RVM
V/V
AVX2
VEX.NDS.256.66.0F38.W0 45 /r
VPSRLVD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
VEX.NDS.256.66.0F38.W1 45 /r
VPSRLVQ ymm1, ymm2, ymm3/m256
RVM
V/V
AVX2
EVEX.NDS.128.66.0F38.W1 10 /r
VPSRLVW xmm1 {k1}{z}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.W1 10 /r
VPSRLVW ymm1 {k1}{z}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.W1 10 /r
VPSRLVW zmm1 {k1}{z}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38.W0 45 /r
VPSRLVD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 45 /r
VPSRLVD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 45 /r
VPSRLVD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
EVEX.NDS.128.66.0F38.W1 45 /r
VPSRLVQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 45 /r
VPSRLVQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 45 /r
VPSRLVQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Shift doublewords in xmm2 right by amount specified
in the corresponding element of xmm3/m128 while
shifting in 0s.
Shift quadwords in xmm2 right by amount specified in
the corresponding element of xmm3/m128 while
shifting in 0s.
Shift doublewords in ymm2 right by amount specified
in the corresponding element of ymm3/m256 while
shifting in 0s.
Shift quadwords in ymm2 right by amount specified in
the corresponding element of ymm3/m256 while
shifting in 0s.
Shift words in xmm2 right by amount specified in the
corresponding element of xmm3/m128 while shifting
in 0s using writemask k1.
Shift words in ymm2 right by amount specified in the
corresponding element of ymm3/m256 while shifting
in 0s using writemask k1.
Shift words in zmm2 right by amount specified in the
corresponding element of zmm3/m512 while shifting
in 0s using writemask k1.
Shift doublewords in xmm2 right by amount specified
in the corresponding element of xmm3/m128/m32bcst
while shifting in 0s using writemask k1.
Shift doublewords in ymm2 right by amount specified
in the corresponding element of ymm3/m256/m32bcst
while shifting in 0s using writemask k1.
Shift doublewords in zmm2 right by amount specified
in the corresponding element of zmm3/m512/m32bcst
while shifting in 0s using writemask k1.
Shift quadwords in xmm2 right by amount specified in
the corresponding element of xmm3/m128/m64bcst
while shifting in 0s using writemask k1.
Shift quadwords in ymm2 right by amount specified in
the corresponding element of ymm3/m256/m64bcst
while shifting in 0s using writemask k1.
Shift quadwords in zmm2 right by amount specified in
the corresponding element of zmm3/m512/m64bcst
while shifting in 0s using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
Vol. 2C 5-455
INSTRUCTION SET REFERENCE, V-Z
Description
Shifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the
right by the count value of respective data elements in the second source operand. As the bits in the data elements
are shifted right, the empty high-order bits are cleared (set to 0).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSRLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.
EVEX encoded VPSRLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is conditionally updated with writemask k1.
Operation
VPSRLVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] ZeroExtend(SRC1[i+15:i] >> SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
5-456 Vol. 2C
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
INSTRUCTION SET REFERENCE, V-Z
VPSRLVD (VEX.128 version)
COUNT_0 SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 SRC2[127 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] ZeroExtend(SRC1[127:96] >> COUNT_3);
ELSE
DEST[127:96] 0;
DEST[MAX_VL-1:128] 0;
VPSRLVD (VEX.256 version)
COUNT_0 SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 SRC2[255 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] 0;
(* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] ZeroExtend(SRC1[255:224] >> COUNT_7);
ELSE
DEST[255:224] 0;
DEST[MAX_VL-1:256] 0;
VPSRLVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] ZeroExtend(SRC1[i+31:i] >> SRC2[31:0])
ELSE DEST[i+31:i] ZeroExtend(SRC1[i+31:i] >> SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
Vol. 2C 5-457
INSTRUCTION SET REFERENCE, V-Z
VPSRLVQ (VEX.128 version)
COUNT_0 SRC2[63 : 0];
COUNT_1 SRC2[127 : 64];
IF COUNT_0 < 64 THEN
DEST[63:0] ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] 0;
IF COUNT_1 < 64 THEN
DEST[127:64] ZeroExtend(SRC1[127:64] >> COUNT_1);
ELSE
DEST[127:64] 0;
DEST[MAX_VL-1:128] 0;
VPSRLVQ (VEX.256 version)
COUNT_0 SRC2[63 : 0];
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 SRC2[255 : 192];
IF COUNT_0 < 64 THEN
DEST[63:0] ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
DEST[255:192] ZeroExtend(SRC1[255:192] >> COUNT_3);
ELSE
DEST[255:192] 0;
DEST[MAX_VL-1:256] 0;
VPSRLVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] ZeroExtend(SRC1[i+63:i] >> SRC2[63:0])
ELSE DEST[i+63:i] ZeroExtend(SRC1[i+63:i] >> SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0;
5-458 Vol. 2C
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPSRLVW __m512i _mm512_srlv_epi16(__m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_mask_srlv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_maskz_srlv_epi16( __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m256i _mm256_mask_srlv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m256i _mm256_maskz_srlv_epi16( __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m128i _mm_mask_srlv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVW __m128i _mm_maskz_srlv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVW __m256i _mm256_srlv_epi32 (__m256i m, __m256i count)
VPSRLVD __m512i _mm512_srlv_epi32(__m512i a, __m512i cnt);
VPSRLVD __m512i _mm512_mask_srlv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m512i _mm512_maskz_srlv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m256i _mm256_mask_srlv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSRLVD __m256i _mm256_maskz_srlv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPSRLVD __m128i _mm_mask_srlv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVD __m128i _mm_maskz_srlv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m512i _mm512_srlv_epi64(__m512i a, __m512i cnt);
VPSRLVQ __m512i _mm512_mask_srlv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);
VPSRLVQ __m512i _mm512_maskz_srlv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPSRLVQ __m256i _mm256_mask_srlv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSRLVQ __m256i _mm256_maskz_srlv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSRLVQ __m128i _mm_mask_srlv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m128i _mm_maskz_srlv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m256i _mm256_srlv_epi64 (__m256i m, __m256i count)
VPSRLVD __m128i _mm_srlv_epi32( __m128i a, __m128i cnt);
VPSRLVQ __m128i _mm_srlv_epi64( __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded VPSRLVD/Q, see Exceptions Type E4.
EVEX-encoded VPSRLVW, see Exceptions Type E4.nb.
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
Vol. 2C 5-459
INSTRUCTION SET REFERENCE, V-Z
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.DDS.128.66.0F3A.W0 25 /r ib
VPTERNLOGD xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst, imm8
EVEX.DDS.256.66.0F3A.W0 25 /r ib
VPTERNLOGD ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.512.66.0F3A.W0 25 /r ib
VPTERNLOGD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst, imm8
FV
V/V
AVX512F
EVEX.DDS.128.66.0F3A.W1 25 /r ib
VPTERNLOGQ xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.256.66.0F3A.W1 25 /r ib
VPTERNLOGQ ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.DDS.512.66.0F3A.W1 25 /r ib
VPTERNLOGQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst, imm8
FV
V/V
AVX512F
Description
Bitwise ternary logic taking xmm1, xmm2 and
xmm3/m128/m32bcst as source operands and writing
the result to xmm1 under writemask k1 with dword
granularity. The immediate value determines the specific
binary function being implemented.
Bitwise ternary logic taking ymm1, ymm2 and
ymm3/m256/m32bcst as source operands and writing
the result to ymm1 under writemask k1 with dword
granularity. The immediate value determines the specific
binary function being implemented.
Bitwise ternary logic taking zmm1, zmm2 and
zmm3/m512/m32bcst as source operands and writing
the result to zmm1 under writemask k1 with dword
granularity. The immediate value determines the specific
binary function being implemented.
Bitwise ternary logic taking xmm1, xmm2 and
xmm3/m128/m64bcst as source operands and writing
the result to xmm1 under writemask k1 with qword
granularity. The immediate value determines the specific
binary function being implemented.
Bitwise ternary logic taking ymm1, ymm2 and
ymm3/m256/m64bcst as source operands and writing
the result to ymm1 under writemask k1 with qword
granularity. The immediate value determines the specific
binary function being implemented.
Bitwise ternary logic taking zmm1, zmm2 and
zmm3/m512/m64bcst as source operands and writing
the result to zmm1 under writemask k1 with qword
granularity. The immediate value determines the specific
binary function being implemented.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
VPTERNLOGD/Q takes three bit vectors of 512-bit length (in the first, second and third operand) as input data to
form a set of 512 indices, each index is comprised of one bit from each input vector. The imm8 byte specifies a
boolean logic table producing a binary value for each 3-bit index value. The final 512-bit boolean result is written
to the destination operand (the first operand) using the writemask k1 with the granularity of doubleword element
or quadword element into the destination.
The destination operand is a ZMM (EVEX.512)/YMM (EVEX.256)/XMM (EVEX.128) register. The first source operand
is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location The destination
operand is a ZMM register conditionally updated with writemask k1.
5-460 Vol. 2C
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
INSTRUCTION SET REFERENCE, V-Z
Table 5-20 shows two examples of Boolean functions specified by immediate values 0xE2 and 0xE4, with the look
up result listed in the fourth column following the three columns containing all possible values of the 3-bit index.
Table 5-20. Examples of VPTERNLOGD/Q Imm8 Boolean Function and Input Index Values
VPTERNLOGD reg1, reg2, src3, 0xE2
Bit Result with
Imm8=0xE2
VPTERNLOGD reg1, reg2, src3, 0xE4
Bit(reg1)
Bit(reg2)
Bit(src3)
Bit Result with
Imm8=0xE4
Bit(reg1)
Bit(reg2)
Bit(src3)
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
Specifying different values in imm8 will allow any arbitrary three-input Boolean functions to be implemented in
software using VPTERNLOGD/Q. Table 5-10 and Table 5-11 provide a mapping of all 256 possible imm8 values to
various Boolean expressions.
Operation
VPTERNLOGD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
FOR k 0 TO 31
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j][k] imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]
ELSE DEST[j][k] imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]
FI;
; table lookup of immediate bellow;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31+i:i] remains unchanged*
ELSE
; zeroing-masking
DEST[31+i:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
Vol. 2C 5-461
INSTRUCTION SET REFERENCE, V-Z
VPTERNLOGQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
FOR k 0 TO 63
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j][k] imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]
ELSE DEST[j][k] imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]
FI;
; table lookup of immediate bellow;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63+i:i] remains unchanged*
ELSE
; zeroing-masking
DEST[63+i:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPTERNLOGD __m512i _mm512_ternarylogic_epi32(__m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_mask_ternarylogic_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_maskz_ternarylogic_epi32(__mmask m, __m512i a, __m512i b, int imm);
VPTERNLOGD __m256i _mm256_ternarylogic_epi32(__m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_mask_ternarylogic_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_maskz_ternarylogic_epi32( __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGD __m128i _mm_ternarylogic_epi32(__m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_mask_ternarylogic_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_maskz_ternarylogic_epi32( __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m512i _mm512_ternarylogic_epi64(__m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_mask_ternarylogic_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_maskz_ternarylogic_epi64( __mmask8 m, __m512i a, __m512i b, int imm);
VPTERNLOGQ __m256i _mm256_ternarylogic_epi64(__m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_mask_ternarylogic_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_maskz_ternarylogic_epi64( __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGQ __m128i _mm_ternarylogic_epi64(__m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_mask_ternarylogic_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_maskz_ternarylogic_epi64( __mmask8 m, __m128i a, __m128i b, int imm);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.
5-462 Vol. 2C
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
INSTRUCTION SET REFERENCE, V-Z
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
Opcode/
Instruction
Op/
En
FVM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512BW
EVEX.NDS.128.66.0F38.W0 26 /r
VPTESTMB k2 {k1}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.W0 26 /r
VPTESTMB k2 {k1}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.W0 26 /r
VPTESTMB k2 {k1}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38.W1 26 /r
VPTESTMW k2 {k1}, xmm2,
xmm3/m128
EVEX.NDS.256.66.0F38.W1 26 /r
VPTESTMW k2 {k1}, ymm2,
ymm3/m256
EVEX.NDS.512.66.0F38.W1 26 /r
VPTESTMW k2 {k1}, zmm2,
zmm3/m512
EVEX.NDS.128.66.0F38.W0 27 /r
VPTESTMD k2 {k1}, xmm2,
xmm3/m128/m32bcst
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512VL
AVX512BW
FVM
V/V
AVX512BW
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W0 27 /r
VPTESTMD k2 {k1}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F38.W0 27 /r
VPTESTMD k2 {k1}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
EVEX.NDS.128.66.0F38.W1 27 /r
VPTESTMQ k2 {k1}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F38.W1 27 /r
VPTESTMQ k2 {k1}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F38.W1 27 /r
VPTESTMQ k2 {k1}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Description
Bitwise AND of packed byte integers in xmm2 and
xmm3/m128 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
Bitwise AND of packed byte integers in ymm2 and
ymm3/m256 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
Bitwise AND of packed byte integers in zmm2 and
zmm3/m512 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
Bitwise AND of packed word integers in xmm2 and
xmm3/m128 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
Bitwise AND of packed word integers in ymm2 and
ymm3/m256 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
Bitwise AND of packed word integers in zmm2 and
zmm3/m512 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
Bitwise AND of packed doubleword integers in xmm2 and
xmm3/m128/m32bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise AND of packed doubleword integers in ymm2 and
ymm3/m256/m32bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise AND of packed doubleword integers in zmm2 and
zmm3/m512/m32bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise AND of packed quadword integers in xmm2 and
xmm3/m128/m64bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise AND of packed quadword integers in ymm2 and
ymm3/m256/m64bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise AND of packed quadword integers in zmm2 and
zmm3/m512/m64bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
Vol. 2C 5-463
INSTRUCTION SET REFERENCE, V-Z
Description
Performs a bitwise logical AND operation on the first source operand (the second operand) and second source
operand (the third operand) and stores the result in the destination operand (the first operand) under the
writemask. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and second
src operands is non-zero; otherwise it is set to 0.
VPTESTMD/VPTESTMQ: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a mask register updated under the writemask.
VPTESTMB/VPTESTMW: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a mask register
updated under the writemask.
Operation
VPTESTMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j 0 TO KL-1
ij*8
IF k1[j] OR *no writemask*
THEN
DEST[j] (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] != 0)? 1 : 0;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPTESTMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j 0 TO KL-1
i j * 16
IF k1[j] OR *no writemask*
THEN
DEST[j] (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] != 0)? 1 : 0;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
VPTESTMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j] (SRC1[i+31:i] BITWISE AND SRC2[31:0] != 0)? 1 : 0;
ELSE DEST[j] (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] != 0)? 1 : 0;
FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
5-464 Vol. 2C
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
INSTRUCTION SET REFERENCE, V-Z
VPTESTMQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j] (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0;
ELSE DEST[j] (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0;
FI;
ELSE
DEST[j] 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] 0
Intel C/C++ Compiler Intrinsic Equivalents
VPTESTMB __mmask64 _mm512_test_epi8_mask( __m512i a, __m512i b);
VPTESTMB __mmask64 _mm512_mask_test_epi8_mask(__mmask64, __m512i a, __m512i b);
VPTESTMW __mmask32 _mm512_test_epi16_mask( __m512i a, __m512i b);
VPTESTMW __mmask32 _mm512_mask_test_epi16_mask(__mmask32, __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_test_epi32_mask( __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_mask_test_epi32_mask(__mmask16, __m512i a, __m512i b);
VPTESTMQ __mmask8 _mm512_test_epi64_mask(__m512i a, __m512i b);
VPTESTMQ __mmask8 _mm512_mask_test_epi64_mask(__mmask8, __m512i a, __m512i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VPTESTMD/Q: See Exceptions Type E4.
VPTESTMB/W: See Exceptions Type E4.nb.
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
Vol. 2C 5-465
INSTRUCTION SET REFERENCE, V-Z
VPTESTNMB/W/D/Q—Logical NAND and Set
Opcode/
Instruction
Op/
En
EVEX.NDS.128.F3.0F38.W0 26 /r
VPTESTNMB k2 {k1}, xmm2,
xmm3/m128
FVM
64/32
bit Mode
Support
V/V
CPUID
Description
AVX512VL
AVX512BW
Bitwise NAND of packed byte integers in xmm2 and
xmm3/m128 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
EVEX.NDS.256.F3.0F38.W0 26 /r
VPTESTNMB k2 {k1}, ymm2,
ymm3/m256
FVM
V/V
AVX512VL
AVX512BW
Bitwise NAND of packed byte integers in ymm2 and
ymm3/m256 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
EVEX.NDS.512.F3.0F38.W0 26 /r
VPTESTNMB k2 {k1}, zmm2,
zmm3/m512
FVM
V/V
AVX512F
AVX512BW
Bitwise NAND of packed byte integers in zmm2 and
zmm3/m512 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
EVEX.NDS.128.F3.0F38.W1 26 /r
VPTESTNMW k2 {k1}, xmm2,
xmm3/m128
FVM
V/V
AVX512VL
AVX512BW
Bitwise NAND of packed word integers in xmm2 and
xmm3/m128 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
EVEX.NDS.256.F3.0F38.W1 26 /r
VPTESTNMW k2 {k1}, ymm2,
ymm3/m256
FVM
V/V
AVX512VL
AVX512BW
Bitwise NAND of packed word integers in ymm2 and
ymm3/m256 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
EVEX.NDS.512.F3.0F38.W1 26 /r
VPTESTNMW k2 {k1}, zmm2,
zmm3/m512
FVM
V/V
AVX512F
AVX512BW
Bitwise NAND of packed word integers in zmm2 and
zmm3/m512 and set mask k2 to reflect the zero/non-zero
status of each element of the result, under writemask k1.
EVEX.NDS.128.F3.0F38.W0 27 /r
VPTESTNMD k2 {k1}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.F3.0F38.W0 27 /r
VPTESTNMD k2 {k1}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.F3.0F38.W0 27 /r
VPTESTNMD k2 {k1}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512F
EVEX.NDS.128.F3.0F38.W1 27 /r
VPTESTNMQ k2 {k1}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.F3.0F38.W1 27 /r
VPTESTNMQ k2 {k1}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.F3.0F38.W1 27 /r
VPTESTNMQ k2 {k1}, zmm2,
zmm3/m512/m64bcst
FV
V/V
AVX512F
Bitwise NAND of packed doubleword integers in xmm2 and
xmm3/m128/m32bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise NAND of packed doubleword integers in ymm2 and
ymm3/m256/m32bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise NAND of packed doubleword integers in zmm2 and
zmm3/m512/m32bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise NAND of packed quadword integers in xmm2 and
xmm3/m128/m64bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise NAND of packed quadword integers in ymm2 and
ymm3/m256/m64bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
Bitwise NAND of packed quadword integers in zmm2 and
zmm3/m512/m64bcst and set mask k2 to reflect the
zero/non-zero status of each element of the result, under
writemask k1.
5-466 Vol. 2C
VPTESTNMB/W/D/Q—Logical NAND and Set
INSTRUCTION SET REFERENCE, V-Z
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FVM
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical NAND operation on the byte/word/doubleword/quadword element of the first source
operand (the second operand) with the corresponding element of the second source operand (the third operand)
and stores the logical comparison result into each bit of the destination operand (the first operand) according to the
writemask k1. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and
second src operands is zero; otherwise it is set to 0.
EVEX encoded VPTESTNMD/Q: The first source operand is a ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted
from a 32/64-bit memory location. The destination is updated according to the writemask.
EVEX encoded VPTESTNMB/W: The first source operand is a ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.
Operation
VPTESTNMB
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j ← 0 TO KL-1
i ← j*8
IF MaskBit(j) OR *no writemask*
THEN
DEST[j] ← (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] == 0)? 1 : 0
ELSE DEST[j] ← 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] ← 0
VPTESTNMW
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j ← 0 TO KL-1
i ← j*16
IF MaskBit(j) OR *no writemask*
THEN
DEST[j] ← (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] == 0)? 1 : 0
ELSE DEST[j] ← 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] ← 0
VPTESTNMB/W/D/Q—Logical NAND and Set
Vol. 2C 5-467
INSTRUCTION SET REFERENCE, V-Z
VPTESTNMD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j*32
IF MaskBit(j) OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] (SRC1[i+31:i] BITWISE AND SRC2[31:0] == 0)? 1 : 0
ELSE DEST[j] (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] == 0)? 1 : 0
FI
ELSE DEST[j] 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] 0
VPTESTNMQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j*64
IF MaskBit(j) OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j] (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0;
ELSE DEST[j] (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0;
FI;
ELSE DEST[j] 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] 0
5-468 Vol. 2C
VPTESTNMB/W/D/Q—Logical NAND and Set
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VPTESTNMB __mmask64 _mm512_testn_epi8_mask( __m512i a, __m512i b);
VPTESTNMB __mmask64 _mm512_mask_testn_epi8_mask(__mmask64, __m512i a, __m512i b);
VPTESTNMB __mmask32 _mm256_testn_epi8_mask(__m256i a, __m256i b);
VPTESTNMB __mmask32 _mm256_mask_testn_epi8_mask(__mmask32, __m256i a, __m256i b);
VPTESTNMB __mmask16 _mm_testn_epi8_mask(__m128i a, __m128i b);
VPTESTNMB __mmask16 _mm_mask_testn_epi8_mask(__mmask16, __m128i a, __m128i b);
VPTESTNMW __mmask32 _mm512_testn_epi16_mask( __m512i a, __m512i b);
VPTESTNMW __mmask32 _mm512_mask_testn_epi16_mask(__mmask32, __m512i a, __m512i b);
VPTESTNMW __mmask16 _mm256_testn_epi16_mask(__m256i a, __m256i b);
VPTESTNMW __mmask16 _mm256_mask_testn_epi16_mask(__mmask16, __m256i a, __m256i b);
VPTESTNMW __mmask8 _mm_testn_epi16_mask(__m128i a, __m128i b);
VPTESTNMW __mmask8 _mm_mask_testn_epi16_mask(__mmask8, __m128i a, __m128i b);
VPTESTNMD __mmask16 _mm512_testn_epi32_mask( __m512i a, __m512i b);
VPTESTNMD __mmask16 _mm512_mask_testn_epi32_mask(__mmask16, __m512i a, __m512i b);
VPTESTNMD __mmask8 _mm256_testn_epi32_mask(__m256i a, __m256i b);
VPTESTNMD __mmask8 _mm256_mask_testn_epi32_mask(__mmask8, __m256i a, __m256i b);
VPTESTNMD __mmask8 _mm_testn_epi32_mask(__m128i a, __m128i b);
VPTESTNMD __mmask8 _mm_mask_testn_epi32_mask(__mmask8, __m128i a, __m128i b);
VPTESTNMQ __mmask8 _mm512_testn_epi64_mask(__m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm512_mask_testn_epi64_mask(__mmask8, __m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm256_testn_epi64_mask(__m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm256_mask_testn_epi64_mask(__mmask8, __m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm_testn_epi64_mask(__m128i a, __m128i b);
VPTESTNMQ __mmask8 _mm_mask_testn_epi64_mask(__mmask8, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VPTESTNMD/VPTESTNMQ: See Exceptions Type E4.
VPTESTNMB/VPTESTNMW: See Exceptions Type E4.nb.
VPTESTNMB/W/D/Q—Logical NAND and Set
Vol. 2C 5-469
INSTRUCTION SET REFERENCE, V-Z
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.NDS.128.66.0F3A.W1 50 /r ib
VRANGEPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst, imm8
EVEX.NDS.256.66.0F3A.W1 50 /r ib
VRANGEPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512DQ
EVEX.NDS.512.66.0F3A.W1 50 /r ib
VRANGEPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{sae}, imm8
FV
V/V
AVX512DQ
Description
Calculate two RANGE operation output value from 2 pairs
of double-precision floating-point values in xmm2 and
xmm3/m128/m32bcst, store the results to xmm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
Calculate four RANGE operation output value from 4pairs
of double-precision floating-point values in ymm2 and
ymm3/m256/m32bcst, store the results to ymm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
Calculate eight RANGE operation output value from 8
pairs of double-precision floating-point values in zmm2
and zmm3/m512/m32bcst, store the results to zmm1
under the writemask k1. Imm8 specifies the comparison
and sign of the range operation.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
This instruction calculates 2/4/8 range operation outputs from two sets of packed input double-precision FP values
in the first source operand (the second operand) and the second source operand (the third operand). The range
outputs are written to the destination operand (the first operand) under the writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
•
Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
absolute value of the input value pair. Each comparison of two input values produces an intermediate result that
combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
•
Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.
7
imm8
6
5
4
3
Must Be Zero
2
Sign Control (SC)
1
0
Compare Operation Select
Imm8[1:0] = 00b : Select Min value
Imm8[3:2] = 00b : Select sign(SRC1)
Imm8[1:0] = 01b : Select Max value
Imm8[3:2] = 01b : Select sign(Compare_Result)
Imm8[1:0] = 10b : Select Min-Abs value
Imm8[3:2] = 10b : Set sign to 0
Imm8[3:2] = 11b : Set sign to 1
Imm8[1:0] = 11b : Select Max-Abs value
Figure 5-27. Imm8 Controls for VRANGEPD/SD/PS/SS
5-470 Vol. 2C
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values
INSTRUCTION SET REFERENCE, V-Z
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-21. If the comparison raises an IE, the sign select control
(Imm8[3:2] has no effect to the range operation output, this is indicated also in Table 5-21.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magnitude-0, opposite-signed input cases are listed in Table 5-22.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS comparison operation with result listed in Table 5-23.
Table 5-21. Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2]
Src1
Src2
Result
IE Signaling Due to Comparison
Imm8[3:2] Effect to Range Output
sNaN1
sNaN2
Quiet(sNaN1)
Yes
Ignored
sNaN1
qNaN2
Quiet(sNaN1)
Yes
Ignored
sNaN1
Norm2
Quiet(sNaN1)
Yes
Ignored
qNaN1
sNaN2
Quiet(sNaN2)
Yes
Ignored
qNaN1
qNaN2
qNaN1
No
Applicable
qNaN1
Norm2
Norm2
No
Applicable
Norm1
sNaN2
Quiet(sNaN2)
Yes
Ignored
Norm1
qNaN2
Norm1
No
Applicable
Table 5-22. Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS and MAX, MAX_ABS
MIN and MIN_ABS
MAX and MAX_ABS
Src1
Src2
Result
Src1
Src2
Result
+0
-0
-0
+0
-0
+0
-0
+0
-0
-0
+0
+0
Table 5-23. Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0)
MIN_ABS (|a| = |b|, a>0, b<0)
MAX_ABS (|a| = |b|, a>0, b<0)
Src1
Src2
Result
Src1
Src2
Result
a
b
b
a
b
a
b
a
b
b
a
a
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values
Vol. 2C 5-471
INSTRUCTION SET REFERENCE, V-Z
Operation
RangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-21
IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);
Src1.exp SRC1[62:52];
Src1.fraction SRC1[51:0];
IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction 0;
ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;
Src2.exp SRC2[62:52];
Src2.fraction SRC2[51:0];
IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction 0;
ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF (SRC2 = QNAN) THEN{TMP[63:0] SRC1[63:0]}
ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] SRC2[63:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] from Table 5-22
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] from Table 5-23
ELSE
Case(CmpOpCtl[1:0])
00: TMP[63:0] (SRC1[63:0] ≤ SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];
01: TMP[63:0] (SRC1[63:0] ≤ SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];
10: TMP[63:0] (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];
11: TMP[63:0] (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit
01: dest TMP[63:0];// Preserve sign of compare result
10: dest (0 << 63) OR (TMP[62:0]);// Zero out sign bit
11: dest (1 << 63) OR (TMP[62:0]);// Set the sign bit
ESAC;
RETURN dest[63:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
5-472 Vol. 2C
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VRANGEPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] RangeDP (SRC1[i+63:i], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
ELSE DEST[i+63:i] RangeDP (SRC1[i+63:i], SRC2[i+63:i], DAZ, CmpOpCtl[1:0], SignSelCtl[1:0]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
The following example describes a common usage of this instruction for checking that the input operand is
bounded between ±1023.
VRANGEPD zmm_dst, zmm_src, zmm_1023, 02h;
Where:
zmm_dst is the destination operand.
zmm_src is the input operand to compare against ±1023 (this is SRC1).
zmm_1023 is the reference operand, contains the value of 1023 (and this is SRC2).
IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of SRC1.sign.
In case |zmm_src| < 1023 (i.e. SRC1 is smaller than 1023 in magnitude), then its value will be written into
zmm_dst. Otherwise, the value stored in zmm_dst will get the value of 1023 (received on zmm_1023, which is
SRC2).
However, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| ≥ 1023, the selected sign of SRC1 is kept.
Thus, if zmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023 while if zmm_src > +1023,
the result of VRANGE will be the maximal value of +1023.
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values
Vol. 2C 5-473
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VRANGEPD __m512d _mm512_range_pd ( __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_range_round_pd ( __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_mask_range_pd (__m512 ds, __mmask8 k, __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_mask_range_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_maskz_range_pd ( __mmask8 k, __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_maskz_range_round_pd ( __mmask8 k, __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m256d _mm256_range_pd ( __m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_mask_range_pd (__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_maskz_range_pd ( __mmask8 k, __m256d a, __m256d b, int imm);
VRANGEPD __m128d _mm_range_pd ( __m128 a, __m128d b, int imm);
VRANGEPD __m128d _mm_mask_range_pd (__m128 s, __mmask8 k, __m128d a, __m128d b, int imm);
VRANGEPD __m128d _mm_maskz_range_pd ( __mmask8 k, __m128d a, __m128d b, int imm);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E2.
5-474 Vol. 2C
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.NDS.128.66.0F3A.W0 50 /r ib
VRANGEPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst, imm8
EVEX.NDS.256.66.0F3A.W0 50 /r ib
VRANGEPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512DQ
EVEX.NDS.512.66.0F3A.W0 50 /r ib
VRANGEPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{sae}, imm8
FV
V/V
AVX512DQ
Description
Calculate four RANGE operation output value from 4 pairs
of single-precision floating-point values in xmm2 and
xmm3/m128/m32bcst, store the results to xmm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
Calculate eight RANGE operation output value from 8 pairs
of single-precision floating-point values in ymm2 and
ymm3/m256/m32bcst, store the results to ymm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
Calculate 16 RANGE operation output value from 16 pairs
of single-precision floating-point values in zmm2 and
zmm3/m512/m32bcst, store the results to zmm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
This instruction calculates 4/8/16 range operation outputs from two sets of packed input single-precision FP values
in the first source operand (the second operand) and the second source operand (the third operand). The range
outputs are written to the destination operand (the first operand) under the writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
•
Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
absolute value of the input value pair. Each comparison of two input values produces an intermediate result
that combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
•
Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-21. If the comparison raises an IE, the sign select control
(Imm8[3:2]) has no effect to the range operation output, this is indicated also in Table 5-21.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magnitude-0, opposite-signed input cases are listed in Table 5-22.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS comparison operation with result listed in Table 5-23.
VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values
Vol. 2C 5-475
INSTRUCTION SET REFERENCE, V-Z
Operation
RangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-21
IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);
Src1.exp SRC1[30:23];
Src1.fraction SRC1[22:0];
IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction 0;
ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;
Src2.exp SRC2[30:23];
Src2.fraction SRC2[22:0];
IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction 0;
ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF (SRC2 = QNAN) THEN{TMP[31:0] SRC1[31:0]}
ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] SRC2[31:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] from Table 5-22
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] from Table 5-23
ELSE
Case(CmpOpCtl[1:0])
00: TMP[31:0] (SRC1[31:0] ≤ SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];
01: TMP[31:0] (SRC1[31:0] ≤ SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];
10: TMP[31:0] (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];
11: TMP[31:0] (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit
01: dest TMP[31:0];// Preserve sign of compare result
10: dest (0 << 31) OR (TMP[30:0]);// Zero out sign bit
11: dest (1 << 31) OR (TMP[30:0]);// Set the sign bit
ESAC;
RETURN dest[31:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
5-476 Vol. 2C
VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values
INSTRUCTION SET REFERENCE, V-Z
VRANGEPS
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] RangeSP (SRC1[i+31:i], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
ELSE DEST[i+31:i] RangeSP (SRC1[i+31:i], SRC2[i+31:i], DAZ, CmpOpCtl[1:0], SignSelCtl[1:0]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] = 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
The following example describes a common usage of this instruction for checking that the input operand is
bounded between ±150.
VRANGEPS zmm_dst, zmm_src, zmm_150, 02h;
Where:
zmm_dst is the destination operand.
zmm_src is the input operand to compare against ±150.
zmm_150 is the reference operand, contains the value of 150.
IMM=02(imm8[1:0]=’10) selects the Min Absolute value operation with selection of src1.sign.
In case |zmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in zmm_dst
will get the value of 150 (received on zmm_150).
However, the sign control (imm8[3:2]=’00) instructs to select the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| ≥ 150, the selected sign of SRC1 is kept.
Thus, if zmm_src < -150, the result of VRANGEPS will be the minimal value of -150 while if zmm_src > +150,
the result of VRANGE will be the maximal value of +150.
VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values
Vol. 2C 5-477
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VRANGEPS __m512 _mm512_range_ps ( __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_range_round_ps ( __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m512 _mm512_mask_range_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_mask_range_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m512 _mm512_maskz_range_ps ( __mmask16 k, __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_maskz_range_round_ps ( __mmask16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m256 _mm256_range_ps ( __m256 a, __m256 b, int imm);
VRANGEPS __m256 _mm256_mask_range_ps (__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);
VRANGEPS __m256 _mm256_maskz_range_ps ( __mmask8 k, __m256 a, __m256 b, int imm);
VRANGEPS __m128 _mm_range_ps ( __m128 a, __m128 b, int imm);
VRANGEPS __m128 _mm_mask_range_ps (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRANGEPS __m128 _mm_maskz_range_ps ( __mmask8 k, __m128 a, __m128 b, int imm);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E2.
5-478 Vol. 2C
VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values
INSTRUCTION SET REFERENCE, V-Z
VRANGESD—Range Restriction Calculation From a pair of Scalar Float64 Values
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W1 51 /r
VRANGESD xmm1 {k1}{z},
xmm2, xmm3/m64{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512DQ
Description
Calculate a RANGE operation output value from 2 doubleprecision floating-point values in xmm2 and xmm3/m64,
store the output to xmm1 under writemask. Imm8 specifies
the comparison and sign of the range operation.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
This instruction calculates a range operation output from two input double-precision FP values in the low qword
element of the first source operand (the second operand) and second source operand (the third operand). The
range output is written to the low qword element of the destination operand (the first operand) under the
writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
•
Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
absolute value of the input value pair. Each comparison of two input values produces an intermediate result
that combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
•
Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.
Bits 128:63 of the destination operand are copied from the respective element of the first source operand.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-21. If the comparison raises an IE, the sign select control
(Imm8[3:2] has no effect to the range operation output, this is indicated also in Table 5-21.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magnitude-0, opposite-signed input cases are listed in Table 5-22.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS comparison operation with result listed in Table 5-23.
VRANGESD—Range Restriction Calculation From a pair of Scalar Float64 Values
Vol. 2C 5-479
INSTRUCTION SET REFERENCE, V-Z
Operation
RangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-21
IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);
Src1.exp SRC1[62:52];
Src1.fraction SRC1[51:0];
IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction 0;
ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;
Src2.exp SRC2[62:52];
Src2.fraction SRC2[51:0];
IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction 0;
ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF (SRC2 = QNAN) THEN{TMP[63:0] SRC1[63:0]}
ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] SRC2[63:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] from Table 5-22
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] from Table 5-23
ELSE
Case(CmpOpCtl[1:0])
00: TMP[63:0] (SRC1[63:0] ≤ SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];
01: TMP[63:0] (SRC1[63:0] ≤ SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];
10: TMP[63:0] (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];
11: TMP[63:0] (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit
01: dest TMP[63:0];// Preserve sign of compare result
10: dest (0 << 63) OR (TMP[62:0]);// Zero out sign bit
11: dest (1 << 63) OR (TMP[62:0]);// Set the sign bit
ESAC;
RETURN dest[63:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
5-480 Vol. 2C
VRANGESD—Range Restriction Calculation From a pair of Scalar Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VRANGESD
IF k1[0] OR *no writemask*
THEN DEST[63:0] RangeDP (SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] = 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
The following example describes a common usage of this instruction for checking that the input operand is
bounded between ±1023.
VRANGESD xmm_dst, xmm_src, xmm_1023, 02h;
Where:
xmm_dst is the destination operand.
xmm_src is the input operand to compare against ±1023.
xmm_1023 is the reference operand, contains the value of 1023.
IMM=02(imm8[1:0]=’10) selects the Min Absolute value operation with selection of src1.sign.
In case |xmm_src| < 1023, then its value will be written into xmm_dst. Otherwise, the value stored in xmm_dst
will get the value of 1023 (received on xmm_1023).
However, the sign control (imm8[3:2]=’00) instructs to select the sign of SRC1 received from xmm_src. So, even
in the case of |xmm_src| ≥ 1023, the selected sign of SRC1 is kept.
Thus, if xmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023while if xmm_src > +1023,
the result of VRANGE will be the maximal value of +1023.
Intel C/C++ Compiler Intrinsic Equivalent
VRANGESD __m128d _mm_range_sd ( __m128d a, __m128d b, int imm);
VRANGESD __m128d _mm_range_round_sd ( __m128d a, __m128d b, int imm, int sae);
VRANGESD __m128d _mm_mask_range_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VRANGESD __m128d _mm_mask_range_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm, int sae);
VRANGESD __m128d _mm_maskz_range_sd ( __mmask8 k, __m128d a, __m128d b, int imm);
VRANGESD __m128d _mm_maskz_range_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E3.
VRANGESD—Range Restriction Calculation From a pair of Scalar Float64 Values
Vol. 2C 5-481
INSTRUCTION SET REFERENCE, V-Z
VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W0 51 /r
VRANGESS xmm1 {k1}{z},
xmm2, xmm3/m32{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512DQ
Description
Calculate a RANGE operation output value from 2 singleprecision floating-point values in xmm2 and xmm3/m32,
store the output to xmm1 under writemask. Imm8 specifies
the comparison and sign of the range operation.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction calculates a range operation output from two input single-precision FP values in the low dword
element of the first source operand (the second operand) and second source operand (the third operand). The
range output is written to the low dword element of the destination operand (the first operand) under the
writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
•
Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
absolute value of the input value pair. Each comparison of two input values produces an intermediate result that
combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
•
Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.
Bits 128:31 of the destination operand are copied from the respective elements of the first source operand.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-21. If the comparison raises an IE, the sign select control
(Imm8[3:2]) has no effect to the range operation output, this is indicated also in Table 5-21.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magnitude-0, opposite-signed input cases are listed in Table 5-22.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS comparison operation with result listed in Table 5-23.
5-482 Vol. 2C
VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values
INSTRUCTION SET REFERENCE, V-Z
Operation
RangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-21
IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);
Src1.exp SRC1[30:23];
Src1.fraction SRC1[22:0];
IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction 0;
ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;
Src2.exp SRC2[30:23];
Src2.fraction SRC2[22:0];
IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction 0;
ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF (SRC2 = QNAN) THEN{TMP[31:0] SRC1[31:0]}
ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] SRC2[31:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] from Table 5-22
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] from Table 5-23
ELSE
Case(CmpOpCtl[1:0])
00: TMP[31:0] (SRC1[31:0] ≤ SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];
01: TMP[31:0] (SRC1[31:0] ≤ SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];
10: TMP[31:0] (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];
11: TMP[31:0] (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit
01: dest TMP[31:0];// Preserve sign of compare result
10: dest (0 << 31) OR (TMP[30:0]);// Zero out sign bit
11: dest (1 << 31) OR (TMP[30:0]);// Set the sign bit
ESAC;
RETURN dest[31:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values
Vol. 2C 5-483
INSTRUCTION SET REFERENCE, V-Z
VRANGESS
IF k1[0] OR *no writemask*
THEN DEST[31:0] RangeSP (SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] = 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
The following example describes a common usage of this instruction for checking that the input operand is bounded between ±150.
VRANGESS zmm_dst, zmm_src, zmm_150, 02h;
Where:
xmm_dst is the destination operand.
xmm_src is the input operand to compare against ±150.
xmm_150 is the reference operand, contains the value of 150.
IMM=02(imm8[1:0]=’10) selects the Min Absolute value operation with selection of src1.sign.
In case |xmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in xmm_dst
will get the value of 150 (received on zmm_150).
However, the sign control (imm8[3:2]=’00) instructs to select the sign of SRC1 received from xmm_src. So, even
in the case of |xmm_src| ≥ 150, the selected sign of SRC1 is kept.
Thus, if xmm_src < -150, the result of VRANGESS will be the minimal value of -150 while if xmm_src > +150,
the result of VRANGE will be the maximal value of +150.
Intel C/C++ Compiler Intrinsic Equivalent
VRANGESS __m128 _mm_range_ss ( __m128 a, __m128 b, int imm);
VRANGESS __m128 _mm_range_round_ss ( __m128 a, __m128 b, int imm, int sae);
VRANGESS __m128 _mm_mask_range_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRANGESS __m128 _mm_mask_range_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm, int sae);
VRANGESS __m128 _mm_maskz_range_ss ( __mmask8 k, __m128 a, __m128 b, int imm);
VRANGESS __m128 _mm_maskz_range_round_ss ( __mmask8 k, __m128 a, __m128 b, int imm, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Exceptions Type E3.
5-484 Vol. 2C
VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values
INSTRUCTION SET REFERENCE, V-Z
VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W1 4C /r
VRCP14PD xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.66.0F38.W1 4C /r
VRCP14PD ymm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.66.0F38.W1 4C /r
VRCP14PD zmm1 {k1}{z},
zmm2/m512/m64bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Computes the approximate reciprocals of the packed doubleprecision floating-point values in xmm2/m128/m64bcst and
stores the results in xmm1. Under writemask.
Computes the approximate reciprocals of the packed doubleprecision floating-point values in ymm2/m256/m64bcst and
stores the results in ymm1. Under writemask.
Computes the approximate reciprocals of the packed doubleprecision floating-point values in zmm2/m512/m64bcst and
stores the results in zmm1. Under writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
This instruction performs a SIMD computation of the approximate reciprocals of eight/four/two packed doubleprecision floating-point values in the source operand (the second operand) and stores the packed double-precision
floating-point results in the destination operand. The maximum relative error for this approximation is less than 214
.
The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64bit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.
The VRCP14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
Table 5-24. VRCP14PD/VRCP14SD Special Cases
Input value
Result value
Comments
0 ≤ X ≤ 2-1024
INF
Very small denormal
-2-1024 ≤
-INF
Very small denormal
Underflow
Up to 18 bits of fractions are returned*
-Underflow
Up to 18 bits of fractions are returned*
X>
X ≤ -0
21022
X < -21022
X=
2-n
X = -2-n
2n
-2n
* in this case the mantissa is shifted right by one or two bits
A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values
Vol. 2C 5-485
INSTRUCTION SET REFERENCE, V-Z
Operation
VRCP14PD ((EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+63:i] APPROXIMATE(1.0/SRC[63:0]);
ELSE DEST[i+63:i] APPROXIMATE(1.0/SRC[i+63:i]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VRCP14PD __m512d _mm512_rcp14_pd( __m512d a);
VRCP14PD __m512d _mm512_mask_rcp14_pd(__m512d s, __mmask8 k, __m512d a);
VRCP14PD __m512d _mm512_maskz_rcp14_pd( __mmask8 k, __m512d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.
5-486 Vol. 2C
VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value
Opcode/
Instruction
Op
/ En
EVEX.NDS.LIG.66.0F38.W1 4D /r
VRCP14SD xmm1 {k1}{z}, xmm2,
xmm3/m64
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Computes the approximate reciprocal of the scalar doubleprecision floating-point value in xmm3/m64 and stores the
result in xmm1 using writemask k1. Also, upper double-precision
floating-point value (bits[127:64]) from xmm2 is copied to
xmm1[127:64].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs a SIMD computation of the approximate reciprocal of the low double-precision floatingpoint value in the second source operand (the third operand) stores the result in the low quadword element of the
destination operand (the first operand) according to the writemask k1. Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand (the second operand). The maximum relative
error for this approximation is less than 2-14. The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register.
The VRCP14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned. See Table 5-24 for special-case input values.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRCP14SD (EVEX version)
IF k1[0] OR *no writemask*
THEN DEST[63:0] APPROXIMATE(1.0/SRC2[63:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value
Vol. 2C 5-487
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VRCP14SD __m128d _mm_rcp14_sd( __m128d a, __m128d b);
VRCP14SD __m128d _mm_mask_rcp14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VRCP14SD __m128d _mm_maskz_rcp14_sd( __mmask8 k, __m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E5.
5-488 Vol. 2C
VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value
INSTRUCTION SET REFERENCE, V-Z
VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W0 4C /r
VRCP14PS xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.66.0F38.W0 4C /r
VRCP14PS ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.66.0F38.W0 4C /r
VRCP14PS zmm1 {k1}{z},
zmm2/m512/m32bcst
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Computes the approximate reciprocals of the packed singleprecision floating-point values in xmm2/m128/m32bcst and
stores the results in xmm1. Under writemask.
Computes the approximate reciprocals of the packed singleprecision floating-point values in ymm2/m256/m32bcst and
stores the results in ymm1. Under writemask.
Computes the approximate reciprocals of the packed singleprecision floating-point values in zmm2/m512/m32bcst and
stores the results in zmm1. Under writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
This instruction performs a SIMD computation of the approximate reciprocals of the packed single-precision
floating-point values in the source operand (the second operand) and stores the packed single-precision floatingpoint results in the destination operand (the first operand). The maximum relative error for this approximation is
less than 2-14.
The source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32bit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.
The VRCP14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
Table 5-25. VRCP14PS/VRCP14SS Special Cases
Input value
Result value
Comments
0 ≤ X ≤ 2-128
INF
Very small denormal
-2-128 ≤
-INF
Very small denormal
Underflow
Up to 18 bits of fractions are returned*
-Underflow
Up to 18 bits of fractions are returned*
X>
X ≤ -0
2126
X < -2126
X=
2-n
X = -2-n
2n
-2n
* in this case the mantissa is shifted right by one or two bits
A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values
Vol. 2C 5-489
INSTRUCTION SET REFERENCE, V-Z
Operation
VRCP14PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+31:i] APPROXIMATE(1.0/SRC[31:0]);
ELSE DEST[i+31:i] APPROXIMATE(1.0/SRC[i+31:i]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VRCP14PS __m512 _mm512_rcp14_ps( __m512 a);
VRCP14PS __m512 _mm512_mask_rcp14_ps(__m512 s, __mmask16 k, __m512 a);
VRCP14PS __m512 _mm512_maskz_rcp14_ps( __mmask16 k, __m512 a);
VRCP14PS __m256 _mm256_rcp14_ps( __m256 a);
VRCP14PS __m256 _mm512_mask_rcp14_ps(__m256 s, __mmask8 k, __m256 a);
VRCP14PS __m256 _mm512_maskz_rcp14_ps( __mmask8 k, __m256 a);
VRCP14PS __m128 _mm_rcp14_ps( __m128 a);
VRCP14PS __m128 _mm_mask_rcp14_ps(__m128 s, __mmask8 k, __m128 a);
VRCP14PS __m128 _mm_maskz_rcp14_ps( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.
5-490 Vol. 2C
VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values
INSTRUCTION SET REFERENCE, V-Z
VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W0 4D /r
VRCP14SS xmm1 {k1}{z}, xmm2,
xmm3/m32
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Computes the approximate reciprocal of the scalar singleprecision floating-point value in xmm3/m32 and stores the
results in xmm1 using writemask k1. Also, upper doubleprecision floating-point value (bits[127:32]) from xmm2 is
copied to xmm1[127:32].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs a SIMD computation of the approximate reciprocal of the low single-precision floatingpoint value in the second source operand (the third operand) and stores the result in the low quadword element of
the destination operand (the first operand) according to the writemask k1. Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand (the second operand). The maximum relative
error for this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register.
The VRCP14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned. See Table 5-25 for special-case input values.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRCP14SS (EVEX version)
IF k1[0] OR *no writemask*
THEN DEST[31:0] APPROXIMATE(1.0/SRC2[31:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value
Vol. 2C 5-491
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VRCP14SS __m128 _mm_rcp14_ss( __m128 a, __m128 b);
VRCP14SS __m128 _mm_mask_rcp14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VRCP14SS __m128 _mm_maskz_rcp14_ss( __mmask8 k, __m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E5.
5-492 Vol. 2C
VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value
INSTRUCTION SET REFERENCE, V-Z
VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values
with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.512.66.0F38.W1 CA /r
VRCP28PD zmm1 {k1}{z},
zmm2/m512/m64bcst {sae}
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes the approximate reciprocals ( < 2^-28 relative error)
of the packed double-precision floating-point values in
zmm2/m512/m64bcst and stores the results in zmm1. Under
writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Computes the reciprocal approximation of the float64 values in the source operand (the second operand) and store
the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than
2^-28 of maximum relative error.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.
The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRCP28PD (EVEX encoded versions)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+63:i] RCP_28_DP(1.0/SRC[63:0]);
ELSE DEST[i+63:i] RCP_28_DP(1.0/SRC[i+63:i]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI;
FI;
ENDFOR;
VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
Vol. 2C 5-493
INSTRUCTION SET REFERENCE, V-Z
Table 5-26. VRCP28PD Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
2-1022
INF
Positive input denormal or zero; #Z
< X ≤ -0
-INF
Negative input denormal or zero; #Z
0≤X<
-2
-1022
X>
21022
X < -2
1022
+0.0f
-0.0f
X = +∞
+0.0f
X = -∞
-0.0f
X=
2-n
-n
X = -2
2n
-2
n
Exact result (unless input/output is a denormal)
Exact result (unless input/output is a denormal)
Intel C/C++ Compiler Intrinsic Equivalent
VRCP28PD __m512d _mm512_rcp28_round_pd ( __m512d a, int sae);
VRCP28PD __m512d _mm512_mask_rcp28_round_pd(__m512d a, __mmask8 m, __m512d b, int sae);
VRCP28PD __m512d _mm512_maskz_rcp28_round_pd( __mmask8 m, __m512d b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E2.
5-494 Vol. 2C
VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
INSTRUCTION SET REFERENCE, V-Z
VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value
with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W1 CB /r
VRCP28SD xmm1 {k1}{z}, xmm2,
xmm3/m64 {sae}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes the approximate reciprocal ( < 2^-28 relative
error) of the scalar double-precision floating-point value
in xmm3/m64 and stores the results in xmm1. Under
writemask. Also, upper double-precision floating-point
value (bits[127:64]) from xmm2 is copied to
xmm1[127:64].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Computes the reciprocal approximation of the low float64 value in the second source operand (the third operand)
and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with
less than 2^-28 of maximum relative error. The result is written into the low float64 element of the destination
operand according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the
first source operand (the second operand).
A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result
is flushed to zero and does not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.
The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory
location. The destination operand is a XMM register, conditionally updated using writemask k1.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRCP28SD ((EVEX encoded versions)
IF k1[0] OR *no writemask* THEN
DEST[63: 0] RCP_28_DP(1.0/SRC2[63: 0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63: 0] remains unchanged*
ELSE
; zeroing-masking
DEST[63: 0] 0
FI;
FI;
ENDFOR;
DEST[127:64] SRC1[127: 64]
DEST[MAX_VL-1:128] 0
VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
Vol. 2C 5-495
INSTRUCTION SET REFERENCE, V-Z
Table 5-27. VRCP28SD Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
2-1022
INF
Positive input denormal or zero; #Z
< X ≤ -0
-INF
Negative input denormal or zero; #Z
0≤X<
-2
-1022
X>
21022
X < -2
1022
+0.0f
-0.0f
X = +∞
+0.0f
X = -∞
-0.0f
X=
2-n
2n
-n
X = -2
-2
n
Exact result (unless input/output is a denormal)
Exact result (unless input/output is a denormal)
Intel C/C++ Compiler Intrinsic Equivalent
VRCP28SD __m128d _mm_rcp28_round_sd ( __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E3.
5-496 Vol. 2C
VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
INSTRUCTION SET REFERENCE, V-Z
VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values
with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.512.66.0F38.W0 CA /r
VRCP28PS zmm1 {k1}{z},
zmm2/m512/m32bcst {sae}
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes the approximate reciprocals ( < 2^-28 relative
error) of the packed single-precision floating-point values in
zmm2/m512/m32bcst and stores the results in zmm1. Under
writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Computes the reciprocal approximation of the float32 values in the source operand (the second operand) and store
the results to the destination operand (the first operand) using the writemask k1. The approximate reciprocal is
evaluated with less than 2^-28 of maximum relative error prior to final rounding. The final results are rounded to
< 2^-23 relative error before written to the destination.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.
The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRCP28PS (EVEX encoded versions)
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+31:i] RCP_28_SP(1.0/SRC[31:0]);
ELSE DEST[i+31:i] RCP_28_SP(1.0/SRC[i+31:i]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR;
VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
Vol. 2C 5-497
INSTRUCTION SET REFERENCE, V-Z
Table 5-28. VRCP28PS Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
2-126
INF
Positive input denormal or zero; #Z
< X ≤ -0
-INF
Negative input denormal or zero; #Z
0≤X<
-2
-126
X>
2126
X < -2
126
+0.0f
-0.0f
X = +∞
+0.0f
X = -∞
-0.0f
X=
2-n
2n
-n
X = -2
-2
n
Exact result (unless input/output is a denormal)
Exact result (unless input/output is a denormal)
Intel C/C++ Compiler Intrinsic Equivalent
VRCP28PS _mm512_rcp28_round_ps ( __m512 a, int sae);
VRCP28PS __m512 _mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a, int sae);
VRCP28PS __m512 _mm512_maskz_rcp28_round_ps( __mmask16 m, __m512 a, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E2.
5-498 Vol. 2C
VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
INSTRUCTION SET REFERENCE, V-Z
VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value
with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W0 CB /r
VRCP28SS xmm1 {k1}{z},
xmm2, xmm3/m32 {sae}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes the approximate reciprocal ( < 2^-28 relative
error) of the scalar single-precision floating-point value in
xmm3/m32 and stores the results in xmm1. Under
writemask. Also, upper 3 single-precision floating-point
values (bits[127:32]) from xmm2 is copied to
xmm1[127:32].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Computes the reciprocal approximation of the low float32 value in the second source operand (the third operand)
and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with
less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 relative
error before written into the low float32 element of the destination according to writemask k1. Bits 127:32 of the
destination is copied from the corresponding bits of the first source operand (the second operand).
A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result
is flushed to zero and does not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.
The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory
location. The destination operand is a XMM register, conditionally updated using writemask k1.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRCP28SS ((EVEX encoded versions)
IF k1[0] OR *no writemask* THEN
DEST[31: 0] RCP_28_SP(1.0/SRC2[31: 0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31: 0] remains unchanged*
ELSE
; zeroing-masking
DEST[31: 0] 0
FI;
FI;
ENDFOR;
DEST[127:32] SRC1[127: 32]
DEST[MAX_VL-1:128] 0
VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error
Vol. 2C 5-499
INSTRUCTION SET REFERENCE, V-Z
Table 5-29. VRCP28SS Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
2-126
INF
Positive input denormal or zero; #Z
< X ≤ -0
-INF
Negative input denormal or zero; #Z
0≤X<
-2
-126
X>
2126
X < -2
+0.0f
126
-0.0f
X = +∞
+0.0f
X = -∞
-0.0f
X=
2-n
2n
-n
X = -2
-2
n
Exact result (unless input/output is a denormal)
Exact result (unless input/output is a denormal)
Intel C/C++ Compiler Intrinsic Equivalent
VRCP28SS __m128 _mm_rcp28_round_ss ( __m128 a, __m128 b, int sae);
VRCP28SS __m128 _mm_mask_rcp28_round_ss(__m128 s, __mmask8 m, __m128 a, __m128 b, int sae);
VRCP28SS __m128 _mm_maskz_rcp28_round_ss(__mmask8 m, __m128 a, __m128 b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E3.
5-500 Vol. 2C
VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error
INSTRUCTION SET REFERENCE, V-Z
VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F3A.W1 56 /r ib
VREDUCEPD xmm1 {k1}{z},
xmm2/m128/m64bcst, imm8
EVEX.256.66.0F3A.W1 56 /r ib
VREDUCEPD ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512DQ
EVEX.512.66.0F3A.W1 56 /r ib
VREDUCEPD zmm1 {k1}{z},
zmm2/m512/m64bcst{sae},
imm8
FV
V/V
AVX512DQ
Description
Perform reduction transformation on packed double-precision
floating point values in xmm2/m128/m32bcst by subtracting
a number of fraction bits specified by the imm8 field. Stores
the result in xmm1 register under writemask k1.
Perform reduction transformation on packed double-precision
floating point values in ymm2/m256/m32bcst by subtracting
a number of fraction bits specified by the imm8 field. Stores
the result in ymm1 register under writemask k1.
Perform reduction transformation on double-precision floating
point values in zmm2/m512/m32bcst by subtracting a
number of fraction bits specified by the imm8 field. Stores the
result in zmm1 register under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Perform reduction transformation of the packed binary encoded double-precision FP values in the source operand
(the second operand) and store the reduced results in binary FP format to the destination operand (the first
operand) under the writemask k1.
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transformation can be expressed as:
dest = src – (ROUND(2M*src))*2-M;
where “Round()” treats “src”, “2M”, and their product as binary FP numbers with normalized significand and biased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC ≠ RNE: 0<=|Reduced Result|<2p-M
This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
7
imm8
6
5
4
Fixed point length
3
2
SPE
RS
1
Round Control Override
Suppress Precision Exception: Imm8[3]
Imm8[7:4] : Number of fixed points to subtract
0
Imm8[3] = 0b : Use MXCSR exception mask
Round Select: Imm8[2]
Imm8[3] = 1b : Suppress
Imm8[2] = 0b : Use Imm8[1:0]
Imm8[2] = 1b : Use MXCSR
Imm8[1:0] = 00b : Round nearest even
Imm8[1:0] = 01b : Round down
Imm8[1:0] = 10b : Round up
Imm8[1:0] = 11b : Truncate
Figure 5-28. Imm8 Controls for VREDUCEPD/SD/PS/SS
VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values
Vol. 2C 5-501
INSTRUCTION SET REFERENCE, V-Z
Handling of special case of input values are listed in Table 5-30.
Table 5-30. VREDUCEPD/SD/PS/SS Special Cases
Round Mode
Returned value
RNE
Src1
RPI, Src1 > 0
Round (Src1-2-M) *
RPI, Src1 ≤ 0
Src1
RNI, Src1 ≥ 0
Src1
RNI, Src1 < 0
Round (Src1+2-M) *
NOT RNI
+0.0
RNI
-0.0
Src1 = ±INF
any
+0.0
Src1= ±NAN
n/a
QNaN(Src1)
|Src1| <
|Src1| <
2-M-1
2-M
Src1 = ±0, or
Dest = ±0 (Src1!=INF)
* Round control = (imm8.MS1)? MXCSR.RC: imm8.RC
Operation
ReduceArgumentDP(SRC[63:0], imm8[7:0])
{
// Check for NaN
IF (SRC [63:0] = NAN) THEN
RETURN (Convert SRC[63:0] to QNaN); FI;
M imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
RC imm8[1:0];// Round Control for ROUND() operation
RC source imm[2];
SPE 0;// Suppress Precision Exception
TMP[63:0] 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
TMP[63:0] SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controls
RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
}
VREDUCEPD
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC *is memory*)
THEN DEST[i+63:i] ReduceArgumentDP(SRC[63:0], imm8[7:0]);
ELSE DEST[i+63:i] ReduceArgumentDP(SRC[i+63:i], imm8[7:0]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
5-502 Vol. 2C
VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VREDUCEPD __m512d _mm512_mask_reduce_pd( __m512d a, int imm, int sae)
VREDUCEPD __m512d _mm512_mask_reduce_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae)
VREDUCEPD __m512d _mm512_maskz_reduce_pd(__mmask8 k, __m512d a, int imm, int sae)
VREDUCEPD __m256d _mm256_mask_reduce_pd( __m256d a, int imm)
VREDUCEPD __m256d _mm256_mask_reduce_pd(__m256d s, __mmask8 k, __m256d a, int imm)
VREDUCEPD __m256d _mm256_maskz_reduce_pd(__mmask8 k, __m256d a, int imm)
VREDUCEPD __m128d _mm_mask_reduce_pd( __m128d a, int imm)
VREDUCEPD __m128d _mm_mask_reduce_pd(__m128d s, __mmask8 k, __m128d a, int imm)
VREDUCEPD __m128d _mm_maskz_reduce_pd(__mmask8 k, __m128d a, int imm)
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E2, additionally
#UD
If EVEX.vvvv != 1111B.
VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values
Vol. 2C 5-503
INSTRUCTION SET REFERENCE, V-Z
VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W1 57
VREDUCESD xmm1 {k1}{z},
xmm2, xmm3/m64{sae},
imm8/r
T1S
64/32 bit
Mode
Support
V/V
CPUID
Feature
Flag
AVX512D
Q
Description
Perform a reduction transformation on a scalar double-precision
floating point value in xmm3/m64 by subtracting a number of
fraction bits specified by the imm8 field. Also, upper double
precision floating-point value (bits[127:64]) from xmm2 are
copied to xmm1[127:64]. Stores the result in xmm1 register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Perform a reduction transformation of the binary encoded double-precision FP value in the low qword element of
the second source operand (the third operand) and store the reduced result in binary FP format to the low qword
element of the destination operand (the first operand) under the writemask k1. Bits 127:64 of the destination
operand are copied from respective qword elements of the first source operand (the second operand).
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transformation can be expressed as:
dest = src – (ROUND(2M*src))*2-M;
where “Round()” treats “src”, “2M”, and their product as binary FP numbers with normalized significand and biased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC ≠ RNE: 0<=|Reduced Result|<2p-M
This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
The operation is write masked.
Handling of special case of input values are listed in Table 5-30.
Operation
ReduceArgumentDP(SRC[63:0], imm8[7:0])
{
// Check for NaN
IF (SRC [63:0] = NAN) THEN
RETURN (Convert SRC[63:0] to QNaN); FI;
M imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
RC imm8[1:0];// Round Control for ROUND() operation
RC source imm[2];
SPE 0;// Suppress Precision Exception
TMP[63:0] 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
TMP[63:0] SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controls
RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
}
5-504 Vol. 2C
VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value
INSTRUCTION SET REFERENCE, V-Z
VREDUCESD
IF k1[0] or *no writemask*
THEN
DEST[63:0] ReduceArgumentDP(SRC2[63:0], imm8[7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] = 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VREDUCESD __m128d _mm_mask_reduce_sd( __m128d a, __m128d b, int imm, int sae)
VREDUCESD __m128d _mm_mask_reduce_sd(__m128d s, __mmask16 k, __m128d a, __m128d b, int imm, int sae)
VREDUCESD __m128d _mm_maskz_reduce_sd(__mmask16 k, __m128d a, __m128d b, int imm, int sae)
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E3.
VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value
Vol. 2C 5-505
INSTRUCTION SET REFERENCE, V-Z
VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512DQ
EVEX.128.66.0F3A.W0 56 /r ib
VREDUCEPS xmm1 {k1}{z},
xmm2/m128/m32bcst, imm8
EVEX.256.66.0F3A.W0 56 /r ib
VREDUCEPS ymm1 {k1}{z},
ymm2/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512DQ
EVEX.512.66.0F3A.W0 56 /r ib
VREDUCEPS zmm1 {k1}{z},
zmm2/m512/m32bcst{sae},
imm8
FV
V/V
AVX512DQ
Description
Perform reduction transformation on packed single-precision
floating point values in xmm2/m128/m32bcst by subtracting
a number of fraction bits specified by the imm8 field. Stores
the result in xmm1 register under writemask k1.
Perform reduction transformation on packed single-precision
floating point values in ymm2/m256/m32bcst by subtracting
a number of fraction bits specified by the imm8 field. Stores
the result in ymm1 register under writemask k1.
Perform reduction transformation on packed single-precision
floating point values in zmm2/m512/m32bcst by subtracting
a number of fraction bits specified by the imm8 field. Stores
the result in zmm1 register under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Perform reduction transformation of the packed binary encoded single-precision FP values in the source operand
(the second operand) and store the reduced results in binary FP format to the destination operand (the first
operand) under the writemask k1.
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transformation can be expressed as:
dest = src – (ROUND(2M*src))*2-M;
where “Round()” treats “src”, “2M”, and their product as binary FP numbers with normalized significand and biased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC ≠ RNE: 0<=|Reduced Result|<2p-M
This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Handling of special case of input values are listed in Table 5-30.
5-506 Vol. 2C
VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values
INSTRUCTION SET REFERENCE, V-Z
Operation
ReduceArgumentSP(SRC[31:0], imm8[7:0])
{
// Check for NaN
IF (SRC [31:0] = NAN) THEN
RETURN (Convert SRC[31:0] to QNaN); FI
M imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
RC imm8[1:0];// Round Control for ROUND() operation
RC source imm[2];
SPE 0;// Suppress Precision Exception
TMP[31:0] 2-M *{ROUND(2M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
TMP[31:0] SRC[31:0] – TMP[31:0]; // subtraction under the same RC,SPE controls
RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand
}
VREDUCEPS
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC *is memory*)
THEN DEST[i+31:i] ReduceArgumentSP(SRC[31:0], imm8[7:0]);
ELSE DEST[i+31:i] ReduceArgumentSP(SRC[i+31:i], imm8[7:0]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] = 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VREDUCEPS __m512 _mm512_mask_reduce_ps( __m512 a, int imm, int sae)
VREDUCEPS __m512 _mm512_mask_reduce_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae)
VREDUCEPS __m512 _mm512_maskz_reduce_ps(__mmask16 k, __m512 a, int imm, int sae)
VREDUCEPS __m256 _mm256_mask_reduce_ps( __m256 a, int imm)
VREDUCEPS __m256 _mm256_mask_reduce_ps(__m256 s, __mmask8 k, __m256 a, int imm)
VREDUCEPS __m256 _mm256_maskz_reduce_ps(__mmask8 k, __m256 a, int imm)
VREDUCEPS __m128 _mm_mask_reduce_ps( __m128 a, int imm)
VREDUCEPS __m128 _mm_mask_reduce_ps(__m128 s, __mmask8 k, __m128 a, int imm)
VREDUCEPS __m128 _mm_maskz_reduce_ps(__mmask8 k, __m128 a, int imm)
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E2, additionally
#UD
If EVEX.vvvv != 1111B.
VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values
Vol. 2C 5-507
INSTRUCTION SET REFERENCE, V-Z
VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W0 57
/r /ib
VREDUCESS xmm1 {k1}{z},
xmm2, xmm3/m32{sae},
imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512DQ
Description
Perform a reduction transformation on a scalar single-precision
floating point value in xmm3/m32 by subtracting a number of
fraction bits specified by the imm8 field. Also, upper single
precision floating-point values (bits[127:32]) from xmm2 are
copied to xmm1[127:32]. Stores the result in xmm1 register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Perform a reduction transformation of the binary encoded single-precision FP value in the low dword element of the
second source operand (the third operand) and store the reduced result in binary FP format to the low dword
element of the destination operand (the first operand) under the writemask k1. Bits 127:32 of the destination
operand are copied from respective dword elements of the first source operand (the second operand).
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transformation can be expressed as:
dest = src – (ROUND(2M*src))*2-M;
where “Round()” treats “src”, “2M”, and their product as binary FP numbers with normalized significand and biased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC ≠ RNE: 0<=|Reduced Result|<2p-M
This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
Handling of special case of input values are listed in Table 5-30.
Operation
ReduceArgumentSP(SRC[31:0], imm8[7:0])
{
// Check for NaN
IF (SRC [31:0] = NAN) THEN
RETURN (Convert SRC[31:0] to QNaN); FI
M imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
RC imm8[1:0];// Round Control for ROUND() operation
RC source imm[2];
SPE 0;// Suppress Precision Exception
TMP[31:0] 2-M *{ROUND(2M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
TMP[31:0] SRC[31:0] – TMP[31:0]; // subtraction under the same RC,SPE controls
RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand
}
5-508 Vol. 2C
VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value
INSTRUCTION SET REFERENCE, V-Z
VREDUCESS
IF k1[0] or *no writemask*
THEN
DEST[31:0] ReduceArgumentSP(SRC2[31:0], imm8[7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] = 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VREDUCESS __m128 _mm_mask_reduce_ss( __m128 a, __m128 b, int imm, int sae)
VREDUCESS __m128 _mm_mask_reduce_ss(__m128 s, __mmask16 k, __m128 a, __m128 b, int imm, int sae)
VREDUCESS __m128 _mm_maskz_reduce_ss(__mmask16 k, __m128 a, __m128 b, int imm, int sae)
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E3.
VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value
Vol. 2C 5-509
INSTRUCTION SET REFERENCE, V-Z
VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F3A.W1 09 /r ib
VRNDSCALEPD xmm1 {k1}{z},
xmm2/m128/m64bcst, imm8
EVEX.256.66.0F3A.W1 09 /r ib
VRNDSCALEPD ymm1 {k1}{z},
ymm2/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F3A.W1 09 /r ib
VRNDSCALEPD zmm1 {k1}{z},
zmm2/m512/m64bcst{sae}, imm8
FV
V/V
AVX512F
Description
Rounds packed double-precision floating point values in
xmm2/m128/m64bcst to a number of fraction bits
specified by the imm8 field. Stores the result in xmm1
register. Under writemask.
Rounds packed double-precision floating point values in
ymm2/m256/m64bcst to a number of fraction bits
specified by the imm8 field. Stores the result in ymm1
register. Under writemask.
Rounds packed double-precision floating-point values in
zmm2/m512/m64bcst to a number of fraction bits
specified by the imm8 field. Stores the result in zmm1
register using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Round the double-precision floating-point values in the source operand by the rounding mode specified in the
immediate operand (see Figure 5-29) and places the result in the destination operand.
The destination operand (the first operand) is a ZMM/YMM/XMM register conditionally updated according to the
writemask. The source operand (the second operand) can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a double-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.
The formula of the operation on each data element for VRNDSCALEPD is
ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
round_ctrl = imm[3:0];
M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).
5-510 Vol. 2C
VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits
INSTRUCTION SET REFERENCE, V-Z
VRNDSCALEPD is a more general form of the VEX-encoded VROUNDPD instruction. In VROUNDPD, the formula of
the operation on each element is
ROUND(x) = Round_to_INT(x, round_ctrl),
round_ctrl = imm[3:0];
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
7
imm8
6
5
4
Fixed point length
3
2
SPE
RS
1
Round Control Override
Suppress Precision Exception: Imm8[3]
Imm8[7:4] : Number of fixed points to preserve
0
Imm8[3] = 0b : Use MXCSR exception mask
Round Select: Imm8[2]
Imm8[3] = 1b : Suppress
Imm8[2] = 0b : Use Imm8[1:0]
Imm8[2] = 1b : Use MXCSR
Imm8[1:0] = 00b : Round nearest even
Imm8[1:0] = 01b : Round down
Imm8[1:0] = 10b : Round up
Imm8[1:0] = 11b : Truncate
Figure 5-29. Imm8 Controls for VRNDSCALEPD/SD/PS/SS
Handling of special case of input values are listed in Table 5-31.
Table 5-31. VRNDSCALEPD/SD/PS/SS Special Cases
Returned value
Src1=±inf
Src1
Src1=±NAN
Src1 converted to QNAN
Src1=±0
Src1
VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits
Vol. 2C 5-511
INSTRUCTION SET REFERENCE, V-Z
Operation
RoundToIntegerDP(SRC[63:0], imm8[7:0]) {
if (imm8[2] = 1)
rounding_direction MXCSR:RC
; get round control from MXCSR
else
rounding_direction imm8[1:0]
; get round control from imm8[1:0]
FI
M imm8[7:4]
; get the scaling factor
case (rounding_direction)
00: TMP[63:0] round_to_nearest_even_integer(2M*SRC[63:0])
01: TMP[63:0] round_to_equal_or_smaller_integer(2M*SRC[63:0])
10: TMP[63:0] round_to_equal_or_larger_integer(2M*SRC[63:0])
11: TMP[63:0] round_to_nearest_smallest_magnitude_integer(2M*SRC[63:0])
ESAC
Dest[63:0] 2-M* TMP[63:0]
; scale down back to 2-M
if (imm8[3] = 0) Then ; check SPE
if (SRC[63:0] != Dest[63:0]) Then
; check precision lost
set_precision()
; set #PE
FI;
FI;
return(Dest[63:0])
}
5-512 Vol. 2C
VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits
INSTRUCTION SET REFERENCE, V-Z
VRNDSCALEPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF *src is a memory operand*
THEN TMP_SRC BROADCAST64(SRC, VL, k1)
ELSE TMP_SRC SRC
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] RoundToIntegerDP((TMP_SRC[i+63:i], imm8[7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALEPD __m512d _mm512_roundscale_pd( __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_roundscale_round_pd( __m512d a, int imm, int sae);
VRNDSCALEPD __m512d _mm512_mask_roundscale_pd(__m512d s, __mmask8 k, __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_mask_roundscale_round_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae);
VRNDSCALEPD __m512d _mm512_maskz_roundscale_pd( __mmask8 k, __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_maskz_roundscale_round_pd( __mmask8 k, __m512d a, int imm, int sae);
VRNDSCALEPD __m256d _mm256_roundscale_pd( __m256d a, int imm);
VRNDSCALEPD __m256d _mm256_mask_roundscale_pd(__m256d s, __mmask8 k, __m256d a, int imm);
VRNDSCALEPD __m256d _mm256_maskz_roundscale_pd( __mmask8 k, __m256d a, int imm);
VRNDSCALEPD __m128d _mm_roundscale_pd( __m128d a, int imm);
VRNDSCALEPD __m128d _mm_mask_roundscale_pd(__m128d s, __mmask8 k, __m128d a, int imm);
VRNDSCALEPD __m128d _mm_maskz_roundscale_pd( __mmask8 k, __m128d a, int imm);
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E2.
VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits
Vol. 2C 5-513
INSTRUCTION SET REFERENCE, V-Z
VRNDSCALESD—Round Scalar Float64 Value To Include A Given Number Of Fraction Bits
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W1 0B /r ib
VRNDSCALESD xmm1 {k1}{z}, xmm2,
xmm3/m64{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Rounds scalar double-precision floating-point value in
xmm3/m64 to a number of fraction bits specified by the
imm8 field. Stores the result in xmm1 register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
Imm8
Description
Rounds a double-precision floating-point value in the low quadword (see Figure 5-29) element the second source
operand (the third operand) by the rounding mode specified in the immediate operand and places the result in the
corresponding element of the destination operand (the third operand) according to the writemask. The quadword
element at bits 127:64 of the destination is copied from the first source operand (the second operand).
The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or
memory location. Bits MAX_VL-1:128 of the destination register are cleared.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a double-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.
The formula of the operation for VRNDSCALESD is
ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
round_ctrl = imm[3:0];
M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).
VRNDSCALESD is a more general form of the VEX-encoded VROUNDSD instruction. In VROUNDSD, the formula of
the operation is
ROUND(x) = Round_to_INT(x, round_ctrl),
round_ctrl = imm[3:0];
EVEX encoded version: The source operand is a XMM register or a 64-bit memory location. The destination operand
is a XMM register.
Handling of special case of input values are listed in Table 5-31.
5-514 Vol. 2C
VRNDSCALESD—Round Scalar Float64 Value To Include A Given Number Of Fraction Bits
INSTRUCTION SET REFERENCE, V-Z
Operation
RoundToIntegerDP(SRC[63:0], imm8[7:0]) {
if (imm8[2] = 1)
rounding_direction MXCSR:RC
; get round control from MXCSR
else
rounding_direction imm8[1:0]
; get round control from imm8[1:0]
FI
M imm8[7:4]
; get the scaling factor
case (rounding_direction)
00: TMP[63:0] round_to_nearest_even_integer(2M*SRC[63:0])
01: TMP[63:0] round_to_equal_or_smaller_integer(2M*SRC[63:0])
10: TMP[63:0] round_to_equal_or_larger_integer(2M*SRC[63:0])
11: TMP[63:0] round_to_nearest_smallest_magnitude_integer(2M*SRC[63:0])
ESAC
Dest[63:0] 2-M* TMP[63:0]
; scale down back to 2-M
if (imm8[3] = 0) Then ; check SPE
if (SRC[63:0] != Dest[63:0]) Then
; check precision lost
set_precision()
; set #PE
FI;
FI;
return(Dest[63:0])
}
VRNDSCALESD (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[63:0] RoundToIntegerDP(SRC2[63:0], Zero_upper_imm[7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALESD __m128d _mm_roundscale_sd ( __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_roundscale_round_sd ( __m128d a, __m128d b, int imm, int sae);
VRNDSCALESD __m128d _mm_mask_roundscale_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_mask_roundscale_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm, int sae);
VRNDSCALESD __m128d _mm_maskz_roundscale_sd ( __mmask8 k, __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_maskz_roundscale_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E3.
VRNDSCALESD—Round Scalar Float64 Value To Include A Given Number Of Fraction Bits
Vol. 2C 5-515
INSTRUCTION SET REFERENCE, V-Z
VRNDSCALEPS—Round Packed Float32 Values To Include A Given Number Of Fraction Bits
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F3A.W0 08 /r ib
VRNDSCALEPS xmm1 {k1}{z},
xmm2/m128/m32bcst, imm8
EVEX.256.66.0F3A.W0 08 /r ib
VRNDSCALEPS ymm1 {k1}{z},
ymm2/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F3A.W0 08 /r ib
VRNDSCALEPS zmm1 {k1}{z},
zmm2/m512/m32bcst{sae}, imm8
FV
V/V
AVX512F
Description
Rounds packed single-precision floating point values in
xmm2/m128/m32bcst to a number of fraction bits
specified by the imm8 field. Stores the result in xmm1
register. Under writemask.
Rounds packed single-precision floating point values in
ymm2/m256/m32bcst to a number of fraction bits
specified by the imm8 field. Stores the result in ymm1
register. Under writemask.
Rounds packed single-precision floating-point values in
zmm2/m512/m32bcst to a number of fraction bits
specified by the imm8 field. Stores the result in zmm1
register using writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
Imm8
NA
Description
Round the single-precision floating-point values in the source operand by the rounding mode specified in the immediate operand (see Figure 5-29) and places the result in the destination operand.
The destination operand (the first operand) is a ZMM register conditionally updated according to the writemask.
The source operand (the second operand) can be a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32-bit memory location.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.
The formula of the operation on each data element for VRNDSCALEPS is
ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
round_ctrl = imm[3:0];
M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).
VRNDSCALEPS is a more general form of the VEX-encoded VROUNDPS instruction. In VROUNDPS, the formula of
the operation on each element is
ROUND(x) = Round_to_INT(x, round_ctrl),
round_ctrl = imm[3:0];
5-516 Vol. 2C
VRNDSCALEPS—Round Packed Float32 Values To Include A Given Number Of Fraction Bits
INSTRUCTION SET REFERENCE, V-Z
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Handling of special case of input values are listed in Table 5-31.
Operation
RoundToIntegerSP(SRC[31:0], imm8[7:0]) {
if (imm8[2] = 1)
rounding_direction MXCSR:RC
; get round control from MXCSR
else
rounding_direction imm8[1:0]
; get round control from imm8[1:0]
FI
M imm8[7:4]
; get the scaling factor
case (rounding_direction)
00: TMP[31:0] round_to_nearest_even_integer(2M*SRC[31:0])
01: TMP[31:0] round_to_equal_or_smaller_integer(2M*SRC[31:0])
10: TMP[31:0] round_to_equal_or_larger_integer(2M*SRC[31:0])
11: TMP[31:0] round_to_nearest_smallest_magnitude_integer(2M*SRC[31:0])
ESAC;
Dest[31:0] 2-M* TMP[31:0]
; scale down back to 2-M
if (imm8[3] = 0) Then
; check SPE
if (SRC[31:0] != Dest[31:0]) Then
; check precision lost
set_precision()
; set #PE
FI;
FI;
return(Dest[31:0])
}
VRNDSCALEPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF *src is a memory operand*
THEN TMP_SRC BROADCAST32(SRC, VL, k1)
ELSE TMP_SRC SRC
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] RoundToIntegerSP(TMP_SRC[i+31:i]), imm8[7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
VRNDSCALEPS—Round Packed Float32 Values To Include A Given Number Of Fraction Bits
Vol. 2C 5-517
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALEPS __m512 _mm512_roundscale_ps( __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_roundscale_round_ps( __m512 a, int imm, int sae);
VRNDSCALEPS __m512 _mm512_mask_roundscale_ps(__m512 s, __mmask16 k, __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_mask_roundscale_round_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae);
VRNDSCALEPS __m512 _mm512_maskz_roundscale_ps( __mmask16 k, __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_maskz_roundscale_round_ps( __mmask16 k, __m512 a, int imm, int sae);
VRNDSCALEPS __m256 _mm256_roundscale_ps( __m256 a, int imm);
VRNDSCALEPS __m256 _mm256_mask_roundscale_ps(__m256 s, __mmask8 k, __m256 a, int imm);
VRNDSCALEPS __m256 _mm256_maskz_roundscale_ps( __mmask8 k, __m256 a, int imm);
VRNDSCALEPS __m128 _mm_roundscale_ps( __m256 a, int imm);
VRNDSCALEPS __m128 _mm_mask_roundscale_ps(__m128 s, __mmask8 k, __m128 a, int imm);
VRNDSCALEPS __m128 _mm_maskz_roundscale_ps( __mmask8 k, __m128 a, int imm);
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E2.
5-518 Vol. 2C
VRNDSCALEPS—Round Packed Float32 Values To Include A Given Number Of Fraction Bits
INSTRUCTION SET REFERENCE, V-Z
VRNDSCALESS—Round Scalar Float32 Value To Include A Given Number Of Fraction Bits
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F3A.W0 0A /r ib
VRNDSCALESS xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}, imm8
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Rounds scalar single-precision floating-point value in
xmm3/m32 to a number of fraction bits specified by the
imm8 field. Stores the result in xmm1 register under
writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Rounds the single-precision floating-point value in the low doubleword element of the second source operand (the
third operand) by the rounding mode specified in the immediate operand (see Figure 5-29) and places the result in
the corresponding element of the destination operand (the first operand) according to the writemask. The doubleword elements at bits 127:32 of the destination are copied from the first source operand (the second operand).
The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or
memory location. Bits MAX_VL-1:128 of the destination register are cleared.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control tables below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.
The formula of the operation for VRNDSCALESS is
ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
round_ctrl = imm[3:0];
M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).
VRNDSCALESS is a more general form of the VEX-encoded VROUNDSS instruction. In VROUNDSS, the formula of
the operation on each element is
ROUND(x) = Round_to_INT(x, round_ctrl),
round_ctrl = imm[3:0];
EVEX encoded version: The source operand is a XMM register or a 32-bit memory location. The destination operand
is a XMM register.
Handling of special case of input values are listed in Table 5-31.
VRNDSCALESS—Round Scalar Float32 Value To Include A Given Number Of Fraction Bits
Vol. 2C 5-519
INSTRUCTION SET REFERENCE, V-Z
Operation
RoundToIntegerSP(SRC[31:0], imm8[7:0]) {
if (imm8[2] = 1)
rounding_direction MXCSR:RC
; get round control from MXCSR
else
rounding_direction imm8[1:0]
; get round control from imm8[1:0]
FI
M imm8[7:4]
; get the scaling factor
case (rounding_direction)
00: TMP[31:0] round_to_nearest_even_integer(2M*SRC[31:0])
01: TMP[31:0] round_to_equal_or_smaller_integer(2M*SRC[31:0])
10: TMP[31:0] round_to_equal_or_larger_integer(2M*SRC[31:0])
11: TMP[31:0] round_to_nearest_smallest_magnitude_integer(2M*SRC[31:0])
ESAC;
Dest[31:0] 2-M* TMP[31:0]
; scale down back to 2-M
if (imm8[3] = 0) Then
; check SPE
if (SRC[31:0] != Dest[31:0]) Then
; check precision lost
set_precision()
; set #PE
FI;
FI;
return(Dest[31:0])
}
VRNDSCALESS (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[31:0] RoundToIntegerSP(SRC2[31:0], Zero_upper_imm[7:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALESS __m128 _mm_roundscale_ss ( __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_roundscale_round_ss ( __m128 a, __m128 b, int imm, int sae);
VRNDSCALESS __m128 _mm_mask_roundscale_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_mask_roundscale_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm, int sae);
VRNDSCALESS __m128 _mm_maskz_roundscale_ss ( __mmask8 k, __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_maskz_roundscale_round_ss ( __mmask8 k, __m128 a, __m128 b, int imm, int sae);
SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
Other Exceptions
See Exceptions Type E3.
5-520 Vol. 2C
VRNDSCALESS—Round Scalar Float32 Value To Include A Given Number Of Fraction Bits
INSTRUCTION SET REFERENCE, V-Z
VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W1 4E /r
VRSQRT14PD xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.66.0F38.W1 4E /r
VRSQRT14PD ymm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.W1 4E /r
VRSQRT14PD zmm1 {k1}{z},
zmm2/m512/m64bcst
FV
V/V
AVX512F
Description
Computes the approximate reciprocal square roots of the
packed double-precision floating-point values in
xmm2/m128/m64bcst and stores the results in xmm1.
Under writemask.
Computes the approximate reciprocal square roots of the
packed double-precision floating-point values in
ymm2/m256/m64bcst and stores the results in ymm1.
Under writemask.
Computes the approximate reciprocal square roots of the
packed double-precision floating-point values in
zmm2/m512/m64bcst and stores the results in zmm1
under writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
This instruction performs a SIMD computation of the approximate reciprocals of the square roots of the eight
packed double-precision floating-point values in the source operand (the second operand) and stores the packed
double-precision floating-point results in the destination operand (the first operand) according to the writemask.
The maximum relative error for this approximation is less than 2-14.
EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally
updated using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using
writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using
writemask k1.
The VRSQRT14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO
value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated
correctly and performs the approximation with the specified masked response. When a source value is a negative
value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the
SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values
Vol. 2C 5-521
INSTRUCTION SET REFERENCE, V-Z
Operation
VRSQRT14PD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+63:i] APPROXIMATE(1.0/ SQRT(SRC[63:0]));
ELSE DEST[i+63:i] APPROXIMATE(1.0/ SQRT(SRC[i+63:i]));
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Table 5-32. VRSQRT14PD Special Cases
Input value
Result value
Comments
Any denormal
Normal
Cannot generate overflow
X=
2-2n
2n
X<0
QNaN_Indefinite
X = -0
-INF
X = +0
+INF
X = +INF
+0
Including -INF
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14PD __m512d _mm512_rsqrt14_pd( __m512d a);
VRSQRT14PD __m512d _mm512_mask_rsqrt14_pd(__m512d s, __mmask8 k, __m512d a);
VRSQRT14PD __m512d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m512d a);
VRSQRT14PD __m256d _mm256_rsqrt14_pd( __m256d a);
VRSQRT14PD __m256d _mm512_mask_rsqrt14_pd(__m256d s, __mmask8 k, __m256d a);
VRSQRT14PD __m256d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m256d a);
VRSQRT14PD __m128d _mm_rsqrt14_pd( __m128d a);
VRSQRT14PD __m128d _mm_mask_rsqrt14_pd(__m128d s, __mmask8 k, __m128d a);
VRSQRT14PD __m128d _mm_maskz_rsqrt14_pd( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4.
5-522 Vol. 2C
VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W1 4F /r
VRSQRT14SD xmm1 {k1}{z},
xmm2, xmm3/m64
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Computes the approximate reciprocal square root of the
scalar double-precision floating-point value in xmm3/m64
and stores the result in the low quadword element of xmm1
using writemask k1. Bits[127:64] of xmm2 is copied to
xmm1[127:64].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Computes the approximate reciprocal of the square roots of the scalar double-precision floating-point value in the
low quadword element of the source operand (the second operand) and stores the result in the low quadword
element of the destination operand (the first operand) according to the writemask. The maximum relative error for
this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The
destination operand is an XMM register.
Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
The VRSQRT14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO
value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated
correctly and performs the approximation with the specified masked response. When a source value is a negative
value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the
SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRSQRT14SD (EVEX version)
IF k1[0] or *no writemask*
THEN
DEST[63:0] APPROXIMATE(1.0/ SQRT(SRC2[63:0]))
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] 0
FI;
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
Vol. 2C 5-523
INSTRUCTION SET REFERENCE, V-Z
Table 5-33. VRSQRT14SD Special Cases
Input value
Result value
Comments
Any denormal
Normal
Cannot generate overflow
X=
2-2n
2
n
X<0
QNaN_Indefinite
X = -0
-INF
X = +0
+INF
X = +INF
+0
Including -INF
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14SD __m128d _mm_rsqrt14_sd( __m128d a, __m128d b);
VRSQRT14SD __m128d _mm_mask_rsqrt14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VRSQRT14SD __m128d _mm_maskz_rsqrt14_sd( __mmask8d m, __m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E5.
5-524 Vol. 2C
VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
INSTRUCTION SET REFERENCE, V-Z
VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.128.66.0F38.W0 4E /r
VRSQRT14PS xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.66.0F38.W0 4E /r
VRSQRT14PS ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F38.W0 4E /r
VRSQRT14PS zmm1 {k1}{z},
zmm2/m512/m32bcst
FV
V/V
AVX512F
Description
Computes the approximate reciprocal square roots of the
packed single-precision floating-point values in
xmm2/m128/m32bcst and stores the results in xmm1.
Under writemask.
Computes the approximate reciprocal square roots of the
packed single-precision floating-point values in
ymm2/m256/m32bcst and stores the results in ymm1.
Under writemask.
Computes the approximate reciprocal square roots of the
packed single-precision floating-point values in
zmm2/m512/m32bcst and stores the results in zmm1. Under
writemask.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
This instruction performs a SIMD computation of the approximate reciprocals of the square roots of 16 packed
single-precision floating-point values in the source operand (the second operand) and stores the packed singleprecision floating-point results in the destination operand (the first operand) according to the writemask. The
maximum relative error for this approximation is less than 2-14.
EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit
vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally
updated using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using
writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using
writemask k1.
The VRSQRT14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO
value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated
correctly and performs the approximation with the specified masked response. When a source value is a negative
value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the
SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values
Vol. 2C 5-525
INSTRUCTION SET REFERENCE, V-Z
Operation
VRSQRT14PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+31:i] APPROXIMATE(1.0/ SQRT(SRC[31:0]));
ELSE DEST[i+31:i] APPROXIMATE(1.0/ SQRT(SRC[i+31:i]));
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR;
DEST[MAX_VL-1:VL] 0
Table 5-34. VRSQRT14PS Special Cases
Input value
Result value
Comments
Any denormal
Normal
Cannot generate overflow
X=
2-2n
2n
X<0
QNaN_Indefinite
X = -0
-INF
X = +0
+INF
X = +INF
+0
Including -INF
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a);
VRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a);
VRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a);
VRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a);
VRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a);
VRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a);
VRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a);
VRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a);
VRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
5-526 Vol. 2C
VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values
INSTRUCTION SET REFERENCE, V-Z
VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W0 4F /r
VRSQRT14SS xmm1 {k1}{z},
xmm2, xmm3/m32
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Computes the approximate reciprocal square root of the
scalar single-precision floating-point value in xmm3/m32
and stores the result in the low doubleword element of
xmm1 using writemask k1. Bits[127:32] of xmm2 is copied
to xmm1[127:32].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
Description
Computes of the approximate reciprocal of the square root of the scalar single-precision floating-point value in the
low doubleword element of the source operand (the second operand) and stores the result in the low doubleword
element of the destination operand (the first operand) according to the writemask. The maximum relative error for
this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The
destination operand is an XMM register.
Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
The VRSQRT14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an ∞, zero with the
sign of the source value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR.
Otherwise it is treated correctly and performs the approximation with the specified masked response. When a
source value is a negative value (other than 0.0) a floating-point indefinite is returned. When a source value is an
SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRSQRT14SS (EVEX version)
IF k1[0] or *no writemask*
THEN
DEST[31:0] APPROXIMATE(1.0/ SQRT(SRC2[31:0]))
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] 0
FI;
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
Vol. 2C 5-527
INSTRUCTION SET REFERENCE, V-Z
Table 5-35. VRSQRT14SS Special Cases
Input value
Result value
Comments
Any denormal
Normal
Cannot generate overflow
X=
2-2n
2
n
X<0
QNaN_Indefinite
X = -0
-INF
X = +0
+INF
X = +INF
+0
Including -INF
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14SS __m128 _mm_rsqrt14_ss( __m128 a, __m128 b);
VRSQRT14SS __m128 _mm_mask_rsqrt14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VRSQRT14SS __m128 _mm_maskz_rsqrt14_ss( __mmask8 k, __m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E5.
5-528 Vol. 2C
VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
INSTRUCTION SET REFERENCE, V-Z
VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision
Floating-Point Values with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.512.66.0F38.W1 CC /r
VRSQRT28PD zmm1 {k1}{z},
zmm2/m512/m64bcst {sae}
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes approximations to the Reciprocal square root (<2^28 relative error) of the packed double-precision floating-point
values from zmm2/m512/m64bcst and stores result in
zmm1with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Computes the reciprocal square root of the float64 values in the source operand (the second operand) and store
the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than
2^-28 of maximum relative error.
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -∞ and set the DivByZero flag.
The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRSQRT28PD (EVEX encoded versions)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+63:i] (1.0/ SQRT(SRC[63:0]));
ELSE DEST[i+63:i] (1.0/ SQRT(SRC[i+63:i]));
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI;
FI;
ENDFOR;
VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28
Vol. 2C 5-529
INSTRUCTION SET REFERENCE, V-Z
Table 5-36. VRSQRT28PD Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
X=
2-2n
n
2
X<0
QNaN_Indefinite
Including -INF
X = -0 or negative denormal
-INF
#Z
X = +0 or positive denormal
+INF
#Z
X = +INF
+0
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28PD __m512d _mm512_rsqrt28_round_pd(__m512d a, int sae);
VRSQRT28PD __m512d _mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m,__m512d a, int sae);
VRSQRT28PD __m512d _mm512_maskz_rsqrt28_round_pd(__mmask8 m,__m512d a, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E2.
5-530 Vol. 2C
VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28
INSTRUCTION SET REFERENCE, V-Z
VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double-Precision
Floating-Point Value with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W1 CD /r
VRSQRT28SD xmm1 {k1}{z},
xmm2, xmm3/m64 {sae}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes approximate reciprocal square root (<2^-28
relative error) of the scalar double-precision floating-point
value from xmm3/m64 and stores result in xmm1with
writemask k1. Also, upper double-precision floating-point
value (bits[127:64]) from xmm2 is copied to
xmm1[127:64].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Computes the reciprocal square root of the low float64 value in the second source operand (the third operand) and
store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated
with less than 2^-28 of maximum relative error. The result is written into the low float64 element of xmm1
according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the first source operand
(the second operand).
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -∞ and set the DivByZero flag.
The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory
location. The destination operand is a XMM register.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRSQRT28SD (EVEX encoded versions)
IF k1[0] OR *no writemask* THEN
DEST[63: 0] (1.0/ SQRT(SRC[63: 0]));
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63: 0] remains unchanged*
ELSE
; zeroing-masking
DEST[63: 0] 0
FI;
FI;
ENDFOR;
DEST[127:64] SRC1[127: 64]
DEST[MAX_VL-1:128] 0
VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28
Vol. 2C 5-531
INSTRUCTION SET REFERENCE, V-Z
Table 5-37. VRSQRT28SD Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
X=
2-2n
n
2
X<0
QNaN_Indefinite
Including -INF
X = -0 or negative denormal
-INF
#Z
X = +0 or positive denormal
+INF
#Z
X = +INF
+0
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28SD __m128d _mm_rsqrt28_round_sd(__m128d a, __m128b b, int sae);
VRSQRT28SD __m128d _mm_mask_rsqrt28_round_pd(__m128d s, __mmask8 m,__m128d a, __m128d b, int sae);
VRSQRT28SD __m128d _mm_maskz_rsqrt28_round_pd( __mmask8 m,__m128d a, __m128d b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E3.
5-532 Vol. 2C
VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28
INSTRUCTION SET REFERENCE, V-Z
VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single-Precision
Floating-Point Values with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.512.66.0F38.W0 CC /r
VRSQRT28PS zmm1 {k1}{z},
zmm2/m512/m32bcst {sae}
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes approximations to the Reciprocal square root
(<2^-28 relative error) of the packed single-precision
floating-point values from zmm2/m512/m32bcst and stores
result in zmm1with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Computes the reciprocal square root of the float32 values in the source operand (the second operand) and store
the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than
2^-28 of maximum relative error prior to final rounding. The final results is rounded to < 2^-23 relative error
before written to the destination.
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -∞ and set the DivByZero flag.
The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRSQRT28PS (EVEX encoded versions)
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+31:i] (1.0/ SQRT(SRC[31:0]));
ELSE DEST[i+31:i] (1.0/ SQRT(SRC[i+31:i]));
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI;
FI;
ENDFOR;
VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28
Vol. 2C 5-533
INSTRUCTION SET REFERENCE, V-Z
Table 5-38. VRSQRT28PS Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
X=
2-2n
n
2
X<0
QNaN_Indefinite
Including -INF
X = -0 or negative denormal
-INF
#Z
X = +0 or positive denormal
+INF
#Z
X = +INF
+0
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28PS __m512 _mm512_rsqrt28_round_ps(__m512 a, int sae);
VRSQRT28PS __m512 _mm512_mask_rsqrt28_round_ps(__m512 s, __mmask16 m,__m512 a, int sae);
VRSQRT28PS __m512 _mm512_maskz_rsqrt28_round_ps(__mmask16 m,__m512 a, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E2.
5-534 Vol. 2C
VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28
INSTRUCTION SET REFERENCE, V-Z
VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single-Precision FloatingPoint Value with Less Than 2^-28 Relative Error
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W0 CD /r
VRSQRT28SS xmm1 {k1}{z},
xmm2, xmm3/m32 {sae}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512ER
Description
Computes approximate reciprocal square root (<2^-28
relative error) of the scalar single-precision floating-point
value from xmm3/m32 and stores result in xmm1with
writemask k1. Also, upper 3 single-precision floating-point
value (bits[127:32]) from xmm2 is copied to
xmm1[127:32].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Computes the reciprocal square root of the low float32 value in the second source operand (the third operand) and
store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated
with less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 relative error before written to the low float32 element of the destination according to the writemask k1. Bits 127:32 of
the destination is copied from the corresponding bits of the first source operand (the second operand).
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -∞ and set the DivByZero flag.
The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory
location. The destination operand is a XMM register.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRSQRT28SS (EVEX encoded versions)
IF k1[0] OR *no writemask* THEN
DEST[31: 0] (1.0/ SQRT(SRC[31: 0]));
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31: 0] remains unchanged*
ELSE
; zeroing-masking
DEST[31: 0] 0
FI;
FI;
ENDFOR;
DEST[127:32] SRC1[127: 32]
DEST[MAX_VL-1:128] 0
VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Rel-
Vol. 2C 5-535
INSTRUCTION SET REFERENCE, V-Z
Table 5-39. VRSQRT28SS Special Cases
Input value
Result value
Comments
NAN
QNAN(input)
If (SRC = SNaN) then #I
X=
2-2n
n
2
X<0
QNaN_Indefinite
Including -INF
X = -0 or negative denormal
-INF
#Z
X = +0 or positive denormal
+INF
#Z
X = +INF
+0
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28SS __m128 _mm_rsqrt28_round_ss(__m128 a, __m128 b, int sae);
VRSQRT28SS __m128 _mm512_mask_rsqrt28_round_ss(__m128 s, __mmask8 m,__m128 a,__m128 b, int sae);
VRSQRT28SS __m128 _mm512_maskz_rsqrt28_round_ss(__mmask8 m,__m128 a,__m128 b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E3.
5-536 Vol. 2C
VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Rel-
INSTRUCTION SET REFERENCE, V-Z
VSCALEFPD—Scale Packed Float64 Values With Float64 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W1 2C /r
VSCALEFPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F38.W1 2C /r
VSCALEFPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F38.W1 2C /r
VSCALEFPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Scale the packed double-precision floating-point values in
xmm2 using values from xmm3/m128/m64bcst. Under
writemask k1.
Scale the packed double-precision floating-point values in
ymm2 using values from ymm3/m256/m64bcst. Under
writemask k1.
Scale the packed double-precision floating-point values in
zmm2 using values from zmm3/m512/m64bcst. Under
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a floating-point scale of the packed double-precision floating-point values in the first source operand by
multiplying it by 2 power of the double-precision floating-point values in second source operand.
The equation of this operation is given by:
zmm1 := zmm2*2floor(zmm3).
Floor(zmm3) means maximum integer value ≤ zmm3.
If the result cannot be represented in double precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a
512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The
destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-40 and Table 5-41.
Table 5-40. \VSCALEFPD/SD/PS/SS Special Cases
Src2
Src1
Set IE
±NaN
+Inf
-Inf
0/Denorm/Norm
±QNaN
QNaN(Src1)
+INF
+0
QNaN(Src1)
IF either source is SNAN
±SNaN
QNaN(Src1)
QNaN(Src1)
QNaN(Src1)
QNaN(Src1)
YES
±Inf
QNaN(Src2)
Src1
QNaN_Indefinite
Src1
IF Src2 is SNAN or -INF
±0
QNaN(Src2)
QNaN_Indefinite
Src1
Src1
IF Src2 is SNAN or +INF
Denorm/Norm
QNaN(Src2)
±INF (Src1 sign)
±0 (Src1 sign)
Compute Result
IF Src2 is SNAN
VSCALEFPD—Scale Packed Float64 Values With Float64 Values
Vol. 2C 5-537
INSTRUCTION SET REFERENCE, V-Z
Table 5-41. Additional VSCALEFPD/SD Special Cases
Special Case
|result| <
2-1074
|result| ≥ 2
1024
Returned value
Faults
±0 or ±Min-Denormal (Src1 sign)
Underflow
±INF (Src1 sign) or ±Max-normal (Src1 sign)
Overflow
Operation
SCALE(SRC1, SRC2)
{
TMP_SRC2 SRC2
TMP_SRC1 SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
/* SRC2 is a 64 bits floating-point value */
DEST[63:0] TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))
}
VSCALEFPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] SCALE(SRC1[i+63:i], SRC2[63:0]);
ELSE DEST[i+63:i] SCALE(SRC1[i+63:i], SRC2[i+63:i]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-538 Vol. 2C
VSCALEFPD—Scale Packed Float64 Values With Float64 Values
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFPD __m512d _mm512_scalef_round_pd(__m512d a, __m512d b, int);
VSCALEFPD __m512d _mm512_mask_scalef_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VSCALEFPD __m512d _mm512_maskz_scalef_round_pd(__mmask8 k, __m512d a, __m512d b, int);
VSCALEFPD __m256d _mm256_scalef_round_pd(__m256d a, __m256d b, int);
VSCALEFPD __m256d _mm256_mask_scalef_round_pd(__m256d s, __mmask8 k, __m256d a, __m256d b, int);
VSCALEFPD __m256d _mm256_maskz_scalef_round_pd(__mmask8 k, __m256d a, __m256d b, int);
VSCALEFPD __m128d _mm_scalef_round_pd(__m128d a, __m128d b, int);
VSCALEFPD __m128d _mm_mask_scalef_round_pd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VSCALEFPD __m128d _mm_maskz_scalef_round_pd(__mmask8 k, __m128d a, __m128d b, int);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.
Other Exceptions
See Exceptions Type E2.
VSCALEFPD—Scale Packed Float64 Values With Float64 Values
Vol. 2C 5-539
INSTRUCTION SET REFERENCE, V-Z
VSCALEFSD—Scale Scalar Float64 Values With Float64 Values
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W1 2D /r
VSCALEFSD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Scale the scalar double-precision floating-point values in
xmm2 using the value from xmm3/m64. Under writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a floating-point scale of the packed double-precision floating-point value in the first source operand by
multiplying it by 2 power of the double-precision floating-point value in second source operand.
The equation of this operation is given by:
xmm1 := xmm2*2floor(xmm3).
Floor(xmm3) means maximum integer value ≤ xmm3.
If the result cannot be represented in double precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register
or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-40 and Table 5-41.
Operation
SCALE(SRC1, SRC2)
{
; Check for denormal operands
TMP_SRC2 SRC2
TMP_SRC1 SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
/* SRC2 is a 64 bits floating-point value */
DEST[63:0] TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))
}
5-540 Vol. 2C
VSCALEFSD—Scale Scalar Float64 Values With Float64 Values
INSTRUCTION SET REFERENCE, V-Z
VSCALEFSD (EVEX encoded version)
IF (EVEX.b= 1) and SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] OR *no writemask*
THEN DEST[63:0] SCALE(SRC1[63:0], SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] 0
FI
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFSD __m128d _mm_scalef_round_sd(__m128d a, __m128d b, int);
VSCALEFSD __m128d _mm_mask_scalef_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VSCALEFSD __m128d _mm_maskz_scalef_round_sd(__mmask8 k, __m128d a, __m128d b, int);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.
Other Exceptions
See Exceptions Type E3.
VSCALEFSD—Scale Scalar Float64 Values With Float64 Values
Vol. 2C 5-541
INSTRUCTION SET REFERENCE, V-Z
VSCALEFPS—Scale Packed Float32 Values With Float32 Values
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.128.66.0F38.W0 2C /r
VSCALEFPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.66.0F38.W0 2C /r
VSCALEFPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.66.0F38.W0 2C /r
VSCALEFPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Scale the packed single-precision floating-point values in
xmm2 using values from xmm3/m128/m32bcst. Under
writemask k1.
Scale the packed single-precision values in ymm2 using
floating point values from ymm3/m256/m32bcst. Under
writemask k1.
Scale the packed single-precision floating-point values in
zmm2 using floating-point values from
zmm3/m512/m32bcst. Under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a floating-point scale of the packed single-precision floating-point values in the first source operand by
multiplying it by 2 power of the float32 values in second source operand.
The equation of this operation is given by:
zmm1 := zmm2*2floor(zmm3).
Floor(zmm3) means maximum integer value ≤ zmm3.
If the result cannot be represented in single precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The destination
operand is a ZMM register conditionally updated with writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.
Handling of special-case input values are listed in Table 5-40 and Table 5-42.
Table 5-42. Additional VSCALEFPS/SS Special Cases
Special Case
Returned value
Faults
|result| <
2-149
±0 or ±Min-Denormal (Src1 sign)
Underflow
|result| ≥
2128
±INF (Src1 sign) or ±Max-normal (Src1 sign)
Overflow
5-542 Vol. 2C
VSCALEFPS—Scale Packed Float32 Values With Float32 Values
INSTRUCTION SET REFERENCE, V-Z
Operation
SCALE(SRC1, SRC2)
{
; Check for denormal operands
TMP_SRC2 SRC2
TMP_SRC1 SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
/* SRC2 is a 32 bits floating-point value */
DEST[31:0] TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))
}
VSCALEFPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SCALE(SRC1[i+31:i], SRC2[31:0]);
ELSE DEST[i+31:i] SCALE(SRC1[i+31:i], SRC2[i+31:i]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0;
Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFPS __m512 _mm512_scalef_round_ps(__m512 a, __m512 b, int);
VSCALEFPS __m512 _mm512_mask_scalef_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VSCALEFPS __m512 _mm512_maskz_scalef_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VSCALEFPS __m256 _mm256_scalef_round_ps(__m256 a, __m256 b, int);
VSCALEFPS __m256 _mm256_mask_scalef_round_ps(__m256 s, __mmask8 k, __m256 a, __m256 b, int);
VSCALEFPS __m256 _mm256_maskz_scalef_round_ps(__mmask8 k, __m256 a, __m256 b, int);
VSCALEFPS __m128 _mm_scalef_round_ps(__m128 a, __m128 b, int);
VSCALEFPS __m128 _mm_mask_scalef_round_ps(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSCALEFPS __m128 _mm_maskz_scalef_round_ps(__mmask8 k, __m128 a, __m128 b, int);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.
Other Exceptions
See Exceptions Type E2.
VSCALEFPS—Scale Packed Float32 Values With Float32 Values
Vol. 2C 5-543
INSTRUCTION SET REFERENCE, V-Z
VSCALEFSS—Scale Scalar Float32 Value With Float32 Value
Opcode/
Instruction
Op /
En
EVEX.NDS.LIG.66.0F38.W0 2D /r
VSCALEFSS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512F
Description
Scale the scalar single-precision floating-point value in
xmm2 using floating-point value from xmm3/m32. Under
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a floating-point scale of the scalar single-precision floating-point value in the first source operand by
multiplying it by 2 power of the float32 value in second source operand.
The equation of this operation is given by:
xmm1 := xmm2*2floor(xmm3).
Floor(xmm3) means maximum integer value ≤ xmm3.
If the result cannot be represented in single precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register
or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-40 and Table 5-42.
5-544 Vol. 2C
VSCALEFSS—Scale Scalar Float32 Value With Float32 Value
INSTRUCTION SET REFERENCE, V-Z
Operation
SCALE(SRC1, SRC2)
{
; Check for denormal operands
TMP_SRC2 SRC2
TMP_SRC1 SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
/* SRC2 is a 32 bits floating-point value */
DEST[31:0] TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))
}
VSCALEFSS (EVEX encoded version)
IF (EVEX.b= 1) and SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] OR *no writemask*
THEN DEST[31:0] SCALE(SRC1[31:0], SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] 0
FI
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFSS __m128 _mm_scalef_round_ss(__m128 a, __m128 b, int);
VSCALEFSS __m128 _mm_mask_scalef_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSCALEFSS __m128 _mm_maskz_scalef_round_ss(__mmask8 k, __m128 a, __m128 b, int);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.
Other Exceptions
See Exceptions Type E3.
VSCALEFSS—Scale Scalar Float32 Value With Float32 Value
Vol. 2C 5-545
INSTRUCTION SET REFERENCE, V-Z
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed
Double with Signed Dword and Qword Indices
Opcode/
Instruction
Op/E
n
EVEX.128.66.0F38.W0 A2 /vsib
VSCATTERDPS vm32x {k1}, xmm1
EVEX.256.66.0F38.W0 A2 /vsib
VSCATTERDPS vm32y {k1}, ymm1
EVEX.512.66.0F38.W0 A2 /vsib
VSCATTERDPS vm32z {k1}, zmm1
EVEX.128.66.0F38.W1 A2 /vsib
VSCATTERDPD vm32x {k1}, xmm1
EVEX.256.66.0F38.W1 A2 /vsib
VSCATTERDPD vm32x {k1}, ymm1
EVEX.512.66.0F38.W1 A2 /vsib
VSCATTERDPD vm32y {k1}, zmm1
EVEX.128.66.0F38.W0 A3 /vsib
VSCATTERQPS vm64x {k1}, xmm1
EVEX.256.66.0F38.W0 A3 /vsib
VSCATTERQPS vm64y {k1}, xmm1
EVEX.512.66.0F38.W0 A3 /vsib
VSCATTERQPS vm64z {k1}, ymm1
EVEX.128.66.0F38.W1 A3 /vsib
VSCATTERQPD vm64x {k1}, xmm1
EVEX.256.66.0F38.W1 A3 /vsib
VSCATTERQPD vm64y {k1}, ymm1
EVEX.512.66.0F38.W1 A3 /vsib
VSCATTERQPD vm64z {k1}, zmm1
T1S
64/32
bit Mode
Support
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
T1S
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
AVX512VL
AVX512F
AVX512VL
AVX512F
AVX512F
Description
Using signed dword indices, scatter single-precision
floating-point values to memory using writemask k1.
Using signed dword indices, scatter single-precision
floating-point values to memory using writemask k1.
Using signed dword indices, scatter single-precision
floating-point values to memory using writemask k1.
Using signed dword indices, scatter double-precision
floating-point values to memory using writemask k1.
Using signed dword indices, scatter double-precision
floating-point values to memory using writemask k1.
Using signed dword indices, scatter double-precision
floating-point values to memory using writemask k1.
Using signed qword indices, scatter single-precision
floating-point values to memory using writemask k1.
Using signed qword indices, scatter single-precision
floating-point values to memory using writemask k1.
Using signed qword indices, scatter single-precision
floating-point values to memory using writemask k1.
Using signed qword indices, scatter double-precision
floating-point values to memory using writemask k1.
Using signed qword indices, scatter double-precision
floating-point values to memory using writemask k1.
Using signed qword indices, scatter double-precision
floating-point values to memory using writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
ModRM:reg (r)
NA
NA
Description
Stores up to 16 elements (or 8 elements) in doubleword/quadword vector zmm1 to the memory locations pointed
by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The elements are specified via the VSIB
(i.e., the index register is a vector register, holding packed indices). Elements will only be stored if their corresponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated. If any traps or interrupts are pending from already scattered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
Note that:
•
Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to
MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not
overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory
ordering model. Note that this does not account for non-overlapping indices that map into the same physical
address locations.
5-546 Vol. 2C
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword
INSTRUCTION SET REFERENCE, V-Z
•
•
If two or more destination indices completely overlap, the “earlier” write(s) may be skipped.
•
Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
•
•
•
This instruction does not perform AC checks, and so will never deliver an AC fault.
Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
Not valid with 16-bit effective addresses. Will deliver a #UD fault.
If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before
the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this
instruction, the new instruction will be executed, and the scatter will not complete.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits
are ignored.
The instruction will #UD fault if the k0 mask register is specified
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword
Vol. 2C 5-547
INSTRUCTION SET REFERENCE, V-Z
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
5-548 Vol. 2C
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword
INSTRUCTION SET REFERENCE, V-Z
VSCATTERDPS (EVEX encoded versions)
(KL, VL)= (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP]
SRC[i+31:i]
k1[j] 0
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VSCATTERDPD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP]
SRC[i+63:i]
k1[j] 0
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VSCATTERQPS (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 32
k j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]
SRC[i+31:i]
k1[j] 0
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VSCATTERQPD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]
SRC[i+63:i]
k1[j] 0
FI;
ENDFOR
k1[MAX_KL-1:KL] 0
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword
Vol. 2C 5-549
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VSCATTERDPD void _mm512_i32scatter_pd(void * base, __m256i vdx, __m512d a, int scale);
VSCATTERDPD void _mm512_mask_i32scatter_pd(void * base, __mmask8 k, __m256i vdx, __m512d a, int scale);
VSCATTERDPS void _mm512_i32scatter_ps(void * base, __m512i vdx, __m512 a, int scale);
VSCATTERDPS void _mm512_mask_i32scatter_ps(void * base, __mmask16 k, __m512i vdx, __m512 a, int scale);
VSCATTERQPD void _mm512_i64scatter_pd(void * base, __m512i vdx, __m512d a, int scale);
VSCATTERQPD void _mm512_mask_i64scatter_pd(void * base, __mmask8 k, __m512i vdx, __m512d a, int scale);
VSCATTERQPS void _mm512_i64scatter_ps(void * base, __m512i vdx, __m256 a, int scale);
VSCATTERQPS void _mm512_mask_i64scatter_ps(void * base, __mmask8 k, __m512i vdx, __m256 a, int scale);
VSCATTERDPD void _mm256_i32scatter_pd(void * base, __m128i vdx, __m256d a, int scale);
VSCATTERDPD void _mm256_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m256d a, int scale);
VSCATTERDPS void _mm256_i32scatter_ps(void * base, __m256i vdx, __m256 a, int scale);
VSCATTERDPS void _mm256_mask_i32scatter_ps(void * base, __mmask8 k, __m256i vdx, __m256 a, int scale);
VSCATTERQPD void _mm256_i64scatter_pd(void * base, __m256i vdx, __m256d a, int scale);
VSCATTERQPD void _mm256_mask_i64scatter_pd(void * base, __mmask8 k, __m256i vdx, __m256d a, int scale);
VSCATTERQPS void _mm256_i64scatter_ps(void * base, __m256i vdx, __m128 a, int scale);
VSCATTERQPS void _mm256_mask_i64scatter_ps(void * base, __mmask8 k, __m256i vdx, __m128 a, int scale);
VSCATTERDPD void _mm_i32scatter_pd(void * base, __m128i vdx, __m128d a, int scale);
VSCATTERDPD void _mm_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);
VSCATTERDPS void _mm_i32scatter_ps(void * base, __m128i vdx, __m128 a, int scale);
VSCATTERDPS void _mm_mask_i32scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);
VSCATTERQPD void _mm_i64scatter_pd(void * base, __m128i vdx, __m128d a, int scale);
VSCATTERQPD void _mm_mask_i64scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);
VSCATTERQPS void _mm_i64scatter_ps(void * base, __m128i vdx, __m128 a, int scale);
VSCATTERQPS void _mm_mask_i64scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);
SIMD Floating-Point Exceptions
Invalid, Overflow, Underflow, Precision, Denormal
Other Exceptions
See Exceptions Type E12.
5-550 Vol. 2C
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword
INSTRUCTION SET REFERENCE, V-Z
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent
to Write
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512PF
EVEX.512.66.0F38.W0 C7 /5 /vsib
VSCATTERPF0QPS vm64z {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C6 /5 /vsib
VSCATTERPF0DPD vm32y {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C7 /5 /vsib
VSCATTERPF0QPD vm64z {k1}
T1S
V/V
AVX512PF
Opcode/
Instruction
Op/
En
EVEX.512.66.0F38.W0 C6 /5 /vsib
VSCATTERPF0DPS vm32z {k1}
Description
Using signed dword indices, prefetch sparse byte
memory locations containing single-precision data using
writemask k1 and T0 hint with intent to write.
Using signed qword indices, prefetch sparse byte
memory locations containing single-precision data using
writemask k1 and T0 hint with intent to write.
Using signed dword indices, prefetch sparse byte
memory locations containing double-precision data
using writemask k1 and T0 hint with intent to write.
Using signed qword indices, prefetch sparse byte
memory locations containing double-precision data
using writemask k1 and T0 hint with intent to write.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
NA
Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
cache lines will be brought into exclusive state (RFO) specified by a locality hint (T0):
• T0 (temporal data)—prefetch data into the first level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruction will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request
for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with
Vol. 2C 5-551
INSTRUCTION SET REFERENCE, V-Z
VSCATTERPF0DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
VSCATTERPF0DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
VSCATTERPF0QPS (EVEX encoded version)
(KL, VL) = (8, 256)
FOR j 0 TO KL-1
i j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
VSCATTERPF0QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
Intel C/C++ Compiler Intrinsic Equivalent
VSCATTERPF0DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);
VSCATTERPF0DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);
VSCATTERPF0DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);
VSCATTERPF0DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);
VSCATTERPF0QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF0QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);
VSCATTERPF0QPS void _mm512_prefetch_i64scatter_ps(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF0QPS void _mm512_mask_prefetch_i64scatter_ps(void * base, __mmask8 m, __m512i vdx, int scale, int hint);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12NP.
5-552 Vol. 2C
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with
INSTRUCTION SET REFERENCE, V-Z
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent
to Write
T1S
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512PF
EVEX.512.66.0F38.W0 C7 /6 /vsib
VSCATTERPF1QPS vm64z {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C6 /6 /vsib
VSCATTERPF1DPD vm32y {k1}
T1S
V/V
AVX512PF
EVEX.512.66.0F38.W1 C7 /6 /vsib
VSCATTERPF1QPD vm64z {k1}
T1S
V/V
AVX512PF
Opcode/
Instruction
Op/
En
EVEX.512.66.0F38.W0 C6 /6 /vsib
VSCATTERPF1DPS vm32z {k1}
Description
Using signed dword indices, prefetch sparse byte memory
locations containing single-precision data using writemask
k1 and T1 hint with intent to write.
Using signed qword indices, prefetch sparse byte memory
locations containing single-precision data using writemask
k1 and T1 hint with intent to write.
Using signed dword indices, prefetch sparse byte memory
locations containing double-precision data using
writemask k1 and T1 hint with intent to write.
Using signed qword indices, prefetch sparse byte memory
locations containing double-precision data using
writemask k1 and T1 hint with intent to write.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
T1S
BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
NA
NA
NA
Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
cache lines will be brought into exclusive state (RFO) specified by a locality hint (T1):
• T1 (temporal data)—prefetch data into the second level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruction will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request
for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with
Vol. 2C 5-553
INSTRUCTION SET REFERENCE, V-Z
VSCATTERPF1DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR
VSCATTERPF1DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 32
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR
VSCATTERPF1QPS (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR
VSCATTERPF1QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j 0 TO KL-1
i j * 64
k j * 64
IF k1[j]
Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR
Intel C/C++ Compiler Intrinsic Equivalent
VSCATTERPF1DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);
VSCATTERPF1DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);
VSCATTERPF1DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);
VSCATTERPF1DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);
VSCATTERPF1QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF1QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);
VSCATTERPF1QPS void _mm512_prefetch_i64scatter_ps(void *base, __m512i vdx, int scale, int hint);
VSCATTERPF1QPS void _mm512_mask_prefetch_i64scatter_ps(void *base, __mmask8 m, __m512i vdx, int scale, int hint);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E12NP.
5-554 Vol. 2C
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with
INSTRUCTION SET REFERENCE, V-Z
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit
Granularity
Opcode/
Instruction
Op /
En
FV
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
AVX512VL
AVX512F
EVEX.NDS.256.66.0F3A.W0 23 /r ib
VSHUFF32X4 ymm1{k1}{z}, ymm2,
ymm3/m256/m32bcst, imm8
EVEX.NDS.512.66.0F3A.W0 23 /r ib
VSHUFF32x4 zmm1{k1}{z}, zmm2,
zmm3/m512/m32bcst, imm8
FV
V/V
AVX512F
EVEX.NDS.256.66.0F3A.W1 23 /r ib
VSHUFF64X2 ymm1{k1}{z}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F3A.W1 23 /r ib
VSHUFF64x2 zmm1{k1}{z}, zmm2,
zmm3/m512/m64bcst, imm8
FV
V/V
AVX512F
EVEX.NDS.256.66.0F3A.W0 43 /r ib
VSHUFI32X4 ymm1{k1}{z}, ymm2,
ymm3/m256/m32bcst, imm8
EVEX.NDS.512.66.0F3A.W0 43 /r ib
VSHUFI32x4 zmm1{k1}{z}, zmm2,
zmm3/m512/m32bcst, imm8
EVEX.NDS.256.66.0F3A.W1 43 /r ib
VSHUFI64X2 ymm1{k1}{z}, ymm2,
ymm3/m256/m64bcst, imm8
EVEX.NDS.512.66.0F3A.W1 43 /r ib
VSHUFI64x2 zmm1{k1}{z}, zmm2,
zmm3/m512/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Shuffle 128-bit packed single-precision floating-point
values selected by imm8 from ymm2 and
ymm3/m256/m32bcst and place results in ymm1
subject to writemask k1.
Shuffle 128-bit packed single-precision floating-point
values selected by imm8 from zmm2 and
zmm3/m512/m32bcst and place results in zmm1
subject to writemask k1.
Shuffle 128-bit packed double-precision floating-point
values selected by imm8 from ymm2 and
ymm3/m256/m64bcst and place results in ymm1
subject to writemask k1.
Shuffle 128-bit packed double-precision floating-point
values selected by imm8 from zmm2 and
zmm3/m512/m64bcst and place results in zmm1
subject to writemask k1.
Shuffle 128-bit packed double-word values selected by
imm8 from ymm2 and ymm3/m256/m32bcst and place
results in ymm1 subject to writemask k1.
Shuffle 128-bit packed double-word values selected by
imm8 from zmm2 and zmm3/m512/m32bcst and place
results in zmm1 subject to writemask k1.
Shuffle 128-bit packed quad-word values selected by
imm8 from ymm2 and ymm3/m256/m64bcst and place
results in ymm1 subject to writemask k1.
Shuffle 128-bit packed quad-word values selected by
imm8 from zmm2 and zmm3/m512/m64bcst and place
results in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
256-bit Version: Moves one of the two 128-bit packed single-precision floating-point values from the first source
operand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two
packed 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the
destination operand. The selector operand (third operand) determines which values are moved to the destination
operand.
512-bit Version: Moves two of the four 128-bit packed single-precision floating-point values from the first source
operand (second operand) into the low 256-bit of each double qword of the destination operand (first operand);
moves two of the four packed 128-bit floating-point values from the second source operand (third operand) into
the high 256-bit of the destination operand. The selector operand (third operand) determines which values are
moved to the destination operand.
The first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory
location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a vector
register.
The writemask updates the destination operand with the granularity of 32/64-bit data elements.
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity
Vol. 2C 5-555
INSTRUCTION SET REFERENCE, V-Z
Operation
Select2(SRC, control) {
CASE (control[0]) OF
0: TMP SRC[127:0];
1: TMP SRC[255:128];
ESAC;
RETURN TMP
}
Select4(SRC, control) {
CASE (control[1:0]) OF
0: TMP SRC[127:0];
1: TMP SRC[255:128];
2: TMP SRC[383:256];
3: TMP SRC[511:384];
ESAC;
RETURN TMP
}
VSHUFF32x4 (EVEX versions)
(KL, VL) = (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] SRC2[31:0]
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
THEN DEST[i+31:i] 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-556 Vol. 2C
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity
INSTRUCTION SET REFERENCE, V-Z
VSHUFF64x2 (EVEX 512-bit version)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] SRC2[63:0]
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
THEN DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSHUFI32x4 (EVEX 512-bit version)
(KL, VL) = (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] SRC2[31:0]
ELSE TMP_SRC2[i+31:i] SRC2[i+31:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j 0 TO KL-1
i j * 32
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity
Vol. 2C 5-557
INSTRUCTION SET REFERENCE, V-Z
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
THEN DEST[i+31:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VSHUFI64x2 (EVEX 512-bit version)
(KL, VL) = (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] SRC2[63:0]
ELSE TMP_SRC2[i+63:i] SRC2[i+63:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
THEN DEST[i+63:i] 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
5-558 Vol. 2C
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VSHUFI32x4 __m512i _mm512_shuffle_i32x4(__m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_mask_shuffle_i32x4(__m512i s, __mmask16 k, __m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_maskz_shuffle_i32x4( __mmask16 k, __m512i a, __m512i b, int imm);
VSHUFI32x4 __m256i _mm256_shuffle_i32x4(__m256i a, __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_mask_shuffle_i32x4(__m256i s, __mmask8 k, __m256i a, __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_maskz_shuffle_i32x4( __mmask8 k, __m256i a, __m256i b, int imm);
VSHUFF32x4 __m512 _mm512_shuffle_f32x4(__m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_mask_shuffle_f32x4(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_maskz_shuffle_f32x4( __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFI64x2 __m512i _mm512_shuffle_i64x2(__m512i a, __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_mask_shuffle_i64x2(__m512i s, __mmask8 k, __m512i b, __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_maskz_shuffle_i64x2( __mmask8 k, __m512i a, __m512i b, int imm);
VSHUFF64x2 __m512d _mm512_shuffle_f64x2(__m512d a, __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_mask_shuffle_f64x2(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_maskz_shuffle_f64x2( __mmask8 k, __m512d a, __m512d b, int imm);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E4NF.
#UD
If EVEX.L’L = 0 for VSHUFF32x4/VSHUFF64x2.
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity
Vol. 2C 5-559
INSTRUCTION SET REFERENCE, V-Z
VTESTPD/VTESTPS—Packed Bit Test
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
VEX.128.66.0F38.W0 0E /r
VTESTPS xmm1, xmm2/m128
RM
V/V
AVX
Set ZF and CF depending on sign bit AND and
ANDN of packed single-precision floating-point
sources.
VEX.256.66.0F38.W0 0E /r
VTESTPS ymm1, ymm2/m256
RM
V/V
AVX
Set ZF and CF depending on sign bit AND and
ANDN of packed single-precision floating-point
sources.
VEX.128.66.0F38.W0 0F /r
VTESTPD xmm1, xmm2/m128
RM
V/V
AVX
Set ZF and CF depending on sign bit AND and
ANDN of packed double-precision floating-point
sources.
VEX.256.66.0F38.W0 0F /r
VTESTPD ymm1, ymm2/m256
RM
V/V
AVX
Set ZF and CF depending on sign bit AND and
ANDN of packed double-precision floating-point
sources.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
Description
VTESTPS performs a bitwise comparison of all the sign bits of the packed single-precision elements in the first
source operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with
the dest sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND of the source sign bits with the
inverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with
VEX.W=1 will cause #UD.
VTESTPD performs a bitwise comparison of all the sign bits of the double-precision elements in the first source
operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with the dest
sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND the source sign bits with the inverted dest
sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will
cause #UD.
The first source register is specified by the ModR/M reg field.
128-bit version: The first source register is an XMM register. The second source register can be an XMM register or
a 128-bit memory location. The destination register is not modified.
VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM
register or a 256-bit memory location. The destination register is not modified.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
5-560 Vol. 2C
VTESTPD/VTESTPS—Packed Bit Test
INSTRUCTION SET REFERENCE, V-Z
Operation
VTESTPS (128-bit version)
TEMP[127:0] SRC[127:0] AND DEST[127:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
THEN ZF 1;
ELSE ZF 0;
TEMP[127:0] SRC[127:0] AND NOT DEST[127:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
THEN CF 1;
ELSE CF 0;
DEST (unmodified)
AF OF PF SF 0;
VTESTPS (VEX.256 encoded version)
TEMP[255:0] SRC[255:0] AND DEST[255:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
THEN ZF 1;
ELSE ZF 0;
TEMP[255:0] SRC[255:0] AND NOT DEST[255:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
THEN CF 1;
ELSE CF 0;
DEST (unmodified)
AF OF PF SF 0;
VTESTPD (128-bit version)
TEMP[127:0] SRC[127:0] AND DEST[127:0]
IF ( TEMP[63] = TEMP[127] = 0)
THEN ZF 1;
ELSE ZF 0;
TEMP[127:0] SRC[127:0] AND NOT DEST[127:0]
IF ( TEMP[63] = TEMP[127] = 0)
THEN CF 1;
ELSE CF 0;
DEST (unmodified)
AF OF PF SF 0;
VTESTPD (VEX.256 encoded version)
TEMP[255:0] SRC[255:0] AND DEST[255:0]
IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
THEN ZF 1;
ELSE ZF 0;
TEMP[255:0] SRC[255:0] AND NOT DEST[255:0]
IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
THEN CF 1;
ELSE CF 0;
DEST (unmodified)
AF OF PF SF 0;
VTESTPD/VTESTPS—Packed Bit Test
Vol. 2C 5-561
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VTESTPS
int _mm256_testz_ps (__m256 s1, __m256 s2);
int _mm256_testc_ps (__m256 s1, __m256 s2);
int _mm256_testnzc_ps (__m256 s1, __m128 s2);
int _mm_testz_ps (__m128 s1, __m128 s2);
int _mm_testc_ps (__m128 s1, __m128 s2);
int _mm_testnzc_ps (__m128 s1, __m128 s2);
VTESTPD
int _mm256_testz_pd (__m256d s1, __m256d s2);
int _mm256_testc_pd (__m256d s1, __m256d s2);
int _mm256_testnzc_pd (__m256d s1, __m256d s2);
int _mm_testz_pd (__m128d s1, __m128d s2);
int _mm_testc_pd (__m128d s1, __m128d s2);
int _mm_testnzc_pd (__m128d s1, __m128d s2);
Flags Affected
The 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.vvvv ≠ 1111B.
If VEX.W = 1 for VTESTPS or VTESTPD.
5-562 Vol. 2C
VTESTPD/VTESTPS—Packed Bit Test
INSTRUCTION SET REFERENCE, V-Z
VZEROALL—Zero All YMM Registers
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
VEX.256.0F.WIG 77
NP
V/V
AVX
Zero all YMM registers.
VZEROALL
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
The instruction zeros contents of all XMM or YMM registers.
Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32bit mode only the lower 8 registers are modified.
Operation
VZEROALL (VEX.256 encoded version)
IF (64-bit mode)
YMM0[VLMAX-1:0] 0
YMM1[VLMAX-1:0] 0
YMM2[VLMAX-1:0] 0
YMM3[VLMAX-1:0] 0
YMM4[VLMAX-1:0] 0
YMM5[VLMAX-1:0] 0
YMM6[VLMAX-1:0] 0
YMM7[VLMAX-1:0] 0
YMM8[VLMAX-1:0] 0
YMM9[VLMAX-1:0] 0
YMM10[VLMAX-1:0] 0
YMM11[VLMAX-1:0] 0
YMM12[VLMAX-1:0] 0
YMM13[VLMAX-1:0] 0
YMM14[VLMAX-1:0] 0
YMM15[VLMAX-1:0] 0
ELSE
YMM0[VLMAX-1:0] 0
YMM1[VLMAX-1:0] 0
YMM2[VLMAX-1:0] 0
YMM3[VLMAX-1:0] 0
YMM4[VLMAX-1:0] 0
YMM5[VLMAX-1:0] 0
YMM6[VLMAX-1:0] 0
YMM7[VLMAX-1:0] 0
YMM8-15: Unmodified
FI
VZEROALL—Zero All YMM Registers
Vol. 2C 5-563
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VZEROALL:
_mm256_zeroall()
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 8.
5-564 Vol. 2C
VZEROALL—Zero All YMM Registers
INSTRUCTION SET REFERENCE, V-Z
VZEROUPPER—Zero Upper Bits of YMM Registers
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
VEX.128.0F.WIG 77
NP
V/V
AVX
Zero upper 128 bits of all YMM registers.
VZEROUPPER
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
The instruction zeros the bits in position 128 and higher of all YMM registers. The lower 128-bits of the registers
(the corresponding XMM registers) are unmodified.
This instruction is recommended when transitioning between AVX and legacy SSE code - it will eliminate performance penalties caused by false dependencies.
Note: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. In Compatibility and legacy 32-bit
mode only the lower 8 registers are modified.
Operation
VZEROUPPER
IF (64-bit mode)
YMM0[VLMAX-1:128] 0
YMM1[VLMAX-1:128] 0
YMM2[VLMAX-1:128] 0
YMM3[VLMAX-1:128] 0
YMM4[VLMAX-1:128] 0
YMM5[VLMAX-1:128] 0
YMM6[VLMAX-1:128] 0
YMM7[VLMAX-1:128] 0
YMM8[VLMAX-1:128] 0
YMM9[VLMAX-1:128] 0
YMM10[VLMAX-1:128] 0
YMM11[VLMAX-1:128] 0
YMM12[VLMAX-1:128] 0
YMM13[VLMAX-1:128] 0
YMM14[VLMAX-1:128] 0
YMM15[VLMAX-1:128] 0
ELSE
YMM0[VLMAX-1:128] 0
YMM1[VLMAX-1:128] 0
YMM2[VLMAX-1:128] 0
YMM3[VLMAX-1:128] 0
YMM4[VLMAX-1:128] 0
YMM5[VLMAX-1:128] 0
YMM6[VLMAX-1:128] 0
YMM7[VLMAX-1:128] 0
YMM8-15: unmodified
FI
VZEROUPPER—Zero Upper Bits of YMM Registers
Vol. 2C 5-565
INSTRUCTION SET REFERENCE, V-Z
Intel C/C++ Compiler Intrinsic Equivalent
VZEROUPPER:
_mm256_zeroupper()
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type 8.
5-566 Vol. 2C
VZEROUPPER—Zero Upper Bits of YMM Registers
INSTRUCTION SET REFERENCE, V-Z
WAIT/FWAIT—Wait
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
9B
WAIT
NP
Valid
Valid
Check pending unmasked floating-point
exceptions.
9B
FWAIT
NP
Valid
Valid
Check pending unmasked floating-point
exceptions.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding.
(FWAIT is an alternate mnemonic for WAIT.)
This instruction is useful for synchronizing exceptions in critical sections of code. Coding a WAIT instruction after a
floating-point instruction ensures that any unmasked floating-point exceptions the instruction may raise are
handled before the processor can modify the instruction’s results. See the section titled “Floating-Point Exception
Synchronization” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,
for more information on using the WAIT/FWAIT instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
CheckForPendingUnmaskedFloatingPointExceptions;
FPU Flags Affected
The C0, C1, C2, and C3 flags are undefined.
Floating-Point Exceptions
None.
Protected Mode Exceptions
#NM
If CR0.MP[bit 1] = 1 and CR0.TS[bit 3] = 1.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
WAIT/FWAIT—Wait
Vol. 2C 5-567
INSTRUCTION SET REFERENCE, V-Z
WBINVD—Write Back and Invalidate Cache
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 09
WBINVD
NP
Valid
Valid
Write back and flush Internal caches; initiate
writing-back and flushing of external caches.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Writes back all modified cache lines in the processor’s internal cache to main memory and invalidates (flushes) the
internal caches. The instruction then issues a special-function bus cycle that directs external caches to also write
back modified data and another bus cycle to indicate that the external caches should be invalidated.
After executing this instruction, the processor does not wait for the external caches to complete their write-back
and flushing operations before proceeding with instruction execution. It is the responsibility of hardware to respond
to the cache write-back and flush signals. The amount of time or cycles for WBINVD to complete will vary due to
size and other factors of different cache hierarchies. As a consequence, the use of the WBINVD instruction can have
an impact on logical processor interrupt/event response time. Additional information of WBINVD behavior in a
cache hierarchy with hierarchical sharing topology can be found in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
The WBINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a
program or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see
“Serializing Instructions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A).
In situations where cache coherency with main memory is not a concern, software can use the INVD instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IA-32 Architecture Compatibility
The WBINVD instruction is implementation dependent, and its function may be implemented differently on future
Intel 64 and IA-32 processors. The instruction is not supported on IA-32 processors earlier than the Intel486
processor.
Operation
WriteBack(InternalCaches);
Flush(InternalCaches);
SignalWriteBack(ExternalCaches);
SignalFlush(ExternalCaches);
Continue; (* Continue execution *)
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If the LOCK prefix is used.
5-568 Vol. 2C
WBINVD—Write Back and Invalidate Cache
INSTRUCTION SET REFERENCE, V-Z
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
WBINVD cannot be executed at the virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
WBINVD—Write Back and Invalidate Cache
Vol. 2C 5-569
INSTRUCTION SET REFERENCE, V-Z
WRFSBASE/WRGSBASE—Write FS/GS Segment Base
Opcode/
Instruction
Op/
En
64/32bit
Mode
CPUID Fea- Description
ture Flag
F3 0F AE /2
WRFSBASE r32
M
V/I
FSGSBASE
Load the FS base address with the 32-bit value in
the source register.
F3 REX.W 0F AE /2
WRFSBASE r64
M
V/I
FSGSBASE
Load the FS base address with the 64-bit value in
the source register.
F3 0F AE /3
WRGSBASE r32
M
V/I
FSGSBASE
Load the GS base address with the 32-bit value in
the source register.
F3 REX.W 0F AE /3
WRGSBASE r64
M
V/I
FSGSBASE
Load the GS base address with the 64-bit value in
the source register.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Loads the FS or GS segment base address with the general-purpose register indicated by the modR/M:r/m field.
The source operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the
operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source
register are ignored and upper 32 bits of the base address (for FS or GS) are cleared.
This instruction is supported only in 64-bit mode.
Operation
FS/GS segment base address ← SRC;
Flags Affected
None
C/C++ Compiler Intrinsic Equivalent
WRFSBASE:
void _writefsbase_u32( unsigned int );
WRFSBASE:
_writefsbase_u64( unsigned __int64 );
WRGSBASE:
void _writegsbase_u32( unsigned int );
WRGSBASE:
_writegsbase_u64( unsigned __int64 );
Protected Mode Exceptions
#UD
The WRFSBASE and WRGSBASE instructions are not recognized in protected mode.
Real-Address Mode Exceptions
#UD
The WRFSBASE and WRGSBASE instructions are not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The WRFSBASE and WRGSBASE instructions are not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
5-570 Vol. 2C
The WRFSBASE and WRGSBASE instructions are not recognized in compatibility mode.
WRFSBASE/WRGSBASE—Write FS/GS Segment Base
INSTRUCTION SET REFERENCE, V-Z
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CR4.FSGSBASE[bit 16] = 0.
If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0
#GP(0)
If the source register contains a non-canonical address.
WRFSBASE/WRGSBASE—Write FS/GS Segment Base
Vol. 2C 5-571
INSTRUCTION SET REFERENCE, V-Z
WRMSR—Write to Model Specific Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 30
WRMSR
NP
Valid
Valid
Write the value in EDX:EAX to MSR specified
by ECX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register.
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of
the EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are
copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32
bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously
read.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection
exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a
general protection exception. The processor will also generate a general protection exception if software attempts
to write to bits in a reserved MSR.
When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries (see
“Translation Lookaside Buffers (TLBs)” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A).
MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors.
Chapter 35, “Model-Specific Registers (MSRs)”, in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C, lists all MSRs that can be written with this instruction and their addresses. Note that each
processor family has its own set of MSRs.
The WRMSR instruction is a serializing instruction (see “Serializing Instructions” in Chapter 8 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A). Note that WRMSR to the IA32_TSC_DEADLINE
MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.
The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before
using this instruction.
IA-32 Architecture Compatibility
The MSRs and the ability to read them with the WRMSR instruction were introduced into the IA-32 architecture with
the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor
results in an invalid opcode exception #UD.
Operation
MSR[ECX] ← EDX:EAX;
Flags Affected
None.
5-572 Vol. 2C
WRMSR—Write to Model Specific Register
INSTRUCTION SET REFERENCE, V-Z
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the value in ECX specifies a reserved or unimplemented MSR address.
If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.
If the source register contains a non-canonical address and ECX specifies one of the following
MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE,
IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If the value in ECX specifies a reserved or unimplemented MSR address.
If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.
If the source register contains a non-canonical address and ECX specifies one of the following
MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE,
IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
The WRMSR instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
WRMSR—Write to Model Specific Register
Vol. 2C 5-573
INSTRUCTION SET REFERENCE, V-Z
WRPKRU—Write Data to User Page Key Register
Opcode*
Instruction
Op/
En
64/32bit
Mode
Support
CPUID
Feature
Flag
Description
0F 01 EF
WRPKRU
NP
V/V
OSPKE
Writes EAX into PKRU.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Writes the value of EAX into PKRU. ECX and EDX must be 0 when WRPKRU is executed; otherwise, a generalprotection exception (#GP) occurs.
WRPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can
discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].
On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX, RDX and RAX are ignored.
Operation
IF (ECX = 0 AND EDX = 0)
THEN PKRU ← EAX;
ELSE #GP(0);
FI;
Flags Affected
None.
C/C++ Compiler Intrinsic Equivalent
WRPKRU:
void _wrpkru(uint32_t);
Protected Mode Exceptions
#GP(0)
If ECX
If EDX
#UD
≠ 0.
≠ 0.
If the LOCK prefix is used.
If CR4.PKE = 0.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
5-574 Vol. 2C
WRPKRU—Write Data to User Page Key Register
INSTRUCTION SET REFERENCE, V-Z
XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints
Opcode/Instruction
F2
XACQUIRE
F3
XRELEASE
64/32bit
Mode
Support
V/V
CPUID
Feature
Flag
HLE1
V/V
HLE
Description
A hint used with an “XACQUIRE-enabled“ instruction to start lock
elision on the instruction memory operand address.
A hint used with an “XRELEASE-enabled“ instruction to end lock
elision on the instruction memory operand address.
NOTES:
1. Software is not required to check the HLE feature flag to use XACQUIRE or XRELEASE, as they are treated as regular prefix if HLE
feature flag reports 0.
Description
The XACQUIRE prefix is a hint to start lock elision on the memory address specified by the instruction and the
XRELEASE prefix is a hint to end lock elision on the memory address specified by the instruction.
The XACQUIRE prefix hint can only be used with the following instructions (these instructions are also referred to
as XACQUIRE-enabled when used with the XACQUIRE prefix):
•
Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction where the destination
operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT,
OR, SBB, SUB, XOR, XADD, and XCHG.
•
The XCHG instruction either with or without the presence of the LOCK prefix.
The XRELEASE prefix hint can only be used with the following instructions (also referred to as XRELEASE-enabled
when used with the XRELEASE prefix):
•
Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction where the destination
operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT,
OR, SBB, SUB, XOR, XADD, and XCHG.
•
•
The XCHG instruction either with or without the presence of the LOCK prefix.
The “MOV mem, reg” (Opcode 88H/89H) and “MOV mem, imm” (Opcode C6H/C7H) instructions. In these
cases, the XRELEASE is recognized without the presence of the LOCK prefix.
The lock variables must satisfy the guidelines described in Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, Section 16.3.3, for elision to be successful, otherwise an HLE abort may be signaled.
If an encoded byte sequence that meets XACQUIRE/XRELEASE requirements includes both prefixes, then the HLE
semantic is determined by the prefix byte that is placed closest to the instruction opcode. For example, an F3F2C6
will not be treated as a XRELEASE-enabled instruction since the F2H (XACQUIRE) is closest to the instruction
opcode C6. Similarly, an F2F3F0 prefixed instruction will be treated as a XRELEASE-enabled instruction since F3H
(XRELEASE) is closest to the instruction opcode.
XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints
Vol. 2C 5-575
INSTRUCTION SET REFERENCE, V-Z
Intel 64 and IA-32 Compatibility
The effect of the XACQUIRE/XRELEASE prefix hint is the same in non-64-bit modes and in 64-bit mode.
For instructions that do not support the XACQUIRE hint, the presence of the F2H prefix behaves the same way as
prior hardware, according to
•
•
•
•
REPNE/REPNZ semantics for string instructions,
Serve as SIMD prefix for legacy SIMD instructions operating on XMM register
Cause #UD if prepending the VEX prefix.
Undefined for non-string instructions or other situations.
For instructions that do not support the XRELEASE hint, the presence of the F3H prefix behaves the same way as in
prior hardware, according to
•
•
•
•
REP/REPE/REPZ semantics for string instructions,
Serve as SIMD prefix for legacy SIMD instructions operating on XMM register
Cause #UD if prepending the VEX prefix.
Undefined for non-string instructions or other situations.
Operation
XACQUIRE
IF XACQUIRE-enabled instruction
THEN
IF (HLE_NEST_COUNT < MAX_HLE_NEST_COUNT) THEN
HLE_NEST_COUNT++
IF (HLE_NEST_COUNT = 1) THEN
HLE_ACTIVE ← 1
IF 64-bit mode
THEN
restartRIP ← instruction pointer of the XACQUIRE-enabled instruction
ELSE
restartEIP ← instruction pointer of the XACQUIRE-enabled instruction
FI;
Enter HLE Execution (* record register state, start tracking memory state *)
FI; (* HLE_NEST_COUNT = 1*)
IF ElisionBufferAvailable
THEN
Allocate elision buffer
Record address and data for forwarding and commit checking
Perform elision
ELSE
Perform lock acquire operation transactionally but without elision
FI;
ELSE (* HLE_NEST_COUNT = MAX_HLE_NEST_COUNT *)
GOTO HLE_ABORT_PROCESSING
FI;
ELSE
Treat instruction as non-XACQUIRE F2H prefixed legacy instruction
FI;
5-576 Vol. 2C
XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints
INSTRUCTION SET REFERENCE, V-Z
XRELEASE
IF XRELEASE-enabled instruction
THEN
IF (HLE_NEST_COUNT > 0)
THEN
HLE_NEST_COUNT-IF lock address matches in elision buffer THEN
IF lock satisfies address and value requirements THEN
Deallocate elision buffer
ELSE
GOTO HLE_ABORT_PROCESSING
FI;
FI;
IF (HLE_NEST_COUNT = 0)
THEN
IF NoAllocatedElisionBuffer
THEN
Try to commit transactional execution
IF fail to commit transactional execution
THEN
GOTO HLE_ABORT_PROCESSING;
ELSE (* commit success *)
HLE_ACTIVE ← 0
FI;
ELSE
GOTO HLE_ABORT_PROCESSING
FI;
FI;
FI; (* HLE_NEST_COUNT > 0 *)
ELSE
Treat instruction as non-XRELEASE F3H prefixed legacy instruction
FI;
(* For any HLE abort condition encountered during HLE execution *)
HLE_ABORT_PROCESSING:
HLE_ACTIVE ← 0
HLE_NEST_COUNT ← 0
Restore architectural register state
Discard memory updates performed in transaction
Free any allocated lock elision buffers
IF 64-bit mode
THEN
RIP ← restartRIP
ELSE
EIP ← restartEIP
FI;
Execute and retire instruction at RIP (or EIP) and ignore any HLE hint
END
XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints
Vol. 2C 5-577
INSTRUCTION SET REFERENCE, V-Z
SIMD Floating-Point Exceptions
None
Other Exceptions
#GP(0)
5-578 Vol. 2C
If the use of prefix causes instruction length to exceed 15 bytes.
XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints
INSTRUCTION SET REFERENCE, V-Z
XABORT — Transactional Abort
Opcode/Instruction
Op/
En
C6 F8 ib
XABORT imm8
A
64/32bit
Mode
Support
V/V
CPUID
Feature
Flag
RTM
Description
Causes an RTM abort if in RTM execution
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
A
imm8
NA
NA
NA
Description
XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback
address computed through the outermost XBEGIN instruction. The EAX register is updated to reflect an XABORT
instruction caused the abort, and the imm8 argument will be provided in bits 31:24 of EAX.
Operation
XABORT
IF RTM_ACTIVE = 0
THEN
Treat as NOP;
ELSE
GOTO RTM_ABORT_PROCESSING;
FI;
(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
Restore architectural register state;
Discard memory updates performed in transaction;
Update EAX with status and XABORT argument;
RTM_NEST_COUNT ← 0;
RTM_ACTIVE ← 0;
IF 64-bit Mode
THEN
RIP ← fallbackRIP;
ELSE
EIP ← fallbackEIP;
FI;
END
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
XABORT:
void _xabort( unsigned int);
SIMD Floating-Point Exceptions
None
XABORT — Transactional Abort
Vol. 2C 5-579
INSTRUCTION SET REFERENCE, V-Z
Other Exceptions
#UD
CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.
If LOCK prefix is used.
5-580 Vol. 2C
XABORT — Transactional Abort
INSTRUCTION SET REFERENCE, V-Z
XADD—Exchange and Add
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F C0 /r
XADD r/m8, r8
MR
Valid
Valid
Exchange r8 and r/m8; load sum into r/m8.
REX + 0F C0 /r
XADD r/m8*, r8*
MR
Valid
N.E.
Exchange r8 and r/m8; load sum into r/m8.
0F C1 /r
XADD r/m16, r16
MR
Valid
Valid
Exchange r16 and r/m16; load sum into r/m16.
0F C1 /r
XADD r/m32, r32
MR
Valid
Valid
Exchange r32 and r/m32; load sum into r/m32.
REX.W + 0F C1 /r
XADD r/m64, r64
MR
Valid
N.E.
Exchange r64 and r/m64; load sum into r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r, w)
NA
NA
Description
Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum
of the two values into the destination operand. The destination operand can be a register or a memory location; the
source operand is a register.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
IA-32 Architecture Compatibility
IA-32 processors earlier than the Intel486 processor do not recognize this instruction. If this instruction is used,
you should provide an equivalent code sequence that runs on earlier processors.
Operation
TEMP ← SRC + DEST;
SRC ← DEST;
DEST ← TEMP;
Flags Affected
The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination
operand.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
XADD—Exchange and Add
Vol. 2C 5-581
INSTRUCTION SET REFERENCE, V-Z
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
5-582 Vol. 2C
XADD—Exchange and Add
INSTRUCTION SET REFERENCE, V-Z
XBEGIN — Transactional Begin
Opcode/Instruction
Op/
En
A
64/32bit
Mode
Support
V/V
CPUID
Feature
Flag
RTM
C7 F8
XBEGIN rel16
C7 F8
XBEGIN rel32
A
V/V
RTM
Description
Specifies the start of an RTM region. Provides a 16-bit relative
offset to compute the address of the fallback instruction address at
which execution resumes following an RTM abort.
Specifies the start of an RTM region. Provides a 32-bit relative
offset to compute the address of the fallback instruction address at
which execution resumes following an RTM abort.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
A
Offset
NA
NA
NA
Description
The XBEGIN instruction specifies the start of an RTM code region. If the logical processor was not already in transactional execution, then the XBEGIN instruction causes the logical processor to transition into transactional execution. The XBEGIN instruction that transitions the logical processor into transactional execution is referred to as the
outermost XBEGIN instruction. The instruction also specifies a relative offset to compute the address of the fallback
code path following a transactional abort.
On an RTM abort, the logical processor discards all architectural register and memory updates performed during
the RTM execution and restores architectural state to that corresponding to the outermost XBEGIN instruction. The
fallback address following an abort is computed from the outermost XBEGIN instruction.
Operation
XBEGIN
IF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT
THEN
RTM_NEST_COUNT++
IF RTM_NEST_COUNT = 1 THEN
IF 64-bit Mode
THEN
fallbackRIP ← RIP + SignExtend64(IMM)
(* RIP is instruction following XBEGIN instruction *)
ELSE
fallbackEIP ← EIP + SignExtend32(IMM)
(* EIP is instruction following XBEGIN instruction *)
FI;
IF (64-bit mode)
THEN IF (fallbackRIP is not canonical)
THEN #GP(0)
FI;
ELSE IF (fallbackEIP outside code segment limit)
THEN #GP(0)
FI;
FI;
RTM_ACTIVE ← 1
Enter RTM Execution (* record register state, start tracking memory state*)
FI; (* RTM_NEST_COUNT = 1 *)
XBEGIN — Transactional Begin
Vol. 2C 5-583
INSTRUCTION SET REFERENCE, V-Z
ELSE (* RTM_NEST_COUNT = MAX_RTM_NEST_COUNT *)
GOTO RTM_ABORT_PROCESSING
FI;
(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
Restore architectural register state
Discard memory updates performed in transaction
Update EAX with status
RTM_NEST_COUNT ← 0
RTM_ACTIVE ← 0
IF 64-bit mode
THEN
RIP ← fallbackRIP
ELSE
EIP ← fallbackEIP
FI;
END
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
XBEGIN:
unsigned int _xbegin( void );
SIMD Floating-Point Exceptions
None
Protected Mode Exceptions
#UD
CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.
If LOCK prefix is used.
#GP(0)
If the fallback address is outside the CS segment.
Real-Address Mode Exceptions
#GP(0)
#UD
If the fallback address is outside the address space 0000H and FFFFH.
CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.
If LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
#UD
If the fallback address is outside the address space 0000H and FFFFH.
CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.
If LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
5-584 Vol. 2C
XBEGIN — Transactional Begin
INSTRUCTION SET REFERENCE, V-Z
64-bit Mode Exceptions
#UD
CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.
If LOCK prefix is used.
#GP(0)
If the fallback address is non-canonical.
XBEGIN — Transactional Begin
Vol. 2C 5-585
INSTRUCTION SET REFERENCE, V-Z
XCHG—Exchange Register/Memory with Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
90+rw
XCHG AX, r16
O
Valid
Valid
Exchange r16 with AX.
90+rw
XCHG r16, AX
O
Valid
Valid
Exchange AX with r16.
90+rd
XCHG EAX, r32
O
Valid
Valid
Exchange r32 with EAX.
REX.W + 90+rd
XCHG RAX, r64
O
Valid
N.E.
Exchange r64 with RAX.
90+rd
XCHG r32, EAX
O
Valid
Valid
Exchange EAX with r32.
REX.W + 90+rd
XCHG r64, RAX
O
Valid
N.E.
Exchange RAX with r64.
86 /r
XCHG r/m8, r8
MR
Valid
Valid
Exchange r8 (byte register) with byte from
r/m8.
REX + 86 /r
XCHG r/m8*, r8*
MR
Valid
N.E.
Exchange r8 (byte register) with byte from
r/m8.
86 /r
XCHG r8, r/m8
RM
Valid
Valid
Exchange byte from r/m8 with r8 (byte
register).
REX + 86 /r
XCHG r8*, r/m8*
RM
Valid
N.E.
Exchange byte from r/m8 with r8 (byte
register).
87 /r
XCHG r/m16, r16
MR
Valid
Valid
Exchange r16 with word from r/m16.
87 /r
XCHG r16, r/m16
RM
Valid
Valid
Exchange word from r/m16 with r16.
87 /r
XCHG r/m32, r32
MR
Valid
Valid
Exchange r32 with doubleword from r/m32.
REX.W + 87 /r
XCHG r/m64, r64
MR
Valid
N.E.
Exchange r64 with quadword from r/m64.
87 /r
XCHG r32, r/m32
RM
Valid
Valid
Exchange doubleword from r/m32 with r32.
REX.W + 87 /r
XCHG r64, r/m64
RM
Valid
N.E.
Exchange quadword from r/m64 with r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
O
AX/EAX/RAX (r, w)
opcode + rd (r, w)
NA
NA
O
opcode + rd (r, w)
AX/EAX/RAX (r, w)
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Exchanges the contents of the destination (first) and source (second) operands. The operands can be two generalpurpose registers or a register and a memory location. If a memory operand is referenced, the processor’s locking
protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or
absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more
information on the locking protocol.)
This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See
“Bus Locking” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for
more information on bus locking.)
The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
5-586 Vol. 2C
XCHG—Exchange Register/Memory with Register
INSTRUCTION SET REFERENCE, V-Z
NOTE
XCHG (E)AX, (E)AX (encoded instruction byte is 90H) is an alias for NOP regardless of data size
prefixes, including REX.W.
Operation
TEMP ← DEST;
DEST ← SRC;
SRC ← TEMP;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If either operand is in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
XCHG—Exchange Register/Memory with Register
Vol. 2C 5-587
INSTRUCTION SET REFERENCE, V-Z
XEND — Transactional End
Opcode/Instruction
Op/
En
0F 01 D5
XEND
A
64/32bit
Mode
Support
V/V
CPUID
Feature
Flag
RTM
Description
Specifies the end of an RTM code region.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
A
NA
NA
NA
NA
Description
The instruction marks the end of an RTM code region. If this corresponds to the outermost scope (that is, including
this XEND instruction, the number of XBEGIN instructions is the same as number of XEND instructions), the logical
processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will
rollback all architectural register and memory updates performed during the RTM execution. The logical processor
will resume execution at the fallback address computed from the outermost XBEGIN instruction. The EAX register
is updated to reflect RTM abort information.
XEND executed outside a transactional region will cause a #GP (General Protection Fault).
Operation
XEND
IF (RTM_ACTIVE = 0) THEN
SIGNAL #GP
ELSE
RTM_NEST_COUNT-IF (RTM_NEST_COUNT = 0) THEN
Try to commit transaction
IF fail to commit transactional execution
THEN
GOTO RTM_ABORT_PROCESSING;
ELSE (* commit success *)
RTM_ACTIVE ← 0
FI;
FI;
FI;
(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
Restore architectural register state
Discard memory updates performed in transaction
Update EAX with status
RTM_NEST_COUNT ← 0
RTM_ACTIVE ← 0
IF 64-bit Mode
THEN
RIP ← fallbackRIP
ELSE
EIP ← fallbackEIP
FI;
END
5-588 Vol. 2C
XEND — Transactional End
INSTRUCTION SET REFERENCE, V-Z
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
XEND:
void _xend( void );
SIMD Floating-Point Exceptions
None
Other Exceptions
#UD
CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.
If LOCK or 66H or F2H or F3H prefix is used.
#GP(0)
XEND — Transactional End
If RTM_ACTIVE = 0.
Vol. 2C 5-589
INSTRUCTION SET REFERENCE, V-Z
XGETBV—Get Value of Extended Control Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 D0
XGETBV
NP
Valid
Valid
Reads an XCR specified by ECX into EDX:EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Reads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On
processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is
loaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer
than 64 bits are implemented in the XCR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.
XCR0 is supported on any processor that supports the XGETBV instruction. If
CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 1, executing XGETBV with ECX = 1 returns in EDX:EAX the logicalAND of XCR0 and the current value of the XINUSE state-component bitmap. This allows software to discover the
state of the init optimization used by XSAVEOPT and XSAVES. See Chapter 13, “Managing State Using the XSAVE
Feature Set‚” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Use of any other value for ECX results in a general-protection (#GP) exception.
Operation
EDX:EAX ← XCR[ECX];
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XGETBV:
unsigned __int64 _xgetbv( unsigned int);
Protected Mode Exceptions
#GP(0)
#UD
If an invalid XCR is specified in ECX (includes ECX = 1 if
CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If the LOCK prefix is used.
If 66H, F3H or F2H prefix is used.
Real-Address Mode Exceptions
#GP(0)
#UD
If an invalid XCR is specified in ECX (includes ECX = 1 if
CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If the LOCK prefix is used.
If 66H, F3H or F2H prefix is used.
5-590 Vol. 2C
XGETBV—Get Value of Extended Control Register
INSTRUCTION SET REFERENCE, V-Z
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
XGETBV—Get Value of Extended Control Register
Vol. 2C 5-591
INSTRUCTION SET REFERENCE, V-Z
XLAT/XLATB—Table Look-up Translation
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
D7
XLAT m8
NP
Valid
Valid
Set AL to memory byte DS:[(E)BX + unsigned
AL].
D7
XLATB
NP
Valid
Valid
Set AL to memory byte DS:[(E)BX + unsigned
AL].
REX.W + D7
XLATB
NP
Valid
N.E.
Set AL to memory byte [RBX + unsigned AL].
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Locates a byte entry in a table in memory, using the contents of the AL register as a table index, then copies the
contents of the table entry back into the AL register. The index in the AL register is treated as an unsigned integer.
The XLAT and XLATB instructions get the base address of the table in memory from either the DS:EBX or the DS:BX
registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The DS segment may
be overridden with a segment override prefix.)
At the assembly-code level, two forms of this instruction are allowed: the “explicit-operand” form and the “nooperand” form. The explicit-operand form (specified with the XLAT mnemonic) allows the base address of the table
to be specified explicitly with a symbol. This explicit-operands form is provided to allow documentation; however,
note that the documentation provided by this form can be misleading. That is, the symbol does not have to specify
the correct base address. The base address is always specified by the DS:(E)BX registers, which must be loaded
correctly before the XLAT instruction is executed.
The no-operands form (XLATB) provides a “short form” of the XLAT instructions. Here also the processor assumes
that the DS:(E)BX registers contain the base address of the table.
In 64-bit mode, operation is similar to that in legacy or compatibility mode. AL is used to specify the table index
(the operand size is fixed at 8 bits). RBX, however, is used to specify the table’s base address. See the summary
chart at the beginning of this section for encoding data and limits.
Operation
IF AddressSize = 16
THEN
AL ← (DS:BX + ZeroExtend(AL));
ELSE IF (AddressSize = 32)
AL ← (DS:EBX + ZeroExtend(AL)); FI;
ELSE (AddressSize = 64)
AL ← (RBX + ZeroExtend(AL));
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
5-592 Vol. 2C
XLAT/XLATB—Table Look-up Translation
INSTRUCTION SET REFERENCE, V-Z
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#UD
If the LOCK prefix is used.
XLAT/XLATB—Table Look-up Translation
Vol. 2C 5-593
INSTRUCTION SET REFERENCE, V-Z
XOR—Logical Exclusive OR
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
34 ib
XOR AL, imm8
I
Valid
Valid
AL XOR imm8.
35 iw
XOR AX, imm16
I
Valid
Valid
AX XOR imm16.
35 id
XOR EAX, imm32
I
Valid
Valid
EAX XOR imm32.
REX.W + 35 id
XOR RAX, imm32
I
Valid
N.E.
RAX XOR imm32 (sign-extended).
80 /6 ib
XOR r/m8, imm8
MI
Valid
Valid
r/m8 XOR imm8.
REX + 80 /6 ib
XOR r/m8*, imm8
MI
Valid
N.E.
r/m8 XOR imm8.
81 /6 iw
XOR r/m16, imm16
MI
Valid
Valid
r/m16 XOR imm16.
81 /6 id
XOR r/m32, imm32
MI
Valid
Valid
r/m32 XOR imm32.
REX.W + 81 /6 id
XOR r/m64, imm32
MI
Valid
N.E.
r/m64 XOR imm32 (sign-extended).
83 /6 ib
XOR r/m16, imm8
MI
Valid
Valid
r/m16 XOR imm8 (sign-extended).
83 /6 ib
XOR r/m32, imm8
MI
Valid
Valid
r/m32 XOR imm8 (sign-extended).
REX.W + 83 /6 ib
XOR r/m64, imm8
MI
Valid
N.E.
r/m64 XOR imm8 (sign-extended).
30 /r
XOR r/m8, r8
MR
Valid
Valid
r/m8 XOR r8.
REX + 30 /r
XOR r/m8*, r8*
MR
Valid
N.E.
r/m8 XOR r8.
31 /r
XOR r/m16, r16
MR
Valid
Valid
r/m16 XOR r16.
31 /r
XOR r/m32, r32
MR
Valid
Valid
r/m32 XOR r32.
REX.W + 31 /r
XOR r/m64, r64
MR
Valid
N.E.
r/m64 XOR r64.
32 /r
XOR r8, r/m8
RM
Valid
Valid
r8 XOR r/m8.
REX + 32 /r
XOR r8*, r/m8*
RM
Valid
N.E.
r8 XOR r/m8.
33 /r
XOR r16, r/m16
RM
Valid
Valid
r16 XOR r/m16.
33 /r
XOR r32, r/m32
RM
Valid
Valid
r32 XOR r/m32.
REX.W + 33 /r
XOR r64, r/m64
RM
Valid
N.E.
r64 XOR r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
I
AL/AX/EAX/RAX
imm8/16/32
NA
NA
MI
ModRM:r/m (r, w)
imm8/16/32
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Performs a bitwise exclusive OR (XOR) operation on the destination (first) and source (second) operands and
stores the result in the destination operand location. The source operand can be an immediate, a register, or a
memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result is 1 if the corresponding bits of the operands are
different; each bit is 0 if the corresponding bits are the same.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
5-594 Vol. 2C
XOR—Logical Exclusive OR
INSTRUCTION SET REFERENCE, V-Z
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a
REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.
Operation
DEST ← DEST XOR SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is
undefined.
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
XOR—Logical Exclusive OR
Vol. 2C 5-595
INSTRUCTION SET REFERENCE, V-Z
XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op /
En
66 0F 57/r
XORPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 57 /r
VXORPD xmm1,xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG 57 /r
VXORPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 57 /r
VXORPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 57 /r
VXORPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 57 /r
VXORPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical XOR of packed doubleprecision floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical XOR of packed doubleprecision floating-point values in xmm2 and
xmm3/m128/m64bcst subject to writemask k1.
Return the bitwise logical XOR of packed doubleprecision floating-point values in ymm2 and
ymm3/m256/m64bcst subject to writemask k1.
Return the bitwise logical XOR of packed doubleprecision floating-point values in zmm2 and
zmm3/m512/m64bcst subject to writemask k1.
RM
RVM
Description
Return the bitwise logical XOR of packed doubleprecision floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical XOR of packed doubleprecision floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical XOR of the two, four or eight packed double-precision floating-point values from the first
source operand and the second source operand, and stores the result in the destination operand
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM
register or a vector memory location. The destination operand is a ZMM register conditionally updated with
writemask k1.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination
are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination
are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
Operation
VXORPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask* THEN
5-596 Vol. 2C
XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] SRC1[i+63:i] BITWISE XOR SRC2[63:0];
ELSE DEST[i+63:i] SRC1[i+63:i] BITWISE XOR SRC2[i+63:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VXORPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[191:128] SRC1[191:128] BITWISE XOR SRC2[191:128]
DEST[255:192] SRC1[255:192] BITWISE XOR SRC2[255:192]
DEST[MAX_VL-1:256] 0
VXORPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[MAX_VL-1:128] 0
XORPD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] BITWISE XOR SRC[63:0]
DEST[127:64] DEST[127:64] BITWISE XOR SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VXORPD __m512d _mm512_xor_pd (__m512d a, __m512d b);
VXORPD __m512d _mm512_mask_xor_pd (__m512d a, __mmask8 m, __m512d b);
VXORPD __m512d _mm512_maskz_xor_pd (__mmask8 m, __m512d a);
VXORPD __m256d _mm256_xor_pd (__m256d a, __m256d b);
VXORPD __m256d _mm256_mask_xor_pd (__m256d a, __mmask8 m, __m256d b);
VXORPD __m256d _mm256_maskz_xor_pd (__mmask8 m, __m256d a);
XORPD __m128d _mm_xor_pd (__m128d a, __m128d b);
VXORPD __m128d _mm_mask_xor_pd (__m128d a, __mmask8 m, __m128d b);
VXORPD __m128d _mm_maskz_xor_pd (__mmask8 m, __m128d a);
SIMD Floating-Point Exceptions
None
XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values
Vol. 2C 5-597
INSTRUCTION SET REFERENCE, V-Z
Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4.
5-598 Vol. 2C
XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 57 /r
XORPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 57 /r
VXORPS xmm1,xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.0F.WIG 57 /r
VXORPS ymm1, ymm2, ymm3/m256
RVM
V/V
AVX
EVEX.NDS.128.0F.W0 57 /r
VXORPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 57 /r
VXORPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 57 /r
VXORPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Description
Return the bitwise logical XOR of packed singleprecision floating-point values in xmm1 and
xmm2/mem.
Return the bitwise logical XOR of packed singleprecision floating-point values in xmm2 and
xmm3/mem.
Return the bitwise logical XOR of packed singleprecision floating-point values in ymm2 and
ymm3/mem.
Return the bitwise logical XOR of packed singleprecision floating-point values in xmm2 and
xmm3/m128/m32bcst subject to writemask k1.
Return the bitwise logical XOR of packed singleprecision floating-point values in ymm2 and
ymm3/m256/m32bcst subject to writemask k1.
Return the bitwise logical XOR of packed singleprecision floating-point values in zmm2 and
zmm3/m512/m32bcst subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical XOR of the four, eight or sixteen packed single-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM
register or a vector memory location. The destination operand is a ZMM register conditionally updated with
writemask k1.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination
are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination
are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values
Vol. 2C 5-599
INSTRUCTION SET REFERENCE, V-Z
Operation
VXORPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j 0 TO KL-1
i j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] SRC1[i+31:i] BITWISE XOR SRC2[31:0];
ELSE DEST[i+31:i] SRC1[i+31:i] BITWISE XOR SRC2[i+31:i];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] = 0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL] 0
VXORPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[159:128] SRC1[159:128] BITWISE XOR SRC2[159:128]
DEST[191:160] SRC1[191:160] BITWISE XOR SRC2[191:160]
DEST[223:192] SRC1[223:192] BITWISE XOR SRC2[223:192]
DEST[255:224] SRC1[255:224] BITWISE XOR SRC2[255:224].
DEST[MAX_VL-1:256] 0
VXORPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[MAX_VL-1:128] 0
XORPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VXORPS __m512 _mm512_xor_ps (__m512 a, __m512 b);
VXORPS __m512 _mm512_mask_xor_ps (__m512 a, __mmask16 m, __m512 b);
VXORPS __m512 _mm512_maskz_xor_ps (__mmask16 m, __m512 a);
VXORPS __m256 _mm256_xor_ps (__m256 a, __m256 b);
VXORPS __m256 _mm256_mask_xor_ps (__m256 a, __mmask8 m, __m256 b);
VXORPS __m256 _mm256_maskz_xor_ps (__mmask8 m, __m256 a);
XORPS __m128 _mm_xor_ps (__m128 a, __m128 b);
VXORPS __m128 _mm_mask_xor_ps (__m128 a, __mmask8 m, __m128 b);
5-600 Vol. 2C
XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
VXORPS __m128 _mm_maskz_xor_ps (__mmask8 m, __m128 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4.
XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values
Vol. 2C 5-601
INSTRUCTION SET REFERENCE, V-Z
XRSTOR—Restore Processor Extended States
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AE /5
XRSTOR mem
M
Valid
Valid
Restore state components specified by
EDX:EAX from mem.
REX.W+ 0F AE /5
XRSTOR64 mem
M
Valid
N.E.
Restore state components specified by
EDX:EAX from mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Performs a full or partial restore of processor state components from the XSAVE area located at the memory
address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Section 13.8, “Operation of XRSTOR,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a highlevel outline:
•
Execution of XRSTOR may take one of two forms: standard and compacted. Bit 63 of the XCOMP_BV field in the
XSAVE header determines which form is used: value 0 specifies the standard form, while value 1 specifies the
compacted form.
•
•
If RFBM[i] = 0, XRSTOR does not update state component i.1
If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header, XRSTOR initializes state
component i.
•
•
If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTOR loads state component i from the XSAVE area.
•
XRSTOR loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of
XSAVEOPT or XSAVES.
•
Immediately following an execution of XRSTOR, the processor tracks as in-use (not in initial configuration) any
state component i for which RFBM[i] = 1 and XSTATE_BV[i] = 1; it tracks as modified any state component
i for which RFBM[i] = 0.
The standard form of XRSTOR treats MXCSR (which is part of state component 1 — SSE) differently from the
XMM registers. If either form attempts to load MXCSR with an illegal value, a general-protection exception
(#GP) occurs.
Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.
Operation
RFBM ← XCR0 AND EDX:EAX; /* bitwise logical AND */
COMPMASK ← XCOMP_BV field from XSAVE header;
RSTORMASK ← XSTATE_BV field from XSAVE header;
IF in VMX non-root operation
THEN VMXNR ← 1;
1. There is an exception if RFBM[1] = 0 and RFBM[2] = 1. In this case, the standard form of XRSTOR will load MXCSR from memory,
even though MXCSR is part of state component 1 — SSE. The compacted form of XRSTOR does not make this exception.
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XRSTOR—Restore Processor Extended States
INSTRUCTION SET REFERENCE, V-Z
ELSE VMXNR ← 0;
FI;
LAXA ← linear address of XSAVE area;
IF COMPMASK[63] = 0
THEN
/* Standard form of XRSTOR */
If RFBM[0] = 1
THEN
IF RSTORMASK[0] = 1
THEN load x87 state from legacy region of XSAVE area;
ELSE initialize x87 state;
FI;
FI;
If RFBM[1] = 1
THEN
IF RSTORMASK[1] = 1
THEN load XMM registers from legacy region of XSAVE area;
ELSE set all XMM registers to 0;
FI;
FI;
If RFBM[2] = 1
THEN
IF RSTORMASK[2] = 1
THEN load AVX state from extended region (standard format) of XSAVE area;
ELSE initialize AVX state;
FI;
FI;
If RFBM[1] = 1 or RFBM[2] = 1
THEN load MXCSR from legacy region of XSAVE area;
FI;
FI;
ELSE
/* Compacted form of XRSTOR */
IF CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0
THEN
/* compacted form not supported */
#GP(0);
FI;
If RFBM[0] = 1
THEN
IF RSTORMASK[0] = 1
THEN load x87 state from legacy region of XSAVE area;
ELSE initialize x87 state;
FI;
FI;
If RFBM[1] = 1
THEN
IF RSTORMASK[1] = 1
THEN load SSE state from legacy region of XSAVE area;
ELSE initialize SSE state;
FI;
FI;
If RFBM[2] = 1
THEN
XRSTOR—Restore Processor Extended States
Vol. 2C 5-603
INSTRUCTION SET REFERENCE, V-Z
IF RSTORMASK[2] = 1
THEN load AVX state from extended region (compacted format) of XSAVE area;
ELSE initialize AVX state;
FI;
FI;
FI;
XRSTOR_INFO ← CPL,VMXNR,LAXA,COMPMASK;
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XRSTOR:
void _xrstor( void * , unsigned __int64);
XRSTOR:
void _xrstor64( void * , unsigned __int64);
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and
CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the
XSTATE_BV field of the XSAVE header is 1.
If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.
If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the
XCOMP_BV field of the XSAVE header is 1.
If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0
and the corresponding bit in the XSTATE_BV field is 1.
If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.
If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and
CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
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INSTRUCTION SET REFERENCE, V-Z
If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the
XSTATE_BV field of the XSAVE header is 1.
If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.
If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the
XCOMP_BV field of the XSAVE header is 1.
If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0
and the corresponding bit in the XSTATE_BV field is 1.
If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.
If attempting to write any reserved bits of the MXCSR register with 1.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If a memory address is in a non-canonical form.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and
CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the
XSTATE_BV field of the XSAVE header is 1.
If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.
If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the
XCOMP_BV field of the XSAVE header is 1.
If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0
and the corresponding bit in the XSTATE_BV field is 1.
If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.
If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
XRSTOR—Restore Processor Extended States
Vol. 2C 5-605
INSTRUCTION SET REFERENCE, V-Z
XRSTORS—Restore Processor Extended States Supervisor
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F C7 /3
XRSTORS mem
M
Valid
Valid
Restore state components specified by
EDX:EAX from mem.
REX.W+ 0F C7 /3
XRSTORS64 mem
M
Valid
N.E.
Restore state components specified by
EDX:EAX from mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
NA
NA
NA
Description
Performs a full or partial restore of processor state components from the XSAVE area located at the memory
address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and the logical-OR of XCR0 with the IA32_XSS MSR. XRSTORS may be executed only if
CPL = 0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Section 13.12, “Operation of XRSTORS,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a
high-level outline:
•
Execution of XRSTORS is similar to that of the compacted form of XRSTOR; XRSTORS cannot restore from an
XSAVE area in which the extended region is in the standard format (see Section 13.4.3, “Extended Region of an
XSAVE Area”).
•
XRSTORS differs from XRSTOR in that it can restore state components corresponding to bits set in the
IA32_XSS MSR.
•
•
If RFBM[i] = 0, XRSTORS does not update state component i.
If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header, XRSTORS initializes state
component i.
•
•
•
If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTORS loads state component i from the XSAVE area.
•
Immediately following an execution of XRSTORS, the processor tracks as in-use (not in initial configuration)
any state component i for which RFBM[i] = 1 and XSTATE_BV[i] = 1; it tracks as modified any state component
i for which RFBM[i] = 0.
If XRSTORS attempts to load MXCSR with an illegal value, a general-protection exception (#GP) occurs.
XRSTORS loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of
XSAVEOPT or XSAVES.
Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.
Operation
RFBM ← (XCR0 OR IA32_XSS) AND EDX:EAX;
/* bitwise logical OR and AND */
COMPMASK ← XCOMP_BV field from XSAVE header;
RSTORMASK ← XSTATE_BV field from XSAVE header;
IF in VMX non-root operation
THEN VMXNR ← 1;
ELSE VMXNR ← 0;
FI;
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INSTRUCTION SET REFERENCE, V-Z
LAXA ← linear address of XSAVE area;
If RFBM[0] = 1
THEN
IF RSTORMASK[0] = 1
THEN load x87 state from legacy region of XSAVE area;
ELSE initialize x87 state;
FI;
FI;
If RFBM[1] = 1
THEN
IF RSTORMASK[1] = 1
THEN load SSE state from legacy region of XSAVE area;
ELSE initialize SSE state;
FI;
FI;
If RFBM[2] = 1
THEN
IF RSTORMASK[2] = 1
THEN load AVX state from extended region (compacted format) of XSAVE area;
ELSE initialize AVX state;
FI;
FI;
XRSTOR_INFO ← CPL,VMXNR,LAXA,COMPMASK;
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XRSTORS:
void _xrstors( void * , unsigned __int64);
XRSTORS64: void _xrstors64( void * , unsigned __int64);
Protected Mode Exceptions
#GP(0)
If CPL > 0.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If bit 63 of the XCOMP_BV field of the XSAVE header is 0.
If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.
If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the
XSTATE_BV field is 1.
If bytes 63:16 of the XSAVE header are not all zero.
If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
XRSTORS—Restore Processor Extended States Supervisor
Vol. 2C 5-607
INSTRUCTION SET REFERENCE, V-Z
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a #GP
is signaled in its place. In addition, the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be
signaled for a 2-byte misalignment, whereas a #GP might be signaled for all other misalignments (4-, 8-, or 16-byte misalignments).
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
If bit 63 of the XCOMP_BV field of the XSAVE header is 0.
If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.
If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the
XSTATE_BV field is 1.
If bytes 63:16 of the XSAVE header are not all zero.
If attempting to write any reserved bits of the MXCSR register with 1.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If CPL > 0.
If a memory address is in a non-canonical form.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If bit 63 of the XCOMP_BV field of the XSAVE header is 0.
If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.
If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the
XSTATE_BV field is 1.
If bytes 63:16 of the XSAVE header are not all zero.
If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
5-608 Vol. 2C
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protecXRSTORS—Restore Processor Extended States Supervisor
INSTRUCTION SET REFERENCE, V-Z
tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
XRSTORS—Restore Processor Extended States Supervisor
Vol. 2C 5-609
INSTRUCTION SET REFERENCE, V-Z
XSAVE—Save Processor Extended States
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F AE /4
XSAVE mem
M
Valid
Valid
Save state components specified by EDX:EAX
to mem.
REX.W+ 0F AE /4
XSAVE64 mem
M
Valid
N.E.
Save state components specified by EDX:EAX
to mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Performs a full or partial save of processor state components to the XSAVE area located at the memory address
specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Section 13.7, “Operation of XSAVE,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1
provides a detailed description of the operation of the XSAVE instruction. The following items provide a high-level
outline:
•
•
XSAVE saves state component i if and only if RFBM[i] = 1.1
•
XSAVE reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, “XSAVE Header”) and writes a
modified value back to memory as follows. If RFBM[i] = 1, XSAVE writes XSTATE_BV[i] with the value of
XINUSE[i]. (XINUSE is a bitmap by which the processor tracks the status of various state components. See
Section 13.6, “Processor Tracking of XSAVE-Managed State.”) If RFBM[i] = 0, XSAVE writes XSTATE_BV[i] with
the value that it read from memory (it does not modify the bit). XSAVE does not write to any part of the XSAVE
header other than the XSTATE_BV field.
•
XSAVE always uses the standard format of the extended region of the XSAVE area (see Section 13.4.3,
“Extended Region of an XSAVE Area”).
XSAVE does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, “Legacy
Region of an XSAVE Area”).
Use of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.
Operation
RFBM ← XCR0 AND EDX:EAX; /* bitwise logical AND */
OLD_BV ← XSTATE_BV field from XSAVE header;
IF RFBM[0] = 1
THEN store x87 state into legacy region of XSAVE area;
FI;
IF RFBM[1] = 1
THEN store XMM registers into legacy region of XSAVE area;
FI;
1. An exception is made for MXCSR and MXCSR_MASK, which belong to state component 1 — SSE. XSAVE saves these values to memory if either RFBM[1] or RFBM[2] is 1.
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XSAVE—Save Processor Extended States
INSTRUCTION SET REFERENCE, V-Z
IF RFBM[2] = 1
THEN store AVX state into extended region of XSAVE area;
FI;
IF RFBM[1] = 1 or RFBM[2] = 1
THEN store MXCSR and MXCSR_MASK into legacy region of XSAVE area;
FI;
XSTATE_BV field in XSAVE header ← (OLD_BV AND ~RFBM) OR (XINUSE AND RFBM);
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XSAVE:
void _xsave( void * , unsigned __int64);
XSAVE:
void _xsave64( void * , unsigned __int64);
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NM
#UD
If CR0.TS[bit 3] = 1.
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
XSAVE—Save Processor Extended States
Vol. 2C 5-611
INSTRUCTION SET REFERENCE, V-Z
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
5-612 Vol. 2C
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
XSAVE—Save Processor Extended States
INSTRUCTION SET REFERENCE, V-Z
XSAVEC—Save Processor Extended States with Compaction
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F C7 /4
XSAVEC mem
M
Valid
Valid
Save state components specified by EDX:EAX
to mem with compaction.
REX.W+ 0F C7 /4
XSAVEC64 mem
M
Valid
N.E.
Save state components specified by EDX:EAX
to mem with compaction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Performs a full or partial save of processor state components to the XSAVE area located at the memory address
specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Section 13.10, “Operation of XSAVEC,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
1 provides a detailed description of the operation of the XSAVEC instruction. The following items provide a highlevel outline:
•
Execution of XSAVEC is similar to that of XSAVE. XSAVEC differs from XSAVE in that it uses compaction and that
it may use the init optimization.
•
XSAVEC saves state component i if and only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE is a bitmap by which
the processor tracks the status of various state components. See Section 13.6, “Processor Tracking of XSAVEManaged State.”)
•
XSAVEC does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, “Legacy
Region of an XSAVE Area”).
•
XSAVEC writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the XSAVE header.2,3 (See
Section 13.4.2, “XSAVE Header.”) XSAVEC sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to
RFBM[62:0]. XSAVEC does not write to any parts of the XSAVE header other than the XSTATE_BV and
XCOMP_BV fields.
•
XSAVEC always uses the compacted format of the extended region of the XSAVE area (see Section 13.4.3,
“Extended Region of an XSAVE Area”).
Use of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.
Operation
RFBM ← XCR0 AND EDX:EAX; /* bitwise logical AND */
COMPMASK ← RFBM OR 80000000_00000000H;
IF RFBM[0] = 1 and XINUSE[0] = 1
1. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not
have its initial value of 1F80H. In this case, XSAVEC saves SSE state as long as RFBM[1] = 1.
2. Unlike XSAVE and XSAVEOPT, XSAVEC clears bits in the XSTATE_BV field that correspond to bits that are clear in RFBM.
3. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not
have its initial value of 1F80H. In this case, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.
XSAVEC—Save Processor Extended States with Compaction
Vol. 2C 5-613
INSTRUCTION SET REFERENCE, V-Z
THEN store x87 state into legacy region of XSAVE area;
FI;
IF RFBM[1] = 1 and (XINUSE[1] = 1 or MXCSR ≠ 1F80H)
THEN store SSE state into legacy region of XSAVE area;
FI;
IF RFBM[2] = 1 AND XINUSE[2] = 1
THEN store AVX state into extended region of XSAVE area;
FI;
XSTATE_BV field in XSAVE header ← XINUSE AND RFBM;1
XCOMP_BV field in XSAVE header ← COMPMASK;
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XSAVEC:
void _xsavec( void * , unsigned __int64);
XSAVEC64:
void _xsavec64( void * , unsigned __int64);
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NM
#UD
If CR0.TS[bit 3] = 1.
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
1. If MXCSR does not have its initial value of 1F80H, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1, regardless of the value
of XINUSE[1].
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XSAVEC—Save Processor Extended States with Compaction
INSTRUCTION SET REFERENCE, V-Z
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
XSAVEC—Save Processor Extended States with Compaction
Vol. 2C 5-615
INSTRUCTION SET REFERENCE, V-Z
XSAVEOPT—Save Processor Extended States Optimized
Opcode/
Instruction
Op/
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
0F AE /6
M
V/V
XSAVEOPT Save state components specified by EDX:EAX
to mem, optimizing if possible.
M
V/V
XSAVEOPT Save state components specified by EDX:EAX
to mem, optimizing if possible.
XSAVEOPT mem
REX.W + 0F AE /6
XSAVEOPT64 mem
Description
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Performs a full or partial save of processor state components to the XSAVE area located at the memory address
specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Section 13.9, “Operation of XSAVEOPT,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1 provides a detailed description of the operation of the XSAVEOPT instruction. The following items provide
a high-level outline:
•
Execution of XSAVEOPT is similar to that of XSAVE. XSAVEOPT differs from XSAVE in that it uses compaction
and that it may use the init and modified optimizations. The performance of XSAVEOPT will be equal to or better
than that of XSAVE.
•
XSAVEOPT saves state component i only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE is a bitmap by which the
processor tracks the status of various state components. See Section 13.6, “Processor Tracking of XSAVEManaged State.”) Even if both bits are 1, XSAVEOPT may optimize and not save state component i if (1) state
component i has not been modified since the last execution of XRTOR or XRSTORS; and (2) this execution of
XSAVES corresponds to that last execution of XRTOR or XRSTORS as determined by the internal value
XRSTOR_INFO (see the Operation section below).
•
XSAVEOPT does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, “Legacy
Region of an XSAVE Area”).
•
XSAVEOPT reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, “XSAVE Header”) and writes a
modified value back to memory as follows. If RFBM[i] = 1, XSAVEOPT writes XSTATE_BV[i] with the value of
XINUSE[i]. If RFBM[i] = 0, XSAVEOPT writes XSTATE_BV[i] with the value that it read from memory (it does
not modify the bit). XSAVEOPT does not write to any part of the XSAVE header other than the XSTATE_BV field.
•
XSAVEOPT always uses the standard format of the extended region of the XSAVE area (see Section 13.4.3,
“Extended Region of an XSAVE Area”).
Use of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) will result in a
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.
Operation
RFBM ← XCR0 AND EDX:EAX; /* bitwise logical AND */
OLD_BV ← XSTATE_BV field from XSAVE header;
1. There is an exception made for MXCSR and MXCSR_MASK, which belong to state component 1 — SSE. XSAVEOPT always saves
these to memory if RFBM[1] = 1 or RFBM[2] = 1, regardless of the value of XINUSE.
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XSAVEOPT—Save Processor Extended States Optimized
INSTRUCTION SET REFERENCE, V-Z
IF in VMX non-root operation
THEN VMXNR ← 1;
ELSE VMXNR ← 0;
FI;
LAXA ← linear address of XSAVE area;
COMPMASK ← 00000000_00000000H;
IF XRSTOR_INFO = CPL,VMXNR,LAXA,COMPMASK
THEN MODOPT ← 1;
ELSE MODOPT ← 0;
FI;
IF RFBM[0] = 1 and XINUSE[0] = 1
THEN store x87 state into legacy region of XSAVE area;
/* might avoid saving if x87 state is not modified and MODOPT = 1 */
FI;
IF RFBM[1] = 1 and XINUSE[1]
THEN store XMM registers into legacy region of XSAVE area;
/* might avoid saving if XMM registers are not modified and MODOPT = 1 */
FI;
IF RFBM[2] = 1 AND XINUSE[2] = 1
THEN store AVX state into extended region of XSAVE area;
/* might avoid saving if AVX state is not modified and MODOPT = 1 */
FI;
IF RFBM[1] = 1 or RFBM[2] = 1
THEN store MXCSR and MXCSR_MASK into legacy region of XSAVE area;
FI;
XSTATE_BV field in XSAVE header ← (OLD_BV AND ~RFBM) OR (XINUSE AND RFBM);
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XSAVEOPT:
void _xsaveopt( void * , unsigned __int64);
XSAVEOPT:
void _xsaveopt64( void * , unsigned __int64);
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] =
0.
If CR4.OSXSAVE[bit 18] = 0.
If the LOCK prefix is used.
If 66H, F3H or F2H prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
XSAVEOPT—Save Processor Extended States Optimized
Vol. 2C 5-617
INSTRUCTION SET REFERENCE, V-Z
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] =
0.
If CR4.OSXSAVE[bit 18] = 0.
If the LOCK prefix is used.
If 66H, F3H or F2H prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] =
0.
If CR4.OSXSAVE[bit 18] = 0.
If the LOCK prefix is used.
If 66H, F3H or F2H prefix is used.
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XSAVEOPT—Save Processor Extended States Optimized
INSTRUCTION SET REFERENCE, V-Z
XSAVES—Save Processor Extended States Supervisor
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F C7 /5
XSAVES mem
M
Valid
Valid
Save state components specified by EDX:EAX
to mem with compaction, optimizing if
possible.
REX.W+ 0F C7 /5
XSAVES64 mem
M
Valid
N.E.
Save state components specified by EDX:EAX
to mem with compaction, optimizing if
possible.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Performs a full or partial save of processor state components to the XSAVE area located at the memory address
specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), the logicalAND of EDX:EAX and the logical-OR of XCR0 with the IA32_XSS MSR. XSAVES may be executed only if CPL = 0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Section 13.11, “Operation of XSAVES,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
1 provides a detailed description of the operation of the XSAVES instruction. The following items provide a highlevel outline:
•
Execution of XSAVES is similar to that of XSAVEC. XSAVES differs from XSAVEC in that it can save state
components corresponding to bits set in the IA32_XSS MSR and that it may use the modified optimization.
•
XSAVES saves state component i only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE is a bitmap by which the
processor tracks the status of various state components. See Section 13.6, “Processor Tracking of XSAVEManaged State.”) Even if both bits are 1, XSAVES may optimize and not save state component i if (1) state
component i has not been modified since the last execution of XRTOR or XRSTORS; and (2) this execution of
XSAVES correspond to that last execution of XRTOR or XRSTORS as determined by XRSTOR_INFO (see the
Operation section below).
•
XSAVES does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, “Legacy
Region of an XSAVE Area”).
•
XSAVES writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the XSAVE header.2 (See Section
13.4.2, “XSAVE Header.”) XSAVES sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to
RFBM[62:0]. XSAVES does not write to any parts of the XSAVE header other than the XSTATE_BV and
XCOMP_BV fields.
•
XSAVES always uses the compacted format of the extended region of the XSAVE area (see Section 13.4.3,
“Extended Region of an XSAVE Area”).
Use of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.
1. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not
have its initial value of 1F80H. In this case, the init optimization does not apply and XSAVEC will save SSE state as long as RFBM[1] =
1 and the modified optimization is not being applied.
2. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not
have its initial value of 1F80H. In this case, XSAVES sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.
XSAVES—Save Processor Extended States Supervisor
Vol. 2C 5-619
INSTRUCTION SET REFERENCE, V-Z
Operation
RFBM ← (XCR0 OR IA32_XSS) AND EDX:EAX;
/* bitwise logical OR and AND */
IF in VMX non-root operation
THEN VMXNR ← 1;
ELSE VMXNR ← 0;
FI;
LAXA ← linear address of XSAVE area;
COMPMASK ← RFBM OR 80000000_00000000H;
IF XRSTOR_INFO = CPL,VMXNR,LAXA,COMPMASK
THEN MODOPT ← 1;
ELSE MODOPT ← 0;
FI;
IF RFBM[0] = 1 and XINUSE[0] = 1
THEN store x87 state into legacy region of XSAVE area;
/* might avoid saving if x87 state is not modified and MODOPT = 1 */
FI;
IF RFBM[1] = 1 and (XINUSE[1] = 1 or MXCSR ≠ 1F80H)
THEN store SSE state into legacy region of XSAVE area;
/* might avoid saving if SSE state is not modified and MODOPT = 1 */
FI;
IF RFBM[2] = 1 AND XINUSE[2] = 1
THEN store AVX state into extended region of XSAVE area;
/* might avoid saving if AVX state is not modified and MODOPT = 1 */
FI;
XSTATE_BV field in XSAVE header ← XINUSE AND RFBM;1
XCOMP_BV field in XSAVE header ← COMPMASK;
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XSAVES:
void _xsaves( void * , unsigned __int64);
XSAVES64:
void _xsaves64( void * , unsigned __int64);
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
1. If MXCSR does not have its initial value of 1F80H, XSAVES sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1, regardless of the value
of XINUSE[1].
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INSTRUCTION SET REFERENCE, V-Z
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
Real-Address Mode Exceptions
#GP
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC
If this exception is disabled a general protection exception (#GP) is signaled if the memory
operand is not aligned on a 16-byte boundary, as described above. If the alignment check
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
vary with implementation, as follows. In all implementations where #AC is not signaled, a
general protection exception is signaled in its place. In addition, the width of the alignment
check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).
XSAVES—Save Processor Extended States Supervisor
Vol. 2C 5-621
INSTRUCTION SET REFERENCE, V-Z
XSETBV—Set Extended Control Register
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 01 D1
XSETBV
NP
Valid
Valid
Write the value in EDX:EAX to the XCR
specified by ECX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Writes the contents of registers EDX:EAX into the 64-bit extended control register (XCR) specified in the ECX
register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The
contents of the EDX register are copied to high-order 32 bits of the selected XCR and the contents of the EAX
register are copied to low-order 32 bits of the XCR. (On processors that support the Intel 64 architecture, the highorder 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an XCR should be set to values
previously read.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection
exception #GP(0) is generated. Specifying a reserved or unimplemented XCR in ECX will also cause a general
protection exception. The processor will also generate a general protection exception if software attempts to write
to reserved bits in an XCR.
Currently, only XCR0 is supported. Thus, all other values of ECX are reserved and will cause a #GP(0). Note that
bit 0 of XCR0 (corresponding to x87 state) must be set to 1; the instruction will cause a #GP(0) if an attempt is
made to clear this bit. In addition, the instruction causes a #GP(0) if an attempt is made to set XCR0[2] (AVX state)
while clearing XCR0[1] (SSE state); it is necessary to set both bits to use AVX instructions; Section 13.3, “Enabling
the XSAVE Feature Set and XSAVE-Enabled Features,” of Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1.
Operation
XCR[ECX] ← EDX:EAX;
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
XSETBV:
void _xsetbv( unsigned int, unsigned __int64);
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If an invalid XCR is specified in ECX.
If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.
If an attempt is made to clear bit 0 of XCR0.
If an attempt is made to set XCR0[2:1] to 10b.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If the LOCK prefix is used.
If 66H, F3H or F2H prefix is used.
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XSETBV—Set Extended Control Register
INSTRUCTION SET REFERENCE, V-Z
Real-Address Mode Exceptions
#GP
If an invalid XCR is specified in ECX.
If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.
If an attempt is made to clear bit 0 of XCR0.
If an attempt is made to set XCR0[2:1] to 10b.
#UD
If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.
If the LOCK prefix is used.
If 66H, F3H or F2H prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
The XSETBV instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
XSETBV—Set Extended Control Register
Vol. 2C 5-623
INSTRUCTION SET REFERENCE, V-Z
XTEST — Test If In Transactional Execution
Opcode/Instruction
Op/
En
0F 01 D6
XTEST
A
64/32bit
Mode
Support
V/V
CPUID
Feature
Flag
HLE or
RTM
Description
Test if executing in a transactional region
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
A
NA
NA
NA
NA
Description
The XTEST instruction queries the transactional execution status. If the instruction executes inside a transactionally executing RTM region or a transactionally executing HLE region, then the ZF flag is cleared, else it is set.
Operation
XTEST
IF (RTM_ACTIVE = 1 OR HLE_ACTIVE = 1)
THEN
ZF ← 0
ELSE
ZF ← 1
FI;
Flags Affected
The ZF flag is cleared if the instruction is executed transactionally; otherwise it is set to 1. The CF, OF, SF, PF, and
AF, flags are cleared.
Intel C/C++ Compiler Intrinsic Equivalent
XTEST:
int _xtest( void );
SIMD Floating-Point Exceptions
None
Other Exceptions
#UD
CPUID.(EAX=7, ECX=0):HLE[bit 4] = 0 and CPUID.(EAX=7, ECX=0):RTM[bit 11] = 0.
If LOCK or 66H or F2H or F3H prefix is used.
5-624 Vol. 2C
XTEST — Test If In Transactional Execution
CHAPTER 6
SAFER MODE EXTENSIONS REFERENCE
6.1
OVERVIEW
This chapter describes the Safer Mode Extensions (SMX) for the Intel 64 and IA-32 architectures. Safer Mode
Extensions (SMX) provide a programming interface for system software to establish a measured environment
within the platform to support trust decisions by end users. The measured environment includes:
•
Measured launch of a system executive, referred to as a Measured Launched Environment (MLE)1. The system
executive may be based on a Virtual Machine Monitor (VMM), a measured VMM is referred to as MVMM2.
•
•
Mechanisms to ensure the above measurement is protected and stored in a secure location in the platform.
Protection mechanisms that allow the VMM to control attempts to modify the VMM.
The measurement and protection mechanisms used by a measured environment are supported by the capabilities
of an Intel® Trusted Execution Technology (Intel® TXT) platform:
•
•
•
The SMX are the processor’s programming interface in an Intel TXT platform.
The chipset in an Intel TXT platform provides enforcement of the protection mechanisms.
Trusted Platform Module (TPM) 1.2 in the platform provides platform configuration registers (PCRs) to store
software measurement values.
6.2
SMX FUNCTIONALITY
SMX functionality is provided in an Intel 64 processor through the GETSEC instruction via leaf functions. The
GETSEC instruction supports multiple leaf functions. Leaf functions are selected by the value in EAX at the time
GETSEC is executed. Each GETSEC leaf function is documented separately in the reference pages with a unique
mnemonic (even though these mnemonics share the same opcode, 0F 37).
6.2.1
Detecting and Enabling SMX
Software can detect support for SMX operation using the CPUID instruction. If software executes CPUID with 1 in
EAX, a value of 1 in bit 6 of ECX indicates support for SMX operation (GETSEC is available), see CPUID instruction
for the layout of feature flags of reported by CPUID.01H:ECX.
System software enables SMX operation by setting CR4.SMXE[Bit 14] = 1 before attempting to execute GETSEC.
Otherwise, execution of GETSEC results in the processor signaling an invalid opcode exception (#UD).
If the CPUID SMX feature flag is clear (CPUID.01H.ECX[Bit 6] = 0), attempting to set CR4.SMXE[Bit 14] results in
a general protection exception.
The IA32_FEATURE_CONTROL MSR (at address 03AH) provides feature control bits that configure operation of
VMX and SMX. These bits are documented in Table 6-1.
1. See Intel® Trusted Execution Technology Measured Launched Environment Programming Guide.
2. An MVMM is sometimes referred to as a measured launched environment (MLE). See Intel® Trusted Execution Technology Measured
Launched Environment Programming Guide
Vol. 2D 6-1
SAFER MODE EXTENSIONS REFERENCE
Table 6-1. Layout of IA32_FEATURE_CONTROL
Bit Position
Description
0
Lock bit (0 = unlocked, 1 = locked). When set to '1' further writes to this MSR are blocked.
1
Enable VMX in SMX operation.
2
Enable VMX outside SMX operation.
7:3
Reserved
14:8
SENTER Local Function Enables: When set, each bit in the field represents an enable control for a corresponding
SENTER function.
15
SENTER Global Enable: Must be set to ‘1’ to enable operation of GETSEC[SENTER].
63:16
Reserved
•
Bit 0 is a lock bit. If the lock bit is clear, an attempt to execute VMXON will cause a general-protection exception.
Attempting to execute GETSEC[SENTER] when the lock bit is clear will also cause a general-protection
exception. If the lock bit is set, WRMSR to the IA32_FEATURE_CONTROL MSR will cause a general-protection
exception. Once the lock bit is set, the MSR cannot be modified until a power-on reset. System BIOS can use
this bit to provide a setup option for BIOS to disable support for VMX, SMX or both VMX and SMX.
•
Bit 1 enables VMX in SMX operation (between executing the SENTER and SEXIT leaves of GETSEC). If this bit is
clear, an attempt to execute VMXON in SMX will cause a general-protection exception if executed in SMX
operation. Attempts to set this bit on logical processors that do not support both VMX operation (Chapter 6,
“Safer Mode Extensions Reference”) and SMX operation cause general-protection exceptions.
•
Bit 2 enables VMX outside SMX operation. If this bit is clear, an attempt to execute VMXON will cause a generalprotection exception if executed outside SMX operation. Attempts to set this bit on logical processors that do
not support VMX operation cause general-protection exceptions.
•
Bits 8 through 14 specify enabled functionality of the SENTER leaf function. Each bit in the field represents an
enable control for a corresponding SENTER function. Only enabled SENTER leaf functionality can be used when
executing SENTER.
•
Bits 15 specify global enable of all SENTER functionalities.
6.2.2
SMX Instruction Summary
System software must first query for available GETSEC leaf functions by executing GETSEC[CAPABILITIES]. The
CAPABILITIES leaf function returns a bit map of available GETSEC leaves. An attempt to execute an unsupported
leaf index results in an undefined opcode (#UD) exception.
6.2.2.1
GETSEC[CAPABILITIES]
The SMX functionality provides an architectural interface for newer processor generations to extend SMX capabilities. Specifically, the GETSEC instruction provides a capability leaf function for system software to discover the
available GETSEC leaf functions that are supported in a processor. Table 6-2 lists the currently available GETSEC
leaf functions.
6-2 Vol. 2D
SAFER MODE EXTENSIONS REFERENCE
.
Table 6-2. GETSEC Leaf Functions
Index (EAX)
Leaf function
Description
0
CAPABILITIES
Returns the available leaf functions of the GETSEC instruction.
1
Undefined
Reserved
2
ENTERACCS
Enter
3
EXITAC
Exit
4
SENTER
Launch an MLE.
5
SEXIT
Exit the MLE.
6
PARAMETERS
Return SMX related parameter information.
7
SMCTRL
SMX mode control.
8
WAKEUP
Wake up sleeping processors in safer mode.
9 - (4G-1)
Undefined
Reserved
6.2.2.2
GETSEC[ENTERACCS]
The GETSEC[ENTERACCS] leaf enables authenticated code execution mode. The ENTERACCS leaf function
performs an authenticated code module load using the chipset public key as the signature verification. ENTERACCS
requires the existence of an Intel® Trusted Execution Technology capable chipset since it unlocks the chipset
private configuration register space after successful authentication of the loaded module. The physical base
address and size of the authenticated code module are specified as input register values in EBX and ECX, respectively.
While in the authenticated code execution mode, certain processor state properties change. For this reason, the
time in which the processor operates in authenticated code execution mode should be limited to minimize impact
on external system events.
Upon entry into , the previous paging context is disabled (since the authenticated code module image is specified
with physical addresses and can no longer rely upon external memory-based page-table structures).
Prior to executing the GETSEC[ENTERACCS] leaf, system software must ensure the logical processor issuing
GETSEC[ENTERACCS] is the boot-strap processor (BSP), as indicated by IA32_APIC_BASE.BSP = 1. System software must ensure other logical processors are in a suitable idle state and not marked as BSP.
The GETSEC[ENTERACCS] leaf may be used by different agents to load different authenticated code modules to
perform functions related to different aspects of a measured environment, for example system software and
Intel® TXT enabled BIOS may use more than one authenticated code modules.
6.2.2.3
GETSEC[EXITAC]
GETSEC[EXITAC] takes the processor out of . When this instruction leaf is executed, the contents of the authenticated code execution area are scrubbed and control is transferred to the non-authenticated context defined by a
near pointer passed with the GETSEC[EXITAC] instruction.
The authenticated code execution area is no longer accessible after completion of GETSEC[EXITAC]. RBX (or EBX)
holds the address of the near absolute indirect target to be taken.
6.2.2.4
GETSEC[SENTER]
The GETSEC[SENTER] leaf function is used by the initiating logical processor (ILP) to launch an MLE.
GETSEC[SENTER] can be considered a superset of the ENTERACCS leaf, because it enters as part of the measured
environment launch.
Measured environment startup consists of the following steps:
Vol. 2D 6-3
SAFER MODE EXTENSIONS REFERENCE
•
the ILP rendezvous the responding logical processors (RLPs) in the platform into a controlled state (At the
completion of this handshake, all the RLPs except for the ILP initiating the measured environment launch are
placed in a newly defined SENTER sleep state).
•
Load and authenticate the authenticated code module required by the measured environment, and enter
authenticated code execution mode.
•
•
•
Verify and lock certain system configuration parameters.
Measure the dynamic root of trust and store into the PCRs in TPM.
Transfer control to the MLE with interrupts disabled.
Prior to executing the GETSEC[SENTER] leaf, system software must ensure the platform’s TPM is ready for access
and the ILP is the boot-strap processor (BSP), as indicated by IA32_APIC_BASE.BSP. System software must ensure
other logical processors (RLPs) are in a suitable idle state and not marked as BSP.
System software launching a measurement environment is responsible for providing a proper authenticate code
module address when executing GETSEC[SENTER]. The AC module responsible for the launch of a measured environment and loaded by GETSEC[SENTER] is referred to as SINIT. See Intel® Trusted Execution Technology
Measured Launched Environment Programming Guide for additional information on system software requirements
prior to executing GETSEC[SENTER].
6.2.2.5
GETSEC[SEXIT]
System software exits the measured environment by executing the instruction GETSEC[SEXIT] on the ILP. This
instruction rendezvous the responding logical processors in the platform for exiting from the measured environment. External events (if left masked) are unmasked and Intel® TXT-capable chipset’s private configuration space
is re-locked.
6.2.2.6
GETSEC[PARAMETERS]
The GETSEC[PARAMETERS] leaf function is used to report attributes, options and limitations of SMX operation.
Software uses this leaf to identify operating limits or additional options.
The information reported by GETSEC[PARAMETERS] may require executing the leaf multiple times using EBX as an
index. If the GETSEC[PARAMETERS] instruction leaf or if a specific parameter field is not available, then SMX operation should be interpreted to use the default limits of respective GETSEC leaves or parameter fields defined in the
GETSEC[PARAMETERS] leaf.
6.2.2.7
GETSEC[SMCTRL]
The GETSEC[SMCTRL] leaf function is used for providing additional control over specific conditions associated with
the SMX architecture. An input register is supported for selecting the control operation to be performed. See the
specific leaf description for details on the type of control provided.
6.2.2.8
GETSEC[WAKEUP]
Responding logical processors (RLPs) are placed in the SENTER sleep state after the initiating logical processor
executes GETSEC[SENTER]. The ILP can wake up RLPs to join the measured environment by using
GETSEC[WAKEUP]. When the RLPs in SENTER sleep state wake up, these logical processors begin execution at the
entry point defined in a data structure held in system memory (pointed to by an chipset register LT.MLE.JOIN) in
TXT configuration space.
6.2.3
Measured Environment and SMX
This section gives a simplified view of a representative life cycle of a measured environment that is launched by a
system executive using SMX leaf functions. Intel® Trusted Execution Technology Measured Launched Environment
Programming Guide provides more detailed examples of using SMX and chipset resources (including chipset registers, Trusted Platform Module) to launch an MVMM.
6-4 Vol. 2D
SAFER MODE EXTENSIONS REFERENCE
The life cycle starts with the system executive (an OS, an OS loader, and so forth) loading the MLE and SINIT AC
module into available system memory. The system executive must validate and prepare the platform for the
measured launch. When the platform is properly configured, the system executive executes GETSEC[SENTER] on
the initiating logical processor (ILP) to rendezvous the responding logical processors into an SENTER sleep state,
the ILP then enters into using the SINIT AC module. In a multi-threaded or multi-processing environment, the
system executive must ensure that other logical processors are already in an idle loop, or asleep (such as after
executing HLT) before executing GETSEC[SENTER].
After the GETSEC[SENTER] rendezvous handshake is performed between all logical processors in the platform, the
ILP loads the chipset authenticated code module (SINIT) and performs an authentication check. If the check
passes, the processor hashes the SINIT AC module and stores the result into TPM PCR 17. It then switches execution context to the SINIT AC module. The SINIT AC module will perform a number of platform operations,
including: verifying the system configuration, protecting the system memory used by the MLE from I/O devices
capable of DMA, producing a hash of the MLE, storing the hash value in TPM PCR 18, and various other operations.
When SINIT completes execution, it executes the GETSEC[EXITAC] instruction and transfers control the MLE at the
designated entry point.
Upon receiving control from the SINIT AC module, the MLE must establish its protection and isolation controls
before enabling DMA and interrupts and transferring control to other software modules. It must also wakeup the
RLPs from their SENTER sleep state using the GETSEC[WAKEUP] instruction and bring them into its protection and
isolation environment.
While executing in a measured environment, the MVMM can access the Trusted Platform Module (TPM) in locality 2.
The MVMM has complete access to all TPM commands and may use the TPM to report current measurement values
or use the measurement values to protect information such that only when the platform configuration registers
(PCRs) contain the same value is the information released from the TPM. This protection mechanism is known as
sealing.
A measured environment shutdown is ultimately completed by executing GETSEC[SEXIT]. Prior to this step system
software is responsible for scrubbing sensitive information left in the processor caches, system memory.
6.3
GETSEC LEAF FUNCTIONS
This section provides detailed descriptions of each leaf function of the GETSEC instruction. GETSEC is available only
if CPUID.01H:ECX[Bit 6] = 1. This indicates the availability of SMX and the GETSEC instruction. Before GETSEC can
be executed, SMX must be enabled by setting CR4.SMXE[Bit 14] = 1.
A GETSEC leaf can only be used if it is shown to be available as reported by the GETSEC[CAPABILITIES] function.
Attempts to access a GETSEC leaf index not supported by the processor, or if CR4.SMXE is 0, results in the signaling
of an undefined opcode exception.
All GETSEC leaf functions are available in protected mode, including the compatibility sub-mode of IA-32e mode
and the 64-bit sub-mode of IA-32e mode. Unless otherwise noted, the behavior of all GETSEC functions and interactions related to the measured environment are independent of IA-32e mode. This also applies to the interpretation of register widths1 passed as input parameters to GETSEC functions and to register results returned as output
parameters.
The GETSEC functions ENTERACCS, SENTER, SEXIT, and WAKEUP require a Intel® TXT capable-chipset to be
present in the platform. The GETSEC[CAPABILITIES] returned bit vector in position 0 indicates an Intel® TXTcapable chipset has been sampled present2 by the processor.
The processor's operating mode also affects the execution of the following GETSEC leaf functions: SMCTRL, ENTERACCS, EXITAC, SENTER, SEXIT, and WAKEUP. These functions are only allowed in protected mode at CPL = 0. They
1.
This chapter uses the 64-bit notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because processors that support SMX also
support Intel 64 Architecture. The MVMM can be launched in IA-32e mode or outside IA-32e mode. The 64-bit notation of processor
registers also refer to its 32-bit forms if SMX is used in 32-bit environment. In some places, notation such as EAX is used to refer
specifically to lower 32 bits of the indicated register
2. Sampled present means that the processor sent a message to the chipset and the chipset responded that it (a) knows about the
message and (b) is capable of executing SENTER. This means that the chipset CAN support Intel® TXT, and is configured and WILLING
to support it.
Vol. 2D 6-5
SAFER MODE EXTENSIONS REFERENCE
are not allowed while in SMM in order to prevent potential intra-mode conflicts. Further execution qualifications
exist to prevent potential architectural conflicts (for example: nesting of the measured environment or authenticated code execution mode). See the definitions of the GETSEC leaf functions for specific requirements.
For the purpose of performance monitor counting, the execution of GETSEC functions is counted as a single instruction with respect to retired instructions. The response by a responding logical processor (RLP) to messages associated with GETSEC[SENTER] or GTSEC[SEXIT] is transparent to the retired instruction count on the ILP.
6-6 Vol. 2D
SAFER MODE EXTENSIONS REFERENCE
GETSEC[CAPABILITIES] - Report the SMX Capabilities
Opcode
Instruction
0F 37
GETSEC[CAPABILITIES] Report the SMX capabilities.
Description
(EAX = 0)
The capabilities index is input in EBX with the result returned in EAX.
Description
The GETSEC[CAPABILITIES] function returns a bit vector of supported GETSEC leaf functions. The CAPABILITIES
leaf of GETSEC is selected with EAX set to 0 at entry. EBX is used as the selector for returning the bit vector field in
EAX. GETSEC[CAPABILITIES] may be executed at all privilege levels, but the CR4.SMXE bit must be set or an undefined opcode exception (#UD) is returned.
With EBX = 0 upon execution of GETSEC[CAPABILITIES], EAX returns the a bit vector representing status on the
presence of a Intel® TXT-capable chipset and the first 30 available GETSEC leaf functions. The format of the
returned bit vector is provided in Table 6-3.
If bit 0 is set to 1, then an Intel® TXT-capable chipset has been sampled present by the processor. If bits in the
range of 1-30 are set, then the corresponding GETSEC leaf function is available. If the bit value at a given bit index
is 0, then the GETSEC leaf function corresponding to that index is unsupported and attempted execution results in
a #UD.
Bit 31 of EAX indicates if further leaf indexes are supported. If the Extended Leafs bit 31 is set, then additional leaf
functions are accessed by repeating GETSEC[CAPABILITIES] with EBX incremented by one. When the most significant bit of EAX is not set, then additional GETSEC leaf functions are not supported; indexing EBX to a higher value
results in EAX returning zero.
Table 6-3. Getsec Capability Result Encoding (EBX = 0)
Field
Bit position
Description
Chipset Present
0
Intel® TXT-capable chipset is present.
Undefined
1
Reserved
ENTERACCS
2
GETSEC[ENTERACCS] is available.
EXITAC
3
GETSEC[EXITAC] is available.
SENTER
4
GETSEC[SENTER] is available.
SEXIT
5
GETSEC[SEXIT] is available.
PARAMETERS
6
GETSEC[PARAMETERS] is available.
SMCTRL
7
GETSEC[SMCTRL] is available.
WAKEUP
8
GETSEC[WAKEUP] is available.
Undefined
30:9
Reserved
Extended Leafs
31
Reserved for extended information reporting of GETSEC capabilities.
GETSEC[CAPABILITIES] - Report the SMX Capabilities
Vol. 2D 6-7
SAFER MODE EXTENSIONS REFERENCE
Operation
IF (CR4.SMXE=0)
THEN #UD;
ELSIF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
IF (EBX=0) THEN
BitVector← 0;
IF (TXT chipset present)
BitVector[Chipset present]← 1;
IF (ENTERACCS Available)
THEN BitVector[ENTERACCS]← 1;
IF (EXITAC Available)
THEN BitVector[EXITAC]← 1;
IF (SENTER Available)
THEN BitVector[SENTER]← 1;
IF (SEXIT Available)
THEN BitVector[SEXIT]← 1;
IF (PARAMETERS Available)
THEN BitVector[PARAMETERS]← 1;
IF (SMCTRL Available)
THEN BitVector[SMCTRL]← 1;
IF (WAKEUP Available)
THEN BitVector[WAKEUP]← 1;
EAX← BitVector;
ELSE
EAX← 0;
END;;
Flags Affected
None
Use of Prefixes
LOCK
Causes #UD
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ)
Operand size
Causes #UD
Segment overrides Ignored
Address size
Ignored
REX
Ignored
Protected Mode Exceptions
#UD
IF CR4.SMXE = 0.
Real-Address Mode Exceptions
#UD
IF CR4.SMXE = 0.
Virtual-8086 Mode Exceptions
#UD
IF CR4.SMXE = 0.
Compatibility Mode Exceptions
#UD
6-8 Vol. 2D
IF CR4.SMXE = 0.
GETSEC[CAPABILITIES] - Report the SMX Capabilities
SAFER MODE EXTENSIONS REFERENCE
64-Bit Mode Exceptions
#UD
IF CR4.SMXE = 0.
VM-exit Condition
Reason (GETSEC)
IF in VMX non-root operation.
GETSEC[CAPABILITIES] - Report the SMX Capabilities
Vol. 2D 6-9
SAFER MODE EXTENSIONS REFERENCE
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
Opcode
Instruction
0F 37
GETSEC[ENTERACCS] Enter authenticated code execution mode.
(EAX = 2)
Description
EBX holds the authenticated code module physical base address. ECX holds the authenticated
code module size (bytes).
Description
The GETSEC[ENTERACCS] function loads, authenticates and executes an authenticated code module using an
Intel® TXT platform chipset's public key. The ENTERACCS leaf of GETSEC is selected with EAX set to 2 at entry.
There are certain restrictions enforced by the processor for the execution of the GETSEC[ENTERACCS] instruction:
•
Execution is not allowed unless the processor is in protected mode or IA-32e mode with CPL = 0 and
EFLAGS.VM = 0.
•
•
Processor cache must be available and not disabled, that is, CR0.CD and CR0.NW bits must be 0.
•
For enforcing consistency of operation with numeric exception reporting using Interrupt 16, CR0.NE must be
set.
•
An Intel TXT-capable chipset must be present as communicated to the processor by sampling of the power-on
configuration capability field after reset.
•
The processor can not already be in authenticated code execution mode as launched by a previous
GETSEC[ENTERACCS] or GETSEC[SENTER] instruction without a subsequent exiting using GETSEC[EXITAC]).
•
To avoid potential operability conflicts between modes, the processor is not allowed to execute this instruction
if it currently is in SMM or VMX operation.
•
To insure consistent handling of SIPI messages, the processor executing the GETSEC[ENTERACCS] instruction
must also be designated the BSP (boot-strap processor) as defined by IA32_APIC_BASE.BSP (Bit 8).
For processor packages containing more than one logical processor, CR0.CD is checked to ensure consistency
between enabled logical processors.
Failure to conform to the above conditions results in the processor signaling a general protection exception.
Prior to execution of the ENTERACCS leaf, other logical processors, i.e., RLPs, in the platform must be:
•
Idle in a wait-for-SIPI state (as initiated by an INIT assertion or through reset for non-BSP designated
processors), or
•
In the SENTER sleep state as initiated by a GETSEC[SENTER] from the initiating logical processor (ILP).
If other logical processor(s) in the same package are not idle in one of these states, execution of ENTERACCS
signals a general protection exception. The same requirement and action applies if the other logical processor(s) of
the same package do not have CR0.CD = 0.
A successful execution of ENTERACCS results in the ILP entering an authenticated code execution mode. Prior to
reaching this point, the processor performs several checks. These include:
•
Establish and check the location and size of the specified authenticated code module to be executed by the
processor.
•
•
•
•
Inhibit the ILP’s response to the external events: INIT, A20M, NMI and SMI.
•
•
Authenticate the authenticated code module.
•
Unlock the Intel® TXT-capable chipset private configuration space and TPM locality 3 space.
Broadcast a message to enable protection of memory and I/O from other processor agents.
Load the designated code module into an authenticated code execution area.
Isolate the contents of the authenticated code execution area from further state modification by external
agents.
Initialize the initiating logical processor state based on information contained in the authenticated code module
header.
6-10 Vol. 2D
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
SAFER MODE EXTENSIONS REFERENCE
•
Begin execution in the authenticated code module at the defined entry point.
The GETSEC[ENTERACCS] function requires two additional input parameters in the general purpose registers EBX
and ECX. EBX holds the authenticated code (AC) module physical base address (the AC module must reside below
4 GBytes in physical address space) and ECX holds the AC module size (in bytes). The physical base address and
size are used to retrieve the code module from system memory and load it into the internal authenticated code
execution area. The base physical address is checked to verify it is on a modulo-4096 byte boundary. The size is
verified to be a multiple of 64, that it does not exceed the internal authenticated code execution area capacity (as
reported by GETSEC[CAPABILITIES]), and that the top address of the AC module does not exceed 32 bits. An error
condition results in an abort of the authenticated code execution launch and the signaling of a general protection
exception.
As an integrity check for proper processor hardware operation, execution of GETSEC[ENTERACCS] will also check
the contents of all the machine check status registers (as reported by the MSRs IA32_MCi_STATUS) for any valid
uncorrectable error condition. In addition, the global machine check status register IA32_MCG_STATUS MCIP bit
must be cleared and the IERR processor package pin (or its equivalent) must not be asserted, indicating that no
machine check exception processing is currently in progress. These checks are performed prior to initiating the
load of the authenticated code module. Any outstanding valid uncorrectable machine check error condition present
in these status registers at this point will result in the processor signaling a general protection violation.
The ILP masks the response to the assertion of the external signals INIT#, A20M, NMI#, and SMI#. This masking
remains active until optionally unmasked by GETSEC[EXITAC] (this defined unmasking behavior assumes
GETSEC[ENTERACCS] was not executed by a prior GETSEC[SENTER]). The purpose of this masking control is to
prevent exposure to existing external event handlers that may not be under the control of the authenticated code
module.
The ILP sets an internal flag to indicate it has entered authenticated code execution mode. The state of the A20M
pin is likewise masked and forced internally to a de-asserted state so that any external assertion is not recognized
during authenticated code execution mode.
To prevent other (logical) processors from interfering with the ILP operating in authenticated code execution mode,
memory (excluding implicit write-back transactions) access and I/O originating from other processor agents are
blocked. This protection starts when the ILP enters into authenticated code execution mode. Only memory and I/O
transactions initiated from the ILP are allowed to proceed. Exiting authenticated code execution mode is done by
executing GETSEC[EXITAC]. The protection of memory and I/O activities remains in effect until the ILP executes
GETSEC[EXITAC].
Prior to launching the authenticated execution module using GETSEC[ENTERACCS] or GETSEC[SENTER], the
processor’s MTRRs (Memory Type Range Registers) must first be initialized to map out the authenticated RAM
addresses as WB (writeback). Failure to do so may affect the ability for the processor to maintain isolation of the
loaded authenticated code module. If the processor detected this requirement is not met, it will signal an Intel®
TXT reset condition with an error code during the loading of the authenticated code module.
While physical addresses within the load module must be mapped as WB, the memory type for locations outside of
the module boundaries must be mapped to one of the supported memory types as returned by GETSEC[PARAMETERS] (or UC as default).
To conform to the minimum granularity of MTRR MSRs for specifying the memory type, authenticated code RAM
(ACRAM) is allocated to the processor in 4096 byte granular blocks. If an AC module size as specified in ECX is not
a multiple of 4096 then the processor will allocate up to the next 4096 byte boundary for mapping as ACRAM with
indeterminate data. This pad area will not be visible to the authenticated code module as external memory nor can
it depend on the value of the data used to fill the pad area.
At the successful completion of GETSEC[ENTERACCS], the architectural state of the processor is partially initialized
from contents held in the header of the authenticated code module. The processor GDTR, CS, and DS selectors are
initialized from fields within the authenticated code module. Since the authenticated code module must be relocatable, all address references must be relative to the authenticated code module base address in EBX. The processor
GDTR base value is initialized to the AC module header field GDTBasePtr + module base address held in EBX and
the GDTR limit is set to the value in the GDTLimit field. The CS selector is initialized to the AC module header
SegSel field, while the DS selector is initialized to CS + 8. The segment descriptor fields are implicitly initialized to
BASE=0, LIMIT=FFFFFh, G=1, D=1, P=1, S=1, read/write access for DS, and execute/read access for CS. The
processor begins the authenticated code module execution with the EIP set to the AC module header EntryPoint
field + module base address (EBX). The AC module based fields used for initializing the processor state are checked
for consistency and any failure results in a shutdown condition.
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
Vol. 2D 6-11
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A summary of the register state initialization after successful completion of GETSEC[ENTERACCS] is given for the
processor in Table 6-4. The paging is disabled upon entry into authenticated code execution mode. The authenticated code module is loaded and initially executed using physical addresses. It is up to the system software after
execution of GETSEC[ENTERACCS] to establish a new (or restore its previous) paging environment with an appropriate mapping to meet new protection requirements. EBP is initialized to the authenticated code module base
physical address for initial execution in the authenticated environment. As a result, the authenticated code can
reference EBP for relative address based references, given that the authenticated code module must be position
independent.
Table 6-4. Register State Initialization after GETSEC[ENTERACCS]
Register State
Initialization Status
Comment
CR0
PG←0, AM←0, WP←0: Others unchanged
Paging, Alignment Check, Write-protection are
disabled.
CR4
MCE←0: Others unchanged
Machine Check Exceptions disabled.
EFLAGS
00000002H
IA32_EFER
0H
IA-32e mode disabled.
EIP
AC.base + EntryPoint
AC.base is in EBX as input to GETSEC[ENTERACCS].
[E|R]BX
Pre-ENTERACCS state: Next [E|R]IP prior to
GETSEC[ENTERACCS]
Carry forward 64-bit processor state across
GETSEC[ENTERACCS].
ECX
Pre-ENTERACCS state: [31:16]=GDTR.limit;
[15:0]=CS.sel
Carry forward processor state across
GETSEC[ENTERACCS].
[E|R]DX
Pre-ENTERACCS state:
GDTR base
Carry forward 64-bit processor state across
GETSEC[ENTERACCS].
EBP
AC.base
CS
Sel=[SegSel], base=0, limit=FFFFFh, G=1, D=1,
AR=9BH
DS
Sel=[SegSel] +8, base=0, limit=FFFFFh, G=1, D=1,
AR=93H
GDTR
Base= AC.base (EBX) + [GDTBasePtr],
Limit=[GDTLimit]
DR7
00000400H
IA32_DEBUGCTL
0H
IA32_MISC_ENABLE
See Table 6-5 for example.
The number of initialized fields may change due to
processor implementation.
The segmentation related processor state that has not been initialized by GETSEC[ENTERACCS] requires appropriate initialization before use. Since a new GDT context has been established, the previous state of the segment
selector values held in ES, SS, FS, GS, TR, and LDTR might not be valid.
The MSR IA32_EFER is also unconditionally cleared as part of the processor state initialized by ENTERACCS. Since
paging is disabled upon entering authenticated code execution mode, a new paging environment will have to be
reestablished in order to establish IA-32e mode while operating in authenticated code execution mode.
Debug exception and trap related signaling is also disabled as part of GETSEC[ENTERACCS]. This is achieved by
resetting DR7, TF in EFLAGs, and the MSR IA32_DEBUGCTL. These debug functions are free to be re-enabled once
supporting exception handler(s), descriptor tables, and debug registers have been properly initialized following
6-12 Vol. 2D
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
SAFER MODE EXTENSIONS REFERENCE
entry into authenticated code execution mode. Also, any pending single-step trap condition will have been cleared
upon entry into this mode.
The IA32_MISC_ENABLE MSR is initialized upon entry into authenticated execution mode. Certain bits of this MSR
are preserved because preserving these bits may be important to maintain previously established platform settings
(See the footnote for Table 6-5.). The remaining bits are cleared for the purpose of establishing a more consistent
environment for the execution of authenticated code modules. One of the impacts of initializing this MSR is any
previous condition established by the MONITOR instruction will be cleared.
To support the possible return to the processor architectural state prior to execution of GETSEC[ENTERACCS],
certain critical processor state is captured and stored in the general- purpose registers at instruction completion.
[E|R]BX holds effective address ([E|R]IP) of the instruction that would execute next after GETSEC[ENTERACCS],
ECX[15:0] holds the CS selector value, ECX[31:16] holds the GDTR limit field, and [E|R]DX holds the GDTR base
field. The subsequent authenticated code can preserve the contents of these registers so that this state can be
manually restored if needed, prior to exiting authenticated code execution mode with GETSEC[EXITAC]. For the
processor state after exiting authenticated code execution mode, see the description of GETSEC[SEXIT].
Table 6-5. IA32_MISC_ENABLE MSR Initialization1 by ENTERACCS and SENTER
Field
Bit position
Description
Fast strings enable
0
Clear to 0.
FOPCODE compatibility mode
enable
2
Clear to 0.
Thermal monitor enable
3
Set to 1 if other thermal monitor capability is not enabled.2
Split-lock disable
4
Clear to 0.
Bus lock on cache line splits
disable
8
Clear to 0.
Hardware prefetch disable
9
Clear to 0.
GV1/2 legacy enable
15
Clear to 0.
MONITOR/MWAIT s/m enable
18
Clear to 0.
Adjacent sector prefetch disable
19
Clear to 0.
NOTES:
1. The number of IA32_MISC_ENABLE fields that are initialized may vary due to processor implementations.
2. ENTERACCS (and SENTER) initialize the state of processor thermal throttling such that at least a minimum level is enabled. If thermal
throttling is already enabled when executing one of these GETSEC leaves, then no change in the thermal throttling control settings
will occur. If thermal throttling is disabled, then it will be enabled via setting of the thermal throttle control bit 3 as a result of executing these GETSEC leaves.
The IDTR will also require reloading with a new IDT context after entering authenticated code execution mode,
before any exceptions or the external interrupts INTR and NMI can be handled. Since external interrupts are reenabled at the completion of authenticated code execution mode (as terminated with EXITAC), it is recommended
that a new IDT context be established before this point. Until such a new IDT context is established, the
programmer must take care in not executing an INT n instruction or any other operation that would result in an
exception or trap signaling.
Prior to completion of the GETSEC[ENTERACCS] instruction and after successful authentication of the AC module,
the private configuration space of the Intel TXT chipset is unlocked. The authenticated code module alone can gain
access to this normally restricted chipset state for the purpose of securing the platform.
Once the authenticated code module is launched at the completion of GETSEC[ENTERACCS], it is free to enable
interrupts by setting EFLAGS.IF and enable NMI by execution of IRET. This presumes that it has re-established
interrupt handling support through initialization of the IDT, GDT, and corresponding interrupt handling code.
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
Vol. 2D 6-13
SAFER MODE EXTENSIONS REFERENCE
Operation in a Uni-Processor Platform
(* The state of the internal flag ACMODEFLAG persists across instruction boundary *)
IF (CR4.SMXE=0)
THEN #UD;
ELSIF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSIF (GETSEC leaf unsupported)
THEN #UD;
ELSIF ((in VMX operation) or
(CR0.PE=0) or (CR0.CD=1) or (CR0.NW=1) or (CR0.NE=0) or
(CPL>0) or (EFLAGS.VM=1) or
(IA32_APIC_BASE.BSP=0) or
(TXT chipset not present) or
(ACMODEFLAG=1) or (IN_SMM=1))
THEN #GP(0);
IF (GETSEC[PARAMETERS].Parameter_Type = 5, MCA_Handling (bit 6) = 0)
FOR I = 0 to IA32_MCG_CAP.COUNT-1 DO
IF (IA32_MC[I]_STATUS = uncorrectable error)
THEN #GP(0);
OD;
FI;
IF (IA32_MCG_STATUS.MCIP=1) or (IERR pin is asserted)
THEN #GP(0);
ACBASE← EBX;
ACSIZE← ECX;
IF (((ACBASE MOD 4096) ≠ 0) or ((ACSIZE MOD 64 ) ≠ 0 ) or (ACSIZE < minimum module size) OR (ACSIZE > authenticated RAM
capacity)) or ((ACBASE+ACSIZE) > (2^32 -1)))
THEN #GP(0);
IF (secondary thread(s) CR0.CD = 1) or ((secondary thread(s) NOT(wait-for-SIPI)) and
(secondary thread(s) not in SENTER sleep state)
THEN #GP(0);
Mask SMI, INIT, A20M, and NMI external pin events;
IA32_MISC_ENABLE← (IA32_MISC_ENABLE & MASK_CONST*)
(* The hexadecimal value of MASK_CONST may vary due to processor implementations *)
A20M← 0;
IA32_DEBUGCTL← 0;
Invalidate processor TLB(s);
Drain Outgoing Transactions;
ACMODEFLAG← 1;
SignalTXTMessage(ProcessorHold);
Load the internal ACRAM based on the AC module size;
(* Ensure that all ACRAM loads hit Write Back memory space *)
IF (ACRAM memory type ≠ WB)
THEN TXT-SHUTDOWN(#BadACMMType);
IF (AC module header version isnot supported) OR (ACRAM[ModuleType] ≠ 2)
THEN TXT-SHUTDOWN(#UnsupportedACM);
(* Authenticate the AC Module and shutdown with an error if it fails *)
KEY← GETKEY(ACRAM, ACBASE);
KEYHASH← HASH(KEY);
CSKEYHASH← READ(TXT.PUBLIC.KEY);
IF (KEYHASH ≠ CSKEYHASH)
THEN TXT-SHUTDOWN(#AuthenticateFail);
SIGNATURE← DECRYPT(ACRAM, ACBASE, KEY);
(* The value of SIGNATURE_LEN_CONST is implementation-specific*)
6-14 Vol. 2D
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
SAFER MODE EXTENSIONS REFERENCE
FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
ACRAM[SCRATCH.I]← SIGNATURE[I];
COMPUTEDSIGNATURE← HASH(ACRAM, ACBASE, ACSIZE);
FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
ACRAM[SCRATCH.SIGNATURE_LEN_CONST+I]← COMPUTEDSIGNATURE[I];
IF (SIGNATURE ≠ COMPUTEDSIGNATURE)
THEN TXT-SHUTDOWN(#AuthenticateFail);
ACMCONTROL← ACRAM[CodeControl];
IF ((ACMCONTROL.0 = 0) and (ACMCONTROL.1 = 1) and (snoop hit to modified line detected on ACRAM load))
THEN TXT-SHUTDOWN(#UnexpectedHITM);
IF (ACMCONTROL reserved bits are set)
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACRAM[GDTBasePtr] < (ACRAM[HeaderLen] * 4 + Scratch_size)) OR
((ACRAM[GDTBasePtr] + ACRAM[GDTLimit]) >= ACSIZE))
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACMCONTROL.0 = 1) and (ACMCONTROL.1 = 1) and (snoop hit to modified line detected on ACRAM load))
THEN ACEntryPoint← ACBASE+ACRAM[ErrorEntryPoint];
ELSE
ACEntryPoint← ACBASE+ACRAM[EntryPoint];
IF ((ACEntryPoint >= ACSIZE) OR (ACEntryPoint < (ACRAM[HeaderLen] * 4 + Scratch_size)))THEN TXT-SHUTDOWN(#BadACMFormat);
IF (ACRAM[GDTLimit] & FFFF0000h)
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACRAM[SegSel] > (ACRAM[GDTLimit] - 15)) OR (ACRAM[SegSel] < 8))
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACRAM[SegSel].TI=1) OR (ACRAM[SegSel].RPL≠0))
THEN TXT-SHUTDOWN(#BadACMFormat);
CR0.[PG.AM.WP]← 0;
CR4.MCE← 0;
EFLAGS← 00000002h;
IA32_EFER← 0h;
[E|R]BX← [E|R]IP of the instruction after GETSEC[ENTERACCS];
ECX← Pre-GETSEC[ENTERACCS] GDT.limit:CS.sel;
[E|R]DX← Pre-GETSEC[ENTERACCS] GDT.base;
EBP← ACBASE;
GDTR.BASE← ACBASE+ACRAM[GDTBasePtr];
GDTR.LIMIT← ACRAM[GDTLimit];
CS.SEL← ACRAM[SegSel];
CS.BASE← 0;
CS.LIMIT← FFFFFh;
CS.G← 1;
CS.D← 1;
CS.AR← 9Bh;
DS.SEL← ACRAM[SegSel]+8;
DS.BASE← 0;
DS.LIMIT← FFFFFh;
DS.G← 1;
DS.D← 1;
DS.AR← 93h;
DR7← 00000400h;
IA32_DEBUGCTL← 0;
SignalTXTMsg(OpenPrivate);
SignalTXTMsg(OpenLocality3);
EIP← ACEntryPoint;
END;
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
Vol. 2D 6-15
SAFER MODE EXTENSIONS REFERENCE
Flags Affected
All flags are cleared.
Use of Prefixes
LOCK
Causes #UD.
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size
Causes #UD.
Segment overrides Ignored.
Address size
Ignored.
REX
Ignored.
Protected Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[ENTERACCS] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
If CR0.CD = 1 or CR0.NW = 1 or CR0.NE = 0 or CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.
If a Intel® TXT-capable chipset is not present.
If in VMX root operation.
If the initiating processor is not designated as the bootstrap processor via the MSR bit
IA32_APIC_BASE.BSP.
If the processor is already in authenticated code execution mode.
If the processor is in SMM.
If a valid uncorrectable machine check error is logged in IA32_MC[I]_STATUS.
If the authenticated code base is not on a 4096 byte boundary.
If the authenticated code size > processor internal authenticated code area capacity.
If the authenticated code size is not modulo 64.
If other enabled logical processor(s) of the same package CR0.CD = 1.
If other enabled logical processor(s) of the same package are not in the wait-for-SIPI or
SENTER sleep state.
Real-Address Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[ENTERACCS] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[ENTERACCS] is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[ENTERACCS] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[ENTERACCS] is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
All protected mode exceptions apply.
#GP
IF AC code module does not reside in physical address below 2^32 -1.
64-Bit Mode Exceptions
All protected mode exceptions apply.
#GP
6-16 Vol. 2D
IF AC code module does not reside in physical address below 2^32 -1.
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
SAFER MODE EXTENSIONS REFERENCE
VM-exit Condition
Reason (GETSEC)
IF in VMX non-root operation.
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
Vol. 2D 6-17
SAFER MODE EXTENSIONS REFERENCE
GETSEC[EXITAC]—Exit Authenticated Code Execution Mode
Opcode
Instruction
Description
0F 37
GETSEC[EXITAC]
Exit authenticated code execution mode.
(EAX=3)
RBX holds the Near Absolute Indirect jump target and EDX hold the exit parameter flags.
Description
The GETSEC[EXITAC] leaf function exits the ILP out of authenticated code execution mode established by
GETSEC[ENTERACCS] or GETSEC[SENTER]. The EXITAC leaf of GETSEC is selected with EAX set to 3 at entry. EBX
(or RBX, if in 64-bit mode) holds the near jump target offset for where the processor execution resumes upon
exiting authenticated code execution mode. EDX contains additional parameter control information. Currently only
an input value of 0 in EDX is supported. All other EDX settings are considered reserved and result in a general
protection violation.
GETSEC[EXITAC] can only be executed if the processor is in protected mode with CPL = 0 and EFLAGS.VM = 0. The
processor must also be in authenticated code execution mode. To avoid potential operability conflicts between
modes, the processor is not allowed to execute this instruction if it is in SMM or in VMX operation. A violation of
these conditions results in a general protection violation.
Upon completion of the GETSEC[EXITAC] operation, the processor unmasks responses to external event signals
INIT#, NMI#, and SMI#. This unmasking is performed conditionally, based on whether the authenticated code
execution mode was entered via execution of GETSEC[SENTER] or GETSEC[ENTERACCS]. If the processor is in
authenticated code execution mode due to the execution of GETSEC[SENTER], then these external event signals
will remain masked. In this case, A20M is kept disabled in the measured environment until the measured environment executes GETSEC[SEXIT]. INIT# is unconditionally unmasked by EXITAC. Note that any events that are
pending, but have been blocked while in authenticated code execution mode, will be recognized at the completion
of the GETSEC[EXITAC] instruction if the pin event is unmasked.
The intent of providing the ability to optionally leave the pin events SMI#, and NMI# masked is to support the
completion of a measured environment bring-up that makes use of VMX. In this envisioned security usage
scenario, these events will remain masked until an appropriate virtual machine has been established in order to
field servicing of these events in a safer manner. Details on when and how events are masked and unmasked in
VMX operation are described in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C. It
should be cautioned that if no VMX environment is to be activated following GETSEC[EXITAC], that these events
will remain masked until the measured environment is exited with GETSEC[SEXIT]. If this is not desired then the
GETSEC function SMCTRL(0) can be used for unmasking SMI# in this context. NMI# can be correspondingly
unmasked by execution of IRET.
A successful exit of the authenticated code execution mode requires the ILP to perform additional steps as outlined
below:
•
•
•
•
•
Invalidate the contents of the internal authenticated code execution area.
•
Perform a near absolute indirect jump to the designated instruction location.
Invalidate processor TLBs.
Clear the internal processor AC Mode indicator flag.
Re-lock the TPM locality 3 space.
Unlock the Intel® TXT-capable chipset memory and I/O protections to allow memory and I/O activity by other
processor agents.
The content of the authenticated code execution area is invalidated by hardware in order to protect it from further
use or visibility. This internal processor storage area can no longer be used or relied upon after GETSEC[EXITAC].
Data structures need to be re-established outside of the authenticated code execution area if they are to be referenced after EXITAC. Since addressed memory content formerly mapped to the authenticated code execution area
may no longer be coherent with external system memory after EXITAC, processor TLBs in support of linear to physical address translation are also invalidated.
Upon completion of GETSEC[EXITAC] a near absolute indirect transfer is performed with EIP loaded with the
contents of EBX (based on the current operating mode size). In 64-bit mode, all 64 bits of RBX are loaded into RIP
6-18 Vol. 2D
GETSEC[EXITAC]—Exit Authenticated Code Execution Mode
SAFER MODE EXTENSIONS REFERENCE
if REX.W precedes GETSEC[EXITAC]. Otherwise RBX is treated as 32 bits even while in 64-bit mode. Conventional
CS limit checking is performed as part of this control transfer. Any exception conditions generated as part of this
control transfer will be directed to the existing IDT; thus it is recommended that an IDTR should also be established
prior to execution of the EXITAC function if there is a need for fault handling. In addition, any segmentation related
(and paging) data structures to be used after EXITAC should be re-established or validated by the authenticated
code prior to EXITAC.
In addition, any segmentation related (and paging) data structures to be used after EXITAC need to be re-established and mapped outside of the authenticated RAM designated area by the authenticated code prior to EXITAC.
Any data structure held within the authenticated RAM allocated area will no longer be accessible after completion
by EXITAC.
Operation
(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)
IF (CR4.SMXE=0)
THEN #UD;
ELSIF ( in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSIF (GETSEC leaf unsupported)
THEN #UD;
ELSIF ((in VMX operation) or ( (in 64-bit mode) and ( RBX is non-canonical) )
(CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or
(ACMODEFLAG=0) or (IN_SMM=1)) or (EDX ≠ 0))
THEN #GP(0);
IF (OperandSize = 32)
THEN tempEIP← EBX;
ELSIF (OperandSize = 64)
THEN tempEIP← RBX;
ELSE
tempEIP← EBX AND 0000FFFFH;
IF (tempEIP > code segment limit)
THEN #GP(0);
Invalidate ACRAM contents;
Invalidate processor TLB(s);
Drain outgoing messages;
SignalTXTMsg(CloseLocality3);
SignalTXTMsg(LockSMRAM);
SignalTXTMsg(ProcessorRelease);
Unmask INIT;
IF (SENTERFLAG=0)
THEN Unmask SMI, INIT, NMI, and A20M pin event;
ELSEIF (IA32_SMM_MONITOR_CTL[0] = 0)
THEN Unmask SMI pin event;
ACMODEFLAG← 0;
EIP← tempEIP;
END;
Flags Affected
None.
Use of Prefixes
LOCK
Causes #UD.
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size
Causes #UD.
GETSEC[EXITAC]—Exit Authenticated Code Execution Mode
Vol. 2D 6-19
SAFER MODE EXTENSIONS REFERENCE
Segment overrides Ignored.
Address size
Ignored.
REX.W
Sets 64-bit mode Operand size attribute.
Protected Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[EXITAC] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
If CR0.PE = 0 or CPL>0 or EFLAGS.VM =1.
If in VMX root operation.
If the processor is not currently in authenticated code execution mode.
If the processor is in SMM.
If any reserved bit position is set in the EDX parameter register.
Real-Address Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[EXITAC] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[EXITAC] is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[EXITAC] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[EXITAC] is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
All protected mode exceptions apply.
64-Bit Mode Exceptions
All protected mode exceptions apply.
#GP(0)
If the target address in RBX is not in a canonical form.
VM-Exit Condition
Reason (GETSEC)
6-20 Vol. 2D
IF in VMX non-root operation.
GETSEC[EXITAC]—Exit Authenticated Code Execution Mode
SAFER MODE EXTENSIONS REFERENCE
GETSEC[SENTER]—Enter a Measured Environment
Opcode
Instruction
Description
0F 37
GETSEC[SENTER]
Launch a measured environment.
(EAX=4)
EBX holds the SINIT authenticated code module physical base address.
ECX holds the SINIT authenticated code module size (bytes).
EDX controls the level of functionality supported by the measured environment launch.
Description
The GETSEC[SENTER] instruction initiates the launch of a measured environment and places the initiating logical
processor (ILP) into the authenticated code execution mode. The SENTER leaf of GETSEC is selected with EAX set
to 4 at execution. The physical base address of the AC module to be loaded and authenticated is specified in EBX.
The size of the module in bytes is specified in ECX. EDX controls the level of functionality supported by the
measured environment launch. To enable the full functionality of the protected environment launch, EDX must be
initialized to zero.
The authenticated code base address and size parameters (in bytes) are passed to the GETSEC[SENTER] instruction using EBX and ECX respectively. The ILP evaluates the contents of these registers according to the rules for the
AC module address in GETSEC[ENTERACCS]. AC module execution follows the same rules, as set by
GETSEC[ENTERACCS].
The launching software must ensure that the TPM.ACCESS_0.activeLocality bit is clear before executing the
GETSEC[SENTER] instruction.
There are restrictions enforced by the processor for execution of the GETSEC[SENTER] instruction:
•
Execution is not allowed unless the processor is in protected mode or IA-32e mode with CPL = 0 and
EFLAGS.VM = 0.
•
•
Processor cache must be available and not disabled using the CR0.CD and NW bits.
•
An Intel TXT-capable chipset must be present as communicated to the processor by sampling of the power-on
configuration capability field after reset.
•
The processor can not be in authenticated code execution mode or already in a measured environment (as
launched by a previous GETSEC[ENTERACCS] or GETSEC[SENTER] instruction).
•
To avoid potential operability conflicts between modes, the processor is not allowed to execute this instruction
if it currently is in SMM or VMX operation.
•
To insure consistent handling of SIPI messages, the processor executing the GETSEC[SENTER] instruction
must also be designated the BSP (boot-strap processor) as defined by A32_APIC_BASE.BSP (Bit 8).
•
EDX must be initialized to a setting supportable by the processor. Unless enumeration by the GETSEC[PARAMETERS] leaf reports otherwise, only a value of zero is supported.
For enforcing consistency of operation with numeric exception reporting using Interrupt 16, CR0.NE must be
set.
Failure to abide by the above conditions results in the processor signaling a general protection violation.
This instruction leaf starts the launch of a measured environment by initiating a rendezvous sequence for all logical
processors in the platform. The rendezvous sequence involves the initiating logical processor sending a message
(by executing GETSEC[SENTER]) and other responding logical processors (RLPs) acknowledging the message,
thus synchronizing the RLP(s) with the ILP.
In response to a message signaling the completion of rendezvous, RLPs clear the bootstrap processor indicator flag
(IA32_APIC_BASE.BSP) and enter an SENTER sleep state. In this sleep state, RLPs enter an idle processor condition while waiting to be activated after a measured environment has been established by the system executive.
RLPs in the SENTER sleep state can only be activated by the GETSEC leaf function WAKEUP in a measured environment.
A successful launch of the measured environment results in the initiating logical processor entering the authenticated code execution mode. Prior to reaching this point, the ILP performs the following steps internally:
•
Inhibit processor response to the external events: INIT, A20M, NMI, and SMI.
GETSEC[SENTER]—Enter a Measured Environment
Vol. 2D 6-21
SAFER MODE EXTENSIONS REFERENCE
•
•
•
•
•
•
•
•
•
•
•
Establish and check the location and size of the authenticated code module to be executed by the ILP.
Check for the existence of an Intel® TXT-capable chipset.
Verify the current power management configuration is acceptable.
Broadcast a message to enable protection of memory and I/O from activities from other processor agents.
Load the designated AC module into authenticated code execution area.
Isolate the content of authenticated code execution area from further state modification by external agents.
Authenticate the AC module.
Updated the Trusted Platform Module (TPM) with the authenticated code module's hash.
Initialize processor state based on the authenticated code module header information.
Unlock the Intel® TXT-capable chipset private configuration register space and TPM locality 3 space.
Begin execution in the authenticated code module at the defined entry point.
As an integrity check for proper processor hardware operation, execution of GETSEC[SENTER] will also check the
contents of all the machine check status registers (as reported by the MSRs IA32_MCi_STATUS) for any valid
uncorrectable error condition. In addition, the global machine check status register IA32_MCG_STATUS MCIP bit
must be cleared and the IERR processor package pin (or its equivalent) must be not asserted, indicating that no
machine check exception processing is currently in-progress. These checks are performed twice: once by the ILP
prior to the broadcast of the rendezvous message to RLPs, and later in response to RLPs acknowledging the rendezvous message. Any outstanding valid uncorrectable machine check error condition present in the machine check
status registers at the first check point will result in the ILP signaling a general protection violation. If an
outstanding valid uncorrectable machine check error condition is present at the second check point, then this will
result in the corresponding logical processor signaling the more severe TXT-shutdown condition with an error code
of 12.
Before loading and authentication of the target code module is performed, the processor also checks that the
current voltage and bus ratio encodings correspond to known good values supportable by the processor. The MSR
IA32_PERF_STATUS values are compared against either the processor supported maximum operating target
setting, system reset setting, or the thermal monitor operating target. If the current settings do not meet any of
these criteria then the SENTER function will attempt to change the voltage and bus ratio select controls in a
processor-specific manner. This adjustment may be to the thermal monitor, minimum (if different), or maximum
operating target depending on the processor.
This implies that some thermal operating target parameters configured by BIOS may be overridden by SENTER.
The measured environment software may need to take responsibility for restoring such settings that are deemed
to be safe, but not necessarily recognized by SENTER. If an adjustment is not possible when an out of range setting
is discovered, then the processor will abort the measured launch. This may be the case for chipset controlled
settings of these values or if the controllability is not enabled on the processor. In this case it is the responsibility of
the external software to program the chipset voltage ID and/or bus ratio select settings to known good values
recognized by the processor, prior to executing SENTER.
NOTE
For a mobile processor, an adjustment can be made according to the thermal monitor operating
target. For a quad-core processor the SENTER adjustment mechanism may result in a more conservative but non-uniform voltage setting, depending on the pre-SENTER settings per core.
The ILP and RLPs mask the response to the assertion of the external signals INIT#, A20M, NMI#, and SMI#. The
purpose of this masking control is to prevent exposure to existing external event handlers until a protected handler
has been put in place to directly handle these events. Masked external pin events may be unmasked conditionally
or unconditionally via the GETSEC[EXITAC], GETSEC[SEXIT], GETSEC[SMCTRL] or for specific VMX related operations such as a VM entry or the VMXOFF instruction (see respective GETSEC leaves and Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C for more details). The state of the A20M pin is masked and
forced internally to a de-asserted state so that external assertion is not recognized. A20M masking as set by
GETSEC[SENTER] is undone only after taking down the measured environment with the GETSEC[SEXIT] instruction or processor reset. INTR is masked by simply clearing the EFLAGS.IF bit. It is the responsibility of system software to control the processor response to INTR through appropriate management of EFLAGS.
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To prevent other (logical) processors from interfering with the ILP operating in authenticated code execution mode,
memory (excluding implicit write-back transactions) and I/O activities originating from other processor agents are
blocked. This protection starts when the ILP enters into authenticated code execution mode. Only memory and I/O
transactions initiated from the ILP are allowed to proceed. Exiting authenticated code execution mode is done by
executing GETSEC[EXITAC]. The protection of memory and I/O activities remains in effect until the ILP executes
GETSEC[EXITAC].
Once the authenticated code module has been loaded into the authenticated code execution area, it is protected
against further modification from external bus snoops. There is also a requirement that the memory type for the
authenticated code module address range be WB (via initialization of the MTRRs prior to execution of this instruction). If this condition is not satisfied, it is a violation of security and the processor will force a TXT system reset
(after writing an error code to the chipset LT.ERRORCODE register). This action is referred to as a Intel® TXT reset
condition. It is performed when it is considered unreliable to signal an error through the conventional exception
reporting mechanism.
To conform to the minimum granularity of MTRR MSRs for specifying the memory type, authenticated code RAM
(ACRAM) is allocated to the processor in 4096 byte granular blocks. If an AC module size as specified in ECX is not
a multiple of 4096 then the processor will allocate up to the next 4096 byte boundary for mapping as ACRAM with
indeterminate data. This pad area will not be visible to the authenticated code module as external memory nor can
it depend on the value of the data used to fill the pad area.
Once successful authentication has been completed by the ILP, the computed hash is stored in a trusted storage
facility in the platform. The following trusted storage facility are supported:
•
If the platform register FTM_INTERFACE_ID.[bits 3:0] = 0, the computed hash is stored to the platform’s TPM
at PCR17 after this register is implicitly reset. PCR17 is a dedicated register for holding the computed hash of
the authenticated code module loaded and subsequently executed by the GETSEC[SENTER]. As part of this
process, the dynamic PCRs 18-22 are reset so they can be utilized by subsequently software for registration of
code and data modules.
•
If the platform register FTM_INTERFACE_ID.[bits 3:0] = 1, the computed hash is stored in a firmware trusted
module (FTM) using a modified protocol similar to the protocol used to write to TPM’s PCR17.
After successful execution of SENTER, either PCR17 (if FTM is not enabled) or the FTM (if enabled) contains the
measurement of AC code and the SENTER launching parameters.
After authentication is completed successfully, the private configuration space of the Intel® TXT-capable chipset is
unlocked so that the authenticated code module and measured environment software can gain access to this
normally restricted chipset state. The Intel® TXT-capable chipset private configuration space can be locked later
by software writing to the chipset LT.CMD.CLOSE-PRIVATE register or unconditionally using the GETSEC[SEXIT]
instruction.
The SENTER leaf function also initializes some processor architecture state for the ILP from contents held in the
header of the authenticated code module. Since the authenticated code module is relocatable, all address references are relative to the base address passed in via EBX. The ILP GDTR base value is initialized to EBX + [GDTBasePtr] and GDTR limit set to [GDTLimit]. The CS selector is initialized to the value held in the AC module header
field SegSel, while the DS, SS, and ES selectors are initialized to CS+8. The segment descriptor fields are initialized
implicitly with BASE=0, LIMIT=FFFFFh, G=1, D=1, P=1, S=1, read/write/accessed for DS, SS, and ES, while
execute/read/accessed for CS. Execution in the authenticated code module for the ILP begins with the EIP set to
EBX + [EntryPoint]. AC module defined fields used for initializing processor state are consistency checked with a
failure resulting in an TXT-shutdown condition.
Table 6-6 provides a summary of processor state initialization for the ILP and RLP(s) after successful completion of
GETSEC[SENTER]. For both ILP and RLP(s), paging is disabled upon entry to the measured environment. It is up to
the ILP to establish a trusted paging environment, with appropriate mappings, to meet protection requirements
established during the launch of the measured environment. RLP state initialization is not completed until a subsequent wake-up has been signaled by execution of the GETSEC[WAKEUP] function by the ILP.
GETSEC[SENTER]—Enter a Measured Environment
Vol. 2D 6-23
SAFER MODE EXTENSIONS REFERENCE
Table 6-6. Register State Initialization after GETSEC[SENTER] and GETSEC[WAKEUP]
Register State
ILP after GETSEC[SENTER]
RLP after GETSEC[WAKEUP]
CR0
PG←0, AM←0, WP←0; Others unchanged
PG←0, CD←0, NW←0, AM←0, WP←0; PE←1, NE←1
CR4
00004000H
00004000H
EFLAGS
00000002H
00000002H
IA32_EFER
0H
0
EIP
[EntryPoint from MLE header1]
[LT.MLE.JOIN + 12]
EBX
Unchanged [SINIT.BASE]
Unchanged
EDX
SENTER control flags
Unchanged
EBP
SINIT.BASE
Unchanged
CS
Sel=[SINIT SegSel], base=0, limit=FFFFFh, G=1,
D=1, AR=9BH
Sel = [LT.MLE.JOIN + 8], base = 0, limit = FFFFFH, G =
1, D = 1, AR = 9BH
DS, ES, SS
Sel=[SINIT SegSel] +8, base=0, limit=FFFFFh, G=1,
D=1, AR=93H
Sel = [LT.MLE.JOIN + 8] +8, base = 0, limit = FFFFFH,
G = 1, D = 1, AR = 93H
GDTR
Base= SINIT.base (EBX) + [SINIT.GDTBasePtr],
Limit=[SINIT.GDTLimit]
Base = [LT.MLE.JOIN + 4], Limit = [LT.MLE.JOIN]
DR7
00000400H
00000400H
IA32_DEBUGCTL
0H
0H
Performance
counters and counter
control registers
0H
0H
IA32_MISC_ENABLE
See Table 6-5
See Table 6-5
IA32_SMM_MONITOR
_CTL
Bit 2←0
Bit 2←0
NOTES:
1. See Intel® Trusted Execution Technology Measured Launched Environment Programming Guide for MLE header
format.
Segmentation related processor state that has not been initialized by GETSEC[SENTER] requires appropriate
initialization before use. Since a new GDT context has been established, the previous state of the segment selector
values held in FS, GS, TR, and LDTR may no longer be valid. The IDTR will also require reloading with a new IDT
context after launching the measured environment before exceptions or the external interrupts INTR and NMI can
be handled. In the meantime, the programmer must take care in not executing an INT n instruction or any other
condition that would result in an exception or trap signaling.
Debug exception and trap related signaling is also disabled as part of execution of GETSEC[SENTER]. This is
achieved by clearing DR7, TF in EFLAGs, and the MSR IA32_DEBUGCTL as defined in Table 6-6. These can be reenabled once supporting exception handler(s), descriptor tables, and debug registers have been properly re-initialized following SENTER. Also, any pending single-step trap condition will be cleared at the completion of SENTER for
both the ILP and RLP(s).
Performance related counters and counter control registers are cleared as part of execution of SENTER on both the
ILP and RLP. This implies any active performance counters at the time of SENTER execution will be disabled. To
reactive the processor performance counters, this state must be re-initialized and re-enabled.
Since MCE along with all other state bits (with the exception of SMXE) are cleared in CR4 upon execution of SENTER
processing, any enabled machine check error condition that occurs will result in the processor performing the TXT-
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GETSEC[SENTER]—Enter a Measured Environment
SAFER MODE EXTENSIONS REFERENCE
shutdown action. This also applies to an RLP while in the SENTER sleep state. For each logical processor CR4.MCE
must be reestablished with a valid machine check exception handler to otherwise avoid an TXT-shutdown under
such conditions.
The MSR IA32_EFER is also unconditionally cleared as part of the processor state initialized by SENTER for both the
ILP and RLP. Since paging is disabled upon entering authenticated code execution mode, a new paging environment will have to be re-established if it is desired to enable IA-32e mode while operating in authenticated code
execution mode.
The miscellaneous feature control MSR, IA32_MISC_ENABLE, is initialized as part of the measured environment
launch. Certain bits of this MSR are preserved because preserving these bits may be important to maintain previously established platform settings. See the footnote for Table 6-5 The remaining bits are cleared for the purpose
of establishing a more consistent environment for the execution of authenticated code modules. Among the impact
of initializing this MSR, any previous condition established by the MONITOR instruction will be cleared.
Effect of MSR IA32_FEATURE_CONTROL MSR
Bits 15:8 of the IA32_FEATURE_CONTROL MSR affect the execution of GETSEC[SENTER]. These bits consist of two
fields:
•
•
Bit 15: a global enable control for execution of SENTER.
Bits 14:8: a parameter control field providing the ability to qualify SENTER execution based on the level of
functionality specified with corresponding EDX parameter bits 6:0.
The layout of these fields in the IA32_FEATURE_CONTROL MSR is shown in Table 6-1.
Prior to the execution of GETSEC[SENTER], the lock bit of IA32_FEATURE_CONTROL MSR must be bit set to affirm
the settings to be used. Once the lock bit is set, only a power-up reset condition will clear this MSR. The
IA32_FEATURE_CONTROL MSR must be configured in accordance to the intended usage at platform initialization.
Note that this MSR is only available on SMX or VMX enabled processors. Otherwise, IA32_FEATURE_CONTROL is
treated as reserved.
The Intel® Trusted Execution Technology Measured Launched Environment Programming Guide provides additional details and
requirements for programming measured environment software to launch in an Intel TXT platform.
Operation in a Uni-Processor Platform
(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)
GETSEC[SENTER] (ILP only):
IF (CR4.SMXE=0)
THEN #UD;
ELSE IF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSE IF (GETSEC leaf unsupported)
THEN #UD;
ELSE IF ((in VMX root operation) or
(CR0.PE=0) or (CR0.CD=1) or (CR0.NW=1) or (CR0.NE=0) or
(CPL>0) or (EFLAGS.VM=1) or
(IA32_APIC_BASE.BSP=0) or (TXT chipset not present) or
(SENTERFLAG=1) or (ACMODEFLAG=1) or (IN_SMM=1) or
(TPM interface is not present) or
(EDX ≠ (SENTER_EDX_support_mask & EDX)) or
(IA32_FEATURE_CONTROL[0]=0) or (IA32_FEATURE_CONTROL[15]=0) or
((IA32_FEATURE_CONTROL[14:8] & EDX[6:0]) ≠ EDX[6:0]))
THEN #GP(0);
IF (GETSEC[PARAMETERS].Parameter_Type = 5, MCA_Handling (bit 6) = 0)
FOR I = 0 to IA32_MCG_CAP.COUNT-1 DO
IF IA32_MC[I]_STATUS = uncorrectable error
THEN #GP(0);
FI;
OD;
GETSEC[SENTER]—Enter a Measured Environment
Vol. 2D 6-25
SAFER MODE EXTENSIONS REFERENCE
FI;
IF (IA32_MCG_STATUS.MCIP=1) or (IERR pin is asserted)
THEN #GP(0);
ACBASE← EBX;
ACSIZE← ECX;
IF (((ACBASE MOD 4096) ≠ 0) or ((ACSIZE MOD 64) ≠ 0 ) or (ACSIZE < minimum
module size) or (ACSIZE > AC RAM capacity) or ((ACBASE+ACSIZE) > (2^32 -1)))
THEN #GP(0);
Mask SMI, INIT, A20M, and NMI external pin events;
SignalTXTMsg(SENTER);
DO
WHILE (no SignalSENTER message);
TXT_SENTER__MSG_EVENT (ILP & RLP):
Mask and clear SignalSENTER event;
Unmask SignalSEXIT event;
IF (in VMX operation)
THEN TXT-SHUTDOWN(#IllegalEvent);
FOR I = 0 to IA32_MCG_CAP.COUNT-1 DO
IF IA32_MC[I]_STATUS = uncorrectable error
THEN TXT-SHUTDOWN(#UnrecovMCError);
FI;
OD;
IF (IA32_MCG_STATUS.MCIP=1) or (IERR pin is asserted)
THEN TXT-SHUTDOWN(#UnrecovMCError);
IF (Voltage or bus ratio status are NOT at a known good state)
THEN IF (Voltage select and bus ratio are internally adjustable)
THEN
Make product-specific adjustment on operating parameters;
ELSE
TXT-SHUTDOWN(#IIlegalVIDBRatio);
FI;
IA32_MISC_ENABLE← (IA32_MISC_ENABLE & MASK_CONST*)
(* The hexadecimal value of MASK_CONST may vary due to processor implementations *)
A20M← 0;
IA32_DEBUGCTL← 0;
Invalidate processor TLB(s);
Drain outgoing transactions;
Clear performance monitor counters and control;
SENTERFLAG← 1;
SignalTXTMsg(SENTERAck);
IF (logical processor is not ILP)
THEN GOTO RLP_SENTER_ROUTINE;
(* ILP waits for all logical processors to ACK *)
DO
DONE← TXT.READ(LT.STS);
WHILE (not DONE);
SignalTXTMsg(SENTERContinue);
SignalTXTMsg(ProcessorHold);
FOR I=ACBASE to ACBASE+ACSIZE-1 DO
ACRAM[I-ACBASE].ADDR← I;
ACRAM[I-ACBASE].DATA← LOAD(I);
OD;
6-26 Vol. 2D
GETSEC[SENTER]—Enter a Measured Environment
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IF (ACRAM memory type ≠ WB)
THEN TXT-SHUTDOWN(#BadACMMType);
IF (AC module header version is not supported) OR (ACRAM[ModuleType] ≠ 2)
THEN TXT-SHUTDOWN(#UnsupportedACM);
KEY← GETKEY(ACRAM, ACBASE);
KEYHASH← HASH(KEY);
CSKEYHASH← LT.READ(LT.PUBLIC.KEY);
IF (KEYHASH ≠ CSKEYHASH)
THEN TXT-SHUTDOWN(#AuthenticateFail);
SIGNATURE← DECRYPT(ACRAM, ACBASE, KEY);
(* The value of SIGNATURE_LEN_CONST is implementation-specific*)
FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
ACRAM[SCRATCH.I]← SIGNATURE[I];
COMPUTEDSIGNATURE← HASH(ACRAM, ACBASE, ACSIZE);
FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
ACRAM[SCRATCH.SIGNATURE_LEN_CONST+I]← COMPUTEDSIGNATURE[I];
IF (SIGNATURE ≠ COMPUTEDSIGNATURE)
THEN TXT-SHUTDOWN(#AuthenticateFail);
ACMCONTROL← ACRAM[CodeControl];
IF ((ACMCONTROL.0 = 0) and (ACMCONTROL.1 = 1) and (snoop hit to modified line detected on ACRAM load))
THEN TXT-SHUTDOWN(#UnexpectedHITM);
IF (ACMCONTROL reserved bits are set)
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACRAM[GDTBasePtr] < (ACRAM[HeaderLen] * 4 + Scratch_size)) OR
((ACRAM[GDTBasePtr] + ACRAM[GDTLimit]) >= ACSIZE))
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACMCONTROL.0 = 1) and (ACMCONTROL.1 = 1) and (snoop hit to modified
line detected on ACRAM load))
THEN ACEntryPoint← ACBASE+ACRAM[ErrorEntryPoint];
ELSE
ACEntryPoint← ACBASE+ACRAM[EntryPoint];
IF ((ACEntryPoint >= ACSIZE) or (ACEntryPoint < (ACRAM[HeaderLen] * 4 + Scratch_size)))
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACRAM[SegSel] > (ACRAM[GDTLimit] - 15)) or (ACRAM[SegSel] < 8))
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACRAM[SegSel].TI=1) or (ACRAM[SegSel].RPL≠0))
THEN TXT-SHUTDOWN(#BadACMFormat);
IF (FTM_INTERFACE_ID.[3:0] = 1 ) (* Alternate FTM Interface has been enabled *)
THEN (* TPM_LOC_CTRL_4 is located at 0FED44008H, TMP_DATA_BUFFER_4 is located at 0FED44080H *)
WRITE(TPM_LOC_CTRL_4) ← 01H; (* Modified HASH.START protocol *)
(* Write to firmware storage *)
WRITE(TPM_DATA_BUFFER_4) ← SIGNATURE_LEN_CONST + 4;
FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
WRITE(TPM_DATA_BUFFER_4 + 2 + I )← ACRAM[SCRATCH.I];
WRITE(TPM_DATA_BUFFER_4 + 2 + SIGNATURE_LEN_CONST) ← EDX;
WRITE(FTM.LOC_CTRL) ← 06H; (* Modified protocol combining HASH.DATA and HASH.END *)
ELSE IF (FTM_INTERFACE_ID.[3:0] = 0 ) (* Use standard TPM Interface *)
ACRAM[SCRATCH.SIGNATURE_LEN_CONST]← EDX;
WRITE(TPM.HASH.START)← 0;
FOR I=0 to SIGNATURE_LEN_CONST + 3 DO
WRITE(TPM.HASH.DATA)← ACRAM[SCRATCH.I];
WRITE(TPM.HASH.END)← 0;
FI;
GETSEC[SENTER]—Enter a Measured Environment
Vol. 2D 6-27
SAFER MODE EXTENSIONS REFERENCE
ACMODEFLAG← 1;
CR0.[PG.AM.WP]← 0;
CR4← 00004000h;
EFLAGS← 00000002h;
IA32_EFER← 0;
EBP← ACBASE;
GDTR.BASE← ACBASE+ACRAM[GDTBasePtr];
GDTR.LIMIT← ACRAM[GDTLimit];
CS.SEL← ACRAM[SegSel];
CS.BASE← 0;
CS.LIMIT← FFFFFh;
CS.G← 1;
CS.D← 1;
CS.AR← 9Bh;
DS.SEL← ACRAM[SegSel]+8;
DS.BASE← 0;
DS.LIMIT← FFFFFh;
DS.G← 1;
DS.D← 1;
DS.AR← 93h;
SS← DS;
ES← DS;
DR7← 00000400h;
IA32_DEBUGCTL← 0;
SignalTXTMsg(UnlockSMRAM);
SignalTXTMsg(OpenPrivate);
SignalTXTMsg(OpenLocality3);
EIP← ACEntryPoint;
END;
RLP_SENTER_ROUTINE: (RLP only)
Mask SMI, INIT, A20M, and NMI external pin events
Unmask SignalWAKEUP event;
Wait for SignalSENTERContinue message;
IA32_APIC_BASE.BSP← 0;
GOTO SENTER sleep state;
END;
Flags Affected
All flags are cleared.
Use of Prefixes
LOCK
Causes #UD.
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size
Causes #UD.
Segment overrides Ignored.
Address size
Ignored.
REX
Ignored.
Protected Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SENTER] is not reported as supported by GETSEC[CAPABILITIES].
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SAFER MODE EXTENSIONS REFERENCE
#GP(0)
If CR0.CD = 1 or CR0.NW = 1 or CR0.NE = 0 or CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.
If in VMX root operation.
If the initiating processor is not designated as the bootstrap processor via the MSR bit
IA32_APIC_BASE.BSP.
If an Intel® TXT-capable chipset is not present.
If an Intel® TXT-capable chipset interface to TPM is not detected as present.
If a protected partition is already active or the processor is already in authenticated code
mode.
If the processor is in SMM.
If a valid uncorrectable machine check error is logged in IA32_MC[I]_STATUS.
If the authenticated code base is not on a 4096 byte boundary.
If the authenticated code size > processor's authenticated code execution area storage
capacity.
If the authenticated code size is not modulo 64.
Real-Address Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SENTER] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[SENTER] is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SENTER] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[SENTER] is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
All protected mode exceptions apply.
#GP
IF AC code module does not reside in physical address below 2^32 -1.
64-Bit Mode Exceptions
All protected mode exceptions apply.
#GP
IF AC code module does not reside in physical address below 2^32 -1.
VM-Exit Condition
Reason (GETSEC)
IF in VMX non-root operation.
GETSEC[SENTER]—Enter a Measured Environment
Vol. 2D 6-29
SAFER MODE EXTENSIONS REFERENCE
GETSEC[SEXIT]—Exit Measured Environment
Opcode
Instruction
Description
0F 37
GETSEC[SEXIT]
Exit measured environment.
(EAX=5)
Description
The GETSEC[SEXIT] instruction initiates an exit of a measured environment established by GETSEC[SENTER]. The
SEXIT leaf of GETSEC is selected with EAX set to 5 at execution. This instruction leaf sends a message to all logical
processors in the platform to signal the measured environment exit.
There are restrictions enforced by the processor for the execution of the GETSEC[SEXIT] instruction:
•
Execution is not allowed unless the processor is in protected mode (CR0.PE = 1) with CPL = 0 and EFLAGS.VM
= 0.
•
The processor must be in a measured environment as launched by a previous GETSEC[SENTER] instruction,
but not still in authenticated code execution mode.
•
To avoid potential inter-operability conflicts between modes, the processor is not allowed to execute this
instruction if it currently is in SMM or in VMX operation.
•
To insure consistent handling of SIPI messages, the processor executing the GETSEC[SEXIT] instruction must
also be designated the BSP (bootstrap processor) as defined by the register bit IA32_APIC_BASE.BSP (bit 8).
Failure to abide by the above conditions results in the processor signaling a general protection violation.
This instruction initiates a sequence to rendezvous the RLPs with the ILP. It then clears the internal processor flag
indicating the processor is operating in a measured environment.
In response to a message signaling the completion of rendezvous, all RLPs restart execution with the instruction
that was to be executed at the time GETSEC[SEXIT] was recognized. This applies to all processor conditions, with
the following exceptions:
•
If an RLP executed HLT and was in this halt state at the time of the message initiated by GETSEC[SEXIT], then
execution resumes in the halt state.
•
If an RLP was executing MWAIT, then a message initiated by GETSEC[SEXIT] causes an exit of the MWAIT state,
falling through to the next instruction.
•
If an RLP was executing an intermediate iteration of a string instruction, then the processor resumes execution
of the string instruction at the point which the message initiated by GETSEC[SEXIT] was recognized.
•
If an RLP is still in the SENTER sleep state (never awakened with GETSEC[WAKEUP]), it will be sent to the waitfor-SIPI state after first clearing the bootstrap processor indicator flag (IA32_APIC_BASE.BSP) and any
pending SIPI state. In this case, such RLPs are initialized to an architectural state consistent with having taken
a soft reset using the INIT# pin.
Prior to completion of the GETSEC[SEXIT] operation, both the ILP and any active RLPs unmask the response of the
external event signals INIT#, A20M, NMI#, and SMI#. This unmasking is performed unconditionally to recognize
pin events which are masked after a GETSEC[SENTER]. The state of A20M is unmasked, as the A20M pin is not
recognized while the measured environment is active.
On a successful exit of the measured environment, the ILP re-locks the Intel® TXT-capable chipset private configuration space. GETSEC[SEXIT] does not affect the content of any PCR.
At completion of GETSEC[SEXIT] by the ILP, execution proceeds to the next instruction. Since EFLAGS and the
debug register state are not modified by this instruction, a pending trap condition is free to be signaled if previously
enabled.
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Operation in a Uni-Processor Platform
(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)
GETSEC[SEXIT] (ILP only):
IF (CR4.SMXE=0)
THEN #UD;
ELSE IF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSE IF (GETSEC leaf unsupported)
THEN #UD;
ELSE IF ((in VMX root operation) or
(CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or
(IA32_APIC_BASE.BSP=0) or
(TXT chipset not present) or
(SENTERFLAG=0) or (ACMODEFLAG=1) or (IN_SMM=1))
THEN #GP(0);
SignalTXTMsg(SEXIT);
DO
WHILE (no SignalSEXIT message);
TXT_SEXIT_MSG_EVENT (ILP & RLP):
Mask and clear SignalSEXIT event;
Clear MONITOR FSM;
Unmask SignalSENTER event;
IF (in VMX operation)
THEN TXT-SHUTDOWN(#IllegalEvent);
SignalTXTMsg(SEXITAck);
IF (logical processor is not ILP)
THEN GOTO RLP_SEXIT_ROUTINE;
(* ILP waits for all logical processors to ACK *)
DO
DONE← READ(LT.STS);
WHILE (NOT DONE);
SignalTXTMsg(SEXITContinue);
SignalTXTMsg(ClosePrivate);
SENTERFLAG← 0;
Unmask SMI, INIT, A20M, and NMI external pin events;
END;
RLP_SEXIT_ROUTINE (RLPs only):
Wait for SignalSEXITContinue message;
Unmask SMI, INIT, A20M, and NMI external pin events;
IF (prior execution state = HLT)
THEN reenter HLT state;
IF (prior execution state = SENTER sleep)
THEN
IA32_APIC_BASE.BSP← 0;
Clear pending SIPI state;
Call INIT_PROCESSOR_STATE;
Unmask SIPI event;
GOTO WAIT-FOR-SIPI;
FI;
END;
GETSEC[SEXIT]—Exit Measured Environment
Vol. 2D 6-31
SAFER MODE EXTENSIONS REFERENCE
Flags Affected
ILP: None.
RLPs: all flags are modified for an RLP. returning to wait-for-SIPI state, none otherwise.
Use of Prefixes
LOCK
Causes #UD.
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size
Causes #UD.
Segment overrides Ignored.
Address size
Ignored.
REX
Ignored.
Protected Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SEXIT] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
If CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.
If in VMX root operation.
If the initiating processor is not designated via the MSR bit IA32_APIC_BASE.BSP.
If an Intel® TXT-capable chipset is not present.
If a protected partition is not already active or the processor is already in authenticated code
mode.
If the processor is in SMM.
Real-Address Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SEXIT] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[SEXIT] is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SEXIT] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[SEXIT] is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
All protected mode exceptions apply.
64-Bit Mode Exceptions
All protected mode exceptions apply.
VM-Exit Condition
Reason (GETSEC)
6-32 Vol. 2D
IF in VMX non-root operation.
GETSEC[SEXIT]—Exit Measured Environment
SAFER MODE EXTENSIONS REFERENCE
GETSEC[PARAMETERS]—Report the SMX Parameters
Opcode
Instruction
Description
0F 37
GETSEC[PARAMETERS]
Report the SMX parameters.
(EAX=6)
The parameters index is input in EBX with the result returned in EAX, EBX, and ECX.
Description
The GETSEC[PARAMETERS] instruction returns specific parameter information for SMX features supported by the
processor. Parameter information is returned in EAX, EBX, and ECX, with the input parameter selected using EBX.
Software retrieves parameter information by searching with an input index for EBX starting at 0, and then reading
the returned results in EAX, EBX, and ECX. EAX[4:0] is designated to return a parameter type field indicating if a
parameter is available and what type it is. If EAX[4:0] is returned with 0, this designates a null parameter and indicates no more parameters are available.
Table 6-7 defines the parameter types supported in current and future implementations.
Table 6-7. SMX Reporting Parameters Format
Parameter
Type EAX[4:0]
Parameter Description
EAX[31:5]
EBX[31:0]
ECX[31:0]
0
NULL
Reserved (0 returned)
Reserved (unmodified)
Reserved (unmodified)
1
Supported AC module
versions
Reserved (0 returned)
Version comparison mask
Version numbers
supported
2
Max size of authenticated
code execution area
Multiply by 32 for size in
bytes
Reserved (unmodified)
Reserved (unmodified)
3
External memory types
supported during AC mode
Memory type bit mask
Reserved (unmodified)
Reserved (unmodified)
4
Selective SENTER
functionality control
EAX[14:8] correspond to
available SENTER function
disable controls
Reserved (unmodified)
Reserved (unmodified)
5
TXT extensions support
TXT Feature Extensions
Flags (see Table 6-8)
Reserved
Reserved
6-31
Undefined
Reserved (unmodified)
Reserved (unmodified)
Reserved (unmodified)
GETSEC[PARAMETERS]—Report the SMX Parameters
Vol. 2D 6-33
SAFER MODE EXTENSIONS REFERENCE
Table 6-8. TXT Feature Extensions Flags
Bit
Definition
Description
5
Processor based
S-CRTM support
Returns 1 if this processor implements a processor-rooted S-CRTM capability and 0 if not (SCRTM is rooted in BIOS).
This flag cannot be used to infer whether the chipset supports TXT or whether the
processor support SMX.
6
Machine Check
Handling
Returns 1 if it machine check status registers can be preserved through ENTERACCS and
SENTER. If this bit is 1, the caller of ENTERACCS and SENTER is not required to clear machine
check error status bits before invoking these GETSEC leaves.
If this bit returns 0, the caller of ENTERACCS and SENTER must clear all machine check error
status bits before invoking these GETSEC leaves.
31:7
Reserved
Reserved for future use. Will return 0.
Supported AC module versions (as defined by the AC module HeaderVersion field) can be determined for a particular SMX capable processor by the type 1 parameter. Using EBX to index through the available parameters reported
by GETSEC[PARAMETERS] for each unique parameter set returned for type 1, software can determine the complete
list of AC module version(s) supported.
For each parameter set, EBX returns the comparison mask and ECX returns the available HeaderVersion field
values supported, after AND'ing the target HeaderVersion with the comparison mask. Software can then determine
if a particular AC module version is supported by following the pseudo-code search routine given below:
parameter_search_index= 0
do {
EBX= parameter_search_index++
EAX= 6
GETSEC
if (EAX[4:0] = 1) {
if ((version_query & EBX) = ECX) {
version_is_supported= 1
break
}
}
} while (EAX[4:0] ≠ 0)
If only AC modules with a HeaderVersion of 0 are supported by the processor, then only one parameter set of type
1 will be returned, as follows: EAX = 00000001H,
EBX = FFFFFFFFH and ECX = 00000000H.
The maximum capacity for an authenticated code execution area supported by the processor is reported with the
parameter type of 2. The maximum supported size in bytes is determined by multiplying the returned size in
EAX[31:5] by 32. Thus, for a maximum supported authenticated RAM size of 32KBytes, EAX returns with
00008002H.
Supportable memory types for memory mapped outside of the authenticated code execution area are reported
with the parameter type of 3. While is active, as initiated by the GETSEC functions SENTER and ENTERACCS and
terminated by EXITAC, there are restrictions on what memory types are allowed for the rest of system memory. It
is the responsibility of the system software to initialize the memory type range register (MTRR) MSRs and/or the
page attribute table (PAT) to only map memory types consistent with the reporting of this parameter. The reporting
of supportable memory types of external memory is indicated using a bit map returned in EAX[31:8]. These bit
positions correspond to the memory type encodings defined for the MTRR MSR and PAT programming. See
Table 6-9.
The parameter type of 4 is used for enumerating the availability of selective GETSEC[SENTER] function disable
controls. If a 1 is reported in bits 14:8 of the returned parameter EAX, then this indicates a disable control capa-
6-34 Vol. 2D
GETSEC[PARAMETERS]—Report the SMX Parameters
SAFER MODE EXTENSIONS REFERENCE
bility exists with SENTER for a particular function. The enumerated field in bits 14:8 corresponds to use of the EDX
input parameter bits 6:0 for SENTER. If an enumerated field bit is set to 1, then the corresponding EDX input
parameter bit of EDX may be set to 1 to disable that designated function. If the enumerated field bit is 0 or this
parameter is not reported, then no disable capability exists with the corresponding EDX input parameter for
SENTER, and EDX bit(s) must be cleared to 0 to enable execution of SENTER. If no selective disable capability for
SENTER exists as enumerated, then the corresponding bits in the IA32_FEATURE_CONTROL MSR bits 14:8 must
also be programmed to 1 if the SENTER global enable bit 15 of the MSR is set. This is required to enable future
extensibility of SENTER selective disable capability with respect to potentially separate software initialization of the
MSR.
Table 6-9. External Memory Types Using Parameter 3
EAX Bit Position
Parameter Description
8
Uncacheable (UC)
9
Write Combining (WC)
11:10
Reserved
12
Write-through (WT)
13
Write-protected (WP)
14
Write-back (WB)
31:15
Reserved
If the GETSEC[PARAMETERS] leaf or specific parameter is not present for a given SMX capable processor, then
default parameter values should be assumed. These are defined in Table 6-10.
Table 6-10. Default Parameter Values
Parameter Type EAX[4:0]
Default Setting
Parameter Description
1
0.0 only
Supported AC module versions.
2
32 KBytes
Authenticated code execution area size.
3
UC only
External memory types supported during AC execution mode.
4
None
Available SENTER selective disable controls.
Operation
(* example of a processor supporting only a 0.0 HeaderVersion, 32K ACRAM size, memory types UC and WC *)
IF (CR4.SMXE=0)
THEN #UD;
ELSE IF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSE IF (GETSEC leaf unsupported)
THEN #UD;
(* example of a processor supporting a 0.0 HeaderVersion *)
IF (EBX=0) THEN
EAX← 00000001h;
EBX← FFFFFFFFh;
ECX← 00000000h;
ELSE IF (EBX=1)
(* example of a processor supporting a 32K ACRAM size *)
GETSEC[PARAMETERS]—Report the SMX Parameters
Vol. 2D 6-35
SAFER MODE EXTENSIONS REFERENCE
THEN EAX← 00008002h;
ESE IF (EBX= 2)
(* example of a processor supporting external memory types of UC and WC *)
THEN EAX← 00000303h;
ESE IF (EBX= other value(s) less than unsupported index value)
(* EAX value varies. Consult Table 6-7 and Table 6-8*)
ELSE (* unsupported index*)
EAX¨ 00000000h;
END;
Flags Affected
None.
Use of Prefixes
LOCK
Causes #UD.
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size
Causes #UD.
Segment overrides Ignored.
Address size
Ignored.
REX
Ignored.
Protected Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[PARAMETERS] is not reported as supported by GETSEC[CAPABILITIES].
Real-Address Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[PARAMETERS] is not reported as supported by GETSEC[CAPABILITIES].
Virtual-8086 Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[PARAMETERS] is not reported as supported by GETSEC[CAPABILITIES].
Compatibility Mode Exceptions
All protected mode exceptions apply.
64-Bit Mode Exceptions
All protected mode exceptions apply.
VM-Exit Condition
Reason (GETSEC)
6-36 Vol. 2D
IF in VMX non-root operation.
GETSEC[PARAMETERS]—Report the SMX Parameters
SAFER MODE EXTENSIONS REFERENCE
GETSEC[SMCTRL]—SMX Mode Control
Opcode
Instruction
Description
0F 37 (EAX = 7)
GETSEC[SMCTRL]
Perform specified SMX mode control as selected with the input EBX.
Description
The GETSEC[SMCTRL] instruction is available for performing certain SMX specific mode control operations. The
operation to be performed is selected through the input register EBX. Currently only an input value in EBX of 0 is
supported. All other EBX settings will result in the signaling of a general protection violation.
If EBX is set to 0, then the SMCTRL leaf is used to re-enable SMI events. SMI is masked by the ILP executing the
GETSEC[SENTER] instruction (SMI is also masked in the responding logical processors in response to SENTER
rendezvous messages.). The determination of when this instruction is allowed and the events that are unmasked
is dependent on the processor context (See Table 6-11). For brevity, the usage of SMCTRL where EBX=0 will be
referred to as GETSEC[SMCTRL(0)].
As part of support for launching a measured environment, the SMI, NMI and INIT events are masked after
GETSEC[SENTER], and remain masked after exiting authenticated execution mode. Unmasking these events
should be accompanied by securely enabling these event handlers. These security concerns can be addressed in
VMX operation by a MVMM.
The VM monitor can choose two approaches:
•
In a dual monitor approach, the executive software will set up an SMM monitor in parallel to the executive VMM
(i.e. the MVMM), see Chapter 34, “System Management Mode” of Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3C. The SMM monitor is dedicated to handling SMI events without compromising
the security of the MVMM. This usage model of handling SMI while a measured environment is active does not
require the use of GETSEC[SMCTRL(0)] as event re-enabling after the VMX environment launch is handled
implicitly and through separate VMX based controls.
•
If a dedicated SMM monitor will not be established and SMIs are to be handled within the measured
environment, then GETSEC[SMCTRL(0)] can be used by the executive software to re-enable SMI that has been
masked as a result of SENTER.
Table 6-11 defines the processor context in which GETSEC[SMCTRL(0)] can be used and which events will be
unmasked. Note that the events that are unmasked are dependent upon the currently operating processor context.
Table 6-11. Supported Actions for GETSEC[SMCTRL(0)]
ILP Mode of Operation
SMCTRL execution action
In VMX non-root operation
VM exit
SENTERFLAG = 0
#GP(0), illegal context
In authenticated code execution mode
(ACMODEFLAG = 1)
#GP(0), illegal context
SENTERFLAG = 1, not in VMX operation, not in
SMM
Unmask SMI
SENTERFLAG = 1, in VMX root operation, not in
SMM
Unmask SMI if SMM monitor is not configured, otherwise #GP(0)
SENTERFLAG = 1, In VMX root operation, in SMM
#GP(0), illegal context
GETSEC[SMCTRL]—SMX Mode Control
Vol. 2D 6-37
SAFER MODE EXTENSIONS REFERENCE
Operation
(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)
IF (CR4.SMXE=0)
THEN #UD;
ELSE IF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSE IF (GETSEC leaf unsupported)
THEN #UD;
ELSE IF ((CR0.PE=0) or (CPL>0) OR (EFLAGS.VM=1))
THEN #GP(0);
ELSE IF((EBX=0) and (SENTERFLAG=1) and (ACMODEFLAG=0) and (IN_SMM=0) and
(((in VMX root operation) and (SMM monitor not configured)) or (not in VMX operation)) )
THEN unmask SMI;
ELSE
#GP(0);
END
Flags Affected
None.
Use of Prefixes
LOCK
Causes #UD.
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size
Causes #UD.
Segment overrides Ignored.
Address size
Ignored.
REX
Ignored.
Protected Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SMCTRL] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
If CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.
If in VMX root operation.
If a protected partition is not already active or the processor is currently in authenticated code
mode.
If the processor is in SMM.
If the SMM monitor is not configured.
Real-Address Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SMCTRL] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[SMCTRL] is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[SMCTRL] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
6-38 Vol. 2D
GETSEC[SMCTRL] is not recognized in virtual-8086 mode.
GETSEC[SMCTRL]—SMX Mode Control
SAFER MODE EXTENSIONS REFERENCE
Compatibility Mode Exceptions
All protected mode exceptions apply.
64-Bit Mode Exceptions
All protected mode exceptions apply.
VM-exit Condition
Reason (GETSEC)
IF in VMX non-root operation.
GETSEC[SMCTRL]—SMX Mode Control
Vol. 2D 6-39
SAFER MODE EXTENSIONS REFERENCE
GETSEC[WAKEUP]—Wake up sleeping processors in measured environment
Opcode
Instruction
Description
0F 37
GETSEC[WAKEUP]
Wake up the responding logical processors from the SENTER sleep state.
(EAX=8)
Description
The GETSEC[WAKEUP] leaf function broadcasts a wake-up message to all logical processors currently in the
SENTER sleep state. This GETSEC leaf must be executed only by the ILP, in order to wake-up the RLPs. Responding
logical processors (RLPs) enter the SENTER sleep state after completion of the SENTER rendezvous sequence.
The GETSEC[WAKEUP] instruction may only be executed:
•
•
•
•
In a measured environment as initiated by execution of GETSEC[SENTER].
Outside of authenticated code execution mode.
Execution is not allowed unless the processor is in protected mode with CPL = 0 and EFLAGS.VM = 0.
In addition, the logical processor must be designated as the boot-strap processor as configured by setting
IA32_APIC_BASE.BSP = 1.
If these conditions are not met, attempts to execute GETSEC[WAKEUP] result in a general protection violation.
An RLP exits the SENTER sleep state and start execution in response to a WAKEUP signal initiated by ILP’s execution of GETSEC[WAKEUP]. The RLP retrieves a pointer to a data structure that contains information to enable
execution from a defined entry point. This data structure is located using a physical address held in the Intel® TXTcapable chipset configuration register LT.MLE.JOIN. The register is publicly writable in the chipset by all processors
and is not restricted by the Intel® TXT-capable chipset configuration register lock status. The format of this data
structure is defined in Table 6-12.
Table 6-12. RLP MVMM JOIN Data Structure
Offset
Field
0
GDT limit
4
GDT base pointer
8
Segment selector initializer
12
EIP
The MLE JOIN data structure contains the information necessary to initialize RLP processor state and permit the
processor to join the measured environment. The GDTR, LIP, and CS, DS, SS, and ES selector values are initialized
using this data structure. The CS selector index is derived directly from the segment selector initializer field; DS,
SS, and ES selectors are initialized to CS+8. The segment descriptor fields are initialized implicitly with BASE = 0,
LIMIT = FFFFFH, G = 1, D = 1, P = 1, S = 1; read/write/access for DS, SS, and ES; and execute/read/access for
CS. It is the responsibility of external software to establish a GDT pointed to by the MLE JOIN data structure that
contains descriptor entries consistent with the implicit settings initialized by the processor (see Table 6-6). Certain
states from the content of Table 6-12 are checked for consistency by the processor prior to execution. A failure of
any consistency check results in the RLP aborting entry into the protected environment and signaling an Intel® TXT
shutdown condition. The specific checks performed are documented later in this section. After successful completion of processor consistency checks and subsequent initialization, RLP execution in the measured environment
begins from the entry point at offset 12 (as indicated in Table 6-12).
6-40 Vol. 2D
GETSEC[WAKEUP]—Wake up sleeping processors in measured environment
SAFER MODE EXTENSIONS REFERENCE
Operation
(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)
IF (CR4.SMXE=0)
THEN #UD;
ELSE IF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSE IF (GETSEC leaf unsupported)
THEN #UD;
ELSE IF ((CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or (SENTERFLAG=0) or (ACMODEFLAG=1) or (IN_SMM=0) or (in VMX operation) or
(IA32_APIC_BASE.BSP=0) or (TXT chipset not present))
THEN #GP(0);
ELSE
SignalTXTMsg(WAKEUP);
END;
RLP_SIPI_WAKEUP_FROM_SENTER_ROUTINE: (RLP only)
WHILE (no SignalWAKEUP event);
IF (IA32_SMM_MONITOR_CTL[0] ≠ ILP.IA32_SMM_MONITOR_CTL[0])
THEN TXT-SHUTDOWN(#IllegalEvent)
IF (IA32_SMM_MONITOR_CTL[0] = 0)
THEN Unmask SMI pin event;
ELSE
Mask SMI pin event;
Mask A20M, and NMI external pin events (unmask INIT);
Mask SignalWAKEUP event;
Invalidate processor TLB(s);
Drain outgoing transactions;
TempGDTRLIMIT← LOAD(LT.MLE.JOIN);
TempGDTRBASE← LOAD(LT.MLE.JOIN+4);
TempSegSel← LOAD(LT.MLE.JOIN+8);
TempEIP← LOAD(LT.MLE.JOIN+12);
IF (TempGDTLimit & FFFF0000h)
THEN TXT-SHUTDOWN(#BadJOINFormat);
IF ((TempSegSel > TempGDTRLIMIT-15) or (TempSegSel < 8))
THEN TXT-SHUTDOWN(#BadJOINFormat);
IF ((TempSegSel.TI=1) or (TempSegSel.RPL≠0))
THEN TXT-SHUTDOWN(#BadJOINFormat);
CR0.[PG,CD,NW,AM,WP]← 0;
CR0.[NE,PE]← 1;
CR4← 00004000h;
EFLAGS← 00000002h;
IA32_EFER← 0;
GDTR.BASE← TempGDTRBASE;
GDTR.LIMIT← TempGDTRLIMIT;
CS.SEL← TempSegSel;
CS.BASE← 0;
CS.LIMIT← FFFFFh;
CS.G← 1;
CS.D← 1;
CS.AR← 9Bh;
DS.SEL← TempSegSel+8;
DS.BASE← 0;
DS.LIMIT← FFFFFh;
DS.G← 1;
GETSEC[WAKEUP]—Wake up sleeping processors in measured environment
Vol. 2D 6-41
SAFER MODE EXTENSIONS REFERENCE
DS.D← 1;
DS.AR← 93h;
SS← DS;
ES← DS;
DR7← 00000400h;
IA32_DEBUGCTL← 0;
EIP← TempEIP;
END;
Flags Affected
None.
Use of Prefixes
LOCK
Causes #UD.
REP*
Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size
Causes #UD.
Segment overrides Ignored.
Address size
Ignored.
REX
Ignored.
Protected Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[WAKEUP] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
If CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.
If in VMX operation.
If a protected partition is not already active or the processor is currently in authenticated code
mode.
If the processor is in SMM.
#UD
If CR4.SMXE = 0.
#GP(0)
GETSEC[WAKEUP] is not recognized in real-address mode.
If GETSEC[WAKEUP] is not reported as supported by GETSEC[CAPABILITIES].
Virtual-8086 Mode Exceptions
#UD
If CR4.SMXE = 0.
If GETSEC[WAKEUP] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0)
GETSEC[WAKEUP] is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
All protected mode exceptions apply.
64-Bit Mode Exceptions
All protected mode exceptions apply.
VM-exit Condition
Reason (GETSEC)
6-42 Vol. 2D
IF in VMX non-root operation.
GETSEC[WAKEUP]—Wake up sleeping processors in measured environment
APPENDIX A
OPCODE MAP
Use the opcode tables in this chapter to interpret IA-32 and Intel 64 architecture object code. Instructions are
divided into encoding groups:
•
1-byte, 2-byte and 3-byte opcode encodings are used to encode integer, system, MMX technology,
SSE/SSE2/SSE3/SSSE3/SSE4, and VMX instructions. Maps for these instructions are given in Table A-2
through Table A-6.
•
Escape opcodes (in the format: ESC character, opcode, ModR/M byte) are used for floating-point instructions.
The maps for these instructions are provided in Table A-7 through Table A-22.
NOTE
All blanks in opcode maps are reserved and must not be used. Do not depend on the operation of
undefined or blank opcodes.
A.1
USING OPCODE TABLES
Tables in this appendix list opcodes of instructions (including required instruction prefixes, opcode extensions in
associated ModR/M byte). Blank cells in the tables indicate opcodes that are reserved or undefined.
The opcode map tables are organized by hex values of the upper and lower 4 bits of an opcode byte. For 1-byte
encodings (Table A-2), use the four high-order bits of an opcode to index a row of the opcode table; use the four
low-order bits to index a column of the table. For 2-byte opcodes beginning with 0FH (Table A-3), skip any instruction prefixes, the 0FH byte (0FH may be preceded by 66H, F2H, or F3H) and use the upper and lower 4-bit values
of the next opcode byte to index table rows and columns. Similarly, for 3-byte opcodes beginning with 0F38H or
0F3AH (Table A-4), skip any instruction prefixes, 0F38H or 0F3AH and use the upper and lower 4-bit values of the
third opcode byte to index table rows and columns. See Section A.2.4, “Opcode Look-up Examples for One, Two,
and Three-Byte Opcodes.”
When a ModR/M byte provides opcode extensions, this information qualifies opcode execution. For information on
how an opcode extension in the ModR/M byte modifies the opcode map in Table A-2 and Table A-3, see Section A.4.
The escape (ESC) opcode tables for floating point instructions identify the eight high order bits of opcodes at the
top of each page. See Section A.5. If the accompanying ModR/M byte is in the range of 00H-BFH, bits 3-5 (the top
row of the third table on each page) along with the reg bits of ModR/M determine the opcode. ModR/M bytes
outside the range of 00H-BFH are mapped by the bottom two tables on each page of the section.
A.2
KEY TO ABBREVIATIONS
Operands are identified by a two-character code of the form Zz. The first character, an uppercase letter, specifies
the addressing method; the second character, a lowercase letter, specifies the type of operand.
A.2.1
Codes for Addressing Method
The following abbreviations are used to document addressing methods:
A
Direct address: the instruction has no ModR/M byte; the address of the operand is encoded in the instruction. No base register, index register, or scaling factor can be applied (for example, far JMP (EA)).
B
The VEX.vvvv field of the VEX prefix selects a general purpose register.
C
The reg field of the ModR/M byte selects a control register (for example, MOV (0F20, 0F22)).
Vol. 2D A-1
OPCODE MAP
D
The reg field of the ModR/M byte selects a debug register (for example,
MOV (0F21,0F23)).
E
A ModR/M byte follows the opcode and specifies the operand. The operand is either a general-purpose
register or a memory address. If it is a memory address, the address is computed from a segment register
and any of the following values: a base register, an index register, a scaling factor, a displacement.
F
EFLAGS/RFLAGS Register.
G
The reg field of the ModR/M byte selects a general register (for example, AX (000)).
H
The VEX.vvvv field of the VEX prefix selects a 128-bit XMM register or a 256-bit YMM register, determined
by operand type. For legacy SSE encodings this operand does not exist, changing the instruction to
destructive form.
I
Immediate data: the operand value is encoded in subsequent bytes of the instruction.
J
The instruction contains a relative offset to be added to the instruction pointer register (for example, JMP
(0E9), LOOP).
L
The upper 4 bits of the 8-bit immediate selects a 128-bit XMM register or a 256-bit YMM register, determined by operand type. (the MSB is ignored in 32-bit mode)
M
The ModR/M byte may refer only to memory (for example, BOUND, LES, LDS, LSS, LFS, LGS,
CMPXCHG8B).
N
The R/M field of the ModR/M byte selects a packed-quadword, MMX technology register.
O
The instruction has no ModR/M byte. The offset of the operand is coded as a word or double word
(depending on address size attribute) in the instruction. No base register, index register, or scaling factor
can be applied (for example, MOV (A0–A3)).
P
The reg field of the ModR/M byte selects a packed quadword MMX technology register.
Q
A ModR/M byte follows the opcode and specifies the operand. The operand is either an MMX technology
register or a memory address. If it is a memory address, the address is computed from a segment register
and any of the following values: a base register, an index register, a scaling factor, and a displacement.
R
The R/M field of the ModR/M byte may refer only to a general register (for example, MOV (0F20-0F23)).
S
The reg field of the ModR/M byte selects a segment register (for example, MOV (8C,8E)).
U
The R/M field of the ModR/M byte selects a 128-bit XMM register or a 256-bit YMM register, determined by
operand type.
V
The reg field of the ModR/M byte selects a 128-bit XMM register or a 256-bit YMM register, determined by
operand type.
W
A ModR/M byte follows the opcode and specifies the operand. The operand is either a 128-bit XMM register,
a 256-bit YMM register (determined by operand type), or a memory address. If it is a memory address, the
address is computed from a segment register and any of the following values: a base register, an index
register, a scaling factor, and a displacement.
X
Memory addressed by the DS:rSI register pair (for example, MOVS, CMPS, OUTS, or LODS).
Y
Memory addressed by the ES:rDI register pair (for example, MOVS, CMPS, INS, STOS, or SCAS).
A.2.2
Codes for Operand Type
The following abbreviations are used to document operand types:
a
Two one-word operands in memory or two double-word operands in memory, depending on operand-size
attribute (used only by the BOUND instruction).
b
Byte, regardless of operand-size attribute.
c
Byte or word, depending on operand-size attribute.
d
Doubleword, regardless of operand-size attribute.
dq
Double-quadword, regardless of operand-size attribute.
A-2 Vol. 2D
OPCODE MAP
p
32-bit, 48-bit, or 80-bit pointer, depending on operand-size attribute.
pd
128-bit or 256-bit packed double-precision floating-point data.
pi
Quadword MMX technology register (for example: mm0).
ps
128-bit or 256-bit packed single-precision floating-point data.
q
Quadword, regardless of operand-size attribute.
qq
Quad-Quadword (256-bits), regardless of operand-size attribute.
s
6-byte or 10-byte pseudo-descriptor.
sd
Scalar element of a 128-bit double-precision floating data.
ss
Scalar element of a 128-bit single-precision floating data.
si
Doubleword integer register (for example: eax).
v
Word, doubleword or quadword (in 64-bit mode), depending on operand-size attribute.
w
Word, regardless of operand-size attribute.
x
dq or qq based on the operand-size attribute.
y
Doubleword or quadword (in 64-bit mode), depending on operand-size attribute.
z
Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size.
A.2.3
Register Codes
When an opcode requires a specific register as an operand, the register is identified by name (for example, AX, CL,
or ESI). The name indicates whether the register is 64, 32, 16, or 8 bits wide.
A register identifier of the form eXX or rXX is used when register width depends on the operand-size attribute. eXX
is used when 16 or 32-bit sizes are possible; rXX is used when 16, 32, or 64-bit sizes are possible. For example:
eAX indicates that the AX register is used when the operand-size attribute is 16 and the EAX register is used when
the operand-size attribute is 32. rAX can indicate AX, EAX or RAX.
When the REX.B bit is used to modify the register specified in the reg field of the opcode, this fact is indicated by
adding “/x” to the register name to indicate the additional possibility. For example, rCX/r9 is used to indicate that
the register could either be rCX or r9. Note that the size of r9 in this case is determined by the operand size attribute (just as for rCX).
A.2.4
Opcode Look-up Examples for One, Two, and Three-Byte Opcodes
This section provides examples that demonstrate how opcode maps are used.
A.2.4.1
One-Byte Opcode Instructions
The opcode map for 1-byte opcodes is shown in Table A-2. The opcode map for 1-byte opcodes is arranged by row
(the least-significant 4 bits of the hexadecimal value) and column (the most-significant 4 bits of the hexadecimal
value). Each entry in the table lists one of the following types of opcodes:
•
•
Instruction mnemonics and operand types using the notations listed in Section A.2
Opcodes used as an instruction prefix
For each entry in the opcode map that corresponds to an instruction, the rules for interpreting the byte following
the primary opcode fall into one of the following cases:
•
A ModR/M byte is required and is interpreted according to the abbreviations listed in Section A.1 and Chapter
2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Operand types are listed according to notations listed in Section A.2.
•
A ModR/M byte is required and includes an opcode extension in the reg field in the ModR/M byte. Use Table A-6
when interpreting the ModR/M byte.
Vol. 2D A-3
OPCODE MAP
•
Use of the ModR/M byte is reserved or undefined. This applies to entries that represent an instruction prefix or
entries for instructions without operands that use ModR/M (for example: 60H, PUSHA; 06H, PUSH ES).
Example A-1. Look-up Example for 1-Byte Opcodes
Opcode 030500000000H for an ADD instruction is interpreted using the 1-byte opcode map (Table A-2) as follows:
•
The first digit (0) of the opcode indicates the table row and the second digit (3) indicates the table column. This
locates an opcode for ADD with two operands.
•
The first operand (type Gv) indicates a general register that is a word or doubleword depending on the operandsize attribute. The second operand (type Ev) indicates a ModR/M byte follows that specifies whether the
operand is a word or doubleword general-purpose register or a memory address.
•
The ModR/M byte for this instruction is 05H, indicating that a 32-bit displacement follows (00000000H). The
reg/opcode portion of the ModR/M byte (bits 3-5) is 000, indicating the EAX register.
The instruction for this opcode is ADD EAX, mem_op, and the offset of mem_op is 00000000H.
Some 1- and 2-byte opcodes point to group numbers (shaded entries in the opcode map table). Group numbers
indicate that the instruction uses the reg/opcode bits in the ModR/M byte as an opcode extension (refer to Section
A.4).
A.2.4.2
Two-Byte Opcode Instructions
The two-byte opcode map shown in Table A-3 includes primary opcodes that are either two bytes or three bytes in
length. Primary opcodes that are 2 bytes in length begin with an escape opcode 0FH. The upper and lower four bits
of the second opcode byte are used to index a particular row and column in Table A-3.
Two-byte opcodes that are 3 bytes in length begin with a mandatory prefix (66H, F2H, or F3H) and the escape
opcode (0FH). The upper and lower four bits of the third byte are used to index a particular row and column in Table
A-3 (except when the second opcode byte is the 3-byte escape opcodes 38H or 3AH; in this situation refer to
Section A.2.4.3).
For each entry in the opcode map, the rules for interpreting the byte following the primary opcode fall into one of
the following cases:
•
A ModR/M byte is required and is interpreted according to the abbreviations listed in Section A.1 and Chapter
2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
The operand types are listed according to notations listed in Section A.2.
•
A ModR/M byte is required and includes an opcode extension in the reg field in the ModR/M byte. Use Table A-6
when interpreting the ModR/M byte.
•
Use of the ModR/M byte is reserved or undefined. This applies to entries that represent an instruction without
operands that are encoded using ModR/M (for example: 0F77H, EMMS).
Example A-2. Look-up Example for 2-Byte Opcodes
Look-up opcode 0FA4050000000003H for a SHLD instruction using Table A-3.
•
The opcode is located in row A, column 4. The location indicates a SHLD instruction with operands Ev, Gv, and
Ib. Interpret the operands as follows:
— Ev: The ModR/M byte follows the opcode to specify a word or doubleword operand.
— Gv: The reg field of the ModR/M byte selects a general-purpose register.
— Ib: Immediate data is encoded in the subsequent byte of the instruction.
•
The third byte is the ModR/M byte (05H). The mod and opcode/reg fields of ModR/M indicate that a 32-bit
displacement is used to locate the first operand in memory and eAX as the second operand.
•
The next part of the opcode is the 32-bit displacement for the destination memory operand (00000000H). The
last byte stores immediate byte that provides the count of the shift (03H).
•
By this breakdown, it has been shown that this opcode represents the instruction: SHLD DS:00000000H, EAX,
3.
A-4 Vol. 2D
OPCODE MAP
A.2.4.3
Three-Byte Opcode Instructions
The three-byte opcode maps shown in Table A-4 and Table A-5 includes primary opcodes that are either 3 or 4
bytes in length. Primary opcodes that are 3 bytes in length begin with two escape bytes 0F38H or 0F3A. The upper
and lower four bits of the third opcode byte are used to index a particular row and column in Table A-4 or Table A-5.
Three-byte opcodes that are 4 bytes in length begin with a mandatory prefix (66H, F2H, or F3H) and two escape
bytes (0F38H or 0F3AH). The upper and lower four bits of the fourth byte are used to index a particular row and
column in Table A-4 or Table A-5.
For each entry in the opcode map, the rules for interpreting the byte following the primary opcode fall into the
following case:
•
A ModR/M byte is required and is interpreted according to the abbreviations listed in A.1 and Chapter 2,
“Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. The
operand types are listed according to notations listed in Section A.2.
Example A-3. Look-up Example for 3-Byte Opcodes
Look-up opcode 660F3A0FC108H for a PALIGNR instruction using Table A-5.
•
66H is a prefix and 0F3AH indicate to use Table A-5. The opcode is located in row 0, column F indicating a
PALIGNR instruction with operands Vdq, Wdq, and Ib. Interpret the operands as follows:
— Vdq: The reg field of the ModR/M byte selects a 128-bit XMM register.
— Wdq: The R/M field of the ModR/M byte selects either a 128-bit XMM register or memory location.
— Ib: Immediate data is encoded in the subsequent byte of the instruction.
•
The next byte is the ModR/M byte (C1H). The reg field indicates that the first operand is XMM0. The mod shows
that the R/M field specifies a register and the R/M indicates that the second operand is XMM1.
•
•
The last byte is the immediate byte (08H).
By this breakdown, it has been shown that this opcode represents the instruction: PALIGNR XMM0, XMM1, 8.
A.2.4.4
VEX Prefix Instructions
Instructions that include a VEX prefix are organized relative to the 2-byte and 3-byte opcode maps, based on the
VEX.mmmmm field encoding of implied 0F, 0F38H, 0F3AH, respectively. Each entry in the opcode map of a VEXencoded instruction is based on the value of the opcode byte, similar to non-VEX-encoded instructions.
A VEX prefix includes several bit fields that encode implied 66H, F2H, F3H prefix functionality (VEX.pp) and
operand size/opcode information (VEX.L). See chapter 4 for details.
Opcode tables A2-A6 include both instructions with a VEX prefix and instructions without a VEX prefix. Many entries
are only made once, but represent both the VEX and non-VEX forms of the instruction. If the VEX prefix is present
all the operands are valid and the mnemonic is usually prefixed with a “v”. If the VEX prefix is not present the
VEX.vvvv operand is not available and the prefix “v” is dropped from the mnemonic.
A few instructions exist only in VEX form and these are marked with a superscript “v”.
Operand size of VEX prefix instructions can be determined by the operand type code. 128-bit vectors are indicated
by 'dq', 256-bit vectors are indicated by 'qq', and instructions with operands supporting either 128 or 256-bit,
determined by VEX.L, are indicated by 'x'. For example, the entry "VMOVUPD Vx,Wx" indicates both VEX.L=0 and
VEX.L=1 are supported.
Vol. 2D A-5
OPCODE MAP
A.2.5
Superscripts Utilized in Opcode Tables
Table A-1 contains notes on particular encodings. These notes are indicated in the following opcode maps by superscripts. Gray cells indicate instruction groupings.
Table A-1. Superscripts Utilized in Opcode Tables
Superscript
Symbol
Meaning of Symbol
1A
Bits 5, 4, and 3 of ModR/M byte used as an opcode extension (refer to Section A.4, “Opcode Extensions For One-Byte
And Two-byte Opcodes”).
1B
Use the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when deliberately trying to generate an invalid opcode
exception (#UD).
1C
Some instructions use the same two-byte opcode. If the instruction has variations, or the opcode represents
different instructions, the ModR/M byte will be used to differentiate the instruction. For the value of the ModR/M
byte needed to decode the instruction, see Table A-6.
i64
The instruction is invalid or not encodable in 64-bit mode. 40 through 4F (single-byte INC and DEC) are REX prefix
combinations when in 64-bit mode (use FE/FF Grp 4 and 5 for INC and DEC).
o64
Instruction is only available when in 64-bit mode.
d64
When in 64-bit mode, instruction defaults to 64-bit operand size and cannot encode 32-bit operand size.
f64
The operand size is forced to a 64-bit operand size when in 64-bit mode (prefixes that change operand size are
ignored for this instruction in 64-bit mode).
v
VEX form only exists. There is no legacy SSE form of the instruction. For Integer GPR instructions it means VEX
prefix required.
v1
VEX128 & SSE forms only exist (no VEX256), when can’t be inferred from the data size.
A.3
ONE, TWO, AND THREE-BYTE OPCODE MAPS
See Table A-2 through Table A-5 below. The tables are multiple page presentations. Rows and columns with
sequential relationships are placed on facing pages to make look-up tasks easier. Note that table footnotes are not
presented on each page. Table footnotes for each table are presented on the last page of the table.
A-6 Vol. 2D
OPCODE MAP
Table A-2. One-byte Opcode Map: (00H — F7H) *
0
1
2
0
Eb, Gb
Ev, Gv
Gb, Eb
Eb, Gb
Ev, Gv
Gb, Eb
Eb, Gb
Ev, Gv
Gb, Eb
Eb, Gb
Ev, Gv
Gb, Eb
1
AL, Ib
rAX, Iz
Gv, Ev
AL, Ib
rAX, Iz
Gv, Ev
AL, Ib
rAX, Iz
Gv, Ev
AL, Ib
rAX, Iz
6
7
PUSH
ESi64
POP
ESi64
PUSH
SSi64
POP
SSi64
SEG=ES
(Prefix)
DAAi64
SEG=SS
(Prefix)
AAAi64
eSI
REX.RX
eDI
REX.RXB
INCi64 general register / REXo64 Prefixes
eAX
REX
eCX
REX.B
eDX
REX.X
eBX
REX.XB
eSP
REX.R
eBP
REX.RB
PUSHd64 general register
5
rAX/r8
rCX/r9
rDX/r10
rBX/r11
rSP/r12
rBP/r13
rSI/r14
rDI/r15
PUSHAi64/
PUSHADi64
POPAi64/
POPADi64
BOUNDi64
Gv, Ma
ARPLi64
Ew, Gw
MOVSXDo64
Gv, Ev
SEG=FS
(Prefix)
SEG=GS
(Prefix)
Operand
Size
(Prefix)
Address
Size
(Prefix)
NZ/NE
BE/NA
NBE/A
Ev, Gv
Eb, Gb
Ev, Gv
Jccf64, Jb - Short-displacement jump on condition
7
O
NO
Eb, Ib
Ev, Iz
B/NAE/C
NB/AE/NC
Z/E
Eb, Ibi64
Ev, Ib
Eb, Gb
rCX/r9
rDX/r10
rBX/r11
Ov, rAX
Immediate Grp 11A
8
NOP
PAUSE(F3)
XCHG r8, rAX
TEST
XCHG
XCHG word, double-word or quad-word register with rAX
A
MOV
rSP/r12
rBP/r13
rSI/r14
rDI/r15
MOVS/B
Yb, Xb
MOVS/W/D/Q
Yv, Xv
CMPS/B
Xb, Yb
CMPS/W/D
Xv, Yv
DH/R14L, Ib
BH/R15L, Ib
AL, Ob
rAX, Ov
Ob, AL
AL/R8L, Ib
CL/R9L, Ib
DL/R10L, Ib
BL/R11L, Ib
AH/R12L, Ib
CH/R13L, Ib
near RETf64
Iw
near RETf64
LESi64
Gz, Mp
VEX+2byte
LDSi64
Gz, Mp
VEX+1byte
B
MOV immediate byte into byte register
Shift Grp 21A
C
Eb, Ib
Ev, Ib
D
F
Gv, Ev
XOR
4
E
5
AND
3
9
4
ADC
2
6
3
ADD
Shift Grp
21A
AAMi64
Eb, 1
Ev, 1
Eb, CL
Ev, CL
LOOPNEf64/
LOOPNZf64
Jb
LOOPEf64/
LOOPZf64
Jb
LOOPf64
Jb
JrCXZf64/
Jb
REPNE
XACQUIRE
(Prefix)
REP/REPE
XRELEASE
(Prefix)
LOCK
(Prefix)
AAD
Ib
Ib
Grp 111A - MOV
Eb, Ib
Ev, Iz
i64
XLAT/
XLATB
IN
OUT
AL, Ib
eAX, Ib
HLT
CMC
Ib, AL
Ib, eAX
Unary Grp 31A
Eb
Ev
Vol. 2D A-7
OPCODE MAP
Table A-2. One-byte Opcode Map: (08H — FFH) *
8
9
A
0
Eb, Gb
Ev, Gv
Gb, Eb
1
Ev, Gv
Gb, Eb
2
Eb, Gb
Ev, Gv
Gb, Eb
Eb, Gb
Ev, Gv
Gb, Eb
rAX, Iz
Gv, Ev
AL, Ib
rAX, Iz
Gv, Ev
AL, Ib
rAX, Iz
Gv, Ev
AL, Ib
rAX, Iz
F
2-byte
escape
(Table A-3)
PUSH
DSi64
POP
DSi64
SEG=CS
(Prefix)
DASi64
SEG=DS
(Prefix)
AASi64
eSI
REX.WRX
eDI
REX.WRXB
eAX
REX.W
eCX
REX.WB
eDX
REX.WX
rAX/r8
rCX/r9
rDX/r10
eBX
REX.WXB
eSP
REX.WR
eBP
REX.WRB
rBX/r11
rSP/r12
rBP/r13
rSI/r14
rDI/r15
PUSHd64
Iz
IMUL
Gv, Ev, Iz
PUSHd64
Ib
IMUL
Gv, Ev, Ib
INS/
INSB
Yb, DX
INS/
INSW/
INSD
Yz, DX
OUTS/
OUTSB
DX, Xb
OUTS/
OUTSW/
OUTSD
DX, Xz
S
NS
P/PE
L/NGE
NL/GE
LE/NG
NLE/G
MOV
Ev, Sw
LEA
Gv, M
MOV
Sw, Ew
Grp 1A1A POPd64
Ev
POPd64 into general register
Jccf64, Jb- Short displacement jump on condition
7
8
NP/PO
MOV
Eb, Gb
Ev, Gv
CBW/
CWDE/
CDQE
A
CWD/
CDQ/
CQO
TEST
Gb, Eb
Gv, Ev
FWAIT/
WAIT
PUSHF/D/Q d64/
Fv
POPF/D/Q d64/
Fv
SAHF
LAHF
Ap
STOS/B
Yb, AL
STOS/W/D/Q
Yv, rAX
LODS/B
AL, Xb
LODS/W/D/Q
rAX, Xv
SCAS/B
AL, Yb
SCAS/W/D/Q
rAX, Yv
far
CALLi64
AL, Ib
rAX, Iz
rAX/r8, Iv
rCX/r9, Iv
rDX/r10, Iv
rBX/r11, Iv
rSP/r12, Iv
rBP/r13, Iv
rSI/r14, Iv
rDI/r15 , Iv
ENTER
LEAVEd64
far RET
far RET
INT 3
INT
INTOi64
IRET/D/Q
B
MOV immediate word or double into word, double, or quad register
Iw, Ib
Iw
D
F
AL, Ib
E
PUSH
CSi64
DECi64 general register / REXo64 Prefixes
5
E
Gv, Ev
CMP
4
C
D
SUB
3
9
C
SBB
Eb, Gb
6
B
OR
Ib
ESC (Escape to coprocessor instruction set)
near CALLf64
JMP
IN
OUT
Jz
nearf64
Jz
fari64
Ap
shortf64
Jb
AL, DX
eAX, DX
DX, AL
DX, eAX
CLC
STC
CLI
STI
CLD
STD
INC/DEC
INC/DEC
Grp 41A
Grp 51A
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-8 Vol. 2D
OPCODE MAP
Table A-3. Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) *
pfx
0
1
2
3
Grp 61A
Grp 71A
LAR
Gv, Ew
LSL
Gv, Ew
vmovups
Vps, Wps
vmovups
Wps, Vps
vmovlps
Vq, Hq, Mq
vmovhlps
Vq, Hq, Uq
vmovlps
Mq, Vq
66
vmovupd
Vpd, Wpd
vmovupd
Wpd,Vpd
vmovlpd
Vq, Hq, Mq
vmovlpd
Mq, Vq
F3
vmovss
Vx, Hx, Wss
vmovss
Wss, Hx, Vss
vmovsldup
Vx, Wx
F2
vmovsd
Vx, Hx, Wsd
vmovsd
Wsd, Hx, Vsd
vmovddup
Vx, Wx
MOV
Rd, Cd
MOV
Rd, Dd
MOV
Cd, Rd
MOV
Dd, Rd
WRMSR
RDTSC
RDMSR
RDPMC
O
NO
B/C/NAE
AE/NB/NC
E/Z
NE/NZ
BE/NA
A/NBE
vmovmskps
Gy, Ups
vsqrtps
Vps, Wps
vrsqrtps
Vps, Wps
vrcpps
Vps, Wps
vandps
Vps, Hps, Wps
vandnps
Vps, Hps, Wps
vorps
Vps, Hps, Wps
vxorps
Vps, Hps, Wps
vmovmskpd
Gy,Upd
vsqrtpd
Vpd, Wpd
vandpd
Vpd, Hpd, Wpd
vandnpd
Vpd, Hpd, Wpd
vorpd
Vpd, Hpd, Wpd
vxorpd
Vpd, Hpd, Wpd
0
1
4
5
6
7
SYSCALLo64
CLTS
SYSRETo64
vunpcklps
Vx, Hx, Wx
vunpckhps
Vx, Hx, Wx
vmovhpsv1
Vdq, Hq, Mq
vmovlhps
Vdq, Hq, Uq
vmovhpsv1
Mq, Vq
vunpcklpd
Vx,Hx,Wx
vunpckhpd
Vx,Hx,Wx
vmovhpdv1
Vdq, Hq, Mq
vmovhpdv1
Mq, Vq
vmovshdup
Vx, Wx
2
3
SYSENTER
SYSEXIT
GETSEC
CMOVcc, (Gv, Ev) - Conditional Move
4
5
6
66
F3
vsqrtss
Vss, Hss, Wss
F2
vsqrtsd
Vsd, Hsd, Wsd
66
vrsqrtss
Vss, Hss, Wss
vrcpss
Vss, Hss, Wss
punpcklbw
Pq, Qd
punpcklwd
Pq, Qd
punpckldq
Pq, Qd
packsswb
Pq, Qq
pcmpgtb
Pq, Qq
pcmpgtw
Pq, Qq
pcmpgtd
Pq, Qq
packuswb
Pq, Qq
vpunpcklbw
Vx, Hx, Wx
vpunpcklwd
Vx, Hx, Wx
vpunpckldq
Vx, Hx, Wx
vpacksswb
Vx, Hx, Wx
vpcmpgtb
Vx, Hx, Wx
vpcmpgtw
Vx, Hx, Wx
vpcmpgtd
Vx, Hx, Wx
vpackuswb
Vx, Hx, Wx
pshufw
Pq, Qq, Ib
(Grp 121A)
(Grp 131A)
(Grp 141A)
pcmpeqb
Pq, Qq
pcmpeqw
Pq, Qq
pcmpeqd
Pq, Qq
emms
vzeroupperv
vzeroallv
vpcmpeqb
Vx, Hx, Wx
vpcmpeqw
Vx, Hx, Wx
vpcmpeqd
Vx, Hx, Wx
F3
7
66
vpshufd
Vx, Wx, Ib
F3
vpshufhw
Vx, Wx, Ib
F2
vpshuflw
Vx, Wx, Ib
Vol. 2D A-9
OPCODE MAP
Table A-3. Two-byte Opcode Map: 08H — 7FH (First Byte is 0FH) *
pfx
8
9
INVD
WBINVD
A
B
C
0
D
E
F
prefetchw(/1)
Ev
2-byte Illegal
Opcodes
UD21B
Prefetch1C
(Grp 161A)
NOP /0 Ev
1
66
2
vmovaps
Vps, Wps
vmovaps
Wps, Vps
cvtpi2ps
Vps, Qpi
vmovntps
Mps, Vps
cvttps2pi
Ppi, Wps
cvtps2pi
Ppi, Wps
vucomiss
Vss, Wss
vcomiss
Vss, Wss
vmovapd
Vpd, Wpd
vmovapd
Wpd,Vpd
cvtpi2pd
Vpd, Qpi
vmovntpd
Mpd, Vpd
cvttpd2pi
Ppi, Wpd
cvtpd2pi
Qpi, Wpd
vucomisd
Vsd, Wsd
vcomisd
Vsd, Wsd
F3
vcvtsi2ss
Vss, Hss, Ey
vcvttss2si
Gy, Wss
vcvtss2si
Gy, Wss
F2
vcvtsi2sd
Vsd, Hsd, Ey
vcvttsd2si
Gy, Wsd
vcvtsd2si
Gy, Wsd
3
3-byte escape
(Table A-4)
3-byte escape
(Table A-5)
4
S
NS
P/PE
NP/PO
L/NGE
NL/GE
LE/NG
NLE/G
vaddps
Vps, Hps, Wps
vmulps
Vps, Hps, Wps
vcvtps2pd
Vpd, Wps
vcvtdq2ps
Vps, Wdq
vsubps
Vps, Hps, Wps
vminps
Vps, Hps, Wps
vdivps
Vps, Hps, Wps
vmaxps
Vps, Hps, Wps
66
vaddpd
Vpd, Hpd, Wpd
vmulpd
Vpd, Hpd, Wpd
vcvtpd2ps
Vps, Wpd
vcvtps2dq
Vdq, Wps
vsubpd
Vpd, Hpd, Wpd
vminpd
Vpd, Hpd, Wpd
vdivpd
Vpd, Hpd, Wpd
vmaxpd
Vpd, Hpd, Wpd
F3
vaddss
Vss, Hss, Wss
vmulss
Vss, Hss, Wss
vcvtss2sd
Vsd, Hx, Wss
vcvttps2dq
Vdq, Wps
vsubss
Vss, Hss, Wss
vminss
Vss, Hss, Wss
vdivss
Vss, Hss, Wss
vmaxss
Vss, Hss, Wss
F2
vaddsd
Vsd, Hsd, Wsd
vmulsd
Vsd, Hsd, Wsd
vcvtsd2ss
Vss, Hx, Wsd
vsubsd
Vsd, Hsd, Wsd
vminsd
Vsd, Hsd, Wsd
vdivsd
Vsd, Hsd, Wsd
vmaxsd
Vsd, Hsd, Wsd
punpckhbw
Pq, Qd
punpckhwd
Pq, Qd
punpckhdq
Pq, Qd
packssdw
Pq, Qd
movd/q
Pd, Ey
movq
Pq, Qq
vpunpckhbw
Vx, Hx, Wx
vpunpckhwd
Vx, Hx, Wx
vpunpckhdq
Vx, Hx, Wx
vpackssdw
Vx, Hx, Wx
vmovd/q
Vy, Ey
vmovdqa
Vx, Wx
CMOVcc(Gv, Ev) - Conditional Move
5
6
66
vpunpcklqdq
Vx, Hx, Wx
vpunpckhqdq
Vx, Hx, Wx
vmovdqu
Vx, Wx
F3
VMREAD
Ey, Gy
66
7
VMWRITE
Gy, Ey
vhaddpd
Vpd, Hpd, Wpd
vhsubpd
Vpd, Hpd, Wpd
F3
F2
A-10 Vol. 2D
vhaddps
Vps, Hps, Wps
vhsubps
Vps, Hps, Wps
movd/q
Ey, Pd
movq
Qq, Pq
vmovd/q
Ey, Vy
vmovdqa
Wx,Vx
vmovq
Vq, Wq
vmovdqu
Wx,Vx
OPCODE MAP
Table A-3. Two-byte Opcode Map: 80H — F7H (First Byte is 0FH) *
pfx
0
1
2
3
4
5
6
7
NE/NZ
BE/NA
A/NBE
BE/NA
A/NBE
Jccf64, Jz - Long-displacement jump on condition
8
O
NO
B/CNAE
9
O
NO
B/C/NAE
AE/NB/NC
E/Z
NE/NZ
A
PUSHd64
FS
POPd64
FS
CPUID
BT
Ev, Gv
SHLD
Ev, Gv, Ib
SHLD
Ev, Gv, CL
B
Eb, Gb
Ev, Gv
LSS
Gv, Mp
BTR
Ev, Gv
LFS
Gv, Mp
LGS
Gv, Mp
XADD
Eb, Gb
XADD
Ev, Gv
vcmpps
Vps,Hps,Wps,Ib
movnti
My, Gy
pinsrw
Pq,Ry/Mw,Ib
AE/NB/NC
E/Z
SETcc, Eb - Byte Set on condition
CMPXCHG
66
vcmppd
Vpd,Hpd,Wpd,Ib
F3
vcmpss
Vss,Hss,Wss,Ib
F2
vcmpsd
Vsd,Hsd,Wsd,Ib
C
66
D
vaddsubpd
Vpd, Hpd, Wpd
Gv, Ew
pextrw
Gd, Nq, Ib
vshufps
Vps,Hps,Wps,Ib
Grp 91A
vpinsrw
Vdq,Hdq,Ry/Mw,Ib
vpextrw
Gd, Udq, Ib
vshufpd
Vpd,Hpd,Wpd,Ib
psrlw
Pq, Qq
psrld
Pq, Qq
psrlq
Pq, Qq
paddq
Pq, Qq
pmullw
Pq, Qq
vpsrlw
Vx, Hx, Wx
vpsrld
Vx, Hx, Wx
vpsrlq
Vx, Hx, Wx
vpaddq
Vx, Hx, Wx
vpmullw
Vx, Hx, Wx
66
E
F
pmovmskb
Gd, Nq
vmovq
Wq, Vq
vaddsubps
Vps, Hps, Wps
movdq2q
Pq, Uq
pavgb
Pq, Qq
psraw
Pq, Qq
psrad
Pq, Qq
pavgw
Pq, Qq
pmulhuw
Pq, Qq
pmulhw
Pq, Qq
vpavgb
Vx, Hx, Wx
vpsraw
Vx, Hx, Wx
vpsrad
Vx, Hx, Wx
vpavgw
Vx, Hx, Wx
vpmulhuw
Vx, Hx, Wx
vpmulhw
Vx, Hx, Wx
movntq
Mq, Pq
vcvttpd2dq
Vx, Wpd
F3
vcvtdq2pd
Vx, Wpd
F2
vcvtpd2dq
Vx, Wpd
66
F2
vpmovmskb
Gd, Ux
movq2dq
Vdq, Nq
F3
F2
MOVZX
Gv, Eb
vmovntdq
Mx, Vx
psllw
Pq, Qq
pslld
Pq, Qq
psllq
Pq, Qq
pmuludq
Pq, Qq
pmaddwd
Pq, Qq
psadbw
Pq, Qq
maskmovq
Pq, Nq
vpsllw
Vx, Hx, Wx
vpslld
Vx, Hx, Wx
vpsllq
Vx, Hx, Wx
vpmuludq
Vx, Hx, Wx
vpmaddwd
Vx, Hx, Wx
vpsadbw
Vx, Hx, Wx
vmaskmovdqu
Vdq, Udq
vlddqu
Vx, Mx
Vol. 2D A-11
OPCODE MAP
Table A-3. Two-byte Opcode Map: 88H — FFH (First Byte is 0FH) *
pfx
8
9
A
B
C
D
E
F
NL/GE
LE/NG
NLE/G
Jccf64, Jz - Long-displacement jump on condition
8
S
NS
P/PE
NP/PO
L/NGE
SETcc, Eb - Byte Set on condition
9
S
NS
P/PE
NP/PO
L/NGE
NL/GE
LE/NG
NLE/G
A
PUSHd64
GS
POPd64
GS
RSM
BTS
Ev, Gv
SHRD
Ev, Gv, Ib
SHRD
Ev, Gv, CL
(Grp 151A)1C
IMUL
Gv, Ev
JMPE
(reserved for
emulator on IPF)
Grp 101A
Invalid Opcode1B
Grp 81A
Ev, Ib
BTC
Ev, Gv
BSF
Gv, Ev
BSR
Gv, Ev
TZCNT
Gv, Ev
LZCNT
Gv, Ev
B
F3
POPCNT
Gv, Ev
MOVSX
Gv, Eb
Gv, Ew
BSWAP
RAX/EAX/
R8/R8D
RCX/ECX/
R9/R9D
RDX/EDX/
R10/R10D
RBX/EBX/
R11/R11D
RSP/ESP/
R12/R12D
RBP/EBP/
R13/R13D
RSI/ESI/
R14/R14D
RDI/EDI/
R15/R15D
psubusb
Pq, Qq
psubusw
Pq, Qq
pminub
Pq, Qq
pand
Pq, Qq
paddusb
Pq, Qq
paddusw
Pq, Qq
pmaxub
Pq, Qq
pandn
Pq, Qq
vpsubusb
Vx, Hx, Wx
vpsubusw
Vx, Hx, Wx
vpminub
Vx, Hx, Wx
vpand
Vx, Hx, Wx
vpaddusb
Vx, Hx, Wx
vpaddusw
Vx, Hx, Wx
vpmaxub
Vx, Hx, Wx
vpandn
Vx, Hx, Wx
psubsb
Pq, Qq
psubsw
Pq, Qq
pminsw
Pq, Qq
por
Pq, Qq
paddsb
Pq, Qq
paddsw
Pq, Qq
pmaxsw
Pq, Qq
pxor
Pq, Qq
vpsubsb
Vx, Hx, Wx
vpsubsw
Vx, Hx, Wx
vpminsw
Vx, Hx, Wx
vpor
Vx, Hx, Wx
vpaddsb
Vx, Hx, Wx
vpaddsw
Vx, Hx, Wx
vpmaxsw
Vx, Hx, Wx
vpxor
Vx, Hx, Wx
psubb
Pq, Qq
psubw
Pq, Qq
psubd
Pq, Qq
psubq
Pq, Qq
paddb
Pq, Qq
paddw
Pq, Qq
paddd
Pq, Qq
vpsubb
Vx, Hx, Wx
vpsubw
Vx, Hx, Wx
vpsubd
Vx, Hx, Wx
vpsubq
Vx, Hx, Wx
vpaddb
Vx, Hx, Wx
vpaddw
Vx, Hx, Wx
vpaddd
Vx, Hx, Wx
C
66
D
F3
F2
66
E
F3
F2
F
66
F2
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-12 Vol. 2D
OPCODE MAP
Table A-4. Three-byte Opcode Map: 00H — F7H (First Two Bytes are 0F 38H) *
pfx
0
pshufb
Pq, Qq
1
phaddw
Pq, Qq
2
phaddd
Pq, Qq
3
phaddsw
Pq, Qq
4
pmaddubsw
Pq, Qq
5
phsubw
Pq, Qq
6
phsubd
Pq, Qq
7
phsubsw
Pq, Qq
vpshufb
Vx, Hx, Wx
pblendvb
Vdq, Wdq
vphaddw
Vx, Hx, Wx
vphaddd
Vx, Hx, Wx
vphaddsw
Vx, Hx, Wx
vcvtph2psv
Vx, Wx, Ib
vpmaddubsw
Vx, Hx, Wx
blendvps
Vdq, Wdq
vphsubw
Vx, Hx, Wx
blendvpd
Vdq, Wdq
vphsubd
Vx, Hx, Wx
vpermpsv
Vqq, Hqq, Wqq
vphsubsw
Vx, Hx, Wx
vptest
Vx, Wx
vpmovsxbw
Vx, Ux/Mq
vpmovzxbw
Vx, Ux/Mq
vpmulld
Vx, Hx, Wx
vpmovsxbd
Vx, Ux/Md
vpmovzxbd
Vx, Ux/Md
vphminposuw
Vdq, Wdq
vpmovsxbq
Vx, Ux/Mw
vpmovzxbq
Vx, Ux/Mw
vpmovsxwd
Vx, Ux/Mq
vpmovzxwd
Vx, Ux/Mq
vpmovsxwq
Vx, Ux/Md
vpmovzxwq
Vx, Ux/Md
vpmovsxdq
Vx, Ux/Mq
vpmovzxdq
Vx, Ux/Mq
vpsrlvd/qv
Vx, Hx, Wx
vpermdv
Vqq, Hqq, Wqq
vpsravdv
Vx, Hx, Wx
vpcmpgtq
Vx, Hx, Wx
vpsllvd/qv
Vx, Hx, Wx
INVEPT
Gy, Mdq
INVVPID
Gy, Mdq
INVPCID
Gy, Mdq
vgatherdd/qv
Vx,Hx,Wx
vgatherqd/qv
Vx,Hx,Wx
vgatherdps/dv
Vx,Hx,Wx
vfmaddsub132ps/dv
Vx,Hx,Wx
vfmsubadd132ps/dv
Vx,Hx,Wx
vfmaddsub213ps/dv
Vx,Hx,Wx
vfmaddsub231ps/dv
Vx,Hx,Wx
vfmsubadd213ps/dv
Vx,Hx,Wx
vfmsubadd231ps/dv
Vx,Hx,Wx
ADCX
Gy, Ey
ADOX
Gy, Ey
MULXv
By,Gy,rDX,Ey
BEXTRv
Gy, Ey, By
SHLXv
Gy, Ey, By
SARXv
Gy, Ey, By
SHRXv
Gy, Ey, By
0
66
1
66
2
66
3
66
4
66
5
6
7
8
66
9
66
A
66
B
66
vgatherqps/dv
Vx,Hx,Wx
C
D
E
66
F
MOVBE
Gy, My
MOVBE
Gw, Mw
MOVBE
My, Gy
MOVBE
Mw, Gw
66 &
F2
BZHIv
Gy, Ey, By
Grp 171A
F3
F2
ANDNv
Gy, By, Ey
CRC32
Gd, Eb
CRC32
Gd, Eb
CRC32
Gd, Ey
CRC32
Gd, Ew
PEXTv
Gy, By, Ey
PDEPv
Gy, By, Ey
Vol. 2D A-13
OPCODE MAP
Table A-4. Three-byte Opcode Map: 08H — FFH (First Two Bytes are 0F 38H) *
pfx
0
66
8
9
A
B
psignb
Pq, Qq
psignw
Pq, Qq
psignd
Pq, Qq
pmulhrsw
Pq, Qq
vpsignb
Vx, Hx, Wx
vpsignw
Vx, Hx, Wx
vpsignd
Vx, Hx, Wx
vpmulhrsw
Vx, Hx, Wx
1
vbroadcastsdv Vqq, vbroadcastf128v Vqq,
Mdq
Wq
C
D
E
F
vpermilpsv
Vx,Hx,Wx
vpermilpdv
Vx,Hx,Wx
vtestpsv
Vx, Wx
vtestpdv
Vx, Wx
pabsb
Pq, Qq
pabsw
Pq, Qq
pabsd
Pq, Qq
vpabsb
Vx, Wx
vpabsw
Vx, Wx
vpabsd
Vx, Wx
66
vbroadcastssv
Vx, Wd
2
66
vpmuldq
Vx, Hx, Wx
vpcmpeqq
Vx, Hx, Wx
vmovntdqa
Vx, Mx
vpackusdw
Vx, Hx, Wx
vmaskmovpsv
Vx,Hx,Mx
vmaskmovpdv
Vx,Hx,Mx
vmaskmovpsv
Mx,Hx,Vx
vmaskmovpdv
Mx,Hx,Vx
3
66
vpminsb
Vx, Hx, Wx
vpminsd
Vx, Hx, Wx
vpminuw
Vx, Hx, Wx
vpminud
Vx, Hx, Wx
vpmaxsb
Vx, Hx, Wx
vpmaxsd
Vx, Hx, Wx
vpmaxuw
Vx, Hx, Wx
vpmaxud
Vx, Hx, Wx
66
vpbroadcastdv
Vx, Wx
vpbroadcastqv
Vx, Wx
vbroadcasti128v
7
66
vpbroadcastbv
Vx, Wx
vpbroadcastwv
Vx, Wx
8
66
9
66
vfmadd132ps/dv
Vx, Hx, Wx
vfmadd132ss/dv
Vx, Hx, Wx
vfmsub132ps/dv
Vx, Hx, Wx
vfmsub132ss/dv
Vx, Hx, Wx
vfnmadd132ps/dv
vfnmadd132ss/dv
vfnmsub132ps/dv
Vx, Hx, Wx
Vx, Hx, Wx
Vx, Hx, Wx
Vx, Hx, Wx
66
vfmadd213ps/dv
Vx, Hx, Wx
vfmadd213ss/dv
Vx, Hx, Wx
vfmsub213ps/dv
Vx, Hx, Wx
vfmsub213ss/dv
Vx, Hx, Wx
vfnmadd213ps/dv
vfnmadd213ss/dv
vfnmsub213ps/dv
vfnmsub213ss/dv
Vx, Hx, Wx
Vx, Hx, Wx
Vx, Hx, Wx
Vx, Hx, Wx
66
vfmadd231ps/dv
Vx, Hx, Wx
vfmadd231ss/dv
Vx, Hx, Wx
vfmsub231ps/dv
Vx, Hx, Wx
vfmsub231ss/dv
Vx, Hx, Wx
vfnmadd231ps/dv
vfnmadd231ss/dv
vfnmsub231ps/dv
vfnmsub231ss/dv
Vx, Hx, Wx
Vx, Hx, Wx
Vx, Hx, Wx
Vx, Hx, Wx
sha1nexte
Vdq,Wdq
sha1msg1
Vdq,Wdq
sha1msg2
Vdq,Wdq
sha256rnds2
Vdq,Wdq
sha256msg1
Vdq,Wdq
sha256msg2
Vdq,Wdq
VAESIMC
VAESENC
VAESENCLAST
VAESDEC
VAESDECLAST
Vdq, Wdq
Vdq,Hdq,Wdq
4
5
Vqq, Mdq
6
A
B
C
vpmaskmovd/qv
Vx,Hx,Mx
vpmaskmovd/qv
Mx,Vx,Hx
vfnmsub132ss/dv
66
D
66
Vdq,Hdq,Wdq
Vdq,Hdq,Wdq
Vdq,Hdq,Wdq
E
66
F
F3
F2
66 & F2
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-14 Vol. 2D
OPCODE MAP
Table A-5. Three-byte Opcode Map: 00H — F7H (First two bytes are 0F 3AH) *
pfx
0
66
1
66
2
66
0
1
2
vpermqv
Vqq, Wqq, Ib
vpermpdv
Vqq, Wqq, Ib
vpblenddv
Vx,Hx,Wx,Ib
vpinsrb
vinsertps
Vdq,Hdq,Ry/Mb,Ib Vdq,Hdq,Udq/Md,Ib
3
4
5
6
vpermilpsv
Vx, Wx, Ib
vpermilpdv
Vx, Wx, Ib
vperm2f128v
Vqq,Hqq,Wqq,Ib
vpextrb
Rd/Mb, Vdq, Ib
vpextrw
Rd/Mw, Vdq, Ib
vpextrd/q
Ey, Vdq, Ib
7
vextractps
Ed, Vdq, Ib
vpinsrd/q
Vdq,Hdq,Ey,Ib
3
4
66
vdpps
Vx,Hx,Wx,Ib
vdppd
Vdq,Hdq,Wdq,Ib
vmpsadbw
Vx,Hx,Wx,Ib
66
vpcmpestrm
Vdq, Wdq, Ib
vpcmpestri
Vdq, Wdq, Ib
vpcmpistrm
Vdq, Wdq, Ib
F2
RORXv
Gy, Ey, Ib
vpclmulqdq
Vdq,Hdq,Wdq,Ib
vperm2i128v
Vqq,Hqq,Wqq,Ib
5
6
vpcmpistri
Vdq, Wdq, Ib
7
8
9
A
B
C
D
E
F
Vol. 2D A-15
OPCODE MAP
Table A-5. Three-byte Opcode Map: 08H — FFH (First Two Bytes are 0F 3AH) *
pfx
8
9
A
B
C
D
E
0
vroundps
Vx,Wx,Ib
vroundpd
Vx,Wx,Ib
vinsertf128v
Vqq,Hqq,Wqq,Ib
vextractf128v
Wdq,Vqq,Ib
vinserti128v
Vqq,Hqq,Wqq,Ib
vextracti128v
Wdq,Vqq,Ib
66
1
F
palignr
Pq, Qq, Ib
66
vroundss
Vss,Wss,Ib
vroundsd
Vsd,Wsd,Ib
vblendps
Vx,Hx,Wx,Ib
vblendpd
Vx,Hx,Wx,Ib
vpblendw
Vx,Hx,Wx,Ib
vpalignr
Vx,Hx,Wx,Ib
vcvtps2phv
Wx, Vx, Ib
2
3
66
4
66
vblendvpsv
Vx,Hx,Wx,Lx
vblendvpdv
Vx,Hx,Wx,Lx
vpblendvbv
Vx,Hx,Wx,Lx
5
6
7
8
9
A
B
sha1rnds4
Vdq,Wdq,Ib
C
D
66
VAESKEYGEN
Vdq, Wdq, Ib
E
F
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-16 Vol. 2D
OPCODE MAP
A.4
OPCODE EXTENSIONS FOR ONE-BYTE AND TWO-BYTE OPCODES
Some 1-byte and 2-byte opcodes use bits 3-5 of the ModR/M byte (the nnn field in Figure A-1) as an extension of
the opcode.
mod
nnn
R/M
Figure A-1. ModR/M Byte nnn Field (Bits 5, 4, and 3)
Opcodes that have opcode extensions are indicated in Table A-6 and organized by group number. Group numbers
(from 1 to 16, second column) provide a table entry point. The encoding for the r/m field for each instruction can
be established using the third column of the table.
A.4.1
Opcode Look-up Examples Using Opcode Extensions
An Example is provided below.
Example A-4. Interpreting an ADD Instruction
An ADD instruction with a 1-byte opcode of 80H is a Group 1 instruction:
•
•
Table A-6 indicates that the opcode extension field encoded in the ModR/M byte for this instruction is 000B.
The r/m field can be encoded to access a register (11B) or a memory address using a specified addressing
mode (for example: mem = 00B, 01B, 10B).
Example A-5. Looking Up 0F01C3H
Look up opcode 0F01C3 for a VMRESUME instruction by using Table A-2, Table A-3 and Table A-6:
•
•
•
0F tells us that this instruction is in the 2-byte opcode map.
•
•
The Op/Reg bits [5,4,3] are 000B. This tells us to look in the 000 column for Group 7.
01 (row 0, column 1 in Table A-3) reveals that this opcode is in Group 7 of Table A-6.
C3 is the ModR/M byte. The first two bits of C3 are 11B. This tells us to look at the second of the Group 7 rows
in Table A-6.
Finally, the R/M bits [2,1,0] are 011B. This identifies the opcode as the VMRESUME instruction.
A.4.2
Opcode Extension Tables
See Table A-6 below.
Vol. 2D A-17
OPCODE MAP
Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group Number *
Encoding of Bits 5,4,3 of the ModR/M Byte (bits 2,1,0 in parenthesis)
Opcode
000
001
010
011
100
101
110
111
mem, 11B
ADD
OR
ADC
SBB
AND
SUB
XOR
CMP
mem, 11B
POP
mem, 11B
ROL
ROR
RCL
RCR
SHL/SAL
SHR
mem, 11B
TEST
Ib/Iz
NOT
NEG
MUL
AL/rAX
IMUL
AL/rAX
DIV
AL/rAX
mem, 11B
INC
Eb
DEC
Eb
mem, 11B
INC
Ev
DEC
Ev
near CALLf64
Ev
far CALL
Ep
near JMPf64
Ev
far JMP
Mp
PUSHd64
Ev
mem, 11B
SLDT
Rv/Mw
STR
Rv/Mw
LLDT
Ew
LTR
Ew
VERR
Ew
VERW
Ew
mem
SGDT
Ms
SIDT
Ms
LGDT
Ms
LIDT
Ms
SMSW
Mw/Rv
Group
Mod 7,6
80-83
1
8F
1A
C0,C1 reg, imm
D0, D1 reg, 1
D2, D3 reg, CL
2
F6, F7
3
FE
4
FF
5
0F 00
6
pfx
11B
0F 01
7
0F BA
8
9
11B
0F B9
10
BT
11
INVLPG
Mb
BTR
BTC
VMPTRLD
Mq
VMPTRST
Mq
VMCLEAR
Mq
F3
VMXON
Mq
RDRAND
Rv
F3
RDSEED
Rv
RDPID
Rd/q
mem
11B
MOV
Eb, Ib
11B
mem
C7
BTS
66
mem
C6
IDIV
AL/rAX
SWAPGS
o64(000)
RDTSCP (001)
CMPXCH8B Mq
CMPXCHG16B
Mdq
0F C7
LMSW
Ew
VMCALL (001)
MONITOR XGETBV (000)
XSETBV (001)
VMLAUNCH
(000)
(010)
MWAIT (001)
VMFUNC
VMRESUME
CLAC (010)
(100)
(011) VMXOFF STAC (011)
XEND (101)
(100)
ENCLS (111) XTEST (110)
ENCLU(111)
mem, 11B
mem
SAR
XABORT (000) Ib
MOV
Ev, Iz
11B
XBEGIN (000) Jz
mem
0F 71
12
11B
66
psrlw
Nq, Ib
psraw
Nq, Ib
psllw
Nq, Ib
vpsrlw
Hx,Ux,Ib
vpsraw
Hx,Ux,Ib
vpsllw
Hx,Ux,Ib
psrld
Nq, Ib
psrad
Nq, Ib
pslld
Nq, Ib
vpsrld
Hx,Ux,Ib
vpsrad
Hx,Ux,Ib
vpslld
Hx,Ux,Ib
mem
0F 72
13
11B
66
mem
0F 73
A-18 Vol. 2D
14
11B
psrlq
Nq, Ib
66
vpsrlq
Hx,Ux,Ib
psllq
Nq, Ib
vpsrldq
Hx,Ux,Ib
vpsllq
Hx,Ux,Ib
vpslldq
Hx,Ux,Ib
OPCODE MAP
Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group Number * (Contd.)
Encoding of Bits 5,4,3 of the ModR/M Byte (bits 2,1,0 in parenthesis)
Opcode
Group
0F AE
15
Mod 7,6
pfx
mem
F3
11B
0F 18
16
mem
111
000
001
010
011
100
101
110
fxsave
fxrstor
ldmxcsr
stmxcsr
XSAVE
XRSTOR
XSAVEOPT
clflush
lfence
mfence
sfence
RDFSBASE
Ry
RDGSBASE
Ry
WRFSBASE
Ry
WRGSBASE
Ry
prefetch
NTA
prefetch
T0
prefetch
T1
prefetch
T2
BLSRv
By, Ey
BLSMSKv
By, Ey
BLSIv
By, Ey
11B
VEX.0F38 F3
17
mem
11B
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
Vol. 2D A-19
OPCODE MAP
A.5
ESCAPE OPCODE INSTRUCTIONS
Opcode maps for coprocessor escape instruction opcodes (x87 floating-point instruction opcodes) are in Table A-7
through Table A-22. These maps are grouped by the first byte of the opcode, from D8-DF. Each of these opcodes
has a ModR/M byte. If the ModR/M byte is within the range of 00H-BFH, bits 3-5 of the ModR/M byte are used as
an opcode extension, similar to the technique used for 1-and 2-byte opcodes (see A.4). If the ModR/M byte is
outside the range of 00H through BFH, the entire ModR/M byte is used as an opcode extension.
A.5.1
Opcode Look-up Examples for Escape Instruction Opcodes
Examples are provided below.
Example A-6. Opcode with ModR/M Byte in the 00H through BFH Range
DD0504000000H can be interpreted as follows:
•
The instruction encoded with this opcode can be located in Section . Since the ModR/M byte (05H) is within the
00H through BFH range, bits 3 through 5 (000) of this byte indicate the opcode for an FLD double-real
instruction (see Table A-9).
•
The double-real value to be loaded is at 00000004H (the 32-bit displacement that follows and belongs to this
opcode).
Example A-7. Opcode with ModR/M Byte outside the 00H through BFH Range
D8C1H can be interpreted as follows:
•
This example illustrates an opcode with a ModR/M byte outside the range of 00H through BFH. The instruction
can be located in Section A.4.
•
In Table A-8, the ModR/M byte C1H indicates row C, column 1 (the FADD instruction using ST(0), ST(1) as
operands).
A.5.2
Escape Opcode Instruction Tables
Tables are listed below.
A.5.2.1
Escape Opcodes with D8 as First Byte
Table A-7 and A-8 contain maps for the escape instruction opcodes that begin with D8H. Table A-7 shows the map if the ModR/M
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-7. D8 Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte (refer to Figure A.4)
000B
001B
010B
011B
100B
101B
110B
111B
FADD
single-real
FMUL
single-real
FCOM
single-real
FCOMP
single-real
FSUB
single-real
FSUBR
single-real
FDIV
single-real
FDIVR
single-real
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-20 Vol. 2D
OPCODE MAP
Table A-8 shows the map if the ModR/M byte is outside the range of 00H-BFH. Here, the first digit of the ModR/M byte selects the
table row and the second digit selects the column.
Table A-8. D8 Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
C
4
5
6
7
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
FADD
D
FCOM
ST(0),ST(0)
ST(0),ST(1)
ST(0),T(2)
ST(0),ST(3)
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
E
ST(0),ST(4)
FSUB
F
FDIV
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
8
9
A
B
C
D
E
F
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
C
FMUL
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(0)
ST(0),ST(1)
ST(0),T(2)
ST(0),ST(3)
D
FCOMP
E
ST(0),ST(4)
FSUBR
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
F
ST(0),ST(4)
FDIVR
ST(0),ST(4)
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A.5.2.2
Escape Opcodes with D9 as First Byte
Table A-9 and A-10 contain maps for escape instruction opcodes that begin with D9H. Table A-9 shows the map if the ModR/M
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
.
Table A-9. D9 Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte
000B
FLD
single-real
001B
010B
011B
100B
101B
110B
111B
FST
single-real
FSTP
single-real
FLDENV
14/28 bytes
FLDCW
2 bytes
FSTENV
14/28 bytes
FSTCW
2 bytes
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
Vol. 2D A-21
OPCODE MAP
Table A-10 shows the map if the ModR/M byte is outside the range of 00H-BFH. Here, the first digit of the ModR/M byte selects
the table row and the second digit selects the column.
Table A-10. D9 Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
C
4
5
6
7
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
FTST
FXAM
FXTRACT
FPREM1
FDECSTP
FINCSTP
C
D
E
F
ST(0),ST(7)
FLD
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
D
FNOP
E
FCHS
FABS
F
F2XM1
FYL2X
FPTAN
FPATAN
8
9
A
B
C
FXCH
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
E
FLD1
FLDL2T
FLDL2E
FLDPI
FLDLG2
FLDLN2
FLDZ
F
FPREM
FYL2XP1
FSQRT
FSINCOS
FRNDINT
FSCALE
FSIN
D
FCOS
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A.5.2.3
Escape Opcodes with DA as First Byte
Table A-11 and A-12 contain maps for escape instruction opcodes that begin with DAH. Table A-11 shows the map if the ModR/M
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-11. DA Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte
000B
001B
010B
011B
100B
101B
110B
111B
FIADD
dword-integer
FIMUL
dword-integer
FICOM
dword-integer
FICOMP
dword-integer
FISUB
dword-integer
FISUBR
dword-integer
FIDIV
dword-integer
FIDIVR
dword-integer
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-22 Vol. 2D
OPCODE MAP
Table A-12 shows the map if the ModR/M byte is outside the range of 00H-BFH. Here, the first digit of the ModR/M byte selects
the table row and the second digit selects the column.
Table A-12. DA Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
C
4
5
6
7
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
FCMOVB
D
FCMOVBE
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
8
9
A
B
C
D
E
F
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
E
F
C
FCMOVE
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
D
FCMOVU
E
ST(0),ST(4)
FUCOMPP
F
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A.5.2.4
Escape Opcodes with DB as First Byte
Table A-13 and A-14 contain maps for escape instruction opcodes that begin with DBH. Table A-13 shows the map if the ModR/M
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-13. DB Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte
000B
001B
010B
011B
FILD
dword-integer
FISTTP
dword-integer
FIST
dword-integer
FISTP
dword-integer
100B
101B
FLD
extended-real
110B
111B
FSTP
extended-real
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
Vol. 2D A-23
OPCODE MAP
Table A-14 shows the map if the ModR/M byte is outside the range of 00H-BFH. Here, the first digit of the ModR/M byte selects
the table row and the second digit selects the column.
Table A-14. DB Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
C
4
5
6
7
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
FCMOVNB
D
FCMOVNBE
ST(0),ST(0)
ST(0),ST(1)
E
ST(0),ST(2)
ST(0),ST(3)
FCLEX
FINIT
F
ST(0),ST(4)
FCOMI
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
8
9
A
B
C
D
E
F
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
C
FCMOVNE
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
D
FCMOVNU
E
ST(0),ST(4)
FUCOMI
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(4)
F
NOTES:
*
All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A.5.2.5
Escape Opcodes with DC as First Byte
Table A-15 and A-16 contain maps for escape instruction opcodes that begin with DCH. Table A-15 shows the map if the ModR/M
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-15. DC Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte (refer to Figure A-1)
000B
001B
010B
011B
100B
101B
110B
111B
FADD
double-real
FMUL
double-real
FCOM
double-real
FCOMP
double-real
FSUB
double-real
FSUBR
double-real
FDIV
double-real
FDIVR
double-real
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-24 Vol. 2D
OPCODE MAP
Table A-16 shows the map if the ModR/M byte is outside the range of 00H-BFH. In this case the first digit of the ModR/M byte
selects the table row and the second digit selects the column.
Table A-16. DC Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
C
4
5
6
7
ST(4),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
FADD
D
E
FSUBR
F
ST(4),ST(0)
FDIVR
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
ST(4),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
8
9
A
B
C
D
E
F
ST(4),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
C
FMUL
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
D
E
FSUB
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
F
ST(4),ST(0)
FDIV
ST(4),ST(0)
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A.5.2.6
Escape Opcodes with DD as First Byte
Table A-17 and A-18 contain maps for escape instruction opcodes that begin with DDH. Table A-17 shows the map if the ModR/M
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-17. DD Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte
000B
001B
010B
011B
100B
FLD
double-real
FISTTP
integer64
FST
double-real
FSTP
double-real
FRSTOR
98/108bytes
101B
110B
111B
FSAVE
98/108bytes
FSTSW
2 bytes
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
Vol. 2D A-25
OPCODE MAP
Table A-18 shows the map if the ModR/M byte is outside the range of 00H-BFH. The first digit of the ModR/M byte selects the table
row and the second digit selects the column.
Table A-18. DD Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
ST(0)
ST(1)
ST(2)
ST(3)
C
4
5
6
7
ST(4)
ST(5)
ST(6)
ST(7)
ST(4)
ST(5)
ST(6)
ST(7)
FFREE
D
FST
ST(0)
ST(1)
ST(2)
ST(3)
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
ST(4),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
8
9
A
B
C
D
E
F
ST(0)
ST(1)
ST(2)
ST(3)
ST(4)
ST(5)
ST(6)
ST(7)
ST(4)
ST(5)
ST(6)
ST(7)
E
FUCOM
F
C
D
FSTP
E
FUCOMP
ST(0)
ST(1)
ST(2)
ST(3)
F
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A.5.2.7
Escape Opcodes with DE as First Byte
Table A-19 and A-20 contain opcode maps for escape instruction opcodes that begin with DEH. Table A-19 shows the opcode map
if the ModR/M byte is in the range of 00H-BFH. In this case, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-19. DE Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte
000B
001B
010B
011B
100B
101B
110B
111B
FIADD
word-integer
FIMUL
word-integer
FICOM
word-integer
FICOMP
word-integer
FISUB
word-integer
FISUBR
word-integer
FIDIV
word-integer
FIDIVR
word-integer
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-26 Vol. 2D
OPCODE MAP
Table A-20 shows the opcode map if the ModR/M byte is outside the range of 00H-BFH. The first digit of the ModR/M byte selects
the table row and the second digit selects the column.
Table A-20. DE Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
C
4
5
6
7
ST(4),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
FADDP
D
E
FSUBRP
F
ST(4),ST(0)
FDIVRP
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
ST(4),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
8
9
A
B
C
D
E
F
ST(4),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
ST(5),ST(0)
ST(6),ST(0)
ST(7),ST(0)
C
FMULP
ST(0),ST(0)
D
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
FCOMPP
E
FSUBP
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0)
ST(3),ST(0)
ST(0),ST(0)
ST(1),ST(0)
ST(2),ST(0).
ST(3),ST(0)
F
ST(4),ST(0)
FDIVP
ST(4),ST(0)
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A.5.2.8
Escape Opcodes with DF As First Byte
Table A-21 and A-22 contain the opcode maps for escape instruction opcodes that begin with DFH. Table A-21 shows the opcode
map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-21. DF Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte
000B
001B
010B
011B
100B
101B
110B
111B
FILD
word-integer
FISTTP
word-integer
FIST
word-integer
FISTP
word-integer
FBLD
packed-BCD
FILD
qword-integer
FBSTP
packed-BCD
FISTP
qword-integer
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
Vol. 2D A-27
OPCODE MAP
Table A-22 shows the opcode map if the ModR/M byte is outside the range of 00H-BFH. The first digit of the ModR/M byte selects
the table row and the second digit selects the column.
Table A-22. DF Opcode Map When ModR/M Byte is Outside 00H to BFH *
0
1
2
3
4
5
6
7
C
D
E
FSTSW
AX
F
FCOMIP
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
8
9
A
B
C
D
E
F
ST(0),ST(4)
ST(0),ST(5)
ST(0),ST(6)
ST(0),ST(7)
C
D
E
FUCOMIP
ST(0),ST(0)
ST(0),ST(1)
ST(0),ST(2)
ST(0),ST(3)
F
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
A-28 Vol. 2D
OPCODE MAP
as
w
e
ft
g
e
l
a
s p nally
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T
io
t
n
inte k.
n
bla
Vol. 2D A-29
OPCODE MAP
A-30 Vol. 2D
APPENDIX B
INSTRUCTION FORMATS AND ENCODINGS
This appendix provides machine instruction formats and encodings of IA-32 instructions. The first section describes
the IA-32 architecture’s machine instruction format. The remaining sections show the formats and encoding of
general-purpose, MMX, P6 family, SSE/SSE2/SSE3, x87 FPU instructions, and VMX instructions. Those instruction
formats also apply to Intel 64 architecture. Instruction formats used in 64-bit mode are provided as supersets of
the above.
B.1
MACHINE INSTRUCTION FORMAT
All Intel Architecture instructions are encoded using subsets of the general machine instruction format shown in
Figure B-1. Each instruction consists of:
•
•
an opcode
•
a displacement and an immediate data field (if required)
a register and/or address mode specifier consisting of the ModR/M byte and sometimes the scale-index-base
(SIB) byte (if required)
Legacy Prefixes
REX Prefixes
76543210
76543210
76543210
TTTTTTTT
TTTTTTTT
TTTTTTTT
Grp 1, Grp 2, (optional)
Grp 3, Grp 4
7-6
5-3
2-0
Mod Reg* R/M
7-6
1, 2, or 3 Byte Opcodes (T = Opcode
5-3
2-0
Scale Index Base
ModR/M Byte
SIB Byte
Register and/or Address
Mode Specifier
d32 | 16 | 8 | None
d32 | 16 | 8 | None
Address Displacement
Immediate Data
(4, 2, 1 Bytes or None) (4,2,1 Bytes or None)
NOTE:
* The Reg Field may be used as an
opcode extension field (TTT) and as a
way to encode diagnostic registers
(eee).
Figure B-1. General Machine Instruction Format
The following sections discuss this format.
B.1.1
Legacy Prefixes
The legacy prefixes noted in Figure B-1 include 66H, 67H, F2H and F3H. They are optional, except when F2H, F3H
and 66H are used in new instruction extensions. Legacy prefixes must be placed before REX prefixes.
Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A, for more information on legacy prefixes.
Vol. 2D B-1
INSTRUCTION FORMATS AND ENCODINGS
B.1.2
REX Prefixes
REX prefixes are a set of 16 opcodes that span one row of the opcode map and occupy entries 40H to 4FH. These
opcodes represent valid instructions (INC or DEC) in IA-32 operating modes and in compatibility mode. In 64-bit
mode, the same opcodes represent the instruction prefix REX and are not treated as individual instructions.
Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A, for more information on REX prefixes.
B.1.3
Opcode Fields
The primary opcode for an instruction is encoded in one to three bytes of the instruction. Within the primary
opcode, smaller encoding fields may be defined. These fields vary according to the class of operation being
performed.
Almost all instructions that refer to a register and/or memory operand have a register and/or address mode byte
following the opcode. This byte, the ModR/M byte, consists of the mod field (2 bits), the reg field (3 bits; this field
is sometimes an opcode extension), and the R/M field (3 bits). Certain encodings of the ModR/M byte indicate that
a second address mode byte, the SIB byte, must be used.
If the addressing mode specifies a displacement, the displacement value is placed immediately following the
ModR/M byte or SIB byte. Possible sizes are 8, 16, or 32 bits. If the instruction specifies an immediate value, the
immediate value follows any displacement bytes. The immediate, if specified, is always the last field of the instruction.
Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A, for more information on opcodes.
B.1.4
Special Fields
Table B-1 lists bit fields that appear in certain instructions, sometimes within the opcode bytes. All of these fields
(except the d bit) occur in the general-purpose instruction formats in Table B-13.
Table B-1. Special Fields Within Instruction Encodings
Field Name
reg
Description
Number of
Bits
General-register specifier (see Table B-4 or B-5).
3
w
Specifies if data is byte or full-sized, where full-sized is 16 or 32 bits (see Table B-6).
1
s
Specifies sign extension of an immediate field (see Table B-7).
1
sreg2
Segment register specifier for CS, SS, DS, ES (see Table B-8).
2
sreg3
Segment register specifier for CS, SS, DS, ES, FS, GS (see Table B-8).
3
eee
Specifies a special-purpose (control or debug) register (see Table B-9).
3
tttn
For conditional instructions, specifies a condition asserted or negated (see Table B-12).
4
Specifies direction of data operation (see Table B-11).
1
d
B-2 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
B.1.4.1
Reg Field (reg) for Non-64-Bit Modes
The reg field in the ModR/M byte specifies a general-purpose register operand. The group of registers specified is
modified by the presence and state of the w bit in an encoding (refer to Section B.1.4.3). Table B-2 shows the
encoding of the reg field when the w bit is not present in an encoding; Table B-3 shows the encoding of the reg field
when the w bit is present.
Table B-2. Encoding of reg Field When w Field is Not Present in Instruction
reg Field
Register Selected during
16-Bit Data Operations
Register Selected during
32-Bit Data Operations
000
AX
EAX
001
CX
ECX
010
DX
EDX
011
BX
EBX
100
SP
ESP
101
BP
EBP
110
SI
ESI
111
DI
EDI
Table B-3. Encoding of reg Field When w Field is Present in Instruction
Register Specified by reg Field
During 16-Bit Data Operations
Register Specified by reg Field
During 32-Bit Data Operations
Function of w Field
Function of w Field
reg
When w = 0
When w = 1
reg
When w = 0
When w = 1
000
AL
AX
000
AL
EAX
001
CL
CX
001
CL
ECX
010
DL
DX
010
DL
EDX
011
BL
BX
011
BL
EBX
100
AH
SP
100
AH
ESP
101
CH
BP
101
CH
EBP
110
DH
SI
110
DH
ESI
111
BH
DI
111
BH
EDI
Vol. 2D B-3
INSTRUCTION FORMATS AND ENCODINGS
B.1.4.2
Reg Field (reg) for 64-Bit Mode
Just like in non-64-bit modes, the reg field in the ModR/M byte specifies a general-purpose register operand. The
group of registers specified is modified by the presence of and state of the w bit in an encoding (refer to Section
B.1.4.3). Table B-4 shows the encoding of the reg field when the w bit is not present in an encoding; Table B-5
shows the encoding of the reg field when the w bit is present.
Table B-4. Encoding of reg Field When w Field is Not Present in Instruction
reg Field
Register Selected during
16-Bit Data Operations
Register Selected during
32-Bit Data Operations
Register Selected during
64-Bit Data Operations
000
AX
EAX
RAX
001
CX
ECX
RCX
010
DX
EDX
RDX
011
BX
EBX
RBX
100
SP
ESP
RSP
101
BP
EBP
RBP
110
SI
ESI
RSI
111
DI
EDI
RDI
Table B-5. Encoding of reg Field When w Field is Present in Instruction
Register Specified by reg Field
During 16-Bit Data Operations
Register Specified by reg Field
During 32-Bit Data Operations
Function of w Field
Function of w Field
reg
When w = 0
When w = 1
reg
When w = 0
When w = 1
000
AL
AX
000
AL
EAX
001
CL
CX
001
CL
ECX
010
DL
DX
010
DL
EDX
011
BL
BX
011
BL
EBX
100
AH1
SP
100
AH*
ESP
101
CH1
BP
101
CH*
EBP
110
DH1
SI
110
DH*
ESI
111
1
DI
111
BH*
EDI
BH
NOTES:
1. AH, CH, DH, BH can not be encoded when REX prefix is used. Such an expression defaults to the low byte.
B.1.4.3
Encoding of Operand Size (w) Bit
The current operand-size attribute determines whether the processor is performing 16-bit, 32-bit or 64-bit operations. Within the constraints of the current operand-size attribute, the operand-size bit (w) can be used to indicate
operations on 8-bit operands or the full operand size specified with the operand-size attribute. Table B-6 shows the
encoding of the w bit depending on the current operand-size attribute.
Table B-6. Encoding of Operand Size (w) Bit
w Bit
Operand Size When
Operand-Size Attribute is 16 Bits
Operand Size When
Operand-Size Attribute is 32 Bits
0
8 Bits
8 Bits
1
16 Bits
32 Bits
B-4 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
B.1.4.4
Sign-Extend (s) Bit
The sign-extend (s) bit occurs in instructions with immediate data fields that are being extended from 8 bits to 16
or 32 bits. See Table B-7.
Table B-7. Encoding of Sign-Extend (s) Bit
Effect on 8-Bit
Immediate Data
s
Effect on 16- or 32-Bit
Immediate Data
0
None
None
1
Sign-extend to fill 16-bit or 32-bit destination
None
B.1.4.5
Segment Register (sreg) Field
When an instruction operates on a segment register, the reg field in the ModR/M byte is called the sreg field and is
used to specify the segment register. Table B-8 shows the encoding of the sreg field. This field is sometimes a 2-bit
field (sreg2) and other times a 3-bit field (sreg3).
Table B-8. Encoding of the Segment Register (sreg) Field
2-Bit sreg2 Field
Segment Register Selected
3-Bit sreg3 Field
Segment Register Selected
00
ES
000
ES
01
CS
001
CS
10
SS
010
SS
11
DS
011
DS
100
FS
101
GS
110
Reserved1
111
Reserved
NOTES:
1. Do not use reserved encodings.
B.1.4.6
Special-Purpose Register (eee) Field
When control or debug registers are referenced in an instruction they are encoded in the eee field, located in bits 5
though 3 of the ModR/M byte (an alternate encoding of the sreg field). See Table B-9.
Table B-9. Encoding of Special-Purpose Register (eee) Field
eee
Control Register
Debug Register
000
CR0
DR0
1
DR1
001
Reserved
010
CR2
DR2
011
CR3
DR3
100
CR4
Reserved
101
Reserved
Reserved
110
Reserved
DR6
111
Reserved
DR7
NOTES:
1. Do not use reserved encodings.
Vol. 2D B-5
INSTRUCTION FORMATS AND ENCODINGS
B.1.4.7
Condition Test (tttn) Field
For conditional instructions (such as conditional jumps and set on condition), the condition test field (tttn) is
encoded for the condition being tested. The ttt part of the field gives the condition to test and the n part indicates
whether to use the condition (n = 0) or its negation (n = 1).
•
•
For 1-byte primary opcodes, the tttn field is located in bits 3, 2, 1, and 0 of the opcode byte.
For 2-byte primary opcodes, the tttn field is located in bits 3, 2, 1, and 0 of the second opcode byte.
Table B-10 shows the encoding of the tttn field.
Table B-10. Encoding of Conditional Test (tttn) Field
tttn
B.1.4.8
Mnemonic
Condition
0000
O
Overflow
0001
NO
No overflow
0010
B, NAE
Below, Not above or equal
0011
NB, AE
Not below, Above or equal
0100
E, Z
Equal, Zero
0101
NE, NZ
Not equal, Not zero
0110
BE, NA
Below or equal, Not above
0111
NBE, A
Not below or equal, Above
1000
S
Sign
1001
NS
Not sign
1010
P, PE
Parity, Parity Even
1011
NP, PO
Not parity, Parity Odd
1100
L, NGE
Less than, Not greater than or equal to
1101
NL, GE
Not less than, Greater than or equal to
1110
LE, NG
Less than or equal to, Not greater than
1111
NLE, G
Not less than or equal to, Greater than
Direction (d) Bit
In many two-operand instructions, a direction bit (d) indicates which operand is considered the source and which
is the destination. See Table B-11.
•
When used for integer instructions, the d bit is located at bit 1 of a 1-byte primary opcode. Note that this bit
does not appear as the symbol “d” in Table B-13; the actual encoding of the bit as 1 or 0 is given.
•
When used for floating-point instructions (in Table B-16), the d bit is shown as bit 2 of the first byte of the
primary opcode.
Table B-11. Encoding of Operation Direction (d) Bit
d
Source
Destination
0
reg Field
ModR/M or SIB Byte
1
ModR/M or SIB Byte
reg Field
B.1.5
Other Notes
Table B-12 contains notes on particular encodings. These notes are indicated in the tables shown in the following
sections by superscripts.
B-6 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-12. Notes on Instruction Encoding
Symbol
Note
A
A value of 11B in bits 7 and 6 of the ModR/M byte is reserved.
B
A value of 01B (or 10B) in bits 7 and 6 of the ModR/M byte is reserved.
B.2
GENERAL-PURPOSE INSTRUCTION FORMATS AND ENCODINGS FOR NON64-BIT MODES
Table B-13 shows machine instruction formats and encodings for general purpose instructions in non-64-bit
modes.
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes
Instruction and Format
Encoding
AAA – ASCII Adjust after Addition
0011 0111
AAD – ASCII Adjust AX before Division
1101 0101 : 0000 1010
AAM – ASCII Adjust AX after Multiply
1101 0100 : 0000 1010
AAS – ASCII Adjust AL after Subtraction
0011 1111
ADC – ADD with Carry
register1 to register2
0001 000w : 11 reg1 reg2
register2 to register1
0001 001w : 11 reg1 reg2
memory to register
0001 001w : mod reg r/m
register to memory
0001 000w : mod reg r/m
immediate to register
1000 00sw : 11 010 reg : immediate data
immediate to AL, AX, or EAX
0001 010w : immediate data
immediate to memory
1000 00sw : mod 010 r/m : immediate data
ADD – Add
register1 to register2
0000 000w : 11 reg1 reg2
register2 to register1
0000 001w : 11 reg1 reg2
memory to register
0000 001w : mod reg r/m
register to memory
0000 000w : mod reg r/m
immediate to register
1000 00sw : 11 000 reg : immediate data
immediate to AL, AX, or EAX
0000 010w : immediate data
immediate to memory
1000 00sw : mod 000 r/m : immediate data
AND – Logical AND
register1 to register2
0010 000w : 11 reg1 reg2
register2 to register1
0010 001w : 11 reg1 reg2
memory to register
0010 001w : mod reg r/m
register to memory
0010 000w : mod reg r/m
immediate to register
1000 00sw : 11 100 reg : immediate data
immediate to AL, AX, or EAX
0010 010w : immediate data
immediate to memory
1000 00sw : mod 100 r/m : immediate data
Vol. 2D B-7
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
ARPL – Adjust RPL Field of Selector
from register
0110 0011 : 11 reg1 reg2
from memory
0110 0011 : mod reg r/m
BOUND – Check Array Against Bounds
0110 0010 : modA reg r/m
BSF – Bit Scan Forward
register1, register2
0000 1111 : 1011 1100 : 11 reg1 reg2
memory, register
0000 1111 : 1011 1100 : mod reg r/m
BSR – Bit Scan Reverse
register1, register2
0000 1111 : 1011 1101 : 11 reg1 reg2
memory, register
0000 1111 : 1011 1101 : mod reg r/m
BSWAP – Byte Swap
0000 1111 : 1100 1 reg
BT – Bit Test
register, immediate
0000 1111 : 1011 1010 : 11 100 reg: imm8 data
memory, immediate
0000 1111 : 1011 1010 : mod 100 r/m : imm8 data
register1, register2
0000 1111 : 1010 0011 : 11 reg2 reg1
memory, reg
0000 1111 : 1010 0011 : mod reg r/m
BTC – Bit Test and Complement
register, immediate
0000 1111 : 1011 1010 : 11 111 reg: imm8 data
memory, immediate
0000 1111 : 1011 1010 : mod 111 r/m : imm8 data
register1, register2
0000 1111 : 1011 1011 : 11 reg2 reg1
memory, reg
0000 1111 : 1011 1011 : mod reg r/m
BTR – Bit Test and Reset
register, immediate
0000 1111 : 1011 1010 : 11 110 reg: imm8 data
memory, immediate
0000 1111 : 1011 1010 : mod 110 r/m : imm8 data
register1, register2
0000 1111 : 1011 0011 : 11 reg2 reg1
memory, reg
0000 1111 : 1011 0011 : mod reg r/m
BTS – Bit Test and Set
register, immediate
0000 1111 : 1011 1010 : 11 101 reg: imm8 data
memory, immediate
0000 1111 : 1011 1010 : mod 101 r/m : imm8 data
register1, register2
0000 1111 : 1010 1011 : 11 reg2 reg1
memory, reg
0000 1111 : 1010 1011 : mod reg r/m
CALL – Call Procedure (in same segment)
direct
1110 1000 : full displacement
register indirect
1111 1111 : 11 010 reg
memory indirect
1111 1111 : mod 010 r/m
CALL – Call Procedure (in other segment)
direct
1001 1010 : unsigned full offset, selector
indirect
1111 1111 : mod 011 r/m
B-8 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
CBW – Convert Byte to Word
1001 1000
CDQ – Convert Doubleword to Qword
1001 1001
CLC – Clear Carry Flag
1111 1000
CLD – Clear Direction Flag
1111 1100
CLI – Clear Interrupt Flag
1111 1010
CLTS – Clear Task-Switched Flag in CR0
0000 1111 : 0000 0110
CMC – Complement Carry Flag
1111 0101
CMP – Compare Two Operands
register1 with register2
0011 100w : 11 reg1 reg2
register2 with register1
0011 101w : 11 reg1 reg2
memory with register
0011 100w : mod reg r/m
register with memory
0011 101w : mod reg r/m
immediate with register
1000 00sw : 11 111 reg : immediate data
immediate with AL, AX, or EAX
0011 110w : immediate data
immediate with memory
1000 00sw : mod 111 r/m : immediate data
CMPS/CMPSB/CMPSW/CMPSD – Compare String Operands
1010 011w
CMPXCHG – Compare and Exchange
register1, register2
0000 1111 : 1011 000w : 11 reg2 reg1
memory, register
0000 1111 : 1011 000w : mod reg r/m
CPUID – CPU Identification
0000 1111 : 1010 0010
CWD – Convert Word to Doubleword
1001 1001
CWDE – Convert Word to Doubleword
1001 1000
DAA – Decimal Adjust AL after Addition
0010 0111
DAS – Decimal Adjust AL after Subtraction
0010 1111
DEC – Decrement by 1
register
1111 111w : 11 001 reg
register (alternate encoding)
0100 1 reg
memory
1111 111w : mod 001 r/m
DIV – Unsigned Divide
AL, AX, or EAX by register
1111 011w : 11 110 reg
AL, AX, or EAX by memory
1111 011w : mod 110 r/m
HLT – Halt
1111 0100
IDIV – Signed Divide
AL, AX, or EAX by register
1111 011w : 11 111 reg
AL, AX, or EAX by memory
1111 011w : mod 111 r/m
Vol. 2D B-9
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
IMUL – Signed Multiply
AL, AX, or EAX with register
1111 011w : 11 101 reg
AL, AX, or EAX with memory
1111 011w : mod 101 reg
register1 with register2
0000 1111 : 1010 1111 : 11 : reg1 reg2
register with memory
0000 1111 : 1010 1111 : mod reg r/m
register1 with immediate to register2
0110 10s1 : 11 reg1 reg2 : immediate data
memory with immediate to register
0110 10s1 : mod reg r/m : immediate data
IN – Input From Port
fixed port
1110 010w : port number
variable port
1110 110w
INC – Increment by 1
reg
1111 111w : 11 000 reg
reg (alternate encoding)
0100 0 reg
memory
1111 111w : mod 000 r/m
INS – Input from DX Port
0110 110w
INT n – Interrupt Type n
1100 1101 : type
INT – Single-Step Interrupt 3
1100 1100
INTO – Interrupt 4 on Overflow
1100 1110
INVD – Invalidate Cache
0000 1111 : 0000 1000
INVLPG – Invalidate TLB Entry
0000 1111 : 0000 0001 : mod 111 r/m
INVPCID – Invalidate Process-Context Identifier
0110 0110:0000 1111:0011 1000:1000 0010: mod reg r/m
IRET/IRETD – Interrupt Return
1100 1111
Jcc – Jump if Condition is Met
8-bit displacement
0111 tttn : 8-bit displacement
full displacement
0000 1111 : 1000 tttn : full displacement
JCXZ/JECXZ – Jump on CX/ECX Zero
Address-size prefix differentiates JCXZ
and JECXZ
1110 0011 : 8-bit displacement
JMP – Unconditional Jump (to same segment)
short
1110 1011 : 8-bit displacement
direct
1110 1001 : full displacement
register indirect
1111 1111 : 11 100 reg
memory indirect
1111 1111 : mod 100 r/m
JMP – Unconditional Jump (to other segment)
direct intersegment
1110 1010 : unsigned full offset, selector
indirect intersegment
1111 1111 : mod 101 r/m
LAHF – Load Flags into AHRegister
B-10 Vol. 2D
1001 1111
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
LAR – Load Access Rights Byte
from register
0000 1111 : 0000 0010 : 11 reg1 reg2
from memory
0000 1111 : 0000 0010 : mod reg r/m
LDS – Load Pointer to DS
1100 0101 : modA,B reg r/m
LEA – Load Effective Address
1000 1101 : modA reg r/m
LEAVE – High Level Procedure Exit
1100 1001
LES – Load Pointer to ES
1100 0100 : modA,B reg r/m
LFS – Load Pointer to FS
0000 1111 : 1011 0100 : modA reg r/m
LGDT – Load Global Descriptor Table Register
0000 1111 : 0000 0001 : modA 010 r/m
LGS – Load Pointer to GS
0000 1111 : 1011 0101 : modA reg r/m
LIDT – Load Interrupt Descriptor Table Register
0000 1111 : 0000 0001 : modA 011 r/m
LLDT – Load Local Descriptor Table Register
LDTR from register
0000 1111 : 0000 0000 : 11 010 reg
LDTR from memory
0000 1111 : 0000 0000 : mod 010 r/m
LMSW – Load Machine Status Word
from register
0000 1111 : 0000 0001 : 11 110 reg
from memory
0000 1111 : 0000 0001 : mod 110 r/m
LOCK – Assert LOCK# Signal Prefix
1111 0000
LODS/LODSB/LODSW/LODSD – Load String Operand
1010 110w
LOOP – Loop Count
1110 0010 : 8-bit displacement
LOOPZ/LOOPE – Loop Count while Zero/Equal
1110 0001 : 8-bit displacement
LOOPNZ/LOOPNE – Loop Count while not Zero/Equal
1110 0000 : 8-bit displacement
LSL – Load Segment Limit
from register
0000 1111 : 0000 0011 : 11 reg1 reg2
from memory
0000 1111 : 0000 0011 : mod reg r/m
LSS – Load Pointer to SS
0000 1111 : 1011 0010 : modA reg r/m
LTR – Load Task Register
from register
0000 1111 : 0000 0000 : 11 011 reg
from memory
0000 1111 : 0000 0000 : mod 011 r/m
MOV – Move Data
register1 to register2
1000 100w : 11 reg1 reg2
register2 to register1
1000 101w : 11 reg1 reg2
memory to reg
1000 101w : mod reg r/m
reg to memory
1000 100w : mod reg r/m
immediate to register
1100 011w : 11 000 reg : immediate data
immediate to register (alternate encoding)
1011 w reg : immediate data
immediate to memory
1100 011w : mod 000 r/m : immediate data
memory to AL, AX, or EAX
1010 000w : full displacement
Vol. 2D B-11
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
AL, AX, or EAX to memory
Encoding
1010 001w : full displacement
MOV – Move to/from Control Registers
CR0 from register
0000 1111 : 0010 0010 : -- 000 reg
CR2 from register
0000 1111 : 0010 0010 : -- 010reg
CR3 from register
0000 1111 : 0010 0010 : -- 011 reg
CR4 from register
0000 1111 : 0010 0010 : -- 100 reg
register from CR0-CR4
0000 1111 : 0010 0000 : -- eee reg
MOV – Move to/from Debug Registers
DR0-DR3 from register
0000 1111 : 0010 0011 : -- eee reg
DR4-DR5 from register
0000 1111 : 0010 0011 : -- eee reg
DR6-DR7 from register
0000 1111 : 0010 0011 : -- eee reg
register from DR6-DR7
0000 1111 : 0010 0001 : -- eee reg
register from DR4-DR5
0000 1111 : 0010 0001 : -- eee reg
register from DR0-DR3
0000 1111 : 0010 0001 : -- eee reg
MOV – Move to/from Segment Registers
register to segment register
1000 1110 : 11 sreg3 reg
register to SS
1000 1110 : 11 sreg3 reg
memory to segment reg
1000 1110 : mod sreg3 r/m
memory to SS
1000 1110 : mod sreg3 r/m
segment register to register
1000 1100 : 11 sreg3 reg
segment register to memory
1000 1100 : mod sreg3 r/m
MOVBE – Move data after swapping bytes
memory to register
0000 1111 : 0011 1000:1111 0000 : mod reg r/m
register to memory
0000 1111 : 0011 1000:1111 0001 : mod reg r/m
MOVS/MOVSB/MOVSW/MOVSD – Move Data from String to
String
1010 010w
MOVSX – Move with Sign-Extend
memory to reg
0000 1111 : 1011 111w : mod reg r/m
MOVZX – Move with Zero-Extend
register2 to register1
0000 1111 : 1011 011w : 11 reg1 reg2
memory to register
0000 1111 : 1011 011w : mod reg r/m
MUL – Unsigned Multiply
AL, AX, or EAX with register
1111 011w : 11 100 reg
AL, AX, or EAX with memory
1111 011w : mod 100 r/m
NEG – Two's Complement Negation
register
1111 011w : 11 011 reg
memory
1111 011w : mod 011 r/m
NOP – No Operation
B-12 Vol. 2D
1001 0000
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
NOP – Multi-byte No Operation1
register
0000 1111 0001 1111 : 11 000 reg
memory
0000 1111 0001 1111 : mod 000 r/m
NOT – One's Complement Negation
register
1111 011w : 11 010 reg
memory
1111 011w : mod 010 r/m
OR – Logical Inclusive OR
register1 to register2
0000 100w : 11 reg1 reg2
register2 to register1
0000 101w : 11 reg1 reg2
memory to register
0000 101w : mod reg r/m
register to memory
0000 100w : mod reg r/m
immediate to register
1000 00sw : 11 001 reg : immediate data
immediate to AL, AX, or EAX
0000 110w : immediate data
immediate to memory
1000 00sw : mod 001 r/m : immediate data
OUT – Output to Port
fixed port
1110 011w : port number
variable port
1110 111w
OUTS – Output to DX Port
0110 111w
POP – Pop a Word from the Stack
register
1000 1111 : 11 000 reg
register (alternate encoding)
0101 1 reg
memory
1000 1111 : mod 000 r/m
POP – Pop a Segment Register from the Stack
(Note: CS cannot be sreg2 in this usage.)
segment register DS, ES
000 sreg2 111
segment register SS
000 sreg2 111
segment register FS, GS
0000 1111: 10 sreg3 001
POPA/POPAD – Pop All General Registers
0110 0001
POPF/POPFD – Pop Stack into FLAGS or EFLAGS Register
1001 1101
PUSH – Push Operand onto the Stack
register
1111 1111 : 11 110 reg
register (alternate encoding)
0101 0 reg
memory
1111 1111 : mod 110 r/m
immediate
0110 10s0 : immediate data
PUSH – Push Segment Register onto the Stack
segment register CS,DS,ES,SS
000 sreg2 110
segment register FS,GS
0000 1111: 10 sreg3 000
Vol. 2D B-13
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
PUSHA/PUSHAD – Push All General Registers
0110 0000
PUSHF/PUSHFD – Push Flags Register onto the Stack
1001 1100
RCL – Rotate thru Carry Left
register by 1
1101 000w : 11 010 reg
memory by 1
1101 000w : mod 010 r/m
register by CL
1101 001w : 11 010 reg
memory by CL
1101 001w : mod 010 r/m
register by immediate count
1100 000w : 11 010 reg : imm8 data
memory by immediate count
1100 000w : mod 010 r/m : imm8 data
RCR – Rotate thru Carry Right
register by 1
1101 000w : 11 011 reg
memory by 1
1101 000w : mod 011 r/m
register by CL
1101 001w : 11 011 reg
memory by CL
1101 001w : mod 011 r/m
register by immediate count
1100 000w : 11 011 reg : imm8 data
memory by immediate count
1100 000w : mod 011 r/m : imm8 data
RDMSR – Read from Model-Specific Register
0000 1111 : 0011 0010
RDPMC – Read Performance Monitoring Counters
0000 1111 : 0011 0011
RDTSC – Read Time-Stamp Counter
0000 1111 : 0011 0001
RDTSCP – Read Time-Stamp Counter and Processor ID
0000 1111 : 0000 0001: 1111 1001
REP INS – Input String
1111 0011 : 0110 110w
REP LODS – Load String
1111 0011 : 1010 110w
REP MOVS – Move String
1111 0011 : 1010 010w
REP OUTS – Output String
1111 0011 : 0110 111w
REP STOS – Store String
1111 0011 : 1010 101w
REPE CMPS – Compare String
1111 0011 : 1010 011w
REPE SCAS – Scan String
1111 0011 : 1010 111w
REPNE CMPS – Compare String
1111 0010 : 1010 011w
REPNE SCAS – Scan String
1111 0010 : 1010 111w
RET – Return from Procedure (to same segment)
no argument
1100 0011
adding immediate to SP
1100 0010 : 16-bit displacement
RET – Return from Procedure (to other segment)
intersegment
1100 1011
adding immediate to SP
1100 1010 : 16-bit displacement
B-14 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
ROL – Rotate Left
register by 1
1101 000w : 11 000 reg
memory by 1
1101 000w : mod 000 r/m
register by CL
1101 001w : 11 000 reg
memory by CL
1101 001w : mod 000 r/m
register by immediate count
1100 000w : 11 000 reg : imm8 data
memory by immediate count
1100 000w : mod 000 r/m : imm8 data
ROR – Rotate Right
register by 1
1101 000w : 11 001 reg
memory by 1
1101 000w : mod 001 r/m
register by CL
1101 001w : 11 001 reg
memory by CL
1101 001w : mod 001 r/m
register by immediate count
1100 000w : 11 001 reg : imm8 data
memory by immediate count
1100 000w : mod 001 r/m : imm8 data
RSM – Resume from System Management Mode
0000 1111 : 1010 1010
SAHF – Store AH into Flags
1001 1110
SAL – Shift Arithmetic Left
same instruction as SHL
SAR – Shift Arithmetic Right
register by 1
1101 000w : 11 111 reg
memory by 1
1101 000w : mod 111 r/m
register by CL
1101 001w : 11 111 reg
memory by CL
1101 001w : mod 111 r/m
register by immediate count
1100 000w : 11 111 reg : imm8 data
memory by immediate count
1100 000w : mod 111 r/m : imm8 data
SBB – Integer Subtraction with Borrow
register1 to register2
0001 100w : 11 reg1 reg2
register2 to register1
0001 101w : 11 reg1 reg2
memory to register
0001 101w : mod reg r/m
register to memory
0001 100w : mod reg r/m
immediate to register
1000 00sw : 11 011 reg : immediate data
immediate to AL, AX, or EAX
0001 110w : immediate data
immediate to memory
1000 00sw : mod 011 r/m : immediate data
SCAS/SCASB/SCASW/SCASD – Scan String
1010 111w
SETcc – Byte Set on Condition
register
memory
SGDT – Store Global Descriptor Table Register
0000 1111 : 1001 tttn : 11 000 reg
0000 1111 : 1001 tttn : mod 000 r/m
0000 1111 : 0000 0001 : modA 000 r/m
Vol. 2D B-15
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
SHL – Shift Left
register by 1
1101 000w : 11 100 reg
memory by 1
1101 000w : mod 100 r/m
register by CL
1101 001w : 11 100 reg
memory by CL
1101 001w : mod 100 r/m
register by immediate count
1100 000w : 11 100 reg : imm8 data
memory by immediate count
1100 000w : mod 100 r/m : imm8 data
SHLD – Double Precision Shift Left
register by immediate count
0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8
memory by immediate count
0000 1111 : 1010 0100 : mod reg r/m : imm8
register by CL
0000 1111 : 1010 0101 : 11 reg2 reg1
memory by CL
0000 1111 : 1010 0101 : mod reg r/m
SHR – Shift Right
register by 1
1101 000w : 11 101 reg
memory by 1
1101 000w : mod 101 r/m
register by CL
1101 001w : 11 101 reg
memory by CL
1101 001w : mod 101 r/m
register by immediate count
1100 000w : 11 101 reg : imm8 data
memory by immediate count
1100 000w : mod 101 r/m : imm8 data
SHRD – Double Precision Shift Right
register by immediate count
0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8
memory by immediate count
0000 1111 : 1010 1100 : mod reg r/m : imm8
register by CL
0000 1111 : 1010 1101 : 11 reg2 reg1
memory by CL
SIDT – Store Interrupt Descriptor Table Register
0000 1111 : 1010 1101 : mod reg r/m
0000 1111 : 0000 0001 : modA 001 r/m
SLDT – Store Local Descriptor Table Register
to register
0000 1111 : 0000 0000 : 11 000 reg
to memory
0000 1111 : 0000 0000 : mod 000 r/m
SMSW – Store Machine Status Word
to register
0000 1111 : 0000 0001 : 11 100 reg
to memory
0000 1111 : 0000 0001 : mod 100 r/m
STC – Set Carry Flag
1111 1001
STD – Set Direction Flag
1111 1101
STI – Set Interrupt Flag
1111 1011
STOS/STOSB/STOSW/STOSD – Store String Data
1010 101w
STR – Store Task Register
to register
0000 1111 : 0000 0000 : 11 001 reg
to memory
0000 1111 : 0000 0000 : mod 001 r/m
B-16 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
SUB – Integer Subtraction
register1 to register2
0010 100w : 11 reg1 reg2
register2 to register1
0010 101w : 11 reg1 reg2
memory to register
0010 101w : mod reg r/m
register to memory
0010 100w : mod reg r/m
immediate to register
1000 00sw : 11 101 reg : immediate data
immediate to AL, AX, or EAX
0010 110w : immediate data
immediate to memory
1000 00sw : mod 101 r/m : immediate data
TEST – Logical Compare
register1 and register2
1000 010w : 11 reg1 reg2
memory and register
1000 010w : mod reg r/m
immediate and register
1111 011w : 11 000 reg : immediate data
immediate and AL, AX, or EAX
1010 100w : immediate data
immediate and memory
1111 011w : mod 000 r/m : immediate data
UD2 – Undefined instruction
0000 FFFF : 0000 1011
VERR – Verify a Segment for Reading
register
0000 1111 : 0000 0000 : 11 100 reg
memory
0000 1111 : 0000 0000 : mod 100 r/m
VERW – Verify a Segment for Writing
register
memory
0000 1111 : 0000 0000 : 11 101 reg
0000 1111 : 0000 0000 : mod 101 r/m
WAIT – Wait
1001 1011
WBINVD – Writeback and Invalidate Data Cache
0000 1111 : 0000 1001
WRMSR – Write to Model-Specific Register
0000 1111 : 0011 0000
XADD – Exchange and Add
register1, register2
0000 1111 : 1100 000w : 11 reg2 reg1
memory, reg
0000 1111 : 1100 000w : mod reg r/m
XCHG – Exchange Register/Memory with Register
register1 with register2
1000 011w : 11 reg1 reg2
AX or EAX with reg
1001 0 reg
memory with reg
1000 011w : mod reg r/m
XLAT/XLATB – Table Look-up Translation
1101 0111
XOR – Logical Exclusive OR
register1 to register2
0011 000w : 11 reg1 reg2
register2 to register1
0011 001w : 11 reg1 reg2
memory to register
0011 001w : mod reg r/m
register to memory
0011 000w : mod reg r/m
immediate to register
1000 00sw : 11 110 reg : immediate data
Vol. 2D B-17
INSTRUCTION FORMATS AND ENCODINGS
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format
Encoding
immediate to AL, AX, or EAX
0011 010w : immediate data
immediate to memory
1000 00sw : mod 110 r/m : immediate data
Prefix Bytes
address size
0110 0111
LOCK
1111 0000
operand size
0110 0110
CS segment override
0010 1110
DS segment override
0011 1110
ES segment override
0010 0110
FS segment override
0110 0100
GS segment override
0110 0101
SS segment override
0011 0110
NOTES:
1. The multi-byte NOP instruction does not alter the content of the register and will not issue a memory operation.
B.2.1
General Purpose Instruction Formats and Encodings for 64-Bit Mode
Table B-15 shows machine instruction formats and encodings for general purpose instructions in 64-bit mode.
Table B-14. Special Symbols
Symbol
Application
S
If the value of REX.W. is 1, it overrides the presence of 66H.
w
The value of bit W. in REX is has no effect.
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode
Instruction and Format
Encoding
ADC – ADD with Carry
register1 to register2
0100 0R0B : 0001 000w : 11 reg1 reg2
qwordregister1 to qwordregister2
0100 1R0B : 0001 0001 : 11 qwordreg1 qwordreg2
register2 to register1
0100 0R0B : 0001 001w : 11 reg1 reg2
qwordregister1 to qwordregister2
0100 1R0B : 0001 0011 : 11 qwordreg1 qwordreg2
memory to register
0100 0RXB : 0001 001w : mod reg r/m
memory to qwordregister
0100 1RXB : 0001 0011 : mod qwordreg r/m
register to memory
0100 0RXB : 0001 000w : mod reg r/m
qwordregister to memory
0100 1RXB : 0001 0001 : mod qwordreg r/m
immediate to register
0100 000B : 1000 00sw : 11 010 reg : immediate
immediate to qwordregister
0100 100B : 1000 0001 : 11 010 qwordreg : imm32
immediate to qwordregister
0100 1R0B : 1000 0011 : 11 010 qwordreg : imm8
immediate to AL, AX, or EAX
0001 010w : immediate data
immediate to RAX
0100 1000 : 0000 0101 : imm32
B-18 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
immediate to memory
0100 00XB : 1000 00sw : mod 010 r/m : immediate
immediate32 to memory64
0100 10XB : 1000 0001 : mod 010 r/m : imm32
immediate8 to memory64
0100 10XB : 1000 0031 : mod 010 r/m : imm8
ADD – Add
register1 to register2
0100 0R0B : 0000 000w : 11 reg1 reg2
qwordregister1 to qwordregister2
0100 1R0B 0000 0000 : 11 qwordreg1 qwordreg2
register2 to register1
0100 0R0B : 0000 001w : 11 reg1 reg2
qwordregister1 to qwordregister2
0100 1R0B 0000 0010 : 11 qwordreg1 qwordreg2
memory to register
0100 0RXB : 0000 001w : mod reg r/m
memory64 to qwordregister
0100 1RXB : 0000 0000 : mod qwordreg r/m
register to memory
0100 0RXB : 0000 000w : mod reg r/m
qwordregister to memory64
0100 1RXB : 0000 0011 : mod qwordreg r/m
immediate to register
0100 0000B : 1000 00sw : 11 000 reg : immediate data
immediate32 to qwordregister
0100 100B : 1000 0001 : 11 010 qwordreg : imm
immediate to AL, AX, or EAX
0000 010w : immediate8
immediate to RAX
0100 1000 : 0000 0101 : imm32
immediate to memory
0100 00XB : 1000 00sw : mod 000 r/m : immediate
immediate32 to memory64
0100 10XB : 1000 0001 : mod 010 r/m : imm32
immediate8 to memory64
0100 10XB : 1000 0011 : mod 010 r/m : imm8
AND – Logical AND
register1 to register2
0100 0R0B 0010 000w : 11 reg1 reg2
qwordregister1 to qwordregister2
0100 1R0B 0010 0001 : 11 qwordreg1 qwordreg2
register2 to register1
0100 0R0B 0010 001w : 11 reg1 reg2
register1 to register2
0100 1R0B 0010 0011 : 11 qwordreg1 qwordreg2
memory to register
0100 0RXB 0010 001w : mod reg r/m
memory64 to qwordregister
0100 1RXB : 0010 0011 : mod qwordreg r/m
register to memory
0100 0RXB : 0010 000w : mod reg r/m
qwordregister to memory64
0100 1RXB : 0010 0001 : mod qwordreg r/m
immediate to register
0100 000B : 1000 00sw : 11 100 reg : immediate
immediate32 to qwordregister
0100 100B 1000 0001 : 11 100 qwordreg : imm32
immediate to AL, AX, or EAX
0010 010w : immediate
immediate32 to RAX
0100 1000 0010 1001 : imm32
immediate to memory
0100 00XB : 1000 00sw : mod 100 r/m : immediate
immediate32 to memory64
0100 10XB : 1000 0001 : mod 100 r/m : immediate32
immediate8 to memory64
0100 10XB : 1000 0011 : mod 100 r/m : imm8
BSF – Bit Scan Forward
register1, register2
0100 0R0B 0000 1111 : 1011 1100 : 11 reg1 reg2
qwordregister1, qwordregister2
0100 1R0B 0000 1111 : 1011 1100 : 11 qwordreg1
qwordreg2
Vol. 2D B-19
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
memory, register
0100 0RXB 0000 1111 : 1011 1100 : mod reg r/m
memory64, qwordregister
0100 1RXB 0000 1111 : 1011 1100 : mod qwordreg r/m
BSR – Bit Scan Reverse
register1, register2
0100 0R0B 0000 1111 : 1011 1101 : 11 reg1 reg2
qwordregister1, qwordregister2
0100 1R0B 0000 1111 : 1011 1101 : 11 qwordreg1
qwordreg2
memory, register
0100 0RXB 0000 1111 : 1011 1101 : mod reg r/m
memory64, qwordregister
0100 1RXB 0000 1111 : 1011 1101 : mod qwordreg r/m
BSWAP – Byte Swap
0000 1111 : 1100 1 reg
BSWAP – Byte Swap
0100 100B 0000 1111 : 1100 1 qwordreg
BT – Bit Test
register, immediate
0100 000B 0000 1111 : 1011 1010 : 11 100 reg: imm8
qwordregister, immediate8
0100 100B 1111 : 1011 1010 : 11 100 qwordreg: imm8 data
memory, immediate
0100 00XB 0000 1111 : 1011 1010 : mod 100 r/m : imm8
memory64, immediate8
0100 10XB 0000 1111 : 1011 1010 : mod 100 r/m : imm8 data
register1, register2
0100 0R0B 0000 1111 : 1010 0011 : 11 reg2 reg1
qwordregister1, qwordregister2
0100 1R0B 0000 1111 : 1010 0011 : 11 qwordreg2
qwordreg1
memory, reg
0100 0RXB 0000 1111 : 1010 0011 : mod reg r/m
memory, qwordreg
0100 1RXB 0000 1111 : 1010 0011 : mod qwordreg r/m
BTC – Bit Test and Complement
register, immediate
0100 000B 0000 1111 : 1011 1010 : 11 111 reg: imm8
qwordregister, immediate8
0100 100B 0000 1111 : 1011 1010 : 11 111 qwordreg: imm8
memory, immediate
0100 00XB 0000 1111 : 1011 1010 : mod 111 r/m : imm8
memory64, immediate8
0100 10XB 0000 1111 : 1011 1010 : mod 111 r/m : imm8
register1, register2
0100 0R0B 0000 1111 : 1011 1011 : 11 reg2 reg1
qwordregister1, qwordregister2
0100 1R0B 0000 1111 : 1011 1011 : 11 qwordreg2
qwordreg1
memory, register
0100 0RXB 0000 1111 : 1011 1011 : mod reg r/m
memory, qwordreg
0100 1RXB 0000 1111 : 1011 1011 : mod qwordreg r/m
BTR – Bit Test and Reset
register, immediate
0100 000B 0000 1111 : 1011 1010 : 11 110 reg: imm8
qwordregister, immediate8
0100 100B 0000 1111 : 1011 1010 : 11 110 qwordreg: imm8
memory, immediate
0100 00XB 0000 1111 : 1011 1010 : mod 110 r/m : imm8
memory64, immediate8
0100 10XB 0000 1111 : 1011 1010 : mod 110 r/m : imm8
register1, register2
0100 0R0B 0000 1111 : 1011 0011 : 11 reg2 reg1
qwordregister1, qwordregister2
0100 1R0B 0000 1111 : 1011 0011 : 11 qwordreg2
qwordreg1
memory, register
0100 0RXB 0000 1111 : 1011 0011 : mod reg r/m
memory64, qwordreg
0100 1RXB 0000 1111 : 1011 0011 : mod qwordreg r/m
B-20 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
BTS – Bit Test and Set
register, immediate
0100 000B 0000 1111 : 1011 1010 : 11 101 reg: imm8
qwordregister, immediate8
0100 100B 0000 1111 : 1011 1010 : 11 101 qwordreg: imm8
memory, immediate
0100 00XB 0000 1111 : 1011 1010 : mod 101 r/m : imm8
memory64, immediate8
0100 10XB 0000 1111 : 1011 1010 : mod 101 r/m : imm8
register1, register2
0100 0R0B 0000 1111 : 1010 1011 : 11 reg2 reg1
qwordregister1, qwordregister2
0100 1R0B 0000 1111 : 1010 1011 : 11 qwordreg2
qwordreg1
memory, register
0100 0RXB 0000 1111 : 1010 1011 : mod reg r/m
memory64, qwordreg
0100 1RXB 0000 1111 : 1010 1011 : mod qwordreg r/m
CALL – Call Procedure (in same segment)
direct
1110 1000 : displacement32
register indirect
0100 WR00w 1111 1111 : 11 010 reg
memory indirect
0100 W0XBw 1111 1111 : mod 010 r/m
CALL – Call Procedure (in other segment)
indirect
1111 1111 : mod 011 r/m
indirect
0100 10XB 0100 1000 1111 1111 : mod 011 r/m
CBW – Convert Byte to Word
1001 1000
CDQ – Convert Doubleword to Qword+
1001 1001
CDQE – RAX, Sign-Extend of EAX
0100 1000 1001 1001
CLC – Clear Carry Flag
1111 1000
CLD – Clear Direction Flag
1111 1100
CLI – Clear Interrupt Flag
1111 1010
CLTS – Clear Task-Switched Flag in CR0
0000 1111 : 0000 0110
CMC – Complement Carry Flag
1111 0101
CMP – Compare Two Operands
register1 with register2
0100 0R0B 0011 100w : 11 reg1 reg2
qwordregister1 with qwordregister2
0100 1R0B 0011 1001 : 11 qwordreg1 qwordreg2
register2 with register1
0100 0R0B 0011 101w : 11 reg1 reg2
qwordregister2 with qwordregister1
0100 1R0B 0011 101w : 11 qwordreg1 qwordreg2
memory with register
0100 0RXB 0011 100w : mod reg r/m
memory64 with qwordregister
0100 1RXB 0011 1001 : mod qwordreg r/m
register with memory
0100 0RXB 0011 101w : mod reg r/m
qwordregister with memory64
0100 1RXB 0011 101w1 : mod qwordreg r/m
immediate with register
0100 000B 1000 00sw : 11 111 reg : imm
immediate32 with qwordregister
0100 100B 1000 0001 : 11 111 qwordreg : imm64
immediate with AL, AX, or EAX
0011 110w : imm
immediate32 with RAX
0100 1000 0011 1101 : imm32
immediate with memory
0100 00XB 1000 00sw : mod 111 r/m : imm
Vol. 2D B-21
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
immediate32 with memory64
0100 1RXB 1000 0001 : mod 111 r/m : imm64
immediate8 with memory64
0100 1RXB 1000 0011 : mod 111 r/m : imm8
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ – Compare String
Operands
compare string operands [ X at DS:(E)SI with Y at ES:(E)DI ]
1010 011w
qword at address RSI with qword at address RDI
0100 1000 1010 0111
CMPXCHG – Compare and Exchange
register1, register2
0000 1111 : 1011 000w : 11 reg2 reg1
byteregister1, byteregister2
0100 000B 0000 1111 : 1011 0000 : 11 bytereg2 reg1
qwordregister1, qwordregister2
0100 100B 0000 1111 : 1011 0001 : 11 qwordreg2 reg1
memory, register
0000 1111 : 1011 000w : mod reg r/m
memory8, byteregister
0100 00XB 0000 1111 : 1011 0000 : mod bytereg r/m
memory64, qwordregister
0100 10XB 0000 1111 : 1011 0001 : mod qwordreg r/m
CPUID – CPU Identification
0000 1111 : 1010 0010
CQO – Sign-Extend RAX
0100 1000 1001 1001
CWD – Convert Word to Doubleword
1001 1001
CWDE – Convert Word to Doubleword
1001 1000
DEC – Decrement by 1
register
0100 000B 1111 111w : 11 001 reg
qwordregister
0100 100B 1111 1111 : 11 001 qwordreg
memory
0100 00XB 1111 111w : mod 001 r/m
memory64
0100 10XB 1111 1111 : mod 001 r/m
DIV – Unsigned Divide
AL, AX, or EAX by register
0100 000B 1111 011w : 11 110 reg
Divide RDX:RAX by qwordregister
0100 100B 1111 0111 : 11 110 qwordreg
AL, AX, or EAX by memory
0100 00XB 1111 011w : mod 110 r/m
Divide RDX:RAX by memory64
0100 10XB 1111 0111 : mod 110 r/m
ENTER – Make Stack Frame for High Level Procedure
1100 1000 : 16-bit displacement : 8-bit level (L)
HLT – Halt
1111 0100
IDIV – Signed Divide
AL, AX, or EAX by register
0100 000B 1111 011w : 11 111 reg
RDX:RAX by qwordregister
0100 100B 1111 0111 : 11 111 qwordreg
AL, AX, or EAX by memory
0100 00XB 1111 011w : mod 111 r/m
RDX:RAX by memory64
0100 10XB 1111 0111 : mod 111 r/m
IMUL – Signed Multiply
AL, AX, or EAX with register
0100 000B 1111 011w : 11 101 reg
RDX:RAX <- RAX with qwordregister
0100 100B 1111 0111 : 11 101 qwordreg
AL, AX, or EAX with memory
0100 00XB 1111 011w : mod 101 r/m
RDX:RAX <- RAX with memory64
0100 10XB 1111 0111 : mod 101 r/m
B-22 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
register1 with register2
0000 1111 : 1010 1111 : 11 : reg1 reg2
qwordregister1 <- qwordregister1 with qwordregister2
0100 1R0B 0000 1111 : 1010 1111 : 11 : qwordreg1
qwordreg2
register with memory
0100 0RXB 0000 1111 : 1010 1111 : mod reg r/m
qwordregister <- qwordregister withmemory64
0100 1RXB 0000 1111 : 1010 1111 : mod qwordreg r/m
register1 with immediate to register2
0100 0R0B 0110 10s1 : 11 reg1 reg2 : imm
qwordregister1 <- qwordregister2 with sign-extended
immediate8
0100 1R0B 0110 1011 : 11 qwordreg1 qwordreg2 : imm8
qwordregister1 <- qwordregister2 with immediate32
0100 1R0B 0110 1001 : 11 qwordreg1 qwordreg2 : imm32
memory with immediate to register
0100 0RXB 0110 10s1 : mod reg r/m : imm
qwordregister <- memory64 with sign-extended immediate8
0100 1RXB 0110 1011 : mod qwordreg r/m : imm8
qwordregister <- memory64 with immediate32
0100 1RXB 0110 1001 : mod qwordreg r/m : imm32
IN – Input From Port
fixed port
1110 010w : port number
variable port
1110 110w
INC – Increment by 1
reg
0100 000B 1111 111w : 11 000 reg
qwordreg
0100 100B 1111 1111 : 11 000 qwordreg
memory
0100 00XB 1111 111w : mod 000 r/m
memory64
0100 10XB 1111 1111 : mod 000 r/m
INS – Input from DX Port
0110 110w
INT n – Interrupt Type n
1100 1101 : type
INT – Single-Step Interrupt 3
1100 1100
INTO – Interrupt 4 on Overflow
1100 1110
INVD – Invalidate Cache
0000 1111 : 0000 1000
INVLPG – Invalidate TLB Entry
0000 1111 : 0000 0001 : mod 111 r/m
INVPCID – Invalidate Process-Context Identifier
0110 0110:0000 1111:0011 1000:1000 0010: mod reg r/m
IRETO – Interrupt Return
1100 1111
Jcc – Jump if Condition is Met
8-bit displacement
0111 tttn : 8-bit displacement
displacements (excluding 16-bit relative offsets)
0000 1111 : 1000 tttn : displacement32
JCXZ/JECXZ – Jump on CX/ECX Zero
Address-size prefix differentiates JCXZ and JECXZ
1110 0011 : 8-bit displacement
JMP – Unconditional Jump (to same segment)
short
1110 1011 : 8-bit displacement
direct
1110 1001 : displacement32
register indirect
0100 W00Bw : 1111 1111 : 11 100 reg
memory indirect
0100 W0XBw : 1111 1111 : mod 100 r/m
Vol. 2D B-23
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
JMP – Unconditional Jump (to other segment)
indirect intersegment
0100 00XB : 1111 1111 : mod 101 r/m
64-bit indirect intersegment
0100 10XB : 1111 1111 : mod 101 r/m
LAR – Load Access Rights Byte
from register
0100 0R0B : 0000 1111 : 0000 0010 : 11 reg1 reg2
from dwordregister to qwordregister, masked by 00FxFF00H
0100 WR0B : 0000 1111 : 0000 0010 : 11 qwordreg1
dwordreg2
from memory
0100 0RXB : 0000 1111 : 0000 0010 : mod reg r/m
from memory32 to qwordregister, masked by 00FxFF00H
0100 WRXB 0000 1111 : 0000 0010 : mod r/m
LEA – Load Effective Address
in wordregister/dwordregister
0100 0RXB : 1000 1101 : modA reg r/m
in qwordregister
0100 1RXB : 1000 1101 : modA qwordreg r/m
LEAVE – High Level Procedure Exit
1100 1001
LFS – Load Pointer to FS
FS:r16/r32 with far pointer from memory
0100 0RXB : 0000 1111 : 1011 0100 : modA reg r/m
FS:r64 with far pointer from memory
0100 1RXB : 0000 1111 : 1011 0100 : modA qwordreg r/m
LGDT – Load Global Descriptor Table Register
0100 10XB : 0000 1111 : 0000 0001 : modA 010 r/m
LGS – Load Pointer to GS
GS:r16/r32 with far pointer from memory
0100 0RXB : 0000 1111 : 1011 0101 : modA reg r/m
GS:r64 with far pointer from memory
0100 1RXB : 0000 1111 : 1011 0101 : modA qwordreg r/m
LIDT – Load Interrupt Descriptor Table Register
0100 10XB : 0000 1111 : 0000 0001 : modA 011 r/m
LLDT – Load Local Descriptor Table Register
LDTR from register
0100 000B : 0000 1111 : 0000 0000 : 11 010 reg
LDTR from memory
0100 00XB :0000 1111 : 0000 0000 : mod 010 r/m
LMSW – Load Machine Status Word
from register
0100 000B : 0000 1111 : 0000 0001 : 11 110 reg
from memory
0100 00XB :0000 1111 : 0000 0001 : mod 110 r/m
LOCK – Assert LOCK# Signal Prefix
1111 0000
LODS/LODSB/LODSW/LODSD/LODSQ – Load String Operand
at DS:(E)SI to AL/EAX/EAX
at (R)SI to RAX
1010 110w
0100 1000 1010 1101
LOOP – Loop Count
if count ≠ 0, 8-bit displacement
1110 0010
if count ≠ 0, RIP + 8-bit displacement sign-extended to 64-bits
0100 1000 1110 0010
LOOPE – Loop Count while Zero/Equal
if count ≠ 0 & ZF =1, 8-bit displacement
1110 0001
if count ≠ 0 & ZF = 1, RIP + 8-bit displacement sign-extended to
64-bits
0100 1000 1110 0001
B-24 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
LOOPNE/LOOPNZ – Loop Count while not Zero/Equal
if count ≠ 0 & ZF = 0, 8-bit displacement
1110 0000
if count ≠ 0 & ZF = 0, RIP + 8-bit displacement sign-extended to
64-bits
0100 1000 1110 0000
LSL – Load Segment Limit
from register
from qwordregister
from memory16
from memory64
0000 1111 : 0000 0011 : 11 reg1 reg2
0100 1R00 0000 1111 : 0000 0011 : 11 qwordreg1 reg2
0000 1111 : 0000 0011 : mod reg r/m
0100 1RXB 0000 1111 : 0000 0011 : mod qwordreg r/m
LSS – Load Pointer to SS
SS:r16/r32 with far pointer from memory
0100 0RXB : 0000 1111 : 1011 0010 : modA reg r/m
SS:r64 with far pointer from memory
0100 1WXB : 0000 1111 : 1011 0010 : modA qwordreg r/m
LTR – Load Task Register
from register
0100 0R00 : 0000 1111 : 0000 0000 : 11 011 reg
from memory
0100 00XB : 0000 1111 : 0000 0000 : mod 011 r/m
MOV – Move Data
register1 to register2
0100 0R0B : 1000 100w : 11 reg1 reg2
qwordregister1 to qwordregister2
0100 1R0B 1000 1001 : 11 qwordeg1 qwordreg2
register2 to register1
0100 0R0B : 1000 101w : 11 reg1 reg2
qwordregister2 to qwordregister1
0100 1R0B 1000 1011 : 11 qwordreg1 qwordreg2
memory to reg
0100 0RXB : 1000 101w : mod reg r/m
memory64 to qwordregister
0100 1RXB 1000 1011 : mod qwordreg r/m
reg to memory
0100 0RXB : 1000 100w : mod reg r/m
qwordregister to memory64
0100 1RXB 1000 1001 : mod qwordreg r/m
immediate to register
0100 000B : 1100 011w : 11 000 reg : imm
immediate32 to qwordregister (zero extend)
0100 100B 1100 0111 : 11 000 qwordreg : imm32
immediate to register (alternate encoding)
0100 000B : 1011 w reg : imm
immediate64 to qwordregister (alternate encoding)
0100 100B 1011 1000 reg : imm64
immediate to memory
0100 00XB : 1100 011w : mod 000 r/m : imm
immediate32 to memory64 (zero extend)
0100 10XB 1100 0111 : mod 000 r/m : imm32
memory to AL, AX, or EAX
0100 0000 : 1010 000w : displacement
memory64 to RAX
0100 1000 1010 0001 : displacement64
AL, AX, or EAX to memory
0100 0000 : 1010 001w : displacement
RAX to memory64
0100 1000 1010 0011 : displacement64
MOV – Move to/from Control Registers
CR0-CR4 from register
0100 0R0B : 0000 1111 : 0010 0010 : 11 eee reg (eee = CR#)
CRx from qwordregister
0100 1R0B : 0000 1111 : 0010 0010 : 11 eee qwordreg (Reee
= CR#)
register from CR0-CR4
0100 0R0B : 0000 1111 : 0010 0000 : 11 eee reg (eee = CR#)
Vol. 2D B-25
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
qwordregister from CRx
Encoding
0100 1R0B 0000 1111 : 0010 0000 : 11 eee qwordreg
(Reee = CR#)
MOV – Move to/from Debug Registers
DR0-DR7 from register
0000 1111 : 0010 0011 : 11 eee reg (eee = DR#)
DR0-DR7 from quadregister
0100 10OB 0000 1111 : 0010 0011 : 11 eee reg (eee = DR#)
register from DR0-DR7
0000 1111 : 0010 0001 : 11 eee reg (eee = DR#)
quadregister from DR0-DR7
0100 10OB 0000 1111 : 0010 0001 : 11 eee quadreg (eee =
DR#)
MOV – Move to/from Segment Registers
register to segment register
0100 W00Bw : 1000 1110 : 11 sreg reg
register to SS
0100 000B : 1000 1110 : 11 sreg reg
memory to segment register
0100 00XB : 1000 1110 : mod sreg r/m
memory64 to segment register (lower 16 bits)
0100 10XB 1000 1110 : mod sreg r/m
memory to SS
0100 00XB : 1000 1110 : mod sreg r/m
segment register to register
0100 000B : 1000 1100 : 11 sreg reg
segment register to qwordregister (zero extended)
0100 100B 1000 1100 : 11 sreg qwordreg
segment register to memory
0100 00XB : 1000 1100 : mod sreg r/m
segment register to memory64 (zero extended)
0100 10XB 1000 1100 : mod sreg3 r/m
MOVBE – Move data after swapping bytes
memory to register
0100 0RXB : 0000 1111 : 0011 1000:1111 0000 : mod reg r/m
memory64 to qwordregister
0100 1RXB : 0000 1111 : 0011 1000:1111 0000 : mod reg r/m
register to memory
0100 0RXB :0000 1111 : 0011 1000:1111 0001 : mod reg r/m
qwordregister to memory64
0100 1RXB :0000 1111 : 0011 1000:1111 0001 : mod reg r/m
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ – Move Data from
String to String
Move data from string to string
Move data from string to string (qword)
1010 010w
0100 1000 1010 0101
MOVSX/MOVSXD – Move with Sign-Extend
register2 to register1
0100 0R0B : 0000 1111 : 1011 111w : 11 reg1 reg2
byteregister2 to qwordregister1 (sign-extend)
0100 1R0B 0000 1111 : 1011 1110 : 11 quadreg1 bytereg2
wordregister2 to qwordregister1
0100 1R0B 0000 1111 : 1011 1111 : 11 quadreg1 wordreg2
dwordregister2 to qwordregister1
0100 1R0B 0110 0011 : 11 quadreg1 dwordreg2
memory to register
0100 0RXB : 0000 1111 : 1011 111w : mod reg r/m
memory8 to qwordregister (sign-extend)
0100 1RXB 0000 1111 : 1011 1110 : mod qwordreg r/m
memory16 to qwordregister
0100 1RXB 0000 1111 : 1011 1111 : mod qwordreg r/m
memory32 to qwordregister
0100 1RXB 0110 0011 : mod qwordreg r/m
MOVZX – Move with Zero-Extend
register2 to register1
0100 0R0B : 0000 1111 : 1011 011w : 11 reg1 reg2
dwordregister2 to qwordregister1
0100 1R0B 0000 1111 : 1011 0111 : 11 qwordreg1
dwordreg2
B-26 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
memory to register
0100 0RXB : 0000 1111 : 1011 011w : mod reg r/m
memory32 to qwordregister
0100 1RXB 0000 1111 : 1011 0111 : mod qwordreg r/m
MUL – Unsigned Multiply
AL, AX, or EAX with register
RAX with qwordregister (to RDX:RAX)
0100 000B : 1111 011w : 11 100 reg
0100 100B 1111 0111 : 11 100 qwordreg
AL, AX, or EAX with memory
0100 00XB 1111 011w : mod 100 r/m
RAX with memory64 (to RDX:RAX)
0100 10XB 1111 0111 : mod 100 r/m
NEG – Two's Complement Negation
register
0100 000B : 1111 011w : 11 011 reg
qwordregister
0100 100B 1111 0111 : 11 011 qwordreg
memory
0100 00XB : 1111 011w : mod 011 r/m
memory64
NOP – No Operation
0100 10XB 1111 0111 : mod 011 r/m
1001 0000
NOT – One's Complement Negation
register
0100 000B : 1111 011w : 11 010 reg
qwordregister
0100 000B 1111 0111 : 11 010 qwordreg
memory
0100 00XB : 1111 011w : mod 010 r/m
memory64
0100 1RXB 1111 0111 : mod 010 r/m
OR – Logical Inclusive OR
register1 to register2
0000 100w : 11 reg1 reg2
byteregister1 to byteregister2
0100 0R0B 0000 1000 : 11 bytereg1 bytereg2
qwordregister1 to qwordregister2
0100 1R0B 0000 1001 : 11 qwordreg1 qwordreg2
register2 to register1
0000 101w : 11 reg1 reg2
byteregister2 to byteregister1
0100 0R0B 0000 1010 : 11 bytereg1 bytereg2
qwordregister2 to qwordregister1
0100 0R0B 0000 1011 : 11 qwordreg1 qwordreg2
memory to register
0000 101w : mod reg r/m
memory8 to byteregister
0100 0RXB 0000 1010 : mod bytereg r/m
memory8 to qwordregister
0100 0RXB 0000 1011 : mod qwordreg r/m
register to memory
0000 100w : mod reg r/m
byteregister to memory8
0100 0RXB 0000 1000 : mod bytereg r/m
qwordregister to memory64
0100 1RXB 0000 1001 : mod qwordreg r/m
immediate to register
1000 00sw : 11 001 reg : imm
immediate8 to byteregister
0100 000B 1000 0000 : 11 001 bytereg : imm8
immediate32 to qwordregister
0100 000B 1000 0001 : 11 001 qwordreg : imm32
immediate8 to qwordregister
0100 000B 1000 0011 : 11 001 qwordreg : imm8
immediate to AL, AX, or EAX
0000 110w : imm
immediate64 to RAX
0100 1000 0000 1101 : imm64
immediate to memory
1000 00sw : mod 001 r/m : imm
Vol. 2D B-27
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
immediate8 to memory8
0100 00XB 1000 0000 : mod 001 r/m : imm8
immediate32 to memory64
0100 00XB 1000 0001 : mod 001 r/m : imm32
immediate8 to memory64
0100 00XB 1000 0011 : mod 001 r/m : imm8
OUT – Output to Port
fixed port
1110 011w : port number
variable port
1110 111w
OUTS – Output to DX Port
output to DX Port
0110 111w
POP – Pop a Value from the Stack
wordregister
0101 0101 : 0100 000B : 1000 1111 : 11 000 reg16
qwordregister
0100 W00BS : 1000 1111 : 11 000 reg64
wordregister (alternate encoding)
0101 0101 : 0100 000B : 0101 1 reg16
qwordregister (alternate encoding)
0100 W00B : 0101 1 reg64
memory64
0100 W0XBS : 1000 1111 : mod 000 r/m
memory16
0101 0101 : 0100 00XB 1000 1111 : mod 000 r/m
POP – Pop a Segment Register from the Stack
(Note: CS cannot be sreg2 in this usage.)
segment register FS, GS
0000 1111: 10 sreg3 001
POPF/POPFQ – Pop Stack into FLAGS/RFLAGS Register
pop stack to FLAGS register
0101 0101 : 1001 1101
pop Stack to RFLAGS register
0100 1000 1001 1101
PUSH – Push Operand onto the Stack
wordregister
0101 0101 : 0100 000B : 1111 1111 : 11 110 reg16
qwordregister
0100 W00BS : 1111 1111 : 11 110 reg64
wordregister (alternate encoding)
0101 0101 : 0100 000B : 0101 0 reg16
qwordregister (alternate encoding)
0100 W00BS : 0101 0 reg64
memory16
0101 0101 : 0100 000B : 1111 1111 : mod 110 r/m
memory64
0100 W00BS : 1111 1111 : mod 110 r/m
immediate8
0110 1010 : imm8
immediate16
0101 0101 : 0110 1000 : imm16
immediate64
0110 1000 : imm64
PUSH – Push Segment Register onto the Stack
segment register FS,GS
PUSHF/PUSHFD – Push Flags Register onto the Stack
0000 1111: 10 sreg3 000
1001 1100
RCL – Rotate thru Carry Left
register by 1
0100 000B : 1101 000w : 11 010 reg
qwordregister by 1
0100 100B 1101 0001 : 11 010 qwordreg
memory by 1
0100 00XB : 1101 000w : mod 010 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 010 r/m
B-28 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
register by CL
0100 000B : 1101 001w : 11 010 reg
qwordregister by CL
0100 100B 1101 0011 : 11 010 qwordreg
memory by CL
0100 00XB : 1101 001w : mod 010 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 010 r/m
register by immediate count
0100 000B : 1100 000w : 11 010 reg : imm
qwordregister by immediate count
0100 100B 1100 0001 : 11 010 qwordreg : imm8
memory by immediate count
0100 00XB : 1100 000w : mod 010 r/m : imm
memory64 by immediate count
0100 10XB 1100 0001 : mod 010 r/m : imm8
RCR – Rotate thru Carry Right
register by 1
0100 000B : 1101 000w : 11 011 reg
qwordregister by 1
0100 100B 1101 0001 : 11 011 qwordreg
memory by 1
0100 00XB : 1101 000w : mod 011 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 011 r/m
register by CL
0100 000B : 1101 001w : 11 011 reg
qwordregister by CL
0100 000B 1101 0010 : 11 011 qwordreg
memory by CL
0100 00XB : 1101 001w : mod 011 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 011 r/m
register by immediate count
0100 000B : 1100 000w : 11 011 reg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 011 qwordreg : imm8
memory by immediate count
0100 00XB : 1100 000w : mod 011 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 011 r/m : imm8
RDMSR – Read from Model-Specific Register
load ECX-specified register into EDX:EAX
0000 1111 : 0011 0010
RDPMC – Read Performance Monitoring Counters
load ECX-specified performance counter into EDX:EAX
0000 1111 : 0011 0011
RDTSC – Read Time-Stamp Counter
read time-stamp counter into EDX:EAX
RDTSCP – Read Time-Stamp Counter and Processor ID
0000 1111 : 0011 0001
0000 1111 : 0000 0001: 1111 1001
REP INS – Input String
REP LODS – Load String
REP MOVS – Move String
REP OUTS – Output String
REP STOS – Store String
REPE CMPS – Compare String
REPE SCAS – Scan String
REPNE CMPS – Compare String
REPNE SCAS – Scan String
RET – Return from Procedure (to same segment)
Vol. 2D B-29
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
no argument
1100 0011
adding immediate to SP
1100 0010 : 16-bit displacement
RET – Return from Procedure (to other segment)
intersegment
1100 1011
adding immediate to SP
1100 1010 : 16-bit displacement
ROL – Rotate Left
register by 1
0100 000B 1101 000w : 11 000 reg
byteregister by 1
0100 000B 1101 0000 : 11 000 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 000 qwordreg
memory by 1
0100 00XB 1101 000w : mod 000 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 000 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 000 r/m
register by CL
0100 000B 1101 001w : 11 000 reg
byteregister by CL
0100 000B 1101 0010 : 11 000 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 000 qwordreg
memory by CL
0100 00XB 1101 001w : mod 000 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 000 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 000 r/m
register by immediate count
1100 000w : 11 000 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 000 bytereg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 000 bytereg : imm8
memory by immediate count
1100 000w : mod 000 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 000 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 000 r/m : imm8
ROR – Rotate Right
register by 1
0100 000B 1101 000w : 11 001 reg
byteregister by 1
0100 000B 1101 0000 : 11 001 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 001 qwordreg
memory by 1
0100 00XB 1101 000w : mod 001 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 001 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 001 r/m
register by CL
0100 000B 1101 001w : 11 001 reg
byteregister by CL
0100 000B 1101 0010 : 11 001 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 001 qwordreg
memory by CL
0100 00XB 1101 001w : mod 001 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 001 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 001 r/m
register by immediate count
0100 000B 1100 000w : 11 001 reg : imm8
B-30 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
byteregister by immediate count
0100 000B 1100 0000 : 11 001 reg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 001 qwordreg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 001 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 001 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 001 r/m : imm8
RSM – Resume from System Management Mode
0000 1111 : 1010 1010
SAL – Shift Arithmetic Left
same instruction as SHL
SAR – Shift Arithmetic Right
register by 1
0100 000B 1101 000w : 11 111 reg
byteregister by 1
0100 000B 1101 0000 : 11 111 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 111 qwordreg
memory by 1
0100 00XB 1101 000w : mod 111 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 111 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 111 r/m
register by CL
0100 000B 1101 001w : 11 111 reg
byteregister by CL
0100 000B 1101 0010 : 11 111 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 111 qwordreg
memory by CL
0100 00XB 1101 001w : mod 111 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 111 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 111 r/m
register by immediate count
0100 000B 1100 000w : 11 111 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 111 bytereg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 111 qwordreg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 111 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 111 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 111 r/m : imm8
SBB – Integer Subtraction with Borrow
register1 to register2
0100 0R0B 0001 100w : 11 reg1 reg2
byteregister1 to byteregister2
0100 0R0B 0001 1000 : 11 bytereg1 bytereg2
quadregister1 to quadregister2
0100 1R0B 0001 1001 : 11 quadreg1 quadreg2
register2 to register1
0100 0R0B 0001 101w : 11 reg1 reg2
byteregister2 to byteregister1
0100 0R0B 0001 1010 : 11 reg1 bytereg2
byteregister2 to byteregister1
0100 1R0B 0001 1011 : 11 reg1 bytereg2
memory to register
0100 0RXB 0001 101w : mod reg r/m
memory8 to byteregister
0100 0RXB 0001 1010 : mod bytereg r/m
memory64 to byteregister
0100 1RXB 0001 1011 : mod quadreg r/m
register to memory
0100 0RXB 0001 100w : mod reg r/m
byteregister to memory8
0100 0RXB 0001 1000 : mod reg r/m
Vol. 2D B-31
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
quadregister to memory64
0100 1RXB 0001 1001 : mod reg r/m
immediate to register
0100 000B 1000 00sw : 11 011 reg : imm
immediate8 to byteregister
0100 000B 1000 0000 : 11 011 bytereg : imm8
immediate32 to qwordregister
0100 100B 1000 0001 : 11 011 qwordreg : imm32
immediate8 to qwordregister
0100 100B 1000 0011 : 11 011 qwordreg : imm8
immediate to AL, AX, or EAX
0100 000B 0001 110w : imm
immediate32 to RAL
0100 1000 0001 1101 : imm32
immediate to memory
0100 00XB 1000 00sw : mod 011 r/m : imm
immediate8 to memory8
0100 00XB 1000 0000 : mod 011 r/m : imm8
immediate32 to memory64
0100 10XB 1000 0001 : mod 011 r/m : imm32
immediate8 to memory64
0100 10XB 1000 0011 : mod 011 r/m : imm8
SCAS/SCASB/SCASW/SCASD – Scan String
scan string
1010 111w
scan string (compare AL with byte at RDI)
0100 1000 1010 1110
scan string (compare RAX with qword at RDI)
0100 1000 1010 1111
SETcc – Byte Set on Condition
register
0100 000B 0000 1111 : 1001 tttn : 11 000 reg
register
0100 0000 0000 1111 : 1001 tttn : 11 000 reg
memory
0100 00XB 0000 1111 : 1001 tttn : mod 000 r/m
memory
0100 0000 0000 1111 : 1001 tttn : mod 000 r/m
SGDT – Store Global Descriptor Table Register
0000 1111 : 0000 0001 : modA 000 r/m
SHL – Shift Left
register by 1
0100 000B 1101 000w : 11 100 reg
byteregister by 1
0100 000B 1101 0000 : 11 100 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 100 qwordreg
memory by 1
0100 00XB 1101 000w : mod 100 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 100 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 100 r/m
register by CL
0100 000B 1101 001w : 11 100 reg
byteregister by CL
0100 000B 1101 0010 : 11 100 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 100 qwordreg
memory by CL
0100 00XB 1101 001w : mod 100 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 100 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 100 r/m
register by immediate count
0100 000B 1100 000w : 11 100 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 100 bytereg : imm8
quadregister by immediate count
0100 100B 1100 0001 : 11 100 quadreg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 100 r/m : imm8
B-32 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
memory8 by immediate count
0100 00XB 1100 0000 : mod 100 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 100 r/m : imm8
SHLD – Double Precision Shift Left
register by immediate count
0100 0R0B 0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8
qwordregister by immediate8
0100 1R0B 0000 1111 : 1010 0100 : 11 qworddreg2
qwordreg1 : imm8
memory by immediate count
0100 0RXB 0000 1111 : 1010 0100 : mod reg r/m : imm8
memory64 by immediate8
0100 1RXB 0000 1111 : 1010 0100 : mod qwordreg r/m :
imm8
register by CL
0100 0R0B 0000 1111 : 1010 0101 : 11 reg2 reg1
quadregister by CL
0100 1R0B 0000 1111 : 1010 0101 : 11 quadreg2 quadreg1
memory by CL
0100 00XB 0000 1111 : 1010 0101 : mod reg r/m
memory64 by CL
0100 1RXB 0000 1111 : 1010 0101 : mod quadreg r/m
SHR – Shift Right
register by 1
0100 000B 1101 000w : 11 101 reg
byteregister by 1
0100 000B 1101 0000 : 11 101 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 101 qwordreg
memory by 1
0100 00XB 1101 000w : mod 101 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 101 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 101 r/m
register by CL
0100 000B 1101 001w : 11 101 reg
byteregister by CL
0100 000B 1101 0010 : 11 101 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 101 qwordreg
memory by CL
0100 00XB 1101 001w : mod 101 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 101 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 101 r/m
register by immediate count
0100 000B 1100 000w : 11 101 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 101 reg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 101 reg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 101 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 101 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 101 r/m : imm8
SHRD – Double Precision Shift Right
register by immediate count
0100 0R0B 0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8
qwordregister by immediate8
0100 1R0B 0000 1111 : 1010 1100 : 11 qwordreg2
qwordreg1 : imm8
memory by immediate count
0100 00XB 0000 1111 : 1010 1100 : mod reg r/m : imm8
memory64 by immediate8
0100 1RXB 0000 1111 : 1010 1100 : mod qwordreg r/m :
imm8
register by CL
0100 000B 0000 1111 : 1010 1101 : 11 reg2 reg1
Vol. 2D B-33
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
qwordregister by CL
0100 1R0B 0000 1111 : 1010 1101 : 11 qwordreg2
qwordreg1
memory by CL
0000 1111 : 1010 1101 : mod reg r/m
memory64 by CL
0100 1RXB 0000 1111 : 1010 1101 : mod qwordreg r/m
SIDT – Store Interrupt Descriptor Table Register
0000 1111 : 0000 0001 : modA 001 r/m
SLDT – Store Local Descriptor Table Register
to register
0100 000B 0000 1111 : 0000 0000 : 11 000 reg
to memory
0100 00XB 0000 1111 : 0000 0000 : mod 000 r/m
SMSW – Store Machine Status Word
to register
0100 000B 0000 1111 : 0000 0001 : 11 100 reg
to memory
0100 00XB 0000 1111 : 0000 0001 : mod 100 r/m
STC – Set Carry Flag
1111 1001
STD – Set Direction Flag
1111 1101
STI – Set Interrupt Flag
1111 1011
STOS/STOSB/STOSW/STOSD/STOSQ – Store String Data
store string data
1010 101w
store string data (RAX at address RDI)
0100 1000 1010 1011
STR – Store Task Register
to register
0100 000B 0000 1111 : 0000 0000 : 11 001 reg
to memory
0100 00XB 0000 1111 : 0000 0000 : mod 001 r/m
SUB – Integer Subtraction
register1 from register2
0100 0R0B 0010 100w : 11 reg1 reg2
byteregister1 from byteregister2
0100 0R0B 0010 1000 : 11 bytereg1 bytereg2
qwordregister1 from qwordregister2
0100 1R0B 0010 1000 : 11 qwordreg1 qwordreg2
register2 from register1
0100 0R0B 0010 101w : 11 reg1 reg2
byteregister2 from byteregister1
0100 0R0B 0010 1010 : 11 bytereg1 bytereg2
qwordregister2 from qwordregister1
0100 1R0B 0010 1011 : 11 qwordreg1 qwordreg2
memory from register
0100 00XB 0010 101w : mod reg r/m
memory8 from byteregister
0100 0RXB 0010 1010 : mod bytereg r/m
memory64 from qwordregister
0100 1RXB 0010 1011 : mod qwordreg r/m
register from memory
0100 0RXB 0010 100w : mod reg r/m
byteregister from memory8
0100 0RXB 0010 1000 : mod bytereg r/m
qwordregister from memory8
0100 1RXB 0010 1000 : mod qwordreg r/m
immediate from register
0100 000B 1000 00sw : 11 101 reg : imm
immediate8 from byteregister
0100 000B 1000 0000 : 11 101 bytereg : imm8
immediate32 from qwordregister
0100 100B 1000 0001 : 11 101 qwordreg : imm32
immediate8 from qwordregister
0100 100B 1000 0011 : 11 101 qwordreg : imm8
immediate from AL, AX, or EAX
0100 000B 0010 110w : imm
immediate32 from RAX
0100 1000 0010 1101 : imm32
B-34 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
immediate from memory
0100 00XB 1000 00sw : mod 101 r/m : imm
immediate8 from memory8
0100 00XB 1000 0000 : mod 101 r/m : imm8
immediate32 from memory64
0100 10XB 1000 0001 : mod 101 r/m : imm32
immediate8 from memory64
0100 10XB 1000 0011 : mod 101 r/m : imm8
SWAPGS – Swap GS Base Register
Exchanges the current GS base register value for value in MSR
C0000102H
0000 1111 0000 0001 1111 1000
SYSCALL – Fast System Call
fast call to privilege level 0 system procedures
0000 1111 0000 0101
SYSRET – Return From Fast System Call
return from fast system call
0000 1111 0000 0111
TEST – Logical Compare
register1 and register2
0100 0R0B 1000 010w : 11 reg1 reg2
byteregister1 and byteregister2
0100 0R0B 1000 0100 : 11 bytereg1 bytereg2
qwordregister1 and qwordregister2
0100 1R0B 1000 0101 : 11 qwordreg1 qwordreg2
memory and register
0100 0R0B 1000 010w : mod reg r/m
memory8 and byteregister
0100 0RXB 1000 0100 : mod bytereg r/m
memory64 and qwordregister
0100 1RXB 1000 0101 : mod qwordreg r/m
immediate and register
0100 000B 1111 011w : 11 000 reg : imm
immediate8 and byteregister
0100 000B 1111 0110 : 11 000 bytereg : imm8
immediate32 and qwordregister
0100 100B 1111 0111 : 11 000 bytereg : imm8
immediate and AL, AX, or EAX
0100 000B 1010 100w : imm
immediate32 and RAX
0100 1000 1010 1001 : imm32
immediate and memory
0100 00XB 1111 011w : mod 000 r/m : imm
immediate8 and memory8
0100 1000 1111 0110 : mod 000 r/m : imm8
immediate32 and memory64
0100 1000 1111 0111 : mod 000 r/m : imm32
UD2 – Undefined instruction
0000 FFFF : 0000 1011
VERR – Verify a Segment for Reading
register
0100 000B 0000 1111 : 0000 0000 : 11 100 reg
memory
0100 00XB 0000 1111 : 0000 0000 : mod 100 r/m
VERW – Verify a Segment for Writing
register
0100 000B 0000 1111 : 0000 0000 : 11 101 reg
memory
0100 00XB 0000 1111 : 0000 0000 : mod 101 r/m
WAIT – Wait
1001 1011
WBINVD – Writeback and Invalidate Data Cache
0000 1111 : 0000 1001
WRMSR – Write to Model-Specific Register
write EDX:EAX to ECX specified MSR
0000 1111 : 0011 0000
write RDX[31:0]:RAX[31:0] to RCX specified MSR
0100 1000 0000 1111 : 0011 0000
Vol. 2D B-35
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
XADD – Exchange and Add
register1, register2
0100 0R0B 0000 1111 : 1100 000w : 11 reg2 reg1
byteregister1, byteregister2
0100 0R0B 0000 1111 : 1100 0000 : 11 bytereg2 bytereg1
qwordregister1, qwordregister2
0100 0R0B 0000 1111 : 1100 0001 : 11 qwordreg2
qwordreg1
memory, register
0100 0RXB 0000 1111 : 1100 000w : mod reg r/m
memory8, bytereg
0100 1RXB 0000 1111 : 1100 0000 : mod bytereg r/m
memory64, qwordreg
0100 1RXB 0000 1111 : 1100 0001 : mod qwordreg r/m
XCHG – Exchange Register/Memory with Register
register1 with register2
1000 011w : 11 reg1 reg2
AX or EAX with register
1001 0 reg
memory with register
1000 011w : mod reg r/m
XLAT/XLATB – Table Look-up Translation
AL to byte DS:[(E)BX + unsigned AL]
1101 0111
AL to byte DS:[RBX + unsigned AL]
0100 1000 1101 0111
XOR – Logical Exclusive OR
register1 to register2
0100 0RXB 0011 000w : 11 reg1 reg2
byteregister1 to byteregister2
0100 0R0B 0011 0000 : 11 bytereg1 bytereg2
qwordregister1 to qwordregister2
0100 1R0B 0011 0001 : 11 qwordreg1 qwordreg2
register2 to register1
0100 0R0B 0011 001w : 11 reg1 reg2
byteregister2 to byteregister1
0100 0R0B 0011 0010 : 11 bytereg1 bytereg2
qwordregister2 to qwordregister1
0100 1R0B 0011 0011 : 11 qwordreg1 qwordreg2
memory to register
0100 0RXB 0011 001w : mod reg r/m
memory8 to byteregister
0100 0RXB 0011 0010 : mod bytereg r/m
memory64 to qwordregister
0100 1RXB 0011 0011 : mod qwordreg r/m
register to memory
0100 0RXB 0011 000w : mod reg r/m
byteregister to memory8
0100 0RXB 0011 0000 : mod bytereg r/m
qwordregister to memory8
0100 1RXB 0011 0001 : mod qwordreg r/m
immediate to register
0100 000B 1000 00sw : 11 110 reg : imm
immediate8 to byteregister
0100 000B 1000 0000 : 11 110 bytereg : imm8
immediate32 to qwordregister
0100 100B 1000 0001 : 11 110 qwordreg : imm32
immediate8 to qwordregister
0100 100B 1000 0011 : 11 110 qwordreg : imm8
immediate to AL, AX, or EAX
0100 000B 0011 010w : imm
immediate to RAX
0100 1000 0011 0101 : immediate data
immediate to memory
0100 00XB 1000 00sw : mod 110 r/m : imm
immediate8 to memory8
0100 00XB 1000 0000 : mod 110 r/m : imm8
immediate32 to memory64
0100 10XB 1000 0001 : mod 110 r/m : imm32
immediate8 to memory64
0100 10XB 1000 0011 : mod 110 r/m : imm8
B-36 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
Prefix Bytes
address size
0110 0111
LOCK
1111 0000
operand size
0110 0110
CS segment override
0010 1110
DS segment override
0011 1110
ES segment override
0010 0110
FS segment override
0110 0100
GS segment override
0110 0101
SS segment override
0011 0110
B.3
PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS
The following table shows formats and encodings introduced by the Pentium processor family.
Table B-16. Pentium Processor Family Instruction Formats and Encodings, Non-64-Bit Modes
Instruction and Format
Encoding
CMPXCHG8B – Compare and Exchange 8 Bytes
EDX:EAX with memory64
0000 1111 : 1100 0111 : mod 001 r/m
Table B-17. Pentium Processor Family Instruction Formats and Encodings, 64-Bit Mode
Instruction and Format
Encoding
CMPXCHG8B/CMPXCHG16B – Compare and Exchange Bytes
EDX:EAX with memory64
0000 1111 : 1100 0111 : mod 001 r/m
RDX:RAX with memory128
0100 10XB 0000 1111 : 1100 0111 : mod 001 r/m
B.4
64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION
EXTENSIONS
Non-64-bit mode instruction encodings for MMX Technology, SSE, SSE2, and SSE3 are covered by applying these
rules to Table B-19 through Table B-31. Table B-34 lists special encodings (instructions that do not follow the rules
below).
1. The REX instruction has no effect:
•
•
•
•
On immediates.
If both operands are MMX registers.
On MMX registers and XMM registers.
If an MMX register is encoded in the reg field of the ModR/M byte.
2. If a memory operand is encoded in the r/m field of the ModR/M byte, REX.X and REX.B may be used for
encoding the memory operand.
Vol. 2D B-37
INSTRUCTION FORMATS AND ENCODINGS
3. If a general-purpose register is encoded in the r/m field of the ModR/M byte, REX.B may be used for register
encoding and REX.W may be used to encode the 64-bit operand size.
4. If an XMM register operand is encoded in the reg field of the ModR/M byte, REX.R may be used for register
encoding. If an XMM register operand is encoded in the r/m field of the ModR/M byte, REX.B may be used for
register encoding.
B.5
MMX INSTRUCTION FORMATS AND ENCODINGS
MMX instructions, except the EMMS instruction, use a format similar to the 2-byte Intel Architecture integer
format. Details of subfield encodings within these formats are presented below.
B.5.1
Granularity Field (gg)
The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this
field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-18 shows the encoding of the gg field.
Table B-18. Encoding of Granularity of Data Field (gg)
gg
B.5.2
Granularity of Data
00
Packed Bytes
01
Packed Words
10
Packed Doublewords
11
Quadword
MMX Technology and General-Purpose Register Fields (mmxreg and reg)
When MMX technology registers (mmxreg) are used as operands, they are encoded in the ModR/M byte in the reg
field (bits 5, 4, and 3) and/or the R/M field (bits 2, 1, and 0).
If an MMX instruction operates on a general-purpose register (reg), the register is encoded in the R/M field of the
ModR/M byte.
B.5.3
MMX Instruction Formats and Encodings Table
Table B-19 shows the formats and encodings of the integer instructions.
Table B-19. MMX Instruction Formats and Encodings
Instruction and Format
EMMS – Empty MMX technology state
Encoding
0000 1111:01110111
MOVD – Move doubleword
reg to mmxreg
0000 1111:0110 1110: 11 mmxreg reg
reg from mmxreg
0000 1111:0111 1110: 11 mmxreg reg
mem to mmxreg
0000 1111:0110 1110: mod mmxreg r/m
mem from mmxreg
0000 1111:0111 1110: mod mmxreg r/m
MOVQ – Move quadword
mmxreg2 to mmxreg1
0000 1111:0110 1111: 11 mmxreg1 mmxreg2
mmxreg2 from mmxreg1
0000 1111:0111 1111: 11 mmxreg1 mmxreg2
mem to mmxreg
0000 1111:0110 1111: mod mmxreg r/m
B-38 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-19. MMX Instruction Formats and Encodings (Contd.)
Instruction and Format
mem from mmxreg
Encoding
0000 1111:0111 1111: mod mmxreg r/m
1
PACKSSDW – Pack dword to word data (signed with
saturation)
mmxreg2 to mmxreg1
0000 1111:0110 1011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 1011: mod mmxreg r/m
1
PACKSSWB – Pack word to byte data (signed with
saturation)
mmxreg2 to mmxreg1
0000 1111:0110 0011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 0011: mod mmxreg r/m
PACKUSWB1 – Pack word to byte data (unsigned with
saturation)
mmxreg2 to mmxreg1
0000 1111:0110 0111: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 0111: mod mmxreg r/m
PADD – Add with wrap-around
mmxreg2 to mmxreg1
0000 1111: 1111 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111: 1111 11gg: mod mmxreg r/m
PADDS – Add signed with saturation
mmxreg2 to mmxreg1
0000 1111: 1110 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111: 1110 11gg: mod mmxreg r/m
PADDUS – Add unsigned with saturation
mmxreg2 to mmxreg1
0000 1111: 1101 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111: 1101 11gg: mod mmxreg r/m
PAND – Bitwise And
mmxreg2 to mmxreg1
0000 1111:1101 1011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1101 1011: mod mmxreg r/m
PANDN – Bitwise AndNot
mmxreg2 to mmxreg1
0000 1111:1101 1111: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1101 1111: mod mmxreg r/m
PCMPEQ – Packed compare for equality
mmxreg1 with mmxreg2
0000 1111:0111 01gg: 11 mmxreg1 mmxreg2
mmxreg with memory
0000 1111:0111 01gg: mod mmxreg r/m
PCMPGT – Packed compare greater (signed)
mmxreg1 with mmxreg2
0000 1111:0110 01gg: 11 mmxreg1 mmxreg2
mmxreg with memory
0000 1111:0110 01gg: mod mmxreg r/m
PMADDWD – Packed multiply add
mmxreg2 to mmxreg1
0000 1111:1111 0101: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1111 0101: mod mmxreg r/m
PMULHUW – Packed multiplication, store high word
(unsigned)
mmxreg2 to mmxreg1
0000 1111: 1110 0100: 11 mmxreg1 mmxreg2
Vol. 2D B-39
INSTRUCTION FORMATS AND ENCODINGS
Table B-19. MMX Instruction Formats and Encodings (Contd.)
Instruction and Format
memory to mmxreg
Encoding
0000 1111: 1110 0100: mod mmxreg r/m
PMULHW – Packed multiplication, store high word
mmxreg2 to mmxreg1
0000 1111:1110 0101: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1110 0101: mod mmxreg r/m
PMULLW – Packed multiplication, store low word
mmxreg2 to mmxreg1
0000 1111:1101 0101: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1101 0101: mod mmxreg r/m
POR – Bitwise Or
mmxreg2 to mmxreg1
0000 1111:1110 1011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1110 1011: mod mmxreg r/m
PSLL2 – Packed shift left logical
mmxreg1 by mmxreg2
0000 1111:1111 00gg: 11 mmxreg1 mmxreg2
mmxreg by memory
0000 1111:1111 00gg: mod mmxreg r/m
mmxreg by immediate
0000 1111:0111 00gg: 11 110 mmxreg: imm8 data
PSRA2
– Packed shift right arithmetic
mmxreg1 by mmxreg2
0000 1111:1110 00gg: 11 mmxreg1 mmxreg2
mmxreg by memory
0000 1111:1110 00gg: mod mmxreg r/m
mmxreg by immediate
0000 1111:0111 00gg: 11 100 mmxreg: imm8 data
PSRL2 – Packed shift right logical
mmxreg1 by mmxreg2
0000 1111:1101 00gg: 11 mmxreg1 mmxreg2
mmxreg by memory
0000 1111:1101 00gg: mod mmxreg r/m
mmxreg by immediate
0000 1111:0111 00gg: 11 010 mmxreg: imm8 data
PSUB – Subtract with wrap-around
mmxreg2 from mmxreg1
0000 1111:1111 10gg: 11 mmxreg1 mmxreg2
memory from mmxreg
0000 1111:1111 10gg: mod mmxreg r/m
PSUBS – Subtract signed with saturation
mmxreg2 from mmxreg1
0000 1111:1110 10gg: 11 mmxreg1 mmxreg2
memory from mmxreg
0000 1111:1110 10gg: mod mmxreg r/m
PSUBUS – Subtract unsigned with saturation
mmxreg2 from mmxreg1
0000 1111:1101 10gg: 11 mmxreg1 mmxreg2
memory from mmxreg
0000 1111:1101 10gg: mod mmxreg r/m
PUNPCKH – Unpack high data to next larger type
mmxreg2 to mmxreg1
0000 1111:0110 10gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 10gg: mod mmxreg r/m
PUNPCKL – Unpack low data to next larger type
mmxreg2 to mmxreg1
0000 1111:0110 00gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 00gg: mod mmxreg r/m
B-40 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-19. MMX Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
PXOR – Bitwise Xor
mmxreg2 to mmxreg1
0000 1111:1110 1111: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1110 1111: mod mmxreg r/m
NOTES:
1. The pack instructions perform saturation from signed packed data of one type to signed or unsigned data of the next smaller type.
2. The format of the shift instructions has one additional format to support shifting by immediate shift-counts. The shift operations
are not supported equally for all data types.
B.6
PROCESSOR EXTENDED STATE INSTRUCTION FORMATS AND ENCODINGS
Table B-20 shows the formats and encodings for several instructions that relate to processor extended state
management.
Table B-20. Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions
Instruction and Format
XGETBV – Get Value of Extended Control Register
XRSTOR – Restore Processor Extended
States1
Encoding
0000 1111:0000 0001: 1101 0000
0000 1111:1010 1110: modA 101 r/m
XSAVE – Save Processor Extended States1
0000 1111:1010 1110: modA 100 r/m
XSETBV – Set Extended Control Register
0000 1111:0000 0001: 1101 0001
NOTES:
1. For XSAVE and XRSTOR, “mod = 11” is reserved.
B.7
P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS
Table B-20 shows the formats and encodings for several instructions that were introduced into the IA-32 architecture in the P6 family processors.
Table B-21. Formats and Encodings of P6 Family Instructions
Instruction and Format
Encoding
CMOVcc – Conditional Move
register2 to register1
0000 1111: 0100 tttn : 11 reg1 reg2
memory to register
0000 1111 : 0100 tttn : mod reg r/m
FCMOVcc – Conditional Move on EFLAG Register Condition
Codes
move if below (B)
11011 010 : 11 000 ST(i)
move if equal (E)
11011 010 : 11 001 ST(i)
move if below or equal (BE)
11011 010 : 11 010 ST(i)
move if unordered (U)
11011 010 : 11 011 ST(i)
move if not below (NB)
11011 011 : 11 000 ST(i)
move if not equal (NE)
11011 011 : 11 001 ST(i)
Vol. 2D B-41
INSTRUCTION FORMATS AND ENCODINGS
Table B-21. Formats and Encodings of P6 Family Instructions (Contd.)
Instruction and Format
Encoding
move if not below or equal (NBE)
11011 011 : 11 010 ST(i)
move if not unordered (NU)
11011 011 : 11 011 ST(i)
FCOMI – Compare Real and Set EFLAGS
11011 011 : 11 110 ST(i)
FXRSTOR – Restore x87 FPU, MMX, SSE, and SSE2 State1
0000 1111:1010 1110: modA 001 r/m
FXSAVE – Save x87 FPU, MMX, SSE, and SSE2 State1
0000 1111:1010 1110: modA 000 r/m
SYSENTER – Fast System Call
0000 1111:0011 0100
SYSEXIT – Fast Return from Fast System Call
0000 1111:0011 0101
NOTES:
1. For FXSAVE and FXRSTOR, “mod = 11” is reserved.
B.8
SSE INSTRUCTION FORMATS AND ENCODINGS
The SSE instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are
not duplicated to provide two directions (that is, separate load and store variants).
The following three tables (Tables B-22, B-23, and B-24) show the formats and encodings for the SSE SIMD
floating-point, SIMD integer, and cacheability and memory ordering instructions, respectively. Some SSE instructions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. Mandatory prefixes are included
in the tables.
Table B-22. Formats and Encodings of SSE Floating-Point Instructions
Instruction and Format
Encoding
ADDPS—Add Packed Single-Precision Floating-Point
Values
xmmreg2 to xmmreg1
0000 1111:0101 1000:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1000: mod xmmreg r/m
ADDSS—Add Scalar Single-Precision Floating-Point
Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:01011000:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:01011000: mod xmmreg r/m
ANDNPS—Bitwise Logical AND NOT of Packed SinglePrecision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0101: mod xmmreg r/m
ANDPS—Bitwise Logical AND of Packed SinglePrecision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0100: mod xmmreg r/m
CMPPS—Compare Packed Single-Precision FloatingPoint Values
xmmreg2 to xmmreg1, imm8
0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0000 1111:1100 0010: mod xmmreg r/m: imm8
CMPSS—Compare Scalar Single-Precision FloatingPoint Values
B-42 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
xmmreg2 to xmmreg1, imm8
1111 0011:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
1111 0011:0000 1111:1100 0010: mod xmmreg r/m: imm8
COMISS—Compare Scalar Ordered Single-Precision
Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
0000 1111:0010 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0010 1111: mod xmmreg r/m
CVTPI2PS—Convert Packed Doubleword Integers to
Packed Single-Precision Floating-Point Values
mmreg to xmmreg
0000 1111:0010 1010:11 xmmreg1 mmreg1
mem to xmmreg
0000 1111:0010 1010: mod xmmreg r/m
CVTPS2PI—Convert Packed Single-Precision FloatingPoint Values to Packed Doubleword Integers
xmmreg to mmreg
0000 1111:0010 1101:11 mmreg1 xmmreg1
mem to mmreg
0000 1111:0010 1101: mod mmreg r/m
CVTSI2SS—Convert Doubleword Integer to Scalar
Single-Precision Floating-Point Value
r32 to xmmreg1
1111 0011:0000 1111:00101010:11 xmmreg1 r32
mem to xmmreg
1111 0011:0000 1111:00101010: mod xmmreg r/m
CVTSS2SI—Convert Scalar Single-Precision FloatingPoint Value to Doubleword Integer
xmmreg to r32
1111 0011:0000 1111:0010 1101:11 r32 xmmreg
mem to r32
1111 0011:0000 1111:0010 1101: mod r32 r/m
CVTTPS2PI—Convert with Truncation Packed SinglePrecision Floating-Point Values to Packed Doubleword
Integers
xmmreg to mmreg
0000 1111:0010 1100:11 mmreg1 xmmreg1
mem to mmreg
0000 1111:0010 1100: mod mmreg r/m
CVTTSS2SI—Convert with Truncation Scalar SinglePrecision Floating-Point Value to Doubleword Integer
xmmreg to r32
1111 0011:0000 1111:0010 1100:11 r32 xmmreg1
mem to r32
1111 0011:0000 1111:0010 1100: mod r32 r/m
DIVPS—Divide Packed Single-Precision Floating-Point
Values
xmmreg2 to xmmreg1
0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1110: mod xmmreg r/m
DIVSS—Divide Scalar Single-Precision Floating-Point
Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1110: mod xmmreg r/m
LDMXCSR—Load MXCSR Register State
m32 to MXCSR
0000 1111:1010 1110:modA 010 mem
MAXPS—Return Maximum Packed Single-Precision
Floating-Point Values
Vol. 2D B-43
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
xmmreg2 to xmmreg1
0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1111: mod xmmreg r/m
MAXSS—Return Maximum Scalar Double-Precision
Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1111: mod xmmreg r/m
MINPS—Return Minimum Packed Double-Precision
Floating-Point
Values
xmmreg2 to xmmreg1
0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1101: mod xmmreg r/m
MINSS—Return Minimum Scalar Double-Precision
Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1101: mod xmmreg r/m
MOVAPS—Move Aligned Packed
Single-Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0010 1000:11 xmmreg2 xmmreg1
mem to xmmreg1
0000 1111:0010 1000: mod xmmreg r/m
xmmreg1 to xmmreg2
0000 1111:0010 1001:11 xmmreg1 xmmreg2
xmmreg1 to mem
0000 1111:0010 1001: mod xmmreg r/m
MOVHLPS—Move Packed Single-Precision FloatingPoint Values High to Low
xmmreg2 to xmmreg1
0000 1111:0001 0010:11 xmmreg1 xmmreg2
MOVHPS—Move High Packed Single-Precision
Floating-Point Values
mem to xmmreg
0000 1111:0001 0110: mod xmmreg r/m
xmmreg to mem
0000 1111:0001 0111: mod xmmreg r/m
MOVLHPS—Move Packed Single-Precision FloatingPoint Values Low to High
xmmreg2 to xmmreg1
0000 1111:00010110:11 xmmreg1 xmmreg2
MOVLPS—Move Low Packed Single-Precision FloatingPoint Values
mem to xmmreg
0000 1111:0001 0010: mod xmmreg r/m
xmmreg to mem
0000 1111:0001 0011: mod xmmreg r/m
MOVMSKPS—Extract Packed Single-Precision FloatingPoint Sign Mask
xmmreg to r32
0000 1111:0101 0000:11 r32 xmmreg
MOVSS—Move Scalar Single-Precision Floating-Point
Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0001 0000:11 xmmreg2 xmmreg1
mem to xmmreg1
1111 0011:0000 1111:0001 0000: mod xmmreg r/m
B-44 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
xmmreg1 to xmmreg2
1111 0011:0000 1111:0001 0001:11 xmmreg1 xmmreg2
xmmreg1 to mem
1111 0011:0000 1111:0001 0001: mod xmmreg r/m
MOVUPS—Move Unaligned Packed Single-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0001 0000:11 xmmreg2 xmmreg1
mem to xmmreg1
0000 1111:0001 0000: mod xmmreg r/m
xmmreg1 to xmmreg2
0000 1111:0001 0001:11 xmmreg1 xmmreg2
xmmreg1 to mem
0000 1111:0001 0001: mod xmmreg r/m
MULPS—Multiply Packed Single-Precision FloatingPoint Values
xmmreg2 to xmmreg1
0000 1111:0101 1001:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1001: mod xmmreg r/m
MULSS—Multiply Scalar Single-Precision Floating-Point
Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1001: mod xmmreg r/m
ORPS—Bitwise Logical OR of Single-Precision FloatingPoint Values
xmmreg2 to xmmreg1
0000 1111:0101 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0110: mod xmmreg r/m
RCPPS—Compute Reciprocals of Packed SinglePrecision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0011:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0011: mod xmmreg r/m
RCPSS—Compute Reciprocals of Scalar SinglePrecision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:01010011:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:01010011: mod xmmreg r/m
RSQRTPS—Compute Reciprocals of Square Roots of
Packed Single-Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0010:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0010: mode xmmreg r/m
RSQRTSS—Compute Reciprocals of Square Roots of
Scalar Single-Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 0010:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 0010: mod xmmreg r/m
SHUFPS—Shuffle Packed Single-Precision FloatingPoint Values
xmmreg2 to xmmreg1, imm8
0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0000 1111:1100 0110: mod xmmreg r/m: imm8
SQRTPS—Compute Square Roots of Packed SinglePrecision Floating-Point Values
Vol. 2D B-45
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
xmmreg2 to xmmreg1
0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0001: mod xmmreg r/m
SQRTSS—Compute Square Root of Scalar SinglePrecision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 0001:mod xmmreg r/m
STMXCSR—Store MXCSR Register State
MXCSR to mem
0000 1111:1010 1110:modA 011 mem
SUBPS—Subtract Packed Single-Precision FloatingPoint Values
xmmreg2 to xmmreg1
0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1100:mod xmmreg r/m
SUBSS—Subtract Scalar Single-Precision FloatingPoint Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1100:mod xmmreg r/m
UCOMISS—Unordered Compare Scalar Ordered SinglePrecision Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
0000 1111:0010 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0010 1110: mod xmmreg r/m
UNPCKHPS—Unpack and Interleave High Packed
Single-Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0001 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0001 0101: mod xmmreg r/m
UNPCKLPS—Unpack and Interleave Low Packed
Single-Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0001 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0001 0100: mod xmmreg r/m
XORPS—Bitwise Logical XOR of Single-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0111:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0111: mod xmmreg r/m
B-46 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-23. Formats and Encodings of SSE Integer Instructions
Instruction and Format
Encoding
PAVGB/PAVGW—Average Packed Integers
mmreg2 to mmreg1
0000 1111:1110 0000:11 mmreg1 mmreg2
0000 1111:1110 0011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 0000: mod mmreg r/m
0000 1111:1110 0011: mod mmreg r/m
PEXTRW—Extract Word
mmreg to reg32, imm8
0000 1111:1100 0101:11 r32 mmreg: imm8
PINSRW—Insert Word
reg32 to mmreg, imm8
0000 1111:1100 0100:11 mmreg r32: imm8
m16 to mmreg, imm8
0000 1111:1100 0100: mod mmreg r/m: imm8
PMAXSW—Maximum of Packed Signed Word Integers
mmreg2 to mmreg1
0000 1111:1110 1110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 1110: mod mmreg r/m
PMAXUB—Maximum of Packed Unsigned Byte Integers
mmreg2 to mmreg1
0000 1111:1101 1110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1101 1110: mod mmreg r/m
PMINSW—Minimum of Packed Signed Word Integers
mmreg2 to mmreg1
0000 1111:1110 1010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 1010: mod mmreg r/m
PMINUB—Minimum of Packed Unsigned Byte Integers
mmreg2 to mmreg1
0000 1111:1101 1010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1101 1010: mod mmreg r/m
PMOVMSKB—Move Byte Mask To Integer
mmreg to reg32
0000 1111:1101 0111:11 r32 mmreg
PMULHUW—Multiply Packed Unsigned Integers and Store High
Result
mmreg2 to mmreg1
0000 1111:1110 0100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 0100: mod mmreg r/m
PSADBW—Compute Sum of Absolute Differences
mmreg2 to mmreg1
0000 1111:1111 0110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1111 0110: mod mmreg r/m
PSHUFW—Shuffle Packed Words
mmreg2 to mmreg1, imm8
0000 1111:0111 0000:11 mmreg1 mmreg2: imm8
mem to mmreg, imm8
0000 1111:0111 0000: mod mmreg r/m: imm8
Vol. 2D B-47
INSTRUCTION FORMATS AND ENCODINGS
Table B-24. Format and Encoding of SSE Cacheability & Memory Ordering Instructions
Instruction and Format
Encoding
MASKMOVQ—Store Selected Bytes of Quadword
mmreg2 to mmreg1
0000 1111:1111 0111:11 mmreg1 mmreg2
MOVNTPS—Store Packed Single-Precision Floating-Point Values Using
Non-Temporal Hint
xmmreg to mem
0000 1111:0010 1011: mod xmmreg r/m
MOVNTQ—Store Quadword Using Non-Temporal Hint
mmreg to mem
0000 1111:1110 0111: mod mmreg r/m
PREFETCHT0—Prefetch Temporal to All Cache Levels
0000 1111:0001 1000:modA 001 mem
PREFETCHT1—Prefetch Temporal to First Level Cache
0000 1111:0001 1000:modA 010 mem
PREFETCHT2—Prefetch Temporal to Second Level Cache
0000 1111:0001 1000:modA 011 mem
PREFETCHNTA—Prefetch Non-Temporal to All Cache Levels
0000 1111:0001 1000:modA 000 mem
SFENCE—Store Fence
0000 1111:1010 1110:11 111 000
B.9
SSE2 INSTRUCTION FORMATS AND ENCODINGS
The SSE2 instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are
not duplicated to provide two directions (that is, separate load and store variants).
The following three tables show the formats and encodings for the SSE2 SIMD floating-point, SIMD integer, and
cacheability instructions, respectively. Some SSE2 instructions require a mandatory prefix (66H, F2H, F3H) as part
of the two-byte opcode. These prefixes are included in the tables.
B.9.1
Granularity Field (gg)
The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this
field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-25 shows the encoding of this gg field.
Table B-25. Encoding of Granularity of Data Field (gg)
gg
B-48 Vol. 2D
Granularity of Data
00
Packed Bytes
01
Packed Words
10
Packed Doublewords
11
Quadword
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions
Instruction and Format
Encoding
ADDPD—Add Packed Double-Precision FloatingPoint Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1000:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1000: mod xmmreg r/m
ADDSD—Add Scalar Double-Precision Floating-Point
Values
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1000:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1000: mod xmmreg r/m
ANDNPD—Bitwise Logical AND NOT of Packed
Double-Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0101: mod xmmreg r/m
ANDPD—Bitwise Logical AND of Packed DoublePrecision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0100: mod xmmreg r/m
CMPPD—Compare Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:1100 0010: mod xmmreg r/m: imm8
CMPSD—Compare Scalar Double-Precision FloatingPoint Values
xmmreg2 to xmmreg1, imm8
1111 0010:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
11110 010:0000 1111:1100 0010: mod xmmreg r/m: imm8
COMISD—Compare Scalar Ordered Double-Precision
Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
0110 0110:0000 1111:0010 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0010 1111: mod xmmreg r/m
CVTPI2PD—Convert Packed Doubleword Integers to
Packed Double-Precision Floating-Point Values
mmreg to xmmreg
0110 0110:0000 1111:0010 1010:11 xmmreg1 mmreg1
mem to xmmreg
0110 0110:0000 1111:0010 1010: mod xmmreg r/m
CVTPD2PI—Convert Packed Double-Precision
Floating-Point Values to Packed Doubleword
Integers
xmmreg to mmreg
0110 0110:0000 1111:0010 1101:11 mmreg1 xmmreg1
mem to mmreg
0110 0110:0000 1111:0010 1101: mod mmreg r/m
CVTSI2SD—Convert Doubleword Integer to Scalar
Double-Precision Floating-Point Value
r32 to xmmreg1
1111 0010:0000 1111:0010 1010:11 xmmreg r32
mem to xmmreg
1111 0010:0000 1111:0010 1010: mod xmmreg r/m
CVTSD2SI—Convert Scalar Double-Precision
Floating-Point Value to Doubleword Integer
Vol. 2D B-49
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
xmmreg to r32
1111 0010:0000 1111:0010 1101:11 r32 xmmreg
mem to r32
1111 0010:0000 1111:0010 1101: mod r32 r/m
CVTTPD2PI—Convert with Truncation Packed
Double-Precision Floating-Point Values to Packed
Doubleword Integers
xmmreg to mmreg
0110 0110:0000 1111:0010 1100:11 mmreg xmmreg
mem to mmreg
0110 0110:0000 1111:0010 1100: mod mmreg r/m
CVTTSD2SI—Convert with
Truncation Scalar Double-Precision Floating-Point
Value to Doubleword Integer
xmmreg to r32
1111 0010:0000 1111:0010 1100:11 r32 xmmreg
mem to r32
1111 0010:0000 1111:0010 1100: mod r32 r/m
CVTPD2PS—Covert Packed Double-Precision
Floating-Point Values to Packed Single-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1010: mod xmmreg r/m
CVTPS2PD—Covert Packed Single-Precision
Floating-Point Values to Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1010: mod xmmreg r/m
CVTSD2SS—Covert Scalar Double-Precision
Floating-Point Value to Scalar Single-Precision
Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1010: mod xmmreg r/m
CVTSS2SD—Covert Scalar Single-Precision FloatingPoint Value to Scalar Double-Precision FloatingPoint Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:00001 111:0101 1010: mod xmmreg r/m
CVTPD2DQ—Convert Packed Double-Precision
Floating-Point Values to Packed Doubleword
Integers
xmmreg2 to xmmreg1
1111 0010:0000 1111:1110 0110:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:1110 0110: mod xmmreg r/m
CVTTPD2DQ—Convert With Truncation Packed
Double-Precision Floating-Point Values to Packed
Doubleword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1110 0110: mod xmmreg r/m
B-50 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
CVTDQ2PD—Convert Packed Doubleword Integers
to Packed Single-Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:1110 0110:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:1110 0110: mod xmmreg r/m
CVTPS2DQ—Convert Packed Single-Precision
Floating-Point Values to Packed Doubleword
Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1011:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1011: mod xmmreg r/m
CVTTPS2DQ—Convert With Truncation Packed
Single-Precision Floating-Point Values to Packed
Doubleword Integers
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1011:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1011: mod xmmreg r/m
CVTDQ2PS—Convert Packed Doubleword Integers
to Packed Double-Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1011:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1011: mod xmmreg r/m
DIVPD—Divide Packed Double-Precision FloatingPoint Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1110: mod xmmreg r/m
DIVSD—Divide Scalar Double-Precision FloatingPoint Values
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1110: mod xmmreg r/m
MAXPD—Return Maximum Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1111: mod xmmreg r/m
MAXSD—Return Maximum Scalar Double-Precision
Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1111: mod xmmreg r/m
MINPD—Return Minimum Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1101: mod xmmreg r/m
MINSD—Return Minimum Scalar Double-Precision
Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1101: mod xmmreg r/m
Vol. 2D B-51
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
MOVAPD—Move Aligned Packed Double-Precision
Floating-Point Values
xmmreg1 to xmmreg2
0110 0110:0000 1111:0010 1001:11 xmmreg2 xmmreg1
xmmreg1 to mem
0110 0110:0000 1111:0010 1001: mod xmmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0010 1000:11 xmmreg1 xmmreg2
mem to xmmreg1
0110 0110:0000 1111:0010 1000: mod xmmreg r/m
MOVHPD—Move High Packed Double-Precision
Floating-Point Values
xmmreg to mem
0110 0110:0000 1111:0001 0111: mod xmmreg r/m
mem to xmmreg
0110 0110:0000 1111:0001 0110: mod xmmreg r/m
MOVLPD—Move Low Packed Double-Precision
Floating-Point Values
xmmreg to mem
0110 0110:0000 1111:0001 0011: mod xmmreg r/m
mem to xmmreg
0110 0110:0000 1111:0001 0010: mod xmmreg r/m
MOVMSKPD—Extract Packed Double-Precision
Floating-Point Sign Mask
xmmreg to r32
0110 0110:0000 1111:0101 0000:11 r32 xmmreg
MOVSD—Move Scalar Double-Precision FloatingPoint Values
xmmreg1 to xmmreg2
1111 0010:0000 1111:0001 0001:11 xmmreg2 xmmreg1
xmmreg1 to mem
1111 0010:0000 1111:0001 0001: mod xmmreg r/m
xmmreg2 to xmmreg1
1111 0010:0000 1111:0001 0000:11 xmmreg1 xmmreg2
mem to xmmreg1
1111 0010:0000 1111:0001 0000: mod xmmreg r/m
MOVUPD—Move Unaligned Packed DoublePrecision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0001 0001:11 xmmreg2 xmmreg1
mem to xmmreg1
0110 0110:0000 1111:0001 0001: mod xmmreg r/m
xmmreg1 to xmmreg2
0110 0110:0000 1111:0001 0000:11 xmmreg1 xmmreg2
xmmreg1 to mem
0110 0110:0000 1111:0001 0000: mod xmmreg r/m
MULPD—Multiply Packed Double-Precision FloatingPoint Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1001:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1001: mod xmmreg r/m
MULSD—Multiply Scalar Double-Precision FloatingPoint Values
xmmreg2 to xmmreg1
1111 0010:00001111:01011001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:00001111:01011001: mod xmmreg r/m
ORPD—Bitwise Logical OR of
Double-Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0110: mod xmmreg r/m
B-52 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
SHUFPD—Shuffle Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:1100 0110: mod xmmreg r/m: imm8
SQRTPD—Compute Square Roots of Packed DoublePrecision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0001: mod xmmreg r/m
SQRTSD—Compute Square Root of Scalar DoublePrecision Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 0001: mod xmmreg r/m
SUBPD—Subtract Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1100: mod xmmreg r/m
SUBSD—Subtract Scalar Double-Precision FloatingPoint Values
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1100: mod xmmreg r/m
UCOMISD—Unordered Compare Scalar Ordered
Double-Precision Floating-Point Values and Set
EFLAGS
xmmreg2 to xmmreg1
0110 0110:0000 1111:0010 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0010 1110: mod xmmreg r/m
UNPCKHPD—Unpack and Interleave High Packed
Double-Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0001 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0001 0101: mod xmmreg r/m
UNPCKLPD—Unpack and Interleave Low Packed
Double-Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0001 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0001 0100: mod xmmreg r/m
XORPD—Bitwise Logical OR of Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0111: mod xmmreg r/m
Vol. 2D B-53
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions
Instruction and Format
Encoding
MOVD—Move Doubleword
reg to xmmreg
0110 0110:0000 1111:0110 1110: 11 xmmreg reg
reg from xmmreg
0110 0110:0000 1111:0111 1110: 11 xmmreg reg
mem to xmmreg
0110 0110:0000 1111:0110 1110: mod xmmreg r/m
mem from xmmreg
0110 0110:0000 1111:0111 1110: mod xmmreg r/m
MOVDQA—Move Aligned Double Quadword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1111:11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1
0110 0110:0000 1111:0111 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 1111: mod xmmreg r/m
mem from xmmreg
0110 0110:0000 1111:0111 1111: mod xmmreg r/m
MOVDQU—Move Unaligned Double Quadword
xmmreg2 to xmmreg1
1111 0011:0000 1111:0110 1111:11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1
1111 0011:0000 1111:0111 1111:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0110 1111: mod xmmreg r/m
mem from xmmreg
1111 0011:0000 1111:0111 1111: mod xmmreg r/m
MOVQ2DQ—Move Quadword from MMX to XMM
Register
mmreg to xmmreg
1111 0011:0000 1111:1101 0110:11 mmreg1 mmreg2
MOVDQ2Q—Move Quadword from XMM to MMX
Register
xmmreg to mmreg
1111 0010:0000 1111:1101 0110:11 mmreg1 mmreg2
MOVQ—Move Quadword
xmmreg2 to xmmreg1
1111 0011:0000 1111:0111 1110: 11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1
0110 0110:0000 1111:1101 0110: 11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0111 1110: mod xmmreg r/m
mem from xmmreg
0110 0110:0000 1111:1101 0110: mod xmmreg r/m
PACKSSDW1—Pack
with saturation)
Dword To Word Data (signed
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:0110 1011: mod xmmreg r/m
PACKSSWB—Pack Word To Byte Data (signed with
saturation)
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 0011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:0110 0011: mod xmmreg r/m
PACKUSWB—Pack Word To Byte Data (unsigned
with saturation)
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 0111: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:0110 0111: mod xmmreg r/m
PADDQ—Add Packed Quadword Integers
mmreg2 to mmreg1
B-54 Vol. 2D
0000 1111:1101 0100:11 mmreg1 mmreg2
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
mem to mmreg
Encoding
0000 1111:1101 0100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1101 0100: mod xmmreg r/m
PADD—Add With Wrap-around
xmmreg2 to xmmreg1
0110 0110:0000 1111: 1111 11gg: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111: 1111 11gg: mod xmmreg r/m
PADDS—Add Signed With Saturation
xmmreg2 to xmmreg1
0110 0110:0000 1111: 1110 11gg: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111: 1110 11gg: mod xmmreg r/m
PADDUS—Add Unsigned With Saturation
xmmreg2 to xmmreg1
0110 0110:0000 1111: 1101 11gg: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111: 1101 11gg: mod xmmreg r/m
PAND—Bitwise And
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1101 1011: mod xmmreg r/m
PANDN—Bitwise AndNot
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1111: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1101 1111: mod xmmreg r/m
PAVGB—Average Packed Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:11100 000:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:11100000 mod xmmreg r/m
PAVGW—Average Packed Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0011:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1110 0011 mod xmmreg r/m
PCMPEQ—Packed Compare For Equality
xmmreg1 with xmmreg2
0110 0110:0000 1111:0111 01gg: 11 xmmreg1 xmmreg2
xmmreg with memory
0110 0110:0000 1111:0111 01gg: mod xmmreg r/m
PCMPGT—Packed Compare Greater (signed)
xmmreg1 with xmmreg2
0110 0110:0000 1111:0110 01gg: 11 xmmreg1 xmmreg2
xmmreg with memory
0110 0110:0000 1111:0110 01gg: mod xmmreg r/m
PEXTRW—Extract Word
xmmreg to reg32, imm8
0110 0110:0000 1111:1100 0101:11 r32 xmmreg: imm8
PINSRW—Insert Word
reg32 to xmmreg, imm8
0110 0110:0000 1111:1100 0100:11 xmmreg r32: imm8
m16 to xmmreg, imm8
0110 0110:0000 1111:1100 0100: mod xmmreg r/m: imm8
PMADDWD—Packed Multiply Add
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 0101: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1111 0101: mod xmmreg r/m
Vol. 2D B-55
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
Encoding
PMAXSW—Maximum of Packed Signed Word
Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1110:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:11101110: mod xmmreg r/m
PMAXUB—Maximum of Packed Unsigned Byte
Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1101 1110: mod xmmreg r/m
PMINSW—Minimum of Packed Signed Word Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1110 1010: mod xmmreg r/m
PMINUB—Minimum of Packed Unsigned Byte
Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1101 1010 mod xmmreg r/m
PMOVMSKB—Move Byte Mask To Integer
xmmreg to reg32
0110 0110:0000 1111:1101 0111:11 r32 xmmreg
PMULHUW—Packed multiplication, store high word
(unsigned)
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0100: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 0100: mod xmmreg r/m
PMULHW—Packed Multiplication, store high word
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0101: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 0101: mod xmmreg r/m
PMULLW—Packed Multiplication, store low word
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 0101: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1101 0101: mod xmmreg r/m
PMULUDQ—Multiply Packed Unsigned Doubleword
Integers
mmreg2 to mmreg1
0000 1111:1111 0100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1111 0100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:00001111:1111 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:00001111:1111 0100: mod xmmreg r/m
POR—Bitwise Or
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 1011: mod xmmreg r/m
PSADBW—Compute Sum of Absolute Differences
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1111 0110: mod xmmreg r/m
PSHUFLW—Shuffle Packed Low Words
B-56 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
Encoding
xmmreg2 to xmmreg1, imm8
1111 0010:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
1111 0010:0000 1111:0111 0000:11 mod xmmreg r/m: imm8
PSHUFHW—Shuffle Packed High Words
xmmreg2 to xmmreg1, imm8
1111 0011:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
1111 0011:0000 1111:0111 0000: mod xmmreg r/m: imm8
PSHUFD—Shuffle Packed Doublewords
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0111 0000: mod xmmreg r/m: imm8
PSLLDQ—Shift Double Quadword Left Logical
xmmreg, imm8
0110 0110:0000 1111:0111 0011:11 111 xmmreg: imm8
PSLL—Packed Shift Left Logical
xmmreg1 by xmmreg2
0110 0110:0000 1111:1111 00gg: 11 xmmreg1 xmmreg2
xmmreg by memory
0110 0110:0000 1111:1111 00gg: mod xmmreg r/m
xmmreg by immediate
0110 0110:0000 1111:0111 00gg: 11 110 xmmreg: imm8
PSRA—Packed Shift Right Arithmetic
xmmreg1 by xmmreg2
0110 0110:0000 1111:1110 00gg: 11 xmmreg1 xmmreg2
xmmreg by memory
0110 0110:0000 1111:1110 00gg: mod xmmreg r/m
xmmreg by immediate
0110 0110:0000 1111:0111 00gg: 11 100 xmmreg: imm8
PSRLDQ—Shift Double Quadword Right Logical
xmmreg, imm8
0110 0110:00001111:01110011:11 011 xmmreg: imm8
PSRL—Packed Shift Right Logical
xmmreg1 by xmmreg2
0110 0110:0000 1111:1101 00gg: 11 xmmreg1 xmmreg2
xmmreg by memory
0110 0110:0000 1111:1101 00gg: mod xmmreg r/m
xmmreg by immediate
0110 0110:0000 1111:0111 00gg: 11 010 xmmreg: imm8
PSUBQ—Subtract Packed Quadword Integers
mmreg2 to mmreg1
0000 1111:11111 011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1111 1011: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 1011:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1111 1011: mod xmmreg r/m
PSUB—Subtract With Wrap-around
xmmreg2 from xmmreg1
0110 0110:0000 1111:1111 10gg: 11 xmmreg1 xmmreg2
memory from xmmreg
0110 0110:0000 1111:1111 10gg: mod xmmreg r/m
PSUBS—Subtract Signed With Saturation
xmmreg2 from xmmreg1
0110 0110:0000 1111:1110 10gg: 11 xmmreg1 xmmreg2
memory from xmmreg
0110 0110:0000 1111:1110 10gg: mod xmmreg r/m
PSUBUS—Subtract Unsigned With Saturation
xmmreg2 from xmmreg1
0000 1111:1101 10gg: 11 xmmreg1 xmmreg2
memory from xmmreg
0000 1111:1101 10gg: mod xmmreg r/m
Vol. 2D B-57
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
Encoding
PUNPCKH—Unpack High Data To Next Larger Type
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 10gg:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 10gg: mod xmmreg r/m
PUNPCKHQDQ—Unpack High Data
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 1101: mod xmmreg r/m
PUNPCKL—Unpack Low Data To Next Larger Type
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 00gg:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 00gg: mod xmmreg r/m
PUNPCKLQDQ—Unpack Low Data
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 1100: mod xmmreg r/m
PXOR—Bitwise Xor
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1111: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 1111: mod xmmreg r/m
Table B-28. Format and Encoding of SSE2 Cacheability Instructions
Instruction and Format
Encoding
MASKMOVDQU—Store Selected Bytes of Double
Quadword
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 0111:11 xmmreg1 xmmreg2
CLFLUSH—Flush Cache Line
mem
0000 1111:1010 1110: mod 111 r/m
MOVNTPD—Store Packed Double-Precision
Floating-Point Values Using Non-Temporal Hint
xmmreg to mem
0110 0110:0000 1111:0010 1011: mod xmmreg r/m
MOVNTDQ—Store Double Quadword Using NonTemporal Hint
xmmreg to mem
0110 0110:0000 1111:1110 0111: mod xmmreg r/m
MOVNTI—Store Doubleword Using Non-Temporal
Hint
reg to mem
0000 1111:1100 0011: mod reg r/m
PAUSE—Spin Loop Hint
1111 0011:1001 0000
LFENCE—Load Fence
0000 1111:1010 1110: 11 101 000
MFENCE—Memory Fence
0000 1111:1010 1110: 11 110 000
B-58 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
B.10
SSE3 FORMATS AND ENCODINGS TABLE
The tables in this section provide SSE3 formats and encodings. Some SSE3 instructions require a mandatory prefix
(66H, F2H, F3H) as part of the two-byte opcode. These prefixes are included in the tables.
When in IA-32e mode, use of the REX.R prefix permits instructions that use general purpose and XMM registers to
access additional registers. Some instructions require the REX.W prefix to promote the instruction to 64-bit operation. Instructions that require the REX.W prefix are listed (with their opcodes) in Section B.13.
Table B-29. Formats and Encodings of SSE3 Floating-Point Instructions
Instruction and Format
Encoding
ADDSUBPD—Add /Sub packed DP FP numbers from
XMM2/Mem to XMM1
xmmreg2 to xmmreg1
01100110:00001111:11010000:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:11010000: mod xmmreg r/m
ADDSUBPS—Add /Sub packed SP FP numbers from
XMM2/Mem to XMM1
xmmreg2 to xmmreg1
11110010:00001111:11010000:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:11010000: mod xmmreg r/m
HADDPD—Add horizontally packed DP FP numbers
XMM2/Mem to XMM1
xmmreg2 to xmmreg1
01100110:00001111:01111100:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:01111100: mod xmmreg r/m
HADDPS—Add horizontally packed SP FP numbers
XMM2/Mem to XMM1
xmmreg2 to xmmreg1
11110010:00001111:01111100:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:01111100: mod xmmreg r/m
HSUBPD—Sub horizontally packed DP FP numbers
XMM2/Mem to XMM1
xmmreg2 to xmmreg1
01100110:00001111:01111101:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:01111101: mod xmmreg r/m
HSUBPS—Sub horizontally packed SP FP numbers
XMM2/Mem to XMM1
xmmreg2 to xmmreg1
11110010:00001111:01111101:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:01111101: mod xmmreg r/m
Table B-30. Formats and Encodings for SSE3 Event Management Instructions
Instruction and Format
Encoding
MONITOR—Set up a linear address range to be monitored
by hardware
eax, ecx, edx
0000 1111 : 0000 0001:11 001 000
MWAIT—Wait until write-back store performed within the
range specified by the instruction MONITOR
eax, ecx
0000 1111 : 0000 0001:11 001 001
Vol. 2D B-59
INSTRUCTION FORMATS AND ENCODINGS
Table B-31. Formats and Encodings for SSE3 Integer and Move Instructions
Instruction and Format
Encoding
FISTTP—Store ST in int16 (chop) and pop
11011 111 : modA 001 r/m
m16int
FISTTP—Store ST in int32 (chop) and pop
11011 011 : modA 001 r/m
m32int
FISTTP—Store ST in int64 (chop) and pop
11011 101 : modA 001 r/m
m64int
LDDQU—Load unaligned integer 128-bit
11110010:00001111:11110000: modA xmmreg r/m
xmm, m128
MOVDDUP—Move 64 bits representing one DP data from
XMM2/Mem to XMM1 and duplicate
xmmreg2 to xmmreg1
11110010:00001111:00010010:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:00010010: mod xmmreg r/m
MOVSHDUP—Move 128 bits representing 4 SP data from
XMM2/Mem to XMM1 and duplicate high
xmmreg2 to xmmreg1
11110011:00001111:00010110:11 xmmreg1 xmmreg2
mem to xmmreg
11110011:00001111:00010110: mod xmmreg r/m
MOVSLDUP—Move 128 bits representing 4 SP data from
XMM2/Mem to XMM1 and duplicate low
xmmreg2 to xmmreg1
11110011:00001111:00010010:11 xmmreg1 xmmreg2
mem to xmmreg
11110011:00001111:00010010: mod xmmreg r/m
B.11
SSSE3 FORMATS AND ENCODING TABLE
The tables in this section provide SSSE3 formats and encodings. Some SSSE3 instructions require a mandatory
prefix (66H) as part of the three-byte opcode. These prefixes are included in the table below.
Table B-32. Formats and Encodings for SSSE3 Instructions
Instruction and Format
Encoding
PABSB—Packed Absolute Value Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0001 1100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0001 1100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 1100: mod xmmreg r/m
PABSD—Packed Absolute Value Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0001 1110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0001 1110: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 1110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 1110: mod xmmreg r/m
PABSW—Packed Absolute Value Words
B-60 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-32. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format
Encoding
mmreg2 to mmreg1
0000 1111:0011 1000: 0001 1101:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0001 1101: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 1101: mod xmmreg r/m
PALIGNR—Packed Align Right
mmreg2 to mmreg1, imm8
0000 1111:0011 1010: 0000 1111:11 mmreg1 mmreg2: imm8
mem to mmreg, imm8
0000 1111:0011 1010: 0000 1111: mod mmreg r/m: imm8
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1111:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1111: mod xmmreg r/m:
imm8
PHADDD—Packed Horizontal Add Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0010: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0010: mod xmmreg r/m
PHADDSW—Packed Horizontal Add and Saturate
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0011: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0011: mod xmmreg r/m
PHADDW—Packed Horizontal Add Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0001:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0001: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0001: mod xmmreg r/m
PHSUBD—Packed Horizontal Subtract Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0110: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0110: mod xmmreg r/m
PHSUBSW—Packed Horizontal Subtract and Saturate
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0111:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0111: mod mmreg r/m
Vol. 2D B-61
INSTRUCTION FORMATS AND ENCODINGS
Table B-32. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format
Encoding
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0111: mod xmmreg r/m
PHSUBW—Packed Horizontal Subtract Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0101:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0101: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0101: mod xmmreg r/m
PMADDUBSW—Multiply and Add Packed Signed and
Unsigned Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0100: mod xmmreg r/m
PMULHRSW—Packed Multiply HIgn with Round and Scale
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1011: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1011: mod xmmreg r/m
PSHUFB—Packed Shuffle Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0000:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0000: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0000: mod xmmreg r/m
PSIGNB—Packed Sign Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1000:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1000: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1000: mod xmmreg r/m
PSIGND—Packed Sign Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1010: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1010: mod xmmreg r/m
PSIGNW—Packed Sign Words
B-62 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-32. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format
Encoding
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1001:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1001: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1001: mod xmmreg r/m
B.12
AESNI AND PCLMULQDQ INSTRUCTION FORMATS AND ENCODINGS
Table B-33 shows the formats and encodings for AESNI and PCLMULQDQ instructions.
Table B-33. Formats and Encodings of AESNI and PCLMULQDQ Instructions
Instruction and Format
Encoding
AESDEC—Perform One Round of an AES Decryption Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1110: mod xmmreg r/m
AESDECLAST—Perform Last Round of an AES Decryption
Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1111: mod xmmreg r/m
AESENC—Perform One Round of an AES Encryption Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1100: mod xmmreg r/m
AESENCLAST—Perform Last Round of an AES Encryption
Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1101: mod xmmreg r/m
AESIMC—Perform the AES InvMixColumn Transformation
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1011: mod xmmreg r/m
AESKEYGENASSIST—AES Round Key Generation Assist
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010:1101 1111:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010:1101 1111: mod xmmreg r/m:
imm8
PCLMULQDQ—Carry-Less Multiplication Quadword
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010:0100 0100:11 xmmreg1
xmmreg2: imm8
Vol. 2D B-63
INSTRUCTION FORMATS AND ENCODINGS
Table B-33. Formats and Encodings of AESNI and PCLMULQDQ Instructions
Instruction and Format
mem to xmmreg, imm8
B.13
Encoding
0110 0110:0000 1111:0011 1010:0100 0100: mod xmmreg r/m:
imm8
SPECIAL ENCODINGS FOR 64-BIT MODE
The following Pentium, P6, MMX, SSE, SSE2, SSE3 instructions are promoted to 64-bit operation in IA-32e mode
by using REX.W. However, these entries are special cases that do not follow the general rules (specified in Section
B.4).
Table B-34. Special Case Instructions Promoted Using REX.W
Instruction and Format
Encoding
CMOVcc—Conditional Move
register2 to register1
0100 0R0B 0000 1111: 0100 tttn : 11 reg1 reg2
qwordregister2 to qwordregister1
0100 1R0B 0000 1111: 0100 tttn : 11 qwordreg1 qwordreg2
memory to register
0100 0RXB 0000 1111 : 0100 tttn : mod reg r/m
memory64 to qwordregister
0100 1RXB 0000 1111 : 0100 tttn : mod qwordreg r/m
CVTSD2SI—Convert Scalar Double-Precision Floating-Point
Value to Doubleword Integer
xmmreg to r32
0100 0R0B 1111 0010:0000 1111:0010 1101:11 r32
xmmreg
xmmreg to r64
0100 1R0B 1111 0010:0000 1111:0010 1101:11 r64
xmmreg
mem64 to r32
0100 0R0XB 1111 0010:0000 1111:0010 1101: mod r32 r/m
mem64 to r64
0100 1RXB 1111 0010:0000 1111:0010 1101: mod r64 r/m
CVTSI2SS—Convert Doubleword Integer to Scalar SinglePrecision Floating-Point Value
r32 to xmmreg1
0100 0R0B 1111 0011:0000 1111:0010 1010:11 xmmreg
r32
r64 to xmmreg1
0100 1R0B 1111 0011:0000 1111:0010 1010:11 xmmreg
r64
mem to xmmreg
0100 0RXB 1111 0011:0000 1111:0010 1010: mod xmmreg
r/m
mem64 to xmmreg
0100 1RXB 1111 0011:0000 1111:0010 1010: mod xmmreg
r/m
CVTSI2SD—Convert Doubleword Integer to Scalar DoublePrecision Floating-Point Value
r32 to xmmreg1
0100 0R0B 1111 0010:0000 1111:0010 1010:11 xmmreg
r32
r64 to xmmreg1
0100 1R0B 1111 0010:0000 1111:0010 1010:11 xmmreg
r64
mem to xmmreg
0100 0RXB 1111 0010:0000 1111:00101 010: mod xmmreg
r/m
B-64 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)
Instruction and Format
mem64 to xmmreg
Encoding
0100 1RXB 1111 0010:0000 1111:0010 1010: mod xmmreg
r/m
CVTSS2SI—Convert Scalar Single-Precision Floating-Point
Value to Doubleword Integer
xmmreg to r32
0100 0R0B 1111 0011:0000 1111:0010 1101:11 r32
xmmreg
xmmreg to r64
0100 1R0B 1111 0011:0000 1111:0010 1101:11 r64
xmmreg
mem to r32
0100 0RXB 11110011:00001111:00101101: mod r32 r/m
mem32 to r64
0100 1RXB 1111 0011:0000 1111:0010 1101: mod r64 r/m
CVTTSD2SI—Convert with Truncation Scalar Double-Precision
Floating-Point Value to Doubleword Integer
xmmreg to r32
0100 0R0B 11110010:00001111:00101100:11 r32 xmmreg
xmmreg to r64
0100 1R0B 1111 0010:0000 1111:0010 1100:11 r64
xmmreg
mem64 to r32
0100 0RXB 1111 0010:0000 1111:0010 1100: mod r32 r/m
mem64 to r64
0100 1RXB 1111 0010:0000 1111:0010 1100: mod r64 r/m
CVTTSS2SI—Convert with Truncation Scalar Single-Precision
Floating-Point Value to Doubleword Integer
xmmreg to r32
0100 0R0B 1111 0011:0000 1111:0010 1100:11 r32
xmmreg1
xmmreg to r64
0100 1R0B 1111 0011:0000 1111:0010 1100:11 r64
xmmreg1
mem to r32
0100 0RXB 1111 0011:0000 1111:0010 1100: mod r32 r/m
mem32 to r64
0100 1RXB 1111 0011:0000 1111:0010 1100: mod r64 r/m
MOVD/MOVQ—Move doubleword
reg to mmxreg
0100 0R0B 0000 1111:0110 1110: 11 mmxreg reg
qwordreg to mmxreg
0100 1R0B 0000 1111:0110 1110: 11 mmxreg qwordreg
reg from mmxreg
0100 0R0B 0000 1111:0111 1110: 11 mmxreg reg
qwordreg from mmxreg
0100 1R0B 0000 1111:0111 1110: 11 mmxreg qwordreg
mem to mmxreg
0100 0RXB 0000 1111:0110 1110: mod mmxreg r/m
mem64 to mmxreg
0100 1RXB 0000 1111:0110 1110: mod mmxreg r/m
mem from mmxreg
0100 0RXB 0000 1111:0111 1110: mod mmxreg r/m
mem64 from mmxreg
0100 1RXB 0000 1111:0111 1110: mod mmxreg r/m
mmxreg with memory
0100 0RXB 0000 1111:0110 01gg: mod mmxreg r/m
MOVMSKPS—Extract Packed Single-Precision Floating-Point
Sign Mask
xmmreg to r32
0100 0R0B 0000 1111:0101 0000:11 r32 xmmreg
xmmreg to r64
0100 1R0B 00001111:01010000:11 r64 xmmreg
PEXTRW—Extract Word
mmreg to reg32, imm8
0100 0R0B 0000 1111:1100 0101:11 r32 mmreg: imm8
Vol. 2D B-65
INSTRUCTION FORMATS AND ENCODINGS
Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)
Instruction and Format
Encoding
mmreg to reg64, imm8
0100 1R0B 0000 1111:1100 0101:11 r64 mmreg: imm8
xmmreg to reg32, imm8
0100 0R0B 0110 0110 0000 1111:1100 0101:11 r32
xmmreg: imm8
xmmreg to reg64, imm8
0100 1R0B 0110 0110 0000 1111:1100 0101:11 r64
xmmreg: imm8
PINSRW—Insert Word
reg32 to mmreg, imm8
0100 0R0B 0000 1111:1100 0100:11 mmreg r32: imm8
reg64 to mmreg, imm8
0100 1R0B 0000 1111:1100 0100:11 mmreg r64: imm8
m16 to mmreg, imm8
0100 0R0B 0000 1111:1100 0100 mod mmreg r/m: imm8
m16 to mmreg, imm8
0100 1RXB 0000 1111:11000100 mod mmreg r/m: imm8
reg32 to xmmreg, imm8
0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg
r32: imm8
reg64 to xmmreg, imm8
0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg
r64: imm8
m16 to xmmreg, imm8
0100 0RXB 0110 0110 0000 1111:1100 0100 mod xmmreg
r/m: imm8
m16 to xmmreg, imm8
0100 1RXB 0110 0110 0000 1111:1100 0100 mod xmmreg
r/m: imm8
PMOVMSKB—Move Byte Mask To Integer
mmreg to reg32
0100 0RXB 0000 1111:1101 0111:11 r32 mmreg
mmreg to reg64
0100 1R0B 0000 1111:1101 0111:11 r64 mmreg
xmmreg to reg32
0100 0RXB 0110 0110 0000 1111:1101 0111:11 r32 mmreg
xmmreg to reg64
0110 0110 0000 1111:1101 0111:11 r64 xmmreg
B.14
SSE4.1 FORMATS AND ENCODING TABLE
The tables in this section provide SSE4.1 formats and encodings. Some SSE4.1 instructions require a mandatory
prefix (66H, F2H, F3H) as part of the three-byte opcode. These prefixes are included in the tables.
In 64-bit mode, some instructions requires REX.W, the byte sequence of REX.W prefix in the opcode sequence is
shown.
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
BLENDPD — Blend Packed Double-Precision Floats
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1010: 0000 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0000 1101: mod xmmreg r/m
BLENDPS — Blend Packed Single-Precision Floats
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1010: 0000 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0000 1100: mod xmmreg r/m
BLENDVPD — Variable Blend Packed Double-Precision
Floats
B-66 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 0101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 0101: mod xmmreg r/m
BLENDVPS — Variable Blend Packed Single-Precision Floats
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 0100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 0100: mod xmmreg r/m
DPPD — Packed Double-Precision Dot Products
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0100 0001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0100 0001: mod xmmreg r/m:
imm8
DPPS — Packed Single-Precision Dot Products
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0100 0000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0100 0000: mod xmmreg r/m:
imm8
EXTRACTPS — Extract From Packed Single-Precision Floats
reg from xmmreg , imm8
0110 0110:0000 1111:0011 1010: 0001 0111:11 xmmreg reg:
imm8
mem from xmmreg , imm8
0110 0110:0000 1111:0011 1010: 0001 0111: mod xmmreg r/m:
imm8
INSERTPS — Insert Into Packed Single-Precision Floats
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0010 0001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0001: mod xmmreg r/m:
imm8
MOVNTDQA — Load Double Quadword Non-temporal
Aligned
m128 to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1010:11 r/m xmmreg2
MPSADBW — Multiple Packed Sums of Absolute Difference
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0100 0010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0100 0010: mod xmmreg r/m:
imm8
PACKUSDW — Pack with Unsigned Saturation
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1011: mod xmmreg r/m
PBLENDVB — Variable Blend Packed Bytes
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 0000: mod xmmreg r/m
Vol. 2D B-67
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
PBLENDW — Blend Packed Words
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0001 1110:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1110: mod xmmreg r/m:
imm8
PCMPEQQ — Compare Packed Qword Data of Equal
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 1001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1001: mod xmmreg r/m
PEXTRB — Extract Byte
reg from xmmreg , imm8
0110 0110:0000 1111:0011 1010: 0001 0100:11 xmmreg reg:
imm8
xmmreg to mem, imm8
0110 0110:0000 1111:0011 1010: 0001 0100: mod xmmreg r/m:
imm8
PEXTRD — Extract DWord
reg from xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0001 0110:11 xmmreg reg:
imm8
xmmreg to mem, imm8
0110 0110:0000 1111:0011 1010: 0001 0110: mod
xmmreg r/m: imm8
PEXTRQ — Extract QWord
r64 from xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0001 0110:11 xmmreg
reg: imm8
m64 from xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0001 0110: mod
xmmreg r/m: imm8
PEXTRW — Extract Word
reg from xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0001 0101:11 reg xmmreg:
imm8
mem from xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0001 0101: mod xmmreg r/m:
imm8
PHMINPOSUW — Packed Horizontal Word Minimum
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0100 0001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0100 0001: mod xmmreg r/m
PINSRB — Extract Byte
reg to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0000:11 xmmreg reg:
imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0000: mod xmmreg r/m:
imm8
PINSRD — Extract DWord
reg to xmmreg, imm8
B-68 Vol. 2D
0110 0110:0000 1111:0011 1010: 0010 0010:11 xmmreg reg:
imm8
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
mem to xmmreg, imm8
Encoding
0110 0110:0000 1111:0011 1010: 0010 0010: mod xmmreg r/m:
imm8
PINSRQ — Extract QWord
r64 to xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0010 0010:11 xmmreg
reg: imm8
m64 to xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0010 0010: mod
xmmreg r/m: imm8
PMAXSB — Maximum of Packed Signed Byte Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1100: mod xmmreg r/m
PMAXSD — Maximum of Packed Signed Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1101: mod xmmreg r/m
PMAXUD — Maximum of Packed Unsigned Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1111: mod xmmreg r/m
PMAXUW — Maximum of Packed Unsigned Word Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1110: mod xmmreg r/m
PMINSB — Minimum of Packed Signed Byte Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1000: mod xmmreg r/m
PMINSD — Minimum of Packed Signed Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1001: mod xmmreg r/m
PMINUD — Minimum of Packed Unsigned Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1011: mod xmmreg r/m
PMINUW — Minimum of Packed Unsigned Word Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1010: mod xmmreg r/m
PMOVSXBD — Packed Move Sign Extend - Byte to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0001:11 xmmreg1
xmmreg2
Vol. 2D B-69
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
mem to xmmreg
Encoding
0110 0110:0000 1111:0011 1000: 0010 0001: mod xmmreg r/m
PMOVSXBQ — Packed Move Sign Extend - Byte to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0010: mod xmmreg r/m
PMOVSXBW — Packed Move Sign Extend - Byte to Word
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0000: mod xmmreg r/m
PMOVSXWD — Packed Move Sign Extend - Word to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0011: mod xmmreg r/m
PMOVSXWQ — Packed Move Sign Extend - Word to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0100: mod xmmreg r/m
PMOVSXDQ — Packed Move Sign Extend - Dword to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0101: mod xmmreg r/m
PMOVZXBD — Packed Move Zero Extend - Byte to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0001: mod xmmreg r/m
PMOVZXBQ — Packed Move Zero Extend - Byte to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0010: mod xmmreg r/m
PMOVZXBW — Packed Move Zero Extend - Byte to Word
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0000: mod xmmreg r/m
PMOVZXWD — Packed Move Zero Extend - Word to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0011: mod xmmreg r/m
PMOVZXWQ — Packed Move Zero Extend - Word to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0100: mod xmmreg r/m
PMOVZXDQ — Packed Move Zero Extend - Dword to Qword
B-70 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0101: mod xmmreg r/m
PMULDQ — Multiply Packed Signed Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 1000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1000: mod xmmreg r/m
PMULLD — Multiply Packed Signed Dword Integers, Store
low Result
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0100 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0100 0000: mod xmmreg r/m
PTEST — Logical Compare
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 0111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 0111: mod xmmreg r/m
ROUNDPD — Round Packed Double-Precision Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1001: mod xmmreg r/m:
imm8
ROUNDPS — Round Packed Single-Precision Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1000: mod xmmreg r/m:
imm8
ROUNDSD — Round Scalar Double-Precision Value
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1011:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1011: mod xmmreg r/m:
imm8
ROUNDSS — Round Scalar Single-Precision Value
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1010: mod xmmreg r/m:
imm8
B.15
SSE4.2 FORMATS AND ENCODING TABLE
The tables in this section provide SSE4.2 formats and encodings. Some SSE4.2 instructions require a mandatory
prefix (66H, F2H, F3H) as part of the three-byte opcode. These prefixes are included in the tables. In 64-bit mode,
some instructions requires REX.W, the byte sequence of REX.W prefix in the opcode sequence is shown.
Vol. 2D B-71
INSTRUCTION FORMATS AND ENCODINGS
Table B-36. Encodings of SSE4.2 instructions
Instruction and Format
Encoding
CRC32 — Accumulate CRC32
reg2 to reg1
1111 0010:0000 1111:0011 1000: 1111 000w :11 reg1 reg2
mem to reg
1111 0010:0000 1111:0011 1000: 1111 000w : mod reg r/m
bytereg2 to reg1
1111 0010:0100 WR0B:0000 1111:0011 1000: 1111 0000 :11
reg1 bytereg2
m8 to reg
1111 0010:0100 WR0B:0000 1111:0011 1000: 1111 0000 : mod
reg r/m
qwreg2 to qwreg1
1111 0010:0100 1R0B:0000 1111:0011 1000: 1111 0001 :11
qwreg1 qwreg2
mem64 to qwreg
1111 0010:0100 1R0B:0000 1111:0011 1000: 1111 0001 : mod
qwreg r/m
PCMPESTRI— Packed Compare Explicit-Length Strings To
Index
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0001: mod xmmreg r/m
PCMPESTRM— Packed Compare Explicit-Length Strings To
Mask
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0000: mod xmmreg r/m
PCMPISTRI— Packed Compare Implicit-Length String To
Index
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0011:11 xmmreg1
xmmreg2: imm8
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0011: mod xmmreg r/m
PCMPISTRM— Packed Compare Implicit-Length Strings To
Mask
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0010: mod xmmreg r/m
PCMPGTQ— Packed Compare Greater Than
xmmreg to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0111: mod xmmreg r/m
POPCNT— Return Number of Bits Set to 1
reg2 to reg1
1111 0011:0000 1111:1011 1000:11 reg1 reg2
mem to reg1
1111 0011:0000 1111:1011 1000:mod reg1 r/m
qwreg2 to qwreg1
1111 0011:0100 1R0B:0000 1111:1011 1000:11 reg1 reg2
mem64 to qwreg1
1111 0011:0100 1R0B:0000 1111:1011 1000:mod reg1 r/m
B-72 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
B.16
AVX FORMATS AND ENCODING TABLE
The tables in this section provide AVX formats and encodings. A mixed form of bit/hex/symbolic forms are used to
express the various bytes:
The C4/C5 and opcode bytes are expressed in hex notation; the first and second payload byte of VEX, the modR/M
byte is expressed in combination of bit/symbolic form. The first payload byte of C4 is expressed as combination of
bits and hex form, with the hex value preceded by an underscore. The VEX bit field to encode upper register 8-15
uses 1’s complement form, each of those bit field is expressed as lower case notation rxb, instead of RXB.
The hybrid bit-nibble-byte form is depicted below:
hex notation
C5
7 6 ----3 2 1 0
hex notation
7-6
R srcreg Lp p
Opcode byte
Mod Reg* R/M
5-3
2-0
Two-Byte VEX
C4
7 6 5 4 ----- 0
7 6 ----3 2 1 0
hex notation
7-6
R X B 0_hex
W srcreg L pp
Opcode byte
Mod Reg R/M
5-3
2-0
mmmmm
Three-Byte VEX
Figure B-2. Hybrid Notation of VEX-Encoded Key Instruction Bytes
Table B-37. Encodings of AVX instructions
Instruction and Format
Encoding
VBLENDPD — Blend Packed Double-Precision Floats
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:0D:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:0D:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 into ymmreg1
C4: rxb0_3: w ymmreg2 101:0D:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: w ymmreg2 101:0D:mod ymmreg1 r/m: imm
VBLENDPS — Blend Packed Single-Precision Floats
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:0C:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:0C:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 into ymmreg1
C4: rxb0_3: w ymmreg2 101:0C:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: w ymmreg2 101:0C:mod ymmreg1 r/m: imm
VBLENDVPD — Variable Blend Packed Double-Precision
Floats
xmmreg2 with xmmreg3 into xmmreg1 using xmmreg4 as
mask
xmmreg2 with mem to xmmreg1 using xmmreg4 as mask
ymmreg2 with ymmreg3 into ymmreg1 using ymmreg4 as
mask
ymmreg2 with mem to ymmreg1 using ymmreg4 as mask
C4: rxb0_3: 0 xmmreg2 001:4B:11 xmmreg1 xmmreg3: xmmreg4
C4: rxb0_3: 0 xmmreg2 001:4B:mod xmmreg1 r/m: xmmreg4
C4: rxb0_3: 0 ymmreg2 101:4B:11 ymmreg1 ymmreg3: ymmreg4
C4: rxb0_3: 0 ymmreg2 101:4B:mod ymmreg1 r/m: ymmreg4
VBLENDVPS — Variable Blend Packed Single-Precision
Floats
Vol. 2D B-73
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with xmmreg3 into xmmreg1 using xmmreg4 as
mask
C4: rxb0_3: 0 xmmreg2 001:4A:11 xmmreg1 xmmreg3: xmmreg4
xmmreg2 with mem to xmmreg1 using xmmreg4 as mask
ymmreg2 with ymmreg3 into ymmreg1 using ymmreg4 as
mask
ymmreg2 with mem to ymmreg1 using ymmreg4 as mask
C4: rxb0_3: 0 xmmreg2 001:4A:mod xmmreg1 r/m: xmmreg4
C4: rxb0_3: 0 ymmreg2 101:4A:11 ymmreg1 ymmreg3: ymmreg4
C4: rxb0_3: 0 ymmreg2 101:4A:mod ymmreg1 r/m: ymmreg4
VDPPD — Packed Double-Precision Dot Products
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:41:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:41:mod xmmreg1 r/m: imm
VDPPS — Packed Single-Precision Dot Products
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:40:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:40:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 into ymmreg1
C4: rxb0_3: w ymmreg2 101:40:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: w ymmreg2 101:40:mod ymmreg1 r/m: imm
VEXTRACTPS — Extract From Packed Single-Precision
Floats
reg from xmmreg1 using imm
C4: rxb0_3: w_F 001:17:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: w_F 001:17:mod xmmreg1 r/m: imm
VINSERTPS — Insert Into Packed Single-Precision Floats
use imm to merge xmmreg3 with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:21:11 xmmreg1 xmmreg3: imm
use imm to merge mem with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:21:mod xmmreg1 r/m: imm
VMOVNTDQA — Load Double Quadword Non-temporal
Aligned
m128 to xmmreg1
C4: rxb0_2: w_F 001:2A:11 xmmreg1 r/m
VMPSADBW — Multiple Packed Sums of Absolute
Difference
xmmreg3 with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:42:11 xmmreg1 xmmreg3: imm
m128 with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:42:mod xmmreg1 r/m: imm
VPACKUSDW — Pack with Unsigned Saturation
xmmreg3 and xmmreg2 to xmmreg1
C4: rxb0_2: w xmmreg2 001:2B:11 xmmreg1 xmmreg3: imm
m128 and xmmreg2 to xmmreg1
C4: rxb0_2: w xmmreg2 001:2B:mod xmmreg1 r/m: imm
VPBLENDVB — Variable Blend Packed Bytes
xmmreg2 with xmmreg3 into xmmreg1 using xmmreg4 as
mask
xmmreg2 with mem to xmmreg1 using xmmreg4 as mask
C4: rxb0_3: w xmmreg2 001:4C:11 xmmreg1 xmmreg3: xmmreg4
C4: rxb0_3: w xmmreg2 001:4C:mod xmmreg1 r/m: xmmreg4
VPBLENDW — Blend Packed Words
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:0E:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:0E:mod xmmreg1 r/m: imm
VPCMPEQQ — Compare Packed Qword Data of Equal
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:29:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:29:mod xmmreg1 r/m:
B-74 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VPEXTRB — Extract Byte
reg from xmmreg1 using imm
C4: rxb0_3: 0_F 001:14:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 0_F 001:14:mod xmmreg1 r/m: imm
VPEXTRD — Extract DWord
reg from xmmreg1 using imm
C4: rxb0_3: 0_F 001:16:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 0_F 001:16:mod xmmreg1 r/m: imm
VPEXTRQ — Extract QWord
reg from xmmreg1 using imm
C4: rxb0_3: 1_F 001:16:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 1_F 001:16:mod xmmreg1 r/m: imm
VPEXTRW — Extract Word
reg from xmmreg1 using imm
C4: rxb0_3: 0_F 001:15:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 0_F 001:15:mod xmmreg1 r/m: imm
VPHMINPOSUW — Packed Horizontal Word Minimum
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:41:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:41:mod xmmreg1 r/m
VPINSRB — Insert Byte
reg with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:20:11 xmmreg1 reg: imm
mem with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:20:mod xmmreg1 r/m: imm
VPINSRD — Insert DWord
reg with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:22:11 xmmreg1 reg: imm
mem with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:22:mod xmmreg1 r/m: imm
VPINSRQ — Insert QWord
r64 with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 1 xmmreg2 001:22:11 xmmreg1 reg: imm
m64 with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 1 xmmreg2 001:22:mod xmmreg1 r/m: imm
VPMAXSB — Maximum of Packed Signed Byte Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3C:mod xmmreg1 r/m
VPMAXSD — Maximum of Packed Signed Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3D:mod xmmreg1 r/m
VPMAXUD — Maximum of Packed Unsigned Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3F:mod xmmreg1 r/m
VPMAXUW — Maximum of Packed Unsigned Word Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3E:mod xmmreg1 r/m
VPMINSB — Minimum of Packed Signed Byte Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:38:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:38:mod xmmreg1 r/m
Vol. 2D B-75
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VPMINSD — Minimum of Packed Signed Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:39:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:39:mod xmmreg1 r/m
VPMINUD — Minimum of Packed Unsigned Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3B:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3B:mod xmmreg1 r/m
VPMINUW — Minimum of Packed Unsigned Word Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3A:mod xmmreg1 r/m
VPMOVSXBD — Packed Move Sign Extend - Byte to Dword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:21:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:21:mod xmmreg1 r/m
VPMOVSXBQ — Packed Move Sign Extend - Byte to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:22:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:22:mod xmmreg1 r/m
VPMOVSXBW — Packed Move Sign Extend - Byte to Word
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:20:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:20:mod xmmreg1 r/m
VPMOVSXWD — Packed Move Sign Extend - Word to Dword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:23:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:23:mod xmmreg1 r/m
VPMOVSXWQ — Packed Move Sign Extend - Word to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:24:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:24:mod xmmreg1 r/m
VPMOVSXDQ — Packed Move Sign Extend - Dword to
Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:25:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:25:mod xmmreg1 r/m
VPMOVZXBD — Packed Move Zero Extend - Byte to Dword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:31:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:31:mod xmmreg1 r/m
VPMOVZXBQ — Packed Move Zero
Extend - Byte to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:32:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:32:mod xmmreg1 r/m
VPMOVZXBW — Packed Move Zero
Extend - Byte to Word
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:30:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:30:mod xmmreg1 r/m
VPMOVZXWD — Packed Move Zero
Extend - Word to Dword
B-76 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:33:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:33:mod xmmreg1 r/m
VPMOVZXWQ — Packed Move Zero
Extend - Word to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:34:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:34:mod xmmreg1 r/m
VPMOVZXDQ — Packed Move Zero
Extend - Dword to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:35:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:35:mod xmmreg1 r/m
VPMULDQ — Multiply Packed Signed
Dword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:mod xmmreg1 r/m
VPMULLD — Multiply Packed Signed
Dword Integers, Store low Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:40:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:40:mod xmmreg1 r/m
VPTEST — Logical Compare
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:17:11 xmmreg1 xmmreg2
mem to xmmreg
C4: rxb0_2: w_F 001:17:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_2: w_F 101:17:11 ymmreg1 ymmreg2
mem to ymmreg
C4: rxb0_2: w_F 101:17:mod ymmreg1 r/m
VROUNDPD — Round Packed DoublePrecision Values
xmmreg2 to xmmreg1, imm8
C4: rxb0_3: w_F 001:09:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm8
C4: rxb0_3: w_F 001:09:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1, imm8
C4: rxb0_3: w_F 101:09:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm8
C4: rxb0_3: w_F 101:09:mod ymmreg1 r/m: imm
VROUNDPS — Round Packed Single-Precision Values
xmmreg2 to xmmreg1, imm8
C4: rxb0_3: w_F 001:08:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm8
C4: rxb0_3: w_F 001:08:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1, imm8
C4: rxb0_3: w_F 101:08:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm8
C4: rxb0_3: w_F 101:08:mod ymmreg1 r/m: imm
VROUNDSD — Round Scalar DoublePrecision Value
xmmreg2 and xmmreg3 to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0B:11 xmmreg1 xmmreg3: imm
xmmreg2 and mem to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0B:mod xmmreg1 r/m: imm
VROUNDSS — Round Scalar SinglePrecision Value
xmmreg2 and xmmreg3 to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0A:11 xmmreg1 xmmreg3: imm
xmmreg2 and mem to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0A:mod xmmreg1 r/m: imm
Vol. 2D B-77
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VPCMPESTRI — Packed Compare Explicit Length Strings,
Return Index
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:61:11 xmmreg1 xmmreg2: imm
mem with xmmreg1, imm8
C4: rxb0_3: w_F 001:61:mod xmmreg1 r/m: imm
VPCMPESTRM — Packed Compare Explicit Length Strings,
Return Mask
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:60:11 xmmreg1 xmmreg2: imm
mem with xmmreg1, imm8
C4: rxb0_3: w_F 001:60:mod xmmreg1 r/m: imm
VPCMPGTQ — Compare Packed Data for Greater Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:mod xmmreg1 r/m
VPCMPISTRI — Packed Compare Implicit Length Strings,
Return Index
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:63:11 xmmreg1 xmmreg2: imm
mem with xmmreg1, imm8
C4: rxb0_3: w_F 001:63:mod xmmreg1 r/m: imm
VPCMPISTRM — Packed Compare Implicit Length Strings,
Return Mask
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:62:11 xmmreg1 xmmreg2: imm
mem with xmmreg, imm8
C4: rxb0_3: w_F 001:62:mod xmmreg1 r/m: imm
VAESDEC — Perform One Round of an AES Decryption Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DE:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DE:mod xmmreg1 r/m
VAESDECLAST — Perform Last Round of an AES Decryption
Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DF:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DF:mod xmmreg1 r/m
VAESENC — Perform One Round of an AES Encryption Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DC:mod xmmreg1 r/m
VAESENCLAST — Perform Last Round of an AES Encryption
Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DD:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DD:mod xmmreg1 r/m
VAESIMC — Perform the AES InvMixColumn Transformation
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:DB:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:DB:mod xmmreg1 r/m
VAESKEYGENASSIST — AES Round Key Generation Assist
xmmreg2 to xmmreg1, imm8
C4: rxb0_3: w_F 001:DF:11 xmmreg1 xmmreg2: imm
mem to xmmreg, imm8
C4: rxb0_3: w_F 001:DF:mod xmmreg1 r/m: imm
VPABSB — Packed Absolute Value
xmmreg2 to xmmreg1
B-78 Vol. 2D
C4: rxb0_2: w_F 001:1C:11 xmmreg1 xmmreg2
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
mem to xmmreg1
Encoding
C4: rxb0_2: w_F 001:1C:mod xmmreg1 r/m
VPABSD — Packed Absolute Value
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:1E:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:1E:mod xmmreg1 r/m
VPABSW — Packed Absolute Value
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:1D:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:1D:mod xmmreg1 r/m
VPALIGNR — Packed Align Right
xmmreg2 with xmmreg3 to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:DD:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:DD:mod xmmreg1 r/m: imm
VPHADDD — Packed Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:02:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:02:mod xmmreg1 r/m
VPHADDW — Packed Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:01:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:01:mod xmmreg1 r/m
VPHADDSW — Packed Horizontal Add and Saturate
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:03:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:03:mod xmmreg1 r/m
VPHSUBD — Packed Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:06:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:06:mod xmmreg1 r/m
VPHSUBW — Packed Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:05:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:05:mod xmmreg1 r/m
VPHSUBSW — Packed Horizontal Subtract and Saturate
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:07:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:07:mod xmmreg1 r/m
VPMADDUBSW — Multiply and Add Packed Signed and
Unsigned Bytes
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:04:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:04:mod xmmreg1 r/m
VPMULHRSW — Packed Multiply High with Round and Scale
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:0B:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:0B:mod xmmreg1 r/m
VPSHUFB — Packed Shuffle Bytes
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:00:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:00:mod xmmreg1 r/m
VPSIGNB — Packed SIGN
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:08:11 xmmreg1 xmmreg3
Vol. 2D B-79
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
xmmreg2 with mem to xmmreg1
Encoding
C4: rxb0_2: w xmmreg2 001:08:mod xmmreg1 r/m
VPSIGND — Packed SIGN
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:0A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:0A:mod xmmreg1 r/m
VPSIGNW — Packed SIGN
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:09:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:09:mod xmmreg1 r/m
VADDSUBPD — Packed Double-FP Add/Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D0:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D0:mod xmmreg1 r/m
xmmreglo21
C5: r_xmmreglo2 001:D0:11 xmmreg1 xmmreglo3
with xmmreglo3 to xmmreg1
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D0:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:D0:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:D0:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:D0:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:D0:mod ymmreg1 r/m
VADDSUBPS — Packed Single-FP Add/Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:D0:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:D0:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:D0:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:D0:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 111:D0:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 111:D0:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 111:D0:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 111:D0:mod ymmreg1 r/m
VHADDPD — Packed Double-FP Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:7C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:7C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:7C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:7C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:7C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:7C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:7C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:7C:mod ymmreg1 r/m
VHADDPS — Packed Single-FP Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:7C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:7C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:7C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:7C:mod xmmreg1 r/m
B-80 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 111:7C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 111:7C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 111:7C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 111:7C:mod ymmreg1 r/m
VHSUBPD — Packed Double-FP Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:7D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:7D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:7D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:7D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:7D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:7D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:7D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:7D:mod ymmreg1 r/m
VHSUBPS — Packed Single-FP Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:7D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:7D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:7D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:7D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 111:7D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 111:7D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 111:7D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 111:7D:mod ymmreg1 r/m
VLDDQU — Load Unaligned Integer 128 Bits
mem to xmmreg1
C4: rxb0_1: w_F 011:F0:mod xmmreg1 r/m
mem to xmmreg1
C5: r_F 011:F0:mod xmmreg1 r/m
mem to ymmreg1
C4: rxb0_1: w_F 111:F0:mod ymmreg1 r/m
mem to ymmreg1
C5: r_F 111:F0:mod ymmreg1 r/m
VMOVDDUP — Move One Double-FP and Duplicate
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 011:12:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 011:12:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 011:12:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 011:12:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 111:12:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 111:12:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_ F 111:12:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 111:12:mod ymmreg1 r/m
VMOVHLPS — Move Packed Single-Precision Floating-Point
Values High to Low
xmmreg2 and xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:12:11 xmmreg1 xmmreg3
Vol. 2D B-81
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
xmmreglo2 and xmmreglo3 to xmmreg1
Encoding
C5: r_xmmreglo2 000:12:11 xmmreg1 xmmreglo3
VMOVSHDUP — Move Packed Single-FP High and Duplicate
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:16:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:16:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:16:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:16:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:16:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:16:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:16:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:16:mod ymmreg1 r/m
VMOVSLDUP — Move Packed Single-FP Low and Duplicate
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:12:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:12:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:12:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:12:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:12:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:12:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:12:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:12:mod ymmreg1 r/m
VADDPD — Add Packed Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:58:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:58:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:58:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:58:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:58:mod ymmreg1 r/m
VADDSD — Add Scalar Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5 r_xmmreglo2 011:58:mod xmmreg1 r/m
VANDPD — Bitwise Logical AND of Packed Double-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:54:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:54:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:54:11 xmmreg1 xmmreglo3
B-82 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:54:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:54:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:54:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:54:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:54:mod ymmreg1 r/m
VANDNPD — Bitwise Logical AND NOT of Packed DoublePrecision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:55:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:55:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:55:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:55:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:55:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:55:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:55:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:55:mod ymmreg1 r/m
VCMPPD — Compare Packed Double-Precision FloatingPoint Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:C2:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:C2:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:C2:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:C2:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:C2:mod ymmreg1 r/m: imm
VCMPSD — Compare Scalar Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:C2:mod xmmreg1 r/m: imm
VCOMISD — Compare Scalar Ordered Double-Precision
Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:2F:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:2F:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:2F:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:2F:mod xmmreg1 r/m
VCVTDQ2PD— Convert Packed Dword Integers to Packed
Double-Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:E6:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:E6:mod xmmreg1 r/m
Vol. 2D B-83
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1
C5: r_F 010:E6:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:E6:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:E6:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:E6:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:E6:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:E6:mod ymmreg1 r/m
VCVTDQ2PS— Convert Packed Dword Integers to Packed
Single-Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:5B:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:5B:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:5B:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:5B:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:5B:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:5B:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:5B:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:5B:mod ymmreg1 r/m
VCVTPD2DQ— Convert Packed Double-Precision FP Values
to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 011:E6:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 011:E6:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 011:E6:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 011:E6:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 111:E6:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 111:E6:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 111:E6:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 111:E6:mod ymmreg1 r/m
VCVTPD2PS— Convert Packed Double-Precision FP Values
to Packed Single-Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:5A:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:5A:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:5A:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:5A:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:5A:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:5A:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:5A:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:5A:mod ymmreg1 r/m
VCVTPS2DQ— Convert Packed Single-Precision FP Values
to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:5B:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:5B:mod xmmreg1 r/m
B-84 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1
C5: r_F 001:5B:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:5B:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:5B:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:5B:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:5B:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:5B:mod ymmreg1 r/m
VCVTPS2PD— Convert Packed Single-Precision FP Values
to Packed Double-Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:5A:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:5A:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:5A:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:5A:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:5A:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:5A:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:5A:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:5A:mod ymmreg1 r/m
VCVTSD2SI— Convert Scalar Double-Precision FP Value to
Integer
xmmreg1 to reg32
C4: rxb0_1: 0_F 011:2D:11 reg xmmreg1
mem to reg32
C4: rxb0_1: 0_F 011:2D:mod reg r/m
xmmreglo to reg32
C5: r_F 011:2D:11 reg xmmreglo
mem to reg32
C5: r_F 011:2D:mod reg r/m
ymmreg1 to reg64
C4: rxb0_1: 1_F 111:2D:11 reg ymmreg1
mem to reg64
C4: rxb0_1: 1_F 111:2D:mod reg r/m
VCVTSD2SS — Convert Scalar Double-Precision FP Value to
Scalar Single-Precision FP Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5A:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5A:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5A:mod xmmreg1 r/m
VCVTSI2SD— Convert Dword Integer to Scalar DoublePrecision FP Value
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 0 xmmreg2 011:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 0 xmmreg2 011:2A:mod xmmreg1 r/m
xmmreglo2 with reglo to xmmreg1
C5: r_xmmreglo2 011:2A:11 xmmreg1 reglo
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:2A:mod xmmreg1 r/m
ymmreg2 with reg to ymmreg1
C4: rxb0_1: 1 ymmreg2 111:2A:11 ymmreg1 reg
ymmreg2 with mem to ymmreg1
C4: rxb0_1: 1 ymmreg2 111:2A:mod ymmreg1 r/m
VCVTSS2SD — Convert Scalar Single-Precision FP Value to
Scalar Double-Precision FP Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5A:11 xmmreg1 xmmreg3
Vol. 2D B-85
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5A:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5A:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5A:mod xmmreg1 r/m
VCVTTPD2DQ— Convert with Truncation Packed DoublePrecision FP Values to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:E6:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:E6:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:E6:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:E6:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:E6:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:E6:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:E6:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:E6:mod ymmreg1 r/m
VCVTTPS2DQ— Convert with Truncation Packed SinglePrecision FP Values to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:5B:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:5B:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:5B:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:5B:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:5B:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:5B:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:5B:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:5B:mod ymmreg1 r/m
VCVTTSD2SI— Convert with Truncation Scalar DoublePrecision FP Value to Signed Integer
xmmreg1 to reg32
C4: rxb0_1: 0_F 011:2C:11 reg xmmreg1
mem to reg32
C4: rxb0_1: 0_F 011:2C:mod reg r/m
xmmreglo to reg32
C5: r_F 011:2C:11 reg xmmreglo
mem to reg32
C5: r_F 011:2C:mod reg r/m
xmmreg1 to reg64
C4: rxb0_1: 1_F 011:2C:11 reg xmmreg1
mem to reg64
C4: rxb0_1: 1_F 011:2C:mod reg r/m
VDIVPD — Divide Packed Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5E:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5E:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5E:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5E:11 ymmreg1 ymmreglo3
B-86 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
ymmreglo2 with mem to ymmreg1
Encoding
C5: r_ymmreglo2 101:5E:mod ymmreg1 r/m
VDIVSD — Divide Scalar Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5E:mod xmmreg1 r/m
VMASKMOVDQU— Store Selected Bytes of Double
Quadword
xmmreg1 to mem; xmmreg2 as mask
C4: rxb0_1: w_F 001:F7:11 r/m xmmreg1: xmmreg2
xmmreg1 to mem; xmmreg2 as mask
C5: r_F 001:F7:11 r/m xmmreg1: xmmreg2
VMAXPD — Return Maximum Packed Double-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5F:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5F:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5F:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5F:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5F:mod ymmreg1 r/m
VMAXSD — Return Maximum Scalar Double-Precision
Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5F:mod xmmreg1 r/m
VMINPD — Return Minimum Packed Double-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5D:mod ymmreg1 r/m
VMINSD — Return Minimum Scalar Double-Precision
Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5D:mod xmmreg1 r/m
Vol. 2D B-87
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5D:mod xmmreg1 r/m
VMOVAPD — Move Aligned Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:28:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:28:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:28:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:28:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 001:29:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 001:29:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 001:29:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 001:29:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:28:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:28:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:28:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:28:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 101:29:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 101:29:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 101:29:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 101:29:mod r/m ymmreg1
VMOVD — Move Doubleword
reg32 to xmmreg1
C4: rxb0_1: 0_F 001:6E:11 xmmreg1 reg32
mem32 to xmmreg1
C4: rxb0_1: 0_F 001:6E:mod xmmreg1 r/m
reg32 to xmmreg1
C5: r_F 001:6E:11 xmmreg1 reg32
mem32 to xmmreg1
C5: r_F 001:6E:mod xmmreg1 r/m
xmmreg1 to reg32
C4: rxb0_1: 0_F 001:7E:11 reg32 xmmreg1
xmmreg1 to mem32
C4: rxb0_1: 0_F 001:7E:mod mem32 xmmreg1
xmmreglo to reg32
C5: r_F 001:7E:11 reg32 xmmreglo
xmmreglo to mem32
C5: r_F 001:7E:mod mem32 xmmreglo
VMOVQ — Move Quadword
reg64 to xmmreg1
C4: rxb0_1: 1_F 001:6E:11 xmmreg1 reg64
mem64 to xmmreg1
C4: rxb0_1: 1_F 001:6E:mod xmmreg1 r/m
xmmreg1 to reg64
C4: rxb0_1: 1_F 001:7E:11 reg64 xmmreg1
xmmreg1 to mem64
C4: rxb0_1: 1_F 001:7E:mod r/m xmmreg1
VMOVDQA — Move Aligned Double Quadword
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:6F:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:6F:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:6F:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:6F:mod xmmreg1 r/m
B-88 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 001:7F:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 001:7F:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 001:7F:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 001:7F:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:6F:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:6F:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:6F:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:6F:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 101:7F:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 101:7F:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 101:7F:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 101:7F:mod r/m ymmreg1
VMOVDQU — Move Unaligned Double Quadword
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:6F:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:6F:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:6F:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:6F:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 010:7F:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 010:7F:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 010:7F:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 010:7F:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:6F:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:6F:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:6F:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:6F:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 110:7F:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 110:7F:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 110:7F:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 110:7F:mod r/m ymmreg1
VMOVHPD — Move High Packed Double-Precision FloatingPoint Value
xmmreg1 and mem to xmmreg2
C4: rxb0_1: w xmmreg1 001:16:11 xmmreg2 r/m
xmmreg1 and mem to xmmreglo2
C5: r_xmmreg1 001:16:11 xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 001:17:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 001:17:mod r/m xmmreglo
VMOVLPD — Move Low Packed Double-Precision FloatingPoint Value
xmmreg1 and mem to xmmreg2
C4: rxb0_1: w xmmreg1 001:12:11 xmmreg2 r/m
xmmreg1 and mem to xmmreglo2
C5: r_xmmreg1 001:12:11 xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 001:13:mod r/m xmmreg1
Vol. 2D B-89
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
xmmreglo to mem
Encoding
C5: r_F 001:13:mod r/m xmmreglo
VMOVMSKPD — Extract Packed Double-Precision FloatingPoint Sign Mask
xmmreg2 to reg
C4: rxb0_1: w_F 001:50:11 reg xmmreg1
xmmreglo to reg
C5: r_F 001:50:11 reg xmmreglo
ymmreg2 to reg
C4: rxb0_1: w_F 101:50:11 reg ymmreg1
ymmreglo to reg
C5: r_F 101:50:11 reg ymmreglo
VMOVNTDQ — Store Double Quadword Using Non-Temporal
Hint
xmmreg1 to mem
C4: rxb0_1: w_F 001:E7:11 r/m xmmreg1
xmmreglo to mem
C5: r_F 001:E7:11 r/m xmmreglo
ymmreg1 to mem
C4: rxb0_1: w_F 101:E7:11 r/m ymmreg1
ymmreglo to mem
C5: r_F 101:E7:11 r/m ymmreglo
VMOVNTPD — Store Packed Double-Precision FloatingPoint Values Using Non-Temporal Hint
xmmreg1 to mem
C4: rxb0_1: w_F 001:2B:11 r/m xmmreg1
xmmreglo to mem
C5: r_F 001:2B:11 r/m xmmreglo
ymmreg1 to mem
C4: rxb0_1: w_F 101:2B:11r/m ymmreg1
ymmreglo to mem
C5: r_F 101:2B:11r/m ymmreglo
VMOVSD — Move Scalar Double-Precision Floating-Point
Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C4: rxb0_1: w_F 011:10:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:10:11 xmmreg1 xmmreglo3
mem to xmmreg1
C5: r_F 011:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:11:11 xmmreg1 xmmreg3
xmmreg1 to mem
C4: rxb0_1: w_F 011:11:mod r/m xmmreg1
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:11:11 xmmreg1 xmmreglo3
xmmreglo to mem
C5: r_F 011:11:mod r/m xmmreglo
VMOVUPD — Move Unaligned Packed Double-Precision
Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:10:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:10:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:10:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:10:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:10:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:10:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:10:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:10:mod ymmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 001:11:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 001:11:mod r/m xmmreg1
B-90 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg1 to xmmreglo
C5: r_F 001:11:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 001:11:mod r/m xmmreg1
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 101:11:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 101:11:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 101:11:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 101:11:mod r/m ymmreg1
VMULPD — Multiply Packed Double-Precision FloatingPoint Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:59:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:59:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:59:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:59:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:59:mod ymmreg1 r/m
VMULSD — Multiply Scalar Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:59:mod xmmreg1 r/m
VORPD — Bitwise Logical OR of Double-Precision FloatingPoint Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:56:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:56:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:56:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:56:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:56:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:56:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:56:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:56:mod ymmreg1 r/m
VPACKSSWB— Pack with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:63:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:63:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:63:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:63:mod xmmreg1 r/m
VPACKSSDW— Pack with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6B:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6B:mod xmmreg1 r/m
Vol. 2D B-91
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6B:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6B:mod xmmreg1 r/m
VPACKUSWB— Pack with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:67:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:67:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:67:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:67:mod xmmreg1 r/m
VPADDB — Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FC:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FC:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FC:mod xmmreg1 r/m
VPADDW — Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FD:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FD:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FD:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FD:mod xmmreg1 r/m
VPADDD — Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FE:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FE:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FE:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FE:mod xmmreg1 r/m
VPADDQ — Add Packed Quadword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D4:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D4:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D4:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D4:mod xmmreg1 r/m
VPADDSB — Add Packed Signed Integers with Signed
Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EC:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EC:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EC:mod xmmreg1 r/m
VPADDSW — Add Packed Signed Integers with Signed
Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:ED:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:ED:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:ED:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:ED:mod xmmreg1 r/m
B-92 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VPADDUSB — Add Packed Unsigned Integers with
Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DC:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DC:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DC:mod xmmreg1 r/m
VPADDUSW — Add Packed Unsigned Integers with
Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DD:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DD:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DD:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DD:mod xmmreg1 r/m
VPAND — Logical AND
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DB:mod xmmreg1 r/m
VPANDN — Logical AND NOT
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DF:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DF:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DF:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DF:mod xmmreg1 r/m
VPAVGB — Average Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E0:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E0:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E0:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E0:mod xmmreg1 r/m
VPAVGW — Average Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E3:mod xmmreg1 r/m
VPCMPEQB — Compare Packed Data for Equal
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:74:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:74:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:74:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:74:mod xmmreg1 r/m
VPCMPEQW — Compare Packed Data for Equal
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:75:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:75:mod xmmreg1 r/m
Vol. 2D B-93
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:75:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:75:mod xmmreg1 r/m
VPCMPEQD — Compare Packed Data for Equal
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:76:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:76:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:76:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:76:mod xmmreg1 r/m
VPCMPGTB — Compare Packed Signed Integers for Greater
Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:64:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:64:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:64:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:64:mod xmmreg1 r/m
VPCMPGTW — Compare Packed Signed Integers for Greater
Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:65:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:65:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:65:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:65:mod xmmreg1 r/m
VPCMPGTD — Compare Packed Signed Integers for Greater
Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:66:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:66:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:66:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:66:mod xmmreg1 r/m
VPEXTRW — Extract Word
xmmreg1 to reg using imm
C4: rxb0_1: 0_F 001:C5:11 reg xmmreg1: imm
xmmreg1 to reg using imm
C5: r_F 001:C5:11 reg xmmreg1: imm
VPINSRW — Insert Word
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 0 xmmreg2 001:C4:11 xmmreg1 reg: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 0 xmmreg2 001:C4:mod xmmreg1 r/m: imm
xmmreglo2 with reglo to xmmreg1
C5: r_xmmreglo2 001:C4:11 xmmreg1 reglo: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:C4:mod xmmreg1 r/m: imm
VPMADDWD — Multiply and Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F5:mod xmmreg1 r/m
VPMAXSW — Maximum of Packed Signed Word Integers
xmmreg2 with xmmreg3 to xmmreg1
B-94 Vol. 2D
C4: rxb0_1: w xmmreg2 001:EE:11 xmmreg1 xmmreg3
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EE:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EE:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EE:mod xmmreg1 r/m
VPMAXUB — Maximum of Packed Unsigned Byte Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DE:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DE:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DE:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DE:mod xmmreg1 r/m
VPMINSW — Minimum of Packed Signed Word Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EA:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EA:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EA:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EA:mod xmmreg1 r/m
VPMINUB — Minimum of Packed Unsigned Byte Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DA:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DA:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DA:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DA:mod xmmreg1 r/m
VPMOVMSKB — Move Byte Mask
xmmreg1 to reg
C4: rxb0_1: w_F 001:D7:11 reg xmmreg1
xmmreg1 to reg
C5: r_F 001:D7:11 reg xmmreg1
VPMULHUW — Multiply Packed Unsigned Integers and
Store High Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E4:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E4:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E4:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E4:mod xmmreg1 r/m
VPMULHW — Multiply Packed Signed Integers and Store
High Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E5:mod xmmreg1 r/m
VPMULLW — Multiply Packed Signed Integers and Store
Low Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D5:mod xmmreg1 r/m
Vol. 2D B-95
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VPMULUDQ — Multiply Packed Unsigned Doubleword
Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F4:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F4:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F4:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F4:mod xmmreg1 r/m
VPOR — Bitwise Logical OR
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EB:mod xmmreg1 r/m
VPSADBW — Compute Sum of Absolute Differences
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F6:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F6:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F6:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F6:mod xmmreg1 r/m
VPSHUFD — Shuffle Packed Doublewords
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 001:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 001:70:mod xmmreg1 r/m: imm
xmmreglo to xmmreg1 using imm
C5: r_F 001:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 001:70:mod xmmreg1 r/m: imm
VPSHUFHW — Shuffle Packed High Words
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 010:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 010:70:mod xmmreg1 r/m: imm
xmmreglo to xmmreg1 using imm
C5: r_F 010:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 010:70:mod xmmreg1 r/m: imm
VPSHUFLW — Shuffle Packed Low Words
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 011:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 011:70:mod xmmreg1 r/m: imm
xmmreglo to xmmreg1 using imm
C5: r_F 011:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 011:70:mod xmmreg1 r/m: imm
VPSLLDQ — Shift Double Quadword Left Logical
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSLLW — Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F1:mod xmmreg1 r/m
B-96 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSLLD — Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSLLQ — Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F3:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSRAW — Shift Packed Data Right Arithmetic
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSRAD — Shift Packed Data Right Arithmetic
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSRLDQ — Shift Double Quadword Right Logical
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSRLW — Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
Vol. 2D B-97
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
xmmreglo to xmmreg1 using imm8
Encoding
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSRLD — Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSRLQ — Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D3:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSUBB — Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F8:mod xmmreg1 r/m
VPSUBW — Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F9:11 xmmreg1 xmmreglo3
xmmrelog2 with mem to xmmreg1
C5: r_xmmreglo2 001:F9:mod xmmreg1 r/m
VPSUBD — Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FA:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FA:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FA:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FA:mod xmmreg1 r/m
VPSUBQ — Subtract Packed Quadword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FB:mod xmmreg1 r/m
VPSUBSB — Subtract Packed Signed Integers with Signed
Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E8:mod xmmreg1 r/m
B-98 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E8:mod xmmreg1 r/m
VPSUBSW — Subtract Packed Signed Integers with Signed
Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E9:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E9:mod xmmreg1 r/m
VPSUBUSB — Subtract Packed Unsigned Integers with
Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D8:mod xmmreg1 r/m
VPSUBUSW — Subtract Packed Unsigned Integers with
Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D9:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D9:mod xmmreg1 r/m
VPUNPCKHBW — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:68:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:68:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:68:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:68:mod xmmreg1 r/m
VPUNPCKHWD — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:69:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:69:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:69:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:69:mod xmmreg1 r/m
VPUNPCKHDQ — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6A:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6A:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6A:mod xmmreg1 r/m
VPUNPCKHQDQ — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6D:mod xmmreg1 r/m
Vol. 2D B-99
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VPUNPCKLBW — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:60:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:60:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:60:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:60:mod xmmreg1 r/m
VPUNPCKLWD — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:61:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:61:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:61:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:61:mod xmmreg1 r/m
VPUNPCKLDQ — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:62:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:62:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:62:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:62:mod xmmreg1 r/m
VPUNPCKLQDQ — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6C:mod xmmreg1 r/m
VPXOR — Logical Exclusive OR
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EF:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EF:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EF:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EF:mod xmmreg1 r/m
VSHUFPD — Shuffle Packed Double-Precision FloatingPoint Values
xmmreg2 with xmmreg3 to xmmreg1 using imm8
C4: rxb0_1: w xmmreg2 001:C6:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1 using imm8
C4: rxb0_1: w xmmreg2 001:C6:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1 using imm8
C5: r_xmmreglo2 001:C6:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1 using imm8
C5: r_xmmreglo2 001:C6:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1 using imm8
C4: rxb0_1: w ymmreg2 101:C6:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1 using imm8
C4: rxb0_1: w ymmreg2 101:C6:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1 using imm8
C5: r_ymmreglo2 101:C6:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1 using imm8
C5: r_ymmreglo2 101:C6:mod ymmreg1 r/m: imm
VSQRTPD — Compute Square Roots of Packed DoublePrecision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:51:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:51:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:51:11 xmmreg1 xmmreglo
B-100 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
mem to xmmreg1
C5: r_F 001:51:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:51:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:51:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:51:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:51:mod ymmreg1 r/m
VSQRTSD — Compute Square Root of Scalar DoublePrecision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:51:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:51:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:51:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:51:mod xmmreg1 r/m
VSUBPD — Subtract Packed Double-Precision FloatingPoint Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5C:mod ymmreg1 r/m
VSUBSD — Subtract Scalar Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5C:mod xmmreg1 r/m
VUCOMISD — Unordered Compare Scalar Double-Precision
Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1, set EFLAGS
C4: rxb0_1: w_F xmmreg1 001:2E:11 xmmreg2
mem with xmmreg1, set EFLAGS
C4: rxb0_1: w_F xmmreg1 001:2E:mod r/m
xmmreglo with xmmreg1, set EFLAGS
C5: r_F xmmreg1 001:2E:11 xmmreglo
mem with xmmreg1, set EFLAGS
C5: r_F xmmreg1 001:2E:mod r/m
VUNPCKHPD — Unpack and Interleave High Packed
Double-Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:15:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:15:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:15:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:15:mod ymmreg1 r/m
Vol. 2D B-101
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:15:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:15:mod ymmreg1 r/m
VUNPCKHPS — Unpack and Interleave High Packed SinglePrecision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:15:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:15:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:15:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:15:mod ymmreg1 r/m
VUNPCKLPD — Unpack and Interleave Low Packed DoublePrecision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:14:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:14:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:14:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:14:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:14:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:14:mod ymmreg1 r/m
VUNPCKLPS — Unpack and Interleave Low Packed SinglePrecision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:14:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:14:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:14:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:14:mod ymmreg1 r/m
VXORPD — Bitwise Logical XOR for Double-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:57:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:57:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:57:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:57:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:57:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:57:mod ymmreg1 r/m
B-102 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:57:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:57:mod ymmreg1 r/m
VADDPS — Add Packed Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:58:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:58:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:58:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:58:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:58:mod ymmreg1 r/m
VADDSS — Add Scalar Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:58:mod xmmreg1 r/m
VANDPS — Bitwise Logical AND of Packed Single-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:54:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:54:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:54:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:54:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:54:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:54:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:54:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:54:mod ymmreg1 r/m
VANDNPS — Bitwise Logical AND NOT of Packed SinglePrecision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:55:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:55:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:55:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:55:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:55:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:55:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:55:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:55:mod ymmreg1 r/m
VCMPPS — Compare Packed Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:C2:11 xmmreg1 xmmreg3: imm
Vol. 2D B-103
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:C2:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:C2:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:C2:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:C2:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:C2:mod ymmreg1 r/m: imm
VCMPSS — Compare Scalar Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:C2:mod xmmreg1 r/m: imm
VCOMISS — Compare Scalar Ordered Single-Precision
Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1
C4: rxb0_1: w_F 000:2F:11 xmmreg1 xmmreg2
mem with xmmreg1
C4: rxb0_1: w_F 000:2F:mod xmmreg1 r/m
xmmreglo with xmmreg1
C5: r_F 000:2F:11 xmmreg1 xmmreglo
mem with xmmreg1
C5: r_F 000:2F:mod xmmreg1 r/m
VCVTSI2SS — Convert Dword Integer to Scalar SinglePrecision FP Value
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 0 xmmreg2 010:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 0 xmmreg2 010:2A:mod xmmreg1 r/m
xmmreglo2 with reglo to xmmreg1
C5: r_xmmreglo2 010:2A:11 xmmreg1 reglo
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:2A:mod xmmreg1 r/m
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 1 xmmreg2 010:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 1 xmmreg2 010:2A:mod xmmreg1 r/m
VCVTSS2SI — Convert Scalar Single-Precision FP Value to
Dword Integer
xmmreg1 to reg
C4: rxb0_1: 0_F 010:2D:11 reg xmmreg1
mem to reg
C4: rxb0_1: 0_F 010:2D:mod reg r/m
xmmreglo to reg
C5: r_F 010:2D:11 reg xmmreglo
mem to reg
C5: r_F 010:2D:mod reg r/m
xmmreg1 to reg
C4: rxb0_1: 1_F 010:2D:11 reg xmmreg1
mem to reg
C4: rxb0_1: 1_F 010:2D:mod reg r/m
VCVTTSS2SI — Convert with Truncation Scalar SinglePrecision FP Value to Dword Integer
xmmreg1 to reg
C4: rxb0_1: 0_F 010:2C:11 reg xmmreg1
mem to reg
C4: rxb0_1: 0_F 010:2C:mod reg r/m
xmmreglo to reg
C5: r_F 010:2C:11 reg xmmreglo
mem to reg
C5: r_F 010:2C:mod reg r/m
B-104 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg1 to reg
C4: rxb0_1: 1_F 010:2C:11 reg xmmreg1
mem to reg
C4: rxb0_1: 1_F 010:2C:mod reg r/m
VDIVPS — Divide Packed Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5E:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5E:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5E:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5E:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5E:mod ymmreg1 r/m
VDIVSS — Divide Scalar Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5E:mod xmmreg1 r/m
VLDMXCSR — Load MXCSR Register
mem to MXCSR reg
C4: rxb0_1: w_F 000:AEmod 011 r/m
mem to MXCSR reg
C5: r_F 000:AEmod 011 r/m
VMAXPS — Return Maximum Packed Single-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5F:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5F:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5F:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5F:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5F:mod ymmreg1 r/m
VMAXSS — Return Maximum Scalar Single-Precision
Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5F:mod xmmreg1 r/m
VMINPS — Return Minimum Packed Single-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5D:mod xmmreg1 r/m
Vol. 2D B-105
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5D:mod ymmreg1 r/m
VMINSS — Return Minimum Scalar Single-Precision
Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5D:mod xmmreg1 r/m
VMOVAPS— Move Aligned Packed Single-Precision
Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:28:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:28:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:28:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:28:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 000:29:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 000:29:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 000:29:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 000:29:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:28:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:28:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:28:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:28:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 100:29:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 100:29:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 100:29:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 100:29:mod r/m ymmreg1
VMOVHPS — Move High Packed Single-Precision FloatingPoint Values
xmmreg1 with mem to xmmreg2
C4: rxb0_1: w xmmreg1 000:16:mod xmmreg2 r/m
xmmreg1 with mem to xmmreglo2
C5: r_xmmreg1 000:16:mod xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 000:17:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 000:17:mod r/m xmmreglo
VMOVLHPS — Move Packed Single-Precision Floating-Point
Values Low to High
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:16:11 xmmreg1 xmmreg3
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:16:11 xmmreg1 xmmreglo3
B-106 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VMOVLPS — Move Low Packed Single-Precision FloatingPoint Values
xmmreg1 with mem to xmmreg2
C4: rxb0_1: w xmmreg1 000:12:mod xmmreg2 r/m
xmmreg1 with mem to xmmreglo2
C5: r_xmmreg1 000:12:mod xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 000:13:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 000:13:mod r/m xmmreglo
VMOVMSKPS — Extract Packed Single-Precision FloatingPoint Sign Mask
xmmreg2 to reg
C4: rxb0_1: w_F 000:50:11 reg xmmreg2
xmmreglo to reg
C5: r_F 000:50:11 reg xmmreglo
ymmreg2 to reg
C4: rxb0_1: w_F 100:50:11 reg ymmreg2
ymmreglo to reg
C5: r_F 100:50:11 reg ymmreglo
VMOVNTPS — Store Packed Single-Precision Floating-Point
Values Using Non-Temporal Hint
xmmreg1 to mem
C4: rxb0_1: w_F 000:2B:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 000:2B:mod r/m xmmreglo
ymmreg1 to mem
C4: rxb0_1: w_F 100:2B:mod r/m ymmreg1
ymmreglo to mem
C5: r_F 100:2B:mod r/m ymmreglo
VMOVSS — Move Scalar Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C4: rxb0_1: w_F 010:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C5: r_xmmreg2 010:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C5: r_F 010:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:11:11 xmmreg1 xmmreg3
xmmreg1 to mem
C4: rxb0_1: w_F 010:11:mod r/m xmmreg1
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:11:11 xmmreg1 xmmreglo3
xmmreglo to mem
C5: r_F 010:11:mod r/m xmmreglo
VMOVUPS— Move Unaligned Packed Single-Precision
Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:10:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:10:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:10:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:10:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:10:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:10:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:10:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:10:mod ymmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 000:11:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 000:11:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 000:11:11 xmmreglo xmmreg1
Vol. 2D B-107
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg1 to mem
C5: r_F 000:11:mod r/m xmmreg1
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 100:11:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 100:11:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 100:11:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 100:11:mod r/m ymmreg1
VMULPS — Multiply Packed Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:59:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:59:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:59:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:59:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:59:mod ymmreg1 r/m
VMULSS — Multiply Scalar Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:59:mod xmmreg1 r/m
VORPS — Bitwise Logical OR of Single-Precision FloatingPoint Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:56:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:56:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:56:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:56:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:56:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:56:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:56:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:56:mod ymmreg1 r/m
VRCPPS — Compute Reciprocals of Packed Single-Precision
Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:53:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:53:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:53:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:53:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:53:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:53:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:53:11 ymmreg1 ymmreglo
B-108 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
mem to ymmreg1
Encoding
C5: r_F 100:53:mod ymmreg1 r/m
VRCPSS — Compute Reciprocal of Scalar Single-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:53:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:53:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:53:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:53:mod xmmreg1 r/m
VRSQRTPS — Compute Reciprocals of Square Roots of
Packed Single-Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:52:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:52:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:52:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:52:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:52:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:52:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:52:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:52:mod ymmreg1 r/m
VRSQRTSS — Compute Reciprocal of Square Root of Scalar
Single-Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:52:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:52:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:52:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:52:mod xmmreg1 r/m
VSHUFPS — Shuffle Packed Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1, imm8
C4: rxb0_1: w xmmreg2 000:C6:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1, imm8
C4: rxb0_1: w xmmreg2 000:C6:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1, imm8
C5: r_xmmreglo2 000:C6:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1, imm8
C5: r_xmmreglo2 000:C6:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1, imm8
C4: rxb0_1: w ymmreg2 100:C6:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1, imm8
C4: rxb0_1: w ymmreg2 100:C6:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1, imm8
C5: r_ymmreglo2 100:C6:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1, imm8
C5: r_ymmreglo2 100:C6:mod ymmreg1 r/m: imm
VSQRTPS — Compute Square Roots of Packed SinglePrecision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:51:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:51:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:51:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:51:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:51:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:51:mod ymmreg1 r/m
Vol. 2D B-109
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo to ymmreg1
C5: r_F 100:51:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:51:mod ymmreg1 r/m
VSQRTSS — Compute Square Root of Scalar SinglePrecision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:51:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:51:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:51:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:51:mod xmmreg1 r/m
VSTMXCSR — Store MXCSR Register State
MXCSR to mem
C4: rxb0_1: w_F 000:AE:mod 011 r/m
MXCSR to mem
C5: r_F 000:AE:mod 011 r/m
VSUBPS — Subtract Packed Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5C:mod ymmreg1 r/m
VSUBSS — Subtract Scalar Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5C:mod xmmreg1 r/m
VUCOMISS — Unordered Compare Scalar Single-Precision
Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1
C4: rxb0_1: w_F 000:2E:11 xmmreg1 xmmreg2
mem with xmmreg1
C4: rxb0_1: w_F 000:2E:mod xmmreg1 r/m
xmmreglo with xmmreg1
C5: r_F 000:2E:11 xmmreg1 xmmreglo
mem with xmmreg1
C5: r_F 000:2E:mod xmmreg1 r/m
UNPCKHPS — Unpack and Interleave High Packed SinglePrecision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:15mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:15mod ymmreg1 r/m
UNPCKLPS — Unpack and Interleave Low Packed SinglePrecision Floating-Point Value
B-110 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:14mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:14mod ymmreg1 r/m
VXORPS — Bitwise Logical XOR for Single-Precision
Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:57:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:57:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:57:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:57:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:57:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:57:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:57:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:57:mod ymmreg1 r/m
VBROADCAST —Load with Broadcast
mem to xmmreg1
C4: rxb0_2: 0_F 001:18:mod xmmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:18:mod ymmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:19:mod ymmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:1A:mod ymmreg1 r/m
VEXTRACTF128 — Extract Packed Floating-Point Values
ymmreg2 to xmmreg1, imm8
C4: rxb0_3: 0_F 001:19:11 xmmreg1 ymmreg2: imm
ymmreg2 to mem, imm8
C4: rxb0_3: 0_F 001:19:mod r/m ymmreg2: imm
VINSERTF128 — Insert Packed Floating-Point Values
xmmreg3 and merge with ymmreg2 to ymmreg1, imm8
C4: rxb0_3: 0 ymmreg2101:18:11 ymmreg1 xmmreg3: imm
mem and merge with ymmreg2 to ymmreg1, imm8
C4: rxb0_3: 0 ymmreg2 101:18:mod ymmreg1 r/m: imm
VPERMILPD — Permute Double-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0D:mod ymmreg1 r/m
xmmreg2 to xmmreg1, imm
C4: rxb0_3: 0_F 001:05:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm
C4: rxb0_3: 0_F 001:05:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1, imm
C4: rxb0_3: 0_F 101:05:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm
C4: rxb0_3: 0_F 101:05:mod ymmreg1 r/m: imm
VPERMILPS — Permute Single-Precision Floating-Point
Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0C:mod xmmreg1 r/m
xmmreg2 to xmmreg1, imm
C4: rxb0_3: 0_F 001:04:11 xmmreg1 xmmreg2: imm
Vol. 2D B-111
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
mem to xmmreg1, imm
C4: rxb0_3: 0_F 001:04:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0C:mod ymmreg1 r/m
ymmreg2 to ymmreg1, imm
C4: rxb0_3: 0_F 101:04:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm
C4: rxb0_3: 0_F 101:04:mod ymmreg1 r/m: imm
VPERM2F128 — Permute Floating-Point Values
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_3: 0 ymmreg2 101:06:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: 0 ymmreg2 101:06:mod ymmreg1 r/m: imm
VTESTPD/VTESTPS — Packed Bit Test
xmmreg2 to xmmreg1
C4: rxb0_2: 0_F 001:0E:11 xmmreg2 xmmreg1
mem to xmmreg1
C4: rxb0_2: 0_F 001:0E:mod xmmreg2 r/m
ymmreg2 to ymmreg1
C4: rxb0_2: 0_F 101:0E:11 ymmreg2 ymmreg1
mem to ymmreg1
C4: rxb0_2: 0_F 101:0E:mod ymmreg2 r/m
xmmreg2 to xmmreg1
C4: rxb0_2: 0_F 001:0F:11 xmmreg1 xmmreg2: imm
mem to xmmreg1
C4: rxb0_2: 0_F 001:0F:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1
C4: rxb0_2: 0_F 101:0F:11 ymmreg1 ymmreg2: imm
mem to ymmreg1
C4: rxb0_2: 0_F 101:0F:mod ymmreg1 r/m: imm
NOTES:
1. The term “lo” refers to the lower eight registers, 0-7
B-112 Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
B.17
FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS
Table B-38 shows the five different formats used for floating-point instructions. In all cases, instructions are at
least two bytes long and begin with the bit pattern 11011.
Table B-38. General Floating-Point Instruction Formats
Instruction
First Byte
Second Byte
1
11011
OPA
1
mod
2
11011
MF
OPA
mod
3
11011
d
P
OPA
1
1
OPB
4
11011
0
0
1
1
1
1
OP
5
11011
0
1
1
1
1
1
OP
15–11
10
9
8
7
6
5
MF = Memory Format
00 — 32-bit real
01 — 32-bit integer
10 — 64-bit real
11 — 16-bit integer
P = Pop
0 — Do not pop stack
1 — Pop stack after operation
d = Destination
0 — Destination is ST(0)
1 — Destination is ST(i)
1
Optional Fields
OPB
OPB
R
4
r/m
s-i-b
disp
r/m
s-i-b
disp
ST(i)
3
2 1 0
R XOR d = 0 — Destination OP Source
R XOR d = 1 — Source OP Destination
ST(i) = Register stack element i
000 = Stack Top
001 = Second stack element
⋅
⋅
⋅
111 = Eighth stack element
The Mod and R/M fields of the ModR/M byte have the same interpretation as the corresponding fields of the integer
instructions. The SIB byte and disp (displacement) are optionally present in instructions that have Mod and R/M
fields. Their presence depends on the values of Mod and R/M, as for integer instructions.
Table B-39 shows the formats and encodings of the floating-point instructions.
Table B-39. Floating-Point Instruction Formats and Encodings
Instruction and Format
F2XM1 – Compute
2ST(0)
–1
FABS – Absolute Value
Encoding
11011 001 : 1111 0000
11011 001 : 1110 0001
FADD – Add
ST(0) ← ST(0) + 32-bit memory
11011 000 : mod 000 r/m
ST(0) ← ST(0) + 64-bit memory
11011 100 : mod 000 r/m
ST(d) ← ST(0) + ST(i)
11011 d00 : 11 000 ST(i)
FADDP – Add and Pop
ST(0) ← ST(0) + ST(i)
11011 110 : 11 000 ST(i)
FBLD – Load Binary Coded Decimal
11011 111 : mod 100 r/m
FBSTP – Store Binary Coded Decimal and Pop
11011 111 : mod 110 r/m
FCHS – Change Sign
11011 001 : 1110 0000
FCLEX – Clear Exceptions
11011 011 : 1110 0010
FCOM – Compare Real
Vol. 2D B-113
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
32-bit memory
Encoding
11011 000 : mod 010 r/m
64-bit memory
11011 100 : mod 010 r/m
ST(i)
11011 000 : 11 010 ST(i)
FCOMP – Compare Real and Pop
32-bit memory
11011 000 : mod 011 r/m
64-bit memory
11011 100 : mod 011 r/m
ST(i)
11011 000 : 11 011 ST(i)
FCOMPP – Compare Real and Pop Twice
11011 110 : 11 011 001
FCOMIP – Compare Real, Set EFLAGS, and Pop
11011 111 : 11 110 ST(i)
FCOS – Cosine of ST(0)
11011 001 : 1111 1111
FDECSTP – Decrement Stack-Top Pointer
11011 001 : 1111 0110
FDIV – Divide
ST(0) ← ST(0) ÷ 32-bit memory
11011 000 : mod 110 r/m
ST(0) ← ST(0) ÷ 64-bit memory
11011 100 : mod 110 r/m
ST(d) ← ST(0) ÷ ST(i)
11011 d00 : 1111 R ST(i)
FDIVP – Divide and Pop
ST(0) ← ST(0) ÷ ST(i)
11011 110 : 1111 1 ST(i)
FDIVR – Reverse Divide
ST(0) ← 32-bit memory ÷ ST(0)
11011 000 : mod 111 r/m
ST(0) ← 64-bit memory ÷ ST(0)
11011 100 : mod 111 r/m
ST(d) ← ST(i) ÷ ST(0)
11011 d00 : 1111 R ST(i)
FDIVRP – Reverse Divide and Pop
ST(0) ¨ ST(i) ÷ ST(0)
FFREE – Free ST(i) Register
11011 110 : 1111 0 ST(i)
11011 101 : 1100 0 ST(i)
FIADD – Add Integer
ST(0) ← ST(0) + 16-bit memory
11011 110 : mod 000 r/m
ST(0) ← ST(0) + 32-bit memory
11011 010 : mod 000 r/m
FICOM – Compare Integer
16-bit memory
11011 110 : mod 010 r/m
32-bit memory
11011 010 : mod 010 r/m
FICOMP – Compare Integer and Pop
16-bit memory
11011 110 : mod 011 r/m
32-bit memory
11011 010 : mod 011 r/m
FIDIV – Divide
ST(0) ← ST(0) ÷ 16-bit memory
11011 110 : mod 110 r/m
ST(0) ← ST(0) ÷ 32-bit memory
11011 010 : mod 110 r/m
FIDIVR – Reverse Divide
ST(0) ← 16-bit memory ÷ ST(0)
B-114 Vol. 2D
11011 110 : mod 111 r/m
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
ST(0) ← 32-bit memory ÷ ST(0)
Encoding
11011 010 : mod 111 r/m
FILD – Load Integer
16-bit memory
11011 111 : mod 000 r/m
32-bit memory
11011 011 : mod 000 r/m
64-bit memory
11011 111 : mod 101 r/m
FIMUL– Multiply
ST(0) ← ST(0) × 16-bit memory
ST(0) ← ST(0) × 32-bit memory
FINCSTP – Increment Stack Pointer
11011 110 : mod 001 r/m
11011 010 : mod 001 r/m
11011 001 : 1111 0111
FINIT – Initialize Floating-Point Unit
FIST – Store Integer
16-bit memory
11011 111 : mod 010 r/m
32-bit memory
11011 011 : mod 010 r/m
FISTP – Store Integer and Pop
16-bit memory
11011 111 : mod 011 r/m
32-bit memory
11011 011 : mod 011 r/m
64-bit memory
11011 111 : mod 111 r/m
FISUB – Subtract
ST(0) ← ST(0) - 16-bit memory
11011 110 : mod 100 r/m
ST(0) ← ST(0) - 32-bit memory
11011 010 : mod 100 r/m
FISUBR – Reverse Subtract
ST(0) ← 16-bit memory − ST(0)
11011 110 : mod 101 r/m
ST(0) ← 32-bit memory − ST(0)
11011 010 : mod 101 r/m
FLD – Load Real
32-bit memory
11011 001 : mod 000 r/m
64-bit memory
11011 101 : mod 000 r/m
80-bit memory
11011 011 : mod 101 r/m
ST(i)
11011 001 : 11 000 ST(i)
FLD1 – Load +1.0 into ST(0)
11011 001 : 1110 1000
FLDCW – Load Control Word
11011 001 : mod 101 r/m
FLDENV – Load FPU Environment
11011 001 : mod 100 r/m
FLDL2E – Load log2(ε) into ST(0)
11011 001 : 1110 1010
FLDL2T – Load log2(10) into ST(0)
11011 001 : 1110 1001
FLDLG2 – Load log10(2) into ST(0)
11011 001 : 1110 1100
FLDLN2 – Load logε(2) into ST(0)
11011 001 : 1110 1101
FLDPI – Load π into ST(0)
11011 001 : 1110 1011
FLDZ – Load +0.0 into ST(0)
11011 001 : 1110 1110
FMUL – Multiply
Vol. 2D B-115
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) ← ST(0) × 32-bit memory
11011 000 : mod 001 r/m
ST(0) ← ST(0) × 64-bit memory
11011 100 : mod 001 r/m
ST(d) ← ST(0) × ST(i)
11011 d00 : 1100 1 ST(i)
FMULP – Multiply
ST(i) ← ST(0) × ST(i)
11011 110 : 1100 1 ST(i)
FNOP – No Operation
11011 001 : 1101 0000
FPATAN – Partial Arctangent
11011 001 : 1111 0011
FPREM – Partial Remainder
11011 001 : 1111 1000
FPREM1 – Partial Remainder (IEEE)
11011 001 : 1111 0101
FPTAN – Partial Tangent
11011 001 : 1111 0010
FRNDINT – Round to Integer
11011 001 : 1111 1100
FRSTOR – Restore FPU State
11011 101 : mod 100 r/m
FSAVE – Store FPU State
11011 101 : mod 110 r/m
FSCALE – Scale
11011 001 : 1111 1101
FSIN – Sine
11011 001 : 1111 1110
FSINCOS – Sine and Cosine
11011 001 : 1111 1011
FSQRT – Square Root
11011 001 : 1111 1010
FST – Store Real
32-bit memory
11011 001 : mod 010 r/m
64-bit memory
11011 101 : mod 010 r/m
ST(i)
11011 101 : 11 010 ST(i)
FSTCW – Store Control Word
11011 001 : mod 111 r/m
FSTENV – Store FPU Environment
11011 001 : mod 110 r/m
FSTP – Store Real and Pop
32-bit memory
11011 001 : mod 011 r/m
64-bit memory
11011 101 : mod 011 r/m
80-bit memory
11011 011 : mod 111 r/m
ST(i)
11011 101 : 11 011 ST(i)
FSTSW – Store Status Word into AX
11011 111 : 1110 0000
FSTSW – Store Status Word into Memory
11011 101 : mod 111 r/m
FSUB – Subtract
ST(0) ← ST(0) – 32-bit memory
11011 000 : mod 100 r/m
ST(0) ← ST(0) – 64-bit memory
11011 100 : mod 100 r/m
ST(d) ← ST(0) – ST(i)
11011 d00 : 1110 R ST(i)
FSUBP – Subtract and Pop
ST(0) ← ST(0) – ST(i)
11011 110 : 1110 1 ST(i)
FSUBR – Reverse Subtract
ST(0) ← 32-bit memory – ST(0)
B-116 Vol. 2D
11011 000 : mod 101 r/m
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) ← 64-bit memory – ST(0)
11011 100 : mod 101 r/m
ST(d) ← ST(i) – ST(0)
11011 d00 : 1110 R ST(i)
FSUBRP – Reverse Subtract and Pop
ST(i) ← ST(i) – ST(0)
11011 110 : 1110 0 ST(i)
FTST – Test
11011 001 : 1110 0100
FUCOM – Unordered Compare Real
11011 101 : 1110 0 ST(i)
FUCOMP – Unordered Compare Real and Pop
11011 101 : 1110 1 ST(i)
FUCOMPP – Unordered Compare Real and Pop Twice
11011 010 : 1110 1001
FUCOMI – Unorderd Compare Real and Set EFLAGS
11011 011 : 11 101 ST(i)
FUCOMIP – Unorderd Compare Real, Set EFLAGS, and Pop
11011 111 : 11 101 ST(i)
FXAM – Examine
11011 001 : 1110 0101
FXCH – Exchange ST(0) and ST(i)
11011 001 : 1100 1 ST(i)
FXTRACT – Extract Exponent and Significand
11011 001 : 1111 0100
FYL2X – ST(1) × log2(ST(0))
11011 001 : 1111 0001
FYL2XP1 – ST(1) × log2(ST(0) + 1.0)
11011 001 : 1111 1001
FWAIT – Wait until FPU Ready
1001 1011 (same instruction as WAIT)
B.18
VMX INSTRUCTIONS
Table B-40 describes virtual-machine extensions (VMX).
Table B-40. Encodings for VMX Instructions
Instruction and Format
Encoding
INVEPT—Invalidate Cached EPT Mappings
Descriptor m128 according to reg
01100110 00001111 00111000 10000000: mod reg r/m
INVVPID—Invalidate Cached VPID Mappings
Descriptor m128 according to reg
01100110 00001111 00111000 10000001: mod reg r/m
VMCALL—Call to VM Monitor
Call VMM: causes VM exit.
00001111 00000001 11000001
VMCLEAR—Clear Virtual-Machine Control Structure
mem32:VMCS_data_ptr
01100110 00001111 11000111: mod 110 r/m
mem64:VMCS_data_ptr
01100110 00001111 11000111: mod 110 r/m
VMFUNC—Invoke VM Function
Invoke VM function specified in EAX
00001111 00000001 11010100
VMLAUNCH—Launch Virtual Machine
Launch VM managed by Current_VMCS
00001111 00000001 11000010
VMRESUME—Resume Virtual Machine
Resume VM managed by Current_VMCS
00001111 00000001 11000011
VMPTRLD—Load Pointer to Virtual-Machine Control
Structure
Vol. 2D B-117
INSTRUCTION FORMATS AND ENCODINGS
Table B-40. Encodings for VMX Instructions
Instruction and Format
Encoding
mem32 to Current_VMCS_ptr
00001111 11000111: mod 110 r/m
mem64 to Current_VMCS_ptr
00001111 11000111: mod 110 r/m
VMPTRST—Store Pointer to Virtual-Machine Control
Structure
Current_VMCS_ptr to mem32
00001111 11000111: mod 111 r/m
Current_VMCS_ptr to mem64
00001111 11000111: mod 111 r/m
VMREAD—Read Field from Virtual-Machine Control
Structure
r32 (VMCS_fieldn) to r32
00001111 01111000: 11 reg2 reg1
r32 (VMCS_fieldn) to mem32
00001111 01111000: mod r32 r/m
r64 (VMCS_fieldn) to r64
00001111 01111000: 11 reg2 reg1
r64 (VMCS_fieldn) to mem64
00001111 01111000: mod r64 r/m
VMWRITE—Write Field to Virtual-Machine Control Structure
r32 to r32 (VMCS_fieldn)
00001111 01111001: 11 reg1 reg2
mem32 to r32 (VMCS_fieldn)
00001111 01111001: mod r32 r/m
r64 to r64 (VMCS_fieldn)
00001111 01111001: 11 reg1 reg2
mem64 to r64 (VMCS_fieldn)
00001111 01111001: mod r64 r/m
VMXOFF—Leave VMX Operation
Leave VMX.
00001111 00000001 11000100
VMXON—Enter VMX Operation
Enter VMX.
B.19
11110011 000011111 11000111: mod 110 r/m
SMX INSTRUCTIONS
Table B-38 describes Safer Mode extensions (VMX). GETSEC leaf functions are selected by a valid value in EAX on input.
Table B-41. Encodings for SMX Instructions
Instruction and Format
Encoding
GETSEC—GETSEC leaf functions are
selected by the value in EAX on input
B-118 Vol. 2D
GETSEC[CAPABILITIES]
00001111 00110111 (EAX= 0)
GETSEC[ENTERACCS]
00001111 00110111 (EAX= 2)
GETSEC[EXITAC]
00001111 00110111 (EAX= 3)
GETSEC[SENTER]
00001111 00110111 (EAX= 4)
GETSEC[SEXIT]
00001111 00110111 (EAX= 5)
GETSEC[PARAMETERS]
00001111 00110111 (EAX= 6)
GETSEC[SMCTRL]
00001111 00110111 (EAX= 7)
GETSEC[WAKEUP]
00001111 00110111 (EAX= 8)
APPENDIX C
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
The two tables in this appendix itemize the Intel C/C++ compiler intrinsics and functional equivalents for the Intel
MMX technology, SSE, SSE2, SSE3, and SSSE3 instructions.
There may be additional intrinsics that do not have an instruction equivalent. It is strongly recommended that the
reader reference the compiler documentation for the complete list of supported intrinsics. Please refer to
http://www.intel.com/support/performancetools/.
Table C-1 presents simple intrinsics and Table C-2 presents composite intrinsics. Some intrinsics are “composites”
because they require more than one instruction to implement them.
Intel C/C++ Compiler intrinsic names reflect the following naming conventions:
_mm__
where:
Indicates the intrinsics basic operation; for example, add for addition and sub for subtraction
Denotes the type of data operated on by the instruction. The first one or two letters of
each suffix denotes whether the data is packed (p), extended packed (ep), or scalar (s).
The remaining letters denote the type:
s
single-precision floating point
d
double-precision floating point
i128
signed 128-bit integer
i64
signed 64-bit integer
u64
unsigned 64-bit integer
i32
signed 32-bit integer
u32
unsigned 32-bit integer
i16
signed 16-bit integer
u16
unsigned 16-bit integer
i8
signed 8-bit integer
u8
unsigned 8-bit integer
The variable r is generally used for the intrinsic's return value. A number appended to a variable name indicates the
element of a packed object. For example, r0 is the lowest word of r.
The packed values are represented in right-to-left order, with the lowest value being used for scalar operations.
Consider the following example operation:
double a[2] = {1.0, 2.0};
__m128d t = _mm_load_pd(a);
The result is the same as either of the following:
__m128d t = _mm_set_pd(2.0, 1.0);
__m128d t = _mm_setr_pd(1.0, 2.0);
In other words, the XMM register that holds the value t will look as follows:
2.0
127
1.0
64 63
0
Vol. 2D C-1
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
The “scalar” element is 1.0. Due to the nature of the instruction, some intrinsics require their arguments to be
immediates (constant integer literals).
To use an intrinsic in your code, insert a line with the following syntax:
data_type intrinsic_name (parameters)
Where:
data_type
Is the return data type, which can be either void, int, __m64, __m128, __m128d, or
__m128i. Only the _mm_empty intrinsic returns void.
intrinsic_name
Is the name of the intrinsic, which behaves like a function that you can use in your C/C++
code instead of in-lining the actual instruction.
parameters
Represents the parameters required by each intrinsic.
C.1
SIMPLE INTRINSICS
NOTE
For detailed descriptions of the intrinsics in Table C-1, see the corresponding mnemonic in Chapter
3, “Instruction Set Reference, A-L” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A, Chapter 4, “Instruction Set Reference, M-U” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, or Chapter 5, “Instruction Set Reference, V-Z,”
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2C.
Table C-1. Simple Intrinsics
Mnemonic
Intrinsic
ADDPD
__m128d _mm_add_pd(__m128d a, __m128d b)
ADDPS
__m128 _mm_add_ps(__m128 a, __m128 b)
ADDSD
__m128d _mm_add_sd(__m128d a, __m128d b)
ADDSS
__m128 _mm_add_ss(__m128 a, __m128 b)
ADDSUBPD
__m128d _mm_addsub_pd(__m128d a, __m128d b)
ADDSUBPS
__m128 _mm_addsub_ps(__m128 a, __m128 b)
AESDEC
__m128i _mm_aesdec (__m128i, __m128i)
AESDECLAST
__m128i _mm_aesdeclast (__m128i, __m128i)
AESENC
__m128i _mm_aesenc (__m128i, __m128i)
AESENCLAST
__m128i _mm_aesenclast (__m128i, __m128i)
AESIMC
__m128i _mm_aesimc (__m128i)
AESKEYGENASSIST
__m128i _mm_aesimc (__m128i, const int)
ANDNPD
__m128d _mm_andnot_pd(__m128d a, __m128d b)
ANDNPS
__m128 _mm_andnot_ps(__m128 a, __m128 b)
ANDPD
__m128d _mm_and_pd(__m128d a, __m128d b)
ANDPS
__m128 _mm_and_ps(__m128 a, __m128 b)
BLENDPD
__m128d _mm_blend_pd(__m128d v1, __m128d v2, const int mask)
BLENDPS
__m128 _mm_blend_ps(__m128 v1, __m128 v2, const int mask)
BLENDVPD
__m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3)
BLENDVPS
__m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3)
CLFLUSH
void _mm_clflush(void const *p)
CMPPD
__m128d _mm_cmpeq_pd(__m128d a, __m128d b)
C-2 Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
__m128d _mm_cmplt_pd(__m128d a, __m128d b)
__m128d _mm_cmple_pd(__m128d a, __m128d b)
__m128d _mm_cmpgt_pd(__m128d a, __m128d b)
__m128d _mm_cmpge_pd(__m128d a, __m128d b)
__m128d _mm_cmpneq_pd(__m128d a, __m128d b)
__m128d _mm_cmpnlt_pd(__m128d a, __m128d b)
__m128d _mm_cmpngt_pd(__m128d a, __m128d b)
__m128d _mm_cmpnge_pd(__m128d a, __m128d b)
__m128d _mm_cmpord_pd(__m128d a, __m128d b)
__m128d _mm_cmpunord_pd(__m128d a, __m128d b)
__m128d _mm_cmpnle_pd(__m128d a, __m128d b)
CMPPS
__m128 _mm_cmpeq_ps(__m128 a, __m128 b)
__m128 _mm_cmplt_ps(__m128 a, __m128 b)
__m128 _mm_cmple_ps(__m128 a, __m128 b)
__m128 _mm_cmpgt_ps(__m128 a, __m128 b)
__m128 _mm_cmpge_ps(__m128 a, __m128 b)
__m128 _mm_cmpneq_ps(__m128 a, __m128 b)
__m128 _mm_cmpnlt_ps(__m128 a, __m128 b)
__m128 _mm_cmpngt_ps(__m128 a, __m128 b)
__m128 _mm_cmpnge_ps(__m128 a, __m128 b)
__m128 _mm_cmpord_ps(__m128 a, __m128 b)
__m128 _mm_cmpunord_ps(__m128 a, __m128 b)
__m128 _mm_cmpnle_ps(__m128 a, __m128 b)
CMPSD
__m128d _mm_cmpeq_sd(__m128d a, __m128d b)
__m128d _mm_cmplt_sd(__m128d a, __m128d b)
__m128d _mm_cmple_sd(__m128d a, __m128d b)
__m128d _mm_cmpgt_sd(__m128d a, __m128d b)
__m128d _mm_cmpge_sd(__m128d a, __m128d b)
__m128 _mm_cmpneq_sd(__m128d a, __m128d b)
__m128 _mm_cmpnlt_sd(__m128d a, __m128d b)
__m128d _mm_cmpnle_sd(__m128d a, __m128d b)
__m128d _mm_cmpngt_sd(__m128d a, __m128d b)
__m128d _mm_cmpnge_sd(__m128d a, __m128d b)
__m128d _mm_cmpord_sd(__m128d a, __m128d b)
__m128d _mm_cmpunord_sd(__m128d a, __m128d b)
CMPSS
__m128 _mm_cmpeq_ss(__m128 a, __m128 b)
__m128 _mm_cmplt_ss(__m128 a, __m128 b)
__m128 _mm_cmple_ss(__m128 a, __m128 b)
__m128 _mm_cmpgt_ss(__m128 a, __m128 b)
__m128 _mm_cmpge_ss(__m128 a, __m128 b)
__m128 _mm_cmpneq_ss(__m128 a, __m128 b)
Vol. 2D C-3
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
__m128 _mm_cmpnlt_ss(__m128 a, __m128 b)
__m128 _mm_cmpnle_ss(__m128 a, __m128 b)
__m128 _mm_cmpngt_ss(__m128 a, __m128 b)
__m128 _mm_cmpnge_ss(__m128 a, __m128 b)
__m128 _mm_cmpord_ss(__m128 a, __m128 b)
__m128 _mm_cmpunord_ss(__m128 a, __m128 b)
COMISD
int _mm_comieq_sd(__m128d a, __m128d b)
int _mm_comilt_sd(__m128d a, __m128d b)
int _mm_comile_sd(__m128d a, __m128d b)
int _mm_comigt_sd(__m128d a, __m128d b)
int _mm_comige_sd(__m128d a, __m128d b)
int _mm_comineq_sd(__m128d a, __m128d b)
COMISS
int _mm_comieq_ss(__m128 a, __m128 b)
int _mm_comilt_ss(__m128 a, __m128 b)
int _mm_comile_ss(__m128 a, __m128 b)
int _mm_comigt_ss(__m128 a, __m128 b)
int _mm_comige_ss(__m128 a, __m128 b)
int _mm_comineq_ss(__m128 a, __m128 b)
CRC32
unsigned int _mm_crc32_u8(unsigned int crc, unsigned char data)
unsigned int _mm_crc32_u16(unsigned int crc, unsigned short data)
unsigned int _mm_crc32_u32(unsigned int crc, unsigned int data)
unsigned __int64 _mm_crc32_u64(unsinged __int64 crc, unsigned __int64 data)
CVTDQ2PD
__m128d _mm_cvtepi32_pd(__m128i a)
CVTDQ2PS
__m128 _mm_cvtepi32_ps(__m128i a)
CVTPD2DQ
__m128i _mm_cvtpd_epi32(__m128d a)
CVTPD2PI
__m64 _mm_cvtpd_pi32(__m128d a)
CVTPD2PS
__m128 _mm_cvtpd_ps(__m128d a)
CVTPI2PD
__m128d _mm_cvtpi32_pd(__m64 a)
CVTPI2PS
__m128 _mm_cvt_pi2ps(__m128 a, __m64 b)
__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
CVTPS2DQ
__m128i _mm_cvtps_epi32(__m128 a)
CVTPS2PD
__m128d _mm_cvtps_pd(__m128 a)
CVTPS2PI
__m64 _mm_cvt_ps2pi(__m128 a)
__m64 _mm_cvtps_pi32(__m128 a)
CVTSD2SI
int _mm_cvtsd_si32(__m128d a)
CVTSD2SS
__m128 _mm_cvtsd_ss(__m128 a, __m128d b)
CVTSI2SD
__m128d _mm_cvtsi32_sd(__m128d a, int b)
CVTSI2SS
__m128 _mm_cvt_si2ss(__m128 a, int b)
__m128 _mm_cvtsi32_ss(__m128 a, int b)
__m128 _mm_cvtsi64_ss(__m128 a, __int64 b)
CVTSS2SD
__m128d _mm_cvtss_sd(__m128d a, __m128 b)
CVTSS2SI
int _mm_cvt_ss2si(__m128 a)
int _mm_cvtss_si32(__m128 a)
C-4 Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
CVTTPD2DQ
Intrinsic
__m128i _mm_cvttpd_epi32(__m128d a)
CVTTPD2PI
__m64 _mm_cvttpd_pi32(__m128d a)
CVTTPS2DQ
__m128i _mm_cvttps_epi32(__m128 a)
CVTTPS2PI
__m64 _mm_cvtt_ps2pi(__m128 a)
__m64 _mm_cvttps_pi32(__m128 a)
CVTTSD2SI
int _mm_cvttsd_si32(__m128d a)
CVTTSS2SI
int _mm_cvtt_ss2si(__m128 a)
int _mm_cvttss_si32(__m128 a)
__m64 _mm_cvtsi32_si64(int i)
int _mm_cvtsi64_si32(__m64 m)
DIVPD
__m128d _mm_div_pd(__m128d a, __m128d b)
DIVPS
__m128 _mm_div_ps(__m128 a, __m128 b)
DIVSD
__m128d _mm_div_sd(__m128d a, __m128d b)
DIVSS
__m128 _mm_div_ss(__m128 a, __m128 b)
DPPD
__m128d _mm_dp_pd(__m128d a, __m128d b, const int mask)
DPPS
__m128 _mm_dp_ps(__m128 a, __m128 b, const int mask)
EMMS
void _mm_empty()
EXTRACTPS
int _mm_extract_ps(__m128 src, const int ndx)
HADDPD
__m128d _mm_hadd_pd(__m128d a, __m128d b)
HADDPS
__m128 _mm_hadd_ps(__m128 a, __m128 b)
HSUBPD
__m128d _mm_hsub_pd(__m128d a, __m128d b)
HSUBPS
__m128 _mm_hsub_ps(__m128 a, __m128 b)
INSERTPS
__m128 _mm_insert_ps(__m128 dst, __m128 src, const int ndx)
LDDQU
__m128i _mm_lddqu_si128(__m128i const *p)
LDMXCSR
__mm_setcsr(unsigned int i)
LFENCE
void _mm_lfence(void)
MASKMOVDQU
void _mm_maskmoveu_si128(__m128i d, __m128i n, char *p)
MASKMOVQ
void _mm_maskmove_si64(__m64 d, __m64 n, char *p)
MAXPD
__m128d _mm_max_pd(__m128d a, __m128d b)
MAXPS
__m128 _mm_max_ps(__m128 a, __m128 b)
MAXSD
__m128d _mm_max_sd(__m128d a, __m128d b)
MAXSS
__m128 _mm_max_ss(__m128 a, __m128 b)
MFENCE
void _mm_mfence(void)
MINPD
__m128d _mm_min_pd(__m128d a, __m128d b)
MINPS
__m128 _mm_min_ps(__m128 a, __m128 b)
MINSD
__m128d _mm_min_sd(__m128d a, __m128d b)
MINSS
__m128 _mm_min_ss(__m128 a, __m128 b)
MONITOR
void _mm_monitor(void const *p, unsigned extensions, unsigned hints)
MOVAPD
__m128d _mm_load_pd(double * p)
void_mm_store_pd(double *p, __m128d a)
MOVAPS
__m128 _mm_load_ps(float * p)
void_mm_store_ps(float *p, __m128 a)
Vol. 2D C-5
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
MOVD
Intrinsic
__m128i _mm_cvtsi32_si128(int a)
int _mm_cvtsi128_si32(__m128i a)
__m64 _mm_cvtsi32_si64(int a)
int _mm_cvtsi64_si32(__m64 a)
MOVDDUP
__m128d _mm_movedup_pd(__m128d a)
MOVDQA
__m128i _mm_load_si128(__m128i * p)
__m128d _mm_loaddup_pd(double const * dp)
void_mm_store_si128(__m128i *p, __m128i a)
MOVDQU
__m128i _mm_loadu_si128(__m128i * p)
void_mm_storeu_si128(__m128i *p, __m128i a)
MOVDQ2Q
__m64 _mm_movepi64_pi64(__m128i a)
MOVHLPS
__m128 _mm_movehl_ps(__m128 a, __m128 b)
MOVHPD
__m128d _mm_loadh_pd(__m128d a, double * p)
void _mm_storeh_pd(double * p, __m128d a)
MOVHPS
__m128 _mm_loadh_pi(__m128 a, __m64 * p)
void _mm_storeh_pi(__m64 * p, __m128 a)
MOVLPD
__m128d _mm_loadl_pd(__m128d a, double * p)
void _mm_storel_pd(double * p, __m128d a)
MOVLPS
__m128 _mm_loadl_pi(__m128 a, __m64 *p)
void_mm_storel_pi(__m64 * p, __m128 a)
MOVLHPS
__m128 _mm_movelh_ps(__m128 a, __m128 b)
MOVMSKPD
int _mm_movemask_pd(__m128d a)
MOVMSKPS
int _mm_movemask_ps(__m128 a)
MOVNTDQA
__m128i _mm_stream_load_si128(__m128i *p)
MOVNTDQ
void_mm_stream_si128(__m128i * p, __m128i a)
MOVNTPD
void_mm_stream_pd(double * p, __m128d a)
MOVNTPS
void_mm_stream_ps(float * p, __m128 a)
MOVNTI
void_mm_stream_si32(int * p, int a)
MOVNTQ
void_mm_stream_pi(__m64 * p, __m64 a)
MOVQ
__m128i _mm_loadl_epi64(__m128i * p)
void_mm_storel_epi64(_m128i * p, __m128i a)
__m128i _mm_move_epi64(__m128i a)
MOVQ2DQ
MOVSD
__m128i _mm_movpi64_epi64(__m64 a)
__m128d _mm_load_sd(double * p)
void_mm_store_sd(double * p, __m128d a)
__m128d _mm_move_sd(__m128d a, __m128d b)
MOVSHDUP
__m128 _mm_movehdup_ps(__m128 a)
MOVSLDUP
__m128 _mm_moveldup_ps(__m128 a)
MOVSS
__m128 _mm_load_ss(float * p)
void_mm_store_ss(float * p, __m128 a)
__m128 _mm_move_ss(__m128 a, __m128 b)
C-6 Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
MOVUPD
Intrinsic
__m128d _mm_loadu_pd(double * p)
void_mm_storeu_pd(double *p, __m128d a)
MOVUPS
__m128 _mm_loadu_ps(float * p)
void_mm_storeu_ps(float *p, __m128 a)
MPSADBW
__m128i _mm_mpsadbw_epu8(__m128i s1, __m128i s2, const int mask)
MULPD
__m128d _mm_mul_pd(__m128d a, __m128d b)
MULPS
__m128 _mm_mul_ss(__m128 a, __m128 b)
MULSD
__m128d _mm_mul_sd(__m128d a, __m128d b)
MULSS
__m128 _mm_mul_ss(__m128 a, __m128 b)
MWAIT
void _mm_mwait(unsigned extensions, unsigned hints)
ORPD
__m128d _mm_or_pd(__m128d a, __m128d b)
ORPS
__m128 _mm_or_ps(__m128 a, __m128 b)
PABSB
__m64 _mm_abs_pi8 (__m64 a)
__m128i _mm_abs_epi8 (__m128i a)
PABSD
__m64 _mm_abs_pi32 (__m64 a)
__m128i _mm_abs_epi32 (__m128i a)
PABSW
__m64 _mm_abs_pi16 (__m64 a)
PACKSSWB
__m128i _mm_packs_epi16(__m128i m1, __m128i m2)
PACKSSWB
__m64 _mm_packs_pi16(__m64 m1, __m64 m2)
PACKSSDW
__m128i _mm_packs_epi32 (__m128i m1, __m128i m2)
PACKSSDW
__m64 _mm_packs_pi32 (__m64 m1, __m64 m2)
PACKUSDW
__m128i _mm_packus_epi32(__m128i m1, __m128i m2)
PACKUSWB
__m128i _mm_packus_epi16(__m128i m1, __m128i m2)
PACKUSWB
__m64 _mm_packs_pu16(__m64 m1, __m64 m2)
__m128i _mm_abs_epi16 (__m128i a)
PADDB
__m128i _mm_add_epi8(__m128i m1, __m128i m2)
PADDB
__m64 _mm_add_pi8(__m64 m1, __m64 m2)
PADDW
__m128i _mm_add_epi16(__m128i m1, __m128i m2)
PADDW
__m64 _mm_add_pi16(__m64 m1, __m64 m2)
PADDD
__m128i _mm_add_epi32(__m128i m1, __m128i m2)
PADDD
__m64 _mm_add_pi32(__m64 m1, __m64 m2)
PADDQ
__m128i _mm_add_epi64(__m128i m1, __m128i m2)
PADDQ
__m64 _mm_add_si64(__m64 m1, __m64 m2)
PADDSB
__m128i _mm_adds_epi8(__m128i m1, __m128i m2)
PADDSB
__m64 _mm_adds_pi8(__m64 m1, __m64 m2)
PADDSW
__m128i _mm_adds_epi16(__m128i m1, __m128i m2)
PADDSW
__m64 _mm_adds_pi16(__m64 m1, __m64 m2)
PADDUSB
__m128i _mm_adds_epu8(__m128i m1, __m128i m2)
PADDUSB
__m64 _mm_adds_pu8(__m64 m1, __m64 m2)
PADDUSW
__m128i _mm_adds_epu16(__m128i m1, __m128i m2)
PADDUSW
__m64 _mm_adds_pu16(__m64 m1, __m64 m2)
Vol. 2D C-7
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PALIGNR
__m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
PAND
__m128i _mm_and_si128(__m128i m1, __m128i m2)
PAND
__m64 _mm_and_si64(__m64 m1, __m64 m2)
PANDN
__m128i _mm_andnot_si128(__m128i m1, __m128i m2)
__m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)
PANDN
__m64 _mm_andnot_si64(__m64 m1, __m64 m2)
PAUSE
void _mm_pause(void)
PAVGB
__m128i _mm_avg_epu8(__m128i a, __m128i b)
PAVGB
__m64 _mm_avg_pu8(__m64 a, __m64 b)
PAVGW
__m128i _mm_avg_epu16(__m128i a, __m128i b)
PAVGW
__m64 _mm_avg_pu16(__m64 a, __m64 b)
PBLENDVB
__m128i _mm_blendv_epi (__m128i v1, __m128i v2, __m128i mask)
PBLENDW
__m128i _mm_blend_epi16(__m128i v1, __m128i v2, const int mask)
PCLMULQDQ
__m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)
PCMPEQB
__m128i _mm_cmpeq_epi8(__m128i m1, __m128i m2)
PCMPEQB
__m64 _mm_cmpeq_pi8(__m64 m1, __m64 m2)
PCMPEQQ
__m128i _mm_cmpeq_epi64(__m128i a, __m128i b)
PCMPEQW
__m128i _mm_cmpeq_epi16 (__m128i m1, __m128i m2)
PCMPEQW
__m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)
PCMPEQD
__m128i _mm_cmpeq_epi32(__m128i m1, __m128i m2)
PCMPEQD
__m64 _mm_cmpeq_pi32(__m64 m1, __m64 m2)
PCMPESTRI
int _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode)
PCMPESTRM
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode)
PCMPGTB
__m128i _mm_cmpgt_epi8 (__m128i m1, __m128i m2)
PCMPGTB
__m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
PCMPGTW
__m128i _mm_cmpgt_epi16(__m128i m1, __m128i m2)
PCMPGTW
__m64 _mm_cmpgt_pi16 (__m64 m1, __m64 m2)
PCMPGTD
__m128i _mm_cmpgt_epi32(__m128i m1, __m128i m2)
PCMPGTD
__m64 _mm_cmpgt_pi32(__m64 m1, __m64 m2)
PCMPISTRI
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
C-8 Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPISTRM
__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode)
int _mm_cmpistra (__m128i a, __m128i b, const int mode)
int _mm_cmpistrc (__m128i a, __m128i b, const int mode)
int _mm_cmpistro (__m128i a, __m128i b, const int mode)
int _mm_cmpistrs (__m128i a, __m128i b, const int mode)
int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPGTQ
__m128i _mm_cmpgt_epi64(__m128i a, __m128i b)
PEXTRB
int _mm_extract_epi8 (__m128i src, const int ndx)
PEXTRD
int _mm_extract_epi32 (__m128i src, const int ndx)
PEXTRQ
__int64 _mm_extract_epi64 (__m128i src, const int ndx)
PEXTRW
int _mm_extract_epi16(__m128i a, int n)
PEXTRW
int _mm_extract_pi16(__m64 a, int n)
int _mm_extract_epi16 (__m128i src, int ndx)
PHADDD
__m64 _mm_hadd_pi32 (__m64 a, __m64 b)
__m128i _mm_hadd_epi32 (__m128i a, __m128i b)
PHADDSW
__m64 _mm_hadds_pi16 (__m64 a, __m64 b)
__m128i _mm_hadds_epi16 (__m128i a, __m128i b)
PHADDW
__m64 _mm_hadd_pi16 (__m64 a, __m64 b)
__m128i _mm_hadd_epi16 (__m128i a, __m128i b)
PHMINPOSUW
__m128i _mm_minpos_epu16( __m128i packed_words)
PHSUBD
__m64 _mm_hsub_pi32 (__m64 a, __m64 b)
__m128i _mm_hsub_epi32 (__m128i a, __m128i b)
PHSUBSW
__m64 _mm_hsubs_pi16 (__m64 a, __m64 b)
__m128i _mm_hsubs_epi16 (__m128i a, __m128i b)
PHSUBW
__m64 _mm_hsub_pi16 (__m64 a, __m64 b)
PINSRB
__m128i _mm_insert_epi8(__m128i s1, int s2, const int ndx)
PINSRD
__m128i _mm_insert_epi32(__m128i s2, int s, const int ndx)
PINSRQ
__m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx)
__m128i _mm_hsub_epi16 (__m128i a, __m128i b)
PINSRW
__m128i _mm_insert_epi16(__m128i a, int d, int n)
PINSRW
__m64 _mm_insert_pi16(__m64 a, int d, int n)
PMADDUBSW
__m64 _mm_maddubs_pi16 (__m64 a, __m64 b)
__m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
PMADDWD
__m128i _mm_madd_epi16(__m128i m1 __m128i m2)
PMADDWD
__m64 _mm_madd_pi16(__m64 m1, __m64 m2)
PMAXSB
__m128i _mm_max_epi8( __m128i a, __m128i b)
PMAXSD
__m128i _mm_max_epi32( __m128i a, __m128i b)
Vol. 2D C-9
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
PMAXSW
Intrinsic
__m128i _mm_max_epi16(__m128i a, __m128i b)
PMAXSW
__m64 _mm_max_pi16(__m64 a, __m64 b)
PMAXUB
__m128i _mm_max_epu8(__m128i a, __m128i b)
PMAXUB
__m64 _mm_max_pu8(__m64 a, __m64 b)
PMAXUD
__m128i _mm_max_epu32( __m128i a, __m128i b)
PMAXUW
__m128i _mm_max_epu16( __m128i a, __m128i b)
PMINSB
_m128i _mm_min_epi8( __m128i a, __m128i b)
PMINSD
__m128i _mm_min_epi32( __m128i a, __m128i b)
PMINSW
__m128i _mm_min_epi16(__m128i a, __m128i b)
PMINSW
__m64 _mm_min_pi16(__m64 a, __m64 b)
PMINUB
__m128i _mm_min_epu8(__m128i a, __m128i b)
PMINUB
__m64 _mm_min_pu8(__m64 a, __m64 b)
PMINUD
__m128i _mm_min_epu32 ( __m128i a, __m128i b)
PMINUW
__m128i _mm_min_epu16 ( __m128i a, __m128i b)
PMOVMSKB
int _mm_movemask_epi8(__m128i a)
PMOVMSKB
int _mm_movemask_pi8(__m64 a)
PMOVSXBW
__m128i _mm_ cvtepi8_epi16( __m128i a)
PMOVSXBD
__m128i _mm_ cvtepi8_epi32( __m128i a)
PMOVSXBQ
__m128i _mm_ cvtepi8_epi64( __m128i a)
PMOVSXWD
__m128i _mm_ cvtepi16_epi32( __m128i a)
PMOVSXWQ
__m128i _mm_ cvtepi16_epi64( __m128i a)
PMOVSXDQ
__m128i _mm_ cvtepi32_epi64( __m128i a)
PMOVZXBW
__m128i _mm_ cvtepu8_epi16( __m128i a)
PMOVZXBD
__m128i _mm_ cvtepu8_epi32( __m128i a)
PMOVZXBQ
__m128i _mm_ cvtepu8_epi64( __m128i a)
PMOVZXWD
__m128i _mm_ cvtepu16_epi32( __m128i a)
PMOVZXWQ
__m128i _mm_ cvtepu16_epi64( __m128i a)
PMOVZXDQ
__m128i _mm_ cvtepu32_epi64( __m128i a)
PMULDQ
__m128i _mm_mul_epi32( __m128i a, __m128i b)
PMULHRSW
__m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)
__m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
PMULHUW
__m128i _mm_mulhi_epu16(__m128i a, __m128i b)
PMULHUW
__m64 _mm_mulhi_pu16(__m64 a, __m64 b)
PMULHW
__m128i _mm_mulhi_epi16(__m128i m1, __m128i m2)
PMULHW
__m64 _mm_mulhi_pi16(__m64 m1, __m64 m2)
PMULLUD
__m128i _mm_mullo_epi32(__m128i a, __m128i b)
PMULLW
__m128i _mm_mullo_epi16(__m128i m1, __m128i m2)
PMULLW
__m64 _mm_mullo_pi16(__m64 m1, __m64 m2)
PMULUDQ
__m64 _mm_mul_su32(__m64 m1, __m64 m2)
__m128i _mm_mul_epu32(__m128i m1, __m128i m2)
C-10 Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
POPCNT
Intrinsic
int _mm_popcnt_u32(unsigned int a)
int64_t _mm_popcnt_u64(unsigned __int64 a)
POR
__m64 _mm_or_si64(__m64 m1, __m64 m2)
POR
__m128i _mm_or_si128(__m128i m1, __m128i m2)
PREFETCHh
void _mm_prefetch(char *a, int sel)
PSADBW
__m128i _mm_sad_epu8(__m128i a, __m128i b)
PSADBW
__m64 _mm_sad_pu8(__m64 a, __m64 b)
PSHUFB
__m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
__m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
PSHUFD
__m128i _mm_shuffle_epi32(__m128i a, int n)
PSHUFHW
__m128i _mm_shufflehi_epi16(__m128i a, int n)
PSHUFLW
__m128i _mm_shufflelo_epi16(__m128i a, int n)
PSHUFW
__m64 _mm_shuffle_pi16(__m64 a, int n)
PSIGNB
__m64 _mm_sign_pi8 (__m64 a, __m64 b)
__m128i _mm_sign_epi8 (__m128i a, __m128i b)
PSIGND
__m64 _mm_sign_pi32 (__m64 a, __m64 b)
__m128i _mm_sign_epi32 (__m128i a, __m128i b)
PSIGNW
__m64 _mm_sign_pi16 (__m64 a, __m64 b)
__m128i _mm_sign_epi16 (__m128i a, __m128i b)
PSLLW
__m128i _mm_sll_epi16(__m128i m, __m128i count)
PSLLW
__m128i _mm_slli_epi16(__m128i m, int count)
PSLLW
__m64 _mm_sll_pi16(__m64 m, __m64 count)
__m64 _mm_slli_pi16(__m64 m, int count)
PSLLD
__m128i _mm_slli_epi32(__m128i m, int count)
__m128i _mm_sll_epi32(__m128i m, __m128i count)
PSLLD
__m64 _mm_slli_pi32(__m64 m, int count)
__m64 _mm_sll_pi32(__m64 m, __m64 count)
PSLLQ
__m64 _mm_sll_si64(__m64 m, __m64 count)
__m64 _mm_slli_si64(__m64 m, int count)
PSLLQ
__m128i _mm_sll_epi64(__m128i m, __m128i count)
__m128i _mm_slli_epi64(__m128i m, int count)
PSLLDQ
__m128i _mm_slli_si128(__m128i m, int imm)
PSRAW
__m128i _mm_sra_epi16(__m128i m, __m128i count)
__m128i _mm_srai_epi16(__m128i m, int count)
PSRAW
__m64 _mm_sra_pi16(__m64 m, __m64 count)
__m64 _mm_srai_pi16(__m64 m, int count)
PSRAD
__m128i _mm_sra_epi32 (__m128i m, __m128i count)
__m128i _mm_srai_epi32 (__m128i m, int count)
PSRAD
__m64 _mm_sra_pi32 (__m64 m, __m64 count)
__m64 _mm_srai_pi32 (__m64 m, int count)
PSRLW
_m128i _mm_srl_epi16 (__m128i m, __m128i count)
Vol. 2D C-11
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
__m128i _mm_srli_epi16 (__m128i m, int count)
__m64 _mm_srl_pi16 (__m64 m, __m64 count)
__m64 _mm_srli_pi16(__m64 m, int count)
PSRLD
__m128i _mm_srl_epi32 (__m128i m, __m128i count)
__m128i _mm_srli_epi32 (__m128i m, int count)
PSRLD
__m64 _mm_srl_pi32 (__m64 m, __m64 count)
__m64 _mm_srli_pi32 (__m64 m, int count)
PSRLQ
__m128i _mm_srl_epi64 (__m128i m, __m128i count)
__m128i _mm_srli_epi64 (__m128i m, int count)
PSRLQ
__m64 _mm_srl_si64 (__m64 m, __m64 count)
__m64 _mm_srli_si64 (__m64 m, int count)
PSRLDQ
__m128i _mm_srli_si128(__m128i m, int imm)
PSUBB
__m128i _mm_sub_epi8(__m128i m1, __m128i m2)
PSUBB
__m64 _mm_sub_pi8(__m64 m1, __m64 m2)
PSUBW
__m128i _mm_sub_epi16(__m128i m1, __m128i m2)
PSUBW
__m64 _mm_sub_pi16(__m64 m1, __m64 m2)
PSUBD
__m128i _mm_sub_epi32(__m128i m1, __m128i m2)
PSUBD
__m64 _mm_sub_pi32(__m64 m1, __m64 m2)
PSUBQ
__m128i _mm_sub_epi64(__m128i m1, __m128i m2)
PSUBQ
__m64 _mm_sub_si64(__m64 m1, __m64 m2)
PSUBSB
__m128i _mm_subs_epi8(__m128i m1, __m128i m2)
PSUBSB
__m64 _mm_subs_pi8(__m64 m1, __m64 m2)
PSUBSW
__m128i _mm_subs_epi16(__m128i m1, __m128i m2)
PSUBSW
__m64 _mm_subs_pi16(__m64 m1, __m64 m2)
PSUBUSB
__m128i _mm_subs_epu8(__m128i m1, __m128i m2)
PSUBUSB
__m64 _mm_subs_pu8(__m64 m1, __m64 m2)
PSUBUSW
__m128i _mm_subs_epu16(__m128i m1, __m128i m2)
PSUBUSW
__m64 _mm_subs_pu16(__m64 m1, __m64 m2)
PTEST
int _mm_testz_si128(__m128i s1, __m128i s2)
int _mm_testc_si128(__m128i s1, __m128i s2)
int _mm_testnzc_si128(__m128i s1, __m128i s2)
PUNPCKHBW
__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)
PUNPCKHBW
__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)
PUNPCKHWD
__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)
PUNPCKHWD
__m128i _mm_unpackhi_epi16(__m128i m1, __m128i m2)
PUNPCKHDQ
___m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)
PUNPCKHDQ
__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)
PUNPCKHQDQ
__m128i _mm_unpackhi_epi64(__m128i m1, __m128i m2)
PUNPCKLBW
__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)
PUNPCKLBW
__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)
PUNPCKLWD
__m64 _mm_unpacklo_pi16(__m64 m1, __m64 m2)
C-12 Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PUNPCKLWD
__m128i _mm_unpacklo_epi16(__m128i m1, __m128i m2)
PUNPCKLDQ
__m64 _mm_unpacklo_pi32(__m64 m1, __m64 m2)
PUNPCKLDQ
__m128i _mm_unpacklo_epi32(__m128i m1, __m128i m2)
PUNPCKLQDQ
__m128i _mm_unpacklo_epi64(__m128i m1, __m128i m2)
PXOR
__m64 _mm_xor_si64(__m64 m1, __m64 m2)
PXOR
__m128i _mm_xor_si128(__m128i m1, __m128i m2)
RCPPS
__m128 _mm_rcp_ps(__m128 a)
RCPSS
__m128 _mm_rcp_ss(__m128 a)
ROUNDPD
__m128 mm_round_pd(__m128d s1, int iRoundMode)
__m128 mm_floor_pd(__m128d s1)
__m128 mm_ceil_pd(__m128d s1)
ROUNDPS
__m128 mm_round_ps(__m128 s1, int iRoundMode)
__m128 mm_floor_ps(__m128 s1)
__m128 mm_ceil_ps(__m128 s1)
ROUNDSD
__m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode)
__m128d mm_floor_sd(__m128d dst, __m128d s1)
__m128d mm_ceil_sd(__m128d dst, __m128d s1)
ROUNDSS
__m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode)
__m128 mm_floor_ss(__m128 dst, __m128 s1)
__m128 mm_ceil_ss(__m128 dst, __m128 s1)
RSQRTPS
__m128 _mm_rsqrt_ps(__m128 a)
RSQRTSS
__m128 _mm_rsqrt_ss(__m128 a)
SFENCE
void_mm_sfence(void)
SHUFPD
__m128d _mm_shuffle_pd(__m128d a, __m128d b, unsigned int imm8)
SHUFPS
__m128 _mm_shuffle_ps(__m128 a, __m128 b, unsigned int imm8)
SQRTPD
__m128d _mm_sqrt_pd(__m128d a)
SQRTPS
__m128 _mm_sqrt_ps(__m128 a)
SQRTSD
__m128d _mm_sqrt_sd(__m128d a)
SQRTSS
__m128 _mm_sqrt_ss(__m128 a)
STMXCSR
_mm_getcsr(void)
SUBPD
__m128d _mm_sub_pd(__m128d a, __m128d b)
SUBPS
__m128 _mm_sub_ps(__m128 a, __m128 b)
SUBSD
__m128d _mm_sub_sd(__m128d a, __m128d b)
SUBSS
__m128 _mm_sub_ss(__m128 a, __m128 b)
UCOMISD
int _mm_ucomieq_sd(__m128d a, __m128d b)
int _mm_ucomilt_sd(__m128d a, __m128d b)
int _mm_ucomile_sd(__m128d a, __m128d b)
int _mm_ucomigt_sd(__m128d a, __m128d b)
int _mm_ucomige_sd(__m128d a, __m128d b)
int _mm_ucomineq_sd(__m128d a, __m128d b)
UCOMISS
int _mm_ucomieq_ss(__m128 a, __m128 b)
Vol. 2D C-13
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
int _mm_ucomilt_ss(__m128 a, __m128 b)
int _mm_ucomile_ss(__m128 a, __m128 b)
int _mm_ucomigt_ss(__m128 a, __m128 b)
int _mm_ucomige_ss(__m128 a, __m128 b)
int _mm_ucomineq_ss(__m128 a, __m128 b)
UNPCKHPD
__m128d _mm_unpackhi_pd(__m128d a, __m128d b)
UNPCKHPS
__m128 _mm_unpackhi_ps(__m128 a, __m128 b)
UNPCKLPD
__m128d _mm_unpacklo_pd(__m128d a, __m128d b)
UNPCKLPS
__m128 _mm_unpacklo_ps(__m128 a, __m128 b)
XORPD
__m128d _mm_xor_pd(__m128d a, __m128d b)
XORPS
__m128 _mm_xor_ps(__m128 a, __m128 b)
C.2
COMPOSITE INTRINSICS
Table C-2. Composite Intrinsics
Mnemonic
Intrinsic
(composite)
__m128i _mm_set_epi64(__m64 q1, __m64 q0)
(composite)
__m128i _mm_set_epi32(int i3, int i2, int i1, int i0)
(composite)
__m128i _mm_set_epi16(short w7,short w6, short w5, short w4, short w3, short w2,
short w1,short w0)
(composite)
__m128i _mm_set_epi8(char w15,char w14, char w13, char w12, char w11, char w10,
char w9, char w8, char w7,char w6, char w5, char w4, char w3, char w2,char w1, char w0)
(composite)
__m128i _mm_set1_epi64(__m64 q)
(composite)
__m128i _mm_set1_epi32(int a)
(composite)
__m128i _mm_set1_epi16(short a)
(composite)
__m128i _mm_set1_epi8(char a)
(composite)
__m128i _mm_setr_epi64(__m64 q1, __m64 q0)
(composite)
__m128i _mm_setr_epi32(int i3, int i2, int i1, int i0)
(composite)
__m128i _mm_setr_epi16(short w7,short w6, short w5, short w4, short w3, short w2, short w,
short w0)
(composite)
__m128i _mm_setr_epi8(char w15,char w14, char w13, char w12, char w11, char w10,
char w9, char w8,char w7, char w6,char w5, char w4, char w3, char w2,char w1,char w0)
(composite)
__m128i _mm_setzero_si128()
(composite)
__m128 _mm_set_ps1(float w)
__m128 _mm_set1_ps(float w)
(composite)
__m128cmm_set1_pd(double w)
(composite)
__m128d _mm_set_sd(double w)
(composite)
__m128d _mm_set_pd(double z, double y)
(composite)
__m128 _mm_set_ps(float z, float y, float x, float w)
(composite)
__m128d _mm_setr_pd(double z, double y)
(composite)
__m128 _mm_setr_ps(float z, float y, float x, float w)
(composite)
__m128d _mm_setzero_pd(void)
(composite)
__m128 _mm_setzero_ps(void)
C-14 Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-2. Composite Intrinsics (Contd.)
Mnemonic
Intrinsic
MOVSD + shuffle
__m128d _mm_load_pd(double * p)
__m128d _mm_load1_pd(double *p)
MOVSS + shuffle
__m128 _mm_load_ps1(float * p)
__m128 _mm_load1_ps(float *p)
MOVAPD + shuffle __m128d _mm_loadr_pd(double * p)
MOVAPS + shuffle __m128 _mm_loadr_ps(float * p)
MOVSD + shuffle
void _mm_store1_pd(double *p, __m128d a)
MOVSS + shuffle
void _mm_store_ps1(float * p, __m128 a)
void _mm_store1_ps(float *p, __m128 a)
MOVAPD + shuffle _mm_storer_pd(double * p, __m128d a)
MOVAPS + shuffle _mm_storer_ps(float * p, __m128 a)
Vol. 2D C-15
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
C-16 Vol. 2D
Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3 (3A, 3B, 3C & 3D):
System Programming Guide
NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of three volumes:
Basic Architecture, Order Number 253665; Instruction Set Reference A-Z, Order Number 325383;
System Programming Guide, Order Number 325384. Refer to all three volumes when evaluating your
design needs.
Order Number: 325384-060US
September 2016
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Copyright © 1997-2016, Intel Corporation. All Rights Reserved.
CONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.4
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1-3
1-6
1-6
1-6
1-7
1-7
1-7
1-8
1-9
1-9
CHAPTER 2
SYSTEM ARCHITECTURE OVERVIEW
2.1
2.1.1
2.1.1.1
2.1.2
2.1.2.1
2.1.3
2.1.3.1
2.1.4
2.1.4.1
2.1.5
2.1.5.1
2.1.6
2.1.6.1
2.1.7
2.2
2.2.1
2.3
2.3.1
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.5
2.5.1
2.6
2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.6.1
2.8.7
2.8.7.1
2.8.8
OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Global and Local Descriptor Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Global and Local Descriptor Tables in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
System Segments, Segment Descriptors, and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Gates in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Task-State Segments and Task Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Task-State Segments in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Interrupt and Exception Handling IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Memory Management in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
System Registers in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Other System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Extended Feature Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
System Flags and Fields in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
MEMORY-MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Global Descriptor Table Register (GDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Local Descriptor Table Register (LDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
IDTR Interrupt Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Task Register (TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
CPUID Qualification of Control Register Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
EXTENDED CONTROL REGISTERS (INCLUDING XCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
PROTECTION KEY RIGHTS REGISTER (PKRU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
SYSTEM INSTRUCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Loading and Storing System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Verifying of Access Privileges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Loading and Storing Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Invalidating Caches and TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Controlling the Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Reading Performance-Monitoring and Time-Stamp Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Reading Counters in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Reading and Writing Model-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Reading and Writing Model-Specific Registers in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Enabling Processor Extended States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Vol. 3A iii
CONTENTS
PAGE
CHAPTER 3
PROTECTED-MODE MEMORY MANAGEMENT
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.3.1
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.5.1
3.5
3.5.1
3.5.2
MEMORY MANAGEMENT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
USING SEGMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Basic Flat Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Protected Flat Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Multi-Segment Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Segmentation in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Paging and Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PHYSICAL ADDRESS SPACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Intel® 64 Processors and Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
LOGICAL AND LINEAR ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Logical Address Translation in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Segment Selectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Segment Loading Instructions in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Segment Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Code- and Data-Segment Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
SYSTEM DESCRIPTOR TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Segment Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Segment Descriptor Tables in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
CHAPTER 4
PAGING
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.3
4.4
4.4.1
4.4.2
4.5
4.6
4.6.1
4.6.2
4.7
4.8
4.9
4.9.1
4.9.2
4.9.3
4.10
4.10.1
4.10.2
4.10.2.1
4.10.2.2
4.10.2.3
4.10.2.4
4.10.3
4.10.3.1
4.10.3.2
4.10.3.3
4.10.4
4.10.4.1
4.10.4.2
4.10.4.3
4.10.4.4
4.10.5
4.11
4.11.1
PAGING MODES AND CONTROL BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Three Paging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Paging-Mode Enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Paging-Mode Modifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Enumeration of Paging Features by CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
32-BIT PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
PAE PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
PDPTE Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Linear-Address Translation with PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
IA-32E PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
ACCESS RIGHTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Determination of Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Protection Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
PAGE-FAULT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
ACCESSED AND DIRTY FLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
PAGING AND MEMORY TYPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors) . . . . . . . . . . . . . . 4-34
Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families). . . . . . . . . . 4-34
Caching Paging-Related Information about Memory Typing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
CACHING TRANSLATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Process-Context Identifiers (PCIDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Translation Lookaside Buffers (TLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Page Numbers, Page Frames, and Page Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Caching Translations in TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Details of TLB Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Global Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Paging-Structure Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Caches for Paging Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Using the Paging-Structure Caches to Translate Linear Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Multiple Cached Entries for a Single Paging-Structure Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Invalidation of TLBs and Paging-Structure Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Operations that Invalidate TLBs and Paging-Structure Caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Recommended Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
Optional Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
Delayed Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
Propagation of Paging-Structure Changes to Multiple Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
VMX Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
iv Vol. 3A
CONTENTS
PAGE
4.11.2
4.12
4.13
VMX Support for Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
USING PAGING FOR VIRTUAL MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47
MAPPING SEGMENTS TO PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47
CHAPTER 5
PROTECTION
5.1
5.2
5.2.1
5.3
5.3.1
5.4
5.4.1
5.4.1.1
5.5
5.6
5.6.1
5.7
5.8
5.8.1
5.8.1.1
5.8.1.2
5.8.2
5.8.3
5.8.3.1
5.8.4
5.8.5
5.8.5.1
5.8.6
5.8.7
5.8.7.1
5.8.8
5.9
5.10
5.10.1
5.10.2
5.10.3
5.10.4
5.10.5
5.11
5.11.1
5.11.2
5.11.3
5.11.4
5.11.5
5.12
5.13
5.13.1
5.13.2
5.13.3
5.13.4
ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Code-Segment Descriptor in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
LIMIT CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Limit Checking in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
TYPE CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Null Segment Selector Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
NULL Segment Checking in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
PRIVILEGE LEVELS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Accessing Data in Code Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS . . . . . . . . . . . . . . . . 5-10
Direct Calls or Jumps to Code Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Accessing Nonconforming Code Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Accessing Conforming Code Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
IA-32e Mode Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Accessing a Code Segment Through a Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Stack Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Stack Switching in 64-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Returning from a Called Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions . . . . . . . . . . . . . . . . . . . . . . . 5-20
SYSENTER and SYSEXIT Instructions in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Fast System Calls in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
PRIVILEGED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
POINTER VALIDATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Checking Access Rights (LAR Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Checking Read/Write Rights (VERR and VERW Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Checking That the Pointer Offset Is Within Limits (LSL Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Checking Caller Access Privileges (ARPL Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Checking Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
PAGE-LEVEL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Page-Protection Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Restricting Addressable Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Page Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Combining Protection of Both Levels of Page Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Overrides to Page Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
COMBINING PAGE AND SEGMENT PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Detecting and Enabling the Execute-Disable Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Execute-Disable Page Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Reserved Bit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
CHAPTER 6
INTERRUPT AND EXCEPTION HANDLING
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.4
6.4.1
INTERRUPT AND EXCEPTION OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXCEPTION AND INTERRUPT VECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOURCES OF INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maskable Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software-Generated Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOURCES OF EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program-Error Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-1
6-2
6-2
6-3
6-4
6-4
6-4
Vol. 3A v
CONTENTS
PAGE
6.4.2
6.4.3
6.5
6.6
6.7
6.7.1
6.8
6.8.1
6.8.2
6.8.3
6.9
6.10
6.11
6.12
6.12.1
6.12.1.1
6.12.1.2
6.12.2
6.13
6.14
6.14.1
6.14.2
6.14.3
6.14.4
6.14.5
6.15
Software-Generated Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Machine-Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
EXCEPTION CLASSIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
PROGRAM OR TASK RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
NONMASKABLE INTERRUPT (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Handling Multiple NMIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
ENABLING AND DISABLING INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Masking Maskable Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Masking Instruction Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Masking Exceptions and Interrupts When Switching Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
INTERRUPT DESCRIPTOR TABLE (IDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
IDT DESCRIPTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
EXCEPTION AND INTERRUPT HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Exception- or Interrupt-Handler Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Protection of Exception- and Interrupt-Handler Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Flag Usage By Exception- or Interrupt-Handler Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Interrupt Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
ERROR CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
64-Bit Mode IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
64-Bit Mode Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
IRET in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Stack Switching in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Interrupt Stack Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
EXCEPTION AND INTERRUPT REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Interrupt 0—Divide Error Exception (#DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Interrupt 1—Debug Exception (#DB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Interrupt 2—NMI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Interrupt 3—Breakpoint Exception (#BP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Interrupt 4—Overflow Exception (#OF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Interrupt 5—BOUND Range Exceeded Exception (#BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Interrupt 6—Invalid Opcode Exception (#UD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Interrupt 7—Device Not Available Exception (#NM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Interrupt 8—Double Fault Exception (#DF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Interrupt 9—Coprocessor Segment Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
Interrupt 10—Invalid TSS Exception (#TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Interrupt 11—Segment Not Present (#NP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
Interrupt 12—Stack Fault Exception (#SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
Interrupt 13—General Protection Exception (#GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
Interrupt 14—Page-Fault Exception (#PF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
Interrupt 16—x87 FPU Floating-Point Error (#MF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43
Interrupt 17—Alignment Check Exception (#AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
Interrupt 18—Machine-Check Exception (#MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
Interrupt 19—SIMD Floating-Point Exception (#XM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Interrupt 20—Virtualization Exception (#VE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
Interrupts 32 to 255—User Defined Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51
CHAPTER 7
TASK MANAGEMENT
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
TASK MANAGEMENT OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Task Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Task State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Executing a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TASK MANAGEMENT DATA STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Task-State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSS Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSS Descriptor in 64-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Task-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TASK SWITCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi Vol. 3A
7-1
7-1
7-2
7-2
7-3
7-3
7-5
7-6
7-7
7-8
7-9
CONTENTS
PAGE
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.6
7.7
TASK LINKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Use of Busy Flag To Prevent Recursive Task Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Modifying Task Linkages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
TASK ADDRESS SPACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Mapping Tasks to the Linear and Physical Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Task Logical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
16-BIT TASK-STATE SEGMENT (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
TASK MANAGEMENT IN 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
CHAPTER 8
MULTIPLE-PROCESSOR MANAGEMENT
8.1
8.1.1
8.1.2
8.1.2.1
8.1.2.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.3
8.2.3.1
8.2.3.2
8.2.3.3
8.2.3.4
8.2.3.5
8.2.3.6
8.2.3.7
8.2.3.8
8.2.3.9
8.2.4
8.2.4.1
8.2.4.2
8.2.5
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.4.1
8.4.4.2
8.4.5
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.7.7
8.7.8
8.7.9
8.7.10
8.7.11
8.7.12
8.7.13
LOCKED ATOMIC OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Guaranteed Atomic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Bus Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Automatic Locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Software Controlled Bus Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Handling Self- and Cross-Modifying Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Effects of a LOCK Operation on Internal Processor Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
MEMORY ORDERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Memory Ordering in the Intel® Pentium® and Intel486™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Memory Ordering in P6 and More Recent Processor Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Examples Illustrating the Memory-Ordering Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Assumptions, Terminology, and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Neither Loads Nor Stores Are Reordered with Like Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Stores Are Not Reordered With Earlier Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Loads May Be Reordered with Earlier Stores to Different Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Intra-Processor Forwarding Is Allowed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Stores Are Transitively Visible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Stores Are Seen in a Consistent Order by Other Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Locked Instructions Have a Total Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Loads and Stores Are Not Reordered with Locked Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Fast-String Operation and Out-of-Order Stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Memory-Ordering Model for String Operations on Write-Back (WB) Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Examples Illustrating Memory-Ordering Principles for String Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Strengthening or Weakening the Memory-Ordering Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
SERIALIZING INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
MULTIPLE-PROCESSOR (MP) INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
BSP and AP Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
MP Initialization Protocol Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
MP Initialization Protocol Algorithm for MP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
MP Initialization Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Typical BSP Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Typical AP Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
Identifying Logical Processors in an MP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
INTEL® HYPER-THREADING TECHNOLOGY AND INTEL® MULTI-CORE TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Initializing Processors Supporting Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Initializing Multi-Core Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Executing Multiple Threads on an Intel® 64 or IA-32 Processor Supporting Hardware Multi-Threading . . . . . . . . . . . . 8-26
Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
INTEL® HYPER-THREADING TECHNOLOGY ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
State of the Logical Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
APIC Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Memory Type Range Registers (MTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Page Attribute Table (PAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Machine Check Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Debug Registers and Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Performance Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
IA32_MISC_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Memory Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Serializing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Microcode Update Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Self Modifying Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
Implementation-Specific Intel HT Technology Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
Vol. 3A vii
CONTENTS
PAGE
8.7.13.1
8.7.13.2
8.7.13.3
8.7.13.4
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.9
8.9.1
8.9.2
8.9.3
8.9.3.1
8.9.4
8.9.5
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
8.10.6
8.10.6.1
8.10.6.2
8.10.6.3
8.10.6.4
8.10.6.5
8.10.6.6
8.10.6.7
8.11
8.11.1
8.11.2
8.11.2.1
Processor Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
Processor Translation Lookaside Buffers (TLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
Thermal Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
External Signal Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
MULTI-CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
Logical Processor Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
Memory Type Range Registers (MTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
Performance Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
IA32_MISC_ENABLE MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
Microcode Update Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS . . . . . . . . . . . . . . . . . . . . . 8-33
Hierarchical Mapping of Shared Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
Hierarchical Mapping of CPUID Extended Topology Leaf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Hierarchical ID of Logical Processors in an MP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
Hierarchical ID of Logical Processors with x2APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37
Algorithm for Three-Level Mappings of APIC_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37
Identifying Topological Relationships in a MP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42
MANAGEMENT OF IDLE AND BLOCKED CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
HLT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
PAUSE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
Detecting Support MONITOR/MWAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
MONITOR/MWAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47
Monitor/Mwait Address Range Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48
Required Operating System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48
Use the PAUSE Instruction in Spin-Wait Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49
Potential Usage of MONITOR/MWAIT in C0 Idle Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49
Halt Idle Logical Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-50
Potential Usage of MONITOR/MWAIT in C1 Idle Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-51
Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources . . . . . . . . . . . . . . . . . . . . . . . . . 8-51
Eliminate Execution-Based Timing Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52
Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52
MP INITIALIZATION FOR P6 FAMILY PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52
Overview of the MP Initialization Process For P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52
MP Initialization Protocol Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53
Error Detection and Handling During the MP Initialization Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-54
CHAPTER 9
PROCESSOR MANAGEMENT AND INITIALIZATION
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.2
9.2.1
9.2.2
9.3
9.4
9.5
9.6
9.7
9.7.1
9.7.2
9.8
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.5.1
9.8.5.2
9.8.5.3
9.8.5.4
9.9
INITIALIZATION OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Processor State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Processor Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Model and Stepping Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
First Instruction Executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
X87 FPU INITIALIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Configuring the x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Setting the Processor for x87 FPU Software Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
CACHE ENABLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
MODEL-SPECIFIC REGISTERS (MSRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
MEMORY TYPE RANGE REGISTERS (MTRRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
INITIALIZING SSE/SSE2/SSE3/SSSE3 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Real-Address Mode IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
NMI Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Protected-Mode System Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Initializing Protected-Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Initializing Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Initializing Multitasking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Initializing IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
IA-32e Mode System Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
IA-32e Mode Interrupts and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
64-bit Mode and Compatibility Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Switching Out of IA-32e Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
MODE SWITCHING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
viii Vol. 3A
CONTENTS
PAGE
9.9.1
Switching to Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.9.2
Switching Back to Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.10
INITIALIZATION AND MODE SWITCHING EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.10.1
Assembler Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.10.2
STARTUP.ASM Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.10.3
MAIN.ASM Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9.10.4
Supporting Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9.11
MICROCODE UPDATE FACILITIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
9.11.1
Microcode Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.11.2
Optional Extended Signature Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.11.3
Processor Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9.11.4
Platform Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9.11.5
Microcode Update Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
9.11.6
Microcode Update Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
9.11.6.1
Hard Resets in Update Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.11.6.2
Update in a Multiprocessor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.11.6.3
Update in a System Supporting Intel Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.11.6.4
Update in a System Supporting Dual-Core Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.11.6.5
Update Loader Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.11.7
Update Signature and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.11.7.1
Determining the Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.11.7.2
Authenticating the Update. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.11.8
Optional Processor Microcode Update Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.11.8.1
Responsibilities of the BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38
9.11.8.2
Responsibilities of the Calling Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9.11.8.3
Microcode Update Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
9.11.8.4
INT 15H-based Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
9.11.8.5
Function 00H—Presence Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
9.11.8.6
Function 01H—Write Microcode Update Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43
9.11.8.7
Function 02H—Microcode Update Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46
9.11.8.8
Function 03H—Read Microcode Update Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
9.11.8.9
Return Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
CHAPTER 10
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.1
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.7.1
10.4.7.2
10.4.7.3
10.4.7.4
10.4.8
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.5.4.1
10.5.5
10.6
10.6.1
10.6.2
10.6.2.1
10.6.2.2
10.6.2.3
LOCAL AND I/O APIC OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
SYSTEM BUS VS. APIC BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
THE INTEL® 82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE X2APIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
LOCAL APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
The Local APIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Presence of the Local APIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Enabling or Disabling the Local APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Local APIC Status and Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Relocating the Local APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Local APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Local APIC State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Local APIC State After Power-Up or Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Local APIC State After It Has Been Software Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Local APIC State After an INIT Reset (“Wait-for-SIPI” State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Local APIC State After It Receives an INIT-Deassert IPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Local APIC Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
HANDLING LOCAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Local Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Valid Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
APIC Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
TSC-Deadline Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
Local Interrupt Acceptance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
ISSUING INTERPROCESSOR INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
Interrupt Command Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
Determining IPI Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
Physical Destination Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
Logical Destination Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
Broadcast/Self Delivery Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
Vol. 3A ix
CONTENTS
PAGE
10.6.2.4
Lowest Priority Delivery Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-24
10.6.3
IPI Delivery and Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-25
10.7
SYSTEM AND APIC BUS ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.8
HANDLING INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.8.1
Interrupt Handling with the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-26
10.8.2
Interrupt Handling with the P6 Family and Pentium Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-27
10.8.3
Interrupt, Task, and Processor Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28
10.8.3.1
Task and Processor Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28
10.8.4
Interrupt Acceptance for Fixed Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-29
10.8.5
Signaling Interrupt Servicing Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-30
10.8.6
Task Priority in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-31
10.8.6.1
Interaction of Task Priorities between CR8 and APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-31
10.9
SPURIOUS INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.10 APIC BUS MESSAGE PASSING MECHANISM AND PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS) . . . . . . . . . . . . . . . . . . . 10-32
10.10.1
Bus Message Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-33
10.11 MESSAGE SIGNALLED INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.11.1
Message Address Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-34
10.11.2
Message Data Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35
10.12 EXTENDED XAPIC (X2APIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36
10.12.1
Detecting and Enabling x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-36
10.12.1.1
Instructions to Access APIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-37
10.12.1.2
x2APIC Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-37
10.12.1.3
Reserved Bit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-39
10.12.2
x2APIC Register Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-40
10.12.3
MSR Access in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-40
10.12.4
VM-Exit Controls for MSRs and x2APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-40
10.12.5
x2APIC State Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-41
10.12.5.1
x2APIC States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-41
x2APIC After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
x2APIC Transitions From x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
x2APIC Transitions From Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-43
State Changes From xAPIC Mode to x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-43
10.12.6
Routing of Device Interrupts in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-43
10.12.7
Initialization by System Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-43
10.12.8
CPUID Extensions And Topology Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-43
10.12.8.1
Consistency of APIC IDs and CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-44
10.12.9
ICR Operation in x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-44
10.12.10 Determining IPI Destination in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-45
10.12.10.1
Logical Destination Mode in x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-45
10.12.10.2
Deriving Logical x2APIC ID from the Local x2APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-46
10.12.11 SELF IPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47
10.13 APIC BUS MESSAGE FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
10.13.1
Bus Message Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47
10.13.2
EOI Message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47
10.13.2.1
Short Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-48
10.13.2.2
Non-focused Lowest Priority Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-49
10.13.2.3
APIC Bus Status Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-50
CHAPTER 11
MEMORY CACHE CONTROL
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.4
11.5
11.5.1
11.5.2
11.5.2.1
11.5.2.2
11.5.2.3
x Vol. 3A
INTERNAL CACHES, TLBS, AND BUFFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
CACHING TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
METHODS OF CACHING AVAILABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Buffering of Write Combining Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
Choosing a Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Code Fetches in Uncacheable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
CACHE CONTROL PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
CACHE CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Cache Control Registers and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10
Precedence of Cache Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13
Selecting Memory Types for Pentium Pro and Pentium II Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14
Selecting Memory Types for Pentium III and More Recent Processor Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15
Writing Values Across Pages with Different Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16
CONTENTS
PAGE
11.5.3
Preventing Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.4
Disabling and Enabling the L3 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.5.5
Cache Management Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.5.6
L1 Data Cache Context Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.5.6.1
Adaptive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.5.6.2
Shared Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.6
SELF-MODIFYING CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.7
IMPLICIT CACHING (PENTIUM 4, INTEL XEON, AND P6 FAMILY PROCESSORS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.8
EXPLICIT CACHING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.9
INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.10 STORE BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.11 MEMORY TYPE RANGE REGISTERS (MTRRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.11.1
MTRR Feature Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
11.11.2
Setting Memory Ranges with MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
11.11.2.1
IA32_MTRR_DEF_TYPE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
11.11.2.2
Fixed Range MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
11.11.2.3
Variable Range MTRRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
11.11.2.4
System-Management Range Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.11.3
Example Base and Mask Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
11.11.3.1
Base and Mask Calculations for Greater-Than 36-bit Physical Address Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
11.11.4
Range Size and Alignment Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28
11.11.4.1
MTRR Precedences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28
11.11.5
MTRR Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
11.11.6
Remapping Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
11.11.7
MTRR Maintenance Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
11.11.7.1
MemTypeGet() Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
11.11.7.2
MemTypeSet() Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
11.11.8
MTRR Considerations in MP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
11.11.9
Large Page Size Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
11.12 PAGE ATTRIBUTE TABLE (PAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
11.12.1
Detecting Support for the PAT Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
11.12.2
IA32_PAT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
11.12.3
Selecting a Memory Type from the PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
11.12.4
Programming the PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
11.12.5
PAT Compatibility with Earlier IA-32 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36
CHAPTER 12
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
12.1
12.2
12.2.1
12.3
12.4
12.5
12.5.1
12.6
EMULATION OF THE MMX INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
THE MMX STATE AND MMX REGISTER ALIASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR
Instructions on the x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
SAVING AND RESTORING THE MMX STATE AND REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
SAVING MMX STATE ON TASK OR CONTEXT SWITCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Effect of MMX Instructions on Pending x87 Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
DEBUGGING MMX CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
CHAPTER 13
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED
STATES
13.1
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.5.1
13.2
13.3
13.4
13.4.1
PROVIDING OPERATING SYSTEM SUPPORT FOR SSE EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Adding Support to an Operating System for SSE Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Checking for CPU Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Initialization of the SSE Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE Instructions. . . . . . . . . . . . . . . . . . . . . 13-4
Providing a Handler for the SIMD Floating-Point Exception (#XM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Numeric Error flag and IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
EMULATION OF SSE EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
SAVING AND RESTORING SSE STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
DESIGNING OS FACILITIES FOR SAVING X87 FPU, SSE AND EXTENDED STATES ON TASK OR CONTEXT SWITCHES . . . . . 13-6
Using the TS Flag to Control the Saving of the x87 FPU and SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Vol. 3A xi
CONTENTS
PAGE
13.5
13.5.1
13.5.2
13.5.3
13.5.4
13.5.5
13.6
13.7
13.8
13.8.1
13.8.2
THE XSAVE FEATURE SET AND PROCESSOR EXTENDED STATE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Checking the Support for XSAVE Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Determining the XSAVE Managed Feature States And The Required Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Enable the Use Of XSAVE Feature Set And XSAVE State Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Provide an Initialization for the XSAVE State Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Providing the Required Exception Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
INTEROPERABILITY OF THE XSAVE FEATURE SET AND FXSAVE/FXRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
THE XSAVE FEATURE SET AND PROCESSOR SUPERVISOR STATE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
SYSTEM PROGRAMMING FOR XSAVE MANAGED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Intel® Advanced Vector Extensions (Intel® AVX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11
CHAPTER 14
POWER AND THERMAL MANAGEMENT
14.1
14.1.1
14.2
14.3
14.3.1
14.3.2
14.3.2.1
14.3.2.2
14.3.2.3
14.3.3
14.3.4
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.5.1
14.4.6
14.4.7
14.5
14.5.1
14.5.2
14.5.3
14.5.4
14.5.4.1
14.5.4.2
14.5.5
14.6
14.7
14.7.1
14.7.2
14.7.2.1
14.7.2.2
14.7.2.3
14.7.2.4
14.7.2.5
14.7.2.6
14.7.3
14.7.3.1
14.7.4
14.7.4.1
14.7.5
14.7.5.1
14.7.5.2
14.7.6
14.8
14.8.1
14.9
14.9.1
ENHANCED INTEL SPEEDSTEP® TECHNOLOGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Software Interface For Initiating Performance State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
P-STATE HARDWARE COORDINATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
SYSTEM SOFTWARE CONSIDERATIONS AND OPPORTUNISTIC PROCESSOR PERFORMANCE OPERATION . . . . . . . . . . . . . . 14-3
Intel Dynamic Acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
System Software Interfaces for Opportunistic Processor Performance Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Discover Hardware Support and Enabling of Opportunistic Processor Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
OS Control of Opportunistic Processor Performance Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Required Changes to OS Power Management P-state Policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Intel Turbo Boost Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Performance and Energy Bias Hint support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
HARDWARE-CONTROLLED PERFORMANCE STATES (HWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
HWP Programming Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Enabling HWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
HWP Performance Range and Dynamic Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Managing HWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
HWP Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Non-Architectural HWP Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-11
HWP Notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-11
Recommendations for OS use of HWP Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-12
HARDWARE DUTY CYCLING (HDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Hardware Duty Cycling Programming Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-13
Package level Enabling HDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14
Logical-Processor Level HDC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14
HDC Residency Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-15
IA32_THREAD_STALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-15
Non-Architectural HDC Residency Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-16
MPERF and APERF Counters Under HDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-18
MWAIT EXTENSIONS FOR ADVANCED POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
THERMAL MONITORING AND PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Catastrophic Shutdown Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-20
Thermal Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-20
Thermal Monitor 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-20
Thermal Monitor 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-20
Two Methods for Enabling TM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-20
Performance State Transitions and Thermal Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-21
Thermal Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-21
Adaptive Thermal Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-22
Software Controlled Clock Modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-23
Extension of Software Controlled Clock Modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-24
Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-24
Detection of Software Controlled Clock Modulation Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-24
On Die Digital Thermal Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-24
Digital Thermal Sensor Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-25
Reading the Digital Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-25
Power Limit Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-28
PACKAGE LEVEL THERMAL MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
Support for Passive and Active cooling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-30
PLATFORM SPECIFIC POWER MANAGEMENT SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
RAPL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-31
xii Vol. 3A
CONTENTS
PAGE
14.9.2
14.9.3
14.9.4
14.9.5
RAPL Domains and Platform Specificity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
Package RAPL Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
PP0/PP1 RAPL Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
DRAM RAPL Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
CHAPTER 15
MACHINE-CHECK ARCHITECTURE
15.1
MACHINE-CHECK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2
COMPATIBILITY WITH PENTIUM PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.3
MACHINE-CHECK MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.3.1
Machine-Check Global Control MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.3.1.1
IA32_MCG_CAP MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.3.1.2
IA32_MCG_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3.1.3
IA32_MCG_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3.1.4
IA32_MCG_EXT_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.1.5
Enabling Local Machine Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.2
Error-Reporting Register Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.2.1
IA32_MCi_CTL MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.2.2
IA32_MCi_STATUS MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.3.2.3
IA32_MCi_ADDR MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.3.2.4
IA32_MCi_MISC MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.3.2.5
IA32_MCi_CTL2 MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.3.2.6
IA32_MCG Extended Machine Check State MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.3.3
Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture . . . . . . . . . . . . . . . . . . . . . 15-12
15.4
ENHANCED CACHE ERROR REPORTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.5
CORRECTED MACHINE CHECK ERROR INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.5.1
CMCI Local APIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.5.2
System Software Recommendation for Managing CMCI and Machine Check Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.5.2.1
CMCI Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.5.2.2
CMCI Threshold Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.5.2.3
CMCI Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.6
RECOVERY OF UNCORRECTED RECOVERABLE (UCR) ERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.6.1
Detection of Software Error Recovery Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.6.2
UCR Error Reporting and Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.6.3
UCR Error Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.6.4
UCR Error Overwrite Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.7
MACHINE-CHECK AVAILABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.8
MACHINE-CHECK INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.9
INTERPRETING THE MCA ERROR CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
15.9.1
Simple Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
15.9.2
Compound Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
15.9.2.1
Correction Report Filtering (F) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.9.2.2
Transaction Type (TT) Sub-Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.9.2.3
Level (LL) Sub-Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.9.2.4
Request (RRRR) Sub-Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
15.9.2.5
Bus and Interconnect Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
15.9.2.6
Memory Controller Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
15.9.3
Architecturally Defined UCR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
15.9.3.1
Architecturally Defined SRAO Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
15.9.3.2
Architecturally Defined SRAR Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
15.9.4
Multiple MCA Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26
15.9.5
Machine-Check Error Codes Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26
15.10 GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26
15.10.1
Machine-Check Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27
15.10.2
Pentium Processor Machine-Check Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28
15.10.3
Logging Correctable Machine-Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28
15.10.4
Machine-Check Software Handler Guidelines for Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30
15.10.4.1
Machine-Check Exception Handler for Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30
15.10.4.2
Corrected Machine-Check Handler for Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34
Vol. 3A xiii
CONTENTS
PAGE
CHAPTER 16
INTERPRETING MACHINE-CHECK ERROR CODES
16.1
16.2
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 06H MACHINE ERROR CODES FOR MACHINE CHECK . . . 16-1
INCREMENTAL DECODING INFORMATION: INTEL CORE 2 PROCESSOR FAMILY MACHINE ERROR CODES FOR MACHINE
CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.2.1
Model-Specific Machine Check Error Codes for Intel Xeon Processor 7400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.2.1.1
Processor Machine Check Status Register Incremental MCA Error Code Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.2.2
Intel Xeon Processor 7400 Model Specific Error Code Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.2.2.1
Processor Model Specific Error Code Field Type B: Bus and Interconnect Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.2.2.2
Processor Model Specific Error Code Field Type C: Cache Bus Controller Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.3
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_1AH, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.3.1
Intel QPI Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.3.2
Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.3.3
Memory Controller Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.4
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_2DH, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.4.1
Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-10
16.4.2
Intel QPI Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-11
16.4.3
Integrated Memory Controller Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-11
16.5
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_3EH, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.5.1
Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-13
16.5.2
Integrated Memory Controller Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-14
16.6
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_3FH, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.6.1
Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-16
16.6.2
Intel QPI Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-17
16.6.3
Integrated Memory Controller Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-17
16.7
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_56H, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
16.7.1
Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-19
16.7.2
Integrated Memory Controller Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-20
16.8
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_4FH, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.8.1
Integrated Memory Controller Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-21
16.8.2
Home Agent Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
16.9
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_55H, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.9.1
Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
16.9.2
Interconnect Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-24
16.9.3
Integrated Memory Controller Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-25
16.9.4
M2M Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-26
16.9.5
Home Agent Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-27
16.10 INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_5FH, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.10.1
Integrated Memory Controller Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-28
16.11 INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 0FH MACHINE ERROR CODES FOR MACHINE CHECK . . 16-29
16.11.1
Model-Specific Machine Check Error Codes for Intel Xeon Processor MP 7100 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-29
16.11.1.1
Processor Machine Check Status Register MCA Error Code Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-30
16.11.2
Other_Info Field (all MCA Error Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-31
16.11.3
Processor Model Specific Error Code Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-32
16.11.3.1
MCA Error Type A: L3 Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-32
16.11.3.2
Processor Model Specific Error Code Field Type B: Bus and Interconnect Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-32
16.11.3.3
Processor Model Specific Error Code Field Type C: Cache Bus Controller Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-33
CHAPTER 17
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.1
17.2
17.2.1
17.2.2
17.2.3
OVERVIEW OF DEBUG SUPPORT FACILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
DEBUG REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
Debug Address Registers (DR0-DR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Debug Registers DR4 and DR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Debug Status Register (DR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
xiv Vol. 3A
CONTENTS
PAGE
17.2.4
17.2.5
17.2.6
17.3
17.3.1
17.3.1.1
17.3.1.2
17.3.1.3
17.3.1.4
17.3.1.5
17.3.2
17.3.3
17.4
17.4.1
17.4.2
17.4.3
17.4.4
17.4.4.1
17.4.5
17.4.6
17.4.7
17.4.8
17.4.8.1
17.4.8.2
17.4.8.3
17.4.9
17.4.9.1
17.4.9.2
17.4.9.3
17.4.9.4
17.4.9.5
17.5
17.5.1
17.5.2
17.6
17.7
17.7.1
17.7.2
17.8
17.9
17.9.1
17.10
17.10.1
17.10.2
17.10.3
17.11
17.11.1
17.11.2
17.11.3
17.12
17.13
17.14
17.14.1
17.14.2
17.14.3
17.15
17.15.1
17.15.2
Debug Control Register (DR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Breakpoint Field Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
Debug Registers and Intel® 64 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
DEBUG EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Debug Exception (#DB)—Interrupt Vector 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
Instruction-Breakpoint Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
Data Memory and I/O Breakpoint Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
General-Detect Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Single-Step Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Task-Switch Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
Breakpoint Exception (#BP)—Interrupt Vector 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory (RTM) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
IA32_DEBUGCTL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
Monitoring Branches, Exceptions, and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
Single-Stepping on Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
Branch Trace Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
Branch Trace Message Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
Branch Trace Store (BTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
CPL-Qualified Branch Trace Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
Freezing LBR and Performance Counters on PMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
LBR Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
LBR Stack and Intel® 64 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
LBR Stack and IA-32 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
Last Exception Records and Intel 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
BTS and DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
64 Bit Format of the DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
Setting Up the DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
Setting Up the BTS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
Setting Up CPL-Qualified BTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
Writing the DS Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ 2 DUO AND INTEL® ATOM™ PROCESSORS) . 17-25
LBR Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25
LBR Stack in Intel Atom Processors based on the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON GOLDMONT
MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON INTEL® MICROARCHITECTURE CODE
NAME NEHALEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27
LBR Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28
Filtering of Last Branch Records. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON INTEL® MICROARCHITECTURE CODE
NAME SANDY BRIDGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON HASWELL
MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29
LBR Stack Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON SKYLAKE
MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31
MSR_LBR_INFO_x MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31
Streamlined Freeze_LBRs_On_PMI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32
LBR Behavior and Deep C-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PROCESSORS BASED ON INTEL NETBURST®
MICROARCHITECTURE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32
MSR_DEBUGCTLA MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33
LBR Stack for Processors Based on Intel NetBurst® Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34
Last Exception Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ SOLO AND INTEL® CORE™ DUO
PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PENTIUM M PROCESSORS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (P6 FAMILY PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38
DEBUGCTLMSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38
Last Branch and Last Exception MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39
Monitoring Branches, Exceptions, and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39
TIME-STAMP COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40
Invariant TSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41
IA32_TSC_AUX Register and RDTSCP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41
Vol. 3A xv
CONTENTS
PAGE
17.15.3
Time-Stamp Counter Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-42
17.15.4
Invariant Time-Keeping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-42
17.16 INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) MONITORING FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42
17.16.1
Overview of Cache Monitoring Technology and Memory Bandwidth Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-43
17.16.2
Enabling Monitoring: Usage Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-43
17.16.3
Enumeration and Detecting Support of Cache Monitoring Technology and Memory Bandwidth Monitoring . . . . . . . . .17-44
17.16.4
Monitoring Resource Type and Capability Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-44
17.16.5
Feature-Specific Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-45
17.16.5.1
Cache Monitoring Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-46
17.16.5.2
Memory Bandwidth Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-46
17.16.6
Monitoring Resource RMID Association. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-46
17.16.7
Monitoring Resource Selection and Reporting Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-47
17.16.8
Monitoring Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-48
17.16.8.1
Monitoring Dynamic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-49
17.16.8.2
Monitoring Operation With Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-49
17.16.8.3
Monitoring Operation with Other Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-49
17.16.8.4
Monitoring Operation with RAS Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-49
17.17 INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-49
17.17.1
Cache Allocation Technology Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-50
17.17.2
Code and Data Prioritization (CDP) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-53
17.17.3
Enabling Cache Allocation Technology Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-54
17.17.3.1
Enumeration and Detection Support of Cache Allocation Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-54
17.17.3.2
Cache Allocation Technology: Resource Type and Capability Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-55
17.17.3.3
Cache Allocation Technology: Cache Mask Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-57
17.17.3.4
Class of Service to Cache Mask Association: Common Across Allocation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-58
17.17.4
Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-58
17.17.4.1
Mapping Between L3 CDP Masks and CAT Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-59
17.17.4.2
L3 CAT: Disabling CDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-59
17.17.5
Cache Allocation Technology Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-59
17.17.5.1
Cache Allocation Technology Dynamic Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-59
17.17.5.2
Cache Allocation Technology Operation With Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-60
17.17.5.3
Cache Allocation Technology Operation with Other Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-60
17.17.5.4
Associating Threads with CAT/CDP Classes of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-61
CHAPTER 18
PERFORMANCE MONITORING
18.1
18.2
18.2.1
18.2.1.1
18.2.1.2
18.2.2
18.2.3
18.2.3.1
18.2.4
18.2.4.1
18.2.4.2
18.2.4.3
18.2.5
18.3
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.4.1
18.4.4.2
18.4.4.3
18.4.4.4
18.5
18.6
18.6.1
18.6.1.1
18.6.2
PERFORMANCE MONITORING OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
ARCHITECTURAL PERFORMANCE MONITORING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
Architectural Performance Monitoring Version 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
Architectural Performance Monitoring Version 1 Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Pre-defined Architectural Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Architectural Performance Monitoring Version 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
Architectural Performance Monitoring Version 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
AnyThread Counting and Software Evolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-11
Architectural Performance Monitoring Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-12
Enhancement in IA32_PERF_GLOBAL_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-12
IA32_PERF_GLOBAL_STATUS_RESET and IA32_PERF_GLOBAL_STATUS_SET MSRS. . . . . . . . . . . . . . . . . . . . . . . . . .18-13
IA32_PERF_GLOBAL_INUSE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-14
Full-Width Writes to Performance Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-15
PERFORMANCE MONITORING (INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . 18-16
PERFORMANCE MONITORING (PROCESSORS BASED ON INTEL® CORE™ MICROARCHITECTURE). . . . . . . . . . . . . . . . . . . . 18-17
Fixed-function Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-18
Global Counter Control Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-19
At-Retirement Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-21
Processor Event Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-21
Setting up the PEBS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-22
PEBS Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-22
Writing a PEBS Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-22
Re-configuring PEBS Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-23
PERFORMANCE MONITORING (45 NM AND 32 NM INTEL® ATOM™ PROCESSORS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24
PERFORMANCE MONITORING FOR SILVERMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24
Enhancements of Performance Monitoring in the Processor Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-24
Processor Event Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-25
Offcore Response Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-26
xvi Vol. 3A
CONTENTS
PAGE
18.6.3
Average Offcore Request Latency Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29
18.7
PERFORMANCE MONITORING FOR GOLDMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29
18.7.1
Processor Event Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-31
18.7.1.1
PEBS Data Linear Address Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33
18.7.1.2
Reduced Skid PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33
18.7.1.3
Enhancements to IA32_PERF_GLOBAL_STATUS.OvfDSBuffer[62] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33
18.7.2
Offcore Response Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33
18.7.3
Average Offcore Request Latency Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35
18.8
PERFORMANCE MONITORING FOR PROCESSORS BASED ON INTEL® MICROARCHITECTURE CODE NAME NEHALEM. . 18-35
18.8.1
Enhancements of Performance Monitoring in the Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36
18.8.1.1
Processor Event Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36
18.8.1.2
Load Latency Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-40
18.8.1.3
Off-core Response Performance Monitoring in the Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42
18.8.2
Performance Monitoring Facility in the Uncore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43
18.8.2.1
Uncore Performance Monitoring Management Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43
18.8.2.2
Uncore Performance Event Configuration Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46
18.8.2.3
Uncore Address/Opcode Match MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47
18.8.3
Intel® Xeon® Processor 7500 Series Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-48
18.8.4
Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Westmere . . . . . . . . . . . . . . . 18-50
18.8.5
Intel® Xeon® Processor E7 Family Performance Monitoring Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50
18.9
PERFORMANCE MONITORING FOR PROCESSORS BASED ON INTEL® MICROARCHITECTURE CODE NAME SANDY
BRIDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51
18.9.1
Global Counter Control Facilities In Intel® Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-52
18.9.2
Counter Coalescence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54
18.9.3
Full Width Writes to Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54
18.9.4
PEBS Support in Intel® Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54
18.9.4.1
PEBS Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-55
18.9.4.2
Load Latency Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56
18.9.4.3
Precise Store Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-57
18.9.4.4
Precise Distribution of Instructions Retired (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58
18.9.5
Off-core Response Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58
18.9.6
Uncore Performance Monitoring Facilities In Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx
Processor Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61
18.9.6.1
Uncore Performance Monitoring Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63
18.9.7
Intel® Xeon® Processor E5 Family Performance Monitoring Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63
18.9.8
Intel® Xeon® Processor E5 Family Uncore Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-64
18.10 3RD GENERATION INTEL® CORE™ PROCESSOR PERFORMANCE MONITORING FACILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-64
18.10.1
Intel® Xeon® Processor E5 v2 and E7 v2 Family Uncore Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . 18-64
18.11 4TH GENERATION INTEL® CORE™ PROCESSOR PERFORMANCE MONITORING FACILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-65
18.11.1
Processor Event Based Sampling (PEBS) Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66
18.11.2
PEBS Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66
18.11.3
PEBS Data Address Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-67
18.11.3.1
EventingIP Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-68
18.11.4
Off-core Response Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-68
18.11.4.1
Off-core Response Performance Monitoring in Intel Xeon Processors E5 v3 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70
18.11.5
Performance Monitoring and Intel® TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70
18.11.5.1
Intel TSX and PEBS Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71
18.11.6
Uncore Performance Monitoring Facilities in the 4th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . 18-72
18.11.7
Intel® Xeon® Processor E5 v3 Family Uncore Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-73
18.12 5TH GENERATION INTEL® CORE™ PROCESSOR AND INTEL® CORE™ M PROCESSOR PERFORMANCE MONITORING
FACILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-73
18.13 6TH GENERATION INTEL® CORE™ PROCESSOR AND 7TH GENERATION INTEL® CORE™ PROCESSOR PERFORMANCE
MONITORING FACILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-74
18.13.1
Processor Event Based Sampling (PEBS) Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-75
18.13.1.1
PEBS Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-76
18.13.1.2
PEBS Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-77
18.13.1.3
Data Address Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78
18.13.1.4
PEBS Facility for Front End Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-79
18.13.1.5
FRONTEND_RETIRED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80
18.13.2
Off-core Response Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80
®
18.14 INTEL XEON PHI™ PROCESSOR 7200/5200/3200 PERFORMANCE MONITORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-82
18.15 PERFORMANCE MONITORING (PROCESSORS BASED ON INTEL NETBURST® MICROARCHITECTURE) . . . . . . . . . . . . . . . . 18-83
18.15.1
ESCR MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-86
18.15.2
Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-87
18.15.3
CCCR MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-88
Vol. 3A xvii
CONTENTS
PAGE
18.15.4
Debug Store (DS) Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-90
18.15.5
Programming the Performance Counters for Non-Retirement Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-90
18.15.5.1
Selecting Events to Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-90
18.15.5.2
Filtering Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-92
18.15.5.3
Starting Event Counting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-93
18.15.5.4
Reading a Performance Counter’s Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-93
18.15.5.5
Halting Event Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-93
18.15.5.6
Cascading Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-94
18.15.5.7
EXTENDED CASCADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-95
18.15.5.8
Generating an Interrupt on Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-96
18.15.5.9
Counter Usage Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-96
18.15.6
At-Retirement Counting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-96
18.15.6.1
Using At-Retirement Counting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-97
18.15.6.2
Tagging Mechanism for Front_end_event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-98
18.15.6.3
Tagging Mechanism For Execution_event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-98
18.15.6.4
Tagging Mechanism for Replay_event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-98
18.15.7
Processor Event-Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-99
18.15.7.1
Detection of the Availability of the PEBS Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-99
18.15.7.2
Setting Up the DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-99
18.15.7.3
Setting Up the PEBS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-99
18.15.7.4
Writing a PEBS Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-99
18.15.7.5
Other DS Mechanism Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-100
18.15.8
Operating System Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-100
18.16 PERFORMANCE MONITORING AND INTEL HYPER-THREADING TECHNOLOGY IN PROCESSORS BASED ON INTEL
NETBURST® MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-100
18.16.1
ESCR MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-100
18.16.2
CCCR MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-101
18.16.3
IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-103
18.16.4
Performance Monitoring Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-103
18.17 COUNTING CLOCKS ON SYSTEMS WITH INTEL HYPER-THREADING TECHNOLOGY IN PROCESSORS BASED ON INTEL
NETBURST® MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-104
18.17.1
Non-Halted Clockticks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-104
18.17.2
Non-Sleep Clockticks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-104
18.18 COUNTING CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-105
18.18.1
Non-Halted Reference Clockticks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-106
18.18.2
Cycle Counting and Opportunistic Processor Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-106
18.18.3
Determining the Processor Base Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-106
18.18.3.1
For Intel® Processors Based on Microarchitecture Code Name Sandy Bridge, Ivy Bridge, Haswell and Broadwell18-107
18.18.3.2
For Intel® Processors Based on Microarchitecture Code Name Nehalem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-107
18.18.3.3
For Intel® Atom™ Processors Based on the Silvermont Microarchitecture (Including Intel Processors Based on Airmont
Microarchitecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-107
18.18.3.4
For Intel® Core™ 2 Processor Family and for Intel® Xeon® Processors Based on Intel Core Microarchitecture . . . 18-107
18.19 IA32_PERF_CAPABILITIES MSR ENUMERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-107
18.19.1
Filtering of SMM Handler Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-108
18.20 PERFORMANCE MONITORING AND DUAL-CORE TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-108
18.21 PERFORMANCE MONITORING ON 64-BIT INTEL XEON PROCESSOR MP WITH UP TO 8-MBYTE L3 CACHE. . . . . . . . . . . . 18-109
18.22 PERFORMANCE MONITORING ON L3 AND CACHING BUS CONTROLLER SUB-SYSTEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-111
18.22.1
Overview of Performance Monitoring with L3/Caching Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-113
18.22.2
GBSQ Event Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-114
18.22.3
GSNPQ Event Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-115
18.22.4
FSB Event Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-116
18.22.4.1
FSB Sub-Event Mask Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-116
18.22.5
Common Event Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-117
18.23 PERFORMANCE MONITORING (P6 FAMILY PROCESSOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-117
18.23.1
PerfEvtSel0 and PerfEvtSel1 MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-118
18.23.2
PerfCtr0 and PerfCtr1 MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-119
18.23.3
Starting and Stopping the Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-119
18.23.4
Event and Time-Stamp Monitoring Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-120
18.23.5
Monitoring Counter Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-120
18.24 PERFORMANCE MONITORING (PENTIUM PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-120
18.24.1
Control and Event Select Register (CESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-121
18.24.2
Use of the Performance-Monitoring Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-122
18.24.3
Events Counted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-122
xviii Vol. 3A
CONTENTS
PAGE
CHAPTER 19
PERFORMANCE-MONITORING EVENTS
19.1
19.2
ARCHITECTURAL PERFORMANCE-MONITORING EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
PERFORMANCE MONITORING EVENTS FOR 6TH GENERATION INTEL® CORE™ PROCESSOR AND 7TH GENERATION INTEL®
CORE™ PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3
PERFORMANCE MONITORING EVENTS FOR THE INTEL® CORE™ M AND 5TH GENERATION INTEL® CORE™
PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
19.4
PERFORMANCE MONITORING EVENTS FOR THE 4TH GENERATION INTEL® CORE™ PROCESSORS. . . . . . . . . . . . . . . . . . 19-21
19.4.1
Performance Monitoring Events in the Processor Core of Intel Xeon Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . 19-33
19.5
PERFORMANCE MONITORING EVENTS FOR 3RD GENERATION INTEL® CORE™ PROCESSORS . . . . . . . . . . . . . . . . . . . . . . 19-34
19.5.1
Performance Monitoring Events in the Processor Core of Intel Xeon Processor E5 v2 Family and Intel Xeon Processor
E7 v2 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-42
19.6
PERFORMANCE MONITORING EVENTS FOR 2ND GENERATION INTEL® CORE™ I7-2XXX, INTEL® CORE™ I5-2XXX,
INTEL® CORE™ I3-2XXX PROCESSOR SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-43
19.7
PERFORMANCE MONITORING EVENTS FOR INTEL® CORE™ I7 PROCESSOR FAMILY AND INTEL® XEON® PROCESSOR
FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-57
19.8
PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON INTEL® MICROARCHITECTURE CODE NAME
WESTMERE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-86
19.9
PERFORMANCE MONITORING EVENTS FOR INTEL® XEON® PROCESSOR 5200, 5400 SERIES AND INTEL® CORE™2
EXTREME PROCESSORS QX 9000 SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-117
19.10 PERFORMANCE MONITORING EVENTS FOR INTEL® XEON® PROCESSOR 3000, 3200, 5100, 5300 SERIES AND
INTEL® CORE™2 DUO PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-118
19.11 PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON THE GOLDMONT MICROARCHITECTURE . . . . . . . 19-143
19.12 PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON THE SILVERMONT MICROARCHITECTURE . . . . . 19-149
19.12.1
Performance Monitoring Events for Processors Based on the Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . 19-153
19.13 PERFORMANCE MONITORING EVENTS FOR 45 NM AND 32 NM INTEL® ATOM™ PROCESSORS . . . . . . . . . . . . . . . . . . . . 19-154
19.14 PERFORMANCE MONITORING EVENTS FOR INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS . . . . . . . 19-168
19.15 PENTIUM® 4 AND INTEL® XEON® PROCESSOR PERFORMANCE-MONITORING EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-173
19.16 PERFORMANCE MONITORING EVENTS FOR INTEL® PENTIUM® M PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-202
19.17 P6 FAMILY PROCESSOR PERFORMANCE-MONITORING EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-204
19.18 PENTIUM PROCESSOR PERFORMANCE-MONITORING EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-213
CHAPTER 20
8086 EMULATION
20.1
REAL-ADDRESS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.1
Address Translation in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.1.2
Registers Supported in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.1.3
Instructions Supported in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.1.4
Interrupt and Exception Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2
VIRTUAL-8086 MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.2.1
Enabling Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.2.2
Structure of a Virtual-8086 Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.2.3
Paging of Virtual-8086 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.2.4
Protection within a Virtual-8086 Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.2.5
Entering Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.2.6
Leaving Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
20.2.7
Sensitive Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
20.2.8
Virtual-8086 Mode I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
20.2.8.1
I/O-Port-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.2.8.2
Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.2.8.3
Special I/O Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.3
INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.3.1
Class 1—Hardware Interrupt and Exception Handling in Virtual-8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.3.1.1
Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate. . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.3.1.2
Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler . . . . . . . . . . . . . . . . . . . . 20-14
20.3.1.3
Handling an Interrupt or Exception Through a Task Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14
20.3.2
Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism . . . . . 20-15
20.3.3
Class 3—Software Interrupt Handling in Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16
20.3.3.1
Method 1: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18
20.3.3.2
Methods 2 and 3: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18
20.3.3.3
Method 4: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
20.3.3.4
Method 5: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
20.3.3.5
Method 6: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
Vol. 3A xix
CONTENTS
PAGE
20.4
PROTECTED-MODE VIRTUAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20
CHAPTER 21
MIXING 16-BIT AND 32-BIT CODE
21.1
21.2
21.3
21.4
21.4.1
21.4.2
21.4.2.1
21.4.2.2
21.4.3
21.4.4
21.4.5
DEFINING 16-BIT AND 32-BIT PROGRAM MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
MIXING 16-BIT AND 32-BIT OPERATIONS WITHIN A CODE SEGMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
TRANSFERRING CONTROL AMONG MIXED-SIZE CODE SEGMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Code-Segment Pointer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
Stack Management for Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
Controlling the Operand-Size Attribute For a Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
Passing Parameters With a Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
Interrupt Control Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
Parameter Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
Writing Interface Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
CHAPTER 22
ARCHITECTURE COMPATIBILITY
22.1
PROCESSOR FAMILIES AND CATEGORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.2
RESERVED BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.3
ENABLING NEW FUNCTIONS AND MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.4
DETECTING THE PRESENCE OF NEW FEATURES THROUGH SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.5
INTEL MMX TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.6
STREAMING SIMD EXTENSIONS (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.7
STREAMING SIMD EXTENSIONS 2 (SSE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.8
STREAMING SIMD EXTENSIONS 3 (SSE3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.9
ADDITIONAL STREAMING SIMD EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.10 INTEL HYPER-THREADING TECHNOLOGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.11 MULTI-CORE TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.12 SPECIFIC FEATURES OF DUAL-CORE PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.13 NEW INSTRUCTIONS IN THE PENTIUM AND LATER IA-32 PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.13.1
Instructions Added Prior to the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.14 OBSOLETE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.15 UNDEFINED OPCODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.16 NEW FLAGS IN THE EFLAGS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.16.1
Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.17 STACK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.17.1
PUSH SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.17.2
EFLAGS Pushed on the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.18 X87 FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.18.1
Control Register CR0 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.18.2
x87 FPU Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.18.2.1
Condition Code Flags (C0 through C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.18.2.2
Stack Fault Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.18.3
x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.18.4
x87 FPU Tag Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.18.5
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.18.5.1
NaNs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.18.5.2
Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.18.6
Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.18.6.1
Denormal Operand Exception (#D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.18.6.2
Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.18.6.3
Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-10
22.18.6.4
Exception Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-10
22.18.6.5
CS and EIP For FPU Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-10
22.18.6.6
FPU Error Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-10
22.18.6.7
Assertion of the FERR# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-10
22.18.6.8
Invalid Operation Exception On Denormals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-11
22.18.6.9
Alignment Check Exceptions (#AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-11
22.18.6.10
Segment Not Present Exception During FLDENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-11
22.18.6.11
Device Not Available Exception (#NM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-11
22.18.6.12
Coprocessor Segment Overrun Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-11
xx Vol. 3A
CONTENTS
PAGE
22.18.6.13
General Protection Exception (#GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.18.6.14
Floating-Point Error Exception (#MF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.18.7
Changes to Floating-Point Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.18.7.1
FDIV, FPREM, and FSQRT Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.2
FSCALE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.3
FPREM1 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.4
FPREM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.5
FUCOM, FUCOMP, and FUCOMPP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.6
FPTAN Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.7
Stack Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.8
FSIN, FCOS, and FSINCOS Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.18.7.9
FPATAN Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.18.7.10
F2XM1 Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.18.7.11
FLD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.18.7.12
FXTRACT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.18.7.13
Load Constant Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.18.7.14
FSETPM Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.18.7.15
FXAM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.18.7.16
FSAVE and FSTENV Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.18.8
Transcendental Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.18.9
Obsolete Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.18.10 WAIT/FWAIT Prefix Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.18.11 Operands Split Across Segments and/or Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.18.12 FPU Instruction Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.19 SERIALIZING INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.20 FPU AND MATH COPROCESSOR INITIALIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.20.1
Intel® 387 and Intel® 287 Math Coprocessor Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.20.2
Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.21 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16
22.22 MEMORY MANAGEMENT FACILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.22.1
New Memory Management Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.22.1.1
Physical Memory Addressing Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.22.1.2
Global Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.22.1.3
Larger Page Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.22.2
CD and NW Cache Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.22.3
Descriptor Types and Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.22.4
Changes in Segment Descriptor Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.23 DEBUG FACILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.23.1
Differences in Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.23.2
Differences in Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.23.3
Debug Registers DR4 and DR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.24 RECOGNITION OF BREAKPOINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.25 EXCEPTIONS AND/OR EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20
22.25.1
Machine-Check Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.25.2
Priority of Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.25.3
Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.26 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.26.1
Interrupt Propagation Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.26.2
NMI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.26.3
IDT Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.27 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.27.1
Software Visible Differences Between the Local APIC and the 82489DX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.27.2
New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.27.3
New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon Processors. . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.28 TASK SWITCHING AND TSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.28.1
P6 Family and Pentium Processor TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.28.2
TSS Selector Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.28.3
Order of Reads/Writes to the TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.28.4
Using A 16-Bit TSS with 32-Bit Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.28.5
Differences in I/O Map Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.29 CACHE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
22.29.1
Self-Modifying Code with Cache Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
22.29.2
Disabling the L3 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
22.30 PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
22.30.1
Large Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
Vol. 3A xxi
CONTENTS
PAGE
22.30.2
22.30.3
22.31
22.31.1
22.31.2
22.31.3
22.31.4
22.32
22.33
22.33.1
22.34
22.35
22.36
22.37
22.37.1
22.37.2
22.37.3
22.37.4
22.37.5
22.38
22.39
PCD and PWT Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-30
Enabling and Disabling Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-31
STACK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31
Selector Pushes and Pops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-31
Error Code Pushes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-31
Fault Handling Effects on the Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-32
Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-32
MIXING 16- AND 32-BIT SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32
SEGMENT AND ADDRESS WRAPAROUND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32
Segment Wraparound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-33
STORE BUFFERS AND MEMORY ORDERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-33
BUS LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34
BUS HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34
MODEL-SPECIFIC EXTENSIONS TO THE IA-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34
Model-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-35
RDMSR and WRMSR Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-35
Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-35
Machine-Check Exception and Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-35
Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-36
TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36
INITIAL STATE OF PENTIUM, PENTIUM PRO AND PENTIUM 4 PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36
CHAPTER 23
INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIRTUAL MACHINE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTRODUCTION TO VMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIFE CYCLE OF VMM SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIRTUAL-MACHINE CONTROL STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DISCOVERING SUPPORT FOR VMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ENABLING AND ENTERING VMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESTRICTIONS ON VMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 24
VIRTUAL MACHINE CONTROL STRUCTURES
24.1
24.2
24.3
24.4
24.4.1
24.4.2
24.5
24.6
24.6.1
24.6.2
24.6.3
24.6.4
24.6.5
24.6.6
24.6.7
24.6.8
24.6.9
24.6.10
24.6.11
24.6.12
24.6.13
24.6.14
24.6.15
24.6.16
24.6.17
24.6.18
24.6.19
23-1
23-1
23-1
23-2
23-2
23-2
23-3
23-3
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
FORMAT OF THE VMCS REGION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
ORGANIZATION OF VMCS DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
GUEST-STATE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
Guest Register State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
Guest Non-Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
HOST-STATE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
VM-EXECUTION CONTROL FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
Pin-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Exception Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-12
I/O-Bitmap Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-12
Time-Stamp Counter Offset and Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-12
Guest/Host Masks and Read Shadows for CR0 and CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-12
CR3-Target Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-13
Controls for APIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-13
MSR-Bitmap Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-14
Executive-VMCS Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-14
Extended-Page-Table Pointer (EPTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-15
Virtual-Processor Identifier (VPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-15
Controls for PAUSE-Loop Exiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-15
VM-Function Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-16
VMCS Shadowing Bitmap Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-16
ENCLS-Exiting Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-16
Control Field for Page-Modification Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-16
Controls for Virtualization Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-16
XSS-Exiting Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-17
xxii Vol. 3A
CONTENTS
PAGE
24.7
24.7.1
24.7.2
24.8
24.8.1
24.8.2
24.8.3
24.9
24.9.1
24.9.2
24.9.3
24.9.4
24.9.5
24.10
24.11
24.11.1
24.11.2
24.11.3
24.11.4
24.11.5
VM-EXIT CONTROL FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17
VM-Exit Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17
VM-Exit Controls for MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18
VM-ENTRY CONTROL FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18
VM-Entry Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
VM-Entry Controls for MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
VM-Entry Controls for Event Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
VM-EXIT INFORMATION FIELDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21
Basic VM-Exit Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21
Information for VM Exits Due to Vectored Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22
Information for VM Exits That Occur During Event Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22
Information for VM Exits Due to Instruction Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23
VM-Instruction Error Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23
VMCS TYPES: ORDINARY AND SHADOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
SOFTWARE USE OF THE VMCS AND RELATED STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
Software Use of Virtual-Machine Control Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
VMREAD, VMWRITE, and Encodings of VMCS Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25
Initializing a VMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27
Software Access to Related Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27
VMXON Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27
CHAPTER 25
VMX NON-ROOT OPERATION
25.1
25.1.1
25.1.2
25.1.3
25.2
25.3
25.4
25.4.1
25.4.2
25.5
25.5.1
25.5.2
25.5.3
25.5.4
25.5.5
25.5.5.1
25.5.5.2
25.5.5.3
25.5.6
25.5.6.1
25.5.6.2
25.5.6.3
25.6
INSTRUCTIONS THAT CAUSE VM EXITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
Relative Priority of Faults and VM Exits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
Instructions That Cause VM Exits Unconditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
Instructions That Cause VM Exits Conditionally. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
OTHER CAUSES OF VM EXITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
CHANGES TO INSTRUCTION BEHAVIOR IN VMX NON-ROOT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
OTHER CHANGES IN VMX NON-ROOT OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
Event Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
Treatment of Task Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
FEATURES SPECIFIC TO VMX NON-ROOT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
VMX-Preemption Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
Monitor Trap Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
Translation of Guest-Physical Addresses Using EPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
APIC Virtualization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
VM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
Enabling VM Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
General Operation of the VMFUNC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
EPTP Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
Virtualization Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
Convertible EPT Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
Virtualization-Exception Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
Delivery of Virtualization Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
UNRESTRICTED GUESTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
CHAPTER 26
VM ENTRIES
26.1
BASIC VM-ENTRY CHECKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2
CHECKS ON VMX CONTROLS AND HOST-STATE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2.1
Checks on VMX Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2.1.1
VM-Execution Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2.1.2
VM-Exit Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
26.2.1.3
VM-Entry Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
26.2.2
Checks on Host Control Registers and MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
26.2.3
Checks on Host Segment and Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
26.2.4
Checks Related to Address-Space Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
26.3
CHECKING AND LOADING GUEST STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
26.3.1
Checks on the Guest State Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
26.3.1.1
Checks on Guest Control Registers, Debug Registers, and MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
26.3.1.2
Checks on Guest Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9
Vol. 3A xxiii
CONTENTS
PAGE
26.3.1.3
26.3.1.4
26.3.1.5
26.3.1.6
26.3.2
26.3.2.1
26.3.2.2
26.3.2.3
26.3.2.4
26.3.2.5
26.3.3
26.4
26.5
26.5.1
26.5.1.1
26.5.1.2
26.5.1.3
26.5.2
26.6
26.6.1
26.6.2
26.6.3
26.6.4
26.6.5
26.6.6
26.6.7
26.6.8
26.6.9
26.7
26.8
Checks on Guest Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-11
Checks on Guest RIP and RFLAGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-11
Checks on Guest Non-Register State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-12
Checks on Guest Page-Directory-Pointer-Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-14
Loading Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-14
Loading Guest Control Registers, Debug Registers, and MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-15
Loading Guest Segment Registers and Descriptor-Table Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-16
Loading Guest RIP, RSP, and RFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-16
Loading Page-Directory-Pointer-Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17
Updating Non-Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17
Clearing Address-Range Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17
LOADING MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17
EVENT INJECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18
Vectored-Event Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-18
Details of Vectored-Event Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-18
VM Exits During Event Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-20
Event Injection for VM Entries to Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-20
Injection of Pending MTF VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-21
SPECIAL FEATURES OF VM ENTRY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21
Interruptibility State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-21
Activity State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-22
Delivery of Pending Debug Exceptions after VM Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-22
VMX-Preemption Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-23
Interrupt-Window Exiting and Virtual-Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-23
NMI-Window Exiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-23
VM Exits Induced by the TPR Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-24
Pending MTF VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-24
VM Entries and Advanced Debugging Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-24
VM-ENTRY FAILURES DURING OR AFTER LOADING GUEST STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25
MACHINE-CHECK EVENTS DURING VM ENTRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25
CHAPTER 27
VM EXITS
27.1
27.2
27.2.1
27.2.2
27.2.3
27.2.4
27.3
27.3.1
27.3.2
27.3.3
27.3.4
27.4
27.5
27.5.1
27.5.2
27.5.3
27.5.4
27.5.5
27.5.6
27.6
27.7
27.8
ARCHITECTURAL STATE BEFORE A VM EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
RECORDING VM-EXIT INFORMATION AND UPDATING VM-ENTRY CONTROL FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
Basic VM-Exit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
Information for VM Exits Due to Vectored Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-11
Information for VM Exits During Event Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-12
Information for VM Exits Due to Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-13
SAVING GUEST STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-20
Saving Control Registers, Debug Registers, and MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-21
Saving Segment Registers and Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-21
Saving RIP, RSP, and RFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-21
Saving Non-Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-23
SAVING MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-25
LOADING HOST STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-25
Loading Host Control Registers, Debug Registers, MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-25
Loading Host Segment and Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-26
Loading Host RIP, RSP, and RFLAGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-28
Checking and Loading Host Page-Directory-Pointer-Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-28
Updating Non-Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-28
Clearing Address-Range Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-29
LOADING MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-29
VMX ABORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-29
MACHINE-CHECK EVENTS DURING VM EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30
CHAPTER 28
VMX SUPPORT FOR ADDRESS TRANSLATION
28.1
28.2
28.2.1
28.2.2
VIRTUAL PROCESSOR IDENTIFIERS (VPIDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
THE EXTENDED PAGE TABLE MECHANISM (EPT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
EPT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
EPT Translation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
xxiv Vol. 3A
CONTENTS
PAGE
28.2.3
EPT-Induced VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.2.3.1
EPT Misconfigurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
28.2.3.2
EPT Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
28.2.3.3
Prioritization of EPT Misconfigurations and EPT Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12
28.2.4
Accessed and Dirty Flags for EPT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13
28.2.5
Page-Modification Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14
28.2.6
EPT and Memory Typing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14
28.2.6.1
Memory Type Used for Accessing EPT Paging Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14
28.2.6.2
Memory Type Used for Translated Guest-Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15
28.3
CACHING TRANSLATION INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15
28.3.1
Information That May Be Cached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15
28.3.2
Creating and Using Cached Translation Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16
28.3.3
Invalidating Cached Translation Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17
28.3.3.1
Operations that Invalidate Cached Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17
28.3.3.2
Operations that Need Not Invalidate Cached Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19
28.3.3.3
Guidelines for Use of the INVVPID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19
28.3.3.4
Guidelines for Use of the INVEPT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20
CHAPTER 29
APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
29.1
29.1.1
29.1.2
29.1.3
29.1.4
29.1.5
29.2
29.2.1
29.2.2
29.3
29.4
29.4.1
29.4.2
29.4.3
29.4.3.1
29.4.3.2
29.4.3.3
29.4.4
29.4.5
29.4.6
29.4.6.1
29.4.6.2
29.5
29.6
VIRTUAL APIC STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
Virtualized APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
TPR Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
PPR Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
EOI Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
Self-IPI Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
EVALUATION AND DELIVERY OF VIRTUAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
Evaluation of Pending Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
Virtual-Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
VIRTUALIZING CR8-BASED TPR ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
VIRTUALIZING MEMORY-MAPPED APIC ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Priority of APIC-Access VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
Virtualizing Reads from the APIC-Access Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
Virtualizing Writes to the APIC-Access Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
Determining Whether a Write Access is Virtualized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
APIC-Write Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8
APIC-Write VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9
Instruction-Specific Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9
Issues Pertaining to Page Size and TLB Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
APIC Accesses Not Directly Resulting From Linear Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
Guest-Physical Accesses to the APIC-Access Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11
Physical Accesses to the APIC-Access Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11
VIRTUALIZING MSR-BASED APIC ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12
POSTED-INTERRUPT PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
CHAPTER 30
VMX INSTRUCTION REFERENCE
30.1
30.2
30.3
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
VMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
INVEPT— Invalidate Translations Derived from EPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
INVVPID— Invalidate Translations Based on VPID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
VMCALL—Call to VM Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
VMCLEAR—Clear Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
VMFUNC—Invoke VM function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13
VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14
VMPTRLD—Load Pointer to Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16
VMPTRST—Store Pointer to Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18
VMREAD—Read Field from Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20
VMRESUME—Resume Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22
VMWRITE—Write Field to Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-23
Vol. 3A xxv
CONTENTS
PAGE
30.4
VMXOFF—Leave VMX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-25
VMXON—Enter VMX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-27
VM INSTRUCTION ERROR NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-29
CHAPTER 31
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
31.1
VMX SYSTEM PROGRAMMING OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.2
SUPPORTING PROCESSOR OPERATING MODES IN GUEST ENVIRONMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.2.1
Using Unrestricted Guest Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.3
MANAGING VMCS REGIONS AND POINTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.4
USING VMX INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.5
VMM SETUP & TEAR DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4
31.5.1
Algorithms for Determining VMX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
31.6
PREPARATION AND LAUNCHING A VIRTUAL MACHINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
31.7
HANDLING OF VM EXITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7
31.7.1
Handling VM Exits Due to Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
31.7.1.1
Reflecting Exceptions to Guest Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
31.7.1.2
Resuming Guest Software after Handling an Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9
31.8
MULTI-PROCESSOR CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10
31.8.1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-11
31.8.2
Moving a VMCS Between Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-11
31.8.3
Paired Index-Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-11
31.8.4
External Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-11
31.8.5
CPUID Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-12
31.9
32-BIT AND 64-BIT GUEST ENVIRONMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12
31.9.1
Operating Modes of Guest Environments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-12
31.9.2
Handling Widths of VMCS Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-12
31.9.2.1
Natural-Width VMCS Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-13
31.9.2.2
64-Bit VMCS Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-13
31.9.3
IA-32e Mode Hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-13
31.9.4
IA-32e Mode Guests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-13
31.9.5
32-Bit Guests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-14
31.10 HANDLING MODEL SPECIFIC REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14
31.10.1
Using VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-14
31.10.2
Using VM-Exit Controls for MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-15
31.10.3
Using VM-Entry Controls for MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-15
31.10.4
Handling Special-Case MSRs and Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-15
31.10.4.1
Handling IA32_EFER MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-16
31.10.4.2
Handling the SYSENTER and SYSEXIT Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-16
31.10.4.3
Handling the SYSCALL and SYSRET Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-16
31.10.4.4
Handling the SWAPGS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-16
31.10.4.5
Implementation Specific Behavior on Writing to Certain MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-16
31.10.5
Handling Accesses to Reserved MSR Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-17
31.11 HANDLING ACCESSES TO CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17
31.12 PERFORMANCE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17
31.13 USE OF THE VMX-PREEMPTION TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17
CHAPTER 32
VIRTUALIZATION OF SYSTEM RESOURCES
32.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.2
VIRTUALIZATION SUPPORT FOR DEBUGGING FACILITIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.2.1
Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.3
MEMORY VIRTUALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.3.1
Processor Operating Modes & Memory Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.3.2
Guest & Host Physical Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.3.3
Virtualizing Virtual Memory by Brute Force . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.3.4
Alternate Approach to Memory Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.3.5
Details of Virtual TLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.3.5.1
Initialization of Virtual TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
32.3.5.2
Response to Page Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
32.3.5.3
Response to Uses of INVLPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7
32.3.5.4
Response to CR3 Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
xxvi Vol. 3A
CONTENTS
PAGE
32.4
32.4.1
32.4.2
MICROCODE UPDATE FACILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
Early Load of Microcode Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
Late Load of Microcode Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
CHAPTER 33
HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITOR
33.1
33.2
33.3
33.3.1
33.3.2
33.3.2.1
33.3.2.2
33.3.2.3
33.3.2.4
33.3.2.5
33.3.3
33.3.3.1
33.3.3.2
33.3.3.3
33.3.3.4
33.4
33.4.1
33.4.2
33.4.3
33.4.3.1
33.4.3.2
33.4.3.3
33.4.3.4
33.4.3.5
33.5
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
INTERRUPT HANDLING IN VMX OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
EXTERNAL INTERRUPT VIRTUALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
Virtualization of Interrupt Vector Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
Control of Platform Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
PIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
xAPIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
Local APIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
I/O APIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
Virtualization of Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
Examples of Handling of External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
Guest Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
Processor Treatment of External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
Processing of External Interrupts by VMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7
Generation of Virtual Interrupt Events by VMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7
ERROR HANDLING BY VMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
VM-Exit Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
Machine-Check Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
MCA Error Handling Guidelines for VMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-9
VMM Error Handling Strategies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
Basic VMM MCA error recovery handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
Implementation Considerations for the Basic Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
MCA Virtualization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
Implementation Considerations for the MCA Virtualization Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-11
HANDLING ACTIVITY STATES BY VMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-11
CHAPTER 34
SYSTEM MANAGEMENT MODE
34.1
34.1.1
34.2
34.3
34.3.1
34.3.2
34.4
34.4.1
34.4.1.1
34.4.2
34.4.2.1
34.5
34.5.1
34.5.2
34.6
34.7
34.7.1
34.8
34.9
34.10
34.10.1
34.11
34.12
34.12.1
34.13
34.14
SYSTEM MANAGEMENT MODE OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1
System Management Mode and VMX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1
SYSTEM MANAGEMENT INTERRUPT (SMI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2
SWITCHING BETWEEN SMM AND THE OTHER
PROCESSOR OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2
Entering SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2
Exiting From SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3
SMRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3
SMRAM State Save Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4
SMRAM State Save Map and Intel 64 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6
SMRAM Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
System Management Range Registers (SMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9
SMI HANDLER EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9
Initial SMM Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9
SMI Handler Operating Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10
EXCEPTIONS AND INTERRUPTS WITHIN SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10
MANAGING SYNCHRONOUS AND ASYNCHRONOUS
SYSTEM MANAGEMENT INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11
I/O State Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-12
NMI HANDLING WHILE IN SMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-13
SMM REVISION IDENTIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-13
AUTO HALT RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-13
Executing the HLT Instruction in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-14
SMBASE RELOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-14
I/O INSTRUCTION RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-15
Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-16
SMM MULTIPLE-PROCESSOR CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-16
DEFAULT TREATMENT OF SMIS AND SMM WITH VMX OPERATION AND SMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . 34-16
Vol. 3A xxvii
CONTENTS
PAGE
34.14.1
Default Treatment of SMI Delivery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-16
34.14.2
Default Treatment of RSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-17
34.14.3
Protection of CR4.VMXE in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-18
34.14.4
VMXOFF and SMI Unblocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-18
34.15 DUAL-MONITOR TREATMENT OF SMIs AND SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-19
34.15.1
Dual-Monitor Treatment Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-19
34.15.2
SMM VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-19
34.15.2.1
Architectural State Before a VM Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-20
34.15.2.2
Updating the Current-VMCS and Executive-VMCS Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-20
34.15.2.3
Recording VM-Exit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-20
34.15.2.4
Saving Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-21
34.15.2.5
Updating Non-Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-21
34.15.3
Operation of the SMM-Transfer Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-21
34.15.4
VM Entries that Return from SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-22
34.15.4.1
Checks on the Executive-VMCS Pointer Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-22
34.15.4.2
Checks on VM-Execution Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-22
34.15.4.3
Checks on VM-Entry Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-22
34.15.4.4
Checks on the Guest State Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-23
34.15.4.5
Loading Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-23
34.15.4.6
VMX-Preemption Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-23
34.15.4.7
Updating the Current-VMCS and SMM-Transfer VMCS Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-23
34.15.4.8
VM Exits Induced by VM Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-24
34.15.4.9
SMI Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-24
34.15.4.10
Failures of VM Entries That Return from SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-24
34.15.5
Enabling the Dual-Monitor Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-24
34.15.6
Activating the Dual-Monitor Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-26
34.15.6.1
Initial Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-26
34.15.6.2
Updating the Current-VMCS and Executive-VMCS Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-27
34.15.6.3
Saving Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-27
34.15.6.4
Saving MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-27
34.15.6.5
Loading Host State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-27
34.15.6.6
Loading MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-28
34.15.7
Deactivating the Dual-Monitor Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-29
34.16 SMI AND PROCESSOR EXTENDED STATE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-29
34.17 MODEL-SPECIFIC SYSTEM MANAGEMENT ENHANCEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-29
34.17.1
SMM Handler Code Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-29
34.17.2
SMI Delivery Delay Reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-30
34.17.3
Blocked SMI Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34-30
CHAPTER 35
MODEL-SPECIFIC REGISTERS (MSRS)
35.1
35.2
35.3
35.4
35.4.1
35.4.2
35.5
35.6
35.6.1
35.6.2
35.7
ARCHITECTURAL MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2
MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-43
MSRS IN THE 45 NM AND 32 NM INTEL® ATOM™ PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-57
MSRS IN INTEL PROCESSORS BASED ON SILVERMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-68
MSRs with Model-Specific Behavior in the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-80
MSRs In Intel Atom Processors Based on Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-83
MSRS IN NEXT GENERATION INTEL ATOM PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-85
MSRS IN THE INTEL® MICROARCHITECTURE CODE NAME NEHALEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-106
Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-124
Additional MSRs in the Intel® Xeon® Processor 7500 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-125
MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES (BASED ON INTEL® MICROARCHITECTURE CODE NAME
WESTMERE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-140
35.8
MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE NAME
WESTMERE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-141
35.9
MSRS IN INTEL® PROCESSOR FAMILY BASED ON INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE. . . . . . 35-142
35.9.1
MSRs In 2nd Generation Intel® Core™ Processor Family (Based on Intel® Microarchitecture Code Name Sandy
Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-161
35.9.2
MSRs In Intel® Xeon® Processor E5 Family (Based on Intel® Microarchitecture Code Name Sandy Bridge) . . . . . 35-166
35.9.3
Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-169
35.10 MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE
NAME IVY BRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-172
35.10.1
MSRs In Intel® Xeon® Processor E5 v2 Product Family (Based on Ivy Bridge-E Microarchitecture) . . . . . . . . . . . . . 35-176
35.10.2
Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-183
xxviii Vol. 3A
CONTENTS
PAGE
35.10.3
Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families . . . . . . . . . . . . . . . . . . . . . . . 35-186
35.11 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS (BASED ON HASWELL MICROARCHITECTURE) . . . . . . 35-188
35.11.1
MSRs in 4th Generation Intel® Core™ Processor Family (based on Haswell Microarchitecture) . . . . . . . . . . . . . . . . . . 35-193
35.11.2
Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-204
35.12 MSRS IN INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-206
35.12.1
Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-215
35.13 MSRS IN INTEL® CORE™ M PROCESSORS AND 5TH GENERATION INTEL CORE PROCESSORS. . . . . . . . . . . . . . . . . . . . . . 35-223
35.14 MSRS IN INTEL® XEON® PROCESSORS E5 V4 FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-226
35.14.1
Additional MSRs Supported in the Intel® Xeon® Processor D Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-236
35.14.2
Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-238
35.15 MSRS IN THE 6TH GENERATION INTEL® CORE™ PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-241
35.16 MSRS IN FUTURE INTEL® XEON® PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-261
35.17 MSRS IN INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-264
35.18 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-277
35.18.1
MSRs Unique to Intel® Xeon® Processor MP with L3 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-301
35.19 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-303
35.20 MSRS IN THE PENTIUM M PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-312
35.21 MSRS IN THE P6 FAMILY PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-319
35.22 MSRS IN PENTIUM PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-327
35.23 MSR INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-328
CHAPTER 36
INTEL® PROCESSOR TRACE
36.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1
36.1.1
Features and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1
36.1.1.1
Packet Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1
36.2
INTEL® PROCESSOR TRACE OPERATIONAL MODEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2
36.2.1
Change of Flow Instruction (COFI) Tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2
36.2.1.1
Direct Transfer COFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3
36.2.1.2
Indirect Transfer COFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3
36.2.1.3
Far Transfer COFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
36.2.2
Software Trace Instrumentation with PTWRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
36.2.3
Power Event Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
36.2.4
Trace Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
36.2.4.1
Filtering by Current Privilege Level (CPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
36.2.4.2
Filtering by CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5
36.2.4.3
Filtering by IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5
36.2.5
Packet Generation Enable Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
36.2.5.1
Packet Enable (PacketEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
36.2.5.2
Trigger Enable (TriggerEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
36.2.5.3
Context Enable (ContextEn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
36.2.5.4
Branch Enable (BranchEn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
36.2.5.5
Filter Enable (FilterEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
36.2.6
Trace Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
36.2.6.1
Single Range Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
36.2.6.2
Table of Physical Addresses (ToPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9
Single Output Region ToPA Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11
ToPA Table Entry Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11
ToPA STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-12
ToPA PMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-12
ToPA PMI and Single Output Region ToPA Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-13
ToPA PMI and XSAVES/XRSTORS State Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-13
ToPA Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-14
36.2.6.3
Trace Transport Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15
36.2.6.4
Restricted Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15
Modifications to Restricted Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15
36.2.7
Enabling and Configuration MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15
36.2.7.1
General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15
36.2.7.2
IA32_RTIT_CTL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-16
36.2.7.3
Enabling and Disabling Packet Generation with TraceEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19
Disabling Packet Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19
Other Writes to IA32_RTIT_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19
36.2.7.4
IA32_RTIT_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19
Vol. 3A xxix
CONTENTS
PAGE
36.2.7.5
IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-20
36.2.7.6
IA32_RTIT_CR3_MATCH MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-21
36.2.7.7
IA32_RTIT_OUTPUT_BASE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-21
36.2.7.8
IA32_RTIT_OUTPUT_MASK_PTRS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-22
36.2.8
Interaction of Intel® Processor Trace and Other Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-23
36.2.8.1
Intel® Transactional Synchronization Extensions (Intel® TSX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-23
36.2.8.2
Virtual-Machine Extensions (VMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-24
36.2.8.3
Intel Software Guard Extensions (SGX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-24
36.2.8.4
SENTER/ENTERACCS and ACM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-25
36.2.8.5
Intel® Memory Protection Extensions (Intel® MPX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-25
36.3
CONFIGURATION AND PROGRAMMING GUIDELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-25
36.3.1
Detection of Intel Processor Trace and Capability Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-25
36.3.1.1
Packet Decoding of RIP versus LIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-29
36.3.1.2
Model Specific Capability Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-29
36.3.2
Enabling and Configuration of Trace Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-29
36.3.2.1
Enabling Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-29
36.3.2.2
Disabling Packet Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-30
36.3.3
Flushing Trace Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-30
36.3.4
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-30
36.3.5
Context Switch Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-30
36.3.5.1
Manual Trace Configuration Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-30
36.3.5.2
Trace Configuration Context Switch Using XSAVES/XRSTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-31
36.3.6
Cycle-Accurate Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-31
36.3.6.1
Cycle Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-32
36.3.6.2
Cycle Packet Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-32
36.3.6.3
Cycle Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-33
36.3.7
Decoder Synchronization (PSB+). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-33
36.3.8
Internal Buffer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-34
36.3.8.1
Overflow Impact on Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-34
36.3.8.2
Overflow Impact on Timing Packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-34
36.3.9
Operational Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-35
36.4
TRACE PACKETS AND DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-35
36.4.1
Packet Relationships and Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-35
36.4.2
Packet Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-36
36.4.2.1
Taken/Not-taken (TNT) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-36
36.4.2.2
Target IP (TIP) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-38
IP Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-38
36.4.2.3
Deferred TIPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-40
36.4.2.4
Packet Generation Enable (TIP.PGE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-41
36.4.2.5
Packet Generation Disable (TIP.PGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-42
36.4.2.6
Flow Update (FUP) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-43
FUP IP Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-44
36.4.2.7
Paging Information (PIP) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-45
36.4.2.8
MODE Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-46
MODE.Exec Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-46
MODE.TSX Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-47
36.4.2.9
TraceStop Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-48
36.4.2.10
Core:Bus Ratio (CBR) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-48
36.4.2.11
Timestamp Counter (TSC) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-49
36.4.2.12
Mini Time Counter (MTC) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-50
36.4.2.13
TSC/MTC Alignment (TMA) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-51
36.4.2.14
Cycle Count Packet (CYC) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-52
36.4.2.15
VMCS Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-53
36.4.2.16
Overflow (OVF) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-54
36.4.2.17
Packet Stream Boundary (PSB) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-54
36.4.2.18
PSBEND Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-55
36.4.2.19
Maintenance (MNT) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-56
36.4.2.20
PAD Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-56
36.4.2.21
PTWRITE Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-57
36.4.2.22
Execution Stop (EXSTOP) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-58
36.4.2.23
MWAIT Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-59
36.4.2.24
Power Entry (PWRE) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-60
36.4.2.25
Power Exit (PWRX) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-61
36.5
TRACING IN VMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-61
xxx Vol. 3A
CONTENTS
PAGE
36.5.1
VMX-Specific Packets and VMCS Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-62
36.5.2
Managing Trace Packet Generation Across VMX Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-63
36.5.2.1
System-Wide Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-63
36.5.2.2
Host-Only Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-63
36.5.2.3
Guest-Only Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-64
36.5.2.4
Virtualization of Guest Output Packet Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-64
36.5.2.5
Emulation of Intel PT Traced State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-64
36.5.2.6
TSC Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-64
36.5.2.7
Failed VM Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-65
36.5.2.8
VMX Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-65
36.6
TRACING AND SMM TRANSFER MONITOR (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-65
36.7
PACKET GENERATION SCENARIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-65
36.8
SOFTWARE CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-78
36.8.1
Tracing SMM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-78
36.8.2
Cooperative Transition of Multiple Trace Collection Agents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-78
36.8.3
Tracking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-79
36.8.3.1
Time Domain Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-79
36.8.3.2
Estimating TSC within Intel PT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-79
36.8.3.3
VMX TSC Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-80
36.8.3.4
Calculating Frequency with Intel PT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-80
CHAPTER 37
INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
37.1
37.2
37.3
37.4
37.5
37.5.1
37.6
37.7
37.7.1
37.7.2
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1
ENCLAVE INTERACTION AND PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1
ENCLAVE LIFE CYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2
DATA STRUCTURES AND ENCLAVE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2
ENCLAVE PAGE CACHE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2
Enclave Page Cache Map (EPCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3
ENCLAVE INSTRUCTIONS AND INTEL® SGX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3
DISCOVERING SUPPORT FOR INTEL® SGX AND ENABLING ENCLAVE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4
Intel® SGX Opt-In Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4
Intel® SGX Resource Enumeration Leaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5
CHAPTER 38
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.1
38.2
38.3
38.4
38.5
38.5.1
38.5.2
38.5.3
38.5.3.1
38.5.3.2
38.6
38.7
38.7.1
38.7.2
38.8
38.8.1
38.8.2
38.8.3
38.8.4
38.9
38.9.1
38.9.1.1
38.9.1.2
38.9.2
38.9.2.1
38.9.2.2
OVERVIEW OF ENCLAVE EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1
ACCESS-CONTROL REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1
SEGMENT-BASED ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
PAGE-BASED ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
Access-control for Accesses that Originate from non-SGX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
Memory Accesses that Split across ELRANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
Implicit vs. Explicit Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
Explicit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3
Implicit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3
INTEL® SGX DATA STRUCTURES OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4
SGX ENCLAVE CONTROL STRUCTURE (SECS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4
ATTRIBUTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5
SECS.MISCSELECT Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5
THREAD CONTROL STRUCTURE (TCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6
TCS.FLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6
State Save Area Offset (OSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6
Current State Save Area Frame (CSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7
Number of State Save Area Frames (NSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7
STATE SAVE AREA (SSA) FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7
GPRSGX Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8
EXITINFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8
VECTOR Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-9
MISC Region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-9
EXINFO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-10
Page Fault Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-10
Vol. 3A xxxi
CONTENTS
PAGE
38.10
38.11
38.11.1
38.11.2
38.12
38.13
38.14
38.15
38.15.1
38.16
38.17
38.17.1
38.17.2
38.18
38.19
PAGE INFORMATION (PAGEINFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-10
SECURITY INFORMATION (SECINFO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11
SECINFO.FLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-11
PAGE_TYPE Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-12
PAGING CRYPTO METADATA (PCMD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-12
ENCLAVE SIGNATURE STRUCTURE (SIGSTRUCT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-12
EINIT TOKEN STRUCTURE (EINITTOKEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-13
REPORT (REPORT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14
REPORTDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-15
REPORT TARGET INFO (TARGETINFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-15
KEY REQUEST (KEYREQUEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-15
KEY REQUEST KeyNames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-16
Key Request Policy Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-16
VERSION ARRAY (VA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16
ENCLAVE PAGE CACHE MAP (EPCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16
CHAPTER 39
ENCLAVE OPERATION
39.1
39.1.1
39.1.2
39.1.3
39.1.4
39.2
39.2.1
39.2.2
39.2.3
39.2.3.1
39.3
39.3.1
39.3.2
39.3.3
39.4
39.4.1
39.4.1.1
39.4.1.2
39.4.2
39.4.2.1
39.4.2.2
39.4.3
39.4.3.1
39.4.3.2
39.5
39.5.1
39.5.2
39.5.2.1
39.5.3
39.5.4
39.5.5
39.5.6
39.5.7
39.5.8
39.5.9
39.5.10
39.5.11
39.6
39.6.1
39.6.2
39.6.3
39.6.4
39.6.5
CONSTRUCTING AN ENCLAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
ECREATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
EADD and EEXTEND Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
EINIT Interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
Intel® SGX Launch Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3
ENCLAVE ENTRY AND EXITING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3
Controlled Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3
Asynchronous Enclave Exit (AEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
Resuming Execution after AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
ERESUME Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
CALLING ENCLAVE PROCEDURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
Register Preservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
Returning to Caller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
INTEL® SGX KEY AND ATTESTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
Enclave Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
MRENCLAVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6
MRSIGNER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6
Security Version Numbers (SVN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7
Enclave Security Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7
Hardware Security Version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7
Sealing Enclave Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8
Using REPORTs for Local Attestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8
EPC AND MANAGEMENT OF EPC PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
EPC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
OS Management of EPC Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
Enhancement to Managing EPC Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
Eviction of Enclave Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
Loading an Enclave Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
Eviction of an SECS Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
Eviction of a Version Array Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-11
Allocating a Regular Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-11
Allocating a TCS Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-11
Trimming a Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-12
Restricting the EPCM Permissions of a Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-12
Extending the EPCM Permissions of a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-13
CHANGES TO INSTRUCTION BEHAVIOR INSIDE AN ENCLAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-13
Illegal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-13
RDRAND and RDSEED Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
PAUSE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
INT 3 Behavior Inside an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
INVD Handling when Enclaves Are Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
xxxii Vol. 3A
CONTENTS
PAGE
CHAPTER 40
ENCLAVE EXITING EVENTS
40.1
40.2
40.3
40.3.1
40.3.2
40.3.3
40.4
40.4.1
COMPATIBLE SWITCH TO THE EXITING STACK OF AEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1
STATE SAVING BY AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
SYNTHETIC STATE ON ASYNCHRONOUS ENCLAVE EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
Processor Synthetic State on Asynchronous Enclave Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
Synthetic State for Extended Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
Synthetic State for MISC Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4
AEX FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4
AEX Operational Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5
CHAPTER 41
SGX INSTRUCTION REFERENCES
41.1
INTEL® SGX INSTRUCTION SYNTAX AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1
41.1.1
ENCLS Register Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1
41.1.2
ENCLU Register Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1
41.1.3
Information and Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2
41.1.4
Internal CREGs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3
41.1.5
Concurrent Operation Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3
41.1.5.1
Concurrency Tables of Intel® SGX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4
41.2
INTEL® SGX INSTRUCTION REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4
ENCLS—Execute an Enclave System Function of Specified Leaf Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5
ENCLU—Execute an Enclave User Function of Specified Leaf Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7
41.3
INTEL® SGX SYSTEM LEAF FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-10
EADD—Add a Page to an Uninitialized Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-11
EAUG—Add a Page to an Initialized Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-15
EBLOCK—Mark a page in EPC as Blocked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18
ECREATE—Create an SECS page in the Enclave Page Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-21
EDBGRD—Read From a Debug Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-25
EDBGWR—Write to a Debug Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-28
EEXTEND—Extend Uninitialized Enclave Measurement by 256 Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-31
EINIT—Initialize an Enclave for Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-34
ELDB/ELDU—Load an EPC page and Marked its State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-41
EMODPR—Restrict the Permissions of an EPC Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-46
EMODT—Change the Type of an EPC Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-49
EPA—Add Version Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-52
EREMOVE—Remove a page from the EPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-54
ETRACK—Activates EBLOCK Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-57
EWB—Invalidate an EPC Page and Write out to Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-59
41.4
INTEL® SGX USER LEAF FUNCTION REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-64
41.4.1
Instruction Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-64
EACCEPT—Accept Changes to an EPC Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-65
EACCEPTCOPY—Initialize a Pending Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-69
EENTER—Enters an Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-73
EEXIT—Exits an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-81
EGETKEY—Retrieves a Cryptographic Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-84
EMODPE—Extend an EPC Page Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-92
EREPORT—Create a Cryptographic Report of the Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-95
ERESUME—Re-Enters an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-99
CHAPTER 42
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
42.1
42.2
42.2.1
42.2.2
42.3
42.3.1
42.3.2
INTEL® SGX AVAILABILITY IN VARIOUS PROCESSOR MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1
IA32_FEATURE_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1
Availability of Intel SGX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1
Intel SGX Launch Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1
INTERACTIONS WITH SEGMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1
Scope of Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1
Interactions of Intel® SGX Instructions with Segment, Operand, and Addressing Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2
Vol. 3A xxxiii
CONTENTS
PAGE
42.3.3
42.3.4
42.4
42.5
42.5.1
42.5.2
42.5.3
42.6
42.7
42.7.1
42.7.2
42.7.2.1
42.7.2.2
42.7.2.3
42.7.2.4
42.7.2.5
42.7.2.6
42.7.2.7
42.7.3
42.7.4
42.7.4.1
42.7.4.2
42.7.5
42.7.5.1
42.7.5.2
42.7.6
42.7.6.1
42.7.6.2
42.7.7
42.7.8
42.7.9
42.8
42.8.1
42.8.2
42.8.3
42.9
42.10
42.11
42.11.1
42.11.2
42.11.3
42.12
42.13
42.13.1
42.14
42.15
42.15.1
42.15.2
42.15.3
42.16
42.17
Interaction of Intel® SGX Instructions with Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2
Interactions of Enclave Execution with Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2
INTERACTIONS WITH PAGING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2
INTERACTIONS WITH VMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3
VMM Controls to Configure Guest Support of Intel® SGX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3
Interactions with the Extended Page Table Mechanism (EPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3
Interactions with APIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4
INTEL® SGX INTERACTIONS WITH ARCHITECTURALLY-VISIBLE EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4
INTERACTIONS WITH THE PROCESSOR EXTENDED STATE AND MISCELLANEOUS STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4
Requirements and Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4
Relevant Fields in Various Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-5
SECS.ATTRIBUTES.XFRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-5
SECS.SSAFRAMESIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-6
XSAVE Area in SSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-6
MISC Area in SSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-6
SIGSTRUCT Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-6
REPORT.ATTRIBUTES.XFRM and REPORT.MISCSELECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-7
KEYREQUEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-7
Processor Extended States and ENCLS[ECREATE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-7
Processor Extended States and ENCLU[EENTER] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-7
Fault Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-7
State Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-7
Processor Extended States and AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8
State Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8
State Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8
Processor Extended States and ENCLU[ERESUME]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8
Fault Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8
State Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8
Processor Extended States and ENCLU[EEXIT] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8
Processor Extended States and ENCLU[EREPORT]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9
Processor Extended States and ENCLU[EGETKEY] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9
INTERACTIONS WITH SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9
Availability of Intel® SGX instructions in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9
SMI while Inside an Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9
SMRAM Synthetic State of AEX Triggered by SMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9
INTERACTIONS OF INIT, SIPI, AND WAIT-FOR-SIPI WITH INTEL® SGX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-10
INTERACTIONS WITH DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-10
INTERACTIONS WITH TXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-10
Enclaves Created Prior to Execution of GETSEC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-10
Interaction of GETSEC with Intel® SGX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-10
Interactions with Authenticated Code Modules (ACMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-11
INTERACTIONS WITH CACHING OF LINEAR-ADDRESS TRANSLATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-11
INTERACTIONS WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS (INTEL® TSX) . . . . . . . . . . . . . . . . . . . . . 42-11
HLE and RTM Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-12
INTEL® SGX INTERACTIONS WITH S STATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-12
INTEL® SGX INTERACTIONS WITH MACHINE CHECK ARCHITECTURE (MCA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-12
Interactions with MCA Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-12
Machine Check Enables (IA32_MCi_CTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-12
CR4.MCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-12
INTEL® SGX INTERACTIONS WITH PROTECTED MODE VIRTUAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-13
INTEL SGX INTERACTION WITH PROTECTION KEYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-13
CHAPTER 43
ENCLAVE CODE DEBUG AND PROFILING
43.1
CONFIGURATION AND CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1
43.1.1
Debug Enclave vs. Production Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1
43.1.2
Tool-Chain Opt-in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1
43.2
SINGLE STEP DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1
43.2.1
Single Stepping ENCLS Instruction Leafs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1
43.2.2
Single Stepping ENCLU Instruction Leafs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1
43.2.3
Single-Stepping Enclave Entry with Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-2
43.2.3.1
Single Stepping without AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-2
43.2.3.2
Single Step Preempted by AEX Due to Non-SMI Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-2
43.2.4
RFLAGS.TF Treatment on AEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3
xxxiv Vol. 3A
CONTENTS
PAGE
43.2.5
43.2.6
43.3
43.3.1
43.3.2
43.3.3
43.3.4
43.4
43.4.1
43.4.2
43.4.3
43.5
43.5.1
43.5.2
43.5.2.1
43.5.2.2
43.5.2.3
43.6
43.6.1
43.6.2
43.6.3
43.6.4
43.6.5
43.6.6
43.6.6.1
Restriction on Setting of TF after an Opt-Out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3
Trampoline Code Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3
CODE AND DATA BREAKPOINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3
Breakpoint Suppression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3
Reporting of Instruction Breakpoint on Next Instruction on a Debug Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4
RF Treatment on AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4
Breakpoint Matching in Intel® SGX Instruction Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4
INT3 CONSIDERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4
Behavior of INT3 Inside an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4
Debugger Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4
VMM Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4
BRANCH TRACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5
BTF Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5
LBR Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5
LBR Stack on Opt-in Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5
LBR Stack on Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-6
Mispredict Bit, Record Type, and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7
INTERACTION WITH PERFORMANCE MONITORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7
IA32_PERF_GLOBAL_STATUS Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7
Performance Monitoring with Opt-in Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7
Performance Monitoring with Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8
Enclave Exit and Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8
PEBS Record Generation on Intel® SGX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8
Exception-Handling on PEBS/BTS Loads/Stores after AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8
Other Interactions with Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-9
APPENDIX A
VMX CAPABILITY REPORTING FACILITY
A.1
A.2
A.3
A.3.1
A.3.2
A.3.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
BASIC VMX INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESERVED CONTROLS AND DEFAULT SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VM-EXECUTION CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Processor-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VM-EXIT CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VM-ENTRY CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MISCELLANEOUS DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMX-FIXED BITS IN CR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMX-FIXED BITS IN CR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMCS ENUMERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VPID AND EPT CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VM FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX B
FIELD ENCODING IN VMCS
B.1
B.1.1
B.1.2
B.1.3
B.2
B.2.1
B.2.2
B.2.3
B.2.4
B.3
B.3.1
B.3.2
B.3.3
B.3.4
B.4
B.4.1
B.4.2
16-BIT FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Host-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-BIT FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-Bit Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-Bit Read-Only Data Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-Bit Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-Bit Host-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-BIT FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Bit Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Bit Read-Only Data Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Bit Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Bit Host-State Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NATURAL-WIDTH FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Natural-Width Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Natural-Width Read-Only Data Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-1
A-2
A-2
A-3
A-3
A-4
A-4
A-5
A-5
A-6
A-6
A-7
A-7
A-8
B-1
B-1
B-1
B-2
B-2
B-2
B-4
B-4
B-5
B-6
B-6
B-7
B-7
B-8
B-8
B-8
B-9
Vol. 3A xxxv
CONTENTS
PAGE
B.4.3
B.4.4
Natural-Width Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
Natural-Width Host-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
APPENDIX C
VMX BASIC EXIT REASONS
xxxvi Vol. 3A
CONTENTS
PAGE
FIGURES
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
Figure 4-13.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10.
Figure 5-11.
Figure 5-12.
Figure 5-13.
Figure 5-14.
Figure 5-15.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 6-6.
Figure 6-7.
Figure 6-8.
Figure 6-9.
Figure 7-1.
Figure 7-2.
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
IA-32 System-Level Registers and Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
System-Level Registers and Data Structures in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Transitions Among the Processor’s Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
IA32_EFER MSR Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
System Flags in the EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
XCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Protection Key Rights Register for User Pages (PKRU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
WBINVD Invalidation of Shared and Non-Shared Cache Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Segmentation and Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Flat Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Protected Flat Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Multi-Segment Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Logical Address to Linear Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Segment Descriptor When Segment-Present Flag Is Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Global and Local Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Pseudo-Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Enabling and Changing Paging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Linear-Address Translation to a 4-KByte Page using 32-Bit Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Linear-Address Translation to a 4-MByte Page using 32-Bit Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Formats of CR3 and Paging-Structure Entries with 32-Bit Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Linear-Address Translation to a 4-KByte Page using PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Linear-Address Translation to a 2-MByte Page using PAE Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Formats of CR3 and Paging-Structure Entries with PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Linear-Address Translation to a 4-KByte Page using IA-32e Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Linear-Address Translation to a 2-MByte Page using IA-32e Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Linear-Address Translation to a 1-GByte Page using IA-32e Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Formats of CR3 and Paging-Structure Entries with IA-32e Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Page-Fault Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Memory Management Convention That Assigns a Page Table to Each Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
Descriptor Fields Used for Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Descriptor Fields with Flags used in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Protection Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Privilege Check for Data Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Examples of Accessing Data Segments From Various Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Privilege Check for Control Transfer Without Using a Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Examples of Accessing Conforming and Nonconforming Code Segments From Various Privilege Levels. . . . . . . . . . 5-12
Call-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Call-Gate Descriptor in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Call-Gate Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Privilege Check for Control Transfer with Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Example of Accessing Call Gates At Various Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Stack Switching During an Interprivilege-Level Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
MSRs Used by SYSCALL and SYSRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Use of RPL to Weaken Privilege Level of Called Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Relationship of the IDTR and IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
IDT Gate Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Interrupt Procedure Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Stack Usage on Transfers to Interrupt and Exception-Handling Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Interrupt Task Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
64-Bit IDT Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
IA-32e Mode Stack Usage After Privilege Level Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Page-Fault Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
Structure of a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
32-Bit Task-State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Vol. 3A xxxvii
CONTENTS
PAGE
Figure 7-3.
Figure 7-4.
Figure 7-5.
Figure 7-6.
Figure 7-7.
Figure 7-8.
Figure 7-9.
Figure 7-10.
Figure 7-11.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 8-7.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 9-7.
Figure 9-8.
Figure 9-9.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure 10-10.
Figure 10-11.
Figure 10-12.
Figure 10-13.
Figure 10-14.
Figure 10-15.
Figure 10-16.
Figure 10-17.
Figure 10-18.
Figure 10-19.
Figure 10-21.
Figure 10-20.
Figure 10-22.
Figure 10-23.
Figure 10-24.
Figure 10-25.
Figure 10-26.
Figure 10-27.
Figure 10-28.
Figure 10-29.
Figure 10-30.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 11-6.
Figure 11-7.
Figure 11-8.
Figure 11-9.
xxxviii Vol. 3A
TSS Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
Format of TSS and LDT Descriptors in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
Task-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
Task Gates Referencing the Same Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
Nested Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Overlapping Linear-to-Physical Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
16-Bit TSS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
64-Bit TSS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Example of Write Ordering in Multiple-Processor Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
Interpretation of APIC ID in Early MP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Local APICs and I/O APIC in MP System Supporting Intel HT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
IA-32 Processor with Two Logical Processors Supporting Intel HT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
Generalized Four level Interpretation of the APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Conceptual Five-level Topology and 32-bit APIC ID Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Topological Relationships between Hierarchical IDs in a Hypothetical MP Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
MP System With Multiple Pentium III Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-54
Contents of CR0 Register after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
Version Information in the EDX Register after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
Processor State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Constructing Temporary GDT and Switching to Protected Mode (Lines 162-172 of List File) . . . . . . . . . . . . . . . . . . . . 9-23
Moving the GDT, IDT, and TSS from ROM to RAM (Lines 196-261 of List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
Task Switching (Lines 282-296 of List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Applying Microcode Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
Microcode Update Write Operation Flow [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45
Microcode Update Write Operation Flow [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46
Relationship of Local APIC and I/O APIC In Single-Processor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Local APICs and I/O APIC When Intel Xeon Processors Are Used in Multiple-Processor Systems . . . . . . . . . . . . . . . . . 10-3
Local APICs and I/O APIC When P6 Family Processors Are Used in Multiple-Processor Systems . . . . . . . . . . . . . . . . . . 10-3
Local APIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
IA32_APIC_BASE MSR (APIC_BASE_MSR in P6 Family) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Local APIC ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Local APIC Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Local Vector Table (LVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Error Status Register (ESR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Divide Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
Initial Count and Current Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
Interrupt Command Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
Logical Destination Register (LDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
Destination Format Register (DFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
Arbitration Priority Register (APR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and Intel Xeon Processors) . . . . . . . . . . . . . . . . . . . . 10-26
Interrupt Acceptance Flow Chart for the Local APIC (P6 Family and Pentium Processors) . . . . . . . . . . . . . . . . . . . . . . 10-27
Task-Priority Register (TPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
Processor-Priority Register (PPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
EOI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
IRR, ISR and TMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
CR8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
Spurious-Interrupt Vector Register (SVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
Layout of the MSI Message Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
Layout of the MSI Message Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
IA32_APIC_BASE MSR Supporting x2APIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37
Local x2APIC State Transitions with IA32_APIC_BASE, INIT, and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42
Interrupt Command Register (ICR) in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45
Logical Destination Register in x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-46
SELF IPI register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
Cache Structure of the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Cache Structure of the Intel Core i7 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Cache-Control Registers and Bits Available in Intel 64 and IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Mapping Physical Memory With MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
IA32_MTRRCAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
IA32_MTRR_DEF_TYPE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn Variable-Range Register Pair . . . . . . . . . . . . . . . . . . . . . . . . 11-25
IA32_SMRR_PHYSBASE and IA32_SMRR_PHYSMASK SMRR Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
IA32_PAT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
CONTENTS
PAGE
Figure 12-1.
Figure 12-2.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
Figure 14-8.
Figure 14-9.
Figure 14-10.
Figure 14-11.
Figure 14-12.
Figure 14-13.
Figure 14-14.
Figure 14-15.
Figure 14-16.
Figure 14-17.
Figure 14-18.
Figure 14-19.
Figure 14-20.
Figure 14-21.
Figure 14-22.
Figure 14-23.
Figure 14-24.
Figure 14-25.
Figure 14-26.
Figure 14-27.
Figure 14-28.
Figure 14-29.
Figure 14-30.
Figure 14-31.
Figure 14-32.
Figure 14-33.
Figure 14-34.
Figure 14-35.
Figure 14-36.
Figure 14-37.
Figure 14-38.
Figure 14-39.
Figure 14-40.
Figure 14-41.
Figure 14-42.
Figure 14-43.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 17-6.
Figure 17-7.
Figure 17-8.
Figure 17-9.
Mapping of MMX Registers to Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Mapping of MMX Registers to x87 FPU Data Register Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
IA32_PERF_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
IA32_ENERGY_PERF_BIAS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
IA32_PM_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
IA32_HWP_CAPABILITIES Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
IA32_HWP_REQUEST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
IA32_HWP_REQUEST_PKG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
IA32_HWP_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
IA32_THERM_STATUS Register With HWP Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
MSR_PPERF MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
IA32_HWP_INTERRUPT MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
IA32_PKG_HDC_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
IA32_PM_CTL1 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
IA32_THREAD_STALL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
MSR_CORE_HDC_RESIDENCY MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
MSR_PKG_HDC_SHALLOW_RESIDENCY MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
MSR_PKG_HDC_DEEP_RESIDENCY MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
MSR_PKG_HDC_CONFIG MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Example of Effective Frequency Reduction and Forced Idle Period of HDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Processor Modulation Through Stop-Clock Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
MSR_THERM2_CTL Register On Processors with CPUID Family/Model/Stepping Signature Encoded as 0x69n or
0x6Dn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
MSR_THERM2_CTL Register for Supporting TM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
IA32_THERM_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
IA32_THERM_INTERRUPT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
IA32_CLOCK_MODULATION MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
IA32_CLOCK_MODULATION MSR with Clock Modulation Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
IA32_THERM_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
IA32_THERM_INTERRUPT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
IA32_PACKAGE_THERM_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
IA32_PACKAGE_THERM_INTERRUPT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
MSR_RAPL_POWER_UNIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
MSR_PKG_POWER_LIMIT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
MSR_PKG_ENERGY_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
MSR_PKG_POWER_INFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
MSR_PKG_PERF_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
MSR_PP0_ENERGY_STATUS/MSR_PP1_ENERGY_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
MSR_PP0_POLICY/MSR_PP1_POLICY Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
MSR_PP0_PERF_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
MSR_DRAM_POWER_LIMIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
MSR_DRAM_ENERGY_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
MSR_DRAM_POWER_INFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
MSR_DRAM_PERF_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Machine-Check MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
IA32_MCG_CAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
IA32_MCG_STATUS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
IA32_MCG_EXT_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
IA32_MCi_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
IA32_MCi_STATUS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
IA32_MCi_ADDR MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
UCR Support in IA32_MCi_MISC Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
IA32_MCi_CTL2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
CMCI Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
DR6/DR7 Layout on Processors Supporting Intel® 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
IA32_DEBUGCTL MSR for Processors based on Intel Core microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
64-bit Address Layout of LBR MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
32-bit Branch Trace Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
PEBS Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
IA-32e Mode DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
64-bit Branch Trace Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
Vol. 3A xxxix
CONTENTS
PAGE
Figure 17-10.
Figure 17-11.
Figure 17-12.
Figure 17-13.
Figure 17-14.
Figure 17-15.
Figure 17-16.
Figure 17-17.
Figure 17-18.
Figure 17-19.
Figure 17-20.
Figure 17-21.
Figure 17-22.
Figure 17-23.
Figure 17-24.
Figure 17-25.
Figure 17-26.
Figure 17-27.
Figure 17-28.
Figure 17-29.
Figure 17-30.
Figure 17-31.
Figure 17-32.
Figure 17-33.
Figure 17-34.
Figure 17-35.
Figure 17-36.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 18-4.
Figure 18-5.
Figure 18-6.
Figure 18-7.
Figure 18-8.
Figure 18-9.
Figure 18-10.
Figure 18-11.
Figure 18-12.
Figure 18-13.
Figure 18-14.
Figure 18-15.
Figure 18-16.
Figure 18-17.
Figure 18-18.
Figure 18-19.
Figure 18-20.
Figure 18-21.
Figure 18-22.
Figure 18-23.
Figure 18-24.
Figure 18-25.
Figure 18-26.
Figure 18-27.
Figure 18-28.
Figure 18-29.
Figure 18-30.
Figure 18-31.
Figure 18-32.
Figure 18-33.
Figure 18-34.
Figure 18-35.
Figure 18-36.
Figure 18-37.
Figure 18-38.
xl Vol. 3A
64-bit PEBS Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
IA32_DEBUGCTL MSR for Processors based on Intel microarchitecture code name Nehalem . . . . . . . . . . . . . . . . . . . 17-27
MSR_DEBUGCTLA MSR for Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33
LBR MSR Branch Record Layout for the Pentium 4 and Intel Xeon Processor Family. . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35
IA32_DEBUGCTL MSR for Intel Core Solo and Intel Core Duo Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36
LBR Branch Record Layout for the Intel Core Solo and Intel Core Duo Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36
MSR_DEBUGCTLB MSR for Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37
LBR Branch Record Layout for the Pentium M Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38
DEBUGCTLMSR Register (P6 Family Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39
Platform Shared Resource Monitoring Usage Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-44
CPUID.(EAX=0FH, ECX=0H) Monitoring Resource Type Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-45
L3 Cache Monitoring Capability Enumeration Data (CPUID.(EAX=0FH, ECX=1H) ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-45
L3 Cache Monitoring Capability Enumeration Event Type Bit Vector (CPUID.(EAX=0FH, ECX=1H) ). . . . . . . . . . . . . . 17-46
IA32_PQR_ASSOC MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-47
IA32_QM_EVTSEL and IA32_QM_CTR MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48
Software Usage of Cache Monitoring Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48
Cache Allocation Technology Allocates More Resource to High Priority Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-50
Examples of Cache Capacity Bitmasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-51
Class of Service and Cache Capacity Bitmasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-52
Code and Data Capacity Bitmasks of CDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-53
Cache Allocation Technology Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-54
CPUID.(EAX=10H, ECX=0H) Available Resource Type Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-55
L3 Cache Allocation Technology and CDP Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-55
L2 Cache Allocation Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56
IA32_PQR_ASSOC, IA32_L3_MASK_n MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57
IA32_L2_MASK_n MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57
Layout of IA32_L3_QOS_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-58
Layout of IA32_PERFEVTSELx MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Layout of IA32_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
Layout of IA32_PERF_GLOBAL_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
Layout of IA32_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Layout of IA32_PERF_GLOBAL_OVF_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Layout of IA32_PERFEVTSELx MSRs Supporting Architectural Performance Monitoring Version 3 . . . . . . . . . . . . . 18-10
IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performance Monitoring Version 3 . . . . . . . . . . . . . . . . . . . . . 18-10
Layout of Global Performance Monitoring Control MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
Global Performance Monitoring Overflow Status and Control MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
IA32_PERF_GLOBAL_STATUS MSR and Architectural Perfmon Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
IA32_PERF_GLOBAL_STATUS_RESET MSR and Architectural Perfmon Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
IA32_PERF_GLOBAL_STATUS_SET MSR and Architectural Perfmon Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
IA32_PERF_GLOBAL_INUSE MSR and Architectural Perfmon Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15
Layout of MSR_PERF_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19
Layout of MSR_PERF_GLOBAL_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19
Layout of MSR_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20
Layout of MSR_PERF_GLOBAL_OVF_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20
Request_Type Fields for MSR_OFFCORE_RSPx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27
Response_Supplier and Snoop Info Fields for MSR_OFFCORE_RSPx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28
IA32_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36
Layout of IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37
PEBS Programming Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39
Layout of MSR_PEBS_LD_LAT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41
Layout of MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 to Configure Off-core Response Events. . . . . . . . . . 18-42
Layout of MSR_UNCORE_PERF_GLOBAL_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44
Layout of MSR_UNCORE_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-45
Layout of MSR_UNCORE_PERF_GLOBAL_OVF_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-45
Layout of MSR_UNCORE_PERFEVTSELx MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46
Layout of MSR_UNCORE_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46
Layout of MSR_UNCORE_ADDR_OPCODE_MATCH MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47
Distributed Units of the Uncore of Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49
IA32_PERF_GLOBAL_CTRL MSR in Intel® Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . . . . . 18-52
IA32_PERF_GLOBAL_STATUS MSR in Intel® Microarchitecture Code Name Sandy Bridge. . . . . . . . . . . . . . . . . . . . . . . 18-53
IA32_PERF_GLOBAL_OVF_CTRL MSR in Intel microarchitecture code name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . 18-53
Layout of IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-55
Request_Type Fields for MSR_OFFCORE_RSP_x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-59
Response_Supplier and Snoop Info Fields for MSR_OFFCORE_RSP_x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60
Layout of Uncore PERFEVTSEL MSR for a C-Box Unit or the ARB Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61
CONTENTS
PAGE
Figure 18-39.
Figure 18-40.
Figure 18-41.
Figure 18-42.
Figure 18-43.
Figure 18-44.
Figure 18-45.
Figure 18-46.
Figure 18-47.
Figure 18-48.
Figure 18-49.
Figure 18-50.
Figure 18-51.
Figure 18-52.
Figure 18-53.
Figure 18-54.
Figure 18-55.
Figure 18-56.
Figure 18-57.
Figure 18-58.
Figure 18-59.
Figure 18-60.
Figure 18-61.
Figure 20-1.
Figure 20-2.
Figure 20-3.
Figure 20-4.
Figure 20-5.
Figure 21-1.
Figure 22-1.
Figure 23-1.
Figure 24-1.
Figure 28-1.
Figure 30-1.
Figure 30-2.
Figure 31-1.
Figure 32-1.
Figure 33-1.
Figure 34-1.
Figure 34-2.
Figure 34-3.
Figure 34-4.
Figure 34-5.
Figure 36-1.
Figure 36-2.
Figure 36-3.
Figure 37-1.
Figure 39-1.
Figure 39-2.
Figure 39-3.
Figure 40-1.
Figure 40-2.
Figure 41-1.
Figure 43-1.
Figure 43-2.
Figure 43-3.
Figure 43-4.
Layout of MSR_UNC_PERF_GLOBAL_CTRL MSR for Uncore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-62
Layout of IA32_PERFEVTSELx MSRs Supporting Intel TSX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71
IA32_PERF_GLOBAL_STATUS MSR in Broadwell Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-73
IA32_PERF_GLOBAL_OVF_CTRL MSR in Broadwell microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-74
Event Selection Control Register (ESCR) for Pentium 4 and Intel Xeon Processors without Intel HT Technology
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-86
Performance Counter (Pentium 4 and Intel Xeon Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-88
Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-89
Effects of Edge Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-93
Event Selection Control Register (ESCR) for the Pentium 4 Processor, Intel Xeon Processor and Intel Xeon
Processor MP Supporting Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-101
Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-102
Layout of IA32_PERF_CAPABILITIES MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-108
Block Diagram of 64-bit Intel Xeon Processor MP with 8-MByte L3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-109
MSR_IFSB_IBUSQx, Addresses: 107CCH and 107CDH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-110
MSR_IFSB_ISNPQx, Addresses: 107CEH and 107CFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-110
MSR_EFSB_DRDYx, Addresses: 107D0H and 107D1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-111
MSR_IFSB_CTL6, Address: 107D2H; MSR_IFSB_CNTR7, Address: 107D3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-111
Block Diagram of Intel Xeon Processor 7400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-112
Block Diagram of Intel Xeon Processor 7100 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-113
MSR_EMON_L3_CTR_CTL0/1, Addresses: 107CCH/107CDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-114
MSR_EMON_L3_CTR_CTL2/3, Addresses: 107CEH/107CFH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-116
MSR_EMON_L3_CTR_CTL4/5/6/7, Addresses: 107D0H-107D3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-116
PerfEvtSel0 and PerfEvtSel1 MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-118
CESR MSR (Pentium Processor Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-121
Real-Address Mode Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
Interrupt Vector Table in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
Entering and Leaving Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
Privilege Level 0 Stack After Interrupt or Exception in Virtual-8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
Software Interrupt Redirection Bit Map in TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18
Stack after Far 16- and 32-Bit Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
I/O Map Base Address Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
Interaction of a Virtual-Machine Monitor and Guests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
States of VMCS X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
Formats of EPTP and EPT Paging-Structure Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11
INVEPT Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
INVVPID Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
VMX Transitions and States of VMCS in a Logical Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
Virtual TLB Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
Host External Interrupts and Guest Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
SMRAM Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-13
Auto HALT Restart Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-14
SMBASE Relocation Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-15
I/O Instruction Restart Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-15
ToPA Memory Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-10
Layout of ToPA Table Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11
Interpreting Tabular Definition of Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-36
An Enclave Within the Application’s Virtual Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1
Enclave Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
Measurement Flow of Enclave Build Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6
SGX Local Attestation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8
Exit Stack Just After Interrupt with Stack Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1
The SSA Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
Relationships Between SECS, SIGSTRUCT and EINITTOKEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-34
Single Stepping with Opt-out Entry - No AEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-2
Single Stepping with Opt-out Entry -AEX Due to Non-SMI Event Before Single-Step Boundary . . . . . . . . . . . . . . . . . . 43-3
LBR Stack Interaction with Opt-in Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-6
LBR Stack Interaction with Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7
Vol. 3A xli
CONTENTS
PAGE
TABLES
Table 2-1.
Table 2-2.
Table 2-3.
Table 3-1.
Table 3-2.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-6.
Table 4-5.
Table 4-7.
Table 4-8.
Table 4-9.
Table 4-10.
Table 4-11.
Table 4-12.
Table 4-13.
Table 4-14.
Table 4-15.
Table 4-16.
Table 4-17.
Table 4-18.
Table 4-19.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-6.
Table 5-7.
Table 5-5.
Table 5-9.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 6-8.
Table 7-1.
Table 7-2.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Table 9-10.
Table 9-11.
xlii Vol. 3A
IA32_EFER MSR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Action Taken By x87 FPU Instructions for Different Combinations of EM, MP, and TS. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Summary of System Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Code- and Data-Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
System-Segment and Gate-Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Properties of Different Paging Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Paging Structures in the Different Paging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Use of CR3 with 32-Bit Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Format of a 32-Bit Page-Directory Entry that Maps a 4-MByte Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Format of a 32-Bit Page-Table Entry that Maps a 4-KByte Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Format of a 32-Bit Page-Directory Entry that References a Page Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Use of CR3 with PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Format of a PAE Page-Directory Entry that Maps a 2-MByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Format of a PAE Page-Directory Entry that References a Page Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Format of a PAE Page-Table Entry that Maps a 4-KByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Use of CR3 with IA-32e Paging and CR4.PCIDE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Use of CR3 with IA-32e Paging and CR4.PCIDE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Format of an IA-32e PML4 Entry (PML4E) that References a Page-Directory-Pointer Table . . . . . . . . . . . . . . . . . . . . . 4-23
Format of an IA-32e Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page . . . . . . . . . . . . . . . . . . . 4-24
Format of an IA-32e Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory . . . . . . . . . . . . 4-25
Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Format of an IA-32e Page-Directory Entry that References a Page Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Format of an IA-32e Page-Table Entry that Maps a 4-KByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Privilege Check Rules for Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
64-Bit-Mode Stack Layout After Far CALL with CPL Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Combined Page-Directory and Page-Table Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Extended Feature Enable MSR (IA32_EFER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Legacy PAE-Enabled 4-KByte Page Level Protection Matrix with Execute-Disable Bit Capability. . . . . . . . . . . . . . . . . 5-31
Legacy PAE-Enabled 2-MByte Page Level Protection with Execute-Disable Bit Capability . . . . . . . . . . . . . . . . . . . . . . . 5-31
IA-32e Mode Page Level Protection Matrix with Execute-Disable Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Reserved Bit Checking WIth Execute-Disable Bit Capability Not Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
IA-32e Mode Page Level Protection Matrix with Execute-Disable Bit Capability Enabled . . . . . . . . . . . . . . . . . . . . . . . . 5-32
Protected-Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Priority Among Simultaneous Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Debug Exception Conditions and Corresponding Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Interrupt and Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Conditions for Generating a Double Fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Invalid TSS Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Alignment Requirements by Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
SIMD Floating-Point Exceptions Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
Exception Conditions Checked During a Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Effect of a Task Switch on Busy Flag, NT Flag, Previous Task Link Field, and TS Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Broadcast INIT-SIPI-SIPI Sequence and Choice of Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
Initial APIC IDs for the Logical Processors in a System that has Four Intel Xeon MP Processors Supporting Intel
Hyper-Threading Technology1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
Initial APIC IDs for the Logical Processors in a System that has Two Physical Processors Supporting Dual-Core and
Intel Hyper-Threading Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
Example of Possible x2APIC ID Assignment in a System that has Two Physical Processors Supporting x2APIC and
Intel Hyper-Threading Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37
Boot Phase IPI Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53
IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Variance of RESET Values in Selected Intel Architecture Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Recommended Settings of EM and MP Flags on IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Software Emulation Settings of EM, MP, and NE Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Main Initialization Steps in STARTUP.ASM Source Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
Relationship Between BLD Item and ASM Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Microcode Update Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
Microcode Update Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
Extended Processor Signature Table Header Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
Processor Signature Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
Processor Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
CONTENTS
PAGE
Table 9-12.
Table 9-13.
Table 9-14.
Table 9-15.
Table 9-16.
Table 9-17.
Table 9-18.
Table 9-19.
Table 10-1
Table 10-2.
Table 10-3
Table 10-4
Table 10-5.
Table 10-6.
Table 10-7.
Table 10-1.
Table 10-2.
Table 10-3.
Table 10-4.
Table 11-1.
Table 11-2.
Table 11-3.
Table 11-4.
Table 11-5.
Table 11-6.
Table 11-7.
Table 11-8.
Table 11-9.
Table 11-10.
Table 11-11.
Table 11-12.
Table 12-1.
Table 12-3.
Table 12-2.
Table 13-1.
Table 13-2.
Table 13-3.
Table 14-1.
Table 14-2.
Table 14-3.
Table 14-4.
Table 15-1.
Table 15-2.
Table 15-3.
Table 15-4.
Table 15-5.
Table 15-6.
Table 15-7.
Table 15-8.
Table 15-9.
Table 15-10.
Table 15-11.
Table 15-12.
Table 15-13.
Table 15-14.
Table 15-15.
Table 15-16.
Table 15-17.
Table 15-18.
Table 15-19.
Table 15-20.
Table 16-1.
Table 16-2.
Table 16-3.
Microcode Update Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
Microcode Update Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
Parameters for the Presence Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
Parameters for the Write Update Data Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43
Parameters for the Control Update Sub-function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
Mnemonic Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
Parameters for the Read Microcode Update Data Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
Return Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49
Local APIC Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Local APIC Timer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
Valid Combinations for the Pentium 4 and Intel Xeon Processors’ Local xAPIC Interrupt Command Register . . . . 10-21
Valid Combinations for the P6 Family Processors’ Local APIC Interrupt Command Register. . . . . . . . . . . . . . . . . . . . . 10-21
x2APIC Operating Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37
Local APIC Register Address Map Supported by x2APIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38
MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
EOI Message (14 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
Short Message (21 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48
Non-Focused Lowest Priority Message (34 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-49
APIC Bus Status Cycles Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51
Characteristics of the Caches, TLBs, Store Buffer, and Write Combining Buffer in Intel 64 and IA-32 Processors . 11-2
Memory Types and Their Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Methods of Caching Available in Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6
Family, and Pentium Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
MESI Cache Line States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Cache Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Effective Page-Level Memory Type for Pentium Pro and Pentium II Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Effective Page-Level Memory Types for Pentium III and More Recent Processor Families. . . . . . . . . . . . . . . . . . . . . . 11-15
Memory Types That Can Be Encoded in MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Address Mapping for Fixed-Range MTRRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
Memory Types That Can Be Encoded With PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
Selection of PAT Entries with PAT, PCD, and PWT Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
Memory Type Setting of PAT Entries Following a Power-up or Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
Action Taken By MMX Instructions for Different Combinations of EM, MP and TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions on the x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . 12-3
Effects of MMX Instructions on x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2, SSE3, EM, MP, and TS. . . . . . . . . . . . . . . . . . . . 13-3
Action Taken for Combinations of OSFXSR, SSSE3, SSE4, EM, and TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
CPUID.(EAX=0DH, ECX=1) EAX Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Architectural and Non-Architectural MSRs Related to HWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Architectural and non-Architecture MSRs Related to HDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
On-Demand Clock Modulation Duty Cycle Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
RAPL MSR Interfaces and RAPL Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
Bits 54:53 in IA32_MCi_STATUS MSRs when IA32_MCG_CAP[11] = 1 and UC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
Overwrite Rules for Enabled Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Address Mode in IA32_MCi_MISC[8:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
Extended Machine Check State MSRs in Processors Without Support for Intel 64 Architecture. . . . . . . . . . . . . . . . . 15-11
Extended Machine Check State MSRs In Processors With Support For Intel 64 Architecture . . . . . . . . . . . . . . . . . . . 15-11
MC Error Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
Overwrite Rules for UC, CE, and UCR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
IA32_MCi_Status [15:0] Simple Error Code Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
IA32_MCi_Status [15:0] Compound Error Code Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
Encoding for TT (Transaction Type) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
Level Encoding for LL (Memory Hierarchy Level) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
Encoding of Request (RRRR) Sub-Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Encodings of PP, T, and II Sub-Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Encodings of MMM and CCCC Sub-Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
MCA Compound Error Code Encoding for SRAO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
IA32_MCi_STATUS Values for SRAO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
IA32_MCG_STATUS Flag Indication for SRAO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
MCA Compound Error Code Encoding for SRAR Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
IA32_MCi_STATUS Values for SRAR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25
IA32_MCG_STATUS Flag Indication for SRAR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25
CPUID DisplayFamily_DisplayModel Signatures for Processor Family 06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Incremental Decoding Information: Processor Family 06H Machine Error Codes For Machine Check. . . . . . . . . . . . . . 16-1
CPUID DisplayFamily_DisplayModel Signatures for Processors Based on Intel Core Microarchitecture . . . . . . . . . . . 16-3
Vol. 3A xliii
CONTENTS
PAGE
Table 16-4.
Table 16-5.
Table 16-6.
Table 16-7.
Table 16-8.
Table 16-9.
Table 16-10.
Table 16-11.
Table 16-12.
Table 16-13.
Table 16-14.
Table 16-15.
Table 16-16.
Table 16-17.
Table 16-18.
Table 16-19.
Table 16-20.
Table 16-21.
Table 16-22.
Table 16-23.
Table 16-24.
Table 16-25.
Table 16-26.
Table 16-27.
Table 16-28.
Table 16-29.
Table 16-30.
Table 16-31.
Table 16-32.
Table 16-33.
Table 16-34.
Table 16-35.
Table 16-36.
Table 16-37.
Table 16-38.
Table 16-39.
Table 16-40.
Table 16-41.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 17-6.
Table 17-7.
Table 17-8.
Table 17-9.
Table 17-10.
Table 17-11.
Table 17-12.
Table 17-13.
Table 17-14.
Table 17-15.
Table 17-16.
Table 17-17.
Table 17-18.
Table 17-19.
Table 18-1.
Table 18-2.
Table 18-3.
Table 18-4.
Table 18-5.
Table 18-6.
Table 18-8.
Table 18-7.
xliv Vol. 3A
Incremental Bus Error Codes of Machine Check for Processors Based on Intel Core Microarchitecture . . . . . . . . . . . 16-4
Incremental MCA Error Code Types for Intel Xeon Processor 7400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Type B Bus and Interconnect Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Type C Cache Bus Controller Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
Intel QPI Machine Check Error Codes for IA32_MC0_STATUS and IA32_MC1_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
Intel QPI Machine Check Error Codes for IA32_MC0_MISC and IA32_MC1_MISC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
Machine Check Error Codes for IA32_MC7_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
Incremental Memory Controller Error Codes of Machine Check for IA32_MC8_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
Incremental Memory Controller Error Codes of Machine Check for IA32_MC8_MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-10
Machine Check Error Codes for IA32_MC4_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-10
Intel QPI MC Error Codes for IA32_MC6_STATUS and IA32_MC7_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-11
Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 8, 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-12
Intel IMC MC Error Codes for IA32_MCi_MISC (i= 8, 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-12
Machine Check Error Codes for IA32_MC4_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-13
Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-14
Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-15
Machine Check Error Codes for IA32_MC4_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-16
Intel QPI MC Error Codes for IA32_MCi_STATUS (i = 5, 20, 21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-17
Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-18
Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-18
Machine Check Error Codes for IA32_MC4_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-19
Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-20
Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-21
Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
Machine Check Error Codes for IA32_MC4_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
Interconnect MC Error Codes for IA32_MCi_STATUS, i = 5, 12, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-24
Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-26
M2M MC Error Codes for IA32_MCi_STATUS (i= 7-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-27
Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-27
Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 6, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-28
Incremental Decoding Information: Processor Family 0FH Machine Error Codes For Machine Check . . . . . . . . . . . . .16-29
MCi_STATUS Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-30
Incremental MCA Error Code for Intel Xeon Processor MP 7100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-31
Other Information Field Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-31
Type A: L3 Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-32
Type B Bus and Interconnect Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-32
Type C Cache Bus Controller Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-33
Decoding Family 0FH Machine Check Codes for Cache Hierarchy Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-34
Breakpoint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Debug Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
Legacy and Streamlined Operation with Freeze_Perfmon_On_PMI = 1, Counter Overflowed . . . . . . . . . . . . . . . . . .17-15
LBR Stack Size and TOS Pointer Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-15
IA32_DEBUGCTL Flag Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-23
CPL-Qualified Branch Trace Store Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-24
MSR_LASTBRANCH_x_TO_IP for the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-26
MSR_LASTBRANCH_x_FROM_IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-28
MSR_LASTBRANCH_x_TO_IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-28
LBR Stack Size and TOS Pointer Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-28
MSR_LBR_SELECT for Intel microarchitecture code name Nehalem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-28
MSR_LBR_SELECT for Intel® microarchitecture code name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-29
MSR_LBR_SELECT for Intel® microarchitecture code name Haswell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-29
MSR_LASTBRANCH_x_FROM_IP with TSX Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-30
LBR Stack Size and TOS Pointer Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-31
MSR_LBR_INFO_x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-31
LBR MSR Stack Size and TOS Pointer Range for the Pentium® 4 and the Intel® Xeon® Processor Family . . . . . . . . .17-34
Monitoring Supported Event IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-46
Re-indexing of COS Numbers and Mapping to CAT/CDP Mask MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-59
UMask and Event Select Encodings for Pre-Defined Architectural Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Association of Fixed-Function Performance Counters with Architectural Performance Events . . . . . . . . . . . . . . . . . . 18-8
Core Specificity Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-16
Agent Specificity Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-16
HW Prefetch Qualification Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-17
MESI Qualification Definitions within a Non-Architectural Umask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-17
Snoop Type Qualification Definitions within a Non-Architectural Umask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-18
Bus Snoop Qualification Definitions within a Non-Architectural Umask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-18
CONTENTS
PAGE
Table 18-9.
Table 18-10.
Table 18-11.
Table 18-12.
Table 18-13.
Table 18-14.
Table 18-15.
Table 18-16.
Table 18-17.
Table 18-18.
Table 18-19.
Table 18-20.
Table 18-21.
Table 18-22.
Table 18-23.
Table 18-24.
Table 18-25.
Table 18-26.
Table 18-27.
Table 18-28.
Table 18-29.
Table 18-30.
Table 18-31.
Table 18-32.
Table 18-33.
Table 18-34.
Table 18-36.
Table 18-35.
Table 18-37.
Table 18-38.
Table 18-39.
Table 18-41.
Table 18-40.
Table 18-42.
Table 18-43.
Table 18-45.
Table 18-44.
Table 18-46.
Table 18-47.
Table 18-48.
Table 18-50.
Table 18-49.
Table 18-51.
Table 18-52.
Table 18-53.
Table 18-54.
Table 18-55.
Table 18-56.
Table 18-57.
Table 18-58.
Table 18-59.
Table 18-60.
Table 18-61.
Table 18-62.
Table 18-63.
Table 18-64.
Table 18-65.
Table 18-66.
Table 18-67.
Table 18-68.
Table 19-1.
Table 19-2.
Table 19-3.
At-Retirement Performance Events for Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
PEBS Performance Events for Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
Requirements to Program PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23
PEBS Performance Events for the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25
PEBS Record Format for the Silvermont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26
OffCore Response Event Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26
MSR_OFFCORE_RSPx Request_Type Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27
MSR_OFFCORE_RSP_x Response Supplier Info Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28
MSR_OFFCORE_RSPx Snoop Info Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29
Core PMU Comparison Between the Goldmont and Silvermont Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30
Precise Events Supported by the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-31
PEBS Record Format for the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32
MSR_OFFCORE_RSPx Request_Type Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34
MSR_OFFCORE_RSPx For L2 Miss and Outstanding Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34
PEBS Record Format for Intel Core i7 Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38
Data Source Encoding for Load Latency Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41
Off-Core Response Event Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42
MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 Bit Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42
Opcode Field Encoding for MSR_UNCORE_ADDR_OPCODE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-48
Uncore PMU MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49
Uncore PMU MSR Summary for Intel® Xeon® Processor E7 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50
Core PMU Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51
PEBS Facility Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54
PEBS Performance Events for Intel® Microarchitecture Code Name Sandy Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56
Layout of Data Source Field of Load Latency Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-57
Layout of Precise Store Information In PEBS Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58
MSR_OFFCORE_RSP_x Request_Type Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-59
Off-Core Response Event Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-59
MSR_OFFCORE_RSP_x Response Supplier Info Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60
MSR_OFFCORE_RSP_x Snoop Info Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61
Uncore PMU MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63
Uncore PMU MSR Summary for Intel® Xeon® Processor E5 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-64
MSR_OFFCORE_RSP_x Supplier Info Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-64
Core PMU Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-65
PEBS Facility Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66
Precise Events That Supports Data Linear Address Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-67
PEBS Record Format for 4th Generation Intel Core Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-67
Layout of Data Linear Address Information In PEBS Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-68
MSR_OFFCORE_RSP_x Request_Type Definition (Haswell microarchitecture). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-69
MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature 06_3CH, 06_46H). . . . . . . . . . . . . . . . . . . . . . 18-69
MSR_OFFCORE_RSP_x Supplier Info Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70
MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature 06_45H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70
TX Abort Information Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-72
Uncore PMU MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-73
Core PMU Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-75
PEBS Facility Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-76
PEBS Record Format for 6th Generation Intel Core Processor and 7th Generation Intel Core Processor Families 18-77
Precise Events for the Skylake and Kaby Lake Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78
Layout of Data Linear Address Information In PEBS Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-79
FrontEnd_Retired Sub-Event Encodings Supported by MSR_PEBS_FRONTEND.EVTSEL . . . . . . . . . . . . . . . . . . . . . . . . 18-79
MSR_PEBS_FRONTEND Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80
MSR_OFFCORE_RSP_x Request_Type Definition (Skylake and Kaby Lake Microarchitectures) . . . . . . . . . . . . . . . . . 18-80
MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature 06_4EH, 06_5EH and 06_8EH, 06_9EH) 18-81
MSR_OFFCORE_RSP_x Snoop Info Field Definition (CPUID Signature 06_4EH, 06_5EH and 06_8EH, 06_9E). . . . 18-82
Performance Counter MSRs and Associated CCCR and ESCR MSRs (Processors Based on Intel NetBurst
Microarchitecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-83
Event Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-90
CCR Names and Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-95
Effect of Logical Processor and CPL Qualification for Logical-Processor-Specific (TS) Events . . . . . . . . . . . . . . . . . .18-103
Effect of Logical Processor and CPL Qualification for Non-logical-Processor-specific (TI) Events . . . . . . . . . . . . . . .18-104
Nominal Core Crystal Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-107
Architectural Performance Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Fixed-Function Performance Counter and Pre-defined Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Non-Architectural Performance Events of the Processor Core Supported by Skylake Microarchitecture and Kaby
Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
Vol. 3A xlv
CONTENTS
PAGE
Table 19-4.
Table 19-5.
Table 19-6.
Table 19-7.
Table 19-8.
Table 19-9.
Table 19-10.
Table 19-11.
Table 19-12.
Table 19-13.
Table 19-14.
Table 19-15.
Table 19-16.
Table 19-17.
Table 19-18.
Table 19-19.
Table 19-20.
Table 19-21.
Table 19-22.
Table 19-23.
Table 19-24.
Table 19-25.
Table 19-26.
Table 19-27.
Table 19-28.
Table 19-29.
Table 19-30.
Table 19-32.
Table 19-33.
Table 19-31.
Table 19-34.
Table 19-35.
Table 19-36.
Table 19-37.
Table 19-38.
Table 20-1.
Table 20-2.
Table 21-1.
Table 22-1.
Table 22-3.
Table 22-2.
Table 22-4.
Table 22-5.
Table 22-6.
Table 22-7.
Table 22-8.
Table 22-9.
Table 22-10.
Table 24-1.
Table 24-2.
Table 24-3.
Table 24-4.
Table 24-5.
Table 24-6.
Table 24-7.
xlvi Vol. 3A
Intel® TSX Performance Event Addendum in Processors based on Skylake Microarchitecture. . . . . . . . . . . . . . . . . . .19-13
Non-Architectural Performance Events of the Processor Core Supported by Broadwell Microarchitecture . . . . . .19-13
Intel® TSX Performance Event Addendum in Processors Based on Broadwell Microarchitecture . . . . . . . . . . . . . . . .19-21
Non-Architectural Performance Events in the Processor Core of 4th Generation Intel® Core™ Processors . . . . . . .19-22
Intel TSX Performance Events in Processors Based on Haswell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-30
Non-Architectural Uncore Performance Events in the 4th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . .19-32
Non-Architectural Performance Events Applicable only to the Processor Core of Intel® Xeon® Processor E5 v3
Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-33
Non-Architectural Performance Events In the Processor Core of 3rd Generation Intel® Core™ i7, i5, i3 Processors19-34
Non-Architectural Performance Events Applicable Only to the Processor Core of Intel® Xeon® Processor E5 v2 Family
and Intel® Xeon® Processor E7 v2 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-43
Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™ i7-2xxx,
Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family . . . . . .19-43
Non-Architectural Performance Events applicable only to the Processor core for 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-53
Non-Architectural Performance Events Applicable only to the Processor Core of Intel® Xeon® Processor E5 Family19-55
Non-Architectural Performance Events In the Processor Uncore for 2nd Generation Intel® Core™ i7-2xxx, Intel®
Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-56
Non-Architectural Performance Events In the Processor Core for Intel® Core™ i7 Processor and Intel® Xeon®
Processor 5500 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-57
Non-Architectural Performance Events In the Processor Uncore for Intel® Core™ i7 Processor and Intel® Xeon®
Processor 5500 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-74
Non-Architectural Performance Events In the Processor Core for Processors Based on Intel® Microarchitecture
Code Name Westmere . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-86
Non-Architectural Performance Events In the Processor Uncore for Processors Based on Intel® Microarchitecture
Code Name Westmere . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-103
Non-Architectural Performance Events for Processors Based on Enhanced Intel Core Microarchitecture . . . . . . 19-118
Fixed-Function Performance Counter and Pre-defined Performance Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-118
Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . 19-119
Non-Architectural Performance Events for the Goldmont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-143
Performance Events for Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-149
Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . 19-154
Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors . . . . . . . . . . . . . . . . . 19-168
Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture for Non-Retirement Counting19-173
Performance Monitoring Events For Intel NetBurst® Microarchitecture for At-Retirement Counting . . . . . . . . . . 19-191
Intel NetBurst® Microarchitecture Model-Specific Performance Monitoring Events (For Model Encoding 3, 4 or 6)19-195
List of Metrics Available for Execution Tagging (For Execution Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-196
List of Metrics Available for Replay Tagging (For Replay Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-196
List of Metrics Available for Front_end Tagging (For Front_end Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-196
Event Mask Qualification for Logical Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-198
Performance Monitoring Events on Intel® Pentium® M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-203
Performance Monitoring Events Modified on Intel® Pentium® M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-204
Events That Can Be Counted with the P6 Family Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . 19-205
Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . 19-214
Real-Address Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Software Interrupt Handling Methods While in Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-17
Characteristics of 16-Bit and 32-Bit Program Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
New Instruction in the Pentium Processor and Later IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
EM and MP Flag Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-16
Recommended Values of the EM, MP, and NE Flags for Intel486 SX Microprocessor/Intel 487 SX Math
Coprocessor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-16
Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment . . . . . . . . . . .22-21
Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception . . . . . . . . . . . . . . . . . . . . . . . . .22-22
Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception . . . . . . . . . . . . . . . . .22-23
Exception Conditions for SIMD/MMX Instructions with Memory Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-24
Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-25
Exception Conditions for Legacy SIMD/MMX Instructions without Memory Reference . . . . . . . . . . . . . . . . . . . . . . . . .22-26
Processor State Following Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors. . . . . . . . . .22-36
Format of the VMCS Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
Format of Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
Format of Interruptibility State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
Format of Pending-Debug-Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
Definitions of Pin-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Definitions of Primary Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Definitions of Secondary Processor-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-11
CONTENTS
PAGE
Table 24-8.
Table 24-9.
Table 24-10.
Table 24-11.
Table 24-12.
Table 24-13.
Table 24-14.
Table 24-15.
Table 24-16.
Table 24-17.
Table 25-1.
Table 27-1.
Table 27-2.
Table 27-3.
Table 27-4.
Table 27-5.
Table 27-6.
Table 27-7.
Table 27-8.
Table 27-9.
Table 27-10.
Table 27-11.
Table 27-12.
Table 27-13.
Table 27-14.
Table 28-1.
Table 28-2.
Table 28-3.
Table 28-4.
Table 28-5.
Table 28-6.
Table 29-1.
Table 30-1.
Table 31-1.
Table 34-1.
Table 34-2.
Table 34-3.
Table 34-4.
Table 34-5.
Table 34-6.
Table 34-7.
Table 34-8.
Table 34-9.
Table 34-10.
Table 35-1.
Table 35-2.
Table 35-3.
Table 35-4.
Table 35-5.
Table 35-6.
Table 35-7.
Table 35-8.
Table 35-9.
Table 35-10.
Table 35-11.
Table 35-12.
Table 35-13.
Table 35-14.
Table 35-15.
Table 35-16.
Table 35-17.
Table 35-18.
Table 35-19.
Format of Extended-Page-Table Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
Definitions of VM-Function Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
Definitions of VM-Exit Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17
Format of an MSR Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18
Definitions of VM-Entry Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
Format of the VM-Entry Interruption-Information Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
Format of Exit Reason . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21
Format of the VM-Exit Interruption-Information Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22
Format of the IDT-Vectoring Information Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23
Structure of VMCS Component Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25
Format of the Virtualization-Exception Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
Exit Qualification for Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
Exit Qualification for Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
Exit Qualification for Control-Register Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
Exit Qualification for MOV DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
Exit Qualification for I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
Exit Qualification for APIC-Access VM Exits from Linear Accesses and Guest-Physical Accesses. . . . . . . . . . . . . . . . . 27-8
Exit Qualification for EPT Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9
Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14
Format of the VM-Exit Instruction-Information Field as Used for INVEPT, INVPCID, and INVVPID . . . . . . . . . . . . . . . 27-15
Format of the VM-Exit Instruction-Information Field as Used for LIDT, LGDT, SIDT, or SGDT. . . . . . . . . . . . . . . . . . . . 27-16
Format of the VM-Exit Instruction-Information Field as Used for LLDT, LTR, SLDT, and STR. . . . . . . . . . . . . . . . . . . . 27-17
Format of the VM-Exit Instruction-Information Field as Used for RDRAND and RDSEED. . . . . . . . . . . . . . . . . . . . . . . . 27-18
Format of the VM-Exit Instruction-Information Field as Used for VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS,
and XSAVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18
Format of the VM-Exit Instruction-Information Field as Used for VMREAD and VMWRITE . . . . . . . . . . . . . . . . . . . . . . 27-19
Format of an EPT PML4 Entry (PML4E) that References an EPT Page-Directory-Pointer Table . . . . . . . . . . . . . . . . . . 28-3
Format of an EPT Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page . . . . . . . . . . . . . . . . . . . . . 28-5
Format of an EPT Page-Directory-Pointer-Table Entry (PDPTE) that References an EPT Page Directory . . . . . . . . . 28-6
Format of an EPT Page-Directory Entry (PDE) that Maps a 2-MByte Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
Format of an EPT Page-Directory Entry (PDE) that References an EPT Page Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
Format of an EPT Page-Table Entry that Maps a 4-KByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
Format of Posted-Interrupt Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
VM-Instruction Error Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-29
Operating Modes for Host and Guest Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12
SMRAM State Save Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5
Processor Signatures and 64-bit SMRAM State Save Map Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6
SMRAM State Save Map for Intel 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7
Processor Register Initialization in SMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9
I/O Instruction Information in the SMM State Save Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-12
I/O Instruction Type Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-12
Auto HALT Restart Flag Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-14
I/O Instruction Restart Field Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-15
Exit Qualification for SMIs That Arrive Immediately After the Retirement of an I/O Instruction. . . . . . . . . . . . . . . . . 34-20
Format of MSEG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-25
CPUID Signature Values of DisplayFamily_DisplayModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1
IA-32 Architectural MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
MSRs in Processors Based on Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-43
MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-57
MSRs Supported by Intel® Atom™ Processors with CPUID Signature 06_27H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-67
MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors. . 35-68
MSRs Common to the Silvermont and Airmont Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-76
Specific MSRs Supported by Intel® Atom™ Processors with CPUID Signatures 06_37H, 06_4AH, 06_5AH,
06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-80
Specific MSRs Supported by Intel® Atom™ Processor E3000 Series with CPUID Signature 06_37H . . . . . . . . . . . . . 35-82
Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH . . . . . . . . . . . . . 35-82
MSRs in Intel Atom Processors Based on the Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-84
MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . 35-86
MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-107
Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-124
Additional MSRs in Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-126
Additional MSRs Supported by Intel Processors (Based on Intel® Microarchitecture Code Name Westmere) . . . .35-140
Additional MSRs Supported by Intel® Xeon® Processor E7 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-141
MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge . . . . . . . . . . . . .35-143
MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge)35-162
Vol. 3A xlvii
CONTENTS
PAGE
Table 35-20.
Table 35-21.
Table 35-22.
Table 35-23.
Table 35-24.
Table 35-25.
Table 35-26.
Table 35-27.
Table 35-28.
Table 35-29.
Table 35-30.
Table 35-31.
Table 35-32.
Table 35-33.
Table 35-34.
Table 35-35.
Table 35-36.
Table 35-37.
Table 35-38.
Table 35-39.
Table 35-40.
Table 35-41.
Table 35-42.
Table 35-43.
Table 35-44.
Table 35-45.
Table 35-46.
Table 35-47.
Table 36-1.
Table 36-2.
Table 36-3.
Table 36-4.
Table 36-5.
Table 36-6.
Table 36-7.
Table 36-9.
Table 36-8.
Table 36-10.
Table 36-11.
Table 36-12.
Table 36-13.
Table 36-14.
Table 36-15.
Table 36-16.
Table 36-17.
Table 36-18.
Table 36-19.
Table 36-20.
Table 36-21.
Table 36-22.
Table 36-23.
Table 36-24.
Table 36-25.
Table 36-26.
Table 36-27.
Table 36-28.
Table 36-29.
Table 36-30.
Table 36-31.
Table 36-32.
Table 36-33.
xlviii Vol. 3A
Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-163
Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) . . 35-166
Uncore PMU MSRs in Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-169
Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name
Ivy Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-172
MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) . 35-176
Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel Signature
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-183
Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-186
Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures . . . . . . . . . . . . 35-188
MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) . . . . . . . . . . . . . . . . . . . . 35-193
Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with
DisplayFamily_DisplayModel Signature 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-204
Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-206
Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-215
Additional MSRs Common to Processors Based the Broadwell Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-223
Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors . . . . . . . . 35-225
Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the
Broadwell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-227
Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H . . . . . . . . . . 35-236
Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH . . . . . . . . . . . 35-238
Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake Microarchitecture . . 35-241
Uncore PMU MSRs Supported by 6th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-259
Machine Check MSRs Supported by Future Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_55H 35-261
Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 06_57H35-264
MSRs in the Pentium® 4 and Intel® Xeon® Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-277
MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-302
MSRs Unique to Intel® Xeon® Processor 7100 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-303
MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV . . . . . . . . . . . . . 35-303
MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-312
MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-319
MSRs in the Pentium Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-328
COFI Type for Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2
IP Filtering Packet Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
ToPA Table Entry Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-11
Algorithm to Manage Intel PT ToPA PMI and XSAVES/XRSTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-14
Behavior on Restricted Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-15
IA32_RTIT_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-16
IA32_RTIT_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-20
IA32_RTIT_OUTPUT_MASK_PTRS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-22
IA32_RTIT_OUTPUT_BASE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-22
TSX Packet Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-23
CPUID Leaf 14H Enumeration of Intel Processor Trace Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-26
CPUID Leaf 14H, sub-leaf 1H Enumeration of Intel Processor Trace Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-28
Memory Layout of the Trace Configuration State Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-31
An Illustrative CYC Packet Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-33
Compound Packet Event Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-36
TNT Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-36
IP Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-38
FUP/TIP IP Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-39
TNT Examples with Deferred TIPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-40
TIP.PGE Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-41
TIP.PGD Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-42
FUP Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-43
FUP Cases and IP Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-44
PIP Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-45
General Form of MODE Packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-46
MODE.Exec Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-46
MODE.TSX Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-47
TraceStop Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-48
CBR Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-48
TSC Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-49
MTC Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-50
TMA Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-51
Cycle Count Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-52
CONTENTS
PAGE
Table 36-34.
Table 36-35.
Table 36-36.
Table 36-37.
Table 36-38.
Table 36-39.
Table 36-40.
Table 36-41.
Table 36-42.
Table 36-43.
Table 36-44.
Table 36-46.
Table 36-45.
Table 36-47.
Table 36-48.
Table 36-49.
Table 36-50.
Table 36-51.
Table 36-52.
Table 37-1.
Table 37-2.
Table 37-3.
Table 37-4.
Table 37-5.
Table 37-6.
Table 38-1.
Table 38-2.
Table 38-3.
Table 38-4.
Table 38-5.
Table 38-6.
Table 38-7.
Table 38-8.
Table 38-10.
Table 38-9.
Table 38-11.
Table 38-12.
Table 38-13.
Table 38-14.
Table 38-15.
Table 38-16.
Table 38-17.
Table 38-18.
Table 38-19.
Table 38-21.
Table 38-20.
Table 38-22.
Table 38-23.
Table 38-24.
Table 38-25.
Table 38-26.
Table 38-27.
Table 39-1.
Table 40-1.
Table 41-1.
Table 41-2.
Table 41-3.
Table 41-4.
Table 41-5.
Table 41-6.
Table 41-7.
Table 41-8.
Table 41-9.
Table 41-10.
Table 41-11.
VMCS Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-53
OVF Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-54
PSB Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-54
PSBEND Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-55
MNT Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-56
PAD Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-56
PTW Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-57
EXSTOP Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-58
MWAIT Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-59
PWRE Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-60
PWRX Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-61
VMCS Controls For Intel Processor Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-62
Common Usages of Intel PT and VMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-62
Packets on VMX Transitions (System-Wide Tracing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-63
Packets on VMX Transitions (Host-Only Tracing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-64
Packets on a Failed VM Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-65
Packet Generation under Different Enable Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-65
PwrEvtEn and PTWEn Packet Generation under Different Enable Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-74
PwrEvtEn and PTWEn Packet Generation under Different Enable Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-78
Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1 . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3
Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX2 . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4
Intel® SGX Opt-in and Enabling Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4
CPUID Leaf 12H, Sub-Leaf 0 Enumeration of Intel® SGX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5
CPUID Leaf 12H, Sub-Leaf 1 Enumeration of Intel® SGX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5
CPUID Leaf 12H, Sub-Leaf Index 2 or Higher Enumeration of Intel® SGX Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-6
List of Implicit and Explicit Memory Access by Intel® SGX Enclave Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3
Layout of SGX Enclave Control Structure (SECS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4
Layout of ATTRIBUTES Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5
Bit Vector Layout of MISCSELECT Field of Extended Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6
Layout of Thread Control Structure (TCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6
Layout of TCS.FLAGS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6
Top-to-Bottom Layout of an SSA Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7
Layout of GPRSGX Portion of the State Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8
Exception Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-9
Layout of EXITINFO Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-9
Layout of MISC region of the State Save Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-10
Layout of EXINFO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-10
Page Fault Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-10
Layout of PAGEINFO Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11
Layout of SECINFO Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11
Layout of SECINFO.FLAGS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11
Supported PAGE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-12
Layout of PCMD Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-12
Layout of Enclave Signature Structure (SIGSTRUCT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-13
Layout of REPORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14
Layout of EINIT Token (EINITTOKEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14
Layout of TARGETINFO Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-15
Layout of KEYREQUEST Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-15
Supported KEYName Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16
Layout of KEYPOLICY Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16
Layout of Version Array Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16
Content of an Enclave Page Cache Map Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-17
Illegal Instructions Inside an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-13
GPR, x87 Synthetic States on Asynchronous Enclave Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
Register Usage of Privileged Enclave Instruction Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1
Register Usage of Unprivileged Enclave Instruction Leaf Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2
Error or Information Codes for Intel® SGX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2
List of Internal CREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3
Concurrency Restrictions of EADD with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-11
Concurrency Restrictions of EADD with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-12
Concurrency Restrictions of EAUG with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-15
Concurrency Restrictions of EAUG with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-16
EBLOCK Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18
Concurrency Restrictions of EBLOCK with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18
Concurrency Restrictions of EBLOCK with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-19
Vol. 3A xlix
CONTENTS
PAGE
Table 41-12.
Table 41-13.
Table 41-14.
Table 41-15.
Table 41-16.
Table 41-17.
Table 41-18.
Table 41-19.
Table 41-20.
Table 41-21.
Table 41-22.
Table 41-23.
Table 41-24.
Table 41-25.
Table 41-26.
Table 41-27.
Table 41-28.
Table 41-29.
Table 41-30.
Table 41-31.
Table 41-32.
Table 41-33.
Table 41-34.
Table 41-35.
Table 41-36.
Table 41-37.
Table 41-38.
Table 41-39.
Table 41-40.
Table 41-41.
Table 41-42.
Table 41-43.
Table 41-44.
Table 41-45.
Table 41-46.
Table 41-47.
Table 41-48.
Table 41-49.
Table 41-50.
Table 41-51.
Table 41-52.
Table 41-53.
Table 41-54.
Table 41-55.
Table 41-56.
Table 41-57.
Table 41-58.
Table 41-59.
Table 41-60.
Table 41-61.
Table 41-62.
Table 41-63.
Table 41-64.
Table 41-65.
Table 42-1.
Table 42-2.
Table A-1.
Table B-1.
Table B-2.
Table B-3.
Table B-4.
Table B-5.
Table B-6.
Table B-7.
Table B-8.
l Vol. 3A
Concurrency Restrictions of ECREATE with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-21
Concurrency Restrictions of ECREATE with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-21
EDBGRD Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-25
Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-26
Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-26
EDBGWR Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-28
Concurrency Restrictions of EDBGWR with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-29
Concurrency Restrictions of EDBGWR with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-29
Concurrency Restrictions of EEXTEND with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-31
Concurrency Restrictions of EEXTEND with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-32
EINIT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-35
Concurrency Restrictions of EINIT with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-36
Concurrency Restrictions of EINIT with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-36
ELDB/ELDU Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-41
Concurrency Restrictions of ELDB/ELDU with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-41
Concurrency Restrictions of ELDB/ELDU with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-42
EMODPR Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-46
Concurrency Restrictions of EMODPR with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-46
Concurrency Restrictions of EMODPR with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-47
EMODT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-49
Concurrency Restrictions of EMODT with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-49
Concurrency Restrictions of EMODT with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-50
Concurrency Restrictions of EPA with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-52
Concurrency Restrictions of EPA with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-52
EREMOVE Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-54
Concurrency Restrictions of EREMOVE with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-55
Concurrency Restrictions of EREMOVE with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-55
ETRACK Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-57
Concurrency Restrictions of ETRACK with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-57
Concurrency Restrictions of ETRACK with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-57
ETRACK Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-58
EWB Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-59
Concurrency Restrictions of EWB with Intel® SGX Instructions - 1of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-59
Concurrency Restrictions of EWB with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-59
EACCEPT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-65
Concurrency Restrictions of EACCEPT with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-65
Concurrency Restrictions of EACCEPT with Intel® SGX Instructions - 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-66
EACCEPTCOPY Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-69
Concurrency Restrictions of EACCEPTCOPY with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-70
Concurrency Restrictions of EACCEPTCOPY with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-70
Concurrency Restrictions of EENTER with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-74
Concurrency Restrictions of EENTER with Intel® SGX Instructions - 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-74
Concurrency Restrictions of EEXIT with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-81
Concurrency Restrictions of EEXIT with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-81
Key Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-85
EGETKEY Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-85
Concurrency Restrictions of EGETKEY with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-85
Concurrency Restrictions of EGETKEY with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-86
Concurrency Restrictions of EMODPE with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-92
Concurrency Restrictions of EMODPE with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-92
Concurrency Restrictions of EREPORT with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-96
Concurrency Restrictions of EREPORT with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41-96
Concurrency Restrictions of ERESUME with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-100
Concurrency Restrictions of ERESUME with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-100
SMRAM Synthetic States on Asynchronous Enclave Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9
Layout of the IA32_SGX_SVN_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42-11
Memory Types Recommended for VMCS and Related Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Encoding for 16-Bit Control Fields (0000_00xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Encodings for 16-Bit Guest-State Fields (0000_10xx_xxxx_xxx0B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Encodings for 16-Bit Host-State Fields (0000_11xx_xxxx_xxx0B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Encodings for 64-Bit Control Fields (0010_00xx_xxxx_xxxAb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Encodings for 64-Bit Read-Only Data Field (0010_01xx_xxxx_xxxAb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encodings for 64-Bit Guest-State Fields (0010_10xx_xxxx_xxxAb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encodings for 64-Bit Host-State Fields (0010_11xx_xxxx_xxxAb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Encodings for 32-Bit Control Fields (0100_00xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
CONTENTS
PAGE
Table B-9.
Table B-10.
Table B-11.
Table B-12.
Table B-13.
Table B-14.
Table B-15.
Table C-1.
Encodings for 32-Bit Read-Only Data Fields (0100_01xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-7
Encodings for 32-Bit Guest-State Fields (0100_10xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-7
Encoding for 32-Bit Host-State Field (0100_11xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-8
Encodings for Natural-Width Control Fields (0110_00xx_xxxx_xxx0B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-8
Encodings for Natural-Width Read-Only Data Fields (0110_01xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-9
Encodings for Natural-Width Guest-State Fields (0110_10xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-9
Encodings for Natural-Width Host-State Fields (0110_11xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
Basic Exit Reasons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Vol. 3A li
CONTENTS
PAGE
lii Vol. 3A
CHAPTER 1
ABOUT THIS MANUAL
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide,
Part 1 (order number 253668), the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide, Part 2 (order number 253669) and the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3C: System Programming Guide, Part 3 (order number 326019) are part of a set that
describes the architecture and programming environment of Intel 64 and IA-32 Architecture processors. The other
volumes in this set are:
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number
253665).
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set
Reference (order numbers 253666, 253667, 326018 and 334569).
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture
and programming environment of Intel 64 and IA-32 processors. The Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volumes 2A, 2B, 2C & 2D, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers who write operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D, describe
the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operatingsystem and BIOS designers. In addition, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
3B, and Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C address the programming
environment for classes of software that host operating systems.
1.1
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL
This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which
include:
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Pentium® processors
P6 family processors
Pentium® 4 processors
Pentium® M processors
Intel® Xeon® processors
Pentium® D processors
Pentium® processor Extreme Editions
64-bit Intel® Xeon® processors
Intel® Core™ Duo processor
Intel® Core™ Solo processor
Dual-Core Intel® Xeon® processor LV
Intel® Core™2 Duo processor
Intel® Core™2 Quad processor Q6000 series
Intel® Xeon® processor 3000, 3200 series
Intel® Xeon® processor 5000 series
Intel® Xeon® processor 5100, 5300 series
Intel® Core™2 Extreme processor X7000 and X6800 series
Intel® Core™2 Extreme QX6000 series
Intel® Xeon® processor 7100 series
Vol. 3A 1-1
ABOUT THIS MANUAL
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•
•
•
•
•
•
•
Intel® Pentium® Dual-Core processor
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Intel® Core™ i7 processor
Intel® Xeon® processor 7200, 7300 series
Intel® Core™2 Extreme QX9000 series
Intel® Xeon® processor 5200, 5400, 7400 series
Intel® Core™2 Extreme processor QX9000 and X9000 series
Intel® Core™2 Quad processor Q9000 series
Intel® Core™2 Duo processor E8000, T9000 series
Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are built from 45 nm and 32 nm processes.
Intel® Core™ i5 processor
Intel® Xeon® processor E7-8800/4800/2800 product families
Intel® Core™ i7-3930K processor
2nd generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series
Intel® Xeon® processor E3-1200 product family
Intel® Xeon® processor E5-2400/1400 product family
Intel® Xeon® processor E5-4600/2600/1600 product family
3rd generation Intel® Core™ processors
Intel® Xeon® processor E3-1200 v2 product family
Intel® Xeon® processor E5-2400/1400 v2 product families
Intel® Xeon® processor E5-4600/2600/1600 v2 product families
Intel® Xeon® processor E7-8800/4800/2800 v2 product families
4th generation Intel® Core™ processors
The Intel® Core™ M processor family
Intel® Core™ i7-59xx Processor Extreme Edition
Intel® Core™ i7-49xx Processor Extreme Edition
Intel® Xeon® processor E3-1200 v3 product family
Intel® Xeon® processor E5-2600/1600 v3 product families
5th generation Intel® Core™ processors
Intel® Xeon® processor D-1500 product family
Intel® Xeon® processor E5 v4 family
Intel® Atom™ processor X7-Z8000 and X5-Z8000 series
Intel® Atom™ processor Z3400 series
Intel® Atom™ processor Z3500 series
6th generation Intel® Core™ processors
Intel® Xeon® processor E3-1500m v5 product family
P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium®
Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors.
The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microarchitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture. Intel Xeon
processor 5000, 7100 series are based on the Intel NetBurst® microarchitecture.
The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LV are based on an improved
Pentium® M processor microarchitecture.
1-2 Vol. 3A
ABOUT THIS MANUAL
The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel® Pentium® dual-core, Intel®
Core™2 Duo, Intel® Core™2 Quad and Intel® Core™2 Extreme processors are based on Intel® Core™ microarchitecture.
The Intel® Xeon® processor 5200, 5400, 7400 series, Intel® Core™2 Quad processor Q9000 series, and Intel®
Core™2 Extreme processors QX9000, X9000 series, Intel® Core™2 processor E8000 series are based on Enhanced
Intel® Core™ microarchitecture.
The Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are based on the Intel® Atom™ microarchitecture and supports Intel 64 architecture.
The Intel® Core™ i7 processor and Intel® Xeon® processor 3400, 5500, 7500 series are based on 45 nm Intel®
microarchitecture code name Nehalem. Intel® microarchitecture code name Westmere is a 32 nm version of Intel®
microarchitecture code name Nehalem. Intel® Xeon® processor 5600 series, Intel Xeon processor E7 and various
Intel Core i7, i5, i3 processors are based on Intel® microarchitecture code name Westmere. These processors
support Intel 64 architecture.
The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor E78800/4800/2800 product families, Intel® Core™ i7-3930K processor, and 2nd generation Intel® Core™ i7-2xxx,
Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series are based on the Intel® microarchitecture code
name Sandy Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E7-8800/4800/2800 v2 product families, Intel® Xeon® processor E3-1200 v2 product
family and 3rd generation Intel® Core™ processors are based on the Intel® microarchitecture code name Ivy
Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E5-4600/2600/1600 v2 product families, Intel® Xeon® processor E5-2400/1400 v2
product families and Intel® Core™ i7-49xx Processor Extreme Edition are based on the Intel® microarchitecture
code name Ivy Bridge-E and support Intel 64 architecture.
The Intel® Xeon® processor E3-1200 v3 product family and 4th Generation Intel® Core™ processors are based on
the Intel® microarchitecture code name Haswell and support Intel 64 architecture.
The Intel® Core™ M processor family, 5th generation Intel® Core™ processors, Intel® Xeon® processor D-1500
product family and the Intel® Xeon® processor E5 v4 family are based on the Intel® microarchitecture code name
Broadwell and support Intel 64 architecture.
The Intel® Xeon® processor E3-1500m v5 product family and 6th generation Intel® Core™ processors are based
on the Intel® microarchitecture code name Skylake and support Intel 64 architecture.
The Intel® Xeon® processor E5-2600/1600 v3 product families and the Intel® Core™ i7-59xx Processor Extreme
Edition are based on the Intel® microarchitecture code name Haswell-E and support Intel 64 architecture.
The Intel® Atom™ processor Z8000 series is based on the Intel microarchitecture code name Airmont.
The Intel® Atom™ processor Z3400 series and the Intel® Atom™ processor Z3500 series are based on the Intel
microarchitecture code name Silvermont.
P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-core Intel® Xeon® processor LV,
and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel® Atom™
processor Z5xx series support IA-32 architecture.
The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel®
Core™2 Duo, Intel® Core™2 Extreme processors, Intel Core 2 Quad processors, Pentium® D processors, Pentium®
Dual-Core processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel® 64 architecture.
IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microprocessors. Intel® 64 architecture is the instruction set architecture and programming environment which is a superset
of and compatible with IA-32 architecture.
1.2
OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE
A description of this manual’s content follows:
Vol. 3A 1-3
ABOUT THIS MANUAL
Chapter 1 — About This Manual. Gives an overview of all eight volumes of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel
manuals and documentation of interest to programmers and hardware designers.
Chapter 2 — System Architecture Overview. Describes the modes of operation used by Intel 64 and IA-32
processors and the mechanisms provided by the architectures to support operating systems and executives,
including the system-oriented registers and data structures and the system-oriented instructions. The steps necessary for switching between real-address and protected modes are also identified.
Chapter 3 — Protected-Mode Memory Management. Describes the data structures, registers, and instructions
that support segmentation and paging. The chapter explains how they can be used to implement a “flat” (unsegmented) memory model or a segmented memory model.
Chapter 4 — Paging. Describes the paging modes supported by Intel 64 and IA-32 processors.
Chapter 5 — Protection. Describes the support for page and segment protection provided in the Intel 64 and IA32 architectures. This chapter also explains the implementation of privilege rules, stack switching, pointer validation, user and supervisor modes.
Chapter 6 — Interrupt and Exception Handling. Describes the basic interrupt mechanisms defined in the Intel
64 and IA-32 architectures, shows how interrupts and exceptions relate to protection, and describes how the architecture handles each exception type. Reference information for each exception is given in this chapter. Includes
programming the LINT0 and LINT1 inputs and gives an example of how to program the LINT0 and LINT1 pins for
specific interrupt vectors.
Chapter 7 — Task Management. Describes mechanisms the Intel 64 and IA-32 architectures provide to support
multitasking and inter-task protection.
Chapter 8 — Multiple-Processor Management. Describes the instructions and flags that support multiple
processors with shared memory, memory ordering, and Intel® Hyper-Threading Technology. Includes MP initialization for P6 family processors and gives an example of how to use the MP protocol to boot P6 family processors in
an MP system.
Chapter 9 — Processor Management and Initialization. Defines the state of an Intel 64 or IA-32 processor
after reset initialization. This chapter also explains how to set up an Intel 64 or IA-32 processor for real-address
mode operation and protected- mode operation, and how to switch between modes.
Chapter 10 — Advanced Programmable Interrupt Controller (APIC). Describes the programming interface
to the local APIC and gives an overview of the interface between the local APIC and the I/O APIC. Includes APIC bus
message formats and describes the message formats for messages transmitted on the APIC bus for P6 family and
Pentium processors.
Chapter 11 — Memory Cache Control. Describes the general concept of caching and the caching mechanisms
supported by the Intel 64 or IA-32 architectures. This chapter also describes the memory type range registers
(MTRRs) and how they can be used to map memory types of physical memory. Information on using the new cache
control and memory streaming instructions introduced with the Pentium III, Pentium 4, and Intel Xeon processors
is also given.
Chapter 12 — Intel® MMX™ Technology System Programming. Describes those aspects of the Intel® MMX™
technology that must be handled and considered at the system programming level, including: task switching,
exception handling, and compatibility with existing system environments.
Chapter 13 — System Programming For Instruction Set Extensions And Processor Extended States.
Describes the operating system requirements to support SSE/SSE2/SSE3/SSSE3/SSE4 extensions, including task
switching, exception handling, and compatibility with existing system environments. The latter part of this chapter
describes the extensible framework of operating system requirements to support processor extended states.
Processor extended state may be required by instruction set extensions beyond those of
SSE/SSE2/SSE3/SSSE3/SSE4 extensions.
Chapter 14 — Power and Thermal Management. Describes facilities of Intel 64 and IA-32 architecture used for
power management and thermal monitoring.
Chapter 15 — Machine-Check Architecture. Describes the machine-check architecture and machine-check
exception mechanism found in the Pentium 4, Intel Xeon, and P6 family processors. Additionally, a signaling mechanism for software to respond to hardware corrected machine check error is covered.
1-4 Vol. 3A
ABOUT THIS MANUAL
Chapter 16 — Interpreting Machine-Check Error Codes. Gives an example of how to interpret the error codes
for a machine-check error that occurred on a P6 family processor.
Chapter 17 — Debug, Branch Profile, TSC, and Resource Monitoring Features. Describes the debugging
registers and other debug mechanism provided in Intel 64 or IA-32 processors. This chapter also describes the
time-stamp counter.
Chapter 18 — Performance Monitoring. Describes the Intel 64 and IA-32 architectures’ facilities for monitoring
performance.
Chapter 19 — Performance-Monitoring Events. Lists architectural performance events. Non-architectural
performance events (i.e. model-specific events) are listed for each generation of microarchitecture.
Chapter 20 — 8086 Emulation. Describes the real-address and virtual-8086 modes of the IA-32 architecture.
Chapter 21 — Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and 32-bit code modules within the
same program or task.
Chapter 22 — IA-32 Architecture Compatibility. Describes architectural compatibility among IA-32 processors.
Chapter 23 — Introduction to Virtual Machine Extensions. Describes the basic elements of virtual machine
architecture and the virtual machine extensions for Intel 64 and IA-32 Architectures.
Chapter 24 — Virtual Machine Control Structures. Describes components that manage VMX operation. These
include the working-VMCS pointer and the controlling-VMCS pointer.
Chapter 25 — VMX Non-Root Operation. Describes the operation of a VMX non-root operation. Processor operation in VMX non-root mode can be restricted programmatically such that certain operations, events or conditions
can cause the processor to transfer control from the guest (running in VMX non-root mode) to the monitor software
(running in VMX root mode).
Chapter 26 — VM Entries. Describes VM entries. VM entry transitions the processor from the VMM running in
VMX root-mode to a VM running in VMX non-root mode. VM-Entry is performed by the execution of VMLAUNCH or
VMRESUME instructions.
Chapter 27 — VM Exits. Describes VM exits. Certain events, operations or situations while the processor is in VMX
non-root operation may cause VM-exit transitions. In addition, VM exits can also occur on failed VM entries.
Chapter 28 — VMX Support for Address Translation. Describes virtual-machine extensions that support
address translation and the virtualization of physical memory.
Chapter 29 — APIC Virtualization and Virtual Interrupts. Describes the VMCS including controls that enable
the virtualization of interrupts and the Advanced Programmable Interrupt Controller (APIC).
Chapter 30 — VMX Instruction Reference. Describes the virtual-machine extensions (VMX). VMX is intended
for a system executive to support virtualization of processor hardware and a system software layer acting as a host
to multiple guest software environments.
Chapter 31 — Virtual-Machine Monitor Programming Considerations. Describes programming considerations for VMMs. VMMs manage virtual machines (VMs).
Chapter 32 — Virtualization of System Resources. Describes the virtualization of the system resources. These
include: debugging facilities, address translation, physical memory, and microcode update facilities.
Chapter 33 — Handling Boundary Conditions in a Virtual Machine Monitor. Describes what a VMM must
consider when handling exceptions, interrupts, error conditions, and transitions between activity states.
Chapter 34 — System Management Mode. Describes Intel 64 and IA-32 architectures’ system management
mode (SMM) facilities.
Chapter 35 — Model-Specific Registers (MSRs). Lists the MSRs available in the Pentium processors, the P6
family processors, the Pentium 4, Intel Xeon, Intel Core Solo, Intel Core Duo processors, and Intel Core 2
processor family and describes their functions.
Chapter 36 — Intel® Processor Trace. Describes details of Intel® Processor Trace.
Chapter 37 — Introduction to Intel® Software Guard Extensions. Provides an overview of the Intel® Software Guard Extensions (Intel® SGX) set of instructions.
Vol. 3A 1-5
ABOUT THIS MANUAL
Chapter 38 — Enclave Access Control and Data Structures. Describes Enclave Access Control procedures and
defines various Intel SGX data structures.
Chapter 39 — Enclave Operation. Describes enclave creation and initialization, adding pages and measuring an
enclave, and enclave entry and exit.
Chapter 40 — Enclave Exiting Events. Describes enclave-exiting events (EEE) and asynchronous enclave exit
(AEX).
Chapter 41 — SGX Instruction References. Describes the supervisor and user level instructions provided by
Intel SGX.
Chapter 42 — Intel® SGX Interactions with IA32 and Intel® 64 Architecture. Describes the Intel SGX
collection of enclave instructions for creating protected execution environments on processors supporting IA32 and
Intel 64 architectures.
Chapter 43 — Enclave Code Debug and Profiling. Describes enclave code debug processes and options.
Appendix A — VMX Capability Reporting Facility. Describes the VMX capability MSRs. Support for specific VMX
features is determined by reading capability MSRs.
Appendix B — Field Encoding in VMCS. Enumerates all fields in the VMCS and their encodings. Fields are
grouped by width (16-bit, 32-bit, etc.) and type (guest-state, host-state, etc.).
Appendix C — VM Basic Exit Reasons. Describes the 32-bit fields that encode reasons for a VM exit. Examples
of exit reasons include, but are not limited to: software interrupts, processor exceptions, software traps, NMIs,
external interrupts, and triple faults.
1.3
NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for
hexadecimal and binary numbers. A review of this notation makes the manual easier to read.
1.3.1
Bit and Byte Order
In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses
increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to
two raised to the power of the bit position. Intel 64 and IA-32 processors are “little endian” machines; this means
the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.
1.3.2
Reserved Bits and Software Compatibility
In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as
reserved, it is essential for compatibility with future processors that software treat these bits as having a future,
though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable. Software should follow these guidelines in dealing with reserved bits:
•
Do not depend on the states of any reserved bits when testing the values of registers which contain such bits.
Mask out the reserved bits before testing.
•
•
•
Do not depend on the states of any reserved bits when storing to memory or to a register.
Do not depend on the ability to retain information written into any reserved bits.
When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or
reload them with values previously read from the same register.
NOTE
Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers.
Depending upon the values of reserved register bits will make software dependent upon the
unspecified manner in which the processor handles these bits. Programs that depend upon
reserved values risk incompatibility with future processors.
1-6 Vol. 3A
ABOUT THIS MANUAL
Highest
31
Address
Data Structure
8 7
24 23
16 15
Byte 3
Byte 2
Byte 1
Bit offset
0
Byte 0
28
24
20
16
12
8
4
0
Lowest
Address
Byte Offset
Figure 1-1. Bit and Byte Order
1.3.3
Instruction Operands
When instructions are represented symbolically, a subset of assembly language is used. In this subset, an instruction has the following format:
label: mnemonic argument1, argument2, argument3
where:
•
•
•
A label is an identifier which is followed by a colon.
A mnemonic is a reserved name for a class of instruction opcodes which have the same function.
The operands argument1, argument2, and argument3 are optional. There may be from zero to three
operands, depending on the opcode. When present, they take the form of either literals or identifiers for data
items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items
declared in another part of the program (which may not be shown in the example).
When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left
operand is the destination.
For example:
LOADREG: MOV EAX, SUBTOTAL
In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,
and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.
1.3.4
Hexadecimal and Binary Numbers
Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for
example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, and F.
Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for
example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might
arise.
1.3.5
Segmented Addressing
The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes.
Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The
range of memory that can be addressed is called an address space.
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ABOUT THIS MANUAL
The processor also supports segmented addressing. This is a form of addressing where a program may have many
independent address spaces, called segments. For example, a program can keep its code (instructions) and stack
in separate segments. Code addresses would always refer to the code space, and stack addresses would always
refer to the stack space. The following notation is used to specify a byte address within a segment:
Segment-register:Byte-address
For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS
register:
DS:FF79H
The following segment address identifies an instruction address in the code segment. The CS register points to the
code segment and the EIP register contains the address of the instruction.
CS:EIP
1.3.6
Syntax for CPUID, CR, and MSR Values
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a single syntax to represent this type of information. See Figure 1-2.
CPUID Input and Output
CPUID.01H:ECX.SSE[bit 25] = 1
Input value for EAX register
Output register and feature flag or field
name with bit position(s)
Value (or range) of output
Control Register Values
CR4.OSFXSR[bit 9] = 1
Example CR name
Feature flag or field name
with bit position(s)
Value (or range) of output
Model-Specific Register Values
IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1
Example MSR name
Feature flag or field name with bit position(s)
Value (or range) of output
SDM20002
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation
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1.3.7
Exceptions
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the
error. An example of the notation used to show an exception and error code is shown below:
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is
reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate
code. In this case, the error code is zero, as shown below for a general-protection exception:
#GP(0)
1.4
RELATED LITERATURE
Literature related to Intel 64 and IA-32 processors is listed and viewable on-line at:
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
See also:
•
•
•
The data sheet for a particular Intel 64 or IA-32 processor
•
Intel® Fortran Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
•
Intel® Software Development Tools:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual (in three or seven volumes):
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
•
Intel® 64 and IA-32 Architectures Optimization Reference Manual:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimizationmanual.html
•
Intel 64 Architecture x2APIC Specification:
The specification update for a particular Intel 64 or IA-32 processor
Intel® C++ Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
http://www.intel.com/content/www/us/en/architecture-and-technology/64-architecture-x2apic-specification.html
•
Intel® Trusted Execution Technology Measured Launched Environment Programming Guide:
http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html
•
Developing Multi-threaded Applications: A Platform Consistent Approach:
https://software.intel.com/sites/default/files/article/147714/51534-developing-multithreaded-applications.pdf
•
Using Spin-Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor:
http://software.intel.com/en-us/articles/ap949-using-spin-loops-on-intel-pentiumr-4-processor-and-intelxeonr-processor/
•
Performance Monitoring Unit Sharing Guide
http://software.intel.com/file/30388
Literature related to selected features in future Intel processors are available at:
•
Intel® Architecture Instruction Set Extensions Programming Reference
https://software.intel.com/en-us/isa-extensions
•
Intel® Software Guard Extensions (Intel® SGX) Programming Reference
https://software.intel.com/en-us/isa-extensions/intel-sgx
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More relevant links are:
•
Intel® Developer Zone:
https://software.intel.com/en-us
•
Developer centers:
http://www.intel.com/content/www/us/en/hardware-developers/developer-centers.html
•
Processor support general link:
http://www.intel.com/support/processors/
•
Software products and packages:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® Hyper-Threading Technology (Intel® HT Technology):
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm
1-10 Vol. 3A
CHAPTER 2
SYSTEM ARCHITECTURE OVERVIEW
IA-32 architecture (beginning with the Intel386 processor family) provides extensive support for operating-system
and system-development software. This support offers multiple modes of operation, which include:
•
Real mode, protected mode, virtual 8086 mode, and system management mode. These are sometimes
referred to as legacy modes.
Intel 64 architecture supports almost all the system programming facilities available in IA-32 architecture and
extends them to a new operating mode (IA-32e mode) that supports a 64-bit programming environment. IA-32e
mode allows software to operate in one of two sub-modes:
•
•
64-bit mode supports 64-bit OS and 64-bit applications
Compatibility mode allows most legacy software to run; it co-exists with 64-bit applications under a 64-bit OS.
The IA-32 system-level architecture includes features to assist in the following operations:
•
•
•
•
•
•
•
•
Memory management
Protection of software modules
Multitasking
Exception and interrupt handling
Multiprocessing
Cache management
Hardware resource and power management
Debugging and performance monitoring
This chapter provides a description of each part of this architecture. It also describes the system registers that are
used to set up and control the processor at the system level and gives a brief overview of the processor’s systemlevel (operating system) instructions.
Many features of the system-level architecture are used only by system programmers. However, application
programmers may need to read this chapter and the following chapters in order to create a reliable and secure
environment for application programs.
This overview and most subsequent chapters of this book focus on protected-mode operation of the IA-32 architecture. IA-32e mode operation of the Intel 64 architecture, as it differs from protected mode operation, is also
described.
All Intel 64 and IA-32 processors enter real-address mode following a power-up or reset (see Chapter 9, “Processor
Management and Initialization”). Software then initiates the switch from real-address mode to protected mode. If
IA-32e mode operation is desired, software also initiates a switch from protected mode to IA-32e mode.
2.1
OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE
System-level architecture consists of a set of registers, data structures, and instructions designed to support basic
system-level operations such as memory management, interrupt and exception handling, task management, and
control of multiple processors.
Figure 2-1 provides a summary of system registers and data structures that applies to 32-bit modes. System registers and data structures that apply to IA-32e mode are shown in Figure 2-2.
Vol. 3A 2-1
SYSTEM ARCHITECTURE OVERVIEW
Physical Address
EFLAGS Register
Control Registers
CR4
CR3
CR2
CR1
CR0
Task Register
Interrupt
Vector
Code, Data or
Stack Segment
Linear Address
Task-State
Segment (TSS)
Segment Selector
Register
Global Descriptor
Table (GDT)
Segment Sel.
Seg. Desc.
TSS Seg. Sel.
TSS Desc.
Interrupt Handler
Code
Current
Stack
TSS
Seg. Desc.
Interrupt Descriptor
Table (IDT)
Task-State
Segment (TSS)
TSS Desc.
Interrupt Gate
LDT Desc.
Task Gate
Task
Code
Data
Stack
GDTR
Trap Gate
IDTR
Task
Code
Data
Stack
Local Descriptor
Table (LDT)
Call-Gate
Segment Selector
Seg. Desc.
Call Gate
XCR0 (XFEM)
Protected Procedure
Code
Current
Stack
TSS
LDTR
Linear Address Space
Dir
Linear Addr.
0
CR3*
Exception Handler
Code
Current
Stack
TSS
Linear Address
Table
Offset
Page Directory
Page Table
Pg. Dir. Entry
Pg. Tbl. Entry
Page
Physical Addr.
This page mapping example is for 4-KByte pages
and the normal 32-bit physical address size.
*Physical Address
Figure 2-1. IA-32 System-Level Registers and Data Structures
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SYSTEM ARCHITECTURE OVERVIEW
RFLAGS
Physical Address
Control Register
CR8
CR4
CR3
CR2
CR1
CR0
Task Register
Interrupt
Vector
Task-State
Segment (TSS)
Segment Selector
Register
Global Descriptor
Table (GDT)
Segment Sel.
Seg. Desc.
TR
TSS Desc.
NULL
Interrupt Handler
Code
Stack
Seg. Desc.
Interrupt Descriptor
Table (IDT)
Interr. Handler
Seg. Desc.
Interrupt Gate
LDT Desc.
Code
Current TSS
Stack
Interrupt Gate
GDTR
Trap Gate
IDTR
Code, Data or Stack
Segment (Base =0)
Linear Address
IST
Local Descriptor
Table (LDT)
Call-Gate
Segment Selector
NULL
Seg. Desc.
Call Gate
XCR0 (XFEM)
NULL
LDTR
Exception Handler
Code
Stack
Protected Procedure
Code
Stack
PKRU
Linear Address Space
Linear Addr.
Linear Address
PML4 Dir. Pointer Directory
PML4
Pg. Dir. Ptr.
Pg. Dir.
Entry
PML4.
Entry
0
CR3*
Page Dir.
Table
Offset
Page Table
Page Tbl
Entry
Page
Physical
Addr.
This page mapping example is for 4-KByte pages
and 40-bit physical address size.
*Physical Address
Figure 2-2. System-Level Registers and Data Structures in IA-32e Mode
2.1.1
Global and Local Descriptor Tables
When operating in protected mode, all memory accesses pass through either the global descriptor table (GDT) or
an optional local descriptor table (LDT) as shown in Figure 2-1. These tables contain entries called segment
descriptors. Segment descriptors provide the base address of segments well as access rights, type, and usage
information.
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Each segment descriptor has an associated segment selector. A segment selector provides the software that uses
it with an index into the GDT or LDT (the offset of its associated segment descriptor), a global/local flag (determines whether the selector points to the GDT or the LDT), and access rights information.
To access a byte in a segment, a segment selector and an offset must be supplied. The segment selector provides
access to the segment descriptor for the segment (in the GDT or LDT). From the segment descriptor, the processor
obtains the base address of the segment in the linear address space. The offset then provides the location of the
byte relative to the base address. This mechanism can be used to access any valid code, data, or stack segment,
provided the segment is accessible from the current privilege level (CPL) at which the processor is operating. The
CPL is defined as the protection level of the currently executing code segment.
See Figure 2-1. The solid arrows in the figure indicate a linear address, dashed lines indicate a segment selector,
and the dotted arrows indicate a physical address. For simplicity, many of the segment selectors are shown as
direct pointers to a segment. However, the actual path from a segment selector to its associated segment is always
through a GDT or LDT.
The linear address of the base of the GDT is contained in the GDT register (GDTR); the linear address of the LDT is
contained in the LDT register (LDTR).
2.1.1.1
Global and Local Descriptor Tables in IA-32e Mode
GDTR and LDTR registers are expanded to 64-bits wide in both IA-32e sub-modes (64-bit mode and compatibility
mode). For more information: see Section 3.5.2, “Segment Descriptor Tables in IA-32e Mode.”
Global and local descriptor tables are expanded in 64-bit mode to support 64-bit base addresses, (16-byte LDT
descriptors hold a 64-bit base address and various attributes). In compatibility mode, descriptors are not
expanded.
2.1.2
System Segments, Segment Descriptors, and Gates
Besides code, data, and stack segments that make up the execution environment of a program or procedure, the
architecture defines two system segments: the task-state segment (TSS) and the LDT. The GDT is not considered
a segment because it is not accessed by means of a segment selector and segment descriptor. TSSs and LDTs have
segment descriptors defined for them.
The architecture also defines a set of special descriptors called gates (call gates, interrupt gates, trap gates, and
task gates). These provide protected gateways to system procedures and handlers that may operate at a different
privilege level than application programs and most procedures. For example, a CALL to a call gate can provide
access to a procedure in a code segment that is at the same or a numerically lower privilege level (more privileged)
than the current code segment. To access a procedure through a call gate, the calling procedure1 supplies the
selector for the call gate. The processor then performs an access rights check on the call gate, comparing the CPL
with the privilege level of the call gate and the destination code segment pointed to by the call gate.
If access to the destination code segment is allowed, the processor gets the segment selector for the destination
code segment and an offset into that code segment from the call gate. If the call requires a change in privilege
level, the processor also switches to the stack for the targeted privilege level. The segment selector for the new
stack is obtained from the TSS for the currently running task. Gates also facilitate transitions between 16-bit and
32-bit code segments, and vice versa.
2.1.2.1
Gates in IA-32e Mode
In IA-32e mode, the following descriptors are 16-byte descriptors (expanded to allow a 64-bit base): LDT descriptors, 64-bit TSSs, call gates, interrupt gates, and trap gates.
Call gates facilitate transitions between 64-bit mode and compatibility mode. Task gates are not supported in IA32e mode. On privilege level changes, stack segment selectors are not read from the TSS. Instead, they are set to
NULL.
1. The word “procedure” is commonly used in this document as a general term for a logical unit or block of code (such as a program, procedure, function, or routine).
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SYSTEM ARCHITECTURE OVERVIEW
2.1.3
Task-State Segments and Task Gates
The TSS (see Figure 2-1) defines the state of the execution environment for a task. It includes the state of generalpurpose registers, segment registers, the EFLAGS register, the EIP register, and segment selectors with stack
pointers for three stack segments (one stack for each privilege level). The TSS also includes the segment selector
for the LDT associated with the task and the base address of the paging-structure hierarchy.
All program execution in protected mode happens within the context of a task (called the current task). The
segment selector for the TSS for the current task is stored in the task register. The simplest method for switching
to a task is to make a call or jump to the new task. Here, the segment selector for the TSS of the new task is given
in the CALL or JMP instruction. In switching tasks, the processor performs the following actions:
1. Stores the state of the current task in the current TSS.
2. Loads the task register with the segment selector for the new task.
3. Accesses the new TSS through a segment descriptor in the GDT.
4. Loads the state of the new task from the new TSS into the general-purpose registers, the segment registers,
the LDTR, control register CR3 (base address of the paging-structure hierarchy), the EFLAGS register, and the
EIP register.
5. Begins execution of the new task.
A task can also be accessed through a task gate. A task gate is similar to a call gate, except that it provides access
(through a segment selector) to a TSS rather than a code segment.
2.1.3.1
Task-State Segments in IA-32e Mode
Hardware task switches are not supported in IA-32e mode. However, TSSs continue to exist. The base address of
a TSS is specified by its descriptor.
A 64-bit TSS holds the following information that is important to 64-bit operation:
•
•
•
Stack pointer addresses for each privilege level
Pointer addresses for the interrupt stack table
Offset address of the IO-permission bitmap (from the TSS base)
The task register is expanded to hold 64-bit base addresses in IA-32e mode. See also: Section 7.7, “Task Management in 64-bit Mode.”
2.1.4
Interrupt and Exception Handling
External interrupts, software interrupts and exceptions are handled through the interrupt descriptor table (IDT).
The IDT stores a collection of gate descriptors that provide access to interrupt and exception handlers. Like the
GDT, the IDT is not a segment. The linear address for the base of the IDT is contained in the IDT register (IDTR).
Gate descriptors in the IDT can be interrupt, trap, or task gate descriptors. To access an interrupt or exception
handler, the processor first receives an interrupt vector from internal hardware, an external interrupt controller, or
from software by means of an INT, INTO, INT 3, or BOUND instruction. The interrupt vector provides an index into
the IDT. If the selected gate descriptor is an interrupt gate or a trap gate, the associated handler procedure is
accessed in a manner similar to calling a procedure through a call gate. If the descriptor is a task gate, the handler
is accessed through a task switch.
2.1.4.1
Interrupt and Exception Handling IA-32e Mode
In IA-32e mode, interrupt gate descriptors are expanded to 16 bytes to support 64-bit base addresses. This is true
for 64-bit mode and compatibility mode.
The IDTR register is expanded to hold a 64-bit base address. Task gates are not supported.
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SYSTEM ARCHITECTURE OVERVIEW
2.1.5
Memory Management
System architecture supports either direct physical addressing of memory or virtual memory (through paging).
When physical addressing is used, a linear address is treated as a physical address. When paging is used: all code,
data, stack, and system segments (including the GDT and IDT) can be paged with only the most recently accessed
pages being held in physical memory.
The location of pages (sometimes called page frames) in physical memory is contained in the paging structures.
These structures reside in physical memory (see Figure 2-1 for the case of 32-bit paging).
The base physical address of the paging-structure hierarchy is contained in control register CR3. The entries in the
paging structures determine the physical address of the base of a page frame, access rights and memory management information.
To use this paging mechanism, a linear address is broken into parts. The parts provide separate offsets into the
paging structures and the page frame. A system can have a single hierarchy of paging structures or several. For
example, each task can have its own hierarchy.
2.1.5.1
Memory Management in IA-32e Mode
In IA-32e mode, physical memory pages are managed by a set of system data structures. In compatibility mode
and 64-bit mode, four levels of system data structures are used. These include:
•
The page map level 4 (PML4) — An entry in a PML4 table contains the physical address of the base of a page
directory pointer table, access rights, and memory management information. The base physical address of the
PML4 is stored in CR3.
•
A set of page directory pointer tables — An entry in a page directory pointer table contains the physical
address of the base of a page directory table, access rights, and memory management information.
•
Sets of page directories — An entry in a page directory table contains the physical address of the base of a
page table, access rights, and memory management information.
•
Sets of page tables — An entry in a page table contains the physical address of a page frame, access rights,
and memory management information.
2.1.6
System Registers
To assist in initializing the processor and controlling system operations, the system architecture provides system
flags in the EFLAGS register and several system registers:
•
The system flags and IOPL field in the EFLAGS register control task and mode switching, interrupt handling,
instruction tracing, and access rights. See also: Section 2.3, “System Flags and Fields in the EFLAGS Register.”
•
The control registers (CR0, CR2, CR3, and CR4) contain a variety of flags and data fields for controlling systemlevel operations. Other flags in these registers are used to indicate support for specific processor capabilities
within the operating system or executive. See also: Section 2.5, “Control Registers” and Section 2.6, “Extended
Control Registers (Including XCR0).”
•
The debug registers (not shown in Figure 2-1) allow the setting of breakpoints for use in debugging programs
and systems software. See also: Chapter 17, “Debug, Branch Profile, TSC, and Resource Monitoring Features.”
•
The GDTR, LDTR, and IDTR registers contain the linear addresses and sizes (limits) of their respective tables.
See also: Section 2.4, “Memory-Management Registers.”
•
The task register contains the linear address and size of the TSS for the current task. See also: Section 2.4,
“Memory-Management Registers.”
•
Model-specific registers (not shown in Figure 2-1).
The model-specific registers (MSRs) are a group of registers available primarily to operating-system or executive
procedures (that is, code running at privilege level 0). These registers control items such as the debug extensions,
the performance-monitoring counters, the machine- check architecture, and the memory type ranges (MTRRs).
The number and function of these registers varies among different members of the Intel 64 and IA-32 processor
families. See also: Section 9.4, “Model-Specific Registers (MSRs),” and Chapter 35, “Model-Specific Registers
(MSRs).”
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SYSTEM ARCHITECTURE OVERVIEW
Most systems restrict access to system registers (other than the EFLAGS register) by application programs.
Systems can be designed, however, where all programs and procedures run at the most privileged level (privilege
level 0). In such a case, application programs would be allowed to modify the system registers.
2.1.6.1
System Registers in IA-32e Mode
In IA-32e mode, the four system-descriptor-table registers (GDTR, IDTR, LDTR, and TR) are expanded in hardware
to hold 64-bit base addresses. EFLAGS becomes the 64-bit RFLAGS register. CR0–CR4 are expanded to 64 bits.
CR8 becomes available. CR8 provides read-write access to the task priority register (TPR) so that the operating
system can control the priority classes of external interrupts.
In 64-bit mode, debug registers DR0–DR7 are 64 bits. In compatibility mode, address-matching in DR0–DR3 is
also done at 64-bit granularity.
On systems that support IA-32e mode, the extended feature enable register (IA32_EFER) is available. This modelspecific register controls activation of IA-32e mode and other IA-32e mode operations. In addition, there are
several model-specific registers that govern IA-32e mode instructions:
•
•
•
•
IA32_KERNEL_GS_BASE — Used by SWAPGS instruction.
IA32_LSTAR — Used by SYSCALL instruction.
IA32_FMASK — Used by SYSCALL instruction.
IA32_STAR — Used by SYSCALL and SYSRET instruction.
2.1.7
Other System Resources
Besides the system registers and data structures described in the previous sections, system architecture provides
the following additional resources:
•
•
•
Operating system instructions (see also: Section 2.8, “System Instruction Summary”).
Performance-monitoring counters (not shown in Figure 2-1).
Internal caches and buffers (not shown in Figure 2-1).
Performance-monitoring counters are event counters that can be programmed to count processor events such as
the number of instructions decoded, the number of interrupts received, or the number of cache loads. See also:
Chapter 19, “Performance Monitoring Events.”
The processor provides several internal caches and buffers. The caches are used to store both data and instructions. The buffers are used to store things like decoded addresses to system and application segments and write
operations waiting to be performed. See also: Chapter 11, “Memory Cache Control.”
2.2
MODES OF OPERATION
The IA-32 architecture supports three operating modes and one quasi-operating mode:
•
Protected mode — This is the native operating mode of the processor. It provides a rich set of architectural
features, flexibility, high performance and backward compatibility to existing software base.
•
Real-address mode — This operating mode provides the programming environment of the Intel 8086
processor, with a few extensions (such as the ability to switch to protected or system management mode).
•
System management mode (SMM) — SMM is a standard architectural feature in all IA-32 processors,
beginning with the Intel386 SL processor. This mode provides an operating system or executive with a
transparent mechanism for implementing power management and OEM differentiation features. SMM is
entered through activation of an external system interrupt pin (SMI#), which generates a system management
interrupt (SMI). In SMM, the processor switches to a separate address space while saving the context of the
currently running program or task. SMM-specific code may then be executed transparently. Upon returning
from SMM, the processor is placed back into its state prior to the SMI.
•
Virtual-8086 mode — In protected mode, the processor supports a quasi-operating mode known as virtual8086 mode. This mode allows the processor execute 8086 software in a protected, multitasking environment.
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SYSTEM ARCHITECTURE OVERVIEW
Intel 64 architecture supports all operating modes of IA-32 architecture and IA-32e modes:
•
IA-32e mode — In IA-32e mode, the processor supports two sub-modes: compatibility mode and 64-bit
mode. 64-bit mode provides 64-bit linear addressing and support for physical address space larger than 64
GBytes. Compatibility mode allows most legacy protected-mode applications to run unchanged.
Figure 2-3 shows how the processor moves between operating modes.
Real-Address
Mode
Reset or
PE=0
PE=1
SMI#
Reset
or
RSM
SMI#
Reset
Protected Mode
See**
VM=0
RSM
LME=1, CR0.PG=1*
SMI#
IA-32e
Mode
RSM
System
Management
Mode
VM=1
* See Section 9.8.5
Virtual-8086
Mode
SMI#
** See Section 9.8.5.4
RSM
Figure 2-3. Transitions Among the Processor’s Operating Modes
The processor is placed in real-address mode following power-up or a reset. The PE flag in control register CR0 then
controls whether the processor is operating in real-address or protected mode. See also: Section 9.9, “Mode
Switching.” and Section 4.1.2, “Paging-Mode Enabling.”
The VM flag in the EFLAGS register determines whether the processor is operating in protected mode or virtual8086 mode. Transitions between protected mode and virtual-8086 mode are generally carried out as part of a task
switch or a return from an interrupt or exception handler. See also: Section 20.2.5, “Entering Virtual-8086 Mode.”
The LMA bit (IA32_EFER.LMA[bit 10]) determines whether the processor is operating in IA-32e mode. When
running in IA-32e mode, 64-bit or compatibility sub-mode operation is determined by CS.L bit of the code segment.
The processor enters into IA-32e mode from protected mode by enabling paging and setting the LME bit
(IA32_EFER.LME[bit 8]). See also: Chapter 9, “Processor Management and Initialization.”
The processor switches to SMM whenever it receives an SMI while the processor is in real-address, protected,
virtual-8086, or IA-32e modes. Upon execution of the RSM instruction, the processor always returns to the mode
it was in when the SMI occurred.
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SYSTEM ARCHITECTURE OVERVIEW
2.2.1
Extended Feature Enable Register
The IA32_EFER MSR provides several fields related to IA-32e mode enabling and operation. It also provides one
field that relates to page-access right modification (see Section 4.6, “Access Rights”). The layout of the
IA32_EFER MSR is shown in Figure 2-4.
63
12 11 10 9 8 7
1
0
IA32_EFER
Execute Disable Bit Enable
IA-32e Mode Active
IA-32e Mode Enable
SYSCALL Enable
Reserved
Figure 2-4. IA32_EFER MSR Layout
Table 2-1. IA32_EFER MSR Information
Bit
Description
0
SYSCALL Enable: IA32_EFER.SCE (R/W)
Enables SYSCALL/SYSRET instructions in 64-bit mode.
7:1
Reserved.
8
IA-32e Mode Enable: IA32_EFER.LME (R/W)
Enables IA-32e mode operation.
9
Reserved.
10
IA-32e Mode Active: IA32_EFER.LMA (R)
Indicates IA-32e mode is active when set.
11
Execute Disable Bit Enable: IA32_EFER.NXE (R/W)
Enables page access restriction by preventing instruction fetches from PAE pages with the XD bit set (See Section 4.6).
63:12
2.3
Reserved.
SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER
The system flags and IOPL field of the EFLAGS register control I/O, maskable hardware interrupts, debugging, task
switching, and the virtual-8086 mode (see Figure 2-5). Only privileged code (typically operating system or executive code) should be allowed to modify these bits.
The system flags and IOPL are:
TF
Trap (bit 8) — Set to enable single-step mode for debugging; clear to disable single-step mode. In singlestep mode, the processor generates a debug exception after each instruction. This allows the execution
state of a program to be inspected after each instruction. If an application program sets the TF flag using a
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SYSTEM ARCHITECTURE OVERVIEW
POPF, POPFD, or IRET instruction, a debug exception is generated after the instruction that follows the
POPF, POPFD, or IRET.
31
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved (set to 0)
V V
I I I A V R 0 N
T
D
C M F
P F
I
O
P
L
O D I T S Z
P
C
A
F F F F F F 0 F 0 F 1 F
ID — Identification Flag
VIP — Virtual Interrupt Pending
VIF — Virtual Interrupt Flag
AC — Alignment Check / Access Control
VM — Virtual-8086 Mode
RF — Resume Flag
NT — Nested Task Flag
IOPL— I/O Privilege Level
IF — Interrupt Enable Flag
TF — Trap Flag
Reserved
Figure 2-5. System Flags in the EFLAGS Register
IF
Interrupt enable (bit 9) — Controls the response of the processor to maskable hardware interrupt
requests (see also: Section 6.3.2, “Maskable Hardware Interrupts”). The flag is set to respond to maskable
hardware interrupts; cleared to inhibit maskable hardware interrupts. The IF flag does not affect the generation of exceptions or nonmaskable interrupts (NMI interrupts). The CPL, IOPL, and the state of the VME
flag in control register CR4 determine whether the IF flag can be modified by the CLI, STI, POPF, POPFD,
and IRET.
IOPL
I/O privilege level field (bits 12 and 13) — Indicates the I/O privilege level (IOPL) of the currently
running program or task. The CPL of the currently running program or task must be less than or equal to
the IOPL to access the I/O address space. The POPF and IRET instructions can modify this field only when
operating at a CPL of 0.
The IOPL is also one of the mechanisms that controls the modification of the IF flag and the handling of
interrupts in virtual-8086 mode when virtual mode extensions are in effect (when CR4.VME = 1). See also:
Chapter 18, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1.
NT
Nested task (bit 14) — Controls the chaining of interrupted and called tasks. The processor sets this flag
on calls to a task initiated with a CALL instruction, an interrupt, or an exception. It examines and modifies
this flag on returns from a task initiated with the IRET instruction. The flag can be explicitly set or cleared
with the POPF/POPFD instructions; however, changing to the state of this flag can generate unexpected
exceptions in application programs.
See also: Section 7.4, “Task Linking.”
RF
Resume (bit 16) — Controls the processor’s response to instruction-breakpoint conditions. When set, this
flag temporarily disables debug exceptions (#DB) from being generated for instruction breakpoints
(although other exception conditions can cause an exception to be generated). When clear, instruction
breakpoints will generate debug exceptions.
The primary function of the RF flag is to allow the restarting of an instruction following a debug exception
that was caused by an instruction breakpoint condition. Here, debug software must set this flag in the
EFLAGS image on the stack just prior to returning to the interrupted program with IRETD (to prevent the
instruction breakpoint from causing another debug exception). The processor then automatically clears
this flag after the instruction returned to has been successfully executed, enabling instruction breakpoint
faults again.
See also: Section 17.3.1.1, “Instruction-Breakpoint Exception Condition.”
VM
Virtual-8086 mode (bit 17) — Set to enable virtual-8086 mode; clear to return to protected mode.
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SYSTEM ARCHITECTURE OVERVIEW
See also: Section 20.2.1, “Enabling Virtual-8086 Mode.”
AC
Alignment check or access control (bit 18) — If the AM bit is set in the CR0 register, alignment
checking of user-mode data accesses is enabled if and only if this flag is 1. An alignment-check exception
is generated when reference is made to an unaligned operand, such as a word at an odd byte address or a
doubleword at an address which is not an integral multiple of four. Alignment-check exceptions are generated only in user mode (privilege level 3). Memory references that default to privilege level 0, such as
segment descriptor loads, do not generate this exception even when caused by instructions executed in
user-mode.
The alignment-check exception can be used to check alignment of data. This is useful when exchanging
data with processors which require all data to be aligned. The alignment-check exception can also be used
by interpreters to flag some pointers as special by misaligning the pointer. This eliminates overhead of
checking each pointer and only handles the special pointer when used.
If the SMAP bit is set in the CR4 register, explicit supervisor-mode data accesses to user-mode pages are
allowed if and only if this bit is 1. See Section 4.6, “Access Rights.”
VIF
Virtual Interrupt (bit 19) — Contains a virtual image of the IF flag. This flag is used in conjunction with
the VIP flag. The processor only recognizes the VIF flag when either the VME flag or the PVI flag in control
register CR4 is set and the IOPL is less than 3. (The VME flag enables the virtual-8086 mode extensions;
the PVI flag enables the protected-mode virtual interrupts.)
See also: Section 20.3.3.5, “Method 6: Software Interrupt Handling,” and Section 20.4, “Protected-Mode
Virtual Interrupts.”
VIP
Virtual interrupt pending (bit 20) — Set by software to indicate that an interrupt is pending; cleared to
indicate that no interrupt is pending. This flag is used in conjunction with the VIF flag. The processor reads
this flag but never modifies it. The processor only recognizes the VIP flag when either the VME flag or the
PVI flag in control register CR4 is set and the IOPL is less than 3. The VME flag enables the virtual-8086
mode extensions; the PVI flag enables the protected-mode virtual interrupts.
See Section 20.3.3.5, “Method 6: Software Interrupt Handling,” and Section 20.4, “Protected-Mode Virtual
Interrupts.”
ID
2.3.1
Identification (bit 21) — The ability of a program or procedure to set or clear this flag indicates support
for the CPUID instruction.
System Flags and Fields in IA-32e Mode
In 64-bit mode, the RFLAGS register expands to 64 bits with the upper 32 bits reserved. System flags in RFLAGS
(64-bit mode) or EFLAGS (compatibility mode) are shown in Figure 2-5.
In IA-32e mode, the processor does not allow the VM bit to be set because virtual-8086 mode is not supported
(attempts to set the bit are ignored). Also, the processor will not set the NT bit. The processor does, however, allow
software to set the NT bit (note that an IRET causes a general protection fault in IA-32e mode if the NT bit is set).
In IA-32e mode, the SYSCALL/SYSRET instructions have a programmable method of specifying which bits are
cleared in RFLAGS/EFLAGS. These instructions save/restore EFLAGS/RFLAGS.
2.4
MEMORY-MANAGEMENT REGISTERS
The processor provides four memory-management registers (GDTR, LDTR, IDTR, and TR) that specify the locations
of the data structures which control segmented memory management (see Figure 2-6). Special instructions are
provided for loading and storing these registers.
Vol. 3A 2-11
SYSTEM ARCHITECTURE OVERVIEW
47(79)
System Table Registers
16 15
0
GDTR
32(64)-bit Linear Base Address
16-Bit Table Limit
IDTR
32(64)-bit Linear Base Address
16-Bit Table Limit
Task
Register
LDTR
System Segment
Registers
15
0
Segment Descriptor Registers (Automatically Loaded)
Attributes
Seg. Sel.
32(64)-bit Linear Base Address
Segment Limit
Seg. Sel.
32(64)-bit Linear Base Address
Segment Limit
Figure 2-6. Memory Management Registers
2.4.1
Global Descriptor Table Register (GDTR)
The GDTR register holds the base address (32 bits in protected mode; 64 bits in IA-32e mode) and the 16-bit table
limit for the GDT. The base address specifies the linear address of byte 0 of the GDT; the table limit specifies the
number of bytes in the table.
The LGDT and SGDT instructions load and store the GDTR register, respectively. On power up or reset of the
processor, the base address is set to the default value of 0 and the limit is set to 0FFFFH. A new base address must
be loaded into the GDTR as part of the processor initialization process for protected-mode operation.
See also: Section 3.5.1, “Segment Descriptor Tables.”
2.4.2
Local Descriptor Table Register (LDTR)
The LDTR register holds the 16-bit segment selector, base address (32 bits in protected mode; 64 bits in IA-32e
mode), segment limit, and descriptor attributes for the LDT. The base address specifies the linear address of byte
0 of the LDT segment; the segment limit specifies the number of bytes in the segment. See also: Section 3.5.1,
“Segment Descriptor Tables.”
The LLDT and SLDT instructions load and store the segment selector part of the LDTR register, respectively. The
segment that contains the LDT must have a segment descriptor in the GDT. When the LLDT instruction loads a
segment selector in the LDTR: the base address, limit, and descriptor attributes from the LDT descriptor are automatically loaded in the LDTR.
When a task switch occurs, the LDTR is automatically loaded with the segment selector and descriptor for the LDT
for the new task. The contents of the LDTR are not automatically saved prior to writing the new LDT information
into the register.
On power up or reset of the processor, the segment selector and base address are set to the default value of 0 and
the limit is set to 0FFFFH.
2.4.3
IDTR Interrupt Descriptor Table Register
The IDTR register holds the base address (32 bits in protected mode; 64 bits in IA-32e mode) and 16-bit table limit
for the IDT. The base address specifies the linear address of byte 0 of the IDT; the table limit specifies the number
of bytes in the table. The LIDT and SIDT instructions load and store the IDTR register, respectively. On power up or
reset of the processor, the base address is set to the default value of 0 and the limit is set to 0FFFFH. The base
address and limit in the register can then be changed as part of the processor initialization process.
See also: Section 6.10, “Interrupt Descriptor Table (IDT).”
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SYSTEM ARCHITECTURE OVERVIEW
2.4.4
Task Register (TR)
The task register holds the 16-bit segment selector, base address (32 bits in protected mode; 64 bits in IA-32e
mode), segment limit, and descriptor attributes for the TSS of the current task. The selector references the TSS
descriptor in the GDT. The base address specifies the linear address of byte 0 of the TSS; the segment limit specifies the number of bytes in the TSS. See also: Section 7.2.4, “Task Register.”
The LTR and STR instructions load and store the segment selector part of the task register, respectively. When the
LTR instruction loads a segment selector in the task register, the base address, limit, and descriptor attributes from
the TSS descriptor are automatically loaded into the task register. On power up or reset of the processor, the base
address is set to the default value of 0 and the limit is set to 0FFFFH.
When a task switch occurs, the task register is automatically loaded with the segment selector and descriptor for
the TSS for the new task. The contents of the task register are not automatically saved prior to writing the new TSS
information into the register.
2.5
CONTROL REGISTERS
Control registers (CR0, CR1, CR2, CR3, and CR4; see Figure 2-7) determine operating mode of the processor and
the characteristics of the currently executing task. These registers are 32 bits in all 32-bit modes and compatibility
mode.
In 64-bit mode, control registers are expanded to 64 bits. The MOV CRn instructions are used to manipulate the
register bits. Operand-size prefixes for these instructions are ignored. The following is also true:
•
The control registers can be read and loaded (or modified) using the move-to-or-from-control-registers forms
of the MOV instruction. In protected mode, the MOV instructions allow the control registers to be read or loaded
(at privilege level 0 only). This restriction means that application programs or operating-system procedures
(running at privilege levels 1, 2, or 3) are prevented from reading or loading the control registers.
•
Bits 63:32 of CR0 and CR4 are reserved and must be written with zeros. Writing a nonzero value to any of the
upper 32 bits results in a general-protection exception, #GP(0).
•
•
•
All 64 bits of CR2 are writable by software.
•
Register CR8 is available in 64-bit mode only.
Bits 51:40 of CR3 are reserved and must be 0.
The MOV CRn instructions do not check that addresses written to CR2 and CR3 are within the linear-address or
physical-address limitations of the implementation.
The control registers are summarized below, and each architecturally defined control field in these control registers
is described individually. In Figure 2-7, the width of the register in 64-bit mode is indicated in parenthesis (except
for CR0).
•
•
•
•
CR0 — Contains system control flags that control operating mode and states of the processor.
CR1 — Reserved.
CR2 — Contains the page-fault linear address (the linear address that caused a page fault).
CR3 — Contains the physical address of the base of the paging-structure hierarchy and two flags (PCD and
PWT). Only the most-significant bits (less the lower 12 bits) of the base address are specified; the lower 12 bits
of the address are assumed to be 0. The first paging structure must thus be aligned to a page (4-KByte)
boundary. The PCD and PWT flags control caching of that paging structure in the processor’s internal data
caches (they do not control TLB caching of page-directory information).
When using the physical address extension, the CR3 register contains the base address of the page-directorypointer table. In IA-32e mode, the CR3 register contains the base address of the PML4 table.
See also: Chapter 4, “Paging.”
•
CR4 — Contains a group of flags that enable several architectural extensions, and indicate operating system or
executive support for specific processor capabilities.
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SYSTEM ARCHITECTURE OVERVIEW
•
CR8 — Provides read and write access to the Task Priority Register (TPR). It specifies the priority threshold
value that operating systems use to control the priority class of external interrupts allowed to interrupt the
processor. This register is available only in 64-bit mode. However, interrupt filtering continues to apply in
compatibility mode.
22 21 20
31(63)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P S S
K M M
E A E
P P
Reserved
S
M
X
E
OSXSAVE
V
M
X
E
U
M
I
P
T P V
P P M P P
C G C A S D S V M
E D I E
E E E E E
FSGSBASE
PCIDE
OSFXSR
OSXMMEXCPT
12 11
5 4 3 2
31(63)
P P
C W
D T
Page-Directory Base
31(63)
CR4
CR3
(PDBR)
0
Page-Fault Linear Address
31(63)
CR2
0
CR1
31 30 29 28
P C N
G D W
19 18 17 16 15
A
M
W
P
6 5 4 3 2 1 0
N E T E M P
E T S M P E
CR0
Reserved
Figure 2-7. Control Registers
When loading a control register, reserved bits should always be set to the values previously read. The flags in
control registers are:
PG
Paging (bit 31 of CR0) — Enables paging when set; disables paging when clear. When paging is
disabled, all linear addresses are treated as physical addresses. The PG flag has no effect if the PE flag (bit
0 of register CR0) is not also set; setting the PG flag when the PE flag is clear causes a general-protection
exception (#GP). See also: Chapter 4, “Paging.”
On Intel 64 processors, enabling and disabling IA-32e mode operation also requires modifying CR0.PG.
CD
Cache Disable (bit 30 of CR0) — When the CD and NW flags are clear, caching of memory locations for
the whole of physical memory in the processor’s internal (and external) caches is enabled. When the CD
flag is set, caching is restricted as described in Table 11-5. To prevent the processor from accessing and
updating its caches, the CD flag must be set and the caches must be invalidated so that no cache hits can
occur.
See also: Section 11.5.3, “Preventing Caching,” and Section 11.5, “Cache Control.”
NW
Not Write-through (bit 29 of CR0) — When the NW and CD flags are clear, write-back (for Pentium 4,
Intel Xeon, P6 family, and Pentium processors) or write-through (for Intel486 processors) is enabled for
writes that hit the cache and invalidation cycles are enabled. See Table 11-5 for detailed information about
the effect of the NW flag on caching for other settings of the CD and NW flags.
AM
Alignment Mask (bit 18 of CR0) — Enables automatic alignment checking when set; disables alignment
checking when clear. Alignment checking is performed only when the AM flag is set, the AC flag in the
EFLAGS register is set, CPL is 3, and the processor is operating in either protected or virtual-8086 mode.
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SYSTEM ARCHITECTURE OVERVIEW
WP
Write Protect (bit 16 of CR0) — When set, inhibits supervisor-level procedures from writing into readonly pages; when clear, allows supervisor-level procedures to write into read-only pages (regardless of the
U/S bit setting; see Section 4.1.3 and Section 4.6). This flag facilitates implementation of the copy-onwrite method of creating a new process (forking) used by operating systems such as UNIX.
NE
Numeric Error (bit 5 of CR0) — Enables the native (internal) mechanism for reporting x87 FPU errors
when set; enables the PC-style x87 FPU error reporting mechanism when clear. When the NE flag is clear
and the IGNNE# input is asserted, x87 FPU errors are ignored. When the NE flag is clear and the IGNNE#
input is deasserted, an unmasked x87 FPU error causes the processor to assert the FERR# pin to generate
an external interrupt and to stop instruction execution immediately before executing the next waiting
floating-point instruction or WAIT/FWAIT instruction.
The FERR# pin is intended to drive an input to an external interrupt controller (the FERR# pin emulates the
ERROR# pin of the Intel 287 and Intel 387 DX math coprocessors). The NE flag, IGNNE# pin, and FERR#
pin are used with external logic to implement PC-style error reporting. Using FERR# and IGNNE# to handle
floating-point exceptions is deprecated by modern operating systems; this non-native approach also limits
newer processors to operate with one logical processor active.
See also: Section 8.7, “Handling x87 FPU Exceptions in Software” in Chapter 8, “Programming with the x87
FPU,” and Appendix A, “EFLAGS Cross-Reference,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1.
ET
Extension Type (bit 4 of CR0) — Reserved in the Pentium 4, Intel Xeon, P6 family, and Pentium processors. In the Pentium 4, Intel Xeon, and P6 family processors, this flag is hardcoded to 1. In the Intel386
and Intel486 processors, this flag indicates support of Intel 387 DX math coprocessor instructions when
set.
TS
Task Switched (bit 3 of CR0) — Allows the saving of the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4
context on a task switch to be delayed until an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is
actually executed by the new task. The processor sets this flag on every task switch and tests it when
executing x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
•
If the TS flag is set and the EM flag (bit 2 of CR0) is clear, a device-not-available exception (#NM) is
raised prior to the execution of any x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction; with the
exception of PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and POPCNT.
See the paragraph below for the special case of the WAIT/FWAIT instructions.
•
If the TS flag is set and the MP flag (bit 1 of CR0) and EM flag are clear, an #NM exception is not raised
prior to the execution of an x87 FPU WAIT/FWAIT instruction.
•
If the EM flag is set, the setting of the TS flag has no effect on the execution of x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
Table 2-2 shows the actions taken when the processor encounters an x87 FPU instruction based on the
settings of the TS, EM, and MP flags. Table 12-1 and 13-1 show the actions taken when the processor
encounters an MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction.
The processor does not automatically save the context of the x87 FPU, XMM, and MXCSR registers on a
task switch. Instead, it sets the TS flag, which causes the processor to raise an #NM exception whenever
it encounters an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction in the instruction stream for the
new task (with the exception of the instructions listed above).
The fault handler for the #NM exception can then be used to clear the TS flag (with the CLTS instruction)
and save the context of the x87 FPU, XMM, and MXCSR registers. If the task never encounters an x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction, the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4
context is never saved.
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SYSTEM ARCHITECTURE OVERVIEW
Table 2-2. Action Taken By x87 FPU Instructions for Different Combinations of EM, MP, and TS
CR0 Flags
EM
EM
MP
x87 FPU Instruction Type
TS
Floating-Point
WAIT/FWAIT
0
0
0
Execute
Execute.
0
0
1
#NM Exception
Execute.
0
1
0
Execute
Execute.
0
1
1
#NM Exception
#NM exception.
1
0
0
#NM Exception
Execute.
1
0
1
#NM Exception
Execute.
1
1
0
#NM Exception
Execute.
1
1
1
#NM Exception
#NM exception.
Emulation (bit 2 of CR0) — Indicates that the processor does not have an internal or external x87 FPU
when set; indicates an x87 FPU is present when clear. This flag also affects the execution of
MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
When the EM flag is set, execution of an x87 FPU instruction generates a device-not-available exception
(#NM). This flag must be set when the processor does not have an internal x87 FPU or is not connected to
an external math coprocessor. Setting this flag forces all floating-point instructions to be handled by software emulation. Table 9-3 shows the recommended setting of this flag, depending on the IA-32 processor
and x87 FPU or math coprocessor present in the system. Table 2-2 shows the interaction of the EM, MP, and
TS flags.
Also, when the EM flag is set, execution of an MMX instruction causes an invalid-opcode exception (#UD)
to be generated (see Table 12-1). Thus, if an IA-32 or Intel 64 processor incorporates MMX technology, the
EM flag must be set to 0 to enable execution of MMX instructions.
Similarly for SSE/SSE2/SSE3/SSSE3/SSE4 extensions, when the EM flag is set, execution of most
SSE/SSE2/SSE3/SSSE3/SSE4 instructions causes an invalid opcode exception (#UD) to be generated (see
Table 13-1). If an IA-32 or Intel 64 processor incorporates the SSE/SSE2/SSE3/SSSE3/SSE4 extensions,
the EM flag must be set to 0 to enable execution of these extensions. SSE/SSE2/SSE3/SSSE3/SSE4
instructions not affected by the EM flag include: PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI,
CLFLUSH, CRC32, and POPCNT.
MP
Monitor Coprocessor (bit 1 of CR0) — Controls the interaction of the WAIT (or FWAIT) instruction with the
TS flag (bit 3 of CR0). If the MP flag is set, a WAIT instruction generates a device-not-available exception
(#NM) if the TS flag is also set. If the MP flag is clear, the WAIT instruction ignores the setting of the TS flag.
Table 9-3 shows the recommended setting of this flag, depending on the IA-32 processor and x87 FPU or
math coprocessor present in the system. Table 2-2 shows the interaction of the MP, EM, and TS flags.
PE
Protection Enable (bit 0 of CR0) — Enables protected mode when set; enables real-address mode when
clear. This flag does not enable paging directly. It only enables segment-level protection. To enable paging,
both the PE and PG flags must be set.
See also: Section 9.9, “Mode Switching.”
PCD
Page-level Cache Disable (bit 4 of CR3) — Controls the memory type used to access the first paging
structure of the current paging-structure hierarchy. See Section 4.9, “Paging and Memory Typing”. This bit
is not used if paging is disabled, with PAE paging, or with IA-32e paging if CR4.PCIDE=1.
PWT
Page-level Write-Through (bit 3 of CR3) — Controls the memory type used to access the first paging
structure of the current paging-structure hierarchy. See Section 4.9, “Paging and Memory Typing”. This bit
is not used if paging is disabled, with PAE paging, or with IA-32e paging if CR4.PCIDE=1.
VME
Virtual-8086 Mode Extensions (bit 0 of CR4) — Enables interrupt- and exception-handling extensions
in virtual-8086 mode when set; disables the extensions when clear. Use of the virtual mode extensions can
improve the performance of virtual-8086 applications by eliminating the overhead of calling the virtual8086 monitor to handle interrupts and exceptions that occur while executing an 8086 program and,
instead, redirecting the interrupts and exceptions back to the 8086 program’s handlers. It also provides
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SYSTEM ARCHITECTURE OVERVIEW
hardware support for a virtual interrupt flag (VIF) to improve reliability of running 8086 programs in multitasking and multiple-processor environments.
See also: Section 20.3, “Interrupt and Exception Handling in Virtual-8086 Mode.”
PVI
Protected-Mode Virtual Interrupts (bit 1 of CR4) — Enables hardware support for a virtual interrupt
flag (VIF) in protected mode when set; disables the VIF flag in protected mode when clear.
See also: Section 20.4, “Protected-Mode Virtual Interrupts.”
TSD
Time Stamp Disable (bit 2 of CR4) — Restricts the execution of the RDTSC instruction to procedures
running at privilege level 0 when set; allows RDTSC instruction to be executed at any privilege level when
clear. This bit also applies to the RDTSCP instruction if supported (if CPUID.80000001H:EDX[27] = 1).
DE
Debugging Extensions (bit 3 of CR4) — References to debug registers DR4 and DR5 cause an undefined opcode (#UD) exception to be generated when set; when clear, processor aliases references to registers DR4 and DR5 for compatibility with software written to run on earlier IA-32 processors.
See also: Section 17.2.2, “Debug Registers DR4 and DR5.”
PSE
Page Size Extensions (bit 4 of CR4) — Enables 4-MByte pages with 32-bit paging when set; restricts
32-bit paging to pages of 4 KBytes when clear.
See also: Section 4.3, “32-Bit Paging.”
PAE
Physical Address Extension (bit 5 of CR4) — When set, enables paging to produce physical addresses
with more than 32 bits. When clear, restricts physical addresses to 32 bits. PAE must be set before entering
IA-32e mode.
See also: Chapter 4, “Paging.”
MCE
Machine-Check Enable (bit 6 of CR4) — Enables the machine-check exception when set; disables the
machine-check exception when clear.
See also: Chapter 15, “Machine-Check Architecture.”
PGE
Page Global Enable (bit 7 of CR4) — (Introduced in the P6 family processors.) Enables the global page
feature when set; disables the global page feature when clear. The global page feature allows frequently
used or shared pages to be marked as global to all users (done with the global flag, bit 8, in a page-directory or page-table entry). Global pages are not flushed from the translation-lookaside buffer (TLB) on a
task switch or a write to register CR3.
When enabling the global page feature, paging must be enabled (by setting the PG flag in control register
CR0) before the PGE flag is set. Reversing this sequence may affect program correctness, and processor
performance will be impacted.
See also: Section 4.10, “Caching Translation Information.”
PCE
Performance-Monitoring Counter Enable (bit 8 of CR4) — Enables execution of the RDPMC instruction for programs or procedures running at any protection level when set; RDPMC instruction can be
executed only at protection level 0 when clear.
OSFXSR
Operating System Support for FXSAVE and FXRSTOR instructions (bit 9 of CR4) — When set, this
flag: (1) indicates to software that the operating system supports the use of the FXSAVE and FXRSTOR
instructions, (2) enables the FXSAVE and FXRSTOR instructions to save and restore the contents of the
XMM and MXCSR registers along with the contents of the x87 FPU and MMX registers, and (3) enables the
processor to execute SSE/SSE2/SSE3/SSSE3/SSE4 instructions, with the exception of the PAUSE,
PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and POPCNT.
If this flag is clear, the FXSAVE and FXRSTOR instructions will save and restore the contents of the x87 FPU
and MMX registers, but they may not save and restore the contents of the XMM and MXCSR registers. Also,
the processor will generate an invalid opcode exception (#UD) if it attempts to execute any
SSE/SSE2/SSE3 instruction, with the exception of PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE,
MOVNTI, CLFLUSH, CRC32, and POPCNT. The operating system or executive must explicitly set this flag.
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SYSTEM ARCHITECTURE OVERVIEW
NOTE
CPUID feature flag FXSR indicates availability of the FXSAVE/FXRSTOR instructions. The OSFXSR
bit provides operating system software with a means of enabling FXSAVE/FXRSTOR to save/restore
the contents of the X87 FPU, XMM and MXCSR registers. Consequently OSFXSR bit indicates that
the operating system provides context switch support for SSE/SSE2/SSE3/SSSE3/SSE4.
OSXMMEXCPT
Operating System Support for Unmasked SIMD Floating-Point Exceptions (bit 10 of CR4) —
When set, indicates that the operating system supports the handling of unmasked SIMD floating-point
exceptions through an exception handler that is invoked when a SIMD floating-point exception (#XM) is
generated. SIMD floating-point exceptions are only generated by SSE/SSE2/SSE3/SSE4.1 SIMD floatingpoint instructions.
The operating system or executive must explicitly set this flag. If this flag is not set, the processor will
generate an invalid opcode exception (#UD) whenever it detects an unmasked SIMD floating-point exception.
UMIP
User-Mode Instruction Prevention (bit 11 of CR4) — When set, the following instructions cannot be
executed if CPL > 0: SGDT, SIDT, SLDT, SMSW, and STR. An attempt at such execution causes a generalprotection exception (#GP).
VMXE
VMX-Enable Bit (bit 13 of CR4) — Enables VMX operation when set. See Chapter 23, “Introduction to
Virtual Machine Extensions.”
SMXE
SMX-Enable Bit (bit 14 of CR4) — Enables SMX operation when set. See Chapter 6, “Safer Mode Extensions Reference” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D.
FSGSBASE
FSGSBASE-Enable Bit (bit 16 of CR4) — Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE,
and WRGSBASE.
PCIDE
PCID-Enable Bit (bit 17 of CR4) — Enables process-context identifiers (PCIDs) when set. See Section
4.10.1, “Process-Context Identifiers (PCIDs)”. Can be set only in IA-32e mode (if IA32_EFER.LMA = 1).
OSXSAVE
XSAVE and Processor Extended States-Enable Bit (bit 18 of CR4) — When set, this flag: (1) indicates (via CPUID.01H:ECX.OSXSAVE[bit 27]) that the operating system supports the use of the XGETBV,
XSAVE and XRSTOR instructions by general software; (2) enables the XSAVE and XRSTOR instructions to
save and restore the x87 FPU state (including MMX registers), the SSE state (XMM registers and MXCSR),
along with other processor extended states enabled in XCR0; (3) enables the processor to execute XGETBV
and XSETBV instructions in order to read and write XCR0. See Section 2.6 and Chapter 13, “System
Programming for Instruction Set Extensions and Processor Extended States”.
SMEP
SMEP-Enable Bit (bit 20 of CR4) — Enables supervisor-mode execution prevention (SMEP) when set.
See Section 4.6, “Access Rights”.
SMAP
SMAP-Enable Bit (bit 21 of CR4) — Enables supervisor-mode access prevention (SMAP) when set. See
Section 4.6, “Access Rights.”
PKE
Protection-Key-Enable Bit (bit 22 of CR4) — Enables IA-32e paging to associate each linear address
with a protection key. The PKRU register specifies, for each protection key, whether user-mode linear
addresses with that protection key can be read or written. This bit also enables access to the PKRU register
using the RDPKRU and WRPKRU instructions.
TPL
Task Priority Level (bit 3:0 of CR8) — This sets the threshold value corresponding to the highest-
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SYSTEM ARCHITECTURE OVERVIEW
priority interrupt to be blocked. A value of 0 means all interrupts are enabled. This field is available in 64bit mode. A value of 15 means all interrupts will be disabled.
2.5.1
CPUID Qualification of Control Register Flags
Not all flags in control register CR4 are implemented on all processors. With the exception of the PCE flag, they can
be qualified with the CPUID instruction to determine if they are implemented on the processor before they are
used.
The CR8 register is available on processors that support Intel 64 architecture.
2.6
EXTENDED CONTROL REGISTERS (INCLUDING XCR0)
If CPUID.01H:ECX.XSAVE[bit 26] is 1, the processor supports one or more extended control registers (XCRs).
Currently, the only such register defined is XCR0. This register specifies the set of processor state components for
which the operating system provides context management, e.g. x87 FPU state, SSE state, AVX state. The OS
programs XCR0 to reflect the features for which it provides context management.
63
9
Reserved (must be 0)
7 6 5 4 3
2 1 0
1
Reserved for XCR0 bit vector expansion
Reserved / Future processor extended states
PKRU state
Hi16_ZMM state
ZMM_Hi256 state
Opmask state
BNDCSR state
BNDREG state
AVX state
SSE state
x87 FPU/MMX state (must be 1)
Figure 2-8. XCR0
Software can access XCR0 only if CR4.OSXSAVE[bit 18] = 1. (This bit is also readable as
CPUID.01H:ECX.OSXSAVE[bit 27].) Software can use CPUID leaf function 0DH to enumerate the bits in XCR0 that
the processor supports (see CPUID instruction in Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A). Each supported state component is represented by a bit in XCR0. System software enables state
components by loading an appropriate bit mask value into XCR0 using the XSETBV instruction.
As each bit in XCR0 (except bit 63) corresponds to a processor state component, XCR0 thus provides support for
up to 63 sets of processor state components. Bit 63 of XCR0 is reserved for future expansion and will not represent
a processor state component.
Currently, XCR0 defines support for the following state components:
•
•
XCR0.X87 (bit 0): This bit 0 must be 1. An attempt to write 0 to this bit causes a #GP exception.
•
XCR0.AVX (bit 2): If 1, AVX instructions can be executed and the XSAVE feature set can be used to manage the
upper halves of the YMM registers (YMM0-YMM15 in 64-bit mode; otherwise YMM0-YMM7).
•
XCR0.BNDREG (bit 3): If 1, MPX instructions can be executed and the XSAVE feature set can be used to
manage the bounds registers BND0–BND3.
XCR0.SSE (bit 1): If 1, the XSAVE feature set can be used to manage MXCSR and the XMM registers (XMM0XMM15 in 64-bit mode; otherwise XMM0-XMM7).
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SYSTEM ARCHITECTURE OVERVIEW
•
XCR0.BNDCSR (bit 4): If 1, MPX instructions can be executed and the XSAVE feature set can be used to
manage the BNDCFGU and BNDSTATUS registers.
•
XCR0.opmask (bit 5): If 1, AVX-512 instructions can be executed and the XSAVE feature set can be used to
manage the opmask registers k0–k7.
•
XCR0.ZMM_Hi256 (bit 6): If 1, AVX-512 instructions can be executed and the XSAVE feature set can be used to
manage the upper halves of the lower ZMM registers (ZMM0-ZMM15 in 64-bit mode; otherwise ZMM0-ZMM7).
•
XCR0.Hi16_ZMM (bit 7): If 1, AVX-512 instructions can be executed and the XSAVE feature set can be used to
manage the upper ZMM registers (ZMM16-ZMM31, only in 64-bit mode).
•
XCR0.PKRU (bit 9): If 1, the XSAVE feature set can be used to manage the PKRU register (see Section 2.7).
An attempt to use XSETBV to write to XCR0 results in general-protection exceptions (#GP) if it would do any of the
following:
•
Set a bit reserved in XCR0 for a given processor (as determined by the contents of EAX and EDX after executing
CPUID with EAX=0DH, ECX= 0H).
•
•
•
•
•
Clear XCR0.x87.
Clear XCR0.SSE and set XCR0.AVX.
Clear XCR0.AVX and set any of XCR0.opmask, XCR0.ZMM_Hi256, and XCR0.Hi16_ZMM.
Set either XCR0.BNDREG and XCR0.BNDCSR while not setting the other.
Set any of XCR0.opmask, XCR0.ZMM_Hi256, and XCR0.Hi16_ZMM while not setting all of them.
After reset, all bits (except bit 0) in XCR0 are cleared to zero; XCR0[0] is set to 1.
2.7
PROTECTION KEY RIGHTS REGISTER (PKRU)
If CPUID.(EAX=07H,ECX=0H):ECX.PKU [bit 3] = 1, the processor supports the protection-key feature for IA-32e
paging. The feature allows selective protection of user-mode pages depending on the 4-bit protection key assigned
to each page. The protection key rights register for user pages (PKRU) allows software to specify the access
rights for each protection key.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Position
W A W A W A W A W A W A W A W A W A W A W A W A W A W A W A W A
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
Figure 2-9. Protection Key Rights Register for User Pages (PKRU)
The layout of the PKRU register is shown in Figure 2-9. It contains 16 pairs of disable controls to prevent data
accesses to user-mode linear addresses based on their protection keys. Each protection key i is associated with two
bits in the PKRU register:
•
Bit 2i, shown as “ADi” (access disable): if set, the processor prevents any data accesses to user-mode linear
addresses with protection key i.
•
Bit 2i+1, shown as “WDi” (write disable): if set, the processor prevents write accesses to user-mode linear
addresses with protection key i.
See Section 4.6.2, “Protection Keys,” for details of how the processor uses the PKRU register to control accesses to
user-mode linear addresses.
2.8
SYSTEM INSTRUCTION SUMMARY
System instructions handle system-level functions such as loading system registers, managing the cache,
managing interrupts, or setting up the debug registers. Many of these instructions can be executed only by oper-
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SYSTEM ARCHITECTURE OVERVIEW
ating-system or executive procedures (that is, procedures running at privilege level 0). Others can be executed at
any privilege level and are thus available to application programs.
Table 2-3 lists the system instructions and indicates whether they are available and useful for application
programs. These instructions are described in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volumes 2A, 2B, 2C & 2D.
Table 2-3. Summary of System Instructions
Useful to
Application?
Protected from
Application?
Instruction
Description
LLDT
Load LDT Register
No
Yes
SLDT
Store LDT Register
No
If CR4.UMIP = 1
LGDT
Load GDT Register
No
Yes
SGDT
Store GDT Register
No
If CR4.UMIP = 1
LTR
Load Task Register
No
Yes
STR
Store Task Register
No
If CR4.UMIP = 1
LIDT
Load IDT Register
No
Yes
SIDT
Store IDT Register
No
If CR4.UMIP = 1
MOV CRn
Load and store control registers
No
Yes
SMSW
Store MSW
Yes
If CR4.UMIP = 1
LMSW
Load MSW
No
Yes
CLTS
Clear TS flag in CR0
No
Yes
ARPL
Adjust RPL
LAR
Load Access Rights
Yes
Yes
No
LSL
Load Segment Limit
Yes
No
1, 5
No
VERR
Verify for Reading
Yes
No
VERW
Verify for Writing
Yes
No
MOV DRn
Load and store debug registers
No
Yes
INVD
Invalidate cache, no writeback
No
Yes
WBINVD
Invalidate cache, with writeback
No
Yes
INVLPG
Invalidate TLB entry
No
Yes
HLT
Halt Processor
No
Yes
LOCK (Prefix)
Bus Lock
Yes
No
RSM
Return from system management mode
No
Yes
RDMSR3
Read Model-Specific Registers
No
Yes
WRMSR3
Write Model-Specific Registers
No
Yes
RDPMC4
Read Performance-Monitoring Counter
Yes
Yes2
RDTSC3
Read Time-Stamp Counter
Yes
Yes2
RDTSCP7
Read Serialized Time-Stamp Counter
Yes
Yes2
XGETBV
Return the state of XCR0
Yes
No
XSETBV
Enable one or more processor extended states
No
Yes
6
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SYSTEM ARCHITECTURE OVERVIEW
Table 2-3. Summary of System Instructions (Contd.)
Instruction
Description
Useful to
Application?
Protected from
Application?
NOTES:
1.
2.
3.
4.
Useful to application programs running at a CPL of 1 or 2.
The TSD and PCE flags in control register CR4 control access to these instructions by application programs running at a CPL of 3.
These instructions were introduced into the IA-32 Architecture with the Pentium processor.
This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor and the Pentium processor with MMX technology.
5. This instruction is not supported in 64-bit mode.
6. Application uses XGETBV to query which set of processor extended states are enabled.
7. RDTSCP is introduced in Intel Core i7 processor.
2.8.1
Loading and Storing System Registers
The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for loading data into and storing
data from the register:
•
•
•
•
•
LGDT (Load GDTR Register) — Loads the GDT base address and limit from memory into the GDTR register.
•
SLDT (Store LDTR Register) — Stores the LDT segment selector from the LDTR register into memory or a
general-purpose register.
•
LTR (Load Task Register) — Loads segment selector and segment descriptor for a TSS from memory into the
task register. (The segment selector operand can also be located in a general-purpose register.)
•
STR (Store Task Register) — Stores the segment selector for the current task TSS from the task register into
memory or a general-purpose register.
SGDT (Store GDTR Register) — Stores the GDT base address and limit from the GDTR register into memory.
LIDT (Load IDTR Register) — Loads the IDT base address and limit from memory into the IDTR register.
SIDT (Store IDTR Register) — Stores the IDT base address and limit from the IDTR register into memory.
LLDT (Load LDTR Register) — Loads the LDT segment selector and segment descriptor from memory into
the LDTR. (The segment selector operand can also be located in a general-purpose register.)
The LMSW (load machine status word) and SMSW (store machine status word) instructions operate on bits 0
through 15 of control register CR0. These instructions are provided for compatibility with the 16-bit Intel 286
processor. Programs written to run on 32-bit IA-32 processors should not use these instructions. Instead, they
should access the control register CR0 using the MOV CR instruction.
The CLTS (clear TS flag in CR0) instruction is provided for use in handling a device-not-available exception (#NM)
that occurs when the processor attempts to execute a floating-point instruction when the TS flag is set. This
instruction allows the TS flag to be cleared after the x87 FPU context has been saved, preventing further #NM
exceptions. See Section 2.5, “Control Registers,” for more information on the TS flag.
The control registers (CR0, CR1, CR2, CR3, CR4, and CR8) are loaded using the MOV instruction. The instruction
loads a control register from a general-purpose register or stores the content of a control register in a generalpurpose register.
2.8.2
Verifying of Access Privileges
The processor provides several instructions for examining segment selectors and segment descriptors to determine
if access to their associated segments is allowed. These instructions duplicate some of the automatic access rights
and type checking done by the processor, thus allowing operating-system or executive software to prevent exceptions from being generated.
The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level) of a segment selector to match that of
the program or procedure that supplied the segment selector. See Section 5.10.4, “Checking Caller Access Privileges (ARPL Instruction)” for a detailed explanation of the function and use of this instruction. Note that ARPL is not
supported in 64-bit mode.
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SYSTEM ARCHITECTURE OVERVIEW
The LAR (load access rights) instruction verifies the accessibility of a specified segment and loads access rights
information from the segment’s segment descriptor into a general-purpose register. Software can then examine
the access rights to determine if the segment type is compatible with its intended use. See Section 5.10.1,
“Checking Access Rights (LAR Instruction)” for a detailed explanation of the function and use of this instruction.
The LSL (load segment limit) instruction verifies the accessibility of a specified segment and loads the segment
limit from the segment’s segment descriptor into a general-purpose register. Software can then compare the
segment limit with an offset into the segment to determine whether the offset lies within the segment. See Section
5.10.3, “Checking That the Pointer Offset Is Within Limits (LSL Instruction)” for a detailed explanation of the function and use of this instruction.
The VERR (verify for reading) and VERW (verify for writing) instructions verify if a selected segment is readable or
writable, respectively, at a given CPL. See Section 5.10.2, “Checking Read/Write Rights (VERR and VERW Instructions)” for a detailed explanation of the function and use of these instructions.
2.8.3
Loading and Storing Debug Registers
Internal debugging facilities in the processor are controlled by a set of 8 debug registers (DR0-DR7). The MOV
instruction allows setup data to be loaded to and stored from these registers.
On processors that support Intel 64 architecture, debug registers DR0-DR7 are 64 bits. In 32-bit modes and
compatibility mode, writes to a debug register fill the upper 32 bits with zeros. Reads return the lower 32 bits. In
64-bit mode, the upper 32 bits of DR6-DR7 are reserved and must be written with zeros. Writing one to any of the
upper 32 bits causes an exception, #GP(0).
In 64-bit mode, MOV DRn instructions read or write all 64 bits of a debug register (operand-size prefixes are
ignored). All 64 bits of DR0-DR3 are writable by software. However, MOV DRn instructions do not check that
addresses written to DR0-DR3 are in the limits of the implementation. Address matching is supported only on valid
addresses generated by the processor implementation.
2.8.4
Invalidating Caches and TLBs
The processor provides several instructions for use in explicitly invalidating its caches and TLB entries. The INVD
(invalidate cache with no writeback) instruction invalidates all data and instruction entries in the internal caches
and sends a signal to the external caches indicating that they should also be invalidated.
The WBINVD (invalidate cache with writeback) instruction performs the same function as the INVD instruction,
except that it writes back modified lines in its internal caches to memory before it invalidates the caches. After
invalidating the caches local to the executing logical processor or processor core, WBINVD signals caches higher in
the cache hierarchy (caches shared with the invalidating logical processor or core) to write back any data they have
in modified state at the time of instruction execution and to invalidate their contents.
Note, non-shared caches may not be written back nor invalidated. In Figure 2-10 below, if code executing on either
LP0 or LP1 were to execute a WBINVD, the shared L1 and L2 for LP0/LP1 will be written back and invalidated as will
the shared L3. However, the L1 and L2 caches not shared with LP0 and LP1 will not be written back nor invalidated.
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SYSTEM ARCHITECTURE OVERVIEW
Logical Processors
L1 & L2 Cache
LP0
LP1
LP2
LP3
LP4
LP5
LP6
Not Written back and
not Invalidated
LP7
Written back
& Invalidated
Execution Engine
L3 Cache
Written back and Invalidated
Uncore
QPI
DDR3
Figure 2-10. WBINVD Invalidation of Shared and Non-Shared Cache Hierarchy
The INVLPG (invalidate TLB entry) instruction invalidates (flushes) the TLB entry for a specified page.
2.8.5
Controlling the Processor
The HLT (halt processor) instruction stops the processor until an enabled interrupt (such as NMI or SMI, which are
normally enabled), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal is received. The
processor generates a special bus cycle to indicate that the halt mode has been entered.
Hardware may respond to this signal in a number of ways. An indicator light on the front panel may be turned on.
An NMI interrupt for recording diagnostic information may be generated. Reset initialization may be invoked (note
that the BINIT# pin was introduced with the Pentium Pro processor). If any non-wake events are pending during
shutdown, they will be handled after the wake event from shutdown is processed (for example, A20M# interrupts).
The LOCK prefix invokes a locked (atomic) read-modify-write operation when modifying a memory operand. This
mechanism is used to allow reliable communications between processors in multiprocessor systems, as described
below:
•
In the Pentium processor and earlier IA-32 processors, the LOCK prefix causes the processor to assert the
LOCK# signal during the instruction. This always causes an explicit bus lock to occur.
•
In the Pentium 4, Intel Xeon, and P6 family processors, the locking operation is handled with either a cache lock
or bus lock. If a memory access is cacheable and affects only a single cache line, a cache lock is invoked and
the system bus and the actual memory location in system memory are not locked during the operation. Here,
other Pentium 4, Intel Xeon, or P6 family processors on the bus write-back any modified data and invalidate
their caches as necessary to maintain system memory coherency. If the memory access is not cacheable
and/or it crosses a cache line boundary, the processor’s LOCK# signal is asserted and the processor does not
respond to requests for bus control during the locked operation.
The RSM (return from SMM) instruction restores the processor (from a context dump) to the state it was in prior to
a system management mode (SMM) interrupt.
2.8.6
Reading Performance-Monitoring and Time-Stamp Counters
The RDPMC (read performance-monitoring counter) and RDTSC (read time-stamp counter) instructions allow
application programs to read the processor’s performance-monitoring and time-stamp counters, respectively.
Processors based on Intel NetBurst® microarchitecture have eighteen 40-bit performance-monitoring counters; P6
family processors have two 40-bit counters. Intel® Atom™ processors and most of the processors based on the
Intel Core microarchitecture support two types of performance monitoring counters: programmable performance
counters similar to those available in the P6 family, and three fixed-function performance monitoring counters.
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Details of programmable and fixed-function performance monitoring counters for each processor generation are
described in Chapter 18, “Performance Monitoring”.
The programmable performance counters can support counting either the occurrence or duration of events. Events
that can be monitored on programmable counters generally are model specific (except for architectural performance events enumerated by CPUID leaf 0AH); they may include the number of instructions decoded, interrupts
received, or the number of cache loads. Individual counters can be set up to monitor different events. Use the
system instruction WRMSR to set up values in one of the IA32_PERFEVTSELx MSR, in one of the 45 ESCRs and one
of the 18 CCCR MSRs (for Pentium 4 and Intel Xeon processors); or in the PerfEvtSel0 or the PerfEvtSel1 MSR (for
the P6 family processors). The RDPMC instruction loads the current count from the selected counter into the
EDX:EAX registers.
Fixed-function performance counters record only specific events that are defined in Chapter 19, “Performance
Monitoring Events”, and the width/number of fixed-function counters are enumerated by CPUID leaf 0AH.
The time-stamp counter is a model-specific 64-bit counter that is reset to zero each time the processor is reset. If
not reset, the counter will increment ~9.5 x 1016 times per year when the processor is operating at a clock rate
of 3GHz. At this clock frequency, it would take over 190 years for the counter to wrap around. The RDTSC
instruction loads the current count of the time-stamp counter into the EDX:EAX registers.
See Section 18.1, “Performance Monitoring Overview,” and Section 17.15, “Time-Stamp Counter,” for more information about the performance monitoring and time-stamp counters.
The RDTSC instruction was introduced into the IA-32 architecture with the Pentium processor. The RDPMC instruction was introduced into the IA-32 architecture with the Pentium Pro processor and the Pentium processor with
MMX technology. Earlier Pentium processors have two performance-monitoring counters, but they can be read only
with the RDMSR instruction, and only at privilege level 0.
2.8.6.1
Reading Counters in 64-Bit Mode
In 64-bit mode, RDTSC operates the same as in protected mode. The count in the time-stamp counter is stored in
EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32] cleared).
RDPMC requires an index to specify the offset of the performance-monitoring counter. In 64-bit mode for Pentium
4 or Intel Xeon processor families, the index is specified in ECX[30:0]. The current count of the performance-monitoring counter is stored in EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32] cleared).
2.8.7
Reading and Writing Model-Specific Registers
The RDMSR (read model-specific register) and WRMSR (write model-specific register) instructions allow a
processor’s 64-bit model-specific registers (MSRs) to be read and written, respectively. The MSR to be read or
written is specified by the value in the ECX register.
RDMSR reads the value from the specified MSR to the EDX:EAX registers; WRMSR writes the value in the EDX:EAX
registers to the specified MSR. RDMSR and WRMSR were introduced into the IA-32 architecture with the Pentium
processor.
See Section 9.4, “Model-Specific Registers (MSRs),” for more information.
2.8.7.1
Reading and Writing Model-Specific Registers in 64-Bit Mode
RDMSR and WRMSR require an index to specify the address of an MSR. In 64-bit mode, the index is 32 bits; it is
specified using ECX.
2.8.8
Enabling Processor Extended States
The XSETBV instruction is required to enable OS support of individual processor extended states in XCR0 (see
Section 2.6).
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2-26 Vol. 3A
CHAPTER 3
PROTECTED-MODE MEMORY MANAGEMENT
This chapter describes the Intel 64 and IA-32 architecture’s protected-mode memory management facilities,
including the physical memory requirements, segmentation mechanism, and paging mechanism.
See also: Chapter 5, “Protection” (for a description of the processor’s protection mechanism) and Chapter 20,
“8086 Emulation” (for a description of memory addressing protection in real-address and virtual-8086 modes).
3.1
MEMORY MANAGEMENT OVERVIEW
The memory management facilities of the IA-32 architecture are divided into two parts: segmentation and paging.
Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple
programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mechanism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s
execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation
between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is
no mode bit to disable segmentation. The use of paging, however, is optional.
These two mechanisms (segmentation and paging) can be configured to support simple single-program (or singletask) systems, multitasking systems, or multiple-processor systems that used shared memory.
As shown in Figure 3-1, segmentation provides a mechanism for dividing the processor’s addressable memory
space (called the linear address space) into smaller protected address spaces called segments. Segments can
be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT).
If more than one program (or task) is running on a processor, each program can be assigned its own set of
segments. The processor then enforces the boundaries between these segments and insures that one program
does not interfere with the execution of another program by writing into the other program’s segments. The
segmentation mechanism also allows typing of segments so that the operations that may be performed on a particular type of segment can be restricted.
All the segments in a system are contained in the processor’s linear address space. To locate a byte in a particular
segment, a logical address (also called a far pointer) must be provided. A logical address consists of a segment
selector and an offset. The segment selector is a unique identifier for a segment. Among other things it provides an
offset into a descriptor table (such as the global descriptor table, GDT) to a data structure called a segment
descriptor. Each segment has a segment descriptor, which specifies the size of the segment, the access rights and
privilege level for the segment, the segment type, and the location of the first byte of the segment in the linear
address space (called the base address of the segment). The offset part of the logical address is added to the base
address for the segment to locate a byte within the segment. The base address plus the offset thus forms a linear
address in the processor’s linear address space.
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Logical Address
(or Far Pointer)
Segment
Selector
Offset
Linear Address
Space
Global Descriptor
Table (GDT)
Dir
Linear Address
Table
Offset
Segment
Segment
Descriptor
Lin. Addr.
Page Table
Page Directory
Physical
Address
Space
Page
Phy. Addr.
Entry
Entry
Segment
Base Address
Page
Segmentation
Paging
Figure 3-1. Segmentation and Paging
If paging is not used, the linear address space of the processor is mapped directly into the physical address space
of processor. The physical address space is defined as the range of addresses that the processor can generate on
its address bus.
Because multitasking computing systems commonly define a linear address space much larger than it is economically feasible to contain all at once in physical memory, some method of “virtualizing” the linear address space is
needed. This virtualization of the linear address space is handled through the processor’s paging mechanism.
Paging supports a “virtual memory” environment where a large linear address space is simulated with a small
amount of physical memory (RAM and ROM) and some disk storage. When using paging, each segment is divided
into pages (typically 4 KBytes each in size), which are stored either in physical memory or on the disk. The operating system or executive maintains a page directory and a set of page tables to keep track of the pages. When a
program (or task) attempts to access an address location in the linear address space, the processor uses the page
directory and page tables to translate the linear address into a physical address and then performs the requested
operation (read or write) on the memory location.
If the page being accessed is not currently in physical memory, the processor interrupts execution of the program
(by generating a page-fault exception). The operating system or executive then reads the page into physical
memory from the disk and continues executing the program.
When paging is implemented properly in the operating-system or executive, the swapping of pages between physical memory and the disk is transparent to the correct execution of a program. Even programs written for 16-bit IA32 processors can be paged (transparently) when they are run in virtual-8086 mode.
3.2
USING SEGMENTS
The segmentation mechanism supported by the IA-32 architecture can be used to implement a wide variety of
system designs. These designs range from flat models that make only minimal use of segmentation to protect
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programs to multi-segmented models that employ segmentation to create a robust operating environment in
which multiple programs and tasks can be executed reliably.
The following sections give several examples of how segmentation can be employed in a system to improve
memory management performance and reliability.
3.2.1
Basic Flat Model
The simplest memory model for a system is the basic “flat model,” in which the operating system and application
programs have access to a continuous, unsegmented address space. To the greatest extent possible, this basic flat
model hides the segmentation mechanism of the architecture from both the system designer and the application
programmer.
To implement a basic flat memory model with the IA-32 architecture, at least two segment descriptors must be
created, one for referencing a code segment and one for referencing a data segment (see Figure 3-2). Both of
these segments, however, are mapped to the entire linear address space: that is, both segment descriptors have
the same base address value of 0 and the same segment limit of 4 GBytes. By setting the segment limit to 4
GBytes, the segmentation mechanism is kept from generating exceptions for out of limit memory references, even
if no physical memory resides at a particular address. ROM (EPROM) is generally located at the top of the physical
address space, because the processor begins execution at FFFF_FFF0H. RAM (DRAM) is placed at the bottom of the
address space because the initial base address for the DS data segment after reset initialization is 0.
3.2.2
Protected Flat Model
The protected flat model is similar to the basic flat model, except the segment limits are set to include only the
range of addresses for which physical memory actually exists (see Figure 3-3). A general-protection exception
(#GP) is then generated on any attempt to access nonexistent memory. This model provides a minimum level of
hardware protection against some kinds of program bugs.
Linear Address Space
(or Physical Memory)
Segment
Registers
CS
SS
DS
ES
Code
Code- and Data-Segment
Descriptors
Access
Limit
Base Address
FFFFFFFFH
Not Present
Data and
Stack
0
FS
GS
Figure 3-2. Flat Model
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Segment
Registers
CS
Segment
Descriptors
Linear Address Space
(or Physical Memory)
Access
Limit
Base Address
Code
FFFFFFFFH
Not Present
ES
SS
DS
FS
Access
Limit
Base Address
Memory I/O
Data and
Stack
GS
0
Figure 3-3. Protected Flat Model
More complexity can be added to this protected flat model to provide more protection. For example, for the paging
mechanism to provide isolation between user and supervisor code and data, four segments need to be defined:
code and data segments at privilege level 3 for the user, and code and data segments at privilege level 0 for the
supervisor. Usually these segments all overlay each other and start at address 0 in the linear address space. This
flat segmentation model along with a simple paging structure can protect the operating system from applications,
and by adding a separate paging structure for each task or process, it can also protect applications from each other.
Similar designs are used by several popular multitasking operating systems.
3.2.3
Multi-Segment Model
A multi-segment model (such as the one shown in Figure 3-4) uses the full capabilities of the segmentation mechanism to provide hardware enforced protection of code, data structures, and programs and tasks. Here, each
program (or task) is given its own table of segment descriptors and its own segments. The segments can be
completely private to their assigned programs or shared among programs. Access to all segments and to the
execution environments of individual programs running on the system is controlled by hardware.
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PROTECTED-MODE MEMORY MANAGEMENT
Segment
Registers
Segment
Descriptors
Linear Address Space
(or Physical Memory)
CS
Access
Limit
Base Address
Stack
SS
Access
Limit
Base Address
DS
Access
Limit
Base Address
ES
Access
Limit
Base Address
FS
Access
Limit
Base Address
GS
Access
Limit
Base Address
Access
Limit
Base Address
Code
Data
Data
Data
Access
Limit
Base Address
Access
Limit
Base Address
Data
Access
Limit
Base Address
Figure 3-4. Multi-Segment Model
Access checks can be used to protect not only against referencing an address outside the limit of a segment, but
also against performing disallowed operations in certain segments. For example, since code segments are designated as read-only segments, hardware can be used to prevent writes into code segments. The access rights information created for segments can also be used to set up protection rings or levels. Protection levels can be used to
protect operating-system procedures from unauthorized access by application programs.
3.2.4
Segmentation in IA-32e Mode
In IA-32e mode of Intel 64 architecture, the effects of segmentation depend on whether the processor is running
in compatibility mode or 64-bit mode. In compatibility mode, segmentation functions just as it does using legacy
16-bit or 32-bit protected mode semantics.
In 64-bit mode, segmentation is generally (but not completely) disabled, creating a flat 64-bit linear-address
space. The processor treats the segment base of CS, DS, ES, SS as zero, creating a linear address that is equal to
the effective address. The FS and GS segments are exceptions. These segment registers (which hold the segment
base) can be used as additional base registers in linear address calculations. They facilitate addressing local data
and certain operating system data structures.
Note that the processor does not perform segment limit checks at runtime in 64-bit mode.
3.2.5
Paging and Segmentation
Paging can be used with any of the segmentation models described in Figures 3-2, 3-3, and 3-4. The processor’s
paging mechanism divides the linear address space (into which segments are mapped) into pages (as shown in
Figure 3-1). These linear-address-space pages are then mapped to pages in the physical address space. The
paging mechanism offers several page-level protection facilities that can be used with or instead of the segment-
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protection facilities. For example, it lets read-write protection be enforced on a page-by-page basis. The paging
mechanism also provides two-level user-supervisor protection that can also be specified on a page-by-page basis.
3.3
PHYSICAL ADDRESS SPACE
In protected mode, the IA-32 architecture provides a normal physical address space of 4 GBytes (232 bytes). This
is the address space that the processor can address on its address bus. This address space is flat (unsegmented),
with addresses ranging continuously from 0 to FFFFFFFFH. This physical address space can be mapped to readwrite memory, read-only memory, and memory mapped I/O. The memory mapping facilities described in this
chapter can be used to divide this physical memory up into segments and/or pages.
Starting with the Pentium Pro processor, the IA-32 architecture also supports an extension of the physical address
space to 236 bytes (64 GBytes); with a maximum physical address of FFFFFFFFFH. This extension is invoked in
either of two ways:
•
•
Using the physical address extension (PAE) flag, located in bit 5 of control register CR4.
Using the 36-bit page size extension (PSE-36) feature (introduced in the Pentium III processors).
Physical address support has since been extended beyond 36 bits. See Chapter 4, “Paging” for more information
about 36-bit physical addressing.
3.3.1
Intel® 64 Processors and Physical Address Space
On processors that support Intel 64 architecture (CPUID.80000001H:EDX[29] = 1), the size of the physical
address range is implementation-specific and indicated by CPUID.80000008H:EAX[bits 7-0].
For the format of information returned in EAX, see “CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A. See also: Chapter 4, “Paging.”
3.4
LOGICAL AND LINEAR ADDRESSES
At the system-architecture level in protected mode, the processor uses two stages of address translation to arrive
at a physical address: logical-address translation and linear address space paging.
Even with the minimum use of segments, every byte in the processor’s address space is accessed with a logical
address. A logical address consists of a 16-bit segment selector and a 32-bit offset (see Figure 3-5). The segment
selector identifies the segment the byte is located in and the offset specifies the location of the byte in the segment
relative to the base address of the segment.
The processor translates every logical address into a linear address. A linear address is a 32-bit address in the
processor’s linear address space. Like the physical address space, the linear address space is a flat (unsegmented),
232-byte address space, with addresses ranging from 0 to FFFFFFFFH. The linear address space contains all the
segments and system tables defined for a system.
To translate a logical address into a linear address, the processor does the following:
1. Uses the offset in the segment selector to locate the segment descriptor for the segment in the GDT or LDT and
reads it into the processor. (This step is needed only when a new segment selector is loaded into a segment
register.)
2. Examines the segment descriptor to check the access rights and range of the segment to insure that the
segment is accessible and that the offset is within the limits of the segment.
3. Adds the base address of the segment from the segment descriptor to the offset to form a linear address.
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Logical
Address
31(63)
0
Offset (Effective Address)
15
0
Seg. Selector
Descriptor Table
Segment
Descriptor
Base Address
+
31(63)
0
Linear Address
Figure 3-5. Logical Address to Linear Address Translation
If paging is not used, the processor maps the linear address directly to a physical address (that is, the linear
address goes out on the processor’s address bus). If the linear address space is paged, a second level of address
translation is used to translate the linear address into a physical address.
See also: Chapter 4, “Paging.”
3.4.1
Logical Address Translation in IA-32e Mode
In IA-32e mode, an Intel 64 processor uses the steps described above to translate a logical address to a linear
address. In 64-bit mode, the offset and base address of the segment are 64-bits instead of 32 bits. The linear
address format is also 64 bits wide and is subject to the canonical form requirement.
Each code segment descriptor provides an L bit. This bit allows a code segment to execute 64-bit code or legacy
32-bit code by code segment.
3.4.2
Segment Selectors
A segment selector is a 16-bit identifier for a segment (see Figure 3-6). It does not point directly to the segment,
but instead points to the segment descriptor that defines the segment. A segment selector contains the following
items:
Index
(Bits 3 through 15) — Selects one of 8192 descriptors in the GDT or LDT. The processor multiplies
the index value by 8 (the number of bytes in a segment descriptor) and adds the result to the base
address of the GDT or LDT (from the GDTR or LDTR register, respectively).
TI (table indicator) flag
(Bit 2) — Specifies the descriptor table to use: clearing this flag selects the GDT; setting this flag
selects the current LDT.
15
3 2 1 0
Index
T RPL
I
Table Indicator
0 = GDT
1 = LDT
Requested Privilege Level (RPL)
Figure 3-6. Segment Selector
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PROTECTED-MODE MEMORY MANAGEMENT
Requested Privilege Level (RPL)
(Bits 0 and 1) — Specifies the privilege level of the selector. The privilege level can range from 0 to
3, with 0 being the most privileged level. See Section 5.5, “Privilege Levels”, for a description of the
relationship of the RPL to the CPL of the executing program (or task) and the descriptor privilege
level (DPL) of the descriptor the segment selector points to.
The first entry of the GDT is not used by the processor. A segment selector that points to this entry of the GDT (that
is, a segment selector with an index of 0 and the TI flag set to 0) is used as a “null segment selector.” The processor
does not generate an exception when a segment register (other than the CS or SS registers) is loaded with a null
selector. It does, however, generate an exception when a segment register holding a null selector is used to access
memory. A null selector can be used to initialize unused segment registers. Loading the CS or SS register with a null
segment selector causes a general-protection exception (#GP) to be generated.
Segment selectors are visible to application programs as part of a pointer variable, but the values of selectors are
usually assigned or modified by link editors or linking loaders, not application programs.
3.4.3
Segment Registers
To reduce address translation time and coding complexity, the processor provides registers for holding up to 6
segment selectors (see Figure 3-7). Each of these segment registers support a specific kind of memory reference
(code, stack, or data). For virtually any kind of program execution to take place, at least the code-segment (CS),
data-segment (DS), and stack-segment (SS) registers must be loaded with valid segment selectors. The processor
also provides three additional data-segment registers (ES, FS, and GS), which can be used to make additional data
segments available to the currently executing program (or task).
For a program to access a segment, the segment selector for the segment must have been loaded in one of the
segment registers. So, although a system can define thousands of segments, only 6 can be available for immediate
use. Other segments can be made available by loading their segment selectors into these registers during program
execution.
Visible Part
Segment Selector
Hidden Part
Base Address, Limit, Access Information
CS
SS
DS
ES
FS
GS
Figure 3-7. Segment Registers
Every segment register has a “visible” part and a “hidden” part. (The hidden part is sometimes referred to as a
“descriptor cache” or a “shadow register.”) When a segment selector is loaded into the visible part of a segment
register, the processor also loads the hidden part of the segment register with the base address, segment limit, and
access control information from the segment descriptor pointed to by the segment selector. The information cached
in the segment register (visible and hidden) allows the processor to translate addresses without taking extra bus
cycles to read the base address and limit from the segment descriptor. In systems in which multiple processors
have access to the same descriptor tables, it is the responsibility of software to reload the segment registers when
the descriptor tables are modified. If this is not done, an old segment descriptor cached in a segment register might
be used after its memory-resident version has been modified.
Two kinds of load instructions are provided for loading the segment registers:
1. Direct load instructions such as the MOV, POP, LDS, LES, LSS, LGS, and LFS instructions. These instructions
explicitly reference the segment registers.
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2. Implied load instructions such as the far pointer versions of the CALL, JMP, and RET instructions, the SYSENTER
and SYSEXIT instructions, and the IRET, INTn, INTO and INT3 instructions. These instructions change the
contents of the CS register (and sometimes other segment registers) as an incidental part of their operation.
The MOV instruction can also be used to store the visible part of a segment register in a general-purpose register.
3.4.4
Segment Loading Instructions in IA-32e Mode
Because ES, DS, and SS segment registers are not used in 64-bit mode, their fields (base, limit, and attribute) in
segment descriptor registers are ignored. Some forms of segment load instructions are also invalid (for example,
LDS, POP ES). Address calculations that reference the ES, DS, or SS segments are treated as if the segment base
is zero.
The processor checks that all linear-address references are in canonical form instead of performing limit checks.
Mode switching does not change the contents of the segment registers or the associated descriptor registers.
These registers are also not changed during 64-bit mode execution, unless explicit segment loads are performed.
In order to set up compatibility mode for an application, segment-load instructions (MOV to Sreg, POP Sreg) work
normally in 64-bit mode. An entry is read from the system descriptor table (GDT or LDT) and is loaded in the
hidden portion of the segment register. The descriptor-register base, limit, and attribute fields are all loaded.
However, the contents of the data and stack segment selector and the descriptor registers are ignored.
When FS and GS segment overrides are used in 64-bit mode, their respective base addresses are used in the linear
address calculation: (FS or GS).base + index + displacement. FS.base and GS.base are then expanded to the full
linear-address size supported by the implementation. The resulting effective address calculation can wrap across
positive and negative addresses; the resulting linear address must be canonical.
In 64-bit mode, memory accesses using FS-segment and GS-segment overrides are not checked for a runtime limit
nor subjected to attribute-checking. Normal segment loads (MOV to Sreg and POP Sreg) into FS and GS load a
standard 32-bit base value in the hidden portion of the segment register. The base address bits above the standard
32 bits are cleared to 0 to allow consistency for implementations that use less than 64 bits.
The hidden descriptor register fields for FS.base and GS.base are physically mapped to MSRs in order to load all
address bits supported by a 64-bit implementation. Software with CPL = 0 (privileged software) can load all
supported linear-address bits into FS.base or GS.base using WRMSR. Addresses written into the 64-bit FS.base
and GS.base registers must be in canonical form. A WRMSR instruction that attempts to write a non-canonical
address to those registers causes a #GP fault.
When in compatibility mode, FS and GS overrides operate as defined by 32-bit mode behavior regardless of the
value loaded into the upper 32 linear-address bits of the hidden descriptor register base field. Compatibility mode
ignores the upper 32 bits when calculating an effective address.
A new 64-bit mode instruction, SWAPGS, can be used to load GS base. SWAPGS exchanges the kernel data structure pointer from the IA32_KERNEL_GS_BASE MSR with the GS base register. The kernel can then use the GS
prefix on normal memory references to access the kernel data structures. An attempt to write a non-canonical
value (using WRMSR) to the IA32_KERNEL_GS_BASE MSR causes a #GP fault.
3.4.5
Segment Descriptors
A segment descriptor is a data structure in a GDT or LDT that provides the processor with the size and location of
a segment, as well as access control and status information. Segment descriptors are typically created by
compilers, linkers, loaders, or the operating system or executive, but not application programs. Figure 3-8 illustrates the general descriptor format for all types of segment descriptors.
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31
24 23 22 21 20 19
Base 31:24
D
A
G / L V
B
L
31
16 15 14 13 12 11
Seg.
Limit
19:16
P
D
P
L
S
0
8 7
Type
16 15
Base Address 15:00
4
Base 23:16
0
Segment Limit 15:00
0
L
— 64-bit code segment (IA-32e mode only)
AVL — Available for use by system software
BASE — Segment base address
D/B — Default operation size (0 = 16-bit segment; 1 = 32-bit segment)
DPL — Descriptor privilege level
G
— Granularity
LIMIT — Segment Limit
P
— Segment present
S
— Descriptor type (0 = system; 1 = code or data)
TYPE — Segment type
Figure 3-8. Segment Descriptor
The flags and fields in a segment descriptor are as follows:
Segment limit field
Specifies the size of the segment. The processor puts together the two segment limit fields to form
a 20-bit value. The processor interprets the segment limit in one of two ways, depending on the
setting of the G (granularity) flag:
•
If the granularity flag is clear, the segment size can range from 1 byte to 1 MByte, in byte increments.
•
If the granularity flag is set, the segment size can range from 4 KBytes to 4 GBytes, in 4-KByte
increments.
The processor uses the segment limit in two different ways, depending on whether the segment is
an expand-up or an expand-down segment. See Section 3.4.5.1, “Code- and Data-Segment
Descriptor Types”, for more information about segment types. For expand-up segments, the offset
in a logical address can range from 0 to the segment limit. Offsets greater than the segment limit
generate general-protection exceptions (#GP, for all segments other than SS) or stack-fault exceptions (#SS for the SS segment). For expand-down segments, the segment limit has the reverse
function; the offset can range from the segment limit plus 1 to FFFFFFFFH or FFFFH, depending on
the setting of the B flag. Offsets less than or equal to the segment limit generate general-protection
exceptions or stack-fault exceptions. Decreasing the value in the segment limit field for an expanddown segment allocates new memory at the bottom of the segment's address space, rather than at
the top. IA-32 architecture stacks always grow downwards, making this mechanism convenient for
expandable stacks.
Base address fields
Defines the location of byte 0 of the segment within the 4-GByte linear address space. The
processor puts together the three base address fields to form a single 32-bit value. Segment base
addresses should be aligned to 16-byte boundaries. Although 16-byte alignment is not required,
this alignment allows programs to maximize performance by aligning code and data on 16-byte
boundaries.
Type field
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Indicates the segment or gate type and specifies the kinds of access that can be made to the
segment and the direction of growth. The interpretation of this field depends on whether the
descriptor type flag specifies an application (code or data) descriptor or a system descriptor. The
encoding of the type field is different for code, data, and system descriptors (see Figure 5-1). See
Section 3.4.5.1, “Code- and Data-Segment Descriptor Types”, for a description of how this field is
used to specify code and data-segment types.
PROTECTED-MODE MEMORY MANAGEMENT
S (descriptor type) flag
Specifies whether the segment descriptor is for a system segment (S flag is clear) or a code or data
segment (S flag is set).
DPL (descriptor privilege level) field
Specifies the privilege level of the segment. The privilege level can range from 0 to 3, with 0 being
the most privileged level. The DPL is used to control access to the segment. See Section 5.5, “Privilege Levels”, for a description of the relationship of the DPL to the CPL of the executing code
segment and the RPL of a segment selector.
P (segment-present) flag
Indicates whether the segment is present in memory (set) or not present (clear). If this flag is clear,
the processor generates a segment-not-present exception (#NP) when a segment selector that
points to the segment descriptor is loaded into a segment register. Memory management software
can use this flag to control which segments are actually loaded into physical memory at a given
time. It offers a control in addition to paging for managing virtual memory.
Figure 3-9 shows the format of a segment descriptor when the segment-present flag is clear. When
this flag is clear, the operating system or executive is free to use the locations marked “Available” to
store its own data, such as information regarding the whereabouts of the missing segment.
D/B (default operation size/default stack pointer size and/or upper bound) flag
Performs different functions depending on whether the segment descriptor is an executable code
segment, an expand-down data segment, or a stack segment. (This flag should always be set to 1
for 32-bit code and data segments and to 0 for 16-bit code and data segments.)
•
Executable code segment. The flag is called the D flag and it indicates the default length for
effective addresses and operands referenced by instructions in the segment. If the flag is set,
32-bit addresses and 32-bit or 8-bit operands are assumed; if it is clear, 16-bit addresses and
16-bit or 8-bit operands are assumed.
The instruction prefix 66H can be used to select an operand size other than the default, and the
prefix 67H can be used select an address size other than the default.
•
Stack segment (data segment pointed to by the SS register). The flag is called the B (big)
flag and it specifies the size of the stack pointer used for implicit stack operations (such as
pushes, pops, and calls). If the flag is set, a 32-bit stack pointer is used, which is stored in the
32-bit ESP register; if the flag is clear, a 16-bit stack pointer is used, which is stored in the 16bit SP register. If the stack segment is set up to be an expand-down data segment (described in
the next paragraph), the B flag also specifies the upper bound of the stack segment.
•
Expand-down data segment. The flag is called the B flag and it specifies the upper bound of
the segment. If the flag is set, the upper bound is FFFFFFFFH (4 GBytes); if the flag is clear, the
upper bound is FFFFH (64 KBytes).
31
16 15 14 13 12 11
Available
0
D
P
L
31
S
0
8 7
Type
4
Available
0
Available
0
Figure 3-9. Segment Descriptor When Segment-Present Flag Is Clear
G (granularity) flag
Determines the scaling of the segment limit field. When the granularity flag is clear, the segment
limit is interpreted in byte units; when flag is set, the segment limit is interpreted in 4-KByte units.
(This flag does not affect the granularity of the base address; it is always byte granular.) When the
granularity flag is set, the twelve least significant bits of an offset are not tested when checking the
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offset against the segment limit. For example, when the granularity flag is set, a limit of 0 results in
valid offsets from 0 to 4095.
L (64-bit code segment) flag
In IA-32e mode, bit 21 of the second doubleword of the segment descriptor indicates whether a
code segment contains native 64-bit code. A value of 1 indicates instructions in this code segment
are executed in 64-bit mode. A value of 0 indicates the instructions in this code segment are
executed in compatibility mode. If L-bit is set, then D-bit must be cleared. When not in IA-32e mode
or for non-code segments, bit 21 is reserved and should always be set to 0.
Available and reserved bits
Bit 20 of the second doubleword of the segment descriptor is available for use by system software.
3.4.5.1
Code- and Data-Segment Descriptor Types
When the S (descriptor type) flag in a segment descriptor is set, the descriptor is for either a code or a data
segment. The highest order bit of the type field (bit 11 of the second double word of the segment descriptor) then
determines whether the descriptor is for a data segment (clear) or a code segment (set).
For data segments, the three low-order bits of the type field (bits 8, 9, and 10) are interpreted as accessed (A),
write-enable (W), and expansion-direction (E). See Table 3-1 for a description of the encoding of the bits in the
type field for code and data segments. Data segments can be read-only or read/write segments, depending on the
setting of the write-enable bit.
Table 3-1. Code- and Data-Segment Types
Type Field
Descriptor
Type
Description
Decimal
11
10
E
9
W
8
A
0
0
0
0
0
Data
Read-Only
1
0
0
0
1
Data
Read-Only, accessed
2
0
0
1
0
Data
Read/Write
3
0
0
1
1
Data
Read/Write, accessed
4
0
1
0
0
Data
Read-Only, expand-down
5
0
1
0
1
Data
Read-Only, expand-down, accessed
6
0
1
1
0
Data
Read/Write, expand-down
7
0
1
1
1
Data
Read/Write, expand-down, accessed
C
R
A
8
1
0
0
0
Code
Execute-Only
9
1
0
0
1
Code
Execute-Only, accessed
10
1
0
1
0
Code
Execute/Read
11
1
0
1
1
Code
Execute/Read, accessed
12
1
1
0
0
Code
Execute-Only, conforming
13
1
1
0
1
Code
Execute-Only, conforming, accessed
14
1
1
1
0
Code
Execute/Read, conforming
15
1
1
1
1
Code
Execute/Read, conforming, accessed
Stack segments are data segments which must be read/write segments. Loading the SS register with a segment
selector for a nonwritable data segment generates a general-protection exception (#GP). If the size of a stack
segment needs to be changed dynamically, the stack segment can be an expand-down data segment (expansiondirection flag set). Here, dynamically changing the segment limit causes stack space to be added to the bottom of
3-12 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
the stack. If the size of a stack segment is intended to remain static, the stack segment may be either an expandup or expand-down type.
The accessed bit indicates whether the segment has been accessed since the last time the operating-system or
executive cleared the bit. The processor sets this bit whenever it loads a segment selector for the segment into a
segment register, assuming that the type of memory that contains the segment descriptor supports processor
writes. The bit remains set until explicitly cleared. This bit can be used both for virtual memory management and
for debugging.
For code segments, the three low-order bits of the type field are interpreted as accessed (A), read enable (R), and
conforming (C). Code segments can be execute-only or execute/read, depending on the setting of the read-enable
bit. An execute/read segment might be used when constants or other static data have been placed with instruction
code in a ROM. Here, data can be read from the code segment either by using an instruction with a CS override
prefix or by loading a segment selector for the code segment in a data-segment register (the DS, ES, FS, or GS
registers). In protected mode, code segments are not writable.
Code segments can be either conforming or nonconforming. A transfer of execution into a more-privileged
conforming segment allows execution to continue at the current privilege level. A transfer into a nonconforming
segment at a different privilege level results in a general-protection exception (#GP), unless a call gate or task
gate is used (see Section 5.8.1, “Direct Calls or Jumps to Code Segments”, for more information on conforming and
nonconforming code segments). System utilities that do not access protected facilities and handlers for some types
of exceptions (such as, divide error or overflow) may be loaded in conforming code segments. Utilities that need to
be protected from less privileged programs and procedures should be placed in nonconforming code segments.
NOTE
Execution cannot be transferred by a call or a jump to a less-privileged (numerically higher
privilege level) code segment, regardless of whether the target segment is a conforming or
nonconforming code segment. Attempting such an execution transfer will result in a generalprotection exception.
All data segments are nonconforming, meaning that they cannot be accessed by less privileged programs or procedures (code executing at numerically higher privilege levels). Unlike code segments, however, data segments can
be accessed by more privileged programs or procedures (code executing at numerically lower privilege levels)
without using a special access gate.
If the segment descriptors in the GDT or an LDT are placed in ROM, the processor can enter an indefinite loop if
software or the processor attempts to update (write to) the ROM-based segment descriptors. To prevent this
problem, set the accessed bits for all segment descriptors placed in a ROM. Also, remove operating-system or
executive code that attempts to modify segment descriptors located in ROM.
3.5
SYSTEM DESCRIPTOR TYPES
When the S (descriptor type) flag in a segment descriptor is clear, the descriptor type is a system descriptor. The
processor recognizes the following types of system descriptors:
•
•
•
•
•
•
Local descriptor-table (LDT) segment descriptor.
Task-state segment (TSS) descriptor.
Call-gate descriptor.
Interrupt-gate descriptor.
Trap-gate descriptor.
Task-gate descriptor.
These descriptor types fall into two categories: system-segment descriptors and gate descriptors. Systemsegment descriptors point to system segments (LDT and TSS segments). Gate descriptors are in themselves
“gates,” which hold pointers to procedure entry points in code segments (call, interrupt, and trap gates) or which
hold segment selectors for TSS’s (task gates).
Vol. 3A 3-13
PROTECTED-MODE MEMORY MANAGEMENT
Table 3-2 shows the encoding of the type field for system-segment descriptors and gate descriptors. Note that
system descriptors in IA-32e mode are 16 bytes instead of 8 bytes.
Table 3-2. System-Segment and Gate-Descriptor Types
Type Field
Description
Decimal
11
10
9
8
32-Bit Mode
IA-32e Mode
0
0
0
0
0
Reserved
Upper 8 bytes of an 16-byte
descriptor
1
0
0
0
1
16-bit TSS (Available)
Reserved
2
0
0
1
0
LDT
LDT
3
0
0
1
1
16-bit TSS (Busy)
Reserved
4
0
1
0
0
16-bit Call Gate
Reserved
5
0
1
0
1
Task Gate
Reserved
6
0
1
1
0
16-bit Interrupt Gate
Reserved
7
0
1
1
1
16-bit Trap Gate
Reserved
8
1
0
0
0
Reserved
Reserved
9
1
0
0
1
32-bit TSS (Available)
64-bit TSS (Available)
10
1
0
1
0
Reserved
Reserved
11
1
0
1
1
32-bit TSS (Busy)
64-bit TSS (Busy)
12
1
1
0
0
32-bit Call Gate
64-bit Call Gate
13
1
1
0
1
Reserved
Reserved
14
1
1
1
0
32-bit Interrupt Gate
64-bit Interrupt Gate
15
1
1
1
1
32-bit Trap Gate
64-bit Trap Gate
See also: Section 3.5.1, “Segment Descriptor Tables”, and Section 7.2.2, “TSS Descriptor” (for more information
on the system-segment descriptors); see Section 5.8.3, “Call Gates”, Section 6.11, “IDT Descriptors”, and Section
7.2.5, “Task-Gate Descriptor” (for more information on the gate descriptors).
3.5.1
Segment Descriptor Tables
A segment descriptor table is an array of segment descriptors (see Figure 3-10). A descriptor table is variable in
length and can contain up to 8192 (213) 8-byte descriptors. There are two kinds of descriptor tables:
•
•
The global descriptor table (GDT)
The local descriptor tables (LDT)
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PROTECTED-MODE MEMORY MANAGEMENT
T
I
Segment
Selector
Global
Descriptor
Table (GDT)
Local
Descriptor
Table (LDT)
TI = 0
TI = 1
First Descriptor in
GDT is Not Used
56
56
48
48
40
40
32
32
24
24
16
16
8
8
0
0
GDTR Register
LDTR Register
Limit
Base Address
Limit
Base Address
Seg. Sel.
Figure 3-10. Global and Local Descriptor Tables
Each system must have one GDT defined, which may be used for all programs and tasks in the system. Optionally,
one or more LDTs can be defined. For example, an LDT can be defined for each separate task being run, or some or
all tasks can share the same LDT.
The GDT is not a segment itself; instead, it is a data structure in linear address space. The base linear address and
limit of the GDT must be loaded into the GDTR register (see Section 2.4, “Memory-Management Registers”). The
base address of the GDT should be aligned on an eight-byte boundary to yield the best processor performance. The
limit value for the GDT is expressed in bytes. As with segments, the limit value is added to the base address to get
the address of the last valid byte. A limit value of 0 results in exactly one valid byte. Because segment descriptors
are always 8 bytes long, the GDT limit should always be one less than an integral multiple of eight (that is, 8N – 1).
The first descriptor in the GDT is not used by the processor. A segment selector to this “null descriptor” does not
generate an exception when loaded into a data-segment register (DS, ES, FS, or GS), but it always generates a
general-protection exception (#GP) when an attempt is made to access memory using the descriptor. By initializing
the segment registers with this segment selector, accidental reference to unused segment registers can be guaranteed to generate an exception.
The LDT is located in a system segment of the LDT type. The GDT must contain a segment descriptor for the LDT
segment. If the system supports multiple LDTs, each must have a separate segment selector and segment
descriptor in the GDT. The segment descriptor for an LDT can be located anywhere in the GDT. See Section 3.5,
“System Descriptor Types”, for information on the LDT segment-descriptor type.
An LDT is accessed with its segment selector. To eliminate address translations when accessing the LDT, the
segment selector, base linear address, limit, and access rights of the LDT are stored in the LDTR register (see
Section 2.4, “Memory-Management Registers”).
When the GDTR register is stored (using the SGDT instruction), a 48-bit “pseudo-descriptor” is stored in memory
(see top diagram in Figure 3-11). To avoid alignment check faults in user mode (privilege level 3), the pseudodescriptor should be located at an odd word address (that is, address MOD 4 is equal to 2). This causes the
Vol. 3A 3-15
PROTECTED-MODE MEMORY MANAGEMENT
processor to store an aligned word, followed by an aligned doubleword. User-mode programs normally do not store
pseudo-descriptors, but the possibility of generating an alignment check fault can be avoided by aligning pseudodescriptors in this way. The same alignment should be used when storing the IDTR register using the SIDT instruction. When storing the LDTR or task register (using the SLDT or STR instruction, respectively), the pseudodescriptor should be located at a doubleword address (that is, address MOD 4 is equal to 0).
47
16 15
79
0
Limit
32-bit Base Address
0
16 15
64-bit Base Address
Limit
Figure 3-11. Pseudo-Descriptor Formats
3.5.2
Segment Descriptor Tables in IA-32e Mode
In IA-32e mode, a segment descriptor table can contain up to 8192 (213) 8-byte descriptors. An entry in the
segment descriptor table can be 8 bytes. System descriptors are expanded to 16 bytes (occupying the space of two
entries).
GDTR and LDTR registers are expanded to hold 64-bit base address. The corresponding pseudo-descriptor is 80
bits. (see the bottom diagram in Figure 3-11).
The following system descriptors expand to 16 bytes:
— Call gate descriptors (see Section 5.8.3.1, “IA-32e Mode Call Gates”)
— IDT gate descriptors (see Section 6.14.1, “64-Bit Mode IDT”)
— LDT and TSS descriptors (see Section 7.2.3, “TSS Descriptor in 64-bit mode”).
3-16 Vol. 3A
CHAPTER 4
PAGING
Chapter 3 explains how segmentation converts logical addresses to linear addresses. Paging (or linear-address
translation) is the process of translating linear addresses so that they can be used to access memory or I/O
devices. Paging translates each linear address to a physical address and determines, for each translation, what
accesses to the linear address are allowed (the address’s access rights) and the type of caching used for such
accesses (the address’s memory type).
Intel-64 processors support three different paging modes. These modes are identified and defined in Section 4.1.
Section 4.2 gives an overview of the translation mechanism that is used in all modes. Section 4.3, Section 4.4, and
Section 4.5 discuss the three paging modes in detail.
Section 4.6 details how paging determines and uses access rights. Section 4.7 discusses exceptions that may be
generated by paging (page-fault exceptions). Section 4.8 considers data which the processor writes in response to
linear-address accesses (accessed and dirty flags).
Section 4.9 describes how paging determines the memory types used for accesses to linear addresses. Section
4.10 provides details of how a processor may cache information about linear-address translation. Section 4.11
outlines interactions between paging and certain VMX features. Section 4.12 gives an overview of how paging can
be used to implement virtual memory.
4.1
PAGING MODES AND CONTROL BITS
Paging behavior is controlled by the following control bits:
•
•
The WP and PG flags in control register CR0 (bit 16 and bit 31, respectively).
•
•
The LME and NXE flags in the IA32_EFER MSR (bit 8 and bit 11, respectively).
The PSE, PAE, PGE, PCIDE, SMEP, SMAP, and PKE flags in control register CR4 (bit 4, bit 5, bit 7, bit 17, bit 20,
bit 21, and bit 22, respectively).
The AC flag in the EFLAGS register (bit 18).
Software enables paging by using the MOV to CR0 instruction to set CR0.PG. Before doing so, software should
ensure that control register CR3 contains the physical address of the first paging structure that the processor will
use for linear-address translation (see Section 4.2) and that structure is initialized as desired. See Table 4-3,
Table 4-7, and Table 4-12 for the use of CR3 in the different paging modes.
Section 4.1.1 describes how the values of CR0.PG, CR4.PAE, and IA32_EFER.LME determine whether paging is in
use and, if so, which of three paging modes is in use. Section 4.1.2 explains how to manage these bits to establish
or make changes in paging modes. Section 4.1.3 discusses how CR0.WP, CR4.PSE, CR4.PGE, CR4.PCIDE,
CR4.SMEP, CR4.SMAP, CR4.PKE, and IA32_EFER.NXE modify the operation of the different paging modes.
4.1.1
Three Paging Modes
If CR0.PG = 0, paging is not used. The logical processor treats all linear addresses as if they were physical
addresses. CR4.PAE and IA32_EFER.LME are ignored by the processor, as are CR0.WP, CR4.PSE, CR4.PGE,
CR4.SMEP, CR4.SMAP, and IA32_EFER.NXE.
Paging is enabled if CR0.PG = 1. Paging can be enabled only if protection is enabled (CR0.PE = 1). If paging is
enabled, one of three paging modes is used. The values of CR4.PAE and IA32_EFER.LME determine which paging
mode is used:
•
If CR0.PG = 1 and CR4.PAE = 0, 32-bit paging is used. 32-bit paging is detailed in Section 4.3. 32-bit paging
uses CR0.WP, CR4.PSE, CR4.PGE, CR4.SMEP, and CR4.SMAP as described in Section 4.1.3.
•
If CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 0, PAE paging is used. PAE paging is detailed in Section
4.4. PAE paging uses CR0.WP, CR4.PGE, CR4.SMEP, CR4.SMAP, and IA32_EFER.NXE as described in Section
4.1.3.
Vol. 3A 4-1
PAGING
•
If CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 1, IA-32e paging is used.1 IA-32e paging is detailed in
Section 4.5. IA-32e paging uses CR0.WP, CR4.PGE, CR4.PCIDE, CR4.SMEP, CR4.SMAP, CR4.PKE, and
IA32_EFER.NXE as described in Section 4.1.3. IA-32e paging is available only on processors that support the
Intel 64 architecture.
The three paging modes differ with regard to the following details:
•
•
•
Linear-address width. The size of the linear addresses that can be translated.
•
Support for execute-disable access rights. In some paging modes, software can be prevented from fetching
instructions from pages that are otherwise readable.
•
Support for PCIDs. With IA-32e paging, software can enable a facility by which a logical processor caches
information for multiple linear-address spaces. The processor may retain cached information when software
switches between different linear-address spaces.
•
Support for protection keys. With IA-32e paging, software can enable a facility by which each linear address is
associated with a protection key. Software can use a new control register to determine, for each protection
keys, how software can access linear addresses associated with that protection key.
Physical-address width. The size of the physical addresses produced by paging.
Page size. The granularity at which linear addresses are translated. Linear addresses on the same page are
translated to corresponding physical addresses on the same page.
Table 4-1 illustrates the principal differences between the three paging modes.
Table 4-1. Properties of Different Paging Modes
Paging
Mode
PG in
CR0
PAE in
CR4
LME in
IA32_EFER
Lin.Addr.
Width
Phys.Addr.
Width1
Page
Sizes
Supports
ExecuteDisable?
Supports
PCIDs and
protection
keys?
None
0
N/A
N/A
32
32
N/A
No
No
32-bit
1
0
02
32
Up to
403
4 KB
4 MB4
No
No
PAE
1
1
0
32
Up to
52
4 KB
2 MB
Yes5
No
IA-32e
1
1
1
48
Up to
52
4 KB
2 MB
1 GB6
Yes5
Yes7
NOTES:
1. The physical-address width is always bounded by MAXPHYADDR; see Section 4.1.4.
2. The processor ensures that IA32_EFER.LME must be 0 if CR0.PG = 1 and CR4.PAE = 0.
3. 32-bit paging supports physical-address widths of more than 32 bits only for 4-MByte pages and only if the PSE-36 mechanism is
supported; see Section 4.1.4 and Section 4.3.
4. 4-MByte pages are used with 32-bit paging only if CR4.PSE = 1; see Section 4.3.
5. Execute-disable access rights are applied only if IA32_EFER.NXE = 1; see Section 4.6.
6. Not all processors that support IA-32e paging support 1-GByte pages; see Section 4.1.4.
7. PCIDs are used only if CR4.PCIDE = 1; see Section 4.10.1. Protection keys are used only if certain conditions hold; see Section 4.6.2.
Because they are used only if IA32_EFER.LME = 0, 32-bit paging and PAE paging are used only in legacy protected
mode. Because legacy protected mode cannot produce linear addresses larger than 32 bits, 32-bit paging and PAE
paging translate 32-bit linear addresses.
1. The LMA flag in the IA32_EFER MSR (bit 10) is a status bit that indicates whether the logical processor is in IA-32e mode (and thus
using IA-32e paging). The processor always sets IA32_EFER.LMA to CR0.PG & IA32_EFER.LME. Software cannot directly modify
IA32_EFER.LMA; an execution of WRMSR to the IA32_EFER MSR ignores bit 10 of its source operand.
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PAGING
Because it is used only if IA32_EFER.LME = 1, IA-32e paging is used only in IA-32e mode. (In fact, it is the use of
IA-32e paging that defines IA-32e mode.) IA-32e mode has two sub-modes:
•
Compatibility mode. This mode uses only 32-bit linear addresses. IA-32e paging treats bits 47:32 of such an
address as all 0.
•
64-bit mode. While this mode produces 64-bit linear addresses, the processor ensures that bits 63:47 of such
an address are identical.1 IA-32e paging does not use bits 63:48 of such addresses.
4.1.2
Paging-Mode Enabling
If CR0.PG = 1, a logical processor is in one of three paging modes, depending on the values of CR4.PAE and
IA32_EFER.LME. Figure 4-1 illustrates how software can enable these modes and make transitions between them.
The following items identify certain limitations and other details:
#GP
#GP
Set LME
No Paging
Set PG
PG = 0
PAE = 0
LME = 0
Clear PG
Set LME
32-bit Paging
PG = 1
PAE = 0
LME = 0
PAE Paging
PG = 1
PAE = 1
LME = 0
Clear PAE
Clear LME
Setr LME
#GP
Clear PAE
Set PG
Set PAE
Clear PG
No Paging
PG = 0
PAE = 0
LME = 1
Clear PAE
No Paging
PG = 0
PAE = 1
LME = 0
Clear PG
Clear LME
Clear PAE
IA-32e Paging
PG = 1
PAE = 1
LME = 1
Set PG
Clear LME
Setr LME
Set PG
#GP
Set PAE
Set PAE
#GP
No Paging
PG = 0
PAE = 1
LME = 1
Figure 4-1. Enabling and Changing Paging Modes
•
IA32_EFER.LME cannot be modified while paging is enabled (CR0.PG = 1). Attempts to do so using WRMSR
cause a general-protection exception (#GP(0)).
•
Paging cannot be enabled (by setting CR0.PG to 1) while CR4.PAE = 0 and IA32_EFER.LME = 1. Attempts to do
so using MOV to CR0 cause a general-protection exception (#GP(0)).
1. Such an address is called canonical. Use of a non-canonical linear address in 64-bit mode produces a general-protection exception
(#GP(0)); the processor does not attempt to translate non-canonical linear addresses using IA-32e paging.
Vol. 3A 4-3
PAGING
•
CR4.PAE cannot be cleared while IA-32e paging is active (CR0.PG = 1 and IA32_EFER.LME = 1). Attempts to
do so using MOV to CR4 cause a general-protection exception (#GP(0)).
•
•
Regardless of the current paging mode, software can disable paging by clearing CR0.PG with MOV to CR0.1
•
Software cannot make transitions directly between IA-32e paging and either of the other two paging modes. It
must first disable paging (by clearing CR0.PG with MOV to CR0), then set CR4.PAE and IA32_EFER.LME to the
desired values (with MOV to CR4 and WRMSR), and then re-enable paging (by setting CR0.PG with MOV to
CR0). As noted earlier, an attempt to clear either CR4.PAE or IA32_EFER.LME cause a general-protection
exception (#GP(0)).
•
VMX transitions allow transitions between paging modes that are not possible using MOV to CR or WRMSR. This
is because VMX transitions can load CR0, CR4, and IA32_EFER in one operation. See Section 4.11.1.
Software can make transitions between 32-bit paging and PAE paging by changing the value of CR4.PAE with
MOV to CR4.
4.1.3
Paging-Mode Modifiers
Details of how each paging mode operates are determined by the following control bits:
•
•
The WP flag in CR0 (bit 16).
•
The NXE flag in the IA32_EFER MSR (bit 11).
The PSE, PGE, PCIDE, SMEP, SMAP, and PKE flags in CR4 (bit 4, bit 7, bit 17, bit 20, bit 21, and bit 22 respectively).
CR0.WP allows pages to be protected from supervisor-mode writes. If CR0.WP = 0, supervisor-mode write
accesses are allowed to linear addresses with read-only access rights; if CR0.WP = 1, they are not. (User-mode
write accesses are never allowed to linear addresses with read-only access rights, regardless of the value of
CR0.WP.) Section 4.6 explains how access rights are determined, including the definition of supervisor-mode and
user-mode accesses.
CR4.PSE enables 4-MByte pages for 32-bit paging. If CR4.PSE = 0, 32-bit paging can use only 4-KByte pages; if
CR4.PSE = 1, 32-bit paging can use both 4-KByte pages and 4-MByte pages. See Section 4.3 for more information.
(PAE paging and IA-32e paging can use multiple page sizes regardless of the value of CR4.PSE.)
CR4.PGE enables global pages. If CR4.PGE = 0, no translations are shared across address spaces; if CR4.PGE = 1,
specified translations may be shared across address spaces. See Section 4.10.2.4 for more information.
CR4.PCIDE enables process-context identifiers (PCIDs) for IA-32e paging (CR4.PCIDE can be 1 only when IA-32e
paging is in use). PCIDs allow a logical processor to cache information for multiple linear-address spaces. See
Section 4.10.1 for more information.
CR4.SMEP allows pages to be protected from supervisor-mode instruction fetches. If CR4.SMEP = 1, software
operating in supervisor mode cannot fetch instructions from linear addresses that are accessible in user mode.
Section 4.6 explains how access rights are determined, including the definition of supervisor-mode accesses and
user-mode accessibility.
CR4.SMAP allows pages to be protected from supervisor-mode data accesses. If CR4.SMAP = 1, software operating
in supervisor mode cannot access data at linear addresses that are accessible in user mode. Software can override
this protection by setting EFLAGS.AC. Section 4.6 explains how access rights are determined, including the definition of supervisor-mode accesses and user-mode accessibility.
CR4.PKE allows each linear address to be associated with a protection key. The PKRU register specifies, for each
protection key, whether linear addresses with that protection key can be read or written by software. See Section
4.6 for more information.
IA32_EFER.NXE enables execute-disable access rights for PAE paging and IA-32e paging. If IA32_EFER.NXE = 1,
instruction fetches can be prevented from specified linear addresses (even if data reads from the addresses are
allowed). Section 4.6 explains how access rights are determined. (IA32_EFER.NXE has no effect with 32-bit
1. If CR4.PCIDE = 1, an attempt to clear CR0.PG causes a general-protection exception (#GP); software should clear CR4.PCIDE before
attempting to disable paging.
4-4 Vol. 3A
PAGING
paging. Software that wants to use this feature to limit instruction fetches from readable pages must use either
PAE paging or IA-32e paging.)
4.1.4
Enumeration of Paging Features by CPUID
Software can discover support for different paging features using the CPUID instruction:
•
PSE: page-size extensions for 32-bit paging.
If CPUID.01H:EDX.PSE [bit 3] = 1, CR4.PSE may be set to 1, enabling support for 4-MByte pages with 32-bit
paging (see Section 4.3).
•
PAE: physical-address extension.
If CPUID.01H:EDX.PAE [bit 6] = 1, CR4.PAE may be set to 1, enabling PAE paging (this setting is also required
for IA-32e paging).
•
PGE: global-page support.
If CPUID.01H:EDX.PGE [bit 13] = 1, CR4.PGE may be set to 1, enabling the global-page feature (see Section
4.10.2.4).
•
PAT: page-attribute table.
If CPUID.01H:EDX.PAT [bit 16] = 1, the 8-entry page-attribute table (PAT) is supported. When the PAT is
supported, three bits in certain paging-structure entries select a memory type (used to determine type of
caching used) from the PAT (see Section 4.9.2).
•
PSE-36: page-size extensions with 40-bit physical-address extension.
If CPUID.01H:EDX.PSE-36 [bit 17] = 1, the PSE-36 mechanism is supported, indicating that translations using
4-MByte pages with 32-bit paging may produce physical addresses with up to 40 bits (see Section 4.3).
•
PCID: process-context identifiers.
If CPUID.01H:ECX.PCID [bit 17] = 1, CR4.PCIDE may be set to 1, enabling process-context identifiers (see
Section 4.10.1).
•
SMEP: supervisor-mode execution prevention.
If CPUID.(EAX=07H,ECX=0H):EBX.SMEP [bit 7] = 1, CR4.SMEP may be set to 1, enabling supervisor-mode
execution prevention (see Section 4.6).
•
SMAP: supervisor-mode access prevention.
If CPUID.(EAX=07H,ECX=0H):EBX.SMAP [bit 20] = 1, CR4.SMAP may be set to 1, enabling supervisor-mode
access prevention (see Section 4.6).
•
PKU: protection keys.
If CPUID.(EAX=07H,ECX=0H):ECX.PKU [bit 3] = 1, CR4.PKE may be set to 1, enabling protection keys (see
Section 4.6).
•
NX: execute disable.
If CPUID.80000001H:EDX.NX [bit 20] = 1, IA32_EFER.NXE may be set to 1, allowing PAE paging and IA-32e
paging to disable execute access to selected pages (see Section 4.6). (Processors that do not support CPUID
function 80000001H do not allow IA32_EFER.NXE to be set to 1.)
•
Page1GB: 1-GByte pages.
If CPUID.80000001H:EDX.Page1GB [bit 26] = 1, 1-GByte pages are supported with IA-32e paging (see
Section 4.5).
•
LM: IA-32e mode support.
If CPUID.80000001H:EDX.LM [bit 29] = 1, IA32_EFER.LME may be set to 1, enabling IA-32e paging.
(Processors that do not support CPUID function 80000001H do not allow IA32_EFER.LME to be set to 1.)
•
CPUID.80000008H:EAX[7:0] reports the physical-address width supported by the processor. (For processors
that do not support CPUID function 80000008H, the width is generally 36 if CPUID.01H:EDX.PAE [bit 6] = 1
and 32 otherwise.) This width is referred to as MAXPHYADDR. MAXPHYADDR is at most 52.
•
CPUID.80000008H:EAX[15:8] reports the linear-address width supported by the processor. Generally, this
value is 48 if CPUID.80000001H:EDX.LM [bit 29] = 1 and 32 otherwise. (Processors that do not support CPUID
function 80000008H, support a linear-address width of 32.)
Vol. 3A 4-5
PAGING
4.2
HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW
All three paging modes translate linear addresses using hierarchical paging structures. This section provides an
overview of their operation. Section 4.3, Section 4.4, and Section 4.5 provide details for the three paging modes.
Every paging structure is 4096 Bytes in size and comprises a number of individual entries. With 32-bit paging,
each entry is 32 bits (4 bytes); there are thus 1024 entries in each structure. With PAE paging and IA-32e paging,
each entry is 64 bits (8 bytes); there are thus 512 entries in each structure. (PAE paging includes one exception, a
paging structure that is 32 bytes in size, containing 4 64-bit entries.)
The processor uses the upper portion of a linear address to identify a series of paging-structure entries. The last of
these entries identifies the physical address of the region to which the linear address translates (called the page
frame). The lower portion of the linear address (called the page offset) identifies the specific address within that
region to which the linear address translates.
Each paging-structure entry contains a physical address, which is either the address of another paging structure or
the address of a page frame. In the first case, the entry is said to reference the other paging structure; in the
latter, the entry is said to map a page.
The first paging structure used for any translation is located at the physical address in CR3. A linear address is
translated using the following iterative procedure. A portion of the linear address (initially the uppermost bits)
selects an entry in a paging structure (initially the one located using CR3). If that entry references another paging
structure, the process continues with that paging structure and with the portion of the linear address immediately
below that just used. If instead the entry maps a page, the process completes: the physical address in the entry is
that of the page frame and the remaining lower portion of the linear address is the page offset.
The following items give an example for each of the three paging modes (each example locates a 4-KByte page
frame):
•
With 32-bit paging, each paging structure comprises 1024 = 210 entries. For this reason, the translation
process uses 10 bits at a time from a 32-bit linear address. Bits 31:22 identify the first paging-structure entry
and bits 21:12 identify a second. The latter identifies the page frame. Bits 11:0 of the linear address are the
page offset within the 4-KByte page frame. (See Figure 4-2 for an illustration.)
•
With PAE paging, the first paging structure comprises only 4 = 22 entries. Translation thus begins by using
bits 31:30 from a 32-bit linear address to identify the first paging-structure entry. Other paging structures
comprise 512 =29 entries, so the process continues by using 9 bits at a time. Bits 29:21 identify a second
paging-structure entry and bits 20:12 identify a third. This last identifies the page frame. (See Figure 4-5 for
an illustration.)
•
With IA-32e paging, each paging structure comprises 512 = 29 entries and translation uses 9 bits at a time
from a 48-bit linear address. Bits 47:39 identify the first paging-structure entry, bits 38:30 identify a second,
bits 29:21 a third, and bits 20:12 identify a fourth. Again, the last identifies the page frame. (See Figure 4-8
for an illustration.)
The translation process in each of the examples above completes by identifying a page frame; the page frame is
part of the translation of the original linear address. In some cases, however, the paging structures may be
configured so that the translation process terminates before identifying a page frame. This occurs if the process
encounters a paging-structure entry that is marked “not present” (because its P flag — bit 0 — is clear) or in which
a reserved bit is set. In this case, there is no translation for the linear address; an access to that address causes a
page-fault exception (see Section 4.7).
In the examples above, a paging-structure entry maps a page with a 4-KByte page frame when only 12 bits remain
in the linear address; entries identified earlier always reference other paging structures. That may not apply in
other cases. The following items identify when an entry maps a page and when it references another paging structure:
•
If more than 12 bits remain in the linear address, bit 7 (PS — page size) of the current paging-structure entry
is consulted. If the bit is 0, the entry references another paging structure; if the bit is 1, the entry maps a page.
•
If only 12 bits remain in the linear address, the current paging-structure entry always maps a page (bit 7 is
used for other purposes).
If a paging-structure entry maps a page when more than 12 bits remain in the linear address, the entry identifies
a page frame larger than 4 KBytes. For example, 32-bit paging uses the upper 10 bits of a linear address to locate
the first paging-structure entry; 22 bits remain. If that entry maps a page, the page frame is 222 Bytes = 4 MBytes.
4-6 Vol. 3A
PAGING
32-bit paging supports 4-MByte pages if CR4.PSE = 1. PAE paging and IA-32e paging support 2-MByte pages
(regardless of the value of CR4.PSE). IA-32e paging may support 1-GByte pages (see Section 4.1.4).
Paging structures are given different names based on their uses in the translation process. Table 4-2 gives the
names of the different paging structures. It also provides, for each structure, the source of the physical address
used to locate it (CR3 or a different paging-structure entry); the bits in the linear address used to select an entry
from the structure; and details of whether and how such an entry can map a page.
Table 4-2. Paging Structures in the Different Paging Modes
Paging Structure
Entry
Name
PML4 table
PML4E
Paging Mode
Physical
Address of
Structure
Bits Selecting
Entry
32-bit, PAE
IA-32e
N/A
CR3
47:39
32-bit
Page-directorypointer table
PDPTE
Page directory
PDE
Page table
PTE
Page Mapping
N/A (PS must be 0)
N/A
PAE
CR3
31:30
N/A (PS must be 0)
IA-32e
PML4E
38:30
1-GByte page if PS=11
32-bit
CR3
31:22
4-MByte page if PS=12
PAE, IA-32e
PDPTE
29:21
2-MByte page if PS=1
21:12
4-KByte page
20:12
4-KByte page
32-bit
PAE, IA-32e
PDE
NOTES:
1. Not all processors allow the PS flag to be 1 in PDPTEs; see Section 4.1.4 for how to determine whether 1-GByte pages are supported.
2. 32-bit paging ignores the PS flag in a PDE (and uses the entry to reference a page table) unless CR4.PSE = 1. Not all processors allow
CR4.PSE to be 1; see Section 4.1.4 for how to determine whether 4-MByte pages are supported with 32-bit paging.
4.3
32-BIT PAGING
A logical processor uses 32-bit paging if CR0.PG = 1 and CR4.PAE = 0. 32-bit paging translates 32-bit linear
addresses to 40-bit physical addresses.1 Although 40 bits corresponds to 1 TByte, linear addresses are limited to
32 bits; at most 4 GBytes of linear-address space may be accessed at any given time.
32-bit paging uses a hierarchy of paging structures to produce a translation for a linear address. CR3 is used to
locate the first paging-structure, the page directory. Table 4-3 illustrates how CR3 is used with 32-bit paging.
32-bit paging may map linear addresses to either 4-KByte pages or 4-MByte pages. Figure 4-2 illustrates the
translation process when it uses a 4-KByte page; Figure 4-3 covers the case of a 4-MByte page. The following
items describe the 32-bit paging process in more detail as well has how the page size is determined:
•
A 4-KByte naturally aligned page directory is located at the physical address specified in bits 31:12 of CR3 (see
Table 4-3). A page directory comprises 1024 32-bit entries (PDEs). A PDE is selected using the physical address
defined as follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from CR3.
1. Bits in the range 39:32 are 0 in any physical address used by 32-bit paging except those used to map 4-MByte pages. If the processor does not support the PSE-36 mechanism, this is true also for physical addresses used to map 4-MByte pages. If the processor
does support the PSE-36 mechanism and MAXPHYADDR < 40, bits in the range 39:MAXPHYADDR are 0 in any physical address used
to map a 4-MByte page. (The corresponding bits are reserved in PDEs.) See Section 4.1.4 for how to determine MAXPHYADDR and
whether the PSE-36 mechanism is supported.
Vol. 3A 4-7
PAGING
— Bits 11:2 are bits 31:22 of the linear address.
— Bits 1:0 are 0.
Because a PDE is identified using bits 31:22 of the linear address, it controls access to a 4-Mbyte region of the
linear-address space. Use of the PDE depends on CR4.PSE and the PDE’s PS flag (bit 7):
•
If CR4.PSE = 1 and the PDE’s PS flag is 1, the PDE maps a 4-MByte page (see Table 4-4). The final physical
address is computed as follows:
— Bits 39:32 are bits 20:13 of the PDE.
— Bits 31:22 are bits 31:22 of the PDE.1
— Bits 21:0 are from the original linear address.
•
If CR4.PSE = 0 or the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is located at the physical
address specified in bits 31:12 of the PDE (see Table 4-5). A page table comprises 1024 32-bit entries (PTEs).
A PTE is selected using the physical address defined as follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from the PDE.
— Bits 11:2 are bits 21:12 of the linear address.
— Bits 1:0 are 0.
•
Because a PTE is identified using bits 31:12 of the linear address, every PTE maps a 4-KByte page (see
Table 4-6). The final physical address is computed as follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the entry is used neither to reference another paging-structure entry nor to map a page. There is no translation for a linear address whose translation would use such a paging-structure entry; a reference to such a linear address causes a page-fault exception
(see Section 4.7).
With 32-bit paging, there are reserved bits only if CR4.PSE = 1:
•
If the P flag and the PS flag (bit 7) of a PDE are both 1, the bits reserved depend on MAXPHYADDR, and whether
the PSE-36 mechanism is supported:2
— If the PSE-36 mechanism is not supported, bits 21:13 are reserved.
— If the PSE-36 mechanism is supported, bits 21:(M–19) are reserved, where M is the minimum of 40 and
MAXPHYADDR.
•
If the PAT is not supported:3
— If the P flag of a PTE is 1, bit 7 is reserved.
— If the P flag and the PS flag of a PDE are both 1, bit 12 is reserved.
(If CR4.PSE = 0, no bits are reserved with 32-bit paging.)
A reference using a linear address that is successfully translated to a physical address is performed only if allowed
by the access rights of the translation; see Section 4.6.
1. The upper bits in the final physical address do not all come from corresponding positions in the PDE; the physical-address bits in the
PDE are not all contiguous.
2. See Section 4.1.4 for how to determine MAXPHYADDR and whether the PSE-36 mechanism is supported.
3. See Section 4.1.4 for how to determine whether the PAT is supported.
4-8 Vol. 3A
PAGING
Linear Address
31
22 21
12 11
Table
Directory
0
Offset
12
Page Table
10
10
4-KByte Page
Physical Address
Page Directory
PTE
PDE with PS=0
32
20
20
CR3
Figure 4-2. Linear-Address Translation to a 4-KByte Page using 32-Bit Paging
31
Linear Address
22 21
Offset
Directory
22
10
Page Directory
PDE with PS=1
32
0
4-MByte Page
Physical Address
18
CR3
Figure 4-3. Linear-Address Translation to a 4-MByte Page using 32-Bit Paging
Figure 4-4 gives a summary of the formats of CR3 and the paging-structure entries with 32-bit paging. For the
paging structure entries, it identifies separately the format of entries that map pages, those that reference other
paging structures, and those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted because they determine how such an entry is used.
Vol. 3A 4-9
PAGING
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Address of page directory1
Bits 31:22 of address
of 4MB page frame
Reserved
(must be 0)
P
Bits 39:32 of A
2
address
T
Address of page table
8
7
6
5
4
3
1
0
Ignored
CR3
G
1 D A
P PW U R
C
/ / 1
D T S W
PDE:
4MB
page
I
g
n
P PW U R
C
/ / 1
D T S W
PDE:
page
table
Ignored
Ignored
0
A
Ignored
Address of 4KB page frame
2
P PW
C
Ignored
D T
0
Ignored
G
P
P
U R
A D A C PW
/ / 1
T
D T S W
Ignored
0
PDE:
not
present
PTE:
4KB
page
PTE:
not
present
Figure 4-4. Formats of CR3 and Paging-Structure Entries with 32-Bit Paging
NOTES:
1. CR3 has 64 bits on processors supporting the Intel-64 architecture. These bits are ignored with 32-bit paging.
2. This example illustrates a processor in which MAXPHYADDR is 36. If this value is larger or smaller, the number of bits reserved in
positions 20:13 of a PDE mapping a 4-MByte page will change.
Table 4-3. Use of CR3 with 32-Bit Paging
Bit
Position(s)
Contents
2:0
Ignored
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page directory during linearaddress translation (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page directory during linearaddress translation (see Section 4.9)
11:5
Ignored
31:12
Physical address of the 4-KByte aligned page directory used for linear-address translation
63:32
Ignored (these bits exist only on processors supporting the Intel-64 architecture)
4-10 Vol. 3A
PAGING
Table 4-4. Format of a 32-Bit Page-Directory Entry that Maps a 4-MByte Page
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to map a 4-MByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 4-MByte page referenced by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 4-MByte page referenced by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the 4-MByte page referenced by
this entry (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the 4-MByte page referenced by
this entry (see Section 4.9)
5 (A)
Accessed; indicates whether software has accessed the 4-MByte page referenced by this entry (see Section 4.8)
6 (D)
Dirty; indicates whether software has written to the 4-MByte page referenced by this entry (see Section 4.8)
7 (PS)
Page size; must be 1 (otherwise, this entry references a page table; see Table 4-5)
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise
11:9
Ignored
12 (PAT)
If the PAT is supported, indirectly determines the memory type used to access the 4-MByte page referenced by this
entry (see Section 4.9.2); otherwise, reserved (must be 0)1
(M–20):13
Bits (M–1):32 of physical address of the 4-MByte page referenced by this entry2
21:(M–19)
Reserved (must be 0)
31:22
Bits 31:22 of physical address of the 4-MByte page referenced by this entry
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.
2. If the PSE-36 mechanism is not supported, M is 32, and this row does not apply. If the PSE-36 mechanism is supported, M is the minimum of 40 and MAXPHYADDR (this row does not apply if MAXPHYADDR = 32). See Section 4.1.4 for how to determine MAXPHYADDR and whether the PSE-36 mechanism is supported.
Vol. 3A 4-11
PAGING
Table 4-5. Format of a 32-Bit Page-Directory Entry that References a Page Table
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page table
1 (R/W)
Read/write; if 0, writes may not be allowed to the 4-MByte region controlled by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 4-MByte region controlled by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9)
5 (A)
Accessed; indicates whether this entry has been used for linear-address translation (see Section 4.8)
6
Ignored
7 (PS)
If CR4.PSE = 1, must be 0 (otherwise, this entry maps a 4-MByte page; see Table 4-4); otherwise, ignored
11:8
Ignored
31:12
Physical address of 4-KByte aligned page table referenced by this entry
Table 4-6. Format of a 32-Bit Page-Table Entry that Maps a 4-KByte Page
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to map a 4-KByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 4-KByte page referenced by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 4-KByte page referenced by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the 4-KByte page referenced by this
entry (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the 4-KByte page referenced by this
entry (see Section 4.9)
5 (A)
Accessed; indicates whether software has accessed the 4-KByte page referenced by this entry (see Section 4.8)
6 (D)
Dirty; indicates whether software has written to the 4-KByte page referenced by this entry (see Section 4.8)
7 (PAT)
If the PAT is supported, indirectly determines the memory type used to access the 4-KByte page referenced by this
entry (see Section 4.9.2); otherwise, reserved (must be 0)1
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise
11:9
Ignored
31:12
Physical address of the 4-KByte page referenced by this entry
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.
4-12 Vol. 3A
PAGING
4.4
PAE PAGING
A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 0. PAE paging translates
32-bit linear addresses to 52-bit physical addresses.1 Although 52 bits corresponds to 4 PBytes, linear addresses
are limited to 32 bits; at most 4 GBytes of linear-address space may be accessed at any given time.
With PAE paging, a logical processor maintains a set of four (4) PDPTE registers, which are loaded from an address
in CR3. Linear address are translated using 4 hierarchies of in-memory paging structures, each located using one
of the PDPTE registers. (This is different from the other paging modes, in which there is one hierarchy referenced
by CR3.)
Section 4.4.1 discusses the PDPTE registers. Section 4.4.2 describes linear-address translation with PAE paging.
4.4.1
PDPTE Registers
When PAE paging is used, CR3 references the base of a 32-Byte page-directory-pointer table. Table 4-7 illustrates how CR3 is used with PAE paging.
Table 4-7. Use of CR3 with PAE Paging
Bit
Position(s)
Contents
4:0
Ignored
31:5
Physical address of the 32-Byte aligned page-directory-pointer table used for linear-address translation
63:32
Ignored (these bits exist only on processors supporting the Intel-64 architecture)
The page-directory-pointer-table comprises four (4) 64-bit entries called PDPTEs. Each PDPTE controls access to a
1-GByte region of the linear-address space. Corresponding to the PDPTEs, the logical processor maintains a set of
four (4) internal, non-architectural PDPTE registers, called PDPTE0, PDPTE1, PDPTE2, and PDPTE3. The logical
processor loads these registers from the PDPTEs in memory as part of certain operations:
•
If PAE paging would be in use following an execution of MOV to CR0 or MOV to CR4 (see Section 4.1.1) and the
instruction is modifying any of CR0.CD, CR0.NW, CR0.PG, CR4.PAE, CR4.PGE, CR4.PSE, or CR4.SMEP; then the
PDPTEs are loaded from the address in CR3.
•
If MOV to CR3 is executed while the logical processor is using PAE paging, the PDPTEs are loaded from the
address being loaded into CR3.
•
If PAE paging is in use and a task switch changes the value of CR3, the PDPTEs are loaded from the address in
the new CR3 value.
•
Certain VMX transitions load the PDPTE registers. See Section 4.11.1.
Table 4-8 gives the format of a PDPTE. If any of the PDPTEs sets both the P flag (bit 0) and any reserved bit, the
MOV to CR instruction causes a general-protection exception (#GP(0)) and the PDPTEs are not loaded.2 As shown
in Table 4-8, bits 2:1, 8:5, and 63:MAXPHYADDR are reserved in the PDPTEs.
1. If MAXPHYADDR < 52, bits in the range 51:MAXPHYADDR will be 0 in any physical address used by PAE paging. (The corresponding
bits are reserved in the paging-structure entries.) See Section 4.1.4 for how to determine MAXPHYADDR.
2. On some processors, reserved bits are checked even in PDPTEs in which the P flag (bit 0) is 0.
Vol. 3A 4-13
PAGING
Table 4-8. Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE)
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page directory
2:1
Reserved (must be 0)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page directory referenced by
this entry (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page directory referenced by
this entry (see Section 4.9)
8:5
Reserved (must be 0)
11:9
Ignored
(M–1):12
Physical address of 4-KByte aligned page directory referenced by this entry1
63:M
Reserved (must be 0)
NOTES:
1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
4.4.2
Linear-Address Translation with PAE Paging
PAE paging may map linear addresses to either 4-KByte pages or 2-MByte pages. Figure 4-5 illustrates the translation process when it produces a 4-KByte page; Figure 4-6 covers the case of a 2-MByte page. The following items
describe the PAE paging process in more detail as well has how the page size is determined:
•
Bits 31:30 of the linear address select a PDPTE register (see Section 4.4.1); this is PDPTEi, where i is the value
of bits 31:30.1 Because a PDPTE register is identified using bits 31:30 of the linear address, it controls access
to a 1-GByte region of the linear-address space. If the P flag (bit 0) of PDPTEi is 0, the processor ignores bits
63:1, and there is no mapping for the 1-GByte region controlled by PDPTEi. A reference using a linear address
in this region causes a page-fault exception (see Section 4.7).
•
If the P flag of PDPTEi is 1, 4-KByte naturally aligned page directory is located at the physical address specified
in bits 51:12 of PDPTEi (see Table 4-8 in Section 4.4.1). A page directory comprises 512 64-bit entries (PDEs).
A PDE is selected using the physical address defined as follows:
— Bits 51:12 are from PDPTEi.
— Bits 11:3 are bits 29:21 of the linear address.
— Bits 2:0 are 0.
Because a PDE is identified using bits 31:21 of the linear address, it controls access to a 2-Mbyte region of the
linear-address space. Use of the PDE depends on its PS flag (bit 7):
•
If the PDE’s PS flag is 1, the PDE maps a 2-MByte page (see Table 4-9). The final physical address is computed
as follows:
— Bits 51:21 are from the PDE.
— Bits 20:0 are from the original linear address.
•
If the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is located at the physical address specified in
bits 51:12 of the PDE (see Table 4-10). A page table comprises 512 64-bit entries (PTEs). A PTE is selected
using the physical address defined as follows:
— Bits 51:12 are from the PDE.
1. With PAE paging, the processor does not use CR3 when translating a linear address (as it does in the other paging modes). It does
not access the PDPTEs in the page-directory-pointer table during linear-address translation.
4-14 Vol. 3A
PAGING
— Bits 11:3 are bits 20:12 of the linear address.
— Bits 2:0 are 0.
•
Because a PTE is identified using bits 31:12 of the linear address, every PTE maps a 4-KByte page (see
Table 4-11). The final physical address is computed as follows:
— Bits 51:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If the P flag (bit 0) of a PDE or a PTE is 0 or if a PDE or a PTE sets any reserved bit, the entry is used neither to
reference another paging-structure entry nor to map a page. There is no translation for a linear address whose
translation would use such a paging-structure entry; a reference to such a linear address causes a page-fault
exception (see Section 4.7).
The following bits are reserved with PAE paging:
•
•
•
•
If the P flag (bit 0) of a PDE or a PTE is 1, bits 62:MAXPHYADDR are reserved.
If the P flag and the PS flag (bit 7) of a PDE are both 1, bits 20:13 are reserved.
If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is reserved.
If the PAT is not supported:1
— If the P flag of a PTE is 1, bit 7 is reserved.
— If the P flag and the PS flag of a PDE are both 1, bit 12 is reserved.
A reference using a linear address that is successfully translated to a physical address is performed only if allowed
by the access rights of the translation; see Section 4.6.
Directory Pointer
Linear Address
31 30 29
21 20
12 11
Table
Directory
0
Offset
12
Page Table
PTE
9
2
Physical Address
9
Page Directory
PDE with PS=0
4-KByte Page
40
40
PDPTE Registers
40
PDPTE value
Figure 4-5. Linear-Address Translation to a 4-KByte Page using PAE Paging
1. See Section 4.1.4 for how to determine whether the PAT is supported.
Vol. 3A 4-15
PAGING
Directory
Pointer
Linear Address
31 30 29
21 20
Offset
Directory
0
21
9
Page Directory
2-MByte Page
Physical Address
PDPTE Registers
2
PDE with PS=1
PDPTE value
31
40
Figure 4-6. Linear-Address Translation to a 2-MByte Page using PAE Paging
Table 4-9. Format of a PAE Page-Directory Entry that Maps a 2-MByte Page
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to map a 2-MByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 2-MByte page referenced by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte page referenced by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the 2-MByte page referenced by
this entry (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the 2-MByte page referenced by this
entry (see Section 4.9)
5 (A)
Accessed; indicates whether software has accessed the 2-MByte page referenced by this entry (see Section 4.8)
6 (D)
Dirty; indicates whether software has written to the 2-MByte page referenced by this entry (see Section 4.8)
7 (PS)
Page size; must be 1 (otherwise, this entry references a page table; see Table 4-10)
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise
11:9
Ignored
12 (PAT)
If the PAT is supported, indirectly determines the memory type used to access the 2-MByte page referenced by this
entry (see Section 4.9.2); otherwise, reserved (must be 0)1
20:13
Reserved (must be 0)
(M–1):21
Physical address of the 2-MByte page referenced by this entry
62:M
Reserved (must be 0)
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte page controlled by
this entry; see Section 4.6); otherwise, reserved (must be 0)
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.
4-16 Vol. 3A
PAGING
Table 4-10. Format of a PAE Page-Directory Entry that References a Page Table
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page table
1 (R/W)
Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte region controlled by this entry (see
Section 4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9)
5 (A)
Accessed; indicates whether this entry has been used for linear-address translation (see Section 4.8)
6
Ignored
7 (PS)
Page size; must be 0 (otherwise, this entry maps a 2-MByte page; see Table 4-9)
11:8
Ignored
(M–1):12
Physical address of 4-KByte aligned page table referenced by this entry
62:M
Reserved (must be 0)
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte region controlled
by this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-11. Format of a PAE Page-Table Entry that Maps a 4-KByte Page
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to map a 4-KByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 4-KByte page referenced by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 4-KByte page referenced by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the 4-KByte page referenced by
this entry (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the 4-KByte page referenced by this
entry (see Section 4.9)
5 (A)
Accessed; indicates whether software has accessed the 4-KByte page referenced by this entry (see Section 4.8)
6 (D)
Dirty; indicates whether software has written to the 4-KByte page referenced by this entry (see Section 4.8)
7 (PAT)
If the PAT is supported, indirectly determines the memory type used to access the 4-KByte page referenced by this
entry (see Section 4.9.2); otherwise, reserved (must be 0)1
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise
Vol. 3A 4-17
PAGING
Table 4-11. Format of a PAE Page-Table Entry that Maps a 4-KByte Page (Contd.)
Bit
Position(s)
Contents
11:9
Ignored
(M–1):12
Physical address of the 4-KByte page referenced by this entry
62:M
Reserved (must be 0)
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 4-KByte page controlled by
this entry; see Section 4.6); otherwise, reserved (must be 0)
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.
Figure 4-7 gives a summary of the formats of CR3 and the paging-structure entries with PAE paging. For the paging
structure entries, it identifies separately the format of entries that map pages, those that reference other paging
structures, and those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted
because they determine how a paging-structure entry is used.
6666555555555
3210987654321
Ignored2
Reserved3
M1 M-1
33322222222221111111111
210987654321098765432109876543210
Address of page-directory-pointer table
Address of page directory
Ign.
Ignored
Rsvd.
P P Rs
PDPTE:
CW
1
present
D T vd
Ignored
X
D
4
X
D
Reserved
Reserved
Address of
2MB page frame
0
Reserved
Address of page table
Reserved
Address of 4KB page frame
PDE:
2MB
page
I PPUR
0 g A C W /S
/ 1
n DT W
PDE:
page
table
Ign.
0
P
PPUR
Ign. G A D A C W /S
/ 1
T
DT W
Ignored
Figure 4-7. Formats of CR3 and Paging-Structure Entries with PAE Paging
NOTES:
1. M is an abbreviation for MAXPHYADDR.
2. CR3 has 64 bits only on processors supporting the Intel-64 architecture. These bits are ignored with PAE paging.
3. Reserved fields must be 0.
4. If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is reserved.
4-18 Vol. 3A
PDTPE:
not
present
P
PPUR
A Ign. G 1 D A C W /S
/ 1
T
DT W
Ignored
X
D
CR3
0
PDE:
not
present
PTE:
4KB
page
PTE:
not
present
PAGING
4.5
IA-32E PAGING
A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 1. With IA-32e paging,
linear address are translated using a hierarchy of in-memory paging structures located using the contents of CR3.
IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.1 Although 52 bits corresponds to 4
PBytes, linear addresses are limited to 48 bits; at most 256 TBytes of linear-address space may be accessed at any
given time.
IA-32e paging uses a hierarchy of paging structures to produce a translation for a linear address. CR3 is used to
locate the first paging-structure, the PML4 table. Use of CR3 with IA-32e paging depends on whether processcontext identifiers (PCIDs) have been enabled by setting CR4.PCIDE:
•
Table 4-12 illustrates how CR3 is used with IA-32e paging if CR4.PCIDE = 0.
Table 4-12. Use of CR3 with IA-32e Paging and CR4.PCIDE = 0
Bit
Position(s)
Contents
2:0
Ignored
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the PML4 table during linearaddress translation (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the PML4 table during linear-address
translation (see Section 4.9.2)
11:5
Ignored
M–1:12
Physical address of the 4-KByte aligned PML4 table used for linear-address translation1
63:M
Reserved (must be 0)
NOTES:
1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
•
Table 4-13 illustrates how CR3 is used with IA-32e paging if CR4.PCIDE = 1.
Table 4-13. Use of CR3 with IA-32e Paging and CR4.PCIDE = 1
Bit
Position(s)
Contents
11:0
PCID (see Section 4.10.1)1
M–1:12
Physical address of the 4-KByte aligned PML4 table used for linear-address translation2
63:M
Reserved (must be 0)3
NOTES:
1. Section 4.9.2 explains how the processor determines the memory type used to access the PML4 table during linear-address translation with CR4.PCIDE = 1.
2. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
3. See Section 4.10.4.1 for use of bit 63 of the source operand of the MOV to CR3 instruction.
After software modifies the value of CR4.PCIDE, the logical processor immediately begins using CR3 as specified
for the new value. For example, if software changes CR4.PCIDE from 1 to 0, the current PCID immediately changes
1. If MAXPHYADDR < 52, bits in the range 51:MAXPHYADDR will be 0 in any physical address used by IA-32e paging. (The corresponding bits are reserved in the paging-structure entries.) See Section 4.1.4 for how to determine MAXPHYADDR.
Vol. 3A 4-19
PAGING
from CR3[11:0] to 000H (see also Section 4.10.4.1). In addition, the logical processor subsequently determines
the memory type used to access the PML4 table using CR3.PWT and CR3.PCD, which had been bits 4:3 of the PCID.
IA-32e paging may map linear addresses to 4-KByte pages, 2-MByte pages, or 1-GByte pages.1 Figure 4-8 illustrates the translation process when it produces a 4-KByte page; Figure 4-9 covers the case of a 2-MByte page, and
Figure 4-10 the case of a 1-GByte page.
47
Linear Address
39 38
30 29
21 20
Directory
Table
PML4
Directory Ptr
9
9
9
12 11
0
Offset
12 4-KByte Page
Physical Addr
PTE
Page-DirectoryPointer Table
PDPTE
PDE with PS=0
40
Page-Directory
40
Page Table
40
9
40
PML4E
40
CR3
Figure 4-8. Linear-Address Translation to a 4-KByte Page using IA-32e Paging
1. Not all processors support 1-GByte pages; see Section 4.1.4.
4-20 Vol. 3A
PAGING
47
Linear Address
39 38
21 20
30 29
Directory
PML4
Directory Ptr
0
Offset
21
9
9
2-MByte Page
Physical Addr
Page-DirectoryPointer Table
PDE with PS=1
31
Page-Directory
PDPTE
40
9
40
PML4E
40
CR3
Figure 4-9. Linear-Address Translation to a 2-MByte Page using IA-32e Paging
47
Linear Address
39 38
30 29
PML4
Directory Ptr
0
Offset
30
9
1-GByte Page
Page-DirectoryPointer Table
Physical Addr
PDPTE with PS=1
22
9
40
PML4E
40
CR3
Figure 4-10. Linear-Address Translation to a 1-GByte Page using IA-32e Paging
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PAGING
If CR4.PKE = 1, IA-32e paging associates with each linear address a protection key. Section 4.6 explains how the
processor uses the protection key in its determination of the access rights of each linear address.
The following items describe the IA-32e paging process in more detail as well has how the page size and protection
key are determined.
•
A 4-KByte naturally aligned PML4 table is located at the physical address specified in bits 51:12 of CR3 (see
Table 4-12). A PML4 table comprises 512 64-bit entries (PML4Es). A PML4E is selected using the physical
address defined as follows:
— Bits 51:12 are from CR3.
— Bits 11:3 are bits 47:39 of the linear address.
— Bits 2:0 are all 0.
Because a PML4E is identified using bits 47:39 of the linear address, it controls access to a 512-GByte region of
the linear-address space.
•
A 4-KByte naturally aligned page-directory-pointer table is located at the physical address specified in
bits 51:12 of the PML4E (see Table 4-14). A page-directory-pointer table comprises 512 64-bit entries
(PDPTEs). A PDPTE is selected using the physical address defined as follows:
— Bits 51:12 are from the PML4E.
— Bits 11:3 are bits 38:30 of the linear address.
— Bits 2:0 are all 0.
Because a PDPTE is identified using bits 47:30 of the linear address, it controls access to a 1-GByte region of the
linear-address space. Use of the PDPTE depends on its PS flag (bit 7):1
•
If the PDPTE’s PS flag is 1, the PDPTE maps a 1-GByte page (see Table 4-15). The final physical address is
computed as follows:
— Bits 51:30 are from the PDPTE.
— Bits 29:0 are from the original linear address.
If CR4.PKE = 1, the linear address’s protection key is the value of bits 62:59 of the PDPTE.
•
If the PDPTE’s PS flag is 0, a 4-KByte naturally aligned page directory is located at the physical address
specified in bits 51:12 of the PDPTE (see Table 4-16). A page directory comprises 512 64-bit entries (PDEs). A
PDE is selected using the physical address defined as follows:
— Bits 51:12 are from the PDPTE.
— Bits 11:3 are bits 29:21 of the linear address.
— Bits 2:0 are all 0.
Because a PDE is identified using bits 47:21 of the linear address, it controls access to a 2-MByte region of the
linear-address space. Use of the PDE depends on its PS flag:
•
If the PDE's PS flag is 1, the PDE maps a 2-MByte page (see Table 4-17). The final physical address is computed
as follows:
— Bits 51:21 are from the PDE.
— Bits 20:0 are from the original linear address.
If CR4.PKE = 1, the linear address’s protection key is the value of bits 62:59 of the PDE.
•
If the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is located at the physical address specified in
bits 51:12 of the PDE (see Table 4-18). A page table comprises 512 64-bit entries (PTEs). A PTE is selected
using the physical address defined as follows:
— Bits 51:12 are from the PDE.
— Bits 11:3 are bits 20:12 of the linear address.
— Bits 2:0 are all 0.
1. The PS flag of a PDPTE is reserved and must be 0 (if the P flag is 1) if 1-GByte pages are not supported. See Section 4.1.4 for how
to determine whether 1-GByte pages are supported.
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PAGING
•
Because a PTE is identified using bits 47:12 of the linear address, every PTE maps a 4-KByte page (see
Table 4-19). The final physical address is computed as follows:
— Bits 51:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If CR4.PKE = 1, the linear address’s protection key is the value of bits 62:59 of the PTE.
If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the entry is used neither to reference another paging-structure entry nor to map a page. There is no translation for a linear address whose translation would use such a paging-structure entry; a reference to such a linear address causes a page-fault exception
(see Section 4.7).
The following bits are reserved with IA-32e paging:
•
•
•
•
•
•
If the P flag of a paging-structure entry is 1, bits 51:MAXPHYADDR are reserved.
If the P flag of a PML4E is 1, the PS flag is reserved.
If 1-GByte pages are not supported and the P flag of a PDPTE is 1, the PS flag is reserved.1
If the P flag and the PS flag of a PDPTE are both 1, bits 29:13 are reserved.
If the P flag and the PS flag of a PDE are both 1, bits 20:13 are reserved.
If IA32_EFER.NXE = 0 and the P flag of a paging-structure entry is 1, the XD flag (bit 63) is reserved.
A reference using a linear address that is successfully translated to a physical address is performed only if allowed
by the access rights of the translation; see Section 4.6.
Figure 4-11 gives a summary of the formats of CR3 and the IA-32e paging-structure entries. For the paging structure entries, it identifies separately the format of entries that map pages, those that reference other paging structures, and those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted because
they determine how a paging-structure entry is used.
Table 4-14. Format of an IA-32e PML4 Entry (PML4E) that References a Page-Directory-Pointer Table
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page-directory-pointer table
1 (R/W)
Read/write; if 0, writes may not be allowed to the 512-GByte region controlled by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 512-GByte region controlled by this entry (see
Section 4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page-directory-pointer table
referenced by this entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page-directory-pointer table
referenced by this entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether this entry has been used for linear-address translation (see Section 4.8)
6
Ignored
7 (PS)
Reserved (must be 0)
11:8
Ignored
1. See Section 4.1.4 for how to determine whether 1-GByte pages are supported.
Vol. 3A 4-23
PAGING
Table 4-14. Format of an IA-32e PML4 Entry (PML4E) that References a Page-Directory-Pointer Table (Contd.)
Bit
Position(s)
Contents
M–1:12
Physical address of 4-KByte aligned page-directory-pointer table referenced by this entry
51:M
Reserved (must be 0)
62:52
Ignored
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 512-GByte region
controlled by this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-15. Format of an IA-32e Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to map a 1-GByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 1-GByte page referenced by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 1-GByte page referenced by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the 1-GByte page referenced by this
entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the 1-GByte page referenced by this
entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether software has accessed the 1-GByte page referenced by this entry (see Section 4.8)
6 (D)
Dirty; indicates whether software has written to the 1-GByte page referenced by this entry (see Section 4.8)
7 (PS)
Page size; must be 1 (otherwise, this entry references a page directory; see Table 4-16)
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise
11:9
Ignored
12 (PAT)
Indirectly determines the memory type used to access the 1-GByte page referenced by this entry (see Section
4.9.2)1
29:13
Reserved (must be 0)
(M–1):30
Physical address of the 1-GByte page referenced by this entry
51:M
Reserved (must be 0)
58:52
Ignored
62:59
Protection key; if CR4.PKE = 1, determines the protection key of the page (see Section 4.6.2); ignored otherwise
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 1-GByte page controlled by
this entry; see Section 4.6); otherwise, reserved (must be 0)
NOTES:
1. The PAT is supported on all processors that support IA-32e paging.
4-24 Vol. 3A
PAGING
Table 4-16. Format of an IA-32e Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page directory
1 (R/W)
Read/write; if 0, writes may not be allowed to the 1-GByte region controlled by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 1-GByte region controlled by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page directory referenced by
this entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page directory referenced by
this entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether this entry has been used for linear-address translation (see Section 4.8)
6
Ignored
7 (PS)
Page size; must be 0 (otherwise, this entry maps a 1-GByte page; see Table 4-15)
11:8
Ignored
(M–1):12
Physical address of 4-KByte aligned page directory referenced by this entry
51:M
Reserved (must be 0)
62:52
Ignored
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 1-GByte region controlled
by this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-17. Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to map a 2-MByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 2-MByte page referenced by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte page referenced by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the 2-MByte page referenced by
this entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the 2-MByte page referenced by
this entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether software has accessed the 2-MByte page referenced by this entry (see Section 4.8)
6 (D)
Dirty; indicates whether software has written to the 2-MByte page referenced by this entry (see Section 4.8)
7 (PS)
Page size; must be 1 (otherwise, this entry references a page table; see Table 4-18)
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise
Vol. 3A 4-25
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Table 4-17. Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page (Contd.)
Bit
Position(s)
Contents
11:9
Ignored
12 (PAT)
Indirectly determines the memory type used to access the 2-MByte page referenced by this entry (see Section
4.9.2)
20:13
Reserved (must be 0)
(M–1):21
Physical address of the 2-MByte page referenced by this entry
51:M
Reserved (must be 0)
58:52
Ignored
62:59
Protection key; if CR4.PKE = 1, determines the protection key of the page (see Section 4.6.2); ignored otherwise
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte page controlled by
this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-18. Format of an IA-32e Page-Directory Entry that References a Page Table
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page table
1 (R/W)
Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte region controlled by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether this entry has been used for linear-address translation (see Section 4.8)
6
Ignored
7 (PS)
Page size; must be 0 (otherwise, this entry maps a 2-MByte page; see Table 4-17)
11:8
Ignored
(M–1):12
Physical address of 4-KByte aligned page table referenced by this entry
51:M
Reserved (must be 0)
62:52
Ignored
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte region controlled
by this entry; see Section 4.6); otherwise, reserved (must be 0)
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Table 4-19. Format of an IA-32e Page-Table Entry that Maps a 4-KByte Page
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to map a 4-KByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 4-KByte page referenced by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 4-KByte page referenced by this entry (see Section
4.6)
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the 4-KByte page referenced by
this entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the 4-KByte page referenced by this
entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether software has accessed the 4-KByte page referenced by this entry (see Section 4.8)
6 (D)
Dirty; indicates whether software has written to the 4-KByte page referenced by this entry (see Section 4.8)
7 (PAT)
Indirectly determines the memory type used to access the 4-KByte page referenced by this entry (see Section 4.9.2)
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise
11:9
Ignored
(M–1):12
Physical address of the 4-KByte page referenced by this entry
51:M
Reserved (must be 0)
58:52
Ignored
62:59
Protection key; if CR4.PKE = 1, determines the protection key of the page (see Section 4.6.2); ignored otherwise
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 4-KByte page controlled by
this entry; see Section 4.6); otherwise, reserved (must be 0)
Vol. 3A 4-27
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.
6666555555555
3210987654321
M1 M-1
33322222222221111111111
210987654321098765432109876543210
Reserved2
X
D
Ignored
3
Address of PML4 table
Rsvd.
Ignored
Address of page-directory-pointer table
Ign.
PP
C W Ign.
DT
PUR
Rs gI A P
PML4E:
C
W
/ 1 present
vd n D T /S W
0
PML4E:
not
present
P
PP R
A Ign. G 1 D A C W U / 1
T
D T /S W
PDPTE:
1GB
page
Ignored
X
D
Prot.
Key4
X
D
Ignored
Ignored
Rsvd.
Address of
1GB page frame
Rsvd.
Reserved
Address of page directory
Ign.
I PPUR
PDPTE:
page
0 g A C W /S / 1
n DT W
directory
Ignored
X
D
Prot.
Key4
X
D
Ignored
Ignored
Rsvd.
Rsvd.
Address of
2MB page frame
0
Reserved
Address of page table
Prot.
Key4
Ignored
Rsvd.
Address of 4KB page frame
PDTPE:
not
present
P
PPUR
A Ign. G 1 D A C W /S
/ 1
T
DT W
PDE:
2MB
page
I PPUR
0 g A C W /S / 1
n DT W
PDE:
page
table
Ign.
Ignored
X
D
CR3
0
P
PPUR
Ign. G A D A C W /S
/ 1
T
DT W
Ignored
0
PDE:
not
present
PTE:
4KB
page
PTE:
not
present
Figure 4-11. Formats of CR3 and Paging-Structure Entries with IA-32e Paging
NOTES:
1. M is an abbreviation for MAXPHYADDR.
2. Reserved fields must be 0.
3. If IA32_EFER.NXE = 0 and the P flag of a paging-structure entry is 1, the XD flag (bit 63) is reserved.
4. If CR4.PKE = 0, the protection key is ignored.
4.6
ACCESS RIGHTS
There is a translation for a linear address if the processes described in Section 4.3, Section 4.4.2, and Section 4.5
(depending upon the paging mode) completes and produces a physical address. Whether an access is permitted by
a translation is determined by the access rights specified by the paging-structure entries controlling the translation;1 paging-mode modifiers in CR0, CR4, and the IA32_EFER MSR; EFLAGS.AC; and the mode of the access.
1. With PAE paging, the PDPTEs do not determine access rights.
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Section 4.6.1 describes how the processor determines the access rights for each linear address. Section 4.6.2
provides additional information about how protection keys contribute to access-rights determination. (They do so
only with IA-32e paging and only if CR4.PKE = 1.)
4.6.1
Determination of Access Rights
Every access to a linear address is either a supervisor-mode access or a user-mode access. For all instruction
fetches and most data accesses, this distinction is determined by the current privilege level (CPL): accesses made
while CPL < 3 are supervisor-mode accesses, while accesses made while CPL = 3 are user-mode accesses.
Some operations implicitly access system data structures with linear addresses; the resulting accesses to those
data structures are supervisor-mode accesses regardless of CPL. Examples of such accesses include the following:
accesses to the global descriptor table (GDT) or local descriptor table (LDT) to load a segment descriptor; accesses
to the interrupt descriptor table (IDT) when delivering an interrupt or exception; and accesses to the task-state
segment (TSS) as part of a task switch or change of CPL. All these accesses are called implicit supervisor-mode
accesses regardless of CPL. Other accesses made while CPL < 3 are called explicit supervisor-mode accesses.
Access rights are also controlled by the mode of a linear address as specified by the paging-structure entries
controlling the translation of the linear address. If the U/S flag (bit 2) is 0 in at least one of the paging-structure
entries, the address is a supervisor-mode address. Otherwise, the address is a user-mode address.
The following items detail how paging determines access rights:
•
For supervisor-mode accesses:
— Data may be read (implicitly or explicitly) from any supervisor-mode address.
— Data reads from user-mode pages.
Access rights depend on the value of CR4.SMAP:
•
If CR4.SMAP = 0, data may be read from any user-mode address with a protection key for which read
access is permitted.
•
If CR4.SMAP = 1, access rights depend on the value of EFLAGS.AC and whether the access is implicit or
explicit:
—
If EFLAGS.AC = 1 and the access is explicit, data may be read from any user-mode address with a
protection key for which read access is permitted.
—
If EFLAGS.AC = 0 or the access is implicit, data may not be read from any user-mode address.
Section 4.6.2 explains how protection keys are associated with user-mode addresses and the accesses that
are permitted for each protection key.
— Data writes to supervisor-mode addresses.
Access rights depend on the value of CR0.WP:
•
•
If CR0.WP = 0, data may be written to any supervisor-mode address.
If CR0.WP = 1, data may be written to any supervisor-mode address with a translation for which the
R/W flag (bit 1) is 1 in every paging-structure entry controlling the translation; data may not be written
to any supervisor-mode address with a translation for which the R/W flag is 0 in any paging-structure
entry controlling the translation.
— Data writes to user-mode addresses.
Access rights depend on the value of CR0.WP:
•
If CR0.WP = 0, access rights depend on the value of CR4.SMAP:
—
If CR4.SMAP = 0, data may be written to any user-mode address with a protection key for which
write access is permitted.
—
If CR4.SMAP = 1, access rights depend on the value of EFLAGS.AC and whether the access is
implicit or explicit:
•
If EFLAGS.AC = 1 and the access is explicit, data may be written to any user-mode address
with a protection key for which write access is permitted.
•
If EFLAGS.AC = 0 or the access is implicit, data may not be written to any user-mode address.
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PAGING
•
If CR0.WP = 1, access rights depend on the value of CR4.SMAP:
—
If CR4.SMAP = 0, data may be written to any user-mode address with a translation for which the
R/W flag is 1 in every paging-structure entry controlling the translation and with a protection key
for which write access is permitted; data may not be written to any user-mode address with a
translation for which the R/W flag is 0 in any paging-structure entry controlling the translation.
—
If CR4.SMAP = 1, access rights depend on the value of EFLAGS.AC and whether the access is
implicit or explicit:
•
If EFLAGS.AC = 1 and the access is explicit, data may be written to any user-mode address
with a translation for which the R/W flag is 1 in every paging-structure entry controlling the
translation and with a protection key for which write access is permitted; data may not be
written to any user-mode address with a translation for which the R/W flag is 0 in any pagingstructure entry controlling the translation.
•
If EFLAGS.AC = 0 or the access is implicit, data may not be written to any user-mode address.
Section 4.6.2 explains how protection keys are associated with user-mode addresses and the accesses that
are permitted for each protection key.
— Instruction fetches from supervisor-mode addresses.
•
For 32-bit paging or if IA32_EFER.NXE = 0, instructions may be fetched from any supervisor-mode
address.
•
For PAE paging or IA-32e paging with IA32_EFER.NXE = 1, instructions may be fetched from any
supervisor-mode address with a translation for which the XD flag (bit 63) is 0 in every paging-structure
entry controlling the translation; instructions may not be fetched from any supervisor-mode address
with a translation for which the XD flag is 1 in any paging-structure entry controlling the translation.
— Instruction fetches from user-mode addresses.
Access rights depend on the values of CR4.SMEP:
•
•
•
If CR4.SMEP = 0, access rights depend on the paging mode and the value of IA32_EFER.NXE:
—
For 32-bit paging or if IA32_EFER.NXE = 0, instructions may be fetched from any user-mode
address.
—
For PAE paging or IA-32e paging with IA32_EFER.NXE = 1, instructions may be fetched from any
user-mode address with a translation for which the XD flag is 0 in every paging-structure entry
controlling the translation; instructions may not be fetched from any user-mode address with a
translation for which the XD flag is 1 in any paging-structure entry controlling the translation.
If CR4.SMEP = 1, instructions may not be fetched from any user-mode address.
For user-mode accesses:
— Data reads.
Access rights depend on the mode of the linear address:
•
Data may be read from any user-mode address with a protection key for which read access is
permitted. Section 4.6.2 explains how protection keys are associated with user-mode addresses and
the accesses that are permitted for each protection key.
•
Data may not be read from any supervisor-mode address.
— Data writes.
Access rights depend on the mode of the linear address:
•
Data may be written to any user-mode address with a translation for which the R/W flag is 1 in every
paging-structure entry controlling the translation and with a protection key for which write access is
permitted. Section 4.6.2 explains how protection keys are associated with user-mode addresses and
the accesses that are permitted for each protection key.
•
Data may not be written to any supervisor-mode address.
— Instruction fetches.
Access rights depend on the mode of the linear address, the paging mode, and the value of
IA32_EFER.NXE:
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PAGING
•
•
•
For 32-bit paging or if IA32_EFER.NXE = 0, instructions may be fetched from any user-mode address.
For PAE paging or IA-32e paging with IA32_EFER.NXE = 1, instructions may be fetched from any usermode address with a translation for which the XD flag is 0 in every paging-structure entry controlling
the translation.
Instructions may not be fetched from any supervisor-mode address.
A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see
Section 4.10). These structures may include information about access rights. The processor may enforce access
rights based on the TLBs and paging-structure caches instead of on the paging structures in memory.
This fact implies that, if software modifies a paging-structure entry to change access rights, the processor might
not use that change for a subsequent access to an affected linear address (see Section 4.10.4.3). See Section
4.10.4.2 for how software can ensure that the processor uses the modified access rights.
4.6.2
Protection Keys
The protection-key feature provides an additional mechanism by which IA-32e paging controls access to usermode addresses. When CR4.PKE = 1, every linear address is associated with the 4-bit protection key located in
bits 62:59 of the paging-structure entry that mapped the page containing the linear address (see Section 4.5). The
PKRU register determines, for each protection key, whether user-mode addresses with that protection key may be
read or written.
If CR4.PKE = 0, or if IA-32e paging is not active, the processor does not associate linear addresses with protection
keys and does not use the access-control mechanism described in this section. In either of these cases, a reference
in Section 4.6.1 to a user-mode address with a protection key should be considered a reference to any user-mode
address.
The PKRU register (protection key rights for user pages) is a 32-bit register with the following format: for each i
(0 ≤ i ≤ 15), PKRU[2i] is the access-disable bit for protection key i (ADi); PKRU[2i+1] is the write-disable bit
for protection key i (WDi).
Software can use the RDPKRU and WRPKRU instructions with ECX = 0 to read and write PKRU. In addition, the
PKRU register is XSAVE-managed state and can thus be read and written by instructions in the XSAVE feature set.
See Chapter 13, “Managing State Using the XSAVE Feature Set,” of Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1 for more information about the XSAVE feature set.
How a linear address’s protection key controls access to the address depends on the mode of a linear address:
•
A linear address’s protection controls only data accesses to the address. It does not in any way affect instructions fetches from the address.
•
The protection key of a supervisor-mode address is ignored and does not control data accesses to the address.
Because of this, Section 4.6.1 does not refer to protection keys when specifying the access rights for
supervisor-mode addresses.
•
Use of the protection key i of a user-mode address depends on the value of the PKRU register:
— If ADi = 1, no data accesses are permitted.
— If WDi = 1, permission may be denied to certain data write accesses:
•
•
4.7
User-mode write accesses are not permitted.
Supervisor-mode write accesses are not permitted if CR0.WP = 1. (If CR0.WP = 0, WDi does not affect
supervisor-mode write accesses to user-mode addresses with protection key i.)
PAGE-FAULT EXCEPTIONS
Accesses using linear addresses may cause page-fault exceptions (#PF; exception 14). An access to a linear
address may cause a page-fault exception for either of two reasons: (1) there is no translation for the linear
address; or (2) there is a translation for the linear address, but its access rights do not permit the access.
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As noted in Section 4.3, Section 4.4.2, and Section 4.5, there is no translation for a linear address if the translation
process for that address would use a paging-structure entry in which the P flag (bit 0) is 0 or one that sets a
reserved bit. If there is a translation for a linear address, its access rights are determined as specified in Section
4.6.
When Intel® Software Guard Extensions (Intel® SGX) are enabled, the processor may deliver exception 14 for
reasons unrelated to paging. See Section 38.3, “Access-control Requirements” and Section 38.19, “Enclave Page
Cache Map (EPCM)” in Chapter 38, “Enclave Access Control and Data Structures.” Such an exception is called an
SGX-induced page fault. The processor uses the error code to distinguish SGX-induced page faults from ordinary
page faults.
Figure 4-12 illustrates the error code that the processor provides on delivery of a page-fault exception. The
following items explain how the bits in the error code describe the nature of the page-fault exception:
31
5 4 3 2 1 0
15
Reserved
P
W/R
U/S
RSVD
I/D
PK
SGX
Reserved
P
0 The fault was caused by a non-present page.
1 The fault was caused by a page-level protection violation.
W/R
0 The access causing the fault was a read.
1 The access causing the fault was a write.
U/S
0 A supervisor-mode access caused the fault.
1 A user-mode access caused the fault.
RSVD
0 The fault was not caused by reserved bit violation.
1 The fault was caused by a reserved bit set to 1 in some
paging-structure entry.
I/D
0 The fault was not caused by an instruction fetch.
1 The fault was caused by an instruction fetch.
PK
0 The fault was not caused by protection keys.
1 There was a protection-key violation.
SGX
0 The fault is not related to SGX.
1 The fault resulted from violation of SGX-specific access-control
requirements.
Figure 4-12. Page-Fault Error Code
•
P flag (bit 0).
This flag is 0 if there is no translation for the linear address because the P flag was 0 in one of the pagingstructure entries used to translate that address.
•
W/R (bit 1).
If the access causing the page-fault exception was a write, this flag is 1; otherwise, it is 0. This flag describes
the access causing the page-fault exception, not the access rights specified by paging.
•
U/S (bit 2).
If a user-mode access caused the page-fault exception, this flag is 1; it is 0 if a supervisor-mode access did so.
This flag describes the access causing the page-fault exception, not the access rights specified by paging. Usermode and supervisor-mode accesses are defined in Section 4.6.
•
RSVD flag (bit 3).
This flag is 1 if there is no translation for the linear address because a reserved bit was set in one of the pagingstructure entries used to translate that address. (Because reserved bits are not checked in a paging-structure
entry whose P flag is 0, bit 3 of the error code can be set only if bit 0 is also set.1)
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PAGING
Bits reserved in the paging-structure entries are reserved for future functionality. Software developers should
be aware that such bits may be used in the future and that a paging-structure entry that causes a page-fault
exception on one processor might not do so in the future.
•
I/D flag (bit 4).
This flag is 1 if (1) the access causing the page-fault exception was an instruction fetch; and (2) either
(a) CR4.SMEP = 1; or (b) both (i) CR4.PAE = 1 (either PAE paging or IA-32e paging is in use); and
(ii) IA32_EFER.NXE = 1. Otherwise, the flag is 0. This flag describes the access causing the page-fault
exception, not the access rights specified by paging.
•
PK flag (bit 5).
This flag is 1 if (1) IA32_EFER.LMA = CR4.PKE = 1; (2) the access causing the page-fault exception was a data
access; (3) the linear address was a user-mode address with protection key i; and (5) the PKRU register (see
Section 4.6.2) is such that either (a) ADi = 1; or (b) the following all hold: (i) WDi = 1; (ii) the access is a write
access; and (iii) either CR0.WP = 1 or the access causing the page-fault exception was a user-mode access.
•
SGX flag (bit 15).
This flag is 1 if the exception is unrelated to paging and resulted from violation of SGX-specific access-control
requirements. Because such a violation can occur only if there is no ordinary page fault, this flag is set only if
the P flag (bit 0) is 1 and the RSVD flag (bit 3) and the PK flag (bit 5) are both 0.
Page-fault exceptions occur only due to an attempt to use a linear address. Failures to load the PDPTE registers
with PAE paging (see Section 4.4.1) cause general-protection exceptions (#GP(0)) and not page-fault exceptions.
4.8
ACCESSED AND DIRTY FLAGS
For any paging-structure entry that is used during linear-address translation, bit 5 is the accessed flag.1 For
paging-structure entries that map a page (as opposed to referencing another paging structure), bit 6 is the dirty
flag. These flags are provided for use by memory-management software to manage the transfer of pages and
paging structures into and out of physical memory.
Whenever the processor uses a paging-structure entry as part of linear-address translation, it sets the accessed
flag in that entry (if it is not already set).
Whenever there is a write to a linear address, the processor sets the dirty flag (if it is not already set) in the pagingstructure entry that identifies the final physical address for the linear address (either a PTE or a paging-structure
entry in which the PS flag is 1).
Memory-management software may clear these flags when a page or a paging structure is initially loaded into
physical memory. These flags are “sticky,” meaning that, once set, the processor does not clear them; only software can clear them.
A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see
Section 4.10). This fact implies that, if software changes an accessed flag or a dirty flag from 1 to 0, the processor
might not set the corresponding bit in memory on a subsequent access using an affected linear address (see
Section 4.10.4.3). See Section 4.10.4.2 for how software can ensure that these bits are updated as desired.
NOTE
The accesses used by the processor to set these flags may or may not be exposed to the
processor’s self-modifying code detection logic. If the processor is executing code from the same
memory area that is being used for the paging structures, the setting of these flags may or may not
result in an immediate change to the executing code stream.
1. Some past processors had errata for some page faults that occur when there is no translation for the linear address because the P
flag was 0 in one of the paging-structure entries used to translate that address. Due to these errata, some such page faults produced error codes that cleared bit 0 (P flag) and set bit 3 (RSVD flag).
1. With PAE paging, the PDPTEs are not used during linear-address translation but only to load the PDPTE registers for some executions of the MOV CR instruction (see Section 4.4.1). For this reason, the PDPTEs do not contain accessed flags with PAE paging.
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4.9
PAGING AND MEMORY TYPING
The memory type of a memory access refers to the type of caching used for that access. Chapter 11, “Memory
Cache Control” provides many details regarding memory typing in the Intel-64 and IA-32 architectures. This
section describes how paging contributes to the determination of memory typing.
The way in which paging contributes to memory typing depends on whether the processor supports the Page
Attribute Table (PAT; see Section 11.12).1 Section 4.9.1 and Section 4.9.2 explain how paging contributes to
memory typing depending on whether the PAT is supported.
4.9.1
Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium
II Processors)
NOTE
The PAT is supported on all processors that support IA-32e paging. Thus, this section applies only
to 32-bit paging and PAE paging.
If the PAT is not supported, paging contributes to memory typing in conjunction with the memory-type range registers (MTRRs) as specified in Table 11-6 in Section 11.5.2.1.
For any access to a physical address, the table combines the memory type specified for that physical address by
the MTRRs with a PCD value and a PWT value. The latter two values are determined as follows:
•
•
•
•
For an access to a PDE with 32-bit paging, the PCD and PWT values come from CR3.
•
With PAE paging, the UC memory type is used when loading the PDPTEs (see Section 4.4.1).
For an access to a PDE with PAE paging, the PCD and PWT values come from the relevant PDPTE register.
For an access to a PTE, the PCD and PWT values come from the relevant PDE.
For an access to the physical address that is the translation of a linear address, the PCD and PWT values come
from the relevant PTE (if the translation uses a 4-KByte page) or the relevant PDE (otherwise).
4.9.2
Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent
Processor Families)
If the PAT is supported, paging contributes to memory typing in conjunction with the PAT and the memory-type
range registers (MTRRs) as specified in Table 11-7 in Section 11.5.2.2.
The PAT is a 64-bit MSR (IA32_PAT; MSR index 277H) comprising eight (8) 8-bit entries (entry i comprises
bits 8i+7:8i of the MSR).
For any access to a physical address, the table combines the memory type specified for that physical address by
the MTRRs with a memory type selected from the PAT. Table 11-11 in Section 11.12.3 specifies how a memory type
is selected from the PAT. Specifically, it comes from entry i of the PAT, where i is defined as follows:
•
For an access to an entry in a paging structure whose address is in CR3 (e.g., the PML4 table with IA-32e
paging):
— For IA-32e paging with CR4.PCIDE = 1, i = 0.
— Otherwise, i = 2*PCD+PWT, where the PCD and PWT values come from CR3.
•
For an access to a PDE with PAE paging, i = 2*PCD+PWT, where the PCD and PWT values come from the
relevant PDPTE register.
•
For an access to a paging-structure entry X whose address is in another paging-structure entry Y, i =
2*PCD+PWT, where the PCD and PWT values come from Y.
1. The PAT is supported on Pentium III and more recent processor families. See Section 4.1.4 for how to determine whether the PAT is
supported.
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PAGING
•
For an access to the physical address that is the translation of a linear address, i = 4*PAT+2*PCD+PWT, where
the PAT, PCD, and PWT values come from the relevant PTE (if the translation uses a 4-KByte page), the relevant
PDE (if the translation uses a 2-MByte page or a 4-MByte page), or the relevant PDPTE (if the translation uses
a 1-GByte page).
•
With PAE paging, the WB memory type is used when loading the PDPTEs (see Section 4.4.1).1
4.9.3
Caching Paging-Related Information about Memory Typing
A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see
Section 4.10). These structures may include information about memory typing. The processor may use memorytyping information from the TLBs and paging-structure caches instead of from the paging structures in memory.
This fact implies that, if software modifies a paging-structure entry to change the memory-typing bits, the
processor might not use that change for a subsequent translation using that entry or for access to an affected
linear address. See Section 4.10.4.2 for how software can ensure that the processor uses the modified memory
typing.
4.10
CACHING TRANSLATION INFORMATION
The Intel-64 and IA-32 architectures may accelerate the address-translation process by caching data from the
paging structures on the processor. Because the processor does not ensure that the data that it caches are always
consistent with the structures in memory, it is important for software developers to understand how and when the
processor may cache such data. They should also understand what actions software can take to remove cached
data that may be inconsistent and when it should do so. This section provides software developers information
about the relevant processor operation.
Section 4.10.1 introduces process-context identifiers (PCIDs), which a logical processor may use to distinguish
information cached for different linear-address spaces. Section 4.10.2 and Section 4.10.3 describe how the
processor may cache information in translation lookaside buffers (TLBs) and paging-structure caches, respectively.
Section 4.10.4 explains how software can remove inconsistent cached information by invalidating portions of the
TLBs and paging-structure caches. Section 4.10.5 describes special considerations for multiprocessor systems.
4.10.1
Process-Context Identifiers (PCIDs)
Process-context identifiers (PCIDs) are a facility by which a logical processor may cache information for multiple
linear-address spaces. The processor may retain cached information when software switches to a different linearaddress space with a different PCID (e.g., by loading CR3; see Section 4.10.4.1 for details).
A PCID is a 12-bit identifier. Non-zero PCIDs are enabled by setting the PCIDE flag (bit 17) of CR4. If CR4.PCIDE =
0, the current PCID is always 000H; otherwise, the current PCID is the value of bits 11:0 of CR3. Not all processors
allow CR4.PCIDE to be set to 1; see Section 4.1.4 for how to determine whether this is allowed.
The processor ensures that CR4.PCIDE can be 1 only in IA-32e mode (thus, 32-bit paging and PAE paging use only
PCID 000H). In addition, software can change CR4.PCIDE from 0 to 1 only if CR3[11:0] = 000H. These requirements are enforced by the following limitations on the MOV CR instruction:
•
MOV to CR4 causes a general-protection exception (#GP) if it would change CR4.PCIDE from 0 to 1 and either
IA32_EFER.LMA = 0 or CR3[11:0] ≠ 000H.
•
MOV to CR0 causes a general-protection exception if it would clear CR0.PG to 0 while CR4.PCIDE = 1.
When a logical processor creates entries in the TLBs (Section 4.10.2) and paging-structure caches (Section
4.10.3), it associates those entries with the current PCID. When using entries in the TLBs and paging-structure
caches to translate a linear address, a logical processor uses only those entries associated with the current PCID
(see Section 4.10.2.4 for an exception).
1. Some older IA-32 processors used the UC memory type when loading the PDPTEs. Some processors may use the UC memory type if
CR0.CD = 1 or if the MTRRs are disabled. These behaviors are model-specific and not architectural.
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If CR4.PCIDE = 0, a logical processor does not cache information for any PCID other than 000H. This is because
(1) if CR4.PCIDE = 0, the logical processor will associate any newly cached information with the current PCID,
000H; and (2) if MOV to CR4 clears CR4.PCIDE, all cached information is invalidated (see Section 4.10.4.1).
NOTE
In revisions of this manual that were produced when no processors allowed CR4.PCIDE to be set to
1, Section 4.10 discussed the caching of translation information without any reference to PCIDs.
While the section now refers to PCIDs in its specification of this caching, this documentation change
is not intended to imply any change to the behavior of processors that do not allow CR4.PCIDE to
be set to 1.
4.10.2
Translation Lookaside Buffers (TLBs)
A processor may cache information about the translation of linear addresses in translation lookaside buffers (TLBs).
In general, TLBs contain entries that map page numbers to page frames; these terms are defined in Section
4.10.2.1. Section 4.10.2.2 describes how information may be cached in TLBs, and Section 4.10.2.3 gives details of
TLB usage. Section 4.10.2.4 explains the global-page feature, which allows software to indicate that certain translations should receive special treatment when cached in the TLBs.
4.10.2.1
Page Numbers, Page Frames, and Page Offsets
Section 4.3, Section 4.4.2, and Section 4.5 give details of how the different paging modes translate linear
addresses to physical addresses. Specifically, the upper bits of a linear address (called the page number) determine the upper bits of the physical address (called the page frame); the lower bits of the linear address (called the
page offset) determine the lower bits of the physical address. The boundary between the page number and the
page offset is determined by the page size. Specifically:
•
32-bit paging:
— If the translation does not use a PTE (because CR4.PSE = 1 and the PS flag is 1 in the PDE used), the page
size is 4 MBytes and the page number comprises bits 31:22 of the linear address.
— If the translation does use a PTE, the page size is 4 KBytes and the page number comprises bits 31:12 of
the linear address.
•
PAE paging:
— If the translation does not use a PTE (because the PS flag is 1 in the PDE used), the page size is 2 MBytes
and the page number comprises bits 31:21 of the linear address.
— If the translation does uses a PTE, the page size is 4 KBytes and the page number comprises bits 31:12 of
the linear address.
•
IA-32e paging:
— If the translation does not use a PDE (because the PS flag is 1 in the PDPTE used), the page size is 1 GByte
and the page number comprises bits 47:30 of the linear address.
— If the translation does use a PDE but does not uses a PTE (because the PS flag is 1 in the PDE used), the
page size is 2 MBytes and the page number comprises bits 47:21 of the linear address.
— If the translation does use a PTE, the page size is 4 KBytes and the page number comprises bits 47:12 of
the linear address.
4.10.2.2
Caching Translations in TLBs
The processor may accelerate the paging process by caching individual translations in translation lookaside
buffers (TLBs). Each entry in a TLB is an individual translation. Each translation is referenced by a page number.
It contains the following information from the paging-structure entries used to translate linear addresses with the
page number:
•
The physical address corresponding to the page number (the page frame).
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•
The access rights from the paging-structure entries used to translate linear addresses with the page number
(see Section 4.6):
— The logical-AND of the R/W flags.
— The logical-AND of the U/S flags.
— The logical-OR of the XD flags (necessary only if IA32_EFER.NXE = 1).
— The protection key (necessary only with IA-32e paging and CR4.PKE = 1).
•
Attributes from a paging-structure entry that identifies the final page frame for the page number (either a PTE
or a paging-structure entry in which the PS flag is 1):
— The dirty flag (see Section 4.8).
— The memory type (see Section 4.9).
(TLB entries may contain other information as well. A processor may implement multiple TLBs, and some of these
may be for special purposes, e.g., only for instruction fetches. Such special-purpose TLBs may not contain some of
this information if it is not necessary. For example, a TLB used only for instruction fetches need not contain information about the R/W and dirty flags.)
As noted in Section 4.10.1, any TLB entries created by a logical processor are associated with the current PCID.
Processors need not implement any TLBs. Processors that do implement TLBs may invalidate any TLB entry at any
time. Software should not rely on the existence of TLBs or on the retention of TLB entries.
4.10.2.3
Details of TLB Use
Because the TLBs cache entries only for linear addresses with translations, there can be a TLB entry for a page
number only if the P flag is 1 and the reserved bits are 0 in each of the paging-structure entries used to translate
that page number. In addition, the processor does not cache a translation for a page number unless the accessed
flag is 1 in each of the paging-structure entries used during translation; before caching a translation, the processor
sets any of these accessed flags that is not already 1.
The processor may cache translations required for prefetches and for accesses that are a result of speculative
execution that would never actually occur in the executed code path.
If the page number of a linear address corresponds to a TLB entry associated with the current PCID, the processor
may use that TLB entry to determine the page frame, access rights, and other attributes for accesses to that linear
address. In this case, the processor may not actually consult the paging structures in memory. The processor may
retain a TLB entry unmodified even if software subsequently modifies the relevant paging-structure entries in
memory. See Section 4.10.4.2 for how software can ensure that the processor uses the modified paging-structure
entries.
If the paging structures specify a translation using a page larger than 4 KBytes, some processors may cache
multiple smaller-page TLB entries for that translation. Each such TLB entry would be associated with a page
number corresponding to the smaller page size (e.g., bits 47:12 of a linear address with IA-32e paging), even
though part of that page number (e.g., bits 20:12) is part of the offset with respect to the page specified by the
paging structures. The upper bits of the physical address in such a TLB entry are derived from the physical address
in the PDE used to create the translation, while the lower bits come from the linear address of the access for which
the translation is created. There is no way for software to be aware that multiple translations for smaller pages
have been used for a large page. For example, an execution of INVLPG for a linear address on such a page invalidates any and all smaller-page TLB entries for the translation of any linear address on that page.
If software modifies the paging structures so that the page size used for a 4-KByte range of linear addresses
changes, the TLBs may subsequently contain multiple translations for the address range (one for each page size).
A reference to a linear address in the address range may use any of these translations. Which translation is used
may vary from one execution to another, and the choice may be implementation-specific.
4.10.2.4
Global Pages
The Intel-64 and IA-32 architectures also allow for global pages when the PGE flag (bit 7) is 1 in CR4. If the G flag
(bit 8) is 1 in a paging-structure entry that maps a page (either a PTE or a paging-structure entry in which the PS
flag is 1), any TLB entry cached for a linear address using that paging-structure entry is considered to be global.
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Because the G flag is used only in paging-structure entries that map a page, and because information from such
entries is not cached in the paging-structure caches, the global-page feature does not affect the behavior of the
paging-structure caches.
A logical processor may use a global TLB entry to translate a linear address, even if the TLB entry is associated with
a PCID different from the current PCID.
4.10.3
Paging-Structure Caches
In addition to the TLBs, a processor may cache other information about the paging structures in memory.
4.10.3.1
Caches for Paging Structures
A processor may support any or all of the following paging-structure caches:
•
PML4 cache (IA-32e paging only). Each PML4-cache entry is referenced by a 9-bit value and is used for linear
addresses for which bits 47:39 have that value. The entry contains information from the PML4E used to
translate such linear addresses:
— The physical address from the PML4E (the address of the page-directory-pointer table).
— The value of the R/W flag of the PML4E.
— The value of the U/S flag of the PML4E.
— The value of the XD flag of the PML4E.
— The values of the PCD and PWT flags of the PML4E.
The following items detail how a processor may use the PML4 cache:
— If the processor has a PML4-cache entry for a linear address, it may use that entry when translating the
linear address (instead of the PML4E in memory).
— The processor does not create a PML4-cache entry unless the P flag is 1 and all reserved bits are 0 in the
PML4E in memory.
— The processor does not create a PML4-cache entry unless the accessed flag is 1 in the PML4E in memory;
before caching a translation, the processor sets the accessed flag if it is not already 1.
— The processor may create a PML4-cache entry even if there are no translations for any linear address that
might use that entry (e.g., because the P flags are 0 in all entries in the referenced page-directory-pointer
table).
— If the processor creates a PML4-cache entry, the processor may retain it unmodified even if software subsequently modifies the corresponding PML4E in memory.
•
PDPTE cache (IA-32e paging only).1 Each PDPTE-cache entry is referenced by an 18-bit value and is used for
linear addresses for which bits 47:30 have that value. The entry contains information from the PML4E and
PDPTE used to translate such linear addresses:
— The physical address from the PDPTE (the address of the page directory). (No PDPTE-cache entry is created
for a PDPTE that maps a 1-GByte page.)
— The logical-AND of the R/W flags in the PML4E and the PDPTE.
— The logical-AND of the U/S flags in the PML4E and the PDPTE.
— The logical-OR of the XD flags in the PML4E and the PDPTE.
— The values of the PCD and PWT flags of the PDPTE.
The following items detail how a processor may use the PDPTE cache:
— If the processor has a PDPTE-cache entry for a linear address, it may use that entry when translating the
linear address (instead of the PML4E and the PDPTE in memory).
1. With PAE paging, the PDPTEs are stored in internal, non-architectural registers. The operation of these registers is described in Section 4.4.1 and differs from that described here.
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— The processor does not create a PDPTE-cache entry unless the P flag is 1, the PS flag is 0, and the reserved
bits are 0 in the PML4E and the PDPTE in memory.
— The processor does not create a PDPTE-cache entry unless the accessed flags are 1 in the PML4E and the
PDPTE in memory; before caching a translation, the processor sets any accessed flags that are not already
1.
— The processor may create a PDPTE-cache entry even if there are no translations for any linear address that
might use that entry.
— If the processor creates a PDPTE-cache entry, the processor may retain it unmodified even if software
subsequently modifies the corresponding PML4E or PDPTE in memory.
•
PDE cache. The use of the PDE cache depends on the paging mode:
— For 32-bit paging, each PDE-cache entry is referenced by a 10-bit value and is used for linear addresses for
which bits 31:22 have that value.
— For PAE paging, each PDE-cache entry is referenced by an 11-bit value and is used for linear addresses for
which bits 31:21 have that value.
— For IA-32e paging, each PDE-cache entry is referenced by a 27-bit value and is used for linear addresses
for which bits 47:21 have that value.
A PDE-cache entry contains information from the PML4E, PDPTE, and PDE used to translate the relevant linear
addresses (for 32-bit paging and PAE paging, only the PDE applies):
— The physical address from the PDE (the address of the page table). (No PDE-cache entry is created for a
PDE that maps a page.)
— The logical-AND of the R/W flags in the PML4E, PDPTE, and PDE.
— The logical-AND of the U/S flags in the PML4E, PDPTE, and PDE.
— The logical-OR of the XD flags in the PML4E, PDPTE, and PDE.
— The values of the PCD and PWT flags of the PDE.
The following items detail how a processor may use the PDE cache (references below to PML4Es and PDPTEs
apply only to IA-32e paging):
— If the processor has a PDE-cache entry for a linear address, it may use that entry when translating the
linear address (instead of the PML4E, the PDPTE, and the PDE in memory).
— The processor does not create a PDE-cache entry unless the P flag is 1, the PS flag is 0, and the reserved
bits are 0 in the PML4E, the PDPTE, and the PDE in memory.
— The processor does not create a PDE-cache entry unless the accessed flag is 1 in the PML4E, the PDPTE,
and the PDE in memory; before caching a translation, the processor sets any accessed flags that are not
already 1.
— The processor may create a PDE-cache entry even if there are no translations for any linear address that
might use that entry.
— If the processor creates a PDE-cache entry, the processor may retain it unmodified even if software subsequently modifies the corresponding PML4E, the PDPTE, or the PDE in memory.
Information from a paging-structure entry can be included in entries in the paging-structure caches for other
paging-structure entries referenced by the original entry. For example, if the R/W flag is 0 in a PML4E, then the R/W
flag will be 0 in any PDPTE-cache entry for a PDPTE from the page-directory-pointer table referenced by that
PML4E. This is because the R/W flag of each such PDPTE-cache entry is the logical-AND of the R/W flags in the
appropriate PML4E and PDPTE.
The paging-structure caches contain information only from paging-structure entries that reference other paging
structures (and not those that map pages). Because the G flag is not used in such paging-structure entries, the
global-page feature does not affect the behavior of the paging-structure caches.
The processor may create entries in paging-structure caches for translations required for prefetches and for
accesses that are a result of speculative execution that would never actually occur in the executed code path.
As noted in Section 4.10.1, any entries created in paging-structure caches by a logical processor are associated
with the current PCID.
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A processor may or may not implement any of the paging-structure caches. Software should rely on neither their
presence nor their absence. The processor may invalidate entries in these caches at any time. Because the
processor may create the cache entries at the time of translation and not update them following subsequent modifications to the paging structures in memory, software should take care to invalidate the cache entries appropriately when causing such modifications. The invalidation of TLBs and the paging-structure caches is described in
Section 4.10.4.
4.10.3.2
Using the Paging-Structure Caches to Translate Linear Addresses
When a linear address is accessed, the processor uses a procedure such as the following to determine the physical
address to which it translates and whether the access should be allowed:
•
If the processor finds a TLB entry that is for the page number of the linear address and that is associated with
the current PCID (or which is global), it may use the physical address, access rights, and other attributes from
that entry.
•
If the processor does not find a relevant TLB entry, it may use the upper bits of the linear address to select an
entry from the PDE cache that is associated with the current PCID (Section 4.10.3.1 indicates which bits are
used in each paging mode). It can then use that entry to complete the translation process (locating a PTE, etc.)
as if it had traversed the PDE (and, for IA-32e paging, the PDPTE and PML4E) corresponding to the PDE-cache
entry.
•
The following items apply when IA-32e paging is used:
— If the processor does not find a relevant TLB entry or a relevant PDE-cache entry, it may use bits 47:30 of
the linear address to select an entry from the PDPTE cache that is associated with the current PCID. It can
then use that entry to complete the translation process (locating a PDE, etc.) as if it had traversed the
PDPTE and the PML4E corresponding to the PDPTE-cache entry.
— If the processor does not find a relevant TLB entry, a relevant PDE-cache entry, or a relevant PDPTE-cache
entry, it may use bits 47:39 of the linear address to select an entry from the PML4 cache that is associated
with the current PCID. It can then use that entry to complete the translation process (locating a PDPTE,
etc.) as if it had traversed the corresponding PML4E.
(Any of the above steps would be skipped if the processor does not support the cache in question.)
If the processor does not find a TLB or paging-structure-cache entry for the linear address, it uses the linear
address to traverse the entire paging-structure hierarchy, as described in Section 4.3, Section 4.4.2, and Section
4.5.
4.10.3.3
Multiple Cached Entries for a Single Paging-Structure Entry
The paging-structure caches and TLBs may contain multiple entries associated with a single PCID and with information derived from a single paging-structure entry. The following items give some examples for IA-32e paging:
•
Suppose that two PML4Es contain the same physical address and thus reference the same page-directorypointer table. Any PDPTE in that table may result in two PDPTE-cache entries, each associated with a different
set of linear addresses. Specifically, suppose that the n1th and n2th entries in the PML4 table contain the same
physical address. This implies that the physical address in the mth PDPTE in the page-directory-pointer table
would appear in the PDPTE-cache entries associated with both p1 and p2, where (p1 » 9) = n1, (p2 » 9) = n2,
and (p1 & 1FFH) = (p2 & 1FFH) = m. This is because both PDPTE-cache entries use the same PDPTE, one
resulting from a reference from the n1th PML4E and one from the n2th PML4E.
•
Suppose that the first PML4E (i.e., the one in position 0) contains the physical address X in CR3 (the physical
address of the PML4 table). This implies the following:
— Any PML4-cache entry associated with linear addresses with 0 in bits 47:39 contains address X.
— Any PDPTE-cache entry associated with linear addresses with 0 in bits 47:30 contains address X. This is
because the translation for a linear address for which the value of bits 47:30 is 0 uses the value of
bits 47:39 (0) to locate a page-directory-pointer table at address X (the address of the PML4 table). It then
uses the value of bits 38:30 (also 0) to find address X again and to store that address in the PDPTE-cache
entry.
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— Any PDE-cache entry associated with linear addresses with 0 in bits 47:21 contains address X for similar
reasons.
— Any TLB entry for page number 0 (associated with linear addresses with 0 in bits 47:12) translates to page
frame X » 12 for similar reasons.
The same PML4E contributes its address X to all these cache entries because the self-referencing nature of the
entry causes it to be used as a PML4E, a PDPTE, a PDE, and a PTE.
4.10.4
Invalidation of TLBs and Paging-Structure Caches
As noted in Section 4.10.2 and Section 4.10.3, the processor may create entries in the TLBs and the paging-structure caches when linear addresses are translated, and it may retain these entries even after the paging structures
used to create them have been modified. To ensure that linear-address translation uses the modified paging structures, software should take action to invalidate any cached entries that may contain information that has since
been modified.
4.10.4.1
Operations that Invalidate TLBs and Paging-Structure Caches
The following instructions invalidate entries in the TLBs and the paging-structure caches:
•
INVLPG. This instruction takes a single operand, which is a linear address. The instruction invalidates any TLB
entries that are for a page number corresponding to the linear address and that are associated with the current
PCID. It also invalidates any global TLB entries with that page number, regardless of PCID (see Section
4.10.2.4).1 INVLPG also invalidates all entries in all paging-structure caches associated with the current PCID,
regardless of the linear addresses to which they correspond.
•
INVPCID. The operation of this instruction is based on instruction operands, called the INVPCID type and the
INVPCID descriptor. Four INVPCID types are currently defined:
— Individual-address. If the INVPCID type is 0, the logical processor invalidates mappings—except global
translations—associated with the PCID specified in the INVPCID descriptor and that would be used to
translate the linear address specified in the INVPCID descriptor.2 (The instruction may also invalidate global
translations, as well as mappings associated with other PCIDs and for other linear addresses.)
— Single-context. If the INVPCID type is 1, the logical processor invalidates all mappings—except global
translations—associated with the PCID specified in the INVPCID descriptor. (The instruction may also
invalidate global translations, as well as mappings associated with other PCIDs.)
— All-context, including globals. If the INVPCID type is 2, the logical processor invalidates
mappings—including global translations—associated with all PCIDs.
— All-context. If the INVPCID type is 3, the logical processor invalidates mappings—except global translations—associated with all PCIDs. (The instruction may also invalidate global translations.)
See Chapter 3 of the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 2A for details of the
INVPCID instruction.
•
MOV to CR0. The instruction invalidates all TLB entries (including global entries) and all entries in all pagingstructure caches (for all PCIDs) if it changes the value of CR0.PG from 1 to 0.
•
MOV to CR3. The behavior of the instruction depends on the value of CR4.PCIDE:
— If CR4.PCIDE = 0, the instruction invalidates all TLB entries associated with PCID 000H except those for
global pages. It also invalidates all entries in all paging-structure caches associated with PCID 000H.
— If CR4.PCIDE = 1 and bit 63 of the instruction’s source operand is 0, the instruction invalidates all TLB
entries associated with the PCID specified in bits 11:0 of the instruction’s source operand except those for
global pages. It also invalidates all entries in all paging-structure caches associated with that PCID. It is not
required to invalidate entries in the TLBs and paging-structure caches that are associated with other PCIDs.
1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page
(see Section 4.10.2.3), the instruction invalidates all of them.
2. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page
(see Section 4.10.2.3), the instruction invalidates all of them.
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— If CR4.PCIDE = 1 and bit 63 of the instruction’s source operand is 1, the instruction is not required to
invalidate any TLB entries or entries in paging-structure caches.
•
MOV to CR4. The behavior of the instruction depends on the bits being modified:
— The instruction invalidates all TLB entries (including global entries) and all entries in all paging-structure
caches (for all PCIDs) if (1) it changes the value of CR4.PGE;1 or (2) it changes the value of the CR4.PCIDE
from 1 to 0.
— The instruction invalidates all TLB entries and all entries in all paging-structure caches for the current PCID
if (1) it changes the value of CR4.PAE; or (2) it changes the value of CR4.SMEP from 0 to 1.
•
Task switch. If a task switch changes the value of CR3, it invalidates all TLB entries associated with PCID 000H
except those for global pages. It also invalidates all entries in all paging-structure caches associated with PCID
000H.2
•
VMX transitions. See Section 4.11.1.
The processor is always free to invalidate additional entries in the TLBs and paging-structure caches. The following
are some examples:
•
INVLPG may invalidate TLB entries for pages other than the one corresponding to its linear-address operand. It
may invalidate TLB entries and paging-structure-cache entries associated with PCIDs other than the current
PCID.
•
INVPCID may invalidate TLB entries for pages other than the one corresponding to the specified linear address.
It may invalidate TLB entries and paging-structure-cache entries associated with PCIDs other than the specified
PCID.
•
MOV to CR0 may invalidate TLB entries even if CR0.PG is not changing. For example, this may occur if either
CR0.CD or CR0.NW is modified.
•
MOV to CR3 may invalidate TLB entries for global pages. If CR4.PCIDE = 1 and bit 63 of the instruction’s source
operand is 0, it may invalidate TLB entries and entries in the paging-structure caches associated with PCIDs
other than the PCID it is establishing. It may invalidate entries if CR4.PCIDE = 1 and bit 63 of the instruction’s
source operand is 1.
•
•
MOV to CR4 may invalidate TLB entries when changing CR4.PSE or when changing CR4.SMEP from 1 to 0.
On a processor supporting Hyper-Threading Technology, invalidations performed on one logical processor may
invalidate entries in the TLBs and paging-structure caches used by other logical processors.
(Other instructions and operations may invalidate entries in the TLBs and the paging-structure caches, but the
instructions identified above are recommended.)
In addition to the instructions identified above, page faults invalidate entries in the TLBs and paging-structure
caches. In particular, a page-fault exception resulting from an attempt to use a linear address will invalidate any
TLB entries that are for a page number corresponding to that linear address and that are associated with the
current PCID. It also invalidates all entries in the paging-structure caches that would be used for that linear address
and that are associated with the current PCID.3 These invalidations ensure that the page-fault exception will not
recur (if the faulting instruction is re-executed) if it would not be caused by the contents of the paging structures
in memory (and if, therefore, it resulted from cached entries that were not invalidated after the paging structures
were modified in memory).
As noted in Section 4.10.2, some processors may choose to cache multiple smaller-page TLB entries for a translation specified by the paging structures to use a page larger than 4 KBytes. There is no way for software to be aware
that multiple translations for smaller pages have been used for a large page. The INVLPG instruction and page
faults provide the same assurances that they provide when a single TLB entry is used: they invalidate all TLB
entries corresponding to the translation specified by the paging structures.
1. If CR4.PGE is changing from 0 to 1, there were no global TLB entries before the execution; if CR4.PGE is changing from 1 to 0, there
will be no global TLB entries after the execution.
2. Task switches do not occur in IA-32e mode and thus cannot occur with IA-32e paging. Since CR4.PCIDE can be set only with IA-32e
paging, task switches occur only with CR4.PCIDE = 0.
3. Unlike INVLPG, page faults need not invalidate all entries in the paging-structure caches, only those that would be used to translate
the faulting linear address.
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4.10.4.2
Recommended Invalidation
The following items provide some recommendations regarding when software should perform invalidations:
•
If software modifies a paging-structure entry that maps a page (rather than referencing another paging
structure), it should execute INVLPG for any linear address with a page number whose translation uses that
paging-structure entry.1
(If the paging-structure entry may be used in the translation of different page numbers — see Section 4.10.3.3
— software should execute INVLPG for linear addresses with each of those page numbers; alternatively, it could
use MOV to CR3 or MOV to CR4.)
•
If software modifies a paging-structure entry that references another paging structure, it may use one of the
following approaches depending upon the types and number of translations controlled by the modified entry:
— Execute INVLPG for linear addresses with each of the page numbers with translations that would use the
entry. However, if no page numbers that would use the entry have translations (e.g., because the P flags
are 0 in all entries in the paging structure referenced by the modified entry), it remains necessary to
execute INVLPG at least once.
— Execute MOV to CR3 if the modified entry controls no global pages.
— Execute MOV to CR4 to modify CR4.PGE.
•
If CR4.PCIDE = 1 and software modifies a paging-structure entry that does not map a page or in which the G
flag (bit 8) is 0, additional steps are required if the entry may be used for PCIDs other than the current one. Any
one of the following suffices:
— Execute MOV to CR4 to modify CR4.PGE, either immediately or before again using any of the affected
PCIDs. For example, software could use different (previously unused) PCIDs for the processes that used the
affected PCIDs.
— For each affected PCID, execute MOV to CR3 to make that PCID current (and to load the address of the
appropriate PML4 table). If the modified entry controls no global pages and bit 63 of the source operand to
MOV to CR3 was 0, no further steps are required. Otherwise, execute INVLPG for linear addresses with each
of the page numbers with translations that would use the entry; if no page numbers that would use the
entry have translations, execute INVLPG at least once.
•
If software using PAE paging modifies a PDPTE, it should reload CR3 with the register’s current value to ensure
that the modified PDPTE is loaded into the corresponding PDPTE register (see Section 4.4.1).
•
If the nature of the paging structures is such that a single entry may be used for multiple purposes (see Section
4.10.3.3), software should perform invalidations for all of these purposes. For example, if a single entry might
serve as both a PDE and PTE, it may be necessary to execute INVLPG with two (or more) linear addresses, one
that uses the entry as a PDE and one that uses it as a PTE. (Alternatively, software could use MOV to CR3 or
MOV to CR4.)
•
As noted in Section 4.10.2, the TLBs may subsequently contain multiple translations for the address range if
software modifies the paging structures so that the page size used for a 4-KByte range of linear addresses
changes. A reference to a linear address in the address range may use any of these translations.
Software wishing to prevent this uncertainty should not write to a paging-structure entry in a way that would
change, for any linear address, both the page size and either the page frame, access rights, or other attributes.
It can instead use the following algorithm: first clear the P flag in the relevant paging-structure entry (e.g.,
PDE); then invalidate any translations for the affected linear addresses (see above); and then modify the
relevant paging-structure entry to set the P flag and establish modified translation(s) for the new page size.
•
Software should clear bit 63 of the source operand to a MOV to CR3 instruction that establishes a PCID that had
been used earlier for a different linear-address space (e.g., with a different value in bits 51:12 of CR3). This
ensures invalidation of any information that may have been cached for the previous linear-address space.
This assumes that both linear-address spaces use the same global pages and that it is thus not necessary to
invalidate any global TLB entries. If that is not the case, software should invalidate those entries by executing
MOV to CR4 to modify CR4.PGE.
1. One execution of INVLPG is sufficient even for a page with size greater than 4 KBytes.
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4.10.4.3
Optional Invalidation
The following items describe cases in which software may choose not to invalidate and the potential consequences
of that choice:
•
If a paging-structure entry is modified to change the P flag from 0 to 1, no invalidation is necessary. This is
because no TLB entry or paging-structure cache entry is created with information from a paging-structure entry
in which the P flag is 0.1
•
If a paging-structure entry is modified to change the accessed flag from 0 to 1, no invalidation is necessary
(assuming that an invalidation was performed the last time the accessed flag was changed from 1 to 0). This is
because no TLB entry or paging-structure cache entry is created with information from a paging-structure entry
in which the accessed flag is 0.
•
If a paging-structure entry is modified to change the R/W flag from 0 to 1, failure to perform an invalidation
may result in a “spurious” page-fault exception (e.g., in response to an attempted write access) but no other
adverse behavior. Such an exception will occur at most once for each affected linear address (see Section
4.10.4.1).
•
If CR4.SMEP = 0 and a paging-structure entry is modified to change the U/S flag from 0 to 1, failure to perform
an invalidation may result in a “spurious” page-fault exception (e.g., in response to an attempted user-mode
access) but no other adverse behavior. Such an exception will occur at most once for each affected linear
address (see Section 4.10.4.1).
•
If a paging-structure entry is modified to change the XD flag from 1 to 0, failure to perform an invalidation may
result in a “spurious” page-fault exception (e.g., in response to an attempted instruction fetch) but no other
adverse behavior. Such an exception will occur at most once for each affected linear address (see Section
4.10.4.1).
•
If a paging-structure entry is modified to change the accessed flag from 1 to 0, failure to perform an invalidation may result in the processor not setting that bit in response to a subsequent access to a linear address
whose translation uses the entry. Software cannot interpret the bit being clear as an indication that such an
access has not occurred.
•
If software modifies a paging-structure entry that identifies the final physical address for a linear address
(either a PTE or a paging-structure entry in which the PS flag is 1) to change the dirty flag from 1 to 0, failure
to perform an invalidation may result in the processor not setting that bit in response to a subsequent write to
a linear address whose translation uses the entry. Software cannot interpret the bit being clear as an indication
that such a write has not occurred.
•
The read of a paging-structure entry in translating an address being used to fetch an instruction may appear to
execute before an earlier write to that paging-structure entry if there is no serializing instruction between the
write and the instruction fetch. Note that the invalidating instructions identified in Section 4.10.4.1 are all
serializing instructions.
•
Section 4.10.3.3 describes situations in which a single paging-structure entry may contain information cached
in multiple entries in the paging-structure caches. Because all entries in these caches are invalidated by any
execution of INVLPG, it is not necessary to follow the modification of such a paging-structure entry by
executing INVLPG multiple times solely for the purpose of invalidating these multiple cached entries. (It may be
necessary to do so to invalidate multiple TLB entries.)
4.10.4.4
Delayed Invalidation
Required invalidations may be delayed under some circumstances. Software developers should understand that,
between the modification of a paging-structure entry and execution of the invalidation instruction recommended in
Section 4.10.4.2, the processor may use translations based on either the old value or the new value of the pagingstructure entry. The following items describe some of the potential consequences of delayed invalidation:
•
If a paging-structure entry is modified to change the P flag from 1 to 0, an access to a linear address whose
translation is controlled by this entry may or may not cause a page-fault exception.
1. If it is also the case that no invalidation was performed the last time the P flag was changed from 1 to 0, the processor may use a
TLB entry or paging-structure cache entry that was created when the P flag had earlier been 1.
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•
If a paging-structure entry is modified to change the R/W flag from 0 to 1, write accesses to linear addresses
whose translation is controlled by this entry may or may not cause a page-fault exception.
•
If a paging-structure entry is modified to change the U/S flag from 0 to 1, user-mode accesses to linear
addresses whose translation is controlled by this entry may or may not cause a page-fault exception.
•
If a paging-structure entry is modified to change the XD flag from 1 to 0, instruction fetches from linear
addresses whose translation is controlled by this entry may or may not cause a page-fault exception.
As noted in Section 8.1.1, an x87 instruction or an SSE instruction that accesses data larger than a quadword may
be implemented using multiple memory accesses. If such an instruction stores to memory and invalidation has
been delayed, some of the accesses may complete (writing to memory) while another causes a page-fault exception.1 In this case, the effects of the completed accesses may be visible to software even though the overall
instruction caused a fault.
In some cases, the consequences of delayed invalidation may not affect software adversely. For example, when
freeing a portion of the linear-address space (by marking paging-structure entries “not present”), invalidation
using INVLPG may be delayed if software does not re-allocate that portion of the linear-address space or the
memory that had been associated with it. However, because of speculative execution (or errant software), there
may be accesses to the freed portion of the linear-address space before the invalidations occur. In this case, the
following can happen:
•
Reads can occur to the freed portion of the linear-address space. Therefore, invalidation should not be delayed
for an address range that has read side effects.
•
The processor may retain entries in the TLBs and paging-structure caches for an extended period of time.
Software should not assume that the processor will not use entries associated with a linear address simply
because time has passed.
•
As noted in Section 4.10.3.1, the processor may create an entry in a paging-structure cache even if there are
no translations for any linear address that might use that entry. Thus, if software has marked “not present” all
entries in a page table, the processor may subsequently create a PDE-cache entry for the PDE that references
that page table (assuming that the PDE itself is marked “present”).
•
If software attempts to write to the freed portion of the linear-address space, the processor might not generate
a page fault. (Such an attempt would likely be the result of a software error.) For that reason, the page frames
previously associated with the freed portion of the linear-address space should not be reallocated for another
purpose until the appropriate invalidations have been performed.
4.10.5
Propagation of Paging-Structure Changes to Multiple Processors
As noted in Section 4.10.4, software that modifies a paging-structure entry may need to invalidate entries in the
TLBs and paging-structure caches that were derived from the modified entry before it was modified. In a system
containing more than one logical processor, software must account for the fact that there may be entries in the
TLBs and paging-structure caches of logical processors other than the one used to modify the paging-structure
entry. The process of propagating the changes to a paging-structure entry is commonly referred to as “TLB shootdown.”
TLB shootdown can be done using memory-based semaphores and/or interprocessor interrupts (IPI). The
following items describe a simple but inefficient example of a TLB shootdown algorithm for processors supporting
the Intel-64 and IA-32 architectures:
1. Begin barrier: Stop all but one logical processor; that is, cause all but one to execute the HLT instruction or to
enter a spin loop.
2. Allow the active logical processor to change the necessary paging-structure entries.
3. Allow all logical processors to perform invalidations appropriate to the modifications to the paging-structure
entries.
4. Allow all logical processors to resume normal operation.
Alternative, performance-optimized, TLB shootdown algorithms may be developed; however, software developers
must take care to ensure that the following conditions are met:
1. If the accesses are to different pages, this may occur even if invalidation has not been delayed.
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•
All logical processors that are using the paging structures that are being modified must participate and perform
appropriate invalidations after the modifications are made.
•
If the modifications to the paging-structure entries are made before the barrier or if there is no barrier, the
operating system must ensure one of the following: (1) that the affected linear-address range is not used
between the time of modification and the time of invalidation; or (2) that it is prepared to deal with the consequences of the affected linear-address range being used during that period. For example, if the operating
system does not allow pages being freed to be reallocated for another purpose until after the required invalidations, writes to those pages by errant software will not unexpectedly modify memory that is in use.
•
Software must be prepared to deal with reads, instruction fetches, and prefetch requests to the affected linearaddress range that are a result of speculative execution that would never actually occur in the executed code
path.
When multiple logical processors are using the same linear-address space at the same time, they must coordinate
before any request to modify the paging-structure entries that control that linear-address space. In these cases,
the barrier in the TLB shootdown routine may not be required. For example, when freeing a range of linear
addresses, some other mechanism can assure no logical processor is using that range before the request to free it
is made. In this case, a logical processor freeing the range can clear the P flags in the PTEs associated with the
range, free the physical page frames associated with the range, and then signal the other logical processors using
that linear-address space to perform the necessary invalidations. All the affected logical processors must complete
their invalidations before the linear-address range and the physical page frames previously associated with that
range can be reallocated.
4.11
INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX)
The architecture for virtual-machine extensions (VMX) includes features that interact with paging. Section 4.11.1
discusses ways in which VMX-specific control transfers, called VMX transitions specially affect paging. Section
4.11.2 gives an overview of VMX features specifically designed to support address translation.
4.11.1
VMX Transitions
The VMX architecture defines two control transfers called VM entries and VM exits; collectively, these are called
VMX transitions. VM entries and VM exits are described in detail in Chapter 26 and Chapter 27, respectively, in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C. The following items identify
paging-related details:
•
VMX transitions modify the CR0 and CR4 registers and the IA32_EFER MSR concurrently. For this reason, they
allow transitions between paging modes that would not otherwise be possible:
— VM entries allow transitions from IA-32e paging directly to either 32-bit paging or PAE paging.
— VM exits allow transitions from either 32-bit paging or PAE paging directly to IA-32e paging.
•
VMX transitions that result in PAE paging load the PDPTE registers (see Section 4.4.1) as follows:
— VM entries load the PDPTE registers either from the physical address being loaded into CR3 or from the
virtual-machine control structure (VMCS); see Section 26.3.2.4.
— VM exits load the PDPTE registers from the physical address being loaded into CR3; see Section 27.5.4.
•
VMX transitions invalidate the TLBs and paging-structure caches based on certain control settings. See Section
26.3.2.5 and Section 27.5.5 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
3C.
4.11.2
VMX Support for Address Translation
Chapter 28, “VMX Support for Address Translation,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C describe two features of the virtual-machine extensions (VMX) that interact directly with
paging. These are virtual-processor identifiers (VPIDs) and the extended page table mechanism (EPT).
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PAGING
VPIDs provide a way for software to identify to the processor the address spaces for different “virtual processors.”
The processor may use this identification to maintain concurrently information for multiple address spaces in its
TLBs and paging-structure caches, even when non-zero PCIDs are not being used. See Section 28.1 for details.
When EPT is in use, the addresses in the paging-structures are not used as physical addresses to access memory
and memory-mapped I/O. Instead, they are treated as guest-physical addresses and are translated through a
set of EPT paging structures to produce physical addresses. EPT can also specify its own access rights and memory
typing; these are used on conjunction with those specified in this chapter. See Section 28.2 for more information.
Both VPIDs and EPT may change the way that a processor maintains information in TLBs and paging structure
caches and the ways in which software can manage that information. Some of the behaviors documented in
Section 4.10 may change. See Section 28.3 for details.
4.12
USING PAGING FOR VIRTUAL MEMORY
With paging, portions of the linear-address space need not be mapped to the physical-address space; data for the
unmapped addresses can be stored externally (e.g., on disk). This method of mapping the linear-address space is
referred to as virtual memory or demand-paged virtual memory.
Paging divides the linear address space into fixed-size pages that can be mapped into the physical-address space
and/or external storage. When a program (or task) references a linear address, the processor uses paging to translate the linear address into a corresponding physical address if such an address is defined.
If the page containing the linear address is not currently mapped into the physical-address space, the processor
generates a page-fault exception as described in Section 4.7. The handler for page-fault exceptions typically
directs the operating system or executive to load data for the unmapped page from external storage into physical
memory (perhaps writing a different page from physical memory out to external storage in the process) and to
map it using paging (by updating the paging structures). When the page has been loaded into physical memory, a
return from the exception handler causes the instruction that generated the exception to be restarted.
Paging differs from segmentation through its use of fixed-size pages. Unlike segments, which usually are the same
size as the code or data structures they hold, pages have a fixed size. If segmentation is the only form of address
translation used, a data structure present in physical memory will have all of its parts in memory. If paging is used,
a data structure can be partly in memory and partly in disk storage.
4.13
MAPPING SEGMENTS TO PAGES
The segmentation and paging mechanisms provide support for a wide variety of approaches to memory management. When segmentation and paging are combined, segments can be mapped to pages in several ways. To implement a flat (unsegmented) addressing environment, for example, all the code, data, and stack modules can be
mapped to one or more large segments (up to 4-GBytes) that share same range of linear addresses (see
Figure 3-2 in Section 3.2.2). Here, segments are essentially invisible to applications and the operating-system or
executive. If paging is used, the paging mechanism can map a single linear-address space (contained in a single
segment) into virtual memory. Alternatively, each program (or task) can have its own large linear-address space
(contained in its own segment), which is mapped into virtual memory through its own paging structures.
Segments can be smaller than the size of a page. If one of these segments is placed in a page which is not shared
with another segment, the extra memory is wasted. For example, a small data structure, such as a 1-Byte semaphore, occupies 4 KBytes if it is placed in a page by itself. If many semaphores are used, it is more efficient to pack
them into a single page.
The Intel-64 and IA-32 architectures do not enforce correspondence between the boundaries of pages and
segments. A page can contain the end of one segment and the beginning of another. Similarly, a segment can
contain the end of one page and the beginning of another.
Memory-management software may be simpler and more efficient if it enforces some alignment between page and
segment boundaries. For example, if a segment which can fit in one page is placed in two pages, there may be
twice as much paging overhead to support access to that segment.
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One approach to combining paging and segmentation that simplifies memory-management software is to give each
segment its own page table, as shown in Figure 4-13. This convention gives the segment a single entry in the page
directory, and this entry provides the access control information for paging the entire segment.
Page Frames
LDT
Page Directory
Page Tables
PTE
PTE
PTE
Seg. Descript.
Seg. Descript.
PDE
PDE
PTE
PTE
Figure 4-13. Memory Management Convention That Assigns a Page Table
to Each Segment
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PROTECTION
In protected mode, the Intel 64 and IA-32 architectures provide a protection mechanism that operates at both the
segment level and the page level. This protection mechanism provides the ability to limit access to certain
segments or pages based on privilege levels (four privilege levels for segments and two privilege levels for pages).
For example, critical operating-system code and data can be protected by placing them in more privileged
segments than those that contain applications code. The processor’s protection mechanism will then prevent application code from accessing the operating-system code and data in any but a controlled, defined manner.
Segment and page protection can be used at all stages of software development to assist in localizing and detecting
design problems and bugs. It can also be incorporated into end-products to offer added robustness to operating
systems, utilities software, and applications software.
When the protection mechanism is used, each memory reference is checked to verify that it satisfies various
protection checks. All checks are made before the memory cycle is started; any violation results in an exception.
Because checks are performed in parallel with address translation, there is no performance penalty. The protection
checks that are performed fall into the following categories:
•
•
•
•
•
•
Limit checks.
Type checks.
Privilege level checks.
Restriction of addressable domain.
Restriction of procedure entry-points.
Restriction of instruction set.
All protection violation results in an exception being generated. See Chapter 6, “Interrupt and Exception Handling,”
for an explanation of the exception mechanism. This chapter describes the protection mechanism and the violations which lead to exceptions.
The following sections describe the protection mechanism available in protected mode. See Chapter 20, “8086
Emulation,” for information on protection in real-address and virtual-8086 mode.
5.1
ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION
Setting the PE flag in register CR0 causes the processor to switch to protected mode, which in turn enables the
segment-protection mechanism. Once in protected mode, there is no control bit for turning the protection mechanism on or off. The part of the segment-protection mechanism that is based on privilege levels can essentially be
disabled while still in protected mode by assigning a privilege level of 0 (most privileged) to all segment selectors
and segment descriptors. This action disables the privilege level protection barriers between segments, but other
protection checks such as limit checking and type checking are still carried out.
Page-level protection is automatically enabled when paging is enabled (by setting the PG flag in register CR0). Here
again there is no mode bit for turning off page-level protection once paging is enabled. However, page-level protection can be disabled by performing the following operations:
•
•
Clear the WP flag in control register CR0.
Set the read/write (R/W) and user/supervisor (U/S) flags for each page-directory and page-table entry.
This action makes each page a writable, user page, which in effect disables page-level protection.
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PROTECTION
5.2
FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND
PAGE-LEVEL PROTECTION
The processor’s protection mechanism uses the following fields and flags in the system data structures to control
access to segments and pages:
•
Descriptor type (S) flag — (Bit 12 in the second doubleword of a segment descriptor.) Determines if the
segment descriptor is for a system segment or a code or data segment.
•
Type field — (Bits 8 through 11 in the second doubleword of a segment descriptor.) Determines the type of
code, data, or system segment.
•
Limit field — (Bits 0 through 15 of the first doubleword and bits 16 through 19 of the second doubleword of a
segment descriptor.) Determines the size of the segment, along with the G flag and E flag (for data segments).
•
G flag — (Bit 23 in the second doubleword of a segment descriptor.) Determines the size of the segment, along
with the limit field and E flag (for data segments).
•
E flag — (Bit 10 in the second doubleword of a data-segment descriptor.) Determines the size of the segment,
along with the limit field and G flag.
•
Descriptor privilege level (DPL) field — (Bits 13 and 14 in the second doubleword of a segment descriptor.)
Determines the privilege level of the segment.
•
Requested privilege level (RPL) field — (Bits 0 and 1 of any segment selector.) Specifies the requested
privilege level of a segment selector.
•
Current privilege level (CPL) field — (Bits 0 and 1 of the CS segment register.) Indicates the privilege level
of the currently executing program or procedure. The term current privilege level (CPL) refers to the setting of
this field.
•
User/supervisor (U/S) flag — (Bit 2 of paging-structure entries.) Determines the type of page: user or
supervisor.
•
Read/write (R/W) flag — (Bit 1 of paging-structure entries.) Determines the type of access allowed to a
page: read-only or read/write.
•
Execute-disable (XD) flag — (Bit 63 of certain paging-structure entries.) Determines the type of access
allowed to a page: executable or not-executable.
Figure 5-1 shows the location of the various fields and flags in the data-, code-, and system-segment descriptors;
Figure 3-6 shows the location of the RPL (or CPL) field in a segment selector (or the CS register); and Chapter 4
identifies the locations of the U/S, R/W, and XD flags in the paging-structure entries.
5-2 Vol. 3A
PROTECTION
Data-Segment Descriptor
31
Base 31:24
24 23 22 21 20 19
16 15 14 13 12 11
A
G B 0 V
L
D
P
L
Limit
19:16
31
P
0
8 7
Type
4
Base 23:16
1 0 E W A
16 15
0
Base Address 15:00
0
Segment Limit 15:00
Code-Segment Descriptor
31
Base 31:24
24 23 22 21 20 19
16 15 14 13 12 11
A
G D 0 V
L
D
P
L
Limit
19:16
31
P
0
8 7
Type
4
Base 23:16
1 1 C R A
16 15
0
Base Address 15:00
0
Segment Limit 15:00
System-Segment Descriptor
31
24 23 22 21 20 19
Base 31:24
G
0
31
16 15 14 13 12 11
Limit
19:16
P
D
P
L
0
0
8 7
Type
16 15
Base Address 15:00
A
AVL
B
C
D
DPL
Accessed
Available to Sys. Programmers
Big
Conforming
Default
Descriptor Privilege Level
4
Base 23:16
0
Segment Limit 15:00
E
G
R
LIMIT
W
P
0
Expansion Direction
Granularity
Readable
Segment Limit
Writable
Present
Reserved
Figure 5-1. Descriptor Fields Used for Protection
Many different styles of protection schemes can be implemented with these fields and flags. When the operating
system creates a descriptor, it places values in these fields and flags in keeping with the particular protection style
chosen for an operating system or executive. Application programs do not generally access or modify these fields
and flags.
The following sections describe how the processor uses these fields and flags to perform the various categories of
checks described in the introduction to this chapter.
5.2.1
Code-Segment Descriptor in 64-bit Mode
Code segments continue to exist in 64-bit mode even though, for address calculations, the segment base is treated
as zero. Some code-segment (CS) descriptor content (the base address and limit fields) is ignored; the remaining
fields function normally (except for the readable bit in the type field).
Code segment descriptors and selectors are needed in IA-32e mode to establish the processor’s operating mode
and execution privilege-level. The usage is as follows:
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PROTECTION
•
IA-32e mode uses a previously unused bit in the CS descriptor. Bit 53 is defined as the 64-bit (L) flag and is
used to select between 64-bit mode and compatibility mode when IA-32e mode is active (IA32_EFER.LMA = 1).
See Figure 5-2.
— If CS.L = 0 and IA-32e mode is active, the processor is running in compatibility mode. In this case, CS.D
selects the default size for data and addresses. If CS.D = 0, the default data and address size is 16 bits. If
CS.D = 1, the default data and address size is 32 bits.
— If CS.L = 1 and IA-32e mode is active, the only valid setting is CS.D = 0. This setting indicates a default
operand size of 32 bits and a default address size of 64 bits. The CS.L = 1 and CS.D = 1 bit combination is
reserved for future use and a #GP fault will be generated on an attempt to use a code segment with these
bits set in IA-32e mode.
•
In IA-32e mode, the CS descriptor’s DPL is used for execution privilege checks (as in legacy 32-bit mode).
Code-Segment Descriptor
31
24 23 22 21 20 19
16 15 14 13 12 11
A
G D L V
L
D
P
L
P
8 7
0
Type
4
1 1 C R A
0
31
0
A
AVL
C
D
DPL
L
Accessed
Available to Sys. Programmer’s
Conforming
Default
Descriptor Privilege Level
64-Bit Flag
G
R
P
Granularity
Readable
Present
Figure 5-2. Descriptor Fields with Flags used in IA-32e Mode
5.3
LIMIT CHECKING
The limit field of a segment descriptor prevents programs or procedures from addressing memory locations outside
the segment. The effective value of the limit depends on the setting of the G (granularity) flag (see Figure 5-1). For
data segments, the limit also depends on the E (expansion direction) flag and the B (default stack pointer size
and/or upper bound) flag. The E flag is one of the bits in the type field when the segment descriptor is for a datasegment type.
When the G flag is clear (byte granularity), the effective limit is the value of the 20-bit limit field in the segment
descriptor. Here, the limit ranges from 0 to FFFFFH (1 MByte). When the G flag is set (4-KByte page granularity),
the processor scales the value in the limit field by a factor of 212 (4 KBytes). In this case, the effective limit ranges
from FFFH (4 KBytes) to FFFFFFFFH (4 GBytes). Note that when scaling is used (G flag is set), the lower 12 bits of
a segment offset (address) are not checked against the limit; for example, note that if the segment limit is 0,
offsets 0 through FFFH are still valid.
For all types of segments except expand-down data segments, the effective limit is the last address that is allowed
to be accessed in the segment, which is one less than the size, in bytes, of the segment. The processor causes a
general-protection exception (or, if the segment is SS, a stack-fault exception) any time an attempt is made to
access the following addresses in a segment:
•
•
•
•
A byte at an offset greater than the effective limit
A word at an offset greater than the (effective-limit – 1)
A doubleword at an offset greater than the (effective-limit – 3)
A quadword at an offset greater than the (effective-limit – 7)
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PROTECTION
•
A double quadword at an offset greater than the (effective limit – 15)
When the effective limit is FFFFFFFFH (4 GBytes), these accesses may or may not cause the indicated exceptions.
Behavior is implementation-specific and may vary from one execution to another.
For expand-down data segments, the segment limit has the same function but is interpreted differently. Here, the
effective limit specifies the last address that is not allowed to be accessed within the segment; the range of valid
offsets is from (effective-limit + 1) to FFFFFFFFH if the B flag is set and from (effective-limit + 1) to FFFFH if the B
flag is clear. An expand-down segment has maximum size when the segment limit is 0.
Limit checking catches programming errors such as runaway code, runaway subscripts, and invalid pointer calculations. These errors are detected when they occur, so identification of the cause is easier. Without limit checking,
these errors could overwrite code or data in another segment.
In addition to checking segment limits, the processor also checks descriptor table limits. The GDTR and IDTR registers contain 16-bit limit values that the processor uses to prevent programs from selecting a segment descriptors
outside the respective descriptor tables. The LDTR and task registers contain 32-bit segment limit value (read from
the segment descriptors for the current LDT and TSS, respectively). The processor uses these segment limits to
prevent accesses beyond the bounds of the current LDT and TSS. See Section 3.5.1, “Segment Descriptor Tables,”
for more information on the GDT and LDT limit fields; see Section 6.10, “Interrupt Descriptor Table (IDT),” for more
information on the IDT limit field; and see Section 7.2.4, “Task Register,” for more information on the TSS segment
limit field.
5.3.1
Limit Checking in 64-bit Mode
In 64-bit mode, the processor does not perform runtime limit checking on code or data segments. However, the
processor does check descriptor-table limits.
5.4
TYPE CHECKING
Segment descriptors contain type information in two places:
•
•
The S (descriptor type) flag.
The type field.
The processor uses this information to detect programming errors that result in an attempt to use a segment or
gate in an incorrect or unintended manner.
The S flag indicates whether a descriptor is a system type or a code or data type. The type field provides 4 additional bits for use in defining various types of code, data, and system descriptors. Table 3-1 shows the encoding of
the type field for code and data descriptors; Table 3-2 shows the encoding of the field for system descriptors.
The processor examines type information at various times while operating on segment selectors and segment
descriptors. The following list gives examples of typical operations where type checking is performed (this list is not
exhaustive):
•
When a segment selector is loaded into a segment register — Certain segment registers can contain only
certain descriptor types, for example:
— The CS register only can be loaded with a selector for a code segment.
— Segment selectors for code segments that are not readable or for system segments cannot be loaded into
data-segment registers (DS, ES, FS, and GS).
— Only segment selectors of writable data segments can be loaded into the SS register.
•
When a segment selector is loaded into the LDTR or task register — For example:
— The LDTR can only be loaded with a selector for an LDT.
— The task register can only be loaded with a segment selector for a TSS.
•
When instructions access segments whose descriptors are already loaded into segment registers —
Certain segments can be used by instructions only in certain predefined ways, for example:
— No instruction may write into an executable segment.
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— No instruction may write into a data segment if it is not writable.
— No instruction may read an executable segment unless the readable flag is set.
•
When an instruction operand contains a segment selector — Certain instructions can access segments
or gates of only a particular type, for example:
— A far CALL or far JMP instruction can only access a segment descriptor for a conforming code segment,
nonconforming code segment, call gate, task gate, or TSS.
— The LLDT instruction must reference a segment descriptor for an LDT.
— The LTR instruction must reference a segment descriptor for a TSS.
— The LAR instruction must reference a segment or gate descriptor for an LDT, TSS, call gate, task gate, code
segment, or data segment.
— The LSL instruction must reference a segment descriptor for a LDT, TSS, code segment, or data segment.
— IDT entries must be interrupt, trap, or task gates.
•
During certain internal operations — For example:
— On a far call or far jump (executed with a far CALL or far JMP instruction), the processor determines the
type of control transfer to be carried out (call or jump to another code segment, a call or jump through a
gate, or a task switch) by checking the type field in the segment (or gate) descriptor pointed to by the
segment (or gate) selector given as an operand in the CALL or JMP instruction. If the descriptor type is for
a code segment or call gate, a call or jump to another code segment is indicated; if the descriptor type is for
a TSS or task gate, a task switch is indicated.
— On a call or jump through a call gate (or on an interrupt- or exception-handler call through a trap or
interrupt gate), the processor automatically checks that the segment descriptor being pointed to by the
gate is for a code segment.
— On a call or jump to a new task through a task gate (or on an interrupt- or exception-handler call to a new
task through a task gate), the processor automatically checks that the segment descriptor being pointed to
by the task gate is for a TSS.
— On a call or jump to a new task by a direct reference to a TSS, the processor automatically checks that the
segment descriptor being pointed to by the CALL or JMP instruction is for a TSS.
— On return from a nested task (initiated by an IRET instruction), the processor checks that the previous task
link field in the current TSS points to a TSS.
5.4.1
Null Segment Selector Checking
Attempting to load a null segment selector (see Section 3.4.2, “Segment Selectors”) into the CS or SS segment
register generates a general-protection exception (#GP). A null segment selector can be loaded into the DS, ES,
FS, or GS register, but any attempt to access a segment through one of these registers when it is loaded with a null
segment selector results in a #GP exception being generated. Loading unused data-segment registers with a null
segment selector is a useful method of detecting accesses to unused segment registers and/or preventing
unwanted accesses to data segments.
5.4.1.1
NULL Segment Checking in 64-bit Mode
In 64-bit mode, the processor does not perform runtime checking on NULL segment selectors. The processor does
not cause a #GP fault when an attempt is made to access memory where the referenced segment register has a
NULL segment selector.
5.5
PRIVILEGE LEVELS
The processor’s segment-protection mechanism recognizes 4 privilege levels, numbered from 0 to 3. The greater
numbers mean lesser privileges. Figure 5-3 shows how these levels of privilege can be interpreted as rings of
protection.
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The center (reserved for the most privileged code, data, and stacks) is used for the segments containing the critical
software, usually the kernel of an operating system. Outer rings are used for less critical software. (Systems that
use only 2 of the 4 possible privilege levels should use levels 0 and 3.)
Protection Rings
Operating
System
Kernel
Level 0
Operating System
Services
Level 1
Level 2
Applications
Level 3
Figure 5-3. Protection Rings
The processor uses privilege levels to prevent a program or task operating at a lesser privilege level from accessing
a segment with a greater privilege, except under controlled situations. When the processor detects a privilege level
violation, it generates a general-protection exception (#GP).
To carry out privilege-level checks between code segments and data segments, the processor recognizes the
following three types of privilege levels:
•
Current privilege level (CPL) — The CPL is the privilege level of the currently executing program or task. It
is stored in bits 0 and 1 of the CS and SS segment registers. Normally, the CPL is equal to the privilege level of
the code segment from which instructions are being fetched. The processor changes the CPL when program
control is transferred to a code segment with a different privilege level. The CPL is treated slightly differently
when accessing conforming code segments. Conforming code segments can be accessed from any privilege
level that is equal to or numerically greater (less privileged) than the DPL of the conforming code segment.
Also, the CPL is not changed when the processor accesses a conforming code segment that has a different
privilege level than the CPL.
•
Descriptor privilege level (DPL) — The DPL is the privilege level of a segment or gate. It is stored in the DPL
field of the segment or gate descriptor for the segment or gate. When the currently executing code segment
attempts to access a segment or gate, the DPL of the segment or gate is compared to the CPL and RPL of the
segment or gate selector (as described later in this section). The DPL is interpreted differently, depending on
the type of segment or gate being accessed:
— Data segment — The DPL indicates the numerically highest privilege level that a program or task can have
to be allowed to access the segment. For example, if the DPL of a data segment is 1, only programs running
at a CPL of 0 or 1 can access the segment.
— Nonconforming code segment (without using a call gate) — The DPL indicates the privilege level that
a program or task must be at to access the segment. For example, if the DPL of a nonconforming code
segment is 0, only programs running at a CPL of 0 can access the segment.
— Call gate — The DPL indicates the numerically highest privilege level that the currently executing program
or task can be at and still be able to access the call gate. (This is the same access rule as for a data
segment.)
— Conforming code segment and nonconforming code segment accessed through a call gate — The
DPL indicates the numerically lowest privilege level that a program or task can have to be allowed to access
the segment. For example, if the DPL of a conforming code segment is 2, programs running at a CPL of 0 or
1 cannot access the segment.
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— TSS — The DPL indicates the numerically highest privilege level that the currently executing program or
task can be at and still be able to access the TSS. (This is the same access rule as for a data segment.)
•
Requested privilege level (RPL) — The RPL is an override privilege level that is assigned to segment
selectors. It is stored in bits 0 and 1 of the segment selector. The processor checks the RPL along with the CPL
to determine if access to a segment is allowed. Even if the program or task requesting access to a segment has
sufficient privilege to access the segment, access is denied if the RPL is not of sufficient privilege level. That is,
if the RPL of a segment selector is numerically greater than the CPL, the RPL overrides the CPL, and vice versa.
The RPL can be used to insure that privileged code does not access a segment on behalf of an application
program unless the program itself has access privileges for that segment. See Section 5.10.4, “Checking Caller
Access Privileges (ARPL Instruction),” for a detailed description of the purpose and typical use of the RPL.
Privilege levels are checked when the segment selector of a segment descriptor is loaded into a segment register.
The checks used for data access differ from those used for transfers of program control among code segments;
therefore, the two kinds of accesses are considered separately in the following sections.
5.6
PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS
To access operands in a data segment, the segment selector for the data segment must be loaded into the datasegment registers (DS, ES, FS, or GS) or into the stack-segment register (SS). (Segment registers can be loaded
with the MOV, POP, LDS, LES, LFS, LGS, and LSS instructions.) Before the processor loads a segment selector into
a segment register, it performs a privilege check (see Figure 5-4) by comparing the privilege levels of the currently
running program or task (the CPL), the RPL of the segment selector, and the DPL of the segment’s segment
descriptor. The processor loads the segment selector into the segment register if the DPL is numerically greater
than or equal to both the CPL and the RPL. Otherwise, a general-protection fault is generated and the segment
register is not loaded.
CS Register
CPL
Segment Selector
For Data Segment
RPL
Data-Segment Descriptor
Privilege
Check
DPL
Figure 5-4. Privilege Check for Data Access
Figure 5-5 shows four procedures (located in codes segments A, B, C, and D), each running at different privilege
levels and each attempting to access the same data segment.
1. The procedure in code segment A is able to access data segment E using segment selector E1, because the CPL
of code segment A and the RPL of segment selector E1 are equal to the DPL of data segment E.
2. The procedure in code segment B is able to access data segment E using segment selector E2, because the CPL
of code segment B and the RPL of segment selector E2 are both numerically lower than (more privileged) than
the DPL of data segment E. A code segment B procedure can also access data segment E using segment
selector E1.
3. The procedure in code segment C is not able to access data segment E using segment selector E3 (dotted line),
because the CPL of code segment C and the RPL of segment selector E3 are both numerically greater than (less
privileged) than the DPL of data segment E. Even if a code segment C procedure were to use segment selector
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E1 or E2, such that the RPL would be acceptable, it still could not access data segment E because its CPL is not
privileged enough.
4. The procedure in code segment D should be able to access data segment E because code segment D’s CPL is
numerically less than the DPL of data segment E. However, the RPL of segment selector E3 (which the code
segment D procedure is using to access data segment E) is numerically greater than the DPL of data segment
E, so access is not allowed. If the code segment D procedure were to use segment selector E1 or E2 to access
the data segment, access would be allowed.
3
2
1
0
Code
Segment C
CPL=3
Lowest Privilege
Segment Sel. E3
RPL=3
Code
Segment A
CPL=2
Segment Sel. E1
RPL=2
Code
Segment B
CPL=1
Segment Sel. E2
RPL=1
Data
Segment E
DPL=2
Highest Privilege
Code
Segment D
CPL=0
Figure 5-5. Examples of Accessing Data Segments From Various Privilege Levels
As demonstrated in the previous examples, the addressable domain of a program or task varies as its CPL changes.
When the CPL is 0, data segments at all privilege levels are accessible; when the CPL is 1, only data segments at
privilege levels 1 through 3 are accessible; when the CPL is 3, only data segments at privilege level 3 are accessible.
The RPL of a segment selector can always override the addressable domain of a program or task. When properly
used, RPLs can prevent problems caused by accidental (or intensional) use of segment selectors for privileged data
segments by less privileged programs or procedures.
It is important to note that the RPL of a segment selector for a data segment is under software control. For
example, an application program running at a CPL of 3 can set the RPL for a data- segment selector to 0. With the
RPL set to 0, only the CPL checks, not the RPL checks, will provide protection against deliberate, direct attempts to
violate privilege-level security for the data segment. To prevent these types of privilege-level-check violations, a
program or procedure can check access privileges whenever it receives a data-segment selector from another
procedure (see Section 5.10.4, “Checking Caller Access Privileges (ARPL Instruction)”).
5.6.1
Accessing Data in Code Segments
In some instances it may be desirable to access data structures that are contained in a code segment. The
following methods of accessing data in code segments are possible:
•
•
•
Load a data-segment register with a segment selector for a nonconforming, readable, code segment.
Load a data-segment register with a segment selector for a conforming, readable, code segment.
Use a code-segment override prefix (CS) to read a readable, code segment whose selector is already loaded in
the CS register.
The same rules for accessing data segments apply to method 1. Method 2 is always valid because the privilege
level of a conforming code segment is effectively the same as the CPL, regardless of its DPL. Method 3 is always
valid because the DPL of the code segment selected by the CS register is the same as the CPL.
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5.7
PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER
Privilege level checking also occurs when the SS register is loaded with the segment selector for a stack segment.
Here all privilege levels related to the stack segment must match the CPL; that is, the CPL, the RPL of the stacksegment selector, and the DPL of the stack-segment descriptor must be the same. If the RPL and DPL are not equal
to the CPL, a general-protection exception (#GP) is generated.
5.8
PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL
BETWEEN CODE SEGMENTS
To transfer program control from one code segment to another, the segment selector for the destination code
segment must be loaded into the code-segment register (CS). As part of this loading process, the processor examines the segment descriptor for the destination code segment and performs various limit, type, and privilege
checks. If these checks are successful, the CS register is loaded, program control is transferred to the new code
segment, and program execution begins at the instruction pointed to by the EIP register.
Program control transfers are carried out with the JMP, CALL, RET, SYSENTER, SYSEXIT, SYSCALL, SYSRET, INT n,
and IRET instructions, as well as by the exception and interrupt mechanisms. Exceptions, interrupts, and the IRET
instruction are special cases discussed in Chapter 6, “Interrupt and Exception Handling.” This chapter discusses
only the JMP, CALL, RET, SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions.
A JMP or CALL instruction can reference another code segment in any of four ways:
•
•
The target operand contains the segment selector for the target code segment.
•
•
The target operand points to a TSS, which contains the segment selector for the target code segment.
The target operand points to a call-gate descriptor, which contains the segment selector for the target code
segment.
The target operand points to a task gate, which points to a TSS, which in turn contains the segment selector for
the target code segment.
The following sections describe first two types of references. See Section 7.3, “Task Switching,” for information on
transferring program control through a task gate and/or TSS.
The SYSENTER and SYSEXIT instructions are special instructions for making fast calls to and returns from operating
system or executive procedures. These instructions are discussed in Section 5.8.7, “Performing Fast Calls to
System Procedures with the SYSENTER and SYSEXIT Instructions.”
The SYCALL and SYSRET instructions are special instructions for making fast calls to and returns from operating
system or executive procedures in 64-bit mode. These instructions are discussed in Section 5.8.8, “Fast System
Calls in 64-Bit Mode.”
5.8.1
Direct Calls or Jumps to Code Segments
The near forms of the JMP, CALL, and RET instructions transfer program control within the current code segment,
so privilege-level checks are not performed. The far forms of the JMP, CALL, and RET instructions transfer control
to other code segments, so the processor does perform privilege-level checks.
When transferring program control to another code segment without going through a call gate, the processor
examines four kinds of privilege level and type information (see Figure 5-6):
•
The CPL. (Here, the CPL is the privilege level of the calling code segment; that is, the code segment that
contains the procedure that is making the call or jump.)
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CS Register
CPL
Segment Selector
For Code Segment
RPL
Destination Code
Segment Descriptor
DPL
Privilege
Check
C
Figure 5-6. Privilege Check for Control Transfer Without Using a Gate
•
•
•
The DPL of the segment descriptor for the destination code segment that contains the called procedure.
The RPL of the segment selector of the destination code segment.
The conforming (C) flag in the segment descriptor for the destination code segment, which determines whether
the segment is a conforming (C flag is set) or nonconforming (C flag is clear) code segment. See Section
3.4.5.1, “Code- and Data-Segment Descriptor Types,” for more information about this flag.
The rules that the processor uses to check the CPL, RPL, and DPL depends on the setting of the C flag, as described
in the following sections.
5.8.1.1
Accessing Nonconforming Code Segments
When accessing nonconforming code segments, the CPL of the calling procedure must be equal to the DPL of the
destination code segment; otherwise, the processor generates a general-protection exception (#GP). For example
in Figure 5-7:
•
Code segment C is a nonconforming code segment. A procedure in code segment A can call a procedure in code
segment C (using segment selector C1) because they are at the same privilege level (CPL of code segment A is
equal to the DPL of code segment C).
•
A procedure in code segment B cannot call a procedure in code segment C (using segment selector C2 or C1)
because the two code segments are at different privilege levels.
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Code
Segment B
CPL=3
3
Segment Sel. D2
RPL=3
Segment Sel. C2
RPL=3
Lowest Privilege
Code
Segment A
CPL=2
2
Segment Sel. C1
RPL=2
Segment Sel. D1
RPL=2
Code
Segment C
DPL=2
Nonconforming
Code Segment
Code
Segment D
DPL=1
Conforming
Code Segment
1
0
Highest Privilege
Figure 5-7. Examples of Accessing Conforming and Nonconforming Code Segments From Various Privilege Levels
The RPL of the segment selector that points to a nonconforming code segment has a limited effect on the privilege
check. The RPL must be numerically less than or equal to the CPL of the calling procedure for a successful control
transfer to occur. So, in the example in Figure 5-7, the RPLs of segment selectors C1 and C2 could legally be set to
0, 1, or 2, but not to 3.
When the segment selector of a nonconforming code segment is loaded into the CS register, the privilege level field
is not changed; that is, it remains at the CPL (which is the privilege level of the calling procedure). This is true, even
if the RPL of the segment selector is different from the CPL.
5.8.1.2
Accessing Conforming Code Segments
When accessing conforming code segments, the CPL of the calling procedure may be numerically equal to or
greater than (less privileged) the DPL of the destination code segment; the processor generates a general-protection exception (#GP) only if the CPL is less than the DPL. (The segment selector RPL for the destination code
segment is not checked if the segment is a conforming code segment.)
In the example in Figure 5-7, code segment D is a conforming code segment. Therefore, calling procedures in both
code segment A and B can access code segment D (using either segment selector D1 or D2, respectively), because
they both have CPLs that are greater than or equal to the DPL of the conforming code segment. For conforming
code segments, the DPL represents the numerically lowest privilege level that a calling procedure may
be at to successfully make a call to the code segment.
(Note that segments selectors D1 and D2 are identical except for their respective RPLs. But since RPLs are not
checked when accessing conforming code segments, the two segment selectors are essentially interchangeable.)
When program control is transferred to a conforming code segment, the CPL does not change, even if the DPL of
the destination code segment is less than the CPL. This situation is the only one where the CPL may be different
from the DPL of the current code segment. Also, since the CPL does not change, no stack switch occurs.
Conforming segments are used for code modules such as math libraries and exception handlers, which support
applications but do not require access to protected system facilities. These modules are part of the operating
system or executive software, but they can be executed at numerically higher privilege levels (less privileged
levels). Keeping the CPL at the level of a calling code segment when switching to a conforming code segment
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prevents an application program from accessing nonconforming code segments while at the privilege level (DPL) of
a conforming code segment and thus prevents it from accessing more privileged data.
Most code segments are nonconforming. For these segments, program control can be transferred only to code
segments at the same level of privilege, unless the transfer is carried out through a call gate, as described in the
following sections.
5.8.2
Gate Descriptors
To provide controlled access to code segments with different privilege levels, the processor provides special set of
descriptors called gate descriptors. There are four kinds of gate descriptors:
•
•
•
•
Call gates
Trap gates
Interrupt gates
Task gates
Task gates are used for task switching and are discussed in Chapter 7, “Task Management”. Trap and interrupt
gates are special kinds of call gates used for calling exception and interrupt handlers. The are described in Chapter
6, “Interrupt and Exception Handling.” This chapter is concerned only with call gates.
5.8.3
Call Gates
Call gates facilitate controlled transfers of program control between different privilege levels. They are typically
used only in operating systems or executives that use the privilege-level protection mechanism. Call gates are also
useful for transferring program control between 16-bit and 32-bit code segments, as described in Section 21.4,
“Transferring Control Among Mixed-Size Code Segments.”
Figure 5-8 shows the format of a call-gate descriptor. A call-gate descriptor may reside in the GDT or in an LDT, but
not in the interrupt descriptor table (IDT). It performs six functions:
•
•
•
It specifies the code segment to be accessed.
It defines an entry point for a procedure in the specified code segment.
It specifies the privilege level required for a caller trying to access the procedure.
31
16 15 14 13 12 11
Offset in Segment 31:16
31
P
D
P
L
6
8 7
Type
0 0 0
0 1 1 0 0
16 15
Segment Selector
0
5 4
Param.
Count
4
0
Offset in Segment 15:00
0
DPL Descriptor Privilege Level
P
Gate Valid
Figure 5-8. Call-Gate Descriptor
•
•
If a stack switch occurs, it specifies the number of optional parameters to be copied between stacks.
•
It specifies whether the call-gate descriptor is valid.
It defines the size of values to be pushed onto the target stack: 16-bit gates force 16-bit pushes and 32-bit
gates force 32-bit pushes.
The segment selector field in a call gate specifies the code segment to be accessed. The offset field specifies the
entry point in the code segment. This entry point is generally to the first instruction of a specific procedure. The
DPL field indicates the privilege level of the call gate, which in turn is the privilege level required to access the
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selected procedure through the gate. The P flag indicates whether the call-gate descriptor is valid. (The presence
of the code segment to which the gate points is indicated by the P flag in the code segment’s descriptor.) The
parameter count field indicates the number of parameters to copy from the calling procedures stack to the new
stack if a stack switch occurs (see Section 5.8.5, “Stack Switching”). The parameter count specifies the number of
words for 16-bit call gates and doublewords for 32-bit call gates.
Note that the P flag in a gate descriptor is normally always set to 1. If it is set to 0, a not present (#NP) exception
is generated when a program attempts to access the descriptor. The operating system can use the P flag for special
purposes. For example, it could be used to track the number of times the gate is used. Here, the P flag is initially
set to 0 causing a trap to the not-present exception handler. The exception handler then increments a counter and
sets the P flag to 1, so that on returning from the handler, the gate descriptor will be valid.
5.8.3.1
IA-32e Mode Call Gates
Call-gate descriptors in 32-bit mode provide a 32-bit offset for the instruction pointer (EIP); 64-bit extensions
double the size of 32-bit mode call gates in order to store 64-bit instruction pointers (RIP). See Figure 5-9:
•
The first eight bytes (bytes 7:0) of a 64-bit mode call gate are similar but not identical to legacy 32-bit mode
call gates. The parameter-copy-count field has been removed.
•
Bytes 11:8 hold the upper 32 bits of the target-segment offset in canonical form. A general-protection
exception (#GP) is generated if software attempts to use a call gate with a target offset that is not in canonical
form.
•
16-byte descriptors may reside in the same descriptor table with 16-bit and 32-bit descriptors. A type field,
used for consistency checking, is defined in bits 12:8 of the 64-bit descriptor’s highest dword (cleared to zero).
A general-protection exception (#GP) results if an attempt is made to access the upper half of a 64-bit mode
descriptor as a 32-bit mode descriptor.
13 12 11 10 9 8 7
31
Type
Reserved
0
Reserved
12
0 0 0 0 0
31
0
8
Offset in Segment 63:31
31
Offset in Segment 31:16
31
P
D
P
L
0
8 7
16 15 14 13 12 11
Type
0
16 15
Segment Selector
.
4
0 1 1 0 0
0
Offset in Segment 15:00
0
DPL Descriptor Privilege Level
P
Gate Valid
Figure 5-9. Call-Gate Descriptor in IA-32e Mode
•
Target code segments referenced by a 64-bit call gate must be 64-bit code segments (CS.L = 1, CS.D = 0). If
not, the reference generates a general-protection exception, #GP (CS selector).
•
Only 64-bit mode call gates can be referenced in IA-32e mode (64-bit mode and compatibility mode). The
legacy 32-bit mode call gate type (0CH) is redefined in IA-32e mode as a 64-bit call-gate type; no 32-bit callgate type exists in IA-32e mode.
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•
If a far call references a 16-bit call gate type (04H) in IA-32e mode, a general-protection exception (#GP) is
generated.
When a call references a 64-bit mode call gate, actions taken are identical to those taken in 32-bit mode, with the
following exceptions:
•
•
•
Stack pushes are made in eight-byte increments.
A 64-bit RIP is pushed onto the stack.
Parameter copying is not performed.
Use a matching far-return instruction size for correct operation (returns from 64-bit calls must be performed with
a 64-bit operand-size return to process the stack correctly).
5.8.4
Accessing a Code Segment Through a Call Gate
To access a call gate, a far pointer to the gate is provided as a target operand in a CALL or JMP instruction. The
segment selector from this pointer identifies the call gate (see Figure 5-10); the offset from the pointer is required,
but not used or checked by the processor. (The offset can be set to any value.)
When the processor has accessed the call gate, it uses the segment selector from the call gate to locate the
segment descriptor for the destination code segment. (This segment descriptor can be in the GDT or the LDT.) It
then combines the base address from the code-segment descriptor with the offset from the call gate to form the
linear address of the procedure entry point in the code segment.
As shown in Figure 5-11, four different privilege levels are used to check the validity of a program control transfer
through a call gate:
•
•
•
•
The CPL (current privilege level).
The RPL (requestor's privilege level) of the call gate’s selector.
The DPL (descriptor privilege level) of the call gate descriptor.
The DPL of the segment descriptor of the destination code segment.
The C flag (conforming) in the segment descriptor for the destination code segment is also checked.
Far Pointer to Call Gate
Segment Selector
Offset
Required but not used by processor
Descriptor Table
Offset
Segment Selector
+
Base
Offset
Base
Base
Call-Gate
Descriptor
Code-Segment
Descriptor
Procedure
Entry Point
Figure 5-10. Call-Gate Mechanism
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PROTECTION
CS Register
CPL
Call-Gate Selector
RPL
Call Gate (Descriptor)
DPL
Privilege
Check
Destination CodeSegment Descriptor
DPL
Figure 5-11. Privilege Check for Control Transfer with Call Gate
The privilege checking rules are different depending on whether the control transfer was initiated with a CALL or a
JMP instruction, as shown in Table 5-1.
Table 5-1. Privilege Check Rules for Call Gates
Instruction
Privilege Check Rules
CALL
CPL ≤ call gate DPL; RPL ≤ call gate DPL
Destination conforming code segment DPL ≤ CPL
Destination nonconforming code segment DPL ≤ CPL
JMP
CPL ≤ call gate DPL; RPL ≤ call gate DPL
Destination conforming code segment DPL ≤ CPL
Destination nonconforming code segment DPL = CPL
The DPL field of the call-gate descriptor specifies the numerically highest privilege level from which a calling procedure can access the call gate; that is, to access a call gate, the CPL of a calling procedure must be equal to or less
than the DPL of the call gate. For example, in Figure 5-15, call gate A has a DPL of 3. So calling procedures at all
CPLs (0 through 3) can access this call gate, which includes calling procedures in code segments A, B, and C. Call
gate B has a DPL of 2, so only calling procedures at a CPL or 0, 1, or 2 can access call gate B, which includes calling
procedures in code segments B and C. The dotted line shows that a calling procedure in code segment A cannot
access call gate B.
The RPL of the segment selector to a call gate must satisfy the same test as the CPL of the calling procedure; that
is, the RPL must be less than or equal to the DPL of the call gate. In the example in Figure 5-15, a calling procedure
in code segment C can access call gate B using gate selector B2 or B1, but it could not use gate selector B3 to
access call gate B.
If the privilege checks between the calling procedure and call gate are successful, the processor then checks the
DPL of the code-segment descriptor against the CPL of the calling procedure. Here, the privilege check rules vary
between CALL and JMP instructions. Only CALL instructions can use call gates to transfer program control to more
privileged (numerically lower privilege level) nonconforming code segments; that is, to nonconforming code
segments with a DPL less than the CPL. A JMP instruction can use a call gate only to transfer program control to a
nonconforming code segment with a DPL equal to the CPL. CALL and JMP instruction can both transfer program
control to a more privileged conforming code segment; that is, to a conforming code segment with a DPL less than
or equal to the CPL.
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If a call is made to a more privileged (numerically lower privilege level) nonconforming destination code segment,
the CPL is lowered to the DPL of the destination code segment and a stack switch occurs (see Section 5.8.5, “Stack
Switching”). If a call or jump is made to a more privileged conforming destination code segment, the CPL is not
changed and no stack switch occurs.
3
Code
Segment A
Gate Selector A
RPL=3
CPL=3
Gate Selector B3
RPL=3
Call
Gate A
DPL=3
Lowest Privilege
Code
Segment B
CPL=2
Gate Selector B1
RPL=2
Call
Gate B
DPL=2
2
Code
Segment C
CPL=1
Gate Selector B2
RPL=1
No Stack
Switch Occurs
1
Stack Switch
Occurs
Code
Segment D
DPL=0
0
Highest Privilege
Conforming
Code Segment
Code
Segment E
DPL=0
Nonconforming
Code Segment
Figure 5-12. Example of Accessing Call Gates At Various Privilege Levels
Call gates allow a single code segment to have procedures that can be accessed at different privilege levels. For
example, an operating system located in a code segment may have some services which are intended to be used
by both the operating system and application software (such as procedures for handling character I/O). Call gates
for these procedures can be set up that allow access at all privilege levels (0 through 3). More privileged call gates
(with DPLs of 0 or 1) can then be set up for other operating system services that are intended to be used only by
the operating system (such as procedures that initialize device drivers).
5.8.5
Stack Switching
Whenever a call gate is used to transfer program control to a more privileged nonconforming code segment (that
is, when the DPL of the nonconforming destination code segment is less than the CPL), the processor automatically
switches to the stack for the destination code segment’s privilege level. This stack switching is carried out to
prevent more privileged procedures from crashing due to insufficient stack space. It also prevents less privileged
procedures from interfering (by accident or intent) with more privileged procedures through a shared stack.
Each task must define up to 4 stacks: one for applications code (running at privilege level 3) and one for each of
the privilege levels 2, 1, and 0 that are used. (If only two privilege levels are used [3 and 0], then only two stacks
must be defined.) Each of these stacks is located in a separate segment and is identified with a segment selector
and an offset into the stack segment (a stack pointer).
The segment selector and stack pointer for the privilege level 3 stack is located in the SS and ESP registers, respectively, when privilege-level-3 code is being executed and is automatically stored on the called procedure’s stack
when a stack switch occurs.
Pointers to the privilege level 0, 1, and 2 stacks are stored in the TSS for the currently running task (see
Figure 7-2). Each of these pointers consists of a segment selector and a stack pointer (loaded into the ESP
register). These initial pointers are strictly read-only values. The processor does not change them while the task is
running. They are used only to create new stacks when calls are made to more privileged levels (numerically lower
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privilege levels). These stacks are disposed of when a return is made from the called procedure. The next time the
procedure is called, a new stack is created using the initial stack pointer. (The TSS does not specify a stack for privilege level 3 because the processor does not allow a transfer of program control from a procedure running at a CPL
of 0, 1, or 2 to a procedure running at a CPL of 3, except on a return.)
The operating system is responsible for creating stacks and stack-segment descriptors for all the privilege levels to
be used and for loading initial pointers for these stacks into the TSS. Each stack must be read/write accessible (as
specified in the type field of its segment descriptor) and must contain enough space (as specified in the limit field)
to hold the following items:
•
•
•
The contents of the SS, ESP, CS, and EIP registers for the calling procedure.
The parameters and temporary variables required by the called procedure.
The EFLAGS register and error code, when implicit calls are made to an exception or interrupt handler.
The stack will need to require enough space to contain many frames of these items, because procedures often call
other procedures, and an operating system may support nesting of multiple interrupts. Each stack should be large
enough to allow for the worst case nesting scenario at its privilege level.
(If the operating system does not use the processor’s multitasking mechanism, it still must create at least one TSS
for this stack-related purpose.)
When a procedure call through a call gate results in a change in privilege level, the processor performs the
following steps to switch stacks and begin execution of the called procedure at a new privilege level:
1. Uses the DPL of the destination code segment (the new CPL) to select a pointer to the new stack (segment
selector and stack pointer) from the TSS.
2. Reads the segment selector and stack pointer for the stack to be switched to from the current TSS. Any limit
violations detected while reading the stack-segment selector, stack pointer, or stack-segment descriptor cause
an invalid TSS (#TS) exception to be generated.
3. Checks the stack-segment descriptor for the proper privileges and type and generates an invalid TSS (#TS)
exception if violations are detected.
4. Temporarily saves the current values of the SS and ESP registers.
5. Loads the segment selector and stack pointer for the new stack in the SS and ESP registers.
6. Pushes the temporarily saved values for the SS and ESP registers (for the calling procedure) onto the new stack
(see Figure 5-13).
7. Copies the number of parameter specified in the parameter count field of the call gate from the calling
procedure’s stack to the new stack. If the count is 0, no parameters are copied.
8. Pushes the return instruction pointer (the current contents of the CS and EIP registers) onto the new stack.
9. Loads the segment selector for the new code segment and the new instruction pointer from the call gate into
the CS and EIP registers, respectively, and begins execution of the called procedure.
See the description of the CALL instruction in Chapter 3, Instruction Set Reference, in the IA-32 Intel Architecture
Software Developer’s Manual, Volume 2, for a detailed description of the privilege level checks and other protection
checks that the processor performs on a far call through a call gate.
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Called Procedure’s Stack
Calling Procedure’s Stack
Calling SS
Parameter 1
Calling ESP
Parameter 2
Parameter 1
Parameter 3
ESP
Parameter 2
Parameter 3
Calling CS
Calling EIP
ESP
Figure 5-13. Stack Switching During an Interprivilege-Level Call
The parameter count field in a call gate specifies the number of data items (up to 31) that the processor should
copy from the calling procedure’s stack to the stack of the called procedure. If more than 31 data items need to be
passed to the called procedure, one of the parameters can be a pointer to a data structure, or the saved contents
of the SS and ESP registers may be used to access parameters in the old stack space. The size of the data items
passed to the called procedure depends on the call gate size, as described in Section 5.8.3, “Call Gates.”
5.8.5.1
Stack Switching in 64-bit Mode
Although protection-check rules for call gates are unchanged from 32-bit mode, stack-switch changes in 64-bit
mode are different.
When stacks are switched as part of a 64-bit mode privilege-level change through a call gate, a new SS (stack
segment) descriptor is not loaded; 64-bit mode only loads an inner-level RSP from the TSS. The new SS is forced
to NULL and the SS selector’s RPL field is forced to the new CPL. The new SS is set to NULL in order to handle
nested far transfers (far CALL, INTn, interrupts and exceptions). The old SS and RSP are saved on the new stack.
On a subsequent far RET, the old SS is popped from the stack and loaded into the SS register. See Table 5-2.
Table 5-2. 64-Bit-Mode Stack Layout After Far CALL with CPL Change
32-bit Mode
IA-32e mode
Old SS Selector
+12
+24
Old SS Selector
Old ESP
+8
+16
Old RSP
CS Selector
+4
+8
Old CS Selector
EIP
0
0
RIP
< 4 Bytes >
ESP
RSP
< 8 Bytes >
In 64-bit mode, stack operations resulting from a privilege-level-changing far call or far return are eight-bytes wide
and change the RSP by eight. The mode does not support the automatic parameter-copy feature found in 32-bit
mode. The call-gate count field is ignored. Software can access the old stack, if necessary, by referencing the old
stack-segment selector and stack pointer saved on the new process stack.
In 64-bit mode, far RET is allowed to load a NULL SS under certain conditions. If the target mode is 64-bit mode
and the target CPL ≠ 3, IRET allows SS to be loaded with a NULL selector. If the called procedure itself is interrupted, the NULL SS is pushed on the stack frame. On the subsequent far RET, the NULL SS on the stack acts as a
flag to tell the processor not to load a new SS descriptor.
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5.8.6
Returning from a Called Procedure
The RET instruction can be used to perform a near return, a far return at the same privilege level, and a far return
to a different privilege level. This instruction is intended to execute returns from procedures that were called with
a CALL instruction. It does not support returns from a JMP instruction, because the JMP instruction does not save a
return instruction pointer on the stack.
A near return only transfers program control within the current code segment; therefore, the processor performs
only a limit check. When the processor pops the return instruction pointer from the stack into the EIP register, it
checks that the pointer does not exceed the limit of the current code segment.
On a far return at the same privilege level, the processor pops both a segment selector for the code segment being
returned to and a return instruction pointer from the stack. Under normal conditions, these pointers should be
valid, because they were pushed on the stack by the CALL instruction. However, the processor performs privilege
checks to detect situations where the current procedure might have altered the pointer or failed to maintain the
stack properly.
A far return that requires a privilege-level change is only allowed when returning to a less privileged level (that is,
the DPL of the return code segment is numerically greater than the CPL). The processor uses the RPL field from the
CS register value saved for the calling procedure (see Figure 5-13) to determine if a return to a numerically higher
privilege level is required. If the RPL is numerically greater (less privileged) than the CPL, a return across privilege
levels occurs.
The processor performs the following steps when performing a far return to a calling procedure (see Figures 6-2
and 6-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of the
stack contents prior to and after a return):
1. Checks the RPL field of the saved CS register value to determine if a privilege level change is required on the
return.
2. Loads the CS and EIP registers with the values on the called procedure’s stack. (Type and privilege level checks
are performed on the code-segment descriptor and RPL of the code- segment selector.)
3. (If the RET instruction includes a parameter count operand and the return requires a privilege level change.)
Adds the parameter count (in bytes obtained from the RET instruction) to the current ESP register value (after
popping the CS and EIP values), to step past the parameters on the called procedure’s stack. The resulting
value in the ESP register points to the saved SS and ESP values for the calling procedure’s stack. (Note that the
byte count in the RET instruction must be chosen to match the parameter count in the call gate that the calling
procedure referenced when it made the original call multiplied by the size of the parameters.)
4. (If the return requires a privilege level change.) Loads the SS and ESP registers with the saved SS and ESP
values and switches back to the calling procedure’s stack. The SS and ESP values for the called procedure’s
stack are discarded. Any limit violations detected while loading the stack-segment selector or stack pointer
cause a general-protection exception (#GP) to be generated. The new stack-segment descriptor is also
checked for type and privilege violations.
5. (If the RET instruction includes a parameter count operand.) Adds the parameter count (in bytes obtained from
the RET instruction) to the current ESP register value, to step past the parameters on the calling procedure’s
stack. The resulting ESP value is not checked against the limit of the stack segment. If the ESP value is beyond
the limit, that fact is not recognized until the next stack operation.
6. (If the return requires a privilege level change.) Checks the contents of the DS, ES, FS, and GS segment
registers. If any of these registers refer to segments whose DPL is less than the new CPL (excluding conforming
code segments), the segment register is loaded with a null segment selector.
See the description of the RET instruction in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for a detailed description of the privilege level checks and other protection checks that
the processor performs on a far return.
5.8.7
Performing Fast Calls to System Procedures with the
SYSENTER and SYSEXIT Instructions
The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processors
for the purpose of providing a fast (low overhead) mechanism for calling operating system or executive procedures.
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SYSENTER is intended for use by user code running at privilege level 3 to access operating system or executive
procedures running at privilege level 0. SYSEXIT is intended for use by privilege level 0 operating system or executive procedures for fast returns to privilege level 3 user code. SYSENTER can be executed from privilege levels 3,
2, 1, or 0; SYSEXIT can only be executed from privilege level 0.
The SYSENTER and SYSEXIT instructions are companion instructions, but they do not constitute a call/return pair.
This is because SYSENTER does not save any state information for use by SYSEXIT on a return.
The target instruction and stack pointer for these instructions are not specified through instruction operands.
Instead, they are specified through parameters entered in MSRs and general-purpose registers.
For SYSENTER, target fields are generated using the following sources:
•
•
•
•
Target code segment — Reads this from IA32_SYSENTER_CS.
Target instruction — Reads this from IA32_SYSENTER_EIP.
Stack segment — Computed by adding 8 to the value in IA32_SYSENTER_CS.
Stack pointer — Reads this from the IA32_SYSENTER_ESP.
For SYSEXIT, target fields are generated using the following sources:
•
•
•
•
Target code segment — Computed by adding 16 to the value in the IA32_SYSENTER_CS.
Target instruction — Reads this from EDX.
Stack segment — Computed by adding 24 to the value in IA32_SYSENTER_CS.
Stack pointer — Reads this from ECX.
The SYSENTER and SYSEXIT instructions preform “fast” calls and returns because they force the processor into a
predefined privilege level 0 state when SYSENTER is executed and into a predefined privilege level 3 state when
SYSEXIT is executed. By forcing predefined and consistent processor states, the number of privilege checks ordinarily required to perform a far call to another privilege levels are greatly reduced. Also, by predefining the target
context state in MSRs and general-purpose registers eliminates all memory accesses except when fetching the
target code.
Any additional state that needs to be saved to allow a return to the calling procedure must be saved explicitly by
the calling procedure or be predefined through programming conventions.
5.8.7.1
SYSENTER and SYSEXIT Instructions in IA-32e Mode
For Intel 64 processors, the SYSENTER and SYSEXIT instructions are enhanced to allow fast system calls from user
code running at privilege level 3 (in compatibility mode or 64-bit mode) to 64-bit executive procedures running at
privilege level 0. IA32_SYSENTER_EIP MSR and IA32_SYSENTER_ESP MSR are expanded to hold 64-bit addresses.
If IA-32e mode is inactive, only the lower 32-bit addresses stored in these MSRs are used. The WRMSR instruction
ensures that the addresses stored in these MSRs are canonical. Note that, in 64-bit mode, IA32_SYSENTER_CS
must not contain a NULL selector.
When SYSENTER transfers control, the following fields are generated and bits set:
•
•
•
•
•
•
Target code segment — Reads non-NULL selector from IA32_SYSENTER_CS.
New CS attributes — CS base = 0, CS limit = FFFFFFFFH.
Target instruction — Reads 64-bit canonical address from IA32_SYSENTER_EIP.
Stack segment — Computed by adding 8 to the value from IA32_SYSENTER_CS.
Stack pointer — Reads 64-bit canonical address from IA32_SYSENTER_ESP.
New SS attributes — SS base = 0, SS limit = FFFFFFFFH.
When the SYSEXIT instruction transfers control to 64-bit mode user code using REX.W, the following fields are
generated and bits set:
•
•
•
•
Target code segment — Computed by adding 32 to the value in IA32_SYSENTER_CS.
New CS attributes — L-bit = 1 (go to 64-bit mode).
Target instruction — Reads 64-bit canonical address in RDX.
Stack segment — Computed by adding 40 to the value of IA32_SYSENTER_CS.
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PROTECTION
•
Stack pointer — Update RSP using 64-bit canonical address in RCX.
When SYSEXIT transfers control to compatibility mode user code when the operand size attribute is 32 bits, the
following fields are generated and bits set:
•
•
•
•
•
Target code segment — Computed by adding 16 to the value in IA32_SYSENTER_CS.
New CS attributes — L-bit = 0 (go to compatibility mode).
Target instruction — Fetch the target instruction from 32-bit address in EDX.
Stack segment — Computed by adding 24 to the value in IA32_SYSENTER_CS.
Stack pointer — Update ESP from 32-bit address in ECX.
5.8.8
Fast System Calls in 64-Bit Mode
The SYSCALL and SYSRET instructions are designed for operating systems that use a flat memory model (segmentation is not used). The instructions, along with SYSENTER and SYSEXIT, are suited for IA-32e mode operation.
SYSCALL and SYSRET, however, are not supported in compatibility mode (or in protected mode). Use CPUID to
check if SYSCALL and SYSRET are available (CPUID.80000001H.EDX[bit 11] = 1).
SYSCALL is intended for use by user code running at privilege level 3 to access operating system or executive
procedures running at privilege level 0. SYSRET is intended for use by privilege level 0 operating system or executive procedures for fast returns to privilege level 3 user code.
Stack pointers for SYSCALL/SYSRET are not specified through model specific registers. The clearing of bits in
RFLAGS is programmable rather than fixed. SYSCALL/SYSRET save and restore the RFLAGS register.
For SYSCALL, the processor saves RFLAGS into R11 and the RIP of the next instruction into RCX; it then gets the
privilege-level 0 target code segment, instruction pointer, stack segment, and flags as follows:
•
•
Target code segment — Reads a non-NULL selector from IA32_STAR[47:32].
•
•
Stack segment — Computed by adding 8 to the value in IA32_STAR[47:32].
Target instruction pointer — Reads a 64-bit address from IA32_LSTAR. (The WRMSR instruction ensures
that the value of the IA32_LSTAR MSR is canonical.)
Flags — The processor sets RFLAGS to the logical-AND of its current value with the complement of the value in
the IA32_FMASK MSR.
When SYSRET transfers control to 64-bit mode user code using REX.W, the processor gets the privilege level 3
target code segment, instruction pointer, stack segment, and flags as follows:
•
•
•
•
Target code segment — Reads a non-NULL selector from IA32_STAR[63:48] + 16.
Target instruction pointer — Copies the value in RCX into RIP.
Stack segment — IA32_STAR[63:48] + 8.
EFLAGS — Loaded from R11.
When SYSRET transfers control to 32-bit mode user code using a 32-bit operand size, the processor gets the privilege level 3 target code segment, instruction pointer, stack segment, and flags as follows:
•
•
•
•
Target code segment — Reads a non-NULL selector from IA32_STAR[63:48].
Target instruction pointer — Copies the value in ECX into EIP.
Stack segment — IA32_STAR[63:48] + 8.
EFLAGS — Loaded from R11.
It is the responsibility of the OS to ensure the descriptors in the GDT/LDT correspond to the selectors loaded by
SYSCALL/SYSRET (consistent with the base, limit, and attribute values forced by the instructions).
See Figure 5-14 for the layout of IA32_STAR, IA32_LSTAR and IA32_FMASK.
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63
0
32 31
SYSCALL EFLAGS Mask
Reserved
IA32_FMASK
63
0
Target RIP for 64-bit Mode Calling Program
IA32_LSTAR
63
32 31
48 47
SYSRET CS and SS
SYSCALL CS and SS
0
Reserved
IA32_STAR
Figure 5-14. MSRs Used by SYSCALL and SYSRET
The SYSCALL instruction does not save the stack pointer, and the SYSRET instruction does not restore it. It is likely
that the OS system-call handler will change the stack pointer from the user stack to the OS stack. If so, it is the
responsibility of software first to save the user stack pointer. This might be done by user code, prior to executing
SYSCALL, or by the OS system-call handler after SYSCALL.
Because the SYSRET instruction does not modify the stack pointer, it is necessary for software to switch back to the
user stack. The OS may load the user stack pointer (if it was saved after SYSCALL) before executing SYSRET; alternatively, user code may load the stack pointer (if it was saved before SYSCALL) after receiving control from
SYSRET.
If the OS loads the stack pointer before executing SYSRET, it must ensure that the handler of any interrupt or
exception delivered between restoring the stack pointer and successful execution of SYSRET is not invoked with the
user stack. It can do so using approaches such as the following:
•
External interrupts. The OS can prevent an external interrupt from being delivered by clearing EFLAGS.IF
before loading the user stack pointer.
•
Nonmaskable interrupts (NMIs). The OS can ensure that the NMI handler is invoked with the correct stack by
using the interrupt stack table (IST) mechanism for gate 2 (NMI) in the IDT (see Section 6.14.5, “Interrupt
Stack Table”).
•
General-protection exceptions (#GP). The SYSRET instruction generates #GP(0) if the value of RCX is not
canonical. The OS can address this possibility using one or more of the following approaches:
— Confirming that the value of RCX is canonical before executing SYSRET.
— Using paging to ensure that the SYSCALL instruction will never save a non-canonical value into RCX.
— Using the IST mechanism for gate 13 (#GP) in the IDT.
5.9
PRIVILEGED INSTRUCTIONS
Some of the system instructions (called “privileged instructions”) are protected from use by application programs.
The privileged instructions control system functions (such as the loading of system registers). They can be
executed only when the CPL is 0 (most privileged). If one of these instructions is executed when the CPL is not 0,
a general-protection exception (#GP) is generated. The following system instructions are privileged instructions:
•
•
LGDT — Load GDT register.
LLDT — Load LDT register.
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PROTECTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LTR — Load task register.
LIDT — Load IDT register.
MOV (control registers) — Load and store control registers.
LMSW — Load machine status word.
CLTS — Clear task-switched flag in register CR0.
MOV (debug registers) — Load and store debug registers.
INVD — Invalidate cache, without writeback.
WBINVD — Invalidate cache, with writeback.
INVLPG —Invalidate TLB entry.
HLT— Halt processor.
RDMSR — Read Model-Specific Registers.
WRMSR —Write Model-Specific Registers.
RDPMC — Read Performance-Monitoring Counter.
RDTSC — Read Time-Stamp Counter.
Some of the privileged instructions are available only in the more recent families of Intel 64 and IA-32 processors
(see Section 22.13, “New Instructions In the Pentium and Later IA-32 Processors”).
The PCE and TSD flags in register CR4 (bits 4 and 2, respectively) enable the RDPMC and RDTSC instructions,
respectively, to be executed at any CPL.
5.10
POINTER VALIDATION
When operating in protected mode, the processor validates all pointers to enforce protection between segments
and maintain isolation between privilege levels. Pointer validation consists of the following checks:
1. Checking access rights to determine if the segment type is compatible with its use.
2. Checking read/write rights.
3. Checking if the pointer offset exceeds the segment limit.
4. Checking if the supplier of the pointer is allowed to access the segment.
5. Checking the offset alignment.
The processor automatically performs first, second, and third checks during instruction execution. Software must
explicitly request the fourth check by issuing an ARPL instruction. The fifth check (offset alignment) is performed
automatically at privilege level 3 if alignment checking is turned on. Offset alignment does not affect isolation of
privilege levels.
5.10.1
Checking Access Rights (LAR Instruction)
When the processor accesses a segment using a far pointer, it performs an access rights check on the segment
descriptor pointed to by the far pointer. This check is performed to determine if type and privilege level (DPL) of the
segment descriptor are compatible with the operation to be performed. For example, when making a far call in
protected mode, the segment-descriptor type must be for a conforming or nonconforming code segment, a call
gate, a task gate, or a TSS. Then, if the call is to a nonconforming code segment, the DPL of the code segment must
be equal to the CPL, and the RPL of the code segment’s segment selector must be less than or equal to the DPL. If
type or privilege level are found to be incompatible, the appropriate exception is generated.
To prevent type incompatibility exceptions from being generated, software can check the access rights of a
segment descriptor using the LAR (load access rights) instruction. The LAR instruction specifies the segment
selector for the segment descriptor whose access rights are to be checked and a destination register. The instruction then performs the following operations:
1. Check that the segment selector is not null.
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2. Checks that the segment selector points to a segment descriptor that is within the descriptor table limit (GDT
or LDT).
3. Checks that the segment descriptor is a code, data, LDT, call gate, task gate, or TSS segment-descriptor type.
4. If the segment is not a conforming code segment, checks if the segment descriptor is visible at the CPL (that
is, if the CPL and the RPL of the segment selector are less than or equal to the DPL).
5. If the privilege level and type checks pass, loads the second doubleword of the segment descriptor into the
destination register (masked by the value 00FXFF00H, where X indicates that the corresponding 4 bits are
undefined) and sets the ZF flag in the EFLAGS register. If the segment selector is not visible at the current
privilege level or is an invalid type for the LAR instruction, the instruction does not modify the destination
register and clears the ZF flag.
Once loaded in the destination register, software can preform additional checks on the access rights information.
5.10.2
Checking Read/Write Rights (VERR and VERW Instructions)
When the processor accesses any code or data segment it checks the read/write privileges assigned to the
segment to verify that the intended read or write operation is allowed. Software can check read/write rights using
the VERR (verify for reading) and VERW (verify for writing) instructions. Both these instructions specify the
segment selector for the segment being checked. The instructions then perform the following operations:
1. Check that the segment selector is not null.
2. Checks that the segment selector points to a segment descriptor that is within the descriptor table limit (GDT
or LDT).
3. Checks that the segment descriptor is a code or data-segment descriptor type.
4. If the segment is not a conforming code segment, checks if the segment descriptor is visible at the CPL (that
is, if the CPL and the RPL of the segment selector are less than or equal to the DPL).
5. Checks that the segment is readable (for the VERR instruction) or writable (for the VERW) instruction.
The VERR instruction sets the ZF flag in the EFLAGS register if the segment is visible at the CPL and readable; the
VERW sets the ZF flag if the segment is visible and writable. (Code segments are never writable.) The ZF flag is
cleared if any of these checks fail.
5.10.3
Checking That the Pointer Offset Is Within Limits (LSL Instruction)
When the processor accesses any segment it performs a limit check to insure that the offset is within the limit of
the segment. Software can perform this limit check using the LSL (load segment limit) instruction. Like the LAR
instruction, the LSL instruction specifies the segment selector for the segment descriptor whose limit is to be
checked and a destination register. The instruction then performs the following operations:
1. Check that the segment selector is not null.
2. Checks that the segment selector points to a segment descriptor that is within the descriptor table limit (GDT
or LDT).
3. Checks that the segment descriptor is a code, data, LDT, or TSS segment-descriptor type.
4. If the segment is not a conforming code segment, checks if the segment descriptor is visible at the CPL (that
is, if the CPL and the RPL of the segment selector less than or equal to the DPL).
5. If the privilege level and type checks pass, loads the unscrambled limit (the limit scaled according to the setting
of the G flag in the segment descriptor) into the destination register and sets the ZF flag in the EFLAGS register.
If the segment selector is not visible at the current privilege level or is an invalid type for the LSL instruction,
the instruction does not modify the destination register and clears the ZF flag.
Once loaded in the destination register, software can compare the segment limit with the offset of a pointer.
Vol. 3A 5-25
PROTECTION
5.10.4
Checking Caller Access Privileges (ARPL Instruction)
The requestor’s privilege level (RPL) field of a segment selector is intended to carry the privilege level of a calling
procedure (the calling procedure’s CPL) to a called procedure. The called procedure then uses the RPL to determine
if access to a segment is allowed. The RPL is said to “weaken” the privilege level of the called procedure to that of
the RPL.
Operating-system procedures typically use the RPL to prevent less privileged application programs from accessing
data located in more privileged segments. When an operating-system procedure (the called procedure) receives a
segment selector from an application program (the calling procedure), it sets the segment selector’s RPL to the
privilege level of the calling procedure. Then, when the operating system uses the segment selector to access its
associated segment, the processor performs privilege checks using the calling procedure’s privilege level (stored in
the RPL) rather than the numerically lower privilege level (the CPL) of the operating-system procedure. The RPL
thus insures that the operating system does not access a segment on behalf of an application program unless that
program itself has access to the segment.
Figure 5-15 shows an example of how the processor uses the RPL field. In this example, an application program
(located in code segment A) possesses a segment selector (segment selector D1) that points to a privileged data
structure (that is, a data structure located in a data segment D at privilege level 0).
The application program cannot access data segment D, because it does not have sufficient privilege, but the operating system (located in code segment C) can. So, in an attempt to access data segment D, the application
program executes a call to the operating system and passes segment selector D1 to the operating system as a
parameter on the stack. Before passing the segment selector, the (well behaved) application program sets the RPL
of the segment selector to its current privilege level (which in this example is 3). If the operating system attempts
to access data segment D using segment selector D1, the processor compares the CPL (which is now 0 following
the call), the RPL of segment selector D1, and the DPL of data segment D (which is 0). Since the RPL is greater than
the DPL, access to data segment D is denied. The processor’s protection mechanism thus protects data segment D
from access by the operating system, because application program’s privilege level (represented by the RPL of
segment selector B) is greater than the DPL of data segment D.
Passed as a
parameter on
the stack.
Application Program
3
Code
Segment A
CPL=3
Lowest Privilege
Gate Selector B
RPL=3
Call
Gate B
DPL=3
Segment Sel. D1
RPL=3
2
Access
not
allowed
1
Code
Operating Segment C
System
DPL=0
0
Highest Privilege
Segment Sel. D2
RPL=0
Access
allowed
Data
Segment D
DPL=0
Figure 5-15. Use of RPL to Weaken Privilege Level of Called Procedure
5-26 Vol. 3A
PROTECTION
Now assume that instead of setting the RPL of the segment selector to 3, the application program sets the RPL to
0 (segment selector D2). The operating system can now access data segment D, because its CPL and the RPL of
segment selector D2 are both equal to the DPL of data segment D.
Because the application program is able to change the RPL of a segment selector to any value, it can potentially use
a procedure operating at a numerically lower privilege level to access a protected data structure. This ability to
lower the RPL of a segment selector breaches the processor’s protection mechanism.
Because a called procedure cannot rely on the calling procedure to set the RPL correctly, operating-system procedures (executing at numerically lower privilege-levels) that receive segment selectors from numerically higher
privilege-level procedures need to test the RPL of the segment selector to determine if it is at the appropriate level.
The ARPL (adjust requested privilege level) instruction is provided for this purpose. This instruction adjusts the RPL
of one segment selector to match that of another segment selector.
The example in Figure 5-15 demonstrates how the ARPL instruction is intended to be used. When the operatingsystem receives segment selector D2 from the application program, it uses the ARPL instruction to compare the
RPL of the segment selector with the privilege level of the application program (represented by the code-segment
selector pushed onto the stack). If the RPL is less than application program’s privilege level, the ARPL instruction
changes the RPL of the segment selector to match the privilege level of the application program (segment selector
D1). Using this instruction thus prevents a procedure running at a numerically higher privilege level from
accessing numerically lower privilege-level (more privileged) segments by lowering the RPL of a segment selector.
Note that the privilege level of the application program can be determined by reading the RPL field of the segment
selector for the application-program’s code segment. This segment selector is stored on the stack as part of the call
to the operating system. The operating system can copy the segment selector from the stack into a register for
use as an operand for the ARPL instruction.
5.10.5
Checking Alignment
When the CPL is 3, alignment of memory references can be checked by setting the AM flag in the CR0 register and
the AC flag in the EFLAGS register. Unaligned memory references generate alignment exceptions (#AC). The
processor does not generate alignment exceptions when operating at privilege level 0, 1, or 2. See Table 6-7 for a
description of the alignment requirements when alignment checking is enabled.
5.11
PAGE-LEVEL PROTECTION
Page-level protection can be used alone or applied to segments. When page-level protection is used with the flat
memory model, it allows supervisor code and data (the operating system or executive) to be protected from user
code and data (application programs). It also allows pages containing code to be write protected. When the
segment- and page-level protection are combined, page-level read/write protection allows more protection granularity within segments.
With page-level protection (as with segment-level protection) each memory reference is checked to verify that
protection checks are satisfied. All checks are made before the memory cycle is started, and any violation prevents
the cycle from starting and results in a page-fault exception being generated. Because checks are performed in
parallel with address translation, there is no performance penalty.
The processor performs two page-level protection checks:
•
•
Restriction of addressable domain (supervisor and user modes).
Page type (read only or read/write).
Violations of either of these checks results in a page-fault exception being generated. See Chapter 6, “Interrupt
14—Page-Fault Exception (#PF),” for an explanation of the page-fault exception mechanism. This chapter
describes the protection violations which lead to page-fault exceptions.
Vol. 3A 5-27
PROTECTION
5.11.1
Page-Protection Flags
Protection information for pages is contained in two flags in a paging-structure entry (see Chapter 4): the
read/write flag (bit 1) and the user/supervisor flag (bit 2). The protection checks use the flags in all paging structures.
5.11.2
Restricting Addressable Domain
The page-level protection mechanism allows restricting access to pages based on two privilege levels:
•
Supervisor mode (U/S flag is 0)—(Most privileged) For the operating system or executive, other system
software (such as device drivers), and protected system data (such as page tables).
•
User mode (U/S flag is 1)—(Least privileged) For application code and data.
The segment privilege levels map to the page privilege levels as follows. If the processor is currently operating at
a CPL of 0, 1, or 2, it is in supervisor mode; if it is operating at a CPL of 3, it is in user mode. When the processor is
in supervisor mode, it can access all pages; when in user mode, it can access only user-level pages. (Note that the
WP flag in control register CR0 modifies the supervisor permissions, as described in Section 5.11.3, “Page Type.”)
Note that to use the page-level protection mechanism, code and data segments must be set up for at least two
segment-based privilege levels: level 0 for supervisor code and data segments and level 3 for user code and data
segments. (In this model, the stacks are placed in the data segments.) To minimize the use of segments, a flat
memory model can be used (see Section 3.2.1, “Basic Flat Model”).
Here, the user and supervisor code and data segments all begin at address zero in the linear address space and
overlay each other. With this arrangement, operating-system code (running at the supervisor level) and application
code (running at the user level) can execute as if there are no segments. Protection between operating-system and
application code and data is provided by the processor’s page-level protection mechanism.
5.11.3
Page Type
The page-level protection mechanism recognizes two page types:
•
•
Read-only access (R/W flag is 0).
Read/write access (R/W flag is 1).
When the processor is in supervisor mode and the WP flag in register CR0 is clear (its state following reset initialization), all pages are both readable and writable (write-protection is ignored). When the processor is in user
mode, it can write only to user-mode pages that are read/write accessible. User-mode pages which are read/write
or read-only are readable; supervisor-mode pages are neither readable nor writable from user mode. A page-fault
exception is generated on any attempt to violate the protection rules.
Starting with the P6 family, Intel processors allow user-mode pages to be write-protected against supervisor-mode
access. Setting CR0.WP = 1 enables supervisor-mode sensitivity to write protected pages. If CR0.WP = 1, readonly pages are not writable from any privilege level. This supervisor write-protect feature is useful for implementing a “copy-on-write” strategy used by some operating systems, such as UNIX*, for task creation (also called
forking or spawning). When a new task is created, it is possible to copy the entire address space of the parent task.
This gives the child task a complete, duplicate set of the parent's segments and pages. An alternative copy-onwrite strategy saves memory space and time by mapping the child's segments and pages to the same segments
and pages used by the parent task. A private copy of a page gets created only when one of the tasks writes to the
page. By using the WP flag and marking the shared pages as read-only, the supervisor can detect an attempt to
write to a page, and can copy the page at that time.
5.11.4
Combining Protection of Both Levels of Page Tables
For any one page, the protection attributes of its page-directory entry (first-level page table) may differ from those
of its page-table entry (second-level page table). The processor checks the protection for a page in both its pagedirectory and the page-table entries. Table 5-3 shows the protection provided by the possible combinations of
protection attributes when the WP flag is clear.
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PROTECTION
5.11.5
Overrides to Page Protection
The following types of memory accesses are checked as if they are privilege-level 0 accesses, regardless of the CPL
at which the processor is currently operating:
•
•
Access to segment descriptors in the GDT, LDT, or IDT.
Access to an inner-privilege-level stack during an inter-privilege-level call or a call to in exception or interrupt
handler, when a change of privilege level occurs.
5.12
COMBINING PAGE AND SEGMENT PROTECTION
When paging is enabled, the processor evaluates segment protection first, then evaluates page protection. If the
processor detects a protection violation at either the segment level or the page level, the memory access is not
carried out and an exception is generated. If an exception is generated by segmentation, no paging exception is
generated.
Page-level protections cannot be used to override segment-level protection. For example, a code segment is by
definition not writable. If a code segment is paged, setting the R/W flag for the pages to read-write does not make
the pages writable. Attempts to write into the pages will be blocked by segment-level protection checks.
Page-level protection can be used to enhance segment-level protection. For example, if a large read-write data
segment is paged, the page-protection mechanism can be used to write-protect individual pages.
Table 5-3. Combined Page-Directory and Page-Table Protection
Page-Directory Entry
Page-Table Entry
Combined Effect
Privilege
Access Type
Privilege
Access Type
Privilege
Access Type
User
Read-Only
User
Read-Only
User
Read-Only
User
Read-Only
User
Read-Write
User
Read-Only
User
Read-Write
User
Read-Only
User
Read-Only
User
Read-Write
User
Read-Write
User
Read/Write
User
Read-Only
Supervisor
Read-Only
Supervisor
Read/Write*
User
Read-Only
Supervisor
Read-Write
Supervisor
Read/Write*
User
Read-Write
Supervisor
Read-Only
Supervisor
Read/Write*
User
Read-Write
Supervisor
Read-Write
Supervisor
Read/Write
Supervisor
Read-Only
User
Read-Only
Supervisor
Read/Write*
Supervisor
Read-Only
User
Read-Write
Supervisor
Read/Write*
Supervisor
Read-Write
User
Read-Only
Supervisor
Read/Write*
Supervisor
Read-Write
User
Read-Write
Supervisor
Read/Write
Supervisor
Read-Only
Supervisor
Read-Only
Supervisor
Read/Write*
Supervisor
Read-Only
Supervisor
Read-Write
Supervisor
Read/Write*
Supervisor
Read-Write
Supervisor
Read-Only
Supervisor
Read/Write*
Supervisor
Read-Write
Supervisor
Read-Write
Supervisor
Read/Write
NOTE:
* If CR0.WP = 1, access type is determined by the R/W flags of the page-directory and page-table entries. IF CR0.WP = 0, supervisor
privilege permits read-write access.
Vol. 3A 5-29
PROTECTION
5.13
PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT
In addition to page-level protection offered by the U/S and R/W flags, paging structures used with PAE paging and
IA-32e paging (see Chapter 4) provide the execute-disable bit. This bit offers additional protection for data pages.
An Intel 64 or IA-32 processor with the execute-disable bit capability can prevent data pages from being used by
malicious software to execute code. This capability is provided in:
•
•
32-bit protected mode with PAE enabled.
IA-32e mode.
While the execute-disable bit capability does not introduce new instructions, it does require operating systems to
use a PAE-enabled environment and establish a page-granular protection policy for memory pages.
If the execute-disable bit of a memory page is set, that page can be used only as data. An attempt to execute code
from a memory page with the execute-disable bit set causes a page-fault exception.
The execute-disable capability is supported only with PAE paging and IA-32e paging. It is not supported with 32-bit
paging. Existing page-level protection mechanisms (see Section 5.11, “Page-Level Protection”) continue to apply
to memory pages independent of the execute-disable setting.
5.13.1
Detecting and Enabling the Execute-Disable Capability
Software can detect the presence of the execute-disable capability using the CPUID instruction.
CPUID.80000001H:EDX.NX [bit 20] = 1 indicates the capability is available.
If the capability is available, software can enable it by setting IA32_EFER.NXE[bit 11] to 1. IA32_EFER is available
if CPUID.80000001H.EDX[bit 20 or 29] = 1.
If the execute-disable capability is not available, a write to set IA32_EFER.NXE produces a #GP exception. See
Table 5-4.
Table 5-4. Extended Feature Enable MSR (IA32_EFER)
63:12
11
10
9
8
7:1
0
Reserved
Execute-disable bit
enable (NXE)
IA-32e mode
active (LMA)
Reserved
IA-32e mode
enable (LME)
Reserved
SysCall enable (SCE)
5.13.2
Execute-Disable Page Protection
The execute-disable bit in the paging structures enhances page protection for data pages. Instructions cannot be
fetched from a memory page if IA32_EFER.NXE =1 and the execute-disable bit is set in any of the paging-structure
entries used to map the page. Table 5-5 lists the valid usage of a page in relation to the value of execute-disable bit
(bit 63) of the corresponding entry in each level of the paging structures. Execute-disable protection can be activated using the execute-disable bit at any level of the paging structure, irrespective of the corresponding entry in
other levels. When execute-disable protection is not activated, the page can be used as code or data.
5-30 Vol. 3A
PROTECTION
Table 5-5. IA-32e Mode Page Level Protection Matrix
with Execute-Disable Bit Capability
Execute Disable Bit Value (Bit 63)
Valid Usage
PML4
PDP
PDE
PTE
Bit 63 = 1
*
*
*
Data
*
Bit 63 = 1
*
*
Data
*
*
Bit 63 = 1
*
Data
*
*
*
Bit 63 = 1
Data
Bit 63 = 0
Bit 63 = 0
Bit 63 = 0
Bit 63 = 0
Data/Code
NOTES:
* Value not checked.
In legacy PAE-enabled mode, Table 5-6 and Table 5-7 show the effect of setting the execute-disable bit for code
and data pages.
Table 5-6. Legacy PAE-Enabled 4-KByte Page Level Protection Matrix
with Execute-Disable Bit Capability
Execute Disable Bit Value (Bit 63)
Valid Usage
PDE
PTE
Bit 63 = 1
*
Data
*
Bit 63 = 1
Data
Bit 63 = 0
Bit 63 = 0
Data/Code
NOTE:
* Value not checked.
Table 5-7. Legacy PAE-Enabled 2-MByte Page Level Protection
with Execute-Disable Bit Capability
Execute Disable Bit Value (Bit 63)
Valid Usage
PDE
Bit 63 = 1
Data
Bit 63 = 0
Data/Code
5.13.3
Reserved Bit Checking
The processor enforces reserved bit checking in paging data structure entries. The bits being checked varies with
paging mode and may vary with the size of physical address space.
Table 5-8 shows the reserved bits that are checked when the execute disable bit capability is enabled (CR4.PAE = 1
and IA32_EFER.NXE = 1). Table 5-8 and Table 5-9 show the following paging modes:
•
•
•
Non-PAE 4-KByte paging: 4-KByte-page only paging (CR4.PAE = 0, CR4.PSE = 0).
PSE36: 4-KByte and 4-MByte pages (CR4.PAE = 0, CR4.PSE = 1).
PAE: 4-KByte and 2-MByte pages (CR4.PAE = 1, CR4.PSE = X).
The reserved bit checking depends on the physical address size supported by the implementation, which is
reported in CPUID.80000008H. See the table note.
Vol. 3A 5-31
PROTECTION
Table 5-8. IA-32e Mode Page Level Protection Matrix with Execute-Disable Bit Capability Enabled
Mode
Paging Mode
Check Bits
32-bit
4-KByte paging (non-PAE)
No reserved bits checked
64-bit
PSE36 - PDE, 4-MByte page
Bit [21]
PSE36 - PDE, 4-KByte page
No reserved bits checked
PSE36 - PTE
No reserved bits checked
PAE - PDP table entry
Bits [63:MAXPHYADDR] & [8:5] & [2:1] *
PAE - PDE, 2-MByte page
Bits [62:MAXPHYADDR] & [20:13] *
PAE - PDE, 4-KByte page
Bits [62:MAXPHYADDR] *
PAE - PTE
Bits [62:MAXPHYADDR] *
PML4E
Bits [51:MAXPHYADDR] *
PDPTE
Bits [51:MAXPHYADDR] *
PDE, 2-MByte page
Bits [51:MAXPHYADDR] & [20:13] *
PDE, 4-KByte page
Bits [51:MAXPHYADDR] *
PTE
Bits [51:MAXPHYADDR] *
NOTES:
* MAXPHYADDR is the maximum physical address size and is indicated by CPUID.80000008H:EAX[bits 7-0].
If execute disable bit capability is not enabled or not available, reserved bit checking in 64-bit mode includes bit 63
and additional bits. This and reserved bit checking for legacy 32-bit paging modes are shown in Table 5-10.
Table 5-9. Reserved Bit Checking WIth Execute-Disable Bit Capability Not Enabled
Mode
Paging Mode
Check Bits
32-bit
KByte paging (non-PAE)
No reserved bits checked
PSE36 - PDE, 4-MByte page
Bit [21]
PSE36 - PDE, 4-KByte page
No reserved bits checked
PSE36 - PTE
No reserved bits checked
PAE - PDP table entry
Bits [63:MAXPHYADDR] & [8:5] & [2:1]*
PAE - PDE, 2-MByte page
Bits [63:MAXPHYADDR] & [20:13]*
PAE - PDE, 4-KByte page
Bits [63:MAXPHYADDR]*
PAE - PTE
Bits [63:MAXPHYADDR]*
PML4E
Bit [63], bits [51:MAXPHYADDR]*
64-bit
PDPTE
Bit [63], bits [51:MAXPHYADDR]*
PDE, 2-MByte page
Bit [63], bits [51:MAXPHYADDR] & [20:13]*
PDE, 4-KByte page
Bit [63], bits [51:MAXPHYADDR]*
PTE
Bit [63], bits [51:MAXPHYADDR]*
NOTES:
* MAXPHYADDR is the maximum physical address size and is indicated by CPUID.80000008H:EAX[bits 7-0].
5.13.4
Exception Handling
When execute disable bit capability is enabled (IA32_EFER.NXE = 1), conditions for a page fault to occur include
the same conditions that apply to an Intel 64 or IA-32 processor without execute disable bit capability plus the
following new condition: an instruction fetch to a linear address that translates to physical address in a memory
page that has the execute-disable bit set.
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PROTECTION
An Execute Disable Bit page fault can occur at all privilege levels. It can occur on any instruction fetch, including
(but not limited to): near branches, far branches, CALL/RET/INT/IRET execution, sequential instruction fetches,
and task switches. The execute-disable bit in the page translation mechanism is checked only when:
•
•
IA32_EFER.NXE = 1.
The instruction translation look-aside buffer (ITLB) is loaded with a page that is not already present in the ITLB.
Vol. 3A 5-33
PROTECTION
5-34 Vol. 3A
CHAPTER 6
INTERRUPT AND EXCEPTION HANDLING
This chapter describes the interrupt and exception-handling mechanism when operating in protected mode on an
Intel 64 or IA-32 processor. Most of the information provided here also applies to interrupt and exception mechanisms used in real-address, virtual-8086 mode, and 64-bit mode.
Chapter 20, “8086 Emulation,” describes information specific to interrupt and exception mechanisms in realaddress and virtual-8086 mode. Section 6.14, “Exception and Interrupt Handling in 64-bit Mode,” describes information specific to interrupt and exception mechanisms in IA-32e mode and 64-bit sub-mode.
6.1
INTERRUPT AND EXCEPTION OVERVIEW
Interrupts and exceptions are events that indicate that a condition exists somewhere in the system, the processor,
or within the currently executing program or task that requires the attention of a processor. They typically result in
a forced transfer of execution from the currently running program or task to a special software routine or task
called an interrupt handler or an exception handler. The action taken by a processor in response to an interrupt or
exception is referred to as servicing or handling the interrupt or exception.
Interrupts occur at random times during the execution of a program, in response to signals from hardware. System
hardware uses interrupts to handle events external to the processor, such as requests to service peripheral devices.
Software can also generate interrupts by executing the INT n instruction.
Exceptions occur when the processor detects an error condition while executing an instruction, such as division by
zero. The processor detects a variety of error conditions including protection violations, page faults, and internal
machine faults. The machine-check architecture of the Pentium 4, Intel Xeon, P6 family, and Pentium processors
also permits a machine-check exception to be generated when internal hardware errors and bus errors are
detected.
When an interrupt is received or an exception is detected, the currently running procedure or task is suspended
while the processor executes an interrupt or exception handler. When execution of the handler is complete, the
processor resumes execution of the interrupted procedure or task. The resumption of the interrupted procedure or
task happens without loss of program continuity, unless recovery from an exception was not possible or an interrupt caused the currently running program to be terminated.
This chapter describes the processor’s interrupt and exception-handling mechanism, when operating in protected
mode. A description of the exceptions and the conditions that cause them to be generated is given at the end of this
chapter.
6.2
EXCEPTION AND INTERRUPT VECTORS
To aid in handling exceptions and interrupts, each architecturally defined exception and each interrupt condition
requiring special handling by the processor is assigned a unique identification number, called a vector number. The
processor uses the vector number assigned to an exception or interrupt as an index into the interrupt descriptor
table (IDT). The table provides the entry point to an exception or interrupt handler (see Section 6.10, “Interrupt
Descriptor Table (IDT)”).
The allowable range for vector numbers is 0 to 255. Vector numbers in the range 0 through 31 are reserved by the
Intel 64 and IA-32 architectures for architecture-defined exceptions and interrupts. Not all of the vector numbers
in this range have a currently defined function. The unassigned vector numbers in this range are reserved. Do not
use the reserved vector numbers.
Vector numbers in the range 32 to 255 are designated as user-defined interrupts and are not reserved by the Intel
64 and IA-32 architecture. These interrupts are generally assigned to external I/O devices to enable those devices
to send interrupts to the processor through one of the external hardware interrupt mechanisms (see Section 6.3,
“Sources of Interrupts”).
Vol. 3A 6-1
INTERRUPT AND EXCEPTION HANDLING
Table 6-1 shows vector number assignments for architecturally defined exceptions and for the NMI interrupt. This
table gives the exception type (see Section 6.5, “Exception Classifications”) and indicates whether an error code is
saved on the stack for the exception. The source of each predefined exception and the NMI interrupt is also given.
6.3
SOURCES OF INTERRUPTS
The processor receives interrupts from two sources:
•
•
External (hardware generated) interrupts.
Software-generated interrupts.
6.3.1
External Interrupts
External interrupts are received through pins on the processor or through the local APIC. The primary interrupt pins
on Pentium 4, Intel Xeon, P6 family, and Pentium processors are the LINT[1:0] pins, which are connected to the
local APIC (see Chapter 10, “Advanced Programmable Interrupt Controller (APIC)”). When the local APIC is
enabled, the LINT[1:0] pins can be programmed through the APIC’s local vector table (LVT) to be associated with
any of the processor’s exception or interrupt vectors.
When the local APIC is global/hardware disabled, these pins are configured as INTR and NMI pins, respectively.
Asserting the INTR pin signals the processor that an external interrupt has occurred. The processor reads from the
system bus the interrupt vector number provided by an external interrupt controller, such as an 8259A (see Section
6.2, “Exception and Interrupt Vectors”). Asserting the NMI pin signals a non-maskable interrupt (NMI), which is
assigned to interrupt vector 2.
Table 6-1. Protected-Mode Exceptions and Interrupts
Vector
Mnemonic
Description
Type
Error
Code
Source
0
#DE
Divide Error
Fault
No
DIV and IDIV instructions.
1
#DB
Debug Exception
Fault/ Trap
No
Instruction, data, and I/O breakpoints;
single-step; and others.
2
—
NMI Interrupt
Interrupt
No
Nonmaskable external interrupt.
3
#BP
Breakpoint
Trap
No
INT 3 instruction.
4
#OF
Overflow
Trap
No
INTO instruction.
5
#BR
BOUND Range Exceeded
Fault
No
BOUND instruction.
6
#UD
Invalid Opcode (Undefined Opcode)
Fault
No
UD2 instruction or reserved opcode.1
7
#NM
Device Not Available (No Math
Coprocessor)
Fault
No
Floating-point or WAIT/FWAIT instruction.
8
#DF
Double Fault
Abort
Yes
(zero)
Any instruction that can generate an
exception, an NMI, or an INTR.
Coprocessor Segment Overrun
(reserved)
Fault
No
Floating-point instruction.2
9
10
#TS
Invalid TSS
Fault
Yes
Task switch or TSS access.
11
#NP
Segment Not Present
Fault
Yes
Loading segment registers or accessing
system segments.
12
#SS
Stack-Segment Fault
Fault
Yes
Stack operations and SS register loads.
13
#GP
General Protection
Fault
Yes
Any memory reference and other
protection checks.
14
#PF
Page Fault
Fault
Yes
Any memory reference.
6-2 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
Table 6-1. Protected-Mode Exceptions and Interrupts (Contd.)
15
—
(Intel reserved. Do not use.)
16
#MF
x87 FPU Floating-Point Error (Math
Fault)
Fault
No
x87 FPU floating-point or WAIT/FWAIT
instruction.
17
#AC
Alignment Check
Fault
Yes
(Zero)
Any data reference in memory.3
18
#MC
Machine Check
Abort
No
Error codes (if any) and source are model
dependent.4
19
#XM
SIMD Floating-Point Exception
Fault
No
SSE/SSE2/SSE3 floating-point
instructions5
20
#VE
Virtualization Exception
Fault
No
EPT violations6
21-31
—
Intel reserved. Do not use.
32-255
—
User Defined (Non-reserved)
Interrupts
No
Interrupt
External interrupt or INT n instruction.
NOTES:
1. The UD2 instruction was introduced in the Pentium Pro processor.
2. Processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.
5. This exception was introduced in the Pentium III processor.
6. This exception can occur only on processors that support the 1-setting of the “EPT-violation #VE” VM-execution control.
The processor’s local APIC is normally connected to a system-based I/O APIC. Here, external interrupts received at
the I/O APIC’s pins can be directed to the local APIC through the system bus (Pentium 4, Intel Core Duo, Intel Core
2, Intel® Atom™, and Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors). The I/O
APIC determines the vector number of the interrupt and sends this number to the local APIC. When a system
contains multiple processors, processors can also send interrupts to one another by means of the system bus
(Pentium 4, Intel Core Duo, Intel Core 2, Intel Atom, and Intel Xeon processors) or the APIC serial bus (P6 family
and Pentium processors).
The LINT[1:0] pins are not available on the Intel486 processor and earlier Pentium processors that do not contain
an on-chip local APIC. These processors have dedicated NMI and INTR pins. With these processors, external interrupts are typically generated by a system-based interrupt controller (8259A), with the interrupts being signaled
through the INTR pin.
Note that several other pins on the processor can cause a processor interrupt to occur. However, these interrupts
are not handled by the interrupt and exception mechanism described in this chapter. These pins include the
RESET#, FLUSH#, STPCLK#, SMI#, R/S#, and INIT# pins. Whether they are included on a particular processor is
implementation dependent. Pin functions are described in the data books for the individual processors. The SMI#
pin is described in Chapter 34, “System Management Mode.”
6.3.2
Maskable Hardware Interrupts
Any external interrupt that is delivered to the processor by means of the INTR pin or through the local APIC is called
a maskable hardware interrupt. Maskable hardware interrupts that can be delivered through the INTR pin include
all IA-32 architecture defined interrupt vectors from 0 through 255; those that can be delivered through the local
APIC include interrupt vectors 16 through 255.
The IF flag in the EFLAGS register permits all maskable hardware interrupts to be masked as a group (see Section
6.8.1, “Masking Maskable Hardware Interrupts”). Note that when interrupts 0 through 15 are delivered through the
local APIC, the APIC indicates the receipt of an illegal vector.
Vol. 3A 6-3
INTERRUPT AND EXCEPTION HANDLING
6.3.3
Software-Generated Interrupts
The INT n instruction permits interrupts to be generated from within software by supplying an interrupt vector
number as an operand. For example, the INT 35 instruction forces an implicit call to the interrupt handler for interrupt 35.
Any of the interrupt vectors from 0 to 255 can be used as a parameter in this instruction. If the processor’s
predefined NMI vector is used, however, the response of the processor will not be the same as it would be from an
NMI interrupt generated in the normal manner. If vector number 2 (the NMI vector) is used in this instruction, the
NMI interrupt handler is called, but the processor’s NMI-handling hardware is not activated.
Interrupts generated in software with the INT n instruction cannot be masked by the IF flag in the EFLAGS register.
6.4
SOURCES OF EXCEPTIONS
The processor receives exceptions from three sources:
•
•
•
Processor-detected program-error exceptions.
Software-generated exceptions.
Machine-check exceptions.
6.4.1
Program-Error Exceptions
The processor generates one or more exceptions when it detects program errors during the execution in an application program or the operating system or executive. Intel 64 and IA-32 architectures define a vector number for
each processor-detectable exception. Exceptions are classified as faults, traps, and aborts (see Section 6.5,
“Exception Classifications”).
6.4.2
Software-Generated Exceptions
The INTO, INT 3, and BOUND instructions permit exceptions to be generated in software. These instructions allow
checks for exception conditions to be performed at points in the instruction stream. For example, INT 3 causes a
breakpoint exception to be generated.
The INT n instruction can be used to emulate exceptions in software; but there is a limitation. If INT n provides a
vector for one of the architecturally-defined exceptions, the processor generates an interrupt to the correct vector
(to access the exception handler) but does not push an error code on the stack. This is true even if the associated
hardware-generated exception normally produces an error code. The exception handler will still attempt to pop an
error code from the stack while handling the exception. Because no error code was pushed, the handler will pop off
and discard the EIP instead (in place of the missing error code). This sends the return to the wrong location.
6.4.3
Machine-Check Exceptions
The P6 family and Pentium processors provide both internal and external machine-check mechanisms for checking
the operation of the internal chip hardware and bus transactions. These mechanisms are implementation dependent. When a machine-check error is detected, the processor signals a machine-check exception (vector 18) and
returns an error code.
See Chapter 6, “Interrupt 18—Machine-Check Exception (#MC)” and Chapter 15, “Machine-Check Architecture,”
for more information about the machine-check mechanism.
6.5
EXCEPTION CLASSIFICATIONS
Exceptions are classified as faults, traps, or aborts depending on the way they are reported and whether the
instruction that caused the exception can be restarted without loss of program or task continuity.
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INTERRUPT AND EXCEPTION HANDLING
•
Faults — A fault is an exception that can generally be corrected and that, once corrected, allows the program
to be restarted with no loss of continuity. When a fault is reported, the processor restores the machine state to
the state prior to the beginning of execution of the faulting instruction. The return address (saved contents of
the CS and EIP registers) for the fault handler points to the faulting instruction, rather than to the instruction
following the faulting instruction.
•
Traps — A trap is an exception that is reported immediately following the execution of the trapping instruction.
Traps allow execution of a program or task to be continued without loss of program continuity. The return
address for the trap handler points to the instruction to be executed after the trapping instruction.
•
Aborts — An abort is an exception that does not always report the precise location of the instruction causing
the exception and does not allow a restart of the program or task that caused the exception. Aborts are used
to report severe errors, such as hardware errors and inconsistent or illegal values in system tables.
NOTE
One exception subset normally reported as a fault is not restartable. Such exceptions result in loss
of some processor state. For example, executing a POPAD instruction where the stack frame
crosses over the end of the stack segment causes a fault to be reported. In this situation, the
exception handler sees that the instruction pointer (CS:EIP) has been restored as if the POPAD
instruction had not been executed. However, internal processor state (the general-purpose
registers) will have been modified. Such cases are considered programming errors. An application
causing this class of exceptions should be terminated by the operating system.
6.6
PROGRAM OR TASK RESTART
To allow the restarting of program or task following the handling of an exception or an interrupt, all exceptions
(except aborts) are guaranteed to report exceptions on an instruction boundary. All interrupts are guaranteed to be
taken on an instruction boundary.
For fault-class exceptions, the return instruction pointer (saved when the processor generates an exception) points
to the faulting instruction. So, when a program or task is restarted following the handling of a fault, the faulting
instruction is restarted (re-executed). Restarting the faulting instruction is commonly used to handle exceptions
that are generated when access to an operand is blocked. The most common example of this type of fault is a pagefault exception (#PF) that occurs when a program or task references an operand located on a page that is not in
memory. When a page-fault exception occurs, the exception handler can load the page into memory and resume
execution of the program or task by restarting the faulting instruction. To insure that the restart is handled transparently to the currently executing program or task, the processor saves the necessary registers and stack pointers
to allow a restart to the state prior to the execution of the faulting instruction.
For trap-class exceptions, the return instruction pointer points to the instruction following the trapping instruction.
If a trap is detected during an instruction which transfers execution, the return instruction pointer reflects the
transfer. For example, if a trap is detected while executing a JMP instruction, the return instruction pointer points
to the destination of the JMP instruction, not to the next address past the JMP instruction. All trap exceptions allow
program or task restart with no loss of continuity. For example, the overflow exception is a trap exception. Here,
the return instruction pointer points to the instruction following the INTO instruction that tested EFLAGS.OF (overflow) flag. The trap handler for this exception resolves the overflow condition. Upon return from the trap handler,
program or task execution continues at the instruction following the INTO instruction.
The abort-class exceptions do not support reliable restarting of the program or task. Abort handlers are designed
to collect diagnostic information about the state of the processor when the abort exception occurred and then shut
down the application and system as gracefully as possible.
Interrupts rigorously support restarting of interrupted programs and tasks without loss of continuity. The return
instruction pointer saved for an interrupt points to the next instruction to be executed at the instruction boundary
where the processor took the interrupt. If the instruction just executed has a repeat prefix, the interrupt is taken
at the end of the current iteration with the registers set to execute the next iteration.
The ability of a P6 family processor to speculatively execute instructions does not affect the taking of interrupts by
the processor. Interrupts are taken at instruction boundaries located during the retirement phase of instruction
execution; so they are always taken in the “in-order” instruction stream. See Chapter 2, “Intel® 64 and IA-32
Vol. 3A 6-5
INTERRUPT AND EXCEPTION HANDLING
Architectures,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about the P6 family processors’ microarchitecture and its support for out-of-order instruction execution.
Note that the Pentium processor and earlier IA-32 processors also perform varying amounts of prefetching and
preliminary decoding. With these processors as well, exceptions and interrupts are not signaled until actual “inorder” execution of the instructions. For a given code sample, the signaling of exceptions occurs uniformly when
the code is executed on any family of IA-32 processors (except where new exceptions or new opcodes have been
defined).
6.7
NONMASKABLE INTERRUPT (NMI)
The nonmaskable interrupt (NMI) can be generated in either of two ways:
•
•
External hardware asserts the NMI pin.
The processor receives a message on the system bus (Pentium 4, Intel Core Duo, Intel Core 2, Intel Atom, and
Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors) with a delivery mode NMI.
When the processor receives a NMI from either of these sources, the processor handles it immediately by calling
the NMI handler pointed to by interrupt vector number 2. The processor also invokes certain hardware conditions
to insure that no other interrupts, including NMI interrupts, are received until the NMI handler has completed
executing (see Section 6.7.1, “Handling Multiple NMIs”).
Also, when an NMI is received from either of the above sources, it cannot be masked by the IF flag in the EFLAGS
register.
It is possible to issue a maskable hardware interrupt (through the INTR pin) to vector 2 to invoke the NMI interrupt
handler; however, this interrupt will not truly be an NMI interrupt. A true NMI interrupt that activates the
processor’s NMI-handling hardware can only be delivered through one of the mechanisms listed above.
6.7.1
Handling Multiple NMIs
While an NMI interrupt handler is executing, the processor blocks delivery of subsequent NMIs until the next execution of the IRET instruction. This blocking of NMIs prevents nested execution of the NMI handler. It is recommended
that the NMI interrupt handler be accessed through an interrupt gate to disable maskable hardware interrupts (see
Section 6.8.1, “Masking Maskable Hardware Interrupts”).
An execution of the IRET instruction unblocks NMIs even if the instruction causes a fault. For example, if the IRET
instruction executes with EFLAGS.VM = 1 and IOPL of less than 3, a general-protection exception is generated (see
Section 20.2.7, “Sensitive Instructions”). In such a case, NMIs are unmasked before the exception handler is
invoked.
6.8
ENABLING AND DISABLING INTERRUPTS
The processor inhibits the generation of some interrupts, depending on the state of the processor and of the IF and
RF flags in the EFLAGS register, as described in the following sections.
6.8.1
Masking Maskable Hardware Interrupts
The IF flag can disable the servicing of maskable hardware interrupts received on the processor’s INTR pin or
through the local APIC (see Section 6.3.2, “Maskable Hardware Interrupts”). When the IF flag is clear, the
processor inhibits interrupts delivered to the INTR pin or through the local APIC from generating an internal interrupt request; when the IF flag is set, interrupts delivered to the INTR or through the local APIC pin are processed
as normal external interrupts.
The IF flag does not affect non-maskable interrupts (NMIs) delivered to the NMI pin or delivery mode NMI
messages delivered through the local APIC, nor does it affect processor generated exceptions. As with the other
flags in the EFLAGS register, the processor clears the IF flag in response to a hardware reset.
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INTERRUPT AND EXCEPTION HANDLING
The fact that the group of maskable hardware interrupts includes the reserved interrupt and exception vectors 0
through 32 can potentially cause confusion. Architecturally, when the IF flag is set, an interrupt for any of the
vectors from 0 through 32 can be delivered to the processor through the INTR pin and any of the vectors from 16
through 32 can be delivered through the local APIC. The processor will then generate an interrupt and call the
interrupt or exception handler pointed to by the vector number. So for example, it is possible to invoke the pagefault handler through the INTR pin (by means of vector 14); however, this is not a true page-fault exception. It is
an interrupt. As with the INT n instruction (see Section 6.4.2, “Software-Generated Exceptions”), when an interrupt is generated through the INTR pin to an exception vector, the processor does not push an error code on the
stack, so the exception handler may not operate correctly.
The IF flag can be set or cleared with the STI (set interrupt-enable flag) and CLI (clear interrupt-enable flag)
instructions, respectively. These instructions may be executed only if the CPL is equal to or less than the IOPL. A
general-protection exception (#GP) is generated if they are executed when the CPL is greater than the IOPL. (The
effect of the IOPL on these instructions is modified slightly when the virtual mode extension is enabled by setting
the VME flag in control register CR4: see Section 20.3, “Interrupt and Exception Handling in Virtual-8086 Mode.”
Behavior is also impacted by the PVI flag: see Section 20.4, “Protected-Mode Virtual Interrupts.”
The IF flag is also affected by the following operations:
•
The PUSHF instruction stores all flags on the stack, where they can be examined and modified. The POPF
instruction can be used to load the modified flags back into the EFLAGS register.
•
Task switches and the POPF and IRET instructions load the EFLAGS register; therefore, they can be used to
modify the setting of the IF flag.
•
When an interrupt is handled through an interrupt gate, the IF flag is automatically cleared, which disables
maskable hardware interrupts. (If an interrupt is handled through a trap gate, the IF flag is not cleared.)
See the descriptions of the CLI, STI, PUSHF, POPF, and IRET instructions in Chapter 3, “Instruction Set Reference,
A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Chapter 4, “Instruction Set Reference, M-U,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for a
detailed description of the operations these instructions are allowed to perform on the IF flag.
6.8.2
Masking Instruction Breakpoints
The RF (resume) flag in the EFLAGS register controls the response of the processor to instruction-breakpoint conditions (see the description of the RF flag in Section 2.3, “System Flags and Fields in the EFLAGS Register”).
When set, it prevents an instruction breakpoint from generating a debug exception (#DB); when clear, instruction
breakpoints will generate debug exceptions. The primary function of the RF flag is to prevent the processor from
going into a debug exception loop on an instruction-breakpoint. See Section 17.3.1.1, “Instruction-Breakpoint
Exception Condition,” for more information on the use of this flag.
6.8.3
Masking Exceptions and Interrupts When Switching Stacks
To switch to a different stack segment, software often uses a pair of instructions, for example:
MOV SS, AX
MOV ESP, StackTop
If an interrupt or exception occurs after the segment selector has been loaded into the SS register but before the
ESP register has been loaded, these two parts of the logical address into the stack space are inconsistent for the
duration of the interrupt or exception handler.
To prevent this situation, the processor inhibits interrupts, debug exceptions, and single-step trap exceptions after
either a MOV to SS instruction or a POP to SS instruction, until the instruction boundary following the next instruction is reached. All other faults may still be generated. If the LSS instruction is used to modify the contents of the
SS register (which is the recommended method of modifying this register), this problem does not occur.
Vol. 3A 6-7
INTERRUPT AND EXCEPTION HANDLING
6.9
PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS
If more than one exception or interrupt is pending at an instruction boundary, the processor services them in a
predictable order. Table 6-2 shows the priority among classes of exception and interrupt sources.
Table 6-2. Priority Among Simultaneous Exceptions and Interrupts
Priority
1 (Highest)
Description
Hardware Reset and Machine Checks
- RESET
- Machine Check
2
Trap on Task Switch
- T flag in TSS is set
3
External Hardware Interventions
- FLUSH
- STOPCLK
- SMI
- INIT
4
Traps on the Previous Instruction
- Breakpoints
- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)
5
Nonmaskable Interrupts (NMI) 1
6
Maskable Hardware Interrupts 1
7
Code Breakpoint Fault
8
Faults from Fetching Next Instruction
- Code-Segment Limit Violation
- Code Page Fault
9
Faults from Decoding the Next Instruction
- Instruction length > 15 bytes
- Invalid Opcode
- Coprocessor Not Available
10 (Lowest)
Faults on Executing an Instruction
- Overflow
- Bound error
- Invalid TSS
- Segment Not Present
- Stack fault
- General Protection
- Data Page Fault
- Alignment Check
- x87 FPU Floating-point exception
- SIMD floating-point exception
- Virtualization exception
NOTE
1. The Intel® 486 processor and earlier processors group nonmaskable and maskable interrupts in the same priority class.
While priority among these classes listed in Table 6-2 is consistent throughout the architecture, exceptions within
each class are implementation-dependent and may vary from processor to processor. The processor first services
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INTERRUPT AND EXCEPTION HANDLING
a pending exception or interrupt from the class which has the highest priority, transferring execution to the first
instruction of the handler. Lower priority exceptions are discarded; lower priority interrupts are held pending.
Discarded exceptions are re-generated when the interrupt handler returns execution to the point in the program or
task where the exceptions and/or interrupts occurred.
6.10
INTERRUPT DESCRIPTOR TABLE (IDT)
The interrupt descriptor table (IDT) associates each exception or interrupt vector with a gate descriptor for the
procedure or task used to service the associated exception or interrupt. Like the GDT and LDTs, the IDT is an array
of 8-byte descriptors (in protected mode). Unlike the GDT, the first entry of the IDT may contain a descriptor. To
form an index into the IDT, the processor scales the exception or interrupt vector by eight (the number of bytes in
a gate descriptor). Because there are only 256 interrupt or exception vectors, the IDT need not contain more than
256 descriptors. It can contain fewer than 256 descriptors, because descriptors are required only for the interrupt
and exception vectors that may occur. All empty descriptor slots in the IDT should have the present flag for the
descriptor set to 0.
The base addresses of the IDT should be aligned on an 8-byte boundary to maximize performance of cache line
fills. The limit value is expressed in bytes and is added to the base address to get the address of the last valid byte.
A limit value of 0 results in exactly 1 valid byte. Because IDT entries are always eight bytes long, the limit should
always be one less than an integral multiple of eight (that is, 8N – 1).
The IDT may reside anywhere in the linear address space. As shown in Figure 6-1, the processor locates the IDT
using the IDTR register. This register holds both a 32-bit base address and 16-bit limit for the IDT.
The LIDT (load IDT register) and SIDT (store IDT register) instructions load and store the contents of the IDTR
register, respectively. The LIDT instruction loads the IDTR register with the base address and limit held in a
memory operand. This instruction can be executed only when the CPL is 0. It normally is used by the initialization
code of an operating system when creating an IDT. An operating system also may use it to change from one IDT to
another. The SIDT instruction copies the base and limit value stored in IDTR to memory. This instruction can be
executed at any privilege level.
If a vector references a descriptor beyond the limit of the IDT, a general-protection exception (#GP) is generated.
NOTE
Because interrupts are delivered to the processor core only once, an incorrectly configured IDT
could result in incomplete interrupt handling and/or the blocking of interrupt delivery.
IA-32 architecture rules need to be followed for setting up IDTR base/limit/access fields and each
field in the gate descriptors. The same apply for the Intel 64 architecture. This includes implicit
referencing of the destination code segment through the GDT or LDT and accessing the stack.
Vol. 3A 6-9
INTERRUPT AND EXCEPTION HANDLING
IDTR Register
47
16 15
IDT Base Address
0
IDT Limit
+
Interrupt
Descriptor Table (IDT)
Gate for
Interrupt #n
(n−1)∗8
Gate for
Interrupt #3
16
Gate for
Interrupt #2
8
Gate for
Interrupt #1
31
0
0
Figure 6-1. Relationship of the IDTR and IDT
6.11
IDT DESCRIPTORS
The IDT may contain any of three kinds of gate descriptors:
•
•
•
Task-gate descriptor
Interrupt-gate descriptor
Trap-gate descriptor
Figure 6-2 shows the formats for the task-gate, interrupt-gate, and trap-gate descriptors. The format of a task
gate used in an IDT is the same as that of a task gate used in the GDT or an LDT (see Section 7.2.5, “Task-Gate
Descriptor”). The task gate contains the segment selector for a TSS for an exception and/or interrupt handler task.
Interrupt and trap gates are very similar to call gates (see Section 5.8.3, “Call Gates”). They contain a far pointer
(segment selector and offset) that the processor uses to transfer program execution to a handler procedure in an
exception- or interrupt-handler code segment. These gates differ in the way the processor handles the IF flag in the
EFLAGS register (see Section 6.12.1.2, “Flag Usage By Exception- or Interrupt-Handler Procedure”).
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INTERRUPT AND EXCEPTION HANDLING
Task Gate
31
16 15 14 13 12
P
31
D
P
L
0
8 7
4
0 0 1 0 1
16 15
0
0
TSS Segment Selector
Interrupt Gate
31
16 15 14 13 12
Offset 31..16
31
P
D
P
L
8 7
0 D 1 1 0
5 4
0
4
0 0 0
16 15
0
Segment Selector
0
Offset 15..0
Trap Gate
31
16 15 14 13 12
Offset 31..16
31
P
D
P
L
8 7
0 D 1 1 1
5 4
DPL
Offset
P
Selector
D
4
0 0 0
16 15
Segment Selector
0
0
Offset 15..0
0
Descriptor Privilege Level
Offset to procedure entry point
Segment Present flag
Segment Selector for destination code segment
Size of gate: 1 = 32 bits; 0 = 16 bits
Reserved
Figure 6-2. IDT Gate Descriptors
6.12
EXCEPTION AND INTERRUPT HANDLING
The processor handles calls to exception- and interrupt-handlers similar to the way it handles calls with a CALL
instruction to a procedure or a task. When responding to an exception or interrupt, the processor uses the exception or interrupt vector as an index to a descriptor in the IDT. If the index points to an interrupt gate or trap gate,
the processor calls the exception or interrupt handler in a manner similar to a CALL to a call gate (see Section
5.8.2, “Gate Descriptors,” through Section 5.8.6, “Returning from a Called Procedure”). If index points to a task
gate, the processor executes a task switch to the exception- or interrupt-handler task in a manner similar to a CALL
to a task gate (see Section 7.3, “Task Switching”).
6.12.1
Exception- or Interrupt-Handler Procedures
An interrupt gate or trap gate references an exception- or interrupt-handler procedure that runs in the context of
the currently executing task (see Figure 6-3). The segment selector for the gate points to a segment descriptor for
an executable code segment in either the GDT or the current LDT. The offset field of the gate descriptor points to
the beginning of the exception- or interrupt-handling procedure.
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INTERRUPT AND EXCEPTION HANDLING
Destination
Code Segment
IDT
Interrupt
Vector
Interrupt or
Trap Gate
Offset
+
Interrupt
Procedure
Segment Selector
GDT or LDT
Base
Address
Segment
Descriptor
Figure 6-3. Interrupt Procedure Call
When the processor performs a call to the exception- or interrupt-handler procedure:
•
If the handler procedure is going to be executed at a numerically lower privilege level, a stack switch occurs.
When the stack switch occurs:
a. The segment selector and stack pointer for the stack to be used by the handler are obtained from the TSS
for the currently executing task. On this new stack, the processor pushes the stack segment selector and
stack pointer of the interrupted procedure.
b. The processor then saves the current state of the EFLAGS, CS, and EIP registers on the new stack (see
Figures 6-4).
c.
•
If an exception causes an error code to be saved, it is pushed on the new stack after the EIP value.
If the handler procedure is going to be executed at the same privilege level as the interrupted procedure:
a. The processor saves the current state of the EFLAGS, CS, and EIP registers on the current stack (see
Figures 6-4).
b. If an exception causes an error code to be saved, it is pushed on the current stack after the EIP value.
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INTERRUPT AND EXCEPTION HANDLING
Stack Usage with No
Privilege-Level Change
Interrupted Procedure’s
and Handler’s Stack
EFLAGS
CS
EIP
Error Code
ESP Before
Transfer to Handler
ESP After
Transfer to Handler
Stack Usage with
Privilege-Level Change
Interrupted Procedure’s
Stack
Handler’s Stack
ESP Before
Transfer to Handler
ESP After
Transfer to Handler
SS
ESP
EFLAGS
CS
EIP
Error Code
Figure 6-4. Stack Usage on Transfers to Interrupt and Exception-Handling Routines
To return from an exception- or interrupt-handler procedure, the handler must use the IRET (or IRETD) instruction.
The IRET instruction is similar to the RET instruction except that it restores the saved flags into the EFLAGS
register. The IOPL field of the EFLAGS register is restored only if the CPL is 0. The IF flag is changed only if the CPL
is less than or equal to the IOPL. See Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for a description of the complete operation performed by the
IRET instruction.
If a stack switch occurred when calling the handler procedure, the IRET instruction switches back to the interrupted
procedure’s stack on the return.
6.12.1.1
Protection of Exception- and Interrupt-Handler Procedures
The privilege-level protection for exception- and interrupt-handler procedures is similar to that used for ordinary
procedure calls when called through a call gate (see Section 5.8.4, “Accessing a Code Segment Through a Call
Gate”). The processor does not permit transfer of execution to an exception- or interrupt-handler procedure in a
less privileged code segment (numerically greater privilege level) than the CPL.
An attempt to violate this rule results in a general-protection exception (#GP). The protection mechanism for
exception- and interrupt-handler procedures is different in the following ways:
•
Because interrupt and exception vectors have no RPL, the RPL is not checked on implicit calls to exception and
interrupt handlers.
•
The processor checks the DPL of the interrupt or trap gate only if an exception or interrupt is generated with an
INT n, INT 3, or INTO instruction. Here, the CPL must be less than or equal to the DPL of the gate. This
restriction prevents application programs or procedures running at privilege level 3 from using a software
interrupt to access critical exception handlers, such as the page-fault handler, providing that those handlers are
placed in more privileged code segments (numerically lower privilege level). For hardware-generated
interrupts and processor-detected exceptions, the processor ignores the DPL of interrupt and trap gates.
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INTERRUPT AND EXCEPTION HANDLING
Because exceptions and interrupts generally do not occur at predictable times, these privilege rules effectively
impose restrictions on the privilege levels at which exception and interrupt- handling procedures can run. Either of
the following techniques can be used to avoid privilege-level violations.
•
The exception or interrupt handler can be placed in a conforming code segment. This technique can be used for
handlers that only need to access data available on the stack (for example, divide error exceptions). If the
handler needs data from a data segment, the data segment needs to be accessible from privilege level 3, which
would make it unprotected.
•
The handler can be placed in a nonconforming code segment with privilege level 0. This handler would always
run, regardless of the CPL that the interrupted program or task is running at.
6.12.1.2
Flag Usage By Exception- or Interrupt-Handler Procedure
When accessing an exception or interrupt handler through either an interrupt gate or a trap gate, the processor
clears the TF flag in the EFLAGS register after it saves the contents of the EFLAGS register on the stack. (On calls
to exception and interrupt handlers, the processor also clears the VM, RF, and NT flags in the EFLAGS register, after
they are saved on the stack.) Clearing the TF flag prevents instruction tracing from affecting interrupt response. A
subsequent IRET instruction restores the TF (and VM, RF, and NT) flags to the values in the saved contents of the
EFLAGS register on the stack.
The only difference between an interrupt gate and a trap gate is the way the processor handles the IF flag in the
EFLAGS register. When accessing an exception- or interrupt-handling procedure through an interrupt gate, the
processor clears the IF flag to prevent other interrupts from interfering with the current interrupt handler. A subsequent IRET instruction restores the IF flag to its value in the saved contents of the EFLAGS register on the stack.
Accessing a handler procedure through a trap gate does not affect the IF flag.
6.12.2
Interrupt Tasks
When an exception or interrupt handler is accessed through a task gate in the IDT, a task switch results. Handling
an exception or interrupt with a separate task offers several advantages:
•
•
The entire context of the interrupted program or task is saved automatically.
•
The handler can be further isolated from other tasks by giving it a separate address space. This is done by
giving it a separate LDT.
A new TSS permits the handler to use a new privilege level 0 stack when handling the exception or interrupt. If
an exception or interrupt occurs when the current privilege level 0 stack is corrupted, accessing the handler
through a task gate can prevent a system crash by providing the handler with a new privilege level 0 stack.
The disadvantage of handling an interrupt with a separate task is that the amount of machine state that must be
saved on a task switch makes it slower than using an interrupt gate, resulting in increased interrupt latency.
A task gate in the IDT references a TSS descriptor in the GDT (see Figure 6-5). A switch to the handler task is
handled in the same manner as an ordinary task switch (see Section 7.3, “Task Switching”). The link back to the
interrupted task is stored in the previous task link field of the handler task’s TSS. If an exception caused an error
code to be generated, this error code is copied to the stack of the new task.
When exception- or interrupt-handler tasks are used in an operating system, there are actually two mechanisms
that can be used to dispatch tasks: the software scheduler (part of the operating system) and the hardware scheduler (part of the processor's interrupt mechanism). The software scheduler needs to accommodate interrupt tasks
that may be dispatched when interrupts are enabled.
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INTERRUPT AND EXCEPTION HANDLING
NOTE
Because IA-32 architecture tasks are not re-entrant, an interrupt-handler task must disable
interrupts between the time it completes handling the interrupt and the time it executes the IRET
instruction. This action prevents another interrupt from occurring while the interrupt task’s TSS is
still marked busy, which would cause a general-protection (#GP) exception.
IDT
Interrupt
Vector
TSS for InterruptHandling Task
Task Gate
TSS Selector
GDT
TSS
Base
Address
TSS Descriptor
Figure 6-5. Interrupt Task Switch
6.13
ERROR CODE
When an exception condition is related to a specific segment selector or IDT vector, the processor pushes an error
code onto the stack of the exception handler (whether it is a procedure or task). The error code has the format
shown in Figure 6-6. The error code resembles a segment selector; however, instead of a TI flag and RPL field, the
error code contains 3 flags:
EXT
External event (bit 0) — When set, indicates that the exception occurred during delivery of an
event external to the program, such as an interrupt or an earlier exception.
IDT
Descriptor location (bit 1) — When set, indicates that the index portion of the error code refers
to a gate descriptor in the IDT; when clear, indicates that the index refers to a descriptor in the GDT
or the current LDT.
TI
GDT/LDT (bit 2) — Only used when the IDT flag is clear. When set, the TI flag indicates that the
index portion of the error code refers to a segment or gate descriptor in the LDT; when clear, it indicates that the index refers to a descriptor in the current GDT.
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INTERRUPT AND EXCEPTION HANDLING
31
3 2 1 0
Reserved
Segment Selector Index
T I E
X
I D
T T
Figure 6-6. Error Code
The segment selector index field provides an index into the IDT, GDT, or current LDT to the segment or gate
selector being referenced by the error code. In some cases the error code is null (all bits are clear except possibly
EXT). A null error code indicates that the error was not caused by a reference to a specific segment or that a null
segment selector was referenced in an operation.
The format of the error code is different for page-fault exceptions (#PF). See the “Interrupt 14—Page-Fault Exception (#PF)” section in this chapter.
The error code is pushed on the stack as a doubleword or word (depending on the default interrupt, trap, or task
gate size). To keep the stack aligned for doubleword pushes, the upper half of the error code is reserved. Note that
the error code is not popped when the IRET instruction is executed to return from an exception handler, so the
handler must remove the error code before executing a return.
Error codes are not pushed on the stack for exceptions that are generated externally (with the INTR or LINT[1:0]
pins) or the INT n instruction, even if an error code is normally produced for those exceptions.
6.14
EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE
In 64-bit mode, interrupt and exception handling is similar to what has been described for non-64-bit modes. The
following are the exceptions:
•
•
•
All interrupt handlers pointed by the IDT are in 64-bit code (this does not apply to the SMI handler).
•
•
•
•
The new SS is set to NULL if there is a change in CPL.
The size of interrupt-stack pushes is fixed at 64 bits; and the processor uses 8-byte, zero extended stores.
The stack pointer (SS:RSP) is pushed unconditionally on interrupts. In legacy modes, this push is conditional
and based on a change in current privilege level (CPL).
IRET behavior changes.
There is a new interrupt stack-switch mechanism.
The alignment of interrupt stack frame is different.
6.14.1
64-Bit Mode IDT
Interrupt and trap gates are 16 bytes in length to provide a 64-bit offset for the instruction pointer (RIP). The 64bit RIP referenced by interrupt-gate descriptors allows an interrupt service routine to be located anywhere in the
linear-address space. See Figure 6-7.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt/Trap Gate
31
0
Reserved
12
31
0
Offset 63..32
31
8
16 15 14 13 12 11
Offset 31..16
31
P
D
P
L
0
8 7
TYPE
5 4
0 0 0 0 0
16 15
Segment Selector
DPL
Offset
P
Selector
IST
0
2
4
IST
0
Offset 15..0
0
Descriptor Privilege Level
Offset to procedure entry point
Segment Present flag
Segment Selector for destination code segment
Interrupt Stack Table
Figure 6-7. 64-Bit IDT Gate Descriptors
In 64-bit mode, the IDT index is formed by scaling the interrupt vector by 16. The first eight bytes (bytes 7:0) of a
64-bit mode interrupt gate are similar but not identical to legacy 32-bit interrupt gates. The type field (bits 11:8 in
bytes 7:4) is described in Table 3-2. The Interrupt Stack Table (IST) field (bits 4:0 in bytes 7:4) is used by the stack
switching mechanisms described in Section 6.14.5, “Interrupt Stack Table.” Bytes 11:8 hold the upper 32 bits of
the target RIP (interrupt segment offset) in canonical form. A general-protection exception (#GP) is generated if
software attempts to reference an interrupt gate with a target RIP that is not in canonical form.
The target code segment referenced by the interrupt gate must be a 64-bit code segment (CS.L = 1, CS.D = 0). If
the target is not a 64-bit code segment, a general-protection exception (#GP) is generated with the IDT vector
number reported as the error code.
Only 64-bit interrupt and trap gates can be referenced in IA-32e mode (64-bit mode and compatibility mode).
Legacy 32-bit interrupt or trap gate types (0EH or 0FH) are redefined in IA-32e mode as 64-bit interrupt and trap
gate types. No 32-bit interrupt or trap gate type exists in IA-32e mode. If a reference is made to a 16-bit interrupt
or trap gate (06H or 07H), a general-protection exception (#GP(0)) is generated.
6.14.2
64-Bit Mode Stack Frame
In legacy mode, the size of an IDT entry (16 bits or 32 bits) determines the size of interrupt-stack-frame pushes.
SS:ESP is pushed only on a CPL change. In 64-bit mode, the size of interrupt stack-frame pushes is fixed at eight
bytes. This is because only 64-bit mode gates can be referenced. 64-bit mode also pushes SS:RSP unconditionally,
rather than only on a CPL change.
Aside from error codes, pushing SS:RSP unconditionally presents operating systems with a consistent interruptstackframe size across all interrupts. Interrupt service-routine entry points that handle interrupts generated by the
INTn instruction or external INTR# signal can push an additional error code place-holder to maintain consistency.
In legacy mode, the stack pointer may be at any alignment when an interrupt or exception causes a stack frame to
be pushed. This causes the stack frame and succeeding pushes done by an interrupt handler to be at arbitrary
alignments. In IA-32e mode, the RSP is aligned to a 16-byte boundary before pushing the stack frame. The stack
frame itself is aligned on a 16-byte boundary when the interrupt handler is called. The processor can arbitrarily
realign the new RSP on interrupts because the previous (possibly unaligned) RSP is unconditionally saved on the
newly aligned stack. The previous RSP will be automatically restored by a subsequent IRET.
Aligning the stack permits exception and interrupt frames to be aligned on a 16-byte boundary before interrupts
are re-enabled. This allows the stack to be formatted for optimal storage of 16-byte XMM registers, which enables
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INTERRUPT AND EXCEPTION HANDLING
the interrupt handler to use faster 16-byte aligned loads and stores (MOVAPS rather than MOVUPS) to save and
restore XMM registers.
Although the RSP alignment is always performed when LMA = 1, it is only of consequence for the kernel-mode case
where there is no stack switch or IST used. For a stack switch or IST, the OS would have presumably put suitably
aligned RSP values in the TSS.
6.14.3
IRET in IA-32e Mode
In IA-32e mode, IRET executes with an 8-byte operand size. There is nothing that forces this requirement. The
stack is formatted in such a way that for actions where IRET is required, the 8-byte IRET operand size works
correctly.
Because interrupt stack-frame pushes are always eight bytes in IA-32e mode, an IRET must pop eight byte items
off the stack. This is accomplished by preceding the IRET with a 64-bit operand-size prefix. The size of the pop is
determined by the address size of the instruction. The SS/ESP/RSP size adjustment is determined by the stack size.
IRET pops SS:RSP unconditionally off the interrupt stack frame only when it is executed in 64-bit mode. In compatibility mode, IRET pops SS:RSP off the stack only if there is a CPL change. This allows legacy applications to
execute properly in compatibility mode when using the IRET instruction. 64-bit interrupt service routines that exit
with an IRET unconditionally pop SS:RSP off of the interrupt stack frame, even if the target code segment is
running in 64-bit mode or at CPL = 0. This is because the original interrupt always pushes SS:RSP.
In IA-32e mode, IRET is allowed to load a NULL SS under certain conditions. If the target mode is 64-bit mode and
the target CPL ≠ 3, IRET allows SS to be loaded with a NULL selector. As part of the stack switch mechanism, an
interrupt or exception sets the new SS to NULL, instead of fetching a new SS selector from the TSS and loading the
corresponding descriptor from the GDT or LDT. The new SS selector is set to NULL in order to properly handle
returns from subsequent nested far transfers. If the called procedure itself is interrupted, the NULL SS is pushed on
the stack frame. On the subsequent IRET, the NULL SS on the stack acts as a flag to tell the processor not to load
a new SS descriptor.
6.14.4
Stack Switching in IA-32e Mode
The IA-32 architecture provides a mechanism to automatically switch stack frames in response to an interrupt. The
64-bit extensions of Intel 64 architecture implement a modified version of the legacy stack-switching mechanism
and an alternative stack-switching mechanism called the interrupt stack table (IST).
In IA-32 modes, the legacy IA-32 stack-switch mechanism is unchanged. In IA-32e mode, the legacy stack-switch
mechanism is modified. When stacks are switched as part of a 64-bit mode privilege-level change (resulting from
an interrupt), a new SS descriptor is not loaded. IA-32e mode loads only an inner-level RSP from the TSS. The new
SS selector is forced to NULL and the SS selector’s RPL field is set to the new CPL. The new SS is set to NULL in
order to handle nested far transfers (far CALL, INT, interrupts and exceptions). The old SS and RSP are saved on
the new stack (Figure 6-8). On the subsequent IRET, the old SS is popped from the stack and loaded into the SS
register.
In summary, a stack switch in IA-32e mode works like the legacy stack switch, except that a new SS selector is not
loaded from the TSS. Instead, the new SS is forced to NULL.
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INTERRUPT AND EXCEPTION HANDLING
Legacy Mode
+20
+16
+12
+8
+4
0
Stack Usage with
Privilege-Level Change
IA-32e Mode
Handler’s Stack
Handler’s Stack
SS
ESP
EFLAGS
CS
EIP
Error Code
SS
RSP
RFLAGS
CS
RIP
Error Code
Stack Pointer After
Transfer to Handler
+40
+32
+24
+16
+8
0
Figure 6-8. IA-32e Mode Stack Usage After Privilege Level Change
6.14.5
Interrupt Stack Table
In IA-32e mode, a new interrupt stack table (IST) mechanism is available as an alternative to the modified legacy
stack-switching mechanism described above. This mechanism unconditionally switches stacks when it is enabled.
It can be enabled on an individual interrupt-vector basis using a field in the IDT entry. This means that some interrupt vectors can use the modified legacy mechanism and others can use the IST mechanism.
The IST mechanism is only available in IA-32e mode. It is part of the 64-bit mode TSS. The motivation for the IST
mechanism is to provide a method for specific interrupts (such as NMI, double-fault, and machine-check) to always
execute on a known good stack. In legacy mode, interrupts can use the task-switch mechanism to set up a knowngood stack by accessing the interrupt service routine through a task gate located in the IDT. However, the legacy
task-switch mechanism is not supported in IA-32e mode.
The IST mechanism provides up to seven IST pointers in the TSS. The pointers are referenced by an interrupt-gate
descriptor in the interrupt-descriptor table (IDT); see Figure 6-7. The gate descriptor contains a 3-bit IST index
field that provides an offset into the IST section of the TSS. Using the IST mechanism, the processor loads the
value pointed by an IST pointer into the RSP.
When an interrupt occurs, the new SS selector is forced to NULL and the SS selector’s RPL field is set to the new
CPL. The old SS, RSP, RFLAGS, CS, and RIP are pushed onto the new stack. Interrupt processing then proceeds as
normal. If the IST index is zero, the modified legacy stack-switching mechanism described above is used.
6.15
EXCEPTION AND INTERRUPT REFERENCE
The following sections describe conditions which generate exceptions and interrupts. They are arranged in the
order of vector numbers. The information contained in these sections are as follows:
•
Exception Class — Indicates whether the exception class is a fault, trap, or abort type. Some exceptions can
be either a fault or trap type, depending on when the error condition is detected. (This section is not applicable
to interrupts.)
•
Description — Gives a general description of the purpose of the exception or interrupt type. It also describes
how the processor handles the exception or interrupt.
•
Exception Error Code — Indicates whether an error code is saved for the exception. If one is saved, the
contents of the error code are described. (This section is not applicable to interrupts.)
•
Saved Instruction Pointer — Describes which instruction the saved (or return) instruction pointer points to.
It also indicates whether the pointer can be used to restart a faulting instruction.
•
Program State Change — Describes the effects of the exception or interrupt on the state of the currently
running program or task and the possibilities of restarting the program or task without loss of continuity.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt 0—Divide Error Exception (#DE)
Exception Class
Fault.
Description
Indicates the divisor operand for a DIV or IDIV instruction is 0 or that the result cannot be represented in the
number of bits specified for the destination operand.
Exception Error Code
None.
Saved Instruction Pointer
Saved contents of CS and EIP registers point to the instruction that generated the exception.
Program State Change
A program-state change does not accompany the divide error, because the exception occurs before the faulting
instruction is executed.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt 1—Debug Exception (#DB)
Trap or Fault. The exception handler can distinguish between traps or faults by examining the contents of DR6 and the other debug registers.
Exception Class
Description
Indicates that one or more of several debug-exception conditions has been detected. Whether the exception is a
fault or a trap depends on the condition (see Table 6-3). See Chapter 17, “Debug, Branch Profile, TSC, and
Resource Monitoring Features,” for detailed information about the debug exceptions.
Table 6-3. Debug Exception Conditions and Corresponding Exception Classes
Exception Condition
Exception Class
Instruction fetch breakpoint
Fault
Data read or write breakpoint
Trap
I/O read or write breakpoint
Trap
General detect condition (in conjunction with in-circuit emulation)
Fault
Single-step
Trap
Task-switch
Trap
Exception Error Code
None. An exception handler can examine the debug registers to determine which condition caused the exception.
Saved Instruction Pointer
Fault — Saved contents of CS and EIP registers point to the instruction that generated the exception.
Trap — Saved contents of CS and EIP registers point to the instruction following the instruction that generated the
exception.
Program State Change
Fault — A program-state change does not accompany the debug exception, because the exception occurs before
the faulting instruction is executed. The program can resume normal execution upon returning from the debug
exception handler.
Trap — A program-state change does accompany the debug exception, because the instruction or task switch being
executed is allowed to complete before the exception is generated. However, the new state of the program is not
corrupted and execution of the program can continue reliably.
Any debug exception inside an RTM region causes a transactional abort and, by default, redirects control flow to the
fallback instruction address. If advanced debugging of RTM transactional regions has been enabled, any transactional abort due to a debug exception instead causes execution to roll back to just before the XBEGIN instruction
and then delivers a #DB. See Section 16.3.7, “RTM-Enabled Debugger Support,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt 2—NMI Interrupt
Exception Class
Not applicable.
Description
The nonmaskable interrupt (NMI) is generated externally by asserting the processor’s NMI pin or through an NMI
request set by the I/O APIC to the local APIC. This interrupt causes the NMI interrupt handler to be called.
Exception Error Code
Not applicable.
Saved Instruction Pointer
The processor always takes an NMI interrupt on an instruction boundary. The saved contents of CS and EIP registers point to the next instruction to be executed at the point the interrupt is taken. See Section 6.5, “Exception
Classifications,” for more information about when the processor takes NMI interrupts.
Program State Change
The instruction executing when an NMI interrupt is received is completed before the NMI is generated. A program
or task can thus be restarted upon returning from an interrupt handler without loss of continuity, provided the
interrupt handler saves the state of the processor before handling the interrupt and restores the processor’s state
prior to a return.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt 3—Breakpoint Exception (#BP)
Exception Class
Trap.
Description
Indicates that a breakpoint instruction (INT 3, opcode CCH) was executed, causing a breakpoint trap to be generated. Typically, a debugger sets a breakpoint by replacing the first opcode byte of an instruction with the opcode
for the INT 3 instruction. (The INT 3 instruction is one byte long, which makes it easy to replace an opcode in a
code segment in RAM with the breakpoint opcode.) The operating system or a debugging tool can use a data
segment mapped to the same physical address space as the code segment to place an INT 3 instruction in places
where it is desired to call the debugger.
With the P6 family, Pentium, Intel486, and Intel386 processors, it is more convenient to set breakpoints with the
debug registers. (See Section 17.3.2, “Breakpoint Exception (#BP)—Interrupt Vector 3,” for information about the
breakpoint exception.) If more breakpoints are needed beyond what the debug registers allow, the INT 3 instruction can be used.
Any breakpoint exception inside an RTM region causes a transactional abort and, by default, redirects control flow
to the fallback instruction address. If advanced debugging of RTM transactional regions has been enabled, any
transactional abort due to a break exception instead causes execution to roll back to just before the XBEGIN
instruction and then delivers a debug exception (#DB) — not a breakpoint exception. See Section 16.3.7, “RTMEnabled Debugger Support,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
A breakpoint exception can also be generated by executing the INT n instruction with an operand of 3. The action
of this instruction (INT 3) is slightly different than that of the INT 3 instruction (see “INTn/INTO/INT3—Call to
Interrupt Procedure” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A).
Exception Error Code
None.
Saved Instruction Pointer
Saved contents of CS and EIP registers point to the instruction following the INT 3 instruction.
Program State Change
Even though the EIP points to the instruction following the breakpoint instruction, the state of the program is
essentially unchanged because the INT 3 instruction does not affect any register or memory locations. The
debugger can thus resume the suspended program by replacing the INT 3 instruction that caused the breakpoint
with the original opcode and decrementing the saved contents of the EIP register. Upon returning from the
debugger, program execution resumes with the replaced instruction.
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Interrupt 4—Overflow Exception (#OF)
Exception Class
Trap.
Description
Indicates that an overflow trap occurred when an INTO instruction was executed. The INTO instruction checks the
state of the OF flag in the EFLAGS register. If the OF flag is set, an overflow trap is generated.
Some arithmetic instructions (such as the ADD and SUB) perform both signed and unsigned arithmetic. These
instructions set the OF and CF flags in the EFLAGS register to indicate signed overflow and unsigned overflow,
respectively. When performing arithmetic on signed operands, the OF flag can be tested directly or the INTO
instruction can be used. The benefit of using the INTO instruction is that if the overflow exception is detected, an
exception handler can be called automatically to handle the overflow condition.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction following the INTO instruction.
Program State Change
Even though the EIP points to the instruction following the INTO instruction, the state of the program is essentially
unchanged because the INTO instruction does not affect any register or memory locations. The program can thus
resume normal execution upon returning from the overflow exception handler.
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Interrupt 5—BOUND Range Exceeded Exception (#BR)
Exception Class
Fault.
Description
Indicates that a BOUND-range-exceeded fault occurred when a BOUND instruction was executed. The BOUND
instruction checks that a signed array index is within the upper and lower bounds of an array located in memory. If
the array index is not within the bounds of the array, a BOUND-range-exceeded fault is generated.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the BOUND instruction that generated the exception.
Program State Change
A program-state change does not accompany the bounds-check fault, because the operands for the BOUND
instruction are not modified. Returning from the BOUND-range-exceeded exception handler causes the BOUND
instruction to be restarted.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt 6—Invalid Opcode Exception (#UD)
Exception Class
Fault.
Description
Indicates that the processor did one of the following things:
•
•
Attempted to execute an invalid or reserved opcode.
•
Attempted to execute an MMX or SSE/SSE2/SSE3 instruction on an Intel 64 or IA-32 processor that does not
support the MMX technology or SSE/SSE2/SSE3/SSSE3 extensions, respectively. CPUID feature flags MMX (bit
23), SSE (bit 25), SSE2 (bit 26), SSE3 (ECX, bit 0), SSSE3 (ECX, bit 9) indicate support for these extensions.
•
Attempted to execute an MMX instruction or SSE/SSE2/SSE3/SSSE3 SIMD instruction (with the exception of
the MOVNTI, PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, CLFLUSH, MONITOR, and MWAIT instructions)
when the EM flag in control register CR0 is set (1).
•
Attempted to execute an SSE/SE2/SSE3/SSSE3 instruction when the OSFXSR bit in control register CR4 is clear
(0). Note this does not include the following SSE/SSE2/SSE3 instructions: MASKMOVQ, MOVNTQ, MOVNTI,
PREFETCHh, SFENCE, LFENCE, MFENCE, and CLFLUSH; or the 64-bit versions of the PAVGB, PAVGW, PEXTRW,
PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW, PADDQ, PSUBQ,
PALIGNR, PABSB, PABSD, PABSW, PHADDD, PHADDSW, PHADDW, PHSUBD, PHSUBSW, PHSUBW,
PMADDUBSM, PMULHRSW, PSHUFB, PSIGNB, PSIGND, and PSIGNW.
•
Attempted to execute an SSE/SSE2/SSE3/SSSE3 instruction on an Intel 64 or IA-32 processor that caused a
SIMD floating-point exception when the OSXMMEXCPT bit in control register CR4 is clear (0).
•
Executed a UD2 instruction. Note that even though it is the execution of the UD2 instruction that causes the
invalid opcode exception, the saved instruction pointer will still points at the UD2 instruction.
•
Detected a LOCK prefix that precedes an instruction that may not be locked or one that may be locked but the
destination operand is not a memory location.
•
Attempted to execute an LLDT, SLDT, LTR, STR, LSL, LAR, VERR, VERW, or ARPL instruction while in realaddress or virtual-8086 mode.
•
Attempted to execute the RSM instruction when not in SMM mode.
Attempted to execute an instruction with an operand type that is invalid for its accompanying opcode; for
example, the source operand for a LES instruction is not a memory location.
In Intel 64 and IA-32 processors that implement out-of-order execution microarchitectures, this exception is not
generated until an attempt is made to retire the result of executing an invalid instruction; that is, decoding and
speculatively attempting to execute an invalid opcode does not generate this exception. Likewise, in the Pentium
processor and earlier IA-32 processors, this exception is not generated as the result of prefetching and preliminary
decoding of an invalid instruction. (See Section 6.5, “Exception Classifications,” for general rules for taking of interrupts and exceptions.)
The opcodes D6 and F1 are undefined opcodes reserved by the Intel 64 and IA-32 architectures. These opcodes,
even though undefined, do not generate an invalid opcode exception.
The UD2 instruction is guaranteed to generate an invalid opcode exception.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction that generated the exception.
Program State Change
A program-state change does not accompany an invalid-opcode fault, because the invalid instruction is not
executed.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt 7—Device Not Available Exception (#NM)
Exception Class
Fault.
Description
Indicates one of the following things:
The device-not-available exception is generated by either of three conditions:
•
The processor executed an x87 FPU floating-point instruction while the EM flag in control register CR0 was set
(1). See the paragraph below for the special case of the WAIT/FWAIT instruction.
•
The processor executed a WAIT/FWAIT instruction while the MP and TS flags of register CR0 were set,
regardless of the setting of the EM flag.
•
The processor executed an x87 FPU, MMX, or SSE/SSE2/SSE3 instruction (with the exception of MOVNTI,
PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, and CLFLUSH) while the TS flag in control register CR0 was set
and the EM flag is clear.
The EM flag is set when the processor does not have an internal x87 FPU floating-point unit. A device-not-available
exception is then generated each time an x87 FPU floating-point instruction is encountered, allowing an exception
handler to call floating-point instruction emulation routines.
The TS flag indicates that a context switch (task switch) has occurred since the last time an x87 floating-point,
MMX, or SSE/SSE2/SSE3 instruction was executed; but that the context of the x87 FPU, XMM, and MXCSR registers
were not saved. When the TS flag is set and the EM flag is clear, the processor generates a device-not-available
exception each time an x87 floating-point, MMX, or SSE/SSE2/SSE3 instruction is encountered (with the exception
of the instructions listed above). The exception handler can then save the context of the x87 FPU, XMM, and MXCSR
registers before it executes the instruction. See Section 2.5, “Control Registers,” for more information about the TS
flag.
The MP flag in control register CR0 is used along with the TS flag to determine if WAIT or FWAIT instructions should
generate a device-not-available exception. It extends the function of the TS flag to the WAIT and FWAIT instructions, giving the exception handler an opportunity to save the context of the x87 FPU before the WAIT or FWAIT
instruction is executed. The MP flag is provided primarily for use with the Intel 286 and Intel386 DX processors. For
programs running on the Pentium 4, Intel Xeon, P6 family, Pentium, or Intel486 DX processors, or the Intel 487 SX
coprocessors, the MP flag should always be set; for programs running on the Intel486 SX processor, the MP flag
should be clear.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the floating-point instruction or the WAIT/FWAIT instruction
that generated the exception.
Program State Change
A program-state change does not accompany a device-not-available fault, because the instruction that generated
the exception is not executed.
If the EM flag is set, the exception handler can then read the floating-point instruction pointed to by the EIP and
call the appropriate emulation routine.
If the MP and TS flags are set or the TS flag alone is set, the exception handler can save the context of the x87 FPU,
clear the TS flag, and continue execution at the interrupted floating-point or WAIT/FWAIT instruction.
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Interrupt 8—Double Fault Exception (#DF)
Exception Class
Abort.
Description
Indicates that the processor detected a second exception while calling an exception handler for a prior exception.
Normally, when the processor detects another exception while trying to call an exception handler, the two exceptions can be handled serially. If, however, the processor cannot handle them serially, it signals the double-fault
exception. To determine when two faults need to be signalled as a double fault, the processor divides the exceptions into three classes: benign exceptions, contributory exceptions, and page faults (see Table 6-4).
Table 6-4. Interrupt and Exception Classes
Class
Vector Number
Description
Benign Exceptions and Interrupts
1
2
3
4
5
6
7
9
16
17
18
Debug
NMI Interrupt
Breakpoint
Overflow
BOUND Range Exceeded
Invalid Opcode
Device Not Available
Coprocessor Segment Overrun
Floating-Point Error
Alignment Check
Machine Check
19
All
All
SIMD floating-point
INT n
INTR
Contributory Exceptions
0
10
11
12
13
Divide Error
Invalid TSS
Segment Not Present
Stack Fault
General Protection
Page Faults
14
20
Page Fault
Virtualization Exception
Table 6-5 shows the various combinations of exception classes that cause a double fault to be generated. A doublefault exception falls in the abort class of exceptions. The program or task cannot be restarted or resumed. The
double-fault handler can be used to collect diagnostic information about the state of the machine and/or, when
possible, to shut the application and/or system down gracefully or restart the system.
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A segment or page fault may be encountered while prefetching instructions; however, this behavior is outside the
domain of Table 6-5. Any further faults generated while the processor is attempting to transfer control to the
appropriate fault handler could still lead to a double-fault sequence.
Table 6-5. Conditions for Generating a Double Fault
Second Exception
First Exception
Benign
Contributory
Page Fault
Benign
Handle Exceptions Serially
Handle Exceptions Serially
Handle Exceptions Serially
Contributory
Handle Exceptions Serially
Generate a Double Fault
Handle Exceptions Serially
Page Fault
Handle Exceptions Serially
Generate a Double Fault
Generate a Double Fault
Double Fault
Handle Exceptions Serially
Enter Shutdown Mode
Enter Shutdown Mode
If another contributory or page fault exception occurs while attempting to call the double-fault handler, the
processor enters shutdown mode. This mode is similar to the state following execution of an HLT instruction. In this
mode, the processor stops executing instructions until an NMI interrupt, SMI interrupt, hardware reset, or INIT# is
received. The processor generates a special bus cycle to indicate that it has entered shutdown mode. Software
designers may need to be aware of the response of hardware when it goes into shutdown mode. For example,
hardware may turn on an indicator light on the front panel, generate an NMI interrupt to record diagnostic information, invoke reset initialization, generate an INIT initialization, or generate an SMI. If any events are pending
during shutdown, they will be handled after an wake event from shutdown is processed (for example, A20M# interrupts).
If a shutdown occurs while the processor is executing an NMI interrupt handler, then only a hardware reset can
restart the processor. Likewise, if the shutdown occurs while executing in SMM, a hardware reset must be used to
restart the processor.
Exception Error Code
Zero. The processor always pushes an error code of 0 onto the stack of the double-fault handler.
Saved Instruction Pointer
The saved contents of CS and EIP registers are undefined.
Program State Change
A program-state following a double-fault exception is undefined. The program or task cannot be resumed or
restarted. The only available action of the double-fault exception handler is to collect all possible context information for use in diagnostics and then close the application and/or shut down or reset the processor.
If the double fault occurs when any portion of the exception handling machine state is corrupted, the handler
cannot be invoked and the processor must be reset.
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Interrupt 9—Coprocessor Segment Overrun
Exception Class
Abort. (Intel reserved; do not use. Recent IA-32 processors do not generate this
exception.)
Description
Indicates that an Intel386 CPU-based systems with an Intel 387 math coprocessor detected a page or segment
violation while transferring the middle portion of an Intel 387 math coprocessor operand. The P6 family, Pentium,
and Intel486 processors do not generate this exception; instead, this condition is detected with a general protection exception (#GP), interrupt 13.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction that generated the exception.
Program State Change
A program-state following a coprocessor segment-overrun exception is undefined. The program or task cannot
be resumed or restarted. The only available action of the exception handler is to save the instruction pointer and
reinitialize the x87 FPU using the FNINIT instruction.
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Interrupt 10—Invalid TSS Exception (#TS)
Exception Class
Fault.
Description
Indicates that there was an error related to a TSS. Such an error might be detected during a task switch or during
the execution of instructions that use information from a TSS. Table 6-6 shows the conditions that cause an invalid
TSS exception to be generated.
Table 6-6. Invalid TSS Conditions
Error Code Index
Invalid Condition
TSS segment selector index
The TSS segment limit is less than 67H for 32-bit TSS or less than 2CH for 16-bit TSS.
TSS segment selector index
During an IRET task switch, the TI flag in the TSS segment selector indicates the LDT.
TSS segment selector index
During an IRET task switch, the TSS segment selector exceeds descriptor table limit.
TSS segment selector index
During an IRET task switch, the busy flag in the TSS descriptor indicates an inactive task.
TSS segment selector index
During an IRET task switch, an attempt to load the backlink limit faults.
TSS segment selector index
During an IRET task switch, the backlink is a NULL selector.
TSS segment selector index
During an IRET task switch, the backlink points to a descriptor which is not a busy TSS.
TSS segment selector index
The new TSS descriptor is beyond the GDT limit.
TSS segment selector index
The new TSS descriptor is not writable.
TSS segment selector index
Stores to the old TSS encounter a fault condition.
TSS segment selector index
The old TSS descriptor is not writable for a jump or IRET task switch.
TSS segment selector index
The new TSS backlink is not writable for a call or exception task switch.
TSS segment selector index
The new TSS selector is null on an attempt to lock the new TSS.
TSS segment selector index
The new TSS selector has the TI bit set on an attempt to lock the new TSS.
TSS segment selector index
The new TSS descriptor is not an available TSS descriptor on an attempt to lock the new
TSS.
LDT segment selector index
LDT or LDT not present.
Stack segment selector index
The stack segment selector exceeds descriptor table limit.
Stack segment selector index
The stack segment selector is NULL.
Stack segment selector index
The stack segment descriptor is a non-data segment.
Stack segment selector index
The stack segment is not writable.
Stack segment selector index
The stack segment DPL ≠ CPL.
Stack segment selector index
The stack segment selector RPL ≠ CPL.
Code segment selector index
The code segment selector exceeds descriptor table limit.
Code segment selector index
The code segment selector is NULL.
Code segment selector index
The code segment descriptor is not a code segment type.
Code segment selector index
The nonconforming code segment DPL ≠ CPL.
Code segment selector index
The conforming code segment DPL is greater than CPL.
Data segment selector index
The data segment selector exceeds the descriptor table limit.
Data segment selector index
The data segment descriptor is not a readable code or data type.
Data segment selector index
The data segment descriptor is a nonconforming code type and RPL > DPL.
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Table 6-6. Invalid TSS Conditions (Contd.)
Error Code Index
Invalid Condition
Data segment selector index
The data segment descriptor is a nonconforming code type and CPL > DPL.
TSS segment selector index
The TSS segment selector is NULL for LTR.
TSS segment selector index
The TSS segment selector has the TI bit set for LTR.
TSS segment selector index
The TSS segment descriptor/upper descriptor is beyond the GDT segment limit.
TSS segment selector index
The TSS segment descriptor is not an available TSS type.
TSS segment selector index
The TSS segment descriptor is an available 286 TSS type in IA-32e mode.
TSS segment selector index
The TSS segment upper descriptor is not the correct type.
TSS segment selector index
The TSS segment descriptor contains a non-canonical base.
TSS segment selector index
There is a limit violation in attempting to load SS selector or ESP from a TSS on a call or
exception which changes privilege levels in legacy mode.
TSS segment selector index
There is a limit violation or canonical fault in attempting to load RSP or IST from a TSS on a
call or exception which changes privilege levels in IA-32e mode.
This exception can generated either in the context of the original task or in the context of the new task (see Section
7.3, “Task Switching”). Until the processor has completely verified the presence of the new TSS, the exception is
generated in the context of the original task. Once the existence of the new TSS is verified, the task switch is
considered complete. Any invalid-TSS conditions detected after this point are handled in the context of the new
task. (A task switch is considered complete when the task register is loaded with the segment selector for the new
TSS and, if the switch is due to a procedure call or interrupt, the previous task link field of the new TSS references
the old TSS.)
The invalid-TSS handler must be a task called using a task gate. Handling this exception inside the faulting TSS
context is not recommended because the processor state may not be consistent.
Exception Error Code
An error code containing the segment selector index for the segment descriptor that caused the violation is pushed
onto the stack of the exception handler. If the EXT flag is set, it indicates that the exception was caused by an event
external to the currently running program (for example, if an external interrupt handler using a task gate
attempted a task switch to an invalid TSS).
Saved Instruction Pointer
If the exception condition was detected before the task switch was carried out, the saved contents of CS and EIP
registers point to the instruction that invoked the task switch. If the exception condition was detected after the task
switch was carried out, the saved contents of CS and EIP registers point to the first instruction of the new task.
Program State Change
The ability of the invalid-TSS handler to recover from the fault depends on the error condition than causes the fault.
See Section 7.3, “Task Switching,” for more information on the task switch process and the possible recovery
actions that can be taken.
If an invalid TSS exception occurs during a task switch, it can occur before or after the commit-to-new-task point.
If it occurs before the commit point, no program state change occurs. If it occurs after the commit point (when the
segment descriptor information for the new segment selectors have been loaded in the segment registers), the
processor will load all the state information from the new TSS before it generates the exception. During a task
switch, the processor first loads all the segment registers with segment selectors from the TSS, then checks their
contents for validity. If an invalid TSS exception is discovered, the remaining segment registers are loaded but not
checked for validity and therefore may not be usable for referencing memory. The invalid TSS handler should not
rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and GS registers without causing
another exception. The exception handler should load all segment registers before trying to resume the new task;
otherwise, general-protection exceptions (#GP) may result later under conditions that make diagnosis more diffi-
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cult. The Intel recommended way of dealing situation is to use a task for the invalid TSS exception handler. The
task switch back to the interrupted task from the invalid-TSS exception-handler task will then cause the processor
to check the registers as it loads them from the TSS.
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Interrupt 11—Segment Not Present (#NP)
Exception Class
Fault.
Description
Indicates that the present flag of a segment or gate descriptor is clear. The processor can generate this exception
during any of the following operations:
•
While attempting to load CS, DS, ES, FS, or GS registers. [Detection of a not-present segment while loading the
SS register causes a stack fault exception (#SS) to be generated.] This situation can occur while performing a
task switch.
•
While attempting to load the LDTR using an LLDT instruction. Detection of a not-present LDT while loading the
LDTR during a task switch operation causes an invalid-TSS exception (#TS) to be generated.
•
•
When executing the LTR instruction and the TSS is marked not present.
While attempting to use a gate descriptor or TSS that is marked segment-not-present, but is otherwise valid.
An operating system typically uses the segment-not-present exception to implement virtual memory at the
segment level. If the exception handler loads the segment and returns, the interrupted program or task resumes
execution.
A not-present indication in a gate descriptor, however, does not indicate that a segment is not present (because
gates do not correspond to segments). The operating system may use the present flag for gate descriptors to
trigger exceptions of special significance to the operating system.
A contributory exception or page fault that subsequently referenced a not-present segment would cause a double
fault (#DF) to be generated instead of #NP.
Exception Error Code
An error code containing the segment selector index for the segment descriptor that caused the violation is pushed
onto the stack of the exception handler. If the EXT flag is set, it indicates that the exception resulted from either:
•
an external event (NMI or INTR) that caused an interrupt, which subsequently referenced a not-present
segment
•
a benign exception that subsequently referenced a not-present segment
The IDT flag is set if the error code refers to an IDT entry. This occurs when the IDT entry for an interrupt being
serviced references a not-present gate. Such an event could be generated by an INT instruction or a hardware
interrupt.
Saved Instruction Pointer
The saved contents of CS and EIP registers normally point to the instruction that generated the exception. If the
exception occurred while loading segment descriptors for the segment selectors in a new TSS, the CS and EIP
registers point to the first instruction in the new task. If the exception occurred while accessing a gate descriptor,
the CS and EIP registers point to the instruction that invoked the access (for example a CALL instruction that references a call gate).
Program State Change
If the segment-not-present exception occurs as the result of loading a register (CS, DS, SS, ES, FS, GS, or LDTR),
a program-state change does accompany the exception because the register is not loaded. Recovery from this
exception is possible by simply loading the missing segment into memory and setting the present flag in the
segment descriptor.
If the segment-not-present exception occurs while accessing a gate descriptor, a program-state change does not
accompany the exception. Recovery from this exception is possible merely by setting the present flag in the gate
descriptor.
If a segment-not-present exception occurs during a task switch, it can occur before or after the commit-to-newtask point (see Section 7.3, “Task Switching”). If it occurs before the commit point, no program state change
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occurs. If it occurs after the commit point, the processor will load all the state information from the new TSS
(without performing any additional limit, present, or type checks) before it generates the exception. The segmentnot-present exception handler should not rely on being able to use the segment selectors found in the CS, SS, DS,
ES, FS, and GS registers without causing another exception. (See the Program State Change description for “Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.)
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Interrupt 12—Stack Fault Exception (#SS)
Exception Class
Fault.
Description
Indicates that one of the following stack related conditions was detected:
•
A limit violation is detected during an operation that refers to the SS register. Operations that can cause a limit
violation include stack-oriented instructions such as POP, PUSH, CALL, RET, IRET, ENTER, and LEAVE, as well as
other memory references which implicitly or explicitly use the SS register (for example, MOV AX, [BP+6] or
MOV AX, SS:[EAX+6]). The ENTER instruction generates this exception when there is not enough stack space
for allocating local variables.
•
A not-present stack segment is detected when attempting to load the SS register. This violation can occur
during the execution of a task switch, a CALL instruction to a different privilege level, a return to a different
privilege level, an LSS instruction, or a MOV or POP instruction to the SS register.
•
A canonical violation is detected in 64-bit mode during an operation that reference memory using the stack
pointer register containing a non-canonical memory address.
Recovery from this fault is possible by either extending the limit of the stack segment (in the case of a limit violation) or loading the missing stack segment into memory (in the case of a not-present violation.
In the case of a canonical violation that was caused intentionally by software, recovery is possible by loading the
correct canonical value into RSP. Otherwise, a canonical violation of the address in RSP likely reflects some register
corruption in the software.
Exception Error Code
If the exception is caused by a not-present stack segment or by overflow of the new stack during an inter-privilegelevel call, the error code contains a segment selector for the segment that caused the exception. Here, the exception handler can test the present flag in the segment descriptor pointed to by the segment selector to determine
the cause of the exception. For a normal limit violation (on a stack segment already in use) the error code is set to
0.
Saved Instruction Pointer
The saved contents of CS and EIP registers generally point to the instruction that generated the exception.
However, when the exception results from attempting to load a not-present stack segment during a task switch,
the CS and EIP registers point to the first instruction of the new task.
Program State Change
A program-state change does not generally accompany a stack-fault exception, because the instruction that generated the fault is not executed. Here, the instruction can be restarted after the exception handler has corrected the
stack fault condition.
If a stack fault occurs during a task switch, it occurs after the commit-to-new-task point (see Section 7.3, “Task
Switching”). Here, the processor loads all the state information from the new TSS (without performing any additional limit, present, or type checks) before it generates the exception. The stack fault handler should thus not rely
on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and GS registers without causing
another exception. The exception handler should check all segment registers before trying to resume the new
task; otherwise, general protection faults may result later under conditions that are more difficult to diagnose. (See
the Program State Change description for “Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for additional
information on how to handle this situation.)
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Interrupt 13—General Protection Exception (#GP)
Exception Class
Fault.
Description
Indicates that the processor detected one of a class of protection violations called “general-protection violations.”
The conditions that cause this exception to be generated comprise all the protection violations that do not cause
other exceptions to be generated (such as, invalid-TSS, segment-not-present, stack-fault, or page-fault exceptions). The following conditions cause general-protection exceptions to be generated:
•
•
Exceeding the segment limit when accessing the CS, DS, ES, FS, or GS segments.
•
•
•
•
Transferring execution to a segment that is not executable.
•
•
•
•
•
•
•
Loading the SS, DS, ES, FS, or GS register with a segment selector for a system segment.
•
•
Violating any of the privilege rules described in Chapter 5, “Protection.”
•
•
•
•
Loading the CR0 register with a set PG flag (paging enabled) and a clear PE flag (protection disabled).
•
•
Attempting to write a 1 into a reserved bit of CR4.
•
•
•
•
Attempting to execute SGDT, SIDT, SLDT, SMSW, or STR when CR4.UMIP = 1 and the CPL is not equal to 0.
•
•
The segment selector in a call, interrupt, or trap gate does not point to a code segment.
•
•
The segment selector operand in the LTR instruction is local or points to a TSS that is not available.
Exceeding the segment limit when referencing a descriptor table (except during a task switch or a stack
switch).
Writing to a code segment or a read-only data segment.
Reading from an execute-only code segment.
Loading the SS register with a segment selector for a read-only segment (unless the selector comes from a TSS
during a task switch, in which case an invalid-TSS exception occurs).
Loading the DS, ES, FS, or GS register with a segment selector for an execute-only code segment.
Loading the SS register with the segment selector of an executable segment or a null segment selector.
Loading the CS register with a segment selector for a data segment or a null segment selector.
Accessing memory using the DS, ES, FS, or GS register when it contains a null segment selector.
Switching to a busy task during a call or jump to a TSS.
Using a segment selector on a non-IRET task switch that points to a TSS descriptor in the current LDT. TSS
descriptors can only reside in the GDT. This condition causes a #TS exception during an IRET task switch.
Exceeding the instruction length limit of 15 bytes (this only can occur when redundant prefixes are placed
before an instruction).
Loading the CR0 register with a set NW flag and a clear CD flag.
Referencing an entry in the IDT (following an interrupt or exception) that is not an interrupt, trap, or task gate.
Attempting to access an interrupt or exception handler through an interrupt or trap gate from virtual-8086
mode when the handler’s code segment DPL is greater than 0.
Attempting to execute a privileged instruction when the CPL is not equal to 0 (see Section 5.9, “Privileged
Instructions,” for a list of privileged instructions).
Writing to a reserved bit in an MSR.
Accessing a gate that contains a null segment selector.
Executing the INT n instruction when the CPL is greater than the DPL of the referenced interrupt, trap, or task
gate.
The segment selector operand in the LLDT instruction is a local type (TI flag is set) or does not point to a
segment descriptor of the LDT type.
The target code-segment selector for a call, jump, or return is null.
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•
If the PAE and/or PSE flag in control register CR4 is set and the processor detects any reserved bits in a pagedirectory-pointer-table entry set to 1. These bits are checked during a write to control registers CR0, CR3, or
CR4 that causes a reloading of the page-directory-pointer-table entry.
•
•
Attempting to write a non-zero value into the reserved bits of the MXCSR register.
Executing an SSE/SSE2/SSE3 instruction that attempts to access a 128-bit memory location that is not aligned
on a 16-byte boundary when the instruction requires 16-byte alignment. This condition also applies to the stack
segment.
A program or task can be restarted following any general-protection exception. If the exception occurs while
attempting to call an interrupt handler, the interrupted program can be restartable, but the interrupt may be lost.
Exception Error Code
The processor pushes an error code onto the exception handler's stack. If the fault condition was detected while
loading a segment descriptor, the error code contains a segment selector to or IDT vector number for the
descriptor; otherwise, the error code is 0. The source of the selector in an error code may be any of the following:
•
•
•
•
An operand of the instruction.
A selector from a gate which is the operand of the instruction.
A selector from a TSS involved in a task switch.
IDT vector number.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction that generated the exception.
Program State Change
In general, a program-state change does not accompany a general-protection exception, because the invalid
instruction or operation is not executed. An exception handler can be designed to correct all of the conditions that
cause general-protection exceptions and restart the program or task without any loss of program continuity.
If a general-protection exception occurs during a task switch, it can occur before or after the commit-to-new-task
point (see Section 7.3, “Task Switching”). If it occurs before the commit point, no program state change occurs. If
it occurs after the commit point, the processor will load all the state information from the new TSS (without
performing any additional limit, present, or type checks) before it generates the exception. The general-protection
exception handler should thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS,
and GS registers without causing another exception. (See the Program State Change description for “Interrupt
10—Invalid TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.)
General Protection Exception in 64-bit Mode
The following conditions cause general-protection exceptions in 64-bit mode:
•
•
•
•
•
If the memory address is in a non-canonical form.
•
•
•
•
•
If the EFLAGS.NT bit is set in IRET.
If a segment descriptor memory address is in non-canonical form.
If the target offset in a destination operand of a call or jmp is in a non-canonical form.
If a code segment or 64-bit call gate overlaps non-canonical space.
If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the L-bit set and the
D-bit clear.
If the stack segment selector of IRET is null when going back to compatibility mode.
If the stack segment selector of IRET is null going back to CPL3 and 64-bit mode.
If a null stack segment selector RPL of IRET is not equal to CPL going back to non-CPL3 and 64-bit mode.
If the proposed new code segment descriptor of IRET has both the D-bit and the L-bit set.
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•
If the segment descriptor pointed to by the segment selector in the destination operand is a code segment and
it has both the D-bit and the L-bit set.
•
•
•
•
•
•
If the segment descriptor from a 64-bit call gate is in non-canonical space.
•
•
If an attempt is made to clear CR0.PG while IA-32e mode is enabled.
If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.
If the type field of the upper 64 bits of a 64-bit call gate is not 0.
If an attempt is made to load a null selector in the SS register in compatibility mode.
If an attempt is made to load null selector in the SS register in CPL3 and 64-bit mode.
If an attempt is made to load a null selector in the SS register in non-CPL3 and 64-bit mode where RPL is not
equal to CPL.
If an attempt is made to set a reserved bit in CR3, CR4 or CR8.
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Interrupt 14—Page-Fault Exception (#PF)
Exception Class
Fault.
Description
Indicates that, with paging enabled (the PG flag in the CR0 register is set), the processor detected one of the
following conditions while using the page-translation mechanism to translate a linear address to a physical
address:
•
The P (present) flag in a page-directory or page-table entry needed for the address translation is clear,
indicating that a page table or the page containing the operand is not present in physical memory.
•
The procedure does not have sufficient privilege to access the indicated page (that is, a procedure running in
user mode attempts to access a supervisor-mode page). If the SMAP flag is set in CR4, a page fault may also
be triggered by code running in supervisor mode that tries to access data at a user-mode address. If the PKE
flag is set in CR4, the PKRU register may cause page faults on data accesses to user-mode addresses with
certain protection keys.
•
Code running in user mode attempts to write to a read-only page. If the WP flag is set in CR0, the page fault
will also be triggered by code running in supervisor mode that tries to write to a read-only page.
•
An instruction fetch to a linear address that translates to a physical address in a memory page with the
execute-disable bit set (for information about the execute-disable bit, see Chapter 4, “Paging”). If the SMEP
flag is set in CR4, a page fault will also be triggered by code running in supervisor mode that tries to fetch an
instruction from a user-mode address.
•
•
One or more reserved bits in paging-structure entry are set to 1. See description below of RSVD error code flag.
An enclave access violates one of the specified access-control requirements. See Section 38.3, “Access-control
Requirements” and Section 38.19, “Enclave Page Cache Map (EPCM)” in Chapter 38, “Enclave Access Control
and Data Structures.” In this case, the exception is called an SGX-induced page fault. The processor uses the
error code (below) to distinguish SGX-induced page faults from ordinary page faults.
The exception handler can recover from page-not-present conditions and restart the program or task without any
loss of program continuity. It can also restart the program or task after a privilege violation, but the problem that
caused the privilege violation may be uncorrectable.
See also: Section 4.7, “Page-Fault Exceptions.”
Exception Error Code
Yes (special format). The processor provides the page-fault handler with two items of information to aid in diagnosing the exception and recovering from it:
•
An error code on the stack. The error code for a page fault has a format different from that for other exceptions
(see Figure 6-9). The processor establishes the bits in the error code as follows:
— P flag (bit 0).
This flag is 0 if there is no translation for the linear address because the P flag was 0 in one of the pagingstructure entries used to translate that address.
— W/R (bit 1).
If the access causing the page-fault exception was a write, this flag is 1; otherwise, it is 0. This flag
describes the access causing the page-fault exception, not the access rights specified by paging.
— U/S (bit 2).
If a user-mode access caused the page-fault exception, this flag is 1; it is 0 if a supervisor-mode access did
so. This flag describes the access causing the page-fault exception, not the access rights specified by
paging.
— RSVD flag (bit 3).
This flag is 1 if there is no translation for the linear address because a reserved bit was set in one of the
paging-structure entries used to translate that address.
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INTERRUPT AND EXCEPTION HANDLING
— I/D flag (bit 4).
This flag is 1 if the access causing the page-fault exception was an instruction fetch. This flag describes the
access causing the page-fault exception, not the access rights specified by paging.
— PK flag (bit 5).
This flag is 1 if the access causing the page-fault exception was a data access to a user-mode address with
protection key disallowed by the value of the PKRU register.
— SGX flag (bit 15).
This flag is 1 if the exception is unrelated to paging and resulted from violation of SGX-specific accesscontrol requirements. Because such a violation can occur only if there is no ordinary page fault, this flag is
set only if the P flag (bit 0) is 1 and the RSVD flag (bit 3) and the PK flag (bit 5) are both 0.
See Section 4.6, “Access Rights” and Section 4.7, “Page-Fault Exceptions” for more information about pagefault exceptions and the error codes that they produce.
31
5 4 3 2 1 0
15
Reserved
P
W/R
U/S
RSVD
I/D
PK
SGX
Reserved
P
0 The fault was caused by a non-present page.
1 The fault was caused by a page-level protection violation.
W/R
0 The access causing the fault was a read.
1 The access causing the fault was a write.
U/S
0 A supervisor-mode access caused the fault.
1 A user-mode access caused the fault.
RSVD
0 The fault was not caused by reserved bit violation.
1 The fault was caused by a reserved bit set to 1 in some
paging-structure entry.
I/D
0 The fault was not caused by an instruction fetch.
1 The fault was caused by an instruction fetch.
PK
0 The fault was not caused by protection keys.
1 There was a protection-key violation.
SGX
0 The fault is not related to SGX.
1 The fault resulted from violation of SGX-specific access-control
requirements.
Figure 6-9. Page-Fault Error Code
•
The contents of the CR2 register. The processor loads the CR2 register with the 32-bit linear address that
generated the exception. The page-fault handler can use this address to locate the corresponding page
directory and page-table entries. Another page fault can potentially occur during execution of the page-fault
handler; the handler should save the contents of the CR2 register before a second page fault can occur.1 If a
page fault is caused by a page-level protection violation, the access flag in the page-directory entry is set when
the fault occurs. The behavior of IA-32 processors regarding the access flag in the corresponding page-table
entry is model specific and not architecturally defined.
1. Processors update CR2 whenever a page fault is detected. If a second page fault occurs while an earlier page fault is being delivered, the faulting linear address of the second fault will overwrite the contents of CR2 (replacing the previous address). These
updates to CR2 occur even if the page fault results in a double fault or occurs during the delivery of a double fault.
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INTERRUPT AND EXCEPTION HANDLING
Saved Instruction Pointer
The saved contents of CS and EIP registers generally point to the instruction that generated the exception. If the
page-fault exception occurred during a task switch, the CS and EIP registers may point to the first instruction of the
new task (as described in the following “Program State Change” section).
Program State Change
A program-state change does not normally accompany a page-fault exception, because the instruction that causes
the exception to be generated is not executed. After the page-fault exception handler has corrected the violation
(for example, loaded the missing page into memory), execution of the program or task can be resumed.
When a page-fault exception is generated during a task switch, the program-state may change, as follows. During
a task switch, a page-fault exception can occur during any of following operations:
•
•
•
•
•
While writing the state of the original task into the TSS of that task.
While reading the GDT to locate the TSS descriptor of the new task.
While reading the TSS of the new task.
While reading segment descriptors associated with segment selectors from the new task.
While reading the LDT of the new task to verify the segment registers stored in the new TSS.
In the last two cases the exception occurs in the context of the new task. The instruction pointer refers to the first
instruction of the new task, not to the instruction which caused the task switch (or the last instruction to be
executed, in the case of an interrupt). If the design of the operating system permits page faults to occur during
task-switches, the page-fault handler should be called through a task gate.
If a page fault occurs during a task switch, the processor will load all the state information from the new TSS
(without performing any additional limit, present, or type checks) before it generates the exception. The page-fault
handler should thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and GS
registers without causing another exception. (See the Program State Change description for “Interrupt 10—Invalid
TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.)
Additional Exception-Handling Information
Special care should be taken to ensure that an exception that occurs during an explicit stack switch does not cause
the processor to use an invalid stack pointer (SS:ESP). Software written for 16-bit IA-32 processors often use a
pair of instructions to change to a new stack, for example:
MOV SS, AX
MOV SP, StackTop
When executing this code on one of the 32-bit IA-32 processors, it is possible to get a page fault, general-protection fault (#GP), or alignment check fault (#AC) after the segment selector has been loaded into the SS register
but before the ESP register has been loaded. At this point, the two parts of the stack pointer (SS and ESP) are
inconsistent. The new stack segment is being used with the old stack pointer.
The processor does not use the inconsistent stack pointer if the exception handler switches to a well defined stack
(that is, the handler is a task or a more privileged procedure). However, if the exception handler is called at the
same privilege level and from the same task, the processor will attempt to use the inconsistent stack pointer.
In systems that handle page-fault, general-protection, or alignment check exceptions within the faulting task (with
trap or interrupt gates), software executing at the same privilege level as the exception handler should initialize a
new stack by using the LSS instruction rather than a pair of MOV instructions, as described earlier in this note.
When the exception handler is running at privilege level 0 (the normal case), the problem is limited to procedures
or tasks that run at privilege level 0, typically the kernel of the operating system.
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Interrupt 16—x87 FPU Floating-Point Error (#MF)
Exception Class
Fault.
Description
Indicates that the x87 FPU has detected a floating-point error. The NE flag in the register CR0 must be set for an
interrupt 16 (floating-point error exception) to be generated. (See Section 2.5, “Control Registers,” for a detailed
description of the NE flag.)
NOTE
SIMD floating-point exceptions (#XM) are signaled through interrupt 19.
While executing x87 FPU instructions, the x87 FPU detects and reports six types of floating-point error conditions:
•
Invalid operation (#I)
— Stack overflow or underflow (#IS)
— Invalid arithmetic operation (#IA)
•
•
•
•
•
Divide-by-zero (#Z)
Denormalized operand (#D)
Numeric overflow (#O)
Numeric underflow (#U)
Inexact result (precision) (#P)
Each of these error conditions represents an x87 FPU exception type, and for each of exception type, the x87 FPU
provides a flag in the x87 FPU status register and a mask bit in the x87 FPU control register. If the x87 FPU detects
a floating-point error and the mask bit for the exception type is set, the x87 FPU handles the exception automatically by generating a predefined (default) response and continuing program execution. The default responses have
been designed to provide a reasonable result for most floating-point applications.
If the mask for the exception is clear and the NE flag in register CR0 is set, the x87 FPU does the following:
1. Sets the necessary flag in the FPU status register.
2. Waits until the next “waiting” x87 FPU instruction or WAIT/FWAIT instruction is encountered in the program’s
instruction stream.
3. Generates an internal error signal that cause the processor to generate a floating-point exception (#MF).
Prior to executing a waiting x87 FPU instruction or the WAIT/FWAIT instruction, the x87 FPU checks for pending
x87 FPU floating-point exceptions (as described in step 2 above). Pending x87 FPU floating-point exceptions are
ignored for “non-waiting” x87 FPU instructions, which include the FNINIT, FNCLEX, FNSTSW, FNSTSW AX, FNSTCW,
FNSTENV, and FNSAVE instructions. Pending x87 FPU exceptions are also ignored when executing the state
management instructions FXSAVE and FXRSTOR.
All of the x87 FPU floating-point error conditions can be recovered from. The x87 FPU floating-point-error exception
handler can determine the error condition that caused the exception from the settings of the flags in the x87 FPU
status word. See “Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for more information on handling x87 FPU floating-point exceptions.
Exception Error Code
None. The x87 FPU provides its own error information.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the floating-point or WAIT/FWAIT instruction that was about to
be executed when the floating-point-error exception was generated. This is not the faulting instruction in which the
error condition was detected. The address of the faulting instruction is contained in the x87 FPU instruction pointer
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INTERRUPT AND EXCEPTION HANDLING
register. See Section 8.1.8, “x87 FPU Instruction and Data (Operand) Pointers” in Chapter 8 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about information the FPU saves
for use in handling floating-point-error exceptions.
Program State Change
A program-state change generally accompanies an x87 FPU floating-point exception because the handling of the
exception is delayed until the next waiting x87 FPU floating-point or WAIT/FWAIT instruction following the faulting
instruction. The x87 FPU, however, saves sufficient information about the error condition to allow recovery from the
error and re-execution of the faulting instruction if needed.
In situations where non- x87 FPU floating-point instructions depend on the results of an x87 FPU floating-point
instruction, a WAIT or FWAIT instruction can be inserted in front of a dependent instruction to force a pending x87
FPU floating-point exception to be handled before the dependent instruction is executed. See “x87 FPU Exception
Synchronization” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,
for more information about synchronization of x87 floating-point-error exceptions.
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INTERRUPT AND EXCEPTION HANDLING
Interrupt 17—Alignment Check Exception (#AC)
Exception Class
Fault.
Description
Indicates that the processor detected an unaligned memory operand when alignment checking was enabled. Alignment checks are only carried out in data (or stack) accesses (not in code fetches or system segment accesses). An
example of an alignment-check violation is a word stored at an odd byte address, or a doubleword stored at an
address that is not an integer multiple of 4. Table 6-7 lists the alignment requirements various data types recognized by the processor.
Table 6-7. Alignment Requirements by Data Type
Data Type
Address Must Be Divisible By
Word
2
Doubleword
4
Single-precision floating-point (32-bits)
4
Double-precision floating-point (64-bits)
8
Double extended-precision floating-point (80-bits)
8
Quadword
8
Double quadword
16
Segment Selector
2
32-bit Far Pointer
2
48-bit Far Pointer
4
32-bit Pointer
4
GDTR, IDTR, LDTR, or Task Register Contents
4
FSTENV/FLDENV Save Area
4 or 2, depending on operand size
FSAVE/FRSTOR Save Area
4 or 2, depending on operand size
Bit String
2 or 4 depending on the operand-size attribute.
Note that the alignment check exception (#AC) is generated only for data types that must be aligned on word,
doubleword, and quadword boundaries. A general-protection exception (#GP) is generated 128-bit data types that
are not aligned on a 16-byte boundary.
To enable alignment checking, the following conditions must be true:
•
•
•
AM flag in CR0 register is set.
AC flag in the EFLAGS register is set.
The CPL is 3 (protected mode or virtual-8086 mode).
Alignment-check exceptions (#AC) are generated only when operating at privilege level 3 (user mode). Memory
references that default to privilege level 0, such as segment descriptor loads, do not generate alignment-check
exceptions, even when caused by a memory reference made from privilege level 3.
Storing the contents of the GDTR, IDTR, LDTR, or task register in memory while at privilege level 3 can generate
an alignment-check exception. Although application programs do not normally store these registers, the fault can
be avoided by aligning the information stored on an even word-address.
The FXSAVE/XSAVE and FXRSTOR/XRSTOR instructions save and restore a 512-byte data structure, the first byte
of which must be aligned on a 16-byte boundary. If the alignment-check exception (#AC) is enabled when
executing these instructions (and CPL is 3), a misaligned memory operand can cause either an alignment-check
exception or a general-protection exception (#GP) depending on the processor implementation (see “FXSAVESave x87 FPU, MMX, SSE, and SSE2 State” and “FXRSTOR-Restore x87 FPU, MMX, SSE, and SSE2 State” in
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Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A; see “XSAVE—Save
Processor Extended States” and “XRSTOR—Restore Processor Extended States” in Chapter 5 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2C).
The MOVDQU, MOVUPS, and MOVUPD instructions perform 128-bit unaligned loads or stores. The LDDQU instructions loads 128-bit unaligned data. They do not generate general-protection exceptions (#GP) when operands are
not aligned on a 16-byte boundary. If alignment checking is enabled, alignment-check exceptions (#AC) may or
may not be generated depending on processor implementation when data addresses are not aligned on an 8-byte
boundary.
FSAVE and FRSTOR instructions can generate unaligned references, which can cause alignment-check faults. These
instructions are rarely needed by application programs.
Exception Error Code
Yes. The error code is null; all bits are clear except possibly bit 0 — EXT; see Section 6.13. EXT is set if the #AC is
recognized during delivery of an event other than a software interrupt (see “INT n/INTO/INT 3—Call to Interrupt
Procedure” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction that generated the exception.
Program State Change
A program-state change does not accompany an alignment-check fault, because the instruction is not executed.
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Interrupt 18—Machine-Check Exception (#MC)
Exception Class
Abort.
Description
Indicates that the processor detected an internal machine error or a bus error, or that an external agent detected
a bus error. The machine-check exception is model-specific, available on the Pentium and later generations of
processors. The implementation of the machine-check exception is different between different processor families,
and these implementations may not be compatible with future Intel 64 or IA-32 processors. (Use the CPUID
instruction to determine whether this feature is present.)
Bus errors detected by external agents are signaled to the processor on dedicated pins: the BINIT# and MCERR#
pins on the Pentium 4, Intel Xeon, and P6 family processors and the BUSCHK# pin on the Pentium processor. When
one of these pins is enabled, asserting the pin causes error information to be loaded into machine-check registers
and a machine-check exception is generated.
The machine-check exception and machine-check architecture are discussed in detail in Chapter 15, “MachineCheck Architecture.” Also, see the data books for the individual processors for processor-specific hardware information.
Exception Error Code
None. Error information is provide by machine-check MSRs.
Saved Instruction Pointer
For the Pentium 4 and Intel Xeon processors, the saved contents of extended machine-check state registers are
directly associated with the error that caused the machine-check exception to be generated (see Section 15.3.1.2,
“IA32_MCG_STATUS MSR,” and Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs”).
For the P6 family processors, if the EIPV flag in the MCG_STATUS MSR is set, the saved contents of CS and EIP
registers are directly associated with the error that caused the machine-check exception to be generated; if the
flag is clear, the saved instruction pointer may not be associated with the error (see Section 15.3.1.2,
“IA32_MCG_STATUS MSR”).
For the Pentium processor, contents of the CS and EIP registers may not be associated with the error.
Program State Change
The machine-check mechanism is enabled by setting the MCE flag in control register CR4.
For the Pentium 4, Intel Xeon, P6 family, and Pentium processors, a program-state change always accompanies a
machine-check exception, and an abort class exception is generated. For abort exceptions, information about the
exception can be collected from the machine-check MSRs, but the program cannot generally be restarted.
If the machine-check mechanism is not enabled (the MCE flag in control register CR4 is clear), a machine-check
exception causes the processor to enter the shutdown state.
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Interrupt 19—SIMD Floating-Point Exception (#XM)
Exception Class
Fault.
Description
Indicates the processor has detected an SSE/SSE2/SSE3 SIMD floating-point exception. The appropriate status
flag in the MXCSR register must be set and the particular exception unmasked for this interrupt to be generated.
There are six classes of numeric exception conditions that can occur while executing an SSE/ SSE2/SSE3 SIMD
floating-point instruction:
•
•
•
•
•
•
Invalid operation (#I)
Divide-by-zero (#Z)
Denormal operand (#D)
Numeric overflow (#O)
Numeric underflow (#U)
Inexact result (Precision) (#P)
The invalid operation, divide-by-zero, and denormal-operand exceptions are pre-computation exceptions; that is,
they are detected before any arithmetic operation occurs. The numeric underflow, numeric overflow, and inexact
result exceptions are post-computational exceptions.
See “SIMD Floating-Point Exceptions” in Chapter 11 of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, for additional information about the SIMD floating-point exception classes.
When a SIMD floating-point exception occurs, the processor does either of the following things:
•
It handles the exception automatically by producing the most reasonable result and allowing program
execution to continue undisturbed. This is the response to masked exceptions.
•
It generates a SIMD floating-point exception, which in turn invokes a software exception handler. This is the
response to unmasked exceptions.
Each of the six SIMD floating-point exception conditions has a corresponding flag bit and mask bit in the MXCSR
register. If an exception is masked (the corresponding mask bit in the MXCSR register is set), the processor takes
an appropriate automatic default action and continues with the computation. If the exception is unmasked (the
corresponding mask bit is clear) and the operating system supports SIMD floating-point exceptions (the OSXMMEXCPT flag in control register CR4 is set), a software exception handler is invoked through a SIMD floating-point
exception. If the exception is unmasked and the OSXMMEXCPT bit is clear (indicating that the operating system
does not support unmasked SIMD floating-point exceptions), an invalid opcode exception (#UD) is signaled instead
of a SIMD floating-point exception.
Note that because SIMD floating-point exceptions are precise and occur immediately, the situation does not arise
where an x87 FPU instruction, a WAIT/FWAIT instruction, or another SSE/SSE2/SSE3 instruction will catch a
pending unmasked SIMD floating-point exception.
In situations where a SIMD floating-point exception occurred while the SIMD floating-point exceptions were
masked (causing the corresponding exception flag to be set) and the SIMD floating-point exception was subsequently unmasked, then no exception is generated when the exception is unmasked.
When SSE/SSE2/SSE3 SIMD floating-point instructions operate on packed operands (made up of two or four suboperands), multiple SIMD floating-point exception conditions may be detected. If no more than one exception
condition is detected for one or more sets of sub-operands, the exception flags are set for each exception condition
detected. For example, an invalid exception detected for one sub-operand will not prevent the reporting of a divideby-zero exception for another sub-operand. However, when two or more exceptions conditions are generated for
one sub-operand, only one exception condition is reported, according to the precedences shown in Table 6-8. This
exception precedence sometimes results in the higher priority exception condition being reported and the lower
priority exception conditions being ignored.
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Table 6-8. SIMD Floating-Point Exceptions Priority
Priority
Description
1 (Highest)
Invalid operation exception due to SNaN operand (or any NaN operand for maximum, minimum, or certain compare and
convert operations).
2
QNaN operand1.
3
Any other invalid operation exception not mentioned above or a divide-by-zero exception2.
4
Denormal operand exception2.
5
Numeric overflow and underflow exceptions possibly in conjunction with the inexact result exception2.
6 (Lowest)
Inexact result exception.
NOTES:
1. Though a QNaN this is not an exception, the handling of a QNaN operand has precedence over lower priority exceptions. For example, a QNaN divided by zero results in a QNaN, not a divide-by-zero- exception.
2. If masked, then instruction execution continues, and a lower priority exception can occur as well.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the SSE/SSE2/SSE3 instruction that was executed when the
SIMD floating-point exception was generated. This is the faulting instruction in which the error condition was
detected.
Program State Change
A program-state change does not accompany a SIMD floating-point exception because the handling of the exception is immediate unless the particular exception is masked. The available state information is often sufficient to
allow recovery from the error and re-execution of the faulting instruction if needed.
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Interrupt 20—Virtualization Exception (#VE)
Exception Class
Fault.
Description
Indicates that the processor detected an EPT violation in VMX non-root operation. Not all EPT violations cause virtualization exceptions. See Section 25.5.6.2 for details.
The exception handler can recover from EPT violations and restart the program or task without any loss of program
continuity. In some cases, however, the problem that caused the EPT violation may be uncorrectable.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers generally point to the instruction that generated the exception.
Program State Change
A program-state change does not normally accompany a virtualization exception, because the instruction that
causes the exception to be generated is not executed. After the virtualization exception handler has corrected the
violation (for example, by executing the EPTP-switching VM function), execution of the program or task can be
resumed.
Additional Exception-Handling Information
The processor saves information about virtualization exceptions in the virtualization-exception information area.
See Section 25.5.6.2 for details.
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Interrupts 32 to 255—User Defined Interrupts
Exception Class
Not applicable.
Description
Indicates that the processor did one of the following things:
•
•
Executed an INT n instruction where the instruction operand is one of the vector numbers from 32 through 255.
Responded to an interrupt request at the INTR pin or from the local APIC when the interrupt vector number
associated with the request is from 32 through 255.
Exception Error Code
Not applicable.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction that follows the INT n instruction or instruction
following the instruction on which the INTR signal occurred.
Program State Change
A program-state change does not accompany interrupts generated by the INT n instruction or the INTR signal. The
INT n instruction generates the interrupt within the instruction stream. When the processor receives an INTR
signal, it commits all state changes for all previous instructions before it responds to the interrupt; so, program
execution can resume upon returning from the interrupt handler.
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6-52 Vol. 3A
CHAPTER 7
TASK MANAGEMENT
This chapter describes the IA-32 architecture’s task management facilities. These facilities are only available when
the processor is running in protected mode.
This chapter focuses on 32-bit tasks and the 32-bit TSS structure. For information on 16-bit tasks and the 16-bit
TSS structure, see Section 7.6, “16-Bit Task-State Segment (TSS).” For information specific to task management in
64-bit mode, see Section 7.7, “Task Management in 64-bit Mode.”
7.1
TASK MANAGEMENT OVERVIEW
A task is a unit of work that a processor can dispatch, execute, and suspend. It can be used to execute a program,
a task or process, an operating-system service utility, an interrupt or exception handler, or a kernel or executive
utility.
The IA-32 architecture provides a mechanism for saving the state of a task, for dispatching tasks for execution, and
for switching from one task to another. When operating in protected mode, all processor execution takes place from
within a task. Even simple systems must define at least one task. More complex systems can use the processor’s
task management facilities to support multitasking applications.
7.1.1
Task Structure
A task is made up of two parts: a task execution space and a task-state segment (TSS). The task execution space
consists of a code segment, a stack segment, and one or more data segments (see Figure 7-1). If an operating
system or executive uses the processor’s privilege-level protection mechanism, the task execution space also
provides a separate stack for each privilege level.
The TSS specifies the segments that make up the task execution space and provides a storage place for task state
information. In multitasking systems, the TSS also provides a mechanism for linking tasks.
A task is identified by the segment selector for its TSS. When a task is loaded into the processor for execution, the
segment selector, base address, limit, and segment descriptor attributes for the TSS are loaded into the task
register (see Section 2.4.4, “Task Register (TR)”).
If paging is implemented for the task, the base address of the page directory used by the task is loaded into control
register CR3.
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TASK MANAGEMENT
Code
Segment
Data
Segment
Task-State
Segment
(TSS)
Stack
Segment
(Current Priv.
Level)
Stack Seg.
Priv. Level 0
Stack Seg.
Priv. Level 1
Task Register
CR3
Stack
Segment
(Priv. Level 2)
Figure 7-1. Structure of a Task
7.1.2
Task State
The following items define the state of the currently executing task:
•
The task’s current execution space, defined by the segment selectors in the segment registers (CS, DS, SS, ES,
FS, and GS).
•
•
•
•
•
•
•
•
•
The state of the general-purpose registers.
The state of the EFLAGS register.
The state of the EIP register.
The state of control register CR3.
The state of the task register.
The state of the LDTR register.
The I/O map base address and I/O map (contained in the TSS).
Stack pointers to the privilege 0, 1, and 2 stacks (contained in the TSS).
Link to previously executed task (contained in the TSS).
Prior to dispatching a task, all of these items are contained in the task’s TSS, except the state of the task register.
Also, the complete contents of the LDTR register are not contained in the TSS, only the segment selector for the
LDT.
7.1.3
Executing a Task
Software or the processor can dispatch a task for execution in one of the following ways:
•
•
•
•
•
A explicit call to a task with the CALL instruction.
A explicit jump to a task with the JMP instruction.
An implicit call (by the processor) to an interrupt-handler task.
An implicit call to an exception-handler task.
A return (initiated with an IRET instruction) when the NT flag in the EFLAGS register is set.
All of these methods for dispatching a task identify the task to be dispatched with a segment selector that points to
a task gate or the TSS for the task. When dispatching a task with a CALL or JMP instruction, the selector in the
instruction may select the TSS directly or a task gate that holds the selector for the TSS. When dispatching a task
7-2 Vol. 3A
TASK MANAGEMENT
to handle an interrupt or exception, the IDT entry for the interrupt or exception must contain a task gate that holds
the selector for the interrupt- or exception-handler TSS.
When a task is dispatched for execution, a task switch occurs between the currently running task and the
dispatched task. During a task switch, the execution environment of the currently executing task (called the task’s
state or context) is saved in its TSS and execution of the task is suspended. The context for the dispatched task is
then loaded into the processor and execution of that task begins with the instruction pointed to by the newly loaded
EIP register. If the task has not been run since the system was last initialized, the EIP will point to the first instruction of the task’s code; otherwise, it will point to the next instruction after the last instruction that the task
executed when it was last active.
If the currently executing task (the calling task) called the task being dispatched (the called task), the TSS
segment selector for the calling task is stored in the TSS of the called task to provide a link back to the calling task.
For all IA-32 processors, tasks are not recursive. A task cannot call or jump to itself.
Interrupts and exceptions can be handled with a task switch to a handler task. Here, the processor performs a task
switch to handle the interrupt or exception and automatically switches back to the interrupted task upon returning
from the interrupt-handler task or exception-handler task. This mechanism can also handle interrupts that occur
during interrupt tasks.
As part of a task switch, the processor can also switch to another LDT, allowing each task to have a different logicalto-physical address mapping for LDT-based segments. The page-directory base register (CR3) also is reloaded on a
task switch, allowing each task to have its own set of page tables. These protection facilities help isolate tasks and
prevent them from interfering with one another.
If protection mechanisms are not used, the processor provides no protection between tasks. This is true even with
operating systems that use multiple privilege levels for protection. A task running at privilege level 3 that uses the
same LDT and page tables as other privilege-level-3 tasks can access code and corrupt data and the stack of other
tasks.
Use of task management facilities for handling multitasking applications is optional. Multitasking can be handled in
software, with each software defined task executed in the context of a single IA-32 architecture task.
7.2
TASK MANAGEMENT DATA STRUCTURES
The processor defines five data structures for handling task-related activities:
•
•
•
•
•
Task-state segment (TSS).
Task-gate descriptor.
TSS descriptor.
Task register.
NT flag in the EFLAGS register.
When operating in protected mode, a TSS and TSS descriptor must be created for at least one task, and the
segment selector for the TSS must be loaded into the task register (using the LTR instruction).
7.2.1
Task-State Segment (TSS)
The processor state information needed to restore a task is saved in a system segment called the task-state
segment (TSS). Figure 7-2 shows the format of a TSS for tasks designed for 32-bit CPUs. The fields of a TSS are
divided into two main categories: dynamic fields and static fields.
For information about 16-bit Intel 286 processor task structures, see Section 7.6, “16-Bit Task-State Segment
(TSS).” For information about 64-bit mode task structures, see Section 7.7, “Task Management in 64-bit Mode.”
Vol. 3A 7-3
TASK MANAGEMENT
31
0
15
Reserved
I/O Map Base Address
T 100
LDT Segment Selector
Reserved
96
Reserved
GS
92
Reserved
FS
88
Reserved
DS
84
Reserved
SS
80
Reserved
CS
76
Reserved
ES
72
EDI
68
ESI
64
EBP
60
ESP
56
EBX
52
EDX
48
ECX
44
EAX
40
EFLAGS
36
EIP
32
CR3 (PDBR)
28
Reserved
SS2
Reserved
SS1
SS0
8
4
ESP0
Reserved
16
12
ESP1
Reserved
24
20
ESP2
Previous Task Link
0
Reserved bits. Set to 0.
Figure 7-2. 32-Bit Task-State Segment (TSS)
The processor updates dynamic fields when a task is suspended during a task switch. The following are dynamic
fields:
•
General-purpose register fields — State of the EAX, ECX, EDX, EBX, ESP, EBP, ESI, and EDI registers prior
to the task switch.
•
Segment selector fields — Segment selectors stored in the ES, CS, SS, DS, FS, and GS registers prior to the
task switch.
•
•
•
EFLAGS register field — State of the EFAGS register prior to the task switch.
EIP (instruction pointer) field — State of the EIP register prior to the task switch.
Previous task link field — Contains the segment selector for the TSS of the previous task (updated on a task
switch that was initiated by a call, interrupt, or exception). This field (which is sometimes called the back link
field) permits a task switch back to the previous task by using the IRET instruction.
The processor reads the static fields, but does not normally change them. These fields are set up when a task is
created. The following are static fields:
•
LDT segment selector field — Contains the segment selector for the task's LDT.
7-4 Vol. 3A
TASK MANAGEMENT
•
CR3 control register field — Contains the base physical address of the page directory to be used by the task.
Control register CR3 is also known as the page-directory base register (PDBR).
•
Privilege level-0, -1, and -2 stack pointer fields — These stack pointers consist of a logical address made
up of the segment selector for the stack segment (SS0, SS1, and SS2) and an offset into the stack (ESP0,
ESP1, and ESP2). Note that the values in these fields are static for a particular task; whereas, the SS and ESP
values will change if stack switching occurs within the task.
•
T (debug trap) flag (byte 100, bit 0) — When set, the T flag causes the processor to raise a debug exception
when a task switch to this task occurs (see Section 17.3.1.5, “Task-Switch Exception Condition”).
•
I/O map base address field — Contains a 16-bit offset from the base of the TSS to the I/O permission bit
map and interrupt redirection bitmap. When present, these maps are stored in the TSS at higher addresses.
The I/O map base address points to the beginning of the I/O permission bit map and the end of the interrupt
redirection bit map. See Chapter 18, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for more information about the I/O permission bit map. See Section 20.3,
“Interrupt and Exception Handling in Virtual-8086 Mode,” for a detailed description of the interrupt redirection
bit map.
If paging is used:
•
Avoid placing a page boundary in the part of the TSS that the processor reads during a task switch (the first 104
bytes). The processor may not correctly perform address translations if a boundary occurs in this area. During
a task switch, the processor reads and writes into the first 104 bytes of each TSS (using contiguous physical
addresses beginning with the physical address of the first byte of the TSS). So, after TSS access begins, if part
of the 104 bytes is not physically contiguous, the processor will access incorrect information without generating
a page-fault exception.
•
Pages corresponding to the previous task’s TSS, the current task’s TSS, and the descriptor table entries for
each all should be marked as read/write.
•
Task switches are carried out faster if the pages containing these structures are present in memory before the
task switch is initiated.
7.2.2
TSS Descriptor
The TSS, like all other segments, is defined by a segment descriptor. Figure 7-3 shows the format of a TSS
descriptor. TSS descriptors may only be placed in the GDT; they cannot be placed in an LDT or the IDT.
An attempt to access a TSS using a segment selector with its TI flag set (which indicates the current LDT) causes
a general-protection exception (#GP) to be generated during CALLs and JMPs; it causes an invalid TSS exception
(#TS) during IRETs. A general-protection exception is also generated if an attempt is made to load a segment
selector for a TSS into a segment register.
The busy flag (B) in the type field indicates whether the task is busy. A busy task is currently running or suspended.
A type field with a value of 1001B indicates an inactive task; a value of 1011B indicates a busy task. Tasks are not
recursive. The processor uses the busy flag to detect an attempt to call a task whose execution has been interrupted. To insure that there is only one busy flag is associated with a task, each TSS should have only one TSS
descriptor that points to it.
Vol. 3A 7-5
TASK MANAGEMENT
TSS Descriptor
31
24 23 22 21 20 19
Base 31:24
A
G 0 0 V
L
31
16 15 14 13 12 11
Limit
19:16
P
D
P
L
0
8 7
Type
16 15
Base Address 15:00
AVL
B
BASE
DPL
G
LIMIT
P
TYPE
4
Base 23:16
0 1 0 B 1
0
Segment Limit 15:00
0
Available for use by system software
Busy flag
Segment Base Address
Descriptor Privilege Level
Granularity
Segment Limit
Segment Present
Segment Type
Figure 7-3. TSS Descriptor
The base, limit, and DPL fields and the granularity and present flags have functions similar to their use in datasegment descriptors (see Section 3.4.5, “Segment Descriptors”). When the G flag is 0 in a TSS descriptor for a 32bit TSS, the limit field must have a value equal to or greater than 67H, one byte less than the minimum size of a
TSS. Attempting to switch to a task whose TSS descriptor has a limit less than 67H generates an invalid-TSS exception (#TS). A larger limit is required if an I/O permission bit map is included or if the operating system stores additional data. The processor does not check for a limit greater than 67H on a task switch; however, it does check
when accessing the I/O permission bit map or interrupt redirection bit map.
Any program or procedure with access to a TSS descriptor (that is, whose CPL is numerically equal to or less than
the DPL of the TSS descriptor) can dispatch the task with a call or a jump.
In most systems, the DPLs of TSS descriptors are set to values less than 3, so that only privileged software can
perform task switching. However, in multitasking applications, DPLs for some TSS descriptors may be set to 3 to
allow task switching at the application (or user) privilege level.
7.2.3
TSS Descriptor in 64-bit mode
In 64-bit mode, task switching is not supported, but TSS descriptors still exist. The format of a 64-bit TSS is
described in Section 7.7.
In 64-bit mode, the TSS descriptor is expanded to 16 bytes (see Figure 7-4). This expansion also applies to an LDT
descriptor in 64-bit mode. Table 3-2 provides the encoding information for the segment type field.
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TASK MANAGEMENT
TSS (or LDT) Descriptor
31
13 12
Reserved
0
8 7
0
12
Reserved
31
0
8
Base Address 63:32
31
24 23 22 21 20 19
Base 31:24
A
G 0 0 V
L
31
16 15 14 13 12 11
Limit
19:16
P
D
P
L
0
8 7
Type
16 15
Base Address 15:00
AVL
B
BASE
DPL
G
LIMIT
P
TYPE
4
Base 23:16
0
0
Segment Limit 15:00
0
Available for use by system software
Busy flag
Segment Base Address
Descriptor Privilege Level
Granularity
Segment Limit
Segment Present
Segment Type
Figure 7-4. Format of TSS and LDT Descriptors in 64-bit Mode
7.2.4
Task Register
The task register holds the 16-bit segment selector and the entire segment descriptor (32-bit base address (64 bits
in IA-32e mode), 16-bit segment limit, and descriptor attributes) for the TSS of the current task (see Figure 2-6).
This information is copied from the TSS descriptor in the GDT for the current task. Figure 7-5 shows the path the
processor uses to access the TSS (using the information in the task register).
The task register has a visible part (that can be read and changed by software) and an invisible part (maintained
by the processor and is inaccessible by software). The segment selector in the visible portion points to a TSS
descriptor in the GDT. The processor uses the invisible portion of the task register to cache the segment descriptor
for the TSS. Caching these values in a register makes execution of the task more efficient. The LTR (load task
register) and STR (store task register) instructions load and read the visible portion of the task register:
The LTR instruction loads a segment selector (source operand) into the task register that points to a TSS descriptor
in the GDT. It then loads the invisible portion of the task register with information from the TSS descriptor. LTR is a
privileged instruction that may be executed only when the CPL is 0. It’s used during system initialization to put an
initial value in the task register. Afterwards, the contents of the task register are changed implicitly when a task
switch occurs.
The STR (store task register) instruction stores the visible portion of the task register in a general-purpose register
or memory. This instruction can be executed by code running at any privilege level in order to identify the currently
running task. However, it is normally used only by operating system software. (If CR4.UMIP = 1, STR can be
executed only when CPL = 0.)
On power up or reset of the processor, segment selector and base address are set to the default value of 0; the limit
is set to FFFFH.
Vol. 3A 7-7
TASK MANAGEMENT
TSS
Task
Register
+
Visible Part
Selector
Invisible Part
Base Address
Segment Limit
GDT
TSS Descriptor
0
Figure 7-5. Task Register
7.2.5
Task-Gate Descriptor
A task-gate descriptor provides an indirect, protected reference to a task (see Figure 7-6). It can be placed in the
GDT, an LDT, or the IDT. The TSS segment selector field in a task-gate descriptor points to a TSS descriptor in the
GDT. The RPL in this segment selector is not used.
The DPL of a task-gate descriptor controls access to the TSS descriptor during a task switch. When a program or
procedure makes a call or jump to a task through a task gate, the CPL and the RPL field of the gate selector pointing
to the task gate must be less than or equal to the DPL of the task-gate descriptor. Note that when a task gate is
used, the DPL of the destination TSS descriptor is not used.
31
16 15 14 13 12 11
Reserved
31
P
D
P
L
Type
DPL
P
TYPE
4
0
Reserved
Descriptor Privilege Level
Segment Present
Segment Type
Figure 7-6. Task-Gate Descriptor
7-8 Vol. 3A
Reserved
0 0 1 0 1
16 15
TSS Segment Selector
0
8 7
0
TASK MANAGEMENT
A task can be accessed either through a task-gate descriptor or a TSS descriptor. Both of these structures satisfy
the following needs:
•
Need for a task to have only one busy flag — Because the busy flag for a task is stored in the TSS
descriptor, each task should have only one TSS descriptor. There may, however, be several task gates that
reference the same TSS descriptor.
•
Need to provide selective access to tasks — Task gates fill this need, because they can reside in an LDT and
can have a DPL that is different from the TSS descriptor's DPL. A program or procedure that does not have
sufficient privilege to access the TSS descriptor for a task in the GDT (which usually has a DPL of 0) may be
allowed access to the task through a task gate with a higher DPL. Task gates give the operating system greater
latitude for limiting access to specific tasks.
•
Need for an interrupt or exception to be handled by an independent task — Task gates may also reside
in the IDT, which allows interrupts and exceptions to be handled by handler tasks. When an interrupt or
exception vector points to a task gate, the processor switches to the specified task.
Figure 7-7 illustrates how a task gate in an LDT, a task gate in the GDT, and a task gate in the IDT can all point to
the same task.
LDT
GDT
TSS
Task Gate
Task Gate
TSS Descriptor
IDT
Task Gate
Figure 7-7. Task Gates Referencing the Same Task
7.3
TASK SWITCHING
The processor transfers execution to another task in one of four cases:
•
•
The current program, task, or procedure executes a JMP or CALL instruction to a TSS descriptor in the GDT.
The current program, task, or procedure executes a JMP or CALL instruction to a task-gate descriptor in the
GDT or the current LDT.
Vol. 3A 7-9
TASK MANAGEMENT
•
•
An interrupt or exception vector points to a task-gate descriptor in the IDT.
The current task executes an IRET when the NT flag in the EFLAGS register is set.
JMP, CALL, and IRET instructions, as well as interrupts and exceptions, are all mechanisms for redirecting a
program. The referencing of a TSS descriptor or a task gate (when calling or jumping to a task) or the state of the
NT flag (when executing an IRET instruction) determines whether a task switch occurs.
The processor performs the following operations when switching to a new task:
1. Obtains the TSS segment selector for the new task as the operand of the JMP or CALL instruction, from a task
gate, or from the previous task link field (for a task switch initiated with an IRET instruction).
2. Checks that the current (old) task is allowed to switch to the new task. Data-access privilege rules apply to JMP
and CALL instructions. The CPL of the current (old) task and the RPL of the segment selector for the new task
must be less than or equal to the DPL of the TSS descriptor or task gate being referenced. Exceptions,
interrupts (except for interrupts generated by the INT n instruction), and the IRET instruction are permitted to
switch tasks regardless of the DPL of the destination task-gate or TSS descriptor. For interrupts generated by
the INT n instruction, the DPL is checked.
3. Checks that the TSS descriptor of the new task is marked present and has a valid limit (greater than or equal
to 67H).
4. Checks that the new task is available (call, jump, exception, or interrupt) or busy (IRET return).
5. Checks that the current (old) TSS, new TSS, and all segment descriptors used in the task switch are paged into
system memory.
6. If the task switch was initiated with a JMP or IRET instruction, the processor clears the busy (B) flag in the
current (old) task’s TSS descriptor; if initiated with a CALL instruction, an exception, or an interrupt: the busy
(B) flag is left set. (See Table 7-2.)
7. If the task switch was initiated with an IRET instruction, the processor clears the NT flag in a temporarily saved
image of the EFLAGS register; if initiated with a CALL or JMP instruction, an exception, or an interrupt, the NT
flag is left unchanged in the saved EFLAGS image.
8. Saves the state of the current (old) task in the current task’s TSS. The processor finds the base address of the
current TSS in the task register and then copies the states of the following registers into the current TSS: all the
general-purpose registers, segment selectors from the segment registers, the temporarily saved image of the
EFLAGS register, and the instruction pointer register (EIP).
9. If the task switch was initiated with a CALL instruction, an exception, or an interrupt, the processor will set the
NT flag in the EFLAGS loaded from the new task. If initiated with an IRET instruction or JMP instruction, the NT
flag will reflect the state of NT in the EFLAGS loaded from the new task (see Table 7-2).
10. If the task switch was initiated with a CALL instruction, JMP instruction, an exception, or an interrupt, the
processor sets the busy (B) flag in the new task’s TSS descriptor; if initiated with an IRET instruction, the busy
(B) flag is left set.
11. Loads the task register with the segment selector and descriptor for the new task's TSS.
12. The TSS state is loaded into the processor. This includes the LDTR register, the PDBR (control register CR3), the
EFLAGS register, the EIP register, the general-purpose registers, and the segment selectors. A fault during the
load of this state may corrupt architectural state. (If paging is not enabled, a PDBR value is read from the new
task's TSS, but it is not loaded into CR3.)
13. The descriptors associated with the segment selectors are loaded and qualified. Any errors associated with this
loading and qualification occur in the context of the new task and may corrupt architectural state.
NOTES
If all checks and saves have been carried out successfully, the processor commits to the task
switch. If an unrecoverable error occurs in steps 1 through 11, the processor does not complete the
task switch and insures that the processor is returned to its state prior to the execution of the
instruction that initiated the task switch.
If an unrecoverable error occurs in step 12, architectural state may be corrupted, but an attempt
will be made to handle the error in the prior execution environment. If an unrecoverable error
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TASK MANAGEMENT
occurs after the commit point (in step 13), the processor completes the task switch (without
performing additional access and segment availability checks) and generates the appropriate
exception prior to beginning execution of the new task.
If exceptions occur after the commit point, the exception handler must finish the task switch itself
before allowing the processor to begin executing the new task. See Chapter 6, “Interrupt
10—Invalid TSS Exception (#TS),” for more information about the affect of exceptions on a task
when they occur after the commit point of a task switch.
14. Begins executing the new task. (To an exception handler, the first instruction of the new task appears not to
have been executed.)
The state of the currently executing task is always saved when a successful task switch occurs. If the task is
resumed, execution starts with the instruction pointed to by the saved EIP value, and the registers are restored to
the values they held when the task was suspended.
When switching tasks, the privilege level of the new task does not inherit its privilege level from the suspended
task. The new task begins executing at the privilege level specified in the CPL field of the CS register, which is
loaded from the TSS. Because tasks are isolated by their separate address spaces and TSSs and because privilege
rules control access to a TSS, software does not need to perform explicit privilege checks on a task switch.
Table 7-1 shows the exception conditions that the processor checks for when switching tasks. It also shows the
exception that is generated for each check if an error is detected and the segment that the error code references.
(The order of the checks in the table is the order used in the P6 family processors. The exact order is model specific
and may be different for other IA-32 processors.) Exception handlers designed to handle these exceptions may be
subject to recursive calls if they attempt to reload the segment selector that generated the exception. The cause of
the exception (or the first of multiple causes) should be fixed before reloading the selector.
Table 7-1. Exception Conditions Checked During a Task Switch
Condition Checked
Segment selector for a TSS descriptor references
the GDT and is within the limits of the table.
Exception1
#GP
Error Code Reference2
New Task’s TSS
#TS (for IRET)
TSS descriptor is present in memory.
#NP
TSS descriptor is not busy (for task switch initiated by a call, interrupt, or
exception).
#GP (for JMP, CALL, INT) Task’s back-link TSS
New Task’s TSS
TSS descriptor is not busy (for task switch initiated by an IRET instruction).
#TS (for IRET)
New Task’s TSS
TSS segment limit greater than or equal to 108 (for 32-bit TSS) or 44 (for 16-bit
TSS).
#TS
New Task’s TSS
LDT segment selector of new task is valid 3.
#TS
New Task’s LDT
Code segment DPL matches segment selector RPL.
#TS
New Code Segment
SS segment selector is valid 2.
#TS
New Stack Segment
Stack segment is present in memory.
#SS
New Stack Segment
Stack segment DPL matches CPL.
#TS
New stack segment
Registers are loaded from the values in the TSS.
LDT of new task is present in memory.
#TS
New Task’s LDT
CS segment selector is valid 3.
#TS
New Code Segment
Code segment is present in memory.
#NP
New Code Segment
#TS
New Stack Segment
Stack segment DPL matches selector RPL.
DS, ES, FS, and GS segment selectors are valid
DS, ES, FS, and GS segments are readable.
3
.
#TS
New Data Segment
#TS
New Data Segment
Vol. 3A 7-11
TASK MANAGEMENT
Table 7-1. Exception Conditions Checked During a Task Switch (Contd.)
Condition Checked
Exception1
Error Code Reference2
DS, ES, FS, and GS segments are present in memory.
#NP
New Data Segment
DS, ES, FS, and GS segment DPL greater than or equal to CPL (unless these are
conforming segments).
#TS
New Data Segment
NOTES:
1. #NP is segment-not-present exception, #GP is general-protection exception, #TS is invalid-TSS exception, and #SS is stack-fault
exception.
2. The error code contains an index to the segment descriptor referenced in this column.
3. A segment selector is valid if it is in a compatible type of table (GDT or LDT), occupies an address within the table's segment limit,
and refers to a compatible type of descriptor (for example, a segment selector in the CS register only is valid when it points to a
code-segment descriptor).
The TS (task switched) flag in the control register CR0 is set every time a task switch occurs. System software uses
the TS flag to coordinate the actions of floating-point unit when generating floating-point exceptions with the rest
of the processor. The TS flag indicates that the context of the floating-point unit may be different from that of the
current task. See Section 2.5, “Control Registers”, for a detailed description of the function and use of the TS flag.
7.4
TASK LINKING
The previous task link field of the TSS (sometimes called the “backlink”) and the NT flag in the EFLAGS register are
used to return execution to the previous task. EFLAGS.NT = 1 indicates that the currently executing task is nested
within the execution of another task.
When a CALL instruction, an interrupt, or an exception causes a task switch: the processor copies the segment
selector for the current TSS to the previous task link field of the TSS for the new task; it then sets EFLAGS.NT = 1.
If software uses an IRET instruction to suspend the new task, the processor checks for EFLAGS.NT = 1; it then uses
the value in the previous task link field to return to the previous task. See Figures 7-8.
When a JMP instruction causes a task switch, the new task is not nested. The previous task link field is not used and
EFLAGS.NT = 0. Use a JMP instruction to dispatch a new task when nesting is not desired.
Top Level
Task
Nested
Task
More Deeply
Nested Task
Currently Executing
Task
TSS
TSS
TSS
EFLAGS
NT=1
NT=0
Previous
Task Link
NT=1
Previous
Task Link
NT=1
Previous
Task Link
Task Register
Figure 7-8. Nested Tasks
Table 7-2 shows the busy flag (in the TSS segment descriptor), the NT flag, the previous task link field, and TS flag
(in control register CR0) during a task switch.
The NT flag may be modified by software executing at any privilege level. It is possible for a program to set the NT
flag and execute an IRET instruction. This might randomly invoke the task specified in the previous link field of the
current task's TSS. To keep such spurious task switches from succeeding, the operating system should initialize the
previous task link field in every TSS that it creates to 0.
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TASK MANAGEMENT
Table 7-2. Effect of a Task Switch on Busy Flag, NT Flag, Previous Task Link Field, and TS Flag
Flag or Field
Effect of JMP instruction
Effect of CALL Instruction or
Interrupt
Effect of IRET
Instruction
Busy (B) flag of new task.
Flag is set. Must have been
clear before.
Flag is set. Must have been
clear before.
No change. Must have been set.
Busy flag of old task.
Flag is cleared.
No change. Flag is currently
set.
Flag is cleared.
NT flag of new task.
Set to value from TSS of new
task.
Flag is set.
Set to value from TSS of new
task.
NT flag of old task.
No change.
No change.
Flag is cleared.
Previous task link field of new
task.
No change.
Loaded with selector
for old task’s TSS.
No change.
Previous task link field of old
task.
No change.
No change.
No change.
TS flag in control register CR0.
Flag is set.
Flag is set.
Flag is set.
7.4.1
Use of Busy Flag To Prevent Recursive Task Switching
A TSS allows only one context to be saved for a task; therefore, once a task is called (dispatched), a recursive (or
re-entrant) call to the task would cause the current state of the task to be lost. The busy flag in the TSS segment
descriptor is provided to prevent re-entrant task switching and a subsequent loss of task state information. The
processor manages the busy flag as follows:
1. When dispatching a task, the processor sets the busy flag of the new task.
2. If during a task switch, the current task is placed in a nested chain (the task switch is being generated by a
CALL instruction, an interrupt, or an exception), the busy flag for the current task remains set.
3. When switching to the new task (initiated by a CALL instruction, interrupt, or exception), the processor
generates a general-protection exception (#GP) if the busy flag of the new task is already set. If the task switch
is initiated with an IRET instruction, the exception is not raised because the processor expects the busy flag to
be set.
4. When a task is terminated by a jump to a new task (initiated with a JMP instruction in the task code) or by an
IRET instruction in the task code, the processor clears the busy flag, returning the task to the “not busy” state.
The processor prevents recursive task switching by preventing a task from switching to itself or to any task in a
nested chain of tasks. The chain of nested suspended tasks may grow to any length, due to multiple calls, interrupts, or exceptions. The busy flag prevents a task from being invoked if it is in this chain.
The busy flag may be used in multiprocessor configurations, because the processor follows a LOCK protocol (on the
bus or in the cache) when it sets or clears the busy flag. This lock keeps two processors from invoking the same
task at the same time. See Section 8.1.2.1, “Automatic Locking,” for more information about setting the busy flag
in a multiprocessor applications.
7.4.2
Modifying Task Linkages
In a uniprocessor system, in situations where it is necessary to remove a task from a chain of linked tasks, use the
following procedure to remove the task:
1. Disable interrupts.
2. Change the previous task link field in the TSS of the pre-empting task (the task that suspended the task to be
removed). It is assumed that the pre-empting task is the next task (newer task) in the chain from the task to
be removed. Change the previous task link field to point to the TSS of the next oldest task in the chain or to an
even older task in the chain.
3. Clear the busy (B) flag in the TSS segment descriptor for the task being removed from the chain. If more than
one task is being removed from the chain, the busy flag for each task being remove must be cleared.
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TASK MANAGEMENT
4. Enable interrupts.
In a multiprocessing system, additional synchronization and serialization operations must be added to this procedure to insure that the TSS and its segment descriptor are both locked when the previous task link field is changed
and the busy flag is cleared.
7.5
TASK ADDRESS SPACE
The address space for a task consists of the segments that the task can access. These segments include the code,
data, stack, and system segments referenced in the TSS and any other segments accessed by the task code. The
segments are mapped into the processor’s linear address space, which is in turn mapped into the processor’s physical address space (either directly or through paging).
The LDT segment field in the TSS can be used to give each task its own LDT. Giving a task its own LDT allows the
task address space to be isolated from other tasks by placing the segment descriptors for all the segments associated with the task in the task’s LDT.
It also is possible for several tasks to use the same LDT. This is a memory-efficient way to allow specific tasks to
communicate with or control each other, without dropping the protection barriers for the entire system.
Because all tasks have access to the GDT, it also is possible to create shared segments accessed through segment
descriptors in this table.
If paging is enabled, the CR3 register (PDBR) field in the TSS allows each task to have its own set of page tables for
mapping linear addresses to physical addresses. Or, several tasks can share the same set of page tables.
7.5.1
Mapping Tasks to the Linear and Physical Address Spaces
Tasks can be mapped to the linear address space and physical address space in one of two ways:
•
One linear-to-physical address space mapping is shared among all tasks. — When paging is not
enabled, this is the only choice. Without paging, all linear addresses map to the same physical addresses. When
paging is enabled, this form of linear-to-physical address space mapping is obtained by using one page
directory for all tasks. The linear address space may exceed the available physical space if demand-paged
virtual memory is supported.
•
Each task has its own linear address space that is mapped to the physical address space. — This form
of mapping is accomplished by using a different page directory for each task. Because the PDBR (control
register CR3) is loaded on task switches, each task may have a different page directory.
The linear address spaces of different tasks may map to completely distinct physical addresses. If the entries of
different page directories point to different page tables and the page tables point to different pages of physical
memory, then the tasks do not share physical addresses.
With either method of mapping task linear address spaces, the TSSs for all tasks must lie in a shared area of the
physical space, which is accessible to all tasks. This mapping is required so that the mapping of TSS addresses does
not change while the processor is reading and updating the TSSs during a task switch. The linear address space
mapped by the GDT also should be mapped to a shared area of the physical space; otherwise, the purpose of the
GDT is defeated. Figure 7-9 shows how the linear address spaces of two tasks can overlap in the physical space by
sharing page tables.
7-14 Vol. 3A
TASK MANAGEMENT
TSS
Page Directories
Page Tables
Page Frames
Task A
Task A TSS
PDBR
PTE
PTE
PTE
PDE
PDE
Task A
Task A
Shared PT
Shared
PTE
PTE
Task B TSS
Shared
Task B
PDBR
PDE
PDE
PTE
PTE
Task B
Figure 7-9. Overlapping Linear-to-Physical Mappings
7.5.2
Task Logical Address Space
To allow the sharing of data among tasks, use the following techniques to create shared logical-to-physical
address-space mappings for data segments:
•
Through the segment descriptors in the GDT — All tasks must have access to the segment descriptors in
the GDT. If some segment descriptors in the GDT point to segments in the linear-address space that are
mapped into an area of the physical-address space common to all tasks, then all tasks can share the data and
code in those segments.
•
Through a shared LDT — Two or more tasks can use the same LDT if the LDT fields in their TSSs point to the
same LDT. If some segment descriptors in a shared LDT point to segments that are mapped to a common area
of the physical address space, the data and code in those segments can be shared among the tasks that share
the LDT. This method of sharing is more selective than sharing through the GDT, because the sharing can be
limited to specific tasks. Other tasks in the system may have different LDTs that do not give them access to the
shared segments.
•
Through segment descriptors in distinct LDTs that are mapped to common addresses in linear
address space — If this common area of the linear address space is mapped to the same area of the physical
address space for each task, these segment descriptors permit the tasks to share segments. Such segment
descriptors are commonly called aliases. This method of sharing is even more selective than those listed above,
because, other segment descriptors in the LDTs may point to independent linear addresses which are not
shared.
7.6
16-BIT TASK-STATE SEGMENT (TSS)
The 32-bit IA-32 processors also recognize a 16-bit TSS format like the one used in Intel 286 processors (see
Figure 7-10). This format is supported for compatibility with software written to run on earlier IA-32 processors.
The following information is important to know about the 16-bit TSS.
•
•
Do not use a 16-bit TSS to implement a virtual-8086 task.
The valid segment limit for a 16-bit TSS is 2CH.
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TASK MANAGEMENT
•
The 16-bit TSS does not contain a field for the base address of the page directory, which is loaded into control
register CR3. A separate set of page tables for each task is not supported for 16-bit tasks. If a 16-bit task is
dispatched, the page-table structure for the previous task is used.
•
•
•
The I/O base address is not included in the 16-bit TSS. None of the functions of the I/O map are supported.
When task state is saved in a 16-bit TSS, the upper 16 bits of the EFLAGS register and the EIP register are lost.
When the general-purpose registers are loaded or saved from a 16-bit TSS, the upper 16 bits of the registers
are modified and not maintained.
15
0
Task LDT Selector
42
DS Selector
40
SS Selector
38
CS Selector
ES Selector
36
34
DI
32
SI
30
BP
28
SP
26
BX
24
DX
22
CX
20
AX
18
FLAG Word
16
IP (Entry Point)
14
SS2
12
SP2
10
SS1
8
SP1
6
SS0
4
SP0
2
Previous Task Link
0
Figure 7-10. 16-Bit TSS Format
7.7
TASK MANAGEMENT IN 64-BIT MODE
In 64-bit mode, task structure and task state are similar to those in protected mode. However, the task switching
mechanism available in protected mode is not supported in 64-bit mode. Task management and switching must be
performed by software. The processor issues a general-protection exception (#GP) if the following is attempted in
64-bit mode:
•
•
Control transfer to a TSS or a task gate using JMP, CALL, INTn, or interrupt.
An IRET with EFLAGS.NT (nested task) set to 1.
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Although hardware task-switching is not supported in 64-bit mode, a 64-bit task state segment (TSS) must exist.
Figure 7-11 shows the format of a 64-bit TSS. The TSS holds information important to 64-bit mode and that is not
directly related to the task-switch mechanism. This information includes:
•
•
•
RSPn — The full 64-bit canonical forms of the stack pointers (RSP) for privilege levels 0-2.
ISTn — The full 64-bit canonical forms of the interrupt stack table (IST) pointers.
I/O map base address — The 16-bit offset to the I/O permission bit map from the 64-bit TSS base.
The operating system must create at least one 64-bit TSS after activating IA-32e mode. It must execute the LTR
instruction (in 64-bit mode) to load the TR register with a pointer to the 64-bit TSS responsible for both 64-bitmode programs and compatibility-mode programs.
31
0
15
Reserved
I/O Map Base Address
Reserved
100
96
Reserved
92
IST7 (upper 32 bits)
88
IST7 (lower 32 bits)
84
IST6 (upper 32 bits)
80
IST6 (lower 32 bits)
76
IST5 (upper 32 bits)
72
IST5 (lower 32 bits)
68
IST4 (upper 32 bits)
64
IST4 (lower 32 bits)
60
IST3 (upper 32 bits)
56
IST3 (lower 32 bits)
52
IST2 (upper 32 bits)
48
IST2 (lower 32 bits)
44
IST1 (upper 32 bits)
40
IST1 (lower 32 bits)
36
Reserved
32
Reserved
28
RSP2 (upper 32 bits)
24
RSP2 (lower 32 bits)
20
RSP1 (upper 32 bits)
16
RSP1 (lower 32 bits)
12
RSP0 (upper 32 bits)
8
RSP0 (lower 32 bits)
4
Reserved
0
Reserved bits. Set to 0.
Figure 7-11. 64-Bit TSS Format
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CHAPTER 8
MULTIPLE-PROCESSOR MANAGEMENT
The Intel 64 and IA-32 architectures provide mechanisms for managing and improving the performance of multiple
processors connected to the same system bus. These include:
•
•
•
Bus locking and/or cache coherency management for performing atomic operations on system memory.
•
A second-level cache (level 2, L2). For the Pentium 4, Intel Xeon, and P6 family processors, the L2 cache is
included in the processor package and is tightly coupled to the processor. For the Pentium and Intel486
processors, pins are provided to support an external L2 cache.
•
A third-level cache (level 3, L3). For Intel Xeon processors, the L3 cache is included in the processor package
and is tightly coupled to the processor.
•
Intel Hyper-Threading Technology. This extension to the Intel 64 and IA-32 architectures enables a single
processor core to execute two or more threads concurrently (see Section 8.5, “Intel® Hyper-Threading
Technology and Intel® Multi-Core Technology”).
Serializing instructions.
An advance programmable interrupt controller (APIC) located on the processor chip (see Chapter 10,
“Advanced Programmable Interrupt Controller (APIC)”). This feature was introduced by the Pentium processor.
These mechanisms are particularly useful in symmetric-multiprocessing (SMP) systems. However, they can also be
used when an Intel 64 or IA-32 processor and a special-purpose processor (such as a communications, graphics,
or video processor) share the system bus.
These multiprocessing mechanisms have the following characteristics:
•
To maintain system memory coherency — When two or more processors are attempting simultaneously to
access the same address in system memory, some communication mechanism or memory access protocol
must be available to promote data coherency and, in some instances, to allow one processor to temporarily lock
a memory location.
•
To maintain cache consistency — When one processor accesses data cached on another processor, it must not
receive incorrect data. If it modifies data, all other processors that access that data must receive the modified
data.
•
To allow predictable ordering of writes to memory — In some circumstances, it is important that memory writes
be observed externally in precisely the same order as programmed.
•
To distribute interrupt handling among a group of processors — When several processors are operating in a
system in parallel, it is useful to have a centralized mechanism for receiving interrupts and distributing them to
available processors for servicing.
•
To increase system performance by exploiting the multi-threaded and multi-process nature of contemporary
operating systems and applications.
The caching mechanism and cache consistency of Intel 64 and IA-32 processors are discussed in Chapter 11. The
APIC architecture is described in Chapter 10. Bus and memory locking, serializing instructions, memory ordering,
and Intel Hyper-Threading Technology are discussed in the following sections.
8.1
LOCKED ATOMIC OPERATIONS
The 32-bit IA-32 processors support locked atomic operations on locations in system memory. These operations
are typically used to manage shared data structures (such as semaphores, segment descriptors, system segments,
or page tables) in which two or more processors may try simultaneously to modify the same field or flag. The
processor uses three interdependent mechanisms for carrying out locked atomic operations:
•
•
Guaranteed atomic operations
Bus locking, using the LOCK# signal and the LOCK instruction prefix
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MULTIPLE-PROCESSOR MANAGEMENT
•
Cache coherency protocols that ensure that atomic operations can be carried out on cached data structures
(cache lock); this mechanism is present in the Pentium 4, Intel Xeon, and P6 family processors
These mechanisms are interdependent in the following ways. Certain basic memory transactions (such as reading
or writing a byte in system memory) are always guaranteed to be handled atomically. That is, once started, the
processor guarantees that the operation will be completed before another processor or bus agent is allowed access
to the memory location. The processor also supports bus locking for performing selected memory operations (such
as a read-modify-write operation in a shared area of memory) that typically need to be handled atomically, but are
not automatically handled this way. Because frequently used memory locations are often cached in a processor’s L1
or L2 caches, atomic operations can often be carried out inside a processor’s caches without asserting the bus lock.
Here the processor’s cache coherency protocols ensure that other processors that are caching the same memory
locations are managed properly while atomic operations are performed on cached memory locations.
NOTE
Where there are contested lock accesses, software may need to implement algorithms that ensure
fair access to resources in order to prevent lock starvation. The hardware provides no resource that
guarantees fairness to participating agents. It is the responsibility of software to manage the
fairness of semaphores and exclusive locking functions.
The mechanisms for handling locked atomic operations have evolved with the complexity of IA-32 processors. More
recent IA-32 processors (such as the Pentium 4, Intel Xeon, and P6 family processors) and Intel 64 provide a more
refined locking mechanism than earlier processors. These mechanisms are described in the following sections.
8.1.1
Guaranteed Atomic Operations
The Intel486 processor (and newer processors since) guarantees that the following basic memory operations will
always be carried out atomically:
•
•
•
Reading or writing a byte
Reading or writing a word aligned on a 16-bit boundary
Reading or writing a doubleword aligned on a 32-bit boundary
The Pentium processor (and newer processors since) guarantees that the following additional memory operations
will always be carried out atomically:
•
•
Reading or writing a quadword aligned on a 64-bit boundary
16-bit accesses to uncached memory locations that fit within a 32-bit data bus
The P6 family processors (and newer processors since) guarantee that the following additional memory operation
will always be carried out atomically:
•
Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line
Accesses to cacheable memory that are split across cache lines and page boundaries are not guaranteed to be
atomic by the Intel Core 2 Duo, Intel® Atom™, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family,
Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel
Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split
accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and
should be avoided.
An x87 instruction or an SSE instructions that accesses data larger than a quadword may be implemented using
multiple memory accesses. If such an instruction stores to memory, some of the accesses may complete (writing
to memory) while another causes the operation to fault for architectural reasons (e.g. due an page-table entry that
is marked “not present”). In this case, the effects of the completed accesses may be visible to software even
though the overall instruction caused a fault. If TLB invalidation has been delayed (see Section 4.10.4.4), such
page faults may occur even if all accesses are to the same page.
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MULTIPLE-PROCESSOR MANAGEMENT
8.1.2
Bus Locking
Intel 64 and IA-32 processors provide a LOCK# signal that is asserted automatically during certain critical memory
operations to lock the system bus or equivalent link. While this output signal is asserted, requests from other
processors or bus agents for control of the bus are blocked. Software can specify other occasions when the LOCK
semantics are to be followed by prepending the LOCK prefix to an instruction.
In the case of the Intel386, Intel486, and Pentium processors, explicitly locked instructions will result in the assertion of the LOCK# signal. It is the responsibility of the hardware designer to make the LOCK# signal available in
system hardware to control memory accesses among processors.
For the P6 and more recent processor families, if the memory area being accessed is cached internally in the
processor, the LOCK# signal is generally not asserted; instead, locking is only applied to the processor’s caches
(see Section 8.1.4, “Effects of a LOCK Operation on Internal Processor Caches”).
8.1.2.1
Automatic Locking
The operations on which the processor automatically follows the LOCK semantics are as follows:
•
•
•
When executing an XCHG instruction that references memory.
When setting the B (busy) flag of a TSS descriptor — The processor tests and sets the busy flag in the
type field of the TSS descriptor when switching to a task. To ensure that two processors do not switch to the
same task simultaneously, the processor follows the LOCK semantics while testing and setting this flag.
When updating segment descriptors — When loading a segment descriptor, the processor will set the
accessed flag in the segment descriptor if the flag is clear. During this operation, the processor follows the
LOCK semantics so that the descriptor will not be modified by another processor while it is being updated. For
this action to be effective, operating-system procedures that update descriptors should use the following steps:
— Use a locked operation to modify the access-rights byte to indicate that the segment descriptor is notpresent, and specify a value for the type field that indicates that the descriptor is being updated.
— Update the fields of the segment descriptor. (This operation may require several memory accesses;
therefore, locked operations cannot be used.)
— Use a locked operation to modify the access-rights byte to indicate that the segment descriptor is valid and
present.
•
The Intel386 processor always updates the accessed flag in the segment descriptor, whether it is clear or not.
The Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors only update this flag if it is not already
set.
•
When updating page-directory and page-table entries — When updating page-directory and page-table
entries, the processor uses locked cycles to set the accessed and dirty flag in the page-directory and page-table
entries.
•
Acknowledging interrupts — After an interrupt request, an interrupt controller may use the data bus to send
the interrupt’s vector to the processor. The processor follows the LOCK semantics during this time to ensure
that no other data appears on the data bus while the vector is being transmitted.
8.1.2.2
Software Controlled Bus Locking
To explicitly force the LOCK semantics, software can use the LOCK prefix with the following instructions when they
are used to modify a memory location. An invalid-opcode exception (#UD) is generated when the LOCK prefix is
used with any other instruction or when no write operation is made to memory (that is, when the destination
operand is in a register).
•
•
•
•
•
The bit test and modify instructions (BTS, BTR, and BTC).
The exchange instructions (XADD, CMPXCHG, and CMPXCHG8B).
The LOCK prefix is automatically assumed for XCHG instruction.
The following single-operand arithmetic and logical instructions: INC, DEC, NOT, and NEG.
The following two-operand arithmetic and logical instructions: ADD, ADC, SUB, SBB, AND, OR, and XOR.
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MULTIPLE-PROCESSOR MANAGEMENT
A locked instruction is guaranteed to lock only the area of memory defined by the destination operand, but may be
interpreted by the system as a lock for a larger memory area.
Software should access semaphores (shared memory used for signalling between multiple processors) using identical addresses and operand lengths. For example, if one processor accesses a semaphore using a word access,
other processors should not access the semaphore using a byte access.
NOTE
Do not implement semaphores using the WC memory type. Do not perform non-temporal stores to
a cache line containing a location used to implement a semaphore.
The integrity of a bus lock is not affected by the alignment of the memory field. The LOCK semantics are followed
for as many bus cycles as necessary to update the entire operand. However, it is recommend that locked accesses
be aligned on their natural boundaries for better system performance:
•
•
•
•
Any boundary for an 8-bit access (locked or otherwise).
16-bit boundary for locked word accesses.
32-bit boundary for locked doubleword accesses.
64-bit boundary for locked quadword accesses.
Locked operations are atomic with respect to all other memory operations and all externally visible events. Only
instruction fetch and page table accesses can pass locked instructions. Locked instructions can be used to synchronize data written by one processor and read by another processor.
For the P6 family processors, locked operations serialize all outstanding load and store operations (that is, wait for
them to complete). This rule is also true for the Pentium 4 and Intel Xeon processors, with one exception. Load
operations that reference weakly ordered memory types (such as the WC memory type) may not be serialized.
Locked instructions should not be used to ensure that data written can be fetched as instructions.
NOTE
The locked instructions for the current versions of the Pentium 4, Intel Xeon, P6 family, Pentium,
and Intel486 processors allow data written to be fetched as instructions. However, Intel
recommends that developers who require the use of self-modifying code use a different synchronizing mechanism, described in the following sections.
8.1.3
Handling Self- and Cross-Modifying Code
The act of a processor writing data into a currently executing code segment with the intent of executing that data
as code is called self-modifying code. IA-32 processors exhibit model-specific behavior when executing selfmodified code, depending upon how far ahead of the current execution pointer the code has been modified.
As processor microarchitectures become more complex and start to speculatively execute code ahead of the retirement point (as in P6 and more recent processor families), the rules regarding which code should execute, pre- or
post-modification, become blurred. To write self-modifying code and ensure that it is compliant with current and
future versions of the IA-32 architectures, use one of the following coding options:
(* OPTION 1 *)
Store modified code (as data) into code segment;
Jump to new code or an intermediate location;
Execute new code;
(* OPTION 2 *)
Store modified code (as data) into code segment;
Execute a serializing instruction; (* For example, CPUID instruction *)
Execute new code;
The use of one of these options is not required for programs intended to run on the Pentium or Intel486 processors,
but are recommended to ensure compatibility with the P6 and more recent processor families.
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MULTIPLE-PROCESSOR MANAGEMENT
Self-modifying code will execute at a lower level of performance than non-self-modifying or normal code. The
degree of the performance deterioration will depend upon the frequency of modification and specific characteristics
of the code.
The act of one processor writing data into the currently executing code segment of a second processor with the
intent of having the second processor execute that data as code is called cross-modifying code. As with selfmodifying code, IA-32 processors exhibit model-specific behavior when executing cross-modifying code,
depending upon how far ahead of the executing processors current execution pointer the code has been modified.
To write cross-modifying code and ensure that it is compliant with current and future versions of the IA-32 architecture, the following processor synchronization algorithm must be implemented:
(* Action of Modifying Processor *)
Memory_Flag ← 0; (* Set Memory_Flag to value other than 1 *)
Store modified code (as data) into code segment;
Memory_Flag ← 1;
(* Action of Executing Processor *)
WHILE (Memory_Flag ≠ 1)
Wait for code to update;
ELIHW;
Execute serializing instruction; (* For example, CPUID instruction *)
Begin executing modified code;
(The use of this option is not required for programs intended to run on the Intel486 processor, but is recommended
to ensure compatibility with the Pentium 4, Intel Xeon, P6 family, and Pentium processors.)
Like self-modifying code, cross-modifying code will execute at a lower level of performance than non-cross-modifying (normal) code, depending upon the frequency of modification and specific characteristics of the code.
The restrictions on self-modifying code and cross-modifying code also apply to the Intel 64 architecture.
8.1.4
Effects of a LOCK Operation on Internal Processor Caches
For the Intel486 and Pentium processors, the LOCK# signal is always asserted on the bus during a LOCK operation,
even if the area of memory being locked is cached in the processor.
For the P6 and more recent processor families, if the area of memory being locked during a LOCK operation is
cached in the processor that is performing the LOCK operation as write-back memory and is completely contained
in a cache line, the processor may not assert the LOCK# signal on the bus. Instead, it will modify the memory location internally and allow it’s cache coherency mechanism to ensure that the operation is carried out atomically. This
operation is called “cache locking.” The cache coherency mechanism automatically prevents two or more processors that have cached the same area of memory from simultaneously modifying data in that area.
8.2
MEMORY ORDERING
The term memory ordering refers to the order in which the processor issues reads (loads) and writes (stores)
through the system bus to system memory. The Intel 64 and IA-32 architectures support several memory-ordering
models depending on the implementation of the architecture. For example, the Intel386 processor enforces
program ordering (generally referred to as strong ordering), where reads and writes are issued on the system
bus in the order they occur in the instruction stream under all circumstances.
To allow performance optimization of instruction execution, the IA-32 architecture allows departures from strongordering model called processor ordering in Pentium 4, Intel Xeon, and P6 family processors. These processorordering variations (called here the memory-ordering model) allow performance enhancing operations such as
allowing reads to go ahead of buffered writes. The goal of any of these variations is to increase instruction execution speeds, while maintaining memory coherency, even in multiple-processor systems.
Section 8.2.1 and Section 8.2.2 describe the memory-ordering implemented by Intel486, Pentium, Intel Core 2
Duo, Intel Atom, Intel Core Duo, Pentium 4, Intel Xeon, and P6 family processors. Section 8.2.3 gives examples
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MULTIPLE-PROCESSOR MANAGEMENT
illustrating the behavior of the memory-ordering model on IA-32 and Intel-64 processors. Section 8.2.4 considers
the special treatment of stores for string operations and Section 8.2.5 discusses how memory-ordering behavior
may be modified through the use of specific instructions.
8.2.1
Memory Ordering in the Intel® Pentium® and Intel486™ Processors
The Pentium and Intel486 processors follow the processor-ordered memory model; however, they operate as
strongly-ordered processors under most circumstances. Reads and writes always appear in programmed order at
the system bus—except for the following situation where processor ordering is exhibited. Read misses are
permitted to go ahead of buffered writes on the system bus when all the buffered writes are cache hits and, therefore, are not directed to the same address being accessed by the read miss.
In the case of I/O operations, both reads and writes always appear in programmed order.
Software intended to operate correctly in processor-ordered processors (such as the Pentium 4, Intel Xeon, and P6
family processors) should not depend on the relatively strong ordering of the Pentium or Intel486 processors.
Instead, it should ensure that accesses to shared variables that are intended to control concurrent execution
among processors are explicitly required to obey program ordering through the use of appropriate locking or serializing operations (see Section 8.2.5, “Strengthening or Weakening the Memory-Ordering Model”).
8.2.2
Memory Ordering in P6 and More Recent Processor Families
The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, and P6 family processors also use a processor-ordered
memory-ordering model that can be further defined as “write ordered with store-buffer forwarding.” This model
can be characterized as follows.
In a single-processor system for memory regions defined as write-back cacheable, the memory-ordering model
respects the following principles (Note the memory-ordering principles for single-processor and multipleprocessor systems are written from the perspective of software executing on the processor, where the term
“processor” refers to a logical processor. For example, a physical processor supporting multiple cores and/or Intel
Hyper-Threading Technology is treated as a multi-processor systems.):
•
•
•
Reads are not reordered with other reads.
Writes are not reordered with older reads.
Writes to memory are not reordered with other writes, with the following exceptions:
— streaming stores (writes) executed with the non-temporal move instructions (MOVNTI, MOVNTQ,
MOVNTDQ, MOVNTPS, and MOVNTPD); and
— string operations (see Section 8.2.4.1).
•
No write to memory may be reordered with an execution of the CLFLUSH instruction; a write may be reordered
with an execution of the CLFLUSHOPT instruction that flushes a cache line other than the one being written.1
Executions of the CLFLUSH instruction are not reordered with each other. Executions of CLFLUSHOPT that
access different cache lines may be reordered with each other. An execution of CLFLUSHOPT may be reordered
with an execution of CLFLUSH that accesses a different cache line.
•
•
•
•
Reads may be reordered with older writes to different locations but not with older writes to the same location.
•
•
•
LFENCE instructions cannot pass earlier reads.
Reads or writes cannot be reordered with I/O instructions, locked instructions, or serializing instructions.
Reads cannot pass earlier LFENCE and MFENCE instructions.
Writes and executions of CLFLUSH and CLFLUSHOPT cannot pass earlier LFENCE, SFENCE, and MFENCE
instructions.
SFENCE instructions cannot pass earlier writes or executions of CLFLUSH and CLFLUSHOPT.
MFENCE instructions cannot pass earlier reads, writes, or executions of CLFLUSH and CLFLUSHOPT.
1. Earlier versions of this manual specified that writes to memory may be reordered with executions of the CLFLUSH instruction. No
processors implementing the CLFLUSH instruction allow such reordering.
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In a multiple-processor system, the following ordering principles apply:
•
•
•
•
•
•
Individual processors use the same ordering principles as in a single-processor system.
Writes by a single processor are observed in the same order by all processors.
Writes from an individual processor are NOT ordered with respect to the writes from other processors.
Memory ordering obeys causality (memory ordering respects transitive visibility).
Any two stores are seen in a consistent order by processors other than those performing the stores
Locked instructions have a total order.
See the example in Figure 8-1. Consider three processors in a system and each processor performs three writes,
one to each of three defined locations (A, B, and C). Individually, the processors perform the writes in the same
program order, but because of bus arbitration and other memory access mechanisms, the order that the three
processors write the individual memory locations can differ each time the respective code sequences are executed
on the processors. The final values in location A, B, and C would possibly vary on each execution of the write
sequence.
The processor-ordering model described in this section is virtually identical to that used by the Pentium and
Intel486 processors. The only enhancements in the Pentium 4, Intel Xeon, and P6 family processors are:
•
•
•
Added support for speculative reads, while still adhering to the ordering principles above.
Store-buffer forwarding, when a read passes a write to the same memory location.
Out of order store from long string store and string move operations (see Section 8.2.4, “Fast-String Operation
and Out-of-Order Stores,” below).
Order of Writes From Individual Processors
Processor #1
Each processor
is guaranteed to
perform writes in
program order.
Write A.1
Write B.1
Write C.1
Processor #2
Write A.2
Write B.2
Write C.2
Processor #3
Write A.3
Write B.3
Write C.3
Example of order of actual writes
from all processors to memory
Writes are in order
with respect to
individual processes.
Write A.1
Write B.1
Write A.2
Write A.3
Write C.1
Write B.2
Write C.2
Write B.3
Write C.3
Writes from all
processors are
not guaranteed
to occur in a
particular order.
Figure 8-1. Example of Write Ordering in Multiple-Processor Systems
NOTE
In P6 processor family, store-buffer forwarding to reads of WC memory from streaming stores to the same address
does not occur due to errata.
8.2.3
Examples Illustrating the Memory-Ordering Principles
This section provides a set of examples that illustrate the behavior of the memory-ordering principles introduced in
Section 8.2.2. They are designed to give software writers an understanding of how memory ordering may affect
the results of different sequences of instructions.
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These examples are limited to accesses to memory regions defined as write-back cacheable (WB). (Section 8.2.3.1
describes other limitations on the generality of the examples.) The reader should understand that they describe
only software-visible behavior. A logical processor may reorder two accesses even if one of examples indicates that
they may not be reordered. Such an example states only that software cannot detect that such a reordering
occurred. Similarly, a logical processor may execute a memory access more than once as long as the behavior
visible to software is consistent with a single execution of the memory access.
8.2.3.1
Assumptions, Terminology, and Notation
As noted above, the examples in this section are limited to accesses to memory regions defined as write-back
cacheable (WB). They apply only to ordinary loads stores and to locked read-modify-write instructions. They do not
necessarily apply to any of the following: out-of-order stores for string instructions (see Section 8.2.4); accesses
with a non-temporal hint; reads from memory by the processor as part of address translation (e.g., page walks);
and updates to segmentation and paging structures by the processor (e.g., to update “accessed” bits).
The principles underlying the examples in this section apply to individual memory accesses and to locked readmodify-write instructions. The Intel-64 memory-ordering model guarantees that, for each of the following
memory-access instructions, the constituent memory operation appears to execute as a single memory access:
•
•
•
•
Instructions that read or write a single byte.
Instructions that read or write a word (2 bytes) whose address is aligned on a 2 byte boundary.
Instructions that read or write a doubleword (4 bytes) whose address is aligned on a 4 byte boundary.
Instructions that read or write a quadword (8 bytes) whose address is aligned on an 8 byte boundary.
Any locked instruction (either the XCHG instruction or another read-modify-write instruction with a LOCK prefix)
appears to execute as an indivisible and uninterruptible sequence of load(s) followed by store(s) regardless of
alignment.
Other instructions may be implemented with multiple memory accesses. From a memory-ordering point of view,
there are no guarantees regarding the relative order in which the constituent memory accesses are made. There is
also no guarantee that the constituent operations of a store are executed in the same order as the constituent
operations of a load.
Section 8.2.3.2 through Section 8.2.3.7 give examples using the MOV instruction. The principles that underlie
these examples apply to load and store accesses in general and to other instructions that load from or store to
memory. Section 8.2.3.8 and Section 8.2.3.9 give examples using the XCHG instruction. The principles that
underlie these examples apply to other locked read-modify-write instructions.
This section uses the term “processor” is to refer to a logical processor. The examples are written using Intel-64
assembly-language syntax and use the following notational conventions:
•
Arguments beginning with an “r”, such as r1 or r2 refer to registers (e.g., EAX) visible only to the processor
being considered.
•
•
•
Memory locations are denoted with x, y, z.
Stores are written as mov [ _x], val, which implies that val is being stored into the memory location x.
Loads are written as mov r, [ _x], which implies that the contents of the memory location x are being loaded
into the register r.
As noted earlier, the examples refer only to software visible behavior. When the succeeding sections make statement such as “the two stores are reordered,” the implication is only that “the two stores appear to be reordered
from the point of view of software.”
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8.2.3.2
Neither Loads Nor Stores Are Reordered with Like Operations
The Intel-64 memory-ordering model allows neither loads nor stores to be reordered with the same kind of operation. That is, it ensures that loads are seen in program order and that stores are seen in program order. This is illustrated by the following example:
Example 8-1. Stores Are Not Reordered with Other Stores
Processor 0
Processor 1
mov [ _x], 1
mov r1, [ _y]
mov [ _y], 1
mov r2, [ _x]
Initially x = y = 0
r1 = 1 and r2 = 0 is not allowed
The disallowed return values could be exhibited only if processor 0’s two stores are reordered (with the two loads
occurring between them) or if processor 1’s two loads are reordered (with the two stores occurring between them).
If r1 = 1, the store to y occurs before the load from y. Because the Intel-64 memory-ordering model does not allow
stores to be reordered, the earlier store to x occurs before the load from y. Because the Intel-64 memory-ordering
model does not allow loads to be reordered, the store to x also occurs before the later load from x. This r2 = 1.
8.2.3.3
Stores Are Not Reordered With Earlier Loads
The Intel-64 memory-ordering model ensures that a store by a processor may not occur before a previous load by
the same processor. This is illustrated by the following example:
Example 8-2. Stores Are Not Reordered with Older Loads
Processor 0
Processor 1
mov r1, [ _x]
mov r2, [ _y]
mov [ _y], 1
mov [ _x], 1
Initially x = y = 0
r1 = 1 and r2 = 1 is not allowed
Assume r1 = 1.
•
•
Because r1 = 1, processor 1’s store to x occurs before processor 0’s load from x.
•
•
Similarly, processor 0’s load from x occurs before its store to y.
Because the Intel-64 memory-ordering model prevents each store from being reordered with the earlier load
by the same processor, processor 1’s load from y occurs before its store to x.
Thus, processor 1’s load from y occurs before processor 0’s store to y, implying r2 = 0.
8.2.3.4
Loads May Be Reordered with Earlier Stores to Different Locations
The Intel-64 memory-ordering model allows a load to be reordered with an earlier store to a different location.
However, loads are not reordered with stores to the same location.
The fact that a load may be reordered with an earlier store to a different location is illustrated by the following
example:
Example 8-3. Loads May be Reordered with Older Stores
Processor 0
Processor 1
mov [ _x], 1
mov [ _y], 1
mov r1, [ _y]
mov r2, [ _x]
Initially x = y = 0
r1 = 0 and r2 = 0 is allowed
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At each processor, the load and the store are to different locations and hence may be reordered. Any interleaving
of the operations is thus allowed. One such interleaving has the two loads occurring before the two stores. This
would result in each load returning value 0.
The fact that a load may not be reordered with an earlier store to the same location is illustrated by the following
example:
Example 8-4. Loads Are not Reordered with Older Stores to the Same Location
Processor 0
mov [ _x], 1
mov r1, [ _x]
Initially x = 0
r1 = 0 is not allowed
The Intel-64 memory-ordering model does not allow the load to be reordered with the earlier store because the
accesses are to the same location. Therefore, r1 = 1 must hold.
8.2.3.5
Intra-Processor Forwarding Is Allowed
The memory-ordering model allows concurrent stores by two processors to be seen in different orders by those two
processors; specifically, each processor may perceive its own store occurring before that of the other. This is illustrated by the following example:
Example 8-5. Intra-Processor Forwarding is Allowed
Processor 0
Processor 1
mov [ _x], 1
mov [ _y], 1
mov r1, [ _x]
mov r3, [ _y]
mov r2, [ _y]
mov r4, [ _x]
Initially x = y = 0
r2 = 0 and r4 = 0 is allowed
The memory-ordering model imposes no constraints on the order in which the two stores appear to execute by the
two processors. This fact allows processor 0 to see its store before seeing processor 1's, while processor 1 sees its
store before seeing processor 0's. (Each processor is self consistent.) This allows r2 = 0 and r4 = 0.
In practice, the reordering in this example can arise as a result of store-buffer forwarding. While a store is temporarily held in a processor's store buffer, it can satisfy the processor's own loads but is not visible to (and cannot
satisfy) loads by other processors.
8.2.3.6
Stores Are Transitively Visible
The memory-ordering model ensures transitive visibility of stores; stores that are causally related appear to all
processors to occur in an order consistent with the causality relation. This is illustrated by the following example:
Example 8-6. Stores Are Transitively Visible
Processor 0
mov [ _x], 1
Processor 1
Processor 2
mov r1, [ _x]
mov [ _y], 1
mov r2, [ _y]
mov r3, [_x]
Initially x = y = 0
r1 = 1, r2 = 1, r3 = 0 is not allowed
Assume that r1 = 1 and r2 = 1.
•
Because r1 = 1, processor 0’s store occurs before processor 1’s load.
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•
Because the memory-ordering model prevents a store from being reordered with an earlier load (see Section
8.2.3.3), processor 1’s load occurs before its store. Thus, processor 0’s store causally precedes processor 1’s
store.
•
Because processor 0’s store causally precedes processor 1’s store, the memory-ordering model ensures that
processor 0’s store appears to occur before processor 1’s store from the point of view of all processors.
•
•
Because r2 = 1, processor 1’s store occurs before processor 2’s load.
•
The above items imply that processor 0’s store to x occurs before processor 2’s load from x. This implies that
r3 = 1.
Because the Intel-64 memory-ordering model prevents loads from being reordered (see Section 8.2.3.2),
processor 2’s load occur in order.
8.2.3.7
Stores Are Seen in a Consistent Order by Other Processors
As noted in Section 8.2.3.5, the memory-ordering model allows stores by two processors to be seen in different
orders by those two processors. However, any two stores must appear to execute in the same order to all processors other than those performing the stores. This is illustrated by the following example:
Example 8-7. Stores Are Seen in a Consistent Order by Other Processors
Processor 0
Processor 1
Processor 2
mov [ _x], 1
mov [ _y], 1
Processor 3
mov r1, [ _x]
mov r3, [_y]
mov r2, [ _y]
mov r4, [_x]
Initially x = y =0
r1 = 1, r2 = 0, r3 = 1, r4 = 0 is not allowed
By the principles discussed in Section 8.2.3.2,
•
•
•
•
processor 2’s first and second load cannot be reordered,
processor 3’s first and second load cannot be reordered.
If r1 = 1 and r2 = 0, processor 0’s store appears to precede processor 1’s store with respect to processor 2.
Similarly, r3 = 1 and r4 = 0 imply that processor 1’s store appears to precede processor 0’s store with respect
to processor 1.
Because the memory-ordering model ensures that any two stores appear to execute in the same order to all
processors (other than those performing the stores), this set of return values is not allowed
8.2.3.8
Locked Instructions Have a Total Order
The memory-ordering model ensures that all processors agree on a single execution order of all locked instructions, including those that are larger than 8 bytes or are not naturally aligned. This is illustrated by the following
example:
Example 8-8. Locked Instructions Have a Total Order
Processor 0
Processor 1
xchg [ _x], r1
Processor 2
Processor 3
xchg [ _y], r2
mov r3, [ _x]
mov r5, [_y]
mov r4, [ _y]
mov r6, [_x]
Initially r1 = r2 = 1, x = y = 0
r3 = 1, r4 = 0, r5 = 1, r6 = 0 is not allowed
Processor 2 and processor 3 must agree on the order of the two executions of XCHG. Without loss of generality,
suppose that processor 0’s XCHG occurs first.
•
If r5 = 1, processor 1’s XCHG into y occurs before processor 3’s load from y.
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•
Because the Intel-64 memory-ordering model prevents loads from being reordered (see Section 8.2.3.2),
processor 3’s loads occur in order and, therefore, processor 1’s XCHG occurs before processor 3’s load from x.
•
Since processor 0’s XCHG into x occurs before processor 1’s XCHG (by assumption), it occurs before
processor 3’s load from x. Thus, r6 = 1.
A similar argument (referring instead to processor 2’s loads) applies if processor 1’s XCHG occurs before
processor 0’s XCHG.
8.2.3.9
Loads and Stores Are Not Reordered with Locked Instructions
The memory-ordering model prevents loads and stores from being reordered with locked instructions that execute
earlier or later. The examples in this section illustrate only cases in which a locked instruction is executed before a
load or a store. The reader should note that reordering is prevented also if the locked instruction is executed after
a load or a store.
The first example illustrates that loads may not be reordered with earlier locked instructions:
Example 8-9. Loads Are not Reordered with Locks
Processor 0
Processor 1
xchg [ _x], r1
xchg [ _y], r3
mov r2, [ _y]
mov r4, [ _x]
Initially x = y = 0, r1 = r3 = 1
r2 = 0 and r4 = 0 is not allowed
As explained in Section 8.2.3.8, there is a total order of the executions of locked instructions. Without loss of
generality, suppose that processor 0’s XCHG occurs first.
Because the Intel-64 memory-ordering model prevents processor 1’s load from being reordered with its earlier
XCHG, processor 0’s XCHG occurs before processor 1’s load. This implies r4 = 1.
A similar argument (referring instead to processor 2’s accesses) applies if processor 1’s XCHG occurs before
processor 0’s XCHG.
The second example illustrates that a store may not be reordered with an earlier locked instruction:
Example 8-10. Stores Are not Reordered with Locks
Processor 0
Processor 1
xchg [ _x], r1
mov r2, [ _y]
mov [ _y], 1
mov r3, [ _x]
Initially x = y = 0, r1 = 1
r2 = 1 and r3 = 0 is not allowed
Assume r2 = 1.
•
•
Because r2 = 1, processor 0’s store to y occurs before processor 1’s load from y.
•
Because the memory-ordering model prevents loads from being reordered (see Section 8.2.3.2), processor 1’s
loads occur in order and, therefore, processor 1’s XCHG into x occurs before processor 1’s load from x. Thus,
r3 = 1.
Because the memory-ordering model prevents a store from being reordered with an earlier locked instruction,
processor 0’s XCHG into x occurs before its store to y. Thus, processor 0’s XCHG into x occurs before
processor 1’s load from y.
8.2.4
Fast-String Operation and Out-of-Order Stores
Section 7.3.9.3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 described an optimization of repeated string operations called fast-string operation.
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As explained in that section, the stores produced by fast-string operation may appear to execute out of order. Software dependent upon sequential store ordering should not use string operations for the entire data structure to be
stored. Data and semaphores should be separated. Order-dependent code should write to a discrete semaphore
variable after any string operations to allow correctly ordered data to be seen by all processors. Atomicity of load
and store operations is guaranteed only for native data elements of the string with native data size, and only if they
are included in a single cache line.
Section 8.2.4.1 and Section 8.2.4.2 provide further explain and examples.
8.2.4.1
Memory-Ordering Model for String Operations on Write-Back (WB) Memory
This section deals with the memory-ordering model for string operations on write-back (WB) memory for the Intel
64 architecture.
The memory-ordering model respects the follow principles:
1. Stores within a single string operation may be executed out of order.
2. Stores from separate string operations (for example, stores from consecutive string operations) do not execute
out of order. All the stores from an earlier string operation will complete before any store from a later string
operation.
3. String operations are not reordered with other store operations.
Fast string operations (e.g. string operations initiated with the MOVS/STOS instructions and the REP prefix) may be
interrupted by exceptions or interrupts. The interrupts are precise but may be delayed - for example, the interruptions may be taken at cache line boundaries, after every few iterations of the loop, or after operating on every few
bytes. Different implementations may choose different options, or may even choose not to delay interrupt
handling, so software should not rely on the delay. When the interrupt/trap handler is reached, the source/destination registers point to the next string element to be operated on, while the EIP stored in the stack points to the
string instruction, and the ECX register has the value it held following the last successful iteration. The return from
that trap/interrupt handler should cause the string instruction to be resumed from the point where it was interrupted.
The string operation memory-ordering principles, (item 2 and 3 above) should be interpreted by taking the incorruptibility of fast string operations into account. For example, if a fast string operation gets interrupted after k iterations, then stores performed by the interrupt handler will become visible after the fast string stores from iteration
0 to k, and before the fast string stores from the (k+1)th iteration onward.
Stores within a single string operation may execute out of order (item 1 above) only if fast string operation is
enabled. Fast string operations are enabled/disabled through the IA32_MISC_ENABLE model specific register.
8.2.4.2
Examples Illustrating Memory-Ordering Principles for String Operations
The following examples uses the same notation and convention as described in Section 8.2.3.1.
In Example 8-11, processor 0 does one round of (128 iterations) doubleword string store operation via rep:stosd,
writing the value 1 (value in EAX) into a block of 512 bytes from location _x (kept in ES:EDI) in ascending order.
Since each operation stores a doubleword (4 bytes), the operation is repeated 128 times (value in ECX). The block
of memory initially contained 0. Processor 1 is reading two memory locations that are part of the memory block
being updated by processor 0, i.e, reading locations in the range _x to (_x+511).
Example 8-11. Stores Within a String Operation May be Reordered
Processor 0
rep:stosd [ _x]
Processor 1
mov r1, [ _z]
mov r2, [ _y]
Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x
Initially [_x] to 511[_x]= 0, _x <= _y < _z < _x+512
r1 = 1 and r2 = 0 is allowed
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It is possible for processor 1 to perceive that the repeated string stores in processor 0 are happening out of order.
Assume that fast string operations are enabled on processor 0.
In Example 8-12, processor 0 does two separate rounds of rep stosd operation of 128 doubleword stores, writing
the value 1 (value in EAX) into the first block of 512 bytes from location _x (kept in ES:EDI) in ascending order. It
then writes 1 into a second block of memory from (_x+512) to (_x+1023). All of the memory locations initially
contain 0. The block of memory initially contained 0. Processor 1 performs two load operations from the two blocks
of memory.
Example 8-12. Stores Across String Operations Are not Reordered
Processor 0
Processor 1
rep:stosd [ _x]
mov r1, [ _z]
mov ecx, $128
mov r2, [ _y]
rep:stosd 512[ _x]
Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x
Initially [_x] to 1023[_x]= 0, _x <= _y < _x+512 < _z < _x+1024
r1 = 1 and r2 = 0 is not allowed
It is not possible in the above example for processor 1 to perceive any of the stores from the later string operation
(to the second 512 block) in processor 0 before seeing the stores from the earlier string operation to the first 512
block.
The above example assumes that writes to the second block (_x+512 to _x+1023) does not get executed while
processor 0’s string operation to the first block has been interrupted. If the string operation to the first block by
processor 0 is interrupted, and a write to the second memory block is executed by the interrupt handler, then that
change in the second memory block will be visible before the string operation to the first memory block resumes.
In Example 8-13, processor 0 does one round of (128 iterations) doubleword string store operation via rep:stosd,
writing the value 1 (value in EAX) into a block of 512 bytes from location _x (kept in ES:EDI) in ascending order. It
then writes to a second memory location outside the memory block of the previous string operation. Processor 1
performs two read operations, the first read is from an address outside the 512-byte block but to be updated by
processor 0, the second ready is from inside the block of memory of string operation.
Example 8-13. String Operations Are not Reordered with later Stores
Processor 0
rep:stosd [ _x]
mov r1, [ _z]
mov [_z], $1
mov r2, [ _y]
Processor 1
Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x
Initially [_y] = [_z] = 0, [_x] to 511[_x]= 0, _x <= _y < _x+512, _z is a separate memory location
r1 = 1 and r2 = 0 is not allowed
Processor 1 cannot perceive the later store by processor 0 until it sees all the stores from the string operation.
Example 8-13 assumes that processor 0’s store to [_z] is not executed while the string operation has been interrupted. If the string operation is interrupted and the store to [_z] by processor 0 is executed by the interrupt
handler, then changes to [_z] will become visible before the string operation resumes.
Example 8-14 illustrates the visibility principle when a string operation is interrupted.
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Example 8-14. Interrupted String Operation
Processor 0
Processor 1
rep:stosd [ _x] // interrupted before es:edi reach _y
mov r1, [ _z]
mov [_z], $1 // interrupt handler
mov r2, [ _y]
Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x
Initially [_y] = [_z] = 0, [_x] to 511[_x]= 0, _x <= _y < _x+512, _z is a separate memory location
r1 = 1 and r2 = 0 is allowed
In Example 8-14, processor 0 started a string operation to write to a memory block of 512 bytes starting at address
_x. Processor 0 got interrupted after k iterations of store operations. The address _y has not yet been updated by
processor 0 when processor 0 got interrupted. The interrupt handler that took control on processor 0 writes to the
address _z. Processor 1 may see the store to _z from the interrupt handler, before seeing the remaining stores to
the 512-byte memory block that are executed when the string operation resumes.
Example 8-15 illustrates the ordering of string operations with earlier stores. No store from a string operation can
be visible before all prior stores are visible.
Example 8-15. String Operations Are not Reordered with Earlier Stores
Processor 0
mov [_z], $1
mov r1, [ _y]
rep:stosd [ _x]
mov r2, [ _z]
Processor 1
Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x
Initially [_y] = [_z] = 0, [_x] to 511[_x]= 0, _x <= _y < _x+512, _z is a separate memory location
r1 = 1 and r2 = 0 is not allowed
8.2.5
Strengthening or Weakening the Memory-Ordering Model
The Intel 64 and IA-32 architectures provide several mechanisms for strengthening or weakening the memoryordering model to handle special programming situations. These mechanisms include:
•
The I/O instructions, locking instructions, the LOCK prefix, and serializing instructions force stronger ordering
on the processor.
•
The SFENCE instruction (introduced to the IA-32 architecture in the Pentium III processor) and the LFENCE and
MFENCE instructions (introduced in the Pentium 4 processor) provide memory-ordering and serialization
capabilities for specific types of memory operations.
•
The memory type range registers (MTRRs) can be used to strengthen or weaken memory ordering for specific
area of physical memory (see Section 11.11, “Memory Type Range Registers (MTRRs)”). MTRRs are available
only in the Pentium 4, Intel Xeon, and P6 family processors.
•
The page attribute table (PAT) can be used to strengthen memory ordering for a specific page or group of pages
(see Section 11.12, “Page Attribute Table (PAT)”). The PAT is available only in the Pentium 4, Intel Xeon, and
Pentium III processors.
These mechanisms can be used as follows:
Memory mapped devices and other I/O devices on the bus are often sensitive to the order of writes to their I/O
buffers. I/O instructions can be used to (the IN and OUT instructions) impose strong write ordering on such
accesses as follows. Prior to executing an I/O instruction, the processor waits for all previous instructions in the
program to complete and for all buffered writes to drain to memory. Only instruction fetch and page tables walks
can pass I/O instructions. Execution of subsequent instructions do not begin until the processor determines that
the I/O instruction has been completed.
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Synchronization mechanisms in multiple-processor systems may depend upon a strong memory-ordering model.
Here, a program can use a locking instruction such as the XCHG instruction or the LOCK prefix to ensure that a
read-modify-write operation on memory is carried out atomically. Locking operations typically operate like I/O
operations in that they wait for all previous instructions to complete and for all buffered writes to drain to memory
(see Section 8.1.2, “Bus Locking”).
Program synchronization can also be carried out with serializing instructions (see Section 8.3). These instructions
are typically used at critical procedure or task boundaries to force completion of all previous instructions before a
jump to a new section of code or a context switch occurs. Like the I/O and locking instructions, the processor waits
until all previous instructions have been completed and all buffered writes have been drained to memory before
executing the serializing instruction.
The SFENCE, LFENCE, and MFENCE instructions provide a performance-efficient way of ensuring load and store
memory ordering between routines that produce weakly-ordered results and routines that consume that data. The
functions of these instructions are as follows:
•
SFENCE — Serializes all store (write) operations that occurred prior to the SFENCE instruction in the program
instruction stream, but does not affect load operations.
•
LFENCE — Serializes all load (read) operations that occurred prior to the LFENCE instruction in the program
instruction stream, but does not affect store operations.2
•
MFENCE — Serializes all store and load operations that occurred prior to the MFENCE instruction in the
program instruction stream.
Note that the SFENCE, LFENCE, and MFENCE instructions provide a more efficient method of controlling memory
ordering than the CPUID instruction.
The MTRRs were introduced in the P6 family processors to define the cache characteristics for specified areas of
physical memory. The following are two examples of how memory types set up with MTRRs can be used strengthen
or weaken memory ordering for the Pentium 4, Intel Xeon, and P6 family processors:
•
The strong uncached (UC) memory type forces a strong-ordering model on memory accesses. Here, all reads
and writes to the UC memory region appear on the bus and out-of-order or speculative accesses are not
performed. This memory type can be applied to an address range dedicated to memory mapped I/O devices to
force strong memory ordering.
•
For areas of memory where weak ordering is acceptable, the write back (WB) memory type can be chosen.
Here, reads can be performed speculatively and writes can be buffered and combined. For this type of memory,
cache locking is performed on atomic (locked) operations that do not split across cache lines, which helps to
reduce the performance penalty associated with the use of the typical synchronization instructions, such as
XCHG, that lock the bus during the entire read-modify-write operation. With the WB memory type, the XCHG
instruction locks the cache instead of the bus if the memory access is contained within a cache line.
The PAT was introduced in the Pentium III processor to enhance the caching characteristics that can be assigned to
pages or groups of pages. The PAT mechanism typically used to strengthen caching characteristics at the page level
with respect to the caching characteristics established by the MTRRs. Table 11-7 shows the interaction of the PAT
with the MTRRs.
Intel recommends that software written to run on Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, Intel
Xeon, and P6 family processors assume the processor-ordering model or a weaker memory-ordering model. The
Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, Intel Xeon, and P6 family processors do not implement a
strong memory-ordering model, except when using the UC memory type. Despite the fact that Pentium 4, Intel
Xeon, and P6 family processors support processor ordering, Intel does not guarantee that future processors will
support this model. To make software portable to future processors, it is recommended that operating systems
provide critical region and resource control constructs and API’s (application program interfaces) based on I/O,
locking, and/or serializing instructions be used to synchronize access to shared areas of memory in multipleprocessor systems. Also, software should not depend on processor ordering in situations where the system hardware does not support this memory-ordering model.
2. Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruction begins execution
until LFENCE completes. As a result, an instruction that loads from memory and that precedes an LFENCE receives data from memory prior to completion of the LFENCE. An LFENCE that follows an instruction that stores to memory might complete before the data
being stored have become globally visible. Instructions following an LFENCE may be fetched from memory before the LFENCE, but
they will not execute until the LFENCE completes.
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8.3
SERIALIZING INSTRUCTIONS
The Intel 64 and IA-32 architectures define several serializing instructions. These instructions force the
processor to complete all modifications to flags, registers, and memory by previous instructions and to drain all
buffered writes to memory before the next instruction is fetched and executed. For example, when a MOV to
control register instruction is used to load a new value into control register CR0 to enable protected mode, the
processor must perform a serializing operation before it enters protected mode. This serializing operation ensures
that all operations that were started while the processor was in real-address mode are completed before the switch
to protected mode is made.
The concept of serializing instructions was introduced into the IA-32 architecture with the Pentium processor to
support parallel instruction execution. Serializing instructions have no meaning for the Intel486 and earlier processors that do not implement parallel instruction execution.
It is important to note that executing of serializing instructions on P6 and more recent processor families constrain
speculative execution because the results of speculatively executed instructions are discarded. The following
instructions are serializing instructions:
•
Privileged serializing instructions — INVD, INVEPT, INVLPG, INVVPID, LGDT, LIDT, LLDT, LTR, MOV (to
control register, with the exception of MOV CR83), MOV (to debug register), WBINVD, and WRMSR4.
•
Non-privileged serializing instructions — CPUID, IRET, and RSM.
When the processor serializes instruction execution, it ensures that all pending memory transactions are
completed (including writes stored in its store buffer) before it executes the next instruction. Nothing can pass a
serializing instruction and a serializing instruction cannot pass any other instruction (read, write, instruction fetch,
or I/O). For example, CPUID can be executed at any privilege level to serialize instruction execution with no effect
on program flow, except that the EAX, EBX, ECX, and EDX registers are modified.
The following instructions are memory-ordering instructions, not serializing instructions. These drain the data
memory subsystem. They do not serialize the instruction execution stream:5
•
Non-privileged memory-ordering instructions — SFENCE, LFENCE, and MFENCE.
The SFENCE, LFENCE, and MFENCE instructions provide more granularity in controlling the serialization of memory
loads and stores (see Section 8.2.5, “Strengthening or Weakening the Memory-Ordering Model”).
The following additional information is worth noting regarding serializing instructions:
•
The processor does not write back the contents of modified data in its data cache to external memory when it
serializes instruction execution. Software can force modified data to be written back by executing the WBINVD
instruction, which is a serializing instruction. The amount of time or cycles for WBINVD to complete will vary
due to the size of different cache hierarchies and other factors. As a consequence, the use of the WBINVD
instruction can have an impact on interrupt/event response time.
•
When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register
CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is
fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction
itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require
the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4,
Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards
and forward compatibility with code written to run on other IA-32 processors, it is recommended that the jump
operation be performed.
•
Whenever an instruction is executed to change the contents of CR3 while paging is enabled, the next
instruction is fetched using the translation tables that correspond to the new value of CR3. Therefore the next
instruction and the sequentially following instructions should have a mapping based upon the new value of
CR3. (Global entries in the TLBs are not invalidated, see Section 4.10.4, “Invalidation of TLBs and PagingStructure Caches.”)
3. MOV CR8 is not defined architecturally as a serializing instruction.
4. WRMSR to the IA32_TSC_DEADLINE MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.
5. LFENCE does provide some guarantees on instruction ordering. It does not execute until all prior instructions have completed locally,
and no later instruction begins execution until LFENCE completes.
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•
The Pentium processor and more recent processor families use branch-prediction techniques to improve
performance by prefetching the destination of a branch instruction before the branch instruction is executed.
Consequently, instruction execution is not deterministically serialized when a branch instruction is executed.
8.4
MULTIPLE-PROCESSOR (MP) INITIALIZATION
The IA-32 architecture (beginning with the P6 family processors) defines a multiple-processor (MP) initialization
protocol called the Multiprocessor Specification Version 1.4. This specification defines the boot protocol to be used
by IA-32 processors in multiple-processor systems. (Here, multiple processors is defined as two or more processors.) The MP initialization protocol has the following important features:
•
•
It supports controlled booting of multiple processors without requiring dedicated system hardware.
•
It allows all IA-32 processors to be booted in the same manner, including those supporting Intel HyperThreading Technology.
•
The MP initialization protocol also applies to MP systems using Intel 64 processors.
It allows hardware to initiate the booting of a system without the need for a dedicated signal or a predefined
boot processor.
The mechanism for carrying out the MP initialization protocol differs depending on the Intel processor generations.
The following bullets summarizes the evolution of the changes:
•
For P6 family or older processors supporting MP operations— The selection of the BSP and APs (see
Section 8.4.1, “BSP and AP Processors”) is handled through arbitration on the APIC bus, using BIPI and FIPI
messages. These processor generations have CPUID signatures of (family=06H, extended_model=0,
model<=0DH), or family <06H. See Section 8.11.1, “Overview of the MP Initialization Process For P6 Family
Processors” for a complete discussion of MP initialization for P6 family processors.
•
Early generations of IA processors with family 0FH — The selection of the BSP and APs (see Section
8.4.1, “BSP and AP Processors”) is handled through arbitration on the system bus, using BIPI and FIPI
messages (see Section 8.4.3, “MP Initialization Protocol Algorithm for MP Systems”). These processor
generations have CPUID signatures of family=0FH, model=0H, stepping<=09H.
•
Later generations of IA processors with family 0FH, and IA processors with system bus — The
selection of the BSP and APs is handled through a special system bus cycle, without using BIPI and FIPI
message arbitration (see Section 8.4.3, “MP Initialization Protocol Algorithm for MP Systems”). These
processor generations have CPUID signatures of family=0FH with (model=0H, stepping>=0AH) or (model >0,
all steppings); or family=06H, extended_model=0, model>=0EH.
•
All other modern IA processor generations supporting MP operations— The selection of the BSP and
APs in the system is handled by platform-specific arrangement of the combination of hardware, BIOS, and/or
configuration input options. The basis of the selection mechanism is similar to those of the Later generations of
family 0FH and other Intel processor using system bus (see Section 8.4.3, “MP Initialization Protocol Algorithm
for MP Systems”). These processor generations have CPUID signatures of family=06H, extended_model>0.
The family, model, and stepping ID for a processor is given in the EAX register when the CPUID instruction is
executed with a value of 1 in the EAX register.
8.4.1
BSP and AP Processors
The MP initialization protocol defines two classes of processors: the bootstrap processor (BSP) and the application
processors (APs). Following a power-up or RESET of an MP system, system hardware dynamically selects one of the
processors on the system bus as the BSP. The remaining processors are designated as APs.
As part of the BSP selection mechanism, the BSP flag is set in the IA32_APIC_BASE MSR (see Figure 10-5) of the
BSP, indicating that it is the BSP. This flag is cleared for all other processors.
The BSP executes the BIOS’s boot-strap code to configure the APIC environment, sets up system-wide data structures, and starts and initializes the APs. When the BSP and APs are initialized, the BSP then begins executing the
operating-system initialization code.
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Following a power-up or reset, the APs complete a minimal self-configuration, then wait for a startup signal (a SIPI
message) from the BSP processor. Upon receiving a SIPI message, an AP executes the BIOS AP configuration code,
which ends with the AP being placed in halt state.
For Intel 64 and IA-32 processors supporting Intel Hyper-Threading Technology, the MP initialization protocol treats
each of the logical processors on the system bus or coherent link domain as a separate processor (with a unique
APIC ID). During boot-up, one of the logical processors is selected as the BSP and the remainder of the logical
processors are designated as APs.
8.4.2
MP Initialization Protocol Requirements and Restrictions
The MP initialization protocol imposes the following requirements and restrictions on the system:
•
The MP protocol is executed only after a power-up or RESET. If the MP protocol has completed and a BSP is
chosen, subsequent INITs (either to a specific processor or system wide) do not cause the MP protocol to be
repeated. Instead, each logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) to determine
whether it should execute the BIOS boot-strap code (if it is the BSP) or enter a wait-for-SIPI state (if it is an
AP).
•
All devices in the system that are capable of delivering interrupts to the processors must be inhibited from
doing so for the duration of the MP initialization protocol. The time during which interrupts must be inhibited
includes the window between when the BSP issues an INIT-SIPI-SIPI sequence to an AP and when the AP
responds to the last SIPI in the sequence.
8.4.3
MP Initialization Protocol Algorithm for MP Systems
Following a power-up or RESET of an MP system, the processors in the system execute the MP initialization protocol
algorithm to initialize each of the logical processors on the system bus or coherent link domain. In the course of
executing this algorithm, the following boot-up and initialization operations are carried out:
1. Each logical processor is assigned a unique APIC ID, based on system topology. The unique ID is a 32-bit value
if the processor supports CPUID leaf 0BH, otherwise the unique ID is an 8-bit value. (see Section 8.4.5, “Identifying Logical Processors in an MP System”).
2. Each logical processor is assigned a unique arbitration priority based on its APIC ID.
3. Each logical processor executes its internal BIST simultaneously with the other logical processors in the
system.
4. Upon completion of the BIST, the logical processors use a hardware-defined selection mechanism to select the
BSP and the APs from the available logical processors on the system bus. The BSP selection mechanism differs
depending on the family, model, and stepping IDs of the processors, as follows:
— Later generations of IA processors within family 0FH (see Section 8.4), IA processors with system bus
(family=06H, extended_model=0, model>=0EH), or all other modern Intel processors (family=06H,
extended_model>0):
•
The logical processors begin monitoring the BNR# signal, which is toggling. When the BNR# pin stops
toggling, each processor attempts to issue a NOP special cycle on the system bus.
•
The logical processor with the highest arbitration priority succeeds in issuing a NOP special cycle and is
nominated the BSP. This processor sets the BSP flag in its IA32_APIC_BASE MSR, then fetches and
begins executing BIOS boot-strap code, beginning at the reset vector (physical address FFFF FFF0H).
•
The remaining logical processors (that failed in issuing a NOP special cycle) are designated as APs. They
leave their BSP flags in the clear state and enter a “wait-for-SIPI state.”
— Early generations of IA processors within family 0FH (family=0FH, model=0H, stepping<=09H), P6 family
or older processors supporting MP operations (family=06H, extended_model=0, model<=0DH; or family
<06H):
•
Each processor broadcasts a BIPI to “all including self.” The first processor that broadcasts a BIPI (and
thus receives its own BIPI vector), selects itself as the BSP and sets the BSP flag in its IA32_APIC_BASE
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MSR. (See Section 8.11.1, “Overview of the MP Initialization Process For P6 Family Processors” for a
description of the BIPI, FIPI, and SIPI messages.)
•
The remainder of the processors (which were not selected as the BSP) are designated as APs. They
leave their BSP flags in the clear state and enter a “wait-for-SIPI state.”
•
The newly established BSP broadcasts an FIPI message to “all including self,” which the BSP and APs
treat as an end of MP initialization signal. Only the processor with its BSP flag set responds to the FIPI
message. It responds by fetching and executing the BIOS boot-strap code, beginning at the reset vector
(physical address FFFF FFF0H).
5. As part of the boot-strap code, the BSP creates an ACPI table and/or an MP table and adds its initial APIC ID to
these tables as appropriate.
6. At the end of the boot-strap procedure, the BSP sets a processor counter to 1, then broadcasts a SIPI message
to all the APs in the system. Here, the SIPI message contains a vector to the BIOS AP initialization code (at
000VV000H, where VV is the vector contained in the SIPI message).
7. The first action of the AP initialization code is to set up a race (among the APs) to a BIOS initialization
semaphore. The first AP to the semaphore begins executing the initialization code. (See Section 8.4.4, “MP
Initialization Example,” for semaphore implementation details.) As part of the AP initialization procedure, the
AP adds its APIC ID number to the ACPI and/or MP tables as appropriate and increments the processor counter
by 1. At the completion of the initialization procedure, the AP executes a CLI instruction and halts itself.
8. When each of the APs has gained access to the semaphore and executed the AP initialization code, the BSP
establishes a count for the number of processors connected to the system bus, completes executing the BIOS
boot-strap code, and then begins executing operating-system boot-strap and start-up code.
9. While the BSP is executing operating-system boot-strap and start-up code, the APs remain in the halted state.
In this state they will respond only to INITs, NMIs, and SMIs. They will also respond to snoops and to assertions
of the STPCLK# pin.
The following section gives an example (with code) of the MP initialization protocol for of multiple processors operating in an MP configuration.
Chapter 35, “Model-Specific Registers (MSRs),” describes how to program the LINT[0:1] pins of the processor’s
local APICs after an MP configuration has been completed.
8.4.4
MP Initialization Example
The following example illustrates the use of the MP initialization protocol used to initialize processors in an MP
system after the BSP and APs have been established. The code runs on Intel 64 or IA-32 processors that use a
protocol. This includes P6 Family processors, Pentium 4 processors, Intel Core Duo, Intel Core 2 Duo and Intel Xeon
processors.
The following constants and data definitions are used in the accompanying
code examples. They are based on the addresses of the APIC registers defined in Table 10-1.
ICR_LOW
SVR
APIC_ID
LVT3
APIC_ENABLED
BOOT_ID
COUNT
VACANT
8.4.4.1
EQU 0FEE00300H
EQU 0FEE000F0H
EQU 0FEE00020H
EQU 0FEE00370H
EQU 0100H
DD ?
EQU 00H
EQU 00H
Typical BSP Initialization Sequence
After the BSP and APs have been selected (by means of a hardware protocol, see Section 8.4.3, “MP Initialization
Protocol Algorithm for MP Systems”), the BSP begins executing BIOS boot-strap code (POST) at the normal IA-32
architecture starting address (FFFF FFF0H). The boot-strap code typically performs the following operations:
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1. Initializes memory.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs.
4. Enables the caches.
5. Executes the CPUID instruction with a value of 0H in the EAX register, then reads the EBX, ECX, and EDX
registers to determine if the BSP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in the EAX register, then saves the values in the EAX, ECX,
and EDX registers in a system configuration space in RAM for use later.
7. Loads start-up code for the AP to execute into a 4-KByte page in the lower 1 MByte of memory.
8. Switches to protected mode and ensures that the APIC address space is mapped to the strong uncacheable
(UC) memory type.
9. Determine the BSP’s APIC ID from the local APIC ID register (default is 0), the code snippet below is an
example that applies to logical processors in a system whose local APIC units operate in xAPIC mode that APIC
registers are accessed using memory mapped interface:
MOV ESI, APIC_ID; Address of local APIC ID register
MOV EAX, [ESI];
AND EAX, 0FF000000H; Zero out all other bits except APIC ID
MOV BOOT_ID, EAX; Save in memory
Saves the APIC ID in the ACPI and/or MP tables and optionally in the system configuration space in RAM.
10. Converts the base address of the 4-KByte page for the AP’s bootup code into 8-bit vector. The 8-bit vector
defines the address of a 4-KByte page in the real-address mode address space (1-MByte space). For example,
a vector of 0BDH specifies a start-up memory address of 000BD000H.
11. Enables the local APIC by setting bit 8 of the APIC spurious vector register (SVR).
MOV ESI, SVR; Address of SVR
MOV EAX, [ESI];
OR EAX, APIC_ENABLED; Set bit 8 to enable (0 on reset)
MOV [ESI], EAX;
12. Sets up the LVT error handling entry by establishing an 8-bit vector for the APIC error handler.
MOV ESI, LVT3;
MOV EAX, [ESI];
AND EAX, FFFFFF00H; Clear out previous vector.
OR EAX, 000000xxH; xx is the 8-bit vector the APIC error handler.
MOV [ESI], EAX;
13. Initializes the Lock Semaphore variable VACANT to 00H. The APs use this semaphore to determine the order in
which they execute BIOS AP initialization code.
14. Performs the following operation to set up the BSP to detect the presence of APs in the system and the number
of processors (within a finite duration, minimally 100 milliseconds):
— Sets the value of the COUNT variable to 1.
— In the AP BIOS initialization code, the AP will increment the COUNT variable to indicate its presence. The
finite duration while waiting for the COUNT to be updated can be accomplished with a timer. When the timer
expires, the BSP checks the value of the COUNT variable. If the timer expires and the COUNT variable has
not been incremented, no APs are present or some error has occurred.
15. Broadcasts an INIT-SIPI-SIPI IPI sequence to the APs to wake them up and initialize them. If software knows
how many logical processors it expects to wake up, it may choose to poll the COUNT variable. If the expected
processors show up before the 100 millisecond timer expires, the timer can be canceled and skip to step 16.
The left-hand-side of the procedure illustrated in Table 8-1 provides an algorithm when the expected processor
count is unknown. The right-hand-side of Table 8-1 can be used when the expected processor count is known.
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Table 8-1. Broadcast INIT-SIPI-SIPI Sequence and Choice of Timeouts
INIT-SIPI-SIPI when the expected processor count is unknown
INIT-SIPI-SIPI when the expected processor count is known
MOV ESI, ICR_LOW; Load address of ICR low dword into ESI.
MOV ESI, ICR_LOW; Load address of ICR low dword into ESI.
MOV EAX, 000C4500H; Load ICR encoding for broadcast INIT IPI
MOV EAX, 000C4500H; Load ICR encoding for broadcast INIT IPI
; to all APs into EAX.
; to all APs into EAX.
MOV [ESI], EAX; Broadcast INIT IPI to all APs
MOV [ESI], EAX; Broadcast INIT IPI to all APs
; 10-millisecond delay loop.
; 10-millisecond delay loop.
MOV EAX, 000C46XXH; Load ICR encoding for broadcast SIPI IP
MOV EAX, 000C46XXH; Load ICR encoding for broadcast SIPI IP
; to all APs into EAX, where xx is the vector computed in step 10.
; to all APs into EAX, where xx is the vector computed in step 10.
MOV [ESI], EAX; Broadcast SIPI IPI to all APs
MOV [ESI], EAX; Broadcast SIPI IPI to all APs
; 200-microsecond delay loop
; 200 microsecond delay loop with check to see if COUNT has
MOV [ESI], EAX; Broadcast second SIPI IPI to all APs
; reached the expected processor count. If COUNT reaches
;Waits for the timer interrupt until the timer expires
; expected processor count, cancel timer and go to step 16.
MOV [ESI], EAX; Broadcast second SIPI IPI to all APs
; Wait for the timer interrupt polling COUNT. If COUNT reaches
; expected processor count, cancel timer and go to step 16.
; If timer expires, go to step 16.
16. Reads and evaluates the COUNT variable and establishes a processor count.
17. If necessary, reconfigures the APIC and continues with the remaining system diagnostics as appropriate.
8.4.4.2
Typical AP Initialization Sequence
When an AP receives the SIPI, it begins executing BIOS AP initialization code at the vector encoded in the SIPI. The
AP initialization code typically performs the following operations:
1. Waits on the BIOS initialization Lock Semaphore. When control of the semaphore is attained, initialization
continues.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs (using the same mapping that was used for the BSP).
4. Enables the cache.
5. Executes the CPUID instruction with a value of 0H in the EAX register, then reads the EBX, ECX, and EDX
registers to determine if the AP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in the EAX register, then saves the values in the EAX, ECX,
and EDX registers in a system configuration space in RAM for use later.
7. Switches to protected mode and ensures that the APIC address space is mapped to the strong uncacheable
(UC) memory type.
8. Determines the AP’s APIC ID from the local APIC ID register, and adds it to the MP and ACPI tables and
optionally to the system configuration space in RAM.
9. Initializes and configures the local APIC by setting bit 8 in the SVR register and setting up the LVT3 (error LVT)
for error handling (as described in steps 9 and 10 in Section 8.4.4.1, “Typical BSP Initialization Sequence”).
10. Configures the APs SMI execution environment. (Each AP and the BSP must have a different SMBASE address.)
11. Increments the COUNT variable by 1.
12. Releases the semaphore.
13. Executes one of the following:
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— the CLI and HLT instructions (if MONITOR/MWAIT is not supported), or
— the CLI, MONITOR and MWAIT sequence to enter a deep C-state.
14. Waits for an INIT IPI.
8.4.5
Identifying Logical Processors in an MP System
After the BIOS has completed the MP initialization protocol, each logical processor can be uniquely identified by its
local APIC ID. Software can access these APIC IDs in either of the following ways:
•
Read APIC ID for a local APIC — Code running on a logical processor can read APIC ID in one of two ways
depending on the local APIC unit is operating in x2APIC mode (see Intel® 64 Architecture x2APIC Specification)or in xAPIC mode:
— If the local APIC unit supports x2APIC and is operating in x2APIC mode, 32-bit APIC ID can be read by
executing a RDMSR instruction to read the processor’s x2APIC ID register. This method is equivalent to
executing CPUID leaf 0BH described below.
— If the local APIC unit is operating in xAPIC mode, 8-bit APIC ID can be read by executing a MOV instruction
to read the processor’s local APIC ID register (see Section 10.4.6, “Local APIC ID”). This is the ID to use for
directing physical destination mode interrupts to the processor.
•
Read ACPI or MP table — As part of the MP initialization protocol, the BIOS creates an ACPI table and an MP
table. These tables are defined in the Multiprocessor Specification Version 1.4 and provide software with a list
of the processors in the system and their local APIC IDs. The format of the ACPI table is derived from the ACPI
specification, which is an industry standard power management and platform configuration specification for MP
systems.
•
Read Initial APIC ID (If the process does not support CPUID leaf 0BH) — An APIC ID is assigned to a logical
processor during power up. This is the initial APIC ID reported by CPUID.1:EBX[31:24] and may be different
from the current value read from the local APIC. The initial APIC ID can be used to determine the topological
relationship between logical processors for multi-processor systems that do not support CPUID leaf 0BH.
Bits in the 8-bit initial APIC ID can be interpreted using several bit masks. Each bit mask can be used to extract
an identifier to represent a hierarchical level of the multi-threading resource topology in an MP system (See
Section 8.9.1, “Hierarchical Mapping of Shared Resources”). The initial APIC ID may consist of up to four bitfields. In a non-clustered MP system, the field consists of up to three bit fields.
•
Read 32-bit APIC ID from CPUID leaf 0BH (If the processor supports CPUID leaf 0BH) — A unique APIC ID
is assigned to a logical processor during power up. This APIC ID is reported by CPUID.0BH:EDX[31:0] as a 32bit value. Use the 32-bit APIC ID and CPUID leaf 0BH to determine the topological relationship between logical
processors if the processor supports CPUID leaf 0BH.
Bits in the 32-bit x2APIC ID can be extracted into sub-fields using CPUID leaf 0BH parameters. (See Section
8.9.1, “Hierarchical Mapping of Shared Resources”).
Figure 8-2 shows two examples of APIC ID bit fields in earlier single-core processors. In single-core Intel Xeon
processors, the APIC ID assigned to a logical processor during power-up and initialization is 8 bits. Bits 2:1 form a
2-bit physical package identifier (which can also be thought of as a socket identifier). In systems that configure
physical processors in clusters, bits 4:3 form a 2-bit cluster ID. Bit 0 is used in the Intel Xeon processor MP to identify the two logical processors within the package (see Section 8.9.3, “Hierarchical ID of Logical Processors in an
MP System”). For Intel Xeon processors that do not support Intel Hyper-Threading Technology, bit 0 is always set
to 0; for Intel Xeon processors supporting Intel Hyper-Threading Technology, bit 0 performs the same function as
it does for Intel Xeon processor MP.
For more recent multi-core processors, see Section 8.9.1, “Hierarchical Mapping of Shared Resources” for a
complete description of the topological relationships between logical processors and bit field locations within an
initial APIC ID across Intel 64 and IA-32 processor families.
Note the number of bit fields and the width of bit-fields are dependent on processor and platform hardware capabilities. Software should determine these at runtime. When initial APIC IDs are assigned to logical processors, the
value of APIC ID assigned to a logical processor will respect the bit-field boundaries corresponding core, physical
package, etc. Additional examples of the bit fields in the initial APIC ID of multi-threading capable systems are
shown in Section 8.9.
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APIC ID Format for Intel Xeon Processors that
do not Support Intel Hyper-Threading Technology
7
5
4
3
2
1
Reserved
0
0
Cluster
Processor ID
APIC ID Format for P6 Family Processors
7
4
3
2
1
0
Reserved
Cluster
Processor ID
Figure 8-2. Interpretation of APIC ID in Early MP Systems
For P6 family processors, the APIC ID that is assigned to a processor during power-up and initialization is 4 bits
(see Figure 8-2). Here, bits 0 and 1 form a 2-bit processor (or socket) identifier and bits 2 and 3 form a 2-bit cluster
ID.
8.5
INTEL® HYPER-THREADING TECHNOLOGY AND INTEL® MULTI-CORE
TECHNOLOGY
Intel Hyper-Threading Technology and Intel multi-core technology are extensions to Intel 64 and IA-32 architectures that enable a single physical processor to execute two or more separate code streams (called threads)
concurrently. In Intel Hyper-Threading Technology, a single processor core provides two logical processors that
share execution resources (see Section 8.7, “Intel® Hyper-Threading Technology Architecture”). In Intel multi-core
technology, a physical processor package provides two or more processor cores. Both configurations require chipsets and a BIOS that support the technologies.
Software should not rely on processor names to determine whether a processor supports Intel Hyper-Threading
Technology or Intel multi-core technology. Use the CPUID instruction to determine processor capability (see
Section 8.6.2, “Initializing Multi-Core Processors”).
8.6
DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY
Use the CPUID instruction to detect the presence of hardware multi-threading support in a physical processor.
Hardware multi-threading can support several varieties of multigrade and/or Intel Hyper-Threading Technology.
CPUID instruction provides several sets of parameter information to aid software enumerating topology information. The relevant topology enumeration parameters provided by CPUID include:
•
Hardware Multi-Threading feature flag (CPUID.1:EDX[28] = 1) — Indicates when set that the physical
package is capable of supporting Intel Hyper-Threading Technology and/or multiple cores.
•
Processor topology enumeration parameters for 8-bit APIC ID:
— Addressable IDs for Logical processors in the same Package (CPUID.1:EBX[23:16]) — Indicates
the maximum number of addressable ID for logical processors in a physical package. Within a physical
package, there may be addressable IDs that are not occupied by any logical processors. This parameter
does not represents the hardware capability of the physical processor.6
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•
Addressable IDs for processor cores in the same Package7 (CPUID.(EAX=4, ECX=08):EAX[31:26] +
1 = Y) — Indicates the maximum number of addressable IDs attributable to processor cores (Y) in the physical
package.
•
Extended Processor Topology Enumeration parameters for 32-bit APIC ID: Intel 64 processors
supporting CPUID leaf 0BH will assign unique APIC IDs to each logical processor in the system. CPUID leaf 0BH
reports the 32-bit APIC ID and provide topology enumeration parameters. See CPUID instruction reference
pages in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
The CPUID feature flag may indicate support for hardware multi-threading when only one logical processor available in the package. In this case, the decimal value represented by bits 16 through 23 in the EBX register will have
a value of 1.
Software should note that the number of logical processors enabled by system software may be less than the value
of “Addressable IDs for Logical processors”. Similarly, the number of cores enabled by system software may be less
than the value of “Addressable IDs for processor cores”.
Software can detect the availability of the CPUID extended topology enumeration leaf (0BH) by performing two
steps:
•
Check maximum input value for basic CPUID information by executing CPUID with EAX= 0. If CPUID.0H:EAX is
greater than or equal or 11 (0BH), then proceed to next step,
•
Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topology enumeration leaf is available. Note the presence of
CPUID leaf 0BH in a processor does not guarantee support that the local APIC supports x2APIC. If
CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for basic CPUID information is greater
than 0BH, then CPUID.0BH leaf is not supported on that processor.
8.6.1
Initializing Processors Supporting Hyper-Threading Technology
The initialization process for an MP system that contains processors supporting Intel Hyper-Threading Technology
is the same as for conventional MP systems (see Section 8.4, “Multiple-Processor (MP) Initialization”). One logical
processor in the system is selected as the BSP and other processors (or logical processors) are designated as APs.
The initialization process is identical to that described in Section 8.4.3, “MP Initialization Protocol Algorithm for MP
Systems,” and Section 8.4.4, “MP Initialization Example.”
During initialization, each logical processor is assigned an APIC ID that is stored in the local APIC ID register for
each logical processor. If two or more processors supporting Intel Hyper-Threading Technology are present, each
logical processor on the system bus is assigned a unique ID (see Section 8.9.3, “Hierarchical ID of Logical Processors in an MP System”). Once logical processors have APIC IDs, software communicates with them by sending APIC
IPI messages.
8.6.2
Initializing Multi-Core Processors
The initialization process for an MP system that contains multi-core Intel 64 or IA-32 processors is the same as for
conventional MP systems (see Section 8.4, “Multiple-Processor (MP) Initialization”). A logical processor in one core
is selected as the BSP; other logical processors are designated as APs.
During initialization, each logical processor is assigned an APIC ID. Once logical processors have APIC IDs, software may communicate with them by sending APIC IPI messages.
6. Operating system and BIOS may implement features that reduce the number of logical processors available in a platform to applications at runtime to less than the number of physical packages times the number of hardware-capable logical processors per package.
7. Software must check CPUID for its support of leaf 4 when implementing support for multi-core. If CPUID leaf 4 is not available at
runtime, software should handle the situation as if there is only one core per package.
8. Maximum number of cores in the physical package must be queried by executing CPUID with EAX=4 and a valid ECX input value.
Valid ECX input values start from 0.
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8.6.3
Executing Multiple Threads on an Intel® 64 or IA-32 Processor Supporting Hardware
Multi-Threading
Upon completing the operating system boot-up procedure, the bootstrap processor (BSP) executes operating
system code. Other logical processors are placed in the halt state. To execute a code stream (thread) on a halted
logical processor, the operating system issues an interprocessor interrupt (IPI) addressed to the halted logical
processor. In response to the IPI, the processor wakes up and begins executing the code identified by the vector
received as part of the IPI.
To manage execution of multiple threads on logical processors, an operating system can use conventional
symmetric multiprocessing (SMP) techniques. For example, the operating-system can use a time-slice or load
balancing mechanism to periodically interrupt each of the active logical processors. Upon interrupting a logical
processor, the operating system checks its run queue for a thread waiting to be executed and dispatches the thread
to the interrupted logical processor.
8.6.4
Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading
Interrupts are handled on processors supporting Intel Hyper-Threading Technology as they are on conventional MP
systems. External interrupts are received by the I/O APIC, which distributes them as interrupt messages to specific
logical processors (see Figure 8-3).
Logical processors can also send IPIs to other logical processors by writing to the ICR register of its local APIC (see
Section 10.6, “Issuing Interprocessor Interrupts”). This also applies to dual-core processors.
Intel Processor with Intel
Intel Processor with Intel
Hyper-Threading Technology Hyper-Threading Technology
Logical
Logical
Processor 0 Processor 1
Logical
Logical
Processor 0 Processor 1
Processor Core
Processor Core
Local APIC Local APIC
Local APIC Local APIC
Bus Interface
Bus Interface
IPIs
Interrupt
Messages
Interrupt
Messages
IPIs
Interrupt Messages
Bridge
PCI
I/O APIC
External
Interrupts
System Chip Set
Figure 8-3. Local APICs and I/O APIC in MP System Supporting Intel HT Technology
8.7
INTEL® HYPER-THREADING TECHNOLOGY ARCHITECTURE
Figure 8-4 shows a generalized view of an Intel processor supporting Intel Hyper-Threading Technology, using the
original Intel Xeon processor MP as an example. This implementation of the Intel Hyper-Threading Technology
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consists of two logical processors (each represented by a separate architectural state) which share the processor’s
execution engine and the bus interface. Each logical processor also has its own advanced programmable interrupt
controller (APIC).
Logical
Processor 0
Architectural
State
Logical
Processor 1
Architectural
State
Execution Engine
Local APIC
Local APIC
Bus Interface
System Bus
Figure 8-4. IA-32 Processor with Two Logical Processors Supporting Intel HT Technology
8.7.1
State of the Logical Processors
The following features are part of the architectural state of logical processors within Intel 64 or IA-32 processors
supporting Intel Hyper-Threading Technology. The features can be subdivided into three groups:
•
•
•
Duplicated for each logical processor
Shared by logical processors in a physical processor
Shared or duplicated, depending on the implementation
The following features are duplicated for each logical processor:
•
•
•
General purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, and EBP)
•
x87 FPU registers (ST0 through ST7, status word, control word, tag word, data operand pointer, and instruction
pointer)
•
•
•
•
•
•
•
•
•
•
MMX registers (MM0 through MM7)
Segment registers (CS, DS, SS, ES, FS, and GS)
EFLAGS and EIP registers. Note that the CS and EIP/RIP registers for each logical processor point to the
instruction stream for the thread being executed by the logical processor.
XMM registers (XMM0 through XMM7) and the MXCSR register
Control registers and system table pointer registers (GDTR, LDTR, IDTR, task register)
Debug registers (DR0, DR1, DR2, DR3, DR6, DR7) and the debug control MSRs
Machine check global status (IA32_MCG_STATUS) and machine check capability (IA32_MCG_CAP) MSRs
Thermal clock modulation and ACPI Power management control MSRs
Time stamp counter MSRs
Most of the other MSR registers, including the page attribute table (PAT). See the exceptions below.
Local APIC registers.
Additional general purpose registers (R8-R15), XMM registers (XMM8-XMM15), control register, IA32_EFER on
Intel 64 processors.
The following features are shared by logical processors:
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•
Memory type range registers (MTRRs)
Whether the following features are shared or duplicated is implementation-specific:
•
•
•
IA32_MISC_ENABLE MSR (MSR address 1A0H)
Machine check architecture (MCA) MSRs (except for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs)
Performance monitoring control and counter MSRs
8.7.2
APIC Functionality
When a processor supporting Intel Hyper-Threading Technology support is initialized, each logical processor is
assigned a local APIC ID (see Table 10-1). The local APIC ID serves as an ID for the logical processor and is stored
in the logical processor’s APIC ID register. If two or more processors supporting Intel Hyper-Threading Technology
are present in a dual processor (DP) or MP system, each logical processor on the system bus is assigned a unique
local APIC ID (see Section 8.9.3, “Hierarchical ID of Logical Processors in an MP System”).
Software communicates with local processors using the APIC’s interprocessor interrupt (IPI) messaging facility.
Setup and programming for APICs is identical in processors that support and do not support Intel Hyper-Threading
Technology. See Chapter 10, “Advanced Programmable Interrupt Controller (APIC),” for a detailed discussion.
8.7.3
Memory Type Range Registers (MTRR)
MTRRs in a processor supporting Intel Hyper-Threading Technology are shared by logical processors. When one
logical processor updates the setting of the MTRRs, settings are automatically shared with the other logical processors in the same physical package.
The architectures require that all MP systems based on Intel 64 and IA-32 processors (this includes logical processors) must use an identical MTRR memory map. This gives software a consistent view of memory, independent of
the processor on which it is running. See Section 11.11, “Memory Type Range Registers (MTRRs),” for information
on setting up MTRRs.
8.7.4
Page Attribute Table (PAT)
Each logical processor has its own PAT MSR (IA32_PAT). However, as described in Section 11.12, “Page Attribute
Table (PAT),” the PAT MSR settings must be the same for all processors in a system, including the logical processors.
8.7.5
Machine Check Architecture
In the Intel HT Technology context as implemented by processors based on Intel NetBurst® microarchitecture, all
of the machine check architecture (MCA) MSRs (except for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs) are
duplicated for each logical processor. This permits logical processors to initialize, configure, query, and handle
machine-check exceptions simultaneously within the same physical processor. The design is compatible with
machine check exception handlers that follow the guidelines given in Chapter 15, “Machine-Check Architecture.”
The IA32_MCG_STATUS MSR is duplicated for each logical processor so that its machine check in progress bit field
(MCIP) can be used to detect recursion on the part of MCA handlers. In addition, the MSR allows each logical
processor to determine that a machine-check exception is in progress independent of the actions of another logical
processor in the same physical package.
Because the logical processors within a physical package are tightly coupled with respect to shared hardware
resources, both logical processors are notified of machine check errors that occur within a given physical processor.
If machine-check exceptions are enabled when a fatal error is reported, all the logical processors within a physical
package are dispatched to the machine-check exception handler. If machine-check exceptions are disabled, the
logical processors enter the shutdown state and assert the IERR# signal.
When enabling machine-check exceptions, the MCE flag in control register CR4 should be set for each logical
processor.
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On Intel Atom family processors that support Intel Hyper-Threading Technology, the MCA facilities are shared
between all logical processors on the same processor core.
8.7.6
Debug Registers and Extensions
Each logical processor has its own set of debug registers (DR0, DR1, DR2, DR3, DR6, DR7) and its own debug
control MSR. These can be set to control and record debug information for each logical processor independently.
Each logical processor also has its own last branch records (LBR) stack.
8.7.7
Performance Monitoring Counters
Performance counters and their companion control MSRs are shared between the logical processors within a
processor core for processors based on Intel NetBurst microarchitecture. As a result, software must manage the
use of these resources. The performance counter interrupts, events, and precise event monitoring support can be
set up and allocated on a per thread (per logical processor) basis.
See Section 18.16, “Performance Monitoring and Intel Hyper-Threading Technology in Processors Based on Intel
NetBurst® Microarchitecture,” for a discussion of performance monitoring in the Intel Xeon processor MP.
In Intel Atom processor family that support Intel Hyper-Threading Technology, the performance counters (generalpurpose and fixed-function counters) and their companion control MSRs are duplicated for each logical processor.
8.7.8
IA32_MISC_ENABLE MSR
The IA32_MISC_ENABLE MSR (MSR address 1A0H) is generally shared between the logical processors in a
processor core supporting Intel Hyper-Threading Technology. However, some bit fields within IA32_MISC_ENABLE
MSR may be duplicated per logical processor. The partition of shared or duplicated bit fields within
IA32_MISC_ENABLE is implementation dependent. Software should program duplicated fields carefully on all
logical processors in the system to ensure consistent behavior.
8.7.9
Memory Ordering
The logical processors in an Intel 64 or IA-32 processor supporting Intel Hyper-Threading Technology obey the
same rules for memory ordering as Intel 64 or IA-32 processors without Intel HT Technology (see Section 8.2,
“Memory Ordering”). Each logical processor uses a processor-ordered memory model that can be further defined
as “write-ordered with store buffer forwarding.” All mechanisms for strengthening or weakening the memoryordering model to handle special programming situations apply to each logical processor.
8.7.10
Serializing Instructions
As a general rule, when a logical processor in a processor supporting Intel Hyper-Threading Technology executes a
serializing instruction, only that logical processor is affected by the operation. An exception to this rule is the
execution of the WBINVD, INVD, and WRMSR instructions; and the MOV CR instruction when the state of the CD
flag in control register CR0 is modified. Here, both logical processors are serialized.
8.7.11
Microcode Update Resources
In an Intel processor supporting Intel Hyper-Threading Technology, the microcode update facilities are shared
between the logical processors; either logical processor can initiate an update. Each logical processor has its own
BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical processor performs an update for
the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical processors are updated with identical
information. If logical processors initiate an update simultaneously, the processor core provides the necessary
synchronization needed to ensure that only one update is performed at a time.
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NOTE
Some processors (prior to the introduction of Intel 64 Architecture and based on Intel NetBurst
microarchitecture) do not support simultaneous loading of microcode update to the sibling logical
processors in the same core. All other processors support logical processors initiating an update
simultaneously. Intel recommends a common approach that the microcode loader use the
sequential technique described in Section 9.11.6.3.
8.7.12
Self Modifying Code
Intel processors supporting Intel Hyper-Threading Technology support self-modifying code, where data writes
modify instructions cached or currently in flight. They also support cross-modifying code, where on an MP system
writes generated by one processor modify instructions cached or currently in flight on another. See Section 8.1.3,
“Handling Self- and Cross-Modifying Code,” for a description of the requirements for self- and cross-modifying code
in an IA-32 processor.
8.7.13
Implementation-Specific Intel HT Technology Facilities
The following non-architectural facilities are implementation-specific in IA-32 processors supporting Intel HyperThreading Technology:
•
•
•
Caches
Translation lookaside buffers (TLBs)
Thermal monitoring facilities
The Intel Xeon processor MP implementation is described in the following sections.
8.7.13.1
Processor Caches
For processors supporting Intel Hyper-Threading Technology, the caches are shared. Any cache manipulation
instruction that is executed on one logical processor has a global effect on the cache hierarchy of the physical
processor. Note the following:
•
WBINVD instruction — The entire cache hierarchy is invalidated after modified data is written back to
memory. All logical processors are stopped from executing until after the write-back and invalidate operation is
completed. A special bus cycle is sent to all caching agents. The amount of time or cycles for WBINVD to
complete will vary due to the size of different cache hierarchies and other factors. As a consequence, the use of
the WBINVD instruction can have an impact on interrupt/event response time.
•
INVD instruction — The entire cache hierarchy is invalidated without writing back modified data to memory.
All logical processors are stopped from executing until after the invalidate operation is completed. A special bus
cycle is sent to all caching agents.
•
CLFLUSH and CLFLUSHOPT instructions — The specified cache line is invalidated from the cache hierarchy
after any modified data is written back to memory and a bus cycle is sent to all caching agents, regardless of
which logical processor caused the cache line to be filled.
•
CD flag in control register CR0 — Each logical processor has its own CR0 control register, and thus its own
CD flag in CR0. The CD flags for the two logical processors are ORed together, such that when any logical
processor sets its CD flag, the entire cache is nominally disabled.
8.7.13.2
Processor Translation Lookaside Buffers (TLBs)
In processors supporting Intel Hyper-Threading Technology, data cache TLBs are shared. The instruction cache TLB
may be duplicated or shared in each logical processor, depending on implementation specifics of different processor
families.
Entries in the TLBs are tagged with an ID that indicates the logical processor that initiated the translation. This tag
applies even for translations that are marked global using the page-global feature for memory paging. See Section
4.10, “Caching Translation Information,” for information about global translations.
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When a logical processor performs a TLB invalidation operation, only the TLB entries that are tagged for that logical
processor are guaranteed to be flushed. This protocol applies to all TLB invalidation operations, including writes to
control registers CR3 and CR4 and uses of the INVLPG instruction.
8.7.13.3
Thermal Monitor
In a processor that supports Intel Hyper-Threading Technology, logical processors share the catastrophic shutdown
detector and the automatic thermal monitoring mechanism (see Section 14.7, “Thermal Monitoring and Protection”). Sharing results in the following behavior:
•
If the processor’s core temperature rises above the preset catastrophic shutdown temperature, the processor
core halts execution, which causes both logical processors to stop execution.
•
When the processor’s core temperature rises above the preset automatic thermal monitor trip temperature, the
frequency of the processor core is automatically modulated, which effects the execution speed of both logical
processors.
For software controlled clock modulation, each logical processor has its own IA32_CLOCK_MODULATION MSR,
allowing clock modulation to be enabled or disabled on a logical processor basis. Typically, if software controlled
clock modulation is going to be used, the feature must be enabled for all the logical processors within a physical
processor and the modulation duty cycle must be set to the same value for each logical processor. If the duty cycle
values differ between the logical processors, the processor clock will be modulated at the highest duty cycle
selected.
8.7.13.4
External Signal Compatibility
This section describes the constraints on external signals received through the pins of a processor supporting Intel
Hyper-Threading Technology and how these signals are shared between its logical processors.
•
STPCLK# — A single STPCLK# pin is provided on the physical package of the Intel Xeon processor MP. External
control logic uses this pin for power management within the system. When the STPCLK# signal is asserted, the
processor core transitions to the stop-grant state, where instruction execution is halted but the processor core
continues to respond to snoop transactions. Regardless of whether the logical processors are active or halted
when the STPCLK# signal is asserted, execution is stopped on both logical processors and neither will respond
to interrupts.
In MP systems, the STPCLK# pins on all physical processors are generally tied together. As a result this signal
affects all the logical processors within the system simultaneously.
•
LINT0 and LINT1 pins — A processor supporting Intel Hyper-Threading Technology has only one set of LINT0
and LINT1 pins, which are shared between the logical processors. When one of these pins is asserted, both
logical processors respond unless the pin has been masked in the APIC local vector tables for one or both of the
logical processors.
Typically in MP systems, the LINT0 and LINT1 pins are not used to deliver interrupts to the logical processors.
Instead all interrupts are delivered to the local processors through the I/O APIC.
•
A20M# pin — On an IA-32 processor, the A20M# pin is typically provided for compatibility with the Intel 286
processor. Asserting this pin causes bit 20 of the physical address to be masked (forced to zero) for all external
bus memory accesses. Processors supporting Intel Hyper-Threading Technology provide one A20M# pin, which
affects the operation of both logical processors within the physical processor.
The functionality of A20M# is used primarily by older operating systems and not used by modern operating
systems. On newer Intel 64 processors, A20M# may be absent.
8.8
MULTI-CORE ARCHITECTURE
This section describes the architecture of Intel 64 and IA-32 processors supporting dual-core and quad-core technology. The discussion is applicable to the Intel Pentium processor Extreme Edition, Pentium D, Intel Core Duo,
Intel Core 2 Duo, Dual-core Intel Xeon processor, Intel Core 2 Quad processors, and quad-core Intel Xeon processors. Features vary across different microarchitectures and are detectable using CPUID.
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In general, each processor core has dedicated microarchitectural resources identical to a single-processor implementation of the underlying microarchitecture without hardware multi-threading capability. Each logical processor
in a dual-core processor (whether supporting Intel Hyper-Threading Technology or not) has its own APIC functionality, PAT, machine check architecture, debug registers and extensions. Each logical processor handles serialization
instructions or self-modifying code on its own. Memory order is handled the same way as in Intel Hyper-Threading
Technology.
The topology of the cache hierarchy (with respect to whether a given cache level is shared by one or more
processor cores or by all logical processors in the physical package) depends on the processor implementation.
Software must use the deterministic cache parameter leaf of CPUID instruction to discover the cache-sharing
topology between the logical processors in a multi-threading environment.
8.8.1
Logical Processor Support
The topological composition of processor cores and logical processors in a multi-core processor can be discovered
using CPUID. Within each processor core, one or more logical processors may be available.
System software must follow the requirement MP initialization sequences (see Section 8.4, “Multiple-Processor
(MP) Initialization”) to recognize and enable logical processors. At runtime, software can enumerate those logical
processors enabled by system software to identify the topological relationships between these logical processors.
(See Section 8.9.5, “Identifying Topological Relationships in a MP System”).
8.8.2
Memory Type Range Registers (MTRR)
MTRR is shared between two logical processors sharing a processor core if the physical processor supports Intel
Hyper-Threading Technology. MTRR is not shared between logical processors located in different cores or different
physical packages.
The Intel 64 and IA-32 architectures require that all logical processors in an MP system use an identical MTRR
memory map. This gives software a consistent view of memory, independent of the processor on which it is
running.
See Section 11.11, “Memory Type Range Registers (MTRRs).”
8.8.3
Performance Monitoring Counters
Performance counters and their companion control MSRs are shared between two logical processors sharing a
processor core if the processor core supports Intel Hyper-Threading Technology and is based on Intel NetBurst
microarchitecture. They are not shared between logical processors in different cores or different physical packages.
As a result, software must manage the use of these resources, based on the topology of performance monitoring
resources. Performance counter interrupts, events, and precise event monitoring support can be set up and allocated on a per thread (per logical processor) basis.
See Section 18.16, “Performance Monitoring and Intel Hyper-Threading Technology in Processors Based on Intel
NetBurst® Microarchitecture.”
8.8.4
IA32_MISC_ENABLE MSR
Some bit fields in IA32_MISC_ENABLE MSR (MSR address 1A0H) may be shared between two logical processors
sharing a processor core, or may be shared between different cores in a physical processor. See Chapter 35,
“Model-Specific Registers (MSRs),”.
8.8.5
Microcode Update Resources
Microcode update facilities are shared between two logical processors sharing a processor core if the physical
package supports Intel Hyper-Threading Technology. They are not shared between logical processors in different
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cores or different physical packages. Either logical processor that has access to the microcode update facility can
initiate an update.
Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical
processor performs an update for the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical
processors are updated with identical information.
All microcode update steps during processor initialization should use the same update data on all cores in all physical packages of the same stepping. Any subsequent microcode update must apply consistent update data to all
cores in all physical packages of the same stepping. If the processor detects an attempt to load an older microcode
update when a newer microcode update had previously been loaded, it may reject the older update to stay with the
newer update.
NOTE
Some processors (prior to the introduction of Intel 64 Architecture and based on Intel NetBurst
microarchitecture) do not support simultaneous loading of microcode update to the sibling logical
processors in the same core. All other processors support logical processors initiating an update
simultaneously. Intel recommends a common approach that the microcode loader use the
sequential technique described in Section 9.11.6.3.
8.9
PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING
CAPABLE PROCESSORS
In a multi-threading environment, there may be certain hardware resources that are physically shared at some
level of the hardware topology. In the multi-processor systems, typically bus and memory sub-systems are physically shared between multiple sockets. Within a hardware multi-threading capable processors, certain resources
are provided for each processor core, while other resources may be provided for each logical processors (see
Section 8.7, “Intel® Hyper-Threading Technology Architecture,” and Section 8.8, “Multi-Core Architecture”).
From a software programming perspective, control transfer of processor operation is managed at the granularity of
logical processor (operating systems dispatch a runnable task by allocating an available logical processor on the
platform). To manage the topology of shared resources in a multi-threading environment, it may be useful for software to understand and manage resources that are shared by more than one logical processors.
8.9.1
Hierarchical Mapping of Shared Resources
The APIC_ID value associated with each logical processor in a multi-processor system is unique (see Section 8.6,
“Detecting Hardware Multi-Threading Support and Topology”). This 8-bit or 32-bit value can be decomposed into
sub-fields, where each sub-field corresponds a hierarchical level of the topological mapping of hardware resources.
The decomposition of an APIC_ID may consist of several sub fields representing the topology within a physical
processor package, the higher-order bits of an APIC ID may also be used by cluster vendors to represent the
topology of cluster nodes of each coherent multiprocessor systems. If the processor does not support CPUID leaf
0BH, the 8-bit initial APIC ID can represent 4 levels of hierarchy:
•
Cluster — Some multi-threading environments consists of multiple clusters of multi-processor systems. The
CLUSTER_ID sub-field is usually supported by vendor firmware to distinguish different clusters. For nonclustered systems, CLUSTER_ID is usually 0 and system topology is reduced to three levels of hierarchy.
•
Package — A multi-processor system consists of two or more sockets, each mates with a physical processor
package. The PACKAGE_ID sub-field distinguishes different physical packages within a cluster.
•
Core — A physical processor package consists of one or more processor cores. The CORE_ID sub-field distinguishes processor cores in a package. For a single-core processor, the width of this bit field is 0.
•
SMT — A processor core provides one or more logical processors sharing execution resources. The SMT_ID
sub-field distinguishes logical processors in a core. The width of this bit field is non-zero if a processor core
provides more than one logical processors.
SMT and CORE sub-fields are bit-wise contiguous in the APIC_ID field (see Figure 8-5).
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X=31 if x2APIC is supported
X
Otherwise X= 7
Reserved
0
Cluster ID
Package ID
Core ID
SMT ID
Figure 8-5. Generalized Four level Interpretation of the APIC ID
If the processor supports CPUID leaf 0BH, the 32-bit APIC ID can represent cluster plus several levels of topology
within the physical processor package. The exact number of hierarchical levels within a physical processor package
must be enumerated through CPUID leaf 0BH. Common processor families may employ topology similar to that
represented by 8-bit Initial APIC ID. In general, CPUID leaf 0BH can support topology enumeration algorithm that
decompose a 32-bit APIC ID into more than four sub-fields (see Figure 8-6).
The width of each sub-field depends on hardware and software configurations. Field widths can be determined at
runtime using the algorithm discussed below (Example 8-16 through Example 8-20).
Figure 7-6 depicts the relationships of three of the hierarchical sub-fields in a hypothetical MP system. The value of
valid APIC_IDs need not be contiguous across package boundary or core boundaries.
0
31
Package
SMT
R
Q
Physical Processor Topology
Reserved
Cluster ID
Package ID
Q ID
R ID
SMT ID
32-bit APIC ID Composition
Figure 8-6. Conceptual Five-level Topology and 32-bit APIC ID Composition
8.9.2
Hierarchical Mapping of CPUID Extended Topology Leaf
CPUID leaf 0BH provides enumeration parameters for software to identify each hierarchy of the processor topology
in a deterministic manner. Each hierarchical level of the topology starting from the SMT level is represented numerically by a sub-leaf index within the CPUID 0BH leaf. Each level of the topology is mapped to a sub-field in the APIC
ID, following the general relationship depicted in Figure 8-6. This mechanism allows software to query the exact
number of levels within a physical processor package and the bit-width of each sub-field of x2APIC ID directly. For
example,
•
Starting from sub-leaf index 0 and incrementing ECX until CPUID.(EAX=0BH, ECX=N):ECX[15:8] returns an
invalid “level type” encoding. The number of levels within the physical processor package is “N” (excluding
PACKAGE). Using Figure 8-6 as an example, CPUID.(EAX=0BH, ECX=3):ECX[15:8] will report 00H, indicating
sub leaf 03H is invalid. This is also depicted by a pseudo code example:
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Example 8-16. Number of Levels Below the Physical Processor Package
Byte type = 1;
s = 0;
While ( type ) {
EAX = 0BH; // query each sub leaf of CPUID leaf 0BH
ECX = s;
CPUID;
type = ECX[15:8]; // examine level type encoding
s ++;
}
N = ECX[7:0];
•
Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract the SMT sub-field of x2APIC
ID. If EAX = 0BH, and ECX =0 is specified as input when executing CPUID, CPUID.(EAX=0BH,
ECX=0):EAX[4:0] reports a value (a right-shift count) that allow software to extract part of x2APIC ID to
distinguish the next higher topological entities above the SMT level. This value also corresponds to the bitwidth of the sub-field of x2APIC ID corresponding the hierarchical level with sub-leaf index 0.
•
For each subsequent higher sub-leaf index m, CPUID.(EAX=0BH, ECX=m):EAX[4:0] reports the right-shift
count that will allow software to extract part of x2APIC ID to distinguish higher-level topological entities. This
means the right-shift value at of sub-leaf m, corresponds to the least significant (m+1) subfields of the 32-bit
x2APIC ID.
Example 8-17. BitWidth Determination of x2APIC ID Subfields
For m = 0, m < N, m ++;
{ cumulative_width[m] = CPUID.(EAX=0BH, ECX= m): EAX[4:0]; }
BitWidth[0] = cumulative_width[0];
For m = 1, m < N, m ++;
BitWidth[m] = cumulative_width[m] - cumulative_width[m-1];
Currently, only the following encoding of hierarchical level type are defined: 0 (invalid), 1 (SMT), and 2 (core).
Software must not assume any “level type“ encoding value to be related to any sub-leaf index, except sub-leaf 0.
Example 8-16 and Example 8-17 represent the general technique for using CPUID leaf 0BH to enumerate processor
topology of more than two levels of hierarchy inside a physical package. Most processor families to date requires
only “SMT” and “CORE” levels within a physical package. The examples in later sections will focus on these threelevel topology only.
8.9.3
Hierarchical ID of Logical Processors in an MP System
For Intel 64 and IA-32 processors, system hardware establishes an 8-bit initial APIC ID (or 32-bit APIC ID if the
processor supports CPUID leaf 0BH) that is unique for each logical processor following power-up or RESET (see
Section 8.6.1). Each logical processor on the system is allocated an initial APIC ID. BIOS may implement features
that tell the OS to support less than the total number of logical processors on the system bus. Those logical processors that are not available to applications at runtime are halted during the OS boot process. As a result, the number
valid local APIC_IDs that can be queried by affinitizing-current-thread-context (See Example 8-22) is limited to the
number of logical processors enabled at runtime by the OS boot process.
Table 8-2 shows an example of the 8-bit APIC IDs that are initially reported for logical processors in a system with
four Intel Xeon MP processors that support Intel Hyper-Threading Technology (a total of 8 logical processors, each
physical package has two processor cores and supports Intel Hyper-Threading Technology). Of the two logical
processors within a Intel Xeon processor MP, logical processor 0 is designated the primary logical processor and
logical processor 1 as the secondary logical processor.
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T0
T1
Core 0
T0
T1
T0
Core1
T1
Core 0
T1
T0
Core1
Core ID
Package ID
Package 1
Package 0
SMT_ID
Figure 8-7. Topological Relationships between Hierarchical IDs in a Hypothetical MP Platform
Table 8-2. Initial APIC IDs for the Logical Processors in a System that has Four Intel Xeon MP Processors Supporting
Intel Hyper-Threading Technology1
Initial APIC ID
Package ID
Core ID
SMT ID
0H
0H
0H
0H
1H
0H
0H
1H
2H
1H
0H
0H
3H
1H
0H
1H
4H
2H
0H
0H
5H
2H
0H
1H
6H
3H
0H
0H
7H
3H
0H
1H
NOTE:
1. Because information on the number of processor cores in a physical package was not available in early single-core processors supporting Intel Hyper-Threading Technology, the core ID can be treated as 0.
Table 8-3 shows the initial APIC IDs for a hypothetical situation with a dual processor system. Each physical
package providing two processor cores, and each processor core also supporting Intel Hyper-Threading Technology.
Table 8-3. Initial APIC IDs for the Logical Processors in a System that has Two Physical Processors Supporting DualCore and Intel Hyper-Threading Technology
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Initial APIC ID
Package ID
Core ID
SMT ID
0H
0H
0H
0H
1H
0H
0H
1H
2H
0H
1H
0H
3H
0H
1H
1H
4H
1H
0H
0H
5H
1H
0H
1H
6H
1H
1H
0H
7H
1H
1H
1H
MULTIPLE-PROCESSOR MANAGEMENT
8.9.3.1
Hierarchical ID of Logical Processors with x2APIC ID
Table 8-4 shows an example of possible x2APIC ID assignments for a dual processor system that support x2APIC.
Each physical package providing four processor cores, and each processor core also supporting Intel HyperThreading Technology. Note that the x2APIC ID need not be contiguous in the system.
Table 8-4. Example of Possible x2APIC ID Assignment in a System that has Two Physical Processors Supporting
x2APIC and Intel Hyper-Threading Technology
8.9.4
x2APIC ID
Package ID
Core ID
SMT ID
0H
0H
0H
0H
1H
0H
0H
1H
2H
0H
1H
0H
3H
0H
1H
1H
4H
0H
2H
0H
5H
0H
2H
1H
6H
0H
3H
0H
7H
0H
3H
1H
10H
1H
0H
0H
11H
1H
0H
1H
12H
1H
1H
0H
13H
1H
1H
1H
14H
1H
2H
0H
15H
1H
2H
1H
16H
1H
3H
0H
17H
1H
3H
1H
Algorithm for Three-Level Mappings of APIC_ID
Software can gather the initial APIC_IDs for each logical processor supported by the operating system at runtime9
and extract identifiers corresponding to the three levels of sharing topology (package, core, and SMT). The threelevel algorithms below focus on a non-clustered MP system for simplicity. They do not assume APIC IDs are contiguous or that all logical processors on the platform are enabled.
Intel supports multi-threading systems where all physical processors report identical values in CPUID leaf 0BH,
CPUID.1:EBX[23:16]), CPUID.410:EAX[31:26], and CPUID.411:EAX[25:14]. The algorithms below assume the
target system has symmetry across physical package boundaries with respect to the number of logical processors
per package, number of cores per package, and cache topology within a package.
The extraction algorithm (for three-level mappings from an APIC ID) uses the general procedure depicted in
Example 8-18, and is supplemented by more detailed descriptions on the derivation of topology enumeration
parameters for extraction bit masks:
1. Detect hardware multi-threading support in the processor.
9. As noted in Section 8.6 and Section 8.9.3, the number of logical processors supported by the OS at runtime may be less than the
total number logical processors available in the platform hardware.
10. Maximum number of addressable ID for processor cores in a physical processor is obtained by executing CPUID with EAX=4 and a
valid ECX index, The ECX index start at 0.
11. Maximum number addressable ID for processor cores sharing the target cache level is obtained by executing CPUID with EAX = 4
and the ECX index corresponding to the target cache level.
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2. Derive a set of bit masks that can extract the sub ID of each hierarchical level of the topology. The algorithm to
derive extraction bit masks for SMT_ID/CORE_ID/PACKAGE_ID differs based on APIC ID is 32-bit (see step 3
below) or 8-bit (see step 4 below):
3. If the processor supports CPUID leaf 0BH, each APIC ID contains a 32-bit value, the topology enumeration
parameters needed to derive three-level extraction bit masks are:
a. Query the right-shift value for the SMT level of the topology using CPUID leaf 0BH with ECX =0H as input.
The number of bits to shift-right on x2APIC ID (EAX[4:0]) can distinguish different higher-level entities
above SMT (e.g. processor cores) in the same physical package. This is also the width of the bit mask to
extract the SMT_ID.
b. Query CPUID leaf 0BH for the amount of bit shift to distinguish next higher-level entities (e.g. physical
processor packages) in the system. This describes an explicit three-level-topology situation for commonly
available processors. Consult Example 8-17 to adapt to situations beyond three-level topology of a physical
processor. The width of the extraction bit mask can be used to derive the cumulative extraction bitmask to
extract the sub IDs of logical processors (including different processor cores) in the same physical package.
The extraction bit mask to distinguish merely different processor cores can be derived by xor’ing the SMT
extraction bit mask from the cumulative extraction bit mask.
c.
Query the 32-bit x2APIC ID for the logical processor where the current thread is executing.
d. Derive the extraction bit masks corresponding to SMT_ID, CORE_ID, and PACKAGE_ID, starting from
SMT_ID.
e. Apply each extraction bit mask to the 32-bit x2APIC ID to extract sub-field IDs.
4. If the processor does not support CPUID leaf 0BH, each initial APIC ID contains an 8-bit value, the topology
enumeration parameters needed to derive extraction bit masks are:
a. Query the size of address space for sub IDs that can accommodate logical processors in a physical
processor package. This size parameters (CPUID.1:EBX[23:16]) can be used to derive the width of an
extraction bitmask to enumerate the sub IDs of different logical processors in the same physical package.
b. Query the size of address space for sub IDs that can accommodate processor cores in a physical processor
package. This size parameters can be used to derive the width of an extraction bitmask to enumerate the
sub IDs of processor cores in the same physical package.
c.
Query the 8-bit initial APIC ID for the logical processor where the current thread is executing.
d. Derive the extraction bit masks using respective address sizes corresponding to SMT_ID, CORE_ID, and
PACKAGE_ID, starting from SMT_ID.
e. Apply each extraction bit mask to the 8-bit initial APIC ID to extract sub-field IDs.
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Example 8-18. Support Routines for Detecting Hardware Multi-Threading and Identifying the Relationships Between Package,
Core and Logical Processors
1.
//
//
//
//
//
Detect support for Hardware Multi-Threading Support in a processor.
Returns a non-zero value if CPUID reports the presence of hardware multi-threading
support in the physical package where the current logical processor is located.
This does not guarantee BIOS or OS will enable all logical processors in the physical
package and make them available to applications.
Returns zero if hardware multi-threading is not present.
#define HWMT_BIT 10000000H
unsigned int HWMTSupported(void)
{
// ensure cpuid instruction is supported
execute cpuid with eax = 0 to get vendor string
execute cpuid with eax = 1 to get feature flag and signature
// Check to see if this a Genuine Intel Processor
if (vendor string EQ GenuineIntel) {
return (feature_flag_edx & HWMT_BIT); // bit 28
}
return 0;
}
Example 8-19. Support Routines for Identifying Package, Core and Logical Processors from 32-bit x2APIC ID
a.
Derive the extraction bitmask for logical processors in a processor core and associated mask offset for different
cores.
int DeriveSMT_Mask_Offsets (void)
{
if (!HWMTSupported()) return -1;
execute cpuid with eax = 11, ECX = 0;
If (returned level type encoding in ECX[15:8] does not match SMT) return -1;
Mask_SMT_shift = EAX[4:0]; // # bits shift right of APIC ID to distinguish different cores
SMT_MASK = ~( (-1) << Mask_SMT_shift); // shift left to derive extraction bitmask for SMT_ID
return 0;
}
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b.
Derive the extraction bitmask for processor cores in a physical processor package and associated mask offset for
different packages.
int DeriveCore_Mask_Offsets (void)
{
if (!HWMTSupported()) return -1;
execute cpuid with eax = 11, ECX = 0;
while( ECX[15:8] ) { // level type encoding is valid
If (returned level type encoding in ECX[15:8] matches CORE) {
Mask_Core_shift = EAX[4:0]; // needed to distinguish different physical packages
COREPlusSMT_MASK = ~( (-1) << Mask_Core_shift);
CORE_MASK = COREPlusSMT_MASK ^ SMT_MASK;
PACKAGE_MASK = (-1) << Mask_Core_shift;
return 0
}
ECX ++;
execute cpuid with eax = 11;
}
return -1;
}
c.
Query the x2APIC ID of a logical processor.
APIC_IDs for each logical processor.
unsigned char Getx2APIC_ID (void)
{
unsigned reg_edx = 0;
execute cpuid with eax = 11, ECX = 0
store returned value of edx
return (unsigned) (reg_edx) ;
}
Example 8-20. Support Routines for Identifying Package, Core and Logical Processors from 8-bit Initial APIC ID
a.
Find the size of address space for logical processors in a physical processor package.
#define NUM_LOGICAL_BITS 00FF0000H
// Use the mask above and CPUID.1.EBX[23:16] to obtain the max number of addressable IDs
// for logical processors in a physical package,
//Returns the size of address space of logical processors in a physical processor package;
// Software should not assume the value to be a power of 2.
unsigned char MaxLPIDsPerPackage(void)
{
if (!HWMTSupported()) return 1;
execute cpuid with eax = 1
store returned value of ebx
return (unsigned char) ((reg_ebx & NUM_LOGICAL_BITS) >> 16);
}
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b.
Find the size of address space for processor cores in a physical processor package.
// Returns the max number of addressable IDs for processor cores in a physical processor package;
// Software should not assume cpuid reports this value to be a power of 2.
unsigned MaxCoreIDsPerPackage(void)
{
if (!HWMTSupported()) return (unsigned char) 1;
if cpuid supports leaf number 4
{ // we can retrieve multi-core topology info using leaf 4
execute cpuid with eax = 4, ecx = 0
store returned value of eax
return (unsigned) ((reg_eax >> 26) +1);
}
else // must be a single-core processor
return 1;
}
c.
Query the initial APIC ID of a logical processor.
#define INITIAL_APIC_ID_BITS FF000000H // CPUID.1.EBX[31:24] initial APIC ID
// Returns the 8-bit unique initial APIC ID for the processor running the code.
// Software can use OS services to affinitize the current thread to each logical processor
// available under the OS to gather the initial APIC_IDs for each logical processor.
unsigned GetInitAPIC_ID (void)
{
unsigned int reg_ebx = 0;
execute cpuid with eax = 1
store returned value of ebx
return (unsigned) ((reg_ebx & INITIAL_APIC_ID_BITS) >> 24;
}
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d.
Find the width of an extraction bitmask from the maximum count of the bit-field (address size).
// Returns the mask bit width of a bit field from the maximum count that bit field can represent.
// This algorithm does not assume ‘address size’ to have a value equal to power of 2.
// Address size for SMT_ID can be calculated from MaxLPIDsPerPackage()/MaxCoreIDsPerPackage()
// Then use the routine below to derive the corresponding width of SMT extraction bitmask
// Address size for CORE_ID is MaxCoreIDsPerPackage(),
// Derive the bitwidth for CORE extraction mask similarly
unsigned FindMaskWidth(Unsigned Max_Count)
{unsigned int mask_width, cnt = Max_Count;
__asm {
mov eax, cnt
mov ecx, 0
mov mask_width, ecx
dec eax
bsr cx, ax
jz next
inc cx
mov mask_width, ecx
next:
mov eax, mask_width
}
return mask_width;
}
e.
Extract a sub ID from an 8-bit full ID, using address size of the sub ID and shift count.
// The routine below can extract SMT_ID, CORE_ID, and PACKAGE_ID respectively from the init APIC_ID
// To extract SMT_ID, MaxSubIDvalue is set to the address size of SMT_ID, Shift_Count = 0
// To extract CORE_ID, MaxSubIDvalue is the address size of CORE_ID, Shift_Count is width of SMT extraction bitmask.
// Returns the value of the sub ID, this is not a zero-based value
Unsigned char GetSubID(unsigned char Full_ID, unsigned char MaxSubIDvalue, unsigned char Shift_Count)
{
MaskWidth = FindMaskWidth(MaxSubIDValue);
MaskBits = ((uchar) (FFH << Shift_Count)) ^ ((uchar) (FFH << Shift_Count + MaskWidth)) ;
SubID = Full_ID & MaskBits;
Return SubID;
}
Software must not assume local APIC_ID values in an MP system are consecutive. Non-consecutive local APIC_IDs
may be the result of hardware configurations or debug features implemented in the BIOS or OS.
An identifier for each hierarchical level can be extracted from an 8-bit APIC_ID using the support routines illustrated in Example 8-20. The appropriate bit mask and shift value to construct the appropriate bit mask for each
level must be determined dynamically at runtime.
8.9.5
Identifying Topological Relationships in a MP System
To detect the number of physical packages, processor cores, or other topological relationships in a MP system, the
following procedures are recommended:
•
Extract the three-level identifiers from the APIC ID of each logical processor enabled by system software. The
sequence is as follows (See the pseudo code shown in Example 8-21 and support routines shown in Example
8-18):
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•
The extraction start from the right-most bit field, corresponding to SMT_ID, the innermost hierarchy in
a three-level topology (See Figure 8-7). For the right-most bit field, the shift value of the working mask
is zero. The width of the bit field is determined dynamically using the maximum number of logical
processor per core, which can be derived from information provided from CPUID.
•
To extract the next bit-field, the shift value of the working mask is determined from the width of the bit
mask of the previous step. The width of the bit field is determined dynamically using the maximum
number of cores per package.
•
To extract the remaining bit-field, the shift value of the working mask is determined from the maximum
number of logical processor per package. So the remaining bits in the APIC ID (excluding those bits
already extracted in the two previous steps) are extracted as the third identifier. This applies to a nonclustered MP system, or if there is no need to distinguish between PACKAGE_ID and CLUSTER_ID.
If there is need to distinguish between PACKAGE_ID and CLUSTER_ID, PACKAGE_ID can be extracted
using an algorithm similar to the extraction of CORE_ID, assuming the number of physical packages in
each node of a clustered system is symmetric.
•
Assemble the three-level identifiers of SMT_ID, CORE_ID, PACKAGE_IDs into arrays for each enabled logical
processor. This is shown in Example 8-22a.
•
To detect the number of physical packages: use PACKAGE_ID to identify those logical processors that reside in
the same physical package. This is shown in Example 8-22b. This example also depicts a technique to construct
a mask to represent the logical processors that reside in the same package.
•
To detect the number of processor cores: use CORE_ID to identify those logical processors that reside in the
same core. This is shown in Example 8-22. This example also depicts a technique to construct a mask to
represent the logical processors that reside in the same core.
In Example 8-21, the numerical ID value can be obtained from the value extracted with the mask by shifting it right
by shift count. Algorithms below do not shift the value. The assumption is that the SubID values can be compared
for equivalence without the need to shift.
Example 8-21. Pseudo Code Depicting Three-level Extraction Algorithm
For Each local_APIC_ID{
// Calculate SMT_MASK, the bit mask pattern to extract SMT_ID,
// SMT_MASK is determined using topology enumertaion parameters
// from CPUID leaf 0BH (Example 8-19);
// otherwise, SMT_MASK is determined using CPUID leaf 01H and leaf 04H (Example 8-20).
// This algorithm assumes there is symmetry across core boundary, i.e. each core within a
// package has the same number of logical processors
// SMT_ID always starts from bit 0, corresponding to the right-most bit-field
SMT_ID = APIC_ID & SMT_MASK;
// Extract CORE_ID:
// CORE_MASK is determined in Example 8-19 or Example 8-20
CORE_ID = (APIC_ID & CORE_MASK) ;
// Extract PACKAGE_ID:
// Assume single cluster.
// Shift out the mask width for maximum logical processors per package
// PACKAGE_MASK is determined in Example 8-19 or Example 8-20
PACKAGE_ID = (APIC_ID & PACKAGE_MASK) ;
}
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Example 8-22. Compute the Number of Packages, Cores, and Processor Relationships in a MP System
a) Assemble lists of PACKAGE_ID, CORE_ID, and SMT_ID of each enabled logical processors
//The BIOS and/or OS may limit the number of logical processors available to applications
// after system boot. The below algorithm will compute topology for the processors visible
// to the thread that is computing it.
// Extract the 3-levels of IDs on every processor
// SystemAffinity is a bitmask of all the processors started by the OS. Use OS specific APIs to
// obtain it.
// ThreadAffinityMask is used to affinitize the topology enumeration thread to each processor
using OS specific APIs.
// Allocate per processor arrays to store the Package_ID, Core_ID and SMT_ID for every started
// processor.
ThreadAffinityMask = 1;
ProcessorNum = 0;
while (ThreadAffinityMask ≠ 0 && ThreadAffinityMask <= SystemAffinity) {
// Check to make sure we can utilize this processor first.
if (ThreadAffinityMask & SystemAffinity){
Set thread to run on the processor specified in ThreadAffinityMask
Wait if necessary and ensure thread is running on specified processor
APIC_ID = GetAPIC_ID(); // 32 bit ID in Example 8-19 or 8-bit ID in Example 8-20
Extract the Package_ID, Core_ID and SMT_ID as explained in three level extraction
algorithm of Example 8-21
PackageID[ProcessorNUM] = PACKAGE_ID;
CoreID[ProcessorNum] = CORE_ID;
SmtID[ProcessorNum] = SMT_ID;
ProcessorNum++;
}
ThreadAffinityMask <<= 1;
}
NumStartedLPs = ProcessorNum;
b) Using the list of PACKAGE_ID to count the number of physical packages in a MP system and construct, for each package, a multi-bit
mask corresponding to those logical processors residing in the same package.
// Compute the number of packages by counting the number of processors
// with unique PACKAGE_IDs in the PackageID array.
// Compute the mask of processors in each package.
PackageIDBucket is an array of unique PACKAGE_ID values. Allocate an array of
NumStartedLPs count of entries in this array.
PackageProcessorMask is a corresponding array of the bit mask of processors belonging to
the same package, these are processors with the same PACKAGE_ID
The algorithm below assumes there is symmetry across package boundary if more than
one socket is populated in an MP system.
// Bucket Package IDs and compute processor mask for every package.
PackageNum = 1;
PackageIDBucket[0] = PackageID[0];
ProcessorMask = 1;
PackageProcessorMask[0] = ProcessorMask;
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For (ProcessorNum = 1; ProcessorNum < NumStartedLPs; ProcessorNum++) {
ProcessorMask << = 1;
For (i=0; i < PackageNum; i++) {
// we may be comparing bit-fields of logical processors residing in different
// packages, the code below assume package symmetry
If (PackageID[ProcessorNum] = PackageIDBucket[i]) {
PackageProcessorMask[i] |= ProcessorMask;
Break; // found in existing bucket, skip to next iteration
}
}
if (i =PackageNum) {
//PACKAGE_ID did not match any bucket, start new bucket
PackageIDBucket[i] = PackageID[ProcessorNum];
PackageProcessorMask[i] = ProcessorMask;
PackageNum++;
}
}
// PackageNum has the number of Packages started in OS
// PackageProcessorMask[] array has the processor set of each package
c) Using the list of CORE_ID to count the number of cores in a MP system and construct, for each core, a multi-bit mask corresponding
to those logical processors residing in the same core.
Processors in the same core can be determined by bucketing the processors with the same PACKAGE_ID and CORE_ID. Note that code
below can BIT OR the values of PACKGE and CORE ID because they have not been shifted right.
The algorithm below assumes there is symmetry across package boundary if more than one socket is populated in an MP system.
//Bucketing PACKAGE and CORE IDs and computing processor mask for every core
CoreNum = 1;
CoreIDBucket[0] = PackageID[0] | CoreID[0];
ProcessorMask = 1;
CoreProcessorMask[0] = ProcessorMask;
For (ProcessorNum = 1; ProcessorNum < NumStartedLPs; ProcessorNum++) {
ProcessorMask << = 1;
For (i=0; i < CoreNum; i++) {
// we may be comparing bit-fields of logical processors residing in different
// packages, the code below assume package symmetry
If ((PackageID[ProcessorNum] | CoreID[ProcessorNum]) = CoreIDBucket[i]) {
CoreProcessorMask[i] |= ProcessorMask;
Break; // found in existing bucket, skip to next iteration
}
}
if (i = CoreNum) {
//Did not match any bucket, start new bucket
CoreIDBucket[i] = PackageID[ProcessorNum] | CoreID[ProcessorNum];
CoreProcessorMask[i] = ProcessorMask;
CoreNum++;
}
}
// CoreNum has the number of cores started in the OS
// CoreProcessorMask[] array has the processor set of each core
Other processor relationships such as processor mask of sibling cores can be computed from set operations of the
PackageProcessorMask[] and CoreProcessorMask[].
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The algorithm shown above can be adapted to work with earlier generations of single-core IA-32 processors that
support Intel Hyper-Threading Technology and in situations that the deterministic cache parameter leaf is not
supported (provided CPUID supports initial APIC ID). A reference code example is available (see Intel® 64 Architecture Processor Topology Enumeration).
8.10
MANAGEMENT OF IDLE AND BLOCKED CONDITIONS
When a logical processor in an MP system (including multi-core processor or processors supporting Intel HyperThreading Technology) is idle (no work to do) or blocked (on a lock or semaphore), additional management of the
core execution engine resource can be accomplished by using the HLT (halt), PAUSE, or the MONITOR/MWAIT
instructions.
8.10.1
HLT Instruction
The HLT instruction stops the execution of the logical processor on which it is executed and places it in a halted
state until further notice (see the description of the HLT instruction in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). When a logical processor is halted, active logical processors
continue to have full access to the shared resources within the physical package. Here shared resources that were
being used by the halted logical processor become available to active logical processors, allowing them to execute
at greater efficiency. When the halted logical processor resumes execution, shared resources are again shared
among all active logical processors. (See Section 8.10.6.3, “Halt Idle Logical Processors,” for more information
about using the HLT instruction with processors supporting Intel Hyper-Threading Technology.)
8.10.2
PAUSE Instruction
The PAUSE instruction can improves the performance of processors supporting Intel Hyper-Threading Technology
when executing “spin-wait loops” and other routines where one thread is accessing a shared lock or semaphore in
a tight polling loop. When executing a spin-wait loop, the processor can suffer a severe performance penalty when
exiting the loop because it detects a possible memory order violation and flushes the core processor’s pipeline. The
PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses
this hint to avoid the memory order violation and prevent the pipeline flush. In addition, the PAUSE instruction depipelines the spin-wait loop to prevent it from consuming execution resources excessively and consume power
needlessly. (See Section 8.10.6.1, “Use the PAUSE Instruction in Spin-Wait Loops,” for more information about
using the PAUSE instruction with IA-32 processors supporting Intel Hyper-Threading Technology.)
8.10.3
Detecting Support MONITOR/MWAIT Instruction
Streaming SIMD Extensions 3 introduced two instructions (MONITOR and MWAIT) to help multithreaded software
improve thread synchronization. In the initial implementation, MONITOR and MWAIT are available to software at
ring 0. The instructions are conditionally available at levels greater than 0. Use the following steps to detect the
availability of MONITOR and MWAIT:
•
•
Use CPUID to query the MONITOR bit (CPUID.1.ECX[3] = 1).
If CPUID indicates support, execute MONITOR inside a TRY/EXCEPT exception handler and trap for an
exception. If an exception occurs, MONITOR and MWAIT are not supported at a privilege level greater than 0.
See Example 8-23.
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Example 8-23. Verifying MONITOR/MWAIT Support
boolean MONITOR_MWAIT_works = TRUE;
try {
_asm {
xor ecx, ecx
xor edx, edx
mov eax, MemArea
monitor
}
// Use monitor
} except (UNWIND) {
// if we get here, MONITOR/MWAIT is not supported
MONITOR_MWAIT_works = FALSE;
}
8.10.4
MONITOR/MWAIT Instruction
Operating systems usually implement idle loops to handle thread synchronization. In a typical idle-loop scenario,
there could be several “busy loops” and they would use a set of memory locations. An impacted processor waits in
a loop and poll a memory location to determine if there is available work to execute. The posting of work is typically
a write to memory (the work-queue of the waiting processor). The time for initiating a work request and getting it
scheduled is on the order of a few bus cycles.
From a resource sharing perspective (logical processors sharing execution resources), use of the HLT instruction in
an OS idle loop is desirable but has implications. Executing the HLT instruction on a idle logical processor puts the
targeted processor in a non-execution state. This requires another processor (when posting work for the halted
logical processor) to wake up the halted processor using an inter-processor interrupt. The posting and servicing of
such an interrupt introduces a delay in the servicing of new work requests.
In a shared memory configuration, exits from busy loops usually occur because of a state change applicable to a
specific memory location; such a change tends to be triggered by writes to the memory location by another agent
(typically a processor).
MONITOR/MWAIT complement the use of HLT and PAUSE to allow for efficient partitioning and un-partitioning of
shared resources among logical processors sharing physical resources. MONITOR sets up an effective address
range that is monitored for write-to-memory activities; MWAIT places the processor in an optimized state (this
may vary between different implementations) until a write to the monitored address range occurs.
In the initial implementation of MONITOR and MWAIT, they are available at CPL = 0 only.
Both instructions rely on the state of the processor’s monitor hardware. The monitor hardware can be either armed
(by executing the MONITOR instruction) or triggered (due to a variety of events, including a store to the monitored
memory region). If upon execution of MWAIT, monitor hardware is in a triggered state: MWAIT behaves as a NOP
and execution continues at the next instruction in the execution stream. The state of monitor hardware is not architecturally visible except through the behavior of MWAIT.
Multiple events other than a write to the triggering address range can cause a processor that executed MWAIT to
wake up. These include events that would lead to voluntary or involuntary context switches, such as:
•
•
•
External interrupts, including NMI, SMI, INIT, BINIT, MCERR, A20M#
•
Voluntary transitions due to fast system call and far calls (occurring prior to issuing MWAIT but after setting the
monitor)
Faults, Aborts (including Machine Check)
Architectural TLB invalidations including writes to CR0, CR3, CR4 and certain MSR writes; execution of LMSW
(occurring prior to issuing MWAIT but after setting the monitor)
Power management related events (such as Thermal Monitor 2 or chipset driven STPCLK# assertion) will not cause
the monitor event pending flag to be cleared. Faults will not cause the monitor event pending flag to be cleared.
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Software should not allow for voluntary context switches in between MONITOR/MWAIT in the instruction flow. Note
that execution of MWAIT does not re-arm the monitor hardware. This means that MONITOR/MWAIT need to be
executed in a loop. Also note that exits from the MWAIT state could be due to a condition other than a write to the
triggering address; software should explicitly check the triggering data location to determine if the write occurred.
Software should also check the value of the triggering address following the execution of the monitor instruction
(and prior to the execution of the MWAIT instruction). This check is to identify any writes to the triggering address
that occurred during the course of MONITOR execution.
The address range provided to the MONITOR instruction must be of write-back caching type. Only write-back
memory type stores to the monitored address range will trigger the monitor hardware. If the address range is not
in memory of write-back type, the address monitor hardware may not be set up properly or the monitor hardware
may not be armed. Software is also responsible for ensuring that
•
Writes that are not intended to cause the exit of a busy loop do not write to a location within the address region
being monitored by the monitor hardware,
•
Writes intended to cause the exit of a busy loop are written to locations within the monitored address region.
Not doing so will lead to more false wakeups (an exit from the MWAIT state not due to a write to the intended data
location). These have negative performance implications. It might be necessary for software to use padding to
prevent false wakeups. CPUID provides a mechanism for determining the size data locations for monitoring as well
as a mechanism for determining the size of a the pad.
8.10.5
Monitor/Mwait Address Range Determination
To use the MONITOR/MWAIT instructions, software should know the length of the region monitored by the
MONITOR/MWAIT instructions and the size of the coherence line size for cache-snoop traffic in a multiprocessor
system. This information can be queried using the CPUID monitor leaf function (EAX = 05H). You will need the
smallest and largest monitor line size:
•
To avoid missed wake-ups: make sure that the data structure used to monitor writes fits within the smallest
monitor line-size. Otherwise, the processor may not wake up after a write intended to trigger an exit from
MWAIT.
•
To avoid false wake-ups; use the largest monitor line size to pad the data structure used to monitor writes.
Software must make sure that beyond the data structure, no unrelated data variable exists in the triggering
area for MWAIT. A pad may be needed to avoid this situation.
These above two values bear no relationship to cache line size in the system and software should not make any
assumptions to that effect. Within a single-cluster system, the two parameters should default to be the same (the
size of the monitor triggering area is the same as the system coherence line size).
Based on the monitor line sizes returned by the CPUID, the OS should dynamically allocate structures with appropriate padding. If static data structures must be used by an OS, attempt to adapt the data structure and use a
dynamically allocated data buffer for thread synchronization. When the latter technique is not possible, consider
not using MONITOR/MWAIT when using static data structures.
To set up the data structure correctly for MONITOR/MWAIT on multi-clustered systems: interaction between
processors, chipsets, and the BIOS is required (system coherence line size may depend on the chipset used in the
system; the size could be different from the processor’s monitor triggering area). The BIOS is responsible to set the
correct value for system coherence line size using the IA32_MONITOR_FILTER_LINE_SIZE MSR. Depending on the
relative magnitude of the size of the monitor triggering area versus the value written into the
IA32_MONITOR_FILTER_LINE_SIZE MSR, the smaller of the parameters will be reported as the Smallest Monitor
Line Size. The larger of the parameters will be reported as the Largest Monitor Line Size.
8.10.6
Required Operating System Support
This section describes changes that must be made to an operating system to run on processors supporting Intel
Hyper-Threading Technology. It also describes optimizations that can help an operating system make more efficient
use of the logical processors sharing execution resources. The required changes and suggested optimizations are
representative of the types of modifications that appear in Windows* XP and Linux* kernel 2.4.0 operating systems
for Intel processors supporting Intel Hyper-Threading Technology. Additional optimizations for processors
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supporting Intel Hyper-Threading Technology are described in the Intel® 64 and IA-32 Architectures Optimization
Reference Manual.
8.10.6.1
Use the PAUSE Instruction in Spin-Wait Loops
Intel recommends that a PAUSE instruction be placed in all spin-wait loops that run on Intel processors supporting
Intel Hyper-Threading Technology and multi-core processors.
Software routines that use spin-wait loops include multiprocessor synchronization primitives (spin-locks, semaphores, and mutex variables) and idle loops. Such routines keep the processor core busy executing a load-comparebranch loop while a thread waits for a resource to become available. Including a PAUSE instruction in such a loop
greatly improves efficiency (see Section 8.10.2, “PAUSE Instruction”). The following routine gives an example of a
spin-wait loop that uses a PAUSE instruction:
Spin_Lock:
CMP lockvar, 0
;Check if lock is free
JE Get_Lock
PAUSE
;Short delay
JMP Spin_Lock
Get_Lock:
MOV EAX, 1
XCHG EAX, lockvar ;Try to get lock
CMP EAX, 0
;Test if successful
JNE Spin_Lock
Critical_Section:
MOV lockvar, 0
...
Continue:
The spin-wait loop above uses a “test, test-and-set” technique for determining the availability of the synchronization variable. This technique is recommended when writing spin-wait loops.
In IA-32 processor generations earlier than the Pentium 4 processor, the PAUSE instruction is treated as a NOP
instruction.
8.10.6.2
Potential Usage of MONITOR/MWAIT in C0 Idle Loops
An operating system may implement different handlers for different idle states. A typical OS idle loop on an ACPIcompatible OS is shown in Example 8-24:
Example 8-24. A Typical OS Idle Loop
// WorkQueue is a memory location indicating there is a thread
// ready to run. A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The idle loop is entered with interrupts disabled.
WHILE (1) {
IF (WorkQueue) THEN {
// Schedule work at WorkQueue.
}
ELSE {
// No work to do - wait in appropriate C-state handler depending
// on Idle time accumulated
IF (IdleTime >= IdleTimeThreshhold) THEN {
// Call appropriate C1, C2, C3 state handler, C1 handler
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// shown below
}
}
}
// C1 handler uses a Halt instruction
VOID C1Handler()
{ STI
HLT
}
The MONITOR and MWAIT instructions may be considered for use in the C0 idle state loops, if MONITOR and MWAIT are supported.
Example 8-25. An OS Idle Loop with MONITOR/MWAIT in the C0 Idle Loop
// WorkQueue is a memory location indicating there is a thread
// ready to run. A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The following example assumes that the necessary padding has been
// added surrounding WorkQueue to eliminate false wakeups
// The idle loop is entered with interrupts disabled.
WHILE (1) {
IF (WorkQueue) THEN {
// Schedule work at WorkQueue.
}
ELSE {
// No work to do - wait in appropriate C-state handler depending
// on Idle time accumulated.
IF (IdleTime >= IdleTimeThreshhold) THEN {
// Call appropriate C1, C2, C3 state handler, C1
// handler shown below
MONITOR WorkQueue // Setup of eax with WorkQueue
// LinearAddress,
// ECX, EDX = 0
IF (WorkQueue ≠ 0) THEN {
MWAIT
}
}
}
}
// C1 handler uses a Halt instruction.
VOID C1Handler()
{ STI
HLT
}
8.10.6.3
Halt Idle Logical Processors
If one of two logical processors is idle or in a spin-wait loop of long duration, explicitly halt that processor by means
of a HLT instruction.
In an MP system, operating systems can place idle processors into a loop that continuously checks the run queue
for runnable software tasks. Logical processors that execute idle loops consume a significant amount of core’s
execution resources that might otherwise be used by the other logical processors in the physical package. For this
reason, halting idle logical processors optimizes the performance.12 If all logical processors within a physical
package are halted, the processor will enter a power-saving state.
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8.10.6.4
Potential Usage of MONITOR/MWAIT in C1 Idle Loops
An operating system may also consider replacing HLT with MONITOR/MWAIT in its C1 idle loop. An example is
shown in Example 8-26:
Example 8-26. An OS Idle Loop with MONITOR/MWAIT in the C1 Idle Loop
// WorkQueue is a memory location indicating there is a thread
// ready to run. A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The following example assumes that the necessary padding has been
// added surrounding WorkQueue to eliminate false wakeups
// The idle loop is entered with interrupts disabled.
WHILE (1) {
IF (WorkQueue) THEN {
// Schedule work at WorkQueue
}
ELSE {
// No work to do - wait in appropriate C-state handler depending
// on Idle time accumulated
IF (IdleTime >= IdleTimeThreshhold) THEN {
// Call appropriate C1, C2, C3 state handler, C1
// handler shown below
}
}
}
VOID C1Handler()
{
MONITOR WorkQueue // Setup of eax with WorkQueue LinearAddress,
// ECX, EDX = 0
IF (WorkQueue ≠ 0) THEN {
STI
MWAIT
// EAX, ECX = 0
}
}
8.10.6.5
Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources
Because the logical processors, the order in which threads are dispatched to logical processors for execution can
affect the overall efficiency of a system. The following guidelines are recommended for scheduling threads for
execution.
•
Dispatch threads to one logical processor per processor core before dispatching threads to the other logical
processor sharing execution resources in the same processor core.
•
In an MP system with two or more physical packages, distribute threads out over all the physical processors,
rather than concentrate them in one or two physical processors.
•
Use processor affinity to assign a thread to a specific processor core or package, depending on the cachesharing topology. The practice increases the chance that the processor’s caches will contain some of the
thread’s code and data when it is dispatched for execution after being suspended.
12. Excessive transitions into and out of the HALT state could also incur performance penalties. Operating systems should evaluate the
performance trade-offs for their operating system.
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8.10.6.6
Eliminate Execution-Based Timing Loops
Intel discourages the use of timing loops that depend on a processor’s execution speed to measure time. There are
several reasons:
•
Timing loops cause problems when they are calibrated on a IA-32 processor running at one frequency and then
executed on a processor running at another frequency.
•
Routines for calibrating execution-based timing loops produce unpredictable results when run on an IA-32
processor supporting Intel Hyper-Threading Technology. This is due to the sharing of execution resources
between the logical processors within a physical package.
To avoid the problems described, timing loop routines must use a timing mechanism for the loop that does not
depend on the execution speed of the logical processors in the system. The following sources are generally available:
•
•
A high resolution system timer (for example, an Intel 8254).
A high resolution timer within the processor (such as, the local APIC timer or the time-stamp counter).
For additional information, see the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
8.10.6.7
Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory
When software uses locks or semaphores to synchronize processes, threads, or other code sections; Intel recommends that only one lock or semaphore be present within a cache line (or 128 byte sector, if 128-byte sector is
supported). In processors based on Intel NetBurst microarchitecture (which support 128-byte sector consisting of
two cache lines), following this recommendation means that each lock or semaphore should be contained in a 128byte block of memory that begins on a 128-byte boundary. The practice minimizes the bus traffic required to
service locks.
8.11
MP INITIALIZATION FOR P6 FAMILY PROCESSORS
This section describes the MP initialization process for systems that use multiple P6 family processors. This process
uses the MP initialization protocol that was introduced with the Pentium Pro processor (see Section 8.4, “MultipleProcessor (MP) Initialization”). For P6 family processors, this protocol is typically used to boot 2 or 4 processors
that reside on single system bus; however, it can support from 2 to 15 processors in a multi-clustered system when
the APIC busses are tied together. Larger systems are not supported.
8.11.1
Overview of the MP Initialization Process For P6 Family Processors
During the execution of the MP initialization protocol, one processor is selected as the bootstrap processor (BSP)
and the remaining processors are designated as application processors (APs), see Section 8.4.1, “BSP and AP
Processors.” Thereafter, the BSP manages the initialization of itself and the APs. This initialization includes
executing BIOS initialization code and operating-system initialization code.
The MP protocol imposes the following requirements and restrictions on the system:
•
•
An APIC clock (APICLK) must be provided.
•
All devices in the system that are capable of delivering interrupts to the processors must be inhibited from
doing so for the duration of the MP initialization protocol. The time during which interrupts must be inhibited
includes the window between when the BSP issues an INIT-SIPI-SIPI sequence to an AP and when the AP
responds to the last SIPI in the sequence.
The MP protocol will be executed only after a power-up or RESET. If the MP protocol has been completed and a
BSP has been chosen, subsequent INITs (either to a specific processor or system wide) do not cause the MP
protocol to be repeated. Instead, each processor examines its BSP flag (in the APIC_BASE MSR) to determine
whether it should execute the BIOS boot-strap code (if it is the BSP) or enter a wait-for-SIPI state (if it is an
AP).
The following special-purpose interprocessor interrupts (IPIs) are used during the boot phase of the MP initialization protocol. These IPIs are broadcast on the APIC bus.
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•
Boot IPI (BIPI)—Initiates the arbitration mechanism that selects a BSP from the group of processors on the
system bus and designates the remainder of the processors as APs. Each processor on the system bus
broadcasts a BIPI to all the processors following a power-up or RESET.
•
Final Boot IPI (FIPI)—Initiates the BIOS initialization procedure for the BSP. This IPI is broadcast to all the
processors on the system bus, but only the BSP responds to it. The BSP responds by beginning execution of the
BIOS initialization code at the reset vector.
•
Startup IPI (SIPI)—Initiates the initialization procedure for an AP. The SIPI message contains a vector to the AP
initialization code in the BIOS.
Table 8-5 describes the various fields of the boot phase IPIs.
Table 8-5. Boot Phase IPI Message Format
Type
Destination
Field
Destination
Shorthand
Trigger
Mode
Level
Destination
Mode
Delivery
Mode
Vector
(Hex)
BIPI
Not used
All including self
Edge
Deassert
Don’t Care
Fixed
(000)
40 to 4E*
FIPI
Not used
All including self
Edge
Deassert
Don’t Care
Fixed
(000)
10
SIPI
Used
All excluding self
Edge
Assert
Physical
StartUp
(110)
00 to FF
NOTE:
* For all P6 family processors.
For BIPI messages, the lower 4 bits of the vector field contain the APIC ID of the processor issuing the message and
the upper 4 bits contain the “generation ID” of the message. All P6 family processor will have a generation ID of
4H. BIPIs will therefore use vector values ranging from 40H to 4EH (4FH can not be used because FH is not a valid
APIC ID).
8.11.2
MP Initialization Protocol Algorithm
Following a power-up or RESET of a system, the P6 family processors in the system execute the MP initialization
protocol algorithm to initialize each of the processors on the system bus. In the course of executing this algorithm,
the following boot-up and initialization operations are carried out:
1. Each processor on the system bus is assigned a unique APIC ID, based on system topology (see Section 8.4.5,
“Identifying Logical Processors in an MP System”). This ID is written into the local APIC ID register for each
processor.
2. Each processor executes its internal BIST simultaneously with the other processors on the system bus. Upon
completion of the BIST (at T0), each processor broadcasts a BIPI to “all including self” (see Figure 8-1).
3. APIC arbitration hardware causes all the APICs to respond to the BIPIs one at a time (at T1, T2, T3, and T4).
4. When the first BIPI is received (at time T1), each APIC compares the four least significant bits of the BIPI’s
vector field with its APIC ID. If the vector and APIC ID match, the processor selects itself as the BSP by setting
the BSP flag in its IA32_APIC_BASE MSR. If the vector and APIC ID do not match, the processor selects itself
as an AP by entering the “wait for SIPI” state. (Note that in Figure 8-1, the BIPI from processor 1 is the first
BIPI to be handled, so processor 1 becomes the BSP.)
5. The newly established BSP broadcasts an FIPI message to “all including self.” The FIPI is guaranteed to be
handled only after the completion of the BIPIs that were issued by the non-BSP processors.
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System (CPU) Bus
Pentium III
Processor 0
Pentium III
Processor 1
Pentium III
Processor 2
Pentium III
Processor 3
APIC Bus
Processor 1
Becomes BSP
T0
T1
BIPI.1
T2
BIPI.0
T3
BIPI.3
T4
BIPI.2
T5
FIPI
Serial Bus Activity
Figure 8-1. MP System With Multiple Pentium III Processors
6. After the BSP has been established, the outstanding BIPIs are received one at a time (at T2, T3, and T4) and
ignored by all processors.
7. When the FIPI is finally received (at T5), only the BSP responds to it. It responds by fetching and executing
BIOS boot-strap code, beginning at the reset vector (physical address FFFF FFF0H).
8. As part of the boot-strap code, the BSP creates an ACPI table and an MP table and adds its initial APIC ID to
these tables as appropriate.
9. At the end of the boot-strap procedure, the BSP broadcasts a SIPI message to all the APs in the system. Here,
the SIPI message contains a vector to the BIOS AP initialization code (at 000V V000H, where VV is the vector
contained in the SIPI message).
10. All APs respond to the SIPI message by racing to a BIOS initialization semaphore. The first one to the
semaphore begins executing the initialization code. (See MP init code for semaphore implementation details.)
As part of the AP initialization procedure, the AP adds its APIC ID number to the ACPI and MP tables as appropriate. At the completion of the initialization procedure, the AP executes a CLI instruction (to clear the IF flag in
the EFLAGS register) and halts itself.
11. When each of the APs has gained access to the semaphore and executed the AP initialization code and all
written their APIC IDs into the appropriate places in the ACPI and MP tables, the BSP establishes a count for the
number of processors connected to the system bus, completes executing the BIOS boot-strap code, and then
begins executing operating-system boot-strap and start-up code.
12. While the BSP is executing operating-system boot-strap and start-up code, the APs remain in the halted state.
In this state they will respond only to INITs, NMIs, and SMIs. They will also respond to snoops and to assertions
of the STPCLK# pin.
See Section 8.4.4, “MP Initialization Example,” for an annotated example the use of the MP protocol to boot IA-32
processors in an MP. This code should run on any IA-32 processor that used the MP protocol.
8.11.2.1
Error Detection and Handling During the MP Initialization Protocol
Errors may occur on the APIC bus during the MP initialization phase. These errors may be transient or permanent
and can be caused by a variety of failure mechanisms (for example, broken traces, soft errors during bus usage,
etc.). All serial bus related errors will result in an APIC checksum or acceptance error.
The MP initialization protocol makes the following assumptions regarding errors that occur during initialization:
•
If errors are detected on the APIC bus during execution of the MP initialization protocol, the processors that
detect the errors are shut down.
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•
The MP initialization protocol will be executed by processors even if they fail their BIST sequences.
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CHAPTER 9
PROCESSOR MANAGEMENT AND INITIALIZATION
This chapter describes the facilities provided for managing processor wide functions and for initializing the
processor. The subjects covered include: processor initialization, x87 FPU initialization, processor configuration,
feature determination, mode switching, the MSRs (in the Pentium, P6 family, Pentium 4, and Intel Xeon processors), and the MTRRs (in the P6 family, Pentium 4, and Intel Xeon processors).
9.1
INITIALIZATION OVERVIEW
Following power-up or an assertion of the RESET# pin, each processor on the system bus performs a hardware
initialization of the processor (known as a hardware reset) and an optional built-in self-test (BIST). A hardware
reset sets each processor’s registers to a known state and places the processor in real-address mode. It also invalidates the internal caches, translation lookaside buffers (TLBs) and the branch target buffer (BTB). At this point,
the action taken depends on the processor family:
•
Pentium 4 processors (CPUID DisplayFamily 0FH) — All the processors on the system bus (including a
single processor in a uniprocessor system) execute the multiple processor (MP) initialization protocol. The
processor that is selected through this protocol as the bootstrap processor (BSP) then immediately starts
executing software-initialization code in the current code segment beginning at the offset in the EIP register.
The application (non-BSP) processors (APs) go into a Wait For Startup IPI (SIPI) state while the BSP is
executing initialization code. See Section 8.4, “Multiple-Processor (MP) Initialization,” for more details. Note
that in a uniprocessor system, the single Pentium 4 or Intel Xeon processor automatically becomes the BSP.
•
IA-32 and Intel 64 processors (CPUID DisplayFamily 06H) — The action taken is the same as for the
Pentium 4 processors (as described in the previous paragraph).
•
Pentium processors — In either a single- or dual- processor system, a single Pentium processor is always
pre-designated as the primary processor. Following a reset, the primary processor behaves as follows in both
single- and dual-processor systems. Using the dual-processor (DP) ready initialization protocol, the primary
processor immediately starts executing software-initialization code in the current code segment beginning at
the offset in the EIP register. The secondary processor (if there is one) goes into a halt state.
•
Intel486 processor — The primary processor (or single processor in a uniprocessor system) immediately
starts executing software-initialization code in the current code segment beginning at the offset in the EIP
register. (The Intel486 does not automatically execute a DP or MP initialization protocol to determine which
processor is the primary processor.)
The software-initialization code performs all system-specific initialization of the BSP or primary processor and the
system logic.
At this point, for MP (or DP) systems, the BSP (or primary) processor wakes up each AP (or secondary) processor
to enable those processors to execute self-configuration code.
When all processors are initialized, configured, and synchronized, the BSP or primary processor begins executing
an initial operating-system or executive task.
The x87 FPU is also initialized to a known state during hardware reset. x87 FPU software initialization code can then
be executed to perform operations such as setting the precision of the x87 FPU and the exception masks. No special
initialization of the x87 FPU is required to switch operating modes.
Asserting the INIT# pin on the processor invokes a similar response to a hardware reset. The major difference is
that during an INIT, the internal caches, MSRs, MTRRs, and x87 FPU state are left unchanged (although, the TLBs
and BTB are invalidated as with a hardware reset). An INIT provides a method for switching from protected to realaddress mode while maintaining the contents of the internal caches.
Vol. 3A 9-1
PROCESSOR MANAGEMENT AND INITIALIZATION
9.1.1
Processor State After Reset
Following power-up, The state of control register CR0 is 60000010H (see Figure 9-1). This places the processor is
in real-address mode with paging disabled.
Paging disabled: 0
Caching disabled: 1
Not write-through disabled: 1
Alignment check disabled: 0
Write-protect disabled: 0
31 30 29 28
P C N
GDW
19 18 17 16 15
Reserved
A
M
W
P
6 5 4 3 2 1 0
Reserved
N
T E M P
1
E
S MP E
External x87 FPU error reporting: 0
(Not used): 1
No task switch: 0
x87 FPU instructions not trapped: 0
WAIT/FWAIT instructions not trapped: 0
Real-address mode: 0
Figure 9-1. Contents of CR0 Register after Reset
The state of the flags and other registers following power-up for the Pentium 4, Pentium Pro, and Pentium processors are shown in Section 22.39, “Initial State of Pentium, Pentium Pro and Pentium 4 Processors” of the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Table 9-1 shows processor states of IA-32 and Intel 64 processors with CPUID DisplayFamily signature of 06H at
the following events: power-up, RESET, and INIT. In a few cases, the behavior of some registers behave slightly
different across warm RESET, the variant cases are marked in Table 9-1 and described in more detail in Table 9-2.
Table 9-1. IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT
Register
Power up
Reset
INIT
EFLAGS1
00000002H
00000002H
00000002H
EIP
0000FFF0H
0000FFF0H
0000FFF0H
CR0
60000010H2
60000010H2
60000010H2
CR2, CR3, CR4
00000000H
00000000H
00000000H
CS
Selector = F000H
Base = FFFF0000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = F000H
Base = FFFF0000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = F000H
Base = FFFF0000H
Limit = FFFFH
AR = Present, R/W, Accessed
SS, DS, ES, FS, GS
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W, Accessed
EDX
000n06xxH3
000n06xxH3
000n06xxH3
EAX
04
04
04
EBX, ECX, ESI, EDI, EBP, ESP
00000000H
00000000H
00000000H
ST0 through ST7
+0.0
+0.0
FINIT/FNINIT: Unchanged
9-2 Vol. 3A
5
PROCESSOR MANAGEMENT AND INITIALIZATION
Table 9-1. IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT (Contd.)
Register
Power up
Reset
INIT
x87 FPU Control Word5
0040H
0040H
FINIT/FNINIT: 037FH
x87 FPU Status Word
0000H
0000H
FINIT/FNINIT: 0000H
x87 FPU Tag Word5
5555H
5555H
FINIT/FNINIT: FFFFH
x87 FPU Data Operand and
CS Seg. Selectors5
0000H
0000H
FINIT/FNINIT: 0000H
x87 FPU Data Operand and
Inst. Pointers5
00000000H
00000000H
FINIT/FNINIT: 00000000H
MM0 through MM75
0000000000000000H
0000000000000000H
INIT or FINIT/FNINIT: Unchanged
XMM0 through XMM7
0H
0H
Unchanged
MXCSR
1F80H
1F80H
Unchanged
GDTR, IDTR
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
LDTR, Task Register
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
DR0, DR1, DR2, DR3
00000000H
00000000H
00000000H
DR6
FFFF0FF0H
FFFF0FF0H
FFFF0FF0H
DR7
00000400H
00000400H
00000400H
R8-R15
0000000000000000H
0000000000000000H
0000000000000000H
XMM8-XMM15
0H
0H
Unchanged
XCR0
1H
1H
Unchanged
IA32_XSS
0H
0H
0H
YMM_H[255:128]
0H
0H
Unchanged
BNDCFGU
0H
0H
0H
BND0-BND3
0H
0H
0H
IA32_BNDCFGS
0H
0H
0H
OPMASK
0H
0H
Unchanged
ZMM_H[511:256]
0H
0H
Unchanged
ZMMHi16[511:0]
0H
0H
Unchanged
PKRU
0H
0H
Unchanged
Intel Processor Trace MSRs
0H
Time-Stamp Counter
5
0H
W
Unchanged
0H
0H
W
Unchanged
IA32_TSC_AUX
0H
0H
Unchanged
IA32_TSC_ADJUST
0H
0H
Unchanged
IA32_TSC_DEADLINE
0H
0H
Unchanged
IA32_SYSENTER_CS/ESP/EIP
0H
0H
Unchanged
IA32_EFER
0000000000000000H
0000000000000000H
0000000000000000H
IA32_STAR/LSTAR
0H
0H
Unchanged
IA32_FS_BASE/GS_BASE
0H
0H
0H
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PROCESSOR MANAGEMENT AND INITIALIZATION
Table 9-1. IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT (Contd.)
Register
Power up
Reset
INIT
IA32_PMCx,
IA32_PERFEVTSELx
0H
0H
Unchanged
IA32_FIXED_CTRx,
IA32_FIXED_CTR_CTRL,
0H
0H
Unchanged
Data and Code Cache, TLBs
Invalid6
Invalid6
Unchanged
Fixed MTRRs
Disabled
Disabled
Unchanged
Global Perf Counter Controls
Variable MTRRs
Disabled
Disabled
Unchanged
Machine-Check Banks
Undefined
UndefinedW
Unchanged
Last Branch Record Stack
0
0W
Unchanged
APIC
Enabled
Enabled
Unchanged
X2APIC
Disabled
Disabled
Unchanged
MSR_FEATURE_CONFIG
0
0W
Unchanged
IA32_DEBUG_INTERFACE
0
0
Unchanged
W
NOTES:
1. The 10 most-significant bits of the EFLAGS register are undefined following a reset. Software should not depend on the states of
any of these bits.
2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits are cleared.
3. Where “n” is the Extended Model Value for the respective processor, and “xx” = don’t care.
4. If Built-In Self-Test (BIST) is invoked on power up or reset, EAX is 0 only if all tests passed. (BIST cannot be invoked during an INIT.)
5. The state of the x87 FPU and MMX registers is not changed by the execution of an INIT.
6. Internal caches are invalid after power-up and RESET, but left unchanged with an INIT.
W: Warm RESET behavior differs from power-on RESET with details listed in Table 9-2.
Table 9-2. Variance of RESET Values in Selected Intel Architecture Processors
State
XREF
Value
Feature Flag or DisplayFamily_DisplayModel Signatures
Time-Stamp Counter
Warm RESET Unmodified across warm
Reset
06_2DH, 06_3EH
Machine-Check Banks
Warm RESET IA32_MCi_Status banks are
unmodified across warm
Reset
06_2DH, 06_3EH, 06_3FH, 06_4FH, 06_56H
Last Branch Record Stack
Warm RESET LBR stack MSRs are
unmodified across warm
Reset
06_1AH, 06_1CH, DisplayFamiy= 06 and DisplayModel >1DH
MSR_FEATURE_CONFIG
Warm RESET Unmodified across warm
Reset
06_2AH, 06_2CH, 06_2DH, 06_2FH, 06_3AH,
DisplayFamiy= 06 and DisplayModel >37H
Intel Processor Trace
MSRs
Warm RESET Clears
IA32_RTIT_CTL.TraceEn,
the rest of MSRs are
unmodified
If CPUID.(EAX=14H, ECX=0H):EBX[bit 2] = 1
IA32_DEBUG_INTERFACE
Warm RESET Unmodified across warm
Reset
If CPUID.01H:ECX.[11] = 1
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PROCESSOR MANAGEMENT AND INITIALIZATION
9.1.2
Processor Built-In Self-Test (BIST)
Hardware may request that the BIST be performed at power-up. The EAX register is cleared (0H) if the processor
passes the BIST. A nonzero value in the EAX register after the BIST indicates that a processor fault was detected.
If the BIST is not requested, the contents of the EAX register after a hardware reset is 0H.
The overhead for performing a BIST varies between processor families. For example, the BIST takes approximately
30 million processor clock periods to execute on the Pentium 4 processor. This clock count is model-specific; Intel
reserves the right to change the number of periods for any Intel 64 or IA-32 processor, without notification.
9.1.3
Model and Stepping Information
Following a hardware reset, the EDX register contains component identification and revision information (see
Figure 9-2). For example, the model, family, and processor type returned for the first processor in the Intel
Pentium 4 family is as follows: model (0000B), family (1111B), and processor type (00B).
31
EDX
28 27
20 19
Extended
Family
16 15 14 13 12 11
Extended
Model
Family
8 7
4 3
Model
0
Stepping
ID
Processor Type
Family (1111B for the Pentium 4 Processor Family)
Model (Beginning with 0000B)
Reserved
Figure 9-2. Version Information in the EDX Register after Reset
The stepping ID field contains a unique identifier for the processor’s stepping ID or revision level. The extended
family and extended model fields were added to the IA-32 architecture in the Pentium 4 processors.
9.1.4
First Instruction Executed
The first instruction that is fetched and executed following a hardware reset is located at physical address
FFFFFFF0H. This address is 16 bytes below the processor’s uppermost physical address. The EPROM containing the
software-initialization code must be located at this address.
The address FFFFFFF0H is beyond the 1-MByte addressable range of the processor while in real-address mode. The
processor is initialized to this starting address as follows. The CS register has two parts: the visible segment
selector part and the hidden base address part. In real-address mode, the base address is normally formed by
shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a
hardware reset, the segment selector in the CS register is loaded with F000H and the base address is loaded with
FFFF0000H. The starting address is thus formed by adding the base address to the value in the EIP register (that
is, FFFF0000 + FFF0H = FFFFFFF0H).
The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal
rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To
insure that the base address in the CS register remains unchanged until the EPROM based software-initialization
code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would
cause the CS selector value to be changed).
9.2
X87 FPU INITIALIZATION
Software-initialization code can determine the whether the processor contains an x87 FPU by using the CPUID
instruction. The code must then initialize the x87 FPU and set flags in control register CR0 to reflect the state of the
x87 FPU environment.
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A hardware reset places the x87 FPU in the state shown in Table 9-1. This state is different from the state the x87
FPU is placed in following the execution of an FINIT or FNINIT instruction (also shown in Table 9-1). If the x87 FPU
is to be used, the software-initialization code should execute an FINIT/FNINIT instruction following a hardware
reset. These instructions, tag all data registers as empty, clear all the exception masks, set the TOP-of-stack value
to 0, and select the default rounding and precision controls setting (round to nearest and 64-bit precision).
If the processor is reset by asserting the INIT# pin, the x87 FPU state is not changed.
9.2.1
Configuring the x87 FPU Environment
Initialization code must load the appropriate values into the MP, EM, and NE flags of control register CR0. These bits
are cleared on hardware reset of the processor. Figure 9-3 shows the suggested settings for these flags, depending
on the IA-32 processor being initialized. Initialization code can test for the type of processor present before setting
or clearing these flags.
Table 9-3. Recommended Settings of EM and MP Flags on IA-32 Processors
EM
MP
NE
IA-32 processor
1
0
1
Intel486™ SX, Intel386™ DX, and Intel386™ SX processors only, without the presence of a math
coprocessor.
0
1
1 or 0*
Pentium 4, Intel Xeon, P6 family, Pentium, Intel486™ DX, and Intel 487 SX processors, and
Intel386 DX and Intel386 SX processors when a companion math coprocessor is present.
0
1
1 or 0*
More recent Intel 64 or IA-32 processors
NOTE:
* The setting of the NE flag depends on the operating system being used.
The EM flag determines whether floating-point instructions are executed by the x87 FPU (EM is cleared) or a
device-not-available exception (#NM) is generated for all floating-point instructions so that an exception handler
can emulate the floating-point operation (EM = 1). Ordinarily, the EM flag is cleared when an x87 FPU or math
coprocessor is present and set if they are not present. If the EM flag is set and no x87 FPU, math coprocessor, or
floating-point emulator is present, the processor will hang when a floating-point instruction is executed.
The MP flag determines whether WAIT/FWAIT instructions react to the setting of the TS flag. If the MP flag is clear,
WAIT/FWAIT instructions ignore the setting of the TS flag; if the MP flag is set, they will generate a device-notavailable exception (#NM) if the TS flag is set. Generally, the MP flag should be set for processors with an integrated x87 FPU and clear for processors without an integrated x87 FPU and without a math coprocessor present.
However, an operating system can choose to save the floating-point context at every context switch, in which case
there would be no need to set the MP bit.
Table 2-2 shows the actions taken for floating-point and WAIT/FWAIT instructions based on the settings of the EM,
MP, and TS flags.
The NE flag determines whether unmasked floating-point exceptions are handled by generating a floating-point
error exception internally (NE is set, native mode) or through an external interrupt (NE is cleared). In systems
where an external interrupt controller is used to invoke numeric exception handlers (such as MS-DOS-based
systems), the NE bit should be cleared.
9.2.2
Setting the Processor for x87 FPU Software Emulation
Setting the EM flag causes the processor to generate a device-not-available exception (#NM) and trap to a software
exception handler whenever it encounters a floating-point instruction. (Table 9-3 shows when it is appropriate to
use this flag.) Setting this flag has two functions:
•
It allows x87 FPU code to run on an IA-32 processor that has neither an integrated x87 FPU nor is connected to
an external math coprocessor, by using a floating-point emulator.
•
It allows floating-point code to be executed using a special or nonstandard floating-point emulator, selected for
a particular application, regardless of whether an x87 FPU or math coprocessor is present.
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PROCESSOR MANAGEMENT AND INITIALIZATION
To emulate floating-point instructions, the EM, MP, and NE flag in control register CR0 should be set as shown in
Table 9-4.
Table 9-4. Software Emulation Settings of EM, MP, and NE Flags
CR0 Bit
Value
EM
1
MP
0
NE
1
Regardless of the value of the EM bit, the Intel486 SX processor generates a device-not-available exception (#NM)
upon encountering any floating-point instruction.
9.3
CACHE ENABLING
IA-32 processors (beginning with the Intel486 processor) and Intel 64 processors contain internal instruction and
data caches. These caches are enabled by clearing the CD and NW flags in control register CR0. (They are set
during a hardware reset.) Because all internal cache lines are invalid following reset initialization, it is not necessary to invalidate the cache before enabling caching. Any external caches may require initialization and invalidation
using a system-specific initialization and invalidation code sequence.
Depending on the hardware and operating system or executive requirements, additional configuration of the
processor’s caching facilities will probably be required. Beginning with the Intel486 processor, page-level caching
can be controlled with the PCD and PWT flags in page-directory and page-table entries. Beginning with the P6
family processors, the memory type range registers (MTRRs) control the caching characteristics of the regions of
physical memory. (For the Intel486 and Pentium processors, external hardware can be used to control the caching
characteristics of regions of physical memory.) See Chapter 11, “Memory Cache Control,” for detailed information
on configuration of the caching facilities in the Pentium 4, Intel Xeon, and P6 family processors and system
memory.
9.4
MODEL-SPECIFIC REGISTERS (MSRS)
Most IA-32 processors (starting from Pentium processors) and Intel 64 processors contain a model-specific registers (MSRs). A given MSR may not be supported across all families and models for Intel 64 and IA-32 processors.
Some MSRs are designated as architectural to simplify software programming; a feature introduced by an architectural MSR is expected to be supported in future processors. Non-architectural MSRs are not guaranteed to be
supported or to have the same functions on future processors.
MSRs that provide control for a number of hardware and software-related features, include:
•
•
•
Performance-monitoring counters (see Chapter 23, “Introduction to Virtual Machine Extensions”).
•
•
•
•
MTRRs (see Section 11.11, “Memory Type Range Registers (MTRRs)”).
Debug extensions (see Chapter 23, “Introduction to Virtual Machine Extensions.”).
Machine-check exception capability and its accompanying machine-check architecture (see Chapter 15,
“Machine-Check Architecture”).
Thermal and power management.
Instruction-specific support (for example: SYSENTER, SYSEXIT, SWAPGS, etc.).
Processor feature/mode support (for example: IA32_EFER, IA32_FEATURE_CONTROL).
The MSRs can be read and written to using the RDMSR and WRMSR instructions, respectively.
When performing software initialization of an IA-32 or Intel 64 processor, many of the MSRs will need to be initialized to set up things like performance-monitoring events, run-time machine checks, and memory types for physical memory.
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Lists of available performance-monitoring events are given in Chapter 19, “Performance Monitoring Events”, and
lists of available MSRs are given in Chapter 35, “Model-Specific Registers (MSRs)” The references earlier in this
section show where the functions of the various groups of MSRs are described in this manual.
9.5
MEMORY TYPE RANGE REGISTERS (MTRRS)
Memory type range registers (MTRRs) were introduced into the IA-32 architecture with the Pentium Pro processor.
They allow the type of caching (or no caching) to be specified in system memory for selected physical address
ranges. They allow memory accesses to be optimized for various types of memory such as RAM, ROM, frame buffer
memory, and memory-mapped I/O devices.
In general, initializing the MTRRs is normally handled by the software initialization code or BIOS and is not an operating system or executive function. At the very least, all the MTRRs must be cleared to 0, which selects the
uncached (UC) memory type. See Section 11.11, “Memory Type Range Registers (MTRRs),” for detailed information on the MTRRs.
9.6
INITIALIZING SSE/SSE2/SSE3/SSSE3 EXTENSIONS
For processors that contain SSE/SSE2/SSE3/SSSE3 extensions, steps must be taken when initializing the
processor to allow execution of these instructions.
1. Check the CPUID feature flags for the presence of the SSE/SSE2/SSE3/SSSE3 extensions (respectively: EDX
bits 25 and 26, ECX bit 0 and 9) and support for the FXSAVE and FXRSTOR instructions (EDX bit 24). Also check
for support for the CLFLUSH instruction (EDX bit 19). The CPUID feature flags are loaded in the EDX and ECX
registers when the CPUID instruction is executed with a 1 in the EAX register.
2. Set the OSFXSR flag (bit 9 in control register CR4) to indicate that the operating system supports saving and
restoring the SSE/SSE2/SSE3/SSSE3 execution environment (XMM and MXCSR registers) with the FXSAVE and
FXRSTOR instructions, respectively. See Section 2.5, “Control Registers,” for a description of the OSFXSR flag.
3. Set the OSXMMEXCPT flag (bit 10 in control register CR4) to indicate that the operating system supports the
handling of SSE/SSE2/SSE3 SIMD floating-point exceptions (#XM). See Section 2.5, “Control Registers,” for a
description of the OSXMMEXCPT flag.
4. Set the mask bits and flags in the MXCSR register according to the mode of operation desired for
SSE/SSE2/SSE3 SIMD floating-point instructions. See “MXCSR Control and Status Register” in Chapter 10,
“Programming with Streaming SIMD Extensions (SSE),” of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1, for a detailed description of the bits and flags in the MXCSR register.
9.7
SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION
Following a hardware reset (either through a power-up or the assertion of the RESET# pin) the processor is placed
in real-address mode and begins executing software initialization code from physical address FFFFFFF0H. Software
initialization code must first set up the necessary data structures for handling basic system functions, such as a
real-mode IDT for handling interrupts and exceptions. If the processor is to remain in real-address mode, software
must then load additional operating-system or executive code modules and data structures to allow reliable execution of application programs in real-address mode.
If the processor is going to operate in protected mode, software must load the necessary data structures to operate
in protected mode and then switch to protected mode. The protected-mode data structures that must be loaded
are described in Section 9.8, “Software Initialization for Protected-Mode Operation.”
9.7.1
Real-Address Mode IDT
In real-address mode, the only system data structure that must be loaded into memory is the IDT (also called the
“interrupt vector table”). By default, the address of the base of the IDT is physical address 0H. This address can be
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PROCESSOR MANAGEMENT AND INITIALIZATION
changed by using the LIDT instruction to change the base address value in the IDTR. Software initialization code
needs to load interrupt- and exception-handler pointers into the IDT before interrupts can be enabled.
The actual interrupt- and exception-handler code can be contained either in EPROM or RAM; however, the code
must be located within the 1-MByte addressable range of the processor in real-address mode. If the handler code
is to be stored in RAM, it must be loaded along with the IDT.
9.7.2
NMI Interrupt Handling
The NMI interrupt is always enabled (except when multiple NMIs are nested). If the IDT and the NMI interrupt
handler need to be loaded into RAM, there will be a period of time following hardware reset when an NMI interrupt
cannot be handled. During this time, hardware must provide a mechanism to prevent an NMI interrupt from halting
code execution until the IDT and the necessary NMI handler software is loaded. Here are two examples of how
NMIs can be handled during the initial states of processor initialization:
•
A simple IDT and NMI interrupt handler can be provided in EPROM. This allows an NMI interrupt to be handled
immediately after reset initialization.
•
The system hardware can provide a mechanism to enable and disable NMIs by passing the NMI# signal through
an AND gate controlled by a flag in an I/O port. Hardware can clear the flag when the processor is reset, and
software can set the flag when it is ready to handle NMI interrupts.
9.8
SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION
The processor is placed in real-address mode following a hardware reset. At this point in the initialization process,
some basic data structures and code modules must be loaded into physical memory to support further initialization
of the processor, as described in Section 9.7, “Software Initialization for Real-Address Mode Operation.” Before the
processor can be switched to protected mode, the software initialization code must load a minimum number of
protected mode data structures and code modules into memory to support reliable operation of the processor in
protected mode. These data structures include the following:
•
•
•
•
•
•
•
A IDT.
A GDT.
A TSS.
(Optional) An LDT.
If paging is to be used, at least one page directory and one page table.
A code segment that contains the code to be executed when the processor switches to protected mode.
One or more code modules that contain the necessary interrupt and exception handlers.
Software initialization code must also initialize the following system registers before the processor can be switched
to protected mode:
•
•
The GDTR.
•
•
Control registers CR1 through CR4.
(Optional.) The IDTR. This register can also be initialized immediately after switching to protected mode, prior
to enabling interrupts.
(Pentium 4, Intel Xeon, and P6 family processors only.) The memory type range registers (MTRRs).
With these data structures, code modules, and system registers initialized, the processor can be switched to
protected mode by loading control register CR0 with a value that sets the PE flag (bit 0).
9.8.1
Protected-Mode System Data Structures
The contents of the protected-mode system data structures loaded into memory during software initialization,
depend largely on the type of memory management the protected-mode operating-system or executive is going to
support: flat, flat with paging, segmented, or segmented with paging.
Vol. 3A 9-9
PROCESSOR MANAGEMENT AND INITIALIZATION
To implement a flat memory model without paging, software initialization code must at a minimum load a GDT with
one code and one data-segment descriptor. A null descriptor in the first GDT entry is also required. The stack can
be placed in a normal read/write data segment, so no dedicated descriptor for the stack is required. A flat memory
model with paging also requires a page directory and at least one page table (unless all pages are 4 MBytes in
which case only a page directory is required). See Section 9.8.3, “Initializing Paging.”
Before the GDT can be used, the base address and limit for the GDT must be loaded into the GDTR register using
an LGDT instruction.
A multi-segmented model may require additional segments for the operating system, as well as segments and LDTs
for each application program. LDTs require segment descriptors in the GDT. Some operating systems allocate new
segments and LDTs as they are needed. This provides maximum flexibility for handling a dynamic programming
environment. However, many operating systems use a single LDT for all tasks, allocating GDT entries in advance.
An embedded system, such as a process controller, might pre-allocate a fixed number of segments and LDTs for a
fixed number of application programs. This would be a simple and efficient way to structure the software environment of a real-time system.
9.8.2
Initializing Protected-Mode Exceptions and Interrupts
Software initialization code must at a minimum load a protected-mode IDT with gate descriptor for each exception
vector that the processor can generate. If interrupt or trap gates are used, the gate descriptors can all point to the
same code segment, which contains the necessary exception handlers. If task gates are used, one TSS and accompanying code, data, and task segments are required for each exception handler called with a task gate.
If hardware allows interrupts to be generated, gate descriptors must be provided in the IDT for one or more interrupt handlers.
Before the IDT can be used, the base address and limit for the IDT must be loaded into the IDTR register using an
LIDT instruction. This operation is typically carried out immediately after switching to protected mode.
9.8.3
Initializing Paging
Paging is controlled by the PG flag in control register CR0. When this flag is clear (its state following a hardware
reset), the paging mechanism is turned off; when it is set, paging is enabled. Before setting the PG flag, the
following data structures and registers must be initialized:
•
Software must load at least one page directory and one page table into physical memory. The page table can
be eliminated if the page directory contains a directory entry pointing to itself (here, the page directory and
page table reside in the same page), or if only 4-MByte pages are used.
•
Control register CR3 (also called the PDBR register) is loaded with the physical base address of the page
directory.
•
(Optional) Software may provide one set of code and data descriptors in the GDT or in an LDT for supervisor
mode and another set for user mode.
With this paging initialization complete, paging is enabled and the processor is switched to protected mode at the
same time by loading control register CR0 with an image in which the PG and PE flags are set. (Paging cannot be
enabled before the processor is switched to protected mode.)
9.8.4
Initializing Multitasking
If the multitasking mechanism is not going to be used and changes between privilege levels are not allowed, it is
not necessary load a TSS into memory or to initialize the task register.
If the multitasking mechanism is going to be used and/or changes between privilege levels are allowed, software
initialization code must load at least one TSS and an accompanying TSS descriptor. (A TSS is required to change
privilege levels because pointers to the privileged-level 0, 1, and 2 stack segments and the stack pointers for these
stacks are obtained from the TSS.) TSS descriptors must not be marked as busy when they are created; they
should be marked busy by the processor only as a side-effect of performing a task switch. As with descriptors for
LDTs, TSS descriptors reside in the GDT.
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PROCESSOR MANAGEMENT AND INITIALIZATION
After the processor has switched to protected mode, the LTR instruction can be used to load a segment selector for
a TSS descriptor into the task register. This instruction marks the TSS descriptor as busy, but does not perform a
task switch. The processor can, however, use the TSS to locate pointers to privilege-level 0, 1, and 2 stacks. The
segment selector for the TSS must be loaded before software performs its first task switch in protected mode,
because a task switch copies the current task state into the TSS.
After the LTR instruction has been executed, further operations on the task register are performed by task
switching. As with other segments and LDTs, TSSs and TSS descriptors can be either pre-allocated or allocated as
needed.
9.8.5
Initializing IA-32e Mode
On Intel 64 processors, the IA32_EFER MSR is cleared on system reset. The operating system must be in protected
mode with paging enabled before attempting to initialize IA-32e mode. IA-32e mode operation also requires physical-address extensions with four levels of enhanced paging structures (see Section 4.5, “IA-32e Paging”).
Operating systems should follow this sequence to initialize IA-32e mode:
1. Starting from protected mode, disable paging by setting CR0.PG = 0. Use the MOV CR0 instruction to disable
paging (the instruction must be located in an identity-mapped page).
2. Enable physical-address extensions (PAE) by setting CR4.PAE = 1. Failure to enable PAE will result in a #GP
fault when an attempt is made to initialize IA-32e mode.
3. Load CR3 with the physical base address of the Level 4 page map table (PML4).
4. Enable IA-32e mode by setting IA32_EFER.LME = 1.
5. Enable paging by setting CR0.PG = 1. This causes the processor to set the IA32_EFER.LMA bit to 1. The MOV
CR0 instruction that enables paging and the following instructions must be located in an identity-mapped page
(until such time that a branch to non-identity mapped pages can be effected).
64-bit mode paging tables must be located in the first 4 GBytes of physical-address space prior to activating IA-32e
mode. This is necessary because the MOV CR3 instruction used to initialize the page-directory base must be
executed in legacy mode prior to activating IA-32e mode (setting CR0.PG = 1 to enable paging). Because MOV CR3
is executed in protected mode, only the lower 32 bits of the register are written, limiting the table location to the
low 4 GBytes of memory. Software can relocate the page tables anywhere in physical memory after IA-32e mode
is activated.
The processor performs 64-bit mode consistency checks whenever software attempts to modify any of the enable
bits directly involved in activating IA-32e mode (IA32_EFER.LME, CR0.PG, and CR4.PAE). It will generate a general
protection fault (#GP) if consistency checks fail. 64-bit mode consistency checks ensure that the processor does
not enter an undefined mode or state with unpredictable behavior.
64-bit mode consistency checks fail in the following circumstances:
•
•
An attempt is made to enable or disable IA-32e mode while paging is enabled.
•
•
•
IA-32e mode is active and an attempt is made to disable physical-address extensions (PAE).
IA-32e mode is enabled and an attempt is made to enable paging prior to enabling physical-address extensions
(PAE).
If the current CS has the L-bit set on an attempt to activate IA-32e mode.
If the TR contains a 16-bit TSS.
9.8.5.1
IA-32e Mode System Data Structures
After activating IA-32e mode, the system-descriptor-table registers (GDTR, LDTR, IDTR, TR) continue to reference
legacy protected-mode descriptor tables. Tables referenced by the descriptors all reside in the lower 4 GBytes of
linear-address space. After activating IA-32e mode, 64-bit operating-systems should use the LGDT, LLDT, LIDT,
and LTR instructions to load the system-descriptor-table registers with references to 64-bit descriptor tables.
Vol. 3A 9-11
PROCESSOR MANAGEMENT AND INITIALIZATION
9.8.5.2
IA-32e Mode Interrupts and Exceptions
Software must not allow exceptions or interrupts to occur between the time IA-32e mode is activated and the
update of the interrupt-descriptor-table register (IDTR) that establishes references to a 64-bit interrupt-descriptor
table (IDT). This is because the IDT remains in legacy form immediately after IA-32e mode is activated.
If an interrupt or exception occurs prior to updating the IDTR, a legacy 32-bit interrupt gate will be referenced and
interpreted as a 64-bit interrupt gate with unpredictable results. External interrupts can be disabled by using the
CLI instruction.
Non-maskable interrupts (NMI) must be disabled using external hardware.
9.8.5.3
64-bit Mode and Compatibility Mode Operation
IA-32e mode uses two code segment-descriptor bits (CS.L and CS.D, see Figure 3-8) to control the operating modes
after IA-32e mode is initialized. If CS.L = 1 and CS.D = 0, the processor is running in 64-bit mode. With this
encoding, the default operand size is 32 bits and default address size is 64 bits. Using instruction prefixes, operand
size can be changed to 64 bits or 16 bits; address size can be changed to 32 bits.
When IA-32e mode is active and CS.L = 0, the processor operates in compatibility mode. In this mode, CS.D
controls default operand and address sizes exactly as it does in the IA-32 architecture. Setting CS.D = 1 specifies
default operand and address size as 32 bits. Clearing CS.D to 0 specifies default operand and address size as 16
bits (the CS.L = 1, CS.D = 1 bit combination is reserved).
Compatibility mode execution is selected on a code-segment basis. This mode allows legacy applications to coexist
with 64-bit applications running in 64-bit mode. An operating system running in IA-32e mode can execute existing
16-bit and 32-bit applications by clearing their code-segment descriptor’s CS.L bit to 0.
In compatibility mode, the following system-level mechanisms continue to operate using the IA-32e-mode architectural semantics:
•
•
•
Linear-to-physical address translation uses the 64-bit mode extended page-translation mechanism.
Interrupts and exceptions are handled using the 64-bit mode mechanisms.
System calls (calls through call gates and SYSENTER/SYSEXIT) are handled using the IA-32e mode
mechanisms.
9.8.5.4
Switching Out of IA-32e Mode Operation
To return from IA-32e mode to paged-protected mode operation. Operating systems must use the following
sequence:
1. Switch to compatibility mode.
2. Deactivate IA-32e mode by clearing CR0.PG = 0. This causes the processor to set IA32_EFER.LMA = 0. The
MOV CR0 instruction used to disable paging and subsequent instructions must be located in an identity-mapped
page.
3. Load CR3 with the physical base address of the legacy page-table-directory base address.
4. Disable IA-32e mode by setting IA32_EFER.LME = 0.
5. Enable legacy paged-protected mode by setting CR0.PG = 1
6. A branch instruction must follow the MOV CR0 that enables paging. Both the MOV CR0 and the branch
instruction must be located in an identity-mapped page.
Registers only available in 64-bit mode (R8-R15 and XMM8-XMM15) are preserved across transitions from 64-bit
mode into compatibility mode then back into 64-bit mode. However, values of R8-R15 and XMM8-XMM15 are undefined after transitions from 64-bit mode through compatibility mode to legacy or real mode and then back through
compatibility mode to 64-bit mode.
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9.9
MODE SWITCHING
To use the processor in protected mode after hardware or software reset, a mode switch must be performed from
real-address mode. Once in protected mode, software generally does not need to return to real-address mode. To
run software written to run in real-address mode (8086 mode), it is generally more convenient to run the software
in virtual-8086 mode, than to switch back to real-address mode.
9.9.1
Switching to Protected Mode
Before switching to protected mode from real mode, a minimum set of system data structures and code modules
must be loaded into memory, as described in Section 9.8, “Software Initialization for Protected-Mode Operation.”
Once these tables are created, software initialization code can switch into protected mode.
Protected mode is entered by executing a MOV CR0 instruction that sets the PE flag in the CR0 register. (In the
same instruction, the PG flag in register CR0 can be set to enable paging.) Execution in protected mode begins with
a CPL of 0.
Intel 64 and IA-32 processors have slightly different requirements for switching to protected mode. To insure
upwards and downwards code compatibility with Intel 64 and IA-32 processors, we recommend that you follow
these steps:
1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI interrupts can be disabled
with external circuitry. (Software must guarantee that no exceptions or interrupts are generated during the
mode switching operation.)
2. Execute the LGDT instruction to load the GDTR register with the base address of the GDT.
3. Execute a MOV CR0 instruction that sets the PE flag (and optionally the PG flag) in control register CR0.
4. Immediately following the MOV CR0 instruction, execute a far JMP or far CALL instruction. (This operation is
typically a far jump or call to the next instruction in the instruction stream.)
5. The JMP or CALL instruction immediately after the MOV CR0 instruction changes the flow of execution and
serializes the processor.
6. If paging is enabled, the code for the MOV CR0 instruction and the JMP or CALL instruction must come from a
page that is identity mapped (that is, the linear address before the jump is the same as the physical address
after paging and protected mode is enabled). The target instruction for the JMP or CALL instruction does not
need to be identity mapped.
7. If a local descriptor table is going to be used, execute the LLDT instruction to load the segment selector for the
LDT in the LDTR register.
8. Execute the LTR instruction to load the task register with a segment selector to the initial protected-mode task
or to a writable area of memory that can be used to store TSS information on a task switch.
9. After entering protected mode, the segment registers continue to hold the contents they had in real-address
mode. The JMP or CALL instruction in step 4 resets the CS register. Perform one of the following operations to
update the contents of the remaining segment registers.
— Reload segment registers DS, SS, ES, FS, and GS. If the ES, FS, and/or GS registers are not going to be
used, load them with a null selector.
— Perform a JMP or CALL instruction to a new task, which automatically resets the values of the segment
registers and branches to a new code segment.
10. Execute the LIDT instruction to load the IDTR register with the address and limit of the protected-mode IDT.
11. Execute the STI instruction to enable maskable hardware interrupts and perform the necessary hardware
operation to enable NMI interrupts.
Random failures can occur if other instructions exist between steps 3 and 4 above. Failures will be readily seen in
some situations, such as when instructions that reference memory are inserted between steps 3 and 4 while in
system management mode.
Vol. 3A 9-13
PROCESSOR MANAGEMENT AND INITIALIZATION
9.9.2
Switching Back to Real-Address Mode
The processor switches from protected mode back to real-address mode if software clears the PE bit in the CR0
register with a MOV CR0 instruction. A procedure that re-enters real-address mode should perform the following
steps:
1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI interrupts can be disabled
with external circuitry.
2. If paging is enabled, perform the following operations:
— Transfer program control to linear addresses that are identity mapped to physical addresses (that is, linear
addresses equal physical addresses).
— Insure that the GDT and IDT are in identity mapped pages.
— Clear the PG bit in the CR0 register.
— Move 0H into the CR3 register to flush the TLB.
3. Transfer program control to a readable segment that has a limit of 64 KBytes (FFFFH). This operation loads the
CS register with the segment limit required in real-address mode.
4. Load segment registers SS, DS, ES, FS, and GS with a selector for a descriptor containing the following values,
which are appropriate for real-address mode:
— Limit = 64 KBytes (0FFFFH)
— Byte granular (G = 0)
— Expand up (E = 0)
— Writable (W = 1)
— Present (P = 1)
— Base = any value
The segment registers must be loaded with non-null segment selectors or the segment registers will be
unusable in real-address mode. Note that if the segment registers are not reloaded, execution continues using
the descriptor attributes loaded during protected mode.
5. Execute an LIDT instruction to point to a real-address mode interrupt table that is within the 1-MByte realaddress mode address range.
6. Clear the PE flag in the CR0 register to switch to real-address mode.
7. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction
queue and loads the appropriate base-address value in the CS register.
8. Load the SS, DS, ES, FS, and GS registers as needed by the real-address mode code. If any of the registers are
not going to be used in real-address mode, write 0s to them.
9. Execute the STI instruction to enable maskable hardware interrupts and perform the necessary hardware
operation to enable NMI interrupts.
NOTE
All the code that is executed in steps 1 through 9 must be in a single page and the linear addresses
in that page must be identity mapped to physical addresses.
9.10
INITIALIZATION AND MODE SWITCHING EXAMPLE
This section provides an initialization and mode switching example that can be incorporated into an application.
This code was originally written to initialize the Intel386 processor, but it will execute successfully on the Pentium
4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The code in this example is intended to reside in EPROM
and to run following a hardware reset of the processor. The function of the code is to do the following:
•
Establish a basic real-address mode operating environment.
9-14 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
•
•
Load the necessary protected-mode system data structures into RAM.
•
Switch the processor to protected mode.
Load the system registers with the necessary pointers to the data structures and the appropriate flag settings
for protected-mode operation.
Figure 9-3 shows the physical memory layout for the processor following a hardware reset and the starting point
of this example. The EPROM that contains the initialization code resides at the upper end of the processor’s physical
memory address range, starting at address FFFFFFFFH and going down from there. The address of the first instruction to be executed is at FFFFFFF0H, the default starting address for the processor following a hardware reset.
The main steps carried out in this example are summarized in Table 9-5. The source listing for the example (with
the filename STARTUP.ASM) is given in Example 9-1. The line numbers given in Table 9-5 refer to the source listing.
The following are some additional notes concerning this example:
•
When the processor is switched into protected mode, the original code segment base-address value of
FFFF0000H (located in the hidden part of the CS register) is retained and execution continues from the current
offset in the EIP register. The processor will thus continue to execute code in the EPROM until a far jump or call
is made to a new code segment, at which time, the base address in the CS register will be changed.
•
Maskable hardware interrupts are disabled after a hardware reset and should remain disabled until the
necessary interrupt handlers have been installed. The NMI interrupt is not disabled following a reset. The NMI#
pin must thus be inhibited from being asserted until an NMI handler has been loaded and made available to the
processor.
•
The use of a temporary GDT allows simple transfer of tables from the EPROM to anywhere in the RAM area. A
GDT entry is constructed with its base pointing to address 0 and a limit of 4 GBytes. When the DS and ES
registers are loaded with this descriptor, the temporary GDT is no longer needed and can be replaced by the
application GDT.
•
This code loads one TSS and no LDTs. If more TSSs exist in the application, they must be loaded into RAM. If
there are LDTs they may be loaded as well.
After Reset
[CS.BASE+EIP]
FFFF FFFFH
FFFF FFF0H
64K EPROM
EIP = 0000 FFF0H
CS.BASE = FFFF 0000H
DS.BASE = 0H
ES.BASE = 0H
SS.BASE = 0H
ESP = 0H
[SP, DS, SS, ES]
FFFF 0000H
0
Figure 9-3. Processor State After Reset
Vol. 3A 9-15
PROCESSOR MANAGEMENT AND INITIALIZATION
Table 9-5. Main Initialization Steps in STARTUP.ASM Source Listing
STARTUP.ASM Line
Numbers
Description
From
To
157
157
Jump (short) to the entry code in the EPROM
162
169
Construct a temporary GDT in RAM with one entry:
0 - null
1 - R/W data segment, base = 0, limit = 4 GBytes
171
172
Load the GDTR to point to the temporary GDT
174
177
Load CR0 with PE flag set to switch to protected mode
179
181
Jump near to clear real mode instruction queue
184
186
Load DS, ES registers with GDT[1] descriptor, so both point to the entire physical memory space
188
195
Perform specific board initialization that is imposed by the new protected mode
196
218
Copy the application's GDT from ROM into RAM
220
238
Copy the application's IDT from ROM into RAM
241
243
Load application's GDTR
244
245
Load application's IDTR
247
261
Copy the application's TSS from ROM into RAM
263
267
Update TSS descriptor and other aliases in GDT (GDT alias or IDT alias)
277
277
Load the task register (without task switch) using LTR instruction
282
286
Load SS, ESP with the value found in the application's TSS
287
287
Push EFLAGS value found in the application's TSS
288
288
Push CS value found in the application's TSS
289
289
Push EIP value found in the application's TSS
290
293
Load DS, ES with the value found in the application's TSS
296
296
Perform IRET; pop the above values and enter the application code
9.10.1
Assembler Usage
In this example, the Intel assembler ASM386 and build tools BLD386 are used to assemble and build the initialization code module. The following assumptions are used when using the Intel ASM386 and BLD386 tools.
•
The ASM386 will generate the right operand size opcodes according to the code-segment attribute. The
attribute is assigned either by the ASM386 invocation controls or in the code-segment definition.
•
If a code segment that is going to run in real-address mode is defined, it must be set to a USE 16 attribute. If
a 32-bit operand is used in an instruction in this code segment (for example, MOV EAX, EBX), the assembler
automatically generates an operand prefix for the instruction that forces the processor to execute a 32-bit
operation, even though its default code-segment attribute is 16-bit.
•
Intel's ASM386 assembler allows specific use of the 16- or 32-bit instructions, for example, LGDTW, LGDTD,
IRETD. If the generic instruction LGDT is used, the default- segment attribute will be used to generate the right
opcode.
9.10.2
STARTUP.ASM Listing
Example 9-1 provides high-level sample code designed to move the processor into protected mode. This listing
does not include any opcode and offset information.
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PROCESSOR MANAGEMENT AND INITIALIZATION
Example 9-1. STARTUP.ASM
MS-DOS* 5.0(045-N) 386(TM) MACRO ASSEMBLER STARTUP
09:44:51 08/19/92 PAGE 1
MS-DOS 5.0(045-N) 386(TM) MACRO ASSEMBLER V4.0, ASSEMBLY OF MODULE STARTUP
OBJECT MODULE PLACED IN startup.obj
ASSEMBLER INVOKED BY: f:\386tools\ASM386.EXE startup.a58 pw (132 )
LINE
1
2
3
4
5
6
7
8
9
10
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SOURCE
NAME
STARTUP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;
ASSUMPTIONS:
;
;
1. The bottom 64K of memory is ram, and can be used for
;
scratch space by this module.
;
;
2. The system has sufficient free usable ram to copy the
;
initial GDT, IDT, and TSS
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; configuration data - must match with build definition
CS_BASE
EQU
0FFFF0000H
; CS_BASE is the linear address of the segment STARTUP_CODE
; - this is specified in the build language file
RAM_START
;
;
;
;
;
;
;
EQU
400H
RAM_START is the start of free, usable ram in the linear
memory space.
The GDT, IDT, and initial TSS will be
copied above this space, and a small data segment will be
discarded at this linear address.
The 32-bit word at
RAM_START will contain the linear address of the first
free byte above the copied tables - this may be useful if
a memory manager is used.
TSS_INDEX
EQU
10
; TSS_INDEX is the index of the
; run after startup
TSS of the
first task to
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ------------------------- STRUCTURES and EQU --------------; structures for system data
; TSS structure
TASK_STATE STRUC
link
DW ?
Vol. 3A 9-17
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46
47
48
49
50
51
52
53
54
55
56
57
58
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93
94
95
96
97
98
99
link_h
DW ?
ESP0
DD ?
SS0
DW ?
SS0_h
DW ?
ESP1
DD ?
SS1
DW ?
SS1_h
DW ?
ESP2
DD ?
SS2
DW ?
SS2_h
DW ?
CR3_reg DD ?
EIP_reg DD ?
EFLAGS_regDD ?
EAX_reg DD ?
ECX_reg DD ?
EDX_reg DD ?
EBX_reg DD ?
ESP_reg DD ?
EBP_reg DD ?
ESI_reg DD ?
EDI_reg DD ?
ES_reg
DW ?
ES_h
DW ?
CS_reg
DW ?
CS_h
DW ?
SS_reg
DW ?
SS_h
DW ?
DS_reg
DW ?
DS_h
DW ?
FS_reg
DW ?
FS_h
DW ?
GS_reg
DW ?
GS_h
DW ?
LDT_reg DW ?
LDT_h
DW ?
TRAP_reg DW ?
IO_map_baseDW ?
TASK_STATE ENDS
; basic structure of a descriptor
DESC
STRUC
lim_0_15 DW ?
bas_0_15 DW ?
bas_16_23 DB ?
access
DB ?
gran
DB ?
bas_24_31 DB ?
DESC
ENDS
; structure for use with LGDT and LIDT instructions
TABLE_REG
STRUC
table_lim DW ?
table_linearDD ?
TABLE_REG
ENDS
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100
101
102
103
104
105
106
107
108
109
110
111
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117
118
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147
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149
150
151
152
153
; offset of GDT and IDT descriptors in builder generated GDT
GDT_DESC_OFF
EQU 1*SIZE(DESC)
IDT_DESC_OFF
EQU 2*SIZE(DESC)
; equates for building temporary GDT in RAM
LINEAR_SEL
EQU
1*SIZE (DESC)
LINEAR_PROTO_LO
EQU
00000FFFFH ; LINEAR_ALIAS
LINEAR_PROTO_HI
EQU
000CF9200H
; Protection Enable Bit in CR0
PE_BIT EQU 1B
; -----------------------------------------------------------; ------------------------- DATA SEGMENT---------------------; Initially, this data segment starts at linear 0, according
; to the processor’s power-up state.
STARTUP_DATA
SEGMENT RW
free_mem_linear_base
LABEL
DWORD
TEMP_GDT
LABEL
BYTE ; must be first in segment
TEMP_GDT_NULL_DESC
DESC
<>
TEMP_GDT_LINEAR_DESC DESC
<>
; scratch areas for LGDT and
TEMP_GDT_SCRATCH TABLE_REG
APP_GDT_RAM
TABLE_REG
APP_IDT_RAM
TABLE_REG
; align end_data
fill
DW
?
LIDT instructions
<>
<>
<>
; last thing in this segment - should be on a dword boundary
end_data
LABEL
BYTE
STARTUP_DATA
ENDS
; ------------------------------------------------------------
; ------------------------- CODE SEGMENT---------------------STARTUP_CODE SEGMENT ER PUBLIC USE16
; filled in by builder
PUBLIC GDT_EPROM
GDT_EPROM
TABLE_REG
<>
; filled in by builder
PUBLIC IDT_EPROM
IDT_EPROM
TABLE_REG
<>
; entry point into startup code - the bootstrap will vector
; here with a near JMP generated by the builder.
This
Vol. 3A 9-19
PROCESSOR MANAGEMENT AND INITIALIZATION
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
; label must be in the top 64K of linear memory.
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
; clear prefetch queue
JMP
CLEAR_LABEL
CLEAR_LABEL:
PUBLIC
STARTUP:
STARTUP
; DS,ES address the bottom 64K of flat linear memory
ASSUME DS:STARTUP_DATA, ES:STARTUP_DATA
; See Figure 9-4
; load GDTR with temporary GDT
LEA
EBX,TEMP_GDT ; build the TEMP_GDT in low ram,
MOV
DWORD PTR [EBX],0
; where we can address
MOV
DWORD PTR [EBX]+4,0
MOV
DWORD PTR [EBX]+8, LINEAR_PROTO_LO
MOV
DWORD PTR [EBX]+12, LINEAR_PROTO_HI
MOV
TEMP_GDT_scratch.table_linear,EBX
MOV
TEMP_GDT_scratch.table_lim,15
DB 66H; execute a 32 bit LGDT
LGDT
TEMP_GDT_scratch
; enter protected mode
MOV
EBX,CR0
OR
EBX,PE_BIT
MOV
CR0,EBX
; make DS and ES address 4G of linear memory
MOV
CX,LINEAR_SEL
MOV
DS,CX
MOV
ES,CX
; do board specific initialization
;
;
; ......
;
9-20 Vol. 3A
; See Figure 9-5
; copy EPROM GDT to ram at:
;
RAM_START + size (STARTUP_DATA)
MOV
EAX,RAM_START
ADD
EAX,OFFSET (end_data)
MOV
EBX,RAM_START
MOV
ECX, CS_BASE
ADD
ECX, OFFSET (GDT_EPROM)
MOV
ESI, [ECX].table_linear
MOV
EDI,EAX
MOVZX
ECX, [ECX].table_lim
MOV
APP_GDT_ram[EBX].table_lim,CX
PROCESSOR MANAGEMENT AND INITIALIZATION
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
INC
MOV
MOV
ADD
REP MOVS
; fixup
MOV
MOV
ROR
MOV
MOV
ECX
EDX,EAX
APP_GDT_ram[EBX].table_linear,EAX
EAX,ECX
BYTE PTR ES:[EDI],BYTE PTR DS:[ESI]
GDT base in descriptor
ECX,EDX
[EDX].bas_0_15+GDT_DESC_OFF,CX
ECX,16
[EDX].bas_16_23+GDT_DESC_OFF,CL
[EDX].bas_24_31+GDT_DESC_OFF,CH
; copy EPROM IDT to ram at:
; RAM_START+size(STARTUP_DATA)+SIZE (EPROM GDT)
MOV
ECX, CS_BASE
ADD
ECX, OFFSET (IDT_EPROM)
MOV
ESI, [ECX].table_linear
MOV
EDI,EAX
MOVZX
ECX, [ECX].table_lim
MOV
APP_IDT_ram[EBX].table_lim,CX
INC
ECX
MOV
APP_IDT_ram[EBX].table_linear,EAX
MOV
EBX,EAX
ADD
EAX,ECX
REP MOVS
BYTE PTR ES:[EDI],BYTE PTR DS:[ESI]
MOV
ROR
MOV
MOV
; fixup IDT pointer in GDT
[EDX].bas_0_15+IDT_DESC_OFF,BX
EBX,16
[EDX].bas_16_23+IDT_DESC_OFF,BL
[EDX].bas_24_31+IDT_DESC_OFF,BH
LIDT
; load GDTR and IDTR
EBX,RAM_START
DB
66H
; execute a 32 bit LGDT
APP_GDT_ram[EBX]
DB
66H
; execute a 32 bit LIDT
APP_IDT_ram[EBX]
MOV
MOV
MOV
MOV
MOV
MOV
ROL
MOV
MOV
LSL
INC
MOV
ADD
; move the TSS
EDI,EAX
EBX,TSS_INDEX*SIZE(DESC)
ECX,GDT_DESC_OFF ;build linear address for TSS
GS,CX
DH,GS:[EBX].bas_24_31
DL,GS:[EBX].bas_16_23
EDX,16
DX,GS:[EBX].bas_0_15
ESI,EDX
ECX,EBX
ECX
EDX,EAX
EAX,ECX
MOV
LGDT
Vol. 3A 9-21
PROCESSOR MANAGEMENT AND INITIALIZATION
261
REP MOVS
BYTE PTR ES:[EDI],BYTE PTR DS:[ESI]
262
263
; fixup TSS pointer
264
MOV
GS:[EBX].bas_0_15,DX
265
ROL
EDX,16
266
MOV
GS:[EBX].bas_24_31,DH
267
MOV
GS:[EBX].bas_16_23,DL
268
ROL
EDX,16
269
;save start of free ram at linear location RAMSTART
270
MOV
free_mem_linear_base+RAM_START,EAX
271
272
;assume no LDT used in the initial task - if necessary,
273
;code to move the LDT could be added, and should resemble
274
;that used to move the TSS
275
276
; load task register
277
LTR
BX
; No task switch, only descriptor loading
278
; See Figure 9-6
279
; load minimal set of registers necessary to simulate task
280
; switch
281
282
283
MOV
AX,[EDX].SS_reg
; start loading registers
284
MOV
EDI,[EDX].ESP_reg
285
MOV
SS,AX
286
MOV
ESP,EDI
; stack now valid
287
PUSH
DWORD PTR [EDX].EFLAGS_reg
288
PUSH
DWORD PTR [EDX].CS_reg
289
PUSH
DWORD PTR [EDX].EIP_reg
290
MOV
AX,[EDX].DS_reg
291
MOV
BX,[EDX].ES_reg
292
MOV
DS,AX
; DS and ES no longer linear memory
293
MOV
ES,BX
294
295
; simulate far jump to initial task
296
IRETD
297
298 STARTUP_CODE ENDS
*** WARNING #377 IN 298, (PASS 2) SEGMENT CONTAINS PRIVILEGED INSTRUCTION(S)
299
300 END STARTUP, DS:STARTUP_DATA, SS:STARTUP_DATA
301
302
ASSEMBLY COMPLETE,
9-22 Vol. 3A
1 WARNING,
NO ERRORS.
PROCESSOR MANAGEMENT AND INITIALIZATION
FFFF FFFFH
START: [CS.BASE+EIP]
FFFF 0000H
• Jump near start
• Construct TEMP_GDT
• LGDT
• Move to protected mode
DS, ES = GDT[1]
4 GB
Base
Limit
GDT [1]
GDT [0]
Base=0, Limit=4G
0
GDT_SCRATCH
TEMP_GDT
Figure 9-4. Constructing Temporary GDT and Switching to Protected Mode (Lines 162-172 of List File)
Vol. 3A 9-23
PROCESSOR MANAGEMENT AND INITIALIZATION
FFFF FFFFH
TSS
IDT
GDT
• Move the GDT, IDT, TSS
from ROM to RAM
• Fix Aliases
• LTR
TSS RAM
IDT RAM
GDT RAM
RAM_START
0
Figure 9-5. Moving the GDT, IDT, and TSS from ROM to RAM (Lines 196-261 of List File)
9-24 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
SS = TSS.SS
ESP = TSS.ESP
PUSH TSS.EFLAG
PUSH TSS.CS
PUSH TSS.EIP
ES = TSS.ES
DS = TSS.DS
IRET
•
•
EIP
EFLAGS
•
•
•
ESP
•
ES
CS
SS
DS
GDT
IDT Alias
GDT Alias
0
TSS RAM
IDT RAM
GDT RAM
RAM_START
Figure 9-6. Task Switching (Lines 282-296 of List File)
9.10.3
MAIN.ASM Source Code
The file MAIN.ASM shown in Example 9-2 defines the data and stack segments for this application and can be
substituted with the main module task written in a high-level language that is invoked by the IRET instruction
executed by STARTUP.ASM.
Example 9-2. MAIN.ASM
NAME
main_module
data
SEGMENT RW
dw 1000 dup(?)
DATA
ENDS
stack stackseg 800
CODE SEGMENT ER use32 PUBLIC
main_start:
nop
nop
nop
CODE ENDS
END main_start, ds:data, ss:stack
9.10.4
Supporting Files
The batch file shown in Example 9-3 can be used to assemble the source code files STARTUP.ASM and MAIN.ASM
and build the final application.
Vol. 3A 9-25
PROCESSOR MANAGEMENT AND INITIALIZATION
Example 9-3. Batch File to Assemble and Build the Application
ASM386 STARTUP.ASM
ASM386 MAIN.ASM
BLD386 STARTUP.OBJ, MAIN.OBJ buildfile(EPROM.BLD) bootstrap(STARTUP) Bootload
BLD386 performs several operations in this example:
It allocates physical memory location to segments and tables.
It generates tables using the build file and the input files.
It links object files and resolves references.
It generates a boot-loadable file to be programmed into the EPROM.
Example 9-4 shows the build file used as an input to BLD386 to perform the above functions.
Example 9-4. Build File
INIT_BLD_EXAMPLE;
SEGMENT
,
;
*SEGMENTS(DPL = 0)
startup.startup_code(BASE = 0FFFF0000H)
TASK
BOOT_TASK(OBJECT = startup, INITIAL,DPL = 0,
NOT INTENABLED)
PROTECTED_MODE_TASK(OBJECT = main_module,DPL = 0,
NOT INTENABLED)
,
;
TABLE
GDT (
LOCATION = GDT_EPROM
,
ENTRY = (
10:
PROTECTED_MODE_TASK
,
startup.startup_code
,
startup.startup_data
,
main_module.data
,
main_module.code
,
main_module.stack
)
),
IDT (
LOCATION = IDT_EPROM
);
MEMORY
(
,
,
,
RESERVE = (0..3FFFH
-- Area for the GDT, IDT, TSS copied from ROM
60000H..0FFFEFFFFH)
RANGE = (ROM_AREA = ROM (0FFFF0000H..0FFFFFFFFH))
-- Eprom size 64K
RANGE = (RAM_AREA = RAM (4000H..05FFFFH))
9-26 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
);
END
Table 9-6 shows the relationship of each build item with an ASM source file.
Table 9-6. Relationship Between BLD Item and ASM Source File
Item
ASM386 and Startup.A58
BLD386 Controls
and BLD file
Effect
Bootstrap
public startup
startup:
bootstrap
start(startup)
Near jump at 0FFFFFFF0H to
start.
GDT location
public GDT_EPROM
GDT_EPROM TABLE_REG <>
TABLE
GDT(location = GDT_EPROM)
The location of the GDT will be
programmed into the
GDT_EPROM location.
IDT location
public IDT_EPROM
IDT_EPROM TABLE_REG <>
TABLE
IDT(location = IDT_EPROM
The location of the IDT will be
programmed into the
IDT_EPROM location.
RAM start
RAM_START equ 400H
memory (reserve = (0..3FFFH))
RAM_START is used as the ram
destination for moving the
tables. It must be excluded from
the application's segment area.
Location of the
application TSS in
the GDT
TSS_INDEX EQU 10
TABLE GDT(
ENTRY = (10: PROTECTED_MODE_
TASK))
Put the descriptor of the
application TSS in GDT entry 10.
EPROM size and
location
size and location of the initialization
code
SEGMENT startup.code (base =
0FFFF0000H) ...memory (RANGE(
ROM_AREA = ROM(x..y))
Initialization code size must be
less than 64K and resides at
upper most 64K of the 4-GByte
memory space.
9.11
MICROCODE UPDATE FACILITIES
The P6 family and later processors have the capability to correct errata by loading an Intel-supplied data block into
the processor. The data block is called a microcode update. This section describes the mechanisms the BIOS needs
to provide in order to use this feature during system initialization. It also describes a specification that permits the
incorporation of future updates into a system BIOS.
Intel considers the release of a microcode update for a silicon revision to be the equivalent of a processor stepping
and completes a full-stepping level validation for releases of microcode updates.
A microcode update is used to correct errata in the processor. The BIOS, which has an update loader, is responsible
for loading the update on processors during system initialization (Figure 9-7). There are two steps to this process:
the first is to incorporate the necessary update data blocks into the BIOS; the second is to load update data blocks
into the processor.
Vol. 3A 9-27
PROCESSOR MANAGEMENT AND INITIALIZATION
Update
Loader
New Update
Update
Blocks
CPU
BIOS
Figure 9-7. Applying Microcode Updates
9.11.1
Microcode Update
A microcode update consists of an Intel-supplied binary that contains a descriptive header and data. No executable
code resides within the update. Each microcode update is tailored for a specific list of processor signatures. A
mismatch of the processor’s signature with the signature contained in the update will result in a failure to load. A
processor signature includes the extended family, extended model, type, family, model, and stepping of the
processor (starting with processor family 0fH, model 03H, a given microcode update may be associated with one of
multiple processor signatures; see Section 9.11.2 for detail).
Microcode updates are composed of a multi-byte header, followed by encrypted data and then by an optional
extended signature table. Table 9-7 provides a definition of the fields; Table 9-8 shows the format of an update.
The header is 48 bytes. The first 4 bytes of the header contain the header version. The update header and its
reserved fields are interpreted by software based upon the header version. An encoding scheme guards against
tampering and provides a means for determining the authenticity of any given update. For microcode updates with
a data size field equal to 00000000H, the size of the microcode update is 2048 bytes. The first 48 bytes contain the
microcode update header. The remaining 2000 bytes contain encrypted data.
For microcode updates with a data size not equal to 00000000H, the total size field specifies the size of the microcode update. The first 48 bytes contain the microcode update header. The second part of the microcode update is
the encrypted data. The data size field of the microcode update header specifies the encrypted data size, its value
must be a multiple of the size of DWORD. The total size field of the microcode update header specifies the
encrypted data size plus the header size; its value must be in multiples of 1024 bytes (1 KBytes). The optional
extended signature table if implemented follows the encrypted data, and its size is calculated by (Total Size – (Data
Size + 48)).
NOTE
The optional extended signature table is supported starting with processor family 0FH, model 03H.
.
Table 9-7. Microcode Update Field Definitions
Field Name
Offset (bytes)
Length
(bytes)
Description
Header Version
0
4
Version number of the update header.
Update Revision
4
4
Unique version number for the update, the basis for the update
signature provided by the processor to indicate the current update
functioning within the processor. Used by the BIOS to authenticate
the update and verify that the processor loads successfully. The
value in this field cannot be used for processor stepping identification
alone. This is a signed 32-bit number.
Date
8
4
Date of the update creation in binary format: mmddyyyy (e.g.
07/18/98 is 07181998H).
9-28 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
Table 9-7. Microcode Update Field Definitions (Contd.)
Field Name
Offset (bytes)
Length
(bytes)
Description
Processor Signature
12
4
Extended family, extended model, type, family, model, and stepping
of processor that requires this particular update revision (e.g.,
00000650H). Each microcode update is designed specifically for a
given extended family, extended model, type, family, model, and
stepping of the processor.
The BIOS uses the processor signature field in conjunction with the
CPUID instruction to determine whether or not an update is
appropriate to load on a processor. The information encoded within
this field exactly corresponds to the bit representations returned by
the CPUID instruction.
Checksum
16
4
Checksum of Update Data and Header. Used to verify the integrity of
the update header and data. Checksum is correct when the
summation of all the DWORDs (including the extended Processor
Signature Table) that comprise the microcode update result in
00000000H.
Loader Revision
20
4
Version number of the loader program needed to correctly load this
update. The initial version is 00000001H.
Processor Flags
24
4
Platform type information is encoded in the lower 8 bits of this 4byte field. Each bit represents a particular platform type for a given
CPUID. The BIOS uses the processor flags field in conjunction with
the platform Id bits in MSR (17H) to determine whether or not an
update is appropriate to load on a processor. Multiple bits may be set
representing support for multiple platform IDs.
Data Size
28
4
Specifies the size of the encrypted data in bytes, and must be a
multiple of DWORDs. If this value is 00000000H, then the microcode
update encrypted data is 2000 bytes (or 500 DWORDs).
Total Size
32
4
Specifies the total size of the microcode update in bytes. It is the
summation of the header size, the encrypted data size and the size of
the optional extended signature table. This value is always a multiple
of 1024.
Reserved
36
12
Reserved fields for future expansion
Update Data
48
Data Size or
2000
Update data
Extended Signature
Count
Data Size + 48
4
Specifies the number of extended signature structures (Processor
Signature[n], processor flags[n] and checksum[n]) that exist in this
microcode update.
Extended Checksum
Data Size + 52
4
Checksum of update extended processor signature table. Used to
verify the integrity of the extended processor signature table.
Checksum is correct when the summation of the DWORDs that
comprise the extended processor signature table results in
00000000H.
Reserved
Data Size + 56
12
Reserved fields
Vol. 3A 9-29
PROCESSOR MANAGEMENT AND INITIALIZATION
Table 9-7. Microcode Update Field Definitions (Contd.)
Field Name
Offset (bytes)
Length
(bytes)
Description
Processor Signature[n]
Data Size + 68 +
(n * 12)
4
Extended family, extended model, type, family, model, and stepping
of processor that requires this particular update revision (e.g.,
00000650H). Each microcode update is designed specifically for a
given extended family, extended model, type, family, model, and
stepping of the processor.
The BIOS uses the processor signature field in conjunction with the
CPUID instruction to determine whether or not an update is
appropriate to load on a processor. The information encoded within
this field exactly corresponds to the bit representations returned by
the CPUID instruction.
Processor Flags[n]
Data Size + 72 +
(n * 12)
4
Platform type information is encoded in the lower 8 bits of this 4byte field. Each bit represents a particular platform type for a given
CPUID. The BIOS uses the processor flags field in conjunction with
the platform Id bits in MSR (17H) to determine whether or not an
update is appropriate to load on a processor. Multiple bits may be set
representing support for multiple platform IDs.
Checksum[n]
Data Size + 76 +
(n * 12)
4
Used by utility software to decompose a microcode update into
multiple microcode updates where each of the new updates is
constructed without the optional Extended Processor Signature
Table.
To calculate the Checksum, substitute the Primary Processor
Signature entry and the Processor Flags entry with the
corresponding Extended Patch entry. Delete the Extended Processor
Signature Table entries. The Checksum is correct when the
summation of all DWORDs that comprise the created Extended
Processor Patch results in 00000000H.
Table 9-8. Microcode Update Format
31
24
16
8
0
Bytes
Header Version
0
Update Revision
4
Month: 8
Day: 8
Year: 16
8
Processor Signature (CPUID)
12
Stepping: 4
Model: 4
Family: 4
Type: 2
Reserved: 2
Extended
Mode: 4
Extended
Family: 8
Res: 4
Checksum
16
Loader Revision
20
Processor Flags
24
P0
P1
P2
P3
P4
P5
P6
P7
Reserved (24 bits)
Data Size
28
Total Size
32
Reserved (12 Bytes)
36
9-30 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
Table 9-8. Microcode Update Format (Contd.)
31
24
16
8
0
Bytes
Update Data (Data Size bytes, or 2000 Bytes if Data Size = 00000000H)
48
Extended Signature Count ‘n’
Data Size +
48
Extended Processor Signature Table Checksum
Data Size +
52
Reserved (12 Bytes)
Data Size +
56
Processor Signature[n]
Data Size +
68 +
(n * 12)
Processor Flags[n]
Data Size +
72 +
(n * 12)
Checksum[n]
Data Size +
76 +
(n * 12)
9.11.2
Optional Extended Signature Table
The extended signature table is a structure that may be appended to the end of the encrypted data when the
encrypted data only supports a single processor signature (optional case). The extended signature table will always
be present when the encrypted data supports multiple processor steppings and/or models (required case).
The extended signature table consists of a 20-byte extended signature header structure, which contains the
extended signature count, the extended processor signature table checksum, and 12 reserved bytes (Table 9-9).
Following the extended signature header structure, the extended signature table contains 0-to-n extended
processor signature structures.
Each processor signature structure consist of the processor signature, processor flags, and a checksum
(Table 9-10).
The extended signature count in the extended signature header structure indicates the number of processor signature structures that exist in the extended signature table.
The extended processor signature table checksum is a checksum of all DWORDs that comprise the extended signature table. That includes the extended signature count, extended processor signature table checksum, 12 reserved
bytes and the n processor signature structures. A valid extended signature table exists when the result of a
DWORD checksum is 00000000H.
Table 9-9. Extended Processor Signature Table Header Structure
Extended Signature Count ‘n’
Extended Processor Signature Table Checksum
Reserved (12 Bytes)
Data Size + 48
Data Size + 52
Data Size + 56
Table 9-10. Processor Signature Structure
Processor Signature[n]
Processor Flags[n]
Checksum[n]
Data Size + 68 + (n * 12)
Data Size + 72 + (n * 12)
Data Size + 76 + (n * 12)
Vol. 3A 9-31
PROCESSOR MANAGEMENT AND INITIALIZATION
9.11.3
Processor Identification
Each microcode update is designed to for a specific processor or set of processors. To determine the correct microcode update to load, software must ensure that one of the processor signatures embedded in the microcode update
matches the 32-bit processor signature returned by the CPUID instruction when executed by the target processor
with EAX = 1. Attempting to load a microcode update that does not match a processor signature embedded in the
microcode update with the processor signature returned by CPUID will cause the BIOS to reject the update.
Example 9-5 shows how to check for a valid processor signature match between the processor and microcode
update.
Example 9-5. Pseudo Code to Validate the Processor Signature
ProcessorSignature ← CPUID(1):EAX
If (Update.HeaderVersion = 00000001h)
{
// first check the ProcessorSignature field
If (ProcessorSignature = Update.ProcessorSignature)
Success
// if extended signature is present
Else If (Update.TotalSize > (Update.DataSize + 48))
{
//
// Assume the Data Size has been used to calculate the
// location of Update.ProcessorSignature[0].
//
For (N ← 0; ((N < Update.ExtendedSignatureCount) AND
(ProcessorSignature ≠ Update.ProcessorSignature[N])); N++);
// if the loops ended when the iteration count is
// less than the number of processor signatures in
// the table, we have a match
If (N < Update.ExtendedSignatureCount)
Success
Else
Fail
}
Else
Fail
Else
Fail
9.11.4
Platform Identification
In addition to verifying the processor signature, the intended processor platform type must be determined to properly target the microcode update. The intended processor platform type is determined by reading the
IA32_PLATFORM_ID register, (MSR 17H). This 64-bit register must be read using the RDMSR instruction.
The three platform ID bits, when read as a binary coded decimal (BCD) number, indicate the bit position in the
microcode update header’s processor flags field associated with the installed processor. The processor flags in the
48-byte header and the processor flags field associated with the extended processor signature structures may have
multiple bits set. Each set bit represents a different platform ID that the update supports.
Register Name:
MSR Address:
9-32 Vol. 3A
IA32_PLATFORM_ID
017H
PROCESSOR MANAGEMENT AND INITIALIZATION
Access:
Read Only
IA32_PLATFORM_ID is a 64-bit register accessed only when referenced as a Qword through a RDMSR instruction.
Table 9-11. Processor Flags
Bit
63:53
52:50
Descriptions
Reserved
Platform Id Bits (RO). The field gives information concerning the intended platform for the processor. See also Table 9-8.
52
0
0
0
0
1
1
1
1
49:0
51
0
0
1
1
0
0
1
1
50
0
1
0
1
0
1
0
1
Processor Flag 0
Processor Flag 1
Processor Flag 2
Processor Flag 3
Processor Flag 4
Processor Flag 5
Processor Flag 6
Processor Flag 7
Reserved
To validate the platform information, software may implement an algorithm similar to the algorithms in
Example 9-6.
Example 9-6. Pseudo Code Example of Processor Flags Test
Flag ← 1 << IA32_PLATFORM_ID[52:50]
If (Update.HeaderVersion = 00000001h)
{
If (Update.ProcessorFlags & Flag)
{
Load Update
}
Else
{
//
// Assume the Data Size has been used to calculate the
// location of Update.ProcessorSignature[N] and a match
// on Update.ProcessorSignature[N] has already succeeded
//
If (Update.ProcessorFlags[n] & Flag)
{
Load Update
}
}
}
9.11.5
Microcode Update Checksum
Each microcode update contains a DWORD checksum located in the update header. It is software’s responsibility to
ensure that a microcode update is not corrupt. To check for a corrupt microcode update, software must perform a
unsigned DWORD (32-bit) checksum of the microcode update. Even though some fields are signed, the checksum
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procedure treats all DWORDs as unsigned. Microcode updates with a header version equal to 00000001H must sum
all DWORDs that comprise the microcode update. A valid checksum check will yield a value of 00000000H. Any
other value indicates the microcode update is corrupt and should not be loaded.
The checksum algorithm shown by the pseudo code in Example 9-7 treats the microcode update as an array of
unsigned DWORDs. If the data size DWORD field at byte offset 32 equals 00000000H, the size of the encrypted
data is 2000 bytes, resulting in 500 DWORDs. Otherwise the microcode update size in DWORDs = (Total Size / 4),
where the total size is a multiple of 1024 bytes (1 KBytes).
Example 9-7. Pseudo Code Example of Checksum Test
N ← 512
If (Update.DataSize ≠ 00000000H)
N ← Update.TotalSize / 4
ChkSum ← 0
For (I ← 0; I < N; I++)
{
ChkSum ← ChkSum + MicrocodeUpdate[I]
}
If (ChkSum = 00000000H)
Success
Else
Fail
9.11.6
Microcode Update Loader
This section describes an update loader used to load an update into a P6 family or later processors. It also discusses
the requirements placed on the BIOS to ensure proper loading. The update loader described contains the minimal
instructions needed to load an update. The specific instruction sequence that is required to load an update is
dependent upon the loader revision field contained within the update header. This revision is expected to change
infrequently (potentially, only when new processor models are introduced).
Example 9-8 below represents the update loader with a loader revision of 00000001H. Note that the microcode
update must be aligned on a 16-byte boundary and the size of the microcode update must be 1-KByte granular.
Example 9-8. Assembly Code Example of Simple Microcode Update Loader
mov ecx,79h
xor eax,eax
xor ebx,ebx
mov ax,cs
shl eax,4
mov bx,offset Update
add eax,ebx
add eax,48d
xor edx,edx
WRMSR
;
;
;
;
MSR to write in ECX
clear EAX
clear EBX
Segment of microcode update
; Offset of microcode update
; Linear Address of Update in EAX
; Offset of the Update Data within the Update
; Zero in EDX
; microcode update trigger
The loader shown in Example 9-8 assumes that update is the address of a microcode update (header and data)
embedded within the code segment of the BIOS. It also assumes that the processor is operating in real mode. The
data may reside anywhere in memory, aligned on a 16-byte boundary, that is accessible by the processor within its
current operating mode.
Before the BIOS executes the microcode update trigger (WRMSR) instruction, the following must be true:
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•
In 64-bit mode, EAX contains the lower 32-bits of the microcode update linear address. In protected mode, EAX
contains the full 32-bit linear address of the microcode update.
•
In 64-bit mode, EDX contains the upper 32-bits of the microcode update linear address. In protected mode,
EDX equals zero.
•
ECX contains 79H (address of IA32_BIOS_UPDT_TRIG).
Other requirements are:
•
If the update is loaded while the processor is in real mode, then the update data may not cross a segment
boundary.
•
If the update is loaded while the processor is in real mode, then the update data may not exceed a segment
limit.
•
•
If paging is enabled, pages that are currently present must map the update data.
The microcode update data requires a 16-byte boundary alignment.
9.11.6.1
Hard Resets in Update Loading
The effects of a loaded update are cleared from the processor upon a hard reset. Therefore, each time a hard reset
is asserted during the BIOS POST, the update must be reloaded on all processors that observed the reset. The
effects of a loaded update are, however, maintained across a processor INIT. There are no side effects caused by
loading an update into a processor multiple times.
9.11.6.2
Update in a Multiprocessor System
A multiprocessor (MP) system requires loading each processor with update data appropriate for its CPUID and platform ID bits. The BIOS is responsible for ensuring that this requirement is met and that the loader is located in a
module executed by all processors in the system. If a system design permits multiple steppings of Pentium 4, Intel
Xeon, and P6 family processors to exist concurrently; then the BIOS must verify individual processors against the
update header information to ensure appropriate loading. Given these considerations, it is most practical to load
the update during MP initialization.
9.11.6.3
Update in a System Supporting Intel Hyper-Threading Technology
Intel Hyper-Threading Technology has implications on the loading of the microcode update. The update must be
loaded for each core in a physical processor. Thus, for a processor supporting Intel Hyper-Threading Technology,
only one logical processor per core is required to load the microcode update. Each individual logical processor can
independently load the update. However, MP initialization must provide some mechanism (e.g. a software semaphore) to force serialization of microcode update loads and to prevent simultaneous load attempts to the same
core.
9.11.6.4
Update in a System Supporting Dual-Core Technology
Dual-core technology has implications on the loading of the microcode update. The microcode update facility is not
shared between processor cores in the same physical package. The update must be loaded for each core in a physical processor.
If processor core supports Intel Hyper-Threading Technology, the guideline described in Section 9.11.6.3 also
applies.
9.11.6.5
Update Loader Enhancements
The update loader presented in Section 9.11.6, “Microcode Update Loader,” is a minimal implementation that can
be enhanced to provide additional functionality. Potential enhancements are described below:
•
BIOS can incorporate multiple updates to support multiple steppings of the Pentium 4, Intel Xeon, and P6
family processors. This feature provides for operating in a mixed stepping environment on an MP system and
enables a user to upgrade to a later version of the processor. In this case, modify the loader to check the CPUID
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and platform ID bits of the processor that it is running on against the available headers before loading a
particular update. The number of updates is only limited by available BIOS space.
•
A loader can load the update and test the processor to determine if the update was loaded correctly. See
Section 9.11.7, “Update Signature and Verification.”
•
A loader can verify the integrity of the update data by performing a checksum on the double words of the
update summing to zero. See Section 9.11.5, “Microcode Update Checksum.”
•
A loader can provide power-on messages indicating successful loading of an update.
9.11.7
Update Signature and Verification
The P6 family and later processors provide capabilities to verify the authenticity of a particular update and to identify the current update revision. This section describes the model-specific extensions of processors that support
this feature. The update verification method below assumes that the BIOS will only verify an update that is more
recent than the revision currently loaded in the processor.
CPUID returns a value in a model specific register in addition to its usual register return values. The semantics of
CPUID cause it to deposit an update ID value in the 64-bit model-specific register at address 08BH
(IA32_BIOS_SIGN_ID). If no update is present in the processor, the value in the MSR remains unmodified. The
BIOS must pre-load a zero into the MSR before executing CPUID. If a read of the MSR at 8BH still returns zero after
executing CPUID, this indicates that no update is present.
The update ID value returned in the EDX register after RDMSR executes indicates the revision of the update loaded
in the processor. This value, in combination with the CPUID value returned in the EAX register, uniquely identifies a
particular update. The signature ID can be directly compared with the update revision field in a microcode update
header for verification of a correct load. No consecutive updates released for a given stepping of a processor may
share the same signature. The processor signature returned by CPUID differentiates updates for different steppings.
9.11.7.1
Determining the Signature
An update that is successfully loaded into the processor provides a signature that matches the update revision of
the currently functioning revision. This signature is available any time after the actual update has been loaded.
Requesting the signature does not have a negative impact upon a loaded update.
The procedure for determining this signature shown in Example 9-9.
Example 9-9. Assembly Code to Retrieve the Update Revision
MOV
XOR
XOR
WRMSR
MOV
cpuid
MOV
rdmsr
ECX, 08BH
EAX, EAX
EDX, EDX
;IA32_BIOS_SIGN_ID
;clear EAX
;clear EDX
;Load 0 to MSR at 8BH
EAX, 1
ECX, 08BH
;IA32_BIOS_SIGN_ID
;Read Model Specific Register
If there is an update active in the processor, its revision is returned in the EDX register after the RDMSR instruction
executes.
IA32_BIOS_SIGN_ID
MSR Address:
Default Value:
Access:
Microcode Update Signature Register
08BH Accessed as a Qword
XXXX XXXX XXXX XXXXh
Read/Write
The IA32_BIOS_SIGN_ID register is used to report the microcode update signature when CPUID executes. The
signature is returned in the upper DWORD (Table 9-12).
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Table 9-12. Microcode Update Signature
Bit
Description
63:32
Microcode update signature. This field contains the signature of the currently loaded microcode update when read following
the execution of the CPUID instruction, function 1. It is required that this register field be pre-loaded with zero prior to
executing the CPUID, function 1. If the field remains equal to zero, then there is no microcode update loaded. Another nonzero value will be the signature.
31:0
Reserved.
9.11.7.2
Authenticating the Update
An update may be authenticated by the BIOS using the signature primitive, described above, and the algorithm in
Example 9-10.
Example 9-10. Pseudo Code to Authenticate the Update
Z ← Obtain Update Revision from the Update Header to be authenticated;
X ← Obtain Current Update Signature from MSR 8BH;
If (Z > X)
{
Load Update that is to be authenticated;
Y ← Obtain New Signature from MSR 8BH;
If (Z = Y)
Success
Else
Fail
}
Else
Fail
Example 9-10 requires that the BIOS only authenticate updates that contain a numerically larger revision than the
currently loaded revision, where Current Signature (X) < New Update Revision (Z). A processor with no loaded
update is considered to have a revision equal to zero.
This authentication procedure relies upon the decoding provided by the processor to verify an update from a potentially hostile source. As an example, this mechanism in conjunction with other safeguards provides security for
dynamically incorporating field updates into the BIOS.
9.11.8
Optional Processor Microcode Update Specifications
This section an interface that an OEM-BIOS may provide to its client system software to manage processor microcode updates. System software may choose to build its own facility to manage microcode updates (e.g. similar to
the facility described in Section 9.11.6) or rely on a facility provided by the BIOS to perform microcode updates.
Sections 9.11.8.1-9.11.8.9 describes an extension (Function 0D042H) to the real mode INT 15H service. INT 15H
0D042H function is one of several alternatives that a BIOS may choose to implement microcode update facility and
offer to its client application (e.g. an OS). Other alternative microcode update facility that BIOS can choose are
dependent on platform-specific capabilities, including the Capsule Update mechanism from the UEFI specification
(www.uefi.org). In this discussion, the application is referred to as the calling program or caller.
The real mode INT15 call specification described here is an Intel extension to an OEM BIOS. This extension allows
an application to read and modify the contents of the microcode update data in NVRAM. The update loader, which
is part of the system BIOS, cannot be updated by the interface. All of the functions defined in the specification must
be implemented for a system to be considered compliant with the specification. The INT15 functions are accessible
only from real mode.
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9.11.8.1
Responsibilities of the BIOS
If a BIOS passes the presence test (INT 15H, AX = 0D042H, BL = 0H), it must implement all of the sub-functions
defined in the INT 15H, AX = 0D042H specification. There are no optional functions. BIOS must load the appropriate
update for each processor during system initialization.
A Header Version of an update block containing the value 0FFFFFFFFH indicates that the update block is unused and
available for storing a new update.
The BIOS is responsible for providing a region of non-volatile storage (NVRAM) for each potential processor stepping within a system. This storage unit consists of one or more update blocks. An update block is a contiguous
2048-byte block of memory. The BIOS for a single processor system need only provide update blocks to store one
microcode update. If the BIOS for a multiple processor system is intended to support mixed processor steppings,
then the BIOS needs to provide enough update blocks to store each unique microcode update or for each processor
socket on the OEM’s system board.
The BIOS is responsible for managing the NVRAM update blocks. This includes garbage collection, such as
removing microcode updates that exist in NVRAM for which a corresponding processor does not exist in the system.
This specification only provides the mechanism for ensuring security, the uniqueness of an entry, and that stale
entries are not loaded. The actual update block management is implementation specific on a per-BIOS basis.
As an example, the BIOS may use update blocks sequentially in ascending order with CPU signatures sorted versus
the first available block. In addition, garbage collection may be implemented as a setup option to clear all NVRAM
slots or as BIOS code that searches and eliminates unused entries during boot.
NOTES
For IA-32 processors starting with family 0FH and model 03H and Intel 64 processors, the
microcode update may be as large as 16 KBytes. Thus, BIOS must allocate 8 update blocks for each
microcode update. In a MP system, a common microcode update may be sufficient for each socket
in the system.
For IA-32 processors earlier than family 0FH and model 03H, the microcode update is 2 KBytes. An
MP-capable BIOS that supports multiple steppings must allocate a block for each socket in the
system.
A single-processor BIOS that supports variable-sized microcode update and fixed-sized microcode
update must allocate one 16-KByte region and a second region of at least 2 KBytes.
The following algorithm (Example 9-11) describes the steps performed during BIOS initialization used to load the
updates into the processor(s). The algorithm assumes:
•
The BIOS ensures that no update contained within NVRAM has a header version or loader version that does not
match one currently supported by the BIOS.
•
•
•
The update contains a correct checksum.
The BIOS ensures that (at most) one update exists for each processor stepping.
Older update revisions are not allowed to overwrite more recent ones.
These requirements are checked by the BIOS during the execution of the write update function of this interface.
The BIOS sequentially scans through all of the update blocks in NVRAM starting with index 0. The BIOS scans until
it finds an update where the processor fields in the header match the processor signature (extended family,
extended model, type, family, model, and stepping) as well as the platform bits of the current processor.
Example 9-11. Pseudo Code, Checks Required Prior to Loading an Update
For each processor in the system
{
Determine the Processor Signature via CPUID function 1;
Determine the Platform Bits ← 1 << IA32_PLATFORM_ID[52:50];
For (I ← UpdateBlock 0, I < NumOfBlocks; I++)
{
If (Update.Header_Version = 00000001H)
{
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PROCESSOR MANAGEMENT AND INITIALIZATION
If ((Update.ProcessorSignature = Processor Signature) &&
(Update.ProcessorFlags & Platform Bits))
{
Load Update.UpdateData into the Processor;
Verify update was correctly loaded into the processor
Go on to next processor
Break;
}
Else If (Update.TotalSize > (Update.DataSize + 48))
{
N ← 0
While (N < Update.ExtendedSignatureCount)
{
If ((Update.ProcessorSignature[N] =
Processor Signature) &&
(Update.ProcessorFlags[N] & Platform Bits))
{
Load Update.UpdateData into the Processor;
Verify update correctly loaded into the processor
Go on to next processor
Break;
}
N ← N + 1
}
I ← I + (Update.TotalSize / 2048)
If ((Update.TotalSize MOD 2048) = 0)
I ← I + 1
}
}
}
}
NOTES
The platform Id bits in IA32_PLATFORM_ID are encoded as a three-bit binary coded decimal field.
The platform bits in the microcode update header are individually bit encoded. The algorithm must
do a translation from one format to the other prior to doing a check.
When performing the INT 15H, 0D042H functions, the BIOS must assume that the caller has no knowledge of platform specific requirements. It is the responsibility of BIOS calls to manage all chipset and platform specific prerequisites for managing the NVRAM device. When writing the update data using the Write Update sub-function, the
BIOS must maintain implementation specific data requirements (such as the update of NVRAM checksum). The
BIOS should also attempt to verify the success of write operations on the storage device used to record the update.
9.11.8.2
Responsibilities of the Calling Program
This section of the document lists the responsibilities of a calling program using the interface specifications to load
microcode update(s) into BIOS NVRAM.
•
The calling program should call the INT 15H, 0D042H functions from a pure real mode program and should be
executing on a system that is running in pure real mode.
•
The caller should issue the presence test function (sub function 0) and verify the signature and return codes of
that function.
•
It is important that the calling program provides the required scratch RAM buffers for the BIOS and the proper
stack size as specified in the interface definition.
•
The calling program should read any update data that already exists in the BIOS in order to make decisions
about the appropriateness of loading the update. The BIOS must refuse to overwrite a newer update with an
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older version. The update header contains information about version and processor specifics for the calling
program to make an intelligent decision about loading.
•
There can be no ambiguous updates. The BIOS must refuse to allow multiple updates for the same CPU to exist
at the same time; it also must refuse to load updates for processors that don’t exist on the system.
•
The calling application should implement a verify function that is run after the update write function successfully completes. This function reads back the update and verifies that the BIOS returned an image identical to
the one that was written.
Example 9-12 represents a calling program.
Example 9-12. INT 15 DO42 Calling Program Pseudo-code
//
// We must be in real mode
//
If the system is not in Real mode exit
//
// Detect presence of Genuine Intel processor(s) that can be updated
// using(CPUID)
//
If no Intel processors exist that can be updated exit
//
// Detect the presence of the Intel microcode update extensions
//
If the BIOS fails the PresenceTestexit
//
// If the APIC is enabled, see if any other processors are out there
//
Read IA32_APICBASE
If APIC enabled
{
Send Broadcast Message to all processors except self via APIC
Have all processors execute CPUID, record the Processor Signature
(i.e.,Extended Family, Extended Model, Type, Family, Model, Stepping)
Have all processors read IA32_PLATFORM_ID[52:50], record Platform
Id Bits
If current processor cannot be updated
exit
}
//
// Determine the number of unique update blocks needed for this system
//
NumBlocks = 0
For each processor
{
If ((this is a unique processor stepping) AND
(we have a unique update in the database for this processor))
{
Checksum the update from the database;
If Checksum fails
exit
NumBlocks ← NumBlocks + size of microcode update / 2048
}
}
//
// Do we have enough update slots for all CPUs?
//
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If there are more blocks required to support the unique processor steppings than update blocks
provided by the BIOS exit
//
// Do we need any update blocks at all? If not, we are done
//
If (NumBlocks = 0)
exit
//
// Record updates for processors in NVRAM.
//
For (I=0; I ISRV[7:4])
THEN
APR[7:0] ← TPR[7:0]
ELSE
APR[7:4] ← max(TPR[7:4] AND ISRV[7:4], IRRV[7:4])
APR[3:0] ← 0.
Here, the TPR value is the task priority value in the TPR (see Figure 10-18), the IRRV value is the vector number
for the highest priority bit that is set in the IRR (see Figure 10-20) or 00H (if no IRR bit is set), and the ISRV value
is the vector number for the highest priority bit that is set in the ISR (see Figure 10-20). Following arbitration
among the destination processors, the processor with the lowest value in its APR handles the IPI and the other
processors ignore it.
(P6 family and Pentium processors.) For these processors, if a focus processor exists, it may accept the interrupt,
regardless of its priority. A processor is said to be the focus of an interrupt if it is currently servicing that interrupt
or if it has a pending request for that interrupt. For Intel Xeon processors, the concept of a focus processor is not
supported.
In operating systems that use the lowest priority delivery mode but do not update the TPR, the TPR information
saved in the chipset will potentially cause the interrupt to be always delivered to the same processor from the
logical set. This behavior is functionally backward compatible with the P6 family processor but may result in unexpected performance implications.
10.6.3
IPI Delivery and Acceptance
When the low double-word of the ICR is written to, the local APIC creates an IPI message from the information
contained in the ICR and sends the message out on the system bus (Pentium 4 and Intel Xeon processors) or the
APIC bus (P6 family and Pentium processors). The manner in which these IPIs are handled after being issues in
described in Section 10.8, “Handling Interrupts.”
10.7
SYSTEM AND APIC BUS ARBITRATION
When several local APICs and the I/O APIC are sending IPI and interrupt messages on the system bus (or APIC
bus), the order in which the messages are sent and handled is determined through bus arbitration.
For the Pentium 4 and Intel Xeon processors, the local and I/O APICs use the arbitration mechanism defined for the
system bus to determine the order in which IPIs are handled. This mechanism is non-architectural and cannot be
controlled by software.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
For the P6 family and Pentium processors, the local and I/O APICs use an APIC-based arbitration mechanism to
determine the order in which IPIs are handled. Here, each local APIC is given an arbitration priority of from 0 to 15,
which the I/O APIC uses during arbitration to determine which local APIC should be given access to the APIC bus.
The local APIC with the highest arbitration priority always wins bus access. Upon completion of an arbitration
round, the winning local APIC lowers its arbitration priority to 0 and the losing local APICs each raise theirs by 1.
The current arbitration priority for a local APIC is stored in a 4-bit, software-transparent arbitration ID (Arb ID)
register. During reset, this register is initialized to the APIC ID number (stored in the local APIC ID register). The
INIT level-deassert IPI, which is issued with and ICR command, can be used to resynchronize the arbitration priorities of the local APICs by resetting Arb ID register of each agent to its current APIC ID value. (The Pentium 4 and
Intel Xeon processors do not implement the Arb ID register.)
Section 10.10, “APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors),” describes the
APIC bus arbitration protocols and bus message formats, while Section 10.6.1, “Interrupt Command Register
(ICR),” describes the INIT level de-assert IPI message.
Note that except for the SIPI IPI (see Section 10.6.1, “Interrupt Command Register (ICR)”), all bus messages that
fail to be delivered to their specified destination or destinations are automatically retried. Software should avoid
situations in which IPIs are sent to disabled or nonexistent local APICs, causing the messages to be resent repeatedly. Additionally, interrupt sources that target the APIC should be masked or changed to no longer target the
APIC.
10.8
HANDLING INTERRUPTS
When a local APIC receives an interrupt from a local source, an interrupt message from an I/O APIC, or and IPI, the
manner in which it handles the message depends on processor implementation, as described in the following
sections.
10.8.1
Interrupt Handling with the Pentium 4 and Intel Xeon Processors
With the Pentium 4 and Intel Xeon processors, the local APIC handles the local interrupts, interrupt messages, and
IPIs it receives as follows:
1. It determines if it is the specified destination or not (see Figure 10-16). If it is the specified destination, it
accepts the message; if it is not, it discards the message.
Wait to Receive
Bus Message
Discard
Message
No
Belong to
Destination?
Yes
Accept
Message
Figure 10-16. Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and Intel Xeon Processors)
2. If the local APIC determines that it is the designated destination for the interrupt and if the interrupt request is
an NMI, SMI, INIT, ExtINT, or SIPI, the interrupt is sent directly to the processor core for handling.
3. If the local APIC determines that it is the designated destination for the interrupt but the interrupt request is
not one of the interrupts given in step 2, the local APIC sets the appropriate bit in the IRR.
4. When interrupts are pending in the IRR register, the local APIC dispatches them to the processor one at a time,
based on their priority and the current processor priority in the PPR (see Section 10.8.3.1, “Task and Processor
Priorities”).
5. When a fixed interrupt has been dispatched to the processor core for handling, the completion of the handler
routine is indicated with an instruction in the instruction handler code that writes to the end-of-interrupt (EOI)
register in the local APIC (see Section 10.8.5, “Signaling Interrupt Servicing Completion”). The act of writing to
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the EOI register causes the local APIC to delete the interrupt from its ISR queue and (for level-triggered
interrupts) send a message on the bus indicating that the interrupt handling has been completed. (A write to
the EOI register must not be included in the handler routine for an NMI, SMI, INIT, ExtINT, or SIPI.)
10.8.2
Interrupt Handling with the P6 Family and Pentium Processors
With the P6 family and Pentium processors, the local APIC handles the local interrupts, interrupt messages, and
IPIs it receives as follows (see Figure 10-17).
Wait to Receive
Bus Message
No
Discard
Message
Belong
to
Destination?
Yes
Is it
NMI/SMI/INIT
/ExtINT?
Yes
Accept
Message
No
Fixed
Delivery
Lowes
Priority
P6 Family
Processor Specific
No
Set Status
to Retry
Am I
Focus?
Is Interrupt Slot
Available?
Yes
Yes
Is Status a
Retry?
Yes
Accept
Message
Yes
Discard
Message
No
No
Other
Focus?
No
Set Status
to Retry
No
Accept
Message
Is Interrupt
Slot Available?
Yes
No
Arbitrate
Am I Winner?
Yes
Accept
Message
Figure 10-17. Interrupt Acceptance Flow Chart for the Local APIC (P6 Family and Pentium Processors)
1. (IPIs only) It examines the IPI message to determines if it is the specified destination for the IPI as described
in Section 10.6.2, “Determining IPI Destination.” If it is the specified destination, it continues its acceptance
procedure; if it is not the destination, it discards the IPI message. When the message specifies lowest-priority
delivery mode, the local APIC will arbitrate with the other processors that were designated on recipients of the
IPI message (see Section 10.6.2.4, “Lowest Priority Delivery Mode”).
2. If the local APIC determines that it is the designated destination for the interrupt and if the interrupt request is
an NMI, SMI, INIT, ExtINT, or INIT-deassert interrupt, or one of the MP protocol IPI messages (BIPI, FIPI, and
SIPI), the interrupt is sent directly to the processor core for handling.
3. If the local APIC determines that it is the designated destination for the interrupt but the interrupt request is
not one of the interrupts given in step 2, the local APIC looks for an open slot in one of its two pending interrupt
queues contained in the IRR and ISR registers (see Figure 10-20). If a slot is available (see Section 10.8.4,
“Interrupt Acceptance for Fixed Interrupts”), places the interrupt in the slot. If a slot is not available, it rejects
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the interrupt request and sends it back to the sender with a retry message.
4. When interrupts are pending in the IRR register, the local APIC dispatches them to the processor one at a time,
based on their priority and the current processor priority in the PPR (see Section 10.8.3.1, “Task and Processor
Priorities”).
5. When a fixed interrupt has been dispatched to the processor core for handling, the completion of the handler
routine is indicated with an instruction in the instruction handler code that writes to the end-of-interrupt (EOI)
register in the local APIC (see Section 10.8.5, “Signaling Interrupt Servicing Completion”). The act of writing to
the EOI register causes the local APIC to delete the interrupt from its queue and (for level-triggered interrupts)
send a message on the bus indicating that the interrupt handling has been completed. (A write to the EOI
register must not be included in the handler routine for an NMI, SMI, INIT, ExtINT, or SIPI.)
The following sections describe the acceptance of interrupts and their handling by the local APIC and processor in
greater detail.
10.8.3
Interrupt, Task, and Processor Priority
Each interrupt delivered to the processor through the local APIC has a priority based on its vector number. The local
APIC uses this priority to determine when to service the interrupt relative to the other activities of the processor,
including the servicing of other interrupts.
Each interrupt vector is an 8-bit value. The interrupt-priority class is the value of bits 7:4 of the interrupt vector.
The lowest interrupt-priority class is 1 and the highest is 15; interrupts with vectors in the range 0–15 (with interrupt-priority class 0) are illegal and are never delivered. Because vectors 0–31 are reserved for dedicated uses by
the Intel 64 and IA-32 architectures, software should configure interrupt vectors to use interrupt-priority classes in
the range 2–15.
Each interrupt-priority class encompasses 16 vectors. The relative priority of interrupts within an interrupt-priority
class is determined by the value of bits 3:0 of the vector number. The higher the value of those bits, the higher the
priority within that interrupt-priority class. Thus, each interrupt vector comprises two parts, with the high 4 bits
indicating its interrupt-priority class and the low 4 bits indicating its ranking within the interrupt-priority class.
10.8.3.1
Task and Processor Priorities
The local APIC also defines a task priority and a processor priority that determine the order in which interrupts
are handled. The task-priority class is the value of bits 7:4 of the task-priority register (TPR), which can be
written by software (TPR is a read/write register); see Figure 10-18.
31
8 7
4 3
0
Reserved
Address: FEE0 0080H
Value after reset: 0H
Task-Priority Class
Task-Priority Sub-Class
Figure 10-18. Task-Priority Register (TPR)
NOTE
In this discussion, the term “task” refers to a software defined task, process, thread, program, or
routine that is dispatched to run on the processor by the operating system. It does not refer to an
IA-32 architecture defined task as described in Chapter 7, “Task Management.”
The task priority allows software to set a priority threshold for interrupting the processor. This mechanism enables
the operating system to temporarily block low priority interrupts from disturbing high-priority work that the
processor is doing. The ability to block such interrupts using task priority results from the way that the TPR controls
the value of the processor-priority register (PPR).5
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The processor-priority class is a value in the range 0–15 that is maintained in bits 7:4 of the processor-priority
register (PPR); see Figure 10-19. The PPR is a read-only register. The processor-priority class represents the
current priority at which the processor is executing.
31
8 7
4 3
0
Reserved
Address: FEE0 00A0H
Value after reset: 0H
Processor-Priority Class
Processor-Priority Sub-Class
Figure 10-19. Processor-Priority Register (PPR)
The value of the PPR is based on the value of TPR and the value ISRV; ISRV is the vector number of the highest
priority bit that is set in the ISR or 00H if no bit is set in the ISR. (See Section 10.8.4 for more details on the ISR.)
The value of PPR is determined as follows:
•
PPR[7:4] (the processor-priority class) the maximum of TPR[7:4] (the task- priority class) and ISRV[7:4] (the
priority of the highest priority interrupt in service).
•
PPR[3:0] (the processor-priority sub-class) is determined as follows:
— If TPR[7:4] > ISRV[7:4], PPR[3:0] is TPR[3:0] (the task-priority sub-class).
— If TPR[7:4] < ISRV[7:4], PPR[3:0] is 0.
— If TPR[7:4] = ISRV[7:4], PPR[3:0] may be either TPR[3:0] or 0. The actual behavior is model-specific.
The processor-priority class determines the priority threshold for interrupting the processor. The processor will
deliver only those interrupts that have an interrupt-priority class higher than the processor-priority class in the
PPR. If the processor-priority class is 0, the PPR does not inhibit the delivery any interrupt; if it is 15, the processor
inhibits the delivery of all interrupts. (The processor-priority mechanism does not affect the delivery of interrupts
with the NMI, SMI, INIT, ExtINT, INIT-deassert, and start-up delivery modes.)
The processor does not use the processor-priority sub-class to determine which interrupts to delivery and which to
inhibit. (The processor uses the processor-priority sub-class only to satisfy reads of the PPR.)
10.8.4
Interrupt Acceptance for Fixed Interrupts
The local APIC queues the fixed interrupts that it accepts in one of two interrupt pending registers: the interrupt
request register (IRR) or in-service register (ISR). These two 256-bit read-only registers are shown in
Figure 10-20. The 256 bits in these registers represent the 256 possible vectors; vectors 0 through 15 are reserved
by the APIC (see also: Section 10.5.2, “Valid Interrupt Vectors”).
NOTE
All interrupts with an NMI, SMI, INIT, ExtINT, start-up, or INIT-deassert delivery mode bypass the
IRR and ISR registers and are sent directly to the processor core for servicing.
The IRR contains the active interrupt requests that have been accepted, but not yet dispatched to the processor for
servicing. When the local APIC accepts an interrupt, it sets the bit in the IRR that corresponds the vector of the
accepted interrupt. When the processor core is ready to handle the next interrupt, the local APIC clears the highest
priority IRR bit that is set and sets the corresponding ISR bit. The vector for the highest priority bit set in the ISR
is then dispatched to the processor core for servicing.
While the processor is servicing the highest priority interrupt, the local APIC can send additional fixed interrupts by
setting bits in the IRR. When the interrupt service routine issues a write to the EOI register (see Section 10.8.5,
“Signaling Interrupt Servicing Completion”), the local APIC responds by clearing the highest priority ISR bit that is
5. The TPR also determines the arbitration priority of the local processor; see Section 10.6.2.4, “Lowest Priority Delivery Mode.”
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
255
16 15
0
Reserved
IRR
Reserved
ISR
Reserved
TMR
Addresses: IRR FEE0 0200H - FEE0 0270H
ISR FEE0 0100H - FEE0 0170H
TMR FEE0 0180H - FEE0 01F0H
Value after reset: 0H
Figure 10-20. IRR, ISR and TMR Registers
set. It then repeats the process of clearing the highest priority bit in the IRR and setting the corresponding bit in
the ISR. The processor core then begins executing the service routing for the highest priority bit set in the ISR.
If more than one interrupt is generated with the same vector number, the local APIC can set the bit for the vector
both in the IRR and the ISR. This means that for the Pentium 4 and Intel Xeon processors, the IRR and ISR can
queue two interrupts for each interrupt vector: one in the IRR and one in the ISR. Any additional interrupts issued
for the same interrupt vector are collapsed into the single bit in the IRR.
For the P6 family and Pentium processors, the IRR and ISR registers can queue no more than two interrupts per
interrupt vector and will reject other interrupts that are received within the same vector.
If the local APIC receives an interrupt with an interrupt-priority class higher than that of the interrupt currently in
service, and interrupts are enabled in the processor core, the local APIC dispatches the higher priority interrupt to
the processor immediately (without waiting for a write to the EOI register). The currently executing interrupt
handler is then interrupted so the higher-priority interrupt can be handled. When the handling of the higher-priority
interrupt has been completed, the servicing of the interrupted interrupt is resumed.
The trigger mode register (TMR) indicates the trigger mode of the interrupt (see Figure 10-20). Upon acceptance
of an interrupt into the IRR, the corresponding TMR bit is cleared for edge-triggered interrupts and set for leveltriggered interrupts. If a TMR bit is set when an EOI cycle for its corresponding interrupt vector is generated, an
EOI message is sent to all I/O APICs.
10.8.5
Signaling Interrupt Servicing Completion
For all interrupts except those delivered with the NMI, SMI, INIT, ExtINT, the start-up, or INIT-Deassert delivery
mode, the interrupt handler must include a write to the end-of-interrupt (EOI) register (see Figure 10-21). This
write must occur at the end of the handler routine, sometime before the IRET instruction. This action indicates that
the servicing of the current interrupt is complete and the local APIC can issue the next interrupt from the ISR.
31
0
Address: 0FEE0 00B0H
Value after reset: 0H
Figure 10-21. EOI Register
Upon receiving an EOI, the APIC clears the highest priority bit in the ISR and dispatches the next highest priority
interrupt to the processor. If the terminated interrupt was a level-triggered interrupt, the local APIC also sends an
end-of-interrupt message to all I/O APICs.
System software may prefer to direct EOIs to specific I/O APICs rather than having the local APIC send end-ofinterrupt messages to all I/O APICs.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Software can inhibit the broadcast of EOI message by setting bit 12 of the Spurious Interrupt Vector Register (see
Section 10.9). If this bit is set, a broadcast EOI is not generated on an EOI cycle even if the associated TMR bit indicates that the current interrupt was level-triggered. The default value for the bit is 0, indicating that EOI broadcasts
are performed.
Bit 12 of the Spurious Interrupt Vector Register is reserved to 0 if the processor does not support suppression of
EOI broadcasts. Support for EOI-broadcast suppression is reported in bit 24 in the Local APIC Version Register (see
Section 10.4.8); the feature is supported if that bit is set to 1. When supported, the feature is available in both
xAPIC mode and x2APIC mode.
System software desiring to perform directed EOIs for level-triggered interrupts should set bit 12 of the Spurious
Interrupt Vector Register and follow each the EOI to the local xAPIC for a level triggered interrupt with a directed
EOI to the I/O APIC generating the interrupt (this is done by writing to the I/O APIC’s EOI register). System software performing directed EOIs must retain a mapping associating level-triggered interrupts with the I/O APICs in
the system.
10.8.6
Task Priority in IA-32e Mode
In IA-32e mode, operating systems can manage the 16 interrupt-priority classes (see Section 10.8.3, “Interrupt,
Task, and Processor Priority”) explicitly using the task priority register (TPR). Operating systems can use the TPR
to temporarily block specific (low-priority) interrupts from interrupting a high-priority task. This is done by loading
TPR with a value in which the task-priority class corresponds to the highest interrupt-priority class that is to be
blocked. For example:
•
Loading the TPR with a task-priority class of 8 (01000B) blocks all interrupts with an interrupt-priority class of
8 or less while allowing all interrupts with an interrupt-priority class of 9 or more to be recognized.
•
•
Loading the TPR with a task-priority class of 0 enables all external interrupts.
Loading the TPR with a task-priority class of 0FH (01111B) disables all external interrupts.
The TPR (shown in Figure 10-18) is cleared to 0 on reset. In 64-bit mode, software can read and write the TPR
using an alternate interface, MOV CR8 instruction. The new task-priority class is established when the MOV CR8
instruction completes execution. Software does not need to force serialization after loading the TPR using MOV
CR8.
Use of the MOV CRn instruction requires a privilege level of 0. Programs running at privilege level greater than 0
cannot read or write the TPR. An attempt to do so causes a general-protection exception. The TPR is abstracted
from the interrupt controller (IC), which prioritizes and manages external interrupt delivery to the processor. The
IC can be an external device, such as an APIC or 8259. Typically, the IC provides a priority mechanism similar or
identical to the TPR. The IC, however, is considered implementation-dependent with the under-lying priority mechanisms subject to change. CR8, by contrast, is part of the Intel 64 architecture. Software can depend on this definition remaining unchanged.
Figure 10-22 shows the layout of CR8; only the low four bits are used. The remaining 60 bits are reserved and
must be written with zeros. Failure to do this causes a general-protection exception.
63
4 3
0
Reserved
Value after reset: 0H
Figure 10-22. CR8 Register
10.8.6.1
Interaction of Task Priorities between CR8 and APIC
The first implementation of Intel 64 architecture includes a local advanced programmable interrupt controller
(APIC) that is similar to the APIC used with previous IA-32 processors. Some aspects of the local APIC affect the
operation of the architecturally defined task priority register and the programming interface using CR8.
Notable CR8 and APIC interactions are:
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•
•
The processor powers up with the local APIC enabled.
•
APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0. A read of CR8 returns a 64-bit value which is the
value of TPR[bits 7:4], zero extended to 64 bits.
The APIC must be enabled for CR8 to function as the TPR. Writes to CR8 are reflected into the APIC Task Priority
Register.
There are no ordering mechanisms between direct updates of the APIC.TPR and CR8. Operating software should
implement either direct APIC TPR updates or CR8 style TPR updates but not mix them. Software can use a serializing instruction (for example, CPUID) to serialize updates between MOV CR8 and stores to the APIC.
10.9
SPURIOUS INTERRUPT
A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the
interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the
interrupt that was to be dispensed has become masked (programmed by software), the local APIC will deliver a
spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this
vector should return without an EOI.
The vector number for the spurious-interrupt vector is specified in the spurious-interrupt vector register (see
Figure 10-23). The functions of the fields in this register are as follows:
Spurious Vector
Determines the vector number to be delivered to the processor when the local APIC generates
a spurious vector.
(Pentium 4 and Intel Xeon processors.) Bits 0 through 7 of the this field are programmable by
software.
(P6 family and Pentium processors). Bits 4 through 7 of the this field are programmable by
software, and bits 0 through 3 are hardwired to logical ones. Software writes to bits 0 through
3 have no effect.
APIC Software Enable/Disable
Allows software to temporarily enable (1) or disable (0) the local APIC (see Section 10.4.3,
“Enabling or Disabling the Local APIC”).
Focus Processor Checking
Determines if focus processor checking is enabled (0) or disabled (1) when using the lowestpriority delivery mode. In Pentium 4 and Intel Xeon processors, this bit is reserved and should
be cleared to 0.
Suppress EOI Broadcasts
Determines whether an EOI for a level-triggered interrupt causes EOI messages to be broadcast to the I/O APICs (0) or not (1). See Section 10.8.5. The default value for this bit is 0, indicating that EOI broadcasts are performed. This bit is reserved to 0 if the processor does not
support EOI-broadcast suppression.
NOTE
Do not program an LVT or IOAPIC RTE with a spurious vector even if you set the mask bit. A
spurious vector ISR does not do an EOI. If for some reason an interrupt is generated by an LVT or
RTE entry, the bit in the in-service register will be left set for the spurious vector. This will mask all
interrupts at the same or lower priority
10.10
APIC BUS MESSAGE PASSING MECHANISM AND
PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS)
The Pentium 4 and Intel Xeon processors pass messages among the local and I/O APICs on the system bus, using
the system bus message passing mechanism and protocol.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
31
12 11 10 9 8 7
0
Reserved
EOI-Broadcast Suppression1
0: Disabled
1: Enabled
Focus Processor Checking2
0: Enabled
1: Disabled
APIC Software Enable/Disable
0: APIC Disabled
1: APIC Enabled
Spurious Vector3
Address: FEE0 00F0H
Value after reset: 0000 00FFH
1. Not supported on all processors.
2. Not supported in Pentium 4 and Intel Xeon processors.
3. For the P6 family and Pentium processors, bits 0 through 3
are always 0.
Figure 10-23. Spurious-Interrupt Vector Register (SVR)
The P6 family and Pentium processors, pass messages among the local and I/O APICs on the serial APIC bus, as
follows. Because only one message can be sent at a time on the APIC bus, the I/O APIC and local APICs employ a
“rotating priority” arbitration protocol to gain permission to send a message on the APIC bus. One or more APICs
may start sending their messages simultaneously. At the beginning of every message, each APIC presents the type
of the message it is sending and its current arbitration priority on the APIC bus. This information is used for arbitration. After each arbitration cycle (within an arbitration round), only the potential winners keep driving the bus.
By the time all arbitration cycles are completed, there will be only one APIC left driving the bus. Once a winner is
selected, it is granted exclusive use of the bus, and will continue driving the bus to send its actual message.
After each successfully transmitted message, all APICs increase their arbitration priority by 1. The previous winner
(that is, the one that has just successfully transmitted its message) assumes a priority of 0 (lowest). An agent
whose arbitration priority was 15 (highest) during arbitration, but did not send a message, adopts the previous
winner’s arbitration priority, increments by 1.
Note that the arbitration protocol described above is slightly different if one of the APICs issues a special End-OfInterrupt (EOI). This high-priority message is granted the bus regardless of its sender’s arbitration priority, unless
more than one APIC issues an EOI message simultaneously. In the latter case, the APICs sending the EOI
messages arbitrate using their arbitration priorities.
If the APICs are set up to use “lowest priority” arbitration (see Section 10.6.2.4, “Lowest Priority Delivery Mode”)
and multiple APICs are currently executing at the lowest priority (the value in the APR register), the arbitration
priorities (unique values in the Arb ID register) are used to break ties. All 8 bits of the APR are used for the lowest
priority arbitration.
10.10.1 Bus Message Formats
See Section 10.13, “APIC Bus Message Formats,” for a description of bus message formats used to transmit
messages on the serial APIC bus.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.11
MESSAGE SIGNALLED INTERRUPTS
The PCI Local Bus Specification, Rev 2.2 (www.pcisig.com) introduces the concept of message signalled interrupts.
As the specification indicates:
“Message signalled interrupts (MSI) is an optional feature that enables PCI devices to request
service by writing a system-specified message to a system-specified address (PCI DWORD memory
write transaction). The transaction address specifies the message destination while the transaction
data specifies the message. System software is expected to initialize the message destination and
message during device configuration, allocating one or more non-shared messages to each MSI
capable function.”
The capabilities mechanism provided by the PCI Local Bus Specification is used to identify and configure MSI
capable PCI devices. Among other fields, this structure contains a Message Data Register and a Message Address
Register. To request service, the PCI device function writes the contents of the Message Data Register to the
address contained in the Message Address Register (and the Message Upper Address register for 64-bit message
addresses).
Section 10.11.1 and Section 10.11.2 provide layout details for the Message Address Register and the Message Data
Register. The operation issued by the device is a PCI write command to the Message Address Register with the
Message Data Register contents. The operation follows semantic rules as defined for PCI write operations and is a
DWORD operation.
10.11.1 Message Address Register Format
The format of the Message Address Register (lower 32-bits) is shown in Figure 10-24.
31
20 19
0FEEH
12 11
Destination ID
4
Reserved
3
2
RH
DM
1
0
XX
Figure 10-24. Layout of the MSI Message Address Register
Fields in the Message Address Register are as follows:
1. Bits 31-20 — These bits contain a fixed value for interrupt messages (0FEEH). This value locates interrupts at
the 1-MByte area with a base address of 4G – 18M. All accesses to this region are directed as interrupt
messages. Care must to be taken to ensure that no other device claims the region as I/O space.
2. Destination ID — This field contains an 8-bit destination ID. It identifies the message’s target processor(s).
The destination ID corresponds to bits 63:56 of the I/O APIC Redirection Table Entry if the IOAPIC is used to
dispatch the interrupt to the processor(s).
3. Redirection hint indication (RH) — This bit indicates whether the message should be directed to the
processor with the lowest interrupt priority among processors that can receive the interrupt.
•
•
When RH is 0, the interrupt is directed to the processor listed in the Destination ID field.
When RH is 1 and the physical destination mode is used, the Destination ID field must not be set to FFH;
it must point to a processor that is present and enabled to receive the interrupt.
•
When RH is 1 and the logical destination mode is active in a system using a flat addressing model, the
Destination ID field must be set so that bits set to 1 identify processors that are present and enabled to
receive the interrupt.
•
If RH is set to 1 and the logical destination mode is active in a system using cluster addressing model,
then Destination ID field must not be set to FFH; the processors identified with this field must be
present and enabled to receive the interrupt.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
4. Destination mode (DM) — This bit indicates whether the Destination ID field should be interpreted as logical
or physical APIC ID for delivery of the lowest priority interrupt. If RH is 1 and DM is 0, the Destination ID field
is in physical destination mode and only the processor in the system that has the matching APIC ID is
considered for delivery of that interrupt (this means no re-direction). If RH is 1 and DM is 1, the Destination ID
Field is interpreted as in logical destination mode and the redirection is limited to only those processors that are
part of the logical group of processors based on the processor’s logical APIC ID and the Destination ID field in
the message. The logical group of processors consists of those identified by matching the 8-bit Destination ID
with the logical destination identified by the Destination Format Register and the Logical Destination Register
in each local APIC. The details are similar to those described in Section 10.6.2, “Determining IPI Destination.”
If RH is 0, then the DM bit is ignored and the message is sent ahead independent of whether the physical or
logical destination mode is used.
10.11.2 Message Data Register Format
The layout of the Message Data Register is shown in Figure 10-25.
63
32
Reserved
31
16
15
Reserved
Trigger Mode
0 - Edge
1 - Level
Level for Trigger Mode = 0
X - Don’t care
Level for Trigger Mode = 1
0 - Deassert
1 - Assert
14
13
Reserved
11 10
8
7
0
Vector
Delivery Mode
000 - Fixed
001 - Lowest Priority
010 - SMI
011 - Reserved
100 - NMI
101 - INIT
110 - Reserved
111 - ExtINT
Figure 10-25. Layout of the MSI Message Data Register
Reserved fields are not assumed to be any value. Software must preserve their contents on writes. Other fields in
the Message Data Register are described below.
1. Vector — This 8-bit field contains the interrupt vector associated with the message. Values range from 010H
to 0FEH. Software must guarantee that the field is not programmed with vector 00H to 0FH.
2. Delivery Mode — This 3-bit field specifies how the interrupt receipt is handled. Delivery Modes operate only in
conjunction with specified Trigger Modes. Correct Trigger Modes must be guaranteed by software. Restrictions
are indicated below:
a. 000B (Fixed Mode) — Deliver the signal to all the agents listed in the destination. The Trigger Mode for
fixed delivery mode can be edge or level.
b. 001B (Lowest Priority) — Deliver the signal to the agent that is executing at the lowest priority of all
agents listed in the destination field. The trigger mode can be edge or level.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
c.
010B (System Management Interrupt or SMI) — The delivery mode is edge only. For systems that rely
on SMI semantics, the vector field is ignored but must be programmed to all zeroes for future compatibility.
d. 100B (NMI) — Deliver the signal to all the agents listed in the destination field. The vector information is
ignored. NMI is an edge triggered interrupt regardless of the Trigger Mode Setting.
e. 101B (INIT) — Deliver this signal to all the agents listed in the destination field. The vector information is
ignored. INIT is an edge triggered interrupt regardless of the Trigger Mode Setting.
f.
111B (ExtINT) — Deliver the signal to the INTR signal of all agents in the destination field (as an interrupt
that originated from an 8259A compatible interrupt controller). The vector is supplied by the INTA cycle
issued by the activation of the ExtINT. ExtINT is an edge triggered interrupt.
3. Level — Edge triggered interrupt messages are always interpreted as assert messages. For edge triggered
interrupts this field is not used. For level triggered interrupts, this bit reflects the state of the interrupt input.
4. Trigger Mode — This field indicates the signal type that will trigger a message.
a. 0 — Indicates edge sensitive.
b. 1 — Indicates level sensitive.
10.12
EXTENDED XAPIC (X2APIC)
The x2APIC architecture extends the xAPIC architecture (described in Section 9.4) in a backward compatible
manner and provides forward extendability for future Intel platform innovations. Specifically, the x2APIC architecture does the following:
•
Retains all key elements of compatibility to the xAPIC architecture:
— delivery modes,
— interrupt and processor priorities,
— interrupt sources,
— interrupt destination types;
•
•
•
•
Provides extensions to scale processor addressability for both the logical and physical destination modes;
Adds new features to enhance performance of interrupt delivery;
Reduces complexity of logical destination mode interrupt delivery on link based platform architectures.
Uses MSR programming interface to access APIC registers in x2APIC mode instead of memory-mapped
interfaces. Memory-mapped interface is supported when operating in xAPIC mode.
10.12.1 Detecting and Enabling x2APIC Mode
Processor support for x2APIC mode can be detected by executing CPUID with EAX=1 and then checking ECX, bit 21
ECX. If CPUID.(EAX=1):ECX.21 is set , the processor supports the x2APIC capability and can be placed into the
x2APIC mode.
System software can place the local APIC in the x2APIC mode by setting the x2APIC mode enable bit (bit 10) in the
IA32_APIC_BASE MSR at MSR address 01BH. The layout for the IA32_APIC_BASE MSR is shown in Figure 10-26.
Table 10-5, “x2APIC operating mode configurations” describe the possible combinations of the enable bit (EN - bit
11) and the extended mode bit (EXTD - bit 10) in the IA32_APIC_BASE MSR.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
63
36 35
Reserved
12 11 10 9 8 7
0
APIC Base
APIC Base—Base physical address
EN—xAPIC global enable/disable
EXTD—Enable x2APIC mode
BSP—Processor is BSP
Reserved
Figure 10-26. IA32_APIC_BASE MSR Supporting x2APIC
Table 10-5. x2APIC Operating Mode Configurations
xAPIC global enable
(IA32_APIC_BASE[11])
x2APIC enable
(IA32_APIC_BASE[10])
Description
0
0
local APIC is disabled
0
1
Invalid
1
0
local APIC is enabled in xAPIC mode
1
1
local APIC is enabled in x2APIC mode
Once the local APIC has been switched to x2APIC mode (EN = 1, EXTD = 1), switching back to xAPIC mode would
require system software to disable the local APIC unit. Specifically, attempting to write a value to the
IA32_APIC_BASE MSR that has (EN= 1, EXTD = 0) when the local APIC is enabled and in x2APIC mode causes a
general-protection exception. Once bit 10 in IA32_APIC_BASE MSR is set, the only way to leave x2APIC mode
using IA32_APIC_BASE would require a WRMSR to set both bit 11 and bit 10 to zero. Section 10.12.5, “x2APIC
State Transitions” provides a detailed state diagram for the state transitions allowed for the local APIC.
10.12.1.1 Instructions to Access APIC Registers
In x2APIC mode, system software uses RDMSR and WRMSR to access the APIC registers. The MSR addresses for
accessing the x2APIC registers are architecturally defined and specified in Section 10.12.1.2, “x2APIC Register
Address Space”. Executing the RDMSR instruction with APIC register address specified in ECX returns the content
of bits 0 through 31 of the APIC registers in EAX. Bits 32 through 63 are returned in register EDX - these bits are
reserved if the APIC register being read is a 32-bit register. Similarly executing the WRMSR instruction with the
APIC register address in ECX, writes bits 0 to 31 of register EAX to bits 0 to 31 of the specified APIC register. If the
register is a 64-bit register then bits 0 to 31 of register EDX are written to bits 32 to 63 of the APIC register. The
Interrupt Command Register is the only APIC register that is implemented as a 64-bit MSR. The semantics of
handling reserved bits are defined in Section 10.12.1.3, “Reserved Bit Checking”.
10.12.1.2 x2APIC Register Address Space
The MSR address range 800H through BFFH is architecturally reserved and dedicated for accessing APIC registers
in x2APIC mode. Table 10-6 lists the APIC registers that are available in x2APIC mode. When appropriate, the table
also gives the offset at which each register is available on the page referenced by IA32_APIC_BASE[35:12] in
xAPIC mode.
There is a one-to-one mapping between the x2APIC MSRs and the legacy xAPIC register offsets with the following
exceptions:
•
The Destination Format Register (DFR): The DFR, supported at offset 0E0H in xAPIC mode, is not supported in
x2APIC mode. There is no MSR with address 80EH.
Vol. 3A 10-37
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•
The Interrupt Command Register (ICR): The two 32-bit registers in xAPIC mode (at offsets 300H and 310H) are
merged into a single 64-bit MSR in x2APIC mode (with MSR address 830H). There is no MSR with address
831H.
•
The SELF IPI register. This register is available only in x2APIC mode at address 83FH. In xAPIC mode, there is
no register defined at offset 3F0H.
Addresses in the range 800H–BFFH that are not listed in Table 10-6 (including 80EH and 831H) are reserved.
Executions of RDMSR and WRMSR that attempt to access such addresses cause general-protection exceptions.
The MSR address space is compressed to allow for future growth. Every 32 bit register on a 128-bit boundary in the
legacy MMIO space is mapped to a single MSR in the local x2APIC MSR address space. The upper 32-bits of all
x2APIC MSRs (except for the ICR) are reserved.
Table 10-6. Local APIC Register Address Map Supported by x2APIC
MSR Address
(x2APIC mode)
MMIO Offset
(xAPIC mode)
Register Name
MSR R/W
Semantics
802H
020H
Local APIC ID register
Read-only1
See Section 10.12.5.1 for initial
values.
803H
030H
Local APIC Version register
Read-only
Same version used in xAPIC mode
and x2APIC mode.
808H
080H
Task Priority Register (TPR)
Read/write
Bits 31:8 are reserved.2
80AH
0A0H
Processor Priority Register
(PPR)
Read-only
80BH
0B0H
EOI register
Write-only3
WRMSR of a non-zero value causes
#GP(0).
80DH
0D0H
Logical Destination Register
(LDR)
Read-only
Read/write in xAPIC mode.
80FH
0F0H
Spurious Interrupt Vector
Register (SVR)
Read/write
See Section 10.9 for reserved bits.
810H
100H
In-Service Register (ISR); bits
31:0
Read-only
811H
110H
ISR bits 63:32
Read-only
812H
120H
ISR bits 95:64
Read-only
813H
130H
ISR bits 127:96
Read-only
814H
140H
ISR bits 159:128
Read-only
815H
150H
ISR bits 191:160
Read-only
816H
160H
ISR bits 223:192
Read-only
817H
170H
ISR bits 255:224
Read-only
818H
180H
Trigger Mode Register (TMR);
bits 31:0
Read-only
819H
190H
TMR bits 63:32
Read-only
81AH
1A0H
TMR bits 95:64
Read-only
81BH
1B0H
TMR bits 127:96
Read-only
81CH
1C0H
TMR bits 159:128
Read-only
81DH
1D0H
TMR bits 191:160
Read-only
81EH
1E0H
TMR bits 223:192
Read-only
81FH
1F0H
TMR bits 255:224
Read-only
10-38 Vol. 3A
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 10-6. Local APIC Register Address Map Supported by x2APIC (Contd.)
MSR Address
(x2APIC mode)
MMIO Offset
(xAPIC mode)
820H
200H
Interrupt Request Register
(IRR); bits 31:0
Read-only
821H
210H
IRR bits 63:32
Read-only
822H
220H
IRR bits 95:64
Read-only
823H
230H
IRR bits 127:96
Read-only
824H
240H
IRR bits 159:128
Read-only
825H
250H
IRR bits 191:160
Read-only
826H
260H
IRR bits 223:192
Read-only
827H
270H
IRR bits 255:224
Read-only
828H
280H
Error Status Register (ESR)
Read/write
WRMSR of a non-zero value causes
#GP(0). See Section 10.5.3.
82FH
2F0H
LVT CMCI register
Read/write
See Figure 10-8 for reserved bits.
830H4
300H and 310H
Interrupt Command Register
(ICR)
Read/write
See Figure 10-28 for reserved bits
832H
320H
LVT Timer register
Read/write
See Figure 10-8 for reserved bits.
833H
330H
LVT Thermal Sensor register
Read/write
See Figure 10-8 for reserved bits.
834H
340H
LVT Performance Monitoring
register
Read/write
See Figure 10-8 for reserved bits.
835H
350H
LVT LINT0 register
Read/write
See Figure 10-8 for reserved bits.
836H
360H
LVT LINT1 register
Read/write
See Figure 10-8 for reserved bits.
837H
370H
LVT Error register
Read/write
See Figure 10-8 for reserved bits.
838H
380H
Initial Count register (for
Timer)
Read/write
839H
390H
Current Count register (for
Timer)
Read-only
83EH
3E0H
Divide Configuration Register
(DCR; for Timer)
Read/write
See Figure 10-10 for reserved bits.
83FH
Not available
SELF IPI5
Write-only
Available only in x2APIC mode.
Register Name
MSR R/W
Semantics
Comments
NOTES:
1. WRMSR causes #GP(0) for read-only registers.
2. WRMSR causes #GP(0) for attempts to set a reserved bit to 1 in a read/write register (including bits 63:32 of each register).
3. RDMSR causes #GP(0) for write-only registers.
4. MSR 831H is reserved; read/write operations cause general-protection exceptions. The contents of the APIC register at MMIO offset
310H are accessible in x2APIC mode through the MSR at address 830H.
5. SELF IPI register is supported only in x2APIC mode.
10.12.1.3 Reserved Bit Checking
Section 10.12.1.2 and Table 10-6 specifies the reserved bit definitions for the APIC registers in x2APIC mode. Nonzero writes (by WRMSR instruction) to reserved bits to these registers will raise a general protection fault exception
while reads return zeros (RsvdZ semantics).
In x2APIC mode, the local APIC ID register is increased to 32 bits wide. This enables 232–1 processors to be
addressable in physical destination mode. This 32-bit value is referred to as “x2APIC ID”. A processor implementa-
Vol. 3A 10-39
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
tion may choose to support less than 32 bits in its hardware. System software should be agnostic to the actual
number of bits that are implemented. All non-implemented bits will return zeros on reads by software.
The APIC ID value of FFFF_FFFFH and the highest value corresponding to the implemented bit-width of the local
APIC ID register in the system are reserved and cannot be assigned to any logical processor.
In x2APIC mode, the local APIC ID register is a read-only register to system software and will be initialized by hardware. It is accessed via the RDMSR instruction reading the MSR at address 0802H.
Each logical processor in the system (including clusters with a communication fabric) must be configured with an
unique x2APIC ID to avoid collisions of x2APIC IDs. On DP and high-end MP processors targeted to specific market
segments and depending on the system configuration, it is possible that logical processors in different and “unconnected” clusters power up initialized with overlapping x2APIC IDs. In these configurations, a model-specific
means may be provided in those product segments to enable BIOS and/or platform firmware to re-configure the
x2APIC IDs in some clusters to provide for unique and non-overlapping system wide IDs before configuring the
disconnected components into a single system.
10.12.2 x2APIC Register Availability
The local APIC registers can be accessed via the MSR interface only when the local APIC has been switched to the
x2APIC mode as described in Section 10.12.1. Accessing any APIC register in the MSR address range 0800H
through 0BFFH via RDMSR or WRMSR when the local APIC is not in x2APIC mode causes a general-protection
exception. In x2APIC mode, the memory mapped interface is not available and any access to the MMIO interface
will behave similar to that of a legacy xAPIC in globally disabled state. Table 10-7 provides the interactions between
the legacy & extended modes and the legacy and register interfaces.
Table 10-7. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation
MMIO Interface
MSR Interface
xAPIC mode
Available
General-protection exception
x2APIC mode
Behavior identical to xAPIC in globally disabled state
Available
10.12.3 MSR Access in x2APIC Mode
To allow for efficient access to the APIC registers in x2APIC mode, the serializing semantics of WRMSR are relaxed
when writing to the APIC registers. Thus, system software should not use “WRMSR to APIC registers in x2APIC
mode” as a serializing instruction. Read and write accesses to the APIC registers will occur in program order. A
WRMSR to an APIC register may complete before all preceding stores are globally visible; software can prevent this
by inserting a serializing instruction, an SFENCE, or an MFENCE before the WRMSR.
The RDMSR instruction is not serializing and this behavior is unchanged when reading APIC registers in x2APIC
mode. System software accessing the APIC registers using the RDMSR instruction should not expect a serializing
behavior. (Note: The MMIO-based xAPIC interface is mapped by system software as an un-cached region. Consequently, read/writes to the xAPIC-MMIO interface have serializing semantics in the xAPIC mode.)
10.12.4 VM-Exit Controls for MSRs and x2APIC Registers
The VMX architecture allows a VMM to specify lists of MSRs to be loaded or stored on VMX transitions using the
VMX-transition MSR areas (see VM-exit MSR-store address field, VM-exit MSR-load address field, and VM-entry
MSR-load address field in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C).
The X2APIC MSRs cannot to be loaded and stored on VMX transitions. A VMX transition fails if the VMM has specified
that the transition should access any MSRs in the address range from 0000_0800H to 0000_08FFH (the range used
for accessing the X2APIC registers). Specifically, processing of an 128-bit entry in any of the VMX-transition MSR
areas fails if bits 31:0 of that entry (represented as ENTRY_LOW_DW) satisfies the expression: “ENTRY_LOW_DW
& FFFFF800H = 00000800H”. Such a failure causes an associated VM entry to fail (by reloading host state) and
causes an associated VM exit to lead to VMX abort.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.12.5 x2APIC State Transitions
This section provides a detailed description of the x2APIC states of a local x2APIC unit, transitions between these
states as well as interactions of these states with INIT and reset.
10.12.5.1 x2APIC States
The valid states for a local x2APIC unit is listed in Table 10-5:
•
•
•
•
APIC disabled: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=0
xAPIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=0
x2APIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=1
Invalid: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=1
The state corresponding to EXTD=1 and EN=0 is not valid and it is not possible to get into this state. An execution
of WRMSR to the IA32_APIC_BASE_MSR that attempts a transition from a valid state to this invalid state causes a
general-protection exception. Figure 10-27 shows the comprehensive state transition diagram for a local x2APIC
unit.
On coming out of reset, the local APIC unit is enabled and is in the xAPIC mode: IA32_APIC_BASE[EN]=1 and
IA32_APIC_BASE[EXTD]=0. The APIC registers are initialized as:
•
The local APIC ID is initialized by hardware with a 32 bit ID (x2APIC ID). The lowest 8 bits of the x2APIC ID is
the legacy local xAPIC ID, and is stored in the upper 8 bits of the APIC register for access in xAPIC mode.
•
The following APIC registers are reset to all zeros for those fields that are defined in the xAPIC mode:
— IRR, ISR, TMR, ICR, LDR, TPR, Divide Configuration Register (See Chapter 8 of “Intel® 64 and IA-32 Architectures Software Developer’s Manual“, Vol. 3B for details of individual APIC registers),
— Timer initial count and timer current count registers,
•
•
•
•
•
The LVT registers are reset to 0s except for the mask bits; these are set to 1s.
The local APIC version register is not affected.
The Spurious Interrupt Vector Register is initialized to 000000FFH.
The DFR (available only in xAPIC mode) is reset to all 1s.
SELF IPI register is reset to zero.
Vol. 3A 10-41
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Reset
Init
Disabled
EN = 0
Extd = 0
EN =1
xAPIC Mode
EN = 0
EN=1, Extd=0
Reset
Extd = 1
Init
EN = 0
Extd = 0
Illegal
Transition
Extd = 1
Illegal
Transition
Extd = 1
Illegal
Transition
Extd = 0
Invalid
State
EN = 0
Illegal
Transition
EN = 0
Extended
Mode
EN=1, Extd=1
Reset
Init
Figure 10-27. Local x2APIC State Transitions with IA32_APIC_BASE, INIT, and Reset
x2APIC After Reset
The valid transitions from the xAPIC mode state are:
•
to the x2APIC mode by setting EXT to 1 (resulting EN=1, EXTD= 1). The physical x2APIC ID (see Figure 10-6)
is preserved across this transition and the logical x2APIC ID (see Figure 10-29) is initialized by hardware during
this transition as documented in Section 10.12.10.2. The state of the extended fields in other APIC registers,
which was not initialized at reset, is not architecturally defined across this transition and system software
should explicitly initialize those programmable APIC registers.
•
to the disabled state by setting EN to 0 (resulting EN=0, EXTD= 0).
The result of an INIT in the xAPIC state places the APIC in the state with EN= 1, EXTD= 0. The state of the local
APIC ID register is preserved (the 8-bit xAPIC ID is in the upper 8 bits of the APIC ID register). All the other APIC
registers are initialized as a result of INIT.
A reset in this state places the APIC in the state with EN= 1, EXTD= 0. The state of the local APIC ID register is
initialized as described in Section 10.12.5.1. All the other APIC registers are initialized described in Section
10.12.5.1.
x2APIC Transitions From x2APIC Mode
From the x2APIC mode, the only valid x2APIC transition using IA32_APIC_BASE is to the state where the x2APIC
is disabled by setting EN to 0 and EXTD to 0. The x2APIC ID (32 bits) and the legacy local xAPIC ID (8 bits) are
preserved across this transition. A transition from the x2APIC mode to xAPIC mode is not valid, and the corresponding WRMSR to the IA32_APIC_BASE MSR causes a general-protection exception.
A reset in this state places the x2APIC in xAPIC mode. All APIC registers (including the local APIC ID register) are
initialized as described in Section 10.12.5.1.
An INIT in this state keeps the x2APIC in the x2APIC mode. The state of the local APIC ID register is preserved (all
32 bits). However, all the other APIC registers are initialized as a result of the INIT transition.
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
x2APIC Transitions From Disabled Mode
From the disabled state, the only valid x2APIC transition using IA32_APIC_BASE is to the xAPIC mode (EN= 1,
EXTD = 0). Thus the only means to transition from x2APIC mode to xAPIC mode is a two-step process:
•
•
first transition from x2APIC mode to local APIC disabled mode (EN= 0, EXTD = 0),
followed by another transition from disabled mode to xAPIC mode (EN= 1, EXTD= 0).
Consequently, all the APIC register states in the x2APIC, except for the x2APIC ID (32 bits), are not preserved
across mode transitions.
A reset in the disabled state places the x2APIC in the xAPIC mode. All APIC registers (including the local APIC ID
register) are initialized as described in Section 10.12.5.1.
An INIT in the disabled state keeps the x2APIC in the disabled state.
State Changes From xAPIC Mode to x2APIC Mode
After APIC register states have been initialized by software in xAPIC mode, a transition from xAPIC mode to x2APIC
mode does not affect most of the APIC register states, except the following:
•
•
•
The Logical Destination Register is not preserved.
Any APIC ID value written to the memory-mapped local APIC ID register is not preserved.
The high half of the Interrupt Command Register is not preserved.
10.12.6 Routing of Device Interrupts in x2APIC Mode
The x2APIC architecture is intended to work with all existing IOxAPIC units as well as all PCI and PCI Express
(PCIe) devices that support the capability for message-signaled interrupts (MSI). Support for x2APIC modifies only
the following:
•
•
•
the local APIC units;
the interconnects joining IOxAPIC units to the local APIC units; and
the interconnects joining MSI-capable PCI and PCIe devices to the local APIC units.
No modifications are required to MSI-capable PCI and PCIe devices. Similarly, no modifications are required to
IOxAPIC units. This made possible through use of the interrupt-remapping architecture specified in the Intel®
Virtualization Technology for Directed I/O, Revision 1.3 for the routing of interrupts from MSI-capable devices to
local APIC units operating in x2APIC mode.
10.12.7 Initialization by System Software
Routing of device interrupts to local APIC units operating in x2APIC mode requires use of the interrupt-remapping
architecture specified in the Intel® Virtualization Technology for Directed I/O, Revision 1.3. Because of this, BIOS
must enumerate support for and software must enable this interrupt remapping with Extended Interrupt Mode
Enabled before it enabling x2APIC mode in the local APIC units.
The ACPI interfaces for the x2APIC are described in Section 5.2, “ACPI System Description Tables,” of the Advanced
Configuration and Power Interface Specification, Revision 4.0a (http://www.acpi.info/spec.htm). The default
behavior for BIOS is to pass the control to the operating system with the local x2APICs in xAPIC mode if all APIC
IDs reported by CPUID.0BH:EDX are less than 255, and in x2APIC mode if there are any logical processor reporting
an APIC ID of 255 or greater.
10.12.8 CPUID Extensions And Topology Enumeration
For Intel 64 and IA-32 processors that support x2APIC, a value of 1 reported by CPUID.01H:ECX[21] indicates that
the processor supports x2APIC and the extended topology enumeration leaf (CPUID.0BH).
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ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The extended topology enumeration leaf can be accessed by executing CPUID with EAX = 0BH. Processors that do
not support x2APIC may support CPUID leaf 0BH. Software can detect the availability of the extended topology
enumeration leaf (0BH) by performing two steps:
•
Check maximum input value for basic CPUID information by executing CPUID with EAX= 0. If CPUID.0H:EAX is
greater than or equal or 11 (0BH), then proceed to next step
•
Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topology enumeration leaf is available. If available, the extended
topology enumeration leaf is the preferred mechanism for enumerating topology. The presence of CPUID leaf 0BH
in a processor does not guarantee support for x2APIC. If CPUID.EAX=0BH, ECX=0H:EBX returns zero and
maximum input value for basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not supported on
that processor.
The extended topology enumeration leaf is intended to assist software with enumerating processor topology on
systems that requires 32-bit x2APIC IDs to address individual logical processors. Details of CPUID leaf 0BH can be
found in the reference pages of CPUID in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A.
Processor topology enumeration algorithm for processors supporting the extended topology enumeration leaf of
CPUID and processors that do not support CPUID leaf 0BH are treated in Section 8.9.4, “Algorithm for Three-Level
Mappings of APIC_ID”.
10.12.8.1 Consistency of APIC IDs and CPUID
The consistency of physical x2APIC ID in MSR 802H in x2APIC mode and the 32-bit value returned in
CPUID.0BH:EDX is facilitated by processor hardware.
CPUID.0BH:EDX will report the full 32 bit ID, in xAPIC and x2APIC mode. This allows BIOS to determine if a system
has processors with IDs exceeding the 8-bit initial APIC ID limit (CPUID.01H:EBX[31:24]). Initial APIC ID
(CPUID.01H:EBX[31:24]) is always equal to CPUID.0BH:EDX[7:0].
If the values of CPUID.0BH:EDX reported by all logical processors in a system are less than 255, BIOS can transfer
control to OS in xAPIC mode.
If the values of CPUID.0BH:EDX reported by some logical processors in a system are greater or equal than 255,
BIOS must support two options to hand off to OS:
•
If BIOS enables logical processors with x2APIC IDs greater than 255, then it should enable X2APIC in Boot
Strap Processor (BSP) and all Application Processors (AP) before passing control to the OS. Application
requiring processor topology information must use OS provided services based on x2APIC IDs or CPUID.0BH
leaf.
•
If a BIOS transfers control to OS in xAPIC mode, then the BIOS must ensure that only logical processors with
CPUID.0BH.EDX value less than 255 are enabled. BIOS initialization on all logical processors with
CPUID.0B.EDX values greater than or equal to 255 must (a) disable APIC and execute CLI in each logical
processor, and (b) leave these logical processor in the lowest power state so that these processors do not
respond to INIT IPI during OS boot. The BSP and all the enabled logical processor operate in xAPIC mode after
BIOS passed control to OS. Application requiring processor topology information can use OS provided legacy
services based on 8-bit initial APIC IDs or legacy topology information from CPUID.01H and CPUID 04H leaves.
Even if the BIOS passes control in xAPIC mode, an OS can switch the processors to x2APIC mode later. BIOS
SMM handler should always read the APIC_BASE_MSR, determine the APIC mode and use the corresponding
access method.
10.12.9 ICR Operation in x2APIC Mode
In x2APIC mode, the layout of the Interrupt Command Register is shown in Figure 10-12. The lower 32 bits of ICR
in x2APIC mode is identical to the lower half of the ICR in xAPIC mode, except the Delivery Status bit is removed
since it is not needed in x2APIC mode. The destination ID field is expanded to 32 bits in x2APIC mode.
To send an IPI using the ICR, software must set up the ICR to indicate the type of IPI message to be sent and the
destination processor or processors. Self IPIs can also be sent using the SELF IPI register (see Section 10.12.11).
10-44 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
63
32
Destination Field
31
20 19 18 17 16 15 14 13 12 11 10
Reserved
Destination Shorthand
00: No Shorthand
01: Self
10: All Including Self
11: All Excluding Self
Reserved
8 7
0
Vector
Delivery Mode
000: Fixed
001: Reserved
010: SMI
011: Reserved
100: NMI
101: INIT
110: Start Up
111: Reserved
Destination Mode
0: Physical
1: Logical
Address: 830H (63 - 0)
Value after Reset: 0H
Level
0 = De-assert
1 = Assert
Trigger Mode
0: Edge
1: Level
Figure 10-28. Interrupt Command Register (ICR) in x2APIC Mode
A single MSR write to the Interrupt Command Register is required for dispatching an interrupt in x2APIC mode.
With the removal of the Delivery Status bit, system software no longer has a reason to read the ICR. It remains
readable only to aid in debugging; however, software should not assume the value returned by reading the ICR is
the last written value.
A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both logical destination and physical
destination modes.
10.12.10 Determining IPI Destination in x2APIC Mode
10.12.10.1 Logical Destination Mode in x2APIC Mode
In x2APIC mode, the Logical Destination Register (LDR) is increased to 32 bits wide. It is a read-only register to
system software. This 32-bit value is referred to as “logical x2APIC ID”. System software accesses this register via
the RDMSR instruction reading the MSR at address 80DH. Figure 10-29 provides the layout of the Logical Destination Register in x2APIC mode.
Vol. 3A 10-45
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
MSR Address: 80DH
31
0
Logical x2APIC ID
Figure 10-29. Logical Destination Register in x2APIC Mode
In the xAPIC mode, the Destination Format Register (DFR) through MMIO interface determines the choice of a flat
logical mode or a clustered logical mode. Flat logical mode is not supported in the x2APIC mode. Hence the Destination Format Register (DFR) is eliminated in x2APIC mode.
The 32-bit logical x2APIC ID field of LDR is partitioned into two sub-fields:
•
•
Cluster ID (LDR[31:16]): is the address of the destination cluster
Logical ID (LDR[15:0]): defines a logical ID of the individual local x2APIC within the cluster specified by
LDR[31:16].
This layout enables 2^16-1 clusters each with up to 16 unique logical IDs - effectively providing an addressability
of ((2^20) - 16) processors in logical destination mode.
It is likely that processor implementations may choose to support less than 16 bits of the cluster ID or less than 16bits of the Logical ID in the Logical Destination Register. However system software should be agnostic to the
number of bits implemented in the cluster ID and logical ID sub-fields. The x2APIC hardware initialization will
ensure that the appropriately initialized logical x2APIC IDs are available to system software and reads of nonimplemented bits return zero. This is a read-only register that software must read to determine the logical x2APIC
ID of the processor. Specifically, software can apply a 16-bit mask to the lowest 16 bits of the logical x2APIC ID to
identify the logical address of a processor within a cluster without needing to know the number of implemented bits
in cluster ID and Logical ID sub-fields. Similarly, software can create a message destination address for cluster
model, by bit-Oring the Logical X2APIC ID (31:0) of processors that have matching Cluster ID(31:16).
To enable cluster ID assignment in a fashion that matches the system topology characteristics and to enable efficient routing of logical mode lowest priority device interrupts in link based platform interconnects, the LDR are
initialized by hardware based on the value of x2APIC ID upon x2APIC state transitions. Details of this initialization
are provided in Section 10.12.10.2.
10.12.10.2 Deriving Logical x2APIC ID from the Local x2APIC ID
In x2APIC mode, the 32-bit logical x2APIC ID, which can be read from LDR, is derived from the 32-bit local x2APIC
ID. Specifically, the 16-bit logical ID sub-field is derived by shifting 1 by the lowest 4 bits of the x2APIC ID, i.e.
Logical ID = 1 « x2APIC ID[3:0]. The remaining bits of the x2APIC ID then form the cluster ID portion of the logical
x2APIC ID:
Logical x2APIC ID = [(x2APIC ID[19:4] « 16) | (1 « x2APIC ID[3:0])]
The use of the lowest 4 bits in the x2APIC ID implies that at least 16 APIC IDs are reserved for logical processors
within a socket in multi-socket configurations. If more than 16 APIC IDS are reserved for logical processors in a
socket/package then multiple cluster IDs can exist within the package.
The LDR initialization occurs whenever the x2APIC mode is enabled (see Section 10.12.5).
10-46 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.12.11 SELF IPI Register
SELF IPIs are used extensively by some system software. The x2APIC architecture introduces a new register interface. This new register is dedicated to the purpose of sending self-IPIs with the intent of enabling a highly optimized path for sending self-IPIs.
Figure 10-30 provides the layout of the SELF IPI register. System software only specifies the vector associated with
the interrupt to be sent. The semantics of sending a self-IPI via the SELF IPI register are identical to sending a self
targeted edge triggered fixed interrupt with the specified vector. Specifically the semantics are identical to the
following settings for an inter-processor interrupt sent via the ICR - Destination Shorthand (ICR[19:18] = 01
(Self)), Trigger Mode (ICR[15] = 0 (Edge)), Delivery Mode (ICR[10:8] = 000 (Fixed)), Vector (ICR[7:0] = Vector).
MSR Address: 083FH
31
8 7
0
Vector
Reserved
Figure 10-30. SELF IPI register
The SELF IPI register is a write-only register. A RDMSR instruction with address of the SELF IPI register causes a
general-protection exception.
The handling and prioritization of a self-IPI sent via the SELF IPI register is architecturally identical to that for an
IPI sent via the ICR from a legacy xAPIC unit. Specifically the state of the interrupt would be tracked via the Interrupt Request Register (IRR) and In Service Register (ISR) and Trigger Mode Register (TMR) as if it were received
from the system bus. Also sending the IPI via the Self Interrupt Register ensures that interrupt is delivered to the
processor core. Specifically completion of the WRMSR instruction to the SELF IPI register implies that the interrupt
has been logged into the IRR. As expected for edge triggered interrupts, depending on the processor priority and
readiness to accept interrupts, it is possible that interrupts sent via the SELF IPI register or via the ICR with identical vectors can be combined.
10.13
APIC BUS MESSAGE FORMATS
This section describes the message formats used when transmitting messages on the serial APIC bus. The information described here pertains only to the Pentium and P6 family processors.
10.13.1 Bus Message Formats
The local and I/O APICs transmit three types of messages on the serial APIC bus: EOI message, short message,
and non-focused lowest priority message. The purpose of each type of message and its format are described
below.
10.13.2 EOI Message
Local APICs send 14-cycle EOI messages to the I/O APIC to indicate that a level triggered interrupt has been
accepted by the processor. This interrupt, in turn, is a result of software writing into the EOI register of the local
APIC. Table 10-1 shows the cycles in an EOI message.
Table 10-1. EOI Message (14 Cycles)
Cycle
Bit1
Bit0
1
1
1
11 = EOI
2
ArbID3
0
Arbitration ID bits 3 through 0
Vol. 3A 10-47
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 10-1. EOI Message (14 Cycles) (Contd.)
Cycle
Bit1
Bit0
3
ArbID2
0
4
ArbID1
0
5
ArbID0
0
6
V7
V6
7
V5
V4
8
V3
V2
9
V1
V0
Interrupt vector V7 - V0
10
C
C
11
0
0
Checksum for cycles 6 - 9
12
A
A
Status Cycle 0
13
A1
A1
Status Cycle 1
14
0
0
Idle
The checksum is computed for cycles 6 through 9. It is a cumulative sum of the 2-bit (Bit1:Bit0) logical data values.
The carry out of all but the last addition is added to the sum. If any APIC computes a different checksum than the
one appearing on the bus in cycle 10, it signals an error, driving 11 on the APIC bus during cycle 12. In this case,
the APICs disregard the message. The sending APIC will receive an appropriate error indication (see Section
10.5.3, “Error Handling”) and resend the message. The status cycles are defined in Table 10-4.
10.13.2.1 Short Message
Short messages (21-cycles) are used for sending fixed, NMI, SMI, INIT, start-up, ExtINT and lowest-priority-withfocus interrupts. Table 10-2 shows the cycles in a short message.
Table 10-2. Short Message (21 Cycles)
Cycle
Bit1
Bit0
1
0
1
0 1 = normal
2
ArbID3
0
Arbitration ID bits 3 through 0
3
ArbID2
0
4
ArbID1
0
5
ArbID0
0
6
DM
M2
DM = Destination Mode
7
M1
M0
M2-M0 = Delivery mode
8
L
TM
L = Level, TM = Trigger Mode
9
V7
V6
V7-V0 = Interrupt Vector
10
V5
V4
11
V3
V2
12
V1
V0
13
D7
D6
14
D5
D4
15
D3
D2
16
D1
D0
10-48 Vol. 3A
D7-D0 = Destination
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 10-2. Short Message (21 Cycles) (Contd.)
Cycle
Bit1
Bit0
17
C
C
Checksum for cycles 6-16
18
0
0
19
A
A
Status cycle 0
20
A1
A1
Status cycle 1
21
0
0
Idle
If the physical delivery mode is being used, then cycles 15 and 16 represent the APIC ID and cycles 13 and 14 are
considered don't care by the receiver. If the logical delivery mode is being used, then cycles 13 through 16 are the
8-bit logical destination field.
For shorthands of “all-incl-self” and “all-excl-self,” the physical delivery mode and an arbitration priority of 15
(D0:D3 = 1111) are used. The agent sending the message is the only one required to distinguish between the two
cases. It does so using internal information.
When using lowest priority delivery with an existing focus processor, the focus processor identifies itself by driving
10 during cycle 19 and accepts the interrupt. This is an indication to other APICs to terminate arbitration. If the
focus processor has not been found, the short message is extended on-the-fly to the non-focused lowest-priority
message. Note that except for the EOI message, messages generating a checksum or an acceptance error (see
Section 10.5.3, “Error Handling”) terminate after cycle 21.
10.13.2.2 Non-focused Lowest Priority Message
These 34-cycle messages (see Table 10-3) are used in the lowest priority delivery mode when a focus processor is
not present. Cycles 1 through 20 are same as for the short message. If during the status cycle (cycle 19) the state
of the (A:A) flags is 10B, a focus processor has been identified, and the short message format is used (see Table
10-2). If the (A:A) flags are set to 00B, lowest priority arbitration is started and the 34-cycles of the non-focused
lowest priority message are competed. For other combinations of status flags, refer to Section 10.13.2.3, “APIC
Bus Status Cycles.”
Table 10-3. Non-Focused Lowest Priority Message (34 Cycles)
Cycle
Bit0
Bit1
1
0
1
0 1 = normal
2
ArbID3
0
Arbitration ID bits 3 through 0
3
ArbID2
0
4
ArbID1
0
5
ArbID0
0
6
DM
M2
DM = Destination mode
7
M1
M0
M2-M0 = Delivery mode
8
L
TM
L = Level, TM = Trigger Mode
9
V7
V6
V7-V0 = Interrupt Vector
10
V5
V4
11
V3
V2
12
V1
V0
13
D7
D6
14
D5
D4
15
D3
D2
16
D1
D0
D7-D0 = Destination
Vol. 3A 10-49
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 10-3. Non-Focused Lowest Priority Message (34 Cycles) (Contd.)
Cycle
Bit0
Bit1
17
C
C
Checksum for cycles 6-16
18
0
0
19
A
A
Status cycle 0
20
A1
A1
Status cycle 1
21
P7
0
22
P6
0
23
P5
0
24
P4
0
25
P3
0
26
P2
0
27
P1
0
28
P0
0
29
ArbID3
0
30
ArbID2
0
31
ArbID1
0
32
ArbID0
0
33
A2
A2
34
0
0
P7 - P0 = Inverted Processor Priority
Arbitration ID 3 -0
Status Cycle
Idle
Cycles 21 through 28 are used to arbitrate for the lowest priority processor. The processors participating in the
arbitration drive their inverted processor priority on the bus. Only the local APICs having free interrupt slots participate in the lowest priority arbitration. If no such APIC exists, the message will be rejected, requiring it to be tried
at a later time.
Cycles 29 through 32 are also used for arbitration in case two or more processors have the same lowest priority. In
the lowest priority delivery mode, all combinations of errors in cycle 33 (A2 A2) will set the “accept error” bit in the
error status register (see Figure 10-9). Arbitration priority update is performed in cycle 20, and is not affected by
errors detected in cycle 33. Only the local APIC that wins in the lowest priority arbitration, drives cycle 33. An error
in cycle 33 will force the sender to resend the message.
10.13.2.3 APIC Bus Status Cycles
Certain cycles within an APIC bus message are status cycles. During these cycles the status flags (A:A) and
(A1:A1) are examined. Table 10-4 shows how these status flags are interpreted, depending on the current delivery
mode and existence of a focus processor.
10-50 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 10-4. APIC Bus Status Cycles Interpretation
Delivery
Mode
A Status
A1 Status
A2 Status
Update ArbID Message
and Cycle#
Length
EOI
00: CS_OK
10: Accept
XX:
Yes, 13
14 Cycle
No
00: CS_OK
11: Retry
XX:
Yes, 13
14 Cycle
Yes
00: CS_OK
0X: Accept Error
XX:
No
14 Cycle
Yes
11: CS_Error
XX:
XX:
No
14 Cycle
Yes
10: Error
XX:
XX:
No
14 Cycle
Yes
01: Error
XX:
XX:
No
14 Cycle
Yes
00: CS_OK
10: Accept
XX:
Yes, 20
21 Cycle
No
00: CS_OK
11: Retry
XX:
Yes, 20
21 Cycle
Yes
00: CS_OK
0X: Accept Error
XX:
No
21 Cycle
Yes
11: CS_Error
XX:
XX:
No
21 Cycle
Yes
10: Error
XX:
XX:
No
21 Cycle
Yes
Fixed
NMI, SMI, INIT,
ExtINT,
Start-Up
Lowest
Retry
01: Error
XX:
XX:
No
21 Cycle
Yes
00: CS_OK
10: Accept
XX:
Yes, 20
21 Cycle
No
00: CS_OK
11: Retry
XX:
Yes, 20
21 Cycle
Yes
00: CS_OK
0X: Accept Error
XX:
No
21 Cycle
Yes
11: CS_Error
XX:
XX:
No
21 Cycle
Yes
10: Error
XX:
XX:
No
21 Cycle
Yes
01: Error
XX:
XX:
No
21 Cycle
Yes
00: CS_OK, NoFocus
11: Do Lowest
10: Accept
Yes, 20
34 Cycle
No
00: CS_OK, NoFocus
11: Do Lowest
11: Error
Yes, 20
34 Cycle
Yes
00: CS_OK, NoFocus
11: Do Lowest
0X: Error
Yes, 20
34 Cycle
Yes
00: CS_OK, NoFocus
10: End and Retry
XX:
Yes, 20
34 Cycle
Yes
00: CS_OK, NoFocus
0X: Error
XX:
No
34 Cycle
Yes
10: CS_OK, Focus
XX:
XX:
Yes, 20
34 Cycle
No
11: CS_Error
XX:
XX:
No
21 Cycle
Yes
01: Error
XX:
XX:
No
21 Cycle
Yes
Vol. 3A 10-51
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10-52 Vol. 3A
CHAPTER 11
MEMORY CACHE CONTROL
This chapter describes the memory cache and cache control mechanisms, the TLBs, and the store buffer in Intel 64
and IA-32 processors. It also describes the memory type range registers (MTRRs) introduced in the P6 family
processors and how they are used to control caching of physical memory locations.
11.1
INTERNAL CACHES, TLBS, AND BUFFERS
The Intel 64 and IA-32 architectures support cache, translation look aside buffers (TLBs), and a store buffer for
temporary on-chip (and external) storage of instructions and data. (Figure 11-1 shows the arrangement of caches,
TLBs, and the store buffer for the Pentium 4 and Intel Xeon processors.) Table 11-1 shows the characteristics of
these caches and buffers for the Pentium 4, Intel Xeon, P6 family, and Pentium processors. The sizes and characteristics of these units are machine specific and may change in future versions of the processor. The
CPUID instruction returns the sizes and characteristics of the caches and buffers for the processor on which the
instruction is executed. See “CPUID—CPU Identification” in Chapter 3, “Instruction Set Reference, A-L,” of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Physical
Memory
System Bus
(External)
L3 Cache†
L2 Cache
Data Cache
Unit (L1)
Instruction
TLBs
Bus Interface Unit
Data TLBs
Instruction Decoder
Trace Cache
Store Buffer
† Intel Xeon processors only
Figure 11-1. Cache Structure of the Pentium 4 and Intel Xeon Processors
Vol. 3A 11-1
MEMORY CACHE CONTROL
Instruction Decoder and front end
ITLB
Instruction
Cache
Chipset
Out-of-Order Engine
QPI
Data TLB
Data Cache
Unit (L1)
STLB
IMC
L2 Cache
L3 Cache
Figure 11-2. Cache Structure of the Intel Core i7 Processors
Figure 11-2 shows the cache arrangement of Intel Core i7 processor.
Table 11-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in Intel 64 and IA-32 Processors
Cache or Buffer
Trace
Cache1
Characteristics
• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst® microarchitecture): 12 Kμops, 8-way set
associative.
• Intel Core i7, Intel Core 2 Duo, Intel® Atom™, Intel Core Duo, Intel Core Solo, Pentium M processor: not
implemented.
• P6 family and Pentium processors: not implemented.
L1 Instruction Cache • Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): not implemented.
• Intel Core i7 processor: 32-KByte, 4-way set associative.
• Intel Core 2 Duo, Intel Atom, Intel Core Duo, Intel Core Solo, Pentium M processor: 32-KByte, 8-way set
associative.
• P6 family and Pentium processors: 8- or 16-KByte, 4-way set associative, 32-byte cache line size; 2-way set
associative for earlier Pentium processors.
L1 Data Cache
11-2 Vol. 3A
• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): 8-KByte, 4-way set
associative, 64-byte cache line size.
• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): 16-KByte, 8-way set
associative, 64-byte cache line size.
• Intel Atom processors: 24-KByte, 6-way set associative, 64-byte cache line size.
• Intel Core i7, Intel Core 2 Duo, Intel Core Duo, Intel Core Solo, Pentium M and Intel Xeon processors: 32KByte, 8-way set associative, 64-byte cache line size.
• P6 family processors: 16-KByte, 4-way set associative, 32-byte cache line size; 8-KBytes, 2-way set
associative for earlier P6 family processors.
• Pentium processors: 16-KByte, 4-way set associative, 32-byte cache line size; 8-KByte, 2-way set
associative for earlier Pentium processors.
MEMORY CACHE CONTROL
Table 11-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in Intel 64 and IA-32 Processors (Contd.)
Cache or Buffer
Characteristics
L2 Unified Cache
• Intel Core 2 Duo and Intel Xeon processors: up to 4-MByte (or 4MBx2 in quadcore processors), 16-way set
associative, 64-byte cache line size.
• Intel Core 2 Duo and Intel Xeon processors: up to 6-MByte (or 6MBx2 in quadcore processors), 24-way set
associative, 64-byte cache line size.
• Intel Core i7, i5, i3 processors: 256KBbyte, 8-way set associative, 64-byte cache line size.
• Intel Atom processors: 512-KByte, 8-way set associative, 64-byte cache line size.
• Intel Core Duo, Intel Core Solo processors: 2-MByte, 8-way set associative, 64-byte cache line size
• Pentium 4 and Intel Xeon processors: 256, 512, 1024, or 2048-KByte, 8-way set associative, 64-byte cache
line size, 128-byte sector size.
• Pentium M processor: 1 or 2-MByte, 8-way set associative, 64-byte cache line size.
• P6 family processors: 128-KByte, 256-KByte, 512-KByte, 1-MByte, or 2-MByte, 4-way set associative,
32-byte cache line size.
• Pentium processor (external optional): System specific, typically 256- or 512-KByte, 4-way set associative,
32-byte cache line size.
L3 Unified Cache
• Intel Xeon processors: 512-KByte, 1-MByte, 2-MByte, or 4-MByte, 8-way set associative, 64-byte cache line
size, 128-byte sector size.
• Intel Core i7 processor, Intel Xeon processor 5500: Up to 8MByte, 16-way set associative, 64-byte cache
line size.
• Intel Xeon processor 5600: Up to 12MByte, 64-byte cache line size.
• Intel Xeon processor 7500: Up to 24MByte, 64-byte cache line size.
Instruction TLB
(4-KByte Pages)
• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): 128 entries, 4-way set
associative.
• Intel Atom processors: 32-entries, fully associative.
• Intel Core i7, i5, i3 processors: 64-entries per thread (128-entries per core), 4-way set associative.
• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128 entries, 4-way set
associative.
• P6 family processors: 32 entries, 4-way set associative.
• Pentium processor: 32 entries, 4-way set associative; fully set associative for Pentium processors with MMX
technology.
Data TLB (4-KByte
Pages)
• Intel Core i7, i5, i3 processors, DTLB0: 64-entries, 4-way set associative.
• Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 256 entries, 4 ways.
• Intel Atom processors: 16-entry-per-thread micro-TLB, fully associative; 64-entry DTLB, 4-way set
associative; 16-entry PDE cache, fully associative.
• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): 64 entry, fully set
associative, shared with large page DTLB.
• Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128 entries, 4-way set associative.
• Pentium and P6 family processors: 64 entries, 4-way set associative; fully set, associative for Pentium
processors with MMX technology.
Instruction TLB
(Large Pages)
•
•
•
•
•
•
Intel Core i7, i5, i3 processors: 7-entries per thread, fully associative.
Intel Core 2 Duo processors: 4 entries, 4 ways.
Pentium 4 and Intel Xeon processors: large pages are fragmented.
Intel Core Duo, Intel Core Solo, Pentium M processor: 2 entries, fully associative.
P6 family processors: 2 entries, fully associative.
Pentium processor: Uses same TLB as used for 4-KByte pages.
Data TLB (Large
Pages)
•
•
•
•
•
•
•
Intel Core i7, i5, i3 processors, DTLB0: 32-entries, 4-way set associative.
Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 32 entries, 4 ways.
Intel Atom processors: 8 entries, 4-way set associative.
Pentium 4 and Intel Xeon processors: 64 entries, fully set associative; shared with small page data TLBs.
Intel Core Duo, Intel Core Solo, Pentium M processor: 8 entries, fully associative.
P6 family processors: 8 entries, 4-way set associative.
Pentium processor: 8 entries, 4-way set associative; uses same TLB as used for 4-KByte pages in Pentium
processors with MMX technology.
Second-level Unified
TLB (4-KByte
Pages)
• Intel Core i7, i5, i3 processor, STLB: 512-entries, 4-way set associative.
Vol. 3A 11-3
MEMORY CACHE CONTROL
Table 11-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in Intel 64 and IA-32 Processors (Contd.)
Cache or Buffer
Characteristics
Store Buffer
•
•
•
•
•
•
•
Intel Core i7, i5, i3 processors: 32entries.
Intel Core 2 Duo processors: 20 entries.
Intel Atom processors: 8 entries, used for both WC and store buffers.
Pentium 4 and Intel Xeon processors: 24 entries.
Pentium M processor: 16 entries.
P6 family processors: 12 entries.
Pentium processor: 2 buffers, 1 entry each (Pentium processors with MMX technology have 4 buffers for 4
entries).
Write Combining
(WC) Buffer
•
•
•
•
•
Intel Core 2 Duo processors: 8 entries.
Intel Atom processors: 8 entries, used for both WC and store buffers.
Pentium 4 and Intel Xeon processors: 6 or 8 entries.
Intel Core Duo, Intel Core Solo, Pentium M processors: 6 entries.
P6 family processors: 4 entries.
NOTES:
1 Introduced to the IA-32 architecture in the Pentium 4 and Intel Xeon processors.
Intel 64 and IA-32 processors may implement four types of caches: the trace cache, the level 1 (L1) cache, the
level 2 (L2) cache, and the level 3 (L3) cache. See Figure 11-1. Cache availability is described below:
•
Intel Core i7, i5, i3 processor Family and Intel Xeon processor Family based on Intel® microarchitecture code name Nehalem and Intel® microarchitecture code name Westmere — The L1 cache is
divided into two sections: one section is dedicated to caching instructions (pre-decoded instructions) and the
other caches data. The L2 cache is a unified data and instruction cache. Each processor core has its own L1 and
L2. The L3 cache is an inclusive, unified data and instruction cache, shared by all processor cores inside a
physical package. No trace cache is implemented.
•
Intel® Core™ 2 processor family and Intel® Xeon® processor family based on Intel® Core™ microarchitecture — The L1 cache is divided into two sections: one section is dedicated to caching instructions (predecoded instructions) and the other caches data. The L2 cache is a unified data and instruction cache located
on the processor chip; it is shared between two processor cores in a dual-core processor implementation.
Quad-core processors have two L2, each shared by two processor cores. No trace cache is implemented.
•
Intel® Atom™ processor — The L1 cache is divided into two sections: one section is dedicated to caching
instructions (pre-decoded instructions) and the other caches data. The L2 cache is a unified data and
instruction cache is located on the processor chip. No trace cache is implemented.
•
Intel® Core™ Solo and Intel® Core™ Duo processors — The L1 cache is divided into two sections: one
section is dedicated to caching instructions (pre-decoded instructions) and the other caches data. The L2 cache
is a unified data and instruction cache located on the processor chip. It is shared between two processor cores
in a dual-core processor implementation. No trace cache is implemented.
•
Pentium® 4 and Intel® Xeon® processors Based on Intel NetBurst® microarchitecture — The trace
cache caches decoded instructions (μops) from the instruction decoder and the L1 cache contains data. The L2
and L3 caches are unified data and instruction caches located on the processor chip. Dualcore processors have
two L2, one in each processor core. Note that the L3 cache is only implemented on some Intel Xeon processors.
•
P6 family processors — The L1 cache is divided into two sections: one dedicated to caching instructions (predecoded instructions) and the other to caching data. The L2 cache is a unified data and instruction cache
located on the processor chip. P6 family processors do not implement a trace cache.
•
Pentium® processors — The L1 cache has the same structure as on P6 family processors. There is no trace
cache. The L2 cache is a unified data and instruction cache external to the processor chip on earlier Pentium
processors and implemented on the processor chip in later Pentium processors. For Pentium processors where
the L2 cache is external to the processor, access to the cache is through the system bus.
For Intel Core i7 processors and processors based on Intel Core, Intel Atom, and Intel NetBurst microarchitectures,
Intel Core Duo, Intel Core Solo and Pentium M processors, the cache lines for the L1 and L2 caches (and L3 caches
if supported) are 64 bytes wide. The processor always reads a cache line from system memory beginning on a 64byte boundary. (A 64-byte aligned cache line begins at an address with its 6 least-significant bits clear.) A cache
11-4 Vol. 3A
MEMORY CACHE CONTROL
line can be filled from memory with a 8-transfer burst transaction. The caches do not support partially-filled cache
lines, so caching even a single doubleword requires caching an entire line.
The L1 and L2 cache lines in the P6 family and Pentium processors are 32 bytes wide, with cache line reads from
system memory beginning on a 32-byte boundary (5 least-significant bits of a memory address clear.) A cache line
can be filled from memory with a 4-transfer burst transaction. Partially-filled cache lines are not supported.
The trace cache in processors based on Intel NetBurst microarchitecture is available in all execution modes:
protected mode, system management mode (SMM), and real-address mode. The L1,L2, and L3 caches are also
available in all execution modes; however, use of them must be handled carefully in SMM (see Section 34.4.2,
“SMRAM Caching”).
The TLBs store the most recently used page-directory and page-table entries. They speed up memory accesses
when paging is enabled by reducing the number of memory accesses that are required to read the page tables
stored in system memory. The TLBs are divided into four groups: instruction TLBs for 4-KByte pages, data TLBs for
4-KByte pages; instruction TLBs for large pages (2-MByte, 4-MByte or 1-GByte pages), and data TLBs for large
pages. The TLBs are normally active only in protected mode with paging enabled. When paging is disabled or the
processor is in real-address mode, the TLBs maintain their contents until explicitly or implicitly flushed (see Section
11.9, “Invalidating the Translation Lookaside Buffers (TLBs)”).
Processors based on Intel Core microarchitectures implement one level of instruction TLB and two levels of data
TLB. Intel Core i7 processor provides a second-level unified TLB.
The store buffer is associated with the processors instruction execution units. It allows writes to system memory
and/or the internal caches to be saved and in some cases combined to optimize the processor’s bus accesses. The
store buffer is always enabled in all execution modes.
The processor’s caches are for the most part transparent to software. When enabled, instructions and data flow
through these caches without the need for explicit software control. However, knowledge of the behavior of these
caches may be useful in optimizing software performance. For example, knowledge of cache dimensions and
replacement algorithms gives an indication of how large of a data structure can be operated on at once without
causing cache thrashing.
In multiprocessor systems, maintenance of cache consistency may, in rare circumstances, require intervention by
system software. For these rare cases, the processor provides privileged cache control instructions for use in
flushing caches and forcing memory ordering.
There are several instructions that software can use to improve the performance of the L1, L2, and L3 caches,
including the PREFETCHh, CLFLUSH, and CLFLUSHOPT instructions and the non-temporal move instructions
(MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD). The use of these instructions are discussed in Section
11.5.5, “Cache Management Instructions.”
11.2
CACHING TERMINOLOGY
IA-32 processors (beginning with the Pentium processor) and Intel 64 processors use the MESI (modified, exclusive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in other processors
(see Section 11.4, “Cache Control Protocol”).
When the processor recognizes that an operand being read from memory is cacheable, the processor reads an
entire cache line into the appropriate cache (L1, L2, L3, or all). This operation is called a cache line fill. If the
memory location containing that operand is still cached the next time the processor attempts to access the
operand, the processor can read the operand from the cache instead of going back to memory. This operation is
called a cache hit.
When the processor attempts to write an operand to a cacheable area of memory, it first checks if a cache line for
that memory location exists in the cache. If a valid cache line does exist, the processor (depending on the write
policy currently in force) can write the operand into the cache instead of writing it out to system memory. This
operation is called a write hit. If a write misses the cache (that is, a valid cache line is not present for area of
memory being written to), the processor performs a cache line fill, write allocation. Then it writes the operand into
the cache line and (depending on the write policy currently in force) can also write it out to memory. If the operand
is to be written out to memory, it is written first into the store buffer, and then written from the store buffer to
memory when the system bus is available. (Note that for the Pentium processor, write misses do not result in a
cache line fill; they always result in a write to memory. For this processor, only read misses result in cache line fills.)
Vol. 3A 11-5
MEMORY CACHE CONTROL
When operating in an MP system, IA-32 processors (beginning with the Intel486 processor) and Intel 64 processors
have the ability to snoop other processor’s accesses to system memory and to their internal caches. They use this
snooping ability to keep their internal caches consistent both with system memory and with the caches in other
processors on the bus. For example, in the Pentium and P6 family processors, if through snooping one processor
detects that another processor intends to write to a memory location that it currently has cached in shared state,
the snooping processor will invalidate its cache line forcing it to perform a cache line fill the next time it accesses
the same memory location.
Beginning with the P6 family processors, if a processor detects (through snooping) that another processor is trying
to access a memory location that it has modified in its cache, but has not yet written back to system memory, the
snooping processor will signal the other processor (by means of the HITM# signal) that the cache line is held in
modified state and will preform an implicit write-back of the modified data. The implicit write-back is transferred
directly to the initial requesting processor and snooped by the memory controller to assure that system memory
has been updated. Here, the processor with the valid data may pass the data to the other processors without actually writing it to system memory; however, it is the responsibility of the memory controller to snoop this operation
and update memory.
11.3
METHODS OF CACHING AVAILABLE
The processor allows any area of system memory to be cached in the L1, L2, and L3 caches. In individual pages or
regions of system memory, it allows the type of caching (also called memory type) to be specified (see Section
11.5). Memory types currently defined for the Intel 64 and IA-32 architectures are (see Table 11-2):
•
Strong Uncacheable (UC) —System memory locations are not cached. All reads and writes appear on the
system bus and are executed in program order without reordering. No speculative memory accesses, pagetable walks, or prefetches of speculated branch targets are made. This type of cache-control is useful for
memory-mapped I/O devices. When used with normal RAM, it greatly reduces processor performance.
NOTE
The behavior of FP and SSE/SSE2 operations on operands in UC memory is implementation
dependent. In some implementations, accesses to UC memory may occur more than once. To
ensure predictable behavior, use loads and stores of general purpose registers to access UC
memory that may have read or write side effects.
Table 11-2. Memory Types and Their Properties
Memory Type and
Mnemonic
Cacheable
Writeback Allows
Cacheable Speculative
Reads
Memory Ordering Model
Strong Uncacheable
(UC)
No
No
No
Strong Ordering
Uncacheable (UC-)
No
No
No
Strong Ordering. Can only be selected through the PAT. Can be
overridden by WC in MTRRs.
Write Combining (WC) No
No
Yes
Weak Ordering. Available by programming MTRRs or by selecting it
through the PAT.
Write Through (WT)
Yes
No
Yes
Speculative Processor Ordering.
Write Back (WB)
Yes
Yes
Yes
Speculative Processor Ordering.
Write Protected (WP)
Yes for
reads; no for
writes
No
Yes
Speculative Processor Ordering. Available by programming MTRRs.
•
Uncacheable (UC-) — Has same characteristics as the strong uncacheable (UC) memory type, except that
this memory type can be overridden by programming the MTRRs for the WC memory type. This memory type
is available in processor families starting from the Pentium III processors and can only be selected through the
PAT.
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MEMORY CACHE CONTROL
•
Write Combining (WC) — System memory locations are not cached (as with uncacheable memory) and
coherency is not enforced by the processor’s bus coherency protocol. Speculative reads are allowed. Writes
may be delayed and combined in the write combining buffer (WC buffer) to reduce memory accesses. If the WC
buffer is partially filled, the writes may be delayed until the next occurrence of a serializing event; such as, an
SFENCE or MFENCE instruction, CPUID execution, a read or write to uncached memory, an interrupt
occurrence, or a LOCK instruction execution. This type of cache-control is appropriate for video frame buffers,
where the order of writes is unimportant as long as the writes update memory so they can be seen on the
graphics display. See Section 11.3.1, “Buffering of Write Combining Memory Locations,” for more information
about caching the WC memory type. This memory type is available in the Pentium Pro and Pentium II
processors by programming the MTRRs; or in processor families starting from the Pentium III processors by
programming the MTRRs or by selecting it through the PAT.
•
Write-through (WT) — Writes and reads to and from system memory are cached. Reads come from cache
lines on cache hits; read misses cause cache fills. Speculative reads are allowed. All writes are written to a
cache line (when possible) and through to system memory. When writing through to memory, invalid cache
lines are never filled, and valid cache lines are either filled or invalidated. Write combining is allowed. This type
of cache-control is appropriate for frame buffers or when there are devices on the system bus that access
system memory, but do not perform snooping of memory accesses. It enforces coherency between caches in
the processors and system memory.
•
Write-back (WB) — Writes and reads to and from system memory are cached. Reads come from cache lines
on cache hits; read misses cause cache fills. Speculative reads are allowed. Write misses cause cache line fills
(in processor families starting with the P6 family processors), and writes are performed entirely in the cache,
when possible. Write combining is allowed. The write-back memory type reduces bus traffic by eliminating
many unnecessary writes to system memory. Writes to a cache line are not immediately forwarded to system
memory; instead, they are accumulated in the cache. The modified cache lines are written to system memory
later, when a write-back operation is performed. Write-back operations are triggered when cache lines need to
be deallocated, such as when new cache lines are being allocated in a cache that is already full. They also are
triggered by the mechanisms used to maintain cache consistency. This type of cache-control provides the best
performance, but it requires that all devices that access system memory on the system bus be able to snoop
memory accesses to insure system memory and cache coherency.
•
Write protected (WP) — Reads come from cache lines when possible, and read misses cause cache fills.
Writes are propagated to the system bus and cause corresponding cache lines on all processors on the bus to
be invalidated. Speculative reads are allowed. This memory type is available in processor families starting from
the P6 family processors by programming the MTRRs (see Table 11-6).
Table 11-3 shows which of these caching methods are available in the Pentium, P6 Family, Pentium 4, and Intel
Xeon processors.
Table 11-3. Methods of Caching Available in Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4,
Intel Xeon, P6 Family, and Pentium Processors
Memory Type
Intel Core 2 Duo, Intel Atom, Intel Core Duo,
P6 Family
Pentium M, Pentium 4 and Intel Xeon Processors Processors
Pentium
Processor
Strong Uncacheable (UC)
Yes
Yes
Yes
Uncacheable (UC-)
Yes
Yes*
No
Write Combining (WC)
Yes
Yes
No
Write Through (WT)
Yes
Yes
Yes
Write Back (WB)
Yes
Yes
Yes
Write Protected (WP)
Yes
Yes
No
NOTE:
* Introduced in the Pentium III processor; not available in the Pentium Pro or Pentium II processors
11.3.1
Buffering of Write Combining Memory Locations
Writes to the WC memory type are not cached in the typical sense of the word cached. They are retained in an
internal write combining buffer (WC buffer) that is separate from the internal L1, L2, and L3 caches and the store
Vol. 3A 11-7
MEMORY CACHE CONTROL
buffer. The WC buffer is not snooped and thus does not provide data coherency. Buffering of writes to WC memory
is done to allow software a small window of time to supply more modified data to the WC buffer while remaining as
non-intrusive to software as possible. The buffering of writes to WC memory also causes data to be collapsed; that
is, multiple writes to the same memory location will leave the last data written in the location and the other writes
will be lost.
The size and structure of the WC buffer is not architecturally defined. For the Intel Core 2 Duo, Intel Atom, Intel
Core Duo, Pentium M, Pentium 4 and Intel Xeon processors; the WC buffer is made up of several 64-byte WC
buffers. For the P6 family processors, the WC buffer is made up of several 32-byte WC buffers.
When software begins writing to WC memory, the processor begins filling the WC buffers one at a time. When one
or more WC buffers has been filled, the processor has the option of evicting the buffers to system memory. The
protocol for evicting the WC buffers is implementation dependent and should not be relied on by software for
system memory coherency. When using the WC memory type, software must be sensitive to the fact that the
writing of data to system memory is being delayed and must deliberately empty the WC buffers when system
memory coherency is required.
Once the processor has started to evict data from the WC buffer into system memory, it will make a bus-transaction
style decision based on how much of the buffer contains valid data. If the buffer is full (for example, all bytes are
valid), the processor will execute a burst-write transaction on the bus. This results in all 32 bytes (P6 family processors) or 64 bytes (Pentium 4 and more recent processor) being transmitted on the data bus in a single burst transaction. If one or more of the WC buffer’s bytes are invalid (for example, have not been written by software), the
processor will transmit the data to memory using “partial write” transactions (one chunk at a time, where a “chunk”
is 8 bytes).
This will result in a maximum of 4 partial write transactions (for P6 family processors) or 8 partial write transactions
(for the Pentium 4 and more recent processors) for one WC buffer of data sent to memory.
The WC memory type is weakly ordered by definition. Once the eviction of a WC buffer has started, the data is
subject to the weak ordering semantics of its definition. Ordering is not maintained between the successive allocation/deallocation of WC buffers (for example, writes to WC buffer 1 followed by writes to WC buffer 2 may appear
as buffer 2 followed by buffer 1 on the system bus). When a WC buffer is evicted to memory as partial writes there
is no guaranteed ordering between successive partial writes (for example, a partial write for chunk 2 may appear
on the bus before the partial write for chunk 1 or vice versa).
The only elements of WC propagation to the system bus that are guaranteed are those provided by transaction
atomicity. For example, with a P6 family processor, a completely full WC buffer will always be propagated as a
single 32-bit burst transaction using any chunk order. In a WC buffer eviction where data will be evicted as partials,
all data contained in the same chunk (0 mod 8 aligned) will be propagated simultaneously. Likewise, for more
recent processors starting with those based on Intel NetBurst microarchitectures, a full WC buffer will always be
propagated as a single burst transactions, using any chunk order within a transaction. For partial buffer propagations, all data contained in the same chunk will be propagated simultaneously.
11.3.2
Choosing a Memory Type
The simplest system memory model does not use memory-mapped I/O with read or write side effects, does not
include a frame buffer, and uses the write-back memory type for all memory. An I/O agent can perform direct
memory access (DMA) to write-back memory and the cache protocol maintains cache coherency.
A system can use strong uncacheable memory for other memory-mapped I/O, and should always use strong
uncacheable memory for memory-mapped I/O with read side effects.
Dual-ported memory can be considered a write side effect, making relatively prompt writes desirable, because
those writes cannot be observed at the other port until they reach the memory agent. A system can use strong
uncacheable, uncacheable, write-through, or write-combining memory for frame buffers or dual-ported memory
that contains pixel values displayed on a screen. Frame buffer memory is typically large (a few megabytes) and is
usually written more than it is read by the processor. Using strong uncacheable memory for a frame buffer generates very large amounts of bus traffic, because operations on the entire buffer are implemented using partial writes
rather than line writes. Using write-through memory for a frame buffer can displace almost all other useful cached
lines in the processor's L2 and L3 caches and L1 data cache. Therefore, systems should use write-combining
memory for frame buffers whenever possible.
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MEMORY CACHE CONTROL
Software can use page-level cache control, to assign appropriate effective memory types when software will not
access data structures in ways that benefit from write-back caching. For example, software may read a large data
structure once and not access the structure again until the structure is rewritten by another agent. Such a large
data structure should be marked as uncacheable, or reading it will evict cached lines that the processor will be
referencing again.
A similar example would be a write-only data structure that is written to (to export the data to another agent), but
never read by software. Such a structure can be marked as uncacheable, because software never reads the values
that it writes (though as uncacheable memory, it will be written using partial writes, while as write-back memory,
it will be written using line writes, which may not occur until the other agent reads the structure and triggers
implicit write-backs).
On the Pentium III, Pentium 4, and more recent processors, new instructions are provided that give software
greater control over the caching, prefetching, and the write-back characteristics of data. These instructions allow
software to use weakly ordered or processor ordered memory types to improve processor performance, but when
necessary to force strong ordering on memory reads and/or writes. They also allow software greater control over
the caching of data. For a description of these instructions and there intended use, see Section 11.5.5, “Cache
Management Instructions.”
11.3.3
Code Fetches in Uncacheable Memory
Programs may execute code from uncacheable (UC) memory, but the implications are different from accessing
data in UC memory. When doing code fetches, the processor never transitions from cacheable code to UC code
speculatively. It also never speculatively fetches branch targets that result in UC code.
The processor may fetch the same UC cache line multiple times in order to decode an instruction once. It may
decode consecutive UC instructions in a cacheline without fetching between each instruction. It may also fetch
additional cachelines from the same or a consecutive 4-KByte page in order to decode one non-speculative UC
instruction (this can be true even when the instruction is contained fully in one line).
Because of the above and because cacheline sizes may change in future processors, software should avoid placing
memory-mapped I/O with read side effects in the same page or in a subsequent page used to execute UC code.
11.4
CACHE CONTROL PROTOCOL
The following section describes the cache control protocol currently defined for the Intel 64 and IA-32 architectures.
In the L1 data cache and in the L2/L3 unified caches, the MESI (modified, exclusive, shared, invalid) cache protocol
maintains consistency with caches of other processors. The L1 data cache and the L2/L3 unified caches have two
MESI status flags per cache line. Each line can be marked as being in one of the states defined in Table 11-4. In
general, the operation of the MESI protocol is transparent to programs.
Table 11-4. MESI Cache Line States
Cache Line State
M (Modified)
E (Exclusive)
S (Shared)
I (Invalid)
This cache line is valid?
Yes
Yes
Yes
No
The memory copy is…
Out of date
Valid
Valid
—
Copies exist in caches of other
processors?
No
No
Maybe
Maybe
A write to this line …
Does not go to the
system bus.
Does not go to the
system bus.
Causes the processor to
gain exclusive ownership
of the line.
Goes directly to the
system bus.
The L1 instruction cache in P6 family processors implements only the “SI” part of the MESI protocol, because the
instruction cache is not writable. The instruction cache monitors changes in the data cache to maintain consistency
Vol. 3A 11-9
MEMORY CACHE CONTROL
between the caches when instructions are modified. See Section 11.6, “Self-Modifying Code,” for more information
on the implications of caching instructions.
11.5
CACHE CONTROL
The Intel 64 and IA-32 architectures provide a variety of mechanisms for controlling the caching of data and
instructions and for controlling the ordering of reads and writes between the processor, the caches, and memory.
These mechanisms can be divided into two groups:
•
Cache control registers and bits — The Intel 64 and IA-32 architectures define several dedicated registers
and various bits within control registers and page- and directory-table entries that control the caching system
memory locations in the L1, L2, and L3 caches. These mechanisms control the caching of virtual memory pages
and of regions of physical memory.
•
Cache control and memory ordering instructions — The Intel 64 and IA-32 architectures provide several
instructions that control the caching of data, the ordering of memory reads and writes, and the prefetching of
data. These instructions allow software to control the caching of specific data structures, to control memory
coherency for specific locations in memory, and to force strong memory ordering at specific locations in a
program.
The following sections describe these two groups of cache control mechanisms.
11.5.1
Cache Control Registers and Bits
Figure 11-3 depicts cache-control mechanisms in IA-32 processors. Other than for the matter of memory address
space, these work the same in Intel 64 processors.
The Intel 64 and IA-32 architectures provide the following cache-control registers and bits for use in enabling or
restricting caching to various pages or regions in memory:
•
CD flag, bit 30 of control register CR0 — Controls caching of system memory locations (see Section 2.5,
“Control Registers”). If the CD flag is clear, caching is enabled for the whole of system memory, but may be
restricted for individual pages or regions of memory by other cache-control mechanisms. When the CD flag is
set, caching is restricted in the processor’s caches (cache hierarchy) for the P6 and more recent processor
families and prevented for the Pentium processor (see note below). With the CD flag set, however, the caches
will still respond to snoop traffic. Caches should be explicitly flushed to insure memory coherency. For highest
processor performance, both the CD and the NW flags in control register CR0 should be cleared. Table 11-5
shows the interaction of the CD and NW flags.
The effect of setting the CD flag is somewhat different for processor families starting with P6 family than the
Pentium processor (see Table 11-5). To insure memory coherency after the CD flag is set, the caches should
be explicitly flushed (see Section 11.5.3, “Preventing Caching”). Setting the CD flag for the P6 and more
recent processor families modify cache line fill and update behaviour. Also, setting the CD flag on these
processors do not force strict ordering of memory accesses unless the MTRRs are disabled and/or all memory
is referenced as uncached (see Section 8.2.5, “Strengthening or Weakening the Memory-Ordering Model”).
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MEMORY CACHE CONTROL
CR4
P
G
E
Enables global pages
designated with G flag
CR3
P P
C W
D T
CR0
C N
D W
CD and NW Flags
control overall caching
of system memory
FFFFFFFFH2
PAT4
Control caching of
page directory
PAT controls caching
of virtual memory
pages
Page-Directory or
Page-Table Entry
P4 1 P P
A G C W
T
D T
MTRRs3
PCD and PWT flags
control page-level
caching
G flag controls pagelevel flushing of TLBs
Store Buffer
Physical Memory
0
MTRRs control caching
of selected regions of
physical memory
TLBs
1. G flag only available in P6 and later processor families
2. The maximum physical address size is reported by CPUID leaf
function 80000008H. The maximum physical address size of
FFFFFFFFFH applies only If 36-bit physical addressing is used.
3. MTRRs available only in P6 and later processor families;
similar control available in Pentium processor with the KEN#
and WB/WT# pins.
4. PAT available only in Pentium III and later processor families.
5. L3 in processors based on Intel NetBurst microarchitecture can
be disabled using IA32_MISC_ENABLE MSR.
Figure 11-3. Cache-Control Registers and Bits Available in Intel 64 and IA-32 Processors
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MEMORY CACHE CONTROL
Table 11-5. Cache Operating Modes
CD
NW
0
0
0
1
L1
L2/L31
• Read hits access the cache; read misses may cause replacement.
• Write hits update the cache.
• Only writes to shared lines and write misses update system memory.
Yes
Yes
Yes
Yes
Yes
Yes
• Write misses cause cache line fills.
• Write hits can change shared lines to modified under control of the MTRRs and with associated
read invalidation cycle.
• (Pentium processor only.) Write misses do not cause cache line fills.
Yes
Yes
Yes
• (Pentium processor only.) Write hits can change shared lines to exclusive under control of WB/WT#.
• Invalidation is allowed.
• External snoop traffic is supported.
Yes
Caching and Read/Write Policy
Normal Cache Mode. Highest performance cache operation.
Yes
Yes
Yes
Yes
NA
NA
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
• Write misses access memory.
• Write hits can change shared lines to exclusive under control of the MTRRs and with associated
read invalidation cycle.
• (Pentium processor only.) Write hits can change shared lines to exclusive under control of the
WB/WT#.
Yes
Yes
Yes
Yes
• (P6 and later processor families only.) Strict memory ordering is not enforced unless the MTRRs are
disabled and/or all memory is referenced as uncached (see Section 7.2.4., “Strengthening or
Weakening the Memory Ordering Model”).
• Invalidation is allowed.
• External snoop traffic is supported.
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Invalid setting.
Generates a general-protection exception (#GP) with an error code of 0.
1
0
No-fill Cache Mode. Memory coherency is maintained.3
• (Pentium 4 and later processor families.) State of processor after a power up or reset.
• Read hits access the cache; read misses do not cause replacement (see Pentium 4 and Intel Xeon
processors reference below).
• Write hits update the cache.
• Only writes to shared lines and write misses update system memory.
1
1
Yes
Memory coherency is not maintained.2, 3
• (P6 family and Pentium processors.) State of the processor after a power up or reset.
• Read hits access the cache; read misses do not cause replacement.
• Write hits update the cache and change exclusive lines to modified.
•
•
•
•
Shared lines remain shared after write hit.
Write misses access memory.
Invalidation is inhibited when snooping; but is allowed with INVD and WBINVD instructions.
External snoop traffic is supported.
Yes
NOTES:
1. The L2/L3 column in this table is definitive for the Pentium 4, Intel Xeon, and P6 family processors. It is intended to represent what
could be implemented in a system based on a Pentium processor with an external, platform specific, write-back L2 cache.
2. The Pentium 4 and more recent processor families do not support this mode; setting the CD and NW bits to 1 selects the no-fill
cache mode.
3. Not supported In Intel Atom processors. If CD = 1 in an Intel Atom processor, caching is disabled.
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MEMORY CACHE CONTROL
•
NW flag, bit 29 of control register CR0 — Controls the write policy for system memory locations (see
Section 2.5, “Control Registers”). If the NW and CD flags are clear, write-back is enabled for the whole of
system memory, but may be restricted for individual pages or regions of memory by other cache-control
mechanisms. Table 11-5 shows how the other combinations of CD and NW flags affects caching.
NOTES
For the Pentium 4 and Intel Xeon processors, the NW flag is a don’t care flag; that is, when the CD
flag is set, the processor uses the no-fill cache mode, regardless of the setting of the NW flag.
For Intel Atom processors, the NW flag is a don’t care flag; that is, when the CD flag is set, the
processor disables caching, regardless of the setting of the NW flag.
For the Pentium processor, when the L1 cache is disabled (the CD and NW flags in control register
CR0 are set), external snoops are accepted in DP (dual-processor) systems and inhibited in uniprocessor systems.
When snoops are inhibited, address parity is not checked and APCHK# is not asserted for a corrupt
address; however, when snoops are accepted, address parity is checked and APCHK# is asserted
for corrupt addresses.
•
PCD and PWT flags in paging-structure entries — Control the memory type used to access paging
structures and pages (see Section 4.9, “Paging and Memory Typing”).
•
PCD and PWT flags in control register CR3 — Control the memory type used to access the first paging
structure of the current paging-structure hierarchy (see Section 4.9, “Paging and Memory Typing”).
•
G (global) flag in the page-directory and page-table entries (introduced to the IA-32 architecture in
the P6 family processors) — Controls the flushing of TLB entries for individual pages. See Section 4.10,
“Caching Translation Information,” for more information about this flag.
•
PGE (page global enable) flag in control register CR4 — Enables the establishment of global pages with
the G flag. See Section 4.10, “Caching Translation Information,” for more information about this flag.
•
Memory type range registers (MTRRs) (introduced in P6 family processors) — Control the type of
caching used in specific regions of physical memory. Any of the caching types described in Section 11.3,
“Methods of Caching Available,” can be selected. See Section 11.11, “Memory Type Range Registers (MTRRs),”
for a detailed description of the MTRRs.
•
Page Attribute Table (PAT) MSR (introduced in the Pentium III processor) — Extends the memory
typing capabilities of the processor to permit memory types to be assigned on a page-by-page basis (see
Section 11.12, “Page Attribute Table (PAT)”).
•
Third-Level Cache Disable flag, bit 6 of the IA32_MISC_ENABLE MSR (Available only in processors
based on Intel NetBurst microarchitecture) — Allows the L3 cache to be disabled and enabled, independently of the L1 and L2 caches.
•
KEN# and WB/WT# pins (Pentium processor) — Allow external hardware to control the caching method
used for specific areas of memory. They perform similar (but not identical) functions to the MTRRs in the P6
family processors.
•
PCD and PWT pins (Pentium processor) — These pins (which are associated with the PCD and PWT flags in
control register CR3 and in the page-directory and page-table entries) permit caching in an external L2 cache
to be controlled on a page-by-page basis, consistent with the control exercised on the L1 cache of these
processors. The P6 and more recent processor families do not provide these pins because the L2 cache in
internal to the chip package.
11.5.2
Precedence of Cache Controls
The cache control flags and MTRRs operate hierarchically for restricting caching. That is, if the CD flag is set,
caching is prevented globally (see Table 11-5). If the CD flag is clear, the page-level cache control flags and/or the
MTRRs can be used to restrict caching. If there is an overlap of page-level and MTRR caching controls, the mechanism that prevents caching has precedence. For example, if an MTRR makes a region of system memory uncacheable, a page-level caching control cannot be used to enable caching for a page in that region. The converse is also
Vol. 3A 11-13
MEMORY CACHE CONTROL
true; that is, if a page-level caching control designates a page as uncacheable, an MTRR cannot be used to make
the page cacheable.
In cases where there is a overlap in the assignment of the write-back and write-through caching policies to a page
and a region of memory, the write-through policy takes precedence. The write-combining policy (which can only be
assigned through an MTRR or the PAT) takes precedence over either write-through or write-back.
The selection of memory types at the page level varies depending on whether PAT is being used to select memory
types for pages, as described in the following sections.
On processors based on Intel NetBurst microarchitecture, the third-level cache can be disabled by bit 6 of the
IA32_MISC_ENABLE MSR. Using IA32_MISC_ENABLE[bit 6] takes precedence over the CD flag, MTRRs, and PAT
for the L3 cache in those processors. That is, when the third-level cache disable flag is set (cache disabled), the
other cache controls have no affect on the L3 cache; when the flag is clear (enabled), the cache controls have the
same affect on the L3 cache as they have on the L1 and L2 caches.
IA32_MISC_ENABLE[bit 6] is not supported in Intel Core i7 processors, nor processors based on Intel Core, and
Intel Atom microarchitectures.
11.5.2.1
Selecting Memory Types for Pentium Pro and Pentium II Processors
The Pentium Pro and Pentium II processors do not support the PAT. Here, the effective memory type for a page is
selected with the MTRRs and the PCD and PWT bits in the page-table or page-directory entry for the page. Table
11-6 describes the mapping of MTRR memory types and page-level caching attributes to effective memory types,
when normal caching is in effect (the CD and NW flags in control register CR0 are clear). Combinations that appear
in gray are implementation-defined for the Pentium Pro and Pentium II processors. System designers are encouraged to avoid these implementation-defined combinations.
Table 11-6. Effective Page-Level Memory Type for Pentium Pro and Pentium II Processors
MTRR Memory Type1
PCD Value
PWT Value
Effective Memory Type
UC
X
X
UC
WC
0
0
WC
0
1
WC
1
0
WC
1
1
UC
0
X
WT
1
X
UC
0
0
WP
0
1
WP
1
0
WC
1
1
UC
0
0
WB
0
1
WT
1
X
UC
WT
WP
WB
NOTE:
1. These effective memory types also apply to the Pentium 4, Intel Xeon, and Pentium III processors when the PAT bit is not used
(set to 0) in page-table and page-directory entries.
When normal caching is in effect, the effective memory type shown in Table 11-6 is determined using the following
rules:
1. If the PCD and PWT attributes for the page are both 0, then the effective memory type is identical to the
MTRR-defined memory type.
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MEMORY CACHE CONTROL
2. If the PCD flag is set, then the effective memory type is UC.
3. If the PCD flag is clear and the PWT flag is set, the effective memory type is WT for the WB memory type and
the MTRR-defined memory type for all other memory types.
4. Setting the PCD and PWT flags to opposite values is considered model-specific for the WP and WC memory
types and architecturally-defined for the WB, WT, and UC memory types.
11.5.2.2
Selecting Memory Types for Pentium III and More Recent Processor Families
The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Intel Core Solo, Pentium M, Pentium 4, Intel Xeon, and Pentium
III processors use the PAT to select effective page-level memory types. Here, a memory type for a page is selected
by the MTRRs and the value in a PAT entry that is selected with the PAT, PCD and PWT bits in a page-table or pagedirectory entry (see Section 11.12.3, “Selecting a Memory Type from the PAT”). Table 11-7 describes the mapping
of MTRR memory types and PAT entry types to effective memory types, when normal caching is in effect (the CD
and NW flags in control register CR0 are clear).
Table 11-7. Effective Page-Level Memory Types for Pentium III and More Recent Processor Families
MTRR Memory Type
PAT Entry Value
Effective Memory Type
UC
UC
UC1
UC-
UC1
WC
WC
WT
UC1
WB
UC1
WP
UC1
UC
UC2
UC-
WC
WC
WC
WT
UC2,3
WB
WC
WP
UC2,3
UC
UC2
UC-
UC2
WC
WC
WT
WT
WB
WT
WP
WP3
UC
UC2
UC-
UC2
WC
WC
WC
WT
WB
WT
WT
WB
WB
WP
WP
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MEMORY CACHE CONTROL
Table 11-7. Effective Page-Level Memory Types for Pentium III and More Recent Processor Families (Contd.)
MTRR Memory Type
PAT Entry Value
Effective Memory Type
WP
UC
UC2
UC-
WC3
WC
WC
WT
WT3
WB
WP
WP
WP
NOTES:
1. The UC attribute comes from the MTRRs and the processors are not required to snoop their caches since the data could never have
been cached. This attribute is preferred for performance reasons.
2. The UC attribute came from the page-table or page-directory entry and processors are required to check their caches because the
data may be cached due to page aliasing, which is not recommended.
3. These combinations were specified as “undefined” in previous editions of the Intel® 64 and IA-32 Architectures Software Developer’s Manual. However, all processors that support both the PAT and the MTRRs determine the effective page-level memory
types for these combinations as given.
11.5.2.3
Writing Values Across Pages with Different Memory Types
If two adjoining pages in memory have different memory types, and a word or longer operand is written to a
memory location that crosses the page boundary between those two pages, the operand might be written to
memory twice. This action does not present a problem for writes to actual memory; however, if a device is mapped
the memory space assigned to the pages, the device might malfunction.
11.5.3
Preventing Caching
To disable the L1, L2, and L3 caches after they have been enabled and have received cache fills, perform the
following steps:
1. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and the NW flag to 0.
2. Flush all caches using the WBINVD instruction.
3. Disable the MTRRs and set the default memory type to uncached or set all MTRRs for the uncached memory
type (see the discussion of the discussion of the TYPE field and the E flag in Section 11.11.2.1,
“IA32_MTRR_DEF_TYPE MSR”).
The caches must be flushed (step 2) after the CD flag is set to insure system memory coherency. If the caches are
not flushed, cache hits on reads will still occur and data will be read from valid cache lines.
The intent of the three separate steps listed above address three distinct requirements: (i) discontinue new data
replacing existing data in the cache (ii) ensure data already in the cache are evicted to memory, (iii) ensure subsequent memory references observe UC memory type semantics. Different processor implementation of caching
control hardware may allow some variation of software implementation of these three requirements. See note
below.
NOTES
Setting the CD flag in control register CR0 modifies the processor’s caching behaviour as indicated
in Table 11-5, but setting the CD flag alone may not be sufficient across all processor families to
force the effective memory type for all physical memory to be UC nor does it force strict memory
ordering, due to hardware implementation variations across different processor families. To force
the UC memory type and strict memory ordering on all of physical memory, it is sufficient to either
program the MTRRs for all physical memory to be UC memory type or disable all MTRRs.
For the Pentium 4 and Intel Xeon processors, after the sequence of steps given above has been
executed, the cache lines containing the code between the end of the WBINVD instruction and
before the MTRRS have actually been disabled may be retained in the cache hierarchy. Here, to
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MEMORY CACHE CONTROL
remove code from the cache completely, a second WBINVD instruction must be executed after the
MTRRs have been disabled.
For Intel Atom processors, setting the CD flag forces all physical memory to observe UC semantics
(without requiring memory type of physical memory to be set explicitly). Consequently, software
does not need to issue a second WBINVD as some other processor generations might require.
11.5.4
Disabling and Enabling the L3 Cache
On processors based on Intel NetBurst microarchitecture, the third-level cache can be disabled by bit 6 of the
IA32_MISC_ENABLE MSR. The third-level cache disable flag (bit 6 of the IA32_MISC_ENABLE MSR) allows the L3
cache to be disabled and enabled, independently of the L1 and L2 caches. Prior to using this control to disable or
enable the L3 cache, software should disable and flush all the processor caches, as described earlier in Section
11.5.3, “Preventing Caching,” to prevent of loss of information stored in the L3 cache. After the L3 cache has been
disabled or enabled, caching for the whole processor can be restored.
Newer Intel 64 processor with L3 do not support IA32_MISC_ENABLE[bit 6], the procedure described in Section
11.5.3, “Preventing Caching,” apply to the entire cache hierarchy.
11.5.5
Cache Management Instructions
The Intel 64 and IA-32 architectures provide several instructions for managing the L1, L2, and L3 caches. The INVD
and WBINVD instructions are privileged instructions and operate on the L1, L2 and L3 caches as a whole. The
PREFETCHh, CLFLUSH and CLFLUSHOPT instructions and the non-temporal move instructions (MOVNTI, MOVNTQ,
MOVNTDQ, MOVNTPS, and MOVNTPD) offer more granular control over caching, and are available to all privileged
levels.
The INVD and WBINVD instructions are used to invalidate the contents of the L1, L2, and L3 caches. The INVD
instruction invalidates all internal cache entries, then generates a special-function bus cycle that indicates that
external caches also should be invalidated. The INVD instruction should be used with care. It does not force a
write-back of modified cache lines; therefore, data stored in the caches and not written back to system memory
will be lost. Unless there is a specific requirement or benefit to invalidating the caches without writing back the
modified lines (such as, during testing or fault recovery where cache coherency with main memory is not a
concern), software should use the WBINVD instruction.
The WBINVD instruction first writes back any modified lines in all the internal caches, then invalidates the contents
of both the L1, L2, and L3 caches. It ensures that cache coherency with main memory is maintained regardless of
the write policy in effect (that is, write-through or write-back). Following this operation, the WBINVD instruction
generates one (P6 family processors) or two (Pentium and Intel486 processors) special-function bus cycles to indicate to external cache controllers that write-back of modified data followed by invalidation of external caches
should occur. The amount of time or cycles for WBINVD to complete will vary due to the size of different cache hierarchies and other factors. As a consequence, the use of the WBINVD instruction can have an impact on interrupt/event response time.
The PREFETCHh instructions allow a program to suggest to the processor that a cache line from a specified location
in system memory be prefetched into the cache hierarchy (see Section 11.8, “Explicit Caching”).
The CLFLUSH and CLFLUSHOPT instructions allow selected cache lines to be flushed from memory. These instructions give a program the ability to explicitly free up cache space, when it is known that cached section of system
memory will not be accessed in the near future.
The non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD) allow data to be
moved from the processor’s registers directly into system memory without being also written into the L1, L2,
and/or L3 caches. These instructions can be used to prevent cache pollution when operating on data that is going
to be modified only once before being stored back into system memory. These instructions operate on data in the
general-purpose, MMX, and XMM registers.
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11.5.6
L1 Data Cache Context Mode
L1 data cache context mode is a feature of processors based on the Intel NetBurst microarchitecture that support
Intel Hyper-Threading Technology. When CPUID.1:ECX[bit 10] = 1, the processor supports setting L1 data cache
context mode using the L1 data cache context mode flag ( IA32_MISC_ENABLE[bit 24] ). Selectable modes are
adaptive mode (default) and shared mode.
The BIOS is responsible for configuring the L1 data cache context mode.
11.5.6.1
Adaptive Mode
Adaptive mode facilitates L1 data cache sharing between logical processors. When running in adaptive mode, the
L1 data cache is shared across logical processors in the same core if:
•
•
CR3 control registers for logical processors sharing the cache are identical.
The same paging mode is used by logical processors sharing the cache.
In this situation, the entire L1 data cache is available to each logical processor (instead of being competitively
shared).
If CR3 values are different for the logical processors sharing an L1 data cache or the logical processors use different
paging modes, processors compete for cache resources. This reduces the effective size of the cache for each logical
processor. Aliasing of the cache is not allowed (which prevents data thrashing).
11.5.6.2
Shared Mode
In shared mode, the L1 data cache is competitively shared between logical processors. This is true even if the
logical processors use identical CR3 registers and paging modes.
In shared mode, linear addresses in the L1 data cache can be aliased, meaning that one linear address in the cache
can point to different physical locations. The mechanism for resolving aliasing can lead to thrashing. For this
reason, IA32_MISC_ENABLE[bit 24] = 0 is the preferred configuration for processors based on the Intel NetBurst
microarchitecture that support Intel Hyper-Threading Technology.
11.6
SELF-MODIFYING CODE
A write to a memory location in a code segment that is currently cached in the processor causes the associated
cache line (or lines) to be invalidated. This check is based on the physical address of the instruction. In addition,
the P6 family and Pentium processors check whether a write to a code segment may modify an instruction that has
been prefetched for execution. If the write affects a prefetched instruction, the prefetch queue is invalidated. This
latter check is based on the linear address of the instruction. For the Pentium 4 and Intel Xeon processors, a write
or a snoop of an instruction in a code segment, where the target instruction is already decoded and resident in the
trace cache, invalidates the entire trace cache. The latter behavior means that programs that self-modify code can
cause severe degradation of performance when run on the Pentium 4 and Intel Xeon processors.
In practice, the check on linear addresses should not create compatibility problems among IA-32 processors. Applications that include self-modifying code use the same linear address for modifying and fetching the instruction.
Systems software, such as a debugger, that might possibly modify an instruction using a different linear address
than that used to fetch the instruction, will execute a serializing operation, such as a CPUID instruction, before the
modified instruction is executed, which will automatically resynchronize the instruction cache and prefetch queue.
(See Section 8.1.3, “Handling Self- and Cross-Modifying Code,” for more information about the use of self-modifying code.)
For Intel486 processors, a write to an instruction in the cache will modify it in both the cache and memory, but if
the instruction was prefetched before the write, the old version of the instruction could be the one executed. To
prevent the old instruction from being executed, flush the instruction prefetch unit by coding a jump instruction
immediately after any write that modifies an instruction.
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MEMORY CACHE CONTROL
11.7
IMPLICIT CACHING (PENTIUM 4, INTEL XEON,
AND P6 FAMILY PROCESSORS)
Implicit caching occurs when a memory element is made potentially cacheable, although the element may never
have been accessed in the normal von Neumann sequence. Implicit caching occurs on the P6 and more recent
processor families due to aggressive prefetching, branch prediction, and TLB miss handling. Implicit caching is an
extension of the behavior of existing Intel386, Intel486, and Pentium processor systems, since software running
on these processor families also has not been able to deterministically predict the behavior of instruction prefetch.
To avoid problems related to implicit caching, the operating system must explicitly invalidate the cache when
changes are made to cacheable data that the cache coherency mechanism does not automatically handle. This
includes writes to dual-ported or physically aliased memory boards that are not detected by the snooping mechanisms of the processor, and changes to page- table entries in memory.
The code in Example 11-1 shows the effect of implicit caching on page-table entries. The linear address F000H
points to physical location B000H (the page-table entry for F000H contains the value B000H), and the page-table
entry for linear address F000 is PTE_F000.
Example 11-1. Effect of Implicit Caching on Page-Table Entries
mov EAX, CR3; Invalidate the TLB
mov CR3, EAX; by copying CR3 to itself
mov PTE_F000, A000H; Change F000H to point to A000H
mov EBX, [F000H];
Because of speculative execution in the P6 and more recent processor families, the last MOV instruction performed
would place the value at physical location B000H into EBX, rather than the value at the new physical address
A000H. This situation is remedied by placing a TLB invalidation between the load and the store.
11.8
EXPLICIT CACHING
The Pentium III processor introduced four new instructions, the PREFETCHh instructions, that provide software with
explicit control over the caching of data. These instructions provide “hints” to the processor that the data requested
by a PREFETCHh instruction should be read into cache hierarchy now or as soon as possible, in anticipation of its
use. The instructions provide different variations of the hint that allow selection of the cache level into which data
will be read.
The PREFETCHh instructions can help reduce the long latency typically associated with reading data from memory
and thus help prevent processor “stalls.” However, these instructions should be used judiciously. Overuse can lead
to resource conflicts and hence reduce the performance of an application. Also, these instructions should only be
used to prefetch data from memory; they should not be used to prefetch instructions. For more detailed information on the proper use of the prefetch instruction, refer to Chapter 7, “Optimizing Cache Usage,” in the Intel® 64
and IA-32 Architectures Optimization Reference Manual.
11.9
INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS)
The processor updates its address translation caches (TLBs) transparently to software. Several mechanisms are
available, however, that allow software and hardware to invalidate the TLBs either explicitly or as a side effect of
another operation. Most details are given in Section 4.10.4, “Invalidation of TLBs and Paging-Structure Caches.” In
addition, the following operations invalidate all TLB entries, irrespective of the setting of the G flag:
•
•
•
Asserting or de-asserting the FLUSH# pin.
(Pentium 4, Intel Xeon, and later processors only.) Writing to an MTRR (with a WRMSR instruction).
Writing to control register CR0 to modify the PG or PE flag.
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MEMORY CACHE CONTROL
•
(Pentium 4, Intel Xeon, and later processors only.) Writing to control register CR4 to modify the PSE, PGE, or
PAE flag.
•
Writing to control register CR4 to change the PCIDE flag from 1 to 0.
See Section 4.10, “Caching Translation Information,” for additional information about the TLBs.
11.10
STORE BUFFER
Intel 64 and IA-32 processors temporarily store each write (store) to memory in a store buffer. The store buffer
improves processor performance by allowing the processor to continue executing instructions without having to
wait until a write to memory and/or to a cache is complete. It also allows writes to be delayed for more efficient use
of memory-access bus cycles.
In general, the existence of the store buffer is transparent to software, even in systems that use multiple processors. The processor ensures that write operations are always carried out in program order. It also insures that the
contents of the store buffer are always drained to memory in the following situations:
•
•
•
•
•
•
•
When an exception or interrupt is generated.
(P6 and more recent processor families only) When a serializing instruction is executed.
When an I/O instruction is executed.
When a LOCK operation is performed.
(P6 and more recent processor families only) When a BINIT operation is performed.
(Pentium III, and more recent processor families only) When using an SFENCE instruction to order stores.
(Pentium 4 and more recent processor families only) When using an MFENCE instruction to order stores.
The discussion of write ordering in Section 8.2, “Memory Ordering,” gives a detailed description of the operation of
the store buffer.
11.11
MEMORY TYPE RANGE REGISTERS (MTRRS)
The following section pertains only to the P6 and more recent processor families.
The memory type range registers (MTRRs) provide a mechanism for associating the memory types (see Section
11.3, “Methods of Caching Available”) with physical-address ranges in system memory. They allow the processor
to optimize operations for different types of memory such as RAM, ROM, frame-buffer memory, and memorymapped I/O devices. They also simplify system hardware design by eliminating the memory control pins used for
this function on earlier IA-32 processors and the external logic needed to drive them.
The MTRR mechanism allows up to 96 memory ranges to be defined in physical memory, and it defines a set of
model-specific registers (MSRs) for specifying the type of memory that is contained in each range. Table 11-8
shows the memory types that can be specified and their properties; Figure 11-4 shows the mapping of physical
memory with MTRRs. See Section 11.3, “Methods of Caching Available,” for a more detailed description of each
memory type.
Following a hardware reset, the P6 and more recent processor families disable all the fixed and variable MTRRs,
which in effect makes all of physical memory uncacheable. Initialization software should then set the MTRRs to a
specific, system-defined memory map. Typically, the BIOS (basic input/output system) software configures the
MTRRs. The operating system or executive is then free to modify the memory map using the normal page-level
cacheability attributes.
In a multiprocessor system using a processor in the P6 family or a more recent family, each processor MUST use
the identical MTRR memory map so that software will have a consistent view of memory.
NOTE
In multiple processor systems, the operating system must maintain MTRR consistency between all
the processors in the system (that is, all processors must use the same MTRR values). The P6 and
more recent processor families provide no hardware support for maintaining this consistency.
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Table 11-8. Memory Types That Can Be Encoded in MTRRs
Memory Type and Mnemonic
Encoding in MTRR
Uncacheable (UC)
00H
Write Combining (WC)
01H
Reserved*
02H
Reserved*
03H
Write-through (WT)
04H
Write-protected (WP)
05H
Writeback (WB)
06H
Reserved*
7H through FFH
NOTE:
*
Use of these encodings results in a general-protection exception (#GP).
Physical Memory
FFFFFFFFH
Address ranges not
mapped by an MTRR
are set to a default type
Variable ranges
(from 4 KBytes to
maximum size of
physical memory)
64 fixed ranges
(4 KBytes each)
16 fixed ranges
(16 KBytes each)
8 fixed ranges
(64-KBytes each)
256 KBytes
256 KBytes
100000H
FFFFFH
C0000H
BFFFFH
80000H
7FFFFH
512 KBytes
0
Figure 11-4. Mapping Physical Memory With MTRRs
11.11.1 MTRR Feature Identification
The availability of the MTRR feature is model-specific. Software can determine if MTRRs are supported on a
processor by executing the CPUID instruction and reading the state of the MTRR flag (bit 12) in the feature information register (EDX).
If the MTRR flag is set (indicating that the processor implements MTRRs), additional information about MTRRs can
be obtained from the 64-bit IA32_MTRRCAP MSR (named MTRRcap MSR for the P6 family processors). The
IA32_MTRRCAP MSR is a read-only MSR that can be read with the RDMSR instruction. Figure 11-5 shows the
contents of the IA32_MTRRCAP MSR. The functions of the flags and field in this register are as follows:
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MEMORY CACHE CONTROL
•
VCNT (variable range registers count) field, bits 0 through 7 — Indicates the number of variable ranges
implemented on the processor.
•
FIX (fixed range registers supported) flag, bit 8 — Fixed range MTRRs (IA32_MTRR_FIX64K_00000
through IA32_MTRR_FIX4K_0F8000) are supported when set; no fixed range registers are supported when
clear.
•
WC (write combining) flag, bit 10 — The write-combining (WC) memory type is supported when set; the
WC type is not supported when clear.
•
SMRR (System-Management Range Register) flag, bit 11 — The system-management range register
(SMRR) interface is supported when bit 11 is set; the SMRR interface is not supported when clear.
Bit 9 and bits 12 through 63 in the IA32_MTRRCAP MSR are reserved. If software attempts to write to the
IA32_MTRRCAP MSR, a general-protection exception (#GP) is generated.
Software must read IA32_MTRRCAP VCNT field to determine the number of variable MTRRs and query other
feature bits in IA32_MTRRCAP to determine additional capabilities that are supported in a processor. For example,
some processors may report a value of ‘8’ in the VCNT field, other processors may report VCNT with different
values.
63
0
11 10 9 8 7
Reserved
W
C
F
I
X
VCNT
SMRR — SMRR interface supported
WC — Write-combining memory type supported
FIX — Fixed range registers supported
VCNT — Number of variable range registers
Reserved
Figure 11-5. IA32_MTRRCAP Register
11.11.2 Setting Memory Ranges with MTRRs
The memory ranges and the types of memory specified in each range are set by three groups of registers: the
IA32_MTRR_DEF_TYPE MSR, the fixed-range MTRRs, and the variable range MTRRs. These registers can be read
and written to using the RDMSR and WRMSR instructions, respectively. The IA32_MTRRCAP MSR indicates the
availability of these registers on the processor (see Section 11.11.1, “MTRR Feature Identification”).
11.11.2.1 IA32_MTRR_DEF_TYPE MSR
The IA32_MTRR_DEF_TYPE MSR (named MTRRdefType MSR for the P6 family processors) sets the default properties of the regions of physical memory that are not encompassed by MTRRs. The functions of the flags and field in
this register are as follows:
•
Type field, bits 0 through 7 — Indicates the default memory type used for those physical memory address
ranges that do not have a memory type specified for them by an MTRR (see Table 11-8 for the encoding of this
field). The legal values for this field are 0, 1, 4, 5, and 6. All other values result in a general-protection
exception (#GP) being generated.
Intel recommends the use of the UC (uncached) memory type for all physical memory addresses where
memory does not exist. To assign the UC type to nonexistent memory locations, it can either be specified as the
default type in the Type field or be explicitly assigned with the fixed and variable MTRRs.
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63
0
12 11 10 9 8 7
Reserved
E F
E
Type
E — MTRR enable/disable
FE — Fixed-range MTRRs enable/disable
Type — Default memory type
Reserved
Figure 11-6. IA32_MTRR_DEF_TYPE MSR
•
FE (fixed MTRRs enabled) flag, bit 10 — Fixed-range MTRRs are enabled when set; fixed-range MTRRs are
disabled when clear. When the fixed-range MTRRs are enabled, they take priority over the variable-range
MTRRs when overlaps in ranges occur. If the fixed-range MTRRs are disabled, the variable-range MTRRs can
still be used and can map the range ordinarily covered by the fixed-range MTRRs.
•
E (MTRRs enabled) flag, bit 11 — MTRRs are enabled when set; all MTRRs are disabled when clear, and the
UC memory type is applied to all of physical memory. When this flag is set, the FE flag can disable the fixedrange MTRRs; when the flag is clear, the FE flag has no affect. When the E flag is set, the type specified in the
default memory type field is used for areas of memory not already mapped by either a fixed or variable MTRR.
Bits 8 and 9, and bits 12 through 63, in the IA32_MTRR_DEF_TYPE MSR are reserved; the processor generates a
general-protection exception (#GP) if software attempts to write nonzero values to them.
11.11.2.2 Fixed Range MTRRs
The fixed memory ranges are mapped with 11 fixed-range registers of 64 bits each. Each of these registers is
divided into 8-bit fields that are used to specify the memory type for each of the sub-ranges the register controls:
•
Register IA32_MTRR_FIX64K_00000 — Maps the 512-KByte address range from 0H to 7FFFFH. This range
is divided into eight 64-KByte sub-ranges.
•
Registers IA32_MTRR_FIX16K_80000 and IA32_MTRR_FIX16K_A0000 — Maps the two 128-KByte
address ranges from 80000H to BFFFFH. This range is divided into sixteen 16-KByte sub-ranges, 8 ranges per
register.
•
Registers IA32_MTRR_FIX4K_C0000 through IA32_MTRR_FIX4K_F8000 — Maps eight 32-KByte
address ranges from C0000H to FFFFFH. This range is divided into sixty-four 4-KByte sub-ranges, 8 ranges per
register.
Table 11-9 shows the relationship between the fixed physical-address ranges and the corresponding fields of the
fixed-range MTRRs; Table 11-8 shows memory type encoding for MTRRs.
For the P6 family processors, the prefix for the fixed range MTRRs is MTRRfix.
11.11.2.3 Variable Range MTRRs
The Pentium 4, Intel Xeon, and P6 family processors permit software to specify the memory type for m variablesize address ranges, using a pair of MTRRs for each range. The number m of ranges supported is given in bits 7:0
of the IA32_MTRRCAP MSR (see Figure 11-5 in Section 11.11.1).
The first entry in each pair (IA32_MTRR_PHYSBASEn) defines the base address and memory type for the range;
the second entry (IA32_MTRR_PHYSMASKn) contains a mask used to determine the address range. The “n” suffix
is in the range 0 through m–1 and identifies a specific register pair.
For P6 family processors, the prefixes for these variable range MTRRs are MTRRphysBase and MTRRphysMask.
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Table 11-9. Address Mapping for Fixed-Range MTRRs
Address Range (hexadecimal)
MTRR
63 56
55 48
47 40
39 32
31
24
23
16
15
8
7
0
700007FFFF
600006FFFF
500005FFFF
400004FFFF
300003FFFF
200002FFFF
100001FFFF
000000FFFF
IA32_MTRR_
FIX64K_00000
9C000
9FFFF
980009BFFF
9400097FFF
9000093FFF
8C0008FFFF
880008BFFF
8400087FFF
8000083FFF
IA32_MTRR_
FIX16K_80000
BC000
BFFFF
B8000BBFFF
B4000B7FFF
B0000B3FFF
AC000AFFFF
A8000ABFFF
A4000A7FFF
A0000A3FFF
IA32_MTRR_
FIX16K_A0000
C7000
C7FFF
C6000C6FFF
C5000C5FFF
C4000C4FFF
C3000C3FFF
C2000C2FFF
C1000C1FFF
C0000C0FFF
IA32_MTRR_
FIX4K_C0000
CF000
CFFFF
CE000CEFFF
CD000CDFFF
CC000CCFFF
CB000CBFFF
CA000CAFFF
C9000C9FFF
C8000C8FFF
IA32_MTRR_
FIX4K_C8000
D7000
D7FFF
D6000D6FFF
D5000D5FFF
D4000D4FFF
D3000D3FFF
D2000D2FFF
D1000D1FFF
D0000D0FFF
IA32_MTRR_
FIX4K_D0000
DF000
DFFFF
DE000DEFFF
DD000DDFFF
DC000DCFFF
DB000DBFFF
DA000DAFFF
D9000D9FFF
D8000D8FFF
IA32_MTRR_
FIX4K_D8000
E7000
E7FFF
E6000E6FFF
E5000E5FFF
E4000E4FFF
E3000E3FFF
E2000E2FFF
E1000E1FFF
E0000E0FFF
IA32_MTRR_
FIX4K_E0000
EF000
EFFFF
EE000EEFFF
ED000EDFFF
EC000ECFFF
EB000EBFFF
EA000EAFFF
E9000E9FFF
E8000E8FFF
IA32_MTRR_
FIX4K_E8000
F7000
F7FFF
F6000F6FFF
F5000F5FFF
F4000F4FFF
F3000F3FFF
F2000F2FFF
F1000F1FFF
F0000F0FFF
IA32_MTRR_
FIX4K_F0000
FF000
FFFFF
FE000FEFFF
FD000FDFFF
FC000FCFFF
FB000FBFFF
FA000FAFFF
F9000F9FFF
F8000F8FFF
IA32_MTRR_
FIX4K_F8000
Figure 11-7 shows flags and fields in these registers. The functions of these flags and fields are:
•
Type field, bits 0 through 7 — Specifies the memory type for the range (see Table 11-8 for the encoding of
this field).
•
PhysBase field, bits 12 through (MAXPHYADDR-1) — Specifies the base address of the address range.
This 24-bit value, in the case where MAXPHYADDR is 36 bits, is extended by 12 bits at the low end to form the
base address (this automatically aligns the address on a 4-KByte boundary).
•
PhysMask field, bits 12 through (MAXPHYADDR-1) — Specifies a mask (24 bits if the maximum physical
address size is 36 bits, 28 bits if the maximum physical address size is 40 bits). The mask determines the range
of the region being mapped, according to the following relationships:
— Address_Within_Range AND PhysMask = PhysBase AND PhysMask
— This value is extended by 12 bits at the low end to form the mask value. For more information: see Section
11.11.3, “Example Base and Mask Calculations.”
— The width of the PhysMask field depends on the maximum physical address size supported by the
processor.
CPUID.80000008H reports the maximum physical address size supported by the processor. If
CPUID.80000008H is not available, software may assume that the processor supports a 36-bit physical
address size (then PhysMask is 24 bits wide and the upper 28 bits of IA32_MTRR_PHYSMASKn are
reserved). See the Note below.
•
V (valid) flag, bit 11 — Enables the register pair when set; disables register pair when clear.
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IA32_MTRR_PHYSBASEn Register
63
MAXPHYADDR 12 11
Reserved
0
8 7
PhysBase
Type
PhysBase — Base address of range
Type — Memory type for range
IA32_MTRR_PHYSMASKn Register
63
MAXPHYADDR
Reserved
0
12 11 10
PhysMask
V
Reserved
PhysMask — Sets range mask
V — Valid
Reserved
MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the maximum
physical address range supported by the processor. It is reported by CPUID leaf
function 80000008H. If CPUID does not support leaf 80000008H, the processor
supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, and
bits 63:36 are reserved.
Figure 11-7. IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn Variable-Range Register Pair
All other bits in the IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn registers are reserved; the processor
generates a general-protection exception (#GP) if software attempts to write to them.
Some mask values can result in ranges that are not continuous. In such ranges, the area not mapped by the mask
value is set to the default memory type, unless some other MTRR specifies a type for that range. Intel does not
encourage the use of “discontinuous” ranges.
NOTE
It is possible for software to parse the memory descriptions that BIOS provides by using the
ACPI/INT15 e820 interface mechanism. This information then can be used to determine how
MTRRs are initialized (for example: allowing the BIOS to define valid memory ranges and the
maximum memory range supported by the platform, including the processor).
See Section 11.11.4.1, “MTRR Precedences,” for information on overlapping variable MTRR ranges.
11.11.2.4 System-Management Range Register Interface
If IA32_MTRRCAP[bit 11] is set, the processor supports the SMRR interface to restrict access to a specified
memory address range used by system-management mode (SMM) software (see Section 34.4.2.1). If the SMRR
interface is supported, SMM software is strongly encouraged to use it to protect the SMI code and data stored by
SMI handler in the SMRAM region.
The system-management range registers consist of a pair of MSRs (see Figure 11-8). The IA32_SMRR_PHYSBASE
MSR defines the base address for the SMRAM memory range and the memory type used to access it in SMM. The
IA32_SMRR_PHYSMASK MSR contains a valid bit and a mask that determines the SMRAM address range protected
by the SMRR interface. These MSRs may be written only in SMM; an attempt to write them outside of SMM causes
a general-protection exception.1
Figure 11-8 shows flags and fields in these registers. The functions of these flags and fields are the following:
1. For some processor models, these MSRs can be accessed by RDMSR and WRMSR only if the SMRR interface has been enabled using
a model-specific bit in the IA32_FEATURE_CONTROL MSR.
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•
Type field, bits 0 through 7 — Specifies the memory type for the range (see Table 11-8 for the encoding of
this field).
•
PhysBase field, bits 12 through 31 — Specifies the base address of the address range. The address must be
less than 4 GBytes and is automatically aligned on a 4-KByte boundary.
•
PhysMask field, bits 12 through 31 — Specifies a mask that determines the range of the region being
mapped, according to the following relationships:
— Address_Within_Range AND PhysMask = PhysBase AND PhysMask
— This value is extended by 12 bits at the low end to form the mask value. For more information: see Section
11.11.3, “Example Base and Mask Calculations.”
•
V (valid) flag, bit 11 — Enables the register pair when set; disables register pair when clear.
Before attempting to access these SMRR registers, software must test bit 11 in the IA32_MTRRCAP register. If
SMRR is not supported, reads from or writes to registers cause general-protection exceptions.
When the valid flag in the IA32_SMRR_PHYSMASK MSR is 1, accesses to the specified address range are treated as
follows:
•
•
If the logical processor is in SMM, accesses uses the memory type in the IA32_SMRR_PHYSBASE MSR.
If the logical processor is not in SMM, write accesses are ignored and read accesses return a fixed value for each
byte. The uncacheable memory type (UC) is used in this case.
The above items apply even if the address range specified overlaps with a range specified by the MTRRs.
IA32_SMRR_PHYSBASE Register
63
31
Reserved
12 11
0
8 7
PhysBase
Type
PhysBase — Base address of range
Type — Memory type for range
IA32_SMRR_PHYSMASK Register
63
31
Reserved
0
12 11 10
PhysMask
V
Reserved
PhysMask — Sets range mask
V — Valid
Reserved
Figure 11-8. IA32_SMRR_PHYSBASE and IA32_SMRR_PHYSMASK SMRR Pair
11.11.3 Example Base and Mask Calculations
The examples in this section apply to processors that support a maximum physical address size of 36 bits. The base
and mask values entered in variable-range MTRR pairs are 24-bit values that the processor extends to 36-bits.
For example, to enter a base address of 2 MBytes (200000H) in the IA32_MTRR_PHYSBASE3 register, the 12 leastsignificant bits are truncated and the value 000200H is entered in the PhysBase field. The same operation must be
performed on mask values. For example, to map the address range from 200000H to 3FFFFFH (2 MBytes to 4
MBytes), a mask value of FFFE00000H is required. Again, the 12 least-significant bits of this mask value are truncated, so that the value entered in the PhysMask field of IA32_MTRR_PHYSMASK3 is FFFE00H. This mask is chosen
so that when any address in the 200000H to 3FFFFFH range is AND’d with the mask value, it will return the same
value as when the base address is AND’d with the mask value (which is 200000H).
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To map the address range from 400000H to 7FFFFFH (4 MBytes to 8 MBytes), a base value of 000400H is entered
in the PhysBase field and a mask value of FFFC00H is entered in the PhysMask field.
Example 11-2. Setting-Up Memory for a System
Here is an example of setting up the MTRRs for an system. Assume that the system has the following characteristics:
•
•
•
•
96 MBytes of system memory is mapped as write-back memory (WB) for highest system performance.
A custom 4-MByte I/O card is mapped to uncached memory (UC) at a base address of 64 MBytes. This
restriction forces the 96 MBytes of system memory to be addressed from 0 to 64 MBytes and from 68 MBytes
to 100 MBytes, leaving a 4-MByte hole for the I/O card.
An 8-MByte graphics card is mapped to write-combining memory (WC) beginning at address A0000000H.
The BIOS area from 15 MBytes to 16 MBytes is mapped to UC memory.
The following settings for the MTRRs will yield the proper mapping of the physical address space for this system
configuration.
IA32_MTRR_PHYSBASE0 = 0000 0000 0000 0006H
IA32_MTRR_PHYSMASK0 = 0000 000F FC00 0800H
Caches 0-64 MByte as WB cache type.
IA32_MTRR_PHYSBASE1 = 0000 0000 0400 0006H
IA32_MTRR_PHYSMASK1 = 0000 000F FE00 0800H
Caches 64-96 MByte as WB cache type.
IA32_MTRR_PHYSBASE2 = 0000 0000 0600 0006H
IA32_MTRR_PHYSMASK2 = 0000 000F FFC0 0800H
Caches 96-100 MByte as WB cache type.
IA32_MTRR_PHYSBASE3 = 0000 0000 0400 0000H
IA32_MTRR_PHYSMASK3 = 0000 000F FFC0 0800H
Caches 64-68 MByte as UC cache type.
IA32_MTRR_PHYSBASE4 = 0000 0000 00F0 0000H
IA32_MTRR_PHYSMASK4 = 0000 000F FFF0 0800H
Caches 15-16 MByte as UC cache type.
IA32_MTRR_PHYSBASE5 = 0000 0000 A000 0001H
IA32_MTRR_PHYSMASK5 = 0000 000F FF80 0800H
Caches A0000000-A0800000 as WC type.
This MTRR setup uses the ability to overlap any two memory ranges (as long as the ranges are mapped to WB and
UC memory types) to minimize the number of MTRR registers that are required to configure the memory environment. This setup also fulfills the requirement that two register pairs are left for operating system usage.
11.11.3.1 Base and Mask Calculations for Greater-Than 36-bit Physical Address Support
For Intel 64 and IA-32 processors that support greater than 36 bits of physical address size, software should query
CPUID.80000008H to determine the maximum physical address. See the example.
Example 11-3. Setting-Up Memory for a System with a 40-Bit Address Size
If a processor supports 40-bits of physical address size, then the PhysMask field (in IA32_MTRR_PHYSMASKn
registers) is 28 bits instead of 24 bits. For this situation, Example 11-2 should be modified as follows:
IA32_MTRR_PHYSBASE0 = 0000 0000 0000 0006H
IA32_MTRR_PHYSMASK0 = 0000 00FF FC00 0800H
Caches 0-64 MByte as WB cache type.
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IA32_MTRR_PHYSBASE1 = 0000 0000 0400 0006H
IA32_MTRR_PHYSMASK1 = 0000 00FF FE00 0800H
Caches 64-96 MByte as WB cache type.
IA32_MTRR_PHYSBASE2 = 0000 0000 0600 0006H
IA32_MTRR_PHYSMASK2 = 0000 00FF FFC0 0800H
Caches 96-100 MByte as WB cache type.
IA32_MTRR_PHYSBASE3 = 0000 0000 0400 0000H
IA32_MTRR_PHYSMASK3 = 0000 00FF FFC0 0800H
Caches 64-68 MByte as UC cache type.
IA32_MTRR_PHYSBASE4 = 0000 0000 00F0 0000H
IA32_MTRR_PHYSMASK4 = 0000 00FF FFF0 0800H
Caches 15-16 MByte as UC cache type.
IA32_MTRR_PHYSBASE5 = 0000 0000 A000 0001H
IA32_MTRR_PHYSMASK5 = 0000 00FF FF80 0800H
Caches A0000000-A0800000 as WC type.
11.11.4 Range Size and Alignment Requirement
A range that is to be mapped to a variable-range MTRR must meet the following “power of 2” size and alignment
rules:
1. The minimum range size is 4 KBytes and the base address of the range must be on at least a 4-KByte
boundary.
2. For ranges greater than 4 KBytes, each range must be of length 2n and its base address must be aligned on a
2n boundary, where n is a value equal to or greater than 12. The base-address alignment value cannot be less
than its length. For example, an 8-KByte range cannot be aligned on a 4-KByte boundary. It must be aligned on
at least an 8-KByte boundary.
11.11.4.1 MTRR Precedences
If the MTRRs are not enabled (by setting the E flag in the IA32_MTRR_DEF_TYPE MSR), then all memory accesses
are of the UC memory type. If the MTRRs are enabled, then the memory type used for a memory access is determined as follows:
1. If the physical address falls within the first 1 MByte of physical memory and fixed MTRRs are enabled, the
processor uses the memory type stored for the appropriate fixed-range MTRR.
2. Otherwise, the processor attempts to match the physical address with a memory type set by the variable-range
MTRRs:
— If one variable memory range matches, the processor uses the memory type stored in the
IA32_MTRR_PHYSBASEn register for that range.
— If two or more variable memory ranges match and the memory types are identical, then that memory type
is used.
— If two or more variable memory ranges match and one of the memory types is UC, the UC memory type
used.
— If two or more variable memory ranges match and the memory types are WT and WB, the WT memory type
is used.
— For overlaps not defined by the above rules, processor behavior is undefined.
3. If no fixed or variable memory range matches, the processor uses the default memory type.
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11.11.5 MTRR Initialization
On a hardware reset, the P6 and more recent processors clear the valid flags in variable-range MTRRs and clear the
E flag in the IA32_MTRR_DEF_TYPE MSR to disable all MTRRs. All other bits in the MTRRs are undefined.
Prior to initializing the MTRRs, software (normally the system BIOS) must initialize all fixed-range and variablerange MTRR register fields to 0. Software can then initialize the MTRRs according to known types of memory,
including memory on devices that it auto-configures. Initialization is expected to occur prior to booting the operating system.
See Section 11.11.8, “MTRR Considerations in MP Systems,” for information on initializing MTRRs in MP (multipleprocessor) systems.
11.11.6 Remapping Memory Types
A system designer may re-map memory types to tune performance or because a future processor may not implement all memory types supported by the Pentium 4, Intel Xeon, and P6 family processors. The following rules
support coherent memory-type re-mappings:
1. A memory type should not be mapped into another memory type that has a weaker memory ordering model.
For example, the uncacheable type cannot be mapped into any other type, and the write-back, write-through,
and write-protected types cannot be mapped into the weakly ordered write-combining type.
2. A memory type that does not delay writes should not be mapped into a memory type that does delay writes,
because applications of such a memory type may rely on its write-through behavior. Accordingly, the writeback type cannot be mapped into the write-through type.
3. A memory type that views write data as not necessarily stored and read back by a subsequent read, such as
the write-protected type, can only be mapped to another type with the same behaviour (and there are no
others for the Pentium 4, Intel Xeon, and P6 family processors) or to the uncacheable type.
In many specific cases, a system designer can have additional information about how a memory type is used,
allowing additional mappings. For example, write-through memory with no associated write side effects can be
mapped into write-back memory.
11.11.7 MTRR Maintenance Programming Interface
The operating system maintains the MTRRs after booting and sets up or changes the memory types for memorymapped devices. The operating system should provide a driver and application programming interface (API) to
access and set the MTRRs. The function calls MemTypeGet() and MemTypeSet() define this interface.
11.11.7.1 MemTypeGet() Function
The MemTypeGet() function returns the memory type of the physical memory range specified by the parameters
base and size. The base address is the starting physical address and the size is the number of bytes for the memory
range. The function automatically aligns the base address and size to 4-KByte boundaries. Pseudocode for the
MemTypeGet() function is given in Example 11-4.
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Example 11-4. MemTypeGet() Pseudocode
#define MIXED_TYPES -1
/* 0 < MIXED_TYPES || MIXED_TYPES > 256 */
IF CPU_FEATURES.MTRR /* processor supports MTRRs */
THEN
Align BASE and SIZE to 4-KByte boundary;
IF (BASE + SIZE) wrap 4-GByte address space
THEN return INVALID;
FI;
IF MTRRdefType.E = 0
THEN return UC;
FI;
FirstType ¨ Get4KMemType (BASE);
/* Obtains memory type for first 4-KByte range. */
/* See Get4KMemType (4KByteRange) in Example 11-5. */
FOR each additional 4-KByte range specified in SIZE
NextType ¨ Get4KMemType (4KByteRange);
IF NextType ¼ FirstType
THEN return MixedTypes;
FI;
ROF;
return FirstType;
ELSE return UNSUPPORTED;
FI;
If the processor does not support MTRRs, the function returns UNSUPPORTED. If the MTRRs are not enabled, then
the UC memory type is returned. If more than one memory type corresponds to the specified range, a status of
MIXED_TYPES is returned. Otherwise, the memory type defined for the range (UC, WC, WT, WB, or WP) is
returned.
The pseudocode for the Get4KMemType() function in Example 11-5 obtains the memory type for a single 4-KByte
range at a given physical address. The sample code determines whether an PHY_ADDRESS falls within a fixed
range by comparing the address with the known fixed ranges: 0 to 7FFFFH (64-KByte regions), 80000H to BFFFFH
(16-KByte regions), and C0000H to FFFFFH (4-KByte regions). If an address falls within one of these ranges, the
appropriate bits within one of its MTRRs determine the memory type.
Example 11-5. Get4KMemType() Pseudocode
IF IA32_MTRRCAP.FIX AND MTRRdefType.FE /* fixed registers enabled */
THEN IF PHY_ADDRESS is within a fixed range
return IA32_MTRR_FIX.Type;
FI;
FOR each variable-range MTRR in IA32_MTRRCAP.VCNT
IF IA32_MTRR_PHYSMASK.V = 0
THEN continue;
FI;
IF (PHY_ADDRESS AND IA32_MTRR_PHYSMASK.Mask) =
(IA32_MTRR_PHYSBASE.Base
AND IA32_MTRR_PHYSMASK.Mask)
THEN
return IA32_MTRR_PHYSBASE.Type;
FI;
ROF;
return MTRRdefType.Type;
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11.11.7.2 MemTypeSet() Function
The MemTypeSet() function in Example 11-6 sets a MTRR for the physical memory range specified by the parameters base and size to the type specified by type. The base address and size are multiples of 4 KBytes and the size
is not 0.
Example 11-6. MemTypeSet Pseudocode
IF CPU_FEATURES.MTRR (* processor supports MTRRs *)
THEN
IF BASE and SIZE are not 4-KByte aligned or size is 0
THEN return INVALID;
FI;
IF (BASE + SIZE) wrap 4-GByte address space
THEN return INVALID;
FI;
IF TYPE is invalid for Pentium 4, Intel Xeon, and P6 family
processors
THEN return UNSUPPORTED;
FI;
IF TYPE is WC and not supported
THEN return UNSUPPORTED;
FI;
IF IA32_MTRRCAP.FIX is set AND range can be mapped using a
fixed-range MTRR
THEN
pre_mtrr_change();
update affected MTRR;
post_mtrr_change();
FI;
ELSE (* try to map using a variable MTRR pair *)
IF IA32_MTRRCAP.VCNT = 0
THEN return UNSUPPORTED;
FI;
IF conflicts with current variable ranges
THEN return RANGE_OVERLAP;
FI;
IF no MTRRs available
THEN return VAR_NOT_AVAILABLE;
FI;
IF BASE and SIZE do not meet the power of 2 requirements for
variable MTRRs
THEN return INVALID_VAR_REQUEST;
FI;
pre_mtrr_change();
Update affected MTRRs;
post_mtrr_change();
FI;
pre_mtrr_change()
BEGIN
disable interrupts;
Save current value of CR4;
disable and flush caches;
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flush TLBs;
disable MTRRs;
IF multiprocessing
THEN maintain consistency through IPIs;
FI;
END
post_mtrr_change()
BEGIN
flush caches and TLBs;
enable MTRRs;
enable caches;
restore value of CR4;
enable interrupts;
END
The physical address to variable range mapping algorithm in the MemTypeSet function detects conflicts with
current variable range registers by cycling through them and determining whether the physical address in question
matches any of the current ranges. During this scan, the algorithm can detect whether any current variable ranges
overlap and can be concatenated into a single range.
The pre_mtrr_change() function disables interrupts prior to changing the MTRRs, to avoid executing code with a
partially valid MTRR setup. The algorithm disables caching by setting the CD flag and clearing the NW flag in control
register CR0. The caches are invalidated using the WBINVD instruction. The algorithm flushes all TLB entries either
by clearing the page-global enable (PGE) flag in control register CR4 (if PGE was already set) or by updating control
register CR3 (if PGE was already clear). Finally, it disables MTRRs by clearing the E flag in the
IA32_MTRR_DEF_TYPE MSR.
After the memory type is updated, the post_mtrr_change() function re-enables the MTRRs and again invalidates
the caches and TLBs. This second invalidation is required because of the processor's aggressive prefetch of both
instructions and data. The algorithm restores interrupts and re-enables caching by setting the CD flag.
An operating system can batch multiple MTRR updates so that only a single pair of cache invalidations occur.
11.11.8 MTRR Considerations in MP Systems
In MP (multiple-processor) systems, the operating systems must maintain MTRR consistency between all the
processors in the system. The Pentium 4, Intel Xeon, and P6 family processors provide no hardware support to
maintain this consistency. In general, all processors must have the same MTRR values.
This requirement implies that when the operating system initializes an MP system, it must load the MTRRs of the
boot processor while the E flag in register MTRRdefType is 0. The operating system then directs other processors to
load their MTRRs with the same memory map. After all the processors have loaded their MTRRs, the operating
system signals them to enable their MTRRs. Barrier synchronization is used to prevent further memory accesses
until all processors indicate that the MTRRs are enabled. This synchronization is likely to be a shoot-down style
algorithm, with shared variables and interprocessor interrupts.
Any change to the value of the MTRRs in an MP system requires the operating system to repeat the loading and
enabling process to maintain consistency, using the following procedure:
1. Broadcast to all processors to execute the following code sequence.
2. Disable interrupts.
3. Wait for all processors to reach this point.
4. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and the NW flag to 0.)
5. Flush all caches using the WBINVD instructions. Note on a processor that supports self-snooping, CPUID
feature flag bit 27, this step is unnecessary.
6. If the PGE flag is set in control register CR4, flush all TLBs by clearing that flag.
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7. If the PGE flag is clear in control register CR4, flush all TLBs by executing a MOV from control register CR3 to
another register and then a MOV from that register back to CR3.
8. Disable all range registers (by clearing the E flag in register MTRRdefType). If only variable ranges are being
modified, software may clear the valid bits for the affected register pairs instead.
9. Update the MTRRs.
10. Enable all range registers (by setting the E flag in register MTRRdefType). If only variable-range registers were
modified and their individual valid bits were cleared, then set the valid bits for the affected ranges instead.
11. Flush all caches and all TLBs a second time. (The TLB flush is required for Pentium 4, Intel Xeon, and P6 family
processors. Executing the WBINVD instruction is not needed when using Pentium 4, Intel Xeon, and P6 family
processors, but it may be needed in future systems.)
12. Enter the normal cache mode to re-enable caching. (Set the CD and NW flags in control register CR0 to 0.)
13. Set PGE flag in control register CR4, if cleared in Step 6 (above).
14. Wait for all processors to reach this point.
15. Enable interrupts.
11.11.9 Large Page Size Considerations
The MTRRs provide memory typing for a limited number of regions that have a 4 KByte granularity (the same granularity as 4-KByte pages). The memory type for a given page is cached in the processor’s TLBs. When using large
pages (2 MBytes, 4 MBytes, or 1 GBytes), a single page-table entry covers multiple 4-KByte granules, each with a
single memory type. Because the memory type for a large page is cached in the TLB, the processor can behave in
an undefined manner if a large page is mapped to a region of memory that MTRRs have mapped with multiple
memory types.
Undefined behavior can be avoided by insuring that all MTRR memory-type ranges within a large page are of the
same type. If a large page maps to a region of memory containing different MTRR-defined memory types, the PCD
and PWT flags in the page-table entry should be set for the most conservative memory type for that range. For
example, a large page used for memory mapped I/O and regular memory is mapped as UC memory. Alternatively,
the operating system can map the region using multiple 4-KByte pages each with its own memory type.
The requirement that all 4-KByte ranges in a large page are of the same memory type implies that large pages with
different memory types may suffer a performance penalty, since they must be marked with the lowest common
denominator memory type. The same consideration apply to 1 GByte pages, each of which may consist of multiple
2-Mbyte ranges.
The Pentium 4, Intel Xeon, and P6 family processors provide special support for the physical memory range from 0
to 4 MBytes, which is potentially mapped by both the fixed and variable MTRRs. This support is invoked when a
Pentium 4, Intel Xeon, or P6 family processor detects a large page overlapping the first 1 MByte of this memory
range with a memory type that conflicts with the fixed MTRRs. Here, the processor maps the memory range as
multiple 4-KByte pages within the TLB. This operation insures correct behavior at the cost of performance. To avoid
this performance penalty, operating-system software should reserve the large page option for regions of memory
at addresses greater than or equal to 4 MBytes.
11.12
PAGE ATTRIBUTE TABLE (PAT)
The Page Attribute Table (PAT) extends the IA-32 architecture’s page-table format to allow memory types to be
assigned to regions of physical memory based on linear address mappings. The PAT is a companion feature to the
MTRRs; that is, the MTRRs allow mapping of memory types to regions of the physical address space, where the PAT
allows mapping of memory types to pages within the linear address space. The MTRRs are useful for statically
describing memory types for physical ranges, and are typically set up by the system BIOS. The PAT extends the
functions of the PCD and PWT bits in page tables to allow all five of the memory types that can be assigned with the
MTRRs (plus one additional memory type) to also be assigned dynamically to pages of the linear address space.
The PAT was introduced to IA-32 architecture on the Pentium III processor. It is also available in the Pentium 4 and
Intel Xeon processors.
Vol. 3A 11-33
MEMORY CACHE CONTROL
11.12.1 Detecting Support for the PAT Feature
An operating system or executive can detect the availability of the PAT by executing the CPUID instruction with a
value of 1 in the EAX register. Support for the PAT is indicated by the PAT flag (bit 16 of the values returned to EDX
register). If the PAT is supported, the operating system or executive can use the IA32_PAT MSR to program the PAT.
When memory types have been assigned to entries in the PAT, software can then use of the PAT-index bit (PAT) in
the page-table and page-directory entries along with the PCD and PWT bits to assign memory types from the PAT
to individual pages.
Note that there is no separate flag or control bit in any of the control registers that enables the PAT. The PAT is
always enabled on all processors that support it, and the table lookup always occurs whenever paging is enabled,
in all paging modes.
11.12.2 IA32_PAT MSR
The IA32_PAT MSR is located at MSR address 277H (see Chapter 35, “Model-Specific Registers (MSRs)”). Figure
11-9. shows the format of the 64-bit IA32_PAT MSR.
The IA32_PAT MSR contains eight page attribute fields: PA0 through PA7. The three low-order bits of each field are
used to specify a memory type. The five high-order bits of each field are reserved, and must be set to all 0s. Each
of the eight page attribute fields can contain any of the memory type encodings specified in Table 11-10.
31
27
Reserved
26
PA3
24
23
19
Reserved
18
PA2
16
15
11
Reserved
10
PA1
8
7
3
Reserved
2
PA0
0
63
59
Reserved
58
PA7
56
55
51
Reserved
50
PA6
48
47
43
Reserved
42
PA5
40
39
35
Reserved
34
PA4
32
Figure 11-9. IA32_PAT MSR
Note that for the P6 family processors, the IA32_PAT MSR is named the PAT MSR.
Table 11-10. Memory Types That Can Be Encoded With PAT
Encoding
Mnemonic
00H
Uncacheable (UC)
01H
Write Combining (WC)
02H
Reserved*
03H
Reserved*
04H
Write Through (WT)
05H
Write Protected (WP)
06H
Write Back (WB)
07H
Uncached (UC-)
08H - FFH
Reserved*
NOTE:
* Using these encodings will result in a general-protection exception (#GP).
11-34 Vol. 3A
MEMORY CACHE CONTROL
11.12.3 Selecting a Memory Type from the PAT
To select a memory type for a page from the PAT, a 3-bit index made up of the PAT, PCD, and PWT bits must be
encoded in the page-table or page-directory entry for the page. Table 11-11 shows the possible encodings of the
PAT, PCD, and PWT bits and the PAT entry selected with each encoding. The PAT bit is bit 7 in page-table entries
that point to 4-KByte pages and bit 12 in paging-structure entries that point to larger pages. The PCD and PWT bits
are bits 4 and 3, respectively, in paging-structure entries that point to pages of any size.
The PAT entry selected for a page is used in conjunction with the MTRR setting for the region of physical memory
in which the page is mapped to determine the effective memory type for the page, as shown in Table 11-7.
Table 11-11. Selection of PAT Entries with PAT, PCD, and PWT Flags
PAT
PCD
PWT
PAT Entry
0
0
0
PAT0
0
0
1
PAT1
0
1
0
PAT2
0
1
1
PAT3
1
0
0
PAT4
1
0
1
PAT5
1
1
0
PAT6
1
1
1
PAT7
11.12.4 Programming the PAT
Table 11-12 shows the default setting for each PAT entry following a power up or reset of the processor. The setting
remain unchanged following a soft reset (INIT reset).
Table 11-12. Memory Type Setting of PAT Entries Following a Power-up or Reset
PAT Entry
Memory Type Following Power-up or Reset
PAT0
WB
PAT1
WT
PAT2
UC-
PAT3
UC
PAT4
WB
PAT5
WT
PAT6
UC-
PAT7
UC
The values in all the entries of the PAT can be changed by writing to the IA32_PAT MSR using the WRMSR instruction. The IA32_PAT MSR is read and write accessible (use of the RDMSR and WRMSR instructions, respectively) to
software operating at a CPL of 0. Table 11-10 shows the allowable encoding of the entries in the PAT. Attempting to
write an undefined memory type encoding into the PAT causes a general-protection (#GP) exception to be generated.
The operating system is responsible for insuring that changes to a PAT entry occur in a manner that maintains the
consistency of the processor caches and translation lookaside buffers (TLB). This is accomplished by following the
procedure as specified in Section 11.11.8, “MTRR Considerations in MP Systems,” for changing the value of an
MTRR in a multiple processor system. It requires a specific sequence of operations that includes flushing the
processors caches and TLBs.
The PAT allows any memory type to be specified in the page tables, and therefore it is possible to have a single
physical page mapped to two or more different linear addresses, each with different memory types. Intel does not
support this practice because it may lead to undefined operations that can result in a system failure. In particular,
a WC page must never be aliased to a cacheable page because WC writes may not check the processor caches.
Vol. 3A 11-35
MEMORY CACHE CONTROL
When remapping a page that was previously mapped as a cacheable memory type to a WC page, an operating
system can avoid this type of aliasing by doing the following:
1. Remove the previous mapping to a cacheable memory type in the page tables; that is, make them not
present.
2. Flush the TLBs of processors that may have used the mapping, even speculatively.
3. Create a new mapping to the same physical address with a new memory type, for instance, WC.
4. Flush the caches on all processors that may have used the mapping previously. Note on processors that support
self-snooping, CPUID feature flag bit 27, this step is unnecessary.
Operating systems that use a page directory as a page table (to map large pages) and enable page size extensions
must carefully scrutinize the use of the PAT index bit for the 4-KByte page-table entries. The PAT index bit for a
page-table entry (bit 7) corresponds to the page size bit in a page-directory entry. Therefore, the operating system
can only use PAT entries PA0 through PA3 when setting the caching type for a page table that is also used as a page
directory. If the operating system attempts to use PAT entries PA4 through PA7 when using this memory as a page
table, it effectively sets the PS bit for the access to this memory as a page directory.
For compatibility with earlier IA-32 processors that do not support the PAT, care should be taken in selecting the
encodings for entries in the PAT (see Section 11.12.5, “PAT Compatibility with Earlier IA-32 Processors”).
11.12.5 PAT Compatibility with Earlier IA-32 Processors
For IA-32 processors that support the PAT, the IA32_PAT MSR is always active. That is, the PCD and PWT bits in
page-table entries and in page-directory entries (that point to pages) are always select a memory type for a page
indirectly by selecting an entry in the PAT. They never select the memory type for a page directly as they do in
earlier IA-32 processors that do not implement the PAT (see Table 11-6).
To allow compatibility for code written to run on earlier IA-32 processor that do not support the PAT, the PAT mechanism has been designed to allow backward compatibility to earlier processors. This compatibility is provided
through the ordering of the PAT, PCD, and PWT bits in the 3-bit PAT entry index. For processors that do not implement the PAT, the PAT index bit (bit 7 in the page-table entries and bit 12 in the page-directory entries) is reserved
and set to 0. With the PAT bit reserved, only the first four entries of the PAT can be selected with the PCD and PWT
bits. At power-up or reset (see Table 11-12), these first four entries are encoded to select the same memory types
as the PCD and PWT bits would normally select directly in an IA-32 processor that does not implement the PAT. So,
if encodings of the first four entries in the PAT are left unchanged following a power-up or reset, code written to run
on earlier IA-32 processors that do not implement the PAT will run correctly on IA-32 processors that do implement
the PAT.
11-36 Vol. 3A
CHAPTER 12
INTEL MMX TECHNOLOGY SYSTEM PROGRAMMING
®
™
This chapter describes those features of the Intel® MMX™ technology that must be considered when designing or
enhancing an operating system to support MMX technology. It covers MMX instruction set emulation, the MMX
state, aliasing of MMX registers, saving MMX state, task and context switching considerations, exception handling,
and debugging.
12.1
EMULATION OF THE MMX INSTRUCTION SET
The IA-32 or Intel 64 architecture does not support emulation of the MMX instructions, as it does for x87 FPU
instructions. The EM flag in control register CR0 (provided to invoke emulation of x87 FPU instructions) cannot be
used for MMX instruction emulation. If an MMX instruction is executed when the EM flag is set, an invalid opcode
exception (UD#) is generated. Table 12-1 shows the interaction of the EM, MP, and TS flags in control register CR0
when executing MMX instructions.
Table 12-1. Action Taken By MMX Instructions for Different Combinations of EM, MP and TS
CR0 Flags
EM
MP*
TS
Action
0
1
0
Execute.
0
1
1
#NM exception.
1
1
0
#UD exception.
1
1
1
#UD exception.
NOTE:
* For processors that support the MMX instructions, the MP flag should be set.
12.2
THE MMX STATE AND MMX REGISTER ALIASING
The MMX state consists of eight 64-bit registers (MM0 through MM7). These registers are aliased to the low 64-bits
(bits 0 through 63) of floating-point registers R0 through R7 (see Figure 12-1). Note that the MMX registers are
mapped to the physical locations of the floating-point registers (R0 through R7), not to the relative locations of the
registers in the floating-point register stack (ST0 through ST7). As a result, the MMX register mapping is fixed and
is not affected by value in the Top Of Stack (TOS) field in the floating-point status word (bits 11 through 13).
Vol. 3A 12-1
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
x87 FPU Tag
Register
79
64 63
Floating-Point Registers
0
00
R7
00
R6
00
R5
00
R4
00
R3
00
R2
00
R1
00
R0
x87 FPU Status Register
13 11
000
63
TOS
MMX Registers
0
MM7
MM6
MM5
MM4
MM3
MM2
TOS = 0
MM1
MM0
Figure 12-1. Mapping of MMX Registers to Floating-Point Registers
When a value is written into an MMX register using an MMX instruction, the value also appears in the corresponding
floating-point register in bits 0 through 63. Likewise, when a floating-point value written into a floating-point
register by a x87 FPU, the low 64 bits of that value also appears in a the corresponding MMX register.
The execution of MMX instructions have several side effects on the x87 FPU state contained in the floating-point
registers, the x87 FPU tag word, and the x87 FPU status word. These side effects are as follows:
•
When an MMX instruction writes a value into an MMX register, at the same time, bits 64 through 79 of the corresponding floating-point register are set to all 1s.
•
When an MMX instruction (other than the EMMS instruction) is executed, each of the tag fields in the x87 FPU
tag word is set to 00B (valid). (See also Section 12.2.1, “Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR
Instructions on the x87 FPU Tag Word.”)
•
•
When the EMMS instruction is executed, each tag field in the x87 FPU tag word is set to 11B (empty).
Each time an MMX instruction is executed, the TOS value is set to 000B.
Execution of MMX instructions does not affect the other bits in the x87 FPU status word (bits 0 through 10 and bits
14 and 15) or the contents of the other x87 FPU registers that comprise the x87 FPU state (the x87 FPU control
word, instruction pointer, data pointer, or opcode registers).
Table 12-2 summarizes the effects of the MMX instructions on the x87 FPU state.
12-2 Vol. 3A
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
Table 12-2. Effects of MMX Instructions on x87 FPU State
MMX Instruction
Type
x87 FPU Tag
Word
TOS Field of x87 Other x87 FPU
FPU Status Word Registers
Bits 64 Through 79
of x87 FPU Data
Registers
Bits 0 Through 63
of x87 FPU Data
Registers
Read from MMX
register
All tags set to 00B
(Valid)
000B
Unchanged
Unchanged
Unchanged
Write to MMX
register
All tags set to 00B
(Valid)
000B
Unchanged
Set to all 1s
Overwritten with
MMX data
EMMS
All fields set to
11B (Empty)
000B
Unchanged
Unchanged
Unchanged
12.2.1
Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR
Instructions on the x87 FPU Tag Word
Table 12-3 summarizes the effect of MMX and x87 FPU instructions and the FXSAVE and FXRSTOR instructions on
the tags in the x87 FPU tag word and the corresponding tags in an image of the tag word stored in memory.
The values in the fields of the x87 FPU tag word do not affect the contents of the MMX registers or the execution of
MMX instructions. However, the MMX instructions do modify the contents of the x87 FPU tag word, as is described
in Section 12.2, “The MMX State and MMX Register Aliasing.” These modifications may affect the operation of the
x87 FPU when executing x87 FPU instructions, if the x87 FPU state is not initialized or restored prior to beginning
x87 FPU instruction execution.
Note that the FSAVE, FXSAVE, and FSTENV instructions (which save x87 FPU state information) read the x87 FPU
tag register and contents of each of the floating-point registers, determine the actual tag values for each register
(empty, nonzero, zero, or special), and store the updated tag word in memory. After executing these instructions,
all the tags in the x87 FPU tag word are set to empty (11B). Likewise, the EMMS instruction clears MMX state from
the MMX/floating-point registers by setting all the tags in the x87 FPU tag word to 11B.
Table 12-3. Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions on the x87 FPU Tag Word
Instruction
Type
Instruction
x87 FPU Tag Word
Image of x87 FPU Tag Word Stored in
Memory
MMX
All (except EMMS)
All tags are set to 00B (valid).
Not affected.
MMX
EMMS
All tags are set to 11B (empty).
Not affected.
x87 FPU
All (except FSAVE,
FSTENV, FRSTOR,
FLDENV)
Tag for modified floating-point register is
set to 00B or 11B.
Not affected.
x87 FPU and
FXSAVE
FSAVE, FSTENV, FXSAVE
Tags and register values are read and
interpreted; then all tags are set to 11B.
Tags are set according to the actual
values in the floating-point registers;
that is, empty registers are marked 11B
and valid registers are marked 00B
(nonzero), 01B (zero), or 10B (special).
x87 FPU and
FXRSTOR
FRSTOR, FLDENV,
FXRSTOR
All tags marked 11B in memory are set
to 11B; all other tags are set according
to the value in the corresponding
floating-point register: 00B (nonzero),
01B (zero), or 10B (special).
Tags are read and interpreted, but not
modified.
12.3
SAVING AND RESTORING THE MMX STATE AND REGISTERS
Because the MMX registers are aliased to the x87 FPU data registers, the MMX state can be saved to memory and
restored from memory as follows:
Vol. 3A 12-3
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
•
Execute an FSAVE, FNSAVE, or FXSAVE instruction to save the MMX state to memory. (The FXSAVE instruction
also saves the state of the XMM and MXCSR registers.)
•
Execute an FRSTOR or FXRSTOR instruction to restore the MMX state from memory. (The FXRSTOR instruction
also restores the state of the XMM and MXCSR registers.)
The save and restore methods described above are required for operating systems (see Section 12.4, “Saving MMX
State on Task or Context Switches”). Applications can in some cases save and restore only the MMX registers in the
following way:
•
Execute eight MOVQ instructions to save the contents of the MMX0 through MMX7 registers to memory. An
EMMS instruction may then (optionally) be executed to clear the MMX state in the x87 FPU.
•
Execute eight MOVQ instructions to read the saved contents of MMX registers from memory into the MMX0
through MMX7 registers.
NOTE
The IA-32 architecture does not support scanning the x87 FPU tag word and then only saving valid
entries.
12.4
SAVING MMX STATE ON TASK OR CONTEXT SWITCHES
When switching from one task or context to another, it is often necessary to save the MMX state. As a general rule,
if the existing task switching code for an operating system includes facilities for saving the state of the x87 FPU,
these facilities can also be relied upon to save the MMX state, without rewriting the task switch code. This reliance
is possible because the MMX state is aliased to the x87 FPU state (see Section 12.2, “The MMX State and MMX
Register Aliasing”).
With the introduction of the FXSAVE and FXRSTOR instructions and of SSE/SSE2/SSE3/SSSE3 extensions, it is
possible (and more efficient) to create state saving facilities in the operating system or executive that save the x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3 state in one operation. Section 13.4, “Designing OS Facilities for Saving x87
FPU, SSE AND EXTENDED States on Task or Context Switches,” describes how to design such facilities. The techniques describes in this section can be adapted to saving only the MMX and x87 FPU state if needed.
12.5
EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS
MMX instructions do not generate x87 FPU floating-point exceptions, nor do they affect the processor’s status flags
in the EFLAGS register or the x87 FPU status word. The following exceptions can be generated during the execution
of an MMX instruction:
•
Exceptions during memory accesses:
— Stack-segment fault (#SS).
— General protection (#GP).
— Page fault (#PF).
— Alignment check (#AC), if alignment checking is enabled.
•
System exceptions:
— Invalid Opcode (#UD), if the EM flag in control register CR0 is set when an MMX instruction is executed (see
Section 12.1, “Emulation of the MMX Instruction Set”).
— Device not available (#NM), if an MMX instruction is executed when the TS flag in control register CR0 is
set. (See Section 13.4.1, “Using the TS Flag to Control the Saving of the x87 FPU and SSE State.”)
•
Floating-point error (#MF). (See Section 12.5.1, “Effect of MMX Instructions on Pending x87 Floating-Point
Exceptions.”)
•
Other exceptions can occur indirectly due to the faulty execution of the exception handlers for the above
exceptions.
12-4 Vol. 3A
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
12.5.1
Effect of MMX Instructions on Pending x87 Floating-Point Exceptions
If an x87 FPU floating-point exception is pending and the processor encounters an MMX instruction, the processor
generates a x87 FPU floating-point error (#MF) prior to executing the MMX instruction, to allow the pending exception to be handled by the x87 FPU floating-point error exception handler. While this exception handler is executing,
the x87 FPU state is maintained and is visible to the handler. Upon returning from the exception handler, the MMX
instruction is executed, which will alter the x87 FPU state, as described in Section 12.2, “The MMX State and MMX
Register Aliasing.”
12.6
DEBUGGING MMX CODE
The debug facilities operate in the same manner when executing MMX instructions as when executing other IA-32
or Intel 64 architecture instructions.
To correctly interpret the contents of the MMX or x87 FPU registers from the FSAVE/FNSAVE or FXSAVE image in
memory, a debugger needs to take account of the relationship between the x87 FPU register’s logical locations
relative to TOS and the MMX register’s physical locations.
In the x87 FPU context, STn refers to an x87 FPU register at location n relative to the TOS. However, the tags in the
x87 FPU tag word are associated with the physical locations of the x87 FPU registers (R0 through R7). The MMX
registers always refer to the physical locations of the registers (with MM0 through MM7 being mapped to R0
through R7). Figure 12-2 shows this relationship. Here, the inner circle refers to the physical location of the x87
FPU and MMX registers. The outer circle refers to the x87 FPU registers’s relative location to the current TOS.
When the TOS equals 0 (case A in Figure 12-2), ST0 points to the physical location R0 on the floating-point stack.
MM0 maps to ST0, MM1 maps to ST1, and so on.
When the TOS equals 2 (case B in Figure 12-2), ST0 points to the physical location R2. MM0 maps to ST6, MM1
maps to ST7, MM2 maps to ST0, and so on.
x87 FPU “push”
ST7
MM7
MM6
ST0
MM0
(R0)
TOS
x87 FPU “pop”
ST6
ST1
MM7
MM1
MM2
(R2)
ST2
MM6
ST7
MM1
MM2
(R2)
ST0
MM3
MM4
MM4
Case A: TOS=0
TOS
MM5
MM3
MM5
MM0
(R0)
x87 FPU “push”
x87 FPU “pop”
ST1
Case B: TOS=2
Outer circle = x87 FPU data register’s logical location relative to TOS
Inner circle = x87 FPU tags = MMX register’s location = FP registers’s physical location
Figure 12-2. Mapping of MMX Registers to x87 FPU Data Register Stack
Vol. 3A 12-5
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
12-6 Vol. 3A
CHAPTER 13
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
PROCESSOR EXTENDED STATES
This chapter describes system programming features for instruction set extensions operating on the processor
state extension known as the SSE state (XMM registers, MXCSR) and for other processor extended states. Instruction set extensions operating on the SSE state include the streaming SIMD extensions (SSE), streaming SIMD
extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), Supplemental SSE3 (SSSE3), and SSE4. Collectively,
these are called SSE extensions1 and the corresponding instructions SSE instructions. FXSAVE/FXRSTOR
instructions can be used save/restore SSE state along with FP state. See Section 10.5 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1 for information about FXSAVE and FXRSTOR.
Sections 13.1 through 13.4 cover system programming requirements to enable the SSE extensions, providing
operating system or executive support for the SSE extensions, SIMD floating-point exceptions, exception handling,
and task (context) switching. These sections primarily discuss use of FXSAVE/FXRSTOR to save/restore SSE state.
XSAVE feature set refers to extensions to the Intel architecture that will allow system executives to implement
support for multiple processor extended states along with FP/SSE states that may be introduced over time without
requiring the system executive to be modified each time a new processor state extension is introduced. XSAVE
feature set provide mechanisms to enumerate the supported extended states, enable some or all of them for software use, instructions to save/restore the states and enumerate the layout of the states when saved to memory.
XSAVE/XRSTOR instructions are part of the XSAVE feature set. These instructions are introduced after the introduction of FP/SSE states but can be used to manage legacy FP/SSE state along with processor extended states. See
CHAPTER 13 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for information
about XSAVE feature set.
System programming for managing processor extended states is described in sections 13.5 through 13.6. XSAVE
feature set is designed to be compatible with FXSAVE/FXRSTOR and hence much of the material through sections
13.1 to 13.4 related to SSE state also applies to XSAVE feature set with the exception of enumeration and
saving/restoring state.
XSAVE Compaction is an XSAVE feature that allows operating systems to allocate space for only the states saved
to conserve memory usage. A new instruction called XSAVEC is introduced to save extended states in compacted
format and XRSTOR instruction is enhanced to comprehend compacted format. System programming for managing
processor extended states in compacted format is also described in section 13.5.
Supervisor state is an extended state that can only be accessed in ring 0. XSAVE feature set has been enhanced
to manage supervisor states. Two new ring 0 instructions, XSAVES/XRSTORS, are introduced to save/restore
supervisor states along with other XSAVE managed states. They are privileged instruction and only operate in
compacted format. System programming for managing supervisor states in described in section 13.7.
Each XSAVE managed features may have additional feature specific system programming requirements such as
exception handlers etc. Feature specific system programming requirements for XSAVE managed features are
described in section 13.8.
13.1
PROVIDING OPERATING SYSTEM SUPPORT FOR SSE EXTENSIONS
To use SSE extensions, the operating system or executive must provide support for initializing the processor to use
these extensions, for handling SIMD floating-point exceptions, and for using FXSAVE and FXRSTOR (Section 10.5
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1) to manage context. XSAVE
feature set can also be used to manage SSE state along with other processor extended states as described in 13.5.
This section primarily focuses on using FXSAVE/FXRSTOR to manage SSE state. Because SSE extensions share the
same state, experience the same sets of non-numerical and numerical exception behavior, these guidelines that
apply to SSE also apply to other sets of SIMD extensions that operate on the same processor state and subject to
the same sets of non-numerical and numerical exception behavior.
1. The collection also includes PCLMULQDQ and AES instructions operating on XMM state.
Vol. 3A 13-1
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2)” and Chapter 12, “Programming with SSE3,
SSSE3 and SSE4,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, provide
details on SSE instruction set.
13.1.1
Adding Support to an Operating System for SSE Extensions
The following guidelines describe functions that an operating system or executive must perform to support SSE
extensions:
1. Check that the processor supports the SSE extensions.
2. Check that the processor supports the FXSAVE and FXRSTOR instructions or the XSAVE feature set.
3. Provide an initialization for the SSE states.
4. Provide support for the FXSAVE and FXRSTOR instructions or the XSAVE feature set.
5. Provide support (if necessary) in non-numeric exception handlers for exceptions generated by the SSE instructions.
6. Provide an exception handler for the SIMD floating-point exception (#XM).
The following sections describe how to implement each of these guidelines.
13.1.2
Checking for CPU Support
If the processor attempts to execute an unsupported SSE instruction, the processor generates an invalid-opcode
exception (#UD). Before an operating system or executive attempts to use SSE extensions, it should check that
support is present by confirming the following bit values returned by the CPUID instruction:
•
•
•
•
•
•
CPUID.1:EDX.SSE[bit 25] = 1
CPUID.1:EDX.SSE2[bit 26] = 1
CPUID.1:ECX.SSE3[bit 0] = 1
CPUID.1:ECX.SSSE3[bit 9] = 1
CPUID.1:ECX.SSE4_1[bit 19] = 1
CPUID.1:ECX.SSE4_2[bit 20] = 1
(To use POPCNT instruction, software must check CPUID.1:ECX.POPCNT[bit 23] = 1.)
Separate checks must be made to ensure that the processor supports either FXSAVE and FXRSTOR or the XSAVE
feature set. See Section 10.5 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 and
Chapter 13 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, respectively.
13.1.3
Initialization of the SSE Extensions
The operating system or executive should carry out the following steps to set up SSE extensions for use by application programs:
1. Set CR4.OSFXSR[bit 9] = 1. Setting this flag implies that the operating system provides facilities for saving
and restoring SSE state using FXSAVE and FXRSTOR instructions. These instructions may be used to save the
SSE state during task switches and when invoking the SIMD floating-point exception (#XM) handler (see
Section 13.1.5, “Providing a Handler for the SIMD Floating-Point Exception (#XM)”).
If the processor does not support the FXSAVE and FXRSTOR instructions, attempting to set the OSFXSR flag
causes a general-protection exception (#GP) to be generated.
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2. Set CR4.OSXMMEXCPT[bit 10] = 1. Setting this flag implies that the operating system provides a SIMD
floating-point exception (#XM) handler (see Section 13.1.5, “Providing a Handler for the SIMD Floating-Point
Exception (#XM)”).
NOTE
The OSFXSR and OSXMMEXCPT bits in control register CR4 must be set by the operating system.
The processor has no other way of detecting operating-system support for the FXSAVE and
FXRSTOR instructions or for handling SIMD floating-point exceptions.
3. Clear CR0.EM[bit 2] = 0. This action disables emulation of the x87 FPU, which is required when executing SSE
instructions (see Section 2.5, “Control Registers”).
4. Set CR0.MP[bit 1] = 1. This setting is required for Intel 64 and IA-32 processors that support the SSE
extensions (see Section 9.2.1, “Configuring the x87 FPU Environment”).
Table 13-1 and Table 13-2 show the actions of the processor when an SSE instruction is executed, depending on
the following:
•
•
•
OSFXSR and OSXMMEXCPT flags in control register CR4
SSE/SSE2/SSE3/SSSE3/SSE4 feature flags returned by CPUID
EM, MP, and TS flags in control register CR0
Table 13-1. Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2, SSE3, EM, MP, and TS1
CR4
CPUID
CR0 Flags
OSFXSR
OSXMMEXCPT
SSE, SSE2,
SSE32,
SSE4_13
EM
MP4
TS
0
X5
X
X
1
X
#UD exception.
1
X
0
X
1
X
#UD exception.
1
X
1
1
1
X
#UD exception.
1
0
1
0
1
0
Execute instruction; #UD exception if unmasked
SIMD floating-point exception is detected.
1
1
1
0
1
0
Execute instruction; #XM exception if unmasked
SIMD floating-point exception is detected.
1
X
1
0
1
1
#NM exception.
Action
NOTES:
1. For execution of any SSE instruction except the PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH instructions.
2. Exception conditions due to CR4.OSFXSR or CR4.OSXMMEXCPT do not apply to FISTTP.
3. Only applies to DPPS, DPPD, ROUNDPS, ROUNDPD, ROUNDSS, ROUNDSD.
4. For processors that support the MMX instructions, the MP flag should be set.
5. X = Don’t care.
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Table 13-2. Action Taken for Combinations of OSFXSR, SSSE3, SSE4, EM, and TS
CR4
CPUID
CR0 Flags
OSFXSR
SSSE3
SSE4_11
SSE4_22
EM
TS
0
X3
X
X
#UD exception.
1
0
X
X
#UD exception.
1
1
1
X
#UD exception.
1
1
0
1
#NM exception.
Action
NOTES:
1. Applies to SSE4_1 instructions except DPPS, DPPD, ROUNDPS, ROUNDPD, ROUNDSS, ROUNDSD.
2. Applies to SSE4_2 instructions except CRC32 and POPCNT.
3. X = Don’t care.
The SIMD floating-point exception mask bits (bits 7 through 12), the flush-to-zero flag (bit 15), the denormals-arezero flag (bit 6), and the rounding control field (bits 13 and 14) in the MXCSR register should be left in their default
values of 0. This permits the application to determine how these features are to be used.
13.1.4
Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE
Instructions
SSE instructions can generate the same type of memory-access exceptions (such as page faults and limit violations) and other non-numeric exceptions as other Intel 64 and IA-32 architecture instructions generate.
Ordinarily, existing exception handlers can handle these and other non-numeric exceptions without code modification. However, depending on the mechanisms used in existing exception handlers, some modifications might need
to be made.
The SSE extensions can generate the non-numeric exceptions listed below:
•
Memory Access Exceptions:
— Stack-segment fault (#SS).
— General protection exception (#GP). Executing most SSE instructions with an unaligned 128-bit memory
reference generates a general-protection exception. (The MOVUPS and MOVUPD instructions allow
unaligned a loads or stores of 128-bit memory locations, without generating a general-protection
exception.) A 128-bit reference within the stack segment that is not aligned to a 16-byte boundary will also
generate a general-protection exception, instead a stack-segment fault exception (#SS).
— Page fault (#PF).
— Alignment check (#AC). When enabled, this type of alignment check operates on operands that are less
than 128-bits in size: 16-bit, 32-bit, and 64-bit. To enable the generation of alignment check exceptions, do
the following:
•
•
•
Set the AM flag (bit 18 of control register CR0)
Set the AC flag (bit 18 of the EFLAGS register)
CPL must be 3
If alignment check exceptions are enabled, 16-bit, 32-bit, and 64-bit misalignment will be detected for the
MOVUPD and MOVUPS instructions; detection of 128-bit misalignment is not guaranteed and may vary
with implementation.
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•
System Exceptions:
— Invalid-opcode exception (#UD). This exception is generated when executing SSE instructions under the
following conditions:
•
SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 feature flags returned by CPUID are set to 0. This condition
does not affect the CLFLUSH instruction, nor POPCNT.
•
The CLFSH feature flag returned by the CPUID instruction is set to 0. This exception condition only
pertains to the execution of the CLFLUSH instruction.
•
The POPCNT feature flag returned by the CPUID instruction is set to 0. This exception condition only
pertains to the execution of the POPCNT instruction.
•
The EM flag (bit 2) in control register CR0 is set to 1, regardless of the value of TS flag (bit 3) of CR0.
This condition does not affect the PAUSE, PREFETCHh, MOVNTI, SFENCE, LFENCE, MFENCE, CLFLUSH,
CRC32 and POPCNT instructions.
•
The OSFXSR flag (bit 9) in control register CR4 is set to 0. This condition does not affect the PSHUFW,
MOVNTQ, MOVNTI, PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, CLFLUSH, CRC32 and POPCNT
instructions.
•
Executing an instruction that causes a SIMD floating-point exception when the OSXMMEXCPT flag (bit
10) in control register CR4 is set to 0. See Section 13.4.1, “Using the TS Flag to Control the Saving of
the x87 FPU and SSE State.”
— Device not available (#NM). This exception is generated by executing a SSE instruction when the TS flag
(bit 3) of CR0 is set to 1.
Other exceptions can occur during delivery of the above exceptions.
13.1.5
Providing a Handler for the SIMD Floating-Point Exception (#XM)
SSE instructions do not generate numeric exceptions on packed integer operations. They can generate the
following numeric (SIMD floating-point) exceptions on packed and scalar single-precision and double-precision
floating-point operations.
•
•
•
•
•
•
Invalid operation (#I)
Divide-by-zero (#Z)
Denormal operand (#D)
Numeric overflow (#O)
Numeric underflow (#U)
Inexact result (Precision) (#P)
These SIMD floating-point exceptions (with the exception of the denormal operand exception) are defined in the
IEEE Standard 754 for Binary Floating-Point Arithmetic and represent the same conditions that cause x87 FPU
floating-point error exceptions (#MF) to be generated for x87 FPU instructions.
Each of these exceptions can be masked, in which case the processor returns a reasonable result to the destination
operand without invoking an exception handler. However, if any of these exceptions are left unmasked, detection
of the exception condition results in a SIMD floating-point exception (#XM) being generated. See Chapter 6,
“Interrupt 19—SIMD Floating-Point Exception (#XM).”
To handle unmasked SIMD floating-point exceptions, the operating system or executive must provide an exception
handler. The section titled “SSE and SSE2 SIMD Floating-Point Exceptions” in Chapter 11, “Programming with
Streaming SIMD Extensions 2 (SSE2),” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, describes the SIMD floating-point exception classes and gives suggestions for writing an exception
handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point exceptions (#XM), the OSXMMEXCPT flag (bit 10) must be set in control register CR4.
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13.1.5.1
Numeric Error flag and IGNNE#
SSE extensions ignore the NE flag in control register CR0 (that is, they treat it as if it were always set) and the
IGNNE# pin. When an unmasked SIMD floating-point exception is detected, it is always reported by generating a
SIMD floating-point exception (#XM).
13.2
EMULATION OF SSE EXTENSIONS
The Intel 64 and IA-32 architectures do not support emulation of the SSE instructions, as they do for x87 FPU
instructions.
The EM flag in control register CR0 (provided to invoke emulation of x87 FPU instructions) cannot be used to invoke
emulation of SSE instructions. If an SSE instruction is executed when CR0.EM = 1, an invalid opcode exception
(#UD) is generated. See Table 13-1.
13.3
SAVING AND RESTORING SSE STATE
The SSE state consists of the state of the XMM and MXCSR registers. Intel recommends the following method for
saving and restoring this state:
•
•
Execute the FXSAVE instruction to save the state of the XMM and MXCSR registers to memory.
Execute the FXRSTOR instruction to restore the state of the XMM and MXCSR registers from the image saved in
memory earlier.
This save and restore method is required for all operating systems. XSAVE feature set can also be used to
save/restore SSE state. See Section 13.5, “The XSAVE Feature Set and Processor Extended State Management,”
for using the XSAVE feature set to save/restore SSE state.
In some cases, applications may choose to save only the XMM and MXCSR registers in the following manner:
•
•
Execute MOVDQ instructions to save the contents of the XMM registers to memory.
Execute a STMXCSR instruction to save the state of the MXCSR register to memory.
Such applications must restore the XMM and MXCSR registers as follows:
•
Execute MOVDQ instructions to load the saved contents of the XMM registers from memory into the XMM
registers.
•
Execute a LDMXCSR instruction to restore the state of the MXCSR register from memory.
13.4
DESIGNING OS FACILITIES FOR SAVING X87 FPU, SSE AND EXTENDED
STATES ON TASK OR CONTEXT SWITCHES
The x87 FPU and SSE state consist of the state of the x87 FPU, XMM, and MXCSR registers. The FXSAVE and
FXRSTOR instructions provide a fast method for saving and restoring this state. The XSAVE feature set can also be
used to save FP and SSE state along with other extended states (see Section 13.5).
Older operating systems may use FSAVE/FNSAVE and FRSTOR to save the x87 FPU state. These facilities can be
extended to save and restore SSE state by substituting FXSAVE and FXRSTOR or the XSAVE feature set in place of
FSAVE/FNSAVE and FRSTOR.
If task or context switching facilities are written from scratch, any of several approaches may be taken for using the
FXSAVE and FXRSTOR instructions or the XSAVE feature set to save and restore x87 FPU and SSE state:
•
The operating system can require applications that are intended to be run as tasks take responsibility for saving
the states prior to a task suspension during a task switch and for restoring the states when the task is resumed.
This approach is appropriate for cooperative multitasking operating systems, where the application has control
over (or is able to determine) when a task switch is about to occur and can save state prior to the task switch.
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•
The operating system can take the responsibility for saving the states as part of the task switch process and
restoring the state of the registers when a suspended task is resumed. This approach is appropriate for
preemptive multitasking operating systems, where the application cannot know when it is going to be
preempted and cannot prepare in advance for task switching.
•
The operating system can take the responsibility for saving the states as part of the task switch process, but
delay the restoring of the states until an instruction operating on the states is actually executed by the new
task. See Section 13.4.1, “Using the TS Flag to Control the Saving of the x87 FPU and SSE State,” for more
information. This approach is called lazy restore.
The use of lazy restore mechanism in context switches is not recommended when XSAVE feature set is used to
save/restore states for the following reasons.
— With XSAVE feature set, Intel processors have optimizations in place to avoid saving the state components
that are in their initial configurations or when they have not been modified since they were restored last.
These optimizations eliminate the need for lazy restore. See section 13.5.4 in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
— Intel processors have power optimizations when state components are in their initial configurations. Use of
lazy restore retains the non-initial configuration of the last thread and is not power efficient.
— Not all extended states support lazy restore mechanisms. As such, when one or more such states are
enabled it becomes very inefficient to use lazy restore as it results in two separate state restore, one in
context switch for the states that does not support lazy restore and one in the #NM handler for states that
support lazy restore.
13.4.1
Using the TS Flag to Control the Saving of the x87 FPU and SSE State
The TS flag in control register CR0 is provided to allow the operating system to delay saving/restoring the x87 FPU
and SSE state until an instruction that actually accesses this state is encountered in a new task. When the TS flag
is set, the processor monitors the instruction stream for x87 FPU, MMX, SSE instructions. When the processor
detects one of these instructions, it raises a device-not-available exception (#NM) prior to executing the instruction. The #NM exception handler can then be used to save the x87 FPU and SSE state for the previous task (using
an FXSAVE, XSAVE, or XSAVEOPT instruction) and load the x87 FPU and SSE state for the current task (using an
FXRSTOR or XRSOTR instruction). If the task never encounters an x87 FPU, MMX, or SSE instruction, the devicenot-available exception will not be raised and a task state will not be saved/restored unnecessarily.
NOTE
The CRC32 and POPCNT instructions do not operate on the x87 FPU or SSE state. They operate on
the general-purpose registers and are not involved with the techniques described above.
The TS flag can be set either explicitly (by executing a MOV instruction to control register CR0) or implicitly (using
the IA-32 architecture’s native task switching mechanism). When the native task switching mechanism is used, the
processor automatically sets the TS flag on a task switch. After the device-not-available handler has saved the x87
FPU and SSE state, it should execute the CLTS instruction to clear the TS flag.
13.5
THE XSAVE FEATURE SET AND PROCESSOR EXTENDED STATE
MANAGEMENT
The architecture of XSAVE feature set is described in CHAPTER 13 of Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1. The XSAVE feature set includes the following:
•
An extensible data layout for existing and future processor state extensions. The layout of the XSAVE area
extends from the 512-byte FXSAVE/FXRSTOR layout to provide compatibility and migration path from
managing the legacy FXSAVE/FXRSTOR area. The XSAVE area is described in more detail in Section 13.4 of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
•
CPUID enhancements for feature enumeration. See Section 13.2 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1.
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•
Control register enhancement and dedicated register for enabling each processor extended state. See Section
13.3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
•
Instructions to save state to and restore state from the XSAVE area. See Section 13.7 through Section 13.9 of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Operating systems can utilize XSAVE feature set to manage both FP/SSE state and processor extended states.
CPUID leaf 0DH enumerates XSAVE feature set related information. The following guidelines provide the steps an
operating system needs to take to support legacy FP/SSE states and processor extended states.
1. Check that the processor supports the XSAVE feature set
2. Determine the set of XSAVE managed features that the operating system intends to enable and calculate the
size of the buffer needed to save/restore the states during context switch and other flows
3. Enable use of XSAVE feature set and XSAVE managed features
4. Provide an initialization for the XSAVE managed feature state components
5. Provide (if necessary) required exception handlers for exceptions generated each of the XSAVE managed
features.
13.5.1
Checking the Support for XSAVE Feature Set
Support for XSAVE Feature set is enumerated in CPUID.1.ECX.XSAVE[bit 26]. Enumeration of this bit indicates that
the processor supports XSAVE/XRSTOR instructions to manage state and XSETBV/XGETBV on XCR0 to enable and
get enabled states. An operating system needs to enable XSAVE feature set as described later.
Additionally CPUID.(EAX=0DH, ECX=1).EAX enumerates additional XSAVE sub features such as optimized save,
compaction and supervisor state support. The following table summarizes XSAVE sub features. Once an operating
system enables XSAVE feature set, all the sub-features enumerated are also available. There is no need to enable
each additional sub feature.
Table 13-3. CPUID.(EAX=0DH, ECX=1) EAX Bit Assignment
EAX Bit Position
0
If set, indicates availability of the XSAVEOPT instruction.
1
If set, indicates availability of the XSAVEC instruction and the corresponding compaction enhancements
to the legacy XRSTOR instruction.
2
If set, indicates support for execution of XGETBV with ECX=1. This execution returns the state-component bitmap XINUSE. If XINUSE[i] = 0, state component i is in its initial configuration. Execution of
XSETBV with ECX=1 causes a #GP.
3
If set, indicates support for XSAVES/XRSTORS and IA32_XSS MSR
31:4
13.5.2
Meaning
Reserved
Determining the XSAVE Managed Feature States And The Required Buffer Size
Each XSAVE managed feature has one or more state components associated with it. An operating system policy
needs to determine the XSAVE managed features to support and determine the corresponding state components
to enable. When determining the XSAVE managed features to support, operating system needs to take into account
the dependencies between them (e.g. AVX feature depends on SSE feature). Similarly, when a XSAVE managed
feature has more than one state component, all of them need to be enabled. Each logical processor enumerates
supported XSAVE state components in CPUID.(EAX=0DH, ECX=0).EDX:EAX. An operating system may enable all
or a subset of the state components enumerated by the processor based on the OS policy.
The size of the memory buffer needed to save enabled XSAVE state components depends on whether the OS optsin to use compacted format or not. Section 13.4.3 of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1 describes the layout of the extended region of the XSAVE area.
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13.5.3
Enable the Use Of XSAVE Feature Set And XSAVE State Components
Operating systems need to enable the use of XSAVE feature set by writing to CR4.OSXSAVE[bit 18] to enable
XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using
XSAVE/XRSTOR. When XSAVE feature set is enabled, all enumerated XSAVE sub features such as optimized save,
compaction and supervisor state support are also enabled. Operating systems also need to enable the XSAVE state
components in XCR0 using XSETBV instruction.
XSAVE state components can subsequently be disabled in XCR0. However, disabling state components of AVX or
AVX-512 that are not in initial configuration may incur power and performance penalty on SSE and AVX instructions
respectively. If AVX state is disabled when it is not in its initial configuration, subsequent SSE instructions may
incur a penalty. If AVX-512 state is disabled when it is not in its initial configuration, subsequent SSE and AVX
instructions may incur a penalty. It is recommended that the operating systems and VMM set AVX or AVX-512 state
components to their initial configuration before disabling them. This can be achieved by one of the two methods
below.
•
Using XRSTOR: Operating system or VMM can set the state of AVX or AVX-512 state components using XRSTOR
instruction before disabling them in XCR0.
•
Using VZEROUPPER: Operating system or VMM can set AVX and AVX-512 state components to their initial
configuration using VZEROUPPER instruction before disabling them in XCR0. Note that this will set both AVX
and AVX-512 state components to their initial configuration. If the intent is to only disable AVX-512 state,
Operating system or VMM will need to save AVX state before executing VZEROUPPER and restore it afterwards.
13.5.4
Provide an Initialization for the XSAVE State Components
The XSAVE header of a newly allocated XSAVE area should be initialized to all zeroes before saving context. An
operating system may choose to establish beginning state-component values for a task by executing XRSTOR from
an XSAVE area that the OS has configured. If it is desired to begin state component i in its initial configuration, the
OS should clear bit i in the XSTATE_BV field in the XSAVE header; otherwise, it should set that bit and place the
desired beginning value in the appropriate location in the XSAVE area.
When a buffer is allocated for compacted size, software must ensure that the XCOMP_BV field is setup correctly
before restoring from the buffer. Bit 63 of the XCOMP_BV field indicates that the save area is in the compacted
format and the remaining bits indicate the states that have space allocated in the save area. If the buffer is first
used to save the state in compacted format, then the save instructions will setup the XCOMP_BV field appropriately. If the buffer is first used to restore the state, then software must set up the XCOMP_BV field.
13.5.5
Providing the Required Exception Handlers
Instructions part of each XSAVE managed features may generate exceptions and operating system may need to
enable such exceptions and provide handlers for them. Section 13.8 describes feature specific OS requirements for
each XSAVE managed features.
13.6
INTEROPERABILITY OF THE XSAVE FEATURE SET AND FXSAVE/FXRSTOR
The FXSAVE instruction writes x87 FPU and SSE state information to a 512-byte FXSAVE save area. FXRSTOR
restores the processor’s x87 FPU and SSE states from an FXSAVE area. The XSAVE features set supports x87 FPU
and SSE states using the same layout as the FXSAVE area to provide interoperability of FXSAVE versus XSAVE, and
FXRSTOR versus XRSTOR. The XSAVE feature set allows system software to manage SSE state independent of x87
FPU states. Thus system software that had been using FXSAVE and FXRSTOR to manage x87 FPU and SSE states
can transition to using the XSAVE feature set to manage x87 FPU, SSE and other processor extended states in a
systematic and forward-looking manner. See Section 10.5 and Chapter 13 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1 for more details.
System software can implement forward-looking processor extended state management using the XSAVE feature
set. In this case, system software must specify the bit vector mask in EDX:EAX appropriately when executing
XSAVE/XRSTOR instructions.
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For instance, the OS can supply instructions in the XSAVE feature set with a bit vector in EDX:EAX with the two
least significant bits (corresponding to x87 FPU and SSE state) equal to 0. Then, the XSAVE instruction will not
write the processor’s x87 FPU and SSE state into memory. Similarly, the XRSTOR instruction executed with a value
in EDX:EAX with the least two significant bit equal to 0 will not restore nor initialize the processor’s x87 FPU and
SSE state.
The processor’s action as a result of executing XRSTOR is given in Section 13.8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. The instruction may be used to initialize x87 FPU or XMM registers. When the MXCSR register is updated from memory, reserved bit checking is enforced. The saving/restoring of
MXCSR is bound to the SSE state, independent of the x87 FPU state. The action of XSAVE is given in Section 13.7
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
13.7
THE XSAVE FEATURE SET AND PROCESSOR SUPERVISOR STATE
MANAGEMENT
Supervisor state is a processor state that is only accessible in ring 0. An extension to XSAVE feature set, enumerated by CPUID.(EAX=0DH, ECX=1).EAX[bit 3] allows the management of the supervisor states using XSAVE
feature set. See Chapter 13 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for the
details of the supervisor state XSAVE feature set extension. The supervisor state extension includes the following:
•
CPUID enhancements to enumerate the set of supervisor states and their sizes that can be managed by XSAVE
feature set.
•
•
A new MSR IA32_XSS to enable XSAVE feature set to manage one or more enumerated supervisor states.
A new pair of privileged save/restore instructions, XSAVES and XRSTORS, to save/restore supervisor states
along with other XSAVE managed feature states.
The guidelines to enable XSAVE feature set to manage supervisor state are very similar to the steps outlines in
Section 13.6 with the differences outline below. The set of supervisor states that can be managed by XSAVE feature
set is enumerated in (EAX=0DH, ECX=1).EDX:ECX. XSAVE managed supervisor states are enabled in IA32_XSS
MSR instead of XCR0 control register. There are semantic differences between user states enabled in XCR0 and
supervisor state enabled in IA32_XSS MSR. A supervisor state enabled in IA32_XSS MSR:
•
May be accessed via other mechanisms such as RDMSR/WRMSR even when they are not enabled in IA32_XSS
MSR. Enabling a supervisor state in the IA32_XSS MSR merely indicates that the state can be saved/restored
using XSAVES/XRSTORS instructions.
•
May have side effects when saving/restoring the state such as disabling/enabling feature associated with the
state. This behavior is feature specific and will be documented along with the feature description.
•
May generate faults when saving/restoring the state. XSAVES/XRSTORS will follow the faulting behavior of
RDMSR/WRMSR respectively if the corresponding state is also accessible using RDMSR/WRMSR.
•
XRSTORS may fault when restoring the state for supervisor features that are already enabled via feature
specific mechanisms. This behavior is feature specific and will be documented along with the feature
description.
When a supervisor state is disabled via a feature specific mechanism, the state does not automatically get marked
as INIT. Hence XSAVES/XRSTORS will continue to save/restore the state subject to available optimizations. If the
software does not intend to preserve the state when it disables the feature, it should initialize it to hardware INIT
value with XRSTORS instruction so that XSAVES/XRSTORS perform optimally for that state.
13.8
SYSTEM PROGRAMMING FOR XSAVE MANAGED FEATURES
This section describes system programming requirement for each XSAVE managed features that are feature
specific such as exception handling.
13-10 Vol. 3A
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
13.8.1
Intel® Advanced Vector Extensions (Intel® AVX)
Intel AVX instructions comprises of 256-bit and 128-bit instructions that operates on 256-bit YMM registers. The
XSAVE feature set allows software to save and restore the state of these registers. See Chapter 13 of the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
For processors that support YMM states, the YMM state exists in all operating modes. However, the available
instruction interfaces to access YMM states may vary in different modes.
Operating systems must use the XSAVE feature set for YMM state management. The XSAVE feature set also
provides flexible and efficient interface to manage XMM/MXCSR states and x87 FPU states in conjunction with
newer processor extended states like YMM states. Operating systems may need to be aware of the following when
supporting AVX.
•
Saving/Restoring AVX state in non-compacted format without SSE state will also save/restore MXCSR even
though MXCSR is not part of AVX state. This does not happen when compacted format is used.
•
Few AVX instructions such as VZEROUPPER/VZEROALL may operate on future expansion of YMM registers.
An operating system must enable its YMM state management to support AVX and any 256-bit extensions that
operate on YMM registers. Otherwise, an attempt to execute an instruction in AVX extensions (including an
enhanced 128-bit SIMD instructions using VEX encoding) will cause a #UD exception.
AVX instructions may generate SIMD floating-point exceptions. An OS must enable SIMD floating-point exception
support by setting CR4.OSXMMEXCPT[bit 10]=1.
13.8.2
Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
Intel AVX-512 instructions are encoded using EVEX prefix. The EVEX encoding scheme can support 512-bit, 256bit and 128-bit instructions that operate on opmask, ZMM, YMM and XMM registers.
For processors that support the Intel AVX-512 family of instructions, the extended processor states (ZMM and
opmask registers) exist in all operating modes. However, the access to these states may vary in different modes.
The processor's support for instruction extensions that employ EVEX prefix encoding is independent of the
processor's support for using XSAVE feature set on those states.
Instructions requiring EVEX prefix encoding are generally supported in 64-bit, 32-bit modes, and 16-bit protected
mode. They are not supported in Real mode, Virtual-8086 mode or entering into SMM mode. Note that bits
MAX_VL-1:256 (511:256) of ZMM register state are maintained across transitions into and out of these modes.
Because the XSAVE feature set instruction can operate in all operating modes, it is possible that the processor's
ZMM register state can be modified by software in any operating mode by executing XRSTOR.
Operating systems must use the XSAVE/XRSTOR/XSAVEOPT instructions for ZMM and opmask state management.
An OS must enable its ZMM and opmask state management to support Intel AVX-512 Foundation instructions.
Otherwise, an attempt to execute an instruction in Intel AVX-512 Foundation instructions (including a scalar 128bit SIMD instructions using EVEX encoding) will cause a #UD exception. An operating system, which enables the
AVX-512 state to support Intel AVX-512 Foundation instructions, is also sufficient to support the rest of the Intel
AVX-512 family of instructions. Note that even though ZMM8-ZMM31 are not accessible in 32 bit mode, a 32 bit OS
is still required to allocate memory for the entire ZMM state.
Intel AVX-512 Foundation instructions may generate SIMD floating-point exceptions. An OS must enable SIMD
floating point exception support by setting CR4.OSXMMEXCPT[bit 10]=1.
Vol. 3A 13-11
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
13-12 Vol. 3A
CHAPTER 14
POWER AND THERMAL MANAGEMENT
This chapter describes facilities of Intel 64 and IA-32 architecture used for power management and thermal monitoring.
14.1
ENHANCED INTEL SPEEDSTEP® TECHNOLOGY
Enhanced Intel SpeedStep® Technology was introduced in the Pentium M processor. The technology enables the
management of processor power consumption via performance state transitions. These states are defined as
discrete operating points associated with different voltages and frequencies.
Enhanced Intel SpeedStep Technology differs from previous generations of Intel SpeedStep Technology in two
ways:
•
Centralization of the control mechanism and software interface in the processor by using model-specific
registers.
•
Reduced hardware overhead; this permits more frequent performance state transitions.
Previous generations of the Intel SpeedStep Technology require processors to be a deep sleep state, holding off bus
master transfers for the duration of a performance state transition. Performance state transitions under the
Enhanced Intel SpeedStep Technology are discrete transitions to a new target frequency.
Support is indicated by CPUID, using ECX feature bit 07. Enhanced Intel SpeedStep Technology is enabled by
setting IA32_MISC_ENABLE MSR, bit 16. On reset, bit 16 of IA32_MISC_ENABLE MSR is cleared.
14.1.1
Software Interface For Initiating Performance State Transitions
State transitions are initiated by writing a 16-bit value to the IA32_PERF_CTL register, see Figure 14-2. If a transition is already in progress, transition to a new value will subsequently take effect.
Reads of IA32_PERF_CTL determine the last targeted operating point. The current operating point can be read from
IA32_PERF_STATUS. IA32_PERF_STATUS is updated dynamically.
The 16-bit encoding that defines valid operating points is model-specific. Applications and performance tools are
not expected to use either IA32_PERF_CTL or IA32_PERF_STATUS and should treat both as reserved. Performance
monitoring tools can access model-specific events and report the occurrences of state transitions.
14.2
P-STATE HARDWARE COORDINATION
The Advanced Configuration and Power Interface (ACPI) defines performance states (P-states) that are used to
facilitate system software’s ability to manage processor power consumption. Different P-states correspond to
different performance levels that are applied while the processor is actively executing instructions. Enhanced Intel
SpeedStep Technology supports P-states by providing software interfaces that control the operating frequency and
voltage of a processor.
With multiple processor cores residing in the same physical package, hardware dependencies may exist for a
subset of logical processors on a platform. These dependencies may impose requirements that impact the coordination of P-state transitions. As a result, multi-core processors may require an OS to provide additional software
support for coordinating P-state transitions for those subsets of logical processors.
ACPI firmware can choose to expose P-states as dependent and hardware-coordinated to OS power management
(OSPM) policy. To support OSPMs, multi-core processors must have additional built-in support for P-state hardware
coordination and feedback.
Intel 64 and IA-32 processors with dependent P-states amongst a subset of logical processors permit hardware
coordination of P-states and provide a hardware-coordination feedback mechanism using IA32_MPERF MSR and
Vol. 3B 14-1
POWER AND THERMAL MANAGEMENT
IA32_APERF MSR. See Figure 14-1 for an overview of the two 64-bit MSRs and the bullets below for a detailed
description:
63
0
IA32_MPERF (Addr: E7H)
63
0
IA32_APERF (Addr: E8H)
Figure 14-1. IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination
•
Use CPUID to check the P-State hardware coordination feedback capability bit. CPUID.06H.ECX[Bit 0] = 1
indicates IA32_MPERF MSR and IA32_APERF MSR are present.
•
IA32_MPERF MSR (E7H) increments in proportion to a fixed frequency, which is configured when the processor
is booted.
•
IA32_APERF MSR (E8H) increments in proportion to actual performance, while accounting for hardware coordination of P-state and TM1/TM2; or software initiated throttling.
•
The MSRs are per logical processor; they measure performance only when the targeted processor is in the C0
state.
•
Only the IA32_APERF/IA32_MPERF ratio is architecturally defined; software should not attach meaning to the
content of the individual of IA32_APERF or IA32_MPERF MSRs.
•
•
When either MSR overflows, both MSRs are reset to zero and continue to increment.
Both MSRs are full 64-bits counters. Each MSR can be written to independently. However, software should
follow the guidelines illustrated in Example 14-1.
If P-states are exposed by the BIOS as hardware coordinated, software is expected to confirm processor support
for P-state hardware coordination feedback and use the feedback mechanism to make P-state decisions. The OSPM
is expected to either save away the current MSR values (for determination of the delta of the counter ratio at a later
time) or reset both MSRs (execute WRMSR with 0 to these MSRs individually) at the start of the time window used
for making the P-state decision. When not resetting the values, overflow of the MSRs can be detected by checking
whether the new values read are less than the previously saved values.
Example 14-1 demonstrates steps for using the hardware feedback mechanism provided by IA32_APERF MSR and
IA32_MPERF MSR to determine a target P-state.
Example 14-1. Determine Target P-state From Hardware Coordinated Feedback
DWORD PercentBusy; // Percentage of processor time not idle.
// Measure “PercentBusy“ during previous sampling window.
// Typically, “PercentBusy“ is measure over a time scale suitable for
// power management decisions
//
// RDMSR of MCNT and ACNT should be performed without delay.
// Software needs to exercise care to avoid delays between
// the two RDMSRs (for example, interrupts).
MCNT = RDMSR(IA32_MPERF);
ACNT = RDMSR(IA32_APERF);
// PercentPerformance indicates the percentage of the processor
// that is in use. The calculation is based on the PercentBusy,
// that is the percentage of processor time not idle and the P-state
// hardware coordinated feedback using the ACNT/MCNT ratio.
// Note that both values need to be calculated over the same
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POWER AND THERMAL MANAGEMENT
// time window.
PercentPerformance = PercentBusy * (ACNT/MCNT);
// This example does not cover the additional logic or algorithms
// necessary to coordinate multiple logical processors to a target P-state.
TargetPstate = FindPstate(PercentPerformance);
if (TargetPstate ≠ currentPstate) {
SetPState(TargetPstate);
}
// WRMSR of MCNT and ACNT should be performed without delay.
// Software needs to exercise care to avoid delays between
// the two WRMSRs (for example, interrupts).
WRMSR(IA32_MPERF, 0);
WRMSR(IA32_APERF, 0);
14.3
SYSTEM SOFTWARE CONSIDERATIONS AND OPPORTUNISTIC PROCESSOR
PERFORMANCE OPERATION
An Intel 64 processor may support a form of processor operation that takes advantage of design headroom to
opportunistically increase performance. The Intel Turbo Boost Technology can convert thermal headroom into
higher performance across multi-threaded and single-threaded workloads. The Intel Dynamic Acceleration feature
can convert thermal headroom into higher performance if only one thread is active.
14.3.1
Intel Dynamic Acceleration
Intel Core 2 Duo processor T 7700 introduces Intel Dynamic Acceleration (IDA). IDA takes advantage of thermal
design headroom and opportunistically allows a single core to operate at a higher performance level when the
operating system requests increased performance.
14.3.2
System Software Interfaces for Opportunistic Processor Performance Operation
Opportunistic processor operation, applicable to Intel Dynamic Acceleration and Intel Turbo Boost Technology, has
the following characteristics:
•
A transition from a normal state of operation (e.g. IDA/Turbo mode disengaged) to a target state is not
guaranteed, but may occur opportunistically after the corresponding enable mechanism is activated, the
headroom is available and certain criteria are met.
•
•
The opportunistic processor performance operation is generally transparent to most application software.
•
When opportunistic processor performance operation is engaged, the OS should use hardware coordination
feedback mechanisms to prevent un-intended policy effects if it is activated during inappropriate situations.
System software (BIOS and Operating system) must be aware of hardware support for opportunistic processor
performance operation and may need to temporarily disengage opportunistic processor performance operation
when it requires more predictable processor operation.
14.3.2.1
Discover Hardware Support and Enabling of Opportunistic Processor Operation
If an Intel 64 processor has hardware support for opportunistic processor performance operation, the power-on
default state of IA32_MISC_ENABLE[38] indicates the presence of such hardware support. For Intel 64 processors
that support opportunistic processor performance operation, the default value is 1, indicating its presence. For
processors that do not support opportunistic processor performance operation, the default value is 0. The powerVol. 3B 14-3
POWER AND THERMAL MANAGEMENT
on default value of IA32_MISC_ENABLE[38] allows BIOS to detect the presence of hardware support of opportunistic processor performance operation.
IA32_MISC_ENABLE[38] is shared across all logical processors in a physical package. It is written by BIOS during
platform initiation to enable/disable opportunistic processor operation in conjunction of OS power management
capabilities, see Section 14.3.2.2. BIOS can set IA32_MISC_ENABLE[38] with 1 to disable opportunistic processor
performance operation; it must clear the default value of IA32_MISC_ENABLE[38] to 0 to enable opportunistic
processor performance operation. OS and applications must use CPUID leaf 06H if it needs to detect processors
that has opportunistic processor operation enabled.
When CPUID is executed with EAX = 06H on input, Bit 1 of EAX in Leaf 06H (i.e. CPUID.06H:EAX[1]) indicates
opportunistic processor performance operation, such as IDA, has been enabled by BIOS.
Opportunistic processor performance operation can be disabled by setting bit 38 of IA32_MISC_ENABLE. This
mechanism is intended for BIOS only. If IA32_MISC_ENABLE[38] is set, CPUID.06H:EAX[1] will return 0.
14.3.2.2
OS Control of Opportunistic Processor Performance Operation
There may be phases of software execution in which system software cannot tolerate the non-deterministic aspects
of opportunistic processor performance operation. For example, when calibrating a real-time workload to make a
CPU reservation request to the OS, it may be undesirable to allow the possibility of the processor delivering
increased performance that cannot be sustained after the calibration phase.
System software can temporarily disengage opportunistic processor performance operation by setting bit 32 of the
IA32_PERF_CTL MSR (0199H), using a read-modify-write sequence on the MSR. The opportunistic processor
performance operation can be re-engaged by clearing bit 32 in IA32_PERF_CTL MSR, using a read-modify-write
sequence. The DISENAGE bit in IA32_PERF_CTL is not reflected in bit 32 of the IA32_PERF_STATUS MSR (0198H),
and it is not shared between logical processors in a physical package. In order for OS to engage IDA/Turbo mode,
the BIOS must
•
•
enable opportunistic processor performance operation, as described in Section 14.3.2.1,
expose the operating points associated with IDA/Turbo mode to the OS.
33 32 31
63
16 15
0
Reserved
IDA/Turbo DISENGAGE
Enhanced Intel Speedstep Technology Transition Target
Figure 14-2. IA32_PERF_CTL Register
14.3.2.3
Required Changes to OS Power Management P-state Policy
Intel Dynamic Acceleration (IDA) and Intel Turbo Boost Technology can provide opportunistic performance greater
than the performance level corresponding to the Processor Base frequency of the processor (see CPUID’s processor
frequency information). System software can use a pair of MSRs to observe performance feedback. Software must
query for the presence of IA32_APERF and IA32_MPERF (see Section 14.2). The ratio between IA32_APERF and
IA32_MPERF is architecturally defined and a value greater than unity indicates performance increase occurred
during the observation period due to IDA. Without incorporating such performance feedback, the target P-state
evaluation algorithm can result in a non-optimal P-state target.
There are other scenarios under which OS power management may want to disable IDA, some of these are listed
below:
•
When engaging ACPI defined passive thermal management, it may be more effective to disable IDA for the
duration of passive thermal management.
14-4 Vol. 3B
POWER AND THERMAL MANAGEMENT
•
When the user has indicated a policy preference of power savings over performance, OS power management
may want to disable IDA while that policy is in effect.
14.3.3
Intel Turbo Boost Technology
Intel Turbo Boost Technology is supported in Intel Core i7 processors and Intel Xeon processors based on Intel®
microarchitecture code name Nehalem. It uses the same principle of leveraging thermal headroom to dynamically
increase processor performance for single-threaded and multi-threaded/multi-tasking environment. The programming interface described in Section 14.3.2 also applies to Intel Turbo Boost Technology.
14.3.4
Performance and Energy Bias Hint support
Intel 64 processors may support additional software hint to guide the hardware heuristic of power management
features to favor increasing dynamic performance or conserve energy consumption.
Software can detect the processor's capability to support the performance-energy bias preference hint by examining bit 3 of ECX in CPUID leaf 6. The processor supports this capability if CPUID.06H:ECX.SETBH[bit 3] is set and
it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
Software can program the lowest four bits of IA32_ENERGY_PERF_BIAS MSR with a value from 0 - 15. The values
represent a sliding scale, where a value of 0 (the default reset value) corresponds to a hint preference for highest
performance and a value of 15 corresponds to the maximum energy savings. A value of 7 roughly translates into a
hint to balance performance with energy consumption.
4 3
63
0
Reserved
Energy Policy Preference Hint
Figure 14-3. IA32_ENERGY_PERF_BIAS Register
The layout of IA32_ENERGY_PERF_BIAS is shown in Figure 14-3. The scope of IA32_ENERGY_PERF_BIAS is per
logical processor, which means that each of the logical processors in the package can be programmed with a
different value. This may be especially important in virtualization scenarios, where the performance / energy
requirements of one logical processor may differ from the other. Conflicting “hints” from various logical processors
at higher hierarchy level will be resolved in favor of performance over energy savings.
Software can use whatever criteria it sees fit to program the MSR with an appropriate value. However, the value
only serves as a hint to the hardware and the actual impact on performance and energy savings is model specific.
14.4
HARDWARE-CONTROLLED PERFORMANCE STATES (HWP)
Intel processors may contain support for Hardware-Controlled Performance States (HWP), which autonomously
selects performance states while utilizing OS supplied performance guidance hints. The Enhanced Intel SpeedStep® Technology provides a means for the OS to control and monitor discrete frequency-based operating points
via the IA32_PERF_CTL and IA32_PERF_STATUS MSRs.
In contrast, HWP is an implementation of the ACPI-defined Collaborative Processor Performance Control (CPPC),
which specifies that the platform enumerate a continuous, abstract unit-less, performance value scale that is not
tied to a specific performance state / frequency by definition. While the enumerated scale is roughly linear in terms
of a delivered integer workload performance result, the OS is required to characterize the performance value range
to comprehend the delivered performance for an applied workload.
Vol. 3B 14-5
POWER AND THERMAL MANAGEMENT
When HWP is enabled, the processor autonomously selects performance states as deemed appropriate for the
applied workload and with consideration of constraining hints that are programmed by the OS. These OS-provided
hints include minimum and maximum performance limits, preference towards energy efficiency or performance,
and the specification of a relevant workload history observation time window. The means for the OS to override
HWP's autonomous selection of performance state with a specific desired performance target is also provided,
however, the effective frequency delivered is subject to the result of energy efficiency and performance optimizations.
14.4.1
HWP Programming Interfaces
The programming interfaces provided by HWP include the following:
•
The CPUID instruction allows software to discover the presence of HWP support in an Intel processor. Specifically, execute CPUID instruction with EAX=06H as input will return 5 bit flags covering the following aspects in
bits 7 through 11 of CPUID.06H:EAX:
— Availability of HWP baseline resource and capability, CPUID.06H:EAX[bit 7]: If this bit is set, HWP provides
several new architectural MSRs: IA32_PM_ENABLE, IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST,
IA32_HWP_STATUS.
— Availability of HWP Notification upon dynamic Guaranteed Performance change, CPUID.06H:EAX[bit 8]: If
this bit is set, HWP provides IA32_HWP_INTERRUPT MSR to enable interrupt generation due to dynamic
Performance changes and excursions.
— Availability of HWP Activity window control, CPUID.06H:EAX[bit 9]: If this bit is set, HWP allows software to
program activity window in the IA32_HWP_REQUEST MSR.
— Availability of HWP energy/performance preference control, CPUID.06H:EAX[bit 10]: If this bit is set, HWP
allows software to set an energy/performance preference hint in the IA32_HWP_REQUEST MSR.
— Availability of HWP package level control, CPUID.06H:EAX[bit 11]:If this bit is set, HWP provides the
IA32_HWP_REQUEST_PKG MSR to convey OS Power Management’s control hints for all logical processors
in the physical package.
Table 14-1. Architectural and Non-Architectural MSRs Related to HWP
•
Address
Archite
ctural
Register Name
Description
770H
Y
IA32_PM_ENABLE
771H
Y
IA32_HWP_CAPABILITIES
Enumerates the HWP performance range (static and dynamic).
772H
Y
IA32_HWP_REQUEST_PKG
Conveys OSPM's control hints (Min, Max, Activity Window, Energy
Performance Preference, Desired) for all logical processor in the physical
package.
773H
Y
IA32_HWP_INTERRUPT
774H
Y
IA32_HWP_REQUEST
777H
Y
IA32_HWP_STATUS
19CH
Y
IA32_THERM_STATUS[bits 15:12]
64EH
N
MSR_PPERF
Enable/Disable HWP.
Controls HWP native interrupt generation (Guaranteed Performance
changes, excursions).
Conveys OSPM's control hints (Min, Max, Activity Window, Energy
Performance Preference, Desired) for a single logical processor.
Status bits indicating changes to Guaranteed Performance and
excursions to Minimum Performance.
Conveys reasons for performance excursions
Productive Performance Count.
Additionally, HWP may provide a non-architectural MSR, MSR_PPERF, which provides a quantitative metric to
software of hardware’s view of workload scalability. This hardware’s view of workload scalability is implementation specific.
14-6 Vol. 3B
POWER AND THERMAL MANAGEMENT
14.4.2
Enabling HWP
The layout of the IA32_PM_ENABLE MSR is shown in Figure 14-4. The bit fields are described below:
63
1 0
Reserved
HWP_ENABLE
Reserved
Figure 14-4. IA32_PM_ENABLE MSR
•
HWP_ENABLE (bit 0, R/W1Once) — Software sets this bit to enable HWP with autonomous selection. When
set, the processor will disregard input from the legacy performance control interface (IA32_PERF_CTL). Note
this bit can only be enabled once from the default value. Once set, writes to the HWP_ENABLE bit are ignored.
Only RESET will clear this bit. Default = zero (0).
•
Bits 63:1 are reserved and must be zero.
After software queries CPUID and verifies the processor’s support of HWP, system software can write 1 to
IA32_PM_ENABLE.HWP_ENABLE (bit 0) to enable hardware controlled performance states. The default value of
IA32_PM_ENABLE MSR at power-on is 0, i.e. HWP is disabled.
Additional MSRs associated with HWP may only be accessed after HWP is enabled, with the exception of
IA32_HWP_INTERRUPT and MSR_PPERF. Accessing the IA32_HWP_INTERRUPT MSR requires only HWP is present
as enumerated by CPUID but does not require enabling HWP.
IA32_PM_ENABLE is a package level MSR, i.e. writing to it from any logical processor within a package affects all
logical processors within that package.
14.4.3
HWP Performance Range and Dynamic Capabilities
The OS reads the IA32_HWP_CAPABILITIES MSR to comprehend the limits of the HWP-managed performance
range as well as the dynamic capability, which may change during processor operation. The enumerated performance range values reported by IA32_HWP_CAPABILITIES directly map to initial frequency targets (prior to workload-specific frequency optimizations of HWP). However the mapping is processor family specific.
The layout of the IA32_HWP_CAPABILITIES MSR is shown in Figure 14-5. The bit fields are described below:
63
32 31
24 23
16 15
8
7
0
Reserved
Lowest_Performance
Most_Efficient_Performance
Guaranteed_Performance
Highest_Performance
Figure 14-5. IA32_HWP_CAPABILITIES Register
•
•
Highest_Performance (bits 7:0, RO) — Value for the maximum non-guaranteed performance level.
•
Most_Efficient_Performance (bits 23:16, RO) — Current value of the most efficient performance level.
This value can change dynamically as a result of workload characteristics.
Guaranteed_Performance (bits 15:8, RO) — Current value for the guaranteed performance level. This
value can change dynamically as a result of internal or external constraints, e.g. thermal or power limits.
Vol. 3B 14-7
POWER AND THERMAL MANAGEMENT
•
Lowest_Performance (bits 31:24, RO) — Value for the lowest performance level that software can program
to IA32_HWP_REQUEST.
•
Bits 63:32 are reserved and must be zero.
The value returned in the Guaranteed_Performance field is hardware's best-effort approximation of the available performance given current operating constraints. Changes to the Guaranteed_Performance value will
primarily occur due to a shift in operational mode. This includes a power or other limit applied by an external agent,
e.g. RAPL (see Figure 14.9.1), or the setting of a Configurable TDP level (see model-specific controls related to
Programmable TDP Limit in Chapter 35, “Model-Specific Registers (MSRs)”). Notification of a change to the
Guaranteed_Performance occurs via interrupt (if configured) and the IA32_HWP_Status MSR. Changes to
Guaranteed_Performance are indicated when a macroscopically meaningful change in performance occurs i.e.
sustained for greater than one second. Consequently, notification of a change in Guaranteed Performance will typically occur no more frequently than once per second. Rapid changes in platform configuration, e.g. docking /
undocking, with corresponding changes to a Configurable TDP level could potentially cause more frequent notifications.
The value returned by the Most_Efficient_Performance field provides the OS with an indication of the practical
lower limit for the IA32_HWP_REQUEST. The processor may not honor IA32_HWP_REQUEST.Maximum Performance settings below this value.
14.4.4
Managing HWP
Typically, the OS controls HWP operation for each logical processor via the writing of control hints / constraints to
the IA32_HWP_REQUEST MSR. The layout of the IA32_HWP_REQUEST MSR is shown in Figure 14-6. The bit fields
are described below:
63
43 42 41
32 31
24 23
16 15
8
7
0
Reserved
Package_Control
Activity_Window
Energy_Performance_Preference
Desired_Performance
Maximum_Performance
Minimum_Performance
Figure 14-6. IA32_HWP_REQUEST Register
•
Minimum_Performance (bits 7:0, RW) — Conveys a hint to the HWP hardware. The OS programs the
minimum performance hint to achieve the required quality of service (QOS) or to meet a service level
agreement (SLA) as needed. Note that an excursion below the level specified is possible due to hardware
constraints. The default value of this field is IA32_HWP_CAPABILITIES.Lowest_Performance.
•
Maximum_Performance (bits 15:8, RW) — Conveys a hint to the HWP hardware. The OS programs this
field to limit the maximum performance that is expected to be supplied by the HWP hardware. Excursions
above the limit requested by OS are possible due to hardware coordination between the processor cores and
other components in the package. The default value of this field is
IA32_HWP_CAPABILITIES.Highest_Performance.
•
Desired_Performance (bits 23:16, RW) — Conveys a hint to the HWP hardware. When set to zero,
hardware autonomous selection determines the performance target. When set to a non-zero value (between
the range of Lowest_Performance and Highest_Performance of IA32_HWP_CAPABILITIES) conveys an explicit
performance request hint to the hardware; effectively disabling HW Autonomous selection. The
Desired_Performance input is non-constraining in terms of Performance and Energy Efficiency optimizations,
which are independently controlled. The default value of this field is 0.
•
Energy_Performance_Preference (bits 31:24, RW) — Conveys a hint to the HWP hardware. The OS may
write a range of values from 0 (performance preference) to 0FFH (energy efficiency preference) to influence the
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POWER AND THERMAL MANAGEMENT
rate of performance increase /decrease and the result of the hardware's energy efficiency and performance
optimizations. The default value of this field is 80H. Note: If CPUID.06H:EAX[bit 10] indicates that this field is
not supported, HWP uses the value of the IA32_ENERGY_PERF_BIAS MSR to determine the energy efficiency /
performance preference.
•
Activity_Window (bits 41:32, RW) — Conveys a hint to the HWP hardware specifying a moving workload
history observation window for performance/frequency optimizations. If 0, the hardware will determine the
appropriate window size. When writing a non-zero value to this field, this field is encoded in the format of bits
38:32 as a 7-bit mantissa and bits 41:39 as a 3-bit exponent value in powers of 10. The resultant value is in
microseconds. Thus, the minimal/maximum activity window size is 1 microsecond/1270 seconds. Combined
with the Energy_Performance_Preference input, Activity_Window influences the rate of performance increase
/ decrease. This non-zero hint only has meaning when Desired_Performance = 0. The default value of this field
is 0.
•
Package_Control (bit 42, RW) — When set causes this logical processor's IA32_HWP_REQUEST control
inputs to be derived from IA32_HWP_REQUEST_PKG
•
Bits 63:43 are reserved and must be zero.
The HWP hardware clips and resolves the field values as necessary to the valid range. Reads return the last value
written not the clipped values.
Processors may support a subset of IA32_HWP_REQUEST fields as indicated by CPUID. Reads of non-supported
fields will return 0. Writes to non-supported fields are ignored.
The OS may override HWP's autonomous selection of performance state with a specific performance target by
setting the Desired_Performance field to a non zero value, however, the effective frequency delivered is subject to
the result of energy efficiency and performance optimizations, which are influenced by the Energy Performance
Preference field.
Software may disable all hardware optimizations by setting Minimum_Performance = Maximum_Performance
(subject to package coordination).
Note: The processor may run below the Minimum_Performance level due to hardware constraints including: power,
thermal, and package coordination constraints. The processor may also run below the Minimum_Performance level
for short durations (few milliseconds) following C-state exit, and when Hardware Duty Cycling (see Section 14.5)
is enabled.
63
42 41
32 31
24 23
16 15
8
7
0
Reserved
Activity_Window
Energy_Performance_Preference
Desired_Performance
Maximum_Performance
Minimum_Performance
Figure 14-7. IA32_HWP_REQUEST_PKG Register
The structure of the IA32_HWP_REQUEST_PKG MSR (package-level) is identical to the IA32_HWP_REQUEST MSR
with the exception of the Package Control field, which does not exist. Field values written to this MSR apply to all
logical processors within the physical package with the exception of logical processors whose
IA32_HWP_REQUEST.Package Control field is clear (zero). Single P-state Control mode is only supported when
IA32_HWP_REQUEST_PKG is not supported.
14.4.5
HWP Feedback
The processor provides several types of feedback to the OS during HWP operation.
Vol. 3B 14-9
POWER AND THERMAL MANAGEMENT
The IA32_MPERF MSR and IA32_APERF MSR mechanism (see Section 14.2) allows the OS to calculate the resultant
effective frequency delivered over a time period. Energy efficiency and performance optimizations directly impact
the resultant effective frequency delivered.
The layout of the IA32_HWP_STATUS MSR is shown in Figure 14-8. It provides feedback regarding changes to
IA32_HWP_CAPABILITIES.Guaranteed_Performance and excursions to
IA32_HWP_CAPABILITIES.Minimum_Performance. The bit fields are described below:
•
Guaranteed_Performance_Change (bit 0, RWC0) — If set (1), a change to Guaranteed_Performance has
occurred. Software should query IA32_HWP_CAPABILITIES.Guaranteed_Performance value to ascertain the
new Guaranteed Performance value and to assess whether to re-adjust HWP hints via IA32_HWP_REQUEST.
Software must clear this bit by writing a zero (0).
•
Excursion_To_Minimum (bit 2, RWC0) — If set (1), an excursion to Minimum_Performance of
IA32_HWP_REQUEST has occurred. Software must clear this bit by writing a zero (0).
•
Bits 63:3, and bit 1 are reserved and must be zero.
63
3 2 1 0
Reserved
Excursion_To_Minimum
Reserved
Guaranteed_Performance_Change
Figure 14-8. IA32_HWP_STATUS MSR
The status bits of IA32_HWP_STATUS must be cleared (0) by software so that a new status condition change will
cause the hardware to set the bit again and issue the notification. Status bits are not set for “normal” excursions
e.g. running below Minimum Performance for short durations during C-state exit. Changes to
Guaranteed_Performance and excursions to Minimum_Performance will occur no more than once per second.
The OS can determine the specific reasons for a Guaranteed_Performance change or an excursion to
Minimum_Performance in IA32_HWP_REQUEST by examining the associated status and log bits reported in the
IA32_THERM_STATUS MSR. The layout of the IA32_HWP_STATUS MSR that HWP uses to support software query of
HWP feedback is shown in Figure 14-9. The bit fields of IA32_THERM_STATUS associated with HWP feedback are
described below (Bit fields of IA32_THERM_STATUS unrelated to HWP can be found in Section 14.7.5.2).
63
32 31
27
23 22
16 15 14 13 12 11 10 9 8 7
6 5
4
3
2
Reserved
Reading Valid
Resolution in Deg. Celsius
Digital Readout
Cross-domain Limit Log
Cross-domain Limit Status
Current Limit Log
Current Limit Status
Power Limit Notification Log
Power Limit Notification Status
Thermal Threshold #2 Log
Thermal Threshold #2 Status
Thermal Threshold #1 Log
Thermal Threshold #1 Status
Critical Temperature Log
Critical Temperature Status
PROCHOT# or FORCEPR# Log
PROCHOT# or FORCEPR# Event
Thermal Status Log
Thermal Status
Figure 14-9. IA32_THERM_STATUS Register With HWP Feedback
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POWER AND THERMAL MANAGEMENT
•
•
Bits 11:0, See Section 14.7.5.2.
•
Current Limit Log (bit 13, RWC0) — If set (1), an electrical current limit has been exceeded that has
adversely impacted energy efficiency optimizations since the last clearing of this bit or a reset. This bit is sticky,
software may clear this bit by writing a zero (0).
•
Cross-domain Limit Status (bit 14, RO) — If set (1), indicates another hardware domain (e.g. processor
graphics) is currently limiting energy efficiency optimizations in the processor core domain.
•
Cross-domain Limit Log (bit 15, RWC0) — If set (1), indicates another hardware domain (e.g. processor
graphics) has limited energy efficiency optimizations in the processor core domain since the last clearing of this
bit or a reset. This bit is sticky, software may clear this bit by writing a zero (0).
•
Bits 63:16, See Section 14.7.5.2.
Current Limit Status (bit 12, RO) — If set (1), indicates an electrical current limit (e.g. Electrical Design
Point/IccMax) is being exceeded and is adversely impacting energy efficiency optimizations.
14.4.5.1
Non-Architectural HWP Feedback
The Productive Performance (MSR_PPERF) MSR (non-architectural) provides hardware's view of workload scalability, which is a rough assessment of the relationship between frequency and workload performance, to software.
The layout of the MSR_PPERF is shown in Figure 14-10.
63
0
PCNT - Productive Performance Count
Figure 14-10. MSR_PPERF MSR
•
PCNT (bits 63:0, RO) — Similar to IA32_APERF but only counts cycles perceived by hardware as contributing
to instruction execution (e.g. unhalted and unstalled cycles). This counter increments at the same rate as
IA32_APERF, where the ratio of (ΔPCNT/ΔACNT) is an indicator of workload scalability (0% to 100%). Note that
values in this register are valid even when HWP is not enabled.
14.4.6
HWP Notifications
Processors may support interrupt-based notification of changes to HWP status as indicated by CPUID. If supported,
the IA32_HWP_INTERRUPT MSR is used to enable interrupt-based notifications. Notification events, when enabled,
are delivered using the existing thermal LVT entry. The layout of the IA32_HWP_INTERRUPT is shown in
Figure 14-11. The bit fields are described below:
63
2 1 0
Reserved
EN_Excursion_Minimum
EN_Guaranteed_Performance_Change
Figure 14-11. IA32_HWP_INTERRUPT MSR
•
EN_Guaranteed_Performance_Change (bit 0, RW) — When set (1), an HWP Interrupt will be generated
whenever a change to the IA32_HWP_CAPABILITIES.Guaranteed_Performance occurs. The default value is 0
(Interrupt generation is disabled).
Vol. 3B 14-11
POWER AND THERMAL MANAGEMENT
•
EN_Excursion_Minimum (bit 1, RW) — When set (1), an HWP Interrupt will be generated whenever the
HWP hardware is unable to meet the IA32_HWP_REQUEST.Minimum_Performance setting. The default value is
0 (Interrupt generation is disabled).
•
Bits 63:2, and bit 1 are reserved and must be zero.
14.4.7
Recommendations for OS use of HWP Controls
Common Cases of Using HWP
The default HWP control field values are expected to be suitable for many applications. The OS can enable autonomous HWP for these common cases by
•
Setting IA32_HWP_REQUEST.Desired Performance = 0 (hardware autonomous selection determines the
performance target). Set IA32_HWP_REQUEST.Activity Window = 0 (enable HW dynamic selection of window
size).
To maximize HWP benefit for the common cases, the OS should set
•
•
IA32_HWP_REQUEST.Minimum_Performance = IA32_HWP_CAPABILITIES.Lowest_Performance and
IA32_HWP_REQUEST.Maximum_Performance = IA32_HWP_CAPABILITIES.Highest_Performance.
Setting IA32_HWP_REQUEST.Minimum_Performance = IA32_HWP_REQUEST.Maximum_Performance is functionally equivalent to using of the IA32_PERF_CTL interface and is therefore not recommended (bypassing HWP).
Calibrating HWP for Application-Specific HWP Optimization
In some applications, the OS may have Quality of Service requirements that may not be met by the default values.
The OS can characterize HWP by:
•
keeping IA32_HWP_REQUEST.Minimum_Performance = IA32_HWP_REQUEST.Maximum_Performance to
prevent non-linearity in the characterization process,
•
utilizing the range values enumerated from the IA32_HWP_CAPABILITIES MSR to program
IA32_HWP_REQUEST while executing workloads of interest and observing the power and performance result.
The power and performance result of characterization is also influenced by the IA32_HWP_REQUEST.Energy
Performance Preference field, which must also be characterized.
Characterization can be used to set IA32_HWP_REQUEST.Minimum_Performance to achieve the required QOS in
terms of performance. If IA32_HWP_REQUEST.Minimum_Performance is set higher than
IA32_HWP_CAPABILITIES.Guaranteed Performance then notification of excursions to Minimum Performance may
be continuous.
If autonomous selection does not deliver the required workload performance, the OS should assess the current
delivered effective frequency and for the duration of the specific performance requirement set
IA32_HWP_REQUEST.Desired_Performance ≠ 0 and adjust IA32_HWP_REQUEST.Energy_Performance_Preference
as necessary to achieve the required workload performance. The MSR_PPERF.PCNT value can be used to better
comprehend the potential performance result from adjustments to IA32_HWP_REQUEST.Desired_Performance.
The OS should set IA32_HWP_REQUEST.Desired_Performance = 0 to re-enable autonomous selection.
Tuning for Maximum Performance or Lowest Power Consumption
Maximum performance will be delivered by setting IA32_HWP_REQUEST.Minimum_Performance =
IA32_HWP_REQUEST.Maximum_Performance = IA32_HWP_CAPABILITIES.Highest_Performance and setting
IA32_HWP_REQUEST.Energy_Performance_Preference = 0 (performance preference).
Lowest power will be achieved by setting IA32_HWP_REQUEST.Minimum_Performance =
IA32_HWP_REQUEST.Maximum_Performance = IA32_HWP_CAPABILITIES.Lowest_Performance and setting
IA32_HWP_REQUEST.Energy_Performance_Preference = 0FFH (energy efficiency preference).
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POWER AND THERMAL MANAGEMENT
Additional Guidelines
Set IA32_HWP_REQUEST.Energy_Performance_Preference as appropriate for the platform's current mode of operation. For example, a mobile platforms' setting may be towards performance preference when on AC power and
more towards energy efficiency when on DC power.
The use of the Running Average Power Limit (RAPL) processor capability (see section 14.7.1) is highly recommended when HWP is enabled. Use of IA32_HWP_Request.Maximum_Performance for thermal control is subject to
limitations and can adversely impact the performance of other processor components e.g. Graphics
If default values deliver undesirable performance latency in response to events, the OS should set
IA32_HWP_REQUEST. Activity_Window to a low (non zero) value and
IA32_HWP_REQUEST.Energy_Performance_Preference towards performance (0) for the event duration.
Similarly, for “real-time” threads, set IA32_HWP_REQUEST.Energy_Performance_Preference towards performance
(0) and IA32_HWP_REQUEST. Activity_Window to a low value, e.g. 01H, for the duration of their execution.
When executing low priority work that may otherwise cause the hardware to deliver high performance, set
IA32_HWP_REQUEST. Activity_Window to a longer value and reduce the
IA32_HWP_Request.Maximum_Performance value as appropriate to control energy efficiency. Adjustments to
IA32_HWP_REQUEST.Energy_Performance_Preference may also be necessary.
14.5
HARDWARE DUTY CYCLING (HDC)
Intel processors may contain support for Hardware Duty Cycling (HDC), which enables the processor to autonomously force its components inside the physical package into idle state. For example, the processor may selectively
force only the processor cores into an idle state.
HDC is disabled by default on processors that support it. System software can dynamically enable or disable HDC
to force one or more components into an idle state or wake up those components previously forced into an idle
state. Forced Idling (and waking up) of multiple components in a physical package can be done with one WRMSR
to a packaged-scope MSR from any logical processor within the same package.
HDC does not delay events such as timer expiration, but it may affect the latency of short (less than 1 msec) software threads, e.g. if a thread is forced to idle state just before completion and entering a “natural idle”.
HDC forced idle operation can be thought of as operating at a lower effective frequency. The effective average
frequency computed by software will include the impact of HDC forced idle.
The primary use of HDC is enable system software to manage low active workloads to increase the package level
C6 residency. Additionally, HDC can lower the effective average frequency in case or power or thermal limitation.
When HDC forces a logical processor, a processor core or a physical package to enter an idle state, its C-State is set
to C3 or deeper. The deep “C-states” referred to in this section are processor-specific C-states.
14.5.1
Hardware Duty Cycling Programming Interfaces
The programming interfaces provided by HDC include the following:
•
The CPUID instruction allows software to discover the presence of HDC support in an Intel processor. Specifically, execute CPUID instruction with EAX=06H as input, bit 13 of EAX indicates the processor’s support of the
following aspects of HDC.
— Availability of HDC baseline resource, CPUID.06H:EAX[bit 13]: If this bit is set, HDC provides the following
architectural MSRs: IA32_PKG_HDC_CTL, IA32_PM_CTL1, and the IA32_THREAD_STALL MSRs.
•
Additionally, HDC may provide several non-architectural MSR.
Table 14-2. Architectural and non-Architecture MSRs Related to HDC
Address
Architec
tural
Register Name
Description
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POWER AND THERMAL MANAGEMENT
Table 14-2. Architectural and non-Architecture MSRs Related to HDC
DB0H
Y
IA32_PKG_HDC_CTL
DB1H
Y
IA32_PM_CTL1
Package Enable/Disable HDC.
Per-logical-processor select control to allow/block HDC forced idling.
DB2H
Y
IA32_THREAD_STALL
653H
N
MSR_CORE_HDC_RESIDENCY
Accumulate stalled cycles on this logical processor due to HDC forced idling.
Core level stalled cycle counter due to HDC forced idling on one or more
logical processor.
655H
N
MSR_PKG_HDC_SHALLOW_RE
SIDENCY
Accumulate the cycles the package was in C21 state and at least one logical
processor was in forced idle
656H
N
MSR_PKG_HDC_DEEP_RESIDE
NCY
Accumulate the cycles the package was in the software specified Cx1 state
and at least one logical processor was in forced idle. Cx is specified in
MSR_PKG_HDC_CONFIG_CTL.
652H
N
MSR_PKG_HDC_CONFIG_CTL
HDC configuration controls
NOTES:
1. The package “C-states” referred to in this section are processor-specific C-states.
14.5.2
Package level Enabling HDC
The layout of the IA32_PKG_HDC_CTL MSR is shown in Figure 14-12. IA32_PKG_HDC_CTL is a writable MSR from
any logical processor in a package. The bit fields are described below:
63
1 0
Reserved
Reserved
HDC_PKG_Enable
Figure 14-12. IA32_PKG_HDC_CTL MSR
•
HDC_PKG_Enable (bit 0, R/W) — Software sets this bit to enable HDC operation by allowing the processor
to force to idle all “HDC-allowed” (see Figure 14.5.3) logical processors in the package. Clearing this bit
disables HDC operation in the package by waking up all the processor cores that were forced into idle by a
previous ‘0’-to-’1’ transition in IA32_PKG_HDC_CTL.HDC_PKG_Enable. This bit is writable only if
CPUID.06H:EAX[bit 13] = 1. Default = zero (0).
•
Bits 63:1 are reserved and must be zero.
After processor support is determined via CPUID, system software can enable HDC operation by setting
IA32_PKG_HDC_CTL.HDC_PKG_Enable to 1. At reset, IA32_PKG_HDC_CTL.HDC_PKG_Enable is cleared to 0. A
'0'-to-'1' transition in HDC_PKG_Enable allows the processor to force to idle all HDC-allowed (indicated by the nonzero state of IA32_PM_CTL1[bit 0]) logical processors in the package. A ‘1’-to-’0’ transition wakes up those HDC
force-idled logical processors.
Software can enable or disable HDC using this package level control multiple times from any logical processor in the
package. Note the latency of writing a value to the package-visible IA32_PKG_HDC_CTL.HDC_PKG_Enable is
longer than the latency of a WRMSR operation to a Logical Processor MSR (as opposed to package level MSR) such
as: IA32_PM_CTL1 (described in Section 14.5.3). Propagation of the change in
IA32_PKG_HDC_CTL.HDC_PKG_Enable and reaching all HDC idled logical processor to be woken up may take on
the order of core C6 exit latency.
14.5.3
Logical-Processor Level HDC Control
The layout of the IA32_PM_CTL1 MSR is shown in Figure 14-13. Each logical processor in a package has its own
IA32_PM_CTL1 MSR. The bit fields are described below:
14-14 Vol. 3B
POWER AND THERMAL MANAGEMENT
63
1 0
Reserved
HDC_Allow_Block
Reserved
Figure 14-13. IA32_PM_CTL1 MSR
•
HDC_Allow_Block (bit 0, R/W) — Software sets this bit to allow this logical processors to honor the
package-level IA32_PKG_HDC_CTL.HDC_PKG_Enable control. Clearing this bit prevents this logical processor
from using the HDC. This bit is writable only if CPUID.06H:EAX[bit 13] = 1. Default = one (1).
•
Bits 63:1 are reserved and must be zero.
Fine-grain OS control of HDC operation at the granularity of per-logical-processor is provided by IA32_PM_CTL1.
At RESET, all logical processors are allowed to participate in HDC operation such that OS can manage HDC using
the package-level IA32_PKG_HDC_CTL.
Writes to IA32_PM_CTL1 complete with the latency that is typical to WRMSR to a Logical Processor level MSR.
When the OS chooses to manage HDC operation at per-logical-processor granularity, it can write to IA32_PM_CTL1
on one or more logical processors as desired. Each write to IA32_PM_CTL1 must be done by code that executes on
the logical processor targeted to be allowed into or blocked from HDC operation.
Blocking one logical processor for HDC operation may have package level impact. For example, the processor may
decide to stop duty cycling of all other Logical Processors as well.
The propagation of IA32_PKG_HDC_CTL.HDC_PKG_Enable in a package takes longer than a WRMSR to
IA32_PM_CTL1. The last completed write to IA32_PM_CTL1 on a logical processor will be honored when a ‘0’-to-’1’
transition of IA32_PKG_HDC_CTL.HDC_PKG_Enable arrives to a logical processor.
14.5.4
HDC Residency Counters
There is a collection of counters available for software to track various residency metrics related to HDC operation.
In general, HDC residency time is defined as the time in HDC forced idle state at the granularity of per-logicalprocessor, per-core, or package. At the granularity of per-core/package-level HDC residency, at least one of the
logical processor in a core/package must be in the HDC forced idle state.
14.5.4.1
IA32_THREAD_STALL
Software can track per-logical-processor HDC residency using the architectural MSR IA32_THREAD_STALL.The
layout of the IA32_THREAD_STALL MSR is shown in Figure 14-14. Each logical processor in a package has its own
IA32_THREAD_STALL MSR. The bit fields are described below:
63
0
Stall_cycle_cnt
Figure 14-14. IA32_THREAD_STALL MSR
•
Stall_Cycle_Cnt (bits 63:0, R/O) — Stores accumulated HDC forced-idle cycle count of this processor core
since last RESET. This counter increments at the same rate of the TSC. The count is updated only after the
logical processor exits from the forced idled C-state. At each update, the number of cycles that the logical
processor was stalled due to forced-idle will be added to the counter. This counter is available only if
CPUID.06H:EAX[bit 13] = 1. Default = zero (0).
Vol. 3B 14-15
POWER AND THERMAL MANAGEMENT
A value of zero in IA32_THREAD_STALL indicates either HDC is not supported or the logical processor never
serviced any forced HDC idle. A non-zero value in IA32_THREAD_STALL indicates the HDC forced-idle residency
times of the logical processor. It also indicates the forced-idle cycles due to HDC that could appear as C0 time to
traditional OS accounting mechanisms (e.g. time-stamping OS idle/exit events).
Software can read IA32_THREAD_STALL irrespective of the state of IA32_PKG_HDC_CTL and IA32_PM_CTL1, as
long as CPUID.06H:EAX[bit 13] = 1.
14.5.4.2
Non-Architectural HDC Residency Counters
Processors that support HDC operation may provide the following model-specific HDC residency counters.
MSR_CORE_HDC_RESIDENCY
Software can track per-core HDC residency using the counter MSR_CORE_HDC_RESIDENCY. This counter increments when the core is in C3 state or deeper (all logical processors in this core are idle due to either HDC or other
mechanisms) and at least one of the logical processors is in HDC forced idle state. The layout of the
MSR_CORE_HDC_RESIDENCY is shown in Figure 14-15. Each processor core in a package has its own
MSR_CORE_HDC_RESIDENCY MSR. The bit fields are described below:
63
0
Core_Cx_duty_cycle_cnt
Figure 14-15. MSR_CORE_HDC_RESIDENCY MSR
•
Core_Cx_Duty_Cycle_Cnt (bits 63:0, R/O) — Stores accumulated HDC forced-idle cycle count of this
processor core since last RESET. This counter increments at the same rate of the TSC. The count is updated only
after core C-state exit from a forced idled C-state. At each update, the increment counts cycles when the core
is in a Cx state (all its logical processor are idle) and at least one logical processor in this core was forced into
idle state due to HDC. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR will cause a #GP fault. Default
= zero (0).
A value of zero in MSR_CORE_HDC_RESIDENCY indicates either HDC is not supported or this processor core never
serviced any forced HDC idle.
MSR_PKG_HDC_SHALLOW_RESIDENCY
The counter MSR_PKG_HDC_SHALLOW_RESIDENCY allows software to track HDC residency time when the
package is in C2 state, all processor cores in the package are not active and at least one logical processor was
forced into idle state due to HDC. The layout of the MSR_PKG_HDC_SHALLOW_RESIDENCY is shown in
Figure 14-16. There is one MSR_PKG_HDC_SHALLOW_RESIDENCY per package. The bit fields are described
below:
63
0
Pkg_Duty_cycle_cnt
Figure 14-16. MSR_PKG_HDC_SHALLOW_RESIDENCY MSR
•
Pkg_Duty_Cycle_Cnt (bits 63:0, R/O) — Stores accumulated HDC forced-idle cycle count of this processor
core since last RESET. This counter increments at the same rate of the TSC. Package shallow residency may be
implementation specific. In the initial implementation, the threshold is package C2-state. The count is
updated only after package C2-state exit from a forced idled C-state. At each update, the increment counts
14-16 Vol. 3B
POWER AND THERMAL MANAGEMENT
cycles when the package is in C2 state and at least one processor core in this package was forced into idle state
due to HDC. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR may cause a #GP fault. Default = zero
(0).
A value of zero in MSR_PKG_HDC_SHALLOW_RESIDENCY indicates either HDC is not supported or this processor
package never serviced any forced HDC idle.
MSR_PKG_HDC_DEEP_RESIDENCY
The counter MSR_PKG_HDC_DEEP_RESIDENCY allows software to track HDC residency time when the package is
in a software-specified package Cx state, all processor cores in the package are not active and at least one logical
processor was forced into idle state due to HDC. Selection of a specific package Cx state can be configured using
MSR_PKG_HDC_CONFIG. The layout of the MSR_PKG_HDC_DEEP_RESIDENCY is shown in Figure 14-17. There is
one MSR_PKG_HDC_DEEP_RESIDENCY per package. The bit fields are described below:
63
0
Pkg_Cx_duty_cycle_cnt
Figure 14-17. MSR_PKG_HDC_DEEP_RESIDENCY MSR
•
Pkg_Cx_Duty_Cycle_Cnt (bits 63:0, R/O) — Stores accumulated HDC forced-idle cycle count of this
processor core since last RESET. This counter increments at the same rate of the TSC. The count is updated
only after package C-state exit from a forced idle state. At each update, the increment counts cycles when the
package is in the software-configured Cx state and at least one processor core in this package was forced into
idle state due to HDC. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR may cause a #GP fault.
Default = zero (0).
A value of zero in MSR_PKG_HDC_SHALLOW_RESIDENCY indicates either HDC is not supported or this processor
package never serviced any forced HDC idle.
MSR_PKG_HDC_CONFIG
MSR_PKG_HDC_CONFIG allows software to configure the package Cx state that the counter
MSR_PKG_HDC_DEEP_RESIDENCY monitors. The layout of the MSR_PKG_HDC_CONFIG is shown in Figure 14-18.
There is one MSR_PKG_HDC_CONFIG per package. The bit fields are described below:
2
63
0
Reserved
Reserved
HDC_Cx_Monitor
Figure 14-18. MSR_PKG_HDC_CONFIG MSR
•
Pkg_Cx_Monitor (bits 2:0, R/W) — Selects which package C-state the MSR_HDC_DEEP_RESIDENCY
counter will monitor. The encoding of the HDC_Cx_Monitor field are: 0: no-counting; 1: count package C2 only,
2: count package C3 and deeper; 3: count package C6 and deeper; 4: count package C7 and deeper; other
encodings are reserved. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR may cause a #GP fault.
Default = zero (0).
•
Bits 63:3 are reserved and must be zero.
Vol. 3B 14-17
POWER AND THERMAL MANAGEMENT
14.5.5
MPERF and APERF Counters Under HDC
HDC operation can be thought of as an average effective frequency drop due to all or some of the Logical Processors enter an idle state period.
1600 MHz: 25% Utilization /75% Forced Idle
Effective Frequency @ 100% Utilization: 400 MHz
Figure 14-19. Example of Effective Frequency Reduction and Forced Idle Period of HDC
By default, the IA32_MPERF counter counts during forced idle periods as if the logical processor was active. The
IA32_APERF counter does not count during forced idle state. This counting convention allows the OS to compute
the average effective frequency of the Logical Processor between the last MWAIT exit and the next MWAIT entry
(OS visible C0) by ΔACNT/ΔMCNT * TSC Frequency.
14.6
MWAIT EXTENSIONS FOR ADVANCED POWER MANAGEMENT
IA-32 processors may support a number of C-states1 that reduce power consumption for inactive states. Intel Core
Solo and Intel Core Duo processors support both deeper C-state and MWAIT extensions that can be used by OS to
implement power management policy.
Software should use CPUID to discover if a target processor supports the enumeration of MWAIT extensions. If
CPUID.05H.ECX[Bit 0] = 1, the target processor supports MWAIT extensions and their enumeration (see Chapter
4, “Instruction Set Reference, M-U,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2B).
If CPUID.05H.ECX[Bit 1] = 1, the target processor supports using interrupts as break-events for MWAIT, even
when interrupts are disabled. Use this feature to measure C-state residency as follows:
•
Software can write to bit 0 in the MWAIT Extensions register (ECX) when issuing an MWAIT to enter into a
processor-specific C-state or sub C-state.
•
When a processor comes out of an inactive C-state or sub C-state, software can read a timestamp before an
interrupt service routine (ISR) is potentially executed.
CPUID.05H.EDX allows software to enumerate processor-specific C-states and sub C-states available for use with
MWAIT extensions. IA-32 processors may support more than one C-state of a given C-state type. These are called
sub C-states. Numerically higher C-state have higher power savings and latency (upon entering and exiting) than
lower-numbered C-state.
At CPL = 0, system software can specify desired C-state and sub C-state by using the MWAIT hints register (EAX).
Processors will not go to C-state and sub C-state deeper than what is specified by the hint register. If CPL > 0 and
if MONITOR/MWAIT is supported at CPL > 0, the processor will only enter C1-state (regardless of the C-state
request in the hints register).
Executing MWAIT generates an exception on processors operating at a privilege level where MONITOR/MWAIT are
not supported.
1. The processor-specific C-states defined in MWAIT extensions can map to ACPI defined C-state types (C0, C1, C2, C3). The mapping
relationship depends on the definition of a C-state by processor implementation and is exposed to OSPM by the BIOS using the ACPI
defined _CST table.
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POWER AND THERMAL MANAGEMENT
NOTE
If MWAIT is used to enter a C-state (including sub C-state) that is numerically higher than C1, a
store to the address range armed by MONITOR instruction will cause the processor to exit MWAIT if
the store was originated by other processor agents. A store from non-processor agent may not
cause the processor to exit MWAIT.
14.7
THERMAL MONITORING AND PROTECTION
The IA-32 architecture provides the following mechanisms for monitoring temperature and controlling thermal
power:
1. The catastrophic shutdown detector forces processor execution to stop if the processor’s core temperature
rises above a preset limit.
2. Automatic and adaptive thermal monitoring mechanisms force the processor to reduce it’s power
consumption in order to operate within predetermined temperature limits.
3. The software controlled clock modulation mechanism permits operating systems to implement power
management policies that reduce power consumption; this is in addition to the reduction offered by automatic
thermal monitoring mechanisms.
4. On-die digital thermal sensor and interrupt mechanisms permit the OS to manage thermal conditions
natively without relying on BIOS or other system board components.
The first mechanism is not visible to software. The other three mechanisms are visible to software using processor
feature information returned by executing CPUID with EAX = 1.
The second mechanism includes:
•
Automatic thermal monitoring provides two modes of operation. One mode modulates the clock duty cycle;
the second mode changes the processor’s frequency. Both modes are used to control the core temperature of
the processor.
•
Adaptive thermal monitoring can provide flexible thermal management on processors made of multiple
cores.
The third mechanism modulates the clock duty cycle of the processor. As shown in Figure 14-20, the phrase ‘duty
cycle’ does not refer to the actual duty cycle of the clock signal. Instead it refers to the time period during which
the clock signal is allowed to drive the processor chip. By using the stop clock mechanism to control how often the
processor is clocked, processor power consumption can be modulated.
Clock Applied to Processor
Stop-Clock Duty Cycle
25% Duty Cycle (example only)
Figure 14-20. Processor Modulation Through Stop-Clock Mechanism
For previous automatic thermal monitoring mechanisms, software controlled mechanisms that changed processor
operating parameters to impact changes in thermal conditions. Software did not have native access to the native
thermal condition of the processor; nor could software alter the trigger condition that initiated software program
control.
The fourth mechanism (listed above) provides access to an on-die digital thermal sensor using a model-specific
register and uses an interrupt mechanism to alert software to initiate digital thermal monitoring.
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14.7.1
Catastrophic Shutdown Detector
P6 family processors introduced a thermal sensor that acts as a catastrophic shutdown detector. This catastrophic
shutdown detector was also implemented in Pentium 4, Intel Xeon and Pentium M processors. It is always enabled.
When processor core temperature reaches a factory preset level, the sensor trips and processor execution is halted
until after the next reset cycle.
14.7.2
Thermal Monitor
Pentium 4, Intel Xeon and Pentium M processors introduced a second temperature sensor that is factory-calibrated
to trip when the processor’s core temperature crosses a level corresponding to the recommended thermal design
envelop. The trip-temperature of the second sensor is calibrated below the temperature assigned to the catastrophic shutdown detector.
14.7.2.1
Thermal Monitor 1
The Pentium 4 processor uses the second temperature sensor in conjunction with a mechanism called Thermal
Monitor 1 (TM1) to control the core temperature of the processor. TM1 controls the processor’s temperature by
modulating the duty cycle of the processor clock. Modulation of duty cycles is processor model specific. Note that
the processors STPCLK# pin is not used here; the stop-clock circuitry is controlled internally.
Support for TM1 is indicated by CPUID.1:EDX.TM[bit 29] = 1.
TM1 is enabled by setting the thermal-monitor enable flag (bit 3) in IA32_MISC_ENABLE [see Chapter 35, “ModelSpecific Registers (MSRs),”]. Following a power-up or reset, the flag is cleared, disabling TM1. BIOS is required to
enable only one automatic thermal monitoring modes. Operating systems and applications must not disable the
operation of these mechanisms.
14.7.2.2
Thermal Monitor 2
An additional automatic thermal protection mechanism, called Thermal Monitor 2 (TM2), was introduced in the
Intel Pentium M processor and also incorporated in newer models of the Pentium 4 processor family. Intel Core Duo
and Solo processors, and Intel Core 2 Duo processor family all support TM1 and TM2. TM2 controls the core
temperature of the processor by reducing the operating frequency and voltage of the processor and offers a higher
performance level for a given level of power reduction than TM1.
TM2 is triggered by the same temperature sensor as TM1. The mechanism to enable TM2 may be implemented
differently across various IA-32 processor families with different CPUID signatures in the family encoding value, but
will be uniform within an IA-32 processor family.
Support for TM2 is indicated by CPUID.1:ECX.TM2[bit 8] = 1.
14.7.2.3
Two Methods for Enabling TM2
On processors with CPUID family/model/stepping signature encoded as 0x69n or 0x6Dn (early Pentium M processors), TM2 is enabled if the TM_SELECT flag (bit 16) of the MSR_THERM2_CTL register is set to 1 (Figure 14-21)
and bit 3 of the IA32_MISC_ENABLE register is set to 1.
Following a power-up or reset, the TM_SELECT flag may be cleared. BIOS is required to enable either TM1 or TM2.
Operating systems and applications must not disable mechanisms that enable TM1 or TM2. If bit 3 of the
IA32_MISC_ENABLE register is set and TM_SELECT flag of the MSR_THERM2_CTL register is cleared, TM1 is
enabled.
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POWER AND THERMAL MANAGEMENT
31
0
16
Reserved
Reserved
TM_SELECT
Figure 14-21. MSR_THERM2_CTL Register On Processors with CPUID Family/Model/Stepping Signature Encoded
as 0x69n or 0x6Dn
On processors introduced after the Pentium 4 processor (this includes most Pentium M processors), the method
used to enable TM2 is different. TM2 is enable by setting bit 13 of IA32_MISC_ENABLE register to 1. This applies to
Intel Core Duo, Core Solo, and Intel Core 2 processor family.
The target operating frequency and voltage for the TM2 transition after TM2 is triggered is specified by the value
written to MSR_THERM2_CTL, bits 15:0 (Figure 14-22). Following a power-up or reset, BIOS is required to enable
at least one of these two thermal monitoring mechanisms. If both TM1 and TM2 are supported, BIOS may choose
to enable TM2 instead of TM1. Operating systems and applications must not disable the mechanisms that enable
TM1or TM2; and they must not alter the value in bits 15:0 of the MSR_THERM2_CTL register.
15
63
0
Reserved
TM2 Transition Target
Figure 14-22. MSR_THERM2_CTL Register for Supporting TM2
14.7.2.4
Performance State Transitions and Thermal Monitoring
If the thermal control circuitry (TCC) for thermal monitor (TM1/TM2) is active, writes to the IA32_PERF_CTL will
effect a new target operating point as follows:
•
If TM1 is enabled and the TCC is engaged, the performance state transition can commence before the TCC is
disengaged.
•
If TM2 is enabled and the TCC is engaged, the performance state transition specified by a write to the
IA32_PERF_CTL will commence after the TCC has disengaged.
14.7.2.5
Thermal Status Information
The status of the temperature sensor that triggers the thermal monitor (TM1/TM2) is indicated through the
thermal status flag and thermal status log flag in the IA32_THERM_STATUS MSR (see Figure 14-23).
The functions of these flags are:
•
Thermal Status flag, bit 0 — When set, indicates that the processor core temperature is currently at the trip
temperature of the thermal monitor and that the processor power consumption is being reduced via either TM1
or TM2, depending on which is enabled. When clear, the flag indicates that the core temperature is below the
thermal monitor trip temperature. This flag is read only.
•
Thermal Status Log flag, bit 1 — When set, indicates that the thermal sensor has tripped since the last
power-up or reset or since the last time that software cleared this flag. This flag is a sticky bit; once set it
remains set until cleared by software or until a power-up or reset of the processor. The default state is clear.
Vol. 3B 14-21
POWER AND THERMAL MANAGEMENT
63
210
Reserved
Thermal Status Log
Thermal Status
Figure 14-23. IA32_THERM_STATUS MSR
After the second temperature sensor has been tripped, the thermal monitor (TM1/TM2) will remain engaged for a
minimum time period (on the order of 1 ms). The thermal monitor will remain engaged until the processor core
temperature drops below the preset trip temperature of the temperature sensor, taking hysteresis into account.
While the processor is in a stop-clock state, interrupts will be blocked from interrupting the processor. This holding
off of interrupts increases the interrupt latency, but does not cause interrupts to be lost. Outstanding interrupts
remain pending until clock modulation is complete.
The thermal monitor can be programmed to generate an interrupt to the processor when the thermal sensor is
tripped. The delivery mode, mask and vector for this interrupt can be programmed through the thermal entry in the
local APIC’s LVT (see Section 10.5.1, “Local Vector Table”). The low-temperature interrupt enable and high-temperature interrupt enable flags in the IA32_THERM_INTERRUPT MSR (see Figure 14-24) control when the interrupt is
generated; that is, on a transition from a temperature below the trip point to above and/or vice-versa.
63
210
Reserved
Low-Temperature Interrupt Enable
High-Temperature Interrupt Enable
Figure 14-24. IA32_THERM_INTERRUPT MSR
•
High-Temperature Interrupt Enable flag, bit 0 — Enables an interrupt to be generated on the transition
from a low-temperature to a high-temperature when set; disables the interrupt when clear.(R/W).
•
Low-Temperature Interrupt Enable flag, bit 1 — Enables an interrupt to be generated on the transition
from a high-temperature to a low-temperature when set; disables the interrupt when clear.
The thermal monitor interrupt can be masked by the thermal LVT entry. After a power-up or reset, the low-temperature interrupt enable and high-temperature interrupt enable flags in the IA32_THERM_INTERRUPT MSR are
cleared (interrupts are disabled) and the thermal LVT entry is set to mask interrupts. This interrupt should be
handled either by the operating system or system management mode (SMM) code.
Note that the operation of the thermal monitoring mechanism has no effect upon the clock rate of the processor's
internal high-resolution timer (time stamp counter).
14.7.2.6
Adaptive Thermal Monitor
The Intel Core 2 Duo processor family supports enhanced thermal management mechanism, referred to as Adaptive Thermal Monitor (Adaptive TM).
Unlike TM2, Adaptive TM is not limited to one TM2 transition target. During a thermal trip event, Adaptive TM (if
enabled) selects an optimal target operating point based on whether or not the current operating point has effectively cooled the processor.
Similar to TM2, Adaptive TM is enable by BIOS. The BIOS is required to test the TM1 and TM2 feature flags and
enable all available thermal control mechanisms (including Adaptive TM) at platform initiation.
Adaptive TM is available only to a subset of processors that support TM2.
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In each chip-multiprocessing (CMP) silicon die, each core has a unique thermal sensor that triggers independently.
These thermal sensor can trigger TM1 or TM2 transitions in the same manner as described in Section 14.7.2.1 and
Section 14.7.2.2. The trip point of the thermal sensor is not programmable by software since it is set during the
fabrication of the processor.
Each thermal sensor in a processor core may be triggered independently to engage thermal management features.
In Adaptive TM, both cores will transition to a lower frequency and/or lower voltage level if one sensor is triggered.
Triggering of this sensor is visible to software via the thermal interrupt LVT entry in the local APIC of a given core.
14.7.3
Software Controlled Clock Modulation
Pentium 4, Intel Xeon and Pentium M processors also support software-controlled clock modulation. This provides
a means for operating systems to implement a power management policy to reduce the power consumption of the
processor. Here, the stop-clock duty cycle is controlled by software through the IA32_CLOCK_MODULATION MSR
(see Figure 14-25).
63
543
10
Reserved
On-Demand Clock Modulation Enable
On-Demand Clock Modulation Duty Cycle
Reserved
Figure 14-25. IA32_CLOCK_MODULATION MSR
The IA32_CLOCK_MODULATION MSR contains the following flag and field used to enable software-controlled clock
modulation and to select the clock modulation duty cycle:
•
On-Demand Clock Modulation Enable, bit 4 — Enables on-demand software controlled clock modulation
when set; disables software-controlled clock modulation when clear.
•
On-Demand Clock Modulation Duty Cycle, bits 1 through 3 — Selects the on-demand clock modulation
duty cycle (see Table 14-3). This field is only active when the on-demand clock modulation enable flag is set.
Note that the on-demand clock modulation mechanism (like the thermal monitor) controls the processor’s stopclock circuitry internally to modulate the clock signal. The STPCLK# pin is not used in this mechanism.
Table 14-3. On-Demand Clock Modulation Duty Cycle Field Encoding
Duty Cycle Field Encoding
Duty Cycle
000B
Reserved
001B
12.5% (Default)
010B
25.0%
011B
37.5%
100B
50.0%
101B
63.5%
110B
75%
111B
87.5%
The on-demand clock modulation mechanism can be used to control processor power consumption. Power
management software can write to the IA32_CLOCK_MODULATION MSR to enable clock modulation and to select
a modulation duty cycle. If on-demand clock modulation and TM1 are both enabled and the thermal status of the
processor is hot (bit 0 of the IA32_THERM_STATUS MSR is set), clock modulation at the duty cycle specified by TM1
takes precedence, regardless of the setting of the on-demand clock modulation duty cycle.
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POWER AND THERMAL MANAGEMENT
For Hyper-Threading Technology enabled processors, the IA32_CLOCK_MODULATION register is duplicated for
each logical processor. In order for the On-demand clock modulation feature to work properly, the feature must be
enabled on all the logical processors within a physical processor. If the programmed duty cycle is not identical for
all the logical processors, the processor core clock will modulate to the highest duty cycle programmed for processors with any of the following CPUID DisplayFamily_DisplayModel signatures (see CPUID instruction in Chapter3,
“Instruction Set Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A): 06_1A, 06_1C, 06_1E, 06_1F, 06_25, 06_26, 06_27, 06_2C, 06_2E, 06_2F, 06_35, 06_36, and 0F_xx. For all
other processors, if the programmed duty cycle is not identical for all logical processors in the same core, the
processor core will modulate at the lowest programmed duty cycle.
For multiple processor cores in a physical package, each processor core can modulate to a programmed duty cycle
independently.
For the P6 family processors, on-demand clock modulation was implemented through the chipset, which controlled
clock modulation through the processor’s STPCLK# pin.
14.7.3.1
Extension of Software Controlled Clock Modulation
Extension of the software controlled clock modulation facility supports on-demand clock modulation duty cycle with
4-bit dynamic range (increased from 3-bit range). Granularity of clock modulation duty cycle is increased to 6.25%
(compared to 12.5%).
Four bit dynamic range control is provided by using bit 0 in conjunction with bits 3:1 of the
IA32_CLOCK_MODULATION MSR (see Figure 14-26).
63
543
0
Reserved
On-Demand Clock Modulation Enable
Extended On-Demand Clock Modulation Duty Cycle
Reserved
Figure 14-26. IA32_CLOCK_MODULATION MSR with Clock Modulation Extension
Extension to software controlled clock modulation is supported only if CPUID.06H:EAX[Bit 5] = 1. If
CPUID.06H:EAX[Bit 5] = 0, then bit 0 of IA32_CLOCK_MODULATION is reserved.
14.7.4
Detection of Thermal Monitor and Software Controlled
Clock Modulation Facilities
The ACPI flag (bit 22) of the CPUID feature flags indicates the presence of the IA32_THERM_STATUS,
IA32_THERM_INTERRUPT, IA32_CLOCK_MODULATION MSRs, and the xAPIC thermal LVT entry.
The TM1 flag (bit 29) of the CPUID feature flags indicates the presence of the automatic thermal monitoring facilities that modulate clock duty cycles.
14.7.4.1
Detection of Software Controlled Clock Modulation Extension
Processor’s support of software controlled clock modulation extension is indicated by CPUID.06H:EAX[Bit 5] = 1.
14.7.5
On Die Digital Thermal Sensors
On die digital thermal sensor can be read using an MSR (no I/O interface). In Intel Core Duo processors, each core
has a unique digital sensor whose temperature is accessible using an MSR. The digital thermal sensor is the
preferred method for reading the die temperature because (a) it is located closer to the hottest portions of the die,
(b) it enables software to accurately track the die temperature and the potential activation of thermal throttling.
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POWER AND THERMAL MANAGEMENT
14.7.5.1
Digital Thermal Sensor Enumeration
The processor supports a digital thermal sensor if CPUID.06H.EAX[0] = 1. If the processor supports digital thermal
sensor, EBX[bits 3:0] determine the number of thermal thresholds that are available for use.
Software sets thermal thresholds by using the IA32_THERM_INTERRUPT MSR. Software reads output of the digital
thermal sensor using the IA32_THERM_STATUS MSR.
14.7.5.2
Reading the Digital Sensor
Unlike traditional analog thermal devices, the output of the digital thermal sensor is a temperature relative to the
maximum supported operating temperature of the processor.
Temperature measurements returned by digital thermal sensors are always at or below TCC activation temperature. Critical temperature conditions are detected using the “Critical Temperature Status” bit. When this bit is set,
the processor is operating at a critical temperature and immediate shutdown of the system should occur. Once the
“Critical Temperature Status” bit is set, reliable operation is not guaranteed.
See Figure 14-27 for the layout of IA32_THERM_STATUS MSR. Bit fields include:
•
Thermal Status (bit 0, RO) — This bit indicates whether the digital thermal sensor high-temperature output
signal (PROCHOT#) is currently active. Bit 0 = 1 indicates the feature is active. This bit may not be written by
software; it reflects the state of the digital thermal sensor.
•
Thermal Status Log (bit 1, R/WC0) — This is a sticky bit that indicates the history of the thermal sensor
high temperature output signal (PROCHOT#). Bit 1 = 1 if PROCHOT# has been asserted since a previous
RESET or the last time software cleared the bit. Software may clear this bit by writing a zero.
•
PROCHOT# or FORCEPR# Event (bit 2, RO) — Indicates whether PROCHOT# or FORCEPR# is being
asserted by another agent on the platform.
63
32 31
27
23 22
16 15
11 10 9 8 7
6 5
4
3
2
1 0
Reserved
Reading Valid
Resolution in Deg. Celsius
Digital Readout
Power Limit Notification Log
Power Limit Notification Status
Thermal Threshold #2 Log
Thermal Threshold #2 Status
Thermal Threshold #1 Log
Thermal Threshold #1 Status
Critical Temperature Log
Critical Temperature Status
PROCHOT# or FORCEPR# Log
PROCHOT# or FORCEPR# Event
Thermal Status Log
Thermal Status
Figure 14-27. IA32_THERM_STATUS Register
•
PROCHOT# or FORCEPR# Log (bit 3, R/WC0) — Sticky bit that indicates whether PROCHOT# or
FORCEPR# has been asserted by another agent on the platform since the last clearing of this bit or a reset. If
bit 3 = 1, PROCHOT# or FORCEPR# has been externally asserted. Software may clear this bit by writing a zero.
External PROCHOT# assertions are only acknowledged if the Bidirectional Prochot feature is enabled.
•
Critical Temperature Status (bit 4, RO) — Indicates whether the critical temperature detector output signal
is currently active. If bit 4 = 1, the critical temperature detector output signal is currently active.
Vol. 3B 14-25
POWER AND THERMAL MANAGEMENT
•
Critical Temperature Log (bit 5, R/WC0) — Sticky bit that indicates whether the critical temperature
detector output signal has been asserted since the last clearing of this bit or reset. If bit 5 = 1, the output
signal has been asserted. Software may clear this bit by writing a zero.
•
Thermal Threshold #1 Status (bit 6, RO) — Indicates whether the actual temperature is currently higher
than or equal to the value set in Thermal Threshold #1. If bit 6 = 0, the actual temperature is lower. If
bit 6 = 1, the actual temperature is greater than or equal to TT#1. Quantitative information of actual
temperature can be inferred from Digital Readout, bits 22:16.
•
Thermal Threshold #1 Log (bit 7, R/WC0) — Sticky bit that indicates whether the Thermal Threshold #1
has been reached since the last clearing of this bit or a reset. If bit 7 = 1, the Threshold #1 has been reached.
Software may clear this bit by writing a zero.
•
Thermal Threshold #2 Status (bit 8, RO) — Indicates whether actual temperature is currently higher than
or equal to the value set in Thermal Threshold #2. If bit 8 = 0, the actual temperature is lower. If bit 8 = 1, the
actual temperature is greater than or equal to TT#2. Quantitative information of actual temperature can be
inferred from Digital Readout, bits 22:16.
•
Thermal Threshold #2 Log (bit 9, R/WC0) — Sticky bit that indicates whether the Thermal Threshold #2
has been reached since the last clearing of this bit or a reset. If bit 9 = 1, the Thermal Threshold #2 has been
reached. Software may clear this bit by writing a zero.
•
Power Limitation Status (bit 10, RO) — Indicates whether the processor is currently operating below OSrequested P-state (specified in IA32_PERF_CTL) or OS-requested clock modulation duty cycle (specified in
IA32_CLOCK_MODULATION). This field is supported only if CPUID.06H:EAX[bit 4] = 1. Package level power
limit notification can be delivered independently to IA32_PACKAGE_THERM_STATUS MSR.
•
Power Notification Log (bit 11, R/WCO) — Sticky bit that indicates the processor went below OSrequested P-state or OS-requested clock modulation duty cycle since the last clearing of this or RESET. This
field is supported only if CPUID.06H:EAX[bit 4] = 1. Package level power limit notification is indicated independently in IA32_PACKAGE_THERM_STATUS MSR.
•
Digital Readout (bits 22:16, RO) — Digital temperature reading in 1 degree Celsius relative to the TCC
activation temperature.
0: TCC Activation temperature,
1: (TCC Activation - 1) , etc. See the processor’s data sheet for details regarding TCC activation.
A lower reading in the Digital Readout field (bits 22:16) indicates a higher actual temperature.
•
Resolution in Degrees Celsius (bits 30:27, RO) — Specifies the resolution (or tolerance) of the digital
thermal sensor. The value is in degrees Celsius. It is recommended that new threshold values be offset from the
current temperature by at least the resolution + 1 in order to avoid hysteresis of interrupt generation.
•
Reading Valid (bit 31, RO) — Indicates if the digital readout in bits 22:16 is valid. The readout is valid if
bit 31 = 1.
Changes to temperature can be detected using two thresholds (see Figure 14-28); one is set above and the other
below the current temperature. These thresholds have the capability of generating interrupts using the core's local
APIC which software must then service. Note that the local APIC entries used by these thresholds are also used by
the Intel® Thermal Monitor; it is up to software to determine the source of a specific interrupt.
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63
25 24 23 22
16 15 14
8
5
4
3
2
1
0
Reserved
Power Limit Notification Enable
Threshold #2 Interrupt Enable
Threshold #2 Value
Threshold #1 Interrupt Enable
Threshold #1 Value
Overheat Interrupt Enable
FORCPR# Interrupt Enable
PROCHOT# Interrupt Enable
Low Temp. Interrupt Enable
High Temp. Interrupt Enable
Figure 14-28. IA32_THERM_INTERRUPT Register
See Figure 14-28 for the layout of IA32_THERM_INTERRUPT MSR. Bit fields include:
•
High-Temperature Interrupt Enable (bit 0, R/W) — This bit allows the BIOS to enable the generation of
an interrupt on the transition from low-temperature to a high-temperature threshold. Bit 0 = 0 (default)
disables interrupts; bit 0 = 1 enables interrupts.
•
Low-Temperature Interrupt Enable (bit 1, R/W) — This bit allows the BIOS to enable the generation of an
interrupt on the transition from high-temperature to a low-temperature (TCC de-activation). Bit 1 = 0 (default)
disables interrupts; bit 1 = 1 enables interrupts.
•
PROCHOT# Interrupt Enable (bit 2, R/W) — This bit allows the BIOS or OS to enable the generation of an
interrupt when PROCHOT# has been asserted by another agent on the platform and the Bidirectional Prochot
feature is enabled. Bit 2 = 0 disables the interrupt; bit 2 = 1 enables the interrupt.
•
FORCEPR# Interrupt Enable (bit 3, R/W) — This bit allows the BIOS or OS to enable the generation of an
interrupt when FORCEPR# has been asserted by another agent on the platform. Bit 3 = 0 disables the
interrupt; bit 3 = 1 enables the interrupt.
•
Critical Temperature Interrupt Enable (bit 4, R/W) — Enables the generation of an interrupt when the
Critical Temperature Detector has detected a critical thermal condition. The recommended response to this
condition is a system shutdown. Bit 4 = 0 disables the interrupt; bit 4 = 1 enables the interrupt.
•
Threshold #1 Value (bits 14:8, R/W) — A temperature threshold, encoded relative to the TCC Activation
temperature (using the same format as the Digital Readout). This threshold is compared against the Digital
Readout and is used to generate the Thermal Threshold #1 Status and Log bits as well as the Threshold #1
thermal interrupt delivery.
•
Threshold #1 Interrupt Enable (bit 15, R/W) — Enables the generation of an interrupt when the actual
temperature crosses the Threshold #1 setting in any direction. Bit 15 = 1 enables the interrupt; bit 15 = 0
disables the interrupt.
•
Threshold #2 Value (bits 22:16, R/W) —A temperature threshold, encoded relative to the TCC Activation
temperature (using the same format as the Digital Readout). This threshold is compared against the Digital
Readout and is used to generate the Thermal Threshold #2 Status and Log bits as well as the Threshold #2
thermal interrupt delivery.
•
Threshold #2 Interrupt Enable (bit 23, R/W) — Enables the generation of an interrupt when the actual
temperature crosses the Threshold #2 setting in any direction. Bit 23 = 1enables the interrupt; bit 23 = 0
disables the interrupt.
•
Power Limit Notification Enable (bit 24, R/W) — Enables the generation of power notification events when
the processor went below OS-requested P-state or OS-requested clock modulation duty cycle. This field is
supported only if CPUID.06H:EAX[bit 4] = 1. Package level power limit notification can be enabled independently by IA32_PACKAGE_THERM_INTERRUPT MSR.
Vol. 3B 14-27
POWER AND THERMAL MANAGEMENT
14.7.6
Power Limit Notification
Platform firmware may be capable of specifying a power limit to restrict power delivered to a platform component,
such as a physical processor package. This constraint imposed by platform firmware may occasionally cause the
processor to operate below OS-requested P or T-state. A power limit notification event can be delivered using the
existing thermal LVT entry in the local APIC.
Software can enumerate the presence of the processor’s support for power limit notification by verifying
CPUID.06H:EAX[bit 4] = 1.
If CPUID.06H:EAX[bit 4] = 1, then IA32_THERM_INTERRUPT and IA32_THERM_STATUS provides the following
facility to manage power limit notification:
•
Bits 10 and 11 in IA32_THERM_STATUS informs software of the occurrence of processor operating below OSrequested P-state or clock modulation duty cycle setting (see Figure 14-27).
•
Bit 24 in IA32_THERM_INTERRUPT enables the local APIC to deliver a thermal event when the processor went
below OS-requested P-state or clock modulation duty cycle setting (see Figure 14-28).
14.8
PACKAGE LEVEL THERMAL MANAGEMENT
The thermal management facilities like IA32_THERM_INTERRUPT and IA32_THERM_STATUS are often implemented with a processor core granularity. To facilitate software manage thermal events from a package level granularity, two architectural MSR is provided for package level thermal management. The
IA32_PACKAGE_THERM_STATUS and IA32_PACKAGE_THERM_INTERRUPT MSRs use similar interfaces as
IA32_THERM_STATUS and IA32_THERM_INTERRUPT, but are shared in each physical processor package.
Software can enumerate the presence of the processor’s support for package level thermal management facility
(IA32_PACKAGE_THERM_STATUS and IA32_PACKAGE_THERM_INTERRUPT) by verifying CPUID.06H:EAX[bit 6] =
1.
The layout of IA32_PACKAGE_THERM_STATUS MSR is shown in Figure 14-29.
63
32 31
27
23 22
16 15
11 10 9 8 7
6 5
4
3
2
1 0
Reserved
PKG Digital Readout
PKG Power Limit Notification Log
PKG Power Limit Notification Status
PKG Thermal Threshold #2 Log
PKG Thermal Threshold #2 Status
PKG Thermal Threshold #1 Log
PKG Thermal Threshold #1 Status
PKG Critical Temperature Log
PKG Critical Temperature Status
PKG PROCHOT# or FORCEPR# Log
PKG PROCHOT# or FORCEPR# Event
PKG Thermal Status Log
PKG Thermal Status
Figure 14-29. IA32_PACKAGE_THERM_STATUS Register
•
Package Thermal Status (bit 0, RO) — This bit indicates whether the digital thermal sensor hightemperature output signal (PROCHOT#) for the package is currently active. Bit 0 = 1 indicates the feature is
active. This bit may not be written by software; it reflects the state of the digital thermal sensor.
14-28 Vol. 3B
POWER AND THERMAL MANAGEMENT
•
Package Thermal Status Log (bit 1, R/WC0) — This is a sticky bit that indicates the history of the thermal
sensor high temperature output signal (PROCHOT#) of the package. Bit 1 = 1 if package PROCHOT# has been
asserted since a previous RESET or the last time software cleared the bit. Software may clear this bit by writing
a zero.
•
Package PROCHOT# Event (bit 2, RO) — Indicates whether package PROCHOT# is being asserted by
another agent on the platform.
•
Package PROCHOT# Log (bit 3, R/WC0) — Sticky bit that indicates whether package PROCHOT# has been
asserted by another agent on the platform since the last clearing of this bit or a reset. If bit 3 = 1, package
PROCHOT# has been externally asserted. Software may clear this bit by writing a zero.
•
Package Critical Temperature Status (bit 4, RO) — Indicates whether the package critical temperature
detector output signal is currently active. If bit 4 = 1, the package critical temperature detector output signal
is currently active.
•
Package Critical Temperature Log (bit 5, R/WC0) — Sticky bit that indicates whether the package critical
temperature detector output signal has been asserted since the last clearing of this bit or reset. If bit 5 = 1, the
output signal has been asserted. Software may clear this bit by writing a zero.
•
Package Thermal Threshold #1 Status (bit 6, RO) — Indicates whether the actual package temperature is
currently higher than or equal to the value set in Package Thermal Threshold #1. If bit 6 = 0, the actual
temperature is lower. If bit 6 = 1, the actual temperature is greater than or equal to PTT#1. Quantitative
information of actual package temperature can be inferred from Package Digital Readout, bits 22:16.
•
Package Thermal Threshold #1 Log (bit 7, R/WC0) — Sticky bit that indicates whether the Package
Thermal Threshold #1 has been reached since the last clearing of this bit or a reset. If bit 7 = 1, the Package
Threshold #1 has been reached. Software may clear this bit by writing a zero.
•
Package Thermal Threshold #2 Status (bit 8, RO) — Indicates whether actual package temperature is
currently higher than or equal to the value set in Package Thermal Threshold #2. If bit 8 = 0, the actual
temperature is lower. If bit 8 = 1, the actual temperature is greater than or equal to PTT#2. Quantitative
information of actual temperature can be inferred from Package Digital Readout, bits 22:16.
•
Package Thermal Threshold #2 Log (bit 9, R/WC0) — Sticky bit that indicates whether the Package
Thermal Threshold #2 has been reached since the last clearing of this bit or a reset. If bit 9 = 1, the Package
Thermal Threshold #2 has been reached. Software may clear this bit by writing a zero.
•
Package Power Limitation Status (bit 10, RO) — Indicates package power limit is forcing one ore more
processors to operate below OS-requested P-state. Note that package power limit violation may be caused by
processor cores or by devices residing in the uncore. Software can examine IA32_THERM_STATUS to
determine if the cause originates from a processor core (see Figure 14-27).
•
Package Power Notification Log (bit 11, R/WCO) — Sticky bit that indicates any processor in the package
went below OS-requested P-state or OS-requested clock modulation duty cycle since the last clearing of this or
RESET.
•
Package Digital Readout (bits 22:16, RO) — Package digital temperature reading in 1 degree Celsius
relative to the package TCC activation temperature.
0: Package TCC Activation temperature,
1: (PTCC Activation - 1) , etc. See the processor’s data sheet for details regarding PTCC activation.
A lower reading in the Package Digital Readout field (bits 22:16) indicates a higher actual temperature.
The layout of IA32_PACKAGE_THERM_INTERRUPT MSR is shown in Figure 14-30.
Vol. 3B 14-29
POWER AND THERMAL MANAGEMENT
63
25 24 23 22
16 15 14
8
5
4
3
2
1
0
Reserved
Pkg Power Limit Notification Enable
Pkg Threshold #2 Interrupt Enable
Pkg Threshold #2 Value
Pkg Threshold #1 Interrupt Enable
Pkg Threshold #1 Value
Pkg Overheat Interrupt Enable
Pkg PROCHOT# Interrupt Enable
Pkg Low Temp. Interrupt Enable
Pkg High Temp. Interrupt Enable
Figure 14-30. IA32_PACKAGE_THERM_INTERRUPT Register
•
Package High-Temperature Interrupt Enable (bit 0, R/W) — This bit allows the BIOS to enable the
generation of an interrupt on the transition from low-temperature to a package high-temperature threshold.
Bit 0 = 0 (default) disables interrupts; bit 0 = 1 enables interrupts.
•
Package Low-Temperature Interrupt Enable (bit 1, R/W) — This bit allows the BIOS to enable the
generation of an interrupt on the transition from high-temperature to a low-temperature (TCC de-activation).
Bit 1 = 0 (default) disables interrupts; bit 1 = 1 enables interrupts.
•
Package PROCHOT# Interrupt Enable (bit 2, R/W) — This bit allows the BIOS or OS to enable the
generation of an interrupt when Package PROCHOT# has been asserted by another agent on the platform and
the Bidirectional Prochot feature is enabled. Bit 2 = 0 disables the interrupt; bit 2 = 1 enables the interrupt.
•
Package Critical Temperature Interrupt Enable (bit 4, R/W) — Enables the generation of an interrupt
when the Package Critical Temperature Detector has detected a critical thermal condition. The recommended
response to this condition is a system shutdown. Bit 4 = 0 disables the interrupt; bit 4 = 1 enables the
interrupt.
•
Package Threshold #1 Value (bits 14:8, R/W) — A temperature threshold, encoded relative to the
Package TCC Activation temperature (using the same format as the Digital Readout). This threshold is
compared against the Package Digital Readout and is used to generate the Package Thermal Threshold #1
Status and Log bits as well as the Package Threshold #1 thermal interrupt delivery.
•
Package Threshold #1 Interrupt Enable (bit 15, R/W) — Enables the generation of an interrupt when the
actual temperature crosses the Package Threshold #1 setting in any direction. Bit 15 = 1 enables the interrupt;
bit 15 = 0 disables the interrupt.
•
Package Threshold #2 Value (bits 22:16, R/W) —A temperature threshold, encoded relative to the PTCC
Activation temperature (using the same format as the Package Digital Readout). This threshold is compared
against the Package Digital Readout and is used to generate the Package Thermal Threshold #2 Status and Log
bits as well as the Package Threshold #2 thermal interrupt delivery.
•
Package Threshold #2 Interrupt Enable (bit 23, R/W) — Enables the generation of an interrupt when the
actual temperature crosses the Package Threshold #2 setting in any direction. Bit 23 = 1 enables the interrupt;
bit 23 = 0 disables the interrupt.
•
Package Power Limit Notification Enable (bit 24, R/W) — Enables the generation of package power
notification events.
14.8.1
Support for Passive and Active cooling
Passive and active cooling may be controlled by the OS power management agent through ACPI control methods.
On platforms providing package level thermal management facility described in the previous section, it is recommended that active cooling (FAN control) should be driven by measuring the package temperature using the
IA32_PACKAGE_THERM_INTERRUPT MSR.
14-30 Vol. 3B
POWER AND THERMAL MANAGEMENT
Passive cooling (frequency throttling) should be driven by measuring (a) the core and package temperatures, or
(b) only the package temperature. If measured package temperature led the power management agent to choose
which core to execute passive cooling, then all cores need to execute passive cooling. Core temperature is
measured using the IA32_THERMAL_STATUS and IA32_THERMAL_INTERRUPT MSRs. The exact implementation
details depend on the platform firmware and possible solutions include defining two different thermal zones (one
for core temperature and passive cooling and the other for package temperature and active cooling).
14.9
PLATFORM SPECIFIC POWER MANAGEMENT SUPPORT
This section covers power management interfaces that are not architectural but addresses the power management
needs of several platform specific components. Specifically, RAPL (Running Average Power Limit) interfaces
provide mechanisms to enforce power consumption limit. Power limiting usages have specific usages in client and
server platforms.
For client platform power limit control and for server platforms used in a data center, the following power and
thermal related usages are desirable:
•
Platform Thermal Management: Robust mechanisms to manage component, platform, and group-level
thermals, either proactively or reactively (e.g., in response to a platform-level thermal trip point).
•
Platform Power Limiting: More deterministic control over the system's power consumption, for example to
meet battery life targets on rack-level or container-level power consumption goals within a datacenter.
•
Power/Performance Budgeting: Efficient means to control the power consumed (and therefore the sustained
performance delivered) within and across platforms.
The server and client usage models are addressed by RAPL interfaces, which expose multiple domains of power
rationing within each processor socket. Generally, these RAPL domains may be viewed to include hierarchically:
•
•
Package domain is the processor die.
Memory domain includes the directly-attached DRAM; an additional power plane may constitute a separate
domain.
In order to manage the power consumed across multiple sockets via RAPL, individual limits must be programmed
for each processor complex. Programming specific RAPL domain across multiple sockets is not supported.
14.9.1
RAPL Interfaces
RAPL interfaces consist of non-architectural MSRs. Each RAPL domain supports the following set of capabilities,
some of which are optional as stated below.
•
•
•
Power limit - MSR interfaces to specify power limit, time window; lock bit, clamp bit etc.
•
Power Info (Optional) - Interface providing information on the range of parameters for a given domain,
minimum power, maximum power etc.
•
Policy (Optional) - 4-bit priority information that is a hint to hardware for dividing budget between sub-domains
in a parent domain.
Energy Status - Power metering interface providing energy consumption information.
Perf Status (Optional) - Interface providing information on the performance effects (regression) due to power
limits. It is defined as a duration metric that measures the power limit effect in the respective domain. The
meaning of duration is domain specific.
Each of the above capabilities requires specific units in order to describe them. Power is expressed in Watts, Time
is expressed in Seconds, and Energy is expressed in Joules. Scaling factors are supplied to each unit to make the
information presented meaningful in a finite number of bits. Units for power, energy, and time are exposed in the
read-only MSR_RAPL_POWER_UNIT MSR.
Vol. 3B 14-31
POWER AND THERMAL MANAGEMENT
63
20 19
16 15 13 12
8 7
4
3
0
Reserved
Time units
Energy status units
Power units
Figure 14-31. MSR_RAPL_POWER_UNIT Register
MSR_RAPL_POWER_UNIT (Figure 14-31) provides the following information across all RAPL domains:
•
Power Units (bits 3:0): Power related information (in Watts) is based on the multiplier, 1/ 2^PU; where PU is
an unsigned integer represented by bits 3:0. Default value is 0011b, indicating power unit is in 1/8 Watts
increment.
•
Energy Status Units (bits 12:8): Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value is 10000b, indicating energy status
unit is in 15.3 micro-Joules increment.
•
Time Units (bits 19:16): Time related information (in Seconds) is based on the multiplier, 1/ 2^TU; where TU
is an unsigned integer represented by bits 19:16. Default value is 1010b, indicating time unit is in 976 microseconds increment.
14.9.2
RAPL Domains and Platform Specificity
The specific RAPL domains available in a platform vary across product segments. Platforms targeting the client
segment support the following RAPL domain hierarchy:
•
•
Package
Two power planes: PP0 and PP1 (PP1 may reflect to uncore devices)
Platforms targeting the server segment support the following RAPL domain hierarchy:
•
•
•
Package
Power plane: PP0
DRAM
Each level of the RAPL hierarchy provides a respective set of RAPL interface MSRs. Table 14-4 lists the RAPL MSR
interfaces available for each RAPL domain. The power limit MSR of each RAPL domain is located at offset 0 relative
to an MSR base address which is non-architectural (see Chapter 35). The energy status MSR of each domain is
located at offset 1 relative to the MSR base address of respective domain.
Table 14-4. RAPL MSR Interfaces and RAPL Domains
Domain
PKG
DRAM
PP0
14-32 Vol. 3B
Power Limit
(Offset 0)
MSR_PKG_POWER_
LIMIT
Energy Status (Offset
1)
MSR_PKG_ENERGY_STA RESERVED
TUS
MSR_DRAM_POWER MSR_DRAM_ENERGY_S
_LIMIT
TATUS
MSR_PP0_POWER_
LIMIT
Policy
(Offset 2)
RESERVED
MSR_PP0_ENERGY_STA MSR_PP0_POLICY
TUS
Perf Status
(Offset 3)
Power Info
(Offset 4)
MSR_PKG_PERF_STATUS
MSR_PKG_POWER_I
NFO
MSR_DRAM_PERF_STATUS
MSR_DRAM_POWER
_INFO
MSR_PP0_PERF_STATUS
RESERVED
POWER AND THERMAL MANAGEMENT
Table 14-4. RAPL MSR Interfaces and RAPL Domains
PP1
MSR_PP1_POWER_
LIMIT
MSR_PP1_ENERGY_STA MSR_PP1_POLICY
TUS
RESERVED
RESERVED
The presence of the optional MSR interfaces (the three right-most columns of Table 14-4) may be model-specific.
See Chapter 35 for detail.
14.9.3
Package RAPL Domain
The MSR interfaces defined for the package RAPL domain are:
•
MSR_PKG_POWER_LIMIT allows software to set power limits for the package and measurement attributes
associated with each limit,
•
•
MSR_PKG_ENERGY_STATUS reports measured actual energy usage,
MSR_PKG_POWER_INFO reports the package power range information for RAPL usage.
MSR_PKG_PERF_STATUS can report the performance impact of power limiting, but its availability may be modelspecific.
63 62
L
O
C
K
56 55
49 48 47 46
Time window
Power Limit #2
32 31
24 23
Pkg Power Limit #2
17 16 15 14
Time window
Power Limit #1
0
Pkg Power Limit #1
Enable limit #1
Pkg clamping limit #1
Enable limit #2
Pkg clamping limit #2
Figure 14-32. MSR_PKG_POWER_LIMIT Register
MSR_PKG_POWER_LIMIT allows a software agent to define power limitation for the package domain. Power limitation is defined in terms of average power usage (Watts) over a time window specified in MSR_PKG_POWER_LIMIT.
Two power limits can be specified, corresponding to time windows of different sizes. Each power limit provides
independent clamping control that would permit the processor cores to go below OS-requested state to meet the
power limits. A lock mechanism allow the software agent to enforce power limit settings. Once the lock bit is set,
the power limit settings are static and un-modifiable until next RESET.
The bit fields of MSR_PKG_POWER_LIMIT (Figure 14-32) are:
•
Package Power Limit #1(bits 14:0): Sets the average power usage limit of the package domain corresponding to time window # 1. The unit of this field is specified by the “Power Units” field of
MSR_RAPL_POWER_UNIT.
•
•
Enable Power Limit #1(bit 15): 0 = disabled; 1 = enabled.
•
Time Window for Power Limit #1 (bits 23:17): Indicates the time window for power limit #1
Package Clamping Limitation #1 (bit 16): Allow going below OS-requested P/T state setting during time
window specified by bits 23:17.
Time limit = 2^Y * (1.0 + Z/4.0) * Time_Unit
Here “Y” is the unsigned integer value represented. by bits 21:17, “Z” is an unsigned integer represented by
bits 23:22. “Time_Unit” is specified by the “Time Units” field of MSR_RAPL_POWER_UNIT.
Vol. 3B 14-33
POWER AND THERMAL MANAGEMENT
•
Package Power Limit #2(bits 46:32): Sets the average power usage limit of the package domain corresponding to time window # 2. The unit of this field is specified by the “Power Units” field of
MSR_RAPL_POWER_UNIT.
•
•
Enable Power Limit #2(bit 47): 0 = disabled; 1 = enabled.
•
Time Window for Power Limit #2 (bits 55:49): Indicates the time window for power limit #2
Package Clamping Limitation #2 (bit 48): Allow going below OS-requested P/T state setting during time
window specified by bits 23:17.
Time limit = 2^Y * (1.0 + Z/4.0) * Time_Unit
Here “Y” is the unsigned integer value represented. by bits 53:49, “Z” is an unsigned integer represented by
bits 55:54. “Time_Unit” is specified by the “Time Units” field of MSR_RAPL_POWER_UNIT. This field may have
a hard-coded value in hardware and ignores values written by software.
•
Lock (bit 63): If set, all write attempts to this MSR are ignored until next RESET.
MSR_PKG_ENERGY_STATUS is a read-only MSR. It reports the actual energy use for the package domain. This MSR
is updated every ~1msec. It has a wraparound time of around 60 secs when power consumption is high, and may
be longer otherwise.
32 31
63
0
Reserved
Total Energy Consumed
Reserved
Figure 14-33. MSR_PKG_ENERGY_STATUS MSR
•
Total Energy Consumed (bits 31:0): The unsigned integer value represents the total amount of energy
consumed since that last time this register is cleared. The unit of this field is specified by the “Energy Status
Units” field of MSR_RAPL_POWER_UNIT.
MSR_PKG_POWER_INFO is a read-only MSR. It reports the package power range information for RAPL usage. This
MSR provides maximum/minimum values (derived from electrical specification), thermal specification power of the
package domain. It also provides the largest possible time window for software to program the RAPL interface.
63
54 53
48 47 46
Maximum Time window
32 31 30
Maximum Power
Minimum Power
16 15 14
0
Thermal Spec Power
Figure 14-34. MSR_PKG_POWER_INFO Register
•
Thermal Spec Power (bits 14:0): The unsigned integer value is the equivalent of thermal specification power
of the package domain. The unit of this field is specified by the “Power Units” field of MSR_RAPL_POWER_UNIT.
•
Minimum Power (bits 30:16): The unsigned integer value is the equivalent of minimum power derived from
electrical spec of the package domain. The unit of this field is specified by the “Power Units” field of
MSR_RAPL_POWER_UNIT.
•
Maximum Power (bits 46:32): The unsigned integer value is the equivalent of maximum power derived from
the electrical spec of the package domain. The unit of this field is specified by the “Power Units” field of
MSR_RAPL_POWER_UNIT.
14-34 Vol. 3B
POWER AND THERMAL MANAGEMENT
•
Maximum Time Window (bits 53:48): The unsigned integer value is the equivalent of largest acceptable
value to program the time window of MSR_PKG_POWER_LIMIT. The unit of this field is specified by the “Time
Units” field of MSR_RAPL_POWER_UNIT.
MSR_PKG_PERF_STATUS is a read-only MSR. It reports the total time for which the package was throttled due to
the RAPL power limits. Throttling in this context is defined as going below the OS-requested P-state or T-state. It
has a wrap-around time of many hours. The availability of this MSR is platform specific (see Chapter 35).
32 31
63
0
Reserved
Accumulated pkg throttled time
Reserved
Figure 14-35. MSR_PKG_PERF_STATUS MSR
•
Accumulated Package Throttled Time (bits 31:0): The unsigned integer value represents the cumulative
time (since the last time this register is cleared) that the package has throttled. The unit of this field is specified
by the “Time Units” field of MSR_RAPL_POWER_UNIT.
14.9.4
PP0/PP1 RAPL Domains
The MSR interfaces defined for the PP0 and PP1 domains are identical in layout. Generally, PP0 refers to the
processor cores. The availability of PP1 RAPL domain interface is platform-specific. For a client platform, the PP1
domain refers to the power plane of a specific device in the uncore. For server platforms, the PP1 domain is not
supported, but its PP0 domain supports the MSR_PP0_PERF_STATUS interface.
•
MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT allow software to set power limits for the respective power
plane domain.
•
•
MSR_PP0_ENERGY_STATUS/MSR_PP1_ENERGY_STATUS report actual energy usage on a power plane.
MSR_PP0_POLICY/MSR_PP1_POLICY allow software to adjust balance for respective power plane.
MSR_PP0_PERF_STATUS can report the performance impact of power limiting, but it is not available in client platforms.
63
32 31 30
L
O
C
K
24 23
Time window
Power Limit
17 16 15 14
0
Power Limit
Enable limit
Clamping limit
Figure 14-36. MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT Register
MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT allow a software agent to define power limitation for the
respective power plane domain. A lock mechanism in each power plane domain allows the software agent to
enforce power limit settings independently. Once a lock bit is set, the power limit settings in that power plane are
static and un-modifiable until next RESET.
The bit fields of MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT (Figure 14-36) are:
•
Power Limit (bits 14:0): Sets the average power usage limit of the respective power plane domain. The unit
of this field is specified by the “Power Units” field of MSR_RAPL_POWER_UNIT.
Vol. 3B 14-35
POWER AND THERMAL MANAGEMENT
•
•
Enable Power Limit (bit 15): 0 = disabled; 1 = enabled.
•
Time Window for Power Limit (bits 23:17): Indicates the length of time window over which the power limit
#1 will be used by the processor. The numeric value encoded by bits 23:17 is represented by the product of
2^Y *F; where F is a single-digit decimal floating-point value between 1.0 and 1.3 with the fraction digit
represented by bits 23:22, Y is an unsigned integer represented by bits 21:17. The unit of this field is specified
by the “Time Units” field of MSR_RAPL_POWER_UNIT.
•
Lock (bit 31): If set, all write attempts to the MSR and corresponding policy
MSR_PP0_POLICY/MSR_PP1_POLICY are ignored until next RESET.
Clamping Limitation (bit 16): Allow going below OS-requested P/T state setting during time window specified
by bits 23:17.
MSR_PP0_ENERGY_STATUS/MSR_PP1_ENERGY_STATUS are read-only MSRs. They report the actual energy use
for the respective power plane domains. These MSRs are updated every ~1msec.
32 31
63
0
Reserved
Total Energy Consumed
Reserved
Figure 14-37. MSR_PP0_ENERGY_STATUS/MSR_PP1_ENERGY_STATUS MSR
•
Total Energy Consumed (bits 31:0): The unsigned integer value represents the total amount of energy
consumed since the last time this register was cleared. The unit of this field is specified by the “Energy Status
Units” field of MSR_RAPL_POWER_UNIT.
MSR_PP0_POLICY/MSR_PP1_POLICY provide balance power policy control for each power plane by providing
inputs to the power budgeting management algorithm. On platforms that support PP0 (IA cores) and PP1 (uncore
graphic device), the default values give priority to the non-IA power plane. These MSRs enable the PCU to balance
power consumption between the IA cores and uncore graphic device.
63
5 4
0
Priority Level
Figure 14-38. MSR_PP0_POLICY/MSR_PP1_POLICY Register
•
Priority Level (bits 4:0): Priority level input to the PCU for respective power plane. PP0 covers the IA
processor cores, PP1 covers the uncore graphic device. The value 31 is considered highest priority.
MSR_PP0_PERF_STATUS is a read-only MSR. It reports the total time for which the PP0 domain was throttled due
to the power limits. This MSR is supported only in server platform. Throttling in this context is defined as going
below the OS-requested P-state or T-state.
14-36 Vol. 3B
POWER AND THERMAL MANAGEMENT
32 31
63
0
Reserved
Accumulated PP0 throttled time
Reserved
Figure 14-39. MSR_PP0_PERF_STATUS MSR
•
Accumulated PP0 Throttled Time (bits 31:0): The unsigned integer value represents the cumulative time
(since the last time this register is cleared) that the PP0 domain has throttled. The unit of this field is specified
by the “Time Units” field of MSR_RAPL_POWER_UNIT.
14.9.5
DRAM RAPL Domain
The MSR interfaces defined for the DRAM domains are supported only in the server platform. The MSR interfaces
are:
•
MSR_DRAM_POWER_LIMIT allows software to set power limits for the DRAM domain and measurement
attributes associated with each limit.
•
•
•
MSR_DRAM_ENERGY_STATUS reports measured actual energy usage.
MSR_DRAM_POWER_INFO reports the DRAM domain power range information for RAPL usage.
MSR_DRAM_PERF_STATUS can report the performance impact of power limiting.
63
32 31 30
24 23
L
O
C
K
Time window
Power Limit
17 16 15 14
0
Power Limit
Enable limit
Clamping limit
Figure 14-40. MSR_DRAM_POWER_LIMIT Register
MSR_DRAM_POWER_LIMIT allows a software agent to define power limitation for the DRAM domain. Power limitation is defined in terms of average power usage (Watts) over a time window specified in
MSR_DRAM_POWER_LIMIT. A power limit can be specified along with a time window. A lock mechanism allow the
software agent to enforce power limit settings. Once the lock bit is set, the power limit settings are static and unmodifiable until next RESET.
The bit fields of MSR_DRAM_POWER_LIMIT (Figure 14-40) are:
•
DRAM Power Limit #1(bits 14:0): Sets the average power usage limit of the DRAM domain corresponding to
time window # 1. The unit of this field is specified by the “Power Units” field of MSR_RAPL_POWER_UNIT.
•
•
Enable Power Limit #1(bit 15): 0 = disabled; 1 = enabled.
•
Lock (bit 31): If set, all write attempts to this MSR are ignored until next RESET.
Time Window for Power Limit (bits 23:17): Indicates the length of time window over which the power limit
will be used by the processor. The numeric value encoded by bits 23:17 is represented by the product of 2^Y
*F; where F is a single-digit decimal floating-point value between 1.0 and 1.3 with the fraction digit
represented by bits 23:22, Y is an unsigned integer represented by bits 21:17. The unit of this field is specified
by the “Time Units” field of MSR_RAPL_POWER_UNIT.
Vol. 3B 14-37
POWER AND THERMAL MANAGEMENT
MSR_DRAM_ENERGY_STATUS is a read-only MSR. It reports the actual energy use for the DRAM domain. This MSR
is updated every ~1msec.
32 31
63
0
Reserved
Total Energy Consumed
Reserved
Figure 14-41. MSR_DRAM_ENERGY_STATUS MSR
•
Total Energy Consumed (bits 31:0): The unsigned integer value represents the total amount of energy
consumed since that last time this register is cleared. The unit of this field is specified by the “Energy Status
Units” field of MSR_RAPL_POWER_UNIT.
MSR_DRAM_POWER_INFO is a read-only MSR. It reports the DRAM power range information for RAPL usage. This
MSR provides maximum/minimum values (derived from electrical specification), thermal specification power of the
DRAM domain. It also provides the largest possible time window for software to program the RAPL interface.
54 53
63
48 47 46
Maximum Time window
32 31 30
Maximum Power
Minimum Power
16 15 14
0
Thermal Spec Power
Figure 14-42. MSR_DRAM_POWER_INFO Register
•
Thermal Spec Power (bits 14:0): The unsigned integer value is the equivalent of thermal specification power
of the DRAM domain. The unit of this field is specified by the “Power Units” field of MSR_RAPL_POWER_UNIT.
•
Minimum Power (bits 30:16): The unsigned integer value is the equivalent of minimum power derived from
electrical spec of the DRAM domain. The unit of this field is specified by the “Power Units” field of
MSR_RAPL_POWER_UNIT.
•
Maximum Power (bits 46:32): The unsigned integer value is the equivalent of maximum power derived from
the electrical spec of the DRAM domain. The unit of this field is specified by the “Power Units” field of
MSR_RAPL_POWER_UNIT.
•
Maximum Time Window (bits 53:48): The unsigned integer value is the equivalent of largest acceptable
value to program the time window of MSR_DRAM_POWER_LIMIT. The unit of this field is specified by the “Time
Units” field of MSR_RAPL_POWER_UNIT.
MSR_DRAM_PERF_STATUS is a read-only MSR. It reports the total time for which the package was throttled due to
the RAPL power limits. Throttling in this context is defined as going below the OS-requested P-state or T-state. It
has a wrap-around time of many hours. The availability of this MSR is platform specific (see Chapter 35).
32 31
63
Reserved
Accumulated DRAM throttled time
Reserved
Figure 14-43. MSR_DRAM_PERF_STATUS MSR
14-38 Vol. 3B
0
POWER AND THERMAL MANAGEMENT
•
Accumulated Package Throttled Time (bits 31:0): The unsigned integer value represents the cumulative
time (since the last time this register is cleared) that the DRAM domain has throttled. The unit of this field is
specified by the “Time Units” field of MSR_RAPL_POWER_UNIT.
Vol. 3B 14-39
POWER AND THERMAL MANAGEMENT
14-40 Vol. 3B
CHAPTER 15
MACHINE-CHECK ARCHITECTURE
This chapter describes the machine-check architecture and machine-check exception mechanism found in the
Pentium 4, Intel Xeon, Intel Atom, and P6 family processors. See Chapter 6, “Interrupt 18—Machine-Check Exception (#MC),” for more information on machine-check exceptions. A brief description of the Pentium processor’s
machine check capability is also given.
Additionally, a signaling mechanism for software to respond to hardware corrected machine check error is covered.
15.1
MACHINE-CHECK ARCHITECTURE
The Pentium 4, Intel Xeon, Intel Atom, and P6 family processors implement a machine-check architecture that
provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC
errors, parity errors, cache errors, and TLB errors. It consists of a set of model-specific registers (MSRs) that are
used to set up machine checking and additional banks of MSRs used for recording errors that are detected.
The processor signals the detection of an uncorrected machine-check error by generating a machine-check exception (#MC), which is an abort class exception. The implementation of the machine-check architecture does not
ordinarily permit the processor to be restarted reliably after generating a machine-check exception. However, the
machine-check-exception handler can collect information about the machine-check error from the machine-check
MSRs.
Starting with 45 nm Intel 64 processor on which CPUID reports DisplayFamily_DisplayModel as 06H_1AH (see
CPUID instruction in Chapter 3, “Instruction Set Reference, A-L” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A), the processor can report information on corrected machine-check errors and
deliver a programmable interrupt for software to respond to MC errors, referred to as corrected machine-check
error interrupt (CMCI). See Section 15.5 for detail.
Intel 64 processors supporting machine-check architecture and CMCI may also support an additional enhancement, namely, support for software recovery from certain uncorrected recoverable machine check errors. See
Section 15.6 for detail.
15.2
COMPATIBILITY WITH PENTIUM PROCESSOR
The Pentium 4, Intel Xeon, Intel Atom, and P6 family processors support and extend the machine-check exception
mechanism introduced in the Pentium processor. The Pentium processor reports the following machine-check
errors:
•
•
data parity errors during read cycles
unsuccessful completion of a bus cycle
The above errors are reported using the P5_MC_TYPE and P5_MC_ADDR MSRs (implementation specific for the
Pentium processor). Use the RDMSR instruction to read these MSRs. See Chapter 35, “Model-Specific Registers
(MSRs),” for the addresses.
The machine-check error reporting mechanism that Pentium processors use is similar to that used in Pentium 4,
Intel Xeon, Intel Atom, and P6 family processors. When an error is detected, it is recorded in P5_MC_TYPE and
P5_MC_ADDR; the processor then generates a machine-check exception (#MC).
See Section 15.3.3, “Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture,”
and Section 15.10.2, “Pentium Processor Machine-Check Exception Handling,” for information on compatibility
between machine-check code written to run on the Pentium processors and code written to run on P6 family
processors.
Vol. 3B 15-1
MACHINE-CHECK ARCHITECTURE
15.3
MACHINE-CHECK MSRS
Machine check MSRs in the Pentium 4, Intel Atom, Intel Xeon, and P6 family processors consist of a set of global
control and status registers and several error-reporting register banks. See Figure 15-1.
Error-Reporting Bank Registers
(One Set for Each Hardware Unit)
Global Control MSRs
63
0
63
IA32_MCG_CAP MSR
63
0
63
IA32_MCG_STATUS MSR
63
0
IA32_MCi_ADDR MSR
IA32_MCG_CTL MSR
0
63
0
IA32_MCi_STATUS MSR
0
63
0
IA32_MCi_CTL MSR
63
IA32_MCG_EXT_CTL MSR
0
IA32_MCi_MISC MSR
0
63
IA32_MCi_CTL2 MSR
Figure 15-1. Machine-Check MSRs
Each error-reporting bank is associated with a specific hardware unit (or group of hardware units) in the processor.
Use RDMSR and WRMSR to read and to write these registers.
15.3.1
Machine-Check Global Control MSRs
The machine-check global control MSRs include the IA32_MCG_CAP, IA32_MCG_STATUS, and optionally
IA32_MCG_CTL and IA32_MCG_EXT_CTL. See Chapter 35, “Model-Specific Registers (MSRs),” for the addresses of
these registers.
15.3.1.1
IA32_MCG_CAP MSR
The IA32_MCG_CAP MSR is a read-only register that provides information about the machine-check architecture of
the processor. Figure 15-2 shows the layout of the register.
15-2 Vol. 3B
MACHINE-CHECK ARCHITECTURE
63
27 26 25 24 23
16 15
0
12 11 10 9 8 7
Count
Reserved
MCG_LMCE_P[27]
MCG_ELOG_P[26]
MCG_EMC_P[25]
MCG_SER_P[24]
MCG_EXT_CNT[23:16]
MCG_TES_P[11]
MCG_CMCI_P[10]
MCG_EXT_P[9]
MCG_CTL_P[8]
Figure 15-2. IA32_MCG_CAP Register
Where:
•
Count field, bits 7:0 — Indicates the number of hardware unit error-reporting banks available in a particular
processor implementation.
•
MCG_CTL_P (control MSR present) flag, bit 8 — Indicates that the processor implements the
IA32_MCG_CTL MSR when set; this register is absent when clear.
•
MCG_EXT_P (extended MSRs present) flag, bit 9 — Indicates that the processor implements the extended
machine-check state registers found starting at MSR address 180H; these registers are absent when clear.
•
MCG_CMCI_P (Corrected MC error counting/signaling extension present) flag, bit 10 — Indicates
(when set) that extended state and associated MSRs necessary to support the reporting of an interrupt on a
corrected MC error event and/or count threshold of corrected MC errors, is present. When this bit is set, it does
not imply this feature is supported across all banks. Software should check the availability of the necessary
logic on a bank by bank basis when using this signaling capability (i.e. bit 30 settable in individual
IA32_MCi_CTL2 register).
•
MCG_TES_P (threshold-based error status present) flag, bit 11 — Indicates (when set) that bits 56:53
of the IA32_MCi_STATUS MSR are part of the architectural space. Bits 56:55 are reserved, and bits 54:53 are
used to report threshold-based error status. Note that when MCG_TES_P is not set, bits 56:53 of the
IA32_MCi_STATUS MSR are model-specific.
•
MCG_EXT_CNT, bits 23:16 — Indicates the number of extended machine-check state registers present. This
field is meaningful only when the MCG_EXT_P flag is set.
•
MCG_SER_P (software error recovery support present) flag, bit 24 — Indicates (when set) that the
processor supports software error recovery (see Section 15.6), and IA32_MCi_STATUS MSR bits 56:55 are
used to report the signaling of uncorrected recoverable errors and whether software must take recovery
actions for uncorrected errors. Note that when MCG_TES_P is not set, bits 56:53 of the IA32_MCi_STATUS MSR
are model-specific. If MCG_TES_P is set but MCG_SER_P is not set, bits 56:55 are reserved.
•
MCG_EMC_P (Enhanced Machine Check Capability) flag, bit 25 — Indicates (when set) that the
processor supports enhanced machine check capabilities for firmware first signaling.
•
MCG_ELOG_P (extended error logging) flag, bit 26 — Indicates (when set) that the processor allows
platform firmware to be invoked when an error is detected so that it may provide additional platform specific
information in an ACPI format “Generic Error Data Entry” that augments the data included in machine check
bank registers.
For additional information about extended error logging interface, see
http://www.intel.com/content/www/us/en/architecture-and-technology/enhanced-mca-logging-xeonpaper.html
Vol. 3B 15-3
MACHINE-CHECK ARCHITECTURE
•
MCG_LMCE_P (local machine check exception) flag, bit 27 — Indicates (when set) that the following
interfaces are present:
— an extended state LMCE_S (located in bit 3 of IA32_MCG_STATUS), and
— the IA32_MCG_EXT_CTL MSR, necessary to support Local Machine Check Exception (LMCE).
A non-zero MCG_LMCE_P indicates that, when LMCE is enabled as described in Section 15.3.1.5, some machine
check errors may be delivered to only a single logical processor.
The effect of writing to the IA32_MCG_CAP MSR is undefined.
15.3.1.2
IA32_MCG_STATUS MSR
The IA32_MCG_STATUS MSR describes the current state of the processor after a machine-check exception has
occurred (see Figure 15-3).
63
3 2 1 0
Reserved
M
C
I
P
E R
I I
P P
V V
LMCE_S—Local machine check exception signaled
MCIP—Machine check in progress flag
EIPV—Error IP valid flag
RIPV—Restart IP valid flag
Figure 15-3. IA32_MCG_STATUS Register
Where:
•
RIPV (restart IP valid) flag, bit 0 — Indicates (when set) that program execution can be restarted reliably
at the instruction pointed to by the instruction pointer pushed on the stack when the machine-check exception
is generated. When clear, the program cannot be reliably restarted at the pushed instruction pointer.
•
EIPV (error IP valid) flag, bit 1 — Indicates (when set) that the instruction pointed to by the instruction
pointer pushed onto the stack when the machine-check exception is generated is directly associated with the
error. When this flag is cleared, the instruction pointed to may not be associated with the error.
•
MCIP (machine check in progress) flag, bit 2 — Indicates (when set) that a machine-check exception was
generated. Software can set or clear this flag. The occurrence of a second Machine-Check Event while MCIP is
set will cause the processor to enter a shutdown state. For information on processor behavior in the shutdown
state, please refer to the description in Chapter 6, “Interrupt and Exception Handling”: “Interrupt 8—Double
Fault Exception (#DF)”.
•
LMCE_S (local machine check exception signaled), bit 3 — Indicates (when set) that a local machinecheck exception was generated. This indicates that the current machine-check event was delivered to only this
logical processor.
Bits 63:04 in IA32_MCG_STATUS are reserved. An attempt to write to IA32_MCG_STATUS with any value other
than 0 would result in #GP.
15.3.1.3
IA32_MCG_CTL MSR
The IA32_MCG_CTL MSR is present if the capability flag MCG_CTL_P is set in the IA32_MCG_CAP MSR.
IA32_MCG_CTL controls the reporting of machine-check exceptions. If present, writing 1s to this register enables
machine-check features and writing all 0s disables machine-check features. All other values are undefined and/or
implementation specific.
15-4 Vol. 3B
MACHINE-CHECK ARCHITECTURE
15.3.1.4
IA32_MCG_EXT_CTL MSR
The IA32_MCG_EXT_CTL MSR is present if the capability flag MCG_LMCE_P is set in the IA32_MCG_CAP MSR.
IA32_MCG_EXT_CTL.LMCE_EN (bit 0) allows the processor to signal some MCEs to only a single logical processor
in the system.
If MCG_LMCE_P is not set in IA32_MCG_CAP, or platform software has not enabled LMCE by setting
IA32_FEATURE_CONTROL.LMCE_ON (bit 20), any attempt to write or read IA32_MCG_EXT_CTL will result in #GP.
The IA32_MCG_EXT_CTL MSR is cleared on RESET.
Figure 15-4 shows the layout of the IA32_MCG_EXT_CTL register
63
1 0
Reserved
LMCE_EN - system software control to enable/disable LMCE
Figure 15-4. IA32_MCG_EXT_CTL Register
where
•
LMCE_EN (local machine check exception enable) flag, bit 0 - System software sets this to allow
hardware to signal some MCEs to only a single logical processor. System software can set LMCE_EN only if the
platform software has configured IA32_FEATURE_CONTROL as described in Section 15.3.1.5.
15.3.1.5
Enabling Local Machine Check
The intended usage of LMCE requires proper configuration by both platform software and system software. Platform software can turn LMCE on by setting bit 20 (LMCE_ON) in IA32_FEATURE_CONTROL MSR (MSR address
3AH).
System software must ensure that both IA32_FEATURE_CONTROL.Lock (bit 0)and
IA32_FEATURE_CONTROL.LMCE_ON (bit 20) are set before attempting to set IA32_MCG_EXT_CTL.LMCE_EN (bit
0). When system software has enabled LMCE, then hardware will determine if a particular error can be delivered
only to a single logical processor. Software should make no assumptions about the type of error that hardware can
choose to deliver as LMCE. The severity and override rules stay the same as described in Table 15-7 to determine
the recovery actions.
15.3.2
Error-Reporting Register Banks
Each error-reporting register bank can contain the IA32_MCi_CTL, IA32_MCi_STATUS, IA32_MCi_ADDR, and
IA32_MCi_MISC MSRs. The number of reporting banks is indicated by bits [7:0] of IA32_MCG_CAP MSR (address
0179H). The first error-reporting register (IA32_MC0_CTL) always starts at address 400H.
See Chapter 35, “Model-Specific Registers (MSRs),” for addresses of the error-reporting registers in the Pentium 4,
Intel Atom, and Intel Xeon processors; and for addresses of the error-reporting registers P6 family processors.
15.3.2.1
IA32_MCi_CTL MSRs
The IA32_MCi_CTL MSR controls signaling of #MC for errors produced by a particular hardware unit (or group of
hardware units). Each of the 64 flags (EEj) represents a potential error. Setting an EEj flag enables signaling #MC
of the associated error and clearing it disables signaling of the error. Error logging happens regardless of the
setting of these bits. The processor drops writes to bits that are not implemented. Figure 15-5 shows the bit fields
of IA32_MCi_CTL.
Vol. 3B 15-5
MACHINE-CHECK ARCHITECTURE
63 62 61
E
E
6
3
E
E
6
2
.....
E
E
6
1
3 2 1 0
E
E
0
2
E
E
0
1
E
E
0
0
EEj—Error reporting enable flag
(where j is 00 through 63)
Figure 15-5. IA32_MCi_CTL Register
NOTE
For P6 family processors, processors based on Intel Core microarchitecture (excluding those on
which on which CPUID reports DisplayFamily_DisplayModel as 06H_1AH and onward): the
operating system or executive software must not modify the contents of the IA32_MC0_CTL MSR.
This MSR is internally aliased to the EBL_CR_POWERON MSR and controls platform-specific error
handling features. System specific firmware (the BIOS) is responsible for the appropriate initialization of the IA32_MC0_CTL MSR. P6 family processors only allow the writing of all 1s or all 0s to
the IA32_MCi_CTL MSR.
15.3.2.2
IA32_MCi_STATUS MSRS
Each IA32_MCi_STATUS MSR contains information related to a machine-check error if its VAL (valid) flag is set (see
Figure 15-6). Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing
1s to them causes a general-protection exception.
NOTE
Figure 15-6 depicts the IA32_MCi_STATUS MSR when IA32_MCG_CAP[24] = 1,
IA32_MCG_CAP[11] = 1 and IA32_MCG_CAP[10] = 1. When IA32_MCG_CAP[24] = 0 and
IA32_MCG_CAP[11] = 1, bits 56:55 is reserved and bits 54:53 for threshold-based error reporting.
When IA32_MCG_CAP[11] = 0, bits 56:53 are part of the “Other Information” field. The use of bits
54:53 for threshold-based error reporting began with Intel Core Duo processors, and is currently
used for cache memory. See Section 15.4, “Enhanced Cache Error reporting,” for more information.
When IA32_MCG_CAP[10] = 0, bits 52:38 are part of the “Other Information” field. The use of bits
52:38 for corrected MC error count is introduced with Intel 64 processor on which CPUID reports
DisplayFamily_DisplayModel as 06H_1AH.
Where:
•
MCA (machine-check architecture) error code field, bits 15:0 — Specifies the machine-check architecture-defined error code for the machine-check error condition detected. The machine-check architecturedefined error codes are guaranteed to be the same for all IA-32 processors that implement the machine-check
architecture. See Section 15.9, “Interpreting the MCA Error Codes,” and Chapter 16, “Interpreting MachineCheck Error Codes”, for information on machine-check error codes.
•
Model-specific error code field, bits 31:16 — Specifies the model-specific error code that uniquely
identifies the machine-check error condition detected. The model-specific error codes may differ among IA-32
processors for the same machine-check error condition. See Chapter 16, “Interpreting Machine-Check Error
Codes”for information on model-specific error codes.
•
Reserved, Error Status, and Other Information fields, bits 56:32 —
•
If IA32_MCG_CAP.MCG_EMC_P[bit 25] is 0, bits 37:32 contain “Other Information” that is implementation-specific and is not part of the machine-check architecture.
•
If IA32_MCG_CAP.MCG_EMC_P is 1, “Other Information” is in bits 36:32. If bit 37 is 0, system firmware
has not changed the contents of IA32_MCi_STATUS. If bit 37 is 1, system firmware may have edited the
contents of IA32_MCi_STATUS.
•
If IA32_MCG_CAP.MCG_CMCI_P[bit 10] is 0, bits 52:38 also contain “Other Information” (in the same
sense as bits 37:32).
15-6 Vol. 3B
MACHINE-CHECK ARCHITECTURE
63 62 61 60 59 58 57 56 55 54 53 52
V O U E
A V C N
L E
R
P S A
R
C
C
Corrected Error
Count
38 37 36
32 31
Other
Info
16 15
MSCOD Model
Specific Error Code
0
MCA Error Code
Firmware updated error status indicator (37)*
Threshold-based error status (54:53)**
AR — Recovery action required for UCR error (55)***
S — Signaling an uncorrected recoverable (UCR) error (56)***
PCC — Processor context corrupted (57)
ADDRV — MCi_ADDR register valid (58)
MISCV — MCi_MISC register valid (59)
EN — Error reporting enabled (60)
UC — Uncorrected error (61)
OVER — Error overflow (62)
VAL — MCi_STATUS register valid (63)
* When IA32_MCG_CAP[25] (MCG_EMC_P) is set, bit 37 is not part of “Other Information”.
** When IA32_MCG_CAP[11] (MCG_TES_P) is not set, these bits are model-specific
(part of “Other Information”).
*** When IA32_MCG_CAP[11] or IA32_MCG_CAP[24] are not set, these bits are reserved, or
model-specific (part of “Other Information”).
Figure 15-6. IA32_MCi_STATUS Register
•
If IA32_MCG_CAP[10] is 1, bits 52:38 are architectural (not model-specific). In this case, bits 52:38
reports the value of a 15 bit counter that increments each time a corrected error is observed by the MCA
recording bank. This count value will continue to increment until cleared by software. The most
significant bit, 52, is a sticky count overflow bit.
•
•
If IA32_MCG_CAP[11] is 0, bits 56:53 also contain “Other Information” (in the same sense).
If IA32_MCG_CAP[11] is 1, bits 56:53 are architectural (not model-specific). In this case, bits 56:53
have the following functionality:
•
•
•
If IA32_MCG_CAP[24] is 0, bits 56:55 are reserved.
If IA32_MCG_CAP[24] is 1, bits 56:55 are defined as follows:
S (Signaling) flag, bit 56 - Signals the reporting of UCR errors in this MC bank. See Section 15.6.2
for additional detail.
•
AR (Action Required) flag, bit 55 - Indicates (when set) that MCA error code specific recovery
action must be performed by system software at the time this error was signaled. See Section
15.6.2 for additional detail.
•
•
If the UC bit (Figure 15-6) is 1, bits 54:53 are undefined.
If the UC bit (Figure 15-6) is 0, bits 54:53 indicate the status of the hardware structure that
reported the threshold-based error. See Table 15-1.
Table 15-1. Bits 54:53 in IA32_MCi_STATUS MSRs when IA32_MCG_CAP[11] = 1 and UC = 0
Bits 54:53
Meaning
00
No tracking - No hardware status tracking is provided for the structure reporting this event.
01
Green - Status tracking is provided for the structure posting the event; the current status is green (below threshold).
For more information, see Section 15.4, “Enhanced Cache Error reporting”.
10
Yellow - Status tracking is provided for the structure posting the event; the current status is yellow (above threshold).
For more information, see Section 15.4, “Enhanced Cache Error reporting”.
11
Reserved
Vol. 3B 15-7
MACHINE-CHECK ARCHITECTURE
•
PCC (processor context corrupt) flag, bit 57 — Indicates (when set) that the state of the processor might
have been corrupted by the error condition detected and that reliable restarting of the processor may not be
possible. When clear, this flag indicates that the error did not affect the processor’s state, and software may be
able to restart. When system software supports recovery, consult Section 15.10.4, “Machine-Check Software
Handler Guidelines for Error Recovery” for additional rules that apply.
•
ADDRV (IA32_MCi_ADDR register valid) flag, bit 58 — Indicates (when set) that the IA32_MCi_ADDR
register contains the address where the error occurred (see Section 15.3.2.3, “IA32_MCi_ADDR MSRs”). When
clear, this flag indicates that the IA32_MCi_ADDR register is either not implemented or does not contain the
address where the error occurred. Do not read these registers if they are not implemented in the processor.
•
MISCV (IA32_MCi_MISC register valid) flag, bit 59 — Indicates (when set) that the IA32_MCi_MISC
register contains additional information regarding the error. When clear, this flag indicates that the
IA32_MCi_MISC register is either not implemented or does not contain additional information regarding the
error. Do not read these registers if they are not implemented in the processor.
•
EN (error enabled) flag, bit 60 — Indicates (when set) that the error was enabled by the associated EEj bit
of the IA32_MCi_CTL register.
•
UC (error uncorrected) flag, bit 61 — Indicates (when set) that the processor did not or was not able to
correct the error condition. When clear, this flag indicates that the processor was able to correct the error
condition.
•
OVER (machine check overflow) flag, bit 62 — Indicates (when set) that a machine-check error occurred
while the results of a previous error were still in the error-reporting register bank (that is, the VAL bit was
already set in the IA32_MCi_STATUS register). The processor sets the OVER flag and software is responsible for
clearing it. In general, enabled errors are written over disabled errors, and uncorrected errors are written over
corrected errors. Uncorrected errors are not written over previous valid uncorrected errors. When
MCG_CMCI_P is set, corrected errors may not set the OVER flag. Software can rely on corrected error count in
IA32_MCi_Status[52:38] to determine if any additional corrected errors may have occurred. For more information, see Section 15.3.2.2.1, “Overwrite Rules for Machine Check Overflow”.
•
VAL (IA32_MCi_STATUS register valid) flag, bit 63 — Indicates (when set) that the information within the
IA32_MCi_STATUS register is valid. When this flag is set, the processor follows the rules given for the OVER flag
in the IA32_MCi_STATUS register when overwriting previously valid entries. The processor sets the VAL flag
and software is responsible for clearing it.
15.3.2.2.1 Overwrite Rules for Machine Check Overflow
Table 15-2 shows the overwrite rules for how to treat a second event if the cache has already posted an event to
the MC bank – that is, what to do if the valid bit for an MC bank already is set to 1. When more than one structure
posts events in a given bank, these rules specify whether a new event will overwrite a previous posting or not.
These rules define a priority for uncorrected (highest priority), yellow, and green/unmonitored (lowest priority)
status.
In Table 15-2, the values in the two left-most columns are IA32_MCi_STATUS[54:53].
Table 15-2. Overwrite Rules for Enabled Errors
First Event
Second Event
UC bit
Color
MCA Info
00/green
00/green
0
00/green
either
00/green
yellow
0
yellow
second error
yellow
00/green
0
yellow
first error
yellow
yellow
0
yellow
either
00/green/yellow
UC
1
undefined
second
UC
00/green/yellow
1
undefined
first
If a second event overwrites a previously posted event, the information (as guarded by individual valid bits) in the
MCi bank is entirely from the second event. Similarly, if a first event is retained, all of the information previously
posted for that event is retained. In general, when the logged error or the recent error is a corrected error, the
OVER bit (MCi_Status[62]) may be set to indicate an overflow. When MCG_CMCI_P is set in IA32_MCG_CAP,
system software should consult IA32_MCi_STATUS[52:38] to determine if additional corrected errors may have
15-8 Vol. 3B
MACHINE-CHECK ARCHITECTURE
occurred. Software may re-read IA32_MCi_STATUS, IA32_MCi_ADDR and IA32_MCi_MISC appropriately to ensure
data collected represent the last error logged.
After software polls a posting and clears the register, the valid bit is no longer set and therefore the meaning of the
rest of the bits, including the yellow/green/00 status field in bits 54:53, is undefined. The yellow/green indication
will only be posted for events associated with monitored structures – otherwise the unmonitored (00) code will be
posted in IA32_MCi_STATUS[54:53].
15.3.2.3
IA32_MCi_ADDR MSRs
The IA32_MCi_ADDR MSR contains the address of the code or data memory location that produced the machinecheck error if the ADDRV flag in the IA32_MCi_STATUS register is set (see Section 15-7, “IA32_MCi_ADDR MSR”).
The IA32_MCi_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MCi_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will
cause a general protection exception.
The address returned is an offset into a segment, linear address, or physical address. This depends on the error
encountered. When these registers are implemented, these registers can be cleared by explicitly writing 0s to
these registers. Writing 1s to these registers will cause a general-protection exception. See Figure 15-7.
Processor Without Support For Intel 64 Architecture
63
0
36 35
Address
Reserved
Processor With Support for Intel 64 Architecture
63
0
Address*
* Useful bits in this field depend on the address methodology in use when the
the register state is saved.
Figure 15-7. IA32_MCi_ADDR MSR
15.3.2.4
IA32_MCi_MISC MSRs
The IA32_MCi_MISC MSR contains additional information describing the machine-check error if the MISCV flag in
the IA32_MCi_STATUS register is set. The IA32_MCi_MISC_MSR is either not implemented or does not contain
additional information if the MISCV flag in the IA32_MCi_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general protection exception.
When implemented in a processor, these registers can be cleared by explicitly writing all 0s to them; writing 1s to
them causes a general-protection exception to be generated. This register is not implemented in any of the errorreporting register banks for the P6 or Intel Atom family processors.
If both MISCV and IA32_MCG_CAP[24] are set, the IA32_MCi_MISC_MSR is defined according to Figure 15-8 to
support software recovery of uncorrected errors (see Section 15.6):
Vol. 3B 15-9
MACHINE-CHECK ARCHITECTURE
9 8
63
6 5
0
Model Specific Information
Address Mode
Recoverable Address LSB
Figure 15-8. UCR Support in IA32_MCi_MISC Register
•
Recoverable Address LSB (bits 5:0): The lowest valid recoverable address bit. Indicates the position of the least
significant bit (LSB) of the recoverable error address. For example, if the processor logs bits [43:9] of the
address, the LSB sub-field in IA32_MCi_MISC is 01001b (9 decimal). For this example, bits [8:0] of the
recoverable error address in IA32_MCi_ADDR should be ignored.
•
Address Mode (bits 8:6): Address mode for the address logged in IA32_MCi_ADDR. The supported address
modes are given in Table 15-3.
Table 15-3. Address Mode in IA32_MCi_MISC[8:6]
IA32_MCi_MISC[8:6] Encoding
000
Segment Offset
001
Linear Address
010
Physical Address
011
Memory Address
100 to 110
111
•
Definition
Reserved
Generic
Model Specific Information (bits 63:9): Not architecturally defined.
15.3.2.5
IA32_MCi_CTL2 MSRs
The IA32_MCi_CTL2 MSR provides the programming interface to use corrected MC error signaling capability that is
indicated by IA32_MCG_CAP[10] = 1. Software must check for the presence of IA32_MCi_CTL2 on a per-bank
basis.
When IA32_MCG_CAP[10] = 1, the IA32_MCi_CTL2 MSR for each bank exists, i.e. reads and writes to these MSR
are supported. However, signaling interface for corrected MC errors may not be supported in all banks.
The layout of IA32_MCi_CTL2 is shown in Figure 15-9:
63
31 30 29
Reserved
15 14
Reserved
CMCI_EN—Enable/disable CMCI
Corrected error count threshold
Figure 15-9. IA32_MCi_CTL2 Register
15-10 Vol. 3B
0
MACHINE-CHECK ARCHITECTURE
•
Corrected error count threshold, bits 14:0 — Software must initialize this field. The value is compared with
the corrected error count field in IA32_MCi_STATUS, bits 38 through 52. An overflow event is signaled to the
CMCI LVT entry (see Table 10-1) in the APIC when the count value equals the threshold value. The new LVT
entry in the APIC is at 02F0H offset from the APIC_BASE. If CMCI interface is not supported for a particular
bank (but IA32_MCG_CAP[10] = 1), this field will always read 0.
•
CMCI_EN (Corrected error interrupt enable/disable/indicator), bits 30 — Software sets this bit to
enable the generation of corrected machine-check error interrupt (CMCI). If CMCI interface is not supported for
a particular bank (but IA32_MCG_CAP[10] = 1), this bit is writeable but will always return 0 for that bank. This
bit also indicates CMCI is supported or not supported in the corresponding bank. See Section 15.5 for details of
software detection of CMCI facility.
Some microarchitectural sub-systems that are the source of corrected MC errors may be shared by more than one
logical processors. Consequently, the facilities for reporting MC errors and controlling mechanisms may be shared
by more than one logical processors. For example, the IA32_MCi_CTL2 MSR is shared between logical processors
sharing a processor core. Software is responsible to program IA32_MCi_CTL2 MSR in a consistent manner with
CMCI delivery and usage.
After processor reset, IA32_MCi_CTL2 MSRs are zero’ed.
15.3.2.6
IA32_MCG Extended Machine Check State MSRs
The Pentium 4 and Intel Xeon processors implement a variable number of extended machine-check state MSRs.
The MCG_EXT_P flag in the IA32_MCG_CAP MSR indicates the presence of these extended registers, and the
MCG_EXT_CNT field indicates the number of these registers actually implemented. See Section 15.3.1.1,
“IA32_MCG_CAP MSR.” Also see Table 15-4.
Table 15-4. Extended Machine Check State MSRs
in Processors Without Support for Intel 64 Architecture
MSR
Address
Description
IA32_MCG_EAX
180H
Contains state of the EAX register at the time of the machine-check error.
IA32_MCG_EBX
181H
Contains state of the EBX register at the time of the machine-check error.
IA32_MCG_ECX
182H
Contains state of the ECX register at the time of the machine-check error.
IA32_MCG_EDX
183H
Contains state of the EDX register at the time of the machine-check error.
IA32_MCG_ESI
184H
Contains state of the ESI register at the time of the machine-check error.
IA32_MCG_EDI
185H
Contains state of the EDI register at the time of the machine-check error.
IA32_MCG_EBP
186H
Contains state of the EBP register at the time of the machine-check error.
IA32_MCG_ESP
187H
Contains state of the ESP register at the time of the machine-check error.
IA32_MCG_EFLAGS
188H
Contains state of the EFLAGS register at the time of the machine-check error.
IA32_MCG_EIP
189H
Contains state of the EIP register at the time of the machine-check error.
IA32_MCG_MISC
18AH
When set, indicates that a page assist or page fault occurred during DS normal
operation.
In processors with support for Intel 64 architecture, 64-bit machine check state MSRs are aliased to the legacy
MSRs. In addition, there may be registers beyond IA32_MCG_MISC. These may include up to five reserved MSRs
(IA32_MCG_RESERVED[1:5]) and save-state MSRs for registers introduced in 64-bit mode. See Table 15-5.
Table 15-5. Extended Machine Check State MSRs
In Processors With Support For Intel 64 Architecture
MSR
Address
Description
IA32_MCG_RAX
180H
Contains state of the RAX register at the time of the machine-check error.
IA32_MCG_RBX
181H
Contains state of the RBX register at the time of the machine-check error.
Vol. 3B 15-11
MACHINE-CHECK ARCHITECTURE
Table 15-5. Extended Machine Check State MSRs
In Processors With Support For Intel 64 Architecture (Contd.)
MSR
Address
Description
IA32_MCG_RCX
182H
Contains state of the RCX register at the time of the machine-check error.
IA32_MCG_RDX
183H
Contains state of the RDX register at the time of the machine-check error.
IA32_MCG_RSI
184H
Contains state of the RSI register at the time of the machine-check error.
IA32_MCG_RDI
185H
Contains state of the RDI register at the time of the machine-check error.
IA32_MCG_RBP
186H
Contains state of the RBP register at the time of the machine-check error.
IA32_MCG_RSP
187H
Contains state of the RSP register at the time of the machine-check error.
IA32_MCG_RFLAGS
188H
Contains state of the RFLAGS register at the time of the machine-check error.
IA32_MCG_RIP
189H
Contains state of the RIP register at the time of the machine-check error.
IA32_MCG_MISC
18AH
When set, indicates that a page assist or page fault occurred during DS normal
operation.
IA32_MCG_
RSERVED[1:5]
18BH18FH
These registers, if present, are reserved.
IA32_MCG_R8
190H
Contains state of the R8 register at the time of the machine-check error.
IA32_MCG_R9
191H
Contains state of the R9 register at the time of the machine-check error.
IA32_MCG_R10
192H
Contains state of the R10 register at the time of the machine-check error.
IA32_MCG_R11
193H
Contains state of the R11 register at the time of the machine-check error.
IA32_MCG_R12
194H
Contains state of the R12 register at the time of the machine-check error.
IA32_MCG_R13
195H
Contains state of the R13 register at the time of the machine-check error.
IA32_MCG_R14
196H
Contains state of the R14 register at the time of the machine-check error.
IA32_MCG_R15
197H
Contains state of the R15 register at the time of the machine-check error.
When a machine-check error is detected on a Pentium 4 or Intel Xeon processor, the processor saves the state of
the general-purpose registers, the R/EFLAGS register, and the R/EIP in these extended machine-check state MSRs.
This information can be used by a debugger to analyze the error.
These registers are read/write to zero registers. This means software can read them; but if software writes to
them, only all zeros is allowed. If software attempts to write a non-zero value into one of these registers, a generalprotection (#GP) exception is generated. These registers are cleared on a hardware reset (power-up or RESET),
but maintain their contents following a soft reset (INIT reset).
15.3.3
Mapping of the Pentium Processor Machine-Check Errors
to the Machine-Check Architecture
The Pentium processor reports machine-check errors using two registers: P5_MC_TYPE and P5_MC_ADDR. The
Pentium 4, Intel Xeon, Intel Atom, and P6 family processors map these registers to the IA32_MCi_STATUS and
IA32_MCi_ADDR in the error-reporting register bank. This bank reports on the same type of external bus errors
reported in P5_MC_TYPE and P5_MC_ADDR.
The information in these registers can then be accessed in two ways:
•
By reading the IA32_MCi_STATUS and IA32_MCi_ADDR registers as part of a general machine-check exception
handler written for Pentium 4, Intel Atom and P6 family processors.
•
By reading the P5_MC_TYPE and P5_MC_ADDR registers using the RDMSR instruction.
The second capability permits a machine-check exception handler written to run on a Pentium processor to be run
on a Pentium 4, Intel Xeon, Intel Atom, or P6 family processor. There is a limitation in that information returned by
the Pentium 4, Intel Xeon, Intel Atom, and P6 family processors is encoded differently than information returned
by the Pentium processor. To run a Pentium processor machine-check exception handler on a Pentium 4, Intel
Xeon, Intel Atom, or P6 family processor; the handler must be written to interpret P5_MC_TYPE encodings
correctly.
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MACHINE-CHECK ARCHITECTURE
15.4
ENHANCED CACHE ERROR REPORTING
Starting with Intel Core Duo processors, cache error reporting was enhanced. In earlier Intel processors, cache
status was based on the number of correction events that occurred in a cache. In the new paradigm, called
“threshold-based error status”, cache status is based on the number of lines (ECC blocks) in a cache that incur
repeated corrections. The threshold is chosen by Intel, based on various factors. If a processor supports thresholdbased error status, it sets IA32_MCG_CAP[11] (MCG_TES_P) to 1; if not, to 0.
A processor that supports enhanced cache error reporting contains hardware that tracks the operating status of
certain caches and provides an indicator of their “health”. The hardware reports a “green” status when the number
of lines that incur repeated corrections is at or below a pre-defined threshold, and a “yellow” status when the
number of affected lines exceeds the threshold. Yellow status means that the cache reporting the event is operating correctly, but you should schedule the system for servicing within a few weeks.
Intel recommends that you rely on this mechanism for structures supported by threshold-base error reporting.
The CPU/system/platform response to a yellow event should be less severe than its response to an uncorrected
error. An uncorrected error means that a serious error has actually occurred, whereas the yellow condition is a
warning that the number of affected lines has exceeded the threshold but is not, in itself, a serious event: the error
was corrected and system state was not compromised.
The green/yellow status indicator is not a foolproof early warning for an uncorrected error resulting from the failure
of two bits in the same ECC block. Such a failure can occur and cause an uncorrected error before the yellow
threshold is reached. However, the chance of an uncorrected error increases as the number of affected lines
increases.
15.5
CORRECTED MACHINE CHECK ERROR INTERRUPT
Corrected machine-check error interrupt (CMCI) is an architectural enhancement to the machine-check architecture. It provides capabilities beyond those of threshold-based error reporting (Section 15.4). With threshold-based
error reporting, software is limited to use periodic polling to query the status of hardware corrected MC errors.
CMCI provides a signaling mechanism to deliver a local interrupt based on threshold values that software can
program using the IA32_MCi_CTL2 MSRs.
CMCI is disabled by default. System software is required to enable CMCI for each IA32_MCi bank that support the
reporting of hardware corrected errors if IA32_MCG_CAP[10] = 1.
System software use IA32_MCi_CTL2 MSR to enable/disable the CMCI capability for each bank and program
threshold values into IA32_MCi_CTL2 MSR. CMCI is not affected by the CR4.MCE bit, and it is not affected by the
IA32_MCi_CTL MSRs.
To detect the existence of thresholding for a given bank, software writes only bits 14:0 with the threshold value. If
the bits persist, then thresholding is available (and CMCI is available). If the bits are all 0's, then no thresholding
exists. To detect that CMCI signaling exists, software writes a 1 to bit 30 of the MCi_CTL2 register. Upon subsequent read, if bit 30 = 0, no CMCI is available for this bank and no corrected or UCNA errors will be reported on this
bank. If bit 30 = 1, then CMCI is available and enabled.
15.5.1
CMCI Local APIC Interface
The operation of CMCI is depicted in Figure 15-10.
Vol. 3B 15-13
MACHINE-CHECK ARCHITECTURE
63
Software write 1 to enable
31 30 29
MCi_CTL2
Error threshold
?=
53 52
MCi_STATUS
0
14
Count overflow threshold -> CMCI LVT in local APIC
38 37
0
APIC_BASE + 2F0H
Error count
Figure 15-10. CMCI Behavior
CMCI interrupt delivery is configured by writing to the LVT CMCI register entry in the local APIC register space at
default address of APIC_BASE + 2F0H. A CMCI interrupt can be delivered to more than one logical processors if
multiple logical processors are affected by the associated MC errors. For example, if a corrected bit error in a cache
shared by two logical processors caused a CMCI, the interrupt will be delivered to both logical processors sharing
that microarchitectural sub-system. Similarly, package level errors may cause CMCI to be delivered to all logical
processors within the package. However, system level errors will not be handled by CMCI.
See Section 10.5.1, “Local Vector Table” for details regarding the LVT CMCI register.
15.5.2
System Software Recommendation for Managing CMCI and Machine Check Resources
System software must enable and manage CMCI, set up interrupt handlers to service CMCI interrupts delivered to
affected logical processors, program CMCI LVT entry, and query machine check banks that are shared by more than
one logical processors.
This section describes techniques system software can implement to manage CMCI initialization, service CMCI
interrupts in a efficient manner to minimize contentions to access shared MSR resources.
15.5.2.1
CMCI Initialization
Although a CMCI interrupt may be delivered to more than one logical processors depending on the nature of the
corrected MC error, only one instance of the interrupt service routine needs to perform the necessary service and
make queries to the machine-check banks. The following steps describes a technique that limits the amount of
work the system has to do in response to a CMCI.
•
To provide maximum flexibility, system software should define per-thread data structure for each logical
processor to allow equal-opportunity and efficient response to interrupt delivery. Specifically, the per-thread
data structure should include a set of per-bank fields to track which machine check bank it needs to access in
response to a delivered CMCI interrupt. The number of banks that needs to be tracked is determined by
IA32_MCG_CAP[7:0].
•
Initialization of per-thread data structure. The initialization of per-thread data structure must be done serially
on each logical processor in the system. The sequencing order to start the per-thread initialization between
different logical processor is arbitrary. But it must observe the following specific detail to satisfy the shared
nature of specific MSR resources:
a. Each thread initializes its data structure to indicate that it does not own any MC bank registers.
b. Each thread examines IA32_MCi_CTL2[30] indicator for each bank to determine if another thread has
already claimed ownership of that bank.
•
If IA32_MCi_CTL2[30] had been set by another thread. This thread can not own bank i and should
proceed to step b. and examine the next machine check bank until all of the machine check banks are
exhausted.
15-14 Vol. 3B
MACHINE-CHECK ARCHITECTURE
•
c.
•
If IA32_MCi_CTL2[30] = 0, proceed to step c.
Check whether writing a 1 into IA32_MCi_CTL2[30] can return with 1 on a subsequent read to determine
this bank can support CMCI.
•
If IA32_MCi_CTL2[30] = 0, this bank does not support CMCI. This thread can not own bank i and should
proceed to step b. and examine the next machine check bank until all of the machine check banks are
exhausted.
•
If IA32_MCi_CTL2[30] = 1, modify the per-thread data structure to indicate this thread claims
ownership to the MC bank; proceed to initialize the error threshold count (bits 15:0) of that bank as
described in Chapter 15, “CMCI Threshold Management”. Then proceed to step b. and examine the next
machine check bank until all of the machine check banks are exhausted.
After the thread has examined all of the machine check banks, it sees if it owns any MC banks to service CMCI.
If any bank has been claimed by this thread:
— Ensure that the CMCI interrupt handler has been set up as described in Chapter 15, “CMCI Interrupt
Handler”.
— Initialize the CMCI LVT entry, as described in Section 15.5.1, “CMCI Local APIC Interface”.
— Log and clear all of IA32_MCi_Status registers for the banks that this thread owns. This will allow new
errors to be logged.
15.5.2.2
CMCI Threshold Management
The Corrected MC error threshold field, IA32_MCi_CTL2[15:0], is architecturally defined. Specifically, all these bits
are writable by software, but different processor implementations may choose to implement less than 15 bits as
threshold for the overflow comparison with IA32_MCi_STATUS[52:38]. The following describes techniques that
software can manage CMCI threshold to be compatible with changes in implementation characteristics:
•
Software can set the initial threshold value to 1 by writing 1 to IA32_MCi_CTL2[15:0]. This will cause overflow
condition on every corrected MC error and generates a CMCI interrupt.
•
To increase the threshold and reduce the frequency of CMCI servicing:
a. Find the maximum threshold value a given processor implementation supports. The steps are:
•
•
Write 7FFFH to IA32_MCi_CTL2[15:0],
Read back IA32_MCi_CTL2[15:0], the lower 15 bits (14:0) is the maximum threshold supported by the
processor.
b. Increase the threshold to a value below the maximum value discovered using step a.
15.5.2.3
CMCI Interrupt Handler
The following describes techniques system software may consider to implement a CMCI service routine:
•
The service routine examines its private per-thread data structure to check which set of MC banks it has
ownership. If the thread does not have ownership of a given MC bank, proceed to the next MC bank. Ownership
is determined at initialization time which is described in Section [Cross Reference to 14.5.2.1].
If the thread had claimed ownership to an MC bank, this technique will allow each logical processors to handle
corrected MC errors independently and requires no synchronization to access shared MSR resources. Consult
Example 15-5 for guidelines on logging when processing CMCI.
15.6
RECOVERY OF UNCORRECTED RECOVERABLE (UCR) ERRORS
Recovery of uncorrected recoverable machine check errors is an enhancement in machine-check architecture. The
first processor that supports this feature is 45 nm Intel 64 processor on which CPUID reports
DisplayFamily_DisplayModel as 06H_2EH (see CPUID instruction in Chapter 3, “Instruction Set Reference, A-L” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). This allow system software to
perform recovery action on certain class of uncorrected errors and continue execution.
Vol. 3B 15-15
MACHINE-CHECK ARCHITECTURE
15.6.1
Detection of Software Error Recovery Support
Software must use bit 24 of IA32_MCG_CAP (MCG_SER_P) to detect the presence of software error recovery
support (see Figure 15-2). When IA32_MCG_CAP[24] is set, this indicates that the processor supports software
error recovery. When this bit is clear, this indicates that there is no support for error recovery from the processor
and the primary responsibility of the machine check handler is logging the machine check error information and
shutting down the system.
The new class of architectural MCA errors from which system software can attempt recovery is called Uncorrected
Recoverable (UCR) Errors. UCR errors are uncorrected errors that have been detected and signaled but have not
corrupted the processor context. For certain UCR errors, this means that once system software has performed a
certain recovery action, it is possible to continue execution on this processor. UCR error reporting provides an error
containment mechanism for data poisoning. The machine check handler will use the error log information from the
error reporting registers to analyze and implement specific error recovery actions for UCR errors.
15.6.2
UCR Error Reporting and Logging
IA32_MCi_STATUS MSR is used for reporting UCR errors and existing corrected or uncorrected errors. The definitions of IA32_MCi_STATUS, including bit fields to identify UCR errors, is shown in Figure 15-6. UCR errors can be
signaled through either the corrected machine check interrupt (CMCI) or machine check exception (MCE) path
depending on the type of the UCR error.
When IA32_MCG_CAP[24] is set, a UCR error is indicated by the following bit settings in the IA32_MCi_STATUS
register:
•
•
•
Valid (bit 63) = 1
UC (bit 61) = 1
PCC (bit 57) = 0
Additional information from the IA32_MCi_MISC and the IA32_MCi_ADDR registers for the UCR error are available
when the ADDRV and the MISCV flags in the IA32_MCi_STATUS register are set (see Section 15.3.2.4). The MCA
error code field of the IA32_MCi_STATUS register indicates the type of UCR error. System software can interpret
the MCA error code field to analyze and identify the necessary recovery action for the given UCR error.
In addition, the IA32_MCi_STATUS register bit fields, bits 56:55, are defined (see Figure 15-6) to provide additional information to help system software to properly identify the necessary recovery action for the UCR error:
•
S (Signaling) flag, bit 56 - Indicates (when set) that a machine check exception was generated for the UCR
error reported in this MC bank and system software needs to check the AR flag and the MCA error code fields in
the IA32_MCi_STATUS register to identify the necessary recovery action for this error. When the S flag in the
IA32_MCi_STATUS register is clear, this UCR error was not signaled via a machine check exception and instead
was reported as a corrected machine check (CMC). System software is not required to take any recovery action
when the S flag in the IA32_MCi_STATUS register is clear.
•
AR (Action Required) flag, bit 55 - Indicates (when set) that MCA error code specific recovery action must be
performed by system software at the time this error was signaled. This recovery action must be completed
successfully before any additional work is scheduled for this processor. When the RIPV flag in the
IA32_MCG_STATUS is clear, an alternative execution stream needs to be provided; when the MCA error code
specific recovery specific recovery action cannot be successfully completed, system software must shut down
the system. When the AR flag in the IA32_MCi_STATUS register is clear, system software may still take MCA
error code specific recovery action but this is optional; system software can safely resume program execution
at the instruction pointer saved on the stack from the machine check exception when the RIPV flag in the
IA32_MCG_STATUS register is set.
Both the S and the AR flags in the IA32_MCi_STATUS register are defined to be sticky bits, which mean that once
set, the processor does not clear them. Only software and good power-on reset can clear the S and the AR-flags.
Both the S and the AR flags are only set when the processor reports the UCR errors (MCG_CAP[24] is set).
15.6.3
UCR Error Classification
With the S and AR flag encoding in the IA32_MCi_STATUS register, UCR errors can be classified as:
15-16 Vol. 3B
MACHINE-CHECK ARCHITECTURE
•
Uncorrected no action required (UCNA) - is a UCR error that is not signaled via a machine check exception and,
instead, is reported to system software as a corrected machine check error. UCNA errors indicate that some
data in the system is corrupted, but the data has not been consumed and the processor state is valid and you
may continue execution on this processor. UCNA errors require no action from system software to continue
execution. A UNCA error is indicated with UC=1, PCC=0, S=0 and AR=0 in the IA32_MCi_STATUS register.
•
Software recoverable action optional (SRAO) - a UCR error is signaled either via a machine check exception or
CMCI. System software recovery action is optional and not required to continue execution from this machine
check exception. SRAO errors indicate that some data in the system is corrupt, but the data has not been
consumed and the processor state is valid. SRAO errors provide the additional error information for system
software to perform a recovery action. An SRAO error when signaled as a machine check is indicated with
UC=1, PCC=0, S=1, EN=1 and AR=0 in the IA32_MCi_STATUS register. In cases when SRAO is signaled via
CMCI the error signature is indicated via UC=1, PCC=0, S=0. Recovery actions for SRAO errors are MCA error
code specific. The MISCV and the ADDRV flags in the IA32_MCi_STATUS register are set when the additional
error information is available from the IA32_MCi_MISC and the IA32_MCi_ADDR registers. System software
needs to inspect the MCA error code fields in the IA32_MCi_STATUS register to identify the specific recovery
action for a given SRAO error. If MISCV and ADDRV are not set, it is recommended that no system software
error recovery be performed however, system software can resume execution.
•
Software recoverable action required (SRAR) - a UCR error that requires system software to take a recovery
action on this processor before scheduling another stream of execution on this processor. SRAR errors indicate
that the error was detected and raised at the point of the consumption in the execution flow. An SRAR error is
indicated with UC=1, PCC=0, S=1, EN=1 and AR=1 in the IA32_MCi_STATUS register. Recovery actions are
MCA error code specific. The MISCV and the ADDRV flags in the IA32_MCi_STATUS register are set when the
additional error information is available from the IA32_MCi_MISC and the IA32_MCi_ADDR registers. System
software needs to inspect the MCA error code fields in the IA32_MCi_STATUS register to identify the specific
recovery action for a given SRAR error. If MISCV and ADDRV are not set, it is recommended that system
software shutdown the system.
Table 15-6 summarizes UCR, corrected, and uncorrected errors.
Table 15-6. MC Error Classifications
Type of Error1
UC
EN
PCC
S
AR
Signaling Software Action
Uncorrected Error (UC)
1
1
1
x
x
MCE
If EN=1, reset the system, else log
and OK to keep the system running.
SRAR
1
1
0
1
1
MCE
For known MCACOD, take specific
recovery action;
Example
Cache to processor load
error.
For unknown MCACOD, must
bugcheck.
If OVER=1, reset system, else take
specific recovery action.
SRAO
1
x2
0
x2 0
MCE/CMC
For known MCACOD, take specific
recovery action;
Patrol scrub and explicit
writeback poison errors.
For unknown MCACOD, OK to keep
the system running.
UCNA
1
x
0
0
0
CMC
Log the error and Ok to keep the
system running.
Poison detection error.
Corrected Error (CE)
0
x
x
x
x
CMC
Log the error and no corrective
action required.
ECC in caches and
memory.
NOTES:
1. SRAR, SRAO and UCNA errors are supported by the processor only when IA32_MCG_CAP[24] (MCG_SER_P) is set.
2. EN=1, S=1 when signaled via MCE. EN=x, S=0 when signaled via CMC.
15.6.4
UCR Error Overwrite Rules
In general, the overwrite rules are as follows:
Vol. 3B 15-17
MACHINE-CHECK ARCHITECTURE
•
•
•
•
UCR errors will overwrite corrected errors.
Uncorrected (PCC=1) errors overwrite UCR (PCC=0) errors.
UCR errors are not written over previous UCR errors.
Corrected errors do not write over previous UCR errors.
Regardless of whether the 1st error is retained or the 2nd error is overwritten over the 1st error, the OVER flag in
the IA32_MCi_STATUS register will be set to indicate an overflow condition. As the S flag and AR flag in the
IA32_MCi_STATUS register are defined to be sticky flags, a second event cannot clear these 2 flags once set,
however the MC bank information may be filled in for the 2nd error. The table below shows the overwrite rules and
how to treat a second error if the first event is already logged in a MC bank along with the resulting bit setting of
the UC, PCC, and AR flags in the IA32_MCi_STATUS register. As UCNA and SRA0 errors do not require recovery
action from system software to continue program execution, a system reset by system software is not required
unless the AR flag or PCC flag is set for the UCR overflow case (OVER=1, VAL=1, UC=1, PCC=0).
Table 15-7 lists overwrite rules for uncorrected errors, corrected errors, and uncorrected recoverable errors.
Table 15-7. Overwrite Rules for UC, CE, and UCR Errors
First Event
Second Event
UC
PCC
S
CE
UCR
1
0
UCR
CE
1
0
UCNA
UCNA
1
UCNA
SRAO
UCNA
SRAO
MCA Bank
Reset System
0 if UCNA, else 1 1 if SRAR, else 0
second
yes, if AR=1
0 if UCNA, else 1 1 if SRAR, else 0
first
yes, if AR=1
0
0
0
first
no
1
0
1
0
first
no
SRAR
1
0
1
1
first
yes
UCNA
1
0
1
0
first
no
SRAO
SRAO
1
0
1
0
first
no
SRAO
SRAR
1
0
1
1
first
yes
SRAR
UCNA
1
0
1
1
first
yes
SRAR
SRAO
1
0
1
1
first
yes
SRAR
SRAR
1
0
1
1
first
yes
UCR
UC
1
1
undefined
undefined
second
yes
UC
UCR
1
1
undefined
undefined
first
yes
15.7
AR
MACHINE-CHECK AVAILABILITY
The machine-check architecture and machine-check exception (#MC) are model-specific features. Software can
execute the CPUID instruction to determine whether a processor implements these features. Following the execution of the CPUID instruction, the settings of the MCA flag (bit 14) and MCE flag (bit 7) in EDX indicate whether the
processor implements the machine-check architecture and machine-check exception.
15.8
MACHINE-CHECK INITIALIZATION
To use the processors machine-check architecture, software must initialize the processor to activate the machinecheck exception and the error-reporting mechanism.
Example 15-1 gives pseudocode for performing this initialization. This pseudocode checks for the existence of the
machine-check architecture and exception; it then enables machine-check exception and the error-reporting
register banks. The pseudocode shown is compatible with the Pentium 4, Intel Xeon, Intel Atom, P6 family, and
Pentium processors.
Following power up or power cycling, IA32_MCi_STATUS registers are not guaranteed to have valid data until after
they are initially cleared to zero by software (as shown in the initialization pseudocode in Example 15-1). In addition, when using P6 family processors, software must set MCi_STATUS registers to zero when doing a soft-reset.
15-18 Vol. 3B
MACHINE-CHECK ARCHITECTURE
Example 15-1. Machine-Check Initialization Pseudocode
Check CPUID Feature Flags for MCE and MCA support
IF CPU supports MCE
THEN
IF CPU supports MCA
THEN
IF (IA32_MCG_CAP.MCG_CTL_P = 1)
(* IA32_MCG_CTL register is present *)
THEN
IA32_MCG_CTL ← FFFFFFFFFFFFFFFFH;
(* enables all MCA features *)
FI
IF (IA32_MCG_CAP.MCG_LMCE_P = 1 and IA32_FEATURE_CONTROL.LOCK = 1 and IA32_FEATURE_CONTROL.LMCE_ON= 1)
(* IA32_MCG_EXT_CTL register is present and platform has enabled LMCE to permit system software to use LMCE *)
THEN
IA32_MCG_EXT_CTL ← IA32_MCG_EXT_CTL | 01H;
(* System software enables LMCE capability for hardware to signal MCE to a single logical processor*)
FI
(* Determine number of error-reporting banks supported *)
COUNT← IA32_MCG_CAP.Count;
MAX_BANK_NUMBER ← COUNT - 1;
IF (Processor Family is 6H and Processor EXTMODEL:MODEL is less than 1AH)
THEN
(* Enable logging of all errors except for MC0_CTL register *)
FOR error-reporting banks (1 through MAX_BANK_NUMBER)
DO
IA32_MCi_CTL ← 0FFFFFFFFFFFFFFFFH;
OD
ELSE
(* Enable logging of all errors including MC0_CTL register *)
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
IA32_MCi_CTL ← 0FFFFFFFFFFFFFFFFH;
OD
FI
(* BIOS clears all errors only on power-on reset *)
IF (BIOS detects Power-on reset)
THEN
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
IA32_MCi_STATUS ← 0;
OD
ELSE
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
(Optional for BIOS and OS) Log valid errors
(OS only) IA32_MCi_STATUS ← 0;
OD
FI
FI
Setup the Machine Check Exception (#MC) handler for vector 18 in IDT
Set the MCE bit (bit 6) in CR4 register to enable Machine-Check Exceptions
FI
Vol. 3B 15-19
MACHINE-CHECK ARCHITECTURE
15.9
INTERPRETING THE MCA ERROR CODES
When the processor detects a machine-check error condition, it writes a 16-bit error code to the MCA error code
field of one of the IA32_MCi_STATUS registers and sets the VAL (valid) flag in that register. The processor may also
write a 16-bit model-specific error code in the IA32_MCi_STATUS register depending on the implementation of the
machine-check architecture of the processor.
The MCA error codes are architecturally defined for Intel 64 and IA-32 processors. To determine the cause of a
machine-check exception, the machine-check exception handler must read the VAL flag for each
IA32_MCi_STATUS register. If the flag is set, the machine check-exception handler must then read the MCA error
code field of the register. It is the encoding of the MCA error code field [15:0] that determines the type of error
being reported and not the register bank reporting it.
There are two types of MCA error codes: simple error codes and compound error codes.
15.9.1
Simple Error Codes
Table 15-8 shows the simple error codes. These unique codes indicate global error information.
Table 15-8. IA32_MCi_Status [15:0] Simple Error Code Encoding
Error Code
Binary Encoding
Meaning
No Error
0000 0000 0000 0000
No error has been reported to this bank of error-reporting
registers.
Unclassified
0000 0000 0000 0001
This error has not been classified into the MCA error classes.
Microcode ROM Parity Error
0000 0000 0000 0010
Parity error in internal microcode ROM
External Error
0000 0000 0000 0011
The BINIT# from another processor caused this processor to
enter machine check.1
FRC Error
0000 0000 0000 0100
FRC (functional redundancy check) master/slave error
Internal Parity Error
0000 0000 0000 0101
Internal parity error.
SMM Handler Code Access
Violation
0000 0000 0000 0110
An attempt was made by the SMM Handler to execute
outside the ranges specified by SMRR.
Internal Timer Error
0000 0100 0000 0000
Internal timer error.
I/O Error
0000 1110 0000 1011
generic I/O error.
Internal Unclassified
0000 01xx xxxx xxxx
Internal unclassified errors. 2
NOTES:
1. BINIT# assertion will cause a machine check exception if the processor (or any processor on the same external bus) has BINIT#
observation enabled during power-on configuration (hardware strapping) and if machine check exceptions are enabled (by setting
CR4.MCE = 1).
2. At least one X must equal one. Internal unclassified errors have not been classified.
15.9.2
Compound Error Codes
Compound error codes describe errors related to the TLBs, memory, caches, bus and interconnect logic, and
internal timer. A set of sub-fields is common to all of compound errors. These sub-fields describe the type of access,
level in the cache hierarchy, and type of request. Table 15-9 shows the general form of the compound error codes.
Table 15-9. IA32_MCi_Status [15:0] Compound Error Code Encoding
Type
Form
Generic Cache Hierarchy
000F 0000 0000 11LL
Generic cache hierarchy error
TLB Errors
000F 0000 0001 TTLL
{TT}TLB{LL}_ERR
Memory Controller Errors
000F 0000 1MMM CCCC
{MMM}_CHANNEL{CCCC}_ERR
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Interpretation
MACHINE-CHECK ARCHITECTURE
Table 15-9. IA32_MCi_Status [15:0] Compound Error Code Encoding (Contd.)
Cache Hierarchy Errors
000F 0001 RRRR TTLL
{TT}CACHE{LL}_{RRRR}_ERR
Bus and Interconnect Errors
000F 1PPT RRRR IILL
BUS{LL}_{PP}_{RRRR}_{II}_{T}_ERR
The “Interpretation” column in the table indicates the name of a compound error. The name is constructed by
substituting mnemonics for the sub-field names given within curly braces. For example, the error code
ICACHEL1_RD_ERR is constructed from the form:
{TT}CACHE{LL}_{RRRR}_ERR,
where {TT} is replaced by I, {LL} is replaced by L1, and {RRRR} is replaced by RD.
For more information on the “Form” and “Interpretation” columns, see Sections Section 15.9.2.1, “Correction
Report Filtering (F) Bit” through Section 15.9.2.5, “Bus and Interconnect Errors”.
15.9.2.1
Correction Report Filtering (F) Bit
Starting with Intel Core Duo processors, bit 12 in the “Form” column in Table 15-9 is used to indicate that a particular posting to a log may be the last posting for corrections in that line/entry, at least for some time:
•
•
0 in bit 12 indicates “normal” filtering (original P6/Pentium4/Atom/Xeon processor meaning).
1 in bit 12 indicates “corrected” filtering (filtering is activated for the line/entry in the posting). Filtering means
that some or all of the subsequent corrections to this entry (in this structure) will not be posted. The enhanced
error reporting introduced with the Intel Core Duo processors is based on tracking the lines affected by
repeated corrections (see Section 15.4, “Enhanced Cache Error reporting”). This capability is indicated by
IA32_MCG_CAP[11]. Only the first few correction events for a line are posted; subsequent redundant
correction events to the same line are not posted. Uncorrected events are always posted.
The behavior of error filtering after crossing the yellow threshold is model-specific. Filtering has meaning only for
corrected errors (UC=0 in IA32_MCi_STATUS MSR). System software must ignore filtering bit (12) for uncorrected
errors.
15.9.2.2
Transaction Type (TT) Sub-Field
The 2-bit TT sub-field (Table 15-10) indicates the type of transaction (data, instruction, or generic). The sub-field
applies to the TLB, cache, and interconnect error conditions. Note that interconnect error conditions are primarily
associated with P6 family and Pentium processors, which utilize an external APIC bus separate from the system
bus. The generic type is reported when the processor cannot determine the transaction type.
Table 15-10. Encoding for TT (Transaction Type) Sub-Field
Transaction Type
Mnemonic
Binary Encoding
Instruction
I
00
Data
D
01
Generic
G
10
15.9.2.3
Level (LL) Sub-Field
The 2-bit LL sub-field (see Table 15-11) indicates the level in the memory hierarchy where the error occurred (level
0, level 1, level 2, or generic). The LL sub-field also applies to the TLB, cache, and interconnect error conditions.
The Pentium 4, Intel Xeon, Intel Atom, and P6 family processors support two levels in the cache hierarchy and one
level in the TLBs. Again, the generic type is reported when the processor cannot determine the hierarchy level.
Table 15-11. Level Encoding for LL (Memory Hierarchy Level) Sub-Field
Hierarchy Level
Mnemonic
Binary Encoding
Level 0
L0
00
Level 1
L1
01
Vol. 3B 15-21
MACHINE-CHECK ARCHITECTURE
Table 15-11. Level Encoding for LL (Memory Hierarchy Level) Sub-Field (Contd.)
Level 2
L2
10
Generic
LG
11
15.9.2.4
Request (RRRR) Sub-Field
The 4-bit RRRR sub-field (see Table 15-12) indicates the type of action associated with the error. Actions include
read and write operations, prefetches, cache evictions, and snoops. Generic error is returned when the type of
error cannot be determined. Generic read and generic write are returned when the processor cannot determine the
type of instruction or data request that caused the error. Eviction and snoop requests apply only to the caches. All
of the other requests apply to TLBs, caches and interconnects.
Table 15-12. Encoding of Request (RRRR) Sub-Field
Request Type
Mnemonic
Generic Error
ERR
0000
Generic Read
RD
0001
Generic Write
WR
0010
Data Read
DRD
0011
Data Write
DWR
0100
Instruction Fetch
IRD
0101
Prefetch
PREFETCH
0110
Eviction
EVICT
0111
Snoop
SNOOP
1000
15.9.2.5
Binary Encoding
Bus and Interconnect Errors
The bus and interconnect errors are defined with the 2-bit PP (participation), 1-bit T (time-out), and 2-bit II
(memory or I/O) sub-fields, in addition to the LL and RRRR sub-fields (see Table 15-13). The bus error conditions
are implementation dependent and related to the type of bus implemented by the processor. Likewise, the interconnect error conditions are predicated on a specific implementation-dependent interconnect model that describes
the connections between the different levels of the storage hierarchy. The type of bus is implementation dependent, and as such is not specified in this document. A bus or interconnect transaction consists of a request involving
an address and a response.
Table 15-13. Encodings of PP, T, and II Sub-Fields
Sub-Field
Transaction
Mnemonic
PP (Participation)
Local processor* originated request
SRC
00
Local processor* responded to request
RES
01
Local processor* observed error as third party
OBS
10
Generic
T (Time-out)
II (Memory or I/O)
Binary Encoding
11
Request timed out
TIMEOUT
1
Request did not time out
NOTIMEOUT
0
Memory Access
M
00
Reserved
I/O
Other transaction
01
IO
10
11
NOTE:
* Local processor differentiates the processor reporting the error from other system components (including the APIC, other processors, etc.).
15-22 Vol. 3B
MACHINE-CHECK ARCHITECTURE
15.9.2.6
Memory Controller Errors
The memory controller errors are defined with the 3-bit MMM (memory transaction type), and 4-bit CCCC
(channel) sub-fields. The encodings for MMM and CCCC are defined in Table 15-14.
Table 15-14. Encodings of MMM and CCCC Sub-Fields
Sub-Field
Transaction
Mnemonic
Binary Encoding
MMM
Generic undefined request
GEN
000
Memory read error
RD
001
Memory write error
WR
010
Address/Command Error
AC
011
Memory Scrubbing Error
MS
100
Reserved
CCCC
101-111
Channel number
CHN
0000-1110
Channel not specified
15.9.3
1111
Architecturally Defined UCR Errors
Software recoverable compound error code are defined in this section.
15.9.3.1
Architecturally Defined SRAO Errors
The following two SRAO errors are architecturally defined.
•
•
UCR Errors detected by memory controller scrubbing; and
UCR Errors detected during L3 cache (L3) explicit writebacks.
The MCA error code encodings for these two architecturally-defined UCR errors corresponds to sub-classes of
compound MCA error codes (see Table 15-9). Their values and compound encoding format are given in Table
15-15.
Table 15-15. MCA Compound Error Code Encoding for SRAO Errors
Type
MCACOD Value
Memory Scrubbing
C0H - CFH
MCA Error Code Encoding1
0000_0000_1100_CCCC
000F 0000 1MMM CCCC (Memory Controller Error), where
Memory subfield MMM = 100B (memory scrubbing)
Channel subfield CCCC = channel # or generic
L3 Explicit Writeback 17AH
0000_0001_0111_1010
000F 0001 RRRR TTLL (Cache Hierarchy Error) where
Request subfields RRRR = 0111B (Eviction)
Transaction Type subfields TT = 10B (Generic)
Level subfields LL = 10B
NOTES:
1. Note that for both of these errors the correction report filtering (F) bit (bit 12) of the MCA error must be ignored.
Table 15-16 lists values of relevant bit fields of IA32_MCi_STATUS for architecturally defined SRAO errors.
Table 15-16. IA32_MCi_STATUS Values for SRAO Errors
SRAO Error
Memory Scrubbing
L3 Explicit Writeback
Valid
1
1
OVER
0
0
UC
1
1
EN
x
1
x
1
MISCV
1
1
ADDRV
1
1
PCC
S
AR
MCACOD
0
x1
0
C0H-CFH
0
x1
0
17AH
Vol. 3B 15-23
MACHINE-CHECK ARCHITECTURE
NOTES:
1. When signaled as MCE, EN=1 and S=1. If error was signaled via CMC, then EN=x, and S=0.
For both the memory scrubbing and L3 explicit writeback errors, the ADDRV and MISCV flags in the
IA32_MCi_STATUS register are set to indicate that the offending physical address information is available from the
IA32_MCi_MISC and the IA32_MCi_ADDR registers. For the memory scrubbing and L3 explicit writeback errors,
the address mode in the IA32_MCi_MISC register should be set as physical address mode (010b) and the address
LSB information in the IA32_MCi_MISC register should indicate the lowest valid address bit in the address information provided from the IA32_MCi_ADDR register.
MCE signal is broadcast to all logical processors as outlined in Section 15.10.4.1. If LMCE is supported and enabled,
some errors (not limited to UCR errors) may be delivered to only a single logical processor. System software should
consult IA32_MCG_STATUS.LMCE_S to determine if the MCE signaled is only to this logical processor.
IA32_MCi_STATUS banks can be shared by logical processors within a core or within the same package. So several
logical processors may find an SRAO error in the shared IA32_MCi_STATUS bank but other processors do not find
it in any of the IA32_MCi_STATUS banks. Table 15-17 shows the RIPV and EIPV flag indication in the
IA32_MCG_STATUS register for the memory scrubbing and L3 explicit writeback errors on both the reporting and
non-reporting logical processors.
Table 15-17. IA32_MCG_STATUS Flag Indication for SRAO Errors
SRAO Type
Reporting Logical Processors
Non-reporting Logical Processors
RIPV
EIPV
RIPV
EIPV
Memory Scrubbing
1
0
1
0
L3 Explicit Writeback
1
0
1
0
15.9.3.2
Architecturally Defined SRAR Errors
The following two SRAR errors are architecturally defined.
•
•
UCR Errors detected on data load; and
UCR Errors detected on instruction fetch.
The MCA error code encodings for these two architecturally-defined UCR errors corresponds to sub-classes of
compound MCA error codes (see Table 15-9). Their values and compound encoding format are given in Table
15-18.
Table 15-18. MCA Compound Error Code Encoding for SRAR Errors
Type
MCACOD Value
Data Load
134H
MCA Error Code Encoding1
0000_0001_0011_0100
000F 0001 RRRR TTLL (Cache Hierarchy Error), where
Request subfield RRRR = 0011B (Data Load)
Transaction Type subfield TT= 01B (Data)
Level subfield LL = 00B (Level 0)
Instruction Fetch
150H
0000_0001_0101_0000
000F 0001 RRRR TTLL (Cache Hierarchy Error), where
Request subfield RRRR = 0101B (Instruction Fetch)
Transaction Type subfield TT= 00B (Instruction)
Level subfield LL = 00B (Level 0)
NOTES:
1. Note that for both of these errors the correction report filtering (F) bit (bit 12) of the MCA error must be ignored.
15-24 Vol. 3B
MACHINE-CHECK ARCHITECTURE
Table 15-19 lists values of relevant bit fields of IA32_MCi_STATUS for architecturally defined SRAR errors.
Table 15-19. IA32_MCi_STATUS Values for SRAR Errors
SRAR Error
Valid
OVER
UC
EN
MISCV
ADDRV
PCC
S
AR
MCACOD
Data Load
1
0
1
1
1
1
0
1
1
134H
Instruction Fetch
1
0
1
1
1
1
0
1
1
150H
For both the data load and instruction fetch errors, the ADDRV and MISCV flags in the IA32_MCi_STATUS register
are set to indicate that the offending physical address information is available from the IA32_MCi_MISC and the
IA32_MCi_ADDR registers. For the memory scrubbing and L3 explicit writeback errors, the address mode in the
IA32_MCi_MISC register should be set as physical address mode (010b) and the address LSB information in the
IA32_MCi_MISC register should indicate the lowest valid address bit in the address information provided from the
IA32_MCi_ADDR register.
MCE signal is broadcast to all logical processors on the system on which the UCR errors are supported, except when
the processor supports LMCE and LMCE is enabled by system software (see Section 15.3.1.5). The
IA32_MCG_STATUS MSR allows system software to distinguish the affected logical processor of an SRAR error
amongst logical processors that observed SRAR via MCi_STATUS bank.
Table 15-20 shows the RIPV and EIPV flag indication in the IA32_MCG_STATUS register for the data load and
instruction fetch errors on both the reporting and non-reporting logical processors. The recoverable SRAR error
reported by a processor may be continuable, where the system software can interpret the context of continuable
as follows: the error was isolated, contained. If software can rectify the error condition in the current instruction
stream, the execution context on that logical processor can be continued without loss of information.
Table 15-20. IA32_MCG_STATUS Flag Indication for SRAR Errors
SRAR Type
Affected Logical Processor
RIPV
EIPV
Non-Affected Logical Processors
Continuable
Recoverablecontinuable
1
1
Yes
Recoverable-notcontinuable
0
x
No
RIPV
EIPV
Continuable
1
1
0
Yes
NOTES:
1. see the definition of the context of “continuable” above and additional detail below.
SRAR Error And Affected Logical Processors
The affected logical processor is the one that has detected and raised an SRAR error at the point of the consumption in the execution flow. The affected logical processor should find the Data Load or the Instruction Fetch error
information in the IA32_MCi_STATUS register that is reporting the SRAR error.
Table 15-20 list the actionable scenarios that system software can respond to an SRAR error on an affected logical
processor according to RIPV and EIPV values:
•
Recoverable-Continuable SRAR Error (RIPV=1, EIPV=1):
For Recoverable-Continuable SRAR errors, the affected logical processor should find that both the
IA32_MCG_STATUS.RIPV and the IA32_MCG_STATUS.EIPV flags are set, indicating that system software may
be able to restart execution from the interrupted context if it is able to rectify the error condition. If system
software cannot rectify the error condition then it must treat the error as a recoverable error where restarting
execution with the interrupted context is not possible. Restarting without rectifying the error condition will
result in most cases with another SRAR error on the same instruction.
•
Recoverable-not-continuable SRAR Error (RIPV=0, EIPV=x):
For Recoverable-not-continuable errors, the affected logical processor should find that either
— IA32_MCG_STATUS.RIPV= 0, IA32_MCG_STATUS.EIPV=1, or
— IA32_MCG_STATUS.RIPV= 0, IA32_MCG_STATUS.EIPV=0.
Vol. 3B 15-25
MACHINE-CHECK ARCHITECTURE
In either case, this indicates that the error is detected at the instruction pointer saved on the stack for this
machine check exception and restarting execution with the interrupted context is not possible. System
software may take the following recovery actions for the affected logical processor:
•
The current executing thread cannot be continued. System software must terminate the interrupted
stream of execution and provide a new stream of execution on return from the machine check handler
for the affected logical processor.
SRAR Error And Non-Affected Logical Processors
The logical processors that observed but not affected by an SRAR error should find that the RIPV flag in the
IA32_MCG_STATUS register is set and the EIPV flag in the IA32_MCG_STATUS register is cleared, indicating that it
is safe to restart the execution at the instruction saved on the stack for the machine check exception on these
processors after the recovery action is successfully taken by system software.
15.9.4
Multiple MCA Errors
When multiple MCA errors are detected within a certain detection window, the processor may aggregate the
reporting of these errors together as a single event, i.e. a single machine exception condition. If this occurs,
system software may find multiple MCA errors logged in different MC banks on one logical processor or find multiple
MCA errors logged across different processors for a single machine check broadcast event. In order to handle
multiple UCR errors reported from a single machine check event and possibly recover from multiple errors, system
software may consider the following:
•
Whether it can recover from multiple errors is determined by the most severe error reported on the system. If
the most severe error is found to be an unrecoverable error (VAL=1, UC=1, PCC=1 and EN=1) after system
software examines the MC banks of all processors to which the MCA signal is broadcast, recovery from the
multiple errors is not possible and system software needs to reset the system.
•
When multiple recoverable errors are reported and no other fatal condition (e.g. overflowed condition for SRAR
error) is found for the reported recoverable errors, it is possible for system software to recover from the
multiple recoverable errors by taking necessary recovery action for each individual recoverable error. However,
system software can no longer expect one to one relationship with the error information recorded in the
IA32_MCi_STATUS register and the states of the RIPV and EIPV flags in the IA32_MCG_STATUS register as the
states of the RIPV and the EIPV flags in the IA32_MCG_STATUS register may indicate the information for the
most severe error recorded on the processor. System software is required to use the RIPV flag indication in the
IA32_MCG_STATUS register to make a final decision of recoverability of the errors and find the restart-ability
requirement after examining each IA32_MCi_STATUS register error information in the MC banks.
In certain cases where system software observes more than one SRAR error logged for a single logical
processor, it can no longer rely on affected threads as specified in Table 15-20 above. System software is
recommended to reset the system if this condition is observed.
15.9.5
Machine-Check Error Codes Interpretation
Chapter 16, “Interpreting Machine-Check Error Codes,” provides information on interpreting the MCA error code,
model-specific error code, and other information error code fields. For P6 family processors, information has been
included on decoding external bus errors. For Pentium 4 and Intel Xeon processors; information is included on
external bus, internal timer and cache hierarchy errors.
15.10
GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE
The machine-check architecture and error logging can be used in three different ways:
•
•
•
To detect machine errors during normal instruction execution, using the machine-check exception (#MC).
To periodically check and log machine errors.
To examine recoverable UCR errors, determine software recoverability and perform recovery actions via a
machine-check exception handler or a corrected machine-check interrupt handler.
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MACHINE-CHECK ARCHITECTURE
To use the machine-check exception, the operating system or executive software must provide a machine-check
exception handler. This handler may need to be designed specifically for each family of processors.
A special program or utility is required to log machine errors.
Guidelines for writing a machine-check exception handler or a machine-error logging utility are given in the
following sections.
15.10.1 Machine-Check Exception Handler
The machine-check exception (#MC) corresponds to vector 18. To service machine-check exceptions, a trap gate
must be added to the IDT. The pointer in the trap gate must point to a machine-check exception handler. Two
approaches can be taken to designing the exception handler:
1. The handler can merely log all the machine status and error information, then call a debugger or shut down the
system.
2. The handler can analyze the reported error information and, in some cases, attempt to correct the error and
restart the processor.
For Pentium 4, Intel Xeon, Intel Atom, P6 family, and Pentium processors; virtually all machine-check conditions
cannot be corrected (they result in abort-type exceptions). The logging of status and error information is therefore
a baseline implementation requirement.
When IA32_MCG_CAP[24] is clear, consider the following when writing a machine-check exception handler:
•
To determine the nature of the error, the handler must read each of the error-reporting register banks. The
count field in the IA32_MCG_CAP register gives number of register banks. The first register of register bank 0
is at address 400H.
•
The VAL (valid) flag in each IA32_MCi_STATUS register indicates whether the error information in the register
is valid. If this flag is clear, the registers in that bank do not contain valid error information and do not need to
be checked.
•
To write a portable exception handler, only the MCA error code field in the IA32_MCi_STATUS register should be
checked. See Section 15.9, “Interpreting the MCA Error Codes,” for information that can be used to write an
algorithm to interpret this field.
•
Correctable errors are corrected automatically by the processor. The UC flag in each IA32_MCi_STATUS register indicates whether the processor automatically corrected an error.
•
The RIPV, PCC, and OVER flags in each IA32_MCi_STATUS register indicate whether recovery from the error is
possible. If PCC or OVER are set, recovery is not possible. If RIPV is not set, program execution can not be
restarted reliably. When recovery is not possible, the handler typically records the error information and signals
an abort to the operating system.
•
The RIPV flag in the IA32_MCG_STATUS register indicates whether the program can be restarted at the
instruction indicated by the instruction pointer (the address of the instruction pushed on the stack when the
exception was generated). If this flag is clear, the processor may still be able to be restarted (for debugging
purposes) but not without loss of program continuity.
•
For unrecoverable errors, the EIPV flag in the IA32_MCG_STATUS register indicates whether the instruction
indicated by the instruction pointer pushed on the stack (when the exception was generated) is related to the
error. If the flag is clear, the pushed instruction may not be related to the error.
•
The MCIP flag in the IA32_MCG_STATUS register indicates whether a machine-check exception was generated.
Before returning from the machine-check exception handler, software should clear this flag so that it can be
used reliably by an error logging utility. The MCIP flag also detects recursion. The machine-check architecture
does not support recursion. When the processor detects machine-check recursion, it enters the shutdown
state.
Example 15-2 gives typical steps carried out by a machine-check exception handler.
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MACHINE-CHECK ARCHITECTURE
Example 15-2. Machine-Check Exception Handler Pseudocode
IF CPU supports MCE
THEN
IF CPU supports MCA
THEN
call errorlogging routine; (* returns restartability *)
FI;
ELSE (* Pentium(R) processor compatible *)
READ P5_MC_ADDR
READ P5_MC_TYPE;
report RESTARTABILITY to console;
FI;
IF error is not restartable
THEN
report RESTARTABILITY to console;
abort system;
FI;
CLEAR MCIP flag in IA32_MCG_STATUS;
15.10.2 Pentium Processor Machine-Check Exception Handling
Machine-check exception handler on P6 family, Intel Atom and later processor families, should follow the guidelines
described in Section 15.10.1 and Example 15-2 that check the processor’s support of MCA.
NOTE
On processors that support MCA (CPUID.1.EDX.MCA = 1) reading the P5_MC_TYPE and
P5_MC_ADDR registers may produce invalid data.
When machine-check exceptions are enabled for the Pentium processor (MCE flag is set in control register CR4),
the machine-check exception handler uses the RDMSR instruction to read the error type from the P5_MC_TYPE
register and the machine check address from the P5_MC_ADDR register. The handler then normally reports these
register values to the system console before aborting execution (see Example 15-2).
15.10.3 Logging Correctable Machine-Check Errors
The error handling routine for servicing the machine-check exceptions is responsible for logging uncorrected
errors.
If a machine-check error is correctable, the processor does not generate a machine-check exception for it. To
detect correctable machine-check errors, a utility program must be written that reads each of the machine-check
error-reporting register banks and logs the results in an accounting file or data structure. This utility can be implemented in either of the following ways.
•
•
A system daemon that polls the register banks on an infrequent basis, such as hourly or daily.
•
An interrupt service routine servicing CMCI can read the MC banks and log the error. Please refer to Section
15.10.4.2 for guidelines on logging correctable machine checks.
A user-initiated application that polls the register banks and records the exceptions. Here, the actual polling
service is provided by an operating-system driver or through the system call interface.
Example 15-3 gives pseudocode for an error logging utility.
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MACHINE-CHECK ARCHITECTURE
Example 15-3. Machine-Check Error Logging Pseudocode
Assume that execution is restartable;
IF the processor supports MCA
THEN
FOR each bank of machine-check registers
DO
READ IA32_MCi_STATUS;
IF VAL flag in IA32_MCi_STATUS = 1
THEN
IF ADDRV flag in IA32_MCi_STATUS = 1
THEN READ IA32_MCi_ADDR;
FI;
IF MISCV flag in IA32_MCi_STATUS = 1
THEN READ IA32_MCi_MISC;
FI;
IF MCIP flag in IA32_MCG_STATUS = 1
(* Machine-check exception is in progress *)
AND PCC flag in IA32_MCi_STATUS = 1
OR RIPV flag in IA32_MCG_STATUS = 0
(* execution is not restartable *)
THEN
RESTARTABILITY = FALSE;
return RESTARTABILITY to calling procedure;
FI;
Save time-stamp counter and processor ID;
Set IA32_MCi_STATUS to all 0s;
Execute serializing instruction (i.e., CPUID);
FI;
OD;
FI;
If the processor supports the machine-check architecture, the utility reads through the banks of error-reporting
registers looking for valid register entries. It then saves the values of the IA32_MCi_STATUS, IA32_MCi_ADDR,
IA32_MCi_MISC and IA32_MCG_STATUS registers for each bank that is valid. The routine minimizes processing
time by recording the raw data into a system data structure or file, reducing the overhead associated with polling.
User utilities analyze the collected data in an off-line environment.
When the MCIP flag is set in the IA32_MCG_STATUS register, a machine-check exception is in progress and the
machine-check exception handler has called the exception logging routine.
Once the logging process has been completed the exception-handling routine must determine whether execution
can be restarted, which is usually possible when damage has not occurred (The PCC flag is clear, in the
IA32_MCi_STATUS register) and when the processor can guarantee that execution is restartable (the RIPV flag is
set in the IA32_MCG_STATUS register). If execution cannot be restarted, the system is not recoverable and the
exception-handling routine should signal the console appropriately before returning the error status to the Operating System kernel for subsequent shutdown.
The machine-check architecture allows buffering of exceptions from a given error-reporting bank although the
Pentium 4, Intel Xeon, Intel Atom, and P6 family processors do not implement this feature. The error logging
routine should provide compatibility with future processors by reading each hardware error-reporting bank's
IA32_MCi_STATUS register and then writing 0s to clear the OVER and VAL flags in this register. The error logging
utility should re-read the IA32_MCi_STATUS register for the bank ensuring that the valid bit is clear. The processor
will write the next error into the register bank and set the VAL flags.
Additional information that should be stored by the exception-logging routine includes the processor’s time-stamp
counter value, which provides a mechanism to indicate the frequency of exceptions. A multiprocessing operating
system stores the identity of the processor node incurring the exception using a unique identifier, such as the
processor’s APIC ID (see Section 10.8, “Handling Interrupts”).
The basic algorithm given in Example 15-3 can be modified to provide more robust recovery techniques. For
example, software has the flexibility to attempt recovery using information unavailable to the hardware. Specifically, the machine-check exception handler can, after logging carefully analyze the error-reporting registers when
the error-logging routine reports an error that does not allow execution to be restarted. These recovery techniques
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MACHINE-CHECK ARCHITECTURE
can use external bus related model-specific information provided with the error report to localize the source of the
error within the system and determine the appropriate recovery strategy.
15.10.4 Machine-Check Software Handler Guidelines for Error Recovery
15.10.4.1 Machine-Check Exception Handler for Error Recovery
When writing a machine-check exception (MCE) handler to support software recovery from Uncorrected Recoverable (UCR) errors, consider the following:
•
When IA32_MCG_CAP [24] is zero, there are no recoverable errors supported and all machine-check are fatal
exceptions. The logging of status and error information is therefore a baseline implementation requirement.
•
When IA32_MCG_CAP [24] is 1, certain uncorrected errors called uncorrected recoverable (UCR) errors may be
software recoverable. The handler can analyze the reported error information, and in some cases attempt to
recover from the uncorrected error and continue execution.
•
For processors on which CPUID reports DisplayFamily_DisplayModel as 06H_0EH and onward, an MCA signal is
broadcast to all logical processors in the system (see CPUID instruction in Chapter 3, “Instruction Set
Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). Due to the
potentially shared machine check MSR resources among the logical processors on the same package/core, the
MCE handler may be required to synchronize with the other processors that received a machine check error and
serialize access to the machine check registers when analyzing, logging and clearing the information in the
machine check registers.
— On processors that indicate ability for local machine-check exception (MCG_LMCE_P), hardware can choose
to report the error to only a single logical processor if system software has enabled LMCE by setting
IA32_MCG_EXT_CTL[LMCE_EN] = 1 as outlined in Section 15.3.1.5.
•
The VAL (valid) flag in each IA32_MCi_STATUS register indicates whether the error information in the register
is valid. If this flag is clear, the registers in that bank do not contain valid error information and should not be
checked.
•
The MCE handler is primarily responsible for processing uncorrected errors. The UC flag in each
IA32_MCi_Status register indicates whether the reported error was corrected (UC=0) or uncorrected (UC=1).
The MCE handler can optionally log and clear the corrected errors in the MC banks if it can implement software
algorithm to avoid the undesired race conditions with the CMCI or CMC polling handler.
•
For uncorrectable errors, the EIPV flag in the IA32_MCG_STATUS register indicates (when set) that the
instruction pointed to by the instruction pointer pushed onto the stack when the machine-check exception is
generated is directly associated with the error. When this flag is cleared, the instruction pointed to may not be
associated with the error.
•
The MCIP flag in the IA32_MCG_STATUS register indicates whether a machine-check exception was generated.
When a machine check exception is generated, it is expected that the MCIP flag in the IA32_MCG_STATUS
register is set to 1. If it is not set, this machine check was generated by either an INT 18 instruction or some
piece of hardware signaling an interrupt with vector 18.
When IA32_MCG_CAP [24] is 1, the following rules can apply when writing a machine check exception (MCE)
handler to support software recovery:
•
The PCC flag in each IA32_MCi_STATUS register indicates whether recovery from the error is possible for
uncorrected errors (UC=1). If the PCC flag is set for enabled uncorrected errors (UC=1 and EN=1), recovery is
not possible. When recovery is not possible, the MCE handler typically records the error information and signals
the operating system to reset the system.
•
The RIPV flag in the IA32_MCG_STATUS register indicates whether restarting the program execution from the
instruction pointer saved on the stack for the machine check exception is possible. When the RIPV is set,
program execution can be restarted reliably when recovery is possible. If the RIPV flag is not set, program
execution cannot be restarted reliably. In this case the recovery algorithm may involve terminating the current
program execution and resuming an alternate thread of execution upon return from the machine check handler
when recovery is possible. When recovery is not possible, the MCE handler signals the operating system to
reset the system.
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MACHINE-CHECK ARCHITECTURE
•
When the EN flag is zero but the VAL and UC flags are one in the IA32_MCi_STATUS register, the reported
uncorrected error in this bank is not enabled. As uncorrected errors with the EN flag = 0 are not the source of
machine check exceptions, the MCE handler should log and clear non-enabled errors when the S bit is set and
should continue searching for enabled errors from the other IA32_MCi_STATUS registers. Note that when
IA32_MCG_CAP [24] is 0, any uncorrected error condition (VAL =1 and UC=1) including the one with the EN
flag cleared are fatal and the handler must signal the operating system to reset the system. For the errors that
do not generate machine check exceptions, the EN flag has no meaning.
•
When the VAL flag is one, the UC flag is one, the EN flag is one and the PCC flag is zero in the
IA32_MCi_STATUS register, the error in this bank is an uncorrected recoverable (UCR) error. The MCE handler
needs to examine the S flag and the AR flag to find the type of the UCR error for software recovery and
determine if software error recovery is possible.
•
When both the S and the AR flags are clear in the IA32_MCi_STATUS register for the UCR error (VAL=1, UC=1,
EN=x and PCC=0), the error in this bank is an uncorrected no-action required error (UCNA). UCNA errors are
uncorrected but do not require any OS recovery action to continue execution. These errors indicate that some
data in the system is corrupt, but that data has not been consumed and may not be consumed. If that data is
consumed a non-UNCA machine check exception will be generated. UCNA errors are signaled in the same way
as corrected machine check errors and the CMCI and CMC polling handler is primarily responsible for handling
UCNA errors. Like corrected errors, the MCA handler can optionally log and clear UCNA errors as long as it can
avoid the undesired race condition with the CMCI or CMC polling handler. As UCNA errors are not the source of
machine check exceptions, the MCA handler should continue searching for uncorrected or software recoverable
errors in all other MC banks.
•
When the S flag in the IA32_MCi_STATUS register is set for the UCR error ((VAL=1, UC=1, EN=1 and PCC=0),
the error in this bank is software recoverable and it was signaled through a machine-check exception. The AR
flag in the IA32_MCi_STATUS register further clarifies the type of the software recoverable errors.
•
When the AR flag in the IA32_MCi_STATUS register is clear for the software recoverable error (VAL=1, UC=1,
EN=1, PCC=0 and S=1), the error in this bank is a software recoverable action optional (SRAO) error. The MCE
handler and the operating system can analyze the IA32_MCi_STATUS [15:0] to implement MCA error code
specific optional recovery action, but this recovery action is optional. System software can resume the program
execution from the instruction pointer saved on the stack for the machine check exception when the RIPV flag
in the IA32_MCG_STATUS register is set.
•
Even if the OVER flag in the IA32_MCi_STATUS register is set for the SRAO error (VAL=1, UC=1, EN=1, PCC=0,
S=1 and AR=0), the MCE handler can take recovery action for the SRAO error logged in the IA32_MCi_STATUS
register. Since the recovery action for SRAO errors is optional, restarting the program execution from the
instruction pointer saved on the stack for the machine check exception is still possible for the overflowed SRAO
error if the RIPV flag in the IA32_MCG_STATUS is set.
•
When the AR flag in the IA32_MCi_STATUS register is set for the software recoverable error (VAL=1, UC=1,
EN=1, PCC=0 and S=1), the error in this bank is a software recoverable action required (SRAR) error. The MCE
handler and the operating system must take recovery action in order to continue execution after the machinecheck exception. The MCA handler and the operating system need to analyze the IA32_MCi_STATUS [15:0] to
determine the MCA error code specific recovery action. If no recovery action can be performed, the operating
system must reset the system.
•
When the OVER flag in the IA32_MCi_STATUS register is set for the SRAR error (VAL=1, UC=1, EN=1, PCC=0,
S=1 and AR=1), the MCE handler cannot take recovery action as the information of the SRAR error in the
IA32_MCi_STATUS register was potentially lost due to the overflow condition. Since the recovery action for
SRAR errors must be taken, the MCE handler must signal the operating system to reset the system.
•
When the MCE handler cannot find any uncorrected (VAL=1, UC=1 and EN=1) or any software recoverable
errors (VAL=1, UC=1, EN=1, PCC=0 and S=1) in any of the IA32_MCi banks of the processors, this is an
unexpected condition for the MCE handler and the handler should signal the operating system to reset the
system.
•
Before returning from the machine-check exception handler, software must clear the MCIP flag in the
IA32_MCG_STATUS register. The MCIP flag is used to detect recursion. The machine-check architecture does
not support recursion. When the processor receives a machine check when MCIP is set, it automatically enters
the shutdown state.
Example 15-4 gives pseudocode for an MC exception handler that supports recovery of UCR.
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MACHINE-CHECK ARCHITECTURE
Example 15-4. Machine-Check Error Handler Pseudocode Supporting UCR
MACHINE CHECK HANDLER: (* Called from INT 18 handler *)
NOERROR = TRUE;
ProcessorCount = 0;
IF CPU supports MCA
THEN
RESTARTABILITY = TRUE;
IF (Processor Family = 6 AND DisplayModel ≥ 0EH) OR (Processor Family > 6)
THEN
IF ( MCG_LMCE = 1)
MCA_BROADCAST = FALSE;
ELSE
MCA_BROADCAST = TRUE;
FI;
Acquire SpinLock;
ProcessorCount++; (* Allowing one logical processor at a time to examine machine check registers *)
CALL MCA ERROR PROCESSING; (* returns RESTARTABILITY and NOERROR *)
ELSE
MCA_BROADCAST = FALSE;
(* Implement a rendezvous mechanism with the other processors if necessary *)
CALL MCA ERROR PROCESSING;
FI;
ELSE (* Pentium(R) processor compatible *)
READ P5_MC_ADDR
READ P5_MC_TYPE;
RESTARTABILITY = FALSE;
FI;
IF NOERROR = TRUE
THEN
IF NOT (MCG_RIPV = 1 AND MCG_EIPV = 0)
THEN
RESTARTABILITY = FALSE;
FI
FI;
IF RESTARTABILITY = FALSE
THEN
Report RESTARTABILITY to console;
Reset system;
FI;
IF MCA_BROADCAST = TRUE
THEN
IF ProcessorCount = MAX_PROCESSORS
AND NOERROR = TRUE
THEN
Report RESTARTABILITY to console;
Reset system;
FI;
Release SpinLock;
Wait till ProcessorCount = MAX_PROCESSRS on system;
(* implement a timeout and abort function if necessary *)
FI;
CLEAR IA32_MCG_STATUS;
RESUME Execution;
(* End of MACHINE CHECK HANDLER*)
MCA ERROR PROCESSING: (* MCA Error Processing Routine called from MCA Handler *)
IF MCIP flag in IA32_MCG_STATUS = 0
THEN (* MCIP=0 upon MCA is unexpected *)
RESTARTABILITY = FALSE;
FI;
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MACHINE-CHECK ARCHITECTURE
FOR each bank of machine-check registers
DO
CLEAR_MC_BANK = FALSE;
READ IA32_MCi_STATUS;
IF VAL Flag in IA32_MCi_STATUS = 1
THEN
IF UC Flag in IA32_MCi_STATUS = 1
THEN
IF Bit 24 in IA32_MCG_CAP = 0
THEN (* the processor does not support software error recovery *)
RESTARTABILITY = FALSE;
NOERROR = FALSE;
GOTO LOG MCA REGISTER;
FI;
(* the processor supports software error recovery *)
IF EN Flag in IA32_MCi_STATUS = 0 AND OVER Flag in IA32_MCi_STATUS=0
THEN (* It is a spurious MCA Log. Log and clear the register *)
CLEAR_MC_BANK = TRUE;
GOTO LOG MCA REGISTER;
FI;
IF PCC = 1 and EN = 1 in IA32_MCi_STATUS
THEN (* processor context might have been corrupted *)
RESTARTABILITY = FALSE;
ELSE (* It is a uncorrected recoverable (UCR) error *)
IF S Flag in IA32_MCi_STATUS = 0
THEN
IF AR Flag in IA32_MCi_STATUS = 0
THEN (* It is a uncorrected no action required (UCNA) error *)
GOTO CONTINUE; (* let CMCI and CMC polling handler to process *)
ELSE
RESTARTABILITY = FALSE; (* S=0, AR=1 is illegal *)
FI
FI;
IF RESTARTABILITY = FALSE
THEN (* no need to take recovery action if RESTARTABILITY is already false *)
NOERROR = FALSE;
GOTO LOG MCA REGISTER;
FI;
(* S in IA32_MCi_STATUS = 1 *)
IF AR Flag in IA32_MCi_STATUS = 1
THEN (* It is a software recoverable and action required (SRAR) error *)
IF OVER Flag in IA32_MCi_STATUS = 1
THEN
RESTARTABILITY = FALSE;
NOERROR = FALSE;
GOTO LOG MCA REGISTER;
FI
IF MCACOD Value in IA32_MCi_STATUS is recognized
AND Current Processor is an Affected Processor
THEN
Implement MCACOD specific recovery action;
CLEAR_MC_BANK = TRUE;
ELSE
RESTARTABILITY = FALSE;
FI;
ELSE (* It is a software recoverable and action optional (SRAO) error *)
IF OVER Flag in IA32_MCi_STATUS = 0 AND
MCACOD in IA32_MCi_STATUS is recognized
THEN
Implement MCACOD specific recovery action;
FI;
CLEAR_MC_BANK = TRUE;
FI; AR
FI; PCC
NOERROR = FALSE;
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MACHINE-CHECK ARCHITECTURE
GOTO LOG MCA REGISTER;
ELSE (* It is a corrected error; continue to the next IA32_MCi_STATUS *)
GOTO CONTINUE;
FI; UC
FI; VAL
LOG MCA REGISTER:
SAVE IA32_MCi_STATUS;
If MISCV in IA32_MCi_STATUS
THEN
SAVE IA32_MCi_MISC;
FI;
IF ADDRV in IA32_MCi_STATUS
THEN
SAVE IA32_MCi_ADDR;
FI;
IF CLEAR_MC_BANK = TRUE
THEN
SET all 0 to IA32_MCi_STATUS;
If MISCV in IA32_MCi_STATUS
THEN
SET all 0 to IA32_MCi_MISC;
FI;
IF ADDRV in IA32_MCi_STATUS
THEN
SET all 0 to IA32_MCi_ADDR;
FI;
FI;
CONTINUE:
OD;
( *END FOR *)
RETURN;
(* End of MCA ERROR PROCESSING*)
15.10.4.2 Corrected Machine-Check Handler for Error Recovery
When writing a corrected machine check handler, which is invoked as a result of CMCI or called from an OS CMC
Polling dispatcher, consider the following:
•
The VAL (valid) flag in each IA32_MCi_STATUS register indicates whether the error information in the register
is valid. If this flag is clear, the registers in that bank does not contain valid error information and does not need
to be checked.
•
The CMCI or CMC polling handler is responsible for logging and clearing corrected errors. The UC flag in each
IA32_MCi_Status register indicates whether the reported error was corrected (UC=0) or not (UC=1).
•
When IA32_MCG_CAP [24] is one, the CMC handler is also responsible for logging and clearing uncorrected noaction required (UCNA) errors. When the UC flag is one but the PCC, S, and AR flags are zero in the
IA32_MCi_STATUS register, the reported error in this bank is an uncorrected no-action required (UCNA) error.
In cases when SRAO error are signaled as UCNA error via CMCI, software can perform recovery for those errors
identified in Table 15-15.
•
In addition to corrected errors and UCNA errors, the CMC handler optionally logs uncorrected (UC=1 and
PCC=1), software recoverable machine check errors (UC=1, PCC=0 and S=1), but should avoid clearing those
errors from the MC banks. Clearing these errors may result in accidentally removing these errors before these
errors are actually handled and processed by the MCE handler for attempted software error recovery.
Example 15-5 gives pseudocode for a CMCI handler with UCR support.
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MACHINE-CHECK ARCHITECTURE
Example 15-5. Corrected Error Handler Pseudocode with UCR Support
Corrected Error HANDLER: (* Called from CMCI handler or OS CMC Polling Dispatcher*)
IF CPU supports MCA
THEN
FOR each bank of machine-check registers
DO
READ IA32_MCi_STATUS;
IF VAL flag in IA32_MCi_STATUS = 1
THEN
IF UC Flag in IA32_MCi_STATUS = 0 (* It is a corrected error *)
THEN
GOTO LOG CMC ERROR;
ELSE
IF Bit 24 in IA32_MCG_CAP = 0
THEN
GOTO CONTINUE;
FI;
IF S Flag in IA32_MCi_STATUS = 0 AND AR Flag in IA32_MCi_STATUS = 0
THEN (* It is a uncorrected no action required error *)
GOTO LOG CMC ERROR
FI
IF EN Flag in IA32_MCi_STATUS = 0
THEN (* It is a spurious MCA error *)
GOTO LOG CMC ERROR
FI;
FI;
FI;
GOTO CONTINUE;
LOG CMC ERROR:
SAVE IA32_MCi_STATUS;
If MISCV Flag in IA32_MCi_STATUS
THEN
SAVE IA32_MCi_MISC;
SET all 0 to IA32_MCi_MISC;
FI;
IF ADDRV Flag in IA32_MCi_STATUS
THEN
SAVE IA32_MCi_ADDR;
SET all 0 to IA32_MCi_ADDR
FI;
SET all 0 to IA32_MCi_STATUS;
CONTINUE:
OD;
( *END FOR *)
FI;
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15-36 Vol. 3B
CHAPTER 16
INTERPRETING MACHINE-CHECK
ERROR CODES
Encoding of the model-specific and other information fields is different across processor families. The differences
are documented in the following sections.
16.1
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 06H
MACHINE ERROR CODES FOR MACHINE CHECK
Section 16.1 provides information for interpreting additional model-specific fields for external bus errors relating to
processor family 06H. The references to processor family 06H refers to only IA-32 processors with CPUID signatures listed in Table 16-1.
Table 16-1. CPUID DisplayFamily_DisplayModel Signatures for Processor Family 06H
DisplayFamily_DisplayModel
Processor Families/Processor Number Series
06_0EH
Intel Core Duo, Intel Core Solo processors
06_0DH
Intel Pentium M processor
06_09H
Intel Pentium M processor
06_7H, 06_08H, 06_0AH, 06_0BH
Intel Pentium III Xeon Processor, Intel Pentium III Processor
06_03H, 06_05H
Intel Pentium II Xeon Processor, Intel Pentium II Processor
06_01H
Intel Pentium Pro Processor
These errors are reported in the IA32_MCi_STATUS MSRs. They are reported architecturally as compound errors
with a general form of 0000 1PPT RRRR IILL in the MCA error code field. See Chapter 15 for information on the
interpretation of compound error codes. Incremental decoding information is listed in Table 16-2.
Table 16-2. Incremental Decoding Information: Processor Family 06H Machine Error Codes For Machine Check
Type
Bit No.
Bit Function
Bit Description
MCA error
codes1
15:0
Model specific
errors
18:16
Reserved
Reserved
Model specific
errors
24:19
Bus queue request
type
000000 for BQ_DCU_READ_TYPE error
000010 for BQ_IFU_DEMAND_TYPE error
000011 for BQ_IFU_DEMAND_NC_TYPE error
000100 for BQ_DCU_RFO_TYPE error
000101 for BQ_DCU_RFO_LOCK_TYPE error
000110 for BQ_DCU_ITOM_TYPE error
001000 for BQ_DCU_WB_TYPE error
001010 for BQ_DCU_WCEVICT_TYPE error
001011 for BQ_DCU_WCLINE_TYPE error
001100 for BQ_DCU_BTM_TYPE error
Vol. 3B 16-1
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-2. Incremental Decoding Information: Processor Family 06H Machine Error Codes For Machine Check
Type
Bit No.
Bit Function
Bit Description
001101 for BQ_DCU_INTACK_TYPE error
001110 for BQ_DCU_INVALL2_TYPE error
001111 for BQ_DCU_FLUSHL2_TYPE error
010000 for BQ_DCU_PART_RD_TYPE error
010010 for BQ_DCU_PART_WR_TYPE error
010100 for BQ_DCU_SPEC_CYC_TYPE error
011000 for BQ_DCU_IO_RD_TYPE error
011001 for BQ_DCU_IO_WR_TYPE error
011100 for BQ_DCU_LOCK_RD_TYPE error
011110 for BQ_DCU_SPLOCK_RD_TYPE error
011101 for BQ_DCU_LOCK_WR_TYPE error
Model specific
errors
27:25
Bus queue error type
000 for BQ_ERR_HARD_TYPE error
001 for BQ_ERR_DOUBLE_TYPE error
010 for BQ_ERR_AERR2_TYPE error
100 for BQ_ERR_SINGLE_TYPE error
101 for BQ_ERR_AERR1_TYPE error
Model specific
errors
Other
information
28
FRC error
1 if FRC error active
29
BERR
1 if BERR is driven
30
Internal BINIT
1 if BINIT driven for this processor
31
Reserved
Reserved
34:32
Reserved
Reserved
35
External BINIT
1 if BINIT is received from external bus.
36
Response parity error This bit is asserted in IA32_MCi_STATUS if this component has received a parity
error on the RS[2:0]# pins for a response transaction. The RS signals are checked
by the RSP# external pin.
37
Bus BINIT
This bit is asserted in IA32_MCi_STATUS if this component has received a hard
error response on a split transaction one access that has needed to be split across
the 64-bit external bus interface into two accesses).
38
Timeout BINIT
This bit is asserted in IA32_MCi_STATUS if this component has experienced a ROB
time-out, which indicates that no micro-instruction has been retired for a
predetermined period of time.
A ROB time-out occurs when the 15-bit ROB time-out counter carries a 1 out of its
high order bit. 2 The timer is cleared when a micro-instruction retires, an exception
is detected by the core processor, RESET is asserted, or when a ROB BINIT occurs.
The ROB time-out counter is prescaled by the 8-bit PIC timer which is a divide by
128 of the bus clock the bus clock is 1:2, 1:3, 1:4 of the core clock). When a carry
out of the 8-bit PIC timer occurs, the ROB counter counts up by one. While this bit
is asserted, it cannot be overwritten by another error.
16-2 Vol. 3B
41:39
Reserved
Reserved
42
Hard error
This bit is asserted in IA32_MCi_STATUS if this component has initiated a bus
transactions which has received a hard error response. While this bit is asserted, it
cannot be overwritten.
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-2. Incremental Decoding Information: Processor Family 06H Machine Error Codes For Machine Check
Type
Bit No.
Bit Function
Bit Description
43
IERR
This bit is asserted in IA32_MCi_STATUS if this component has experienced a
failure that causes the IERR pin to be asserted. While this bit is asserted, it cannot
be overwritten.
44
AERR
This bit is asserted in IA32_MCi_STATUS if this component has initiated 2 failing
bus transactions which have failed due to Address Parity Errors AERR asserted).
While this bit is asserted, it cannot be overwritten.
45
UECC
The Uncorrectable ECC error bit is asserted in IA32_MCi_STATUS for uncorrected
ECC errors. While this bit is asserted, the ECC syndrome field will not be
overwritten.
46
CECC
The correctable ECC error bit is asserted in IA32_MCi_STATUS for corrected ECC
errors.
54:47
ECC syndrome
The ECC syndrome field in IA32_MCi_STATUS contains the 8-bit ECC syndrome only
if the error was a correctable/uncorrectable ECC error and there wasn't a previous
valid ECC error syndrome logged in IA32_MCi_STATUS.
A previous valid ECC error in IA32_MCi_STATUS is indicated by
IA32_MCi_STATUS.bit45 uncorrectable error occurred) being asserted. After
processing an ECC error, machine-check handling software should clear
IA32_MCi_STATUS.bit45 so that future ECC error syndromes can be logged.
56:55
Status register
validity
indicators1
Reserved
Reserved.
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
2. For processors with a CPUID signature of 06_0EH, a ROB time-out occurs when the 23-bit ROB time-out counter carries a 1 out of its
high order bit.
16.2
INCREMENTAL DECODING INFORMATION: INTEL CORE 2 PROCESSOR
FAMILY MACHINE ERROR CODES FOR MACHINE CHECK
Table 16-4 provides information for interpreting additional model-specific fields for external bus errors relating to
processor based on Intel Core microarchitecture, which implements the P4 bus specification. Table 16-3 lists the
CPUID signatures for Intel 64 processors that are covered by Table 16-4. These errors are reported in the
IA32_MCi_STATUS MSRs. They are reported architecturally as compound errors with a general form of
0000 1PPT RRRR IILL in the MCA error code field. See Chapter 15 for information on the interpretation of
compound error codes.
Table 16-3. CPUID DisplayFamily_DisplayModel Signatures for Processors Based on Intel Core Microarchitecture
DisplayFamily_DisplayModel Processor Families/Processor Number Series
06_1DH
Intel Xeon Processor 7400 series.
06_17H
Intel Xeon Processor 5200, 5400 series, Intel Core 2 Quad processor Q9650.
06_0FH
Intel Xeon Processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad, Intel Core 2 Extreme,
Intel Core 2 Duo processors, Intel Pentium dual-core processors.
Vol. 3B 16-3
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-4. Incremental Bus Error Codes of Machine Check for Processors
Based on Intel Core Microarchitecture
Type
Bit No.
Bit Function
Bit Description
MCA error
codes1
15:0
Model specific
errors
18:16
Reserved
Reserved
Model specific
errors
24:19
Bus queue request
type
‘000001 for BQ_PREF_READ_TYPE error
000000 for BQ_DCU_READ_TYPE error
000010 for BQ_IFU_DEMAND_TYPE error
000011 for BQ_IFU_DEMAND_NC_TYPE error
000100 for BQ_DCU_RFO_TYPE error
000101 for BQ_DCU_RFO_LOCK_TYPE error
000110 for BQ_DCU_ITOM_TYPE error
001000 for BQ_DCU_WB_TYPE error
001010 for BQ_DCU_WCEVICT_TYPE error
001011 for BQ_DCU_WCLINE_TYPE error
001100 for BQ_DCU_BTM_TYPE error
001101 for BQ_DCU_INTACK_TYPE error
001110 for BQ_DCU_INVALL2_TYPE error
001111 for BQ_DCU_FLUSHL2_TYPE error
010000 for BQ_DCU_PART_RD_TYPE error
010010 for BQ_DCU_PART_WR_TYPE error
010100 for BQ_DCU_SPEC_CYC_TYPE error
011000 for BQ_DCU_IO_RD_TYPE error
011001 for BQ_DCU_IO_WR_TYPE error
011100 for BQ_DCU_LOCK_RD_TYPE error
011110 for BQ_DCU_SPLOCK_RD_TYPE error
011101 for BQ_DCU_LOCK_WR_TYPE error
100100 for BQ_L2_WI_RFO_TYPE error
100110 for BQ_L2_WI_ITOM_TYPE error
Model specific
errors
27:25
Bus queue error type
‘001 for Address Parity Error
Model specific
errors
28
MCE Driven
1 if MCE is driven
29
MCE Observed
1 if MCE is observed
30
Internal BINIT
1 if BINIT driven for this processor
31
BINIT Observed
1 if BINIT is observed for this processor
33:32
Reserved
Reserved
34
PIC and FSB data
parity
Data Parity detected on either PIC or FSB access
35
Reserved
Reserved
‘010 for Response Hard Error
‘011 for Response Parity Error
Other
information
16-4 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-4. Incremental Bus Error Codes of Machine Check for Processors
Based on Intel Core Microarchitecture (Contd.)
Type
Bit No.
Bit Function
Bit Description
36
Response parity error This bit is asserted in IA32_MCi_STATUS if this component has received a parity
error on the RS[2:0]# pins for a response transaction. The RS signals are checked
by the RSP# external pin.
37
FSB address parity
Address parity error detected:
1 = Address parity error detected
0 = No address parity error
38
Timeout BINIT
This bit is asserted in IA32_MCi_STATUS if this component has experienced a ROB
time-out, which indicates that no micro-instruction has been retired for a
predetermined period of time.
A ROB time-out occurs when the 23-bit ROB time-out counter carries a 1 out of its
high order bit. The timer is cleared when a micro-instruction retires, an exception is
detected by the core processor, RESET is asserted, or when a ROB BINIT occurs.
The ROB time-out counter is prescaled by the 8-bit PIC timer which is a divide by
128 of the bus clock the bus clock is 1:2, 1:3, 1:4 of the core clock). When a carry
out of the 8-bit PIC timer occurs, the ROB counter counts up by one. While this bit
is asserted, it cannot be overwritten by another error.
Status register
validity
indicators1
41:39
Reserved
Reserved
42
Hard error
This bit is asserted in IA32_MCi_STATUS if this component has initiated a bus
transactions which has received a hard error response. While this bit is asserted, it
cannot be overwritten.
43
IERR
This bit is asserted in IA32_MCi_STATUS if this component has experienced a
failure that causes the IERR pin to be asserted. While this bit is asserted, it cannot
be overwritten.
44
Reserved
Reserved
45
Reserved
Reserved
46
Reserved
Reserved
54:47
Reserved
Reserved
56:55
Reserved
Reserved.
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.2.1
Model-Specific Machine Check Error Codes for Intel Xeon Processor 7400 Series
Intel Xeon processor 7400 series has machine check register banks that generally follows the description of
Chapter 15 and Section 16.2. Additional error codes specific to Intel Xeon processor 7400 series is describe in this
section.
MC4_STATUS[63:0] is the main error logging for the processor’s L3 and front side bus errors for Intel Xeon
processor 7400 series. It supports the L3 Errors, Bus and Interconnect Errors Compound Error Codes in the MCA
Error Code Field.
Vol. 3B 16-5
INTERPRETING MACHINE-CHECK ERROR CODES
16.2.1.1
Processor Machine Check Status Register
Incremental MCA Error Code Definition
Intel Xeon processor 7400 series use compound MCA Error Codes for logging its Bus internal machine check
errors, L3 Errors, and Bus/Interconnect Errors. It defines incremental Machine Check error types
(IA32_MC6_STATUS[15:0]) beyond those defined in Chapter 15. Table 16-5 lists these incremental MCA error
code types that apply to IA32_MC6_STATUS. Error code details are specified in MC6_STATUS [31:16] (see
Section 16.2.2), the “Model Specific Error Code” field. The information in the “Other_Info” field
(MC4_STATUS[56:32]) is common to the three processor error types and contains a correctable event count and
specifies the MC6_MISC register format.
Table 16-5. Incremental MCA Error Code Types for Intel Xeon Processor 7400
Processor MCA_Error_Code (MC6_STATUS[15:0])
Type
Error Code
Binary Encoding
Meaning
C
Internal Error
0000 0100 0000 0000 Internal Error Type Code
B
Bus and
Interconnect
0000 100x 0000 1111
Not used but this encoding is reserved for compatibility with other MCA
implementations
Error
0000 101x 0000 1111
Not used but this encoding is reserved for compatibility with other MCA
implementations
0000 110x 0000 1111
Not used but this encoding is reserved for compatibility with other MCA
implementations
0000 1110 0000 1111 Bus and Interconnection Error Type Code
0000 1111 0000 1111 Not used but this encoding is reserved for compatibility with other MCA
implementations
The Bold faced binary encodings are the only encodings used by the processor for MC4_STATUS[15:0].
16.2.2
Intel Xeon Processor 7400 Model Specific Error Code Field
16.2.2.1
Processor Model Specific Error Code Field
Type B: Bus and Interconnect Error
Note:
The Model Specific Error Code field in MC6_STATUS (bits 31:16).
Table 16-6. Type B Bus and Interconnect Error Codes
Bit Num
Sub-Field Name
Description
16
FSB Request Parity
Parity error detected during FSB request phase
19:17
Reserved
20
FSB Hard Fail Response
“Hard Failure“ response received for a local transaction
21
FSB Response Parity
Parity error on FSB response field detected
22
FSB Data Parity
FSB data parity error on inbound data detected
31:23
---
Reserved
16-6 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
16.2.2.2
Processor Model Specific Error Code Field
Type C: Cache Bus Controller Error
Table 16-7. Type C Cache Bus Controller Error Codes
MC4_STATUS[31:16] (MSCE) Value
Error Description
0000_0000_0000_0001 0001H
Inclusion Error from Core 0
0000_0000_0000_0010 0002H
Inclusion Error from Core 1
0000_0000_0000_0011 0003H
Write Exclusive Error from Core 0
0000_0000_0000_0100 0004H
Write Exclusive Error from Core 1
0000_0000_0000_0101 0005H
Inclusion Error from FSB
0000_0000_0000_0110 0006H
SNP Stall Error from FSB
0000_0000_0000_0111 0007H
Write Stall Error from FSB
0000_0000_0000_1000 0008H
FSB Arb Timeout Error
0000_0000_0000_1010 000AH
Inclusion Error from Core 2
0000_0000_0000_1011 000BH
Write Exclusive Error from Core 2
0000_0010_0000_0000 0200H
Internal Timeout error
0000_0011_0000_0000 0300H
Internal Timeout Error
0000_0100_0000_0000 0400H
Intel® Cache Safe Technology Queue Full Error or Disabled-ways-in-a-set overflow
0000_0101_0000_0000 0500H
Quiet cycle Timeout Error (correctable)
1100_0000_0000_0010 C002H
Correctable ECC event on outgoing Core 0 data
1100_0000_0000_0100 C004H
Correctable ECC event on outgoing Core 1 data
1100_0000_0000_1000 C008H
Correctable ECC event on outgoing Core 2 data
1110_0000_0000_0010 E002H
Uncorrectable ECC error on outgoing Core 0 data
1110_0000_0000_0100 E004H
Uncorrectable ECC error on outgoing Core 1 data
1110_0000_0000_1000 E008H
Uncorrectable ECC error on outgoing Core 2 data
— all other encodings —
Reserved
16.3
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH
CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_1AH, MACHINE
ERROR CODES FOR MACHINE CHECK
Table 16-8 through Table 16-12 provide information for interpreting additional model-specific fields for memory
controller errors relating to the processor family with CPUID DisplayFamily_DisplaySignature 06_1AH, which
supports Intel QuickPath Interconnect links. Incremental MC error codes related to the Intel QPI links are reported
in the register banks IA32_MC0 and IA32_MC1, incremental error codes for internal machine check is reported in
the register bank IA32_MC7, and incremental error codes for the memory controller unit is reported in the register
banks IA32_MC8.
Vol. 3B 16-7
INTERPRETING MACHINE-CHECK ERROR CODES
16.3.1
Intel QPI Machine Check Errors
Table 16-8. Intel QPI Machine Check Error Codes for IA32_MC0_STATUS and IA32_MC1_STATUS
Type
1
MCA error codes
Bit No.
Bit Function
Bit Description
15:0
MCACOD
Bus error format: 1PPTRRRRIILL
16
Header Parity
if 1, QPI Header had bad parity
17
Data Parity
If 1, QPI Data packet had bad parity
18
Retries Exceeded
If 1, number of QPI retries was exceeded
19
Received Poison
if 1, Received a data packet that was marked as poisoned by the sender
21:20
Reserved
Reserved
22
Unsupported Message
If 1, QPI received a message encoding it does not support
23
Unsupported Credit
If 1, QPI credit type is not supported.
24
Receive Flit Overrun
If 1, Sender sent too many QPI flits to the receiver.
25
Received Failed
Response
If 1, Indicates that sender sent a failed response to receiver.
26
Receiver Clock Jitter
If 1, clock jitter detected in the internal QPI clocking
56:27
Reserved
Reserved
Model specific errors
Status register
validity indicators1
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
Table 16-9. Intel QPI Machine Check Error Codes for IA32_MC0_MISC and IA32_MC1_MISC
Type
Model specific
Bit No.
Bit Function
Bit Description
7:0
QPI Opcode
Message class and opcode from the packet with the error
13:8
RTId
QPI Request Transaction ID
15:14
Reserved
Reserved
18:16
RHNID
QPI Requestor/Home Node ID
23:19
Reserved
Reserved
24
IIB
QPI Interleave/Head Indication Bit
errors1
NOTES:
1. Which of these fields are valid depends on the error type.
16.3.2
Internal Machine Check Errors
Table 16-10. Machine Check Error Codes for IA32_MC7_STATUS
Type
Bit No.
Bit Function
MCA error codes1
15:0
MCACOD
Model specific errors
16-8 Vol. 3B
Bit Description
INTERPRETING MACHINE-CHECK ERROR CODES
Type
Bit No.
Bit Function
Bit Description
23:16
Reserved
Reserved
31:24
Reserved except for
the following
00h - No Error
03h - Reset firmware did not complete
08h - Received an invalid CMPD
0Ah - Invalid Power Management Request
0Dh - Invalid S-state transition
11h - VID controller does not match POC controller selected
1Ah - MSID from POC does not match CPU MSID
56:32
Status register validity
indicators1
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.3.3
Memory Controller Errors
Table 16-11. Incremental Memory Controller Error Codes of Machine Check for IA32_MC8_STATUS
Type
MCA error
codes1
Bit No.
Bit Function
Bit Description
15:0
MCACOD
Memory error format: 1MMMCCCC
16
Read ECC error
if 1, ECC occurred on a read
17
RAS ECC error
If 1, ECC occurred on a scrub
18
Write parity error
If 1, bad parity on a write
19
Redundancy loss
if 1, Error in half of redundant memory
20
Reserved
Reserved
21
Memory range error
If 1, Memory access out of range
22
RTID out of range
If 1, Internal ID invalid
23
Address parity error
If 1, bad address parity
24
Byte enable parity
error
If 1, bad enable parity
37:25
Reserved
Reserved
52:38
CORE_ERR_CNT
Corrected error count
56:53
Reserved
Reserved
Model specific errors
Other information
Status register validity
indicators1
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
Vol. 3B 16-9
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-12. Incremental Memory Controller Error Codes of Machine Check for IA32_MC8_MISC
Type
Model specific
Bit No.
Bit Function
Bit Description
7:0
RTId
Transaction Tracker ID
15:8
Reserved
Reserved
17:16
DIMM
DIMM ID which got the error
19:18
Channel
Channel ID which got the error
31:20
Reserved
Reserved
63:32
Syndrome
ECC Syndrome
errors1
NOTES:
1. Which of these fields are valid depends on the error type.
16.4
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID
DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_2DH, MACHINE ERROR
CODES FOR MACHINE CHECK
Table 16-13 through Table 16-15 provide information for interpreting additional model-specific fields for memory
controller errors relating to the processor family with CPUID DisplayFamily_DisplaySignature 06_2DH, which
supports Intel QuickPath Interconnect links. Incremental MC error codes related to the Intel QPI links are reported
in the register banks IA32_MC6 and IA32_MC7, incremental error codes for internal machine check error from PCU
controller is reported in the register bank IA32_MC4, and incremental error codes for the memory controller unit is
reported in the register banks IA32_MC8-IA32_MC11.
16.4.1
Internal Machine Check Errors
Table 16-13. Machine Check Error Codes for IA32_MC4_STATUS
Type
Bit No.
Bit Function
MCA error
codes1
15:0
MCACOD
Model specific
errors
19:16
Reserved except for
the following
Bit Description
0000b - No Error
0001b - Non_IMem_Sel
0010b - I_Parity_Error
0011b - Bad_OpCode
0100b - I_Stack_Underflow
0101b - I_Stack_Overflow
0110b - D_Stack_Underflow
0111b - D_Stack_Overflow
1000b - Non-DMem_Sel
1001b - D_Parity_Error
16-10 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
Type
Bit No.
Bit Function
Bit Description
23:20
Reserved
Reserved
31:24
Reserved except for
the following
00h - No Error
0Dh - MC_IMC_FORCE_SR_S3_TIMEOUT
0Eh - MC_CPD_UNCPD_ST_TIMEOUT
0Fh - MC_PKGS_SAFE_WP_TIMEOUT
43h - MC_PECI_MAILBOX_QUIESCE_TIMEOUT
5Ch - MC_MORE_THAN_ONE_LT_AGENT
60h - MC_INVALID_PKGS_REQ_PCH
61h - MC_INVALID_PKGS_REQ_QPI
62h - MC_INVALID_PKGS_RES_QPI
63h - MC_INVALID_PKGC_RES_PCH
64h - MC_INVALID_PKG_STATE_CONFIG
70h - MC_WATCHDG_TIMEOUT_PKGC_SLAVE
71h - MC_WATCHDG_TIMEOUT_PKGC_MASTER
72h - MC_WATCHDG_TIMEOUT_PKGS_MASTER
7ah - MC_HA_FAILSTS_CHANGE_DETECTED
81h - MC_RECOVERABLE_DIE_THERMAL_TOO_HOT
56:32
Status register
validity
indicators1
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.4.2
Intel QPI Machine Check Errors
Table 16-14. Intel QPI MC Error Codes for IA32_MC6_STATUS and IA32_MC7_STATUS
Type
Bit No.
Bit Function
Bit Description
MCA error
codes1
15:0
MCACOD
Bus error format: 1PPTRRRRIILL
56:16
Reserved
Reserved
Model specific
errors
Status register
validity
indicators1
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.4.3
Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC8_STATUSIA32_MC11_STATUS. The supported error codes are follows the architectural MCACOD definition type 1MMMCCCC
(see Chapter 15, “Machine-Check Architecture,”). MSR_ERROR_CONTROL.[bit 1] can enable additional informaVol. 3B 16-11
INTERPRETING MACHINE-CHECK ERROR CODES
tion logging of the IMC. The additional error information logged by the IMC is stored in IA32_MCi_STATUS and
IA32_MCi_MISC; (i = 8, 11).
Table 16-15. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 8, 11)
Type
Bit No.
Bit Function
Bit Description
15:0
MCACOD
Bus error format: 1PPTRRRRIILL
Model specific
errors
31:16
Reserved except for
the following
001H - Address parity error
002H - HA Wrt buffer Data parity error
004H - HA Wrt byte enable parity error
008H - Corrected patrol scrub error
010H - Uncorrected patrol scrub error
020H - Corrected spare error
040H - Uncorrected spare error
Model specific
errors
36:32
Other info
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first device
error when corrected error is detected during normal read.
37
Reserved
Reserved
MCA error
codes1
56:38
Status register
validity indicators1
See Chapter 15, “Machine-Check Architecture,”
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
Table 16-16. Intel IMC MC Error Codes for IA32_MCi_MISC (i= 8, 11)
Type
Bit No.
MCA addr info1
Bit Function
Bit Description
8:0
See Chapter 15, “Machine-Check Architecture,”
Model specific
errors
13:9
• When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second device
error when corrected error is detected during normal read.
• Otherwise contain parity error if MCi_Status indicates HA_WB_Data or
HA_W_BE parity error.
Model specific
errors
29:14
ErrMask_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error bit
mask.
Model specific
errors
45:30
ErrMask_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error
bit mask.
50:46
FailRank_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error
failing rank.
55:51
FailRank_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error
failing rank.
58:56
Reserved
Reserved
61:59
Reserved
Reserved
62
Valid_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data
from the first correctable error in a memory device.
63
Valid_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data due
to a second correctable error in a memory device. Use this information only after
there is valid first error info indicated by bit 62.
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16-12 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
16.5
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH
CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_3EH, MACHINE
ERROR CODES FOR MACHINE CHECK
Intel Xeon processor E5 v2 family and Intel Xeon processor E7 v2 family are based on the Ivy Bridge-EP microarchitecture and can be identified with CPUID DisplayFamily_DisplaySignature 06_3EH. Incremental error codes for
internal machine check error from PCU controller is reported in the register bank IA32_MC4, Table lists modelspecific fields to interpret error codes applicable to IA32_MC4_STATUS. Incremental MC error codes related to the
Intel QPI links are reported in the register banks IA32_MC5. Information listed in Table 16-14 for QPI MC error code
apply to IA32_MC5_STATUS. Incremental error codes for the memory controller unit is reported in the register
banks IA32_MC9-IA32_MC16. Table 16-18 lists model-specific error codes apply to IA32_MCi_STATUS, i = 9-16.
16.5.1
Internal Machine Check Errors
Table 16-17. Machine Check Error Codes for IA32_MC4_STATUS
Type
MCA error
codes1
Model specific errors
Bit No.
Bit Function
15:0
MCACOD
19:16
Reserved except for
the following
Bit Description
0000b - No Error
0001b - Non_IMem_Sel
0010b - I_Parity_Error
0011b - Bad_OpCode
0100b - I_Stack_Underflow
0101b - I_Stack_Overflow
0110b - D_Stack_Underflow
0111b - D_Stack_Overflow
1000b - Non-DMem_Sel
1001b - D_Parity_Error
23:20
Reserved
Reserved
31:24
Reserved except for
the following
00h - No Error
0Dh - MC_IMC_FORCE_SR_S3_TIMEOUT
0Eh - MC_CPD_UNCPD_ST_TIMEOUT
0Fh - MC_PKGS_SAFE_WP_TIMEOUT
43h - MC_PECI_MAILBOX_QUIESCE_TIMEOUT
44h - MC_CRITICAL_VR_FAILED
45h - MC_ICC_MAX-NOTSUPPORTED
5Ch - MC_MORE_THAN_ONE_LT_AGENT
60h - MC_INVALID_PKGS_REQ_PCH
61h - MC_INVALID_PKGS_REQ_QPI
62h - MC_INVALID_PKGS_RES_QPI
63h - MC_INVALID_PKGC_RES_PCH
64h - MC_INVALID_PKG_STATE_CONFIG
70h - MC_WATCHDG_TIMEOUT_PKGC_SLAVE
71h - MC_WATCHDG_TIMEOUT_PKGC_MASTER
72h - MC_WATCHDG_TIMEOUT_PKGS_MASTER
Vol. 3B 16-13
INTERPRETING MACHINE-CHECK ERROR CODES
Type
Bit No.
Bit Function
Bit Description
7Ah - MC_HA_FAILSTS_CHANGE_DETECTED
7Bh - MC_PCIE_R2PCIE-RW_BLOCK_ACK_TIMEOUT
81h - MC_RECOVERABLE_DIE_THERMAL_TOO_HOT
56:32
Status register
validity indicators1
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.5.2
Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC9_STATUSIA32_MC16_STATUS. The supported error codes are follows the architectural MCACOD definition type 1MMMCCCC
(see Chapter 15, “Machine-Check Architecture,”).
MSR_ERROR_CONTROL.[bit 1] can enable additional information logging of the IMC. The additional error information logged by the IMC is stored in IA32_MCi_STATUS and IA32_MCi_MISC; (i = 9-16).
Table 16-18. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16)
Type
MCA error
codes1
Model specific
errors
Bit No.
Bit Function
Bit Description
15:0
MCACOD
Memory Controller error format: 000F 0000 1MMM CCCC
31:16
Reserved except for
the following
001H - Address parity error
002H - HA Wrt buffer Data parity error
004H - HA Wrt byte enable parity error
008H - Corrected patrol scrub error
010H - Uncorrected patrol scrub error
020H - Corrected spare error
040H - Uncorrected spare error
080H - Corrected memory read error. (Only applicable with iMC’s “Additional
Error logging” Mode-1 enabled.)
100H - iMC, WDB, parity errors
36:32
Other info
When MSR_ERROR_CONTROL.[1] is set, logs an encoded value from the first error
device.
37
56:38
Status register
validity indicators1
Reserved
Reserved
See Chapter 15, “Machine-Check Architecture,”
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16-14 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-19. Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9-16)
Type
Bit No.
MCA addr info1
8:0
Bit Function
See Chapter 15, “Machine-Check Architecture,”
Model specific
errors
13:9
If the error logged is MCWrDataPar error or MCWrBEPar error, this field is the WDB
ID that has the parity error. OR if the second error logged is a correctable read
error, MC logs the second error device in this field.
Model specific
errors
29:14
ErrMask_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error bit
mask.
Model specific
errors
45:30
ErrMask_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error
bit mask.
50:46
FailRank_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error
failing rank.
55:51
FailRank_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error
failing rank.
61:56
Bit Description
Reserved
62
Valid_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data
from a correctable error from memory read associated with first error device.
63
Valid_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data due
to a second correctable error in a memory device. Use this information only after
there is valid first error info indicated by bit 62.
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.6
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH
CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_3FH, MACHINE
ERROR CODES FOR MACHINE CHECK
Intel Xeon processor E5 v3 family is based on the Haswell-E microarchitecture and can be identified with CPUID
DisplayFamily_DisplaySignature 06_3FH. Incremental error codes for internal machine check error from PCU
controller is reported in the register bank IA32_MC4, Table 16-20 lists model-specific fields to interpret error codes
applicable to IA32_MC4_STATUS. Incremental MC error codes related to the Intel QPI links are reported in the
register banks IA32_MC5, IA32_MC20, and IA32_MC21. Information listed in Table 16-21 for QPI MC error codes.
Incremental error codes for the memory controller unit is reported in the register banks IA32_MC9-IA32_MC16.
Table 16-22 lists model-specific error codes apply to IA32_MCi_STATUS, i = 9-16.
Vol. 3B 16-15
INTERPRETING MACHINE-CHECK ERROR CODES
16.6.1
Internal Machine Check Errors
Table 16-20. Machine Check Error Codes for IA32_MC4_STATUS
Type
1
MCA error codes
2
MCACOD
Bit No.
Bit Function
15:0
MCACOD
15:0
Internal Errors
Bit Description
0402h - PCU internal Errors
0403h - PCU internal Errors
0406h - Intel TXT Errors
0407h - Other UBOX internal Errors.
On an IERR caused by a core 3-strike the IA32_MC3_STATUS (MLC) is copied
to the IA32_MC4_STATUS (After a 3-strike, the core MCA banks will be
unavailable).
Model specific errors
19:16
Reserved except for
the following
0000b - No Error
23:20
Reserved
Reserved
31:24
Reserved except for
the following
00h - No Error
00xxb - PCU internal error
09h - MC_MESSAGE_CHANNEL_TIMEOUT
13h - MC_DMI_TRAINING_TIMEOUT
15h - MC_DMI_CPU_RESET_ACK_TIMEOUT
1Eh - MC_VR_ICC_MAX_LT_FUSED_ICC_MAX
25h - MC_SVID_COMMAND_TIMEOUT
29h - MC_VR_VOUT_MAC_LT_FUSED_SVID
2Bh - MC_PKGC_WATCHDOG_HANG_CBZ_DOWN
2Ch - MC_PKGC_WATCHDOG_HANG_CBZ_UP
44h - MC_CRITICAL_VR_FAILED
46h - MC_VID_RAMP_DOWN_FAILED
49h - MC_SVID_WRITE_REG_VOUT_MAX_FAILED
4Bh - MC_BOOT_VID_TIMEOUT. Timeout setting boot VID for DRAM 0.
4Fh - MC_SVID_COMMAND_ERROR.
52h - MC_FIVR_CATAS_OVERVOL_FAULT.
53h - MC_FIVR_CATAS_OVERCUR_FAULT.
57h - MC_SVID_PKGC_REQUEST_FAILED
58h - MC_SVID_IMON_REQUEST_FAILED
59h - MC_SVID_ALERT_REQUEST_FAILED
62h - MC_INVALID_PKGS_RSP_QPI
64h - MC_INVALID_PKG_STATE_CONFIG
67h - MC_HA_IMC_RW_BLOCK_ACK_TIMEOUT
6Ah - MC_MSGCH_PMREQ_CMP_TIMEOUT
72h - MC_WATCHDG_TIMEOUT_PKGS_MASTER
81h - MC_RECOVERABLE_DIE_THERMAL_TOO_HOT
56:32
Status register
validity indicators1
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16-16 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
2. The internal error codes may be model-specific.
16.6.2
Intel QPI Machine Check Errors
MC error codes associated with the Intel QPI agents are reported in the MSRs IA32_MC5_STATUS,
IA32_MC20_STATUS, and IA32_MC21_STATUS. The supported error codes follow the architectural MCACOD definition type 1PPTRRRRIILL (see Chapter 15, “Machine-Check Architecture,”).
Table 16-21 lists model-specific fields to interpret error codes applicable to IA32_MC5_STATUS,
IA32_MC20_STATUS, and IA32_MC21_STATUS.
Table 16-21. Intel QPI MC Error Codes for IA32_MCi_STATUS (i = 5, 20, 21)
Type
Bit No.
Bit Function
Bit Description
MCA error
codes1
15:0
MCACOD
Bus error format: 1PPTRRRRIILL
Model specific
errors
31:16
MSCOD
02h - Intel QPI physical layer detected drift buffer alarm.
03h - Intel QPI physical layer detected latency buffer rollover.
10h - Intel QPI link layer detected control error from R3QPI.
11h - Rx entered LLR abort state on CRC error.
12h - Unsupported or undefined packet.
13h - Intel QPI link layer control error.
15h - RBT used un-initialized value.
20h - Intel QPI physical layer detected a QPI in-band reset but aborted initialization
21h - Link failover data self-healing
22h - Phy detected in-band reset (no width change).
23h - Link failover clock failover
30h -Rx detected CRC error - successful LLR after Phy re-init.
31h -Rx detected CRC error - successful LLR without Phy re-init.
All other values are reserved.
Status register
validity
indicators1
37:32
Reserved
52:38
Corrected Error Cnt
56:53
Reserved
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.6.3
Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC9_STATUSIA32_MC16_STATUS. The supported error codes follow the architectural MCACOD definition type 1MMMCCCC (see
Chapter 15, “Machine-Check Architecture,”).
MSR_ERROR_CONTROL.[bit 1] can enable additional information logging of the IMC. The additional error information logged by the IMC is stored in IA32_MCi_STATUS and IA32_MCi_MISC; (i = 9-16).
Vol. 3B 16-17
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-22. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16)
Type
Bit No.
Bit Function
Bit Description
MCA error codes1
15:0
MCACOD
Memory Controller error format: 0000 0000 1MMM CCCC
Model specific
errors
31:16
Reserved except for
the following
0001H - DDR3 address parity error
0002H - Uncorrected HA write data error
0004H - Uncorrected HA data byte enable error
0008H - Corrected patrol scrub error
0010H - Uncorrected patrol scrub error
0020H - Corrected spare error
0040H - Uncorrected spare error
0080H - Corrected memory read error. (Only applicable with iMC’s “Additional
Error logging” Mode-1 enabled.)
0100H - iMC, write data buffer parity errors
0200H - DDR4 command address parity error
36:32
Other info
When MSR_ERROR_CONTROL.[1] is set, logs an encoded value from the first error
device.
37
Reserved
56:38
Status register
validity indicators1
Reserved
See Chapter 15, “Machine-Check Architecture,”
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
Table 16-23. Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9-16)
Type
Bit No.
MCA addr info1
Bit Function
8:0
See Chapter 15, “Machine-Check Architecture,”
Model specific
errors
13:9
If the error logged is MCWrDataPar error or MCWrBEPar error, this field is the WDB
ID that has the parity error. OR if the second error logged is a correctable read
error, MC logs the second error device in this field.
Model specific
errors
29:14
ErrMask_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error bit
mask.
Model specific
errors
45:30
ErrMask_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error
bit mask.
50:46
FailRank_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first-device error
failing rank.
55:51
FailRank_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second-device error
failing rank.
61:56
16-18 Vol. 3B
Bit Description
Reserved
62
Valid_1stErrDev
When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data
from a correctable error from memory read associated with first error device.
63
Valid_2ndErrDev
When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid data due
to a second correctable error in a memory device. Use this information only after
there is valid first error info indicated by bit 62.
INTERPRETING MACHINE-CHECK ERROR CODES
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.7
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH
CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_56H, MACHINE
ERROR CODES FOR MACHINE CHECK
Intel Xeon processor D family is based on the Broadwell microarchitecture and can be identified with CPUID
DisplayFamily_DisplaySignature 06_56H. Incremental error codes for internal machine check error from PCU
controller is reported in the register bank IA32_MC4, Table 16-24 lists model-specific fields to interpret error codes
applicable to IA32_MC4_STATUS. Incremental error codes for the memory controller unit is reported in the register
banks IA32_MC9-IA32_MC10. Table 16-18 lists model-specific error codes apply to IA32_MCi_STATUS, i = 9-10.
16.7.1
Internal Machine Check Errors
Table 16-24. Machine Check Error Codes for IA32_MC4_STATUS
Type
MCA error
codes1
MCACOD2
Bit No.
Bit Function
15:0
MCACOD
15:0
internal Errors
Bit Description
0402h - PCU internal Errors
0403h - internal Errors
0406h - Intel TXT Errors
0407h - Other UBOX internal Errors.
On an IERR caused by a core 3-strike the IA32_MC3_STATUS (MLC) is copied
to the IA32_MC4_STATUS (After a 3-strike, the core MCA banks will be
unavailable).
Model specific errors
19:16
Reserved except for
the following
0000b - No Error
00x1b - PCU internal error
001xb - PCU internal error
23:20
Reserved except for
the following
x1xxb - UBOX error
31:24
Reserved except for
the following
00h - No Error
09h - MC_MESSAGE_CHANNEL_TIMEOUT
13h - MC_DMI_TRAINING_TIMEOUT
15h - MC_DMI_CPU_RESET_ACK_TIMEOUT
1Eh - MC_VR_ICC_MAX_LT_FUSED_ICC_MAX
25h - MC_SVID_COMMAND_TIMEOUT
26h - MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT
29h - MC_VR_VOUT_MAC_LT_FUSED_SVID
2Bh - MC_PKGC_WATCHDOG_HANG_CBZ_DOWN
2Ch - MC_PKGC_WATCHDOG_HANG_CBZ_UP
44h - MC_CRITICAL_VR_FAILED
46h - MC_VID_RAMP_DOWN_FAILED
49h - MC_SVID_WRITE_REG_VOUT_MAX_FAILED
Vol. 3B 16-19
INTERPRETING MACHINE-CHECK ERROR CODES
Type
Bit No.
Bit Function
Bit Description
4Bh - MC_PP1_BOOT_VID_TIMEOUT. Timeout setting boot VID for DRAM 0.
4Fh - MC_SVID_COMMAND_ERROR.
52h - MC_FIVR_CATAS_OVERVOL_FAULT.
53h - MC_FIVR_CATAS_OVERCUR_FAULT.
57h - MC_SVID_PKGC_REQUEST_FAILED
58h - MC_SVID_IMON_REQUEST_FAILED
59h - MC_SVID_ALERT_REQUEST_FAILED
62h - MC_INVALID_PKGS_RSP_QPI
64h - MC_INVALID_PKG_STATE_CONFIG
67h - MC_HA_IMC_RW_BLOCK_ACK_TIMEOUT
6Ah - MC_MSGCH_PMREQ_CMP_TIMEOUT
72h - MC_WATCHDG_TIMEOUT_PKGS_MASTER
81h - MC_RECOVERABLE_DIE_THERMAL_TOO_HOT
56:32
Status register
validity indicators1
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
2. The internal error codes may be model-specific.
16.7.2
Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC9_STATUSIA32_MC10_STATUS. The supported error codes follow the architectural MCACOD definition type 1MMMCCCC (see
Chapter 15, “Machine-Check Architecture,”).
MSR_ERROR_CONTROL.[bit 1] can enable additional information logging of the IMC. The additional error information logged by the IMC is stored in IA32_MCi_STATUS and IA32_MCi_MISC; (i = 9-10).
Table 16-25. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-10)
Type
MCA error
codes1
Model specific
errors
Bit No.
Bit Function
Bit Description
15:0
MCACOD
Memory Controller error format: 0000 0000 1MMM CCCC
31:16
Reserved except for
the following
0001H - DDR3 address parity error
0002H - Uncorrected HA write data error
0004H - Uncorrected HA data byte enable error
0008H - Corrected patrol scrub error
0010H - Uncorrected patrol scrub error
0100H - iMC, write data buffer parity errors
0200H - DDR4 command address parity error
36:32
Other info
Reserved
37
Reserved
Reserved
56:38
Status register
validity indicators1
16-20 Vol. 3B
63:57
See Chapter 15, “Machine-Check Architecture,”
INTERPRETING MACHINE-CHECK ERROR CODES
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.8
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH
CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_4FH, MACHINE
ERROR CODES FOR MACHINE CHECK
Next Generation Intel Xeon processor E5 family is based on the Broadwell microarchitecture and can be identified
with CPUID DisplayFamily_DisplaySignature 06_4FH. Incremental error codes for internal machine check error
from PCU controller is reported in the register bank IA32_MC4, Table 16-20 in Section 16.6.1lists model-specific
fields to interpret error codes applicable to IA32_MC4_STATUS.
Incremental MC error codes related to the Intel QPI links are reported in the register banks IA32_MC5,
IA32_MC20, and IA32_MC21. Information listed in Table 16-21 of Section 16.6.1 covers QPI MC error codes.
16.8.1
Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC9_STATUSIA32_MC16_STATUS. The supported error codes follow the architectural MCACOD definition type 1MMMCCCC (see
Chapter 15, “Machine-Check Architecture”).
Table 16-26 lists model-specific error codes apply to IA32_MCi_STATUS, i = 9-16.
Table 16-26. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16)
Type
MCA error
codes1
Model specific
errors
Bit No.
Bit Function
Bit Description
15:0
MCACOD
Memory Controller error format: 0000 0000 1MMM CCCC
31:16
Reserved except for
the following
0001H - DDR3 address parity error
0002H - Uncorrected HA write data error
0004H - Uncorrected HA data byte enable error
0008H - Corrected patrol scrub error
0010H - Uncorrected patrol scrub error
0020H - Corrected spare error
0040H - Uncorrected spare error
0100H - iMC, write data buffer parity errors
0200H - DDR4 command address parity error
36:32
Other info
Reserved
37
Reserved
Reserved
56:38
Status register
validity indicators1
See Chapter 15, “Machine-Check Architecture,”
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
Vol. 3B 16-21
INTERPRETING MACHINE-CHECK ERROR CODES
16.8.2
Home Agent Machine Check Errors
MC error codes associated with mirrored memory corrections are reported in the MSRs IA32_MC7_MISC and
IA32_MC8_MISC. Table 16-27 lists model-specific error codes apply to IA32_MCi_MISC, i = 7, 8.
Table 16-27. Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8)
Bit No.
Bit Function
Bit Description
5:0
LSB
See Figure 15-8.
8:6
Address Mode
See Table 15-3.
40:9
Reserved
Reserved
41
Failover
Error occurred at a pair of mirrored memory channels. Error was corrected by mirroring with
channel failover.
42
Mirrorcorr
Error was corrected by mirroring and primary channel scrubbed successfully.
63:43
Reserved
Reserved
16.9
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID
DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_55H, MACHINE ERROR
CODES FOR MACHINE CHECK
In future Intel Xeon processors with CPUID DisplayFamily_DisplaySignature 06_55H, incremental error codes for
internal machine check errors from the PCU controller are reported in the register bank IA32_MC4. Table 16-28 in
Section 16.9.1 lists model-specific fields to interpret error codes applicable to IA32_MC4_STATUS.
16.9.1
Internal Machine Check Errors
Table 16-28. Machine Check Error Codes for IA32_MC4_STATUS
Type
MCA error
codes1
MCACOD2
Bit No.
Bit Function
15:0
MCACOD
15:0
internal Errors
Bit Description
0402h - PCU internal Errors
0403h - PCU internal Errors
0406h - Intel TXT Errors
0407h - Other UBOX internal Errors.
On an IERR caused by a core 3-strike the IA32_MC3_STATUS (MLC) is copied
to the IA32_MC4_STATUS (After a 3-strike, the core MCA banks will be
unavailable).
Model specific errors
16-22 Vol. 3B
19:16
Reserved except for
the following
0000b - No Error
00xxb - PCU internal error
INTERPRETING MACHINE-CHECK ERROR CODES
Type
Bit No.
Bit Function
Bit Description
23:20
Reserved
Reserved
31:24
Reserved except for
the following
00h - No Error
0Dh - MCA_DMI_TRAINING_TIMEOUT
0Fh - MCA_DMI_CPU_RESET_ACK_TIMEOUT
10h - MCA_MORE_THAN_ONE_LT_AGENT
1Eh - MCA_BIOS_RST_CPL_INVALID_SEQ
1Fh - MCA_BIOS_INVALID_PKG_STATE_CONFIG
25h - MCA_MESSAGE_CHANNEL_TIMEOUT
27h - MCA_MSGCH_PMREQ_CMP_TIMEOUT
30h - MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT
31h - MCA_PKGC_INVALID_RSP_PCH
33h - MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN
34h - MCA_PKGC_WATCHDOG_HANG_CBZ_UP
38h - MCA_PKGC_WATCHDOG_HANG_C3_UP_SF
40h - MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE
41h - MCA_SVID_COMMAND_TIMEOUT
42h - MCA_SVID_VCCIN_VR_VOUT_MAX_FAILURE
43h - MCA_SVID_CPU_VR_CAPABILITY_ERROR
44h - MCA_SVID_CRITICAL_VR_FAILED
45h - MCA_SVID_SA_ITD_ERROR
46h - MCA_SVID_READ_REG_FAILED
47h - MCA_SVID_WRITE_REG_FAILED
48h - MCA_SVID_PKGC_INIT_FAILED
49h - MCA_SVID_PKGC_CONFIG_FAILED
4Ah - MCA_SVID_PKGC_REQUEST_FAILED
4Bh - MCA_SVID_IMON_REQUEST_FAILED
4Ch - MCA_SVID_ALERT_REQUEST_FAILED
4Dh - MCA_SVID_MCP_VP_ABSENT_OR_RAMP_ERROR
4Eh - MCA_SVID_UNEXPECTED_MCP_VP_DETECTED
51h - MCA_FIVR_CATAS_OVERVOL_FAULT
52h - MCA_FIVR_CATAS_OVERCUR_FAULT
58h - MCA_WATCHDG_TIMEOUT_PKGC_SLAVE
59h - MCA_WATCHDG_TIMEOUT_PKGC_MASTER
5Ah - MCA_WATCHDG_TIMEOUT_PKGS_MASTER
61h - MCA_PKGS_CPD_UNPCD_TIMEOUT
63h - MCA_PKGS_INVALID_REQ_PCH
64h - MCA_PKGS_INVALID_REQ_INTERNAL
65h - MCA_PKGS_INVALID_RSP_INTERNAL
6Bh - MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT
81h - MC_RECOVERABLE_DIE_THERMAL_TOO_HOT
52:32
Reserved
Reserved
54:53
CORR_ERR_STATUS
Reserved
Vol. 3B 16-23
INTERPRETING MACHINE-CHECK ERROR CODES
Type
Status register
validity indicators1
Bit No.
Bit Function
Bit Description
56:55
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
2. The internal error codes may be model-specific.
16.9.2
Interconnect Machine Check Errors
MC error codes associated with the link interconnect agents are reported in the MSRs IA32_MC5_STATUS,
IA32_MC12_STATUS, IA32_MC19_STATUS. The supported error codes follow the architectural MCACOD definition
type 1PPTRRRRIILL (see Chapter 15, “Machine-Check Architecture”).
Table 16-29 lists model-specific fields to interpret error codes applicable to IA32_MCi_STATUS, i= 5, 12, 19.
Table 16-29. Interconnect MC Error Codes for IA32_MCi_STATUS, i = 5, 12, 19
Type
Bit No.
Bit Function
Bit Description
MCA error
codes1
15:0
MCACOD
Bus error format: 1PPTRRRRIILL
The two supported compound error codes:
- 0x0C0F - Unsupported/Undefined Packet
- 0x0E0F - For all other corrected and uncorrected errors
Model specific
errors
21:16
MSCOD
The encoding of Uncorrectable (UC) errors are:
00h - UC Phy Initialization Failure.
01h - UC Phy detected drift buffer alarm.
02h - UC Phy detected latency buffer rollover.
10h - UC link layer Rx detected CRC error: unsuccessful LLR entered abort state
11h - UC LL Rx unsupported or undefined packet.
12h - UC LL or Phy control error.
13h - UC LL Rx parameter exchange exception.
1fh - UC LL detected control error from the link-mesh interface
The encoding of correctable (COR) errors are:
20h - COR Phy initialization abort
21h - COR Phy reset
22h - COR Phy lane failure, recovery in x8 width.
23h - COR Phy L0c error corrected without Phy reset
24h - COR Phy L0c error triggering Phy reset
25h - COR Phy L0p exit error corrected with Phy reset
30h - COR LL Rx detected CRC error - successful LLR without Phy re-init.
31h - COR LL Rx detected CRC error - successful LLR with Phy re-init.
All other values are reserved.
16-24 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
Type
Bit No.
Bit Function
31:22
MSCOD_SPARE
Bit Description
The definition below applies to MSCOD 12h (UC LL or Phy Control Errors)
[Bit 22] : Phy Control Error
[Bit 23] : Unexpected Retry.Ack flit
[Bit 24] : Unexpected Retry.Req flit
[Bit 25] : RF parity error
[Bit 26] : Routeback Table error
[Bit 27] : unexpected Tx Protocol flit (EOP, Header or Data)
[Bit 28] : Rx Header-or-Credit BGF credit overflow/underflow
[Bit 29] : Link Layer Reset still in progress when Phy enters L0 (Phy training should
not be enabled until after LL reset is complete as indicated by
KTILCL.LinkLayerReset going back to 0).
[Bit 30] : Link Layer reset initiated while protocol traffic not idle
[Bit 31] : Link Layer Tx Parity Error
Status register
validity
indicators1
37:32
Reserved
52:38
Corrected Error Cnt
56:53
Reserved
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.9.3
Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC13_STATUSIA32_MC16_STATUS. The supported error codes follow the architectural MCACOD definition type 1MMMCCCC (see
Chapter 15, “Machine-Check Architecture”).
Vol. 3B 16-25
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-30. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13-16)
Type
Bit No.
Bit Function
Bit Description
MCA error codes1
15:0
MCACOD
Memory Controller error format: 0000 0000 1MMM CCCC
Model specific
errors
31:16
Reserved except for
the following
0001H - Address parity error
0002H - HA write data parity error
0004H - HA write byte enable parity error
0008H - Corrected patrol scrub error
0010H - Uncorrected patrol scrub error
0020H - Corrected spare error
0040H - Uncorrected spare error
0080H - Any HA read error
0100H - WDB read parity error
0200H - DDR4 command address parity error
0400H - Uncorrected address parity error
0800H - Unrecognized request type
0801H - Read response to an invalid scoreboard entry
0802H - Unexpected read response
0803H - DDR4 completion to an invalid scoreboard entry
0804H - Completion to an invalid scoreboard entry
0805H - Completion FIFO overflow
0806H - Correctable parity error
0807H - Uncorrectable error
0808H - Interrupt received while outstanding interrupt was not ACKed
0809H - ERID FIFO overflow
080aH - Error on Write credits
080bH - Error on Read credits
080cH - Scheduler error
080dH - Error event
36:32
Other info
MC logs the first error device. This is an encoded 5-bit value of the device.
37
Reserved
Reserved
56:38
Status register
validity indicators1
See Chapter 15, “Machine-Check Architecture,”
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.9.4
M2M Machine Check Errors
MC error codes associated with M2M are reported in the MSRs IA32_MC7_STATUS, IA32_MC8_STATUS. The
supported error codes follow the architectural MCACOD definition type 1MMMCCCC (see Chapter 15, “MachineCheck Architecture,”).
16-26 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-31. M2M MC Error Codes for IA32_MCi_STATUS (i= 7-8)
Type
Bit No.
Bit Function
Bit Description
MCA error codes1
15:0
MCACOD
Compound error format: 0000 0000 1MMM CCCC
Model specific
errors
16
MscodDataRdErr
Logged an MC read data error
17
Reserved
Reserved
18
MscodPtlWrErr
Logged an MC partial write data error
19
MscodFullWrErr
Logged a full write data error
20
MscodBgfErr
Logged an M2M clock-domain-crossing buffer (BGF) error
21
MscodTimeOut
Logged an M2M time out
22
MscodParErr
Logged an M2M tracker parity error
23
MscodBucket1Err
Logged a fatal Bucket1 error
31:24
Reserved
Reserved
36:32
Other info
MC logs the first error device. This is an encoded 5-bit value of the device.
37
Reserved
Reserved
56:38
Status register
validity indicators1
See Chapter 15, “Machine-Check Architecture,”
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16.9.5
Home Agent Machine Check Errors
MC error codes associated with mirrored memory corrections are reported in the MSRs IA32_MC7_MISC and
IA32_MC8_MISC. Table 16-32 lists model-specific error codes apply to IA32_MCi_MISC, i = 7, 8.
Table 16-32. Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8)
Bit No.
Bit Function
Bit Description
5:0
LSB
See Figure 15-8.
8:6
Address Mode
See Table 15-3.
40:9
Reserved
Reserved
61:41
Reserved
Reserved
62
Mirrorcorr
Error was corrected by mirroring and primary channel scrubbed successfully.
63
Failover
Error occurred at a pair of mirrored memory channels. Error was corrected by mirroring with
channel failover.
Vol. 3B 16-27
INTERPRETING MACHINE-CHECK ERROR CODES
16.10
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID
DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_5FH, MACHINE ERROR
CODES FOR MACHINE CHECK
In future Intel® Atom™ processors based on Goldmont Microarchitecture with CPUID
DisplayFamily_DisplaySignature 06_5FH (code name Denverton), incremental error codes for the memory
controller unit are reported in the register banks IA32_MC6 and IA32_MC7. Table 16-33 in Section 16.10.1 lists
model-specific fields to interpret error codes applicable to IA32_MCi_STATUS, i = 6, 7.
16.10.1 Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC6_STATUS and
IA32_MC7_STATUS. The supported error codes follow the architectural MCACOD definition type 1MMMCCCC (see
Chapter 15, “Machine-Check Architecture”).
Table 16-33. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 6, 7)
Type
MCA error
codes1
Model specific errors
Bit No.
Bit Function
15:0
MCACOD
31:16
Reserved except for
the following
Bit Description
01h - Cmd/Addr parity
02h - Corrected Demand/Patrol Scrub Error
04h - Uncorrected patrol scrub error
08h - Uncorrected demand read error
10h - WDB read ECC
36:32
Other info
37
Reserved
56:38
Status register
validity indicators1
See Chapter 15, “Machine-Check Architecture”.
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16-28 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
16.11
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 0FH
MACHINE ERROR CODES FOR MACHINE CHECK
Table 16-34 provides information for interpreting additional family 0FH model-specific fields for external bus
errors. These errors are reported in the IA32_MCi_STATUS MSRs. They are reported architecturally) as compound
errors with a general form of 0000 1PPT RRRR IILL in the MCA error code field. See Chapter 15 for information on
the interpretation of compound error codes.
Table 16-34. Incremental Decoding Information: Processor Family 0FH Machine Error Codes For Machine Check
Type
Bit No. Bit Function
MCA error
codes1
15:0
Model-specific
error codes
16
FSB address parity
Bit Description
Address parity error detected:
1 = Address parity error detected
0 = No address parity error
17
Response hard fail
Hardware failure detected on response
18
Response parity
Parity error detected on response
19
PIC and FSB data parity
Data Parity detected on either PIC or FSB access
20
Processor Signature =
00000F04H: Invalid PIC
request
Processor Signature = 00000F04H. Indicates error due to an invalid PIC
request access was made to PIC space with WB memory):
1 = Invalid PIC request error
0 = No Invalid PIC request error
Reserved
All other processors:
Reserved
Other
Information
21
Pad state machine
The state machine that tracks P and N data-strobe relative timing has
become unsynchronized or a glitch has been detected.
22
Pad strobe glitch
Data strobe glitch
23
Pad address glitch
Address strobe glitch
56:24
Reserved
Reserved
Status register 63:57
validity
indicators1
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
Table 16-10 provides information on interpreting additional family 0FH, model specific fields for cache hierarchy
errors. These errors are reported in one of the IA32_MCi_STATUS MSRs. These errors are reported, architecturally,
as compound errors with a general form of 0000 0001 RRRR TTLL in the MCA error code field. See Chapter 15 for
how to interpret the compound error code.
16.11.1 Model-Specific Machine Check Error Codes for Intel Xeon Processor MP 7100 Series
Intel Xeon processor MP 7100 series has 5 register banks which contains information related to Machine Check
Errors. MCi_STATUS[63:0] refers to all 5 register banks. MC0_STATUS[63:0] through MC3_STATUS[63:0] is the
same as on previous generation of Intel Xeon processors within Family 0FH. MC4_STATUS[63:0] is the main error
Vol. 3B 16-29
INTERPRETING MACHINE-CHECK ERROR CODES
logging for the processor’s L3 and front side bus errors. It supports the L3 Errors, Bus and Interconnect Errors
Compound Error Codes in the MCA Error Code Field.
Table 16-35. MCi_STATUS Register Bit Definition
Bit Field Name
Bits
Description
MCA_Error_Code
15:0
Specifies the machine check architecture defined error code for the machine check error condition
detected. The machine check architecture defined error codes are guaranteed to be the same for all
Intel Architecture processors that implement the machine check architecture. See tables below
Model_Specific_E 31:16
rror_Code
Specifies the model specific error code that uniquely identifies the machine check error condition
detected. The model specific error codes may differ among Intel Architecture processors for the same
Machine Check Error condition. See tables below
Other_Info
56:32
The functions of the bits in this field are implementation specific and are not part of the machine check
architecture. Software that is intended to be portable among Intel Architecture processors should not
rely on the values in this field.
PCC
57
Processor Context Corrupt flag indicates that the state of the processor might have been corrupted by
the error condition detected and that reliable restarting of the processor may not be possible. When
clear, this flag indicates that the error did not affect the processor's state. This bit will always be set for
MC errors which are not corrected.
ADDRV
58
MC_ADDR register valid flag indicates that the MC_ADDR register contains the address where the error
occurred. When clear, this flag indicates that the MC_ADDR register does not contain the address where
the error occurred. The MC_ADDR register should not be read if the ADDRV bit is clear.
MISCV
59
MC_MISC register valid flag indicates that the MC_MISC register contains additional
information regarding the error. When clear, this flag indicates that the MC_MISC register does not
contain additional information regarding the error. MC_MISC should not be read if the MISCV bit is not
set.
EN
60
Error enabled flag indicates that reporting of the machine check exception for this error was enabled by
the associated flag bit of the MC_CTL register. Note that correctable errors do not have associated
enable bits in the MC_CTL register so the EN bit should be clear when a correctable error is logged.
UC
61
Error uncorrected flag indicates that the processor did not correct the error condition. When clear, this
flag indicates that the processor was able to correct the event condition.
OVER
62
Machine check overflow flag indicates that a machine check error occurred while the results of a
previous error were still in the register bank (i.e., the VAL bit was already set in the
MC_STATUS register). The processor sets the OVER flag and software is responsible for clearing it.
Enabled errors are written over disabled errors, and uncorrected errors are written over corrected
events. Uncorrected errors are not written over previous valid uncorrected errors.
VAL
63
MC_STATUS register valid flag indicates that the information within the MC_STATUS register is valid.
When this flag is set, the processor follows the rules given for the OVER flag in the MC_STATUS register
when overwriting previously valid entries. The processor sets the VAL flag and software is responsible
for clearing it.
16.11.1.1 Processor Machine Check Status Register
MCA Error Code Definition
Intel Xeon processor MP 7100 series use compound MCA Error Codes for logging its CBC internal machine check
errors, L3 Errors, and Bus/Interconnect Errors. It defines additional Machine Check error types
(IA32_MC4_STATUS[15:0]) beyond those defined in Chapter 15. Table 16-36 lists these model-specific MCA error
codes. Error code details are specified in MC4_STATUS [31:16] (see Section 16.11.3), the “Model Specific Error
Code” field. The information in the “Other_Info” field (MC4_STATUS[56:32]) is common to the three processor
error types and contains a correctable event count and specifies the MC4_MISC register format.
16-30 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
Table 16-36. Incremental MCA Error Code for Intel Xeon Processor MP 7100
Processor MCA_Error_Code (MC4_STATUS[15:0])
Type
Error Code
Binary Encoding
Meaning
C
Internal Error
0000 0100 0000 0000 Internal Error Type Code
A
L3 Tag Error
0000 0001 0000 1011 L3 Tag Error Type Code
B
Bus and
Interconnect
0000 100x 0000 1111
Not used but this encoding is reserved for compatibility with other MCA
implementations
Error
0000 101x 0000 1111
Not used but this encoding is reserved for compatibility with other MCA
implementations
0000 110x 0000 1111
Not used but this encoding is reserved for compatibility with other MCA
implementations
0000 1110 0000 1111 Bus and Interconnection Error Type Code
0000 1111 0000 1111 Not used but this encoding is reserved for compatibility with other MCA
implementations
The Bold faced binary encodings are the only encodings used by the processor for MC4_STATUS[15:0].
16.11.2 Other_Info Field (all MCA Error Types)
The MC4_STATUS[56:32] field is common to the processor's three MCA error types (A, B & C).
Table 16-37. Other Information Field Bit Definition
Bit Field Name
Bits
Description
39:32
8-bit Correctable
Event Count
Holds a count of the number of correctable events since cold reset. This is a saturating counter;
the counter begins at 1 (with the first error) and saturates at a count of 255.
41:40
MC4_MISC
format type
The value in this field specifies the format of information in the MC4_MISC register. Currently,
only two values are defined. Valid only when MISCV is asserted.
43:42
–
Reserved
51:44
ECC syndrome
ECC syndrome value for a correctable ECC event when the “Valid ECC syndrome” bit is asserted
52
Valid ECC
syndrome
Set when correctable ECC event supplies the ECC syndrome
54:53
Threshold-Based 00: No tracking - No hardware status tracking is provided for the structure reporting this event.
Error Status
01: Green - Status tracking is provided for the structure posting the event; the current status is
green (below threshold).
10: Yellow - Status tracking is provided for the structure posting the event; the current status is
yellow (above threshold).
11: Reserved for future use
Valid only if Valid bit (bit 63) is set
Undefined if the UC bit (bit 61) is set
56:55
–
Reserved
Vol. 3B 16-31
INTERPRETING MACHINE-CHECK ERROR CODES
16.11.3 Processor Model Specific Error Code Field
16.11.3.1 MCA Error Type A: L3 Error
Note:
The Model Specific Error Code field in MC4_STATUS (bits 31:16).
Table 16-38. Type A: L3 Error Codes
Bit
Num
Sub-Field
Name
Description
Legal Value(s)
18:16
L3 Error
Code
Describes the L3
error
encountered
000 - No error
001 - More than one way reporting a correctable event
010 - More than one way reporting an uncorrectable error
011 - More than one way reporting a tag hit
100 - No error
101 - One way reporting a correctable event
110 - One way reporting an uncorrectable error
111 - One or more ways reporting a correctable event while one or more ways are
reporting an uncorrectable error
20:19
–
Reserved
00
31:21
–
Fixed pattern
0010_0000_000
16.11.3.2 Processor Model Specific Error Code Field Type B: Bus and Interconnect Error
Note:
The Model Specific Error Code field in MC4_STATUS (bits 31:16).
Table 16-39. Type B Bus and Interconnect Error Codes
Bit Num
Sub-Field Name
Description
16
FSB Request Parity
Parity error detected during FSB request phase
17
Core0 Addr Parity
Parity error detected on Core 0 request’s address field
18
Core1 Addr Parity
Parity error detected on Core 1 request’s address field
19
Reserved
20
FSB Response Parity
Parity error on FSB response field detected
21
FSB Data Parity
FSB data parity error on inbound data detected
22
Core0 Data Parity
Data parity error on data received from Core 0 detected
23
Core1 Data Parity
Data parity error on data received from Core 1 detected
24
IDS Parity
Detected an Enhanced Defer parity error (phase A or phase B)
25
FSB Inbound Data ECC
Data ECC event to error on inbound data (correctable or uncorrectable)
26
FSB Data Glitch
Pad logic detected a data strobe ‘glitch’ (or sequencing error)
27
FSB Address Glitch
Pad logic detected a request strobe ‘glitch’ (or sequencing error)
31:28
---
Reserved
Exactly one of the bits defined in the preceding table will be set for a Bus and Interconnect Error. The Data ECC can
be correctable or uncorrectable (the MC4_STATUS.UC bit, of course, distinguishes between correctable and uncorrectable cases with the Other_Info field possibly providing the ECC Syndrome for correctable errors). All other
errors for this processor MCA Error Type are uncorrectable.
16-32 Vol. 3B
INTERPRETING MACHINE-CHECK ERROR CODES
16.11.3.3 Processor Model Specific Error Code Field Type C: Cache Bus Controller Error
Table 16-40. Type C Cache Bus Controller Error Codes
MC4_STATUS[31:16] (MSCE) Value
Error Description
0000_0000_0000_0001 0001H
Inclusion Error from Core 0
0000_0000_0000_0010 0002H
Inclusion Error from Core 1
0000_0000_0000_0011 0003H
Write Exclusive Error from Core 0
0000_0000_0000_0100 0004H
Write Exclusive Error from Core 1
0000_0000_0000_0101 0005H
Inclusion Error from FSB
0000_0000_0000_0110 0006H
SNP Stall Error from FSB
0000_0000_0000_0111 0007H
Write Stall Error from FSB
0000_0000_0000_1000 0008H
FSB Arb Timeout Error
0000_0000_0000_1001 0009H
CBC OOD Queue Underflow/overflow
0000_0001_0000_0000 0100H
Enhanced Intel SpeedStep Technology TM1-TM2 Error
0000_0010_0000_0000 0200H
Internal Timeout error
0000_0011_0000_0000 0300H
Internal Timeout Error
0000_0100_0000_0000 0400H
Intel® Cache Safe Technology Queue Full Error or Disabled-ways-in-a-set overflow
1100_0000_0000_0001 C001H
Correctable ECC event on outgoing FSB data
1100_0000_0000_0010 C002H
Correctable ECC event on outgoing Core 0 data
1100_0000_0000_0100 C004H
Correctable ECC event on outgoing Core 1 data
1110_0000_0000_0001 E001H
Uncorrectable ECC error on outgoing FSB data
1110_0000_0000_0010 E002H
Uncorrectable ECC error on outgoing Core 0 data
1110_0000_0000_0100 E004H
Uncorrectable ECC error on outgoing Core 1 data
— all other encodings —
Reserved
Vol. 3B 16-33
INTERPRETING MACHINE-CHECK ERROR CODES
All errors - except for the correctable ECC types - in this table are uncorrectable. The correctable ECC events may
supply the ECC syndrome in the Other_Info field of the MC4_STATUS MSR.
Table 16-41. Decoding Family 0FH Machine Check Codes for Cache Hierarchy Errors
Type
Bit No.
MCA error
codes1
15:0
Model
specific error
codes
17:16
Bit Function
Bit Description
Tag Error Code
Contains the tag error code for this machine check error:
00 = No error detected
01 = Parity error on tag miss with a clean line
10 = Parity error/multiple tag match on tag hit
11 = Parity error/multiple tag match on tag miss
19:18
Data Error Code
Contains the data error code for this machine check error:
00 = No error detected
01 = Single bit error
10 = Double bit error on a clean line
11 = Double bit error on a modified line
20
L3 Error
This bit is set if the machine check error originated in the L3 it can be ignored for
invalid PIC request errors):
1 = L3 error
0 = L2 error
21
Invalid PIC Request
Indicates error due to invalid PIC request access was made to PIC space with WB
memory):
1 = Invalid PIC request error
0 = No invalid PIC request error
Other
Information
Status
register
validity
indicators1
31:22
Reserved
Reserved
39:32
8-bit Error Count
Holds a count of the number of errors since reset. The counter begins at 0 for the
first error and saturates at a count of 255.
56:40
Reserved
Reserved
63:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.
16-34 Vol. 3B
CHAPTER 17
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING
FEATURES
Intel 64 and IA-32 architectures provide debug facilities for use in debugging code and monitoring performance.
These facilities are valuable for debugging application software, system software, and multitasking operating
systems. Debug support is accessed using debug registers (DR0 through DR7) and model-specific registers
(MSRs):
•
Debug registers hold the addresses of memory and I/O locations called breakpoints. Breakpoints are userselected locations in a program, a data-storage area in memory, or specific I/O ports. They are set where a
programmer or system designer wishes to halt execution of a program and examine the state of the processor
by invoking debugger software. A debug exception (#DB) is generated when a memory or I/O access is made
to a breakpoint address.
•
MSRs monitor branches, interrupts, and exceptions; they record addresses of the last branch, interrupt or
exception taken and the last branch taken before an interrupt or exception.
•
•
Time stamp counter is described in Section 17.15, “Time-Stamp Counter”.
•
Features which enable control over shared platform resources are described in Section 17.17, “Intel® Resource
Director Technology (Intel® RDT) Allocation Features”.
Features which allow monitoring of shared platform resources such as the L3 cache are described in Section
17.16, “Intel® Resource Director Technology (Intel® RDT) Monitoring Features”.
17.1
OVERVIEW OF DEBUG SUPPORT FACILITIES
The following processor facilities support debugging and performance monitoring:
•
Debug exception (#DB) — Transfers program control to a debug procedure or task when a debug event
occurs.
•
•
•
Breakpoint exception (#BP) — See breakpoint instruction (INT 3) below.
Breakpoint-address registers (DR0 through DR3) — Specifies the addresses of up to 4 breakpoints.
Debug status register (DR6) — Reports the conditions that were in effect when a debug or breakpoint
exception was generated.
•
Debug control register (DR7) — Specifies the forms of memory or I/O access that cause breakpoints to be
generated.
•
T (trap) flag, TSS — Generates a debug exception (#DB) when an attempt is made to switch to a task with
the T flag set in its TSS.
•
•
RF (resume) flag, EFLAGS register — Suppresses multiple exceptions to the same instruction.
•
Breakpoint instruction (INT 3) — Generates a breakpoint exception (#BP) that transfers program control to
the debugger procedure or task. This instruction is an alternative way to set code breakpoints. It is especially
useful when more than four breakpoints are desired, or when breakpoints are being placed in the source code.
•
Last branch recording facilities — Store branch records in the last branch record (LBR) stack MSRs for the
most recent taken branches, interrupts, and/or exceptions in MSRs. A branch record consist of a branch-from
and a branch-to instruction address. Send branch records out on the system bus as branch trace messages
(BTMs).
TF (trap) flag, EFLAGS register — Generates a debug exception (#DB) after every execution of an
instruction.
These facilities allow a debugger to be called as a separate task or as a procedure in the context of the current
program or task. The following conditions can be used to invoke the debugger:
•
•
Task switch to a specific task.
Execution of the breakpoint instruction.
Vol. 3B 17-1
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
•
•
•
•
•
•
Execution of any instruction.
Execution of an instruction at a specified address.
Read or write to a specified memory address/range.
Write to a specified memory address/range.
Input from a specified I/O address/range.
Output to a specified I/O address/range.
Attempt to change the contents of a debug register.
17.2
DEBUG REGISTERS
Eight debug registers (see Figure 17-1 for 32-bit operation and Figure 17-2 for 64-bit operation) control the debug
operation of the processor. These registers can be written to and read using the move to/from debug register form
of the MOV instruction. A debug register may be the source or destination operand for one of these instructions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEN R/W LEN R/W LEN R/W LEN R/W 0 0 G 0 R 1 G L G L G L G L G L
DR7
T
3
3
2
2
1
1
0
0
D
E E 3 3 2 2 1 1 0 0
M
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved (set to 1)
R
T B B B 0 1 1 1 1 1 1 1 1 B B B B DR6
3 2 1 0
MT S D
31
0
DR5
31
0
DR4
31
0
DR3
Breakpoint 3 Linear Address
31
0
DR2
Breakpoint 2 Linear Address
31
0
DR1
Breakpoint 1 Linear Address
31
0
Breakpoint 0 Linear Address
Reserved
Figure 17-1. Debug Registers
17-2 Vol. 3B
DR0
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
Debug registers are privileged resources; a MOV instruction that accesses these registers can only be executed in
real-address mode, in SMM or in protected mode at a CPL of 0. An attempt to read or write the debug registers
from any other privilege level generates a general-protection exception (#GP).
The primary function of the debug registers is to set up and monitor from 1 to 4 breakpoints, numbered 0 though
3. For each breakpoint, the following information can be specified:
•
•
•
•
•
The linear address where the breakpoint is to occur.
The length of the breakpoint location: 1, 2, 4, or 8 bytes (refer to the notes in Section 17.2.4).
The operation that must be performed at the address for a debug exception to be generated.
Whether the breakpoint is enabled.
Whether the breakpoint condition was present when the debug exception was generated.
The following paragraphs describe the functions of flags and fields in the debug registers.
17.2.1
Debug Address Registers (DR0-DR3)
Each of the debug-address registers (DR0 through DR3) holds the 32-bit linear address of a breakpoint (see
Figure 17-1). Breakpoint comparisons are made before physical address translation occurs. The contents of debug
register DR7 further specifies breakpoint conditions.
17.2.2
Debug Registers DR4 and DR5
Debug registers DR4 and DR5 are reserved when debug extensions are enabled (when the DE flag in control
register CR4 is set) and attempts to reference the DR4 and DR5 registers cause invalid-opcode exceptions (#UD).
When debug extensions are not enabled (when the DE flag is clear), these registers are aliased to debug registers
DR6 and DR7.
17.2.3
Debug Status Register (DR6)
The debug status register (DR6) reports debug conditions that were sampled at the time the last debug exception
was generated (see Figure 17-1). Updates to this register only occur when an exception is generated. The flags in
this register show the following information:
•
B0 through B3 (breakpoint condition detected) flags (bits 0 through 3) — Indicates (when set) that its
associated breakpoint condition was met when a debug exception was generated. These flags are set if the
condition described for each breakpoint by the LENn, and R/Wn flags in debug control register DR7 is true.
They may or may not be set if the breakpoint is not enabled by the Ln or the Gn flags in register DR7. Therefore
on a #DB, a debug handler should check only those B0-B3 bits which correspond to an enabled breakpoint.
•
BD (debug register access detected) flag (bit 13) — Indicates that the next instruction in the instruction
stream accesses one of the debug registers (DR0 through DR7). This flag is enabled when the GD (general
detect) flag in debug control register DR7 is set. See Section 17.2.4, “Debug Control Register (DR7),” for
further explanation of the purpose of this flag.
•
BS (single step) flag (bit 14) — Indicates (when set) that the debug exception was triggered by the singlestep execution mode (enabled with the TF flag in the EFLAGS register). The single-step mode is the highestpriority debug exception. When the BS flag is set, any of the other debug status bits also may be set.
•
BT (task switch) flag (bit 15) — Indicates (when set) that the debug exception resulted from a task switch
where the T flag (debug trap flag) in the TSS of the target task was set. See Section 7.2.1, “Task-State
Segment (TSS),” for the format of a TSS. There is no flag in debug control register DR7 to enable or disable this
exception; the T flag of the TSS is the only enabling flag.
•
RTM (restricted transactional memory) flag (bit 16) — Indicates (when clear) that a debug exception
(#DB) or breakpoint exception (#BP) occurred inside an RTM region while advanced debugging of RTM transactional regions was enabled (see Section 17.3.3). This bit is set for any other debug exception (including all
those that occur when advanced debugging of RTM transactional regions is not enabled). This bit is always 1 if
the processor does not support RTM.
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Certain debug exceptions may clear bits 0-3. The remaining contents of the DR6 register are never cleared by the
processor. To avoid confusion in identifying debug exceptions, debug handlers should clear the register (except
bit 16, which they should set) before returning to the interrupted task.
17.2.4
Debug Control Register (DR7)
The debug control register (DR7) enables or disables breakpoints and sets breakpoint conditions (see Figure 17-1).
The flags and fields in this register control the following things:
•
L0 through L3 (local breakpoint enable) flags (bits 0, 2, 4, and 6) — Enables (when set) the breakpoint
condition for the associated breakpoint for the current task. When a breakpoint condition is detected and its
associated Ln flag is set, a debug exception is generated. The processor automatically clears these flags on
every task switch to avoid unwanted breakpoint conditions in the new task.
•
G0 through G3 (global breakpoint enable) flags (bits 1, 3, 5, and 7) — Enables (when set) the
breakpoint condition for the associated breakpoint for all tasks. When a breakpoint condition is detected and its
associated Gn flag is set, a debug exception is generated. The processor does not clear these flags on a task
switch, allowing a breakpoint to be enabled for all tasks.
•
LE and GE (local and global exact breakpoint enable) flags (bits 8, 9) — This feature is not supported in
the P6 family processors, later IA-32 processors, and Intel 64 processors. When set, these flags cause the
processor to detect the exact instruction that caused a data breakpoint condition. For backward and forward
compatibility with other Intel processors, we recommend that the LE and GE flags be set to 1 if exact
breakpoints are required.
•
RTM (restricted transactional memory) flag (bit 11) — Enables (when set) advanced debugging of RTM
transactional regions (see Section 17.3.3). This advanced debugging is enabled only if IA32_DEBUGCTL.RTM is
also set.
•
GD (general detect enable) flag (bit 13) — Enables (when set) debug-register protection, which causes a
debug exception to be generated prior to any MOV instruction that accesses a debug register. When such a
condition is detected, the BD flag in debug status register DR6 is set prior to generating the exception. This
condition is provided to support in-circuit emulators.
When the emulator needs to access the debug registers, emulator software can set the GD flag to prevent
interference from the program currently executing on the processor.
The processor clears the GD flag upon entering to the debug exception handler, to allow the handler access to
the debug registers.
•
R/W0 through R/W3 (read/write) fields (bits 16, 17, 20, 21, 24, 25, 28, and 29) — Specifies the
breakpoint condition for the corresponding breakpoint. The DE (debug extensions) flag in control register CR4
determines how the bits in the R/Wn fields are interpreted. When the DE flag is set, the processor interprets
bits as follows:
00
01
10
11
—
—
—
—
Break
Break
Break
Break
on
on
on
on
instruction execution only.
data writes only.
I/O reads or writes.
data reads or writes but not instruction fetches.
When the DE flag is clear, the processor interprets the R/Wn bits the same as for the Intel386™ and Intel486™
processors, which is as follows:
00
01
10
11
•
—
—
—
—
Break on instruction execution only.
Break on data writes only.
Undefined.
Break on data reads or writes but not instruction fetches.
LEN0 through LEN3 (Length) fields (bits 18, 19, 22, 23, 26, 27, 30, and 31) — Specify the size of the
memory location at the address specified in the corresponding breakpoint address register (DR0 through DR3).
These fields are interpreted as follows:
00
01
10
11
17-4 Vol. 3B
—
—
—
—
1-byte length.
2-byte length.
Undefined (or 8 byte length, see note below).
4-byte length.
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
If the corresponding RWn field in register DR7 is 00 (instruction execution), then the LENn field should also be 00.
The effect of using other lengths is undefined. See Section 17.2.5, “Breakpoint Field Recognition,” below.
NOTES
For Pentium® 4 and Intel® Xeon® processors with a CPUID signature corresponding to family 15
(model 3, 4, and 6), break point conditions permit specifying 8-byte length on data read/write with
an of encoding 10B in the LENn field.
Encoding 10B is also supported in processors based on Intel Core microarchitecture or enhanced
Intel Core microarchitecture, the respective CPUID signatures corresponding to family 6, model 15,
and family 6, DisplayModel value 23 (see CPUID instruction in Chapter 3, “Instruction Set
Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A). The Encoding 10B is supported in processors based on Intel® Atom™ microarchitecture, with
CPUID signature of family 6, DisplayModel value 1CH. The encoding 10B is undefined for other
processors.
17.2.5
Breakpoint Field Recognition
Breakpoint address registers (debug registers DR0 through DR3) and the LENn fields for each breakpoint define a
range of sequential byte addresses for a data or I/O breakpoint. The LENn fields permit specification of a 1-, 2-, 4or 8-byte range, beginning at the linear address specified in the corresponding debug register (DRn). Two-byte
ranges must be aligned on word boundaries; 4-byte ranges must be aligned on doubleword boundaries, 8-byte
ranges must be aligned on quadword boundaries. I/O addresses are zero-extended (from 16 to 32 bits, for
comparison with the breakpoint address in the selected debug register). These requirements are enforced by the
processor; it uses LENn field bits to mask the lower address bits in the debug registers. Unaligned data or I/O
breakpoint addresses do not yield valid results.
A data breakpoint for reading or writing data is triggered if any of the bytes participating in an access is within the
range defined by a breakpoint address register and its LENn field. Table 17-1 provides an example setup of debug
registers and data accesses that would subsequently trap or not trap on the breakpoints.
A data breakpoint for an unaligned operand can be constructed using two breakpoints, where each breakpoint is
byte-aligned and the two breakpoints together cover the operand. The breakpoints generate exceptions only for
the operand, not for neighboring bytes.
Instruction breakpoint addresses must have a length specification of 1 byte (the LENn field is set to 00). Code
breakpoints for other operand sizes are undefined. The processor recognizes an instruction breakpoint address
only when it points to the first byte of an instruction. If the instruction has prefixes, the breakpoint address must
point to the first prefix.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
Table 17-1. Breakpoint Examples
Debug Register Setup
Debug Register
R/Wn
Breakpoint Address
LENn
DR0
DR1
DR2
DR3
R/W0 = 11 (Read/Write)
R/W1 = 01 (Write)
R/W2 = 11 (Read/Write)
R/W3 = 01 (Write)
A0001H
A0002H
B0002H
C0000H
LEN0 = 00 (1 byte)
LEN1 = 00 (1 byte)
LEN2 = 01) (2 bytes)
LEN3 = 11 (4 bytes)
Data Accesses
Operation
Address
Access Length
(In Bytes)
Data operations that trap
- Read or write
- Read or write
- Write
- Write
- Read or write
- Read or write
- Read or write
- Write
- Write
- Write
A0001H
A0001H
A0002H
A0002H
B0001H
B0002H
B0002H
C0000H
C0001H
C0003H
1
2
1
2
4
1
2
4
2
1
Data operations that do not trap
- Read or write
- Read
- Read or write
- Read or write
- Read
- Read or write
A0000H
A0002H
A0003H
B0000H
C0000H
C0004H
1
1
4
2
2
4
17.2.6
Debug Registers and Intel® 64 Processors
For Intel 64 architecture processors, debug registers DR0–DR7 are 64 bits. In 16-bit or 32-bit modes (protected
mode and compatibility mode), writes to a debug register fill the upper 32 bits with zeros. Reads from a debug
register return the lower 32 bits. In 64-bit mode, MOV DRn instructions read or write all 64 bits. Operand-size
prefixes are ignored.
In 64-bit mode, the upper 32 bits of DR6 and DR7 are reserved and must be written with zeros. Writing 1 to any of
the upper 32 bits results in a #GP(0) exception (see Figure 17-2). All 64 bits of DR0–DR3 are writable by software.
However, MOV DRn instructions do not check that addresses written to DR0–DR3 are in the linear-address limits of
the processor implementation (address matching is supported only on valid addresses generated by the processor
implementation). Break point conditions for 8-byte memory read/writes are supported in all modes.
17.3
DEBUG EXCEPTIONS
The Intel 64 and IA-32 architectures dedicate two interrupt vectors to handling debug exceptions: vector 1 (debug
exception, #DB) and vector 3 (breakpoint exception, #BP). The following sections describe how these exceptions
are generated and typical exception handler operations.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
63
32
DR7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEN R/W LEN R/W LEN R/W LEN R/W 0 0 G 0 0 1 G L G L G L G L G L
DR7
3
3
2
2
1
1
0
0
D
E E 3 3 2 2 1 1 0 0
63
32
DR6
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved (set to 1)
B B B 0 1 1 1 1 1 1 1 1 1 B B B B
DR6
T S D
3 2 1 0
63
0
DR5
63
0
DR4
63
0
DR3
Breakpoint 3 Linear Address
63
0
DR2
Breakpoint 2 Linear Address
63
0
DR1
Breakpoint 1 Linear Address
63
0
Breakpoint 0 Linear Address
DR0
Reserved
Figure 17-2. DR6/DR7 Layout on Processors Supporting Intel® 64 Architecture
17.3.1
Debug Exception (#DB)—Interrupt Vector 1
The debug-exception handler is usually a debugger program or part of a larger software system. The processor
generates a debug exception for any of several conditions. The debugger checks flags in the DR6 and DR7 registers
to determine which condition caused the exception and which other conditions might apply. Table 17-2 shows the
states of these flags following the generation of each kind of breakpoint condition.
Instruction-breakpoint and general-detect condition (see Section 17.3.1.3, “General-Detect Exception Condition”)
result in faults; other debug-exception conditions result in traps. The debug exception may report one or both at
one time. The following sections describe each class of debug exception.
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See also: Chapter 6, “Interrupt 1—Debug Exception (#DB),” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A.
Table 17-2. Debug Exception Conditions
Debug or Breakpoint Condition
DR6 Flags Tested
Single-step trap
BS = 1
Instruction breakpoint, at addresses defined by DRn and
LENn
Bn = 1 and
(Gn or Ln = 1)
R/Wn = 0
Fault
Data write breakpoint, at addresses defined by DRn and
LENn
Bn = 1 and
(Gn or Ln = 1)
R/Wn = 1
Trap
I/O read or write breakpoint, at addresses defined by DRn
and LENn
Bn = 1 and
(Gn or Ln = 1)
R/Wn = 2
Trap
Data read or write (but not instruction fetches), at
addresses defined by DRn and LENn
Bn = 1 and
(Gn or Ln = 1)
R/Wn = 3
Trap
General detect fault, resulting from an attempt to modify
debug registers (usually in conjunction with in-circuit
emulation)
BD = 1
Fault
Task switch
BT = 1
Trap
17.3.1.1
DR7 Flags Tested
Exception Class
Trap
Instruction-Breakpoint Exception Condition
The processor reports an instruction breakpoint when it attempts to execute an instruction at an address specified
in a breakpoint-address register (DR0 through DR3) that has been set up to detect instruction execution (R/W flag
is set to 0). Upon reporting the instruction breakpoint, the processor generates a fault-class, debug exception
(#DB) before it executes the target instruction for the breakpoint.
Instruction breakpoints are the highest priority debug exceptions. They are serviced before any other exceptions
detected during the decoding or execution of an instruction. However, if a code instruction breakpoint is placed on
an instruction located immediately after a POP SS/MOV SS instruction, the breakpoint may not be triggered. In
most situations, POP SS/MOV SS will inhibit such interrupts (see “MOV—Move” and “POP—Pop a Value from the
Stack” in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B).
Because the debug exception for an instruction breakpoint is generated before the instruction is executed, if the
instruction breakpoint is not removed by the exception handler; the processor will detect the instruction breakpoint
again when the instruction is restarted and generate another debug exception. To prevent looping on an instruction
breakpoint, the Intel 64 and IA-32 architectures provide the RF flag (resume flag) in the EFLAGS register (see
Section 2.3, “System Flags and Fields in the EFLAGS Register,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A). When the RF flag is set, the processor ignores instruction breakpoints.
All Intel 64 and IA-32 processors manage the RF flag as follows. The RF Flag is cleared at the start of the instruction
after the check for code breakpoint, CS limit violation and FP exceptions. Task Switches and IRETD/IRETQ instructions transfer the RF image from the TSS/stack to the EFLAGS register.
When calling an event handler, Intel 64 and IA-32 processors establish the value of the RF flag in the EFLAGS image
pushed on the stack:
•
For any fault-class exception except a debug exception generated in response to an instruction breakpoint, the
value pushed for RF is 1.
•
For any interrupt arriving after any iteration of a repeated string instruction but the last iteration, the value
pushed for RF is 1.
•
For any trap-class exception generated by any iteration of a repeated string instruction but the last iteration,
the value pushed for RF is 1.
•
For other cases, the value pushed for RF is the value that was in EFLAG.RF at the time the event handler was
called. This includes:
— Debug exceptions generated in response to instruction breakpoints
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
— Hardware-generated interrupts arriving between instructions (including those arriving after the last
iteration of a repeated string instruction)
— Trap-class exceptions generated after an instruction completes (including those generated after the last
iteration of a repeated string instruction)
— Software-generated interrupts (RF is pushed as 0, since it was cleared at the start of the software interrupt)
As noted above, the processor does not set the RF flag prior to calling the debug exception handler for debug
exceptions resulting from instruction breakpoints. The debug exception handler can prevent recurrence of the
instruction breakpoint by setting the RF flag in the EFLAGS image on the stack. If the RF flag in the EFLAGS image
is set when the processor returns from the exception handler, it is copied into the RF flag in the EFLAGS register by
IRETD/IRETQ or a task switch that causes the return. The processor then ignores instruction breakpoints for the
duration of the next instruction. (Note that the POPF, POPFD, and IRET instructions do not transfer the RF image
into the EFLAGS register.) Setting the RF flag does not prevent other types of debug-exception conditions (such as,
I/O or data breakpoints) from being detected, nor does it prevent non-debug exceptions from being generated.
For the Pentium processor, when an instruction breakpoint coincides with another fault-type exception (such as a
page fault), the processor may generate one spurious debug exception after the second exception has been
handled, even though the debug exception handler set the RF flag in the EFLAGS image. To prevent a spurious
exception with Pentium processors, all fault-class exception handlers should set the RF flag in the EFLAGS image.
17.3.1.2
Data Memory and I/O Breakpoint Exception Conditions
Data memory and I/O breakpoints are reported when the processor attempts to access a memory or I/O address
specified in a breakpoint-address register (DR0 through DR3) that has been set up to detect data or I/O accesses
(R/W flag is set to 1, 2, or 3). The processor generates the exception after it executes the instruction that made the
access, so these breakpoint condition causes a trap-class exception to be generated.
Because data breakpoints are traps, an instruction that writes memory overwrites the original data before the
debug exception generated by a data breakpoint is generated. If a debugger needs to save the contents of a write
breakpoint location, it should save the original contents before setting the breakpoint. The handler can report the
saved value after the breakpoint is triggered. The address in the debug registers can be used to locate the new
value stored by the instruction that triggered the breakpoint.
If a data breakpoint is detected during an iteration of a string instruction executed with fast-string operation (see
Section 7.3.9.3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1), delivery of the
resulting debug exception may be delayed until completion of the corresponding group of iterations.
Intel486 and later processors ignore the GE and LE flags in DR7. In Intel386 processors, exact data breakpoint
matching does not occur unless it is enabled by setting the LE and/or the GE flags.
For repeated INS and OUTS instructions that generate an I/O-breakpoint debug exception, the processor generates the exception after the completion of the first iteration. Repeated INS and OUTS instructions generate a databreakpoint debug exception after the iteration in which the memory address breakpoint location is accessed.
17.3.1.3
General-Detect Exception Condition
When the GD flag in DR7 is set, the general-detect debug exception occurs when a program attempts to access any
of the debug registers (DR0 through DR7) at the same time they are being used by another application, such as an
emulator or debugger. This protection feature guarantees full control over the debug registers when required. The
debug exception handler can detect this condition by checking the state of the BD flag in the DR6 register. The
processor generates the exception before it executes the MOV instruction that accesses a debug register, which
causes a fault-class exception to be generated.
17.3.1.4
Single-Step Exception Condition
The processor generates a single-step debug exception if (while an instruction is being executed) it detects that the
TF flag in the EFLAGS register is set. The exception is a trap-class exception, because the exception is generated
after the instruction is executed. The processor will not generate this exception after the instruction that sets the
TF flag. For example, if the POPF instruction is used to set the TF flag, a single-step trap does not occur until after
the instruction that follows the POPF instruction.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
The processor clears the TF flag before calling the exception handler. If the TF flag was set in a TSS at the time of
a task switch, the exception occurs after the first instruction is executed in the new task.
The TF flag normally is not cleared by privilege changes inside a task. The INT n and INTO instructions, however,
do clear this flag. Therefore, software debuggers that single-step code must recognize and emulate INT n or INTO
instructions rather than executing them directly. To maintain protection, the operating system should check the
CPL after any single-step trap to see if single stepping should continue at the current privilege level.
The interrupt priorities guarantee that, if an external interrupt occurs, single stepping stops. When both an external
interrupt and a single-step interrupt occur together, the single-step interrupt is processed first. This operation
clears the TF flag. After saving the return address or switching tasks, the external interrupt input is examined
before the first instruction of the single-step handler executes. If the external interrupt is still pending, then it is
serviced. The external interrupt handler does not run in single-step mode. To single step an interrupt handler,
single step an INT n instruction that calls the interrupt handler.
17.3.1.5
Task-Switch Exception Condition
The processor generates a debug exception after a task switch if the T flag of the new task's TSS is set. This exception is generated after program control has passed to the new task, and prior to the execution of the first instruction of that task. The exception handler can detect this condition by examining the BT flag of the DR6 register.
If entry 1 (#DB) in the IDT is a task gate, the T bit of the corresponding TSS should not be set. Failure to observe
this rule will put the processor in a loop.
17.3.2
Breakpoint Exception (#BP)—Interrupt Vector 3
The breakpoint exception (interrupt 3) is caused by execution of an INT 3 instruction. See Chapter 6, “Interrupt
3—Breakpoint Exception (#BP).” Debuggers use break exceptions in the same way that they use the breakpoint
registers; that is, as a mechanism for suspending program execution to examine registers and memory locations.
With earlier IA-32 processors, breakpoint exceptions are used extensively for setting instruction breakpoints.
With the Intel386 and later IA-32 processors, it is more convenient to set breakpoints with the breakpoint-address
registers (DR0 through DR3). However, the breakpoint exception still is useful for breakpointing debuggers,
because a breakpoint exception can call a separate exception handler. The breakpoint exception is also useful when
it is necessary to set more breakpoints than there are debug registers or when breakpoints are being placed in the
source code of a program under development.
17.3.3
Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory
(RTM)
Chapter 16, “Programming with Intel® Transactional Synchronization Extensions,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 describes Restricted Transactional Memory (RTM). This is an
instruction-set interface that allows software to identify transactional regions (or critical sections) using the
XBEGIN and XEND instructions.
Execution of an RTM transactional region begins with an XBEGIN instruction. If execution of the region successfully
reaches an XEND instruction, the processor ensures that all memory operations performed within the region
appear to have occurred instantaneously when viewed from other logical processors. Execution of an RTM transaction region does not succeed if the processor cannot commit the updates atomically. When this happens, the
processor rolls back the execution, a process referred to as a transactional abort. In this case, the processor
discards all updates performed in the region, restores architectural state to appear as if the execution had not
occurred, and resumes execution at a fallback instruction address that was specified with the XBEGIN instruction.
If debug exception (#DB) or breakpoint exception (#BP) occurs within an RTM transaction region, a transactional
abort occurs, the processor sets EAX[4], and no exception is delivered.
Software can enable advanced debugging of RTM transactional regions by setting DR7.RTM[bit 11] and
IA32_DEBUGCTL.RTM[bit 15]. If these bits are both set, the transactional abort caused by a #DB or #BP within an
RTM transaction region does not resume execution at the fallback instruction address specified with the XBEGIN
instruction that begin the region. Instead, execution is resumed at that XBEGIN instruction, and a #DB is delivered.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
(A #DB is delivered even if the transactional abort was caused by a #BP.) Such a #DB will clear DR6.RTM[bit 16]
(all other debug exceptions set DR6[16]).
17.4
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING OVERVIEW
P6 family processors introduced the ability to set breakpoints on taken branches, interrupts, and exceptions, and
to single-step from one branch to the next. This capability has been modified and extended in the Pentium 4, Intel
Xeon, Pentium M, Intel® Core™ Solo, Intel® Core™ Duo, Intel® Core™2 Duo, Intel® Core™ i7 and Intel® Atom™
processors to allow logging of branch trace messages in a branch trace store (BTS) buffer in memory.
See the following sections for processor specific implementation of last branch, interrupt and exception recording:
— Section 17.5, “Last Branch, Interrupt, and Exception Recording (Intel® Core™ 2 Duo and Intel® Atom™
Processors)”
— Section 17.6, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on
Goldmont Microarchitecture”
— Section 17.7, “Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Nehalem”
— Section 17.8, “Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Sandy Bridge”
— Section 17.9, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Haswell
Microarchitecture”
— Section 17.10, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on
Skylake Microarchitecture”
— Section 17.12, “Last Branch, Interrupt, and Exception Recording (Intel® Core™ Solo and Intel® Core™
Duo Processors)”
— Section 17.13, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors)”
— Section 17.14, “Last Branch, Interrupt, and Exception Recording (P6 Family Processors)”
The following subsections of Section 17.4 describe common features of profiling branches. These features are
generally enabled using the IA32_DEBUGCTL MSR (older processor may have implemented a subset or modelspecific features, see definitions of MSR_DEBUGCTLA, MSR_DEBUGCTLB, MSR_DEBUGCTL).
17.4.1
IA32_DEBUGCTL MSR
The IA32_DEBUGCTL MSR provides bit field controls to enable debug trace interrupts, debug trace stores, trace
messages enable, single stepping on branches, last branch record recording, and to control freezing of LBR stack
or performance counters on a PMI request. IA32_DEBUGCTL MSR is located at register address 01D9H.
See Figure 17-3 for the MSR layout and the bullets below for a description of the flags:
•
LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records a running trace of
the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug exception
being generated) in the last branch record (LBR) stack. For more information, see the Section 17.5.1, “LBR
Stack” (Intel® Core™2 Duo and Intel® Atom™ Processor Family) and Section 17.7.1, “LBR Stack” (processors
based on Intel® Microarchitecture code name Nehalem).
•
BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS
register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism
allows single-stepping the processor on taken branches. See Section 17.4.3, “Single-Stepping on Branches,”
for more information about the BTF flag.
•
TR (trace message enable) flag (bit 6) — When set, branch trace messages are enabled. When the
processor detects a taken branch, interrupt, or exception; it sends the branch record out on the system bus as
a branch trace message (BTM). See Section 17.4.4, “Branch Trace Messages,” for more information about the
TR flag.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
BTS (branch trace store) flag (bit 7) — When set, the flag enables BTS facilities to log BTMs to a memoryresident BTS buffer that is part of the DS save area. See Section 17.4.9, “BTS and DS Save Area.”
•
BTINT (branch trace interrupt) flag (bit 8) — When set, the BTS facilities generate an interrupt when the
BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 17.4.5, “Branch
Trace Store (BTS),” for a description of this mechanism.
31
15 14
12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RTM
FREEZE_WHILE_SMM_EN
FREEZE_PERFMON_ON_PMI
FREEZE_LBRS_ON_PMI
BTS_OFF_USR — BTS off in user code
BTS_OFF_OS — BTS off in OS
BTINT — Branch trace interrupt
BTS — Branch trace store
TR — Trace messages enable
Reserved
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
Figure 17-3. IA32_DEBUGCTL MSR for Processors based
on Intel Core microarchitecture
•
BTS_OFF_OS (branch trace off in privileged code) flag (bit 9) — When set, BTS or BTM is skipped if CPL
is 0. See Section 17.11.2.
•
BTS_OFF_USR (branch trace off in user code) flag (bit 10) — When set, BTS or BTM is skipped if CPL is
greater than 0. See Section 17.11.2.
•
FREEZE_LBRS_ON_PMI flag (bit 11) — When set, the LBR stack is frozen on a hardware PMI request (e.g.
when a counter overflows and is configured to trigger PMI). See Section 17.4.7 for details.
•
FREEZE_PERFMON_ON_PMI flag (bit 12) — When set, the performance counters (IA32_PMCx and
IA32_FIXED_CTRx) are frozen on a PMI request. See Section 17.4.7 for details.
•
FREEZE_WHILE_SMM_EN (bit 14) — If this bit is set, upon the delivery of an SMI, the processor will clear all
the enable bits of IA32_PERF_GLOBAL_CTRL, save a copy of the content of IA32_DEBUGCTL and disable LBR,
BTF, TR, and BTS fields of IA32_DEBUGCTL before transferring control to the SMI handler. Subsequently, the
enable bits of IA32_PERF_GLOBAL_CTRL will be set to 1, the saved copy of IA32_DEBUGCTL prior to SMI
delivery will be restored, after the SMI handler issues RSM to complete its service. Note that system software
must check if the processor supports the IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN control bit.
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN is supported if
IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See Section 18.19 for details of
detecting the presence of IA32_PERF_CAPABILITIES MSR.
•
RTM (bit 15) — If this bit is set, advanced debugging of RTM transactional regions is enabled if DR7.RTM is
also set. See Section 17.3.3.
17.4.2
Monitoring Branches, Exceptions, and Interrupts
When the LBR flag (bit 0) in the IA32_DEBUGCTL MSR is set, the processor automatically begins recording branch
records for taken branches, interrupts, and exceptions (except for debug exceptions) in the LBR stack MSRs.
When the processor generates a debug exception (#DB), it automatically clears the LBR flag before executing the
exception handler. This action does not clear previously stored LBR stack MSRs.
A debugger can use the linear addresses in the LBR stack to re-set breakpoints in the breakpoint address registers
(DR0 through DR3). This allows a backward trace from the manifestation of a particular bug toward its source.
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On some processors, if the LBR flag is cleared and TR flag in the IA32_DEBUGCTL MSR remains set, the processor
will continue to update LBR stack MSRs. This is because those processors use the entries in the LBR stack in the
process of generating BTM/BTS records. A #DB does not automatically clear the TR flag.
17.4.3
Single-Stepping on Branches
When software sets both the BTF flag (bit 1) in the IA32_DEBUGCTL MSR and the TF flag in the EFLAGS register,
the processor generates a single-step debug exception only after instructions that cause a branch.1 This mechanism allows a debugger to single-step on control transfers caused by branches. This “branch single stepping” helps
isolate a bug to a particular block of code before instruction single-stepping further narrows the search. The
processor clears the BTF flag when it generates a debug exception. The debugger must set the BTF flag before
resuming program execution to continue single-stepping on branches.
17.4.4
Branch Trace Messages
Setting the TR flag (bit 6) in the IA32_DEBUGCTL MSR enables branch trace messages (BTMs). Thereafter, when
the processor detects a branch, exception, or interrupt, it sends a branch record out on the system bus as a BTM.
A debugging device that is monitoring the system bus can read these messages and synchronize operations with
taken branch, interrupt, and exception events.
When interrupts or exceptions occur in conjunction with a taken branch, additional BTMs are sent out on the bus,
as described in Section 17.4.2, “Monitoring Branches, Exceptions, and Interrupts.”
For P6 processor family, Pentium M processor family, processors based on Intel Core microarchitecture, TR and LBR
bits can not be set at the same time due to hardware limitation. The content of LBR stack is undefined when TR is
set.
For processors with Intel NetBurst microarchitecture, Intel Atom processors, and Intel Core and related Intel Xeon
processors both starting with the Nehalem microarchitecture, the processor can collect branch records in the LBR
stack and at the same time send/store BTMs when both the TR and LBR flags are set in the IA32_DEBUGCTL MSR
(or the equivalent MSR_DEBUGCTLA, MSR_DEBUGCTLB).
The following exception applies:
•
BTM may not be observable on Intel Atom processor families that do not provide an externally visible system
bus (i.e., processors based on the Silvermont microarchitecture or later).
17.4.4.1
Branch Trace Message Visibility
Branch trace message (BTM) visibility is implementation specific and limited to systems with a front side bus
(FSB). BTMs may not be visible to newer system link interfaces or a system bus that deviates from a traditional
FSB.
17.4.5
Branch Trace Store (BTS)
A trace of taken branches, interrupts, and exceptions is useful for debugging code by providing a method of determining the decision path taken to reach a particular code location. The LBR flag (bit 0) of IA32_DEBUGCTL provides
a mechanism for capturing records of taken branches, interrupts, and exceptions and saving them in the last
branch record (LBR) stack MSRs, setting the TR flag for sending them out onto the system bus as BTMs. The branch
trace store (BTS) mechanism provides the additional capability of saving the branch records in a memory-resident
BTS buffer, which is part of the DS save area. The BTS buffer can be configured to be circular so that the most
recent branch records are always available or it can be configured to generate an interrupt when the buffer is
nearly full so that all the branch records can be saved. The BTINT flag (bit 8) can be used to enable the generation
of interrupt when the BTS buffer is full. See Section 17.4.9.2, “Setting Up the DS Save Area.” for additional details.
1. Executions of CALL, IRET, and JMP that cause task switches never cause single-step debug exceptions (regardless of the value of the
BTF flag). A debugger desiring debug exceptions on switches to a task should set the T flag (debug trap flag) in the TSS of that task.
See Section 7.2.1, “Task-State Segment (TSS).”
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
Setting this flag (BTS) alone can greatly reduce the performance of the processor. CPL-qualified branch trace
storing mechanism can help mitigate the performance impact of sending/logging branch trace messages.
17.4.6
CPL-Qualified Branch Trace Mechanism
CPL-qualified branch trace mechanism is available to a subset of Intel 64 and IA-32 processors that support the
branch trace storing mechanism. The processor supports the CPL-qualified branch trace mechanism if
CPUID.01H:ECX[bit 4] = 1.
The CPL-qualified branch trace mechanism is described in Section 17.4.9.4. System software can selectively specify
CPL qualification to not send/store Branch Trace Messages associated with a specified privilege level. Two bit fields,
BTS_OFF_USR (bit 10) and BTS_OFF_OS (bit 9), are provided in the debug control register to specify the CPL of
BTMs that will not be logged in the BTS buffer or sent on the bus.
17.4.7
Freezing LBR and Performance Counters on PMI
Many issues may generate a performance monitoring interrupt (PMI); a PMI service handler will need to determine
cause to handle the situation. Two capabilities that allow a PMI service routine to improve branch tracing and
performance monitoring are available for processors supporting architectural performance monitoring version 2 or
greater (i.e. CPUID.0AH:EAX[7:0] > 1). These capabilities provides the following interface in IA32_DEBUGCTL to
reduce runtime overhead of PMI servicing, profiler-contributed skew effects on analysis or counter metrics:
•
Freezing LBRs on PMI (bit 11)— Allows the PMI service routine to ensure the content in the LBR stack are
associated with the target workload and not polluted by the branch flows of handling the PMI. Depending on the
version ID enumerated by CPUID.0AH:EAX.ArchPerfMonVerID[bits 7:0], two flavors are supported:
— Legacy Freeze_LBR_on_PMI is supported for ArchPerfMonVerID <= 3 and ArchPerfMonVerID >1. If
IA32_DEBUGCTL.Freeze_LBR_On_PMI = 1, the LBR is frozen on the overflowed condition of the buffer
area, the processor clears the LBR bit (bit 0) in IA32_DEBUGCTL. Software must then re-enable
IA32_DEBUGCTL.LBR to resume recording branches. When using this feature, software should be careful
about writes to IA32_DEBUGCTL to avoid re-enabling LBRs by accident if they were just disabled.
— Streamlined Freeze_LBR_on_PMI is supported for ArchPerfMonVerID >= 4. If
IA32_DEBUGCTL.Freeze_LBR_On_PMI = 1, the processor behaves as follows:
•
•
sets IA32_PERF_GLOBAL_STATUS.LBR_Frz =1 to disable recording, but does not change the LBR bit
(bit 0) in IA32_DEBUGCTL. The LBRs are frozen on the overflowed condition of the buffer area.
Freezing PMCs on PMI (bit 12) — Allows the PMI service routine to ensure the content in the performance
counters are associated with the target workload and not polluted by the PMI and activities within the PMI
service routine. Depending on the version ID enumerated by CPUID.0AH:EAX.ArchPerfMonVerID[bits 7:0], two
flavors are supported:
— Legacy Freeze_Perfmon_on_PMI is supported for ArchPerfMonVerID <= 3 and ArchPerfMonVerID >1. If
IA32_DEBUGCTL.Freeze_Perfmon_On_PMI = 1, the performance counters are frozen on the counter
overflowed condition when the processor clears the IA32_PERF_GLOBAL_CTRL MSR (see Figure 18-3). The
PMCs affected include both general-purpose counters and fixed-function counters (see Section 18.4.1,
“Fixed-function Performance Counters”). Software must re-enable counts by writing 1s to the corresponding enable bits in IA32_PERF_GLOBAL_CTRL before leaving a PMI service routine to continue counter
operation.
— Streamlined Freeze_Perfmon_on_PMI is supported for ArchPerfMonVerID >= 4. The processor behaves as
follows:
•
sets IA32_PERF_GLOBAL_STATUS.CTR_Frz =1 to disable counting on a counter overflow condition, but
does not change the IA32_PERF_GLOBAL_CTRL MSR.
Freezing LBRs and PMCs on PMIs (both legacy and streamlined operation) occur when one of the following applies:
•
A performance counter had an overflow and was programmed to signal a PMI in case of an overflow.
— For the general-purpose counters; enabling PMI is done by setting bit 20 of the IA32_PERFEVTSELx
register.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
— For the fixed-function counters; enabling PMI is done by setting the 3rd bit in the corresponding 4-bit
control field of the MSR_PERF_FIXED_CTR_CTRL register (see Figure 18-1) or IA32_FIXED_CTR_CTRL MSR
(see Figure 18-2).
•
•
The PEBS buffer is almost full and reaches the interrupt threshold.
The BTS buffer is almost full and reaches the interrupt threshold.
Table 17-3 compares the interaction of the processor with the PMI handler using the legacy versus streamlined
Freeza_Perfmon_On_PMI interface.
Table 17-3. Legacy and Streamlined Operation with Freeze_Perfmon_On_PMI = 1, Counter Overflowed
Legacy Freeze_Perfmon_On_PMI
Streamlined Freeze_Perfmon_On_PMI
Comment
Processor freezes the counters on overflow
Processor freezes the counters on overflow
Unchanged
Processor clears IA32_PERF_GLOBAL_CTRL
Processor set
IA32_PERF_GLOBAL_STATUS.CTR_FTZ
Handler reads IA32_PERF_GLOBAL_STATUS
mask = RDMSR(0x38E)
(0x38E) to examine which counter(s) overflowed
Similar
Handler services the PMI
Handler services the PMI
Unchanged
Handler writes 1s to
IA32_PERF_GLOBAL_OVF_CTL (0x390)
Handler writes mask into
IA32_PERF_GLOBAL_OVF_RESET (0x390)
Processor clears IA32_PERF_GLOBAL_STATUS
Processor clears IA32_PERF_GLOBAL_STATUS Unchanged
Handler re-enables IA32_PERF_GLOBAL_CTRL
None
17.4.8
Reduced software overhead
LBR Stack
The last branch record stack and top-of-stack (TOS) pointer MSRs are supported across Intel 64 and IA-32
processor families. However, the number of MSRs in the LBR stack and the valid range of TOS pointer value can
vary between different processor families. Table 17-4 lists the LBR stack size and TOS pointer range for several
processor families according to the CPUID signatures of DisplayFamily_DisplayModel encoding (see CPUID instruction in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).
Table 17-4. LBR Stack Size and TOS Pointer Range
DisplayFamily_DisplayModel
Size of LBR Stack
Component of an LBR Entry
Range of TOS Pointer
06_5CH, 06_5FH
32
FROM_IP, TO_IP
0 to 31
1
06_4EH, 06_5EH, 06_8EH, 06_9EH
32
FROM_IP, TO_IP, LBR_INFO
0 to 31
06_3DH, 06_47H, 06_4FH, 06_56H
16
FROM_IP, TO_IP
0 to 15
06_3CH, 06_45H, 06_46H, 06_3FH
16
FROM_IP, TO_IP
0 to 15
06_2AH, 06_2DH, 06_3AH, 06_3EH
16
FROM_IP, TO_IP
0 to 15
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H,
06_2CH, 06_2FH
16
FROM_IP, TO_IP
0 to 15
06_17H, 06_1DH
4
FROM_IP, TO_IP
0 to 3
06_0FH
4
FROM_IP, TO_IP
0 to 3
06_37H, 06_4AH, 06_4CH, 06_4DH, 06_5AH,
06_5DH
8
FROM_IP, TO_IP
0 to 7
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
8
FROM_IP, TO_IP
0 to 7
NOTES:
1. See Section 17.10.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
The last branch recording mechanism tracks not only branch instructions (like JMP, Jcc, LOOP and CALL instructions), but also other operations that cause a change in the instruction pointer (like external interrupts, traps and
faults). The branch recording mechanisms generally employs a set of MSRs, referred to as last branch record (LBR)
stack. The size and exact locations of the LBR stack are generally model-specific (see Chapter 35, “Model-Specific
Registers (MSRs)” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C for modelspecific MSR addresses).
•
Last Branch Record (LBR) Stack — The LBR consists of N pairs of MSRs (N is listed in the LBR stack size
column of Table 17-4) that store source and destination address of recent branches (see Figure 17-3):
— MSR_LASTBRANCH_0_FROM_IP (address is model specific) through the next consecutive (N-1) MSR
address store source addresses.
— MSR_LASTBRANCH_0_TO_IP (address is model specific ) through the next consecutive (N-1) MSR address
store destination addresses.
•
Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant M bits of the TOS Pointer MSR
(MSR_LASTBRANCH_TOS, address is model specific) contains an M-bit pointer to the MSR in the LBR stack that
contains the most recent branch, interrupt, or exception recorded. The valid range of the M-bit POS pointer is
given in Table 17-4.
17.4.8.1
LBR Stack and Intel® 64 Processors
LBR MSRs are 64-bits. In 64-bit mode, last branch records store the full address. Outside of 64-bit mode, the upper
32-bits of branch addresses will be stored as 0.
MSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_(N-1)_FROM_IP
0
63
Source Address
MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_(N-1)_TO_IP
0
63
Destination Address
Figure 17-4. 64-bit Address Layout of LBR MSR
Software should query an architectural MSR IA32_PERF_CAPABILITIES[5:0] about the format of the address that
is stored in the LBR stack. Four formats are defined by the following encoding:
— 000000B (32-bit record format) — Stores 32-bit offset in current CS of respective source/destination,
— 000001B (64-bit LIP record format) — Stores 64-bit linear address of respective source/destination,
— 000010B (64-bit EIP record format) — Stores 64-bit offset (effective address) of respective
source/destination.
— 000011B (64-bit EIP record format) and Flags — Stores 64-bit offset (effective address) of respective
source/destination. Misprediction info is reported in the upper bit of 'FROM' registers in the LBR stack. See
LBR stack details below for flag support and definition.
— 000100B (64-bit EIP record format), Flags and TSX — Stores 64-bit offset (effective address) of
respective source/destination. Misprediction and TSX info are reported in the upper bits of ‘FROM’ registers
in the LBR stack.
— 000101B (64-bit EIP record format), Flags, TSX, LBR_INFO — Stores 64-bit offset (effective
address) of respective source/destination. Misprediction, TSX, and elapsed cycles since the last LBR update
are reported in the LBR_INFO MSR stack.
— 000110B (64-bit EIP record format), Flags, Cycles — Stores 64-bit linear address (CS.Base +
effective address) of respective source/destination. Misprediction info is reported in the upper bits of
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
'FROM' registers in the LBR stack. Elapsed cycles since the last LBR update are reported in the upper 16 bits
of the 'TO' registers in the LBR stack (see Section 17.6).
Processor’s support for the architectural MSR IA32_PERF_CAPABILITIES is provided by
CPUID.01H:ECX[PERF_CAPAB_MSR] (bit 15).
17.4.8.2
LBR Stack and IA-32 Processors
The LBR MSRs in IA-32 processors introduced prior to Intel 64 architecture store the 32-bit “To Linear Address” and
“From Linear Address“ using the high and low half of each 64-bit MSR.
17.4.8.3
Last Exception Records and Intel 64 Architecture
Intel 64 and IA-32 processors also provide MSRs that store the branch record for the last branch taken prior to an
exception or an interrupt. The location of the last exception record (LER) MSRs are model specific. The MSRs that
store last exception records are 64-bits. If IA-32e mode is disabled, only the lower 32-bits of the address is
recorded. If IA-32e mode is enabled, the processor writes 64-bit values into the MSR. In 64-bit mode, last exception records store 64-bit addresses; in compatibility mode, the upper 32-bits of last exception records are cleared.
17.4.9
BTS and DS Save Area
The Debug store (DS) feature flag (bit 21), returned by CPUID.1:EDX[21] indicates that the processor provides
the debug store (DS) mechanism. The DS mechanism allows:
•
•
BTMs to be stored in a memory-resident BTS buffer. See Section 17.4.5, “Branch Trace Store (BTS).”
Processor event-based sampling (PEBS) also uses the DS save area provided by debug store mechanism. The
capability of PEBS varies across different microarchitectures. See Section 18.4.4, “Processor Event Based
Sampling (PEBS),” and the relevant PEBS sub-sections across the core PMU sections in Chapter 18, “Performance Monitoring.”.
When CPUID.1:EDX[21] is set:
•
The BTS_UNAVAILABLE and PEBS_UNAVAILABLE flags in the IA32_MISC_ENABLE MSR indicate (when clear)
the availability of the BTS and PEBS facilities, including the ability to set the BTS and BTINT bits in the
appropriate DEBUGCTL MSR.
•
The IA32_DS_AREA MSR exists and points to the DS save area.
The debug store (DS) save area is a software-designated area of memory that is used to collect the following two
types of information:
•
Branch records — When the BTS flag in the IA32_DEBUGCTL MSR is set, a branch record is stored in the BTS
buffer in the DS save area whenever a taken branch, interrupt, or exception is detected.
•
PEBS records — When a performance counter is configured for PEBS, a PEBS record is stored in the PEBS
buffer in the DS save area after the counter overflow occurs. This record contains the architectural state of the
processor (state of the 8 general purpose registers, EIP register, and EFLAGS register) at the next occurrence
of the PEBS event that caused the counter to overflow. When the state information has been logged, the
counter is automatically reset to a specified value, and event counting begins again. The content layout of a
PEBS record varies across different implementations that support PEBS. See Section 18.4.4.2 for details of
enumerating PEBS record format.
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NOTES
Prior to processors based on the Goldmont microarchitecture, PEBS facility only supports a subset
of implementation-specific precise events. See Section 18.7.1 for a PEBS enhancement that can
generate records for both precise and non-precise events.
The DS save area and recording mechanism are disabled on INIT, processor Reset or transition to
system-management mode (SMM) or IA-32e mode. It is similarly disabled on the generation of a
machine-check exception on 45nm and 32nm Intel Atom processors and on processors with
Netburst or Intel Core microarchitecture.
The BTS and PEBS facilities may not be available on all processors. The availability of these facilities
is indicated by the BTS_UNAVAILABLE and PEBS_UNAVAILABLE flags, respectively, in the
IA32_MISC_ENABLE MSR (see Chapter 35).
The DS save area is divided into three parts (see Figure 17-5): buffer management area, branch trace store (BTS)
buffer, and PEBS buffer. The buffer management area is used to define the location and size of the BTS and PEBS
buffers. The processor then uses the buffer management area to keep track of the branch and/or PEBS records in
their respective buffers and to record the performance counter reset value. The linear address of the first byte of
the DS buffer management area is specified with the IA32_DS_AREA MSR.
The fields in the buffer management area are as follows:
•
BTS buffer base — Linear address of the first byte of the BTS buffer. This address should point to a natural
doubleword boundary.
•
BTS index — Linear address of the first byte of the next BTS record to be written to. Initially, this address
should be the same as the address in the BTS buffer base field.
•
BTS absolute maximum — Linear address of the next byte past the end of the BTS buffer. This address should
be a multiple of the BTS record size (12 bytes) plus 1.
•
BTS interrupt threshold — Linear address of the BTS record on which an interrupt is to be generated. This
address must point to an offset from the BTS buffer base that is a multiple of the BTS record size. Also, it must
be several records short of the BTS absolute maximum address to allow a pending interrupt to be handled prior
to processor writing the BTS absolute maximum record.
•
PEBS buffer base — Linear address of the first byte of the PEBS buffer. This address should point to a natural
doubleword boundary.
•
PEBS index — Linear address of the first byte of the next PEBS record to be written to. Initially, this address
should be the same as the address in the PEBS buffer base field.
•
PEBS absolute maximum — Linear address of the next byte past the end of the PEBS buffer. This address
should be a multiple of the PEBS record size (40 bytes) plus 1.
•
PEBS interrupt threshold — Linear address of the PEBS record on which an interrupt is to be generated. This
address must point to an offset from the PEBS buffer base that is a multiple of the PEBS record size. Also, it
must be several records short of the PEBS absolute maximum address to allow a pending interrupt to be
handled prior to processor writing the PEBS absolute maximum record.
•
PEBS counter reset value — A 40-bit value that the counter is to be reset to after state information has
collected following counter overflow. This value allows state information to be collected after a preset number
of events have been counted.
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IA32_DS_AREA MSR
DS Buffer Management Area
BTS Buffer Base
0H
BTS Index
4H
BTS Absolute
Maximum
BTS Interrupt
Threshold
BTS Buffer
Branch Record 0
8H
Branch Record 1
CH
PEBS Buffer Base 10H
PEBS Index
PEBS Absolute
Maximum
PEBS Interrupt
Threshold
PEBS
Counter Reset
Reserved
14H
18H
Branch Record n
1CH
20H
24H
PEBS Buffer
30H
PEBS Record 0
PEBS Record 1
PEBS Record n
Figure 17-5. DS Save Area
Figures 17-6 shows the structure of a 12-byte branch record in the BTS buffer. The fields in each record are as
follows:
•
Last branch from — Linear address of the instruction from which the branch, interrupt, or exception was
taken.
•
Last branch to — Linear address of the branch target or the first instruction in the interrupt or exception
service routine.
•
Branch predicted — Bit 4 of field indicates whether the branch that was taken was predicted (set) or not
predicted (clear).
31
4
0
Last Branch From
0H
Last Branch To
4H
8H
Branch Predicted
Figure 17-6. 32-bit Branch Trace Record Format
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Figure 17-7 shows the structure of the 40-byte PEBS records. Nominally the register values are those at the beginning of the instruction that caused the event. However, there are cases where the registers may be logged in a
partially modified state. The linear IP field shows the value in the EIP register translated from an offset into the
current code segment to a linear address.
31
0
EFLAGS
0H
Linear IP
4H
EAX
8H
EBX
CH
ECX
10H
EDX
14H
ESI
18H
EDI
1CH
EBP
20H
ESP
24H
Figure 17-7. PEBS Record Format
17.4.9.1
64 Bit Format of the DS Save Area
When DTES64 = 1 (CPUID.1.ECX[2] = 1), the structure of the DS save area is shown in Figure 17-8.
When DTES64 = 0 (CPUID.1.ECX[2] = 0) and IA-32e mode is active, the structure of the DS save area is shown in
Figure 17-8. If IA-32e mode is not active the structure of the DS save area is as shown in Figure 17-6.
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IA32_DS_AREA MSR
DS Buffer Management Area
BTS Buffer Base
0H
BTS Index
8H
BTS Absolute
Maximum
BTS Interrupt
Threshold
BTS Buffer
Branch Record 0
10H
Branch Record 1
18H
PEBS Buffer Base 20H
PEBS Index
PEBS Absolute
Maximum
PEBS Interrupt
Threshold
PEBS
Counter Reset
Reserved
28H
30H
Branch Record n
38H
40H
48H
PEBS Buffer
50H
PEBS Record 0
PEBS Record 1
PEBS Record n
Figure 17-8. IA-32e Mode DS Save Area
The IA32_DS_AREA MSR holds the 64-bit linear address of the first byte of the DS buffer management area. The
structure of a branch trace record is similar to that shown in Figure 17-6, but each field is 8 bytes in length. This
makes each BTS record 24 bytes (see Figure 17-9). The structure of a PEBS record is similar to that shown in
Figure 17-7, but each field is 8 bytes in length and architectural states include register R8 through R15. This makes
the size of a PEBS record in 64-bit mode 144 bytes (see Figure 17-10).
63
4
0
Last Branch From
0H
Last Branch To
8H
10H
Branch Predicted
Figure 17-9. 64-bit Branch Trace Record Format
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
63
0
RFLAGS
0H
RIP
8H
RAX
10H
RBX
18H
RCX
20H
RDX
28H
RSI
30H
RDI
38H
RBP
40H
RSP
48H
R8
50H
...
...
R15
88H
Figure 17-10. 64-bit PEBS Record Format
Fields in the buffer management area of a DS save area are described in Section 17.4.9.
The format of a branch trace record and a PEBS record are the same as the 64-bit record formats shown in Figures
17-9 and Figures 17-10, with the exception that the branch predicted bit is not supported by Intel Core microarchitecture or Intel Atom microarchitecture. The 64-bit record formats for BTS and PEBS apply to DS save area for all
operating modes.
The procedures used to program IA32_DEBUGCTL MSR to set up a BTS buffer or a CPL-qualified BTS are described
in Section 17.4.9.3 and Section 17.4.9.4.
Required elements for writing a DS interrupt service routine are largely the same on processors that support using
DS Save area for BTS or PEBS records. However, on processors based on Intel NetBurst® microarchitecture, reenabling counting requires writing to CCCRs. But a DS interrupt service routine on processors supporting architectural performance monitoring should:
•
•
Re-enable the enable bits in IA32_PERF_GLOBAL_CTRL MSR if it is servicing an overflow PMI due to PEBS.
Clear overflow indications by writing to IA32_PERF_GLOBAL_OVF_CTRL when a counting configuration is
changed. This includes bit 62 (ClrOvfBuffer) and the overflow indication of counters used in either PEBS or
general-purpose counting (specifically: bits 0 or 1; see Figures 18-3).
17.4.9.2
Setting Up the DS Save Area
To save branch records with the BTS buffer, the DS save area must first be set up in memory as described in the
following procedure (See Section 18.4.4.1, “Setting up the PEBS Buffer,” for instructions for setting up a PEBS
buffer, respectively, in the DS save area):
1. Create the DS buffer management information area in memory (see Section 17.4.9, “BTS and DS Save Area,”
and Section 17.4.9.1, “64 Bit Format of the DS Save Area”). Also see the additional notes in this section.
2. Write the base linear address of the DS buffer management area into the IA32_DS_AREA MSR.
3. Set up the performance counter entry in the xAPIC LVT for fixed delivery and edge sensitive. See Section
10.5.1, “Local Vector Table.”
4. Establish an interrupt handler in the IDT for the vector associated with the performance counter entry in the
xAPIC LVT.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
5. Write an interrupt service routine to handle the interrupt. See Section 17.4.9.5, “Writing the DS Interrupt
Service Routine.”
The following restrictions should be applied to the DS save area.
•
The three DS save area sections should be allocated from a non-paged pool, and marked accessed and dirty. It
is the responsibility of the operating system to keep the pages that contain the buffer present and to mark
them accessed and dirty. The implication is that the operating system cannot do “lazy” page-table entry
propagation for these pages.
•
The DS save area can be larger than a page, but the pages must be mapped to contiguous linear addresses.
The buffer may share a page, so it need not be aligned on a 4-KByte boundary. For performance reasons, the
base of the buffer must be aligned on a doubleword boundary and should be aligned on a cache line boundary.
•
It is recommended that the buffer size for the BTS buffer and the PEBS buffer be an integer multiple of the
corresponding record sizes.
•
The precise event records buffer should be large enough to hold the number of precise event records that can
occur while waiting for the interrupt to be serviced.
•
The DS save area should be in kernel space. It must not be on the same page as code, to avoid triggering selfmodifying code actions.
•
There are no memory type restrictions on the buffers, although it is recommended that the buffers be
designated as WB memory type for performance considerations.
•
Either the system must be prevented from entering A20M mode while DS save area is active, or bit 20 of all
addresses within buffer bounds must be 0.
•
Pages that contain buffers must be mapped to the same physical addresses for all processes, such that any
change to control register CR3 will not change the DS addresses.
•
The DS save area is expected to used only on systems with an enabled APIC. The LVT Performance Counter
entry in the APCI must be initialized to use an interrupt gate instead of the trap gate.
17.4.9.3
Setting Up the BTS Buffer
Three flags in the MSR_DEBUGCTLA MSR (see Table 17-5), IA32_DEBUGCTL (see Figure 17-3), or
MSR_DEBUGCTLB (see Figure 17-16) control the generation of branch records and storing of them in the BTS
buffer; these are TR, BTS, and BTINT. The TR flag enables the generation of BTMs. The BTS flag determines
whether the BTMs are sent out on the system bus (clear) or stored in the BTS buffer (set). BTMs cannot be simultaneously sent to the system bus and logged in the BTS buffer. The BTINT flag enables the generation of an interrupt when the BTS buffer is full. When this flag is clear, the BTS buffer is a circular buffer.
Table 17-5. IA32_DEBUGCTL Flag Encodings
TR
BTS
BTINT
Description
0
X
X
Branch trace messages (BTMs) off
1
0
X
Generate BTMs
1
1
0
Store BTMs in the BTS buffer, used here as a circular buffer
1
1
1
Store BTMs in the BTS buffer, and generate an interrupt when the buffer is nearly full
The following procedure describes how to set up a DS Save area to collect branch records in the BTS buffer:
1. Place values in the BTS buffer base, BTS index, BTS absolute maximum, and BTS interrupt threshold fields of
the DS buffer management area to set up the BTS buffer in memory.
2. Set the TR and BTS flags in the IA32_DEBUGCTL for Intel Core Solo and Intel Core Duo processors or later
processors (or MSR_DEBUGCTLA MSR for processors based on Intel NetBurst Microarchitecture; or
MSR_DEBUGCTLB for Pentium M processors).
3. Clear the BTINT flag in the corresponding IA32_DEBUGCTL (or MSR_DEBUGCTLA MSR; or MSR_DEBUGCTLB)
if a circular BTS buffer is desired.
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NOTES
If the buffer size is set to less than the minimum allowable value (i.e. BTS absolute maximum < 1
+ size of BTS record), the results of BTS is undefined.
In order to prevent generating an interrupt, when working with circular BTS buffer, SW need to set
BTS interrupt threshold to a value greater than BTS absolute maximum (fields of the DS buffer
management area). It's not enough to clear the BTINT flag itself only.
17.4.9.4
Setting Up CPL-Qualified BTS
If the processor supports CPL-qualified last branch recording mechanism, the generation of branch records and
storing of them in the BTS buffer are determined by: TR, BTS, BTS_OFF_OS, BTS_OFF_USR, and BTINT. The
encoding of these five bits are shown in Table 17-6.
Table 17-6. CPL-Qualified Branch Trace Store Encodings
TR
BTS
BTS_OFF_OS
BTS_OFF_USR
BTINT
Description
0
X
X
X
X
Branch trace messages (BTMs) off
1
0
X
X
X
Generates BTMs but do not store BTMs
1
1
0
0
0
Store all BTMs in the BTS buffer, used here as a circular buffer
1
1
1
0
0
Store BTMs with CPL > 0 in the BTS buffer
1
1
0
1
0
Store BTMs with CPL = 0 in the BTS buffer
1
1
1
1
X
Generate BTMs but do not store BTMs
1
1
0
0
1
Store all BTMs in the BTS buffer; generate an interrupt when the
buffer is nearly full
1
1
1
0
1
Store BTMs with CPL > 0 in the BTS buffer; generate an interrupt
when the buffer is nearly full
1
1
0
1
1
Store BTMs with CPL = 0 in the BTS buffer; generate an interrupt
when the buffer is nearly full
17.4.9.5
Writing the DS Interrupt Service Routine
The BTS, non-precise event-based sampling, and PEBS facilities share the same interrupt vector and interrupt
service routine (called the debug store interrupt service routine or DS ISR). To handle BTS, non-precise eventbased sampling, and PEBS interrupts: separate handler routines must be included in the DS ISR. Use the following
guidelines when writing a DS ISR to handle BTS, non-precise event-based sampling, and/or PEBS interrupts.
•
The DS interrupt service routine (ISR) must be part of a kernel driver and operate at a current privilege level of
0 to secure the buffer storage area.
•
Because the BTS, non-precise event-based sampling, and PEBS facilities share the same interrupt vector, the
DS ISR must check for all the possible causes of interrupts from these facilities and pass control on to the
appropriate handler.
BTS and PEBS buffer overflow would be the sources of the interrupt if the buffer index matches/exceeds the
interrupt threshold specified. Detection of non-precise event-based sampling as the source of the interrupt is
accomplished by checking for counter overflow.
•
•
There must be separate save areas, buffers, and state for each processor in an MP system.
•
The processor will not disable the DS save area when the buffer is full and the circular mode has not been
selected. The current DS setting must be retained and restored by the ISR on exit.
Upon entering the ISR, branch trace messages and PEBS should be disabled to prevent race conditions during
access to the DS save area. This is done by clearing TR flag in the IA32_DEBUGCTL (or MSR_DEBUGCTLA MSR)
and by clearing the precise event enable flag in the MSR_PEBS_ENABLE MSR. These settings should be
restored to their original values when exiting the ISR.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
After reading the data in the appropriate buffer, up to but not including the current index into the buffer, the ISR
must reset the buffer index to the beginning of the buffer. Otherwise, everything up to the index will look like
new entries upon the next invocation of the ISR.
•
•
The ISR must clear the mask bit in the performance counter LVT entry.
•
The Pentium 4 Processor and Intel Xeon Processor mask PMIs upon receiving an interrupt. Clear this condition
before leaving the interrupt handler.
The ISR must re-enable the counters to count via IA32_PERF_GLOBAL_CTRL/IA32_PERF_GLOBAL_OVF_CTRL
if it is servicing an overflow PMI due to PEBS (or via CCCR's ENABLE bit on processor based on Intel NetBurst
microarchitecture).
17.5
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ 2
DUO AND INTEL® ATOM™ PROCESSORS)
The Intel Core 2 Duo processor family and Intel Xeon processors based on Intel Core microarchitecture or
enhanced Intel Core microarchitecture provide last branch interrupt and exception recording. The facilities
described in this section also apply to 45 nm and 32 nm Intel Atom processors. These capabilities are similar to
those found in Pentium 4 processors, including support for the following facilities:
•
Debug Trace and Branch Recording Control — The IA32_DEBUGCTL MSR provide bit fields for software to
configure mechanisms related to debug trace, branch recording, branch trace store, and performance counter
operations. See Section 17.4.1 for a description of the flags. See Figure 17-3 for the MSR layout.
•
Last branch record (LBR) stack — There are a collection of MSR pairs that store the source and destination
addresses related to recently executed branches. See Section 17.5.1.
•
Monitoring and single-stepping of branches, exceptions, and interrupts
— See Section 17.4.2 and Section 17.4.3. In addition, the ability to freeze the LBR stack on a PMI request is
available.
— 45 nm and 32 nm Intel Atom processors clear the TR flag when the FREEZE_LBRS_ON_PMI flag is set.
•
•
•
•
•
Branch trace messages — See Section 17.4.4.
•
FREEZE_WHILE_SMM_EN (bit 14) — FREEZE_WHILE_SMM_EN is supported if
IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See Section 17.4.1.
Last exception records — See Section 17.11.3.
Branch trace store and CPL-qualified BTS — See Section 17.4.5.
FREEZE_LBRS_ON_PMI flag (bit 11) — see Section 17.4.7 for legacy Freeze_LBRs_On_PMI operation.
FREEZE_PERFMON_ON_PMI flag (bit 12) — see Section 17.4.7 for legacy Freeze_Perfmon_On_PMI
operation.
17.5.1
LBR Stack
The last branch record stack and top-of-stack (TOS) pointer MSRs are supported across Intel Core 2, Intel Atom
processor families, and Intel processors based on Intel NetBurst microarchitecture.
Four pairs of MSRs are supported in the LBR stack for Intel Core 2 processors families and Intel processors based
on Intel NetBurst microarchitecture:
•
Last Branch Record (LBR) Stack
— MSR_LASTBRANCH_0_FROM_IP (address 40H) through MSR_LASTBRANCH_3_FROM_IP (address 43H)
store source addresses
— MSR_LASTBRANCH_0_TO_IP (address 60H) through MSR_LASTBRANCH_3_TO_IP (address 63H) store
destination addresses
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant 2 bits of the TOS Pointer MSR
(MSR_LASTBRANCH_TOS, address 1C9H) contains a pointer to the MSR in the LBR stack that contains the most
recent branch, interrupt, or exception recorded.
Eight pairs of MSRs are supported in the LBR stack for 45 nm and 32 nm Intel Atom processors:
•
Last Branch Record (LBR) Stack
— MSR_LASTBRANCH_0_FROM_IP (address 40H) through MSR_LASTBRANCH_7_FROM_IP (address 47H)
store source addresses
— MSR_LASTBRANCH_0_TO_IP (address 60H) through MSR_LASTBRANCH_7_TO_IP (address 67H) store
destination addresses
•
Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant 3 bits of the TOS Pointer MSR
(MSR_LASTBRANCH_TOS, address 1C9H) contains a pointer to the MSR in the LBR stack that contains the most
recent branch, interrupt, or exception recorded.
The address format written in the FROM_IP/TO_IP MSRS may differ between processors. Software should query
IA32_PERF_CAPABILITIES[5:0] and consult Section 17.4.8.1. The behavior of the MSR_LER_TO_LIP and the
MSR_LER_FROM_LIP MSRs corresponds to that of the LastExceptionToIP and LastExceptionFromIP MSRs found in
P6 family processors.
17.5.2
LBR Stack in Intel Atom Processors based on the Silvermont Microarchitecture
The last branch record stack and top-of-stack (TOS) pointer MSRs are supported in Intel Atom processors based on
the Silvermont and Airmont microarchitectures. Eight pairs of MSRs are supported in the LBR stack.
LBR filtering is supported. Filtering of LBRs based on a combination of CPL and branch type conditions is supported.
When LBR filtering is enabled, the LBR stack only captures the subset of branches that are specified by
MSR_LBR_SELECT. The layout of MSR_LBR_SELECT is described in Table 17-11.
17.6
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING
FOR PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE
Next generation Intel Atom processors are based on the Goldmont microarchitecture. Processors based on the
Goldmont microarchitecture extend the capabilities described in Section 17.5.2 with the following enhancements:
•
•
Supports new LBR format encoding 00110b in IA32_PERF_CAPABILITIES[5:0].
•
LBR call stack filtering supported. The layout of MSR_LBR_SELECT is described in Table 17-13.
•
Elapsed cycle information is added to MSR_LASTBRANCH_x_TO_IP. Format is shown in Table 17-7.
•
Misprediction info is reported in the upper bits of MSR_LASTBRANCH_x_FROM_IP. MISPRED bit format is
shown in Table 17-8.
•
Streamlined Freeze_LBRs_On_PMI operation; see Section 17.10.2.
Size of LBR stack increased to 32. Each entry includes MSR_LASTBRANCH_x_FROM_IP (address 0x680..0x69f)
and MSR_LASTBRANCH_x_TO_IP (address 0x6c0..0x6df).
• LBR MSRs may be cleared when MWAIT is used to request a C-state that is numerically higher than C1; see
Section 17.10.3.
Table 17-7. MSR_LASTBRANCH_x_TO_IP for the Goldmont Microarchitecture
Bit Field
Bit Offset
Access
Description
Data
47:0
R/O
This is the “branch to“ address. See Section 17.4.8.1 for address format.
Cycle Count
(Saturating)
63:48
R/0
Elapsed core clocks since last update to the LBR stack.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.7
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR
PROCESSORS BASED ON INTEL® MICROARCHITECTURE CODE NAME
NEHALEM
The processors based on Intel® microarchitecture code name Nehalem and Intel® microarchitecture code name
Westmere support last branch interrupt and exception recording. These capabilities are similar to those found in
Intel Core 2 processors and adds additional capabilities:
•
Debug Trace and Branch Recording Control — The IA32_DEBUGCTL MSR provides bit fields for software to
configure mechanisms related to debug trace, branch recording, branch trace store, and performance counter
operations. See Section 17.4.1 for a description of the flags. See Figure 17-11 for the MSR layout.
•
Last branch record (LBR) stack — There are 16 MSR pairs that store the source and destination addresses
related to recently executed branches. See Section 17.7.1.
•
Monitoring and single-stepping of branches, exceptions, and interrupts — See Section 17.4.2 and
Section 17.4.3. In addition, the ability to freeze the LBR stack on a PMI request is available.
•
Branch trace messages — The IA32_DEBUGCTL MSR provides bit fields for software to enable each logical
processor to generate branch trace messages. See Section 17.4.4. However, not all BTM messages are
observable using the Intel® QPI link.
•
•
•
•
Last exception records — See Section 17.11.3.
•
UNCORE_PMI_EN (bit 13) — When set. this logical processor is enabled to receive an counter overflow
interrupt form the uncore.
•
FREEZE_WHILE_SMM_EN (bit 14) — FREEZE_WHILE_SMM_EN is supported if
IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See Section 17.4.1.
Branch trace store and CPL-qualified BTS — See Section 17.4.6 and Section 17.4.5.
FREEZE_LBRS_ON_PMI flag (bit 11) — see Section 17.4.7 for legacy Freeze_LBRs_On_PMI operation.
FREEZE_PERFMON_ON_PMI flag (bit 12) — see Section 17.4.7 for legacy Freeze_Perfmon_On_PMI
operation.
Processors based on Intel microarchitecture code name Nehalem provide additional capabilities:
•
Independent control of uncore PMI — The IA32_DEBUGCTL MSR provides a bit field (see Figure 17-11) for
software to enable each logical processor to receive an uncore counter overflow interrupt.
•
LBR filtering — Processors based on Intel microarchitecture code name Nehalem support filtering of LBR
based on combination of CPL and branch type conditions. When LBR filtering is enabled, the LBR stack only
captures the subset of branches that are specified by MSR_LBR_SELECT.
31
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FREEZE_WHILE_SMM_EN
UNCORE_PMI_EN
FREEZE_PERFMON_ON_PMI
FREEZE_LBRS_ON_PMI
BTS_OFF_USR — BTS off in user code
BTS_OFF_OS — BTS off in OS
BTINT — Branch trace interrupt
BTS — Branch trace store
TR — Trace messages enable
Reserved
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
Figure 17-11. IA32_DEBUGCTL MSR for Processors based
on Intel microarchitecture code name Nehalem
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.7.1
LBR Stack
Processors based on Intel microarchitecture code name Nehalem provide 16 pairs of MSR to record last branch
record information. The layout of each MSR pair is shown in Table 17-8 and Table 17-9.
Table 17-8. MSR_LASTBRANCH_x_FROM_IP
Bit Field
Bit Offset
Access
Description
Data
47:0
R/O
This is the “branch from“ address. See Section 17.4.8.1 for address format.
SIGN_EXt
62:48
R/0
Signed extension of bit 47 of this register.
MISPRED
63
R/O
When set, indicates either the target of the branch was mispredicted and/or the
direction (taken/non-taken) was mispredicted; otherwise, the target branch was
predicted.
Table 17-9. MSR_LASTBRANCH_x_TO_IP
Bit Field
Bit Offset
Access
Description
Data
47:0
R/O
This is the “branch to“ address. See Section 17.4.8.1 for address format
SIGN_EXt
63:48
R/0
Signed extension of bit 47 of this register.
Processors based on Intel microarchitecture code name Nehalem have an LBR MSR Stack as shown in Table 17-10.
Table 17-10. LBR Stack Size and TOS Pointer Range
DisplayFamily_DisplayModel
Size of LBR Stack
Range of TOS Pointer
06_1AH
16
0 to 15
17.7.2
Filtering of Last Branch Records
MSR_LBR_SELECT is cleared to zero at RESET, and LBR filtering is disabled, i.e. all branches will be captured.
MSR_LBR_SELECT provides bit fields to specify the conditions of subsets of branches that will not be captured in
the LBR. The layout of MSR_LBR_SELECT is shown in Table 17-11.
Table 17-11. MSR_LBR_SELECT for Intel microarchitecture code name Nehalem
Bit Field
Bit Offset
Access
Description
CPL_EQ_0
0
R/W
When set, do not capture branches occurring in ring 0
CPL_NEQ_0
1
R/W
When set, do not capture branches occurring in ring >0
JCC
2
R/W
When set, do not capture conditional branches
NEAR_REL_CALL
3
R/W
When set, do not capture near relative calls
NEAR_IND_CALL
4
R/W
When set, do not capture near indirect calls
NEAR_RET
5
R/W
When set, do not capture near returns
NEAR_IND_JMP
6
R/W
When set, do not capture near indirect jumps
NEAR_REL_JMP
7
R/W
When set, do not capture near relative jumps
FAR_BRANCH
8
R/W
When set, do not capture far branches
Reserved
63:9
17-28 Vol. 3B
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.8
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR
PROCESSORS BASED ON INTEL® MICROARCHITECTURE CODE NAME
SANDY BRIDGE
Generally, all of the last branch record, interrupt and exception recording facility described in Section 17.7, “Last
Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name
Nehalem”, apply to processors based on Intel microarchitecture code name Sandy Bridge. For processors based on
Intel microarchitecture code name Ivy Bridge, the same holds true.
One difference of note is that MSR_LBR_SELECT is shared between two logical processors in the same core. In Intel
microarchitecture code name Sandy Bridge, each logical processor has its own MSR_LBR_SELECT. The filtering
semantics for “Near_ind_jmp” and “Near_rel_jmp” has been enhanced, see Table 17-12.
Table 17-12. MSR_LBR_SELECT for Intel® microarchitecture code name Sandy Bridge
Bit Field
Bit Offset
Access
Description
CPL_EQ_0
0
R/W
When set, do not capture branches occurring in ring 0
CPL_NEQ_0
1
R/W
When set, do not capture branches occurring in ring >0
JCC
2
R/W
When set, do not capture conditional branches
NEAR_REL_CALL
3
R/W
When set, do not capture near relative calls
NEAR_IND_CALL
4
R/W
When set, do not capture near indirect calls
NEAR_RET
5
R/W
When set, do not capture near returns
NEAR_IND_JMP
6
R/W
When set, do not capture near indirect jumps except near indirect calls and near returns
NEAR_REL_JMP
7
R/W
When set, do not capture near relative jumps except near relative calls.
FAR_BRANCH
8
R/W
When set, do not capture far branches
Reserved
63:9
17.9
Must be zero
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING
FOR PROCESSORS BASED ON HASWELL MICROARCHITECTURE
Generally, all of the last branch record, interrupt and exception recording facility described in Section 17.8, “Last
Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Sandy
Bridge”, apply to next generation processors based on Intel microarchitecture code name Haswell.
The LBR facility also supports an alternate capability to profile call stack profiles. Configuring the LBR facility to
conduct call stack profiling is by writing 1 to the MSR_LBR_SELECT.EN_CALLSTACK[bit 9]; see Table 17-13. If
MSR_LBR_SELECT.EN_CALLSTACK is clear, the LBR facility will capture branches normally as described in Section
17.8.
Table 17-13. MSR_LBR_SELECT for Intel® microarchitecture code name Haswell
Bit Field
Bit Offset
Access
Description
CPL_EQ_0
0
R/W
When set, do not capture branches occurring in ring 0
CPL_NEQ_0
1
R/W
When set, do not capture branches occurring in ring >0
JCC
2
R/W
When set, do not capture conditional branches
NEAR_REL_CALL
3
R/W
When set, do not capture near relative calls
NEAR_IND_CALL
4
R/W
When set, do not capture near indirect calls
NEAR_RET
5
R/W
When set, do not capture near returns
NEAR_IND_JMP
6
R/W
When set, do not capture near indirect jumps except near indirect calls and near returns
NEAR_REL_JMP
7
R/W
When set, do not capture near relative jumps except near relative calls.
Vol. 3B 17-29
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Table 17-13. MSR_LBR_SELECT for Intel® microarchitecture code name Haswell
Bit Field
FAR_BRANCH
1
Bit Offset
Access
Description
8
R/W
When set, do not capture far branches
EN_CALLSTACK
9
Enable LBR stack to use LIFO filtering to capture Call stack profile
Reserved
63:10
Must be zero
NOTES:
1. Must set valid combination of bits 0-8 in conjunction with bit 9 (as described below), otherwise the contents of the LBR MSRs are
undefined.
The call stack profiling capability is an enhancement of the LBR facility. The LBR stack is a ring buffer typically used
to profile control flow transitions resulting from branches. However, the finite depth of the LBR stack often become
less effective when profiling certain high-level languages (e.g. C++), where a transition of the execution flow is
accompanied by a large number of leaf function calls, each of which returns an individual parameter to form the list
of parameters for the main execution function call. A long list of such parameters returned by the leaf functions
would serve to flush the data captured in the LBR stack, often losing the main execution context.
When the call stack feature is enabled, the LBR stack will capture unfiltered call data normally, but as return
instructions are executed the last captured branch record is flushed from the on-chip registers in a last-in first-out
(LIFO) manner. Thus, branch information relative to leaf functions will not be captured, while preserving the call
stack information of the main line execution path.
The configuration of the call stack facility is summarized below:
•
Set IA32_DEBUGCTL.LBR (bit 0) to enable the LBR stack to capture branch records. The source and target
addresses of the call branches will be captured in the 16 pairs of From/To LBR MSRs that form the LBR stack.
•
Program the Top of Stack (TOS) MSR that points to the last valid from/to pair. This register is incremented by
1, modulo 16, before recording the next pair of addresses.
•
•
Program the branch filtering bits of MSR_LBR_SELECT (bits 0:8) as desired.
Program the MSR_LBR_SELECT to enable LIFO filtering of return instructions with:
— The following bits in MSR_LBR_SELECT must be set to ‘1’: JCC, NEAR_IND_JMP, NEAR_REL_JMP,
FAR_BRANCH, EN_CALLSTACK;
— The following bits in MSR_LBR_SELECT must be cleared: NEAR_REL_CALL, NEAR-IND_CALL, NEAR_RET;
— At most one of CPL_EQ_0, CPL_NEQ_0 is set.
Note that when call stack profiling is enabled, “zero length calls” are excluded from writing into the LBRs. (A “zero
length call” uses the attribute of the call instruction to push the immediate instruction pointer on to the stack and
then pops off that address into a register. This is accomplished without any matching return on the call.)
17.9.1
LBR Stack Enhancement
Processors based on Intel microarchitecture code name Haswell provide 16 pairs of MSR to record last branch
record information. The layout of each MSR pair is enumerated by IA32_PERF_CAPABILITIES[5:0] = 04H, and is
shown in Table 17-14 and Table 17-9.
Table 17-14. MSR_LASTBRANCH_x_FROM_IP with TSX Information
Bit Field
Bit Offset
Access
Description
Data
47:0
R/O
This is the “branch from“ address. See Section 17.4.8.1 for address format.
SIGN_EXT
60:48
R/0
Signed extension of bit 47 of this register.
TSX_ABORT
61
R/0
When set, indicates a TSX Abort entry
LBR_FROM: EIP at the time of the TSX Abort
LBR_TO: EIP of the start of HLE region, or EIP of the RTM Abort Handler
IN_TSX
62
R/0
When set, indicates the entry occurred in a TSX region
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Table 17-14. MSR_LASTBRANCH_x_FROM_IP with TSX Information (Contd.)
Bit Field
Bit Offset
Access
Description
MISPRED
63
R/O
When set, indicates either the target of the branch was mispredicted and/or the
direction (taken/non-taken) was mispredicted; otherwise, the target branch was
predicted.
17.10
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING
FOR PROCESSORS BASED ON SKYLAKE MICROARCHITECTURE
Processors based on the Skylake microarchitecture provide a number of enhancement with storing last branch
records:
•
enumeration of new LBR format: encoding 00101b in IA32_PERF_CAPABILITIES[5:0] is supported, see Section
17.4.8.1.
•
Each LBR stack entry consists of a triplets of MSRs:
— MSR_LASTBRANCH_x_FROM_IP, the layout is simplified, see Table 17-9.
— MSR_LASTBRANCH_x_TO_IP, the layout is the same as Table 17-9.
— MSR_LBR_INFO_x, stores branch prediction flag, TSX info, and elapsed cycle data.
•
Size of LBR stack increased to 32.
Processors based on the Skylake microarchitecture supports the same LBR filtering capabilities as described in
Table 17-13.
Table 17-15. LBR Stack Size and TOS Pointer Range
DisplayFamily_DisplayModel
Size of LBR Stack
Range of TOS Pointer
06_4EH, 06_5EH
32
0 to 31
17.10.1
MSR_LBR_INFO_x MSR
The layout of each MSR_LBR_INFO_x MSR is shown in Table 17-16.
Table 17-16. MSR_LBR_INFO_x
Bit Field
Bit Offset
Access
Description
Cycle Count
(saturating)
15:0
R/O
Elapsed core clocks since last update to the LBR stack
Reserved
60:16
R/O
Reserved
TSX_ABORT
61
R/0
When set, indicates a TSX Abort entry
LBR_FROM: EIP at the time of the TSX Abort
LBR_TO: EIP of the start of HLE region OR
EIP of the RTM Abort Handler
IN_TSX
62
R/0
When set, indicates the entry occurred in a TSX region.
MISPRED
63
R/O
When set, indicates either the target of the branch was mispredicted and/or the
direction (taken/non-taken) was mispredicted; otherwise, the target branch was
predicted.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.10.2
Streamlined Freeze_LBRs_On_PMI Operation
The FREEZE_LBRS_ON_PMI feature causes the LBRs to be frozen on a hardware request for a PMI. This prevents
the LBRs from being overwritten by new branches, allowing the PMI handler to examine the control flow that
preceded the PMI generation. Architectural performance monitoring version 4 and above supports a streamlined
FREEZE_LBRs_ON_PMI operation for PMI service routine that replaces the legacy FREEZE_LBRs_ON_PMI operation
(see Section 17.4.7).
While the legacy FREEZE_LBRS_ON_PMI clear the LBR bit in the IA32_DEBUGCTL MSR on a PMI request, the
streamlined FREEZE_LBRS_ON_PMI will set the LBR_FRZ bit in IA32_PERF_GLOBAL_STATUS. Branches will not
cause the LBRs to be updated when LBR_FRZ is set. Software can clear LBR_FRZ at the same time as it clears overflow bits by setting the LBR_FRZ bit as well as the needed overflow bit when writing to
IA32_PERF_GLOBAL_STATUS_RESET MSR.
This streamlined behavior avoids race conditions between software and processor writes to IA32_DEBUGCTL that
are possible with FREEZE_LBRS_ON_PMI clearing of the LBR enable.
17.10.3
LBR Behavior and Deep C-State
When MWAIT is used to request a C-state that is numerically higher than C1, then LBR state may be initialized to
zero depending on optimized “waiting” state that is selected by the processor The affected LBR states include the
FROM, TO, INFO, LAST_BRANCH, LER and LBR_TOS registers. The LBR enable bit and LBR_FROZEN bit are not
affected. The LBR-time of the first LBR record inserted after an exit from such a C-state request will be zero.
17.11
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PROCESSORS
BASED ON INTEL NETBURST® MICROARCHITECTURE)
Pentium 4 and Intel Xeon processors based on Intel NetBurst microarchitecture provide the following methods for
recording taken branches, interrupts and exceptions:
•
Store branch records in the last branch record (LBR) stack MSRs for the most recent taken branches,
interrupts, and/or exceptions in MSRs. A branch record consist of a branch-from and a branch-to instruction
address.
•
•
Send the branch records out on the system bus as branch trace messages (BTMs).
Log BTMs in a memory-resident branch trace store (BTS) buffer.
To support these functions, the processor provides the following MSRs and related facilities:
•
MSR_DEBUGCTLA MSR — Enables last branch, interrupt, and exception recording; single-stepping on taken
branches; branch trace messages (BTMs); and branch trace store (BTS). This register is named DebugCtlMSR
in the P6 family processors.
•
Debug store (DS) feature flag (CPUID.1:EDX.DS[bit 21]) — Indicates that the processor provides the
debug store (DS) mechanism, which allows BTMs to be stored in a memory-resident BTS buffer.
•
CPL-qualified debug store (DS) feature flag (CPUID.1:ECX.DS-CPL[bit 4]) — Indicates that the
processor provides a CPL-qualified debug store (DS) mechanism, which allows software to selectively skip
sending and storing BTMs, according to specified current privilege level settings, into a memory-resident BTS
buffer.
•
•
IA32_MISC_ENABLE MSR — Indicates that the processor provides the BTS facilities.
•
Last branch record top-of-stack (TOS) pointer — The TOS Pointer MSR contains a 2-bit pointer (0-3) to
the MSR in the LBR stack that contains the most recent branch, interrupt, or exception recorded for the Pentium
Last branch record (LBR) stack — The LBR stack is a circular stack that consists of four MSRs
(MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3) for the Pentium 4 and Intel Xeon processor family
[CPUID family 0FH, models 0H-02H]. The LBR stack consists of 16 MSR pairs
(MSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_15_FROM_IP and
MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_15_TO_IP) for the Pentium 4 and Intel Xeon
processor family [CPUID family 0FH, model 03H].
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4 and Intel Xeon processor family [CPUID family 0FH, models 0H-02H]. This pointer becomes a 4-bit pointer
(0-15) for the Pentium 4 and Intel Xeon processor family [CPUID family 0FH, model 03H]. See also: Table
17-17, Figure 17-12, and Section 17.11.2, “LBR Stack for Processors Based on Intel NetBurst® Microarchitecture.”
•
Last exception record — See Section 17.11.3, “Last Exception Records.”
17.11.1
MSR_DEBUGCTLA MSR
The MSR_DEBUGCTLA MSR enables and disables the various last branch recording mechanisms described in the
previous section. This register can be written to using the WRMSR instruction, when operating at privilege level 0
or when in real-address mode. A protected-mode operating system procedure is required to provide user access to
this register. Figure 17-12 shows the flags in the MSR_DEBUGCTLA MSR. The functions of these flags are as
follows:
•
LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records a running trace of
the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug exception
being generated) in the last branch record (LBR) stack. Each branch, interrupt, or exception is recorded as a
64-bit branch record. The processor clears this flag whenever a debug exception is generated (for example,
when an instruction or data breakpoint or a single-step trap occurs). See Section 17.11.2, “LBR Stack for
Processors Based on Intel NetBurst® Microarchitecture.”
•
BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS
register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism
allows single-stepping the processor on taken branches. See Section 17.4.3, “Single-Stepping on Branches.”
•
TR (trace message enable) flag (bit 2) — When set, branch trace messages are enabled. Thereafter, when
the processor detects a taken branch, interrupt, or exception, it sends the branch record out on the system bus
as a branch trace message (BTM). See Section 17.4.4, “Branch Trace Messages.”
31
7 6 5 4 3 2 1 0
Reserved
BTS_OFF_USR — Disable storing non-CPL_0 BTS
BTS_OFF_OS — Disable storing CPL_0 BTS
BTINT — Branch trace interrupt
BTS — Branch trace store
TR — Trace messages enable
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
Figure 17-12. MSR_DEBUGCTLA MSR for Pentium 4 and Intel Xeon Processors
•
BTS (branch trace store) flag (bit 3) — When set, enables the BTS facilities to log BTMs to a memoryresident BTS buffer that is part of the DS save area. See Section 17.4.9, “BTS and DS Save Area.”
•
BTINT (branch trace interrupt) flag (bits 4) — When set, the BTS facilities generate an interrupt when the
BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 17.4.5, “Branch
Trace Store (BTS).”
•
BTS_OFF_OS (disable ring 0 branch trace store) flag (bit 5) — When set, enables the BTS facilities to
skip sending/logging CPL_0 BTMs to the memory-resident BTS buffer. See Section 17.11.2, “LBR Stack for
Processors Based on Intel NetBurst® Microarchitecture.”
•
BTS_OFF_USR (disable ring 0 branch trace store) flag (bit 6) — When set, enables the BTS facilities to
skip sending/logging non-CPL_0 BTMs to the memory-resident BTS buffer. See Section 17.11.2, “LBR Stack for
Processors Based on Intel NetBurst® Microarchitecture.”
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NOTE
The initial implementation of BTS_OFF_USR and BTS_OFF_OS in MSR_DEBUGCTLA is shown in
Figure 17-12. The BTS_OFF_USR and BTS_OFF_OS fields may be implemented on other modelspecific debug control register at different locations.
See Chapter 35, “Model-Specific Registers (MSRs),” for a detailed description of each of the last branch recording
MSRs.
17.11.2
LBR Stack for Processors Based on Intel NetBurst® Microarchitecture
The LBR stack is made up of LBR MSRs that are treated by the processor as a circular stack. The TOS pointer
(MSR_LASTBRANCH_TOS MSR) points to the LBR MSR (or LBR MSR pair) that contains the most recent (last)
branch record placed on the stack. Prior to placing a new branch record on the stack, the TOS is incremented by 1.
When the TOS pointer reaches it maximum value, it wraps around to 0. See Table 17-17 and Figure 17-12.
Table 17-17. LBR MSR Stack Size and TOS Pointer Range for the Pentium® 4 and the Intel® Xeon® Processor Family
DisplayFamily_DisplayModel
Size of LBR Stack
Range of TOS Pointer
Family 0FH, Models 0H-02H; MSRs at locations 1DBH-1DEH.
4
0 to 3
Family 0FH, Models; MSRs at locations 680H-68FH.
16
0 to 15
Family 0FH, Model 03H; MSRs at locations 6C0H-6CFH.
16
0 to 15
The registers in the LBR MSR stack and the MSR_LASTBRANCH_TOS MSR are read-only and can be read using the
RDMSR instruction.
Figure 17-13 shows the layout of a branch record in an LBR MSR (or MSR pair). Each branch record consists of two
linear addresses, which represent the “from” and “to” instruction pointers for a branch, interrupt, or exception. The
contents of the from and to addresses differ, depending on the source of the branch:
•
Taken branch — If the record is for a taken branch, the “from” address is the address of the branch instruction
and the “to” address is the target instruction of the branch.
•
Interrupt — If the record is for an interrupt, the “from” address the return instruction pointer (RIP) saved for
the interrupt and the “to” address is the address of the first instruction in the interrupt handler routine. The RIP
is the linear address of the next instruction to be executed upon returning from the interrupt handler.
•
Exception — If the record is for an exception, the “from” address is the linear address of the instruction that
caused the exception to be generated and the “to” address is the address of the first instruction in the exception
handler routine.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
CPUID Family 0FH, Models 0H-02H
MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3
63
0
32 - 31
From Linear Address
To Linear Address
CPUID Family 0FH, Model 03H-04H
MSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_15_FROM_IP
0
32 - 31
63
Reserved
From Linear Address
MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_15_TO_IP
63
0
32 - 31
Reserved
To Linear Address
Figure 17-13. LBR MSR Branch Record Layout for the Pentium 4
and Intel Xeon Processor Family
Additional information is saved if an exception or interrupt occurs in conjunction with a branch instruction. If a
branch instruction generates a trap type exception, two branch records are stored in the LBR stack: a branch
record for the branch instruction followed by a branch record for the exception.
If a branch instruction is immediately followed by an interrupt, a branch record is stored in the LBR stack for the
branch instruction followed by a record for the interrupt.
17.11.3
Last Exception Records
The Pentium 4, Intel Xeon, Pentium M, Intel® Core™ Solo, Intel® Core™ Duo, Intel® Core™2 Duo, Intel® Core™ i7
and Intel® Atom™ processors provide two MSRs (the MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that
duplicate the functions of the LastExceptionToIP and LastExceptionFromIP MSRs found in the P6 family processors.
The MSR_LER_TO_LIP and MSR_LER_FROM_LIP MSRs contain a branch record for the last branch that the
processor took prior to an exception or interrupt being generated.
17.12
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™
SOLO AND INTEL® CORE™ DUO PROCESSORS)
Intel Core Solo and Intel Core Duo processors provide last branch interrupt and exception recording. This capability
is almost identical to that found in Pentium 4 and Intel Xeon processors. There are differences in the stack and in
some MSR names and locations.
Note the following:
•
IA32_DEBUGCTL MSR — Enables debug trace interrupt, debug trace store, trace messages enable,
performance monitoring breakpoint flags, single stepping on branches, and last branch. IA32_DEBUGCTL MSR
is located at register address 01D9H.
See Figure 17-14 for the layout and the entries below for a description of the flags:
— LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records a running trace
of the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug
exception being generated) in the last branch record (LBR) stack. For more information, see the “Last
Branch Record (LBR) Stack” below.
— BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS
register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
allows single-stepping the processor on taken branches. See Section 17.4.3, “Single-Stepping on
Branches,” for more information about the BTF flag.
— TR (trace message enable) flag (bit 6) — When set, branch trace messages are enabled. When the
processor detects a taken branch, interrupt, or exception; it sends the branch record out on the system bus
as a branch trace message (BTM). See Section 17.4.4, “Branch Trace Messages,” for more information
about the TR flag.
— BTS (branch trace store) flag (bit 7) — When set, the flag enables BTS facilities to log BTMs to a
memory-resident BTS buffer that is part of the DS save area. See Section 17.4.9, “BTS and DS Save Area.”
— BTINT (branch trace interrupt) flag (bits 8) — When set, the BTS facilities generate an interrupt when
the BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 17.4.5,
“Branch Trace Store (BTS),” for a description of this mechanism.
31
8 7 6 5 4 3 2 1 0
Reserved
BTINT — Branch trace interrupt
BTS — Branch trace store
TR — Trace messages enable
Reserved
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
Figure 17-14. IA32_DEBUGCTL MSR for Intel Core Solo
and Intel Core Duo Processors
•
Debug store (DS) feature flag (bit 21), returned by the CPUID instruction — Indicates that the
processor provides the debug store (DS) mechanism, which allows BTMs to be stored in a memory-resident
BTS buffer. See Section 17.4.5, “Branch Trace Store (BTS).”
•
Last Branch Record (LBR) Stack — The LBR stack consists of 8 MSRs (MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’ address, bits 63-32 hold the ‘to’ address (MSR addresses start
at 40H). See Figure 17-15.
•
Last Branch Record Top-of-Stack (TOS) Pointer — The TOS Pointer MSR contains a 3-bit pointer (bits 2-0)
to the MSR in the LBR stack that contains the most recent branch, interrupt, or exception recorded. For Intel
Core Solo and Intel Core Duo processors, this MSR is located at register address 01C9H.
For compatibility, the Intel Core Solo and Intel Core Duo processors provide two 32-bit MSRs (the
MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that duplicate functions of the LastExceptionToIP and LastExceptionFromIP MSRs found in P6 family processors.
For details, see Section 17.10, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based
on Skylake Microarchitecture,” and Section 35.19, “MSRs In Intel® Core™ Solo and Intel® Core™ Duo Processors”
MSR_LASTBRANCH_0 through MSR_LASTBRANCH_7
63
0
32 - 31
To Linear Address
From Linear Address
Figure 17-15. LBR Branch Record Layout for the Intel Core Solo
and Intel Core Duo Processor
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17.13
LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (PENTIUM M PROCESSORS)
Like the Pentium 4 and Intel Xeon processor family, Pentium M processors provide last branch interrupt and exception recording. The capability operates almost identically to that found in Pentium 4 and Intel Xeon processors.
There are differences in the shape of the stack and in some MSR names and locations. Note the following:
•
MSR_DEBUGCTLB MSR — Enables debug trace interrupt, debug trace store, trace messages enable,
performance monitoring breakpoint flags, single stepping on branches, and last branch. For Pentium M
processors, this MSR is located at register address 01D9H. See Figure 17-16 and the entries below for a
description of the flags.
— LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records a running trace
of the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug
exception being generated) in the last branch record (LBR) stack. For more information, see the “Last
Branch Record (LBR) Stack” bullet below.
— BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS
register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism
allows single-stepping the processor on taken branches. See Section 17.4.3, “Single-Stepping on
Branches,” for more information about the BTF flag.
— PBi (performance monitoring/breakpoint pins) flags (bits 5-2) — When these flags are set, the
performance monitoring/breakpoint pins on the processor (BP0#, BP1#, BP2#, and BP3#) report
breakpoint matches in the corresponding breakpoint-address registers (DR0 through DR3). The processor
asserts then deasserts the corresponding BPi# pin when a breakpoint match occurs. When a PBi flag is
clear, the performance monitoring/breakpoint pins report performance events. Processor execution is not
affected by reporting performance events.
— TR (trace message enable) flag (bit 6) — When set, branch trace messages are enabled. When the
processor detects a taken branch, interrupt, or exception, it sends the branch record out on the system bus
as a branch trace message (BTM). See Section 17.4.4, “Branch Trace Messages,” for more information
about the TR flag.
— BTS (branch trace store) flag (bit 7) — When set, enables the BTS facilities to log BTMs to a memoryresident BTS buffer that is part of the DS save area. See Section 17.4.9, “BTS and DS Save Area.”
— BTINT (branch trace interrupt) flag (bits 8) — When set, the BTS facilities generate an interrupt when
the BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 17.4.5,
“Branch Trace Store (BTS),” for a description of this mechanism.
31
8 7 6 5 4 3 2 1 0
Reserved
BTINT — Branch trace interrupt
BTS — Branch trace store
TR — Trace messages enable
PB3/2/1/0 — Performance monitoring breakpoint flags
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
Figure 17-16. MSR_DEBUGCTLB MSR for Pentium M Processors
•
Debug store (DS) feature flag (bit 21), returned by the CPUID instruction — Indicates that the
processor provides the debug store (DS) mechanism, which allows BTMs to be stored in a memory-resident
BTS buffer. See Section 17.4.5, “Branch Trace Store (BTS).”
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
Last Branch Record (LBR) Stack — The LBR stack consists of 8 MSRs (MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’ address, bits 63-32 hold the ‘to’ address. For Pentium M
Processors, these pairs are located at register addresses 040H-047H. See Figure 17-17.
•
Last Branch Record Top-of-Stack (TOS) Pointer — The TOS Pointer MSR contains a 3-bit pointer (bits 2-0)
to the MSR in the LBR stack that contains the most recent branch, interrupt, or exception recorded. For Pentium
M Processors, this MSR is located at register address 01C9H.
MSR_LASTBRANCH_0
through MSR_LASTBRANCH_7
0
32 - 31
63
To Linear Address
From Linear Address
Figure 17-17. LBR Branch Record Layout for the Pentium M Processor
For more detail on these capabilities, see Section 17.11.3, “Last Exception Records,” and Section 35.20, “MSRs In
the Pentium M Processor.”
17.14
LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (P6 FAMILY PROCESSORS)
The P6 family processors provide five MSRs for recording the last branch, interrupt, or exception taken by the
processor: DEBUGCTLMSR, LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP.
These registers can be used to collect last branch records, to set breakpoints on branches, interrupts, and exceptions, and to single-step from one branch to the next.
See Chapter 35, “Model-Specific Registers (MSRs),” for a detailed description of each of the last branch recording
MSRs.
17.14.1
DEBUGCTLMSR Register
The version of the DEBUGCTLMSR register found in the P6 family processors enables last branch, interrupt, and
exception recording; taken branch breakpoints; the breakpoint reporting pins; and trace messages. This register
can be written to using the WRMSR instruction, when operating at privilege level 0 or when in real-address mode.
A protected-mode operating system procedure is required to provide user access to this register. Figure 17-18
shows the flags in the DEBUGCTLMSR register for the P6 family processors. The functions of these flags are as
follows:
•
LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records the source and
target addresses (in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP
MSRs) for the last branch and the last exception or interrupt taken by the processor prior to a debug exception
being generated. The processor clears this flag whenever a debug exception, such as an instruction or data
breakpoint or single-step trap occurs.
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31
7 6 5 4 3 2 1 0
Reserved
P P P P B L
T B B B B T B
R 3 2 1 0 F R
TR — Trace messages enable
PBi — Performance monitoring/breakpoint pins
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
Figure 17-18. DEBUGCTLMSR Register (P6 Family Processors)
•
BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS
register as a “single-step on branches” flag. See Section 17.4.3, “Single-Stepping on Branches.”
•
PBi (performance monitoring/breakpoint pins) flags (bits 2 through 5) — When these flags are set,
the performance monitoring/breakpoint pins on the processor (BP0#, BP1#, BP2#, and BP3#) report
breakpoint matches in the corresponding breakpoint-address registers (DR0 through DR3). The processor
asserts then deasserts the corresponding BPi# pin when a breakpoint match occurs. When a PBi flag is clear,
the performance monitoring/breakpoint pins report performance events. Processor execution is not affected by
reporting performance events.
•
TR (trace message enable) flag (bit 6) — When set, trace messages are enabled as described in Section
17.4.4, “Branch Trace Messages.” Setting this flag greatly reduces the performance of the processor. When
trace messages are enabled, the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP,
and LastExceptionFromIP MSRs are undefined.
17.14.2
Last Branch and Last Exception MSRs
The LastBranchToIP and LastBranchFromIP MSRs are 32-bit registers for recording the instruction pointers for the
last branch, interrupt, or exception that the processor took prior to a debug exception being generated. When a
branch occurs, the processor loads the address of the branch instruction into the LastBranchFromIP MSR and loads
the target address for the branch into the LastBranchToIP MSR.
When an interrupt or exception occurs (other than a debug exception), the address of the instruction that was
interrupted by the exception or interrupt is loaded into the LastBranchFromIP MSR and the address of the exception or interrupt handler that is called is loaded into the LastBranchToIP MSR.
The LastExceptionToIP and LastExceptionFromIP MSRs (also 32-bit registers) record the instruction pointers for
the last branch that the processor took prior to an exception or interrupt being generated. When an exception or
interrupt occurs, the contents of the LastBranchToIP and LastBranchFromIP MSRs are copied into these registers
before the to and from addresses of the exception or interrupt are recorded in the LastBranchToIP and LastBranchFromIP MSRs.
These registers can be read using the RDMSR instruction.
Note that the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP
MSRs are offsets into the current code segment, as opposed to linear addresses, which are saved in last branch
records for the Pentium 4 and Intel Xeon processors.
17.14.3
Monitoring Branches, Exceptions, and Interrupts
When the LBR flag in the DEBUGCTLMSR register is set, the processor automatically begins recording branches
that it takes, exceptions that are generated (except for debug exceptions), and interrupts that are serviced. Each
time a branch, exception, or interrupt occurs, the processor records the to and from instruction pointers in the
LastBranchToIP and LastBranchFromIP MSRs. In addition, for interrupts and exceptions, the processor copies the
contents of the LastBranchToIP and LastBranchFromIP MSRs into the LastExceptionToIP and LastExceptionFromIP
MSRs prior to recording the to and from addresses of the interrupt or exception.
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When the processor generates a debug exception (#DB), it automatically clears the LBR flag before executing the
exception handler, but does not touch the last branch and last exception MSRs. The addresses for the last branch,
interrupt, or exception taken are thus retained in the LastBranchToIP and LastBranchFromIP MSRs and the
addresses of the last branch prior to an interrupt or exception are retained in the LastExceptionToIP, and LastExceptionFromIP MSRs.
The debugger can use the last branch, interrupt, and/or exception addresses in combination with code-segment
selectors retrieved from the stack to reset breakpoints in the breakpoint-address registers (DR0 through DR3),
allowing a backward trace from the manifestation of a particular bug toward its source. Because the instruction
pointers recorded in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP MSRs are
offsets into a code segment, software must determine the segment base address of the code segment associated
with the control transfer to calculate the linear address to be placed in the breakpoint-address registers. The
segment base address can be determined by reading the segment selector for the code segment from the stack
and using it to locate the segment descriptor for the segment in the GDT or LDT. The segment base address can
then be read from the segment descriptor.
Before resuming program execution from a debug-exception handler, the handler must set the LBR flag again to reenable last branch and last exception/interrupt recording.
17.15
TIME-STAMP COUNTER
The Intel 64 and IA-32 architectures (beginning with the Pentium processor) define a time-stamp counter mechanism that can be used to monitor and identify the relative time occurrence of processor events. The counter’s architecture includes the following components:
•
TSC flag — A feature bit that indicates the availability of the time-stamp counter. The counter is available in an
if the function CPUID.1:EDX.TSC[bit 4] = 1.
•
IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and Pentium processors) — The MSR used
as the counter.
•
•
RDTSC instruction — An instruction used to read the time-stamp counter.
TSD flag — A control register flag is used to enable or disable the time-stamp counter (enabled if
CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, Intel Xeon, Intel Core
Solo and Intel Core Duo processors and later processors) is a 64-bit counter that is set to 0 following a RESET of
the processor. Following a RESET, the counter increments even when the processor is halted by the HLT instruction
or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp
counter to stop.
Processor families increment the time-stamp counter differently:
•
For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors, Intel Xeon processors
(family [0FH], models [00H, 01H, or 02H]); and for P6 family processors: the time-stamp counter increments
with every internal processor clock cycle.
The internal processor clock cycle is determined by the current core-clock to bus-clock ratio. Intel®
SpeedStep® technology transitions may also impact the processor clock.
•
For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]); for Intel Core Solo
and Intel Core Duo processors (family [06H], model [0EH]); for the Intel Xeon processor 5100 series and Intel
Core 2 Duo processors (family [06H], model [0FH]); for Intel Core 2 and Intel Xeon processors (family [06H],
DisplayModel [17H]); for Intel Atom processors (family [06H],
DisplayModel [1CH]): the time-stamp counter increments at a constant rate. That rate may be set by the
maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at
which the processor is booted. The maximum resolved frequency may differ from the processor base
frequency, see Section 18.18.2 for more detail. On certain processors, the TSC frequency may not be the same
as the frequency in the brand string.
The specific processor configuration determines the behavior. Constant TSC behavior ensures that the duration
of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if the processor core
changes frequency. This is the architectural behavior moving forward.
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NOTE
To determine average processor clock frequency, Intel recommends the use of performance
monitoring logic to count processor core clocks over the period of time for which the average is
required. See Section 18.17, “Counting Clocks on systems with Intel Hyper-Threading Technology
in Processors Based on Intel NetBurst® Microarchitecture,” and Chapter 19, “PerformanceMonitoring Events,” for more information.
The RDTSC instruction reads the time-stamp counter and is guaranteed to return a monotonically increasing
unique value whenever executed, except for a 64-bit counter wraparound. Intel guarantees that the time-stamp
counter will not wraparound within 10 years after being reset. The period for counter wrap is longer for Pentium 4,
Intel Xeon, P6 family, and Pentium processors.
Normally, the RDTSC instruction can be executed by programs and procedures running at any privilege level and in
virtual-8086 mode. The TSD flag allows use of this instruction to be restricted to programs and procedures running
at privilege level 0. A secure operating system would set the TSD flag during system initialization to disable user
access to the time-stamp counter. An operating system that disables user access to the time-stamp counter should
emulate the instruction through a user-accessible programming interface.
The RDTSC instruction is not serializing or ordered with other instructions. It does not necessarily wait until all
previous instructions have been executed before reading the counter. Similarly, subsequent instructions may begin
execution before the RDTSC instruction operation is performed.
The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the time-stamp counter as
an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family processors, all 64-bits of the timestamp counter are read using RDMSR (just as with RDTSC). When WRMSR is used to write the time-stamp counter
on processors before family [0FH], models [03H, 04H]: only the low-order 32-bits of the time-stamp counter can
be written (the high-order 32 bits are cleared to 0). For family [0FH], models [03H, 04H, 06H]; for family [06H]],
model [0EH, 0FH]; for family [06H]], DisplayModel [17H, 1AH, 1CH, 1DH]: all 64 bits are writable.
17.15.1
Invariant TSC
The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC.
Processor’s support for invariant TSC is indicated by CPUID.80000007H:EDX[8].
The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior
moving forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services
(instead of ACPI or HPET timers). TSC reads are much more efficient and do not incur the overhead associated with
a ring transition or access to a platform resource.
17.15.2
IA32_TSC_AUX Register and RDTSCP Support
Processors based on Intel microarchitecture code name Nehalem provide an auxiliary TSC register, IA32_TSC_AUX
that is designed to be used in conjunction with IA32_TSC. IA32_TSC_AUX provides a 32-bit field that is initialized
by privileged software with a signature value (for example, a logical processor ID).
The primary usage of IA32_TSC_AUX in conjunction with IA32_TSC is to allow software to read the 64-bit time
stamp in IA32_TSC and signature value in IA32_TSC_AUX with the instruction RDTSCP in an atomic operation.
RDTSCP returns the 64-bit time stamp in EDX:EAX and the 32-bit TSC_AUX signature value in ECX. The atomicity
of RDTSCP ensures that no context switch can occur between the reads of the TSC and TSC_AUX values.
Support for RDTSCP is indicated by CPUID.80000001H:EDX[27]. As with RDTSC instruction, non-ring 0 access is
controlled by CR4.TSD (Time Stamp Disable flag).
User mode software can use RDTSCP to detect if CPU migration has occurred between successive reads of the TSC.
It can also be used to adjust for per-CPU differences in TSC values in a NUMA system.
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17.15.3
Time-Stamp Counter Adjustment
Software can modify the value of the time-stamp counter (TSC) of a logical processor by using the WRMSR instruction to write to the IA32_TIME_STAMP_COUNTER MSR (address 10H). Because such a write applies only to that
logical processor, software seeking to synchronize the TSC values of multiple logical processors must perform these
writes on each logical processor. It may be difficult for software to do this in a way than ensures that all logical
processors will have the same value for the TSC at a given point in time.
The synchronization of TSC adjustment can be simplified by using the 64-bit IA32_TSC_ADJUST MSR (address
3BH). Like the IA32_TIME_STAMP_COUNTER MSR, the IA32_TSC_ADJUST MSR is maintained separately for each
logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows:
•
•
On RESET, the value of the IA32_TSC_ADJUST MSR is 0.
•
If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or subtracts) value X from that MSR, the logical
processor also adds (or subtracts) value X from the TSC.
If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC,
the logical processor also adds (or subtracts) value X from the IA32_TSC_ADJUST MSR.
Unlike the TSC, the value of the IA32_TSC_ADJUST MSR changes only in response to WRMSR (either to the MSR
itself, or to the IA32_TIME_STAMP_COUNTER MSR). Its value does not otherwise change as time elapses. Software
seeking to adjust the TSC can do so by using WRMSR to write the same value to the IA32_TSC_ADJUST MSR on
each logical processor.
Processor support for the IA32_TSC_ADJUST MSR is indicated by CPUID.(EAX=07H, ECX=0H):EBX.TSC_ADJUST
(bit 1).
17.15.4
Invariant Time-Keeping
The invariant TSC is based on the invariant timekeeping hardware (called Always Running Timer or ART), that runs
at the core crystal clock frequency. The ratio defined by CPUID leaf 15H expresses the frequency relationship
between the ART hardware and TSC.
If CPUID.15H:EBX[31:0] != 0 and CPUID.80000007H:EDX[InvariantTSC] = 1, the following linearity relationship
holds between TSC and the ART hardware:
TSC_Value = (ART_Value * CPUID.15H:EBX[31:0] )/ CPUID.15H:EAX[31:0] + K
Where 'K' is an offset that can be adjusted by a privileged agent2.
When ART hardware is reset, both invariant TSC and K are also reset.
17.16
INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) MONITORING
FEATURES
The Intel Resource Director Technology (Intel RDT) feature set provides a set of monitoring capabilities including
Cache Monitoring Technology (CMT) and Memory Bandwidth Monitoring (MBM). The Intel® Xeon® processor E5 v3
family introduced resource monitoring capability in each logical processor to measure specific platform shared
resource metrics, for example, L3 cache occupancy. The programming interface for these monitoring features is
described in this section. Two features within the monitoring feature set provided are described - Cache Monitoring
Technology (CMT) and Memory Bandwidth Monitoring.
Cache Monitoring Technology (CMT) allows an Operating System, Hypervisor or similar system management agent
to determine the usage of cache by applications running on the platform. The initial implementation is directed at
L3 cache monitoring (currently the last level cache in most server platforms).
Memory Bandwidth Monitoring (MBM), introduced in the Intel® Xeon® processor E5 v4 family, builds on the CMT
infrastructure to allow monitoring of bandwidth from one level of the cache hierarchy to the next - in this case
2. IA32_TSC_ADJUST MSR and the TSC-offset field in the VM execution controls of VMCS are some of the common interfaces that privileged software can use to manage the time stamp counter for keeping time
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focusing on the L3 cache, which is typically backed directly by system memory. As a result of this implementation,
memory bandwidth can be monitored.
The monitoring mechanisms described provide the following key shared infrastructure features:
•
A mechanism to enumerate the presence of the monitoring capabilities within the platform (via a CPUID feature
bit).
•
A framework to enumerate the details of each sub-feature (including CMT and MBM, as discussed later, via
CPUID leaves and sub-leaves).
•
A mechanism for the OS or Hypervisor to indicate a software-defined ID for each of the software threads (applications, virtual machines, etc.) that are scheduled to run on a logical processor. These identifiers are known as
Resource Monitoring IDs (RMIDs).
•
Mechanisms in hardware to monitor cache occupancy and bandwidth statistics as applicable to a given product
generation on a per software-id basis.
•
Mechanisms for the OS or Hypervisor to read back the collected metrics such as L3 occupancy or Memory
Bandwidth for a given software ID at any point during runtime.
17.16.1
Overview of Cache Monitoring Technology and Memory Bandwidth Monitoring
The shared resource monitoring features described in this chapter provide a layer of abstraction between applications and logical processors through the use of Resource Monitoring IDs (RMIDs). Each logical processor in the
system can be assigned an RMID independently, or multiple logical processors can be assigned to the same RMID
value (e.g., to track an application with multiple threads). For each logical processor, only one RMID value is active
at a time. This is enforced by the IA32_PQR_ASSOC MSR, which specifies the active RMID of a logical processor.
Writing to this MSR by software changes the active RMID of the logical processor from an old value to a new value.
The underlying platform shared resource monitoring hardware tracks cache metrics such as cache utilization and
misses as a result of memory accesses according to the RMIDs and reports monitored data via a counter register
(IA32_QM_CTR). The specific event types supported vary by generation and can be enumerated via CPUID. Before
reading back monitored data software must configure an event selection MSR (IA32_QM_EVTSEL) to specify which
metric is to be reported, and the specific RMID for which the data should be returned.
Processor support of the monitoring framework and sub-features such as CMT is reported via the CPUID instruction. The resource type available to the monitoring framework is enumerated via a new leaf function in CPUID.
Reading and writing to the monitoring MSRs requires the RDMSR and WRMSR instructions.
The Cache Monitoring Technology feature set provides the following unique mechanisms:
•
A mechanism to enumerate the presence and details of the CMT feature as applicable to a given level of the
cache hierarchy, independent of other monitoring features.
•
CMT-specific event codes to read occupancy for a given level of the cache hierarchy.
The Memory Bandwidth Monitoring feature provides the following unique mechanisms:
•
A mechanism to enumerate the presence and details of the MBM feature as applicable to a given level of the
cache hierarchy, independent of other monitoring features.
•
MBM-specific event codes to read bandwidth out to the next level of the hierarchy and various sub-event codes
to read more specific metrics as discussed later (e.g., total bandwidth vs. bandwidth only from local memory
controllers on the same package).
17.16.2
Enabling Monitoring: Usage Flow
Figure 17-19 illustrates the key steps for OS/VMM to detect support of shared resource monitoring features such
as CMT and enable resource monitoring for available resource types and monitoring events.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
On OS/VMM Initialization
PQM Capability
Enumeration
CPUID[
CPUID.(7,0):EBX.12
CPUID.(0FH,0):EDX[31:1]
CPUID.(0FH,1):ECX[31:0]
CPUID.(0FH,1):EDX[31:0]
CPUID.(0FH,1):EBX[31:0]
CPUID.(0FH,0):EBX[31:0]
On Context Switch
Set RMID to monitor
the scheduled app
Periodical Resource
Selection/Reporting
Configure event type
Read monitored data
WRMSR
IA32_PQR_ASSOC.RMID
RDMSR/WRMSR
IA32_QM_EVTSEL
IA32_QM_CTR
Figure 17-19. Platform Shared Resource Monitoring Usage Flow
17.16.3
Enumeration and Detecting Support of Cache Monitoring Technology and Memory
Bandwidth Monitoring
Software can query processor support of shared resource monitoring features capabilities by executing CPUID
instruction with EAX = 07H, ECX = 0H as input. If CPUID.(EAX=07H, ECX=0):EBX.PQM[bit 12] reports 1, the
processor provides the following programming interfaces for shared resource monitoring, including Cache Monitoring Technology:
•
CPUID leaf function 0FH (Shared Resource Monitoring Enumeration leaf) provides information on available
resource types (see Section 17.16.4), and monitoring capabilities for each resource type (see Section 17.16.5).
Note CMT and MBM capabilities are enumerated as separate event vectors using shared enumeration infrastructure under a given resource type.
•
IA32_PQR_ASSOC.RMID: The per-logical-processor MSR, IA32_PQR_ASSOC, that OS/VMM can use to assign
an RMID to each logical processor, see Section 17.16.6.
•
IA32_QM_EVTSEL: This MSR specifies an Event ID (EvtID) and an RMID which the platform uses to look up and
provide monitoring data in the monitoring counter, IA32_QM_CTR, see Section 17.16.7.
•
IA32_QM_CTR: This MSR reports monitored resource data when available along with bits to allow software to
check for error conditions and verify data validity.
Software must follow the following sequence of enumeration to discover Cache Monitoring Technology capabilities:
1. Execute CPUID with EAX=0 to discover the “cpuid_maxLeaf” supported in the processor;
2. If cpuid_maxLeaf >= 7, then execute CPUID with EAX=7, ECX= 0 to verify CPUID.(EAX=07H,
ECX=0):EBX.PQM[bit 12] is set;
3. If CPUID.(EAX=07H, ECX=0):EBX.PQM[bit 12] = 1, then execute CPUID with EAX=0FH, ECX= 0 to query
available resource types that support monitoring;
4. If CPUID.(EAX=0FH, ECX=0):EDX.L3[bit 1] = 1, then execute CPUID with EAX=0FH, ECX= 1 to query the
specific capabilities of L3 Cache Monitoring Technology (CMT) and Memory Bandwidth Monitoring.
5. If CPUID.(EAX=0FH, ECX=0):EDX reports additional resource types supporting monitoring, then execute
CPUID with EAX=0FH, ECX set to a corresponding resource type ID (ResID) as enumerated by the bit position
of CPUID.(EAX=0FH, ECX=0):EDX.
17.16.4
Monitoring Resource Type and Capability Enumeration
CPUID leaf function 0FH (Shared Resource Monitoring Enumeration leaf) provides one sub-leaf (sub-function 0)
that reports shared enumeration infrastructure, and one or more sub-functions that report feature-specific
enumeration data:
•
Monitoring leaf sub-function 0 enumerates available resources that support monitoring, i.e. executing CPUID
with EAX=0FH and ECX=0H. In the initial implementation, L3 cache is the only resource type available. Each
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supported resource type is represented by a bit in CPUID.(EAX=0FH, ECX=0):EDX[31:1]. The bit position
corresponds to the sub-leaf index (ResID) that software must use to query details of the monitoring capability
of that resource type (see Figure 17-21 and Figure 17-22). Reserved bits of CPUID.(EAX=0FH,
ECX=0):EDX[31:2] correspond to unsupported sub-leaves of the CPUID.0FH leaf. Additionally,
CPUID.(EAX=0FH, ECX=0H):EBX reports the highest RMID value of any resource type that supports
monitoring in the processor.
CPUID.(EAX=0FH, ECX=0H) Output: (EAX: Reserved; ECX: Reserved)
31
EDX
Reserved
2 1
L
3
31
EBX
0
0
Highest RMID Value of Any Resource Type (Zero-Based)
Figure 17-20. CPUID.(EAX=0FH, ECX=0H) Monitoring Resource Type Enumeration
17.16.5
Feature-Specific Enumeration
Each additional sub-leaf of CPUID.(EAX=0FH, ECX=ResID) enumerates the specific details for software to program
Monitoring MSRs using the resource type associated with the given ResID.
Note that in future Monitoring implementations the meanings of the returned registers may vary in other subleaves that are not yet defined. The registers will be specified and defined on a per-ResID basis.
CPUID.(EAX=0FH, ECX=1H) Output: (EAX: Reserved)
31
EBX
0
31
ECX
Upscaling Factor
Upscaling Factor to Total Occupancy (Bytes)
0
Highest RMID Value of This Resource Type (Zero-Based)
MaxRMID
Figure 17-21. L3 Cache Monitoring Capability Enumeration Data (CPUID.(EAX=0FH, ECX=1H) )
For each supported Cache Monitoring resource type, hardware supports only a finite number of RMIDs.
CPUID.(EAX=0FH, ECX=1H).ECX enumerates the highest RMID value that can be monitored with this resource
type, see Figure 17-21.
CPUID.(EAX=0FH, ECX=1H).EDX specifies a bit vector that is used to look up the EventID (See Figure 17-22 and
Table 17-18) that software must program with IA32_QM_EVTSEL in order to retrieve event data. After software
configures IA32_QMEVTSEL with the desired RMID and EventID, it can read the resulting data from IA32_QM_CTR.
The raw numerical value reported from IA32_QM_CTR can be converted to the final value (occupancy in bytes or
bandwidth in bytes per sampled time period) by multiplying the counter value by the value from CPUID.(EAX=0FH,
ECX=1H).EBX, see Figure 17-21.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
EventTypeBitMask
31
EDX
3 2 1
0
Reserved
L3 Occupancy
L3 Total BW
L3 Local BW
Figure 17-22. L3 Cache Monitoring Capability Enumeration Event Type Bit Vector (CPUID.(EAX=0FH, ECX=1H) )
17.16.5.1 Cache Monitoring Technology
On processors for which Cache Monitoring Technology supports the L3 cache occupancy event, CPUID.(EAX=0FH,
ECX=1H).EDX would return with only bit 0 set. The corresponding event ID can be looked up from Table 17-18. The
L3 occupancy data accumulated in IA32_QM_CTR can be converted to total occupancy (in bytes) by multiplying
with CPUID.(EAX=0FH, ECX=1H).EBX.
Event codes for Cache Monitoring Technology are discussed in the next section.
17.16.5.2 Memory Bandwidth Monitoring
On processors that monitoring supports Memory Bandwidth Monitoring using ResID=1 (L3), two additional bits will
be set in the vector at CPUID.(EAX=0FH, ECX=1H).EDX:
•
CPUID.(EAX=0FH, ECX=1H).EDX[bit 1]: indicates the L3 total external bandwidth monitoring event is
supported if set. This event monitors the L3 total external bandwidth to the next level of the cache hierarchy,
including all demand and prefetch misses from the L3 to the next hierarchy of the memory system. In most
platforms, this represents memory bandwidth.
•
CPUID.(EAX=0FH, ECX=1H).EDX[bit 2]: indicates L3 local memory bandwidth monitoring event is supported if
set. This event monitors the L3 external bandwidth satisfied by the local memory. In most platforms that
support this event, L3 requests are likely serviced by a memory system with non-uniform memory architecture.
This allows bandwidth to off-package memory resources to be tracked by subtracting total from local bandwidth
(for instance, bandwidth over QPI to a memory controller on another physical processor could be tracked by
subtraction).
The corresponding Event ID can be looked up from Table 17-18. The L3 bandwidth data accumulated in
IA32_QM_CTR can be converted to total bandwidth (in bytes) using CPUID.(EAX=0FH, ECX=1H).EBX.
Table 17-18. Monitoring Supported Event IDs
Event Type
Event ID
Context
L3 Cache Occupancy
01H
Cache Monitoring Technology
L3 Total External Bandwidth
02H
MBM
L3 Local External Bandwidth
03H
MBM
Reserved
All other event codes
N/A
17.16.6
Monitoring Resource RMID Association
After Monitoring and sub-features has been enumerated, software can begin using the monitoring features. The
first step is to associate a given software thread (or multiple threads as part of an application, VM, group of applications or other abstraction) with an RMID.
Note that the process of associating an RMID with a given software thread is the same for all shared resource monitoring features (CMT, MBM), and a given RMID number has the same meaning from the viewpoint of any logical
processors in a package. Stated another way, a thread may be associated in a 1:1 mapping with an RMID, and that
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RMID may allow cache occupancy, memory bandwidth information or other monitoring data to be read back later
with monitoring event codes (retrieving data is discussed in a previous section).
The association of an application thread with an RMID requires an OS to program the per-logical-processor MSR
IA32_PQR_ASSOC at context swap time (updates may also be made at any other arbitrary points during program
execution such as application phase changes). The IA32_PQR_ASSOC MSR specifies the active RMID that monitoring hardware will use to tag internal operations, such as L3 cache requests. The layout of the MSR is shown in
Figure 17-23. Software specifies the active RMID to monitor in the IA32_PQR_ASSOC.RMID field. The width of the
RMID field can vary from one implementation to another, and is derived from Ceil (LOG2 ( 1 + CPUID.(EAX=0FH,
ECX=0):EBX[31:0])). The value of IA32_PQR_ASSOC after power-on is 0.
Width of IA32_PQR_ASSOC.RMID field: Log2 ( CPUID.(EAX=0FH, ECX=0H).EBX[31:0] +1)
32 31
63
Reserved for CLOS*
0
10 9
Reserved
RMID
IA32_PQR_ASSOC
*See Section 17.15
Figure 17-23. IA32_PQR_ASSOC MSR
In the initial implementation, the width of the RMID field is up to 10 bits wide, zero-referenced and fully encoded.
However, software must use CPUID to query the maximum RMID supported by the processor. If a value larger than
the maximum RMID is written to IA32_PQR_ASSOC.RMID, a #GP(0) fault will be generated.
RMIDs have a global scope within the physical package- if an RMID is assigned to one logical processor then the
same RMID can be used to read multiple thread attributes later (for example, L3 cache occupancy or external
bandwidth from the L3 to the next level of the cache hierarchy). In a multiple LLC platform the RMIDs are to be
reassigned by the OS or VMM scheduler when an application is migrated across LLCs.
Note that in a situation where Monitoring supports multiple resource types, some upper range of RMIDs (e.g. RMID
31) may only be supported by one resource type but not by another resource type.
17.16.7
Monitoring Resource Selection and Reporting Infrastructure
The reporting mechanism for Cache Monitoring Technology and other related features is architecturally exposed as
an MSR pair that can be programmed and read to measure various metrics such as the L3 cache occupancy (CMT)
and bandwidths (MBM) depending on the level of Monitoring support provided by the platform. Data is reported
back on a per-RMID basis. These events do not trigger based on event counts or trigger APIC interrupts (e.g. no
Performance Monitoring Interrupt occurs based on counts). Rather, they are used to sample counts explicitly.
The MSR pair for the shared resource monitoring features (CMT, MBM) is separate from and not shared with architectural Perfmon counters, meaning software can use these monitoring features simultaneously with the Perfmon
counters.
Access to the aggregated monitoring information is accomplished through the following programmable monitoring
MSRs:
•
IA32_QM_EVTSEL: This MSR provides a role similar to the event select MSRs for programmable performance
monitoring described in Chapter 18. The simplified layout of the MSR is shown in Figure 17-24. Bits
IA32_QM_EVTSEL.EvtID (bits 7:0) specify an event code of a supported resource type for hardware to report
monitored data associated with IA32_QM_EVTSEL.RMID (bits 41:32). Software can configure
IA32_QM_EVTSEL.RMID with any RMID that is active within the physical processor. The width of
IA32_QM_EVTSEL.RMID matches that of IA32_PQR_ASSOC.RMID. Supported event codes for the
IA32_QM_EVTSEL register are shown in Table 17-18. Note that valid event codes may not necessarily map
directly to the bit position used to enumerate support for the resource via CPUID.
Software can program an RMID / Event ID pair into the IA32_QM_EVTSEL MSR bit field to select an RMID to
read a particular counter for a given resource. The currently supported list of Monitoring Event IDs is discussed
in Section 17.16.5, which covers feature-specific details.
Vol. 3B 17-47
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
Thread access to the IA32_QM_EVTSEL and IA32_QM_CTR MSR pair should be serialized to avoid situations
where one thread changes the RMID/EvtID just before another thread reads monitoring data from
IA32_QM_CTR.
•
IA32_QM_CTR: This MSR reports monitored data when available. It contains three bit fields. If software
configures an unsupported RMID or event type in IA32_QM_EVTSEL, then IA32_QM_CTR.Error (bit 63) will be
set, indicating there is no valid data to report. If IA32_QM_CTR.Unavailable (bit 62) is set, it indicates
monitored data for the RMID is not available, and IA32_QM_CTR.data (bits 61:0) should be ignored. Therefore,
IA32_QM_CTR.data (bits 61:0) is valid only if bit 63 and 62 are both clear. For Cache Monitoring Technology,
software can convert IA32_QM_CTR.data into cache occupancy or bandwidth metrics expressed in bytes by
multiplying with the conversion factor from CPUID.(EAX=0FH, ECX=1H).EBX.
63
32 31
42 41
Reserved
8 7
Reserved
RMID
61
63
0
IA32_QM_EVTSEL
EvtID
0
E U
IA32_QM_CTR
Resource Monitoring Data
Figure 17-24. IA32_QM_EVTSEL and IA32_QM_CTR MSRs
17.16.8
Monitoring Programming Considerations
Figure 17-23 illustrates how system software can program IA32_QOSEVTSEL and IA32_QM_CTR to perform
resource monitoring.
System Software
RMID
Event ID
IA32_QOSEVTSEL MSR
63
Reserved
32
41
RMID
7
Reserved
Counter Data
IA32_QM_CTR MSR
63 62
0
Event ID
Resource Monitoring ID
0
Monitoring Data
EvtID
Availability
Error
Figure 17-25. Software Usage of Cache Monitoring Resources
Though the field provided in IA32_QM_CTR allows for up to 62 bits of data to be returned, often a subset of bits are
used. With Cache Monitoring Technology for instance, the number of bits used will be proportional to the base-two
logarithm of the total cache size divided by the Upscaling Factor from CPUID.
In Memory Bandwidth Monitoring the initial counter size is 24 bits, and retrieving the value at 1Hz or faster is sufficient to ensure at most one rollover per sampling period. Any future changes to counter width will be enumerated
to software.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.16.8.1 Monitoring Dynamic Configuration
Both the IA32_QM_EVTSEL and IA32_PQR_ASSOC registers are accessible and modifiable at any time during
execution using RDMSR/WRMSR unless otherwise noted. When writing to these MSRs a #GP(0) will be generated
if any of the following conditions occur:
•
•
A reserved bit is modified,
An RMID exceeding the maxRMID is used.
17.16.8.2 Monitoring Operation With Power Saving Features
Note that some advanced power management features such as deep package C-states may shrink the L3 cache
and cause CMT occupancy count to be reduced. MBM bandwidth counts may increase due to flushing cached data
out of L3.
17.16.8.3 Monitoring Operation with Other Operating Modes
The states in IA32_PQR_ASSOC and monitoring counter are unmodified across an SMI delivery. Thus, the execution of SMM handler code and SMM handler’s data can manifest as spurious contribution in the monitored data.
It is possible for an SMM handler to minimize the impact on of spurious contribution in the QOS monitoring counters by reserving a dedicated RMID for monitoring the SMM handler. Such an SMM handler can save the previously
configured QOS Monitoring state immediately upon entering SMM, and restoring the QOS monitoring state back to
the prev-SMM RMID upon exit.
17.16.8.4 Monitoring Operation with RAS Features
In general the Reliability, Availability and Serviceability (RAS) features present in Intel Platforms are not expected
to significantly affect shared resource monitoring counts. In cases where software RAS features cause memory
copies or cache accesses these may be tracked and may influence the shared resource monitoring counter values.
17.17
INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION
FEATURES
The Intel Resource Director Technology (Intel RDT) feature set provides a set of allocation (resource control) capabilities including Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP). The Intel Xeon
processor E5 v4 family (and subset of communication-focused Intel Xeon processors E5 v3 family) introduce capabilities to configure and make use of the Cache Allocation Technology (CAT) mechanisms on the L3 cache. Some
future Intel platforms may also provide support for control over the L2 cache, with capabilities as described below.
The programming interface for Cache Allocation Technology and for the more general allocation capabilities are
described in the rest of this chapter.
Cache Allocation Technology enables an Operating System (OS), Hypervisor /Virtual Machine Manager (VMM) or
similar system service management agent to specify the amount of cache space into which an application can fill
(as a hint to hardware - certain features such as power management may override CAT settings). Specialized userlevel implementations with minimal OS support are also possible, though not necessarily recommended (see notes
below for OS/Hypervisor with respect to ring 3 software and virtual guests). Depending on the processor famility,
L2 or L3 cache allocation capability may be provided, and the technology is designed to scale across multiple cache
levels and technology generations.
Software can determine which levels are supported in a give platform programmatically using CPUID as described
in the following sections.
The CAT mechanisms defined in this document provide the following key features:
•
A mechanism to enumerate platform Cache Allocation Technology capabilities and available resource types that
provides CAT control capabilities. For implementations that support Cache Allocation Technology, CPUID
provides enumeration support to query which levels of the cache hierarchy are supported and specific CAT
capabilities, such as the max allocation bitmask size,
Vol. 3B 17-49
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
A mechanism for the OS or Hypervisor to configure the amount of a resource available to a particular Class of
Service via a list of allocation bitmasks,
•
•
Mechanisms for the OS or Hypervisor to signal the Class of Service to which an application belongs, and
Hardware mechanisms to guide the LLC fill policy when an application has been designated to belong to a
specific Class of Service.
Note that for many usages, an OS or Hypervisor may not want to expose Cache Allocation Technology mechanisms
to Ring3 software or virtualized guests.
The Cache Allocation Technology feature enables more cache resources (i.e. cache space) to be made available for
high priority applications based on guidance from the execution environment as shown in Figure 17-26. The architecture also allows dynamic resource reassignment during runtime to further optimize the performance of the high
priority application with minimal degradation to the low priority app. Additionally, resources can be rebalanced for
system throughput benefit across uses cases of OSes, VMMs, containers and other scenarios by managing the
CPUID and MSR interfaces. This section describes the hardware and software support required in the platform
including what is required of the execution environment (i.e. OS/VMM) to support such resource control. Note that
in Figure 17-26 the L3 Cache is shown as an example resource.
With CAT
Without CAT
Hi Pri App
Lo Pri App
Hi Pri App
Lo Pri App
Core 0
Core 1
Core 0
Core 1
Shared LLC, Low priority got more cache
Shared LLC, High priority got more cache
Figure 17-26. Cache Allocation Technology Allocates More Resource to High Priority Applications
17.17.1
Cache Allocation Technology Architecture
The fundamental goal of Cache Allocation Technology is to enable resource allocation based on application priority
or Class of Service (COS or CLOS). The processor exposes a set of Classes of Service into which applications (or
individual threads) can be assigned. Cache allocation for the respective applications or threads is then restricted
based on the class with which they are associated. Each Class of Service can be configured using capacity bitmasks
(CBMs) which represent capacity and indicate the degree of overlap and isolation between classes. For each logical
processor there is a register exposed (referred to here as the IA32_PQR_ASSOC MSR or PQR) to allow the OS/VMM
to specify a COS when an application, thread or VM is scheduled.
The usage of Classes of Service (COS) are consistent across resources - and a COS may have multiple re-source
control attributes attached, which reduces software overhead at context swap time. Rather than adding new types
of COS tags per resource for instance, the COS management overhead is constant. Cache allocation for the indicated application/thread/VM is then controlled automatically by the hardware based on the class and the bitmask
associated with that class. Bitmasks are configured via the IA32_resourceType_MASK_n MSRs, where
resourceType indicates a resource type (e.g. “L3” for the L3 cache) and n indicates a COS number.
The basic ingredients of Cache Allocation Technology are as follows:
•
An architecturally exposed mechanism using CPUID to indicate whether CAT is supported, and what resource
types are available which can be controlled,
•
For each available resourceType, CPUID also enumerates the total number of Classes of Services and the length
of the capacity bitmasks that can be used to enforce cache allocation to applications on the platform,
•
An architecturally exposed mechanism to allow the execution environment (OS/VMM) to configure the behavior
of different classes of service using the bitmasks available,
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
An architecturally exposed mechanism to allow the execution environment (OS/VMM) to assign a COS to an
executing software thread (i.e. associating the active CR3 of a logical processor with the COS in
IA32_PQR_ASSOC),
•
Implementation-dependent mechanisms to indicate which COS is associated with a memory access and to
enforce the cache allocation on a per COS basis.
A capacity bitmask (CBM) provides a hint to the hardware indicating the cache space an application should be
limited to as well as providing an indication of overlap and isolation in the CAT-capable cache from other applications contending for the cache. The bitlength of the capacity mask available generally depends on the configuration
of the cache and is specified in the enumeration process for CAT in CPUID (this may vary between models in a
processor family as well). Similarly, other parameters such as the number of supported COS may vary for each
resource type, and these details can be enumerated via CPUID.
M7
M6
M5
M4
M3
M2
M1
M0
COS0
A
A
A
A
A
A
A
A
COS1
A
A
A
A
A
A
A
A
COS2
A
A
A
A
A
A
A
A
COS3
A
A
A
A
A
A
A
A
M7
M6
A
COS0
M5
A
M4
A
M3
A
COS1
M2
M1
M0
A
A
A
A
A
A
A
A
A
A
COS2
M7
COS1
COS2
COS3
Overlapped Bitmask
A
COS3
COS0
Default Bitmask
M6
A
M5
A
M4
A
M3
M2
M1
M0
A
Isolated Bitmask
A
A
A
A
Figure 17-27. Examples of Cache Capacity Bitmasks
Sample cache capacity bitmasks for a bitlength of 8 are shown in Figure 17-27. Please note that all (and only)
contiguous '1' combinations are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.). Attempts to program a value without
contiguous '1's (including zero) will result in a general protection fault (#GP(0)). It is generally expected that in
way-based implementations, one capacity mask bit corresponds to some number of ways in cache, but the specific
mapping is implementation-dependent. In all cases, a mask bit set to '1' specifies that a particular Class of Service
can allocate into the cache subset represented by that bit. A value of '0' in a mask bit specifies that a Class of
Service cannot allocate into the given cache subset. In general, allocating more cache to a given application is
usually beneficial to its performance.
Figure 17-27 also shows three examples of sets of Cache Capacity Bitmasks. For simplicity these are represented
as 8-bit vectors, though this may vary depending on the implementation and how the mask is mapped to the available cache capacity. The first example shows the default case where all 4 Classes of Service (the total number of
COS are implementation-dependent) have full access to the cache. The second case shows an overlapped case,
which would allow some lower-priority threads share cache space with the highest priority threads. The third case
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
shows various non-overlapped partitioning schemes. As a matter of software policy for extensibility COS0 should
typically be considered and configured as the highest priority COS, followed by COS1, and so on, though there is
no hardware restriction enforcing this mapping. When the system boots all threads are initialized to COS0, which
has full access to the cache by default.
Though the representation of the CBMs looks similar to a way-based mapping they are independent of any specific
enforcement implementation (e.g. way partitioning.) Rather, this is a convenient manner to represent capacity,
overlap and isolation of cache space. For example, executing a POPCNT instruction (population count of set bits) on
the capacity bitmask can provide the fraction of cache space that a class of service can allocate into. In addition to
the fraction, the exact location of the bits also shows whether the class of service overlaps with other classes of
service or is entirely isolated in terms of cache space used.
Enum/Confg
Association
Enforcement
Enumerate
Enforcement
OS Context
Switch
Application
Memory Request
Configure CBM for
each Class of Service
Set Class of Service
in IA32_PQR
Tag with Cache
Class of Service
Config
COS = 2
Mem Request
COS
Transaction
Cache Subsystem
Enforce Mask
Cache Allocation
Set 1
Set 2
COS 0
Capacity bitmask 3
COS 1
Capacity bitmask 3
COS 2
Capacity bitmask 3
COS 3
Capacity bitmask 3
....
Set n
way 1
......
way 16
Figure 17-28. Class of Service and Cache Capacity Bitmasks
Figure 17-28 shows how the Cache Capacity Bitmasks and the per-logical-processor Class of Service are logically
used to enable Cache Allocation Technology. All (and only) contiguous 1's in the CBM are permitted. The length of
CBM may vary from resource to resource or between processor generations and can be enumerated using CPUID.
From the available mask set and based on the goals of the OS/VMM (shared or isolated cache, etc.) bitmasks are
selected and associated with different classes of service. For the available Classes of Service the associated CBMs
can be programmed via the global set of CAT configuration registers (in the case of L3 CAT, via the
IA32_L3_MASK_n MSRs, where “n” is the Class of Service, starting from zero). In all architectural implementations
supporting CPUID it is possible to change the CBMs dynamically, during program execution, unless stated otherwise by Intel.
The currently running application's Class of Service is communicated to the hardware through the per-logicalprocessor PQR MSR (IA32_PQR_ASSOC MSR). When the OS schedules an application thread on a logical processor,
the application thread is associated with a specific COS (i.e. the corresponding COS in the PQR) and all requests to
the CAT-capable resource from that logical processor are tagged with that COS (in other words, the application
thread is configured to belong to a specific COS). The cache subsystem uses this tagged request information to
enforce QoS. The capacity bitmask may be mapped into a way bitmask (or a similar enforcement entity based on
the implementation) at the cache before it is applied to the allocation policy. For example, the capacity bitmask can
be an 8-bit mask and the enforcement may be accomplished using a 16-way bitmask for a cache enforcement
implementation based on way partitioning.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
The following sections describe extensions of CAT such as Code and Data Prioritization (CDP), followed by details
on specific features such as L3 CAT, L3 CDP, and L2 CAT. Depending on the specific processor a mix of features may
be supported, and CPUID provides enumeration capabilities to enable software to detect the set of supported
features.
17.17.2
Code and Data Prioritization (CDP) Technology
Code and Data Prioritization Technology is an extension of CAT. CDP enables isolation and separate prioritization of
code and data fetches to the L3 cache in a software configurable manner, which can enable workload prioritization
and tuning of cache capacity to the characteristics of the workload. CDP extends Cache Allocation Technology (CAT)
by providing separate code and data masks per Class of Service (COS).
By default, CDP is disabled on the processor. If the CAT MSRs are used without enabling CDP, the processor operates in a traditional CAT-only mode. When CDP is enabled,
•
the CAT mask MSRs are re-mapped into interleaved pairs of mask MSRs for data or code fetches (see
Figure 17-29),
•
the range of COS for CAT is re-indexed, with the lower-half of the COS range available for CDP.
Using the CDP feature, virtual isolation between code and data can be configured on the L3 cache if desired, similar
to how some processor cache levels provide separate L1 data and L1 instruction caches.
Like the CAT feature, CDP may be dynamically configured by privileged software at any point during normal system
operation, including dynamically enabling or disabling the feature provided that certain software configuration
requirements are met (see Section 17.17.4).
An example of the operating mode of CDP is shown in Figure 17-29. Shown at the top are traditional CAT usage
models where capacity masks map 1:1 with a COS number to enable control over the cache space which a given
COS (and thus applications, threads or VMs) may occupy. Shown at the bottom are example mask configurations
where CDP is enabled, and each COS number maps 1:2 to two masks, one for code and one for data. This enables
code and data to be either overlapped or isolated to varying degrees either globally or on a per-COS basis,
depending on application and system needs.
Example of CAT-Only Usage - 16 bit Capacity Masks
COS0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
COS1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
COS2
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
COS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Traditional
CAT
Example of Code/Data Prioritization Usage - 16 bit Capacity Masks
COS0.Data
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
COS0.Code
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
COS1.Data
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
COS1.Code
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Other COS.Data
Other COS.Code
CAT with
CDP
Figure 17-29. Code and Data Capacity Bitmasks of CDP
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
When CDP is enabled, the existing mask space for CAT-only operation is split. As an example if the system supports
16 CAT-only COS, when CDP is enabled the same MSR interfaces are used, however half of the masks correspond
to code, half correspond to data, and the effective number of COS is reduced by half. Code/Data masks are defined
per-COS and interleaved in the MSR space as described in subsequent sections.
17.17.3
Enabling Cache Allocation Technology Usage Flow
Figure 17-30 illustrates the key steps for OS/VMM to detect support of Cache Allocation Technology and enable
priority-based resource allocation for a CAT-capable resource.
On OS/VMM Initialization
CQE Capability
Enumeration
Cache Allocation Configuration
Set COS for scheduled
thread context
Configure CBM
per COS
WRMSR
CPUID[
CPUID.(7,0):EBX.15
CPUID.(10H,0):EBX[31:1]
CPUID.(10H,1):EAX[4:0]
CPUID.(10H,1):EDX[15:0]
CPUID.(10H,1):EBX[
On Context Switch
IA32_L3_QOS_MASK_0
...
WRMSR
IA32_PQR_ASSOC
A32_L3_QOS_MASK_n
Figure 17-30. Cache Allocation Technology Usage Flow
Enumeration and configuration of L2 CAT is similar to L3 CAT, however CPUID details and MSR addresses differ.
Common CLOS are used across the features.
17.17.3.1 Enumeration and Detection Support of Cache Allocation Technology
Software can query processor support of CAT capabilities by executing CPUID instruction with EAX = 07H, ECX =
0H as input. If CPUID.(EAX=07H, ECX=0):EBX.PQE[bit 15] reports 1, the processor supports software control over
shared processor resources. Software must use CPUID leaf 10H to enumerate additional details of available
resource types, classes of services and capability bitmasks. The programming interfaces provided by Cache Allocation Technology include:
•
CPUID leaf function 10H (Cache Allocation Technology Enumeration leaf) and its sub-functions provide
information on available resource types, and CAT capability for each resource type (see Section 17.17.3.2).
•
IA32_L3_MASK_n: A range of MSRs is provided for each resource type, each MSR within that range specifying
a software-configured capacity bitmask for each class of service. For L3 with Cache Allocation support, the CBM
is specified using one of the IA32_L3_QOS_MASK_n MSR, where 'n' corresponds to a number within the
supported range of COS, i.e. the range between 0 and CPUID.(EAX=10H, ECX=ResID):EDX[15:0], inclusive.
See Section 17.17.3.3 for details.
•
IA32_L2_MASK_n: A range of MSRs is provided for L2 Cache Allocation Technology, enabling software control
over the amount of L2 cache available for each CLOS. Similar to L3 CAT, a CBM is specified for each CLOS using
the set of registers, IA32_L2_QOS_MASK_n MSR, where 'n' ranges from zero to the maximum CLOS number
reported for L2 CAT in CPUID. See Section 17.17.3.3 for details.
The L2 mask MSRs are scoped at the same level as the L2 cache (similarly, the L3 mask MSRs are scoped at the
same level as the L3 cache). Software may determine which logical processors share an MSR (for instance local
to a core, or shared across multiple cores) by performing a write to one of these MSRs and noting which logical
threads observe the change. Example flows for a similar method to determine register scope are described in
Section 15.5.2, “System Software Recommendation for Managing CMCI and Machine Check Resources”.
Software may also use CPUID leaf 4 to determine the maximum number of logical processor IDs that may share
a given level of the cache.
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
IA32_PQR_ASSOC.CLOS: The IA32_PQR_ASSOC MSR provides a COS field that OS/VMM can use to assign a
logical processor to an available COS. The set of COS are common across all allocation features, meaning that
multiple features may be supported in the same processor without additional software COS management
overhead at context swap time. See Section 17.17.3.4 for details.
17.17.3.2 Cache Allocation Technology: Resource Type and Capability Enumeration
CPUID leaf function 10H (Cache Allocation Technology Enumeration leaf) provides two or more sub-functions:
•
CAT Enumeration leaf sub-function 0 enumerates available resource types that support allocation control, i.e.
by executing CPUID with EAX=10H and ECX=0H. Each supported resource type is represented by a bit field in
CPUID.(EAX=10H, ECX=0):EBX[31:1]. The bit position of each set bit corresponds to a Resource ID (ResID),
for instance ResID=1 is used to indicate L3 CAT support, and ResID=2 indicates L2 CAT support. The ResID is
also the sub-leaf index that software must use to query details of the CAT capability of that resource type (see
Figure 17-31).
CPUID.(EAX=10H, ECX=0H) Output: (EAX: Reserved; ECX: Reserved; EDX: Reserved)
3 2 1
L L
2 3
31
EBX
Reserved
0
Figure 17-31. CPUID.(EAX=10H, ECX=0H) Available Resource Type Identification
— EAX[4:0] reports the length of the capacity bitmask length using minus-one notation, i.e. a value of 15
corresponds to the capability bitmask having length of 16 bits. Bits 31:5 of EAX are reserved.
•
Sub-functions of CPUID.EAX=10H with a non-zero ECX input matching a supported ResID enumerate the
specific enforcement details of the corresponding ResID. The capabilities enumerated include the length of the
capacity bitmasks and the number of Classes of Service for a given ResID. Software should query the capability
of each available ResID that supports CAT from a sub-leaf of leaf 10H using the sub-leaf index reported by the
corresponding non-zero bit in CPUID.(EAX=10H, ECX=0):EBX[31:1] in order to obtain additional feature
details.
•
CAT capability for L3 is enumerated by CPUID.(EAX=10H, ECX=1H), see Figure 17-32. The specific CAT
capabilities reported by CPUID.(EAX=10H, ECX=1) are:
CPUID.(EAX=10H, ECX=ResID=1) Output:
5 4
31
EAX
Reserved
0
CBM_LEN
31
EBX
0
Bitmask of Shareable Resource with Other executing entities
31
ECX
2 1
0
Reserved
CDP
16 15
31
EDX
Reserved
0
COS_MAX
Figure 17-32. L3 Cache Allocation Technology and CDP Enumeration
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— CPUID.(EAX=10H, ECX=ResID=1):EAX[4:0] reports the length of the capacity bitmask length using
minus-one notation, i.e. a value of 15 corresponds to the capability bitmask having length of 16 bits. Bits
31:5 of EAX are reserved.
— CPUID.(EAX=10H, ECX=1):EBX[31:0] reports a bit mask. Each set bit within the length of the CBM
indicates the corresponding unit of the L3 allocation may be used by other entities in the platform (e.g. an
integrated graphics engine or hardware units outside the processor core and have direct access to L3). Each
cleared bit within the length of the CBM indicates the corresponding allocation unit can be configured to
implement a priority-based allocation scheme chosen by an OS/VMM without interference with other
hardware agents in the system. Bits outside the length of the CBM are reserved.
— CPUID.(EAX=10H, ECX=1):ECX.CDP[bit 2]: If 1, indicates Code and Data Prioritization Technology is
supported (see Section 17.17.4). Other bits of CPUID.(EAX=10H, ECX=1):ECX are reserved.
— CPUID.(EAX=10H, ECX=1):EDX[15:0] reports the maximum COS supported for the resource (COS are
zero-referenced, meaning a reported value of '15' would indicate 16 total supported COS). Bits 31:16 are
reserved.
•
CAT capability for L2 is enumerated by CPUID.(EAX=10H, ECX=2H), see Figure 17-33. The specific CAT
capabilities reported by CPUID.(EAX=10H, ECX=2) are:
CPUID.(EAX=10H, ECX=ResID=2) Output:
5 4
31
EAX
Reserved
0
CBM_LEN
31
EBX
0
Bitmask of Shareable Resource with Other executing entities
31
ECX
0
Reserved
16 15
31
EDX
Reserved
0
COS_MAX
Figure 17-33. L2 Cache Allocation Technology
— CPUID.(EAX=10H, ECX=ResID=2):EAX[4:0] reports the length of the capacity bitmask length using
minus-one notation, i.e. a value of 15 corresponds to the capability bitmask having length of 16 bits. Bits
31:5 of EAX are reserved.
— CPUID.(EAX=10H, ECX=2):EBX[31:0] reports a bit mask. Each set bit within the length of the CBM
indicates the corresponding unit of the L2 allocation may be used by other entities in the platform. Each
cleared bit within the length of the CBM indicates the corresponding allocation unit can be configured to
implement a priority-based allocation scheme chosen by an OS/VMM without interference with other
hardware agents in the system. Bits outside the length of the CBM are reserved.
— CPUID.(EAX=10H, ECX=2):ECX: reserved.
— CPUID.(EAX=10H, ECX=2):EDX[15:0] reports the maximum COS supported for the resource (COS are
zero-referenced, meaning a reported value of '15' would indicate 16 total supported COS). Bits 31:16 are
reserved.
A note on migration of Classes of Service (COS): Software should minimize migrations of COS across logical
processors (across threads or cores), as a reduction in the performance of the Cache Allocation Technology feature
may result if COS are migrated frequently. This is aligned with the industry-standard practice of minimizing unnecessary thread migrations across processor cores in order to avoid excessive time spent warming up processor
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caches after a migration. In general, for best performance, minimize thread migration and COS migration across
processor logical threads and processor cores.
17.17.3.3 Cache Allocation Technology: Cache Mask Configuration
After determining the length of the capacity bitmasks (CBM) and number of COS supported using CPUID (see
Section 17.17.3.2), each COS needs to be programmed with a CBM to dictate its available cache via a write to the
corresponding IA32_resourceType_MASK_n register, where 'n' corresponds to a number within the supported
range of COS, i.e. the range between 0 and CPUID.(EAX=10H, ECX=ResID):EDX[15:0], inclusive, and
'resourceType' corresponds to a specific resource as enumerated by the set bits of CPUID.(EAX=10H,
ECX=0):EAX[31:1], for instance, ‘L2’ or ‘L3’ cache.
A hierarchy of MSRs is reserved for Cache Allocation Technology registers of the form
IA32_resourceType_MASK_n:
•
from 0C90H through 0D8FH (inclusive), providing support for multiple sub-ranges to support varying resource
types. The first supported resourceType is 'L3', corresponding to the L3 cache in a platform. The MSRs range
from 0C90H through 0D0FH (inclusive), enables support for up to 128 L3 CAT Classes of Service.
31
63
COS
63
0
10 9
32 31
Reserved
IA32_PQR_ASSOC
RMID
Reserved
0
IA32_L3_MASK_0
Bit_Mask
....
63
32 31
Reserved
0
Bit_Mask
IA32_L3_MASK_n
Figure 17-34. IA32_PQR_ASSOC, IA32_L3_MASK_n MSRs
•
Within the same CAT range hierarchy, another set of registers is defined for resourceType 'L2', corresponding
to the L2 cache in a platform, and MSRs IA32_L2_MASK_n are defined for n=[0,63] at addresses 0D10H
through 0D4FH (inclusive).
Figure 17-34 and Figure 17-35 provide an overview of the relevant registers.
63
32 31
Reserved
0
IA32_L2_MASK_0
Bit_Mask
....
63
32 31
Reserved
0
Bit_Mask
IA32_L2_MASK_n
Figure 17-35. IA32_L2_MASK_n MSRs
All CAT configuration registers can be accessed using the standard RDMSR / WRMSR instructions.
Note that once L3 or L2 CAT masks are configured, threads can be grouped into Classes of Service (COS) using the
IA32_PQR_ASSOC MSR as described in Section 17.17.3.4 (Class of Service (COS) to Cache Mask Association:
Common Across Allocation Features)
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17.17.3.4 Class of Service to Cache Mask Association: Common Across Allocation Features
After configuring the available classes of service with the preferred set of capacity bitmasks, the OS/VMM can set
the IA32_PQR_ASSOC.COS of a logical processor to the class of service with the desired CBM when a thread
context switch occurs. This allows the OS/VMM to indicate which class of service an executing thread/VM belongs
within. Each logical processor contains an instance of the IA32_PQR_ASSOC register at MSR location 0C8FH, and
Figure 17-34 shows the bit field layout for this register. Bits[63:32] contain the COS field for each logical processor.
Note that placing the RMID field within the same PQR register enables both RMID and CLOS to be swapped at
context swap time for simultaneous use of monitoring and allocation features with a single register write for efficiency.
When CDP is enabled, Specifying a COS value in IA32_PQR_ASSOC.COS greater than MAX_COS_CDP =(
CPUID.(EAX=10H, ECX=1):EDX[15:0] >> 1) will cause undefined performance impact to code and data fetches.
Note that if the IA32_PQR_ASSOC.COS is never written then the CAT capability defaults to using COS 0, which in
turn is set to the default mask in IA32_L3_MASK_0 - which is all “1”s (on reset). This essentially disables the
enforcement feature by default or for legacy operating systems and software.
See Section 17.17.5, “Cache Allocation Technology Programming Considerations” for important COS programming
considerations including maximum values when using CAT and CDP.
17.17.4
Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology
CDP is an extension of CAT. The presence of the CDP feature is enumerated via CPUID.(EAX=10H,
ECX=1):ECX.CDP[bit 2] (see Figure 17-32). Most of the CPUID.(EAX=10H, ECX=1) sub-leaf data that applies to
CAT also apply to CDP. However, CPUID.(EAX=10H, ECX=1):EDX.COS_MAX_CAT specifies the maximum COS
applicable to CAT-only operation. For CDP operations, COS_MAX_CDP is equal to (CPUID.(EAX=10H,
ECX=1):EDX.COS_MAX_CAT >>1).
If CPUID.(EAX=10H, ECX=1):ECX.CDP[bit 2] =1, the processor supports CDP and provides a new MSR
IA32_L3_QOS_CFG at address 0C81H. The layout of IA32_L3_QOS_CFG is shown in Figure 17-36. The bit field
definition of IA32_L3_QOS_CFG are:
•
Bit 0: L3 CDP Enable. If set, enables CDP, maps CAT mask MSRs into pairs of Data Mask and Code Mask MSRs.
The maximum allowed value to write into IA32_PQR_ASSOC.COS is COS_MAX_CDP.
•
Bits 63:1: Reserved. Attempts to write to reserved bits result in a #GP(0).
63
IA32_L3_QOS_CFG
3 2 1
0
Reserved
L3 CDP Enable
Figure 17-36. Layout of IA32_L3_QOS_CFG
IA32_L3_QOS_CFG default values are all 0s at RESET, the mask MSRs are all 1s. Hence. all logical processors are
initialized in COS0 allocated with the entire L3 with CDP disabled, until software programs CAT and CDP.
Before enabling or disabling CDP, software should write all 1's to all of the CAT/CDP masks to ensure proper
behavior (e.g., the IA32_L3_QOS_Mask_n set of MSRs). When enabling CDP, software should also ensure that only
COS number which are valid in CDP operation is used, otherwise undefined behavior may result. For instance in a
case with 16 CAT COS, since COS are reduced by half when CDP is enabled, software should ensure that only COS
0-7 are in use before enabling CDP (along with writing 1's to all mask bits before enabling or disabling CDP).
Software should also account for the fact that mask interpretations change when CDP is enabled or disabled,
meaning for instance that a CAT mask for a given COS may become a code mask for a different Class of Service
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when CDP is enabled. In order to simplify this behavior and prevent unintended remapping software should
consider resetting all threads to COS[0] before enabling or disabling CDP.
17.17.4.1 Mapping Between L3 CDP Masks and CAT Masks
When CDP is enabled, the existing CAT mask MSR space is re-mapped to provide a code mask and a data mask per
COS. The re-mapping is shown in
Table 17-19. Re-indexing of COS Numbers and Mapping to CAT/CDP Mask MSRs
Mask MSR
CAT-only Operation
CDP Operation
IA32_L3_QOS_Mask_0
COS0
COS0.Data
IA32_L3_QOS_Mask_1
COS1
COS0.Code
IA32_L3_QOS_Mask_2
COS2
COS1.Data
IA32_L3_QOS_Mask_3
COS3
COS1.Code
IA32_L3_QOS_Mask_4
COS4
COS2.Data
IA32_L3_QOS_Mask_5
COS5
COS2.Code
....
....
....
IA32_L3_QOS_Mask_’2n’
COS’2n’
COS’n’.Data
IA32_L3_QOS_Mask_’2n+1’
COS’2n+1’
COS’n’.Code
One can derive the MSR address for the data mask or code mask for a given COS number ‘n’ by:
•
•
data_mask_address (n) = base + (n <<1), where base is the address of IA32_L3_QOS_MASK_0.
code_mask_address (n) = base + (n <<1) +1.
When CDP is enabled, each COS is mapped 1:2 with mask MSRs, with one mask enabling programmatic control
over data fill location and one mask enabling control over data placement. A variety of overlapped and isolated
mask configurations are possible (see the example in Figure 17-29).
Mask MSR field definitions remain the same. Capacity masks must be formed of contiguous set bits, with a length
of 1 bit or longer and should not exceed the maximum mask length specified in CPUID. As examples, valid masks
on a cache with max bitmask length of 16b (from CPUID) include 0xFFFF, 0xFF00, 0x00FF, 0x00F0, 0x0001,
0x0003 and so on. Maximum valid mask lengths are unchanged whether CDP is enabled or disabled, and writes of
invalid mask values may lead to undefined behavior. Writes to reserved bits will generate #GP(0).
17.17.4.2 L3 CAT: Disabling CDP
Before enabling or disabling CDP, software should write all 1's to all of the CAT/CDP masks to ensure proper
behavior (e.g., the IA32_L3_QOS_Mask_n set of MSRs).
Software should also account for the fact that mask interpretations change when CDP is enabled or disabled,
meaning for instance that a CAT mask for a given COS may become a code mask for a different Class of Service
when CDP is enabled. In order to simplify this behavior and prevent unintended remapping software should
consider resetting all threads to COS[0] before enabling or disabling CDP.
17.17.5
Cache Allocation Technology Programming Considerations
17.17.5.1 Cache Allocation Technology Dynamic Configuration
Both the CAT masks and CQM registers are accessible and modifiable at any time during execution using
RDMSR/WRMSR unless otherwise noted. When writing to these MSRs a #GP(0) will be generated if any of the
following conditions occur:
•
A reserved bit is modified,
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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
•
Accessing a QOS mask register outside the supported COS (the max COS number is specified in
CPUID.(EAX=10H, ECX=ResID):EDX[15:0]), or
•
Writing a COS greater than the supported maximum (specified as the maximum value of CPUID.(EAX=10H,
ECX=ResID):EDX[15:0] for all valid ResID values) is written to the IA32_PQR_ASSOC.CLOS field.
When CDP is enabled, specifying a COS value in IA32_PQR_ASSOC.COS outside of the lower half of the COS space
will cause undefined performance impact to code and data fetches due to MSR space re-indexing into code/data
masks when CDP is enabled.
When reading the IA32_PQR_ASSOC register the currently programmed COS on the core will be returned.
When reading an IA32_resourceType_MASK_n register the current capacity bit mask for COS 'n' will be returned.
As noted previously, software should minimize migrations of COS across logical processors (across threads or
cores), as a reduction in the accuracy of the Cache Allocation feature may result if COS are migrated frequently.
This is aligned with the industry standard practice of minimizing unnecessary thread migrations across processor
cores in order to avoid excessive time spent warming up processor caches after a migration. In general, for best
performance, minimize thread migration and COS migration across processor logical threads and processor cores.
17.17.5.2 Cache Allocation Technology Operation With Power Saving Features
Note that the Cache Allocation Technology feature cannot be used to enforce cache coherency, and that some
advanced power management features such as C-states which may shrink or power off various caches within the
system may interfere with CAT hints - in such cases the CAT bitmasks are ignored and the other features take
precedence. If the highest possible level of CAT differentiation or determinism is required, disable any powersaving features which shrink the caches or power off caches. The details of the power management interfaces are
typically implementation-specific, but can be found at Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C.
If software requires differentiation between threads but not absolute determinism then in many cases it is possible
to leave power-saving cache shrink features enabled, which can provide substantial power savings and increase
battery life in mobile platforms. In such cases when the caches are powered off (e.g., package C-states) the entire
cache of a portion thereof may be powered off. Upon resuming an active state any new incoming data to the cache
will be filled subject to the cache capacity bitmasks. Any data in the cache prior to the cache shrink or power off
may have been flushed to memory during the process of entering the idle state, however, and is not guaranteed to
remain in the cache. If differentiation between threads is the goal of system software then this model allows
substantial power savings while continuing to deliver performance differentiation. If system software needs
optimal determinism then power saving modes which flush portions of the caches and power them off should be
disabled.
NOTE
IA32_PQR_ASSOC is saved and restored across C6 entry/exit. Similarly, the mask register contents
are saved across package C-state entry/exit and are not lost.
17.17.5.3 Cache Allocation Technology Operation with Other Operating Modes
The states in IA32_PQR_ASSOC and mask registers are unmodified across an SMI delivery. Thus, the execution of
SMM handler code can interact with the Cache Allocation Technology resource and manifest some degree of nondeterminism to the non-SMM software stack. An SMM handler may also perform certain system-level or power
management practices that affect CAT operation.
It is possible for an SMM handler to minimize the impact on data determinism in the cache by reserving a COS with
a dedicated partition in the cache. Such an SMM handler can switch to the dedicated COS immediately upon
entering SMM, and switching back to the previously running COS upon exit.
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17.17.5.4 Associating Threads with CAT/CDP Classes of Service
Threads are associated with Classes of Service (CLOS) via the per-logical-processor IA32_PQR_ASSOC MSR. The
same COS concept applies to both CAT and CDP (for instance, COS[5] means the same thing whether CAT or CDP
is in use, and the COS has associated resource usage constraint attributes including cache capacity masks). The
mapping of COS to mask MSRs does change when CDP is enabled, according to the following guidelines:
•
In CAT-only Mode - one set of bitmasks in one mask MSR control both code and data.
— Each COS number map 1:1 with a capacity mask on the applicable resource (e.g., L3 cache).
•
When CDP is enabled,
— Two mask sets exist for each COS number, one for code, one for data.
— Masks for code/data are interleaved in the MSR address space (see Table 17-19).
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CHAPTER 18
PERFORMANCE MONITORING
Intel 64 and IA-32 architectures provide facilities for monitoring performance via a PMU (Performance Monitoring
Unit).
18.1
PERFORMANCE MONITORING OVERVIEW
Performance monitoring was introduced in the Pentium processor with a set of model-specific performance-monitoring counter MSRs. These counters permit selection of processor performance parameters to be monitored and
measured. The information obtained from these counters can be used for tuning system and compiler performance.
In Intel P6 family of processors, the performance monitoring mechanism was enhanced to permit a wider selection
of events to be monitored and to allow greater control events to be monitored. Next, Intel processors based on
Intel NetBurst microarchitecture introduced a distributed style of performance monitoring mechanism and performance events.
The performance monitoring mechanisms and performance events defined for the Pentium, P6 family, and Intel
processors based on Intel NetBurst microarchitecture are not architectural. They are all model specific (not
compatible among processor families). Intel Core Solo and Intel Core Duo processors support a set of architectural
performance events and a set of non-architectural performance events. Newer Intel processor generations support
enhanced architectural performance events and non-architectural performance events.
Starting with Intel Core Solo and Intel Core Duo processors, there are two classes of performance monitoring capabilities. The first class supports events for monitoring performance using counting or interrupt-based event
sampling usage. These events are non-architectural and vary from one processor model to another. They are
similar to those available in Pentium M processors. These non-architectural performance monitoring events are
specific to the microarchitecture and may change with enhancements. They are discussed in Section 18.3, “Performance Monitoring (Intel® Core™ Solo and Intel® Core™ Duo Processors).” Non-architectural events for a given
microarchitecture cannot be enumerated using CPUID; and they are listed in Chapter 19, “PerformanceMonitoring Events.”
The second class of performance monitoring capabilities is referred to as architectural performance monitoring.
This class supports the same counting and Interrupt-based event sampling usages, with a smaller set of available
events. The visible behavior of architectural performance events is consistent across processor implementations.
Availability of architectural performance monitoring capabilities is enumerated using the CPUID.0AH. These events
are discussed in Section 18.2.
See also:
— Section 18.2, “Architectural Performance Monitoring”
— Section 18.3, “Performance Monitoring (Intel® Core™ Solo and Intel® Core™ Duo Processors)”
— Section 18.4, “Performance Monitoring (Processors Based on Intel® Core™ Microarchitecture)”
— Section 18.5, “Performance Monitoring (45 nm and 32 nm Intel® Atom™ Processors)”
— Section 18.6, “Performance Monitoring for Silvermont Microarchitecture”
— Section 18.7, “Performance Monitoring for Goldmont Microarchitecture”
— Section 18.8, “Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name
Nehalem”
— Section 18.8.4, “Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name
Westmere”
— Section 18.9, “Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Sandy
Bridge”
— Section 18.9.8, “Intel® Xeon® Processor E5 Family Uncore Performance Monitoring Facility”
Vol. 3B 18-1
PERFORMANCE MONITORING
— Section 18.10, “3rd Generation Intel® Core™ Processor Performance Monitoring Facility”
— Section 18.11, “4th Generation Intel® Core™ Processor Performance Monitoring Facility”
— Section 18.12, “5th Generation Intel® Core™ Processor and Intel® Core™ M Processor Performance
Monitoring Facility”
— Section 18.13, “6th Generation Intel® Core™ Processor and 7th Generation Intel® Core™ Processor
Performance Monitoring Facility”
— Section 18.14, “Intel® Xeon Phi™ Processor 7200/5200/3200 Performance Monitoring”
— Section 18.15, “Performance Monitoring (Processors Based on Intel NetBurst® Microarchitecture)”
— Section 18.16, “Performance Monitoring and Intel Hyper-Threading Technology in Processors Based on Intel
NetBurst® Microarchitecture”
— Section 18.20, “Performance Monitoring and Dual-Core Technology”
— Section 18.21, “Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache”
— Section 18.23, “Performance Monitoring (P6 Family Processor)”
— Section 18.24, “Performance Monitoring (Pentium Processors)”
18.2
ARCHITECTURAL PERFORMANCE MONITORING
Performance monitoring events are architectural when they behave consistently across microarchitectures. Intel
Core Solo and Intel Core Duo processors introduced architectural performance monitoring. The feature provides a
mechanism for software to enumerate performance events and provides configuration and counting facilities for
events.
Architectural performance monitoring does allow for enhancement across processor implementations. The
CPUID.0AH leaf provides version ID for each enhancement. Intel Core Solo and Intel Core Duo processors support
base level functionality identified by version ID of 1. Processors based on Intel Core microarchitecture support, at
a minimum, the base level functionality of architectural performance monitoring. Intel Core 2 Duo processor T
7700 and newer processors based on Intel Core microarchitecture support both the base level functionality and
enhanced architectural performance monitoring identified by version ID of 2.
45 nm and 32 nm Intel Atom processors and Intel Atom processors based on the Silvermont microarchitecture
support the functionality provided by versionID 1, 2, and 3; CPUID.0AH:EAX[7:0] reports versionID = 3 to indicate
the aggregate of architectural performance monitoring capabilities. Intel Atom processors based on the Airmont
microarchitecture support the same performance monitoring capabilities as those based on the Silvermont microarchitecture.
Intel Core processors and related Intel Xeon processor families based on the Nehalem through Broadwell microarchitectures support version ID 1, 2, and 3. Intel processors based on the Skylake and Kaby Lake microarchitectures
support versionID 4.
Next generation Intel Atom processors are based on the Goldmont microarchitecture. Intel processors based on the
Goldmont microarchitecture support versionID 4.
18.2.1
Architectural Performance Monitoring Version 1
Configuring an architectural performance monitoring event involves programming performance event select registers. There are a finite number of performance event select MSRs (IA32_PERFEVTSELx MSRs). The result of a
performance monitoring event is reported in a performance monitoring counter (IA32_PMCx MSR). Performance
monitoring counters are paired with performance monitoring select registers.
Performance monitoring select registers and counters are architectural in the following respects:
•
•
•
Bit field layout of IA32_PERFEVTSELx is consistent across microarchitectures.
Addresses of IA32_PERFEVTSELx MSRs remain the same across microarchitectures.
Addresses of IA32_PMC MSRs remain the same across microarchitectures.
18-2 Vol. 3B
PERFORMANCE MONITORING
•
Each logical processor has its own set of IA32_PERFEVTSELx and IA32_PMCx MSRs. Configuration facilities and
counters are not shared between logical processors sharing a processor core.
Architectural performance monitoring provides a CPUID mechanism for enumerating the following information:
•
Number of performance monitoring counters available in a logical processor (each IA32_PERFEVTSELx MSR is
paired to the corresponding IA32_PMCx MSR)
•
•
Number of bits supported in each IA32_PMCx
Number of architectural performance monitoring events supported in a logical processor
Software can use CPUID to discover architectural performance monitoring availability (CPUID.0AH). The architectural performance monitoring leaf provides an identifier corresponding to the version number of architectural
performance monitoring available in the processor.
The version identifier is retrieved by querying CPUID.0AH:EAX[bits 7:0] (see Chapter 3, “Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). If the version identifier is greater than zero, architectural performance monitoring capability is supported. Software queries the
CPUID.0AH for the version identifier first; it then analyzes the value returned in CPUID.0AH.EAX, CPUID.0AH.EBX
to determine the facilities available.
In the initial implementation of architectural performance monitoring; software can determine how many
IA32_PERFEVTSELx/ IA32_PMCx MSR pairs are supported per core, the bit-width of PMC, and the number of architectural performance monitoring events available.
18.2.1.1
Architectural Performance Monitoring Version 1 Facilities
Architectural performance monitoring facilities include a set of performance monitoring counters and performance
event select registers. These MSRs have the following properties:
•
IA32_PMCx MSRs start at address 0C1H and occupy a contiguous block of MSR address space; the number of
MSRs per logical processor is reported using CPUID.0AH:EAX[15:8].
•
IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous block of MSR address space. Each
performance event select register is paired with a corresponding performance counter in the 0C1H address
block.
•
The bit width of an IA32_PMCx MSR is reported using the CPUID.0AH:EAX[23:16]. This the number of valid bits
for read operation. On write operations, the lower-order 32 bits of the MSR may be written with any value, and
the high-order bits are sign-extended from the value of bit 31.
•
Bit field layout of IA32_PERFEVTSELx MSRs is defined architecturally.
See Figure 18-1 for the bit field layout of IA32_PERFEVTSELx MSRs. The bit fields are:
•
Event select field (bits 0 through 7) — Selects the event logic unit used to detect microarchitectural
conditions (see Table 18-1, for a list of architectural events and their 8-bit codes). The set of values for this field
is defined architecturally; each value corresponds to an event logic unit for use with an architectural
performance event. The number of architectural events is queried using CPUID.0AH:EAX. A processor may
support only a subset of pre-defined values.
63
31
24 23 22 21 20 19 18 17 16 15
Counter Mask I E
N
(CMASK)
V N
INV—Invert counter mask
EN—Enable counters
INT—APIC interrupt enable
PC—Pin control
E—Edge detect
OS—Operating system mode
USR—User Mode
0
8 7
I
U
N P E O S Unit Mask (UMASK)
S R
T C
Event Select
Reserved
Figure 18-1. Layout of IA32_PERFEVTSELx MSRs
Vol. 3B 18-3
PERFORMANCE MONITORING
•
Unit mask (UMASK) field (bits 8 through 15) — These bits qualify the condition that the selected event
logic unit detects. Valid UMASK values for each event logic unit are specific to the unit. For each architectural
performance event, its corresponding UMASK value defines a specific microarchitectural condition.
A pre-defined microarchitectural condition associated with an architectural event may not be applicable to a
given processor. The processor then reports only a subset of pre-defined architectural events. Pre-defined
architectural events are listed in Table 18-1; support for pre-defined architectural events is enumerated using
CPUID.0AH:EBX. Architectural performance events available in the initial implementation are listed in Table
19-1.
•
USR (user mode) flag (bit 16) — Specifies that the selected microarchitectural condition is counted when
the logical processor is operating at privilege levels 1, 2 or 3. This flag can be used with the OS flag.
•
OS (operating system mode) flag (bit 17) — Specifies that the selected microarchitectural condition is
counted when the logical processor is operating at privilege level 0. This flag can be used with the USR flag.
•
E (edge detect) flag (bit 18) — Enables (when set) edge detection of the selected microarchitectural
condition. The logical processor counts the number of deasserted to asserted transitions for any condition that
can be expressed by the other fields. The mechanism does not permit back-to-back assertions to be distinguished.
This mechanism allows software to measure not only the fraction of time spent in a particular state, but also the
average length of time spent in such a state (for example, the time spent waiting for an interrupt to be
serviced).
•
PC (pin control) flag (bit 19) — When set, the logical processor toggles the PMi pins and increments the
counter when performance-monitoring events occur; when clear, the processor toggles the PMi pins when the
counter overflows. The toggling of a pin is defined as assertion of the pin for a single bus clock followed by
deassertion.
•
INT (APIC interrupt enable) flag (bit 20) — When set, the logical processor generates an exception
through its local APIC on counter overflow.
•
EN (Enable Counters) Flag (bit 22) — When set, performance counting is enabled in the corresponding
performance-monitoring counter; when clear, the corresponding counter is disabled. The event logic unit for a
UMASK must be disabled by setting IA32_PERFEVTSELx[bit 22] = 0, before writing to IA32_PMCx.
•
INV (invert) flag (bit 23) — When set, inverts the counter-mask (CMASK) comparison, so that both greater
than or equal to and less than comparisons can be made (0: greater than or equal; 1: less than). Note if
counter-mask is programmed to zero, INV flag is ignored.
•
Counter mask (CMASK) field (bits 24 through 31) — When this field is not zero, a logical processor
compares this mask to the events count of the detected microarchitectural condition during a single cycle. If
the event count is greater than or equal to this mask, the counter is incremented by one. Otherwise the counter
is not incremented.
This mask is intended for software to characterize microarchitectural conditions that can count multiple
occurrences per cycle (for example, two or more instructions retired per clock; or bus queue occupations). If
the counter-mask field is 0, then the counter is incremented each cycle by the event count associated with
multiple occurrences.
18.2.1.2
Pre-defined Architectural Performance Events
Table 18-1 lists architecturally defined events.
Table 18-1. UMask and Event Select Encodings for Pre-Defined Architectural Performance Events
Bit Position
CPUID.AH.EBX
Event Name
UMask
Event Select
0
UnHalted Core Cycles
00H
3CH
1
Instruction Retired
00H
C0H
2
UnHalted Reference Cycles
01H
3CH
3
LLC Reference
4FH
2EH
4
LLC Misses
41H
2EH
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PERFORMANCE MONITORING
Table 18-1. UMask and Event Select Encodings for Pre-Defined Architectural Performance Events
5
Branch Instruction Retired
00H
C4H
6
Branch Misses Retired
00H
C5H
A processor that supports architectural performance monitoring may not support all the predefined architectural
performance events (Table 18-1). The non-zero bits in CPUID.0AH:EBX indicate the events that are not available.
The behavior of each architectural performance event is expected to be consistent on all processors that support
that event. Minor variations between microarchitectures are noted below:
•
UnHalted Core Cycles — Event select 3CH, Umask 00H
This event counts core clock cycles when the clock signal on a specific core is running (not halted). The counter
does not advance in the following conditions:
— an ACPI C-state other than C0 for normal operation
— HLT
— STPCLK# pin asserted
— being throttled by TM1
— during the frequency switching phase of a performance state transition (see Chapter 14, “Power and
Thermal Management”)
The performance counter for this event counts across performance state transitions using different core clock
frequencies
•
Instructions Retired — Event select C0H, Umask 00H
This event counts the number of instructions at retirement. For instructions that consist of multiple micro-ops,
this event counts the retirement of the last micro-op of the instruction. An instruction with a REP prefix counts
as one instruction (not per iteration). Faults before the retirement of the last micro-op of a multi-ops instruction
are not counted.
This event does not increment under VM-exit conditions. Counters continue counting during hardware
interrupts, traps, and inside interrupt handlers.
•
UnHalted Reference Cycles — Event select 3CH, Umask 01H
This event counts reference clock cycles at a fixed frequency while the clock signal on the core is running. The
event counts at a fixed frequency, irrespective of core frequency changes due to performance state transitions.
Processors may implement this behavior differently. Current implementations use the core crystal clock, TSC
or the bus clock. Because the rate may differ between implementations, software should calibrate it to a time
source with known frequency.
•
Last Level Cache References — Event select 2EH, Umask 4FH
This event counts requests originating from the core that reference a cache line in the last level cache. The
event count includes speculation and cache line fills due to the first-level cache hardware prefetcher, but may
exclude cache line fills due to other hardware-prefetchers.
Because cache hierarchy, cache sizes and other implementation-specific characteristics; value comparison to
estimate performance differences is not recommended.
•
Last Level Cache Misses — Event select 2EH, Umask 41H
This event counts each cache miss condition for references to the last level cache. The event count may include
speculation and cache line fills due to the first-level cache hardware prefetcher, but may exclude cache line fills
due to other hardware-prefetchers.
Because cache hierarchy, cache sizes and other implementation-specific characteristics; value comparison to
estimate performance differences is not recommended.
•
Branch Instructions Retired — Event select C4H, Umask 00H
This event counts branch instructions at retirement. It counts the retirement of the last micro-op of a branch
instruction.
•
All Branch Mispredict Retired — Event select C5H, Umask 00H
Vol. 3B 18-5
PERFORMANCE MONITORING
This event counts mispredicted branch instructions at retirement. It counts the retirement of the last micro-op
of a branch instruction in the architectural path of execution and experienced misprediction in the branch
prediction hardware.
Branch prediction hardware is implementation-specific across microarchitectures; value comparison to
estimate performance differences is not recommended.
NOTE
Programming decisions or software precisians on functionality should not be based on the event
values or dependent on the existence of performance monitoring events.
18.2.2
Architectural Performance Monitoring Version 2
The enhanced features provided by architectural performance monitoring version 2 include the following:
•
Fixed-function performance counter register and associated control register — Three of the architectural performance events are counted using three fixed-function MSRs (IA32_FIXED_CTR0 through
IA32_FIXED_CTR2). Each of the fixed-function PMC can count only one architectural performance event.
Configuring the fixed-function PMCs is done by writing to bit fields in the MSR (IA32_FIXED_CTR_CTRL) located
at address 38DH. Unlike configuring performance events for general-purpose PMCs (IA32_PMCx) via UMASK
field in (IA32_PERFEVTSELx), configuring, programming IA32_FIXED_CTR_CTRL for fixed-function PMCs do
not require any UMASK.
•
Simplified event programming — Most frequent operation in programming performance events are
enabling/disabling event counting and checking the status of counter overflows. Architectural performance
event version 2 provides three architectural MSRs:
— IA32_PERF_GLOBAL_CTRL allows software to enable/disable event counting of all or any combination of
fixed-function PMCs (IA32_FIXED_CTRx) or any general-purpose PMCs via a single WRMSR.
— IA32_PERF_GLOBAL_STATUS allows software to query counter overflow conditions on any combination of
fixed-function PMCs or general-purpose PMCs via a single RDMSR.
— IA32_PERF_GLOBAL_OVF_CTRL allows software to clear counter overflow conditions on any combination of
fixed-function PMCs or general-purpose PMCs via a single WRMSR.
•
PMI Overhead Mitigation — Architectural performance monitoring version 2 introduces two bit field interface
in IA32_DEBUGCTL for PMI service routine to accumulate performance monitoring data and LBR records with
reduced perturbation from servicing the PMI. The two bit fields are:
— IA32_DEBUGCTL.Freeze_LBR_On_PMI(bit 11). In architectural performance monitoring version 2, only the
legacy semantic behavior is supported. See Section 17.4.7 for details of the legacy Freeze LBRs on PMI
control.
— IA32_DEBUGCTL.Freeze_PerfMon_On_PMI(bit 12). In architectural performance monitoring version 2, only
the legacy semantic behavior is supported. See Section 17.4.7 for details of the legacy Freeze LBRs on PMI
control.
The facilities provided by architectural performance monitoring version 2 can be queried from CPUID leaf 0AH by
examining the content of register EDX:
•
Bits 0 through 4 of CPUID.0AH.EDX indicates the number of fixed-function performance counters available per
core,
•
Bits 5 through 12 of CPUID.0AH.EDX indicates the bit-width of fixed-function performance counters. Bits
beyond the width of the fixed-function counter are reserved and must be written as zeros.
NOTE
Early generation of processors based on Intel Core microarchitecture may report in
CPUID.0AH:EDX of support for version 2 but indicating incorrect information of version 2 facilities.
The IA32_FIXED_CTR_CTRL MSR include multiple sets of 4-bit field, each 4 bit field controls the operation of a
fixed-function performance counter. Figure 18-2 shows the layout of 4-bit controls for each fixed-function PMC.
Two sub-fields are currently defined within each control. The definitions of the bit fields are:
18-6 Vol. 3B
PERFORMANCE MONITORING
63
12 11
9 8 7
P
M
I
P
M
I
E
N
5 43 2 1 0
E
N
P
M
I
E
N
Cntr2 — Controls for IA32_FIXED_CTR2
Cntr1 — Controls for IA32_FIXED_CTR1
PMI — Enable PMI on overflow
Cntr0 — Controls for IA32_FIXED_CTR0
ENABLE — 0: disable; 1: OS; 2: User; 3: All ring levels
Reserved
Figure 18-2. Layout of IA32_FIXED_CTR_CTRL MSR
•
Enable field (lowest 2 bits within each 4-bit control) — When bit 0 is set, performance counting is
enabled in the corresponding fixed-function performance counter to increment while the target condition
associated with the architecture performance event occurred at ring 0. When bit 1 is set, performance counting
is enabled in the corresponding fixed-function performance counter to increment while the target condition
associated with the architecture performance event occurred at ring greater than 0. Writing 0 to both bits stops
the performance counter. Writing a value of 11B enables the counter to increment irrespective of privilege
levels.
•
PMI field (the fourth bit within each 4-bit control) — When set, the logical processor generates an
exception through its local APIC on overflow condition of the respective fixed-function counter.
IA32_PERF_GLOBAL_CTRL MSR provides single-bit controls to enable counting of each performance counter.
Figure 18-3 shows the layout of IA32_PERF_GLOBAL_CTRL. Each enable bit in IA32_PERF_GLOBAL_CTRL is
AND’ed with the enable bits for all privilege levels in the respective IA32_PERFEVTSELx or
IA32_PERF_FIXED_CTR_CTRL MSRs to start/stop the counting of respective counters. Counting is enabled if the
AND’ed results is true; counting is disabled when the result is false.
63
35 34 33 32 31
2 10
IA32_FIXED_CTR2 enable
IA32_FIXED_CTR1 enable
IA32_FIXED_CTR0 enable
IA32_PMC1 enable
IA32_PMC0 enable
Reserved
Figure 18-3. Layout of IA32_PERF_GLOBAL_CTRL MSR
The behavior of the fixed function performance counters supported by architectural performance version 2 is
expected to be consistent on all processors that support those counters, and is defined as follows.
Vol. 3B 18-7
PERFORMANCE MONITORING
Table 18-2. Association of Fixed-Function Performance Counters with Architectural Performance Events
Fixed-Function Performance Counter
Address
Event Mask Mnemonic
Description
MSR_PERF_FIXED_CTR0/IA32_FIXED_CTR0
309H
INST_RETIRED.ANY
This event counts the number of
instructions that retire execution. For
instructions that consist of multiple
uops, this event counts the
retirement of the last uop of the
instruction. The counter continues
counting during hardware interrupts,
traps, and in-side interrupt handlers.
MSR_PERF_FIXED_CTR1//IA32_FIXED_CTR1
30AH
CPU_CLK_UNHALTED.THREAD
The CPU_CLK_UNHALTED.THREAD
event counts the number of core
cycles while the logical processor is
not in a halt state.
CPU_CLK_UNHALTED.CORE
If there is only one logical processor
in a processor core,
CPU_CLK_UNHALTED.CORE counts
the unhalted cycles of the processor
core.
The core frequency may change from
time to time due to transitions
associated with Enhanced Intel
SpeedStep Technology or TM2. For
this reason this event may have a
changing ratio with regards to time.
MSR_PERF_FIXED_CTR2//IA32_FIXED_CTR2
30BH
CPU_CLK_UNHALTED.REF_TSC
This event counts the number of
reference cycles at the TSC rate
when the core is not in a halt state
and not in a TM stop-clock state. The
core enters the halt state when it is
running the HLT instruction or the
MWAIT instruction. This event is not
affected by core frequency changes
(e.g., P states) but counts at the same
frequency as the time stamp counter.
This event can approximate elapsed
time while the core was not in a halt
state and not in a TM stopclock state.
IA32_PERF_GLOBAL_STATUS MSR provides single-bit status for software to query the overflow condition of each
performance counter. IA32_PERF_GLOBAL_STATUS[bit 62] indicates overflow conditions of the DS area data
buffer. IA32_PERF_GLOBAL_STATUS[bit 63] provides a CondChgd bit to indicate changes to the state of performance monitoring hardware. Figure 18-4 shows the layout of IA32_PERF_GLOBAL_STATUS. A value of 1 in bits 0,
1, 32 through 34 indicates a counter overflow condition has occurred in the associated counter.
When a performance counter is configured for PEBS, overflow condition in the counter generates a performancemonitoring interrupt signaling a PEBS event. On a PEBS event, the processor stores data records into the buffer
area (see Section 18.15.5), clears the counter overflow status., and sets the “OvfBuffer” bit in
IA32_PERF_GLOBAL_STATUS.
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PERFORMANCE MONITORING
63 62
35 34 33 32 31
2 10
CondChgd
OvfDSBuffer
IA32_FIXED_CTR2 Overflow
IA32_FIXED_CTR1 Overflow
IA32_FIXED_CTR0 Overflow
IA32_PMC1 Overflow
IA32_PMC0 Overflow
Reserved
Figure 18-4. Layout of IA32_PERF_GLOBAL_STATUS MSR
IA32_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow indicator(s) of any general-purpose or fixedfunction counters via a single WRMSR. Software should clear overflow indications when
•
•
•
Setting up new values in the event select and/or UMASK field for counting or interrupt-based event sampling.
Reloading counter values to continue collecting next sample.
Disabling event counting or interrupt-based event sampling.
The layout of IA32_PERF_GLOBAL_OVF_CTL is shown in Figure 18-5.
63 62
35 34 33 32 31
2 10
ClrCondChgd
ClrOvfDSBuffer
IA32_FIXED_CTR2 ClrOverflow
IA32_FIXED_CTR1 ClrOverflow
IA32_FIXED_CTR0 ClrOverflow
IA32_PMC1 ClrOverflow
IA32_PMC0 ClrOverflow
Reserved
Figure 18-5. Layout of IA32_PERF_GLOBAL_OVF_CTRL MSR
18.2.3
Architectural Performance Monitoring Version 3
Processors supporting architectural performance monitoring version 3 also supports version 1 and 2, as well as
capability enumerated by CPUID leaf 0AH. Specifically, version 3 provides the following enhancement in performance monitoring facilities if a processor core comprising of more than one logical processor, i.e. a processor core
supporting Intel Hyper-Threading Technology or simultaneous multi-threading capability:
•
Anythread counting for processor core supporting two or more logical processors. The interface that supports
AnyThread counting include:
— Each IA32_PERFEVTSELx MSR (starting at MSR address 186H) support the bit field layout defined in Figure
18-6.
Vol. 3B 18-9
PERFORMANCE MONITORING
63
31
24 23 22 21 20 19 18 17 16 15
0
8 7
A I
U
Counter Mask I E N
N
N P E O S Unit Mask (UMASK)
(CMASK)
S R
V N Y T C
INV—Invert counter mask
EN—Enable counters
ANY—Any Thread
INT—APIC interrupt enable
PC—Pin control
E—Edge detect
OS—Operating system mode
USR—User Mode
Event Select
Reserved
Figure 18-6. Layout of IA32_PERFEVTSELx MSRs Supporting Architectural Performance Monitoring Version 3
Bit 21 (AnyThread) of IA32_PERFEVTSELx is supported in architectural performance monitoring version 3 for
processor core comprising of two or more logical processors. When set to 1, it enables counting the associated
event conditions (including matching the thread’s CPL with the OS/USR setting of IA32_PERFEVTSELx)
occurring across all logical processors sharing a processor core. When bit 21 is 0, the counter only increments
the associated event conditions (including matching the thread’s CPL with the OS/USR setting of
IA32_PERFEVTSELx) occurring in the logical processor which programmed the IA32_PERFEVTSELx MSR.
— Each fixed-function performance counter IA32_FIXED_CTRx (starting at MSR address 309H) is configured
by a 4-bit control block in the IA32_PERF_FIXED_CTR_CTRL MSR. The control block also allow threadspecificity configuration using an AnyThread bit. The layout of IA32_PERF_FIXED_CTR_CTRL MSR is shown.
63
12 11
P A
M N
I Y
9 8 7
E
N
P A
M N
I Y
5 43 2 1 0
E
N
P A
M N
I Y
E
N
Cntr2 — Controls for IA32_FIXED_CTR2
Cntr1 — Controls for IA32_FIXED_CTR1
PMI — Enable PMI on overflow on IA32_FIXED_CTR0
AnyThread — AnyThread for IA32_FIXED_CTR0
ENABLE — IA32_FIXED_CTR0. 0: disable; 1: OS; 2: User; 3: All ring levels
Reserved
Figure 18-7. IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performance Monitoring Version 3
Each control block for a fixed-function performance counter provides a AnyThread (bit position 2 + 4*N, N=
0, 1, etc.) bit. When set to 1, it enables counting the associated event conditions (including matching the
thread’s CPL with the ENABLE setting of the corresponding control block of IA32_PERF_FIXED_CTR_CTRL)
occurring across all logical processors sharing a processor core. When an AnyThread bit is 0 in
IA32_PERF_FIXED_CTR_CTRL, the corresponding fixed counter only increments the associated event
conditions occurring in the logical processor which programmed the IA32_PERF_FIXED_CTR_CTRL MSR.
•
The IA32_PERF_GLOBAL_CTRL, IA32_PERF_GLOBAL_STATUS, IA32_PERF_GLOBAL_OVF_CTRL MSRs provide
single-bit controls/status for each general-purpose and fixed-function performance counter. Figure 18-8 and
Figure 18-9 show the layout of these MSRs for N general-purpose performance counters (where N is reported
by CPUID.0AH:EAX[15:8]) and three fixed-function counters.
Note: The number of general-purpose performance monitoring counters (i.e. N in Figure 18-9) can vary across
processor generations within a processor family, across processor families, or could be different depending on
the configuration chosen at boot time in the BIOS regarding Intel Hyper Threading Technology, (e.g. N=2 for 45
nm Intel Atom processors; N =4 for processors based on the Nehalem microarchitecture; for processors based
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PERFORMANCE MONITORING
on the Sandy Bridge microarchitecture, N = 4 if Intel Hyper Threading Technology is active and N=8 if not
active).
Global Enable Controls IA32_PERF_GLOBAL_CTRL
35 34 33 32 31
63
N .. .. 1 0
Reserved
IA32_FIXED_CTR2 enable
IA32_FIXED_CTR1 enable
IA32_FIXED_CTR0 enable
IA32_PMC(N-1) enable
.................... enable
IA32_PMC1 enable
IA32_PMC0 enable
Figure 18-8. Layout of Global Performance Monitoring Control MSR
63 62 61
Global Overflow Status IA32_PERF_GLOBAL_STATUS
35 34 33 32 31
CondChgd
OvfDSBuffer
OvfUncore
IA32_FIXED_CTR2 Overflow
IA32_FIXED_CTR1 Overflow
IA32_FIXED_CTR0 Overflow
IA32_PMC1 Overflow
IA32_PMC0 Overflow
63 62
N .. .. 1 0
IA32_PMC(N-1) Overflow
...................... Overflow
Global Overflow Status IA32_PERF_GLOBAL_OVF_CTRL
35 34 33 32 31
ClrCondChgd
ClrOvfDSBuffer
ClrOvfUncore
IA32_FIXED_CTR2 ClrOverflow
IA32_FIXED_CTR1 ClrOverflow
IA32_FIXED_CTR0 ClrOverflow
IA32_PMC1 ClrOverflow
IA32_PMC0 ClrOverflow
N .. .. 1 0
IA32_PMC(N-1) ClrOverflow
........................ ClrOverflow
Figure 18-9. Global Performance Monitoring Overflow Status and Control MSRs
18.2.3.1
AnyThread Counting and Software Evolution
The motivation for characterizing software workload over multiple software threads running on multiple logical
processors of the same processor core originates from a time earlier than the introduction of the AnyThread interface in IA32_PERFEVTSELx and IA32_FIXED_CTR_CTRL. While Anythread counting provides some benefits in
simple software environments of an earlier era, the evolution contemporary software environments introduce
certain concepts and pre-requisites that AnyThread counting does not comply with.
Vol. 3B 18-11
PERFORMANCE MONITORING
One example is the proliferation of software environments that support multiple virtual machines (VM) under VMX
(see Chapter 23, “Introduction to Virtual-Machine Extensions”) where each VM represents a domain separated
from one another.
A Virtual Machine Monitor (VMM) that manages the VMs may allow individual VM to employ performance monitoring facilities to profiles the performance characteristics of a workload. The use of the Anythread interface in
IA32_PERFEVTSELx and IA32_FIXED_CTR_CTRL is discouraged with software environments supporting virtualization or requiring domain separation.
Specifically, Intel recommends VMM:
•
configure the MSR bitmap to cause VM-exits for WRMSR to IA32_PERFEVTSELx and IA32_FIXED_CTR_CTRL in
VMX non-Root operation (see CHAPTER 24 for additional information),
•
clear the AnyThread bit of IA32_PERFEVTSELx and IA32_FIXED_CTR_CTRL in the MSR-load lists for VM exits
and VM entries (see CHAPTER 24, CHAPTER 26, and CHAPTER 27).
Even when operating in simpler legacy software environments which might not emphasize the pre-requisites of a
virtualized software environment, the use of the AnyThread interface should be moderated and follow any eventspecific guidance where explicitly noted (see relevant sections of Chapter 19, “Performance Monitoring Events”).
18.2.4
Architectural Performance Monitoring Version 4
Processors supporting architectural performance monitoring version 4 also supports version 1, 2, and 3, as well as
capability enumerated by CPUID leaf 0AH. Version 4 introduced a streamlined PMI overhead mitigation interface
that replaces the legacy semantic behavior but retains the same control interface in
IA32_DEBUGCTL.Freeze_LBRs_On_PMI and Freeze_PerfMon_On_PMI. Specifically version 4 provides the following
enhancement:
•
•
New indicators (LBR_FRZ, CTR_FRZ) in IA32_PERF_GLOBAL_STATUS, see Section 18.2.4.1.
•
Fine-grain separation of control interface to manage overflow/status of IA32_PERF_GLOBAL_STATUS and readonly performance counter enabling interface in IA32_PERF_GLOBAL_STATUS: see Section 18.2.4.2.
•
Performance monitoring resource in-use MSR to facilitate cooperative sharing protocol between perfmonmanaging privilege agents.
Streamlined Freeze/PMI Overhead management interfaces to use IA32_DEBUGCTL.Freeze_LBRs_On_PMI and
IA32_DEBUGCTL.Freeze_PerfMon_On_PMI: see Section 18.2.4.1. Legacy semantics of Freeze_LBRs_On_PMI
and Freeze_PerfMon_On_PMI (applicable to version 2 and 3) are not supported with version 4 or higher.
18.2.4.1
Enhancement in IA32_PERF_GLOBAL_STATUS
The IA32_PERF_GLOBAL_STATUS MSR provides the following indicators with architectural performance monitoring
version 4:
•
IA32_PERF_GLOBAL_STATUS.LBR_FRZ[bit 58]: This bit is set due to the following conditions:
— IA32_DEBUGCTL.FREEZE_LBR_ON_PMI has been set by the profiling agent, and
— A performance counter, configured to generate PMI, has overflowed to signal a PMI. Consequently the LBR
stack is frozen.
Effectively, the IA32_PERF_GLOBAL_STATUS.LBR_FRZ bit also serve as an read-only control to enable
capturing data in the LBR stack. To enable capturing LBR records, the following expression must hold with
architectural perfmon version 4 or higher:
— (IA32_DEBUGCTL.LBR & (!IA32_PERF_GLOBAL_STATUS.LBR_FRZ) ) =1
•
IA32_PERF_GLOBAL_STATUS.CTR_FRZ[bit 59]: This bit is set due to the following conditions:
— IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI has been set by the profiling agent, and
— A performance counter, configured to generate PMI, has overflowed to signal a PMI. Consequently, all the
performance counters are frozen.
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PERFORMANCE MONITORING
Effectively, the IA32_PERF_GLOBAL_STATUS.CTR_FRZ bit also serve as an read-only control to enable
programmable performance counters and fixed counters in the core PMU. To enable counting with the
performance counters, the following expression must hold with architectural perfmon version 4 or higher:
•
(IA32_PERFEVTSELn.EN & IA32_PERF_GLOBAL_CTRL.PMCn &
(!IA32_PERF_GLOBAL_STATUS.CTR_FRZ) ) = 1 for programmable counter ‘n’, or
•
(IA32_PERF_FIXED_CRTL.ENi & IA32_PERF_GLOBAL_CTRL.FCi &
(!IA32_PERF_GLOBAL_STATUS.CTR_FRZ) ) = 1 for fixed counter ‘i’
The read-only enable interface IA32_PERF_GLOBAL_STATUS.CTR_FRZ provides a more efficient flow for a PMI
handler to use IA32_DEBUGCTL.Freeza_Perfmon_On_PMI to filter out data that may distort target workload analysis, see Table 17-3. It should be noted the IA32_PERF_GLOBAL_CTRL register continue to serve as the primary
interface to control all performance counters of the logical processor.
For example, when the Freeze-On-PMI mode is not being used, a PMI handler would be setting
IA32_PERF_GLOBAL_CTRL as the very last step to commence the overall operation after configuring the individual
counter registers, controls and PEBS facility. This does not only assure atomic monitoring but also avoids unnecessary complications (e.g. race conditions) when software attempts to change the core PMU configuration while some
counters are kept enabled.
Additionally, IA32_PERF_GLOBAL_STATUS.TraceToPAPMI[bit 55]: On processors that support Intel Processor Trace
and configured to store trace output packets to physical memory using the ToPA scheme, bit 55 is set when a PMI
occurred due to a ToPA entry memory buffer was completely filled.
IA32_PERF_GLOBAL_STATUS also provides an indicator to distinguish interaction of performance monitoring operations with other side-band activities, which apply Intel SGX on processors that support SGX (For additional information about Intel SGX, see “Intel® Software Guard Extensions Programming Reference”.):
•
IA32_PERF_GLOBAL_STATUS.ASCI[bit 60]: This bit is set when data accumulated in any of the configured
performance counters (i.e. IA32_PMCx or IA32_FIXED_CTRx) may include contributions from direct or indirect
operation of Intel SGX to protect an enclave (since the last time IA32_PERF_GLOBAL_STATUS.ASCI was
cleared).
63 62 61 60 59 58
CondChgd
OvfDSBuffer
OvfUncore
ASCI
CTR_Frz
LBR_Frz
TraceToPAPMI
IA32_FIXED_CTR2 Overflow
IA32_FIXED_CTR1 Overflow
IA32_FIXED_CTR0 Overflow
55
35 34 33 32 31
N .. .. 1 0
IA32_PMC(N-1) Overflow
...................... Overflow
IA32_PMC1 Overflow
IA32_PMC0 Overflow
Reserved
Figure 18-10. IA32_PERF_GLOBAL_STATUS MSR and Architectural Perfmon Version 4
Note, a processor’s support for IA32_PERF_GLOBAL_STATUS.TraceToPAPMI[bit 55] is enumerated as a result of
CPUID enumerated capability of Intel Processor Trace and the use of the ToPA buffer scheme. Support of
IA32_PERF_GLOBAL_STATUS.ASCI[bit 60] is enumerated by the CPUID enumeration of Intel SGX.
18.2.4.2
IA32_PERF_GLOBAL_STATUS_RESET and IA32_PERF_GLOBAL_STATUS_SET MSRS
With architectural performance monitoring version 3 and lower, clearing of the set bits in
IA32_PERF_GLOBAL_STATUS MSR by software is done via IA32_PERF_GLOBAL_OVF_CTRL MSR. Starting with
architectural performance monitoring version 4, software can manage the overflow and other indicators in
IA32_PERF_GLOBAL_STATUS using separate interfaces to set or clear individual bits.
Vol. 3B 18-13
PERFORMANCE MONITORING
The address and the architecturally-defined bits of IA32_PERF_GLOBAL_OVF_CTRL is inherited by
IA32_PERF_GLOBAL_STATUS_RESET (see Figure 18-11). Further, IA32_PERF_GLOBAL_STATUS_RESET provides
additional bit fields to clear the new indicators in IA32_PERF_GLOBAL_STATUS described in Section 18.2.4.1.
63 62 61 60 59 58
55
35 34 33 32 31
Clr CondChgd
Clr OvfDSBuffer
Clr OvfUncore
Clr ASCI
Clr CTR_Frz
Clr LBR_Frz
Clr TraceToPAPMI
Clr IA32_FIXED_CTR2 Ovf
Clr IA32_FIXED_CTR1 Ovf
Clr IA32_FIXED_CTR0 Ovf
N .. .. 1 0
Clr IA32_PMC(N-1) Ovf
Clr ...................... Ovf
Clr IA32_PMC1 Ovf
Clr IA32_PMC0 Ovf
Reserved
Figure 18-11. IA32_PERF_GLOBAL_STATUS_RESET MSR and Architectural Perfmon Version 4
The IA32_PERF_GLOBAL_STATUS_SET MSR is introduced with architectural performance monitoring version 4. It
allows software to set individual bits in IA32_PERF_GLOBAL_STATUS. The IA32_PERF_GLOBAL_STATUS_SET
interface can be used by a VMM to virtualize the state of IA32_PERF_GLOBAL_STATUS across VMs.
63 62 61 60 59 58
55
35 34 33 32 31
Set CondChgd
Set OvfDSBuffer
Set OvfUncore
Set ASCI
Set CTR_Frz
Set LBR_Frz
Set TraceToPAPMI
Set IA32_FIXED_CTR2 Ovf
Set IA32_FIXED_CTR1 Ovf
Set IA32_FIXED_CTR0 Ovf
N .. .. 1 0
Set IA32_PMC(N-1) Ovf
Set ...................... Ovf
Set IA32_PMC1 Ovf
Set IA32_PMC0 Ovf
Reserved
Figure 18-12. IA32_PERF_GLOBAL_STATUS_SET MSR and Architectural Perfmon Version 4
18.2.4.3
IA32_PERF_GLOBAL_INUSE MSR
In a contemporary software environment, multiple privileged service agents may wish to employ the processor’s
performance monitoring facilities. The IA32_MISC_ENABLE.PERFMON_AVAILABLE[bit 7] interface could not serve
the need of multiple agent adequately. A white paper, “Performance Monitoring Unit Sharing Guideline”1, proposed
a cooperative sharing protocol that is voluntary for participating software agents.
Architectural performance monitoring version 4 introduces a new MSR, IA32_PERF_GLOBAL_INUSE, that simplifies
the task of multiple cooperating agents to implement the sharing protocol.
The layout of IA32_PERF_GLOBAL_INUSE is shown in Figure 18-13.
1. Available at http://www.intel.com/sdm
18-14 Vol. 3B
PERFORMANCE MONITORING
63
35 34 33 32 31
PMI InUse
FIXED_CTR2 InUse
FIXED_CTR1 InUse
FIXED_CTR0 InUse
N .. .. 1 0
PERFEVTSEL(N-1) InUse
....................... InUse
PERFEVTSEL1 InUse
PERFEVTSEL0 InUse
N = CPUID.0AH:EAX[15:8]
Reserved
Figure 18-13. IA32_PERF_GLOBAL_INUSE MSR and Architectural Perfmon Version 4
The IA32_PERF_GLOBAL_INUSE MSR provides an “InUse” bit for each programmable performance counter and
fixed counter in the processor. Additionally, it includes an indicator if the PMI mechanism has been configured by a
profiling agent.
•
IA32_PERF_GLOBAL_INUSE.PERFEVTSEL0_InUse[bit 0]: This bit reflects the logical state of
(IA32_PERFEVTSEL0[7:0] != 0).
•
IA32_PERF_GLOBAL_INUSE.PERFEVTSEL1_InUse[bit 1]: This bit reflects the logical state of
(IA32_PERFEVTSEL1[7:0] != 0).
•
IA32_PERF_GLOBAL_INUSE.PERFEVTSEL2_InUse[bit 2]: This bit reflects the logical state of
(IA32_PERFEVTSEL2[7:0] != 0).
•
IA32_PERF_GLOBAL_INUSE.PERFEVTSELn_InUse[bit n]: This bit reflects the logical state of
(IA32_PERFEVTSELn[7:0] != 0), n < CPUID.0AH:EAX[15:8].
•
IA32_PERF_GLOBAL_INUSE.FC0_InUse[bit 32]: This bit reflects the logical state of
(IA32_FIXED_CTR_CTRL[1:0] != 0).
•
IA32_PERF_GLOBAL_INUSE.FC1_InUse[bit 33]: This bit reflects the logical state of
(IA32_FIXED_CTR_CTRL[5:4] != 0).
•
IA32_PERF_GLOBAL_INUSE.FC2_InUse[bit 34]: This bit reflects the logical state of
(IA32_FIXED_CTR_CTRL[9:8] != 0).
•
IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 32]: This bit is set if any one of the following bit is set:
— IA32_PERFEVTSELn.INT[bit 20], n < CPUID.0AH:EAX[15:8];
— IA32_FIXED_CTR_CTRL.ENi_PMI, i = 0, 1, 2;
— IA32_PEBS_ENABLES.EN_PMCi, i = 0, 1, 2, 3
18.2.5
Full-Width Writes to Performance Counter Registers
The general-purpose performance counter registers IA32_PMCx are writable via WRMSR instruction. However, the
value written into IA32_PMCx by WRMSR is the signed extended 64-bit value of the EAX[31:0] input of WRMSR.
A processor that supports full-width writes to the general-purpose performance counters enumerated by
CPUID.0AH:EAX[15:8] will set IA32_PERF_CAPABILITIES[13] to enumerate its full-width-write capability See
Figure 18-49.
If IA32_PERF_CAPABILITIES.FW_WRITE[bit 13] =1, each IA32_PMCi is accompanied by a corresponding alias
address starting at 4C1H for IA32_A_PMC0.
The bit width of the performance monitoring counters is specified in CPUID.0AH:EAX[23:16].
Vol. 3B 18-15
PERFORMANCE MONITORING
If IA32_A_PMCi is present, the 64-bit input value (EDX:EAX) of WRMSR to IA32_A_PMCi will cause IA32_PMCi to
be updated by:
COUNTERWIDTH = CPUID.0AH:EAX[23:16] bit width of the performance monitoring counter
IA32_PMCi[COUNTERWIDTH-1:32] ← EDX[COUNTERWIDTH-33:0]);
IA32_PMCi[31:0] ← EAX[31:0];
EDX[63:COUNTERWIDTH] are reserved
18.3
PERFORMANCE MONITORING (INTEL® CORE™ SOLO AND INTEL® CORE™ DUO
PROCESSORS)
In Intel Core Solo and Intel Core Duo processors, non-architectural performance monitoring events are
programmed using the same facilities (see Figure 18-1) used for architectural performance events.
Non-architectural performance events use event select values that are model-specific. Event mask (Umask) values
are also specific to event logic units. Some microarchitectural conditions detectable by a Umask value may have
specificity related to processor topology (see Section 8.6, “Detecting Hardware Multi-Threading Support and
Topology,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). As a result, the unit
mask field (for example, IA32_PERFEVTSELx[bits 15:8]) may contain sub-fields that specify topology information
of processor cores.
The sub-field layout within the Umask field may support two-bit encoding that qualifies the relationship between a
microarchitectural condition and the originating core. This data is shown in Table 18-3. The two-bit encoding for
core-specificity is only supported for a subset of Umask values (see Chapter 19, “Performance Monitoring Events”)
and for Intel Core Duo processors. Such events are referred to as core-specific events.
Table 18-3. Core Specificity Encoding within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit 15:14 Encoding
Description
11B
All cores
10B
Reserved
01B
This core
00B
Reserved
Some microarchitectural conditions allow detection specificity only at the boundary of physical processors. Some
bus events belong to this category, providing specificity between the originating physical processor (a bus agent)
versus other agents on the bus. Sub-field encoding for agent specificity is shown in Table 18-4.
Table 18-4. Agent Specificity Encoding within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit 13 Encoding
Description
0
This agent
1
Include all agents
Some microarchitectural conditions are detectable only from the originating core. In such cases, unit mask does
not support core-specificity or agent-specificity encodings. These are referred to as core-only conditions.
Some microarchitectural conditions allow detection specificity that includes or excludes the action of hardware
prefetches. A two-bit encoding may be supported to qualify hardware prefetch actions. Typically, this applies only
to some L2 or bus events. The sub-field encoding for hardware prefetch qualification is shown in Table 18-5.
18-16 Vol. 3B
PERFORMANCE MONITORING
Table 18-5. HW Prefetch Qualification Encoding within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit 13:12 Encoding
Description
11B
All inclusive
10B
Reserved
01B
Hardware prefetch only
00B
Exclude hardware prefetch
Some performance events may (a) support none of the three event-specific qualification encodings (b) may
support core-specificity and agent specificity simultaneously (c) or may support core-specificity and hardware
prefetch qualification simultaneously. Agent-specificity and hardware prefetch qualification are mutually exclusive.
In addition, some L2 events permit qualifications that distinguish cache coherent states. The sub-field definition for
cache coherency state qualification is shown in Table 18-6. If no bits in the MESI qualification sub-field are set for
an event that requires setting MESI qualification bits, the event count will not increment.
Table 18-6. MESI Qualification Definitions within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit Position 11:8
Description
Bit 11
Counts modified state
Bit 10
Counts exclusive state
Bit 9
Counts shared state
Bit 8
Counts Invalid state
18.4
PERFORMANCE MONITORING (PROCESSORS BASED ON INTEL® CORE™
MICROARCHITECTURE)
In addition to architectural performance monitoring, processors based on the Intel Core microarchitecture support
non-architectural performance monitoring events.
Architectural performance events can be collected using general-purpose performance counters. Non-architectural
performance events can be collected using general-purpose performance counters (coupled with two
IA32_PERFEVTSELx MSRs for detailed event configurations), or fixed-function performance counters (see Section
18.4.1). IA32_PERFEVTSELx MSRs are architectural; their layout is shown in Figure 18-1. Starting with Intel Core
2 processor T 7700, fixed-function performance counters and associated counter control and status MSR becomes
part of architectural performance monitoring version 2 facilities (see also Section 18.2.2).
Non-architectural performance events in processors based on Intel Core microarchitecture use event select values
that are model-specific. Valid event mask (Umask) bits are listed in Chapter 19. The UMASK field may contain subfields identical to those listed in Table 18-3, Table 18-4, Table 18-5, and Table 18-6. One or more of these subfields may apply to specific events on an event-by-event basis. Details are listed in Table 19-23 in Chapter 19,
“Performance-Monitoring Events.”
In addition, the UMASK filed may also contain a sub-field that allows detection specificity related to snoop
responses. Bits of the snoop response qualification sub-field are defined in Table 18-7.
Vol. 3B 18-17
PERFORMANCE MONITORING
Table 18-7. Bus Snoop Qualification Definitions within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit Position 11:8
Description
Bit 11
HITM response
Bit 10
Reserved
Bit 9
HIT response
Bit 8
CLEAN response
There are also non-architectural events that support qualification of different types of snoop operation. The corresponding bit field for snoop type qualification are listed in Table 18-8.
Table 18-8. Snoop Type Qualification Definitions within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit Position 9:8
Description
Bit 9
CMP2I snoops
Bit 8
CMP2S snoops
No more than one sub-field of MESI, snoop response, and snoop type qualification sub-fields can be supported in a
performance event.
NOTE
Software must write known values to the performance counters prior to enabling the counters. The
content of general-purpose counters and fixed-function counters are undefined after INIT or RESET.
18.4.1
Fixed-function Performance Counters
Processors based on Intel Core microarchitecture provide three fixed-function performance counters. Bits beyond
the width of the fixed counter are reserved and must be written as zeros. Model-specific fixed-function performance counters on processors that support Architectural Perfmon version 1 are 40 bits wide.
Each of the fixed-function counter is dedicated to count a pre-defined performance monitoring events. See Table
18-2 for details of the PMC addresses and what these events count.
Programming the fixed-function performance counters does not involve any of the IA32_PERFEVTSELx MSRs, and
does not require specifying any event masks. Instead, the MSR MSR_PERF_FIXED_CTR_CTRL provides multiple
sets of 4-bit fields; each 4-bit field controls the operation of a fixed-function performance counter (PMC). See
Figures 18-14. Two sub-fields are defined for each control. See Figure 18-14; bit fields are:
•
Enable field (low 2 bits in each 4-bit control) — When bit 0 is set, performance counting is enabled in the
corresponding fixed-function performance counter to increment when the target condition associated with the
architecture performance event occurs at ring 0.
When bit 1 is set, performance counting is enabled in the corresponding fixed-function performance counter to
increment when the target condition associated with the architecture performance event occurs at ring greater
than 0.
Writing 0 to both bits stops the performance counter. Writing 11B causes the counter to increment irrespective
of privilege levels.
18-18 Vol. 3B
PERFORMANCE MONITORING
63
12 11
9 8 7
P
M
I
P
M
I
E
N
5 43 2 1 0
E
N
P
M
I
E
N
Cntr2 — Controls for MSR_PERF_FIXED_CTR2
Cntr1 — Controls for MSR_PERF_FIXED_CTR1
PMI — Enable PMI on overflow
Cntr0 — Controls for MSR_PERF_FIXED_CTR0
ENABLE — 0: disable; 1: OS; 2: User; 3: All ring levels
Reserved
Figure 18-14. Layout of MSR_PERF_FIXED_CTR_CTRL MSR
•
PMI field (fourth bit in each 4-bit control) — When set, the logical processor generates an exception
through its local APIC on overflow condition of the respective fixed-function counter.
18.4.2
Global Counter Control Facilities
Processors based on Intel Core microarchitecture provides simplified performance counter control that simplifies
the most frequent operations in programming performance events, i.e. enabling/disabling event counting and
checking the status of counter overflows. This is done by the following three MSRs:
•
MSR_PERF_GLOBAL_CTRL enables/disables event counting for all or any combination of fixed-function PMCs
(MSR_PERF_FIXED_CTRx) or general-purpose PMCs via a single WRMSR.
•
MSR_PERF_GLOBAL_STATUS allows software to query counter overflow conditions on any combination of
fixed-function PMCs (MSR_PERF_FIXED_CTRx) or general-purpose PMCs via a single RDMSR.
•
MSR_PERF_GLOBAL_OVF_CTRL allows software to clear counter overflow conditions on any combination of
fixed-function PMCs (MSR_PERF_FIXED_CTRx) or general-purpose PMCs via a single WRMSR.
MSR_PERF_GLOBAL_CTRL MSR provides single-bit controls to enable counting in each performance counter (see
Figure 18-15). Each enable bit in MSR_PERF_GLOBAL_CTRL is AND’ed with the enable bits for all privilege levels in
the respective IA32_PERFEVTSELx or MSR_PERF_FIXED_CTR_CTRL MSRs to start/stop the counting of respective
counters. Counting is enabled if the AND’ed results is true; counting is disabled when the result is false.
63
35 34 33 32 31
2 10
FIXED_CTR2 enable
FIXED_CTR1 enable
FIXED_CTR0 enable
PMC1 enable
PMC0 enable
Reserved
Figure 18-15. Layout of MSR_PERF_GLOBAL_CTRL MSR
Vol. 3B 18-19
PERFORMANCE MONITORING
MSR_PERF_GLOBAL_STATUS MSR provides single-bit status used by software to query the overflow condition of
each performance counter. MSR_PERF_GLOBAL_STATUS[bit 62] indicates overflow conditions of the DS area data
buffer. MSR_PERF_GLOBAL_STATUS[bit 63] provides a CondChgd bit to indicate changes to the state of performance monitoring hardware (see Figure 18-16). A value of 1 in bits 34:32, 1, 0 indicates an overflow condition has
occurred in the associated counter.
63 62
35 34 33 32 31
2 10
CondChgd
OvfBuffer
FIXED_CTR2 Overflow
FIXED_CTR1 Overflow
FIXED_CTR0 Overflow
PMC1 Overflow
PMC0 Overflow
Reserved
Figure 18-16. Layout of MSR_PERF_GLOBAL_STATUS MSR
When a performance counter is configured for PEBS, an overflow condition in the counter will arm PEBS. On the
subsequent event following overflow, the processor will generate a PEBS event. On a PEBS event, the processor will
perform bounds checks based on the parameters defined in the DS Save Area (see Section 17.4.9). Upon
successful bounds checks, the processor will store the data record in the defined buffer area, clear the counter
overflow status, and reload the counter. If the bounds checks fail, the PEBS will be skipped entirely. In the event
that the PEBS buffer fills up, the processor will set the OvfBuffer bit in MSR_PERF_GLOBAL_STATUS.
MSR_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow the indicators for general-purpose or fixedfunction counters via a single WRMSR (see Figure 18-17). Clear overflow indications when:
•
•
•
Setting up new values in the event select and/or UMASK field for counting or interrupt-based event sampling.
Reloading counter values to continue collecting next sample.
Disabling event counting or interrupt-based event sampling.
63 62
35 34 33 32 31
2 10
ClrCondChgd
ClrOvfBuffer
FIXED_CTR2 ClrOverflow
FIXED_CTR1 ClrOverflow
FIXED_CTR0 ClrOverflow
PMC1 ClrOverflow
PMC0 ClrOverflow
Reserved
Figure 18-17. Layout of MSR_PERF_GLOBAL_OVF_CTRL MSR
18-20 Vol. 3B
PERFORMANCE MONITORING
18.4.3
At-Retirement Events
Many non-architectural performance events are impacted by the speculative nature of out-of-order execution. A
subset of non-architectural performance events on processors based on Intel Core microarchitecture are enhanced
with a tagging mechanism (similar to that found in Intel NetBurst® microarchitecture) that exclude contributions
that arise from speculative execution. The at-retirement events available in processors based on Intel Core microarchitecture does not require special MSR programming control (see Section 18.15.6, “At-Retirement Counting”),
but is limited to IA32_PMC0. See Table 18-9 for a list of events available to processors based on Intel Core microarchitecture.
Table 18-9. At-Retirement Performance Events for Intel Core Microarchitecture
Event Name
UMask
Event Select
ITLB_MISS_RETIRED
00H
C9H
MEM_LOAD_RETIRED.L1D_MISS
01H
CBH
MEM_LOAD_RETIRED.L1D_LINE_MISS
02H
CBH
MEM_LOAD_RETIRED.L2_MISS
04H
CBH
MEM_LOAD_RETIRED.L2_LINE_MISS
08H
CBH
MEM_LOAD_RETIRED.DTLB_MISS
10H
CBH
18.4.4
Processor Event Based Sampling (PEBS)
Processors based on Intel Core microarchitecture also support processor event based sampling (PEBS). This
feature was introduced by processors based on Intel NetBurst microarchitecture.
PEBS uses a debug store mechanism and a performance monitoring interrupt to store a set of architectural state
information for the processor. The information provides architectural state of the instruction executed after the
instruction that caused the event (See Section 18.4.4.2 and Section 17.4.9).
In cases where the same instruction causes BTS and PEBS to be activated, PEBS is processed before BTS are
processed. The PMI request is held until the processor completes processing of PEBS and BTS.
For processors based on Intel Core microarchitecture, precise events that can be used with PEBS are listed in
Table 18-10. The procedure for detecting availability of PEBS is the same as described in Section 18.15.7.1.
Table 18-10. PEBS Performance Events for Intel Core Microarchitecture
Event Name
UMask
Event Select
INSTR_RETIRED.ANY_P
00H
C0H
X87_OPS_RETIRED.ANY
FEH
C1H
BR_INST_RETIRED.MISPRED
00H
C5H
SIMD_INST_RETIRED.ANY
1FH
C7H
MEM_LOAD_RETIRED.L1D_MISS
01H
CBH
MEM_LOAD_RETIRED.L1D_LINE_MISS
02H
CBH
MEM_LOAD_RETIRED.L2_MISS
04H
CBH
MEM_LOAD_RETIRED.L2_LINE_MISS
08H
CBH
MEM_LOAD_RETIRED.DTLB_MISS
10H
CBH
Vol. 3B 18-21
PERFORMANCE MONITORING
18.4.4.1
Setting up the PEBS Buffer
For processors based on Intel Core microarchitecture, PEBS is available using IA32_PMC0 only. Use the following
procedure to set up the processor and IA32_PMC0 counter for PEBS:
1. Set up the precise event buffering facilities. Place values in the precise event buffer base, precise event index,
precise event absolute maximum, precise event interrupt threshold, and precise event counter reset fields of
the DS buffer management area. In processors based on Intel Core microarchitecture, PEBS records consist of
64-bit address entries. See Figure 17-8 to set up the precise event records buffer in memory.
2. Enable PEBS. Set the Enable PEBS on PMC0 flag (bit 0) in IA32_PEBS_ENABLE MSR.
3. Set up the IA32_PMC0 performance counter and IA32_PERFEVTSEL0 for an event listed in Table 18-10.
18.4.4.2
PEBS Record Format
The PEBS record format may be extended across different processor implementations. The
IA32_PERF_CAPABILITES MSR defines a mechanism for software to handle the evolution of PEBS record format in
processors that support architectural performance monitoring with version id equals 2 or higher. The bit fields of
IA32_PERF_CAPABILITES are defined in Table 35-2 of Chapter 35, “Model-Specific Registers (MSRs)”. The relevant
bit fields that governs PEBS are:
•
PEBSTrap [bit 6]: When set, PEBS recording is trap-like. After the PEBS-enabled counter has overflowed, PEBS
record is recorded for the next PEBS-able event at the completion of the sampled instruction causing the PEBS
event. When clear, PEBS recording is fault-like. The PEBS record is recorded before the sampled instruction
causing the PEBS event.
•
PEBSSaveArchRegs [bit 7]: When set, PEBS will save architectural register and state information according to
the encoded value of the PEBSRecordFormat field. When clear, only the return instruction pointer and flags are
recorded. On processors based on Intel Core microarchitecture, this bit is always 1
•
PEBSRecordFormat [bits 11:8]: Valid encodings are:
— 0000B: Only general-purpose registers, instruction pointer and RFLAGS registers are saved in each PEBS
record (seeSection 18.15.7).
— 0001B: PEBS record includes additional information of IA32_PERF_GLOBAL_STATUS and load latency data.
(seeSection 18.8.1.1).
— 0010B: PEBS record includes additional information of IA32_PERF_GLOBAL_STATUS, load latency data,
and TSX tuning information. (seeSection 18.11.2).
— 0011B: PEBS record includes additional information of load latency data, TSX tuning information, TSC data,
and the applicable counter field replaces IA32_PERF_GLOBAL_STATUS at offset 90H. (see Section
18.13.1.1).
18.4.4.3
Writing a PEBS Interrupt Service Routine
The PEBS facilities share the same interrupt vector and interrupt service routine (called the DS ISR) with the Interrupt-based event sampling and BTS facilities. To handle PEBS interrupts, PEBS handler code must be included in
the DS ISR. See Section 17.4.9.1, “64 Bit Format of the DS Save Area,” for guidelines when writing the DS ISR.
The service routine can query MSR_PERF_GLOBAL_STATUS to determine which counter(s) caused of overflow
condition. The service routine should clear overflow indicator by writing to MSR_PERF_GLOBAL_OVF_CTL.
18-22 Vol. 3B
PERFORMANCE MONITORING
A comparison of the sequence of requirements to program PEBS for processors based on Intel Core and Intel
NetBurst microarchitectures is listed in Table 18-11.
Table 18-11. Requirements to Program PEBS
For Processors based on Intel Core
microarchitecture
For Processors based on Intel NetBurst
microarchitecture
Verify PEBS support of
processor/OS
• IA32_MISC_ENABLE.EMON_AVAILABE (bit 7) is set.
• IA32_MISC_ENABLE.PEBS_UNAVAILABE (bit 12) is clear.
Ensure counters are in disabled
On initial set up or changing event
configurations, write
MSR_PERF_GLOBAL_CTRL MSR (38FH) with 0.
Optional
On subsequent entries:
• Clear all counters if “Counter Freeze on PMI“
is not enabled.
• If IA32_DebugCTL.Freeze is enabled,
counters are automatically disabled.
Counters MUST be stopped before writing.1
Disable PEBS.
Clear ENABLE PMC0 bit in IA32_PEBS_ENABLE
MSR (3F1H).
Optional
Check overflow conditions.
Check MSR_PERF_GLOBAL_STATUS MSR
(38EH) handle any overflow conditions.
Check OVF flag of each CCCR for overflow
condition
Clear overflow status.
Clear MSR_PERF_GLOBAL_STATUS MSR
(38EH) using IA32_PERF_GLOBAL_OVF_CTRL
MSR (390H).
Clear OVF flag of each CCCR.
Write “sample-after“ values.
Configure the counter(s) with the sample after value.
Configure specific counter
configuration MSR.
• Set local enable bit 22 - 1.
• Do NOT set local counter PMI/INT bit, bit 20
- 0.
• Event programmed must be PEBS capable.
Allocate buffer for PEBS states.
Allocate a buffer in memory for the precise information.
Program the IA32_DS_AREA MSR.
Program the IA32_DS_AREA MSR.
Configure the PEBS buffer
management records.
Configure the PEBS buffer management records in the DS buffer management area.
Configure/Enable PEBS.
Set Enable PMC0 bit in IA32_PEBS_ENABLE
MSR (3F1H).
Configure MSR_PEBS_ENABLE,
MSR_PEBS_MATRIX_VERT and
MSR_PEBS_MATRIX_HORZ as needed.
Enable counters.
Set Enable bits in MSR_PERF_GLOBAL_CTRL
MSR (38FH).
Set each CCCR enable bit 12 - 1.
• Set appropriate OVF_PMI bits - 1.
• Only CCCR for MSR_IQ_COUNTER4 support
PEBS.
NOTES:
1. Counters read while enabled are not guaranteed to be precise with event counts that occur in timing proximity to the RDMSR.
18.4.4.4
Re-configuring PEBS Facilities
When software needs to reconfigure PEBS facilities, it should allow a quiescent period between stopping the prior
event counting and setting up a new PEBS event. The quiescent period is to allow any latent residual PEBS records
to complete its capture at their previously specified buffer address (provided by IA32_DS_AREA).
Vol. 3B 18-23
PERFORMANCE MONITORING
18.5
PERFORMANCE MONITORING (45 NM AND 32 NM INTEL® ATOM™
PROCESSORS)
45 nm and 32 nm Intel Atom processors report architectural performance monitoring versionID = 3 (supporting
the aggregate capabilities of versionID 1, 2, and 3; see Section 18.2.3) and a host of non-architectural monitoring
capabilities. These 45 nm and 32 nm Intel Atom processors provide two general-purpose performance counters
(IA32_PMC0, IA32_PMC1) and three fixed-function performance counters (IA32_FIXED_CTR0, IA32_FIXED_CTR1,
IA32_FIXED_CTR2).
Non-architectural performance monitoring in Intel Atom processor family uses the IA32_PERFEVTSELx MSR to
configure a set of non-architecture performance monitoring events to be counted by the corresponding generalpurpose performance counter. The list of non-architectural performance monitoring events is listed in Table 19-26.
Architectural and non-architectural performance monitoring events in 45 nm and 32 nm Intel Atom processors
support thread qualification using bit 21 (AnyThread) of IA32_PERFEVTSELx MSR, i.e. if
IA32_PERFEVTSELx.AnyThread =1, event counts include monitored conditions due to either logical processors in
the same processor core.
The bit fields within each IA32_PERFEVTSELx MSR are defined in Figure 18-6 and described in Section 18.2.1.1 and
Section 18.2.3.
Valid event mask (Umask) bits are listed in Chapter 19. The UMASK field may contain sub-fields that provide the
same qualifying actions like those listed in Table 18-3, Table 18-4, Table 18-5, and Table 18-6. One or more of
these sub-fields may apply to specific events on an event-by-event basis. Details are listed in Table 19-26 in
Chapter 19, “Performance-Monitoring Events.” Precise Event Based Monitoring is supported using IA32_PMC0 (see
also Section 17.4.9, “BTS and DS Save Area”).
18.6
PERFORMANCE MONITORING FOR SILVERMONT MICROARCHITECTURE
Intel processors based on the Silvermont microarchitecture report architectural performance monitoring versionID
= 3 (see Section 18.2.3) and a host of non-architectural monitoring capabilities. Intel processors based on the
Silvermont microarchitecture provide two general-purpose performance counters (IA32_PMC0, IA32_PMC1) and
three fixed-function performance counters (IA32_FIXED_CTR0, IA32_FIXED_CTR1, IA32_FIXED_CTR2). Intel
Atom processors based on the Airmont microarchitecture support the same performance monitoring capabilities as
those based on the Silvermont microarchitecture.
Non-architectural performance monitoring in the Silvermont microarchitecture uses the IA32_PERFEVTSELx MSR
to configure a set of non-architecture performance monitoring events to be counted by the corresponding generalpurpose performance counter. The list of non-architectural performance monitoring events is listed in Table 19-25.
The bit fields (except bit 21) within each IA32_PERFEVTSELx MSR are defined in Figure 18-6 and described in
Section 18.2.1.1 and Section 18.2.3. Architectural and non-architectural performance monitoring events in the
Silvermont microarchitecture ignore the AnyThread qualification regardless of its setting in IA32_PERFEVTSELx
MSR.
18.6.1
Enhancements of Performance Monitoring in the Processor Core
The notable enhancements in the monitoring of performance events in the processor core include:
•
•
•
The width of counter reported by CPUID.0AH:EAX[23:16] is 40 bits.
Off-core response counting facility. This facility in the processor core allows software to count certain
transaction responses between the processor core to sub-systems outside the processor core (uncore).
Counting off-core response requires additional event qualification configuration facility in conjunction with
IA32_PERFEVTSELx. Two off-core response MSRs are provided to use in conjunction with specific event codes
that must be specified with IA32_PERFEVTSELx.
Average request latency measurement. The off-core response counting facility can be combined to use two
performance counters to count the occurrences and weighted cycles of transaction requests.
18-24 Vol. 3B
PERFORMANCE MONITORING
18.6.1.1
Processor Event Based Sampling (PEBS)
In the Silvermont microarchitecture, the PEBS facility can be used with precise events. PEBS is supported using
IA32_PMC0 (see also Section 17.4.9).
PEBS uses a debug store mechanism to store a set of architectural state information for the processor. The information provides architectural state of the instruction executed after the instruction that caused the event (See
Section 18.4.4).
The list of precise events supported in the Silvermont microarchitecture is shown in Table 18-12.
Table 18-12. PEBS Performance Events for the Silvermont Microarchitecture
Event Name
Event Select
Sub-event
UMask
BR_INST_RETIRED
C4H
ALL_BRANCHES
00H
JCC
7EH
TAKEN_JCC
FEH
BR_MISP_RETIRED
MEM_UOPS_RETIRED
REHABQ
C5H
04H
03H
CALL
F9H
REL_CALL
FDH
IND_CALL
FBH
NON_RETURN_IND
EBH
FAR_BRANCH
BFH
RETURN
F7H
ALL_BRANCHES
00H
JCC
7EH
TAKEN_JCC
FEH
IND_CALL
FBH
NON_RETURN_IND
EBH
RETURN
F7H
L2_HIT_LOADS
02H
L2_MISS_LOADS
04H
DLTB_MISS_LOADS
08H
HITM
20H
LD_BLOCK_ST_FORWARD
01H
LD_SPLITS
08H
Vol. 3B 18-25
PERFORMANCE MONITORING
PEBS Record Format The PEBS record format supported by processors based on the Intel Silvermont microarchitecture is shown in Table 18-13, and each field in the PEBS record is 64 bits long.
Table 18-13. PEBS Record Format for the Silvermont Microarchitecture
Byte Offset
Field
Byte Offset
Field
00H
R/EFLAGS
60H
R10
08H
R/EIP
68H
R11
10H
R/EAX
70H
R12
18H
R/EBX
78H
R13
20H
R/ECX
80H
R14
28H
R/EDX
88H
R15
30H
R/ESI
90H
IA32_PERF_GLOBAL_STATUS
38H
R/EDI
98H
Reserved
40H
R/EBP
A0H
Reserved
48H
R/ESP
A8H
Reserved
50H
R8
B0H
EventingRIP
58H
R9
B8H
Reserved
18.6.2
Offcore Response Event
Event number 0B7H support offcore response monitoring using an associated configuration MSR,
MSR_OFFCORE_RSP0 (address 1A6H) in conjunction with umask value 01H or MSR_OFFCORE_RSP1 (address
1A7H) in conjunction with umask value 02H. Table 18-14 lists the event code, mask value and additional off-core
configuration MSR that must be programmed to count off-core response events using IA32_PMCx.
In the Silvermont microarchitecture, each MSR_OFFCORE_RSPx is shared by two processor cores.
Table 18-14. OffCore Response Event Encoding
Counter
Event code
UMask
Required Off-core Response MSR
PMC0-1
B7H
01H
MSR_OFFCORE_RSP0 (address 1A6H)
PMC0-1
B7H
02H
MSR_OFFCORE_RSP1 (address 1A7H)
The layout of MSR_OFFCORE_RSP0 and MSR_OFFCORE_RSP1 are shown in Figure 18-18 and Figure 18-19. Bits
15:0 specifies the request type of a transaction request to the uncore. Bits 30:16 specifies supplier information,
bits 37:31 specifies snoop response information.
Additionally, MSR_OFFCORE_RSP0 provides bit 38 to enable measurement of average latency of specific type of
offcore transaction requests using two programmable counter simultaneously, see Section 18.6.3 for details.
18-26 Vol. 3B
PERFORMANCE MONITORING
63
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
37
See Figure 18-30
RESPONSE TYPE — Other (R/W)
REQUEST TYPE — PARTIAL_STRM_ST (R/W)
REQUEST TYPE — PF_DATA_RD (R/W)
REQUEST TYPE — SW_PREFETCH (R/W)
REQUEST TYPE — STRM_ST (R/W)
REQUEST TYPE — BUS_LOCKS (R/W)
REQUEST TYPE — UC_IFETCH (R/W)
REQUEST TYPE — PARTIAL_WRITE (R/W)
REQUEST TYPE — PARTIAL_READ (R/W)
REQUEST TYPE — PF_IFETCH (R/W)
REQUEST TYPE — PF_RFO (R/W)
REQUEST TYPE — PF_DATA_RD (R/W)
REQUEST TYPE — WB (R/W)
REQUEST TYPE — DMND_IFETCH (R/W)
REQUEST TYPE — DMND_RFO (R/W)
REQUEST TYPE — DMND_DATA_RD (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-18. Request_Type Fields for MSR_OFFCORE_RSPx
Table 18-15. MSR_OFFCORE_RSPx Request_Type Field Definition
Bit Name
Offset
Description
DMND_DATA_RD
0
(R/W). Counts the number of demand and DCU prefetch data reads of full and partial cachelines as
well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or
instruction fetches.
DMND_RFO
1
(R/W). Counts the number of demand and DCU prefetch reads for ownership (RFO) requests
generated by a write to data cacheline. Does not count L2 RFO prefetches.
DMND_IFETCH
2
(R/W). Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count
L2 code read prefetches.
WB
3
(R/W). Counts the number of writeback (modified to exclusive) transactions.
PF_DATA_RD
4
(R/W). Counts the number of data cacheline reads generated by L2 prefetchers.
PF_RFO
5
(R/W). Counts the number of RFO requests generated by L2 prefetchers.
PF_IFETCH
6
(R/W). Counts the number of code reads generated by L2 prefetchers.
PARTIAL_READ
7
(R/W). Counts the number of demand reads of partial cache lines (including UC and WC).
PARTIAL_WRITE
8
(R/W). Counts the number of demand RFO requests to write to partial cache lines (includes UC, WT
and WP)
UC_IFETCH
9
(R/W). Counts the number of UC instruction fetches.
BUS_LOCKS
10
(R/W). Bus lock and split lock requests
STRM_ST
11
(R/W). Streaming store requests
SW_PREFETCH
12
(R/W). Counts software prefetch requests
PF_DATA_RD
13
(R/W). Counts DCU hardware prefetcher data read requests
PARTIAL_STRM_ST
14
(R/W). Streaming store requests
ANY
15
(R/W). Any request that crosses IDI, including I/O.
Vol. 3B 18-27
PERFORMANCE MONITORING
63
38 37 36 35 34 33 32 31
22 21 20 19 18 17 16
AVG LATENCY — ENABLE AVG LATENCY(R/W)
RESPONSE TYPE — NON_DRAM (R/W)
RSPNS_SNOOP — HITM (R/W)
RESERVED
RSPNS_SNOOP — SNOOP_HIT (R/W)
RSPNS_SNOOP — SNOOP_MISS (R/W)
RESERVED
RSPNS_SNOOP — SNOOP_NONE (R/W)
RESERVED
RSPNS_SUPPLIER — L2_HIT (R/W)
RESERVED
RSPNS_SUPPLIER — ANY (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-19. Response_Supplier and Snoop Info Fields for MSR_OFFCORE_RSPx
To properly program this extra register, software must set at least one request type bit (Table 18-15) and a valid
response type pattern (Table 18-16, Table 18-17). Otherwise, the event count reported will be zero. It is permissible and useful to set multiple request and response type bits in order to obtain various classes of off-core
response events. Although MSR_OFFCORE_RSPx allow an agent software to program numerous combinations that
meet the above guideline, not all combinations produce meaningful data.
Table 18-16. MSR_OFFCORE_RSP_x Response Supplier Info Field Definition
Subtype
Bit Name
Offset
Description
Common
ANY_RESPONSE
16
(R/W). Catch all value for any response types.
Supplier Info
Reserved
17
Reserved
L2_HIT
18
(R/W). Cache reference hit L2 in either M/E/S states.
Reserved
30:19
Reserved
To specify a complete offcore response filter, software must properly program bits in the request and response type
fields. A valid request type must have at least one bit set in the non-reserved bits of 15:0. A valid response type
must be a non-zero value of the following expression:
ANY | [(‘OR’ of Supplier Info Bits) & (‘OR’ of Snoop Info Bits)]
If “ANY” bit is set, the supplier and snoop info bits are ignored.
18-28 Vol. 3B
PERFORMANCE MONITORING
Table 18-17. MSR_OFFCORE_RSPx Snoop Info Field Definition
Subtype
Bit Name
Offset
Description
Snoop
Info
SNP_NONE
31
(R/W). No details on snoop-related information.
Reserved
32
Reserved
SNOOP_MISS
33
(R/W). Counts the number of snoop misses when L2 misses.
SNOOP_HIT
34
(R/W). Counts the number of snoops hit in the other module where no modified copies
were found.
Reserved
35
Reserved
HITM
36
(R/W). Counts the number of snoops hit in the other module where modified copies
were found in other core's L1 cache.
NON_DRAM
37
(R/W). Target was non-DRAM system address. This includes MMIO transactions.
AVG_LATENCY
38
(R/W). Enable average latency measurement by counting weighted cycles of
outstanding offcore requests of the request type specified in bits 15:0 and any
response (bits 37:16 cleared to 0).
This bit is available in MSR_OFFCORE_RESP0. The weighted cycles is accumulated in the
specified programmable counter IA32_PMCx and the occurrence of specified requests
are counted in the other programmable counter.
18.6.3
Average Offcore Request Latency Measurement
Average latency for offcore transactions can be determined by using both MSR_OFFCORE_RSP registers. Using two
performance monitoring counters, program the two OFFCORE_RESPONSE event encodings into the corresponding
IA32_PERFEVTSELx MSRs. Count the weighted cycles via MSR_OFFCORE_RSP0 by programming a request type in
MSR_OFFCORE_RSP0.[15:0] and setting MSR_OFFCORE_RSP0.OUTSTANDING[38] to 1, white setting the
remaining bits to 0. Count the number of requests via MSR_OFFCORE_RSP1 by programming the same request
type from MSR_OFFCORE_RSP0 into MSR_OFFCORE_RSP1[bit 15:0], and setting
MSR_OFFCORE_RSP1.ANY_RESPONSE[16] = 1, while setting the remaining bits to 0. The average latency can be
obtained by dividing the value of the IA32_PMCx register that counted weight cycles by the register that counted
requests.
18.7
PERFORMANCE MONITORING FOR GOLDMONT MICROARCHITECTURE
Next generation Intel Atom processors are based on the Goldmont microarchitecture. They report architectural
performance monitoring versionID = 4 (see Section 18.2.4) and support non-architectural monitoring capabilities
described in this section.
Architectural performance monitoring version 4 capabilities are described in Section 18.2.4.
The bit fields (except bit 21) within each IA32_PERFEVTSELx MSR are defined in Figure 18-6 and described in
Section 18.2.1.1 and Section 18.2.3. Architectural and non-architectural performance monitoring events in the
Goldmont microarchitecture ignore the AnyThread qualification regardless of its setting in the IA32_PERFEVTSELx
MSR.
The core PMU’s capability is similar to that of the Silvermont microarchitecture described in Section 18.6 , with
some differences and enhancements summarized in Table 18-18.
Vol. 3B 18-29
PERFORMANCE MONITORING
Table 18-18. Core PMU Comparison Between the Goldmont and Silvermont Microarchitectures
Box
The Goldmont microarchitecture
The Silvermont microarchitecture
Comment
# of Fixed counters per core
3
3
Use CPUID to enumerate
# of counters.
# of general-purpose
counters per core
4
2
Counter width (R,W)
R:48, W: 32/48
R:40, W:32
See Section 18.2.2.
Architectural Performance
Monitoring version ID
4
3
Use CPUID to enumerate
# of counters.
PMI Overhead Mitigation
• Freeze_Perfmon_on_PMI with
streamlined semantics.
• Freeze_on_LBR with legacy
semantics for branch profiling.
• Freeze_while_SMM.
• Freeze_Perfmon_on_PMI with
legacy semantics.
• Freeze_on_LBR with legacy
semantics for branch profiling.
• Freeze_while_SMM.
See Section 17.4.7.
Counter and Buffer
Overflow Status
Management
• Query via
IA32_PERF_GLOBAL_STATUS
• Reset via
IA32_PERF_GLOBAL_STATUS_R
ESET
• Set via
IA32_PERF_GLOBAL_STATUS_S
ET
• Query via
IA32_PERF_GLOBAL_STATUS
• Reset via
IA32_PERF_GLOBAL_OVF_CTRL
See Section 18.2.4.
IA32_PERF_GLOBAL_STATU
S Indicators of
Overflow/Overhead/Interfer
ence
•
•
•
•
• Individual counter overflow
• PEBS buffer overflow
See Section 18.2.4.
Enable control in
IA32_PERF_GLOBAL_STATU
S
• CTR_Frz,
• LBR_Frz
No
See Section 18.2.4.1.
Perfmon Counter In-Use
Indicator
Query IA32_PERF_GLOBAL_INUSE
No
See Section 18.2.4.3.
Processor Event Based
Sampling (PEBS) Events
General-Purpose Counter 0 only.
Supports all events (precise and
non-precise). Precise events are
listed in Table 18-19.
See Section 18.6.1.1. GeneralPurpose Counter 0 only. Only
supports precise events (see
Table 18-12).
IA32_PMC0 only.
PEBS record format
encoding
0011b
0010b
Reduce skid PEBS
IA32_PMC0 only
No
Data Address Profiling
Yes
No
PEBS record layout
Table 18-20; enhanced fields at
offsets 90H- 98H; and TSC record
field at C0H.
Table 18-13.
PEBS EventingIP
Yes
Yes
Off-core Response Event
MSR 1A6H and 1A7H, each core
has its own register.
MSR 1A6H and 1A7H, shared by a
pair of cores.
18-30 Vol. 3B
Individual counter overflow
PEBS buffer overflow
ToPA buffer overflow
CTR_Frz, LBR_Frz
Legacy semantics not
supported with version 4
or higher.
Nehalem supports 1A6H
only.
PERFORMANCE MONITORING
18.7.1
Processor Event Based Sampling (PEBS)
Processor event based sampling (PEBS) on the Goldmont microarchitecture is enhanced over prior generations
with respect to sampling support of precise events and non-precise events. In the Goldmont microarchitecture,
PEBS is supported using IA32_PMC0 for all events (see Section 17.4.9).
PEBS uses a debug store mechanism to store a set of architectural state information for the processor at the time
the sample was generated.
Precise events work the same way as on the Silvermont microarchitecture. They can capture precise eventingIP
associated with a retired instruction that caused the event. The PEBS record provides architectural state of the
instruction executed after the instruction that caused the event (See Section 18.4.4 and Section 17.4.9). The PEBS
record also provides architectural state of the processor after the instruction that caused the event completes. The
list of precise events supported in the Goldmont microarchitecture is shown in Table 18-19.
In the Goldmont microarchitecture, the PEBS facility also supports the use of non-precise events to record
processor state information into PEBS records with the same format as with precise events.
However, a non-precise event may not be attributable to a particular retired instruction or the time of instruction
execution. When the counter overflows, a PEBS record will be generated at the next opportunity. Consider the
event ICACHE.HIT. When the counter overflows, the processor is fetching future instructions. The PEBS record will
be generated at the next opportunity and capture the state at the processor's current retirement point. Other
examples of a non-precise events are CPU_CLK_UNHALTED.CORE_P and HARDWARE_INTERRUPTS.RECEIVED.
There may be many instructions in various stages of execution, multiple or zero instructions being retired each
cycle as CPU_CLK_UNHALTED.CORE_P increments. HARDWARE_INTERRUPTS.RECEIVED increments independent
of any instructions being executed. The PEBS record will be generated at the next opportunity, capturing the
processor state when the machine received the interrupt, even if interrupts are masked. The PEBS facility thus
allows for identification of the instructions which were executing when the event overflowed.
After generating a record, the PEBS facility reloads the counter and resumes execution, just as is done for precise
events. Unlike interrupt-based sampling, which requires an interrupt service routine to collect the sample and
reload the counter, the PEBS facility can collect samples even when interrupts are masked and without using NMI.
Since a PEBS record is generated immediately when a counter for a non-precise event is enabled, it may also be
generated after an overflow is set by an MSR write to IA32_PERF_GLOBAL_STATUS_SET.
Table 18-19. Precise Events Supported by the Goldmont Microarchitecture
Event Name
Event Select
Sub-event
UMask
LD_BLOCKS
03H
DATA_UNKNOWN
01H
STORE_FORWARD
02H
4K_ALIAS
04H
UTLB_MISS
08H
ALL_BLOCK
10H
LOAD_PAGE_SPLIT
02H
MISALIGN_MEM_REF
13H
STORE_PAGE_SPLIT
04H
INST_RETIRED
C0H
ANY
00H
UOPS_RETITRED
C2H
ANY
00H
LD_SPLITSMS
01H
ALL_BRANCHES
00H
JCC
7EH
TAKEN_JCC
FEH
CALL
F9H
REL_CALL
FDH
IND_CALL
FBH
NON_RETURN_IND
EBH
FAR_BRANCH
BFH
BR_INST_RETIRED
C4H
Vol. 3B 18-31
PERFORMANCE MONITORING
Table 18-19. Precise Events Supported by the Goldmont Microarchitecture (Contd.)
Event Name
Event Select
BR_MISP_RETIRED
C5H
MEM_UOPS_RETIRED
D0H
MEM_LOAD_UOPS_RETIRED
D1H
Sub-event
UMask
RETURN
F7H
ALL_BRANCHES
00H
JCC
7EH
TAKEN_JCC
FEH
IND_CALL
FBH
NON_RETURN_IND
EBH
RETURN
F7H
ALL_LOADS
81H
ALL_STORES
82H
ALL
83H
DLTB_MISS_LOADS
11H
DLTB_MISS_STORES
12H
DLTB_MISS
13H
L1_HIT
01H
L2_HIT
02H
L1_MISS
08H
L2_MISS
10H
HITM
20H
WCB_HIT
40H
DRAM_HIT
80H
The PEBS record format supported by processors based on the Intel Silvermont microarchitecture is shown in
Table 18-13, and each field in the PEBS record is 64 bits long.
Table 18-20. PEBS Record Format for the Goldmont Microarchitecture
Byte Offset
Field
Byte Offset
Field
00H
R/EFLAGS
68H
R11
08H
R/EIP
70H
R12
10H
R/EAX
78H
R13
18H
R/EBX
80H
R14
20H
R/ECX
88H
R15
28H
R/EDX
90H
Applicable Counters
30H
R/ESI
98H
Data Linear Address
38H
R/EDI
A0H
Reserved
40H
R/EBP
A8H
Reserved
48H
R/ESP
B0H
EventingRIP
50H
R8
B8H
Reserved
58H
R9
C0H
TSC
60H
R10
On Goldmont microarchitecture, all 64 bits of architectural registers are written into the PEBS record regardless of
processor mode.
18-32 Vol. 3B
PERFORMANCE MONITORING
With PEBS record format encoding 0011b, offset 90H reports the “applicable counter” field, which is a multicounter PEBS resolution index allowing software to correlate the PEBS record entry with the eventing PEBS overflow when multiple counters are configured to record PEBS records. Additionally, offset C0H captures a snapshot of
the TSC that provides a time line annotation for each PEBS record entry.
18.7.1.1
PEBS Data Linear Address Profiling
Goldmont supports the Data Linear Address field introduced in Haswell. It does not support the Data Source
Encoding or Latency Value fields that are also part of Data Address Profiling. The fields are present in the record but
are reserved.
For Goldmont, the Data Linear Address field will record the linear address of memory accesses in the previous
instruction (e.g. the one that triggered a precise event that caused the PEBS record to be generated).
18.7.1.2
Reduced Skid PEBS
For precise events, upon triggering a PEBS assist, there will be a finite delay between the time the counter overflows and when the microcode starts to carry out its data collection obligations. The Reduced Skid mechanism mitigates the “skid” problem by providing an early indication of when the counter is about to overflow, allowing the
machine to more precisely trap on the instruction that actually caused the counter overflow thus greatly reducing
skid.
This mechanism is a superset of the PDIR mechanism available in the Sandy Bridge microarchitecture. See Section
18.9.4.4
In the Goldmont microarchitecture, the mechanism applies to all precise events including, INST_RETIRED, except
for UOPS_RETIRED. However, the Reduced Skid mechanism is disabled for any counter when the INV, ANY, E, or
CMASK fields are set.
To ensure the Reduced Skid mechanism operates correctly, disable PEBS via the IA32_PEBS_ENABLE or
IA32_PERF_GLOBAL_CTRL MSRs before writing to the configuration registers (IA32_PERFEVTSELx) or to the counters (IA32_PMCx and IA32_A_PMCx).
18.7.1.3
Enhancements to IA32_PERF_GLOBAL_STATUS.OvfDSBuffer[62]
In addition to IA32_PERF_GLOBAL_STATUS.OvfDSBuffer[62] being set when PEBS_Index reaches the
PEBS_Interrupt_Theshold, the bit is also set when PEBS_Index is out of bounds. That is, the bit will be set when
PEBS_Index < PEBS_Buffer_Base or PEBS_Index > PEBS_Absolute_Maximum. Note that when an out of bound
condition is encountered, the overflow bits in IA32_PERF_GLOBAL_STATUS will be cleared according to Applicable
Counters, however the IA32_PMCx values will not be reloaded with the Reset values stored in the DS_AREA.
18.7.2
Offcore Response Event
Event number 0B7H support offcore response monitoring using an associated configuration MSR,
MSR_OFFCORE_RSP0 (address 1A6H) in conjunction with umask value 01H or MSR_OFFCORE_RSP1 (address
1A7H) in conjunction with umask value 02H. Table 18-14 lists the event code, mask value and additional off-core
configuration MSR that must be programmed to count off-core response events using IA32_PMCx.
The Goldmont microarchitecture provides unique pairs of MSR_OFFCORE_RSPx registers per core.
The layout of MSR_OFFCORE_RSP0 and MSR_OFFCORE_RSP1 are organized as follows:
•
•
•
•
Bits 15:0 specifies the request type of a transaction request to the uncore. This is described in Table 18-21.
Bits 30:16 specifies common supplier information or an L2 Hit, and is described in Table 18-16.
If L2 misses, then Bits 37:31 can be used to specify snoop response information and is described in
Table 18-22.
For outstanding requests, bit 38 can enable measurement of average latency of specific type of offcore
transaction requests using two programmable counter simultaneously; see Section 18.6.3 for details.
Vol. 3B 18-33
PERFORMANCE MONITORING
Table 18-21. MSR_OFFCORE_RSPx Request_Type Field Definition
Bit Name
Offset
Description
DEMAND_DATA_RD
0
(R/W) Counts cacheline read requests due to demand reads (excludes prefetches).
DEMAND_RFO
1
(R/W) Counts cacheline read for ownership (RFO) requests due to demand writes
(excludes prefetches).
DEMAND_CODE_RD
2
(R/W) Counts demand instruction cacheline and I-side prefetch requests that miss the
instruction cache.
COREWB
3
(R/W) Counts writeback transactions caused by L1 or L2 cache evictions.
PF_L2_DATA_RD
4
(R/W) Counts data cacheline reads generated by hardware L2 cache prefetcher.
PF_L2_RFO
5
(R/W) Counts reads for ownership (RFO) requests generated by L2 prefetcher.
Reserved
6
Reserved.
PARTIAL_READS
7
(R/W) Counts demand data partial reads, including data in uncacheable (UC) or
uncacheable (WC) write combining memory types.
PARTIAL_WRITES
8
(R/W) Counts partial writes, including uncacheable (UC), write through (WT) and write
protected (WP) memory type writes.
UC_CODE_READS
9
(R/W) Counts code reads in uncacheable (UC) memory region.
BUS_LOCKS
10
(R/W) Counts bus lock and split lock requests.
FULL_STREAMING_STORES
11
(R/W) Counts full cacheline writes due to streaming stores.
SW_PREFETCH
12
(R/W) Counts cacheline requests due to software prefetch instructions.
PF_L1_DATA_RD
13
(R/W) Counts data cacheline reads generated by hardware L1 data cache prefetcher.
PARTIAL_STREAMING_STORES
14
(R/W) Counts partial cacheline writes due to streaming stores.
ANY_REQUEST
15
(R/W) Counts requests to the uncore subsystem.
To properly program this extra register, software must set at least one request type bit (Table 18-15) and a valid
response type pattern (either Table 18-16 or Table 18-22). Otherwise, the event count reported will be zero. It is
permissible and useful to set multiple request and response type bits in order to obtain various classes of off-core
response events. Although MSR_OFFCORE_RSPx allow an agent software to program numerous combinations that
meet the above guideline, not all combinations produce meaningful data.
Table 18-22. MSR_OFFCORE_RSPx For L2 Miss and Outstanding Requests
Subtype
Bit Name
Offset
Description
L2_MISS
(Snoop Info)
Reserved
32:31
Reserved
L2_MISS.SNOOP_MISS_O 33
R_NO_SNOOP_NEEDED
(R/W). A true miss to this module, for which a snoop request missed the other
module or no snoop was performed/needed.
L2_MISS.HIT_OTHER_CO
RE_NO_FWD
34
(R/W) A snoop hit in the other processor module, but no data forwarding is
required.
Reserved
35
Reserved
L2_MISS.HITM_OTHER_C 36
ORE
(R/W) Counts the number of snoops hit in the other module or other core's L1
where modified copies were found.
L2_MISS.NON_DRAM
37
(R/W) Target was a non-DRAM system address. This includes MMIO transactions.
38
(R/W) Counts weighted cycles of outstanding offcore requests of the request type
specified in bits 15:0, from the time the XQ receives the request and any
response is received. Bits 37:16 must be set to 0. This bit is only available in
MSR_OFFCORE_RESP0.
Outstanding OUTSTANDING
requests1
18-34 Vol. 3B
PERFORMANCE MONITORING
NOTES:
1. See Section 18.6.3, “Average Offcore Request Latency Measurement” for details on how to use this bit to extract average latency.
To specify a complete offcore response filter, software must properly program bits in the request and response type
fields. A valid request type must have at least one bit set in the non-reserved bits of 15:0. A valid response type
must be a non-zero value of the following expression:
[ANY ‘OR’ (L2 Hit) ] ‘XOR’ ( Snoop Info Bits) ‘XOR’ (Avg Latency)
18.7.3
Average Offcore Request Latency Measurement
In Goldmont microarachitecture, measurement of average latency of offcore transaction requests is the same as
described in Section 18.6.3.
18.8
PERFORMANCE MONITORING FOR PROCESSORS BASED ON INTEL®
MICROARCHITECTURE CODE NAME NEHALEM
Intel Core i7 processor family2 supports architectural performance monitoring capability with version ID 3 (see
Section 18.2.3) and a host of non-architectural monitoring capabilities. The Intel Core i7 processor family is based
on Intel® microarchitecture code name Nehalem, and provides four general-purpose performance counters
(IA32_PMC0, IA32_PMC1, IA32_PMC2, IA32_PMC3) and three fixed-function performance counters
(IA32_FIXED_CTR0, IA32_FIXED_CTR1, IA32_FIXED_CTR2) in the processor core.
Non-architectural performance monitoring in Intel Core i7 processor family uses the IA32_PERFEVTSELx MSR to
configure a set of non-architecture performance monitoring events to be counted by the corresponding generalpurpose performance counter. The list of non-architectural performance monitoring events is listed in Table 19-26.
Non-architectural performance monitoring events fall into two broad categories:
•
Performance monitoring events in the processor core: These include many events that are similar to
performance monitoring events available to processor based on Intel Core microarchitecture. Additionally,
there are several enhancements in the performance monitoring capability for detecting microarchitectural
conditions in the processor core or in the interaction of the processor core to the off-core sub-systems in the
physical processor package. The off-core sub-systems in the physical processor package is loosely referred to
as “uncore“.
•
Performance monitoring events in the uncore: The uncore sub-system is shared by more than one processor
cores in the physical processor package. It provides additional performance monitoring facility outside of
IA32_PMCx and performance monitoring events that are specific to the uncore sub-system.
Architectural and non-architectural performance monitoring events in Intel Core i7 processor family support thread
qualification using bit 21 of IA32_PERFEVTSELx MSR.
The bit fields within each IA32_PERFEVTSELx MSR are defined in Figure 18-6 and described in Section 18.2.1.1 and
Section 18.2.3.
2. Intel Xeon processor 5500 series and 3400 series are also based on Intel microarchitecture code name Nehalem, so the performance monitoring facilities described in this section generally also apply.
Vol. 3B 18-35
PERFORMANCE MONITORING
63 62 61 60
353433 3231
8 7 6 5 43 2 1 0
CHG (R/W)
OVF_PMI (R/W)
OVF_FC2 (R/O)
OVF_FC1 (R/O)
OVF_FC0 (R/O)
OVF_PC7 (R/O), if CCNT>7
OVF_PC6 (R/O), if CCNT>6
OVF_PC5 (R/O), if CCNT>5
OVF_PC4 (R/O), if CCNT>4
OVF_PC3 (R/O)
OVF_PC2 (R/O)
OVF_PC1 (R/O)
OVF_PC0 (R/O)
Reserved
RESET Value — 00000000_00000000H
CCNT: CPUID.AH:EAX[15:8]
Figure 18-20. IA32_PERF_GLOBAL_STATUS MSR
18.8.1
Enhancements of Performance Monitoring in the Processor Core
The notable enhancements in the monitoring of performance events in the processor core include:
•
Four general purpose performance counters, IA32_PMCx, associated counter configuration MSRs,
IA32_PERFEVTSELx, and global counter control MSR supporting simplified control of four counters. Each of the
four performance counter can support processor event based sampling (PEBS) and thread-qualification of
architectural and non-architectural performance events. Width of IA32_PMCx supported by hardware has been
increased. The width of counter reported by CPUID.0AH:EAX[23:16] is 48 bits. The PEBS facility in Intel microarchitecture code name Nehalem has been enhanced to include new data format to capture additional information, such as load latency.
•
Load latency sampling facility. Average latency of memory load operation can be sampled using load-latency
facility in processors based on Intel microarchitecture code name Nehalem. This field measures the load
latency from load's first dispatch of till final data writeback from the memory subsystem. The latency is
reported for retired demand load operations and in core cycles (it accounts for re-dispatches). This facility is
used in conjunction with the PEBS facility.
•
Off-core response counting facility. This facility in the processor core allows software to count certain
transaction responses between the processor core to sub-systems outside the processor core (uncore).
Counting off-core response requires additional event qualification configuration facility in conjunction with
IA32_PERFEVTSELx. Two off-core response MSRs are provided to use in conjunction with specific event codes
that must be specified with IA32_PERFEVTSELx.
18.8.1.1
Processor Event Based Sampling (PEBS)
All four general-purpose performance counters, IA32_PMCx, can be used for PEBS if the performance event
supports PEBS. Software uses IA32_MISC_ENABLE[7] and IA32_MISC_ENABLE[12] to detect whether the performance monitoring facility and PEBS functionality are supported in the processor. The MSR IA32_PEBS_ENABLE
provides 4 bits that software must use to enable which IA32_PMCx overflow condition will cause the PEBS record
to be captured.
Additionally, the PEBS record is expanded to allow latency information to be captured. The MSR
IA32_PEBS_ENABLE provides 4 additional bits that software must use to enable latency data recording in the PEBS
record upon the respective IA32_PMCx overflow condition. The layout of IA32_PEBS_ENABLE for processors based
on Intel microarchitecture code name Nehalem is shown in Figure 18-21.
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PERFORMANCE MONITORING
When a counter is enabled to capture machine state (PEBS_EN_PMCx = 1), the processor will write machine state
information to a memory buffer specified by software as detailed below. When the counter IA32_PMCx overflows
from maximum count to zero, the PEBS hardware is armed.
63
36 3534 33 32 31
8 7 6 5 43 2 1 0
LL_EN_PMC3 (R/W)
LL_EN_PMC2 (R/W)
LL_EN_PMC1 (R/W)
LL_EN_PMC0 (R/W)
PEBS_EN_PMC3 (R/W)
PEBS_EN_PMC2 (R/W)
PEBS_EN_PMC1 (R/W)
PEBS_EN_PMC0 (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-21. Layout of IA32_PEBS_ENABLE MSR
Upon occurrence of the next PEBS event, the PEBS hardware triggers an assist and causes a PEBS record to be
written. The format of the PEBS record is indicated by the bit field IA32_PERF_CAPABILITIES[11:8] (see
Figure 18-49).
The behavior of PEBS assists is reported by IA32_PERF_CAPABILITIES[6] (see Figure 18-49). The return instruction pointer (RIP) reported in the PEBS record will point to the instruction after (+1) the instruction that causes the
PEBS assist. The machine state reported in the PEBS record is the machine state after the instruction that causes
the PEBS assist is retired. For instance, if the instructions:
mov eax, [eax] ; causes PEBS assist
nop
are executed, the PEBS record will report the address of the nop, and the value of EAX in the PEBS record will show
the value read from memory, not the target address of the read operation.
The PEBS record format is shown in Table 18-23, and each field in the PEBS record is 64 bits long. The PEBS record
format, along with debug/store area storage format, does not change regardless of IA-32e mode is active or not.
CPUID.01H:ECX.DTES64[bit 2] reports whether the processor's DS storage format support is mode-independent.
When set, it uses 64-bit DS storage format.
Vol. 3B 18-37
PERFORMANCE MONITORING
Table 18-23. PEBS Record Format for Intel Core i7 Processor Family
Byte Offset
Field
Byte Offset
Field
00H
R/EFLAGS
58H
R9
08H
R/EIP
60H
R10
10H
R/EAX
68H
R11
18H
R/EBX
70H
R12
20H
R/ECX
78H
R13
28H
R/EDX
80H
R14
30H
R/ESI
88H
R15
38H
R/EDI
90H
IA32_PERF_GLOBAL_STATUS
40H
R/EBP
98H
Data Linear Address
48H
R/ESP
A0H
Data Source Encoding
50H
R8
A8H
Latency value (core cycles)
In IA-32e mode, the full 64-bit value is written to the register. If the processor is not operating in IA-32e mode, 32bit value is written to registers with bits 63:32 zeroed. Registers not defined when the processor is not in IA-32e
mode are written to zero.
Bytes AFH:90H are enhancement to the PEBS record format. Support for this enhanced PEBS record format is indicated by IA32_PERF_CAPABILITIES[11:8] encoding of 0001B.
The value written to bytes 97H:90H is the state of the IA32_PERF_GLOBAL_STATUS register before the PEBS assist
occurred. This value is written so software can determine which counters overflowed when this PEBS record was
written. Note that this field indicates the overflow status for all counters, regardless of whether they were
programmed for PEBS or not.
Programming PEBS Facility
Only a subset of non-architectural performance events in the processor support PEBS. The subset of precise events
are listed in Table 18-10. In addition to using IA32_PERFEVTSELx to specify event unit/mask settings and setting
the EN_PMCx bit in the IA32_PEBS_ENABLE register for the respective counter, the software must also initialize the
DS_BUFFER_MANAGEMENT_AREA data structure in memory to support capturing PEBS records for precise events.
NOTE
PEBS events are only valid when the following fields of IA32_PERFEVTSELx are all zero: AnyThread,
Edge, Invert, CMask.
The beginning linear address of the DS_BUFFER_MANAGEMENT_AREA data structure must be programmed into
the IA32_DS_AREA register. The layout of the DS_BUFFER_MANAGEMENT_AREA is shown in Figure 18-22.
•
PEBS Buffer Base: This field is programmed with the linear address of the first byte of the PEBS buffer
allocated by software. The processor reads this field to determine the base address of the PEBS buffer. Software
should allocate this memory from the non-paged pool.
•
PEBS Index: This field is initially programmed with the same value as the PEBS Buffer Base field, or the
beginning linear address of the PEBS buffer. The processor reads this field to determine the location of the next
PEBS record to write to. After a PEBS record has been written, the processor also updates this field with the
address of the next PEBS record to be written. The figure above illustrates the state of PEBS Index after the first
PEBS record is written.
•
PEBS Absolute Maximum: This field represents the absolute address of the maximum length of the allocated
PEBS buffer plus the starting address of the PEBS buffer. The processor will not write any PEBS record beyond
the end of PEBS buffer, when PEBS Index equals PEBS Absolute Maximum. No signaling is generated when
PEBS buffer is full. Software must reset the PEBS Index field to the beginning of the PEBS buffer address to
continue capturing PEBS records.
18-38 Vol. 3B
PERFORMANCE MONITORING
IA32_DS_AREA MSR
DS Buffer Management Area
BTS Buffer Base
0H
BTS Index
8H
BTS Absolute
Maximum
BTS Interrupt
Threshold
BTS Buffer
Branch Record 0
10H
Branch Record 1
18H
PEBS Buffer Base 20H
PEBS Index
PEBS Absolute
Maximum
PEBS Interrupt
Threshold
PEBS
Counter0 Reset
PEBS
Counter1 Reset
PEBS
Counter2 Reset
PEBS
Counter3 Reset
Reserved
28H
30H
38H
Branch Record n
40H
48H
PEBS Buffer
PEBS Record 0
50H
58H
PEBS Record 1
60H
PEBS Record n
Figure 18-22. PEBS Programming Environment
•
PEBS Interrupt Threshold: This field specifies the threshold value to trigger a performance interrupt and
notify software that the PEBS buffer is nearly full. This field is programmed with the linear address of the first
byte of the PEBS record within the PEBS buffer that represents the threshold record. After the processor writes
a PEBS record and updates PEBS Index, if the PEBS Index reaches the threshold value of this field, the
processor will generate a performance interrupt. This is the same interrupt that is generated by a performance
counter overflow, as programmed in the Performance Monitoring Counters vector in the Local Vector Table of
the Local APIC. When a performance interrupt due to PEBS buffer full is generated, the
IA32_PERF_GLOBAL_STATUS.PEBS_Ovf bit will be set.
•
PEBS CounterX Reset: This field allows software to set up PEBS counter overflow condition to occur at a rate
useful for profiling workload, thereby generating multiple PEBS records to facilitate characterizing the profile
the execution of test code. After each PEBS record is written, the processor checks each counter to see if it
overflowed and was enabled for PEBS (the corresponding bit in IA32_PEBS_ENABLED was set). If these
conditions are met, then the reset value for each overflowed counter is loaded from the DS Buffer Management
Area. For example, if counter IA32_PMC0 caused a PEBS record to be written, then the value of “PEBS Counter
0 Reset” would be written to counter IA32_PMC0. If a counter is not enabled for PEBS, its value will not be
modified by the PEBS assist.
Performance Counter Prioritization
Performance monitoring interrupts are triggered by a counter transitioning from maximum count to zero
(assuming IA32_PerfEvtSelX.INT is set). This same transition will cause PEBS hardware to arm, but not trigger.
PEBS hardware triggers upon detection of the first PEBS event after the PEBS hardware has been armed (a 0 to 1
transition of the counter). At this point, a PEBS assist will be undertaken by the processor.
Vol. 3B 18-39
PERFORMANCE MONITORING
Performance counters (fixed and general-purpose) are prioritized in index order. That is, counter IA32_PMC0 takes
precedence over all other counters. Counter IA32_PMC1 takes precedence over counters IA32_PMC2 and
IA32_PMC3, and so on. This means that if simultaneous overflows or PEBS assists occur, the appropriate action will
be taken for the highest priority performance counter. For example, if IA32_PMC1 cause an overflow interrupt and
IA32_PMC2 causes an PEBS assist simultaneously, then the overflow interrupt will be serviced first.
The PEBS threshold interrupt is triggered by the PEBS assist, and is by definition prioritized lower than the PEBS
assist. Hardware will not generate separate interrupts for each counter that simultaneously overflows. Generalpurpose performance counters are prioritized over fixed counters.
If a counter is programmed with a precise (PEBS-enabled) event and programmed to generate a counter overflow
interrupt, the PEBS assist is serviced before the counter overflow interrupt is serviced. If in addition the PEBS interrupt threshold is met, the
threshold interrupt is generated after the PEBS assist completes, followed by the counter overflow interrupt (two
separate interrupts are generated).
Uncore counters may be programmed to interrupt one or more processor cores (see Section 18.8.2). It is possible
for interrupts posted from the uncore facility to occur coincident with counter overflow interrupts from the
processor core. Software must check core and uncore status registers to determine the exact origin of counter
overflow interrupts.
18.8.1.2
Load Latency Performance Monitoring Facility
The load latency facility provides software a means to characterize the average load latency to different levels of
cache/memory hierarchy. This facility requires processor supporting enhanced PEBS record format in the PEBS
buffer, see Table 18-23. This field measures the load latency from load's first dispatch of till final data writeback
from the memory subsystem. The latency is reported for retired demand load operations and in core cycles (it
accounts for re-dispatches).
To use this feature software must assure:
•
One of the IA32_PERFEVTSELx MSR is programmed to specify the event unit MEM_INST_RETIRED, and the
LATENCY_ABOVE_THRESHOLD event mask must be specified (IA32_PerfEvtSelX[15:0] = 100H). The corresponding counter IA32_PMCx will accumulate event counts for architecturally visible loads which exceed the
programmed latency threshold specified separately in a MSR. Stores are ignored when this event is
programmed. The CMASK or INV fields of the IA32_PerfEvtSelX register used for counting load latency must be
0. Writing other values will result in undefined behavior.
•
The MSR_PEBS_LD_LAT_THRESHOLD MSR is programmed with the desired latency threshold in core clock
cycles. Loads with latencies greater than this value are eligible for counting and latency data reporting. The
minimum value that may be programmed in this register is 3 (the minimum detectable load latency is 4 core
clock cycles).
•
The PEBS enable bit in the IA32_PEBS_ENABLE register is set for the corresponding IA32_PMCx counter
register. This means that both the PEBS_EN_CTRX and LL_EN_CTRX bits must be set for the counter(s) of
interest. For example, to enable load latency on counter IA32_PMC0, the IA32_PEBS_ENABLE register must be
programmed with the 64-bit value 00000001_00000001H.
When the load-latency facility is enabled, load operations are randomly selected by hardware and tagged to carry
information related to data source locality and latency. Latency and data source information of tagged loads are
updated internally.
When a PEBS assist occurs, the last update of latency and data source information are captured by the assist and
written as part of the PEBS record. The PEBS sample after value (SAV), specified in PEBS CounterX Reset, operates
orthogonally to the tagging mechanism. Loads are randomly tagged to collect latency data. The SAV controls the
number of tagged loads with latency information that will be written into the PEBS record field by the PEBS assists.
The load latency data written to the PEBS record will be for the last tagged load operation which retired just before
the PEBS assist was invoked.
The load-latency information written into a PEBS record (see Table 18-23, bytes AFH:98H) consists of:
•
•
Data Linear Address: This is the linear address of the target of the load operation.
Latency Value: This is the elapsed cycles of the tagged load operation between dispatch to GO, measured in
processor core clock domain.
18-40 Vol. 3B
PERFORMANCE MONITORING
•
Data Source: The encoded value indicates the origin of the data obtained by the load instruction. The
encoding is shown in Table 18-24. In the descriptions local memory refers to system memory physically
attached to a processor package, and remote memory referrals to system memory physically attached to
another processor package.
Table 18-24. Data Source Encoding for Load Latency Record
Encoding
Description
00H
Unknown L3 cache miss
01H
Minimal latency core cache hit. This request was satisfied by the L1 data cache.
02H
Pending core cache HIT. Outstanding core cache miss to same cache-line address was already underway.
03H
This data request was satisfied by the L2.
04H
L3 HIT. Local or Remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping).
05H
L3 HIT. Local or Remote home requests that hit the L3 cache and was serviced by another processor core with a cross
core snoop where no modified copies were found. (clean).
06H
L3 HIT. Local or Remote home requests that hit the L3 cache and was serviced by another processor core with a cross
core snoop where modified copies were found. (HITM).
07H1
Reserved/LLC Snoop HitM. Local or Remote home requests that hit the last level cache and was serviced by another
core with a cross core snoop where modified copies found
08H
L3 MISS. Local homed requests that missed the L3 cache and was serviced by forwarded data following a cross
package snoop where no modified copies found. (Remote home requests are not counted).
09H
Reserved
0AH
L3 MISS. Local home requests that missed the L3 cache and was serviced by local DRAM (go to shared state).
0BH
L3 MISS. Remote home requests that missed the L3 cache and was serviced by remote DRAM (go to shared state).
0CH
L3 MISS. Local home requests that missed the L3 cache and was serviced by local DRAM (go to exclusive state).
0DH
L3 MISS. Remote home requests that missed the L3 cache and was serviced by remote DRAM (go to exclusive state).
0EH
I/O, Request of input/output operation
0FH
The request was to un-cacheable memory.
NOTES:
1. Bit 7 is supported only for processor with CPUID DisplayFamily_DisplayModel signature of 06_2A, and 06_2E; otherwise it is
reserved.
The layout of MSR_PEBS_LD_LAT_THRESHOLD is shown in Figure 18-23.
63
1615
0
THRHLD - Load latency threshold
Reserved
RESET Value — 00000000_00000000H
Figure 18-23. Layout of MSR_PEBS_LD_LAT MSR
Bits 15:0 specifies the threshold load latency in core clock cycles. Performance events with latencies greater than
this value are counted in IA32_PMCx and their latency information is reported in the PEBS record. Otherwise, they
are ignored. The minimum value that may be programmed in this field is 3.
Vol. 3B 18-41
PERFORMANCE MONITORING
18.8.1.3
Off-core Response Performance Monitoring in the Processor Core
Programming a performance event using the off-core response facility can choose any of the four
IA32_PERFEVTSELx MSR with specific event codes and predefine mask bit value. Each event code for off-core
response monitoring requires programming an associated configuration MSR, MSR_OFFCORE_RSP_0. There is only
one off-core response configuration MSR. Table 18-25 lists the event code, mask value and additional off-core
configuration MSR that must be programmed to count off-core response events using IA32_PMCx.
Table 18-25. Off-Core Response Event Encoding
Event code in
IA32_PERFEVTSELx
Mask Value in
IA32_PERFEVTSELx
Required Off-core Response MSR
B7H
01H
MSR_OFFCORE_RSP_0 (address 1A6H)
The layout of MSR_OFFCORE_RSP_0 is shown in Figure 18-24. Bits 7:0 specifies the request type of a transaction
request to the uncore. Bits 15:8 specifies the response of the uncore subsystem.
63
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPONSE TYPE — NON_DRAM (R/W)
RESPONSE TYPE — LOCAL_DRAM (R/W)
RESPONSE TYPE — REMOTE_DRAM (R/W)
RESPONSE TYPE — REMOTE_CACHE_FWD (R/W)
RESPONSE TYPE — RESERVED
RESPONSE TYPE — OTHER_CORE_HITM (R/W)
RESPONSE TYPE — OTHER_CORE_HIT_SNP (R/W)
RESPONSE TYPE — UNCORE_HIT (R/W)
REQUEST TYPE — OTHER (R/W)
REQUEST TYPE — PF_IFETCH (R/W)
REQUEST TYPE — PF_RFO (R/W)
REQUEST TYPE — PF_DATA_RD (R/W)
REQUEST TYPE — WB (R/W)
REQUEST TYPE — DMND_IFETCH (R/W)
REQUEST TYPE — DMND_RFO (R/W)
REQUEST TYPE — DMND_DATA_RD (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-24. Layout of MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 to Configure Off-core Response Events
Table 18-26. MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 Bit Field Definition
Bit Name
Offset
Description
DMND_DATA_RD
0
(R/W). Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well
as demand data page table entry cacheline reads. Does not count L2 data read prefetches or
instruction fetches.
DMND_RFO
1
(R/W). Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated
by a write to data cacheline. Does not count L2 RFO.
DMND_IFETCH
2
(R/W). Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2
code read prefetches.
WB
3
(R/W). Counts the number of writeback (modified to exclusive) transactions.
PF_DATA_RD
4
(R/W). Counts the number of data cacheline reads generated by L2 prefetchers.
PF_RFO
5
(R/W). Counts the number of RFO requests generated by L2 prefetchers.
18-42 Vol. 3B
PERFORMANCE MONITORING
Table 18-26. MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 Bit Field Definition (Contd.)
Bit Name
Offset
Description
PF_IFETCH
6
(R/W). Counts the number of code reads generated by L2 prefetchers.
OTHER
7
(R/W). Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes,
WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock.
UNCORE_HIT
8
(R/W). L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions
required (snooping).
OTHER_CORE_HI
T_SNP
9
(R/W). L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by
another core with a cross core snoop where no modified copies were found (clean).
OTHER_CORE_HI
TM
10
(R/W). L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by
another core with a cross core snoop where modified copies were found (HITM).
Reserved
11
Reserved
REMOTE_CACHE_ 12
FWD
(R/W). L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data
following a cross package snoop where no modified copies found. (Remote home requests are not
counted)
REMOTE_DRAM
13
(R/W). L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM.
LOCAL_DRAM
14
(R/W). L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM.
NON_DRAM
15
(R/W). Non-DRAM requests that were serviced by IOH.
18.8.2
Performance Monitoring Facility in the Uncore
The “uncore” in Intel microarchitecture code name Nehalem refers to subsystems in the physical processor
package that are shared by multiple processor cores. Some of the sub-systems in the uncore include the L3 cache,
Intel QuickPath Interconnect link logic, and integrated memory controller. The performance monitoring facilities
inside the uncore operates in the same clock domain as the uncore (U-clock domain), which is usually different
from the processor core clock domain. The uncore performance monitoring facilities described in this section apply
to Intel Xeon processor 5500 series and processors with the following CPUID signatures: 06_1AH, 06_1EH, 06_1FH
(see Chapter 35). An overview of the uncore performance monitoring facilities is described separately.
The performance monitoring facilities available in the U-clock domain consist of:
•
Eight General-purpose counters (MSR_UNCORE_PerfCntr0 through MSR_UNCORE_PerfCntr7). The counters
are 48 bits wide. Each counter is associated with a configuration MSR, MSR_UNCORE_PerfEvtSelx, to specify
event code, event mask and other event qualification fields. A set of global uncore performance counter
enabling/overflow/status control MSRs are also provided for software.
•
Performance monitoring in the uncore provides an address/opcode match MSR that provides event qualification
control based on address value or QPI command opcode.
•
One fixed-function counter, MSR_UNCORE_FixedCntr0. The fixed-function uncore counter increments at the
rate of the U-clock when enabled.
The frequency of the uncore clock domain can be determined from the uncore clock ratio which is available in
the PCI configuration space register at offset C0H under device number 0 and Function 0.
18.8.2.1
Uncore Performance Monitoring Management Facility
MSR_UNCORE_PERF_GLOBAL_CTRL provides bit fields to enable/disable general-purpose and fixed-function counters in the uncore. Figure 18-25 shows the layout of MSR_UNCORE_PERF_GLOBAL_CTRL for an uncore that is
shared by four processor cores in a physical package.
•
EN_PCn (bit n, n = 0, 7): When set, enables counting for the general-purpose uncore counter
MSR_UNCORE_PerfCntr n.
•
EN_FC0 (bit 32): When set, enables counting for the fixed-function uncore counter MSR_UNCORE_FixedCntr0.
Vol. 3B 18-43
PERFORMANCE MONITORING
•
EN_PMI_COREn (bit n, n = 0, 3 if four cores are present): When set, processor core n is programmed to receive
an interrupt signal from any interrupt enabled uncore counter. PMI delivery due to an uncore counter overflow
is enabled by setting IA32_DEBUGCTL.Offcore_PMI_EN to 1.
•
PMI_FRZ (bit 63): When set, all U-clock uncore counters are disabled when any one of them signals a
performance interrupt. Software must explicitly re-enable the counter by setting the enable bits in
MSR_UNCORE_PERF_GLOBAL_CTRL upon exit from the ISR.
63 62
51 50 49 48
32 31
8 7 6 5 43 2 1 0
PMI_FRZ (R/W)
EN_PMI_CORE3 (R/W)
EN_PMI_CORE2 (R/W)
EN_PMI_CORE1 (R/W)
EN_PMI_CORE0 (R/W)
EN_FC0 (R/W)
EN_PC7 (R/W)
EN_PC6 (R/W)
EN_PC5 (R/W)
EN_PC4 (R/W)
EN_PC3 (R/W)
EN_PC2 (R/W)
EN_PC1 (R/W)
EN_PC0 (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-25. Layout of MSR_UNCORE_PERF_GLOBAL_CTRL MSR
MSR_UNCORE_PERF_GLOBAL_STATUS provides overflow status of the U-clock performance counters in the
uncore. This is a read-only register. If an overflow status bit is set the corresponding counter has overflowed. The
register provides a condition change bit (bit 63) which can be quickly checked by software to determine if a significant change has occurred since the last time the condition change status was cleared. Figure 18-26 shows the
layout of MSR_UNCORE_PERF_GLOBAL_STATUS.
•
OVF_PCn (bit n, n = 0, 7): When set, indicates general-purpose uncore counter MSR_UNCORE_PerfCntr n has
overflowed.
•
OVF_FC0 (bit 32): When set, indicates the fixed-function uncore counter MSR_UNCORE_FixedCntr0 has
overflowed.
•
•
OVF_PMI (bit 61): When set indicates that an uncore counter overflowed and generated an interrupt request.
CHG (bit 63): When set indicates that at least one status bit in MSR_UNCORE_PERF_GLOBAL_STATUS register
has changed state.
MSR_UNCORE_PERF_GLOBAL_OVF_CTRL allows software to clear the status bits in the
UNCORE_PERF_GLOBAL_STATUS register. This is a write-only register, and individual status bits in the global
status register are cleared by writing a binary one to the corresponding bit in this register. Writing zero to any bit
position in this register has no effect on the uncore PMU hardware.
18-44 Vol. 3B
PERFORMANCE MONITORING
63 62 61 60
32 31
8 7 6 5 43 2 1 0
CHG (R/W)
OVF_PMI (R/W)
OVF_FC0 (R/O)
OVF_PC7 (R/O)
OVF_PC6 (R/O)
OVF_PC5 (R/O)
OVF_PC4 (R/O)
OVF_PC3 (R/O)
OVF_PC2 (R/O)
OVF_PC1 (R/O)
OVF_PC0 (R/O)
Reserved
RESET Value — 00000000_00000000H
Figure 18-26. Layout of MSR_UNCORE_PERF_GLOBAL_STATUS MSR
Figure 18-27 shows the layout of MSR_UNCORE_PERF_GLOBAL_OVF_CTRL.
63 62 61 60
32 31
8 7 6 5 43 2 1 0
CLR_CHG (WO1)
CLR_OVF_PMI (WO1)
CLR_OVF_FC0 (WO1)
CLR_OVF_PC7 (WO1)
CLR_OVF_PC6 (WO1)
CLR_OVF_PC5 (WO1)
CLR_OVF_PC4 (WO1)
CLR_OVF_PC3 (WO1)
CLR_OVF_PC2 (WO1)
CLR_OVF_PC1 (WO1)
CLR_OVF_PC0 (WO1)
Reserved
RESET Value — 00000000_00000000H
Figure 18-27. Layout of MSR_UNCORE_PERF_GLOBAL_OVF_CTRL MSR
•
CLR_OVF_PCn (bit n, n = 0, 7): Set this bit to clear the overflow status for general-purpose uncore counter
MSR_UNCORE_PerfCntr n. Writing a value other than 1 is ignored.
•
CLR_OVF_FC0 (bit 32): Set this bit to clear the overflow status for the fixed-function uncore counter
MSR_UNCORE_FixedCntr0. Writing a value other than 1 is ignored.
•
CLR_OVF_PMI (bit 61): Set this bit to clear the OVF_PMI flag in MSR_UNCORE_PERF_GLOBAL_STATUS. Writing
a value other than 1 is ignored.
•
CLR_CHG (bit 63): Set this bit to clear the CHG flag in MSR_UNCORE_PERF_GLOBAL_STATUS register. Writing
a value other than 1 is ignored.
Vol. 3B 18-45
PERFORMANCE MONITORING
18.8.2.2
Uncore Performance Event Configuration Facility
MSR_UNCORE_PerfEvtSel0 through MSR_UNCORE_PerfEvtSel7 are used to select performance event and
configure the counting behavior of the respective uncore performance counter. Each uncore PerfEvtSel MSR is
paired with an uncore performance counter. Each uncore counter must be locally configured using the corresponding MSR_UNCORE_PerfEvtSelx and counting must be enabled using the respective EN_PCx bit in
MSR_UNCORE_PERF_GLOBAL_CTRL. Figure 18-28 shows the layout of MSR_UNCORE_PERFEVTSELx.
63
31
24 23 22 21 20 19 18 17 16 15
Counter Mask
(CMASK)
8 7
Unit Mask (UMASK)
INV—Invert counter mask
EN—Enable counters
PMI—Enable PMI on overflow
E—Edge detect
OCC_CTR_RST—Rest Queue Occ
0
Event Select
Reserved
RESET Value — 00000000_00000000H
Figure 18-28. Layout of MSR_UNCORE_PERFEVTSELx MSRs
•
•
•
Event Select (bits 7:0): Selects the event logic unit used to detect uncore events.
•
Edge Detect (bit 18): When set causes the counter to increment when a deasserted to asserted transition
occurs for the conditions that can be expressed by any of the fields in this register.
•
PMI (bit 20): When set, the uncore will generate an interrupt request when this counter overflowed. This
request will be routed to the logical processors as enabled in the PMI enable bits (EN_PMI_COREx) in the
register MSR_UNCORE_PERF_GLOBAL_CTRL.
•
EN (bit 22): When clear, this counter is locally disabled. When set, this counter is locally enabled and counting
starts when the corresponding EN_PCx bit in MSR_UNCORE_PERF_GLOBAL_CTRL is set.
•
INV (bit 23): When clear, the Counter Mask field is interpreted as greater than or equal to. When set, the
Counter Mask field is interpreted as less than.
•
Counter Mask (bits 31:24): When this field is clear, it has no effect on counting. When set to a value other than
zero, the logical processor compares this field to the event counts on each core clock cycle. If INV is clear and
the event counts are greater than or equal to this field, the counter is incremented by one. If INV is set and the
event counts are less than this field, the counter is incremented by one. Otherwise the counter is not incremented.
Unit Mask (bits 15:8) : Condition qualifiers for the event selection logic specified in the Event Select field.
OCC_CTR_RST (bit17): When set causes the queue occupancy counter associated with this event to be cleared
(zeroed). Writing a zero to this bit will be ignored. It will always read as a zero.
Figure 18-29 shows the layout of MSR_UNCORE_FIXED_CTR_CTRL.
63
8 7 6 5 43 2 1 0
PMI - Generate PMI on overflow
EN - Enable
Reserved
RESET Value — 00000000_00000000H
Figure 18-29. Layout of MSR_UNCORE_FIXED_CTR_CTRL MSR
18-46 Vol. 3B
PERFORMANCE MONITORING
•
EN (bit 0): When clear, the uncore fixed-function counter is locally disabled. When set, it is locally enabled and
counting starts when the EN_FC0 bit in MSR_UNCORE_PERF_GLOBAL_CTRL is set.
•
PMI (bit 2): When set, the uncore will generate an interrupt request when the uncore fixed-function counter
overflowed. This request will be routed to the logical processors as enabled in the PMI enable bits
(EN_PMI_COREx) in the register MSR_UNCORE_PERF_GLOBAL_CTRL.
Both the general-purpose counters (MSR_UNCORE_PerfCntr) and the fixed-function counter
(MSR_UNCORE_FixedCntr0) are 48 bits wide. They support both counting and interrupt based sampling usages.
The event logic unit can filter event counts to specific regions of code or transaction types incoming to the home
node logic.
18.8.2.3
Uncore Address/Opcode Match MSR
The Event Select field [7:0] of MSR_UNCORE_PERFEVTSELx is used to select different uncore event logic unit.
When the event “ADDR_OPCODE_MATCH” is selected in the Event Select field, software can filter uncore performance events according to transaction address and certain transaction responses. The address filter and transaction response filtering requires the use of MSR_UNCORE_ADDR_OPCODE_MATCH register. The layout is shown in
Figure 18-30.
63
60
48 47
40 39
Opcode
3 2 0
ADDR
MatchSel—Select addr/Opcode
Opcode—Opcode and Message
ADDR—Bits 39:4 of physical address
Reserved
RESET Value — 00000000_00000000H
Figure 18-30. Layout of MSR_UNCORE_ADDR_OPCODE_MATCH MSR
•
Addr (bits 39:3): The physical address to match if “MatchSel“ field is set to select address match. The uncore
performance counter will increment if the lowest 40-bit incoming physical address (excluding bits 2:0) for a
transaction request matches bits 39:3.
•
Opcode (bits 47:40) : Bits 47:40 allow software to filter uncore transactions based on QPI link message
class/packed header opcode. These bits are consists two sub-fields:
— Bits 43:40 specify the QPI packet header opcode,
— Bits 47:44 specify the QPI message classes.
Table 18-27 lists the encodings supported in the opcode field.
Vol. 3B 18-47
PERFORMANCE MONITORING
Table 18-27. Opcode Field Encoding for MSR_UNCORE_ADDR_OPCODE_MATCH
Opcode [43:40]
QPI Message Class
Home Request
Snoop Response
Data Response
[47:44] = 0000B
[47:44] = 0001B
[47:44] = 1110B
1
DMND_IFETCH
2
2
WB
3
3
PF_DATA_RD
4
4
PF_RFO
5
5
PF_IFETCH
6
6
OTHER
7
7
NON_DRAM
15
15
•
MatchSel (bits 63:61): Software specifies the match criteria according to the following encoding:
— 000B: Disable addr_opcode match hardware
— 100B: Count if only the address field matches,
— 010B: Count if only the opcode field matches
— 110B: Count if either opcode field matches or the address field matches
— 001B: Count only if both opcode and address field match
— Other encoding are reserved
18.8.3
Intel® Xeon® Processor 7500 Series Performance Monitoring Facility
The performance monitoring facility in the processor core of Intel® Xeon® processor 7500 series are the same as
those supported in Intel Xeon processor 5500 series. The uncore subsystem in Intel Xeon processor 7500 series are
significantly different The uncore performance monitoring facility consist of many distributed units associated with
individual logic control units (referred to as boxes) within the uncore subsystem. A high level block diagram of the
various box units of the uncore is shown in Figure 18-31.
Uncore PMUs are programmed via MSR interfaces. Each of the distributed uncore PMU units have several generalpurpose counters. Each counter requires an associated event select MSR, and may require additional MSRs to
configure sub-event conditions. The uncore PMU MSRs associated with each box can be categorized based on its
functional scope: per-counter, per-box, or global across the uncore. The number counters available in each box
type are different. Each box generally provides a set of MSRs to enable/disable, check status/overflow of multiple
counters within each box.
18-48 Vol. 3B
PERFORMANCE MONITORING
L3 Cache
CBox
CBox
CBox
CBox
CBox
SBox
CBox
CBox
CBox
SBox
SMI Channels
PBox
MBox
BBox
RBox
BBox
MBox
PBox
SMI Channels
WBox
PBox
PBox
PBox
PBox
UBox
4 Intel QPI Links
Figure 18-31. Distributed Units of the Uncore of Intel® Xeon® Processor 7500 Series
Table 18-28 summarizes the number MSRs for uncore PMU for each box.
Table 18-28. Uncore PMU MSR Summary
Box
# of Boxes
Counters per Box
Counter
Width
General
Purpose
Global
Enable
Sub-control MSRs
C-Box
8
6
48
Yes
per-box
None
S-Box
2
4
48
Yes
per-box
Match/Mask
B-Box
2
4
48
Yes
per-box
Match/Mask
M-Box
2
6
48
Yes
per-box
Yes
R-Box
1
16 ( 2 port, 8 per port)
48
Yes
per-box
Yes
W-Box
1
4
48
Yes
per-box
None
1
48
No
per-box
None
1
48
Yes
uncore
None
U-Box
1
The W-Box provides 4 general-purpose counters, each requiring an event select configuration MSR, similar to the
general-purpose counters in other boxes. There is also a fixed-function counter that increments clockticks in the
uncore clock domain.
For C,S,B,M,R, and W boxes, each box provides an MSR to enable/disable counting, configuring PMI of multiple
counters within the same box, this is somewhat similar the “global control“ programming interface,
IA32_PERF_GLOBAL_CTRL, offered in the core PMU. Similarly status information and counter overflow control for
multiple counters within the same box are also provided in C,S,B,M,R, and W boxes.
In the U-Box, MSR_U_PMON_GLOBAL_CTL provides overall uncore PMU enable/disable and PMI configuration
control. The scope of status information in the U-box is at per-box granularity, in contrast to the per-box status
information MSR (in the C,S,B,M,R, and W boxes) providing status information of individual counter overflow. The
difference in scope also apply to the overflow control MSR in the U-Box versus those in the other Boxes.
Vol. 3B 18-49
PERFORMANCE MONITORING
The individual MSRs that provide uncore PMU interfaces are listed in Chapter 35, Table 35-15 under the general
naming style of MSR_%box#%_PMON_%scope_function%, where %box#% designates the type of box and zerobased index if there are more the one box of the same type, %scope_function% follows the examples below:
•
Multi-counter enabling MSRs: MSR_U_PMON_GLOBAL_CTL, MSR_S0_PMON_BOX_CTL,
MSR_C7_PMON_BOX_CTL, etc.
•
Multi-counter status MSRs: MSR_U_PMON_GLOBAL_STATUS, MSR_S0_PMON_BOX_STATUS,
MSR_C7_PMON_BOX_STATUS, etc.
•
Multi-counter overflow control MSRs: MSR_U_PMON_GLOBAL_OVF_CTL, MSR_S0_PMON_BOX_OVF_CTL,
MSR_C7_PMON_BOX_OVF_CTL, etc.
•
Performance counters MSRs: the scope is implicitly per counter, e.g. MSR_U_PMON_CTR,
MSR_S0_PMON_CTR0, MSR_C7_PMON_CTR5, etc.
•
Event select MSRs: the scope is implicitly per counter, e.g. MSR_U_PMON_EVNT_SEL,
MSR_S0_PMON_EVNT_SEL0, MSR_C7_PMON_EVNT_SEL5, etc
•
Sub-control MSRs: the scope is implicitly per-box granularity, e.g. MSR_M0_PMON_TIMESTAMP,
MSR_R0_PMON_IPERF0_P1, MSR_S1_PMON_MATCH.
Details of uncore PMU MSR bit field definitions can be found in a separate document “Intel Xeon Processor 7500
Series Uncore Performance Monitoring Guide“.
18.8.4
Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name
Westmere
All of the performance monitoring programming interfaces (architectural and non-architectural core PMU facilities,
and uncore PMU) described in Section 18.8 also apply to processors based on Intel® microarchitecture code name
Westmere.
Table 18-25 describes a non-architectural performance monitoring event (event code 0B7H) and associated
MSR_OFFCORE_RSP_0 (address 1A6H) in the core PMU. This event and a second functionally equivalent offcore
response event using event code 0BBH and MSR_OFFCORE_RSP_1 (address 1A7H) are supported in processors
based on Intel microarchitecture code name Westmere. The event code and event mask definitions of Non-architectural performance monitoring events are listed in Table 19-26.
The load latency facility is the same as described in Section 18.8.1.2, but added enhancement to provide more
information in the data source encoding field of each load latency record. The additional information relates to
STLB_MISS and LOCK, see Table 18-33.
18.8.5
Intel® Xeon® Processor E7 Family Performance Monitoring Facility
The performance monitoring facility in the processor core of the Intel® Xeon® processor E7 family is the same as
those supported in the Intel Xeon processor 5600 series3. The uncore subsystem in the Intel Xeon processor E7
family is similar to those of the Intel Xeon processor 7500 series. The high level construction of the uncore subsystem is similar to that shown in Figure 18-31, with the additional capability that up to 10 C-Box units are
supported.
Table 18-29 summarizes the number MSRs for uncore PMU for each box.
Table 18-29. Uncore PMU MSR Summary for Intel® Xeon® Processor E7 Family
Box
# of Boxes
Counters per Box
Counter
Width
General
Purpose
Global
Enable
Sub-control MSRs
C-Box
10
6
48
Yes
per-box
None
S-Box
2
4
48
Yes
per-box
Match/Mask
3. Exceptions are indicated for event code 0FH in Table 19-19; and valid bits of data source encoding field of each load
latency record is limited to bits 5:4 of Table 18-33.
18-50 Vol. 3B
PERFORMANCE MONITORING
Table 18-29. Uncore PMU MSR Summary for Intel® Xeon® Processor E7 Family
Box
# of Boxes
Counters per Box
Counter
Width
General
Purpose
Global
Enable
Sub-control MSRs
B-Box
2
4
48
Yes
per-box
Match/Mask
M-Box
2
6
48
Yes
per-box
Yes
R-Box
1
16 ( 2 port, 8 per port)
48
Yes
per-box
Yes
W-Box
1
4
48
Yes
per-box
None
1
48
No
per-box
None
1
48
Yes
uncore
None
U-Box
1
Details of the uncore performance monitoring facility of Intel Xeon Processor E7 family is available in the “Intel®
Xeon® Processor E7 Uncore Performance Monitoring Programming Reference Manual”.
18.9
PERFORMANCE MONITORING FOR PROCESSORS BASED ON INTEL®
MICROARCHITECTURE CODE NAME SANDY BRIDGE
Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series, and Intel® Xeon® processor
E3-1200 family are based on Intel microarchitecture code name Sandy Bridge; this section describes the performance monitoring facilities provided in the processor core. The core PMU supports architectural performance monitoring capability with version ID 3 (see Section 18.2.3) and a host of non-architectural monitoring capabilities.
Architectural performance monitoring version 3 capabilities are described in Section 18.2.3.
The core PMU’s capability is similar to those described in Section 18.8.1 and Section 18.8.4, with some differences
and enhancements relative to Intel microarchitecture code name Westmere summarized in Table 18-30.
Table 18-30. Core PMU Comparison
Intel® microarchitecture code
name Sandy Bridge
Intel® microarchitecture code
name Westmere
# of Fixed counters per
thread
3
3
# of general-purpose
counters per core
8
8
Counter width (R,W)
R:48, W: 32/48
R:48, W:32
See Section 18.2.2.
# of programmable counters
per thread
4 or (8 if a core not shared by two
threads)
4
Use CPUID to enumerate # of
counters.
PMI Overhead Mitigation
• Freeze_Perfmon_on_PMI with
legacy semantics.
• Freeze_on_LBR with legacy
semantics for branch profiling.
• Freeze_while_SMM.
• Freeze_Perfmon_on_PMI
with legacy semantics.
• Freeze_on_LBR with legacy
semantics for branch
profiling.
• Freeze_while_SMM.
See Section 17.4.7.
Processor Event Based
Sampling (PEBS) Events
See Table 18-32.
See Table 18-10.
IA32_PMC4-IA32_PMC7 do
not support PEBS.
PEBS-Load Latency
See Section 18.9.4.2;
Data source encoding
Box
Comment
Use CPUID to enumerate # of
counters.
• Data source encoding
• STLB miss encoding
• Lock transaction encoding
PEBS-Precise Store
Section 18.9.4.3
No
Vol. 3B 18-51
PERFORMANCE MONITORING
Table 18-30. Core PMU Comparison (Contd.)
Intel® microarchitecture code
name Sandy Bridge
Intel® microarchitecture code
name Westmere
PEBS-PDIR
Yes (using precise
INST_RETIRED.ALL).
No
Off-core Response Event
MSR 1A6H and 1A7H, extended
request and response types.
MSR 1A6H and 1A7H, limited
response types.
Box
Comment
Nehalem supports 1A6H
only.
Global Counter Control Facilities In Intel® Microarchitecture Code Name Sandy Bridge
18.9.1
The number of general-purpose performance counters visible to a logical processor can vary across Processors
based on Intel microarchitecture code name Sandy Bridge. Software must use CPUID to determine the number
performance counters/event select registers (See Section 18.2.1.1).
63
35 34 33 32 31
8 7 6 5 4 3 2 10
FIXED_CTR2 enable
FIXED_CTR1 enable
FIXED_CTR0 enable
PMC7_EN (if PMC7 present)
PMC6_EN (if PMC6 present)
PMC5_EN (if PMC5 present)
PMC4_EN (if PMC4 present)
PMC3_EN
PMC2_EN
PMC1_EN
PMC0_EN
Reserved
Valid if CPUID.0AH:EAX[15:8] = 8, else reserved.
Figure 18-32. IA32_PERF_GLOBAL_CTRL MSR in Intel® Microarchitecture Code Name Sandy Bridge
Figure 18-15 depicts the layout of IA32_PERF_GLOBAL_CTRL MSR. The enable bits (PMC4_EN, PMC5_EN,
PMC6_EN, PMC7_EN) corresponding to IA32_PMC4-IA32_PMC7 are valid only if CPUID.0AH:EAX[15:8] reports a
value of ‘8’. If CPUID.0AH:EAX[15:8] = 4, attempts to set the invalid bits will cause #GP.
Each enable bit in IA32_PERF_GLOBAL_CTRL is AND’ed with the enable bits for all privilege levels in the respective
IA32_PERFEVTSELx or IA32_PERF_FIXED_CTR_CTRL MSRs to start/stop the counting of respective counters.
Counting is enabled if the AND’ed results is true; counting is disabled when the result is false.
IA32_PERF_GLOBAL_STATUS MSR provides single-bit status used by software to query the overflow condition of
each performance counter. IA32_PERF_GLOBAL_STATUS[bit 62] indicates overflow conditions of the DS area data
buffer (see Figure 18-33). A value of 1 in each bit of the PMCx_OVF field indicates an overflow condition has
occurred in the associated counter.
18-52 Vol. 3B
PERFORMANCE MONITORING
63 62 61
35 34 33 32 31
8 7 6 5 4 3 2 10
CondChgd
Ovf_DSBuffer
Ovf_UncorePMU
FIXED_CTR2 Overflow (RO)
FIXED_CTR1 Overflow (RO)
FIXED_CTR0 Overflow (RO)
PMC7_OVF (RO, If PMC7 present)
PMC6_OVF (RO, If PMC6 present)
PMC5_OVF (RO, If PMC5 present)
PMC4_OVF (RO, If PMC4 present)
PMC3_OVF (RO)
PMC2_OVF (RO)
PMC1_OVF (RO)
PMC0_OVF (RO)
Valid if CPUID.0AH:EAX[15:8] = 8; else reserved
Reserved
Figure 18-33. IA32_PERF_GLOBAL_STATUS MSR in Intel® Microarchitecture Code Name Sandy Bridge
When a performance counter is configured for PEBS, an overflow condition in the counter will arm PEBS. On the
subsequent event following overflow, the processor will generate a PEBS event. On a PEBS event, the processor will
perform bounds checks based on the parameters defined in the DS Save Area (see Section 17.4.9). Upon
successful bounds checks, the processor will store the data record in the defined buffer area, clear the counter
overflow status, and reload the counter. If the bounds checks fail, the PEBS will be skipped entirely. In the event
that the PEBS buffer fills up, the processor will set the OvfBuffer bit in MSR_PERF_GLOBAL_STATUS.
IA32_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow the indicators for general-purpose or fixedfunction counters via a single WRMSR (see Figure 18-34). Clear overflow indications when:
•
•
•
Setting up new values in the event select and/or UMASK field for counting or interrupt based sampling
Reloading counter values to continue sampling
Disabling event counting or interrupt based sampling
63 62
35 34 33 32 31
8 7 6 5 4 3
2 10
ClrCondChgd
ClrOvfDSBuffer
ClrOvfUncore
FIXED_CTR2 ClrOverflow
FIXED_CTR1 ClrOverflow
FIXED_CTR0 ClrOverflow
PMC7_ClrOvf (if PMC7 present)
PMC6_ClrOvf (if PMC6 present)
PMC5_ClrOvf (if PMC5 present)
PMC4_ClrOvf (if PMC4 present)
PMC3_ClrOvf
PMC2_ClrOvf
PMC1_ClrOvf
PMC0_ClrOvf
Reserved
Valid if CPUID.0AH:EAX[15:8] = 8; else reserved
Figure 18-34. IA32_PERF_GLOBAL_OVF_CTRL MSR in Intel microarchitecture code name Sandy Bridge
Vol. 3B 18-53
PERFORMANCE MONITORING
18.9.2
Counter Coalescence
In processors based on Intel microarchitecture code name Sandy Bridge, each processor core implements eight
general-purpose counters. CPUID.0AH:EAX[15:8] will report either 4 or 8 depending specific processor’s product
features.
If a processor core is shared by two logical processors, each logical processors can access 4 counters (IA32_PMC0IA32_PMC3). This is the same as in the prior generation for processors based on Intel microarchitecture code name
Nehalem.
If a processor core is not shared by two logical processors, all eight general-purpose counters are visible, and
CPUID.0AH:EAX[15:8] reports 8. IA32_PMC4-IA32_PMC7 occupy MSR addresses 0C5H through 0C8H. Each
counter is accompanied by an event select MSR (IA32_PERFEVTSEL4-IA32_PERFEVTSEL7).
If CPUID.0AH:EAX[15:8] report 4, access to IA32_PMC4-IA32_PMC7, IA32_PMC4-IA32_PMC7 will cause #GP.
Writing 1’s to bit position 7:4 of IA32_PERF_GLOBAL_CTRL, IA32_PERF_GLOBAL_STATUS, or
IA32_PERF_GLOBAL_OVF_CTL will also cause #GP.
18.9.3
Full Width Writes to Performance Counters
Processors based on Intel microarchitecture code name Sandy Bridge support full-width writes to the generalpurpose counters, IA32_PMCx. Support of full-width writes are enumerated by
IA32_PERF_CAPABILITIES.FW_WRITES[13] (see Section 18.2.4).
The default behavior of IA32_PMCx is unchanged, i.e. WRMSR to IA32_PMCx results in a sign-extended 32-bit
value of the input EAX written into IA32_PMCx. Full-width writes must issue WRMSR to a dedicated alias MSR
address for each IA32_PMCx.
Software must check the presence of full-width write capability and the presence of the alias address IA32_A_PMCx
by testing IA32_PERF_CAPABILITIES[13].
18.9.4
PEBS Support in Intel® Microarchitecture Code Name Sandy Bridge
Processors based on Intel microarchitecture code name Sandy Bridge support PEBS, similar to those offered in
prior generation, with several enhanced features. The key components and differences of PEBS facility relative to
Intel microarchitecture code name Westmere is summarized in Table 18-31.
Table 18-31. PEBS Facility Comparison
Box
Intel® microarchitecture code name
Sandy Bridge
Intel® microarchitecture
code name Westmere
Comment
Valid IA32_PMCx
PMC0-PMC3
PMC0-PMC3
No PEBS on PMC4-PMC7.
PEBS Buffer Programming
Section 18.8.1.1
Section 18.8.1.1
Unchanged
IA32_PEBS_ENABLE
Layout
Figure 18-35
Figure 18-21
PEBS record layout
Physical Layout same as Table 18-23.
Table 18-23
Enhanced fields at offsets 98H,
A0H, A8H.
PEBS Events
See Table 18-32.
See Table 18-10.
IA32_PMC4-IA32_PMC7 do not
support PEBS.
PEBS-Load Latency
See Table 18-33.
Table 18-24
PEBS-Precise Store
Yes; see Section 18.9.4.3.
No
IA32_PMC3 only
PEBS-PDIR
Yes
No
IA32_PMC1 only
PEBS skid from EventingIP
1 (or 2 if micro+macro fusion)
1
SAMPLING Restriction
Small SAV(CountDown) value incur higher overhead than prior
generation.
18-54 Vol. 3B
PERFORMANCE MONITORING
Only IA32_PMC0 through IA32_PMC3 support PEBS.
NOTE
PEBS events are only valid when the following fields of IA32_PERFEVTSELx are all zero: AnyThread,
Edge, Invert, CMask.
In a PMU with PDIR capability, PEBS behavior is unpredictable if IA32_PERFEVTSELx or IA32_PMCx
is changed for a PEBS-enabled counter while an event is being counted. To avoid this, changes to
the programming or value of a PEBS-enabled counter should be performed when the counter is
disabled.
In IA32_PEBS_ENABLE MSR, bit 63 is defined as PS_ENABLE: When set, this enables IA32_PMC3 to capture
precise store information. Only IA32_PMC3 supports the precise store facility. In typical usage of PEBS, the bit
fields in IA32_PEBS_ENABLE are written to when the agent software starts PEBS operation; the enabled bit fields
should be modified only when re-programming another PEBS event or cleared when the agent uses the performance counters for non-PEBS operations.
63 62
36 3534 33 32 31
8 7 6 5 43 2 1 0
PS_EN (R/W)
LL_EN_PMC3 (R/W)
LL_EN_PMC2 (R/W)
LL_EN_PMC1 (R/W)
LL_EN_PMC0 (R/W)
PEBS_EN_PMC3 (R/W)
PEBS_EN_PMC2 (R/W)
PEBS_EN_PMC1 (R/W)
PEBS_EN_PMC0 (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-35. Layout of IA32_PEBS_ENABLE MSR
18.9.4.1
PEBS Record Format
The layout of PEBS records physically identical to those shown in Table 18-23, but the fields at offset 98H, A0H and
A8H have been enhanced to support additional PEBS capabilities.
•
Load/Store Data Linear Address (Offset 98H): This field will contain the linear address of the source of the load,
or linear address of the destination of the store.
•
Data Source /Store Status (Offset A0H):When load latency is enabled, this field will contain three piece of
information (including an encoded value indicating the source which satisfied the load operation). The source
field encodings are detailed in Table 18-24. When precise store is enabled, this field will contain information
indicating the status of the store, as detailed in Table 19.
•
Latency Value/0 (Offset A8H): When load latency is enabled, this field contains the latency in cycles to service
the load. This field is not meaningful when precise store is enabled and will be written to zero in that case. Upon
writing the PEBS record, microcode clears the overflow status bits in the IA32_PERF_GLOBAL_STATUS corresponding to those counters that both overflowed and were enabled in the IA32_PEBS_ENABLE register. The
status bits of other counters remain unaffected.
The number PEBS events has expanded. The list of PEBS events supported in Intel microarchitecture code name
Sandy Bridge is shown in Table 18-32.
Vol. 3B 18-55
PERFORMANCE MONITORING
Table 18-32. PEBS Performance Events for Intel® Microarchitecture Code Name Sandy Bridge
Event Name
Event Select
Sub-event
UMask
INST_RETIRED
C0H
PREC_DIST
01H1
UOPS_RETIRED
C2H
All
01H
Retire_Slots
02H
Conditional
01H
Near_Call
02H
BR_INST_RETIRED
BR_MISP_RETIRED
MEM_UOPS_RETIRED
MEM_LOAD_UOPS_RETIRED
MEM_LOAD_UOPS_LLC_HIT_RETIRED
C4H
C5H
D0H
D1H
D2H
All_branches
04H
Near_Return
08H
Near_Taken
20H
Conditional
01H
Near_Call
02H
All_branches
04H
Not_Taken
10H
Taken
20H
STLB_MISS_LOADS
11H
STLB_MISS_STORE
12H
LOCK_LOADS
21H
SPLIT_LOADS
41H
SPLIT_STORES
42H
ALL_LOADS
81H
ALL_STORES
82H
L1_Hit
01H
L2_Hit
02H
L3_Hit
04H
Hit_LFB
40H
XSNP_Miss
01H
XSNP_Hit
02H
XSNP_Hitm
04H
XSNP_None
08H
NOTES:
1. Only available on IA32_PMC1.
18.9.4.2
Load Latency Performance Monitoring Facility
The load latency facility in Intel microarchitecture code name Sandy Bridge is similar to that in prior microarchitecture. It provides software a means to characterize the average load latency to different levels of cache/memory
hierarchy. This facility requires processor supporting enhanced PEBS record format in the PEBS buffer, see
Table 18-23 and Section 18.9.4.1. This field measures the load latency from load's first dispatch of till final data
writeback from the memory subsystem. The latency is reported for retired demand load operations and in core
cycles (it accounts for re-dispatches).
To use this feature software must assure:
•
One of the IA32_PERFEVTSELx MSR is programmed to specify the event unit MEM_TRANS_RETIRED, and the
LATENCY_ABOVE_THRESHOLD event mask must be specified (IA32_PerfEvtSelX[15:0] = 1CDH). The corresponding counter IA32_PMCx will accumulate event counts for architecturally visible loads which exceed the
18-56 Vol. 3B
PERFORMANCE MONITORING
programmed latency threshold specified separately in a MSR. Stores are ignored when this event is
programmed. The CMASK or INV fields of the IA32_PerfEvtSelX register used for counting load latency must be
0. Writing other values will result in undefined behavior.
•
The MSR_PEBS_LD_LAT_THRESHOLD MSR is programmed with the desired latency threshold in core clock
cycles. Loads with latencies greater than this value are eligible for counting and latency data reporting. The
minimum value that may be programmed in this register is 3 (the minimum detectable load latency is 4 core
clock cycles).
•
The PEBS enable bit in the IA32_PEBS_ENABLE register is set for the corresponding IA32_PMCx counter
register. This means that both the PEBS_EN_CTRX and LL_EN_CTRX bits must be set for the counter(s) of
interest. For example, to enable load latency on counter IA32_PMC0, the IA32_PEBS_ENABLE register must be
programmed with the 64-bit value 00000001.00000001H.
•
When Load latency event is enabled, no other PEBS event can be configured with other counters.
When the load-latency facility is enabled, load operations are randomly selected by hardware and tagged to carry
information related to data source locality and latency. Latency and data source information of tagged loads are
updated internally. The MEM_TRANS_RETIRED event for load latency counts only tagged retired loads. If a load is
cancelled it will not be counted and the internal state of the load latency facility will not be updated. In this case the
hardware will tag the next available load.
When a PEBS assist occurs, the last update of latency and data source information are captured by the assist and
written as part of the PEBS record. The PEBS sample after value (SAV), specified in PEBS CounterX Reset, operates
orthogonally to the tagging mechanism. Loads are randomly tagged to collect latency data. The SAV controls the
number of tagged loads with latency information that will be written into the PEBS record field by the PEBS assists.
The load latency data written to the PEBS record will be for the last tagged load operation which retired just before
the PEBS assist was invoked.
The physical layout of the PEBS records is the same as shown in Table 18-23. The specificity of Data Source entry
at offset A0H has been enhanced to report three piece of information.
Table 18-33. Layout of Data Source Field of Load Latency Record
Field
Position
Description
Source
3:0
See Table 18-24
STLB_MISS
4
0: The load did not miss the STLB (hit the DTLB or STLB).
1: The load missed the STLB.
Lock
5
0: The load was not part of a locked transaction.
1: The load was part of a locked transaction.
Reserved
63:6
Reserved
The layout of MSR_PEBS_LD_LAT_THRESHOLD is the same as shown in Figure 18-23.
18.9.4.3
Precise Store Facility
Processors based on Intel microarchitecture code name Sandy Bridge offer a precise store capability that complements the load latency facility. It provides a means to profile store memory references in the system.
Precise stores leverage the PEBS facility and provide additional information about sampled stores. Having precise
memory reference events with linear address information for both loads and stores can help programmers improve
data structure layout, eliminate remote node references, and identify cache-line conflicts in NUMA systems.
Only IA32_PMC3 can be used to capture precise store information. After enabling this facility, counter overflows
will initiate the generation of PEBS records as previously described in PEBS. Upon counter overflow hardware
captures the linear address and other status information of the next store that retires. This information is then
written to the PEBS record.
To enable the precise store facility, software must complete the following steps. Please note that the precise store
facility relies on the PEBS facility, so the PEBS configuration requirements must be completed before attempting to
capture precise store information.
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PERFORMANCE MONITORING
•
•
Complete the PEBS configuration steps.
•
Set IA32_PEBS_ENABLE[3] and IA32_PEBS_ENABLE[63]. This enables IA32_PMC3 as a PEBS counter and
enables the precise store facility, respectively.
Program the MEM_TRANS_RETIRED.PRECISE_STORE event in IA32_PERFEVTSEL3. Only counter 3
(IA32_PMC3) supports collection of precise store information.
The precise store information written into a PEBS record affects entries at offset 98H, A0H and A8H of Table 18-23.
The specificity of Data Source entry at offset A0H has been enhanced to report three piece of information.
Table 18-34. Layout of Precise Store Information In PEBS Record
Field
Offset Description
Store Data
98H
Linear Address
The linear address of the destination of the store.
Store Status
L1D Hit (Bit 0): The store hit the data cache closest to the core (lowest latency cache) if this bit is set,
otherwise the store missed the data cache.
A0H
STLB Miss (bit 4): The store missed the STLB if set, otherwise the store hit the STLB
Locked Access (bit 5): The store was part of a locked access if set, otherwise the store was not part of a
locked access.
Reserved
18.9.4.4
A8H
Reserved
Precise Distribution of Instructions Retired (PDIR)
Upon triggering a PEBS assist, there will be a finite delay between the time the counter overflows and when the
microcode starts to carry out its data collection obligations. INST_RETIRED is a very common event that is used to
sample where performance bottleneck happened and to help identify its location in instruction address space. Even
if the delay is constant in core clock space, it invariably manifest as variable “skids” in instruction address space.
This creates a challenge for programmers to profile a workload and pinpoint the location of bottlenecks.
The core PMU in processors based on Intel microarchitecture code name Sandy Bridge include a facility referred to
as precise distribution of Instruction Retired (PDIR).
The PDIR facility mitigates the “skid” problem by providing an early indication of when the INST_RETIRED counter
is about to overflow, allowing the machine to more precisely trap on the instruction that actually caused the counter
overflow thus eliminating skid.
PDIR applies only to the INST_RETIRED.ALL precise event, and must use IA32_PMC1 with PerfEvtSel1 property
configured and bit 1 in the IA32_PEBS_ENABLE set to 1. INST_RETIRED.ALL is a non-architectural performance
event, it is not supported in prior generation microarchitectures. Additionally, on processors with CPUID
DisplayFamily_DisplayModel signatures of 06_2A and 06_2D, the tool that programs PDIR should quiesce the rest
of the programmable counters in the core when PDIR is active.
18.9.5
Off-core Response Performance Monitoring
The core PMU in processors based on Intel microarchitecture code name Sandy Bridge provides off-core response
facility similar to prior generation. Off-core response can be programmed only with a specific pair of event select
and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the off-core transaction. Two event codes are dedicated for off-core response event programming. Each
event code for off-core response monitoring requires programming an associated configuration MSR,
MSR_OFFCORE_RSP_x. Table 18-35 lists the event code, mask value and additional off-core configuration MSR
that must be programmed to count off-core response events using IA32_PMCx.
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PERFORMANCE MONITORING
Table 18-35. Off-Core Response Event Encoding
Counter
Event code
UMask
Required Off-core Response MSR
PMC0-3
B7H
01H
MSR_OFFCORE_RSP_0 (address 1A6H)
PMC0-3
BBH
01H
MSR_OFFCORE_RSP_1 (address 1A7H)
The layout of MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 are shown in Figure 18-36 and Figure 18-37. Bits
15:0 specifies the request type of a transaction request to the uncore. Bits 30:16 specifies supplier information,
bits 37:31 specifies snoop response information.
63
37
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
See Figure 18-30
RESPONSE TYPE — Other (R/W)
RESERVED
REQUEST TYPE — STRM_ST (R/W)
REQUEST TYPE — BUS_LOCKS (R/W)
REQUEST TYPE — PF_LLC_IFETCH (R/W)
REQUEST TYPE — PF_LLC_RFO (R/W)
REQUEST TYPE — PF_LLC_DATA_RD (R/W)
REQUEST TYPE — PF_IFETCH (R/W)
REQUEST TYPE — PF_RFO (R/W)
REQUEST TYPE — PF_DATA_RD (R/W)
REQUEST TYPE — WB (R/W)
REQUEST TYPE — DMND_IFETCH (R/W)
REQUEST TYPE — DMND_RFO (R/W)
REQUEST TYPE — DMND_DATA_RD (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-36. Request_Type Fields for MSR_OFFCORE_RSP_x
Table 18-36. MSR_OFFCORE_RSP_x Request_Type Field Definition
Bit Name
Offset Description
DMND_DATA_RD
0
(R/W). Counts the number of demand data reads of full and partial cachelines as well as demand data
page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
DMND_RFO
1
(R/W). Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated
by a write to data cacheline. Does not count L2 RFO prefetches.
DMND_IFETCH
2
(R/W). Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2
code read prefetches.
WB
3
(R/W). Counts the number of writeback (modified to exclusive) transactions.
PF_DATA_RD
4
(R/W). Counts the number of data cacheline reads generated by L2 prefetchers.
PF_RFO
5
(R/W). Counts the number of RFO requests generated by L2 prefetchers.
PF_IFETCH
6
(R/W). Counts the number of code reads generated by L2 prefetchers.
PF_LLC_DATA_RD
7
(R/W). L2 prefetcher to L3 for loads.
PF_LLC_RFO
8
(R/W). RFO requests generated by L2 prefetcher
PF_LLC_IFETCH
9
(R/W). L2 prefetcher to L3 for instruction fetches.
BUS_LOCKS
10
(R/W). Bus lock and split lock requests
STRM_ST
11
(R/W). Streaming store requests
OTHER
15
(R/W). Any other request that crosses IDI, including I/O.
Vol. 3B 18-59
PERFORMANCE MONITORING
63
37 36 35 34 33 32 31
22 21 20 19 18 17 16
RESPONSE TYPE — NON_DRAM (R/W)
RSPNS_SNOOP — HITM (R/W)
RSPNS_SNOOP — HIT_FWD
RSPNS_SNOOP — HIT_NO_FWD (R/W)
RSPNS_SNOOP — SNP_MISS (R/W)
RSPNS_SNOOP — SNP_NOT_NEEDED (R/W)
RSPNS_SNOOP — SNPl_NONE (R/W)
RSPNS_SUPPLIER — RESERVED
RSPNS_SUPPLIER — Local
RSPNS_SUPPLIER — LLC_HITF (R/W)
RSPNS_SUPPLIER — LLC_HITS (R/W)
RSPNS_SUPPLIER — LLC_HITE (R/W)
RSPNS_SUPPLIER — LLC_HITM (R/W)
RSPNS_SUPPLIER — No_SUPP (R/W)
RSPNS_SUPPLIER — ANY (R/W)
Reserved
RESET Value — 00000000_00000000H
Figure 18-37. Response_Supplier and Snoop Info Fields for MSR_OFFCORE_RSP_x
To properly program this extra register, software must set at least one request type bit and a valid response type
pattern. Otherwise, the event count reported will be zero. It is permissible and useful to set multiple request and
response type bits in order to obtain various classes of off-core response events. Although MSR_OFFCORE_RSP_x
allow an agent software to program numerous combinations that meet the above guideline, not all combinations
produce meaningful data.
Table 18-37. MSR_OFFCORE_RSP_x Response Supplier Info Field Definition
Subtype
Bit Name
Offset
Description
Common
Any
16
(R/W). Catch all value for any response types.
Supplier
Info
NO_SUPP
17
(R/W). No Supplier Information available
LLC_HITM
18
(R/W). M-state initial lookup stat in L3.
LLC_HITE
19
(R/W). E-state
LLC_HITS
20
(R/W). S-state
LLC_HITF
21
(R/W). F-state
LOCAL
22
(R/W). Local DRAM Controller
Reserved
30:23
Reserved
To specify a complete offcore response filter, software must properly program bits in the request and response type
fields. A valid request type must have at least one bit set in the non-reserved bits of 15:0. A valid response type
must be a non-zero value of the following expression:
ANY | [(‘OR’ of Supplier Info Bits) & (‘OR’ of Snoop Info Bits)]
If “ANY“ bit is set, the supplier and snoop info bits are ignored.
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PERFORMANCE MONITORING
Table 18-38. MSR_OFFCORE_RSP_x Snoop Info Field Definition
Subtype
Bit Name
Offset
Description
Snoop
Info
SNP_NONE
31
(R/W). No details on snoop-related information
SNP_NOT_NEEDED 32
(R/W). No snoop was needed to satisfy the request.
SNP_MISS
(R/W). A snoop was needed and it missed all snooped caches:
33
-For LLC Hit, ReslHitl was returned by all cores
-For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.
SNP_NO_FWD
34
(R/W). A snoop was needed and it hits in at least one snooped cache. Hit denotes a cacheline was valid before snoop effect. This includes:
-Snoop Hit w/ Invalidation (LLC Hit, RFO)
-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
In the LLC Miss case, data is returned from DRAM.
SNP_FWD
35
(R/W). A snoop was needed and data was forwarded from a remote socket. This includes:
-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
HITM
36
(R/W). A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cacheline was in modified state before effect as a results of snoop. This includes:
-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
-Snoop MtoS (LLC Hit, IFetch/Data_RD).
NON_DRAM
18.9.6
37
(R/W). Target was non-DRAM system address. This includes MMIO transactions.
Uncore Performance Monitoring Facilities In Intel® Core™ i7-2xxx, Intel® Core™ i52xxx, Intel® Core™ i3-2xxx Processor Series
The uncore sub-system in Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series
provides a unified L3 that can support up to four processor cores. The L3 cache consists multiple slices, each slice
interface with a processor via a coherence engine, referred to as a C-Box. Each C-Box provides dedicated facility of
MSRs to select uncore performance monitoring events and each C-Box event select MSR is paired with a counter
register, similar in style as those described in Section 18.8.2.2. The ARB unit in the uncore also provides its local
performance counters and event select MSRs. The layout of the event select MSRs in the C-Boxes and the ARB unit
are shown in Figure 18-38.
63
28
24 23 22 21 20 19 18 17 16 15
Counter Mask
(CMASK)
0
8 7
Unit Mask (UMASK)
Event Select
INV—Invert counter mask
EN—Enable counter
OVF_EN—Overflow forwarding
E—Edge detect
Reserved
RESET Value — 00000000_00000000H
Figure 18-38. Layout of Uncore PERFEVTSEL MSR for a C-Box Unit or the ARB Unit
Vol. 3B 18-61
PERFORMANCE MONITORING
The bit fields of the uncore event select MSRs for a C-box unit or the ARB unit are summarized below:
•
Event_Select (bits 7:0) and UMASK (bits 15:8): Specifies the microarchitectural condition to count in a local
uncore PMU counter, see Table 19-16.
•
•
E (bit 18): Enables edge detection filtering, if 1.
•
•
•
EN (bit 22): Enables the local counter associated with this event select MSR.
OVF_EN (bit 20): Enables the overflow indicator from the uncore counter forwarded to
MSR_UNC_PERF_GLOBAL_CTRL, if 1.
INV (bit 23): Event count increments with non-negative value if 0, with negated value if 1.
CMASK (bits 28:24): Specifies a positive threshold value to filter raw event count input.
At the uncore domain level, there is a master set of control MSRs that centrally manages all the performance monitoring facility of uncore units. Figure 18-39 shows the layout of the uncore domain global control.
When an uncore counter overflows, a PMI can be routed to a processor core. Bits 3:0 of
MSR_UNC_PERF_GLOBAL_CTRL can be used to select which processor core to handle the uncore PMI. Software
must then write to bit 13 of IA32_DEBUGCTL (at address 1D9H) to enable this capability.
•
PMI_SEL_Core#: Enables the forwarding of an uncore PMI request to a processor core, if 1. If bit 30 (WakePMI)
is ‘1’, a wake request is sent to the respective processor core prior to sending the PMI.
•
EN: Enables the fixed uncore counter, the ARB counters, and the CBO counters in the uncore PMU, if 1. This bit
is cleared if bit 31 (FREEZE) is set and any enabled uncore counters overflow.
•
WakePMI: Controls sending a wake request to any halted processor core before issuing the uncore PMI request.
If a processor core was halted and not sent a wake request, the uncore PMI will not be serviced by the
processor core.
•
FREEZE: Provides the capability to freeze all uncore counters when an overflow condition occurs in a unit
counter. When this bit is set, and a counter overflow occurs, the uncore PMU logic will clear the global enable bit
(bit 29).
63
32 31 30 29 28
4 3 2 1
0
FREEZE—Freeze counters
WakePMI—Wake cores on PMI
EN—Enable all uncore counters
PMI_Sel_Core3 — Uncore PMI to core 3
PMI_Sel_Core2 — Uncore PMI to core 2
PMI_Sel_Core1 — Uncore PMI to core 1
PMI_Sel_Core0 — Uncore PMI to core 0
Reserved
RESET Value — 00000000_00000000H
Figure 18-39. Layout of MSR_UNC_PERF_GLOBAL_CTRL MSR for Uncore
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PERFORMANCE MONITORING
Additionally, there is also a fixed counter, counting uncore clockticks, for the uncore domain. Table 18-39 summarizes the number MSRs for uncore PMU for each box.
Table 18-39. Uncore PMU MSR Summary
Box
# of Boxes
Counters per
Box
Counter
Width
General
Purpose
Global
Enable
C-Box
SKU specific
2
44
Yes
Per-box
ARB
1
2
44
Yes
Uncore
Fixed
Counter
N.A.
N.A.
48
No
Uncore
18.9.6.1
Comment
Up to 4, seeTable 35-19
MSR_UNC_CBO_CONFIG
Uncore Performance Monitoring Events
There are certain restrictions on the uncore performance counters in each C-Box. Specifically,
•
Occupancy events are supported only with counter 0 but not counter 1.
Other uncore C-Box events can be programmed with either counter 0 or 1.
The C-Box uncore performance events described in Table 19-16 can collect performance characteristics of transactions initiated by processor core. In that respect, they are similar to various sub-events in the
OFFCORE_RESPONSE family of performance events in the core PMU. Information such as data supplier locality
(LLC HIT/MISS) and snoop responses can be collected via OFFCORE_RESPONSE and qualified on a per-thread
basis.
On the other hand, uncore performance event logic can not associate its counts with the same level of per-thread
qualification attributes as the core PMU events can. Therefore, whenever similar event programming capabilities
are available from both core PMU and uncore PMU, the recommendation is that utilizing the core PMU events may
be less affected by artifacts, complex interactions and other factors.
18.9.7
Intel® Xeon® Processor E5 Family Performance Monitoring Facility
The Intel® Xeon® Processor E5 Family (and Intel® Core™ i7-3930K Processor) are based on Intel microarchitecture code name Sandy Bridge-E. While the processor cores share the same microarchitecture as those of the Intel®
Xeon® Processor E3 Family and 2nd generation Intel Core i7-2xxx, Intel Core i5-2xxx, Intel Core i3-2xxx processor
series, the uncore subsystems are different. An overview of the uncore performance monitoring facilities of the
Intel Xeon processor E5 family (and Intel Core i7-3930K processor) is described in Section 18.9.8.
Thus, the performance monitoring facilities in the processor core generally are the same as those described in
Section 18.9 through Section 18.9.5. However, the MSR_OFFCORE_RSP_0/MSR_OFFCORE_RSP_1 Response
Supplier Info field shown in Table 18-37 applies to Intel Core Processors with CPUID signature of
DisplayFamily_DisplayModel encoding of 06_2AH; Intel Xeon processor with CPUID signature of
DisplayFamily_DisplayModel encoding of 06_2DH supports an additional field for remote DRAM controller shown in
Table 18-40. Additionally, the are some small differences in the non-architectural performance monitoring events
(see Table 19-14).
Vol. 3B 18-63
PERFORMANCE MONITORING
Table 18-40. MSR_OFFCORE_RSP_x Supplier Info Field Definitions
Subtype
Bit Name
Offset
Description
Common
Any
16
(R/W). Catch all value for any response types.
Supplier Info
18.9.8
NO_SUPP
17
(R/W). No Supplier Information available
LLC_HITM
18
(R/W). M-state initial lookup stat in L3.
LLC_HITE
19
(R/W). E-state
LLC_HITS
20
(R/W). S-state
LLC_HITF
21
(R/W). F-state
LOCAL
22
(R/W). Local DRAM Controller
Remote
30:23
(R/W): Remote DRAM Controller (either all 0s or all 1s)
Intel® Xeon® Processor E5 Family Uncore Performance Monitoring Facility
The uncore subsystem in the Intel Xeon processor E5-2600 product family has some similarities with those of the
Intel Xeon processor E7 family. Within the uncore subsystem, localized performance counter sets are provided at
logic control unit scope. For example, each Cbox caching agent has a set of local performance counters, and the
power controller unit (PCU) has its own local performance counters. Up to 8 C-Box units are supported in the
uncore sub-system.
Table 18-41 summarizes the uncore PMU facilities providing MSR interfaces.
Table 18-41. Uncore PMU MSR Summary for Intel® Xeon® Processor E5 Family
Box
# of Boxes
Counters per Box
Counter
Width
General
Purpose
Global
Enable
Sub-control MSRs
C-Box
8
4
44
Yes
per-box
None
PCU
1
4
48
Yes
per-box
Match/Mask
U-Box
1
2
44
Yes
uncore
None
Details of the uncore performance monitoring facility of Intel Xeon Processor E5 family is available in “Intel®
Xeon® Processor E5 Uncore Performance Monitoring Programming Reference Manual”. The MSR-based uncore PMU
interfaces are listed in Table 35-22.
18.10
3RD GENERATION INTEL® CORE™ PROCESSOR PERFORMANCE
MONITORING FACILITY
The 3rd generation Intel® Core™ processor family and Intel® Xeon® processor E3-1200v2 product family are
based on the Ivy Bridge microarchitecture. The performance monitoring facilities in the processor core generally
are the same as those described in Section 18.9 through Section 18.9.5. The non-architectural performance monitoring events supported by the processor core are listed in Table 19-14.
18.10.1 Intel® Xeon® Processor E5 v2 and E7 v2 Family Uncore Performance Monitoring
Facility
The uncore subsystem in the Intel Xeon processor E5 v2 and Intel Xeon Processor E7 v2 product families are based
on the Ivy Bridge-E microarchitecture. There are some similarities with those of the Intel Xeon processor E5 family
based on the Sandy Bridge microarchitecture. Within the uncore subsystem, localized performance counter sets
are provided at logic control unit scope.
18-64 Vol. 3B
PERFORMANCE MONITORING
Details of the uncore performance monitoring facility of Intel Xeon Processor E5 v2 and Intel Xeon Processor E7 v2
families are available in “Intel® Xeon® Processor E5 v2 and E7 v2 Uncore Performance Monitoring Programming
Reference Manual”. The MSR-based uncore PMU interfaces are listed in Table 35-26.
18.11
4TH GENERATION INTEL® CORE™ PROCESSOR PERFORMANCE
MONITORING FACILITY
The 4th generation Intel® Core™ processor and Intel® Xeon® processor E3-1200 v3 product family are based on
the Haswell microarchitecture. The core PMU supports architectural performance monitoring capability with version
ID 3 (see Section 18.2.3) and a host of non-architectural monitoring capabilities.
Architectural performance monitoring version 3 capabilities are described in Section 18.2.3.
The core PMU’s capability is similar to those described in Section 18.9 through Section 18.9.5, with some differences and enhancements summarized in Table 18-42. Additionally, the core PMU provides some enhancement to
support performance monitoring when the target workload contains instruction streams using Intel® Transactional
Synchronization Extensions (TSX), see Section 18.11.5. For details of Intel TSX, see Chapter 16, “Programming with
Intel® Transactional Synchronization Extensions” of Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1.
Table 18-42. Core PMU Comparison
Box
Intel® microarchitecture code
name Haswell
Intel® microarchitecture code
name Sandy Bridge
Comment
# of Fixed counters per thread
3
3
# of general-purpose counters
per core
8
8
Counter width (R,W)
R:48, W: 32/48
R:48, W: 32/48
See Section 18.2.2.
# of programmable counters per
thread
4 or (8 if a core not shared by two
threads)
4 or (8 if a core not shared by
two threads)
Use CPUID to enumerate
# of counters.
PMI Overhead Mitigation
• Freeze_Perfmon_on_PMI with
legacy semantics.
• Freeze_on_LBR with legacy
semantics for branch profiling.
• Freeze_while_SMM.
• Freeze_Perfmon_on_PMI
with legacy semantics.
• Freeze_on_LBR with legacy
semantics for branch
profiling.
• Freeze_while_SMM.
See Section 17.4.7.
Processor Event Based Sampling
(PEBS) Events
See Table 18-32 and Section
18.11.5.1.
See Table 18-32.
IA32_PMC4-IA32_PMC7
do not support PEBS.
PEBS-Load Latency
See Section 18.9.4.2.
See Section 18.9.4.2.
PEBS-Precise Store
No, replaced by Data Address
profiling.
Section 18.9.4.3
PEBS-PDIR
Yes (using precise
INST_RETIRED.ALL)
Yes (using precise
INST_RETIRED.ALL)
PEBS-EventingIP
Yes
No
Data Address Profiling
Yes
No
LBR Profiling
Yes
Yes
Call Stack Profiling
Yes, see Section 17.9.
No
Off-core Response Event
MSR 1A6H and 1A7H; extended
request and response types.
MSR 1A6H and 1A7H; extended
request and response types.
Intel TSX support for Perfmon
See Section 18.11.5.
No
Use LBR facility.
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PERFORMANCE MONITORING
18.11.1 Processor Event Based Sampling (PEBS) Facility
The PEBS facility in the 4th Generation Intel Core processor is similar to those in processors based on Intel microarchitecture code name Sandy Bridge, with several enhanced features. The key components and differences of
PEBS facility relative to Intel microarchitecture code name Sandy Bridge is summarized in Table 18-43.
Table 18-43. PEBS Facility Comparison
Box
Intel® microarchitecture code
name Haswell
Intel® microarchitecture code
name Sandy Bridge
Comment
Valid IA32_PMCx
PMC0-PMC3
PMC0-PMC3
No PEBS on PMC4-PMC7
PEBS Buffer Programming
Section 18.8.1.1
Section 18.8.1.1
Unchanged
IA32_PEBS_ENABLE Layout
Figure 18-21
Figure 18-35
PEBS record layout
Table 18-44; enhanced fields at
offsets 98H, A0H, A8H, B0H.
Table 18-23; enhanced fields
at offsets 98H, A0H, A8H.
Precise Events
See Table 18-32.
See Table 18-32.
PEBS-Load Latency
See Table 18-33.
Table 18-33
PEBS-Precise Store
No, replaced by data address
profiling.
Yes; see Section 18.9.4.3.
PEBS-PDIR
Yes
Yes
PEBS skid from EventingIP
1 (or 2 if micro+macro fusion)
1
SAMPLING Restriction
Small SAV(CountDown) value incur higher overhead than prior
generation.
IA32_PMC4-IA32_PMC7 do not
support PEBS.
IA32_PMC1 only.
Only IA32_PMC0 through IA32_PMC3 support PEBS.
NOTE
PEBS events are only valid when the following fields of IA32_PERFEVTSELx are all zero: AnyThread,
Edge, Invert, CMask.
In a PMU with PDIR capability, PEBS behavior is unpredictable if IA32_PERFEVTSELx or IA32_PMCx
is changed for a PEBS-enabled counter while an event is being counted. To avoid this, changes to
the programming or value of a PEBS-enabled counter should be performed when the counter is
disabled.
18.11.2 PEBS Data Format
The PEBS record format for the 4th Generation Intel Core processor is shown in Table 18-44. The PEBS record
format, along with debug/store area storage format, does not change regardless of whether IA-32e mode is active
or not. CPUID.01H:ECX.DTES64[bit 2] reports whether the processor's DS storage format support is mode-independent. When set, it uses 64-bit DS storage format.
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PERFORMANCE MONITORING
Table 18-44. PEBS Record Format for 4th Generation Intel Core Processor Family
Byte Offset
Field
Byte Offset
Field
00H
R/EFLAGS
60H
R10
08H
R/EIP
68H
R11
10H
R/EAX
70H
R12
18H
R/EBX
78H
R13
20H
R/ECX
80H
R14
28H
R/EDX
88H
R15
30H
R/ESI
90H
IA32_PERF_GLOBAL_STATUS
38H
R/EDI
98H
Data Linear Address
40H
R/EBP
A0H
Data Source Encoding
48H
R/ESP
A8H
Latency value (core cycles)
50H
R8
B0H
EventingIP
58H
R9
B8H
TX Abort Information (Section 18.11.5.1)
The layout of PEBS records are almost identical to those shown in Table 18-23. Offset B0H is a new field that
records the eventing IP address of the retired instruction that triggered the PEBS assist.
The PEBS records at offsets 98H, A0H, and ABH record data gathered from three of the PEBS capabilities in prior
processor generations: load latency facility (Section 18.9.4.2), PDIR (Section 18.9.4.4), and the equivalent capability of precise store in prior generation (see Section 18.11.3).
In the core PMU of the 4th generation Intel Core processor, load latency facility and PDIR capabilities are
unchanged. However, precise store is replaced by an enhanced capability, data address profiling, that is not
restricted to store address. Data address profiling also records information in PEBS records at offsets 98H, A0H,
and ABH.
18.11.3 PEBS Data Address Profiling
The Data Linear Address facility is also abbreviated as DataLA. The facility is a replacement or extension of the
precise store facility in previous processor generations. The DataLA facility complements the load latency facility by
providing a means to profile load and store memory references in the system, leverages the PEBS facility, and
provides additional information about sampled loads and stores. Having precise memory reference events with
linear address information for both loads and stores provides information to improve data structure layout, eliminate remote node references, and identify cache-line conflicts in NUMA systems.
The DataLA facility in the 4th generation processor supports the following events configured to use PEBS:
Table 18-45. Precise Events That Supports Data Linear Address Profiling
Event Name
Event Name
MEM_UOPS_RETIRED.STLB_MISS_LOADS
MEM_UOPS_RETIRED.STLB_MISS_STORES
MEM_UOPS_RETIRED.LOCK_LOADS
MEM_UOPS_RETIRED.SPLIT_STORES
MEM_UOPS_RETIRED.SPLIT_LOADS
MEM_UOPS_RETIRED.ALL_STORES
MEM_UOPS_RETIRED.ALL_LOADS
MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
MEM_LOAD_UOPS_RETIRED.L1_HIT
MEM_LOAD_UOPS_RETIRED.L2_HIT
MEM_LOAD_UOPS_RETIRED.L3_HIT
MEM_LOAD_UOPS_RETIRED.L1_MISS
MEM_LOAD_UOPS_RETIRED.L2_MISS
MEM_LOAD_UOPS_RETIRED.L3_MISS
MEM_LOAD_UOPS_RETIRED.HIT_LFB
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS
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PERFORMANCE MONITORING
Table 18-45. Precise Events That Supports Data Linear Address Profiling (Contd.)
Event Name
Event Name
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM
UOPS_RETIRED.ALL (if load or store is tagged)
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
DataLA can use any one of the IA32_PMC0-IA32_PMC3 counters. Counter overflows will initiate the generation of
PEBS records. Upon counter overflow, hardware captures the linear address and possible other status information
of the retiring memory uop. This information is then written to the PEBS record that is subsequently generated.
To enable the DataLA facility, software must complete the following steps. Please note that the DataLA facility relies
on the PEBS facility, so the PEBS configuration requirements must be completed before attempting to capture
DataLA information.
•
•
•
Complete the PEBS configuration steps.
Program the an event listed in Table 18-45 using any one of IA32_PERFEVTSEL0-IA32_PERFEVTSEL3.
Set the corresponding IA32_PEBS_ENABLE.PEBS_EN_CTRx bit. This enables the corresponding IA32_PMCx as
a PEBS counter and enables the DataLA facility.
When the DataLA facility is enabled, the relevant information written into a PEBS record affects entries at offsets
98H, A0H and A8H, as shown in Table 18-46.
Table 18-46. Layout of Data Linear Address Information In PEBS Record
Field
Offset
Description
Data Linear
Address
98H
The linear address of the load or the destination of the store.
Store Status
A0H
• DCU Hit (Bit 0): The store hit the data cache closest to the core (L1 cache) if this bit is set, otherwise
the store missed the data cache. This information is valid only for the following store events:
UOPS_RETIRED.ALL (if store is tagged),
MEM_UOPS_RETIRED.STLB_MISS_STORES,
MEM_UOPS_RETIRED.SPLIT_STORES, MEM_UOPS_RETIRED.ALL_STORES
• Other bits are zero, The STLB_MISS, LOCK bit information can be obtained by programming the
corresponding store event in Table 18-45.
Reserved
A8H
Always zero.
18.11.3.1 EventingIP Record
The PEBS record layout for processors based on Intel microarchitecture code name Haswell adds a new field at
offset 0B0H. This is the eventingIP field that records the IP address of the retired instruction that triggered the
PEBS assist. The EIP/RIP field at offset 08H records the IP address of the next instruction to be executed following
the PEBS assist.
18.11.4 Off-core Response Performance Monitoring
The core PMU facility to collect off-core response events are similar to those described in Section 18.9.5. The event
codes are listed in Table 18-35. Each event code for off-core response monitoring requires programming an associated configuration MSR, MSR_OFFCORE_RSP_x. Software must program MSR_OFFCORE_RSP_x according to:
•
•
•
Transaction request type encoding (bits 15:0): see Table 18-47.
Supplier information (bits 30:16): see Table 18-48.
Snoop response information (bits 37:31): see Table 18-38.
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PERFORMANCE MONITORING
Table 18-47. MSR_OFFCORE_RSP_x Request_Type Definition (Haswell microarchitecture)
Bit Name
Offset Description
DMND_DATA_RD
0
(R/W). Counts the number of demand data reads of full and partial cachelines as well as demand data
page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
DMND_RFO
1
(R/W). Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated
by a write to data cacheline. Does not count L2 RFO prefetches.
DMND_IFETCH
2
(R/W). Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2
code read prefetches.
COREWB
3
(R/W). Counts the number of modified cachelines written back.
PF_DATA_RD
4
(R/W). Counts the number of data cacheline reads generated by L2 prefetchers.
PF_RFO
5
(R/W). Counts the number of RFO requests generated by L2 prefetchers.
PF_IFETCH
6
(R/W). Counts the number of code reads generated by L2 prefetchers.
PF_L3_DATA_RD
7
(R/W). Counts the number of data cacheline reads generated by L3 prefetchers.
PF_L3_RFO
8
(R/W). Counts the number of RFO requests generated by L3 prefetchers.
PF_L3_CODE_RD
9
(R/W). Counts the number of code reads generated by L3 prefetchers.
SPLIT_LOCK_UC_
LOCK
10
(R/W). Counts the number of lock requests that split across two cachelines or are to UC memory.
STRM_ST
11
(R/W). Counts the number of streaming store requests electronically.
Reserved
12-14
Reserved
OTHER
15
(R/W). Any other request that crosses IDI, including I/O.
The supplier information field listed in Table 18-48. The fields vary across products (according to CPUID signatures) and is noted in the description.
Table 18-48. MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature 06_3CH, 06_46H)
Subtype
Bit Name
Offset
Description
Common
Any
16
(R/W). Catch all value for any response types.
Supplier
Info
NO_SUPP
17
(R/W). No Supplier Information available
L3_HITM
18
(R/W). M-state initial lookup stat in L3.
L3_HITE
19
(R/W). E-state
L3_HITS
20
(R/W). S-state
Reserved
21
Reserved
LOCAL
22
(R/W). Local DRAM Controller
Reserved
30:23
Reserved
Vol. 3B 18-69
PERFORMANCE MONITORING
Table 18-49. MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature 06_45H)
Subtype
Bit Name
Offset
Description
Common
Any
16
(R/W). Catch all value for any response types.
Supplier
Info
NO_SUPP
17
(R/W). No Supplier Information available
L3_HITM
18
(R/W). M-state initial lookup stat in L3.
L3_HITE
19
(R/W). E-state
L3_HITS
20
(R/W). S-state
Reserved
21
Reserved
L4_HIT_LOCAL_L4
22
(R/W). L4 Cache
L4_HIT_REMOTE_HOP0_L4
23
(R/W). L4 Cache
L4_HIT_REMOTE_HOP1_L4
24
(R/W). L4 Cache
L4_HIT_REMOTE_HOP2P_L4
25
(R/W). L4 Cache
Reserved
30:26
Reserved
18.11.4.1 Off-core Response Performance Monitoring in Intel Xeon Processors E5 v3 Series
Table 18-48 lists the supplier information field that apply to Intel Xeon processor E5 v3 series (CPUID signature
06_3FH).
Table 18-50. MSR_OFFCORE_RSP_x Supplier Info Field Definition
Subtype
Bit Name
Offset
Description
Common
Any
16
(R/W). Catch all value for any response types.
Supplier
Info
NO_SUPP
17
(R/W). No Supplier Information available
L3_HITM
18
(R/W). M-state initial lookup stat in L3.
L3_HITE
19
(R/W). E-state
L3_HITS
20
(R/W). S-state
L3_HITF
21
(R/W). F-state
LOCAL
22
(R/W). Local DRAM Controller
Reserved
26:23
Reserved
L3_MISS_REMOTE_HOP0
27
(R/W). Hop 0 Remote supplier
L3_MISS_REMOTE_HOP1
28
(R/W). Hop 1 Remote supplier
L3_MISS_REMOTE_HOP2P
29
(R/W). Hop 2 or more Remote supplier
Reserved
30
Reserved
18.11.5 Performance Monitoring and Intel® TSX
Chapter 16 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 describes the details of
Intel® Transactional Synchronization Extensions (Intel TSX). This section describes performance monitoring
support for Intel TSX.
If a processor supports Intel TSX, the core PMU enhances it’s IA32_PERFEVTSELx MSR with two additional bit fields
for event filtering. Support for Intel TSX is indicated by either (a) CPUID.(EAX=7, ECX=0):RTM[bit 11]=1, or (b) if
CPUID.07H.EBX.HLE [bit 4] = 1. The TSX-enhanced layout of IA32_PERFEVTSELx is shown in Figure 18-40. The
two additional bit fields are:
18-70 Vol. 3B
PERFORMANCE MONITORING
•
IN_TX (bit 32): When set, the counter will only include counts that occurred inside a transactional region,
regardless of whether that region was aborted or committed. This bit may only be set if the processor supports
HLE or RTM.
•
IN_TXCP (bit 33): When set, the counter will not include counts that occurred inside of an aborted transactional region. This bit may only be set if the processor supports HLE or RTM. This bit may only be set for
IA32_PERFEVTSEL2.
When the IA32_PERFEVTSELx MSR is programmed with both IN_TX=0 and IN_TXCP=0 on a processor that
supports Intel TSX, the result in a counter may include detectable conditions associated with a transaction code
region for its aborted execution (if any) and completed execution.
In the initial implementation, software may need to take pre-caution when using the IN_TXCP bit. see Table 35-27.
63
34
Reserved
31
24 23 22 21 20 19 18 17 16 15
8 7
A I
U
Counter Mask I E N
N
N P E O S Unit Mask (UMASK)
(CMASK)
S R
V N Y T C
0
Event Select
USR—User Mode
OS—Operating system mode
E—Edge detect
PC—Pin control
INT—APIC interrupt enable
ANY—Any Thread
EN—Enable counters
INV—Invert counter mask
IN_TX—In Trans. Rgn
IN_TXCP—In Tx exclude abort (PERFEVTSEL2 Only)
Figure 18-40. Layout of IA32_PERFEVTSELx MSRs Supporting Intel TSX
A common usage of setting IN_TXCP=1 is to capture the number of events that were discarded due to a transactional abort. With IA32_PMC2 configured to count in such a manner, then when a transactional region aborts, the
value for that counter is restored to the value it had prior to the aborted transactional region. As a result, any
updates performed to the counter during the aborted transactional region are discarded.
On the other hand, setting IN_TX=1 can be used to drill down on the performance characteristics of transactional
code regions. When a PMCx is configured with the corresponding IA32_PERFEVTSELx.IN_TX=1, only eventing
conditions that occur inside transactional code regions are propagated to the event logic and reflected in the
counter result. Eventing conditions specified by IA32_PERFEVTSELx but occurring outside a transactional region
are discarded. The following example illustrates using three counters to drill down cycles spent inside and outside
of transactional regions:
•
Program IA32_PERFEVTSEL2 to count Unhalted_Core_Cycles with (IN_TXCP=1, IN_TX=0), such that
IA32_PMC2 will count cycles spent due to aborted TSX transactions;
•
Program IA32_PERFEVTSEL0 to count Unhalted_Core_Cycles with (IN_TXCP=0, IN_TX=1), such that
IA32_PMC0 will count cycles spent by the transactional code regions;
•
Program IA32_PERFEVTSEL1 to count Unhalted_Core_Cycles with (IN_TXCP=0, IN_TX=0), such that
IA32_PMC1 will count total cycles spent by the non-transactional code and transactional code regions.
Additionally, a number of performance events are solely focused on characterizing the execution of Intel TSX transactional code, they are listed in Table 19-8.
18.11.5.1 Intel TSX and PEBS Support
If a PEBS event would have occurred inside a transactional region, then the transactional region first aborts, and
then the PEBS event is processed.
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PERFORMANCE MONITORING
Two of the TSX performance monitoring events in Table 19-8 also support using PEBS facility to capture additional
information. They are:
•
•
HLE_RETIRED.ABORT ED (encoding C8H mask 04H),
RTM_RETIRED.ABORTED (encoding C9H mask 04H).
A transactional abort (HLE_RETIRED.ABORTED,RTM_RETIRED.ABORTED) can also be programmed to cause PEBS
events. In this scenario, a PEBS event is processed following the abort.
Pending a PEBS record inside of a transactional region will cause a transactional abort. If a PEBS record was pended
at the time of the abort or on an overflow of the TSX PEBS events listed above, only the following PEBS entries will
be valid (enumerated by PEBS entry offset B8H bits[33:32] to indicate an HLE abort or an RTM abort):
•
•
Offset B0H: EventingIP,
Offset B8H: TX Abort Information
These fields are set for all PEBS events.
•
Offset 08H (RIP/EIP) corresponds to the instruction following the outermost XACQUIRE in HLE or the first
instruction of the fallback handler of the outermost XBEGIN instruction in RTM. This is useful to identify the
aborted transactional region.
In the case of HLE, an aborted transaction will restart execution deterministically at the start of the HLE region. In
the case of RTM, an aborted transaction will transfer execution to the RTM fallback handler.
The layout of the TX Abort Information field is given in Table 18-51.
Table 18-51. TX Abort Information Field Definition
Bit Name
Offset
Description
Cycles_Last_TX
31:0
The number of cycles in the last TSX region, regardless of whether that region had aborted or
committed.
HLE_Abort
32
If set, the abort information corresponds to an aborted HLE execution
RTM_Abort
33
If set, the abort information corresponds to an aborted RTM execution
Instruction_Abort
34
If set, the abort was associated with the instruction corresponding to the eventing IP (offset
0B0H) within the transactional region.
Non_Instruction_Abort
35
If set, the instruction corresponding to the eventing IP may not necessarily be related to the
transactional abort.
Retry
36
If set, retrying the transactional execution may have succeeded.
Data_Conflict
37
If set, another logical processor conflicted with a memory address that was part of the
transactional region that aborted.
Capacity Writes
38
If set, the transactional region aborted due to exceeding resources for transactional writes.
Capacity Reads
39
If set, the transactional region aborted due to exceeding resources for transactional reads.
Reserved
63:40
Reserved
18.11.6 Uncore Performance Monitoring Facilities in the 4th Generation Intel® Core™
Processors
The uncore sub-system in the 4th Generation Intel® Core™ processors provides its own performance monitoring
facility. The uncore PMU facility provides dedicated MSRs to select uncore performance monitoring events in a
similar manner as those described in Section 18.9.6.
The ARB unit and each C-Box provide local pairs of event select MSR and counter register. The layout of the event
select MSRs in the C-Boxes are identical as shown in Figure 18-38.
At the uncore domain level, there is a master set of control MSRs that centrally manages all the performance monitoring facility of uncore units. Figure 18-39 shows the layout of the uncore domain global control.
18-72 Vol. 3B
PERFORMANCE MONITORING
Additionally, there is also a fixed counter, counting uncore clockticks, for the uncore domain. Table 18-39 summarizes the number MSRs for uncore PMU for each box.
Table 18-52. Uncore PMU MSR Summary
Box
# of Boxes
Counters per
Box
Counter
Width
General
Purpose
Global
Enable
C-Box
SKU specific
2
44
Yes
Per-box
ARB
1
2
44
Yes
Uncore
Fixed Counter
N.A.
N.A.
48
No
Uncore
Comment
Up to 4, seeTable 35-19
MSR_UNC_CBO_CONFIG
The uncore performance events for the C-Box and ARB units are listed in Table 19-9.
18.11.7 Intel® Xeon® Processor E5 v3 Family Uncore Performance Monitoring Facility
Details of the uncore performance monitoring facility of Intel Xeon Processor E5 v3 families are available in “Intel®
Xeon® Processor E5 v3 Uncore Performance Monitoring Programming Reference Manual”. The MSR-based uncore
PMU interfaces are listed in Table 35-31.
18.12
5TH GENERATION INTEL® CORE™ PROCESSOR AND INTEL® CORE™ M
PROCESSOR PERFORMANCE MONITORING FACILITY
The 5th Generation Intel® Core™ processor and the Intel® Core™ M processor families are based on the Broadwell
microarchitecture. The core PMU supports architectural performance monitoring capability with version ID 3 (see
Section 18.2.3) and a host of non-architectural monitoring capabilities.
Architectural performance monitoring version 3 capabilities are described in Section 18.2.3.
The core PMU has the same capability as those described in Section 18.11. IA32_PERF_GLOBAL_STATUS provide a
bit indicator (bit 55) for PMI handler to distinguish PMI due to output buffer overflow condition due to accumulating
packet data from Intel Processor Trace.
63 62 61
55
35 34 33 32 31
8 7 6 5 4 3 2 10
CondChgd
Ovf_Buffer
Ovf_UncorePMU
Trace_ToPA_PMI
FIXED_CTR2 Overflow (RO)
FIXED_CTR1 Overflow (RO)
FIXED_CTR0 Overflow (RO)
PMC7_OVF (RO, If PMC7 present)
PMC6_OVF (RO, If PMC6 present)
PMC5_OVF (RO, If PMC5 present)
PMC4_OVF (RO, If PMC4 present)
PMC3_OVF (RO)
PMC2_OVF (RO)
PMC1_OVF (RO)
PMC0_OVF (RO)
Reserved
Valid if CPUID.0AH:EAX[15:8] = 8; else reserved
Figure 18-41. IA32_PERF_GLOBAL_STATUS MSR in Broadwell Microarchitecture
Vol. 3B 18-73
PERFORMANCE MONITORING
Details of Intel Processor Trace is described in Chapter 36, “Intel® Processor Trace”.
IA32_PERF_GLOBAL_OVF_CTRL MSR provide a corresponding reset control bit.
63 62 61
55
35 34 33 32 31
8 7 6 5 4 3
2 10
ClrCondChgd
ClrOvfDSBuffer
ClrOvfUncore
ClrTraceToPA_PMI
FIXED_CTR2 ClrOverflow
FIXED_CTR1 ClrOverflow
FIXED_CTR0 ClrOverflow
PMC7_ClrOvf (if PMC7 present)
PMC6_ClrOvf (if PMC6 present)
PMC5_ClrOvf (if PMC5 present)
PMC4_ClrOvf (if PMC4 present)
PMC3_ClrOvf
PMC2_ClrOvf
PMC1_ClrOvf
PMC0_ClrOvf
Reserved
Valid if CPUID.0AH:EAX[15:8] = 8; else reserved
Figure 18-42. IA32_PERF_GLOBAL_OVF_CTRL MSR in Broadwell microarchitecture
The specifics of non-architectural performance events are listed in Chapter 19, “Performance Monitoring Events”.
18.13
6TH GENERATION INTEL® CORE™ PROCESSOR AND 7TH GENERATION
INTEL® CORE™ PROCESSOR PERFORMANCE MONITORING FACILITY
The 6th generation Intel® Core™ processor is based on the Skylake microarchitecture. The 7th generation Intel®
Core™ processor is based on the Kaby Lake microarchitecture. The core PMU supports architectural performance
monitoring capability with version ID 4 (see Section 18.2.4) and a host of non-architectural monitoring capabilities.
Architectural performance monitoring version 4 capabilities are described in Section 18.2.4.
The core PMU’s capability is similar to those described in Section 18.9 through Section 18.9.5, with some differences and enhancements summarized in Table 18-42. Additionally, the core PMU provides some enhancement to
support performance monitoring when the target workload contains instruction streams using Intel® Transactional
Synchronization Extensions (TSX), see Section 18.11.5. For details of Intel TSX, see Chapter 16, “Programming with
Intel® Transactional Synchronization Extensions” of Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1.
Performance monitoring result may be affected by side-band activity on processors that support Intel SGX, details
are described in Chapter 43, “Enclave Code Debug and Profiling”.
18-74 Vol. 3B
PERFORMANCE MONITORING
Table 18-53. Core PMU Comparison
Box
Intel® microarchitecture code name
Skylake and Kaby Lake
Intel® microarchitecture code
name Haswell and Broadwell
# of Fixed counters per thread
3
3
# of general-purpose counters
per core
8
8
Counter width (R,W)
R:48, W: 32/48
R:48, W: 32/48
See Section 18.2.2.
# of programmable counters
per thread
4 or (8 if a core not shared by two
threads)
4 or (8 if a core not shared by two
threads)
CPUID enumerates
# of counters.
Architectural Perfmon version
4
3
See Section 18.2.4
PMI Overhead Mitigation
• Freeze_Perfmon_on_PMI with
streamlined semantics.
• Freeze_on_LBR with streamlined
semantics.
• Freeze_while_SMM.
• Freeze_Perfmon_on_PMI with
legacy semantics.
• Freeze_on_LBR with legacy
semantics for branch profiling.
• Freeze_while_SMM.
See Section 17.4.7.
Comment
Legacy semantics
not supported with
version 4 or higher.
Counter and Buffer Overflow
Status Management
• Query via
• Query via
IA32_PERF_GLOBAL_STATUS
IA32_PERF_GLOBAL_STATUS
• Reset via
• Reset via
IA32_PERF_GLOBAL_OVF_CTRL
IA32_PERF_GLOBAL_STATUS_RESET
• Set via
IA32_PERF_GLOBAL_STATUS_SET
See Section 18.2.4.
IA32_PERF_GLOBAL_STATUS
Indicators of
Overflow/Overhead/Interferen
ce
•
•
•
•
• Individual counter overflow
• PEBS buffer overflow
• ToPA buffer overflow (applicable
to Broadwell microarchitecture)
See Section 18.2.4.
Enable control in
IA32_PERF_GLOBAL_STATUS
• CTR_Frz,
• LBR_Frz
NA
See Section
18.2.4.1.
Perfmon Counter In-Use
Indicator
Query IA32_PERF_GLOBAL_INUSE
NA
See Section
18.2.4.3.
Precise Events
See Table 18-56.
See Table 18-32.
IA32_PMC4-PMC7
do not support
PEBS.
PEBS for front end events
See Section 18.13.1.4;
No
LBR Record Format Encoding
000101b
000100b
LBR Size
32 entries
16 entries
LBR Entry
From_IP/To_IP/LBR_Info triplet
From_IP/To_IP pair
Section 17.10
LBR Timing
Yes
No
Section 17.10.1
Call Stack Profiling
Yes, see Section 17.9
Yes, see Section 17.9
Use LBR facility
Off-core Response Event
MSR 1A6H and 1A7H; Extended request
and response types.
MSR 1A6H and 1A7H; Extended
request and response types.
Intel TSX support for Perfmon
See Section 18.11.5;
See Section 18.11.5;
Individual counter overflow
PEBS buffer overflow
ToPA buffer overflow
CTR_Frz, LBR_Frz, ASCI
Section 17.4.8.1
18.13.1 Processor Event Based Sampling (PEBS) Facility
The PEBS facility in the 6th and 7th generation Intel Core processors provides a number enhancement relative to
PEBS in processors based on Haswell/Broadwell microarchitectures. The key components and differences of PEBS
facility relative to Haswell/Broadwell microarchitecture is summarized in Table 18-54.
Vol. 3B 18-75
PERFORMANCE MONITORING
Table 18-54. PEBS Facility Comparison
Box
Intel® microarchitecture code Intel® microarchitecture code
name Skylake and Kaby Lake name Haswell and Broadwell
Comment
Valid IA32_PMCx
PMC0-PMC3
PMC0-PMC3
No PEBS on PMC4-PMC7.
PEBS Buffer Programming
Section 18.8.1.1
Section 18.8.1.1
Unchanged
IA32_PEBS_ENABLE Layout
Figure 18-21
Figure 18-21
PEBS-EventingIP
Yes
Yes
PEBS record format encoding 0011b
0010b
PEBS record layout
Table 18-55; enhanced fields
at offsets 98H- B8H; and TSC
record field at C0H.
Table 18-44; enhanced fields at
offsets 98H, A0H, A8H, B0H.
Multi-counter PEBS
resolution
PEBS record 90H resolves the
eventing counter overflow.
PEBS record 90H reflects
IA32_PERF_GLOBAL_STATUS.
Precise Events
See Table 18-56.
See Table 18-32.
IA32_PMC4-IA32_PMC7 do not
support PEBS.
PEBS-PDIR
Yes
Yes
IA32_PMC1 only.
PEBS-Load Latency
See Section 18.9.4.2.
See Section 18.9.4.2.
Data Address Profiling
Yes
Yes
FrontEnd event support
FrontEnd_Retried event and
MSR_PEBS_FRONTEND.
No
IA32_PMC0-PMC3 only.
Only IA32_PMC0 through IA32_PMC3 support PEBS.
NOTES
Precise events are only valid when the following fields of IA32_PERFEVTSELx are all zero:
AnyThread, Edge, Invert, CMask.
In a PMU with PDIR capability, PEBS behavior is unpredictable if IA32_PERFEVTSELx or IA32_PMCx
is changed for a PEBS-enabled counter while an event is being counted. To avoid this, changes to
the programming or value of a PEBS-enabled counter should be performed when the counter is
disabled.
18.13.1.1 PEBS Data Format
The PEBS record format for the 6th and 7th generation Intel Core processors is reporting with encoding 0011b in
IA32_PERF_CAPABILITIES[11:8]. The lay out is shown in Table 18-55. The PEBS record format, along with
debug/store area storage format, does not change regardless of whether IA-32e mode is active or not.
CPUID.01H:ECX.DTES64[bit 2] reports whether the processor's DS storage format support is mode-independent.
When set, it uses 64-bit DS storage format.
18-76 Vol. 3B
PERFORMANCE MONITORING
Table 18-55. PEBS Record Format for 6th Generation Intel Core Processor
and 7th Generation Intel Core Processor Families
Byte Offset
Field
Byte Offset
Field
00H
R/EFLAGS
68H
R11
08H
R/EIP
70H
R12
10H
R/EAX
78H
R13
18H
R/EBX
80H
R14
20H
R/ECX
88H
R15
28H
R/EDX
90H
Applicable Counter
30H
R/ESI
98H
Data Linear Address
38H
R/EDI
A0H
Data Source Encoding
40H
R/EBP
A8H
Latency value (core cycles)
48H
R/ESP
B0H
EventingIP
50H
R8
B8H
TX Abort Information (Section 18.11.5.1)
58H
R9
C0H
TSC
60H
R10
The layout of PEBS records are largely identical to those shown in Table 18-44.
The PEBS records at offsets 98H, A0H, and ABH record data gathered from three of the PEBS capabilities in prior
processor generations: load latency facility (Section 18.9.4.2), PDIR (Section 18.9.4.4), and data address profiling
(Section 18.11.3).
In the core PMU of the 6th and 7th generation Intel Core processors, load latency facility and PDIR capabilities and
data address profiling are unchanged relative to the 4th and 5th generation Intel Core processors. Similarly,
precise store is replaced by data address profiling.
With format 0010b, a snapshot of the IA32_PERF_GLOBAL_STATUS may be useful to resolve the situations when
more than one of IA32_PMICx have been configured to collect PEBS data and two consecutive overflows of the
PEBS-enabled counters are sufficiently far apart in time. It is also possible for the image at 90H to indicate multiple
PEBS-enabled counters have overflowed. In the latter scenario, software cannot to correlate the PEBS record entry
to the multiple overflowed bits.
With PEBS record format encoding 0011b, offset 90H reports the “applicable counter” field, which is a multicounter PEBS resolution index allowing software to correlate the PEBS record entry with the eventing PEBS overflow when multiple counters are configured to record PEBS records. Additionally, offset C0H captures a snapshot of
the TSC that provides a time line annotation for each PEBS record entry.
18.13.1.2 PEBS Events
The list of precise events supported for PEBS in the Skylake and Kaby Lake microarchitectures is shown in
Table 18-56.
Vol. 3B 18-77
PERFORMANCE MONITORING
Table 18-56. Precise Events for the Skylake and Kaby Lake Microarchitectures
Event Name
Event Select
INST_RETIRED
C0H
Sub-event
UMask
1
01H
PREC_DIST
2
ALL_CYCLES
01H
OTHER_ASSISTS
C1H
ANY
3FH
BR_INST_RETIRED
C4H
CONDITIONAL
01H
NEAR_CALL
02H
BR_MISP_RETIRED
C5H
FRONTEND_RETIRED
C6H
ALL_BRANCHES
04H
NEAR_RETURN
08H
NEAR_TAKEN
20H
FAR_BRACHES
40H
CONDITIONAL
01H
ALL_BRANCHES
04H
NEAR_TAKEN
20H
3>
3 DSB lines.
AEH
01H
ITLB.ITLB_FLUSH
Counts the number of ITLB flushes, includes
4k/2M/4M pages.
B0H
01H
OFFCORE_REQUESTS.DEMAND_D Demand data read requests sent to uncore.
ATA_RD
B0H
02H
OFFCORE_REQUESTS.DEMAND_C Demand code read requests sent to uncore.
ODE_RD
B0H
04H
OFFCORE_REQUESTS.DEMAND_R Demand RFO read requests sent to uncore,
FO
including regular RFOs, locks, ItoM.
B0H
08H
OFFCORE_REQUESTS.ALL_DATA_ Data read requests sent to uncore (demand and
RD
prefetch).
B1H
01H
UOPS_EXECUTED.THREAD
Counts total number of uops to be executed perthread each cycle. Set Cmask = 1, INV =1 to count
stall cycles.
B1H
02H
UOPS_EXECUTED.CORE
Counts total number of uops to be executed percore each cycle.
Event Mask Mnemonic
Description
Comment
Do not need to set ANY.
Vol. 3B 19-39
PERFORMANCE-MONITORING EVENTS
Table 19-11. Non-Architectural Performance Events In the Processor Core of
3rd Generation Intel® Core™ i7, i5, i3 Processors (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment
B7H
01H
OFFCORE_RESPONSE_0
See Section 18.9.5, “Off-core Response
Performance Monitoring”.
Requires MSR 01A6H.
BBH
01H
OFFCORE_RESPONSE_1
See Section 18.9.5, “Off-core Response
Performance Monitoring”.
Requires MSR 01A7H.
BDH
01H
TLB_FLUSH.DTLB_THREAD
DTLB flush attempts of the thread-specific entries.
BDH
20H
TLB_FLUSH.STLB_ANY
Count number of STLB flush attempts.
C0H
00H
INST_RETIRED.ANY_P
Number of instructions at retirement.
C0H
01H
INST_RETIRED.PREC_DIST
Precise instruction retired event with HW to reduce PMC1 only.
effect of PEBS shadow in IP distribution.
C1H
08H
OTHER_ASSISTS.AVX_STORE
Number of assists associated with 256-bit AVX
store operations.
C1H
10H
OTHER_ASSISTS.AVX_TO_SSE
Number of transitions from AVX-256 to legacy SSE
when penalty applicable.
C1H
20H
OTHER_ASSISTS.SSE_TO_AVX
Number of transitions from SSE to AVX-256 when
penalty applicable.
C1H
80H
OTHER_ASSISTS.WB
Number of times microcode assist is invoked by
hardware upon uop writeback.
C2H
01H
UOPS_RETIRED.ALL
Counts the number of micro-ops retired, Use
Supports PEBS, use
cmask=1 and invert to count active cycles or stalled Any=1 for core granular.
cycles.
C2H
02H
UOPS_RETIRED.RETIRE_SLOTS
Counts the number of retirement slots used each
cycle.
C3H
02H
MACHINE_CLEARS.MEMORY_ORD Counts the number of machine clears due to
ERING
memory order conflicts.
C3H
04H
MACHINE_CLEARS.SMC
Number of self-modifying-code machine clears
detected.
C3H
20H
MACHINE_CLEARS.MASKMOV
Counts the number of executed AVX masked load
operations that refer to an illegal address range
with the mask bits set to 0.
C4H
00H
BR_INST_RETIRED.ALL_BRANCH
ES
Branch instructions at retirement.
C4H
01H
BR_INST_RETIRED.CONDITIONAL Counts the number of conditional branch
instructions retired.
Supports PEBS.
C4H
02H
BR_INST_RETIRED.NEAR_CALL
Direct and indirect near call instructions retired.
Supports PEBS.
C4H
04H
BR_INST_RETIRED.ALL_BRANCH
ES
Counts the number of branch instructions retired.
Supports PEBS.
C4H
08H
BR_INST_RETIRED.NEAR_RETUR Counts the number of near return instructions
N
retired.
C4H
10H
BR_INST_RETIRED.NOT_TAKEN
Counts the number of not taken branch instructions Supports PEBS.
retired.
C4H
20H
BR_INST_RETIRED.NEAR_TAKEN
Number of near taken branches retired.
C4H
40H
BR_INST_RETIRED.FAR_BRANCH Number of far branches retired.
Supports PEBS.
C5H
00H
BR_MISP_RETIRED.ALL_BRANCH Mispredicted branch instructions at retirement.
ES
See Table 19-1.
C5H
01H
BR_MISP_RETIRED.CONDITIONAL Mispredicted conditional branch instructions retired. Supports PEBS.
19-40 Vol. 3B
See Table 19-1.
Supports PEBS.
See Table 19-1.
Supports PEBS.
Supports PEBS.
PERFORMANCE-MONITORING EVENTS
Table 19-11. Non-Architectural Performance Events In the Processor Core of
3rd Generation Intel® Core™ i7, i5, i3 Processors (Contd.)
Event
Num.
Umask
Value
C5H
04H
BR_MISP_RETIRED.ALL_BRANCH Mispredicted macro branch instructions retired.
ES
Supports PEBS.
C5H
20H
BR_MISP_RETIRED.NEAR_TAKEN Mispredicted taken branch instructions retired.
Supports PEBS.
CAH
02H
FP_ASSIST.X87_OUTPUT
Supports PEBS.
CAH
04H
FP_ASSIST.X87_INPUT
Number of X87 FP assists due to input values.
Supports PEBS.
CAH
08H
FP_ASSIST.SIMD_OUTPUT
Number of SIMD FP assists due to output values.
Supports PEBS.
CAH
10H
FP_ASSIST.SIMD_INPUT
Number of SIMD FP assists due to input values.
CAH
1EH
FP_ASSIST.ANY
Cycles with any input/output SSE* or FP assists.
CCH
20H
ROB_MISC_EVENTS.LBR_INSERT
S
Count cases of saving new LBR records by
hardware.
CDH
01H
MEM_TRANS_RETIRED.LOAD_LA
TENCY
Randomly sampled loads whose latency is above a
user defined threshold. A small fraction of the
overall loads are sampled due to randomization.
Specify threshold in MSR
3F6H. PMC 3 only.
CDH
02H
MEM_TRANS_RETIRED.PRECISE_
STORE
Sample stores and collect precise store operation
via PEBS record. PMC3 only.
See Section 18.9.4.3.
D0H
11H
MEM_UOPS_RETIRED.STLB_MISS Retired load uops that miss the STLB.
_LOADS
Supports PEBS.
D0H
12H
MEM_UOPS_RETIRED.STLB_MISS Retired store uops that miss the STLB.
_STORES
Supports PEBS.
D0H
21H
MEM_UOPS_RETIRED.LOCK_LOA
DS
Retired load uops with locked access.
Supports PEBS.
D0H
41H
MEM_UOPS_RETIRED.SPLIT_LOA
DS
Retired load uops that split across a cacheline
boundary.
Supports PEBS.
D0H
42H
MEM_UOPS_RETIRED.SPLIT_STO
RES
Retired store uops that split across a cacheline
boundary.
Supports PEBS.
D0H
81H
MEM_UOPS_RETIRED.ALL_LOADS All retired load uops.
Supports PEBS.
D0H
82H
MEM_UOPS_RETIRED.ALL_STORE All retired store uops.
S
Supports PEBS.
D1H
01H
MEM_LOAD_UOPS_RETIRED.L1_
HIT
Retired load uops with L1 cache hits as data
sources.
Supports PEBS.
D1H
02H
MEM_LOAD_UOPS_RETIRED.L2_
HIT
Retired load uops with L2 cache hits as data
sources.
Supports PEBS.
D1H
04H
MEM_LOAD_UOPS_RETIRED.LLC_ Retired load uops whose data source was LLC hit
HIT
with no snoop required.
Supports PEBS.
D1H
08H
MEM_LOAD_UOPS_RETIRED.L1_
MISS
Retired load uops whose data source followed an
L1 miss.
Supports PEBS.
D1H
10H
MEM_LOAD_UOPS_RETIRED.L2_
MISS
Retired load uops that missed L2, excluding
unknown sources.
Supports PEBS.
D1H
20H
MEM_LOAD_UOPS_RETIRED.LLC_ Retired load uops whose data source is LLC miss.
MISS
D1H
40H
MEM_LOAD_UOPS_RETIRED.HIT_ Retired load uops which data sources were load
Supports PEBS.
LFB
uops missed L1 but hit FB due to preceding miss to
the same cache line with data not ready.
Event Mask Mnemonic
Description
Number of X87 FP assists due to output values.
Comment
Supports PEBS.
Restricted to counters 03 when HTT is disabled.
Vol. 3B 19-41
PERFORMANCE-MONITORING EVENTS
Table 19-11. Non-Architectural Performance Events In the Processor Core of
3rd Generation Intel® Core™ i7, i5, i3 Processors (Contd.)
Event
Num.
Umask
Value
D2H
01H
MEM_LOAD_UOPS_LLC_HIT_RETI Retired load uops whose data source was an onRED.XSNP_MISS
package core cache LLC hit and cross-core snoop
missed.
Supports PEBS.
D2H
02H
MEM_LOAD_UOPS_LLC_HIT_RETI Retired load uops whose data source was an onRED.XSNP_HIT
package LLC hit and cross-core snoop hits.
Supports PEBS.
D2H
04H
MEM_LOAD_UOPS_LLC_HIT_RETI Retired load uops whose data source was an onRED.XSNP_HITM
package core cache with HitM responses.
Supports PEBS.
D2H
08H
MEM_LOAD_UOPS_LLC_HIT_RETI Retired load uops whose data source was LLC hit
RED.XSNP_NONE
with no snoop required.
Supports PEBS.
D3H
01H
MEM_LOAD_UOPS_LLC_MISS_RE
TIRED.LOCAL_DRAM
Retired load uops whose data source was local
Supports PEBS.
memory (cross-socket snoop not needed or missed).
E6H
1FH
BACLEARS.ANY
Number of front end re-steers due to BPU
misprediction.
F0H
01H
L2_TRANS.DEMAND_DATA_RD
Demand Data Read requests that access L2 cache.
F0H
02H
L2_TRANS.RFO
RFO requests that access L2 cache.
F0H
04H
L2_TRANS.CODE_RD
L2 cache accesses when fetching instructions.
F0H
08H
L2_TRANS.ALL_PF
Any MLC or LLC HW prefetch accessing L2, including
rejects.
F0H
10H
L2_TRANS.L1D_WB
L1D writebacks that access L2 cache.
F0H
20H
L2_TRANS.L2_FILL
L2 fill requests that access L2 cache.
F0H
40H
L2_TRANS.L2_WB
L2 writebacks that access L2 cache.
F0H
80H
L2_TRANS.ALL_REQUESTS
Transactions accessing L2 pipe.
F1H
01H
L2_LINES_IN.I
L2 cache lines in I state filling L2.
Counting does not cover
rejects.
F1H
02H
L2_LINES_IN.S
L2 cache lines in S state filling L2.
Counting does not cover
rejects.
F1H
04H
L2_LINES_IN.E
L2 cache lines in E state filling L2.
Counting does not cover
rejects.
F1H
07H
L2_LINES_IN.ALL
L2 cache lines filling L2.
Counting does not cover
rejects.
F2H
01H
L2_LINES_OUT.DEMAND_CLEAN
Clean L2 cache lines evicted by demand.
F2H
02H
L2_LINES_OUT.DEMAND_DIRTY
Dirty L2 cache lines evicted by demand.
F2H
04H
L2_LINES_OUT.PF_CLEAN
Clean L2 cache lines evicted by the MLC prefetcher.
F2H
08H
L2_LINES_OUT.PF_DIRTY
Dirty L2 cache lines evicted by the MLC prefetcher.
F2H
0AH
L2_LINES_OUT.DIRTY_ALL
Dirty L2 cache lines filling the L2.
19.5.1
Event Mask Mnemonic
Description
Comment
Counting does not cover
rejects.
Performance Monitoring Events in the Processor Core of Intel Xeon Processor E5 v2
Family and Intel Xeon Processor E7 v2 Family
Non-architectural performance monitoring events in the processor core that are applicable only to Intel Xeon
processor E5 v2 family and Intel Xeon processor E7 v2 family based on the Ivy Bridge-E microarchitecture, with
CPUID signature of DisplayFamily_DisplayModel 06_3EH, are listed in Table 19-12.
19-42 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-12. Non-Architectural Performance Events Applicable Only to the Processor Core of
Intel® Xeon® Processor E5 v2 Family and Intel® Xeon® Processor E7 v2 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment
D3H
03H
MEM_LOAD_UOPS_LLC_MISS_R
ETIRED.LOCAL_DRAM
Retired load uops whose data sources were local
DRAM (snoop not needed, Snoop Miss, or Snoop Hit
data not forwarded).
Supports PEBS.
D3H
0CH
MEM_LOAD_UOPS_LLC_MISS_R
ETIRED.REMOTE_DRAM
Retired load uops whose data source was remote
DRAM (snoop not needed, Snoop Miss, or Snoop Hit
data not forwarded).
Supports PEBS.
D3H
10H
MEM_LOAD_UOPS_LLC_MISS_R
ETIRED.REMOTE_HITM
Retired load uops whose data sources were remote
HITM.
Supports PEBS.
D3H
20H
MEM_LOAD_UOPS_LLC_MISS_R
ETIRED.REMOTE_FWD
Retired load uops whose data sources were forwards
from a remote cache.
Supports PEBS.
19.6
PERFORMANCE MONITORING EVENTS FOR 2ND GENERATION
INTEL® CORE™ I7-2XXX, INTEL® CORE™ I5-2XXX, INTEL® CORE™ I3-2XXX
PROCESSOR SERIES
2nd generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series, and Intel
Xeon processor E3-1200 product family are based on the Intel microarchitecture code name Sandy Bridge. They
support architectural performance-monitoring events listed in Table 19-1. Non-architectural performance-monitoring events in the processor core are listed in Table 19-13, Table 19-14, and Table 19-15. The events in Table
19-13 apply to processors with CPUID signature of DisplayFamily_DisplayModel encoding with the following
values: 06_2AH and 06_2DH. The events in Table 19-14 apply to processors with CPUID signature 06_2AH. The
events in Table 19-15 apply to processors with CPUID signature 06_2DH. Fixed counters in the core PMU support
the architecture events defined in Table 19-2.
Additional information on event specifics (e.g. derivative events using specific IA32_PERFEVTSELx modifiers, limitations, special notes and recommendations) can be found at http://software.intel.com/en-us/forums/softwaretuning-performance-optimization-platform-monitoring.
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
03H
01H
LD_BLOCKS.DATA_UNKNOWN
Blocked loads due to store buffer blocks with
unknown data.
03H
02H
LD_BLOCKS.STORE_FORWARD Loads blocked by overlapping with store buffer that
cannot be forwarded.
03H
08H
LD_BLOCKS.NO_SR
# of Split loads blocked due to resource not
available.
03H
10H
LD_BLOCKS.ALL_BLOCK
Number of cases where any load is blocked but has
no DCU miss.
05H
01H
MISALIGN_MEM_REF.LOADS
Speculative cache-line split load uops dispatched to
L1D.
05H
02H
MISALIGN_MEM_REF.STORES
Speculative cache-line split Store-address uops
dispatched to L1D.
07H
01H
LD_BLOCKS_PARTIAL.ADDRES False dependencies in MOB due to partial compare
S_ALIAS
on address.
Comment
Vol. 3B 19-43
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
07H
08H
LD_BLOCKS_PARTIAL.ALL_STA The number of times that load operations are
_BLOCK
temporarily blocked because of older stores, with
addresses that are not yet known. A load operation
may incur more than one block of this type.
08H
01H
DTLB_LOAD_MISSES.MISS_CA
USES_A_WALK
08H
02H
DTLB_LOAD_MISSES.WALK_CO Misses in all TLB levels that caused page walk
MPLETED
completed of any size.
08H
04H
DTLB_LOAD_MISSES.WALK_DU Cycle PMH is busy with a walk.
RATION
08H
10H
DTLB_LOAD_MISSES.STLB_HIT Number of cache load STLB hits. No page walk.
0DH
03H
INT_MISC.RECOVERY_CYCLES
Cycles waiting to recover after Machine Clears or
JEClear. Set Cmask= 1.
0DH
40H
INT_MISC.RAT_STALL_CYCLES
Cycles RAT external stall is sent to IDQ for this
thread.
0EH
01H
UOPS_ISSUED.ANY
Increments each cycle the # of Uops issued by the
RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count
stalled cycles of this core.
10H
01H
FP_COMP_OPS_EXE.X87
Counts number of X87 uops executed.
10H
10H
FP_COMP_OPS_EXE.SSE_FP_P Counts number of SSE* double precision FP packed
ACKED_DOUBLE
uops executed.
10H
20H
FP_COMP_OPS_EXE.SSE_FP_S Counts number of SSE* single precision FP scalar
CALAR_SINGLE
uops executed.
10H
40H
FP_COMP_OPS_EXE.SSE_PACK Counts number of SSE* single precision FP packed
ED SINGLE
uops executed.
10H
80H
FP_COMP_OPS_EXE.SSE_SCAL Counts number of SSE* double precision FP scalar
AR_DOUBLE
uops executed.
11H
01H
SIMD_FP_256.PACKED_SINGLE Counts 256-bit packed single-precision floatingpoint instructions.
11H
02H
SIMD_FP_256.PACKED_DOUBL Counts 256-bit packed double-precision floatingE
point instructions.
14H
01H
ARITH.FPU_DIV_ACTIVE
Cycles that the divider is active, includes INT and FP.
Set 'edge =1, cmask=1' to count the number of
divides.
17H
01H
INSTS_WRITTEN_TO_IQ.INSTS
Counts the number of instructions written into the
IQ every cycle.
24H
01H
L2_RQSTS.DEMAND_DATA_RD Demand Data Read requests that hit L2 cache.
_HIT
24H
03H
L2_RQSTS.ALL_DEMAND_DAT
A_RD
Counts any demand and L1 HW prefetch data load
requests to L2.
24H
04H
L2_RQSTS.RFO_HITS
Counts the number of store RFO requests that hit
the L2 cache.
24H
08H
L2_RQSTS.RFO_MISS
Counts the number of store RFO requests that miss
the L2 cache.
Event Mask Mnemonic
Description
Misses in all TLB levels that cause a page walk of
any page size.
24H
0CH
L2_RQSTS.ALL_RFO
Counts all L2 store RFO requests.
24H
10H
L2_RQSTS.CODE_RD_HIT
Number of instruction fetches that hit the L2 cache.
19-44 Vol. 3B
Comment
Set Edge to count
occurrences.
Set Cmask = 1, Inv = 1to
count stalled cycles.
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
24H
20H
L2_RQSTS.CODE_RD_MISS
Number of instruction fetches that missed the L2
cache.
24H
30H
L2_RQSTS.ALL_CODE_RD
Counts all L2 code requests.
24H
40H
L2_RQSTS.PF_HIT
Requests from L2 Hardware prefetcher that hit L2.
24H
80H
L2_RQSTS.PF_MISS
Requests from L2 Hardware prefetcher that missed
L2.
24H
C0H
L2_RQSTS.ALL_PF
Any requests from L2 Hardware prefetchers.
27H
01H
L2_STORE_LOCK_RQSTS.MISS
RFOs that miss cache lines.
27H
04H
L2_STORE_LOCK_RQSTS.HIT_
E
RFOs that hit cache lines in E state.
27H
08H
L2_STORE_LOCK_RQSTS.HIT_
M
RFOs that hit cache lines in M state.
Comment
27H
0FH
L2_STORE_LOCK_RQSTS.ALL
RFOs that access cache lines in any state.
28H
01H
L2_L1D_WB_RQSTS.MISS
Not rejected writebacks from L1D to L2 cache lines
that missed L2.
28H
02H
L2_L1D_WB_RQSTS.HIT_S
Not rejected writebacks from L1D to L2 cache lines
in S state.
28H
04H
L2_L1D_WB_RQSTS.HIT_E
Not rejected writebacks from L1D to L2 cache lines
in E state.
28H
08H
L2_L1D_WB_RQSTS.HIT_M
Not rejected writebacks from L1D to L2 cache lines
in M state.
28H
0FH
L2_L1D_WB_RQSTS.ALL
Not rejected writebacks from L1D to L2 cache.
2EH
4FH
LONGEST_LAT_CACHE.REFERE This event counts requests originating from the
NCE
core that reference a cache line in the last level
cache.
See Table 19-1.
2EH
41H
LONGEST_LAT_CACHE.MISS
See Table 19-1.
3CH
00H
CPU_CLK_UNHALTED.THREAD Counts the number of thread cycles while the
_P
thread is not in a halt state. The thread enters the
halt state when it is running the HLT instruction.
The core frequency may change from time to time
due to power or thermal throttling.
See Table 19-1.
3CH
01H
CPU_CLK_THREAD_UNHALTED Increments at the frequency of XCLK (100 MHz)
.REF_XCLK
when not halted.
See Table 19-1.
48H
01H
L1D_PEND_MISS.PENDING
PMC2 only;
This event counts each cache miss condition for
references to the last level cache.
Increments the number of outstanding L1D misses
every cycle. Set Cmask = 1 and Edge =1 to count
occurrences.
49H
01H
DTLB_STORE_MISSES.MISS_CA Miss in all TLB levels causes a page walk of any page
USES_A_WALK
size (4K/2M/4M/1G).
49H
02H
DTLB_STORE_MISSES.WALK_C Miss in all TLB levels causes a page walk that
OMPLETED
completes of any page size (4K/2M/4M/1G).
49H
04H
DTLB_STORE_MISSES.WALK_D Cycles PMH is busy with this walk.
URATION
49H
10H
DTLB_STORE_MISSES.STLB_HI Store operations that miss the first TLB level but hit
T
the second and do not cause page walks.
Set Cmask = 1 to count
cycles.
Vol. 3B 19-45
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
4CH
01H
LOAD_HIT_PRE.SW_PF
Not SW-prefetch load dispatches that hit fill buffer
allocated for S/W prefetch.
4CH
02H
LOAD_HIT_PRE.HW_PF
Not SW-prefetch load dispatches that hit fill buffer
allocated for H/W prefetch.
4EH
02H
HW_PRE_REQ.DL1_MISS
Hardware Prefetch requests that miss the L1D
cache. A request is being counted each time it
access the cache & miss it, including if a block is
applicable or if hit the Fill Buffer for example.
51H
01H
L1D.REPLACEMENT
Counts the number of lines brought into the L1 data
cache.
51H
02H
L1D.ALLOCATED_IN_M
Counts the number of allocations of modified L1D
cache lines.
51H
04H
L1D.EVICTION
Counts the number of modified lines evicted from
the L1 data cache due to replacement.
51H
08H
L1D.ALL_M_REPLACEMENT
Cache lines in M state evicted out of L1D due to
Snoop HitM or dirty line replacement.
59H
20H
PARTIAL_RAT_STALLS.FLAGS_ Increments the number of flags-merge uops in flight
MERGE_UOP
each cycle. Set Cmask = 1 to count cycles.
59H
40H
PARTIAL_RAT_STALLS.SLOW_
LEA_WINDOW
59H
80H
PARTIAL_RAT_STALLS.MUL_SI Number of Multiply packed/scalar single precision
NGLE_UOP
uops allocated.
5BH
0CH
RESOURCE_STALLS2.ALL_FL_
EMPTY
5BH
0FH
RESOURCE_STALLS2.ALL_PRF Cycles stalled due to control structures full for
_CONTROL
physical registers.
5BH
40H
RESOURCE_STALLS2.BOB_FUL Cycles Allocator is stalled due Branch Order Buffer.
L
5BH
4FH
RESOURCE_STALLS2.OOO_RS
RC
Cycles stalled due to out of order resources full.
5CH
01H
CPL_CYCLES.RING0
Unhalted core cycles when the thread is in ring 0.
5CH
02H
CPL_CYCLES.RING123
Unhalted core cycles when the thread is not in ring
0.
5EH
01H
RS_EVENTS.EMPTY_CYCLES
Cycles the RS is empty for the thread.
60H
01H
OFFCORE_REQUESTS_OUTSTA Offcore outstanding Demand Data Read
NDING.DEMAND_DATA_RD
transactions in SQ to uncore. Set Cmask=1 to count
cycles.
60H
04H
OFFCORE_REQUESTS_OUTSTA Offcore outstanding RFO store transactions in SQ to
NDING.DEMAND_RFO
uncore. Set Cmask=1 to count cycles.
60H
08H
OFFCORE_REQUESTS_OUTSTA Offcore outstanding cacheable data read
NDING.ALL_DATA_RD
transactions in SQ to uncore. Set Cmask=1 to count
cycles.
63H
01H
LOCK_CYCLES.SPLIT_LOCK_UC Cycles in which the L1D and L2 are locked, due to a
_LOCK_DURATION
UC lock or split lock.
19-46 Vol. 3B
Comment
This accounts for both L1
streamer and IP-based
(IPP) HW prefetchers.
Cycles with at least one slow LEA uop allocated.
Cycles stalled due to free list empty.
PMC0-3 only regardless
HTT.
Use Edge to count
transition.
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
63H
02H
LOCK_CYCLES.CACHE_LOCK_D
URATION
Cycles in which the L1D is locked.
79H
02H
IDQ.EMPTY
Counts cycles the IDQ is empty.
79H
04H
IDQ.MITE_UOPS
Increment each cycle # of uops delivered to IDQ
from MITE path. Set Cmask = 1 to count cycles.
Can combine Umask 04H
and 20H.
79H
08H
IDQ.DSB_UOPS
Increment each cycle. # of uops delivered to IDQ
from DSB path. Set Cmask = 1 to count cycles.
Can combine Umask 08H
and 10H.
79H
10H
IDQ.MS_DSB_UOPS
Increment each cycle # of uops delivered to IDQ
when MS busy by DSB. Set Cmask = 1 to count
cycles MS is busy. Set Cmask=1 and Edge =1 to
count MS activations.
Can combine Umask 08H
and 10H.
79H
20H
IDQ.MS_MITE_UOPS
Increment each cycle # of uops delivered to IDQ
when MS is busy by MITE. Set Cmask = 1 to count
cycles.
Can combine Umask 04H
and 20H.
79H
30H
IDQ.MS_UOPS
Increment each cycle # of uops delivered to IDQ
from MS by either DSB or MITE. Set Cmask = 1 to
count cycles.
Can combine Umask 04H,
08H and 30H.
80H
02H
ICACHE.MISSES
Number of Instruction Cache, Streaming Buffer and
Victim Cache Misses. Includes UC accesses.
85H
01H
ITLB_MISSES.MISS_CAUSES_A
_WALK
Misses in all ITLB levels that cause page walks.
85H
02H
ITLB_MISSES.WALK_COMPLET
ED
Misses in all ITLB levels that cause completed page
walks.
85H
04H
ITLB_MISSES.WALK_DURATIO
N
Cycle PMH is busy with a walk.
85H
10H
ITLB_MISSES.STLB_HIT
Number of cache load STLB hits. No page walk.
87H
01H
ILD_STALL.LCP
Stalls caused by changing prefix length of the
instruction.
87H
04H
ILD_STALL.IQ_FULL
Stall cycles due to IQ is full.
88H
41H
BR_INST_EXEC.NONTAKEN_CO Not-taken macro conditional branches.
NDITIONAL
88H
81H
BR_INST_EXEC.TAKEN_CONDI
TIONAL
88H
82H
BR_INST_EXEC.TAKEN_DIRECT Taken speculative and retired conditional branches
_JUMP
excluding calls and indirects.
88H
84H
BR_INST_EXEC.TAKEN_INDIRE Taken speculative and retired indirect branches
CT_JUMP_NON_CALL_RET
excluding calls and returns.
88H
88H
BR_INST_EXEC.TAKEN_INDIRE Taken speculative and retired indirect branches that
CT_NEAR_RETURN
are returns.
88H
90H
BR_INST_EXEC.TAKEN_DIRECT Taken speculative and retired direct near calls.
_NEAR_CALL
88H
A0H
BR_INST_EXEC.TAKEN_INDIRE Taken speculative and retired indirect near calls.
CT_NEAR_CALL
88H
C1H
BR_INST_EXEC.ALL_CONDITIO Speculative and retired conditional branches.
NAL
Comment
Taken speculative and retired conditional branches.
Vol. 3B 19-47
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
88H
C2H
BR_INST_EXEC.ALL_DIRECT_J
UMP
Speculative and retired conditional branches
excluding calls and indirects.
88H
C4H
BR_INST_EXEC.ALL_INDIRECT
_JUMP_NON_CALL_RET
Speculative and retired indirect branches excluding
calls and returns.
88H
C8H
BR_INST_EXEC.ALL_INDIRECT
_NEAR_RETURN
Speculative and retired indirect branches that are
returns.
88H
D0H
BR_INST_EXEC.ALL_NEAR_CA
LL
Speculative and retired direct near calls.
88H
FFH
BR_INST_EXEC.ALL_BRANCHE Speculative and retired branches.
S
89H
41H
BR_MISP_EXEC.NONTAKEN_CO Not-taken mispredicted macro conditional branches.
NDITIONAL
89H
81H
BR_MISP_EXEC.TAKEN_CONDI
TIONAL
89H
84H
BR_MISP_EXEC.TAKEN_INDIRE Taken speculative and retired mispredicted indirect
CT_JUMP_NON_CALL_RET
branches excluding calls and returns.
89H
88H
BR_MISP_EXEC.TAKEN_RETUR Taken speculative and retired mispredicted indirect
N_NEAR
branches that are returns.
89H
90H
BR_MISP_EXEC.TAKEN_DIRECT Taken speculative and retired mispredicted direct
_NEAR_CALL
near calls.
89H
A0H
BR_MISP_EXEC.TAKEN_INDIRE Taken speculative and retired mispredicted indirect
CT_NEAR_CALL
near calls.
89H
C1H
BR_MISP_EXEC.ALL_CONDITIO Speculative and retired mispredicted conditional
NAL
branches.
89H
C4H
BR_MISP_EXEC.ALL_INDIRECT
_JUMP_NON_CALL_RET
89H
D0H
BR_MISP_EXEC.ALL_NEAR_CA Speculative and retired mispredicted direct near
LL
calls.
89H
FFH
BR_MISP_EXEC.ALL_BRANCHE Speculative and retired mispredicted branches.
S
9CH
01H
IDQ_UOPS_NOT_DELIVERED.C
ORE
A1H
01H
UOPS_DISPATCHED_PORT.POR Cycles which a Uop is dispatched on port 0.
T_0
A1H
02H
UOPS_DISPATCHED_PORT.POR Cycles which a Uop is dispatched on port 1.
T_1
A1H
0CH
UOPS_DISPATCHED_PORT.POR Cycles which a Uop is dispatched on port 2.
T_2
A1H
30H
UOPS_DISPATCHED_PORT.POR Cycles which a Uop is dispatched on port 3.
T_3
A1H
40H
UOPS_DISPATCHED_PORT.POR Cycles which a Uop is dispatched on port 4.
T_4
A1H
80H
UOPS_DISPATCHED_PORT.POR Cycles which a Uop is dispatched on port 5.
T_5
19-48 Vol. 3B
Comment
Taken speculative and retired mispredicted
conditional branches.
Speculative and retired mispredicted indirect
branches excluding calls and returns.
Count issue pipeline slots where no uop was
delivered from the front end to the back end when
there is no back-end stall.
Use Cmask to qualify uop
b/w.
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
A2H
01H
RESOURCE_STALLS.ANY
Cycles Allocation is stalled due to Resource Related
reason.
A2H
02H
RESOURCE_STALLS.LB
Counts the cycles of stall due to lack of load buffers.
A2H
04H
RESOURCE_STALLS.RS
Cycles stalled due to no eligible RS entry available.
A2H
08H
RESOURCE_STALLS.SB
Cycles stalled due to no store buffers available (not
including draining form sync).
A2H
10H
RESOURCE_STALLS.ROB
Cycles stalled due to re-order buffer full.
A2H
20H
RESOURCE_STALLS.FCSW
Cycles stalled due to writing the FPU control word.
A3H
01H
CYCLE_ACTIVITY.CYCLES_L2_P Cycles with pending L2 miss loads. Set AnyThread
ENDING
to count per core.
A3H
02H
CYCLE_ACTIVITY.CYCLES_L1D_ Cycles with pending L1 cache miss loads. Set
PENDING
AnyThread to count per core.
A3H
04H
CYCLE_ACTIVITY.CYCLES_NO_
DISPATCH
A3H
05H
CYCLE_ACTIVITY.STALL_CYCLE
S_L2_PENDING
PMC0-3 only.
A3H
06H
CYCLE_ACTIVITY.STALL_CYCLE
S_L1D_PENDING
PMC2 only.
A8H
01H
LSD.UOPS
Number of Uops delivered by the LSD.
ABH
01H
DSB2MITE_SWITCHES.COUNT
Number of DSB to MITE switches.
ABH
02H
DSB2MITE_SWITCHES.PENALT
Y_CYCLES
Cycles DSB to MITE switches caused delay.
ACH
02H
DSB_FILL.OTHER_CANCEL
Cases of cancelling valid DSB fill not because of
exceeding way limit.
ACH
08H
DSB_FILL.EXCEED_DSB_LINES
DSB Fill encountered > 3 DSB lines.
AEH
01H
ITLB.ITLB_FLUSH
Counts the number of ITLB flushes; includes
4k/2M/4M pages.
B0H
01H
OFFCORE_REQUESTS.DEMAND Demand data read requests sent to uncore.
_DATA_RD
B0H
04H
OFFCORE_REQUESTS.DEMAND Demand RFO read requests sent to uncore, including
_RFO
regular RFOs, locks, ItoM.
B0H
08H
OFFCORE_REQUESTS.ALL_DAT Data read requests sent to uncore (demand and
A_RD
prefetch).
B1H
01H
UOPS_DISPATCHED.THREAD
Counts total number of uops to be dispatched perthread each cycle. Set Cmask = 1, INV =1 to count
stall cycles.
PMC0-3 only regardless
HTT.
B1H
02H
UOPS_DISPATCHED.CORE
Counts total number of uops to be dispatched percore each cycle.
Do not need to set ANY.
B2H
01H
OFFCORE_REQUESTS_BUFFER Offcore requests buffer cannot take more entries
.SQ_FULL
for this thread core.
B6H
01H
AGU_BYPASS_CANCEL.COUNT
Comment
PMC2 only.
Cycles of dispatch stalls. Set AnyThread to count per PMC0-3 only.
core.
Counts executed load operations with all the
following traits: 1. Addressing of the format [base +
offset], 2. The offset is between 1 and 2047, 3. The
address specified in the base register is in one page
and the address [base+offset] is in another page.
Vol. 3B 19-49
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment
B7H
01H
OFF_CORE_RESPONSE_0
See Section 18.9.5, “Off-core Response
Performance Monitoring”.
Requires MSR 01A6H.
BBH
01H
OFF_CORE_RESPONSE_1
See Section 18.9.5, “Off-core Response
Performance Monitoring”.
Requires MSR 01A7H.
BDH
01H
TLB_FLUSH.DTLB_THREAD
DTLB flush attempts of the thread-specific entries.
BDH
20H
TLB_FLUSH.STLB_ANY
Count number of STLB flush attempts.
BFH
05H
L1D_BLOCKS.BANK_CONFLICT Cycles when dispatched loads are cancelled due to
_CYCLES
L1D bank conflicts with other load ports.
Cmask=1.
C0H
00H
INST_RETIRED.ANY_P
Number of instructions at retirement.
See Table 19-1.
C0H
01H
INST_RETIRED.PREC_DIST
Precise instruction retired event with HW to reduce PMC1 only; must quiesce
effect of PEBS shadow in IP distribution.
other PMCs.
C1H
02H
OTHER_ASSISTS.ITLB_MISS_R
ETIRED
Instructions that experienced an ITLB miss.
C1H
08H
OTHER_ASSISTS.AVX_STORE
Number of assists associated with 256-bit AVX
store operations.
C1H
10H
OTHER_ASSISTS.AVX_TO_SSE Number of transitions from AVX-256 to legacy SSE
when penalty applicable.
C1H
20H
OTHER_ASSISTS.SSE_TO_AVX Number of transitions from SSE to AVX-256 when
penalty applicable.
C2H
01H
UOPS_RETIRED.ALL
C2H
02H
UOPS_RETIRED.RETIRE_SLOTS Counts the number of retirement slots used each
cycle.
C3H
02H
MACHINE_CLEARS.MEMORY_O Counts the number of machine clears due to
RDERING
memory order conflicts.
C3H
04H
MACHINE_CLEARS.SMC
Counts the number of times that a program writes
to a code section.
C3H
20H
MACHINE_CLEARS.MASKMOV
Counts the number of executed AVX masked load
operations that refer to an illegal address range
with the mask bits set to 0.
C4H
00H
BR_INST_RETIRED.ALL_BRAN
CHES
Branch instructions at retirement.
C4H
01H
BR_INST_RETIRED.CONDITION Counts the number of conditional branch
AL
instructions retired.
Supports PEBS.
C4H
02H
BR_INST_RETIRED.NEAR_CALL Direct and indirect near call instructions retired.
Supports PEBS.
C4H
04H
BR_INST_RETIRED.ALL_BRAN
CHES
Counts the number of branch instructions retired.
Supports PEBS.
C4H
08H
BR_INST_RETIRED.NEAR_RET
URN
Counts the number of near return instructions
retired.
Supports PEBS.
C4H
10H
BR_INST_RETIRED.NOT_TAKE
N
Counts the number of not taken branch instructions
retired.
C4H
20H
BR_INST_RETIRED.NEAR_TAK
EN
Number of near taken branches retired.
19-50 Vol. 3B
Counts the number of micro-ops retired, Use
Supports PEBS.
cmask=1 and invert to count active cycles or stalled
cycles.
Supports PEBS.
See Table 19-1.
Supports PEBS.
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
C4H
40H
BR_INST_RETIRED.FAR_BRAN
CH
Number of far branches retired.
C5H
00H
BR_MISP_RETIRED.ALL_BRAN
CHES
Mispredicted branch instructions at retirement.
C5H
01H
BR_MISP_RETIRED.CONDITION Mispredicted conditional branch instructions retired. Supports PEBS.
AL
C5H
02H
BR_MISP_RETIRED.NEAR_CAL
L
Direct and indirect mispredicted near call
instructions retired.
Supports PEBS.
C5H
04H
BR_MISP_RETIRED.ALL_BRAN
CHES
Mispredicted macro branch instructions retired.
Supports PEBS.
C5H
10H
BR_MISP_RETIRED.NOT_TAKE
N
Mispredicted not taken branch instructions retired.
Supports PEBS.
C5H
20H
BR_MISP_RETIRED.TAKEN
Mispredicted taken branch instructions retired.
Supports PEBS.
CAH
02H
FP_ASSIST.X87_OUTPUT
Number of X87 assists due to output value.
CAH
04H
FP_ASSIST.X87_INPUT
Number of X87 assists due to input value.
CAH
08H
FP_ASSIST.SIMD_OUTPUT
Number of SIMD FP assists due to output values.
CAH
10H
FP_ASSIST.SIMD_INPUT
Number of SIMD FP assists due to input values.
CAH
1EH
FP_ASSIST.ANY
Cycles with any input/output SSE* or FP assists.
CCH
20H
ROB_MISC_EVENTS.LBR_INSE
RTS
Count cases of saving new LBR records by
hardware.
CDH
01H
MEM_TRANS_RETIRED.LOAD_
LATENCY
Randomly sampled loads whose latency is above a
user defined threshold. A small fraction of the
overall loads are sampled due to randomization.
PMC3 only.
CDH
02H
MEM_TRANS_RETIRED.PRECIS Sample stores and collect precise store operation
E_STORE
via PEBS record. PMC3 only.
See Section 18.9.4.3.
D0H
11H
MEM_UOPS_RETIRED.STLB_MI Retired load uops that miss the STLB.
SS_LOADS
Supports PEBS. PMC0-3
only regardless HTT.
D0H
12H
MEM_UOPS_RETIRED.STLB_MI Retired store uops that miss the STLB.
SS_STORES
Supports PEBS. PMC0-3
only regardless HTT.
D0H
21H
MEM_UOPS_RETIRED.LOCK_LO Retired load uops with locked access.
ADS
Supports PEBS. PMC0-3
only regardless HTT.
D0H
41H
MEM_UOPS_RETIRED.SPLIT_L
OADS
Retired load uops that split across a cacheline
boundary.
Supports PEBS. PMC0-3
only regardless HTT.
D0H
42H
MEM_UOPS_RETIRED.SPLIT_S
TORES
Retired store uops that split across a cacheline
boundary.
Supports PEBS. PMC0-3
only regardless HTT.
D0H
81H
MEM_UOPS_RETIRED.ALL_LOA All retired load uops.
DS
Supports PEBS. PMC0-3
only regardless HTT.
D0H
82H
MEM_UOPS_RETIRED.ALL_STO All retired store uops.
RES
Supports PEBS. PMC0-3
only regardless HTT.
D1H
01H
MEM_LOAD_UOPS_RETIRED.L
1_HIT
Retired load uops with L1 cache hits as data
sources.
Supports PEBS. PMC0-3
only regardless HTT.
D1H
02H
MEM_LOAD_UOPS_RETIRED.L
2_HIT
Retired load uops with L2 cache hits as data
sources.
Supports PEBS.
Comment
See Table 19-1.
Specify threshold in MSR
3F6H.
Vol. 3B 19-51
PERFORMANCE-MONITORING EVENTS
Table 19-13. Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™
i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family
Event
Num.
Umask
Value
D1H
04H
MEM_LOAD_UOPS_RETIRED.LL Retired load uops which data sources were data hits Supports PEBS.
C_HIT
in LLC without snoops required.
D1H
20H
MEM_LOAD_UOPS_RETIRED.LL Retired load uops which data sources were data
C_MISS
missed LLC (excluding unknown data source).
Supports PEBS.
D1H
40H
MEM_LOAD_UOPS_RETIRED.HI Retired load uops which data sources were load
T_LFB
uops missed L1 but hit FB due to preceding miss to
the same cache line with data not ready.
Supports PEBS.
D2H
01H
MEM_LOAD_UOPS_LLC_HIT_R
ETIRED.XSNP_MISS
Retired load uops whose data source was an onpackage core cache LLC hit and cross-core snoop
missed.
Supports PEBS.
D2H
02H
MEM_LOAD_UOPS_LLC_HIT_R
ETIRED.XSNP_HIT
Retired load uops whose data source was an onpackage LLC hit and cross-core snoop hits.
Supports PEBS.
D2H
04H
MEM_LOAD_UOPS_LLC_HIT_R
ETIRED.XSNP_HITM
Retired load uops whose data source was an onpackage core cache with HitM responses.
Supports PEBS.
D2H
08H
MEM_LOAD_UOPS_LLC_HIT_R
ETIRED.XSNP_NONE
Retired load uops whose data source was LLC hit
with no snoop required.
Supports PEBS.
E6H
01H
BACLEARS.ANY
Counts the number of times the front end is resteered, mainly when the BPU cannot provide a
correct prediction and this is corrected by other
branch handling mechanisms at the front end.
F0H
01H
L2_TRANS.DEMAND_DATA_RD Demand Data Read requests that access L2 cache.
F0H
02H
L2_TRANS.RFO
RFO requests that access L2 cache.
F0H
04H
L2_TRANS.CODE_RD
L2 cache accesses when fetching instructions.
F0H
08H
L2_TRANS.ALL_PF
L2 or LLC HW prefetches that access L2 cache.
F0H
10H
L2_TRANS.L1D_WB
L1D writebacks that access L2 cache.
F0H
20H
L2_TRANS.L2_FILL
L2 fill requests that access L2 cache.
F0H
40H
L2_TRANS.L2_WB
L2 writebacks that access L2 cache.
F0H
80H
L2_TRANS.ALL_REQUESTS
Transactions accessing L2 pipe.
F1H
01H
L2_LINES_IN.I
L2 cache lines in I state filling L2.
Counting does not cover
rejects.
F1H
02H
L2_LINES_IN.S
L2 cache lines in S state filling L2.
Counting does not cover
rejects.
F1H
04H
L2_LINES_IN.E
L2 cache lines in E state filling L2.
Counting does not cover
rejects.
F1H
07H
L2_LINES_IN.ALL
L2 cache lines filling L2.
Counting does not cover
rejects.
F2H
01H
L2_LINES_OUT.DEMAND_CLEA Clean L2 cache lines evicted by demand.
N
F2H
02H
L2_LINES_OUT.DEMAND_DIRT
Y
F2H
04H
L2_LINES_OUT.PF_CLEAN
Clean L2 cache lines evicted by L2 prefetch.
F2H
08H
L2_LINES_OUT.PF_DIRTY
Dirty L2 cache lines evicted by L2 prefetch.
F2H
0AH
L2_LINES_OUT.DIRTY_ALL
Dirty L2 cache lines filling the L2.
F4H
10H
SQ_MISC.SPLIT_LOCK
Split locks in SQ.
19-52 Vol. 3B
Event Mask Mnemonic
Description
Comment
Including rejects.
Dirty L2 cache lines evicted by demand.
Counting does not cover
rejects.
PERFORMANCE-MONITORING EVENTS
Non-architecture performance monitoring events in the processor core that are applicable only to Intel processors
with CPUID signature of DisplayFamily_DisplayModel 06_2AH are listed in Table 19-14.
Table 19-14. Non-Architectural Performance Events applicable only to the Processor core for 2nd Generation Intel®
Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series
Event
Num.
Umask
Value
D2H
01H
MEM_LOAD_UOPS_LLC_HIT_R Retired load uops which data sources were LLC hit and Supports PEBS. PMC0ETIRED.XSNP_MISS
cross-core snoop missed in on-pkg core cache.
3 only regardless HTT.
D2H
02H
MEM_LOAD_UOPS_LLC_HIT_R Retired load uops which data sources were LLC and
ETIRED.XSNP_HIT
cross-core snoop hits in on-pkg core cache.
Supports PEBS.
D2H
04H
MEM_LOAD_UOPS_LLC_HIT_R Retired load uops which data sources were HitM
ETIRED.XSNP_HITM
responses from shared LLC.
Supports PEBS.
D2H
08H
MEM_LOAD_UOPS_LLC_HIT_R Retired load uops which data sources were hits in LLC
ETIRED.XSNP_NONE
without snoops required.
Supports PEBS.
D4H
02H
MEM_LOAD_UOPS_MISC_RETI
RED.LLC_MISS
Retired load uops with unknown information as data
source in cache serviced the load.
Supports PEBS. PMC03 only regardless HTT.
OFF_CORE_RESPONSE_N
Sub-events of OFF_CORE_RESPONSE_N (suffix N = 0,
1) programmed using MSR 01A6H/01A7H with values
shown in the comment column.
B7H/BBH 01H
Event Mask Mnemonic
Description
Comment
OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT_N
10003C0244H
OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0244H
OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS_N
2003C0244H
OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.MISS_DRAM_N
300400244H
OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE_N
3F803C0091H
OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM_N
300400091H
OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE_N
3F803C0240H
OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0240H
OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE_N
10003C0240H
OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0240H
OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS_N
2003C0240H
OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM_N
300400240H
OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM_N
300400090H
OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE_N
3F803C0120H
OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0120H
OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE_N
10003C0120H
OFFCORE_RESPONSE.ALL_PF_RfO.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0120H
OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS_N
2003C0120H
OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM_N
300400120H
OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM_N
3004003F7H
OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE_N
3F803C0122H
OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0122H
OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE_N
10003C0122H
OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0122H
OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS_N
2003C0122H
OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM_N
300400122H
Vol. 3B 19-53
PERFORMANCE-MONITORING EVENTS
Table 19-14. Non-Architectural Performance Events applicable only to the Processor core for 2nd Generation Intel®
Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE_N
10003C0004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS_N
2003C0004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM_N
300400004H
OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM_N
300400001H
OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE_N
3F803C0002H
OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0002H
OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_N
10003C0002H
OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0002H
OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS_N
2003C0002H
OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM_N
300400002H
OFFCORE_RESPONSE.OTHER.ANY_RESPONSE_N
18000H
OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0040H
OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE_N
10003C0040H
OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0040H
OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS_N
2003C0040H
OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM_N
300400040H
OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM_N
300400010H
OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE_N
3F803C0020H
OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0020H
OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE_N
10003C0020H
OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0020H
OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS_N
2003C0020H
OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM_N
300400020H
OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0200H
OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE_N
10003C0200H
OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0200H
OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS_N
2003C0200H
OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM_N
300400200H
OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM_N
300400080H
OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE_N
3F803C0100H
OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_N
4003C0100H
OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE_N
10003C0100H
OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED_N
1003C0100H
OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS_N
2003C0100H
OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM_N
300400100H
Non-architecture performance monitoring events in the processor core that are applicable only to Intel Xeon
processor E5 family (and Intel Core i7-3930 processor) based on Intel microarchitecture code name Sandy Bridge,
with CPUID signature of DisplayFamily_DisplayModel 06_2DH, are listed in Table 19-15.
19-54 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-15. Non-Architectural Performance Events Applicable only to the Processor Core of
Intel® Xeon® Processor E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
CDH
01H
MEM_TRANS_RETIRED.LOAD_
LATENCY
Additional Configuration: Disable BL bypass and direct2core, and if the memory
is remotely homed. The count is not reliable If the memory is locally homed.
D1H
04H
MEM_LOAD_UOPS_RETIRED.LL Additional Configuration: Disable BL bypass. Supports PEBS.
C_HIT
D1H
20H
MEM_LOAD_UOPS_RETIRED.LL Additional Configuration: Disable BL bypass and direct2core. Supports PEBS.
C_MISS
D2H
01H
MEM_LOAD_UOPS_LLC_HIT_R Additional Configuration: Disable bypass. Supports PEBS.
ETIRED.XSNP_MISS
D2H
02H
MEM_LOAD_UOPS_LLC_HIT_R Additional Configuration: Disable bypass. Supports PEBS.
ETIRED.XSNP_HIT
D2H
04H
MEM_LOAD_UOPS_LLC_HIT_R Additional Configuration: Disable bypass. Supports PEBS.
ETIRED.XSNP_HITM
D2H
08H
MEM_LOAD_UOPS_LLC_HIT_R Additional Configuration: Disable bypass. Supports PEBS.
ETIRED.XSNP_NONE
D3H
01H
MEM_LOAD_UOPS_LLC_MISS_
RETIRED.LOCAL_DRAM
Retired load uops which data sources were data
missed LLC but serviced by local DRAM. Supports
PEBS.
Disable BL bypass and
direct2core (see MSR
3C9H).
D3H
04H
MEM_LOAD_UOPS_LLC_MISS_
RETIRED.REMOTE_DRAM
Retired load uops which data sources were data
missed LLC but serviced by remote DRAM. Supports
PEBS.
Disable BL bypass and
direct2core (see MSR
3C9H).
OFF_CORE_RESPONSE_N
Sub-events of OFF_CORE_RESPONSE_N (suffix N = 0,
1) programmed using MSR 01A6H/01A7H with values
shown in the comment column.
B7H/BB 01H
H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE_N
Comment
3FFFC00004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM_N
600400004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM_N
67F800004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FWD_N
87F800004H
OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM_N
107FC00004H
OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM_N
67FC00001H
OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE_N
3F803C0001H
OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM_N
600400001H
OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM_N
67F800001H
OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FWD_N
87F800001H
OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM_N
107FC00001H
OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE_N
3F803C0040H
OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM_N
67FC00010H
OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE_N
3F803C0010H
OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM_N
600400010H
OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM_N
67F800010H
OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FWD_N
87F800010H
OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM_N
107FC00010H
Vol. 3B 19-55
PERFORMANCE-MONITORING EVENTS
Table 19-15. Non-Architectural Performance Events Applicable only to the Processor Core of
Intel® Xeon® Processor E5 Family
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment
OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE_N
3FFFC00200H
OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE_N
3FFFC00080H
Non-architectural Performance monitoring events that are located in the uncore sub-system are implementation
specific between different platforms using processors based on Intel microarchitecture code name Sandy Bridge.
Processors with CPUID signature of DisplayFamily_DisplayModel 06_2AH support performance events listed in
Table 19-16.
Table 19-16. Non-Architectural Performance Events In the Processor Uncore for 2nd Generation
Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series
Event
Num.1
Umask
Value
22H
01H
UNC_CBO_XSNP_RESPONSE.M A snoop misses in some processor core.
ISS
22H
02H
UNC_CBO_XSNP_RESPONSE.I
NVAL
22H
04H
UNC_CBO_XSNP_RESPONSE.H A snoop hits a non-modified line in some processor
IT
core.
22H
08H
UNC_CBO_XSNP_RESPONSE.H A snoop hits a modified line in some processor core.
ITM
22H
10H
UNC_CBO_XSNP_RESPONSE.I
NVAL_M
A snoop invalidates a modified line in some processor
core.
22H
20H
UNC_CBO_XSNP_RESPONSE.E
XTERNAL_FILTER
Filter on cross-core snoops initiated by this Cbox due
to external snoop request.
22H
40H
UNC_CBO_XSNP_RESPONSE.X Filter on cross-core snoops initiated by this Cbox due
CORE_FILTER
to processor core memory request.
22H
80H
UNC_CBO_XSNP_RESPONSE.E
VICTION_FILTER
Filter on cross-core snoops initiated by this Cbox due
to LLC eviction.
34H
01H
UNC_CBO_CACHE_LOOKUP.M
34H
02H
UNC_CBO_CACHE_LOOKUP.E
LLC lookup request that access cache and found line in Must combine with
M-state.
one of the umask
LLC lookup request that access cache and found line in values of 10H, 20H,
40H, 80H.
E-state.
34H
04H
UNC_CBO_CACHE_LOOKUP.S
LLC lookup request that access cache and found line in
S-state.
34H
08H
UNC_CBO_CACHE_LOOKUP.I
LLC lookup request that access cache and found line in
I-state.
34H
10H
UNC_CBO_CACHE_LOOKUP.RE
AD_FILTER
Filter on processor core initiated cacheable read
requests. Must combine with at least one of 01H, 02H,
04H, 08H.
34H
20H
UNC_CBO_CACHE_LOOKUP.WR Filter on processor core initiated cacheable write
ITE_FILTER
requests. Must combine with at least one of 01H, 02H,
04H, 08H.
34H
40H
UNC_CBO_CACHE_LOOKUP.EX
TSNP_FILTER
34H
80H
UNC_CBO_CACHE_LOOKUP.AN Filter on any IRQ or IPQ initiated requests including
Y_REQUEST_FILTER
uncacheable, non-coherent requests. Must combine
with at least one of 01H, 02H, 04H, 08H.
19-56 Vol. 3B
Event Mask Mnemonic
Description
A snoop invalidates a non-modified line in some
processor core.
Filter on external snoop requests. Must combine with
at least one of 01H, 02H, 04H, 08H.
Comment
Must combine with
one of the umask
values of 20H, 40H,
80H.
Must combine with at
least one of 01H, 02H,
04H, 08H, 10H.
PERFORMANCE-MONITORING EVENTS
Table 19-16. Non-Architectural Performance Events In the Processor Uncore for 2nd Generation
Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series (Contd.)
Event
Num.1
Umask
Value
80H
01H
UNC_ARB_TRK_OCCUPANCY.A Counts cycles weighted by the number of requests
Counter 0 only.
LL
waiting for data returning from the memory controller.
Accounts for coherent and non-coherent requests
initiated by IA cores, processor graphic units, or LLC.
81H
01H
UNC_ARB_TRK_REQUEST.ALL
Counts the number of coherent and in-coherent
requests initiated by IA cores, processor graphic units,
or LLC.
81H
20H
UNC_ARB_TRK_REQUEST.WRI
TES
Counts the number of allocated write entries, include
full, partial, and LLC evictions.
81H
80H
UNC_ARB_TRK_REQUEST.EVIC Counts the number of LLC evictions allocated.
TIONS
83H
01H
UNC_ARB_COH_TRK_OCCUPA
NCY.ALL
Cycles weighted by number of requests pending in
Coherency Tracker.
84H
01H
UNC_ARB_COH_TRK_REQUES
T.ALL
Number of requests allocated in Coherency Tracker.
Event Mask Mnemonic
Description
Comment
Counter 0 only.
NOTES:
1. The uncore events must be programmed using MSRs located in specific performance monitoring units in the uncore. UNC_CBO*
events are supported using MSR_UNC_CBO* MSRs; UNC_ARB* events are supported using MSR_UNC_ARB*MSRs.
19.7
PERFORMANCE MONITORING EVENTS FOR INTEL® CORE™ I7 PROCESSOR
FAMILY AND INTEL® XEON® PROCESSOR FAMILY
Processors based on the Intel microarchitecture code name Nehalem support the architectural and non-architectural performance-monitoring events listed in Table 19-1 and Table 19-17. The events in Table 19-17 generally
applies to processors with CPUID signature of DisplayFamily_DisplayModel encoding with the following values:
06_1AH, 06_1EH, 06_1FH, and 06_2EH. However, Intel Xeon processors with CPUID signature of
DisplayFamily_DisplayModel 06_2EH have a small number of events that are not supported in processors with
CPUID signature 06_1AH, 06_1EH, and 06_1FH. These events are noted in the comment column.
In addition, these processors (CPUID signature of DisplayFamily_DisplayModel 06_1AH, 06_1EH, 06_1FH) also
support the following non-architectural, product-specific uncore performance-monitoring events listed in Table
19-18.
Fixed counters in the core PMU support the architecture events defined in Table 19-2.
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
04H
07H
SB_DRAIN.ANY
Counts the number of store buffer drains.
06H
04H
STORE_BLOCKS.AT_RET
Counts number of loads delayed with at-Retirement
block code. The following loads need to be executed
at retirement and wait for all senior stores on the
same thread to be drained: load splitting across 4K
boundary (page split), load accessing uncacheable
(UC or WC) memory, load lock, and load with page
table in UC or WC memory region.
06H
08H
STORE_BLOCKS.L1D_BLOCK
Cacheable loads delayed with L1D block code.
Comment
Vol. 3B 19-57
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
07H
01H
PARTIAL_ADDRESS_ALIAS
Counts false dependency due to partial address
aliasing.
08H
01H
DTLB_LOAD_MISSES.ANY
Counts all load misses that cause a page walk.
08H
02H
DTLB_LOAD_MISSES.WALK_CO Counts number of completed page walks due to load
MPLETED
miss in the STLB.
08H
10H
DTLB_LOAD_MISSES.STLB_HIT Number of cache load STLB hits.
08H
20H
DTLB_LOAD_MISSES.PDE_MIS
S
08H
80H
DTLB_LOAD_MISSES.LARGE_W Counts number of completed large page walks due
ALK_COMPLETED
to load miss in the STLB.
0BH
01H
MEM_INST_RETIRED.LOADS
Counts the number of instructions with an
architecturally-visible load retired on the
architected path.
0BH
02H
MEM_INST_RETIRED.STORES
Counts the number of instructions with an
architecturally-visible store retired on the
architected path.
0BH
10H
MEM_INST_RETIRED.LATENCY
_ABOVE_THRESHOLD
Counts the number of instructions exceeding the
latency specified with ld_lat facility.
0CH
01H
MEM_STORE_RETIRED.DTLB_
MISS
The event counts the number of retired stores that
missed the DTLB. The DTLB miss is not counted if
the store operation causes a fault. Does not counter
prefetches. Counts both primary and secondary
misses to the TLB.
0EH
01H
UOPS_ISSUED.ANY
Counts the number of Uops issued by the Register
Allocation Table to the Reservation Station, i.e. the
UOPs issued from the front end to the back end.
0EH
01H
UOPS_ISSUED.STALLED_CYCLE Counts the number of cycles no Uops issued by the Set “invert=1, cmask =
S
Register Allocation Table to the Reservation
1“.
Station, i.e. the UOPs issued from the front end to
the back end.
0EH
02H
UOPS_ISSUED.FUSED
Counts the number of fused Uops that were issued
from the Register Allocation Table to the
Reservation Station.
0FH
01H
MEM_UNCORE_RETIRED.L3_D
ATA_MISS_UNKNOWN
Counts number of memory load instructions retired Available only for CPUID
where the memory reference missed L3 and data
signature 06_2EH.
source is unknown.
0FH
02H
MEM_UNCORE_RETIRED.OTHE Counts number of memory load instructions retired
R_CORE_L2_HITM
where the memory reference hit modified data in a
sibling core residing on the same socket.
0FH
08H
MEM_UNCORE_RETIRED.REMO Counts number of memory load instructions retired
TE_CACHE_LOCAL_HOME_HIT where the memory reference missed the L1, L2 and
L3 caches and HIT in a remote socket's cache. Only
counts locally homed lines.
19-58 Vol. 3B
Comment
Number of DTLB cache load misses where the low
part of the linear to physical address translation
was missed.
In conjunction with ld_lat
facility.
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
0FH
10H
MEM_UNCORE_RETIRED.REMO Counts number of memory load instructions retired
TE_DRAM
where the memory reference missed the L1, L2 and
L3 caches and was remotely homed. This includes
both DRAM access and HITM in a remote socket's
cache for remotely homed lines.
0FH
20H
MEM_UNCORE_RETIRED.LOCA
L_DRAM
0FH
80H
MEM_UNCORE_RETIRED.UNCA Counts number of memory load instructions retired Available only for CPUID
CHEABLE
where the memory reference missed the L1, L2 and signature 06_2EH.
L3 caches and to perform I/O.
10H
01H
FP_COMP_OPS_EXE.X87
Counts the number of FP Computational Uops
Executed. The number of FADD, FSUB, FCOM,
FMULs, integer MULs and IMULs, FDIVs, FPREMs,
FSQRTS, integer DIVs, and IDIVs. This event does
not distinguish an FADD used in the middle of a
transcendental flow from a separate FADD
instruction.
10H
02H
FP_COMP_OPS_EXE.MMX
Counts number of MMX Uops executed.
10H
04H
FP_COMP_OPS_EXE.SSE_FP
Counts number of SSE and SSE2 FP uops executed.
10H
08H
FP_COMP_OPS_EXE.SSE2_INT Counts number of SSE2 integer uops executed.
EGER
10H
10H
FP_COMP_OPS_EXE.SSE_FP_P Counts number of SSE FP packed uops executed.
ACKED
10H
20H
FP_COMP_OPS_EXE.SSE_FP_S Counts number of SSE FP scalar uops executed.
CALAR
10H
40H
FP_COMP_OPS_EXE.SSE_SING Counts number of SSE* FP single precision uops
LE_PRECISION
executed.
10H
80H
FP_COMP_OPS_EXE.SSE_DOU
BLE_PRECISION
Counts number of SSE* FP double precision uops
executed.
12H
01H
SIMD_INT_128.PACKED_MPY
Counts number of 128 bit SIMD integer multiply
operations.
12H
02H
SIMD_INT_128.PACKED_SHIFT Counts number of 128 bit SIMD integer shift
operations.
12H
04H
SIMD_INT_128.PACK
Counts number of 128 bit SIMD integer pack
operations.
12H
08H
SIMD_INT_128.UNPACK
Counts number of 128 bit SIMD integer unpack
operations.
12H
10H
SIMD_INT_128.PACKED_LOGIC Counts number of 128 bit SIMD integer logical
AL
operations.
12H
20H
SIMD_INT_128.PACKED_ARITH Counts number of 128 bit SIMD integer arithmetic
operations.
12H
40H
SIMD_INT_128.SHUFFLE_MOV Counts number of 128 bit SIMD integer shuffle and
E
move operations.
Event Mask Mnemonic
Description
Comment
Counts number of memory load instructions retired
where the memory reference missed the L1, L2 and
L3 caches and required a local socket memory
reference. This includes locally homed cachelines
that were in a modified state in another socket.
Vol. 3B 19-59
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
13H
01H
LOAD_DISPATCH.RS
Counts number of loads dispatched from the
Reservation Station that bypass the Memory Order
Buffer.
13H
02H
LOAD_DISPATCH.RS_DELAYED
Counts the number of delayed RS dispatches at the
stage latch. If an RS dispatch cannot bypass to LB, it
has another chance to dispatch from the one-cycle
delayed staging latch before it is written into the
LB.
13H
04H
LOAD_DISPATCH.MOB
Counts the number of loads dispatched from the
Reservation Station to the Memory Order Buffer.
13H
07H
LOAD_DISPATCH.ANY
Counts all loads dispatched from the Reservation
Station.
14H
01H
ARITH.CYCLES_DIV_BUSY
Counts the number of cycles the divider is busy
executing divide or square root operations. The
divide can be integer, X87 or Streaming SIMD
Extensions (SSE). The square root operation can be
either X87 or SSE.
Comment
Count may be incorrect
When SMT is on.
Set 'edge =1, invert=1, cmask=1' to count the
number of divides.
14H
02H
ARITH.MUL
Counts the number of multiply operations executed. Count may be incorrect
This includes integer as well as floating point
When SMT is on.
multiply operations but excludes DPPS mul and
MPSAD.
17H
01H
INST_QUEUE_WRITES
Counts the number of instructions written into the
instruction queue every cycle.
18H
01H
INST_DECODED.DEC0
Counts number of instructions that require decoder
0 to be decoded. Usually, this means that the
instruction maps to more than 1 uop.
19H
01H
TWO_UOP_INSTS_DECODED
An instruction that generates two uops was
decoded.
1EH
01H
INST_QUEUE_WRITE_CYCLES
This event counts the number of cycles during
which instructions are written to the instruction
queue. Dividing this counter by the number of
instructions written to the instruction queue
(INST_QUEUE_WRITES) yields the average number
of instructions decoded each cycle. If this number is
less than four and the pipe stalls, this indicates that
the decoder is failing to decode enough instructions
per cycle to sustain the 4-wide pipeline.
20H
01H
LSD_OVERFLOW
Counts number of loops that can’t stream from the
instruction queue.
24H
01H
L2_RQSTS.LD_HIT
Counts number of loads that hit the L2 cache. L2
loads include both L1D demand misses as well as
L1D prefetches. L2 loads can be rejected for various
reasons. Only non rejected loads are counted.
24H
02H
L2_RQSTS.LD_MISS
Counts the number of loads that miss the L2 cache.
L2 loads include both L1D demand misses as well as
L1D prefetches.
19-60 Vol. 3B
If SSE* instructions that
are 6 bytes or longer
arrive one after another,
then front end
throughput may limit
execution speed.
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
24H
03H
L2_RQSTS.LOADS
Counts all L2 load requests. L2 loads include both
L1D demand misses as well as L1D prefetches.
24H
04H
L2_RQSTS.RFO_HIT
Counts the number of store RFO requests that hit
the L2 cache. L2 RFO requests include both L1D
demand RFO misses as well as L1D RFO prefetches.
Count includes WC memory requests, where the
data is not fetched but the permission to write the
line is required.
24H
08H
L2_RQSTS.RFO_MISS
Counts the number of store RFO requests that miss
the L2 cache. L2 RFO requests include both L1D
demand RFO misses as well as L1D RFO prefetches.
24H
0CH
L2_RQSTS.RFOS
Counts all L2 store RFO requests. L2 RFO requests
include both L1D demand RFO misses as well as
L1D RFO prefetches.
24H
10H
L2_RQSTS.IFETCH_HIT
Counts number of instruction fetches that hit the
L2 cache. L2 instruction fetches include both L1I
demand misses as well as L1I instruction
prefetches.
24H
20H
L2_RQSTS.IFETCH_MISS
Counts number of instruction fetches that miss the
L2 cache. L2 instruction fetches include both L1I
demand misses as well as L1I instruction
prefetches.
24H
30H
L2_RQSTS.IFETCHES
Counts all instruction fetches. L2 instruction fetches
include both L1I demand misses as well as L1I
instruction prefetches.
24H
40H
L2_RQSTS.PREFETCH_HIT
Counts L2 prefetch hits for both code and data.
24H
80H
L2_RQSTS.PREFETCH_MISS
Counts L2 prefetch misses for both code and data.
24H
C0H
L2_RQSTS.PREFETCHES
Counts all L2 prefetches for both code and data.
24H
AAH
L2_RQSTS.MISS
Counts all L2 misses for both code and data.
24H
FFH
L2_RQSTS.REFERENCES
Counts all L2 requests for both code and data.
26H
01H
L2_DATA_RQSTS.DEMAND.I_S
TATE
Counts number of L2 data demand loads where the
cache line to be loaded is in the I (invalid) state, i.e., a
cache miss. L2 demand loads are both L1D demand
misses and L1D prefetches.
26H
02H
L2_DATA_RQSTS.DEMAND.S_S Counts number of L2 data demand loads where the
TATE
cache line to be loaded is in the S (shared) state. L2
demand loads are both L1D demand misses and L1D
prefetches.
26H
04H
L2_DATA_RQSTS.DEMAND.E_S Counts number of L2 data demand loads where the
TATE
cache line to be loaded is in the E (exclusive) state.
L2 demand loads are both L1D demand misses and
L1D prefetches.
26H
08H
L2_DATA_RQSTS.DEMAND.M_
STATE
Comment
Counts number of L2 data demand loads where the
cache line to be loaded is in the M (modified) state.
L2 demand loads are both L1D demand misses and
L1D prefetches.
Vol. 3B 19-61
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
26H
0FH
L2_DATA_RQSTS.DEMAND.ME
SI
Counts all L2 data demand requests. L2 demand
loads are both L1D demand misses and L1D
prefetches.
26H
10H
L2_DATA_RQSTS.PREFETCH.I_ Counts number of L2 prefetch data loads where the
STATE
cache line to be loaded is in the I (invalid) state, i.e., a
cache miss.
26H
20H
L2_DATA_RQSTS.PREFETCH.S
_STATE
Counts number of L2 prefetch data loads where the
cache line to be loaded is in the S (shared) state. A
prefetch RFO will miss on an S state line, while a
prefetch read will hit on an S state line.
26H
40H
L2_DATA_RQSTS.PREFETCH.E
_STATE
Counts number of L2 prefetch data loads where the
cache line to be loaded is in the E (exclusive) state.
26H
80H
L2_DATA_RQSTS.PREFETCH.M Counts number of L2 prefetch data loads where the
_STATE
cache line to be loaded is in the M (modified) state.
26H
F0H
L2_DATA_RQSTS.PREFETCH.M Counts all L2 prefetch requests.
ESI
26H
FFH
L2_DATA_RQSTS.ANY
Counts all L2 data requests.
27H
01H
L2_WRITE.RFO.I_STATE
Counts number of L2 demand store RFO requests
This is a demand RFO
where the cache line to be loaded is in the I (invalid) request.
state, i.e., a cache miss. The L1D prefetcher does
not issue a RFO prefetch.
27H
02H
L2_WRITE.RFO.S_STATE
Counts number of L2 store RFO requests where the This is a demand RFO
cache line to be loaded is in the S (shared) state.
request.
The L1D prefetcher does not issue a RFO prefetch.
27H
08H
L2_WRITE.RFO.M_STATE
Counts number of L2 store RFO requests where the This is a demand RFO
cache line to be loaded is in the M (modified) state. request.
The L1D prefetcher does not issue a RFO prefetch.
27H
0EH
L2_WRITE.RFO.HIT
Counts number of L2 store RFO requests where the This is a demand RFO
cache line to be loaded is in either the S, E or M
request.
states. The L1D prefetcher does not issue a RFO
prefetch.
27H
0FH
L2_WRITE.RFO.MESI
Counts all L2 store RFO requests. The L1D
prefetcher does not issue a RFO prefetch.
27H
10H
L2_WRITE.LOCK.I_STATE
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in the I (invalid)
state, for example, a cache miss.
27H
20H
L2_WRITE.LOCK.S_STATE
Counts number of L2 lock RFO requests where the
cache line to be loaded is in the S (shared) state.
27H
40H
L2_WRITE.LOCK.E_STATE
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in the E
(exclusive) state.
27H
80H
L2_WRITE.LOCK.M_STATE
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in the M
(modified) state.
27H
E0H
L2_WRITE.LOCK.HIT
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in either the S,
E, or M state.
27H
F0H
L2_WRITE.LOCK.MESI
Counts all L2 demand lock RFO requests.
19-62 Vol. 3B
Comment
This is a demand RFO
request.
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
28H
01H
L1D_WB_L2.I_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the I (invalid) state,
i.e., a cache miss.
28H
02H
L1D_WB_L2.S_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the S state.
28H
04H
L1D_WB_L2.E_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the E (exclusive)
state.
28H
08H
L1D_WB_L2.M_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the M (modified)
state.
28H
0FH
L1D_WB_L2.MESI
Counts all L1 writebacks to the L2 .
2EH
4FH
L3_LAT_CACHE.REFERENCE
This event counts requests originating from the
See Table 19-1.
core that reference a cache line in the last level
cache. The event count includes speculative traffic
but excludes cache line fills due to a L2 hardwareprefetch. Because cache hierarchy, cache sizes and
other implementation-specific characteristics; value
comparison to estimate performance differences is
not recommended.
2EH
41H
L3_LAT_CACHE.MISS
This event counts each cache miss condition for
references to the last level cache. The event count
may include speculative traffic but excludes cache
line fills due to L2 hardware-prefetches. Because
cache hierarchy, cache sizes and other
implementation-specific characteristics; value
comparison to estimate performance differences is
not recommended.
See Table 19-1.
3CH
00H
CPU_CLK_UNHALTED.THREAD Counts the number of thread cycles while the
_P
thread is not in a halt state. The thread enters the
halt state when it is running the HLT instruction.
The core frequency may change from time to time
due to power or thermal throttling.
See Table 19-1.
3CH
01H
CPU_CLK_UNHALTED.REF_P
Increments at the frequency of TSC when not
halted.
See Table 19-1.
40H
01H
L1D_CACHE_LD.I_STATE
Counts L1 data cache read requests where the
cache line to be loaded is in the I (invalid) state, i.e.
the read request missed the cache.
Counter 0, 1 only.
40H
02H
L1D_CACHE_LD.S_STATE
Counts L1 data cache read requests where the
cache line to be loaded is in the S (shared) state.
Counter 0, 1 only.
40H
04H
L1D_CACHE_LD.E_STATE
Counts L1 data cache read requests where the
cache line to be loaded is in the E (exclusive) state.
Counter 0, 1 only.
40H
08H
L1D_CACHE_LD.M_STATE
Counts L1 data cache read requests where the
cache line to be loaded is in the M (modified) state.
Counter 0, 1 only.
40H
0FH
L1D_CACHE_LD.MESI
Counts L1 data cache read requests.
Counter 0, 1 only.
41H
02H
L1D_CACHE_ST.S_STATE
Counts L1 data cache store RFO requests where the Counter 0, 1 only.
cache line to be loaded is in the S (shared) state.
Comment
Vol. 3B 19-63
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
41H
04H
L1D_CACHE_ST.E_STATE
Counts L1 data cache store RFO requests where the Counter 0, 1 only.
cache line to be loaded is in the E (exclusive) state.
41H
08H
L1D_CACHE_ST.M_STATE
Counts L1 data cache store RFO requests where
cache line to be loaded is in the M (modified) state.
Counter 0, 1 only.
42H
01H
L1D_CACHE_LOCK.HIT
Counts retired load locks that hit in the L1 data
cache or hit in an already allocated fill buffer. The
lock portion of the load lock transaction must hit in
the L1D.
The initial load will pull
the lock into the L1 data
cache. Counter 0, 1 only.
42H
02H
L1D_CACHE_LOCK.S_STATE
Counts L1 data cache retired load locks that hit the
target cache line in the shared state.
Counter 0, 1 only.
42H
04H
L1D_CACHE_LOCK.E_STATE
Counts L1 data cache retired load locks that hit the
target cache line in the exclusive state.
Counter 0, 1 only.
42H
08H
L1D_CACHE_LOCK.M_STATE
Counts L1 data cache retired load locks that hit the
target cache line in the modified state.
Counter 0, 1 only.
43H
01H
L1D_ALL_REF.ANY
Counts all references (uncached, speculated and
retired) to the L1 data cache, including all loads and
stores with any memory types. The event counts
memory accesses only when they are actually
performed. For example, a load blocked by unknown
store address and later performed is only counted
once.
The event does not
include non-memory
accesses, such as I/O
accesses. Counter 0, 1
only.
43H
02H
L1D_ALL_REF.CACHEABLE
Counts all data reads and writes (speculated and
retired) from cacheable memory, including locked
operations.
Counter 0, 1 only.
49H
01H
DTLB_MISSES.ANY
Counts the number of misses in the STLB which
causes a page walk.
49H
02H
DTLB_MISSES.WALK_COMPLET Counts number of misses in the STLB which
ED
resulted in a completed page walk.
49H
10H
DTLB_MISSES.STLB_HIT
Counts the number of DTLB first level misses that
hit in the second level TLB. This event is only
relevant if the core contains multiple DTLB levels.
49H
20H
DTLB_MISSES.PDE_MISS
Number of DTLB misses caused by low part of
address, includes references to 2M pages because
2M pages do not use the PDE.
49H
80H
DTLB_MISSES.LARGE_WALK_C Counts number of misses in the STLB which
OMPLETED
resulted in a completed page walk for large pages.
4CH
01H
LOAD_HIT_PRE
Counts load operations sent to the L1 data cache
while a previous SSE prefetch instruction to the
same cache line has started prefetching but has not
yet finished.
4EH
01H
L1D_PREFETCH.REQUESTS
Counts number of hardware prefetch requests
dispatched out of the prefetch FIFO.
19-64 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
4EH
02H
L1D_PREFETCH.MISS
Counts number of hardware prefetch requests that
miss the L1D. There are two prefetchers in the L1D.
A streamer, which predicts lines sequentially after
this one should be fetched, and the IP prefetcher
that remembers access patterns for the current
instruction. The streamer prefetcher stops on an
L1D hit, while the IP prefetcher does not.
4EH
04H
L1D_PREFETCH.TRIGGERS
Counts number of prefetch requests triggered by
the Finite State Machine and pushed into the
prefetch FIFO. Some of the prefetch requests are
dropped due to overwrites or competition between
the IP index prefetcher and streamer prefetcher.
The prefetch FIFO contains 4 entries.
51H
01H
L1D.REPL
Counts the number of lines brought into the L1 data Counter 0, 1 only.
cache.
51H
02H
L1D.M_REPL
Counts the number of modified lines brought into
the L1 data cache.
Counter 0, 1 only.
51H
04H
L1D.M_EVICT
Counts the number of modified lines evicted from
the L1 data cache due to replacement.
Counter 0, 1 only.
51H
08H
L1D.M_SNOOP_EVICT
Counts the number of modified lines evicted from
the L1 data cache due to snoop HITM intervention.
Counter 0, 1 only.
52H
01H
L1D_CACHE_PREFETCH_LOCK
_FB_HIT
Counts the number of cacheable load lock
speculated instructions accepted into the fill buffer.
53H
01H
L1D_CACHE_LOCK_FB_HIT
Counts the number of cacheable load lock
speculated or retired instructions accepted into the
fill buffer.
63H
01H
CACHE_LOCK_CYCLES.L1D_L2
Cycle count during which the L1D and L2 are locked.
A lock is asserted when there is a locked memory
access, due to uncacheable memory, a locked
operation that spans two cache lines, or a page walk
from an uncacheable page table.
Counter 0, 1 only. L1D
and L2 locks have a very
high performance
penalty and it is highly
recommended to avoid
such accesses.
63H
02H
CACHE_LOCK_CYCLES.L1D
Counts the number of cycles that cacheline in the
L1 data cache unit is locked.
Counter 0, 1 only.
6CH
01H
IO_TRANSACTIONS
Counts the number of completed I/O transactions.
80H
01H
L1I.HITS
Counts all instruction fetches that hit the L1
instruction cache.
80H
02H
L1I.MISSES
Counts all instruction fetches that miss the L1I
cache. This includes instruction cache misses,
streaming buffer misses, victim cache misses and
uncacheable fetches. An instruction fetch miss is
counted only once and not once for every cycle it is
outstanding.
80H
03H
L1I.READS
Counts all instruction fetches, including uncacheable
fetches that bypass the L1I.
80H
04H
L1I.CYCLES_STALLED
Cycle counts for which an instruction fetch stalls
due to a L1I cache miss, ITLB miss or ITLB fault.
82H
01H
LARGE_ITLB.HIT
Counts number of large ITLB hits.
Comment
Vol. 3B 19-65
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
85H
01H
ITLB_MISSES.ANY
Counts the number of misses in all levels of the ITLB
which causes a page walk.
85H
02H
ITLB_MISSES.WALK_COMPLET
ED
Counts number of misses in all levels of the ITLB
which resulted in a completed page walk.
87H
01H
ILD_STALL.LCP
Cycles Instruction Length Decoder stalls due to
length changing prefixes: 66, 67 or REX.W (for Intel
64) instructions which change the length of the
decoded instruction.
87H
02H
ILD_STALL.MRU
Instruction Length Decoder stall cycles due to Brand
Prediction Unit (PBU) Most Recently Used (MRU)
bypass.
87H
04H
ILD_STALL.IQ_FULL
Stall cycles due to a full instruction queue.
87H
08H
ILD_STALL.REGEN
Counts the number of regen stalls.
87H
0FH
ILD_STALL.ANY
Counts any cycles the Instruction Length Decoder is
stalled.
88H
01H
BR_INST_EXEC.COND
Counts the number of conditional near branch
instructions executed, but not necessarily retired.
88H
02H
BR_INST_EXEC.DIRECT
Counts all unconditional near branch instructions
excluding calls and indirect branches.
88H
04H
BR_INST_EXEC.INDIRECT_NON Counts the number of executed indirect near
_CALL
branch instructions that are not calls.
88H
07H
BR_INST_EXEC.NON_CALLS
Counts all non-call near branch instructions
executed, but not necessarily retired.
88H
08H
BR_INST_EXEC.RETURN_NEA
R
Counts indirect near branches that have a return
mnemonic.
88H
10H
BR_INST_EXEC.DIRECT_NEAR
_CALL
Counts unconditional near call branch instructions,
excluding non-call branch, executed.
88H
20H
BR_INST_EXEC.INDIRECT_NEA Counts indirect near calls, including both register
R_CALL
and memory indirect, executed.
88H
30H
BR_INST_EXEC.NEAR_CALLS
Counts all near call branches executed, but not
necessarily retired.
88H
40H
BR_INST_EXEC.TAKEN
Counts taken near branches executed, but not
necessarily retired.
88H
7FH
BR_INST_EXEC.ANY
Counts all near executed branches (not necessarily
retired). This includes only instructions and not
micro-op branches. Frequent branching is not
necessarily a major performance issue. However
frequent branch mispredictions may be a problem.
89H
01H
BR_MISP_EXEC.COND
Counts the number of mispredicted conditional near
branch instructions executed, but not necessarily
retired.
89H
02H
BR_MISP_EXEC.DIRECT
Counts mispredicted macro unconditional near
branch instructions, excluding calls and indirect
branches (should always be 0).
89H
04H
BR_MISP_EXEC.INDIRECT_NO
N_CALL
Counts the number of executed mispredicted
indirect near branch instructions that are not calls.
19-66 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
89H
07H
BR_MISP_EXEC.NON_CALLS
Counts mispredicted non-call near branches
executed, but not necessarily retired.
89H
08H
BR_MISP_EXEC.RETURN_NEA
R
Counts mispredicted indirect branches that have a
rear return mnemonic.
89H
10H
BR_MISP_EXEC.DIRECT_NEAR
_CALL
Counts mispredicted non-indirect near calls
executed, (should always be 0).
89H
20H
BR_MISP_EXEC.INDIRECT_NEA Counts mispredicted indirect near calls executed,
R_CALL
including both register and memory indirect.
89H
30H
BR_MISP_EXEC.NEAR_CALLS
Counts all mispredicted near call branches executed,
but not necessarily retired.
89H
40H
BR_MISP_EXEC.TAKEN
Counts executed mispredicted near branches that
are taken, but not necessarily retired.
89H
7FH
BR_MISP_EXEC.ANY
Counts the number of mispredicted near branch
instructions that were executed, but not
necessarily retired.
A2H
01H
RESOURCE_STALLS.ANY
Counts the number of Allocator resource related
stalls. Includes register renaming buffer entries,
memory buffer entries. In addition to resource
related stalls, this event counts some other events.
Includes stalls arising during branch misprediction
recovery, such as if retirement of the mispredicted
branch is delayed and stalls arising while store
buffer is draining from synchronizing operations.
A2H
02H
RESOURCE_STALLS.LOAD
Counts the cycles of stall due to lack of load buffer
for load operation.
A2H
04H
RESOURCE_STALLS.RS_FULL
This event counts the number of cycles when the
number of instructions in the pipeline waiting for
execution reaches the limit the processor can
handle. A high count of this event indicates that
there are long latency operations in the pipe
(possibly load and store operations that miss the L2
cache, or instructions dependent upon instructions
further down the pipeline that have yet to retire.
A2H
08H
RESOURCE_STALLS.STORE
This event counts the number of cycles that a
resource related stall will occur due to the number
of store instructions reaching the limit of the
pipeline, (i.e. all store buffers are used). The stall
ends when a store instruction commits its data to
the cache or memory.
A2H
10H
RESOURCE_STALLS.ROB_FULL Counts the cycles of stall due to re-order buffer full.
A2H
20H
RESOURCE_STALLS.FPCW
Counts the number of cycles while execution was
stalled due to writing the floating-point unit (FPU)
control word.
A2H
40H
RESOURCE_STALLS.MXCSR
Stalls due to the MXCSR register rename occurring
to close to a previous MXCSR rename. The MXCSR
provides control and status for the MMX registers.
A2H
80H
RESOURCE_STALLS.OTHER
Counts the number of cycles while execution was
stalled due to other resource issues.
Comment
Does not include stalls
due to SuperQ (off core)
queue full, too many
cache misses, etc.
When RS is full, new
instructions cannot enter
the reservation station
and start execution.
Vol. 3B 19-67
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
A6H
01H
MACRO_INSTS.FUSIONS_DECO Counts the number of instructions decoded that are
DED
macro-fused but not necessarily executed or
retired.
A7H
01H
BACLEAR_FORCE_IQ
Counts number of times a BACLEAR was forced by
the Instruction Queue. The IQ is also responsible for
providing conditional branch prediction direction
based on a static scheme and dynamic data
provided by the L2 Branch Prediction Unit. If the
conditional branch target is not found in the Target
Array and the IQ predicts that the branch is taken,
then the IQ will force the Branch Address Calculator
to issue a BACLEAR. Each BACLEAR asserted by the
BAC generates approximately an 8 cycle bubble in
the instruction fetch pipeline.
A8H
01H
LSD.UOPS
Counts the number of micro-ops delivered by loop
stream detector.
Counts the number of ITLB flushes.
Event Mask Mnemonic
Description
AEH
01H
ITLB_FLUSH
B0H
40H
OFFCORE_REQUESTS.L1D_WR Counts number of L1D writebacks to the uncore.
ITEBACK
B1H
01H
UOPS_EXECUTED.PORT0
Counts number of uops executed that were issued
on port 0. Port 0 handles integer arithmetic, SIMD
and FP add uops.
B1H
02H
UOPS_EXECUTED.PORT1
Counts number of uops executed that were issued
on port 1. Port 1 handles integer arithmetic, SIMD,
integer shift, FP multiply and FP divide uops.
B1H
04H
UOPS_EXECUTED.PORT2_COR Counts number of uops executed that were issued
E
on port 2. Port 2 handles the load uops. This is a
core count only and cannot be collected per thread.
B1H
08H
UOPS_EXECUTED.PORT3_COR Counts number of uops executed that were issued
E
on port 3. Port 3 handles store uops. This is a core
count only and cannot be collected per thread.
B1H
10H
UOPS_EXECUTED.PORT4_COR Counts number of uops executed that where issued
E
on port 4. Port 4 handles the value to be stored for
the store uops issued on port 3. This is a core count
only and cannot be collected per thread.
B1H
1FH
UOPS_EXECUTED.CORE_ACTIV Counts cycles when the uops executed were issued
E_CYCLES_NO_PORT5
from any ports except port 5. Use Cmask=1 for
active cycles; Cmask=0 for weighted cycles. Use
CMask=1, Invert=1 to count P0-4 stalled cycles. Use
Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
B1H
20H
UOPS_EXECUTED.PORT5
B1H
3FH
UOPS_EXECUTED.CORE_ACTIV Counts cycles when the uops are executing. Use
E_CYCLES
Cmask=1 for active cycles; Cmask=0 for weighted
cycles. Use CMask=1, Invert=1 to count P0-4 stalled
cycles. Use Cmask=1, Edge=1, Invert=1 to count P04 stalls.
B1H
40H
UOPS_EXECUTED.PORT015
19-68 Vol. 3B
Comment
Use cmask=1 and invert
to count cycles.
Counts number of uops executed that where issued
on port 5.
Counts number of uops executed that where issued Use cmask=1, invert=1
on port 0, 1, or 5.
to count stall cycles.
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
B1H
80H
UOPS_EXECUTED.PORT234
Counts number of uops executed that where issued
on port 2, 3, or 4.
B2H
01H
OFFCORE_REQUESTS_SQ_FUL Counts number of cycles the SQ is full to handle offL
core requests.
B7H
01H
OFF_CORE_RESPONSE_0
See Section 18.8.1.3, “Off-core Response
Performance Monitoring in the Processor Core”.
B8H
01H
SNOOP_RESPONSE.HIT
Counts HIT snoop response sent by this thread in
response to a snoop request.
B8H
02H
SNOOP_RESPONSE.HITE
Counts HIT E snoop response sent by this thread in
response to a snoop request.
B8H
04H
SNOOP_RESPONSE.HITM
Counts HIT M snoop response sent by this thread in
response to a snoop request.
BBH
01H
OFF_CORE_RESPONSE_1
Requires programming
See Section 18.8.4, “Performance Monitoring for
Processors Based on Intel® Microarchitecture Code MSR 01A7H.
Name Westmere”.
C0H
00H
INST_RETIRED.ANY_P
See Table 19-1.
Notes: INST_RETIRED.ANY is counted by a
designated fixed counter. INST_RETIRED.ANY_P is
counted by a programmable counter and is an
architectural performance event. Event is
supported if CPUID.A.EBX[1] = 0.
Comment
Requires programming
MSR 01A6H.
Counting: Faulting
executions of
GETSEC/VM entry/VM
Exit/MWait will not count
as retired instructions.
C0H
02H
INST_RETIRED.X87
Counts the number of MMX instructions retired.
C0H
04H
INST_RETIRED.MMX
Counts the number of floating point computational
operations retired: floating point computational
operations executed by the assist handler and suboperations of complex floating point instructions
like transcendental instructions.
C2H
01H
UOPS_RETIRED.ANY
Counts the number of micro-ops retired, (macroUse cmask=1 and invert
fused=1, micro-fused=2, others=1; maximum count to count active cycles or
of 8 per cycle). Most instructions are composed of
stalled cycles.
one or two micro-ops. Some instructions are
decoded into longer sequences such as repeat
instructions, floating point transcendental
instructions, and assists.
C2H
02H
UOPS_RETIRED.RETIRE_SLOTS Counts the number of retirement slots used each
cycle.
C2H
04H
UOPS_RETIRED.MACRO_FUSE
D
Counts number of macro-fused uops retired.
C3H
01H
MACHINE_CLEARS.CYCLES
Counts the cycles machine clear is asserted.
C3H
02H
MACHINE_CLEARS.MEM_ORDE Counts the number of machine clears due to
R
memory order conflicts.
C3H
04H
MACHINE_CLEARS.SMC
Counts the number of times that a program writes
to a code section. Self-modifying code causes a
severe penalty in all Intel 64 and IA-32 processors.
The modified cache line is written back to the L2
and L3caches.
C4H
00H
BR_INST_RETIRED.ALL_BRAN
CHES
Branch instructions at retirement.
See Table 19-1.
Vol. 3B 19-69
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
C4H
01H
BR_INST_RETIRED.CONDITION Counts the number of conditional branch
AL
instructions retired.
C4H
02H
BR_INST_RETIRED.NEAR_CAL
L
Counts the number of direct & indirect near
unconditional calls retired.
C5H
00H
BR_MISP_RETIRED.ALL_BRAN
CHES
Mispredicted branch instructions at retirement.
C5H
02H
BR_MISP_RETIRED.NEAR_CAL
L
Counts mispredicted direct & indirect near
unconditional retired calls.
C7H
01H
SSEX_UOPS_RETIRED.PACKED Counts SIMD packed single-precision floating point
_SINGLE
Uops retired.
C7H
02H
SSEX_UOPS_RETIRED.SCALAR Counts SIMD scalar single-precision floating point
_SINGLE
Uops retired.
C7H
04H
SSEX_UOPS_RETIRED.PACKED Counts SIMD packed double-precision floating point
_DOUBLE
Uops retired.
C7H
08H
SSEX_UOPS_RETIRED.SCALAR Counts SIMD scalar double-precision floating point
_DOUBLE
Uops retired.
C7H
10H
SSEX_UOPS_RETIRED.VECTOR Counts 128-bit SIMD vector integer Uops retired.
_INTEGER
C8H
20H
ITLB_MISS_RETIRED
CBH
01H
MEM_LOAD_RETIRED.L1D_HIT Counts number of retired loads that hit the L1 data
cache.
CBH
02H
MEM_LOAD_RETIRED.L2_HIT
Counts number of retired loads that hit the L2 data
cache.
CBH
04H
MEM_LOAD_RETIRED.L3_UNS
HARED_HIT
Counts number of retired loads that hit their own,
unshared lines in the L3 cache.
CBH
08H
MEM_LOAD_RETIRED.OTHER_
CORE_L2_HIT_HITM
Counts number of retired loads that hit in a sibling
core's L2 (on die core). Since the L3 is inclusive of all
cores on the package, this is an L3 hit. This counts
both clean and modified hits.
CBH
10H
MEM_LOAD_RETIRED.L3_MISS Counts number of retired loads that miss the L3
cache. The load was satisfied by a remote socket,
local memory or an IOH.
CBH
40H
MEM_LOAD_RETIRED.HIT_LFB Counts number of retired loads that miss the L1D
and the address is located in an allocated line fill
buffer and will soon be committed to cache. This is
counting secondary L1D misses.
CBH
80H
MEM_LOAD_RETIRED.DTLB_MI Counts the number of retired loads that missed the
SS
DTLB. The DTLB miss is not counted if the load
operation causes a fault. This event counts loads
from cacheable memory only. The event does not
count loads by software prefetches. Counts both
primary and secondary misses to the TLB.
CCH
01H
FP_MMX_TRANS.TO_FP
19-70 Vol. 3B
Event Mask Mnemonic
Description
Counts the number of retired instructions that
missed the ITLB when the instruction was fetched.
Counts the first floating-point instruction following
any MMX instruction. You can use this event to
estimate the penalties for the transitions between
floating-point and MMX technology states.
Comment
See Table 19-1.
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
CCH
02H
FP_MMX_TRANS.TO_MMX
Counts the first MMX instruction following a
floating-point instruction. You can use this event to
estimate the penalties for the transitions between
floating-point and MMX technology states.
CCH
03H
FP_MMX_TRANS.ANY
Counts all transitions from floating point to MMX
instructions and from MMX instructions to floating
point instructions. You can use this event to
estimate the penalties for the transitions between
floating-point and MMX technology states.
D0H
01H
MACRO_INSTS.DECODED
Counts the number of instructions decoded, (but
not necessarily executed or retired).
D1H
02H
UOPS_DECODED.MS
Counts the number of Uops decoded by the
Microcode Sequencer, MS. The MS delivers uops
when the instruction is more than 4 uops long or a
microcode assist is occurring.
D1H
04H
UOPS_DECODED.ESP_FOLDING Counts number of stack pointer (ESP) instructions
decoded: push, pop, call, ret, etc. ESP instructions do
not generate a Uop to increment or decrement ESP.
Instead, they update an ESP_Offset register that
keeps track of the delta to the current value of the
ESP register.
D1H
08H
UOPS_DECODED.ESP_SYNC
Counts number of stack pointer (ESP) sync
operations where an ESP instruction is corrected by
adding the ESP offset register to the current value
of the ESP register.
D2H
01H
RAT_STALLS.FLAGS
Counts the number of cycles during which
execution stalled due to several reasons, one of
which is a partial flag register stall. A partial register
stall may occur when two conditions are met: 1) an
instruction modifies some, but not all, of the flags in
the flag register and 2) the next instruction, which
depends on flags, depends on flags that were not
modified by this instruction.
D2H
02H
RAT_STALLS.REGISTERS
This event counts the number of cycles instruction
execution latency became longer than the defined
latency because the instruction used a register that
was partially written by previous instruction.
D2H
04H
RAT_STALLS.ROB_READ_POR
T
Counts the number of cycles when ROB read port
stalls occurred, which did not allow new micro-ops
to enter the out-of-order pipeline. Note that, at this
stage in the pipeline, additional stalls may occur at
the same cycle and prevent the stalled micro-ops
from entering the pipe. In such a case, micro-ops
retry entering the execution pipe in the next cycle
and the ROB-read port stall is counted again.
D2H
08H
RAT_STALLS.SCOREBOARD
Counts the cycles where we stall due to
microarchitecturally required serialization.
Microcode scoreboarding stalls.
Comment
Vol. 3B 19-71
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
D2H
0FH
RAT_STALLS.ANY
Counts all Register Allocation Table stall cycles due
to: Cycles when ROB read port stalls occurred,
which did not allow new micro-ops to enter the
execution pipe. Cycles when partial register stalls
occurred. Cycles when flag stalls occurred. Cycles
floating-point unit (FPU) status word stalls occurred.
To count each of these conditions separately use
the events: RAT_STALLS.ROB_READ_PORT,
RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and
RAT_STALLS.FPSW.
D4H
01H
SEG_RENAME_STALLS
Counts the number of stall cycles due to the lack of
renaming resources for the ES, DS, FS, and GS
segment registers. If a segment is renamed but not
retired and a second update to the same segment
occurs, a stall occurs in the front end of the pipeline
until the renamed segment retires.
D5H
01H
ES_REG_RENAMES
Counts the number of times the ES segment
register is renamed.
DBH
01H
UOP_UNFUSION
Counts unfusion events due to floating-point
exception to a fused uop.
E0H
01H
BR_INST_DECODED
Counts the number of branch instructions decoded.
E5H
01H
BPU_MISSED_CALL_RET
Counts number of times the Branch Prediction Unit
missed predicting a call or return branch.
E6H
01H
BACLEAR.CLEAR
Counts the number of times the front end is
resteered, mainly when the Branch Prediction Unit
cannot provide a correct prediction and this is
corrected by the Branch Address Calculator at the
front end. This can occur if the code has many
branches such that they cannot be consumed by
the BPU. Each BACLEAR asserted by the BAC
generates approximately an 8 cycle bubble in the
instruction fetch pipeline. The effect on total
execution time depends on the surrounding code.
E6H
02H
BACLEAR.BAD_TARGET
Counts number of Branch Address Calculator clears
(BACLEAR) asserted due to conditional branch
instructions in which there was a target hit but the
direction was wrong. Each BACLEAR asserted by
the BAC generates approximately an 8 cycle bubble
in the instruction fetch pipeline.
E8H
01H
BPU_CLEARS.EARLY
Counts early (normal) Branch Prediction Unit clears: The BPU clear leads to 2
BPU predicted a taken branch after incorrectly
cycle bubble in the front
assuming that it was not taken.
end.
E8H
02H
BPU_CLEARS.LATE
Counts late Branch Prediction Unit clears due to
Most Recently Used conflicts. The PBU clear leads
to a 3 cycle bubble in the front end.
F0H
01H
L2_TRANSACTIONS.LOAD
Counts L2 load operations due to HW prefetch or
demand loads.
F0H
02H
L2_TRANSACTIONS.RFO
Counts L2 RFO operations due to HW prefetch or
demand RFOs.
19-72 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
F0H
04H
L2_TRANSACTIONS.IFETCH
Counts L2 instruction fetch operations due to HW
prefetch or demand ifetch.
F0H
08H
L2_TRANSACTIONS.PREFETCH Counts L2 prefetch operations.
F0H
10H
L2_TRANSACTIONS.L1D_WB
Counts L1D writeback operations to the L2.
F0H
20H
L2_TRANSACTIONS.FILL
Counts L2 cache line fill operations due to load, RFO,
L1D writeback or prefetch.
F0H
40H
L2_TRANSACTIONS.WB
Counts L2 writeback operations to the L3.
F0H
80H
L2_TRANSACTIONS.ANY
Counts all L2 cache operations.
F1H
02H
L2_LINES_IN.S_STATE
Counts the number of cache lines allocated in the
L2 cache in the S (shared) state.
F1H
04H
L2_LINES_IN.E_STATE
Counts the number of cache lines allocated in the
L2 cache in the E (exclusive) state.
F1H
07H
L2_LINES_IN.ANY
Counts the number of cache lines allocated in the
L2 cache.
F2H
01H
L2_LINES_OUT.DEMAND_CLEA Counts L2 clean cache lines evicted by a demand
N
request.
F2H
02H
L2_LINES_OUT.DEMAND_DIRT Counts L2 dirty (modified) cache lines evicted by a
Y
demand request.
F2H
04H
L2_LINES_OUT.PREFETCH_CLE Counts L2 clean cache line evicted by a prefetch
AN
request.
F2H
08H
L2_LINES_OUT.PREFETCH_DIR Counts L2 modified cache line evicted by a prefetch
TY
request.
F2H
0FH
L2_LINES_OUT.ANY
Counts all L2 cache lines evicted for any reason.
F4H
10H
SQ_MISC.SPLIT_LOCK
Counts the number of SQ lock splits across a cache
line.
F6H
01H
SQ_FULL_STALL_CYCLES
Counts cycles the Super Queue is full. Neither of the
threads on this core will be able to access the
uncore.
F7H
01H
FP_ASSIST.ALL
Counts the number of floating point operations
executed that required micro-code assist
intervention. Assists are required in the following
cases: SSE instructions (denormal input when the
DAZ flag is off or underflow result when the FTZ
flag is off); x87 instructions (NaN or denormal are
loaded to a register or used as input from memory,
division by 0 or underflow output).
F7H
02H
FP_ASSIST.OUTPUT
Counts number of floating point micro-code assist
when the output value (destination register) is
invalid.
F7H
04H
FP_ASSIST.INPUT
Counts number of floating point micro-code assist
when the input value (one of the source operands
to an FP instruction) is invalid.
FDH
01H
SIMD_INT_64.PACKED_MPY
Counts number of SID integer 64 bit packed multiply
operations.
FDH
02H
SIMD_INT_64.PACKED_SHIFT
Counts number of SID integer 64 bit packed shift
operations.
Comment
Vol. 3B 19-73
PERFORMANCE-MONITORING EVENTS
Table 19-17. Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
FDH
04H
SIMD_INT_64.PACK
Counts number of SID integer 64 bit pack
operations.
FDH
08H
SIMD_INT_64.UNPACK
Counts number of SID integer 64 bit unpack
operations.
FDH
10H
SIMD_INT_64.PACKED_LOGICA Counts number of SID integer 64 bit logical
L
operations.
FDH
20H
SIMD_INT_64.PACKED_ARITH
FDH
40H
SIMD_INT_64.SHUFFLE_MOVE Counts number of SID integer 64 bit shift or move
operations.
Comment
Counts number of SID integer 64 bit arithmetic
operations.
Non-architectural performance monitoring events that are located in the uncore sub-system are implementation
specific between different platforms using processors based on Intel microarchitecture code name Nehalem.
Processors with CPUID signature of DisplayFamily_DisplayModel 06_1AH, 06_1EH, and 06_1FH support performance events listed in Table 19-18.
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series
Event
Num.
Umask
Value
00H
01H
UNC_GQ_CYCLES_FULL.READ_ Uncore cycles Global Queue read tracker is full.
TRACKER
00H
02H
UNC_GQ_CYCLES_FULL.WRITE Uncore cycles Global Queue write tracker is full.
_TRACKER
00H
04H
UNC_GQ_CYCLES_FULL.PEER_ Uncore cycles Global Queue peer probe tracker is full.
PROBE_TRACKER
The peer probe tracker queue tracks snoops from the
IOH and remote sockets.
01H
01H
UNC_GQ_CYCLES_NOT_EMPTY Uncore cycles were Global Queue read tracker has at
.READ_TRACKER
least one valid entry.
01H
02H
UNC_GQ_CYCLES_NOT_EMPTY Uncore cycles were Global Queue write tracker has at
.WRITE_TRACKER
least one valid entry.
01H
04H
UNC_GQ_CYCLES_NOT_EMPTY Uncore cycles were Global Queue peer probe tracker
.PEER_PROBE_TRACKER
has at least one valid entry. The peer probe tracker
queue tracks IOH and remote socket snoops.
03H
01H
UNC_GQ_ALLOC.READ_TRACK Counts the number of tread tracker allocate to
ER
deallocate entries. The GQ read tracker allocate to
deallocate occupancy count is divided by the count to
obtain the average read tracker latency.
03H
02H
UNC_GQ_ALLOC.RT_L3_MISS
19-74 Vol. 3B
Event Mask Mnemonic
Description
Counts the number GQ read tracker entries for which a
full cache line read has missed the L3. The GQ read
tracker L3 miss to fill occupancy count is divided by
this count to obtain the average cache line read L3
miss latency. The latency represents the time after
which the L3 has determined that the cache line has
missed. The time between a GQ read tracker allocation
and the L3 determining that the cache line has missed
is the average L3 hit latency. The total L3 cache line
read miss latency is the hit latency + L3 miss latency.
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
03H
04H
UNC_GQ_ALLOC.RT_TO_L3_RE Counts the number of GQ read tracker entries that are
SP
allocated in the read tracker queue that hit or miss the
L3. The GQ read tracker L3 hit occupancy count is
divided by this count to obtain the average L3 hit
latency.
03H
08H
UNC_GQ_ALLOC.RT_TO_RTID_ Counts the number of GQ read tracker entries that are
ACQUIRED
allocated in the read tracker, have missed in the L3
and have not acquired a Request Transaction ID. The
GQ read tracker L3 miss to RTID acquired occupancy
count is divided by this count to obtain the average
latency for a read L3 miss to acquire an RTID.
03H
10H
UNC_GQ_ALLOC.WT_TO_RTID
_ACQUIRED
Counts the number of GQ write tracker entries that
are allocated in the write tracker, have missed in the
L3 and have not acquired a Request Transaction ID.
The GQ write tracker L3 miss to RTID occupancy count
is divided by this count to obtain the average latency
for a write L3 miss to acquire an RTID.
03H
20H
UNC_GQ_ALLOC.WRITE_TRAC
KER
Counts the number of GQ write tracker entries that
are allocated in the write tracker queue that miss the
L3. The GQ write tracker occupancy count is divided by
this count to obtain the average L3 write miss latency.
03H
40H
UNC_GQ_ALLOC.PEER_PROBE
_TRACKER
Counts the number of GQ peer probe tracker (snoop)
entries that are allocated in the peer probe tracker
queue that miss the L3. The GQ peer probe occupancy
count is divided by this count to obtain the average L3
peer probe miss latency.
04H
01H
UNC_GQ_DATA.FROM_QPI
Cycles Global Queue Quickpath Interface input data
port is busy importing data from the Quickpath
Interface. Each cycle the input port can transfer 8 or
16 bytes of data.
04H
02H
UNC_GQ_DATA.FROM_QMC
Cycles Global Queue Quickpath Memory Interface input
data port is busy importing data from the Quickpath
Memory Interface. Each cycle the input port can
transfer 8 or 16 bytes of data.
04H
04H
UNC_GQ_DATA.FROM_L3
Cycles GQ L3 input data port is busy importing data
from the Last Level Cache. Each cycle the input port
can transfer 32 bytes of data.
04H
08H
UNC_GQ_DATA.FROM_CORES_ Cycles GQ Core 0 and 2 input data port is busy
02
importing data from processor cores 0 and 2. Each
cycle the input port can transfer 32 bytes of data.
04H
10H
UNC_GQ_DATA.FROM_CORES_ Cycles GQ Core 1 and 3 input data port is busy
13
importing data from processor cores 1 and 3. Each
cycle the input port can transfer 32 bytes of data.
05H
01H
UNC_GQ_DATA.TO_QPI_QMC
Cycles GQ QPI and QMC output data port is busy
sending data to the Quickpath Interface or Quickpath
Memory Interface. Each cycle the output port can
transfer 32 bytes of data.
05H
02H
UNC_GQ_DATA.TO_L3
Cycles GQ L3 output data port is busy sending data to
the Last Level Cache. Each cycle the output port can
transfer 32 bytes of data.
Event Mask Mnemonic
Description
Comment
Vol. 3B 19-75
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
05H
04H
UNC_GQ_DATA.TO_CORES
Cycles GQ Core output data port is busy sending data
to the Cores. Each cycle the output port can transfer
32 bytes of data.
06H
01H
UNC_SNP_RESP_TO_LOCAL_H Number of snoop responses to the local home that L3
OME.I_STATE
does not have the referenced cache line.
06H
02H
UNC_SNP_RESP_TO_LOCAL_H Number of snoop responses to the local home that L3
OME.S_STATE
has the referenced line cached in the S state.
06H
04H
UNC_SNP_RESP_TO_LOCAL_H Number of responses to code or data read snoops to
OME.FWD_S_STATE
the local home that the L3 has the referenced cache
line in the E state. The L3 cache line state is changed
to the S state and the line is forwarded to the local
home in the S state.
06H
08H
UNC_SNP_RESP_TO_LOCAL_H Number of responses to read invalidate snoops to the
OME.FWD_I_STATE
local home that the L3 has the referenced cache line in
the M state. The L3 cache line state is invalidated and
the line is forwarded to the local home in the M state.
06H
10H
UNC_SNP_RESP_TO_LOCAL_H Number of conflict snoop responses sent to the local
OME.CONFLICT
home.
06H
20H
UNC_SNP_RESP_TO_LOCAL_H Number of responses to code or data read snoops to
OME.WB
the local home that the L3 has the referenced line
cached in the M state.
07H
01H
UNC_SNP_RESP_TO_REMOTE
_HOME.I_STATE
Number of snoop responses to a remote home that L3
does not have the referenced cache line.
07H
02H
UNC_SNP_RESP_TO_REMOTE
_HOME.S_STATE
Number of snoop responses to a remote home that L3
has the referenced line cached in the S state.
07H
04H
UNC_SNP_RESP_TO_REMOTE
_HOME.FWD_S_STATE
Number of responses to code or data read snoops to a
remote home that the L3 has the referenced cache
line in the E state. The L3 cache line state is changed
to the S state and the line is forwarded to the remote
home in the S state.
07H
08H
UNC_SNP_RESP_TO_REMOTE
_HOME.FWD_I_STATE
Number of responses to read invalidate snoops to a
remote home that the L3 has the referenced cache
line in the M state. The L3 cache line state is
invalidated and the line is forwarded to the remote
home in the M state.
07H
10H
UNC_SNP_RESP_TO_REMOTE
_HOME.CONFLICT
Number of conflict snoop responses sent to the local
home.
07H
20H
UNC_SNP_RESP_TO_REMOTE
_HOME.WB
Number of responses to code or data read snoops to a
remote home that the L3 has the referenced line
cached in the M state.
07H
24H
UNC_SNP_RESP_TO_REMOTE
_HOME.HITM
Number of HITM snoop responses to a remote home.
08H
01H
UNC_L3_HITS.READ
Number of code read, data read and RFO requests that
hit in the L3.
08H
02H
UNC_L3_HITS.WRITE
Number of writeback requests that hit in the L3.
Writebacks from the cores will always result in L3 hits
due to the inclusive property of the L3.
19-76 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
08H
04H
UNC_L3_HITS.PROBE
Number of snoops from IOH or remote sockets that hit
in the L3.
08H
03H
UNC_L3_HITS.ANY
Number of reads and writes that hit the L3.
09H
01H
UNC_L3_MISS.READ
Number of code read, data read and RFO requests that
miss the L3.
09H
02H
UNC_L3_MISS.WRITE
Number of writeback requests that miss the L3.
Should always be zero as writebacks from the cores
will always result in L3 hits due to the inclusive
property of the L3.
09H
04H
UNC_L3_MISS.PROBE
Number of snoops from IOH or remote sockets that
miss the L3.
09H
03H
UNC_L3_MISS.ANY
Number of reads and writes that miss the L3.
0AH
01H
UNC_L3_LINES_IN.M_STATE
Counts the number of L3 lines allocated in M state. The
only time a cache line is allocated in the M state is
when the line was forwarded in M state is forwarded
due to a Snoop Read Invalidate Own request.
0AH
02H
UNC_L3_LINES_IN.E_STATE
Counts the number of L3 lines allocated in E state.
0AH
04H
UNC_L3_LINES_IN.S_STATE
Counts the number of L3 lines allocated in S state.
0AH
08H
UNC_L3_LINES_IN.F_STATE
Counts the number of L3 lines allocated in F state.
0AH
0FH
UNC_L3_LINES_IN.ANY
Counts the number of L3 lines allocated in any state.
0BH
01H
UNC_L3_LINES_OUT.M_STATE Counts the number of L3 lines victimized that were in
the M state. When the victim cache line is in M state,
the line is written to its home cache agent which can
be either local or remote.
0BH
02H
UNC_L3_LINES_OUT.E_STATE
Counts the number of L3 lines victimized that were in
the E state.
0BH
04H
UNC_L3_LINES_OUT.S_STATE
Counts the number of L3 lines victimized that were in
the S state.
0BH
08H
UNC_L3_LINES_OUT.I_STATE
Counts the number of L3 lines victimized that were in
the I state.
0BH
10H
UNC_L3_LINES_OUT.F_STATE
Counts the number of L3 lines victimized that were in
the F state.
0BH
1FH
UNC_L3_LINES_OUT.ANY
Counts the number of L3 lines victimized in any state.
20H
01H
UNC_QHL_REQUESTS.IOH_RE
ADS
Counts number of Quickpath Home Logic read
requests from the IOH.
20H
02H
UNC_QHL_REQUESTS.IOH_WR Counts number of Quickpath Home Logic write
ITES
requests from the IOH.
20H
04H
UNC_QHL_REQUESTS.REMOTE Counts number of Quickpath Home Logic read
_READS
requests from a remote socket.
20H
08H
UNC_QHL_REQUESTS.REMOTE Counts number of Quickpath Home Logic write
_WRITES
requests from a remote socket.
20H
10H
UNC_QHL_REQUESTS.LOCAL_
READS
Counts number of Quickpath Home Logic read
requests from the local socket.
20H
20H
UNC_QHL_REQUESTS.LOCAL_
WRITES
Counts number of Quickpath Home Logic write
requests from the local socket.
Comment
Vol. 3B 19-77
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
21H
01H
UNC_QHL_CYCLES_FULL.IOH
Counts uclk cycles all entries in the Quickpath Home
Logic IOH are full.
21H
02H
UNC_QHL_CYCLES_FULL.REM
OTE
Counts uclk cycles all entries in the Quickpath Home
Logic remote tracker are full.
21H
04H
UNC_QHL_CYCLES_FULL.LOCA Counts uclk cycles all entries in the Quickpath Home
L
Logic local tracker are full.
22H
01H
UNC_QHL_CYCLES_NOT_EMPT Counts uclk cycles all entries in the Quickpath Home
Y.IOH
Logic IOH is busy.
22H
02H
UNC_QHL_CYCLES_NOT_EMPT Counts uclk cycles all entries in the Quickpath Home
Y.REMOTE
Logic remote tracker is busy.
22H
04H
UNC_QHL_CYCLES_NOT_EMPT Counts uclk cycles all entries in the Quickpath Home
Y.LOCAL
Logic local tracker is busy.
23H
01H
UNC_QHL_OCCUPANCY.IOH
23H
02H
UNC_QHL_OCCUPANCY.REMOT QHL remote tracker allocate to deallocate read
E
occupancy.
23H
04H
UNC_QHL_OCCUPANCY.LOCAL
24H
02H
UNC_QHL_ADDRESS_CONFLIC Counts number of QHL Active Address Table (AAT)
TS.2WAY
entries that saw a max of 2 conflicts. The AAT is a
structure that tracks requests that are in conflict. The
requests themselves are in the home tracker entries.
The count is reported when an AAT entry deallocates.
24H
04H
UNC_QHL_ADDRESS_CONFLIC Counts number of QHL Active Address Table (AAT)
TS.3WAY
entries that saw a max of 3 conflicts. The AAT is a
structure that tracks requests that are in conflict. The
requests themselves are in the home tracker entries.
The count is reported when an AAT entry deallocates.
25H
01H
UNC_QHL_CONFLICT_CYCLES.I Counts cycles the Quickpath Home Logic IOH Tracker
OH
contains two or more requests with an address
conflict. A max of 3 requests can be in conflict.
25H
02H
UNC_QHL_CONFLICT_CYCLES.
REMOTE
Counts cycles the Quickpath Home Logic Remote
Tracker contains two or more requests with an
address conflict. A max of 3 requests can be in conflict.
25H
04H
UNC_QHL_CONFLICT_CYCLES.
LOCAL
Counts cycles the Quickpath Home Logic Local Tracker
contains two or more requests with an address
conflict. A max of 3 requests can be in conflict.
26H
01H
UNC_QHL_TO_QMC_BYPASS
Counts number or requests to the Quickpath Memory
Controller that bypass the Quickpath Home Logic. All
local accesses can be bypassed. For remote requests,
only read requests can be bypassed.
27H
01H
UNC_QMC_NORMAL_FULL.RE
AD.CH0
Uncore cycles all the entries in the DRAM channel 0
medium or low priority queue are occupied with read
requests.
27H
02H
UNC_QMC_NORMAL_FULL.RE
AD.CH1
Uncore cycles all the entries in the DRAM channel 1
medium or low priority queue are occupied with read
requests.
19-78 Vol. 3B
QHL IOH tracker allocate to deallocate read occupancy.
QHL local tracker allocate to deallocate read
occupancy.
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
27H
04H
UNC_QMC_NORMAL_FULL.RE
AD.CH2
Uncore cycles all the entries in the DRAM channel 2
medium or low priority queue are occupied with read
requests.
27H
08H
UNC_QMC_NORMAL_FULL.WRI Uncore cycles all the entries in the DRAM channel 0
TE.CH0
medium or low priority queue are occupied with write
requests.
27H
10H
UNC_QMC_NORMAL_FULL.WRI Counts cycles all the entries in the DRAM channel 1
TE.CH1
medium or low priority queue are occupied with write
requests.
27H
20H
UNC_QMC_NORMAL_FULL.WRI Uncore cycles all the entries in the DRAM channel 2
TE.CH2
medium or low priority queue are occupied with write
requests.
28H
01H
UNC_QMC_ISOC_FULL.READ.C
H0
Counts cycles all the entries in the DRAM channel 0
high priority queue are occupied with isochronous
read requests.
28H
02H
UNC_QMC_ISOC_FULL.READ.C
H1
Counts cycles all the entries in the DRAM channel
1high priority queue are occupied with isochronous
read requests.
28H
04H
UNC_QMC_ISOC_FULL.READ.C
H2
Counts cycles all the entries in the DRAM channel 2
high priority queue are occupied with isochronous
read requests.
28H
08H
UNC_QMC_ISOC_FULL.WRITE.C Counts cycles all the entries in the DRAM channel 0
H0
high priority queue are occupied with isochronous
write requests.
28H
10H
UNC_QMC_ISOC_FULL.WRITE.C Counts cycles all the entries in the DRAM channel 1
H1
high priority queue are occupied with isochronous
write requests.
28H
20H
UNC_QMC_ISOC_FULL.WRITE.C Counts cycles all the entries in the DRAM channel 2
H2
high priority queue are occupied with isochronous
write requests.
29H
01H
UNC_QMC_BUSY.READ.CH0
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding read request to DRAM channel
0.
29H
02H
UNC_QMC_BUSY.READ.CH1
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding read request to DRAM channel
1.
29H
04H
UNC_QMC_BUSY.READ.CH2
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding read request to DRAM channel
2.
29H
08H
UNC_QMC_BUSY.WRITE.CH0
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding write request to DRAM channel
0.
29H
10H
UNC_QMC_BUSY.WRITE.CH1
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding write request to DRAM channel
1.
29H
20H
UNC_QMC_BUSY.WRITE.CH2
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding write request to DRAM channel
2.
Comment
Vol. 3B 19-79
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
2AH
01H
UNC_QMC_OCCUPANCY.CH0
IMC channel 0 normal read request occupancy.
2AH
02H
UNC_QMC_OCCUPANCY.CH1
IMC channel 1 normal read request occupancy.
2AH
04H
UNC_QMC_OCCUPANCY.CH2
IMC channel 2 normal read request occupancy.
2BH
01H
UNC_QMC_ISSOC_OCCUPANCY. IMC channel 0 issoc read request occupancy.
CH0
2BH
02H
UNC_QMC_ISSOC_OCCUPANCY. IMC channel 1 issoc read request occupancy.
CH1
2BH
04H
UNC_QMC_ISSOC_OCCUPANCY. IMC channel 2 issoc read request occupancy.
CH2
2BH
07H
UNC_QMC_ISSOC_READS.ANY
IMC issoc read request occupancy.
2CH
01H
UNC_QMC_NORMAL_READS.C
H0
Counts the number of Quickpath Memory Controller
channel 0 medium and low priority read requests. The
QMC channel 0 normal read occupancy divided by this
count provides the average QMC channel 0 read
latency.
2CH
02H
UNC_QMC_NORMAL_READS.C
H1
Counts the number of Quickpath Memory Controller
channel 1 medium and low priority read requests. The
QMC channel 1 normal read occupancy divided by this
count provides the average QMC channel 1 read
latency.
2CH
04H
UNC_QMC_NORMAL_READS.C
H2
Counts the number of Quickpath Memory Controller
channel 2 medium and low priority read requests. The
QMC channel 2 normal read occupancy divided by this
count provides the average QMC channel 2 read
latency.
2CH
07H
UNC_QMC_NORMAL_READS.A
NY
Counts the number of Quickpath Memory Controller
medium and low priority read requests. The QMC
normal read occupancy divided by this count provides
the average QMC read latency.
2DH
01H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.CH0
channel 0 high priority isochronous read requests.
2DH
02H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.CH1
channel 1 high priority isochronous read requests.
2DH
04H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.CH2
channel 2 high priority isochronous read requests.
2DH
07H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.ANY
high priority isochronous read requests.
2EH
01H
UNC_QMC_CRITICAL_PRIORIT
Y_READS.CH0
Counts the number of Quickpath Memory Controller
channel 0 critical priority isochronous read requests.
2EH
02H
UNC_QMC_CRITICAL_PRIORIT
Y_READS.CH1
Counts the number of Quickpath Memory Controller
channel 1 critical priority isochronous read requests.
2EH
04H
UNC_QMC_CRITICAL_PRIORIT
Y_READS.CH2
Counts the number of Quickpath Memory Controller
channel 2 critical priority isochronous read requests.
2EH
07H
UNC_QMC_CRITICAL_PRIORIT
Y_READS.ANY
Counts the number of Quickpath Memory Controller
critical priority isochronous read requests.
2FH
01H
UNC_QMC_WRITES.FULL.CH0
Counts number of full cache line writes to DRAM
channel 0.
19-80 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
2FH
02H
UNC_QMC_WRITES.FULL.CH1
Counts number of full cache line writes to DRAM
channel 1.
2FH
04H
UNC_QMC_WRITES.FULL.CH2
Counts number of full cache line writes to DRAM
channel 2.
2FH
07H
UNC_QMC_WRITES.FULL.ANY
Counts number of full cache line writes to DRAM.
2FH
08H
UNC_QMC_WRITES.PARTIAL.C
H0
Counts number of partial cache line writes to DRAM
channel 0.
2FH
10H
UNC_QMC_WRITES.PARTIAL.C
H1
Counts number of partial cache line writes to DRAM
channel 1.
2FH
20H
UNC_QMC_WRITES.PARTIAL.C
H2
Counts number of partial cache line writes to DRAM
channel 2.
2FH
38H
UNC_QMC_WRITES.PARTIAL.A
NY
Counts number of partial cache line writes to DRAM.
30H
01H
UNC_QMC_CANCEL.CH0
Counts number of DRAM channel 0 cancel requests.
30H
02H
UNC_QMC_CANCEL.CH1
Counts number of DRAM channel 1 cancel requests.
30H
04H
UNC_QMC_CANCEL.CH2
Counts number of DRAM channel 2 cancel requests.
30H
07H
UNC_QMC_CANCEL.ANY
Counts number of DRAM cancel requests.
31H
01H
UNC_QMC_PRIORITY_UPDATE
S.CH0
Counts number of DRAM channel 0 priority updates. A
priority update occurs when an ISOC high or critical
request is received by the QHL and there is a matching
request with normal priority that has already been
issued to the QMC. In this instance, the QHL will send
a priority update to QMC to expedite the request.
31H
02H
UNC_QMC_PRIORITY_UPDATE
S.CH1
Counts number of DRAM channel 1 priority updates. A
priority update occurs when an ISOC high or critical
request is received by the QHL and there is a matching
request with normal priority that has already been
issued to the QMC. In this instance, the QHL will send a
priority update to QMC to expedite the request.
31H
04H
UNC_QMC_PRIORITY_UPDATE
S.CH2
Counts number of DRAM channel 2 priority updates. A
priority update occurs when an ISOC high or critical
request is received by the QHL and there is a matching
request with normal priority that has already been
issued to the QMC. In this instance, the QHL will send
a priority update to QMC to expedite the request.
31H
07H
UNC_QMC_PRIORITY_UPDATE
S.ANY
Counts number of DRAM priority updates. A priority
update occurs when an ISOC high or critical request is
received by the QHL and there is a matching request
with normal priority that has already been issued to
the QMC. In this instance, the QHL will send a priority
update to QMC to expedite the request.
33H
04H
UNC_QHL_FRC_ACK_CNFLTS.L Counts number of Force Acknowledge Conflict
OCAL
messages sent by the Quickpath Home Logic to the
local home.
Comment
Vol. 3B 19-81
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
40H
01H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 0 HOME
E_FLIT.HOME.LINK_0
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
02H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 0 SNOOP
E_FLIT.SNOOP.LINK_0
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
04H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 0 non-data
E_FLIT.NDR.LINK_0
response virtual channel is stalled due to lack of a VNA
and VN0 credit. Note that this event does not filter out
when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
40H
08H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 1 HOME
E_FLIT.HOME.LINK_1
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
10H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 1 SNOOP
E_FLIT.SNOOP.LINK_1
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
20H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 1 non-data
E_FLIT.NDR.LINK_1
response virtual channel is stalled due to lack of a VNA
and VN0 credit. Note that this event does not filter out
when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
40H
07H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 0 virtual
E_FLIT.LINK_0
channels are stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
38H
UNC_QPI_TX_STALLED_SINGL Counts cycles the Quickpath outbound link 1 virtual
E_FLIT.LINK_1
channels are stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
41H
01H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 Data
_FLIT.DRS.LINK_0
Response virtual channel is stalled due to lack of VNA
and VN0 credits. Note that this event does not filter
out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
19-82 Vol. 3B
Event Mask Mnemonic
Description
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
41H
02H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 Non_FLIT.NCB.LINK_0
Coherent Bypass virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
04H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 Non_FLIT.NCS.LINK_0
Coherent Standard virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
08H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 Data
_FLIT.DRS.LINK_1
Response virtual channel is stalled due to lack of VNA
and VN0 credits. Note that this event does not filter
out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
10H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 Non_FLIT.NCB.LINK_1
Coherent Bypass virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
20H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 Non_FLIT.NCS.LINK_1
Coherent Standard virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
07H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 virtual
_FLIT.LINK_0
channels are stalled due to lack of VNA and VN0
credits. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
41H
38H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 virtual
_FLIT.LINK_1
channels are stalled due to lack of VNA and VN0
credits. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
42H
02H
UNC_QPI_TX_HEADER.BUSY.LI Number of cycles that the header buffer in the
NK_0
Quickpath Interface outbound link 0 is busy.
42H
08H
UNC_QPI_TX_HEADER.BUSY.LI Number of cycles that the header buffer in the
NK_1
Quickpath Interface outbound link 1 is busy.
43H
01H
UNC_QPI_RX_NO_PPT_CREDI
T.STALLS.LINK_0
Event Mask Mnemonic
Description
Comment
Number of cycles that snoop packets incoming to the
Quickpath Interface link 0 are stalled and not sent to
the GQ because the GQ Peer Probe Tracker (PPT) does
not have any available entries.
Vol. 3B 19-83
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
43H
02H
UNC_QPI_RX_NO_PPT_CREDI
T.STALLS.LINK_1
Number of cycles that snoop packets incoming to the
Quickpath Interface link 1 are stalled and not sent to
the GQ because the GQ Peer Probe Tracker (PPT) does
not have any available entries.
60H
01H
UNC_DRAM_OPEN.CH0
Counts number of DRAM Channel 0 open commands
issued either for read or write. To read or write data,
the referenced DRAM page must first be opened.
60H
02H
UNC_DRAM_OPEN.CH1
Counts number of DRAM Channel 1 open commands
issued either for read or write. To read or write data,
the referenced DRAM page must first be opened.
60H
04H
UNC_DRAM_OPEN.CH2
Counts number of DRAM Channel 2 open commands
issued either for read or write. To read or write data,
the referenced DRAM page must first be opened.
61H
01H
UNC_DRAM_PAGE_CLOSE.CH0 DRAM channel 0 command issued to CLOSE a page due
to page idle timer expiration. Closing a page is done by
issuing a precharge.
61H
02H
UNC_DRAM_PAGE_CLOSE.CH1 DRAM channel 1 command issued to CLOSE a page due
to page idle timer expiration. Closing a page is done by
issuing a precharge.
61H
04H
UNC_DRAM_PAGE_CLOSE.CH2 DRAM channel 2 command issued to CLOSE a page due
to page idle timer expiration. Closing a page is done by
issuing a precharge.
62H
01H
UNC_DRAM_PAGE_MISS.CH0
Counts the number of precharges (PRE) that were
issued to DRAM channel 0 because there was a page
miss. A page miss refers to a situation in which a page
is currently open and another page from the same
bank needs to be opened. The new page experiences a
page miss. Closing of the old page is done by issuing a
precharge.
62H
02H
UNC_DRAM_PAGE_MISS.CH1
Counts the number of precharges (PRE) that were
issued to DRAM channel 1 because there was a page
miss. A page miss refers to a situation in which a page
is currently open and another page from the same
bank needs to be opened. The new page experiences a
page miss. Closing of the old page is done by issuing a
precharge.
62H
04H
UNC_DRAM_PAGE_MISS.CH2
Counts the number of precharges (PRE) that were
issued to DRAM channel 2 because there was a page
miss. A page miss refers to a situation in which a page
is currently open and another page from the same
bank needs to be opened. The new page experiences a
page miss. Closing of the old page is done by issuing a
precharge.
63H
01H
UNC_DRAM_READ_CAS.CH0
Counts the number of times a read CAS command was
issued on DRAM channel 0.
63H
02H
UNC_DRAM_READ_CAS.AUTO
PRE_CH0
Counts the number of times a read CAS command was
issued on DRAM channel 0 where the command issued
used the auto-precharge (auto page close) mode.
19-84 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
63H
04H
UNC_DRAM_READ_CAS.CH1
Counts the number of times a read CAS command was
issued on DRAM channel 1.
63H
08H
UNC_DRAM_READ_CAS.AUTO
PRE_CH1
Counts the number of times a read CAS command was
issued on DRAM channel 1 where the command issued
used the auto-precharge (auto page close) mode.
63H
10H
UNC_DRAM_READ_CAS.CH2
Counts the number of times a read CAS command was
issued on DRAM channel 2.
63H
20H
UNC_DRAM_READ_CAS.AUTO
PRE_CH2
Counts the number of times a read CAS command was
issued on DRAM channel 2 where the command issued
used the auto-precharge (auto page close) mode.
64H
01H
UNC_DRAM_WRITE_CAS.CH0
Counts the number of times a write CAS command was
issued on DRAM channel 0.
64H
02H
UNC_DRAM_WRITE_CAS.AUTO Counts the number of times a write CAS command was
PRE_CH0
issued on DRAM channel 0 where the command issued
used the auto-precharge (auto page close) mode.
64H
04H
UNC_DRAM_WRITE_CAS.CH1
64H
08H
UNC_DRAM_WRITE_CAS.AUTO Counts the number of times a write CAS command was
PRE_CH1
issued on DRAM channel 1 where the command issued
used the auto-precharge (auto page close) mode.
64H
10H
UNC_DRAM_WRITE_CAS.CH2
64H
20H
UNC_DRAM_WRITE_CAS.AUTO Counts the number of times a write CAS command was
PRE_CH2
issued on DRAM channel 2 where the command issued
used the auto-precharge (auto page close) mode.
65H
01H
UNC_DRAM_REFRESH.CH0
Counts number of DRAM channel 0 refresh commands.
DRAM loses data content over time. In order to keep
correct data content, the data values have to be
refreshed periodically.
65H
02H
UNC_DRAM_REFRESH.CH1
Counts number of DRAM channel 1 refresh commands.
DRAM loses data content over time. In order to keep
correct data content, the data values have to be
refreshed periodically.
65H
04H
UNC_DRAM_REFRESH.CH2
Counts number of DRAM channel 2 refresh commands.
DRAM loses data content over time. In order to keep
correct data content, the data values have to be
refreshed periodically.
66H
01H
UNC_DRAM_PRE_ALL.CH0
Counts number of DRAM Channel 0 precharge-all
(PREALL) commands that close all open pages in a
rank. PREALL is issued when the DRAM needs to be
refreshed or needs to go into a power down mode.
Comment
Counts the number of times a write CAS command was
issued on DRAM channel 1.
Counts the number of times a write CAS command was
issued on DRAM channel 2.
Vol. 3B 19-85
PERFORMANCE-MONITORING EVENTS
Table 19-18. Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
66H
02H
UNC_DRAM_PRE_ALL.CH1
Counts number of DRAM Channel 1 precharge-all
(PREALL) commands that close all open pages in a
rank. PREALL is issued when the DRAM needs to be
refreshed or needs to go into a power down mode.
66H
04H
UNC_DRAM_PRE_ALL.CH2
Counts number of DRAM Channel 2 precharge-all
(PREALL) commands that close all open pages in a
rank. PREALL is issued when the DRAM needs to be
refreshed or needs to go into a power down mode.
Comment
Intel Xeon processors with CPUID signature of DisplayFamily_DisplayModel 06_2EH have a distinct uncore subsystem that is significantly different from the uncore found in processors with CPUID signature 06_1AH, 06_1EH,
and 06_1FH. Non-architectural Performance monitoring events for its uncore will be available in future documentation.
19.8
PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON
INTEL® MICROARCHITECTURE CODE NAME WESTMERE
Intel 64 processors based on Intel® microarchitecture code name Westmere support the architectural and nonarchitectural performance-monitoring events listed in Table 19-1 and Table 19-19. Table 19-19 applies to processors with CPUID signature of DisplayFamily_DisplayModel encoding with the following values: 06_25H, 06_2CH. In
addition, these processors (CPUID signature of DisplayFamily_DisplayModel 06_25H, 06_2CH) also support the
following non-architectural, product-specific uncore performance-monitoring events listed in Table 19-20. Fixed
counters support the architecture events defined in Table 19-2.
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere
Event
Num.
Umask
Value
03H
02H
LOAD_BLOCK.OVERLAP_STOR Loads that partially overlap an earlier store.
E
04H
07H
SB_DRAIN.ANY
All Store buffer stall cycles.
05H
02H
MISALIGN_MEMORY.STORE
All store referenced with misaligned address.
06H
04H
STORE_BLOCKS.AT_RET
Counts number of loads delayed with at-Retirement
block code. The following loads need to be executed
at retirement and wait for all senior stores on the
same thread to be drained: load splitting across 4K
boundary (page split), load accessing uncacheable
(UC or WC) memory, load lock, and load with page
table in UC or WC memory region.
06H
08H
STORE_BLOCKS.L1D_BLOCK
Cacheable loads delayed with L1D block code.
07H
01H
PARTIAL_ADDRESS_ALIAS
Counts false dependency due to partial address
aliasing.
Event Mask Mnemonic
Description
08H
01H
DTLB_LOAD_MISSES.ANY
Counts all load misses that cause a page walk.
08H
02H
DTLB_LOAD_MISSES.WALK_C
OMPLETED
Counts number of completed page walks due to load
miss in the STLB.
08H
04H
DTLB_LOAD_MISSES.WALK_CY Cycles PMH is busy with a page walk due to a load
CLES
miss in the STLB.
19-86 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
08H
10H
DTLB_LOAD_MISSES.STLB_HI
T
Number of cache load STLB hits.
08H
20H
DTLB_LOAD_MISSES.PDE_MIS
S
Number of DTLB cache load misses where the low
part of the linear to physical address translation
was missed.
0BH
01H
MEM_INST_RETIRED.LOADS
Counts the number of instructions with an
architecturally-visible load retired on the
architected path.
0BH
02H
MEM_INST_RETIRED.STORES
Counts the number of instructions with an
architecturally-visible store retired on the
architected path.
0BH
10H
MEM_INST_RETIRED.LATENCY Counts the number of instructions exceeding the
_ABOVE_THRESHOLD
latency specified with ld_lat facility.
0CH
01H
MEM_STORE_RETIRED.DTLB_
MISS
The event counts the number of retired stores that
missed the DTLB. The DTLB miss is not counted if
the store operation causes a fault. Does not counter
prefetches. Counts both primary and secondary
misses to the TLB.
0EH
01H
UOPS_ISSUED.ANY
Counts the number of Uops issued by the Register
Allocation Table to the Reservation Station, i.e. the
UOPs issued from the front end to the back end.
0EH
01H
UOPS_ISSUED.STALLED_CYCL
ES
Counts the number of cycles no uops issued by the
Register Allocation Table to the Reservation
Station, i.e. the UOPs issued from the front end to
the back end.
0EH
02H
UOPS_ISSUED.FUSED
Counts the number of fused Uops that were issued
from the Register Allocation Table to the
Reservation Station.
0FH
01H
MEM_UNCORE_RETIRED.UNK
NOWN_SOURCE
Load instructions retired with unknown LLC miss
(Precise Event).
0FH
02H
MEM_UNCORE_RETIRED.OHTE Load instructions retired that HIT modified data in
R_CORE_L2_HIT
sibling core (Precise Event).
Applicable to one and
two sockets.
0FH
04H
MEM_UNCORE_RETIRED.REMO Load instructions retired that HIT modified data in
TE_HITM
remote socket (Precise Event).
Applicable to two
sockets only.
0FH
08H
MEM_UNCORE_RETIRED.LOCA Load instructions retired local dram and remote
L_DRAM_AND_REMOTE_CACH cache HIT data sources (Precise Event).
E_HIT
Applicable to one and
two sockets.
0FH
10H
MEM_UNCORE_RETIRED.REMO Load instructions retired remote DRAM and remote
TE_DRAM
home-remote cache HITM (Precise Event).
Applicable to two
sockets only.
0FH
20H
MEM_UNCORE_RETIRED.OTHE Load instructions retired other LLC miss (Precise
R_LLC_MISS
Event).
Applicable to two
sockets only.
0FH
80H
MEM_UNCORE_RETIRED.UNCA Load instructions retired I/O (Precise Event).
CHEABLE
Applicable to one and
two sockets.
Comment
In conjunction with ld_lat
facility.
Set “invert=1, cmask =
1“.
Applicable to one and
two sockets.
Vol. 3B 19-87
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
10H
01H
FP_COMP_OPS_EXE.X87
Counts the number of FP Computational Uops
Executed. The number of FADD, FSUB, FCOM,
FMULs, integer MULs and IMULs, FDIVs, FPREMs,
FSQRTS, integer DIVs, and IDIVs. This event does
not distinguish an FADD used in the middle of a
transcendental flow from a separate FADD
instruction.
10H
02H
FP_COMP_OPS_EXE.MMX
Counts number of MMX Uops executed.
10H
04H
FP_COMP_OPS_EXE.SSE_FP
Counts number of SSE and SSE2 FP uops executed.
10H
08H
FP_COMP_OPS_EXE.SSE2_INT Counts number of SSE2 integer uops executed.
EGER
10H
10H
FP_COMP_OPS_EXE.SSE_FP_P Counts number of SSE FP packed uops executed.
ACKED
10H
20H
FP_COMP_OPS_EXE.SSE_FP_S Counts number of SSE FP scalar uops executed.
CALAR
10H
40H
FP_COMP_OPS_EXE.SSE_SING Counts number of SSE* FP single precision uops
LE_PRECISION
executed.
10H
80H
FP_COMP_OPS_EXE.SSE_DOU Counts number of SSE* FP double precision uops
BLE_PRECISION
executed.
12H
01H
SIMD_INT_128.PACKED_MPY
12H
02H
SIMD_INT_128.PACKED_SHIFT Counts number of 128 bit SIMD integer shift
operations.
12H
04H
SIMD_INT_128.PACK
Counts number of 128 bit SIMD integer pack
operations.
12H
08H
SIMD_INT_128.UNPACK
Counts number of 128 bit SIMD integer unpack
operations.
12H
10H
SIMD_INT_128.PACKED_LOGIC Counts number of 128 bit SIMD integer logical
AL
operations.
12H
20H
SIMD_INT_128.PACKED_ARIT
H
12H
40H
SIMD_INT_128.SHUFFLE_MOV Counts number of 128 bit SIMD integer shuffle and
E
move operations.
13H
01H
LOAD_DISPATCH.RS
13H
02H
LOAD_DISPATCH.RS_DELAYED Counts the number of delayed RS dispatches at the
stage latch. If an RS dispatch cannot bypass to LB, it
has another chance to dispatch from the one-cycle
delayed staging latch before it is written into the
LB.
13H
04H
LOAD_DISPATCH.MOB
Counts the number of loads dispatched from the
Reservation Station to the Memory Order Buffer.
13H
07H
LOAD_DISPATCH.ANY
Counts all loads dispatched from the Reservation
Station.
19-88 Vol. 3B
Counts number of 128 bit SIMD integer multiply
operations.
Counts number of 128 bit SIMD integer arithmetic
operations.
Counts number of loads dispatched from the
Reservation Station that bypass the Memory Order
Buffer.
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
14H
01H
ARITH.CYCLES_DIV_BUSY
Counts the number of cycles the divider is busy
Count may be incorrect
executing divide or square root operations. The
When SMT is on.
divide can be integer, X87 or Streaming SIMD
Extensions (SSE). The square root operation can be
either X87 or SSE. Set 'edge =1, invert=1, cmask=1'
to count the number of divides.
14H
02H
ARITH.MUL
Counts the number of multiply operations executed. Count may be incorrect
This includes integer as well as floating point
When SMT is on.
multiply operations but excludes DPPS mul and
MPSAD.
17H
01H
INST_QUEUE_WRITES
Counts the number of instructions written into the
instruction queue every cycle.
18H
01H
INST_DECODED.DEC0
Counts number of instructions that require decoder
0 to be decoded. Usually, this means that the
instruction maps to more than 1 uop.
19H
01H
TWO_UOP_INSTS_DECODED
An instruction that generates two uops was
decoded.
1EH
01H
INST_QUEUE_WRITE_CYCLES
This event counts the number of cycles during
which instructions are written to the instruction
queue. Dividing this counter by the number of
instructions written to the instruction queue
(INST_QUEUE_WRITES) yields the average number
of instructions decoded each cycle. If this number is
less than four and the pipe stalls, this indicates that
the decoder is failing to decode enough instructions
per cycle to sustain the 4-wide pipeline.
20H
01H
LSD_OVERFLOW
Number of loops that cannot stream from the
instruction queue.
24H
01H
L2_RQSTS.LD_HIT
Counts number of loads that hit the L2 cache. L2
loads include both L1D demand misses as well as
L1D prefetches. L2 loads can be rejected for various
reasons. Only non rejected loads are counted.
24H
02H
L2_RQSTS.LD_MISS
Counts the number of loads that miss the L2 cache.
L2 loads include both L1D demand misses as well as
L1D prefetches.
24H
03H
L2_RQSTS.LOADS
Counts all L2 load requests. L2 loads include both
L1D demand misses as well as L1D prefetches.
24H
04H
L2_RQSTS.RFO_HIT
Counts the number of store RFO requests that hit
the L2 cache. L2 RFO requests include both L1D
demand RFO misses as well as L1D RFO prefetches.
Count includes WC memory requests, where the
data is not fetched but the permission to write the
line is required.
24H
08H
L2_RQSTS.RFO_MISS
Counts the number of store RFO requests that miss
the L2 cache. L2 RFO requests include both L1D
demand RFO misses as well as L1D RFO prefetches.
24H
0CH
L2_RQSTS.RFOS
Counts all L2 store RFO requests. L2 RFO requests
include both L1D demand RFO misses as well as L1D
RFO prefetches.
Comment
If SSE* instructions that
are 6 bytes or longer
arrive one after another,
then front end
throughput may limit
execution speed.
Vol. 3B 19-89
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
24H
10H
L2_RQSTS.IFETCH_HIT
Counts number of instruction fetches that hit the
L2 cache. L2 instruction fetches include both L1I
demand misses as well as L1I instruction
prefetches.
24H
20H
L2_RQSTS.IFETCH_MISS
Counts number of instruction fetches that miss the
L2 cache. L2 instruction fetches include both L1I
demand misses as well as L1I instruction
prefetches.
24H
30H
L2_RQSTS.IFETCHES
Counts all instruction fetches. L2 instruction fetches
include both L1I demand misses as well as L1I
instruction prefetches.
24H
40H
L2_RQSTS.PREFETCH_HIT
Counts L2 prefetch hits for both code and data.
24H
80H
L2_RQSTS.PREFETCH_MISS
Counts L2 prefetch misses for both code and data.
24H
C0H
L2_RQSTS.PREFETCHES
Counts all L2 prefetches for both code and data.
24H
AAH
L2_RQSTS.MISS
Counts all L2 misses for both code and data.
24H
FFH
L2_RQSTS.REFERENCES
Counts all L2 requests for both code and data.
26H
01H
L2_DATA_RQSTS.DEMAND.I_S Counts number of L2 data demand loads where the
TATE
cache line to be loaded is in the I (invalid) state, i.e., a
cache miss. L2 demand loads are both L1D demand
misses and L1D prefetches.
26H
02H
L2_DATA_RQSTS.DEMAND.S_
STATE
Counts number of L2 data demand loads where the
cache line to be loaded is in the S (shared) state. L2
demand loads are both L1D demand misses and L1D
prefetches.
26H
04H
L2_DATA_RQSTS.DEMAND.E_
STATE
Counts number of L2 data demand loads where the
cache line to be loaded is in the E (exclusive) state.
L2 demand loads are both L1D demand misses and
L1D prefetches.
26H
08H
L2_DATA_RQSTS.DEMAND.M_ Counts number of L2 data demand loads where the
STATE
cache line to be loaded is in the M (modified) state.
L2 demand loads are both L1D demand misses and
L1D prefetches.
26H
0FH
L2_DATA_RQSTS.DEMAND.ME Counts all L2 data demand requests. L2 demand
SI
loads are both L1D demand misses and L1D
prefetches.
26H
10H
L2_DATA_RQSTS.PREFETCH.I_ Counts number of L2 prefetch data loads where the
STATE
cache line to be loaded is in the I (invalid) state, i.e., a
cache miss.
26H
20H
L2_DATA_RQSTS.PREFETCH.S Counts number of L2 prefetch data loads where the
_STATE
cache line to be loaded is in the S (shared) state. A
prefetch RFO will miss on an S state line, while a
prefetch read will hit on an S state line.
26H
40H
L2_DATA_RQSTS.PREFETCH.E Counts number of L2 prefetch data loads where the
_STATE
cache line to be loaded is in the E (exclusive) state.
26H
80H
L2_DATA_RQSTS.PREFETCH.M Counts number of L2 prefetch data loads where the
_STATE
cache line to be loaded is in the M (modified) state.
26H
F0H
L2_DATA_RQSTS.PREFETCH.M Counts all L2 prefetch requests.
ESI
19-90 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
26H
FFH
L2_DATA_RQSTS.ANY
Counts all L2 data requests.
27H
01H
L2_WRITE.RFO.I_STATE
Counts number of L2 demand store RFO requests
This is a demand RFO
where the cache line to be loaded is in the I (invalid) request.
state, i.e., a cache miss. The L1D prefetcher does
not issue a RFO prefetch.
27H
02H
L2_WRITE.RFO.S_STATE
Counts number of L2 store RFO requests where the This is a demand RFO
cache line to be loaded is in the S (shared) state.
request.
The L1D prefetcher does not issue a RFO prefetch.
27H
08H
L2_WRITE.RFO.M_STATE
Counts number of L2 store RFO requests where the This is a demand RFO
cache line to be loaded is in the M (modified) state. request.
The L1D prefetcher does not issue a RFO prefetch.
27H
0EH
L2_WRITE.RFO.HIT
Counts number of L2 store RFO requests where the This is a demand RFO
cache line to be loaded is in either the S, E or M
request.
states. The L1D prefetcher does not issue a RFO
prefetch.
27H
0FH
L2_WRITE.RFO.MESI
Counts all L2 store RFO requests. The L1D
prefetcher does not issue a RFO prefetch.
27H
10H
L2_WRITE.LOCK.I_STATE
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in the I (invalid)
state, i.e., a cache miss.
27H
20H
L2_WRITE.LOCK.S_STATE
Counts number of L2 lock RFO requests where the
cache line to be loaded is in the S (shared) state.
27H
40H
L2_WRITE.LOCK.E_STATE
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in the E
(exclusive) state.
27H
80H
L2_WRITE.LOCK.M_STATE
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in the M
(modified) state.
27H
E0H
L2_WRITE.LOCK.HIT
Counts number of L2 demand lock RFO requests
where the cache line to be loaded is in either the S,
E, or M state.
27H
F0H
L2_WRITE.LOCK.MESI
Counts all L2 demand lock RFO requests.
28H
01H
L1D_WB_L2.I_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the I (invalid) state,
i.e., a cache miss.
28H
02H
L1D_WB_L2.S_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the S state.
28H
04H
L1D_WB_L2.E_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the E (exclusive)
state.
28H
08H
L1D_WB_L2.M_STATE
Counts number of L1 writebacks to the L2 where
the cache line to be written is in the M (modified)
state.
28H
0FH
L1D_WB_L2.MESI
Counts all L1 writebacks to the L2 .
Comment
This is a demand RFO
request.
Vol. 3B 19-91
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment
2EH
41H
L3_LAT_CACHE.MISS
Counts uncore Last Level Cache misses. Because
cache hierarchy, cache sizes and other
implementation-specific characteristics; value
comparison to estimate performance differences is
not recommended.
See Table 19-1.
2EH
4FH
L3_LAT_CACHE.REFERENCE
Counts uncore Last Level Cache references.
Because cache hierarchy, cache sizes and other
implementation-specific characteristics; value
comparison to estimate performance differences is
not recommended.
See Table 19-1.
3CH
00H
CPU_CLK_UNHALTED.THREAD Counts the number of thread cycles while the
_P
thread is not in a halt state. The thread enters the
halt state when it is running the HLT instruction.
The core frequency may change from time to time
due to power or thermal throttling.
See Table 19-1.
3CH
01H
CPU_CLK_UNHALTED.REF_P
Increments at the frequency of TSC when not
halted.
See Table 19-1.
49H
01H
DTLB_MISSES.ANY
Counts the number of misses in the STLB which
causes a page walk.
49H
02H
DTLB_MISSES.WALK_COMPLE
TED
Counts number of misses in the STLB which
resulted in a completed page walk.
49H
04H
DTLB_MISSES.WALK_CYCLES
Counts cycles of page walk due to misses in the
STLB.
49H
10H
DTLB_MISSES.STLB_HIT
Counts the number of DTLB first level misses that
hit in the second level TLB. This event is only
relevant if the core contains multiple DTLB levels.
49H
20H
DTLB_MISSES.PDE_MISS
Number of DTLB misses caused by low part of
address, includes references to 2M pages because
2M pages do not use the PDE.
49H
80H
DTLB_MISSES.LARGE_WALK_C Counts number of completed large page walks due
OMPLETED
to misses in the STLB.
4CH
01H
LOAD_HIT_PRE
Counts load operations sent to the L1 data cache
Counter 0, 1 only.
while a previous SSE prefetch instruction to the
same cache line has started prefetching but has not
yet finished.
4EH
01H
L1D_PREFETCH.REQUESTS
Counts number of hardware prefetch requests
dispatched out of the prefetch FIFO.
4EH
02H
L1D_PREFETCH.MISS
Counts number of hardware prefetch requests that Counter 0, 1 only.
miss the L1D. There are two prefetchers in the L1D.
A streamer, which predicts lines sequentially after
this one should be fetched, and the IP prefetcher
that remembers access patterns for the current
instruction. The streamer prefetcher stops on an
L1D hit, while the IP prefetcher does not.
19-92 Vol. 3B
Counter 0, 1 only.
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
4EH
04H
L1D_PREFETCH.TRIGGERS
Counts number of prefetch requests triggered by
Counter 0, 1 only.
the Finite State Machine and pushed into the
prefetch FIFO. Some of the prefetch requests are
dropped due to overwrites or competition between
the IP index prefetcher and streamer prefetcher.
The prefetch FIFO contains 4 entries.
4FH
10H
EPT.WALK_CYCLES
Counts Extended Page walk cycles.
51H
01H
L1D.REPL
Counts the number of lines brought into the L1 data Counter 0, 1 only.
cache.
51H
02H
L1D.M_REPL
Counts the number of modified lines brought into
the L1 data cache.
Counter 0, 1 only.
51H
04H
L1D.M_EVICT
Counts the number of modified lines evicted from
the L1 data cache due to replacement.
Counter 0, 1 only.
51H
08H
L1D.M_SNOOP_EVICT
Counts the number of modified lines evicted from
the L1 data cache due to snoop HITM intervention.
Counter 0, 1 only.
52H
01H
L1D_CACHE_PREFETCH_LOCK Counts the number of cacheable load lock
_FB_HIT
speculated instructions accepted into the fill buffer.
60H
01H
OFFCORE_REQUESTS_OUTST Counts weighted cycles of offcore demand data
ANDING.DEMAND.READ_DATA read requests. Does not include L2 prefetch
requests.
Counter 0.
60H
02H
OFFCORE_REQUESTS_OUTST Counts weighted cycles of offcore demand code
ANDING.DEMAND.READ_CODE read requests. Does not include L2 prefetch
requests.
Counter 0.
60H
04H
OFFCORE_REQUESTS_OUTST
ANDING.DEMAND.RFO
Counts weighted cycles of offcore demand RFO
requests. Does not include L2 prefetch requests.
Counter 0.
60H
08H
OFFCORE_REQUESTS_OUTST
ANDING.ANY.READ
Counts weighted cycles of offcore read requests of
any kind. Include L2 prefetch requests.
Counter 0.
63H
01H
CACHE_LOCK_CYCLES.L1D_L2 Cycle count during which the L1D and L2 are locked.
A lock is asserted when there is a locked memory
access, due to uncacheable memory, a locked
operation that spans two cache lines, or a page walk
from an uncacheable page table. This event does
not cause locks, it merely detects them.
Counter 0, 1 only. L1D
and L2 locks have a very
high performance
penalty and it is highly
recommended to avoid
such accesses.
63H
02H
CACHE_LOCK_CYCLES.L1D
Counts the number of cycles that cacheline in the
L1 data cache unit is locked.
Counter 0, 1 only.
6CH
01H
IO_TRANSACTIONS
Counts the number of completed I/O transactions.
80H
01H
L1I.HITS
Counts all instruction fetches that hit the L1
instruction cache.
80H
02H
L1I.MISSES
Counts all instruction fetches that miss the L1I
cache. This includes instruction cache misses,
streaming buffer misses, victim cache misses and
uncacheable fetches. An instruction fetch miss is
counted only once and not once for every cycle it is
outstanding.
80H
03H
L1I.READS
Counts all instruction fetches, including uncacheable
fetches that bypass the L1I.
80H
04H
L1I.CYCLES_STALLED
Cycle counts for which an instruction fetch stalls
due to a L1I cache miss, ITLB miss or ITLB fault.
Comment
Vol. 3B 19-93
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
82H
01H
LARGE_ITLB.HIT
Counts number of large ITLB hits.
85H
01H
ITLB_MISSES.ANY
Counts the number of misses in all levels of the ITLB
which causes a page walk.
85H
02H
ITLB_MISSES.WALK_COMPLET Counts number of misses in all levels of the ITLB
ED
which resulted in a completed page walk.
85H
04H
ITLB_MISSES.WALK_CYCLES
Counts ITLB miss page walk cycles.
85H
10H
ITLB_MISSES.STLB_HIT
Counts number of ITLB first level miss but second
level hits.
85H
80H
ITLB_MISSES.LARGE_WALK_C
OMPLETED
Counts number of completed large page walks due
to misses in the STLB.
87H
01H
ILD_STALL.LCP
Cycles Instruction Length Decoder stalls due to
length changing prefixes: 66, 67 or REX.W (for Intel
64) instructions which change the length of the
decoded instruction.
87H
02H
ILD_STALL.MRU
Instruction Length Decoder stall cycles due to Brand
Prediction Unit (PBU) Most Recently Used (MRU)
bypass.
87H
04H
ILD_STALL.IQ_FULL
Stall cycles due to a full instruction queue.
87H
08H
ILD_STALL.REGEN
Counts the number of regen stalls.
87H
0FH
ILD_STALL.ANY
Counts any cycles the Instruction Length Decoder is
stalled.
88H
01H
BR_INST_EXEC.COND
Counts the number of conditional near branch
instructions executed, but not necessarily retired.
88H
02H
BR_INST_EXEC.DIRECT
Counts all unconditional near branch instructions
excluding calls and indirect branches.
88H
04H
BR_INST_EXEC.INDIRECT_NO
N_CALL
Counts the number of executed indirect near branch
instructions that are not calls.
88H
07H
BR_INST_EXEC.NON_CALLS
Counts all non-call near branch instructions
executed, but not necessarily retired.
88H
08H
BR_INST_EXEC.RETURN_NEA
R
Counts indirect near branches that have a return
mnemonic.
88H
10H
BR_INST_EXEC.DIRECT_NEAR
_CALL
Counts unconditional near call branch instructions,
excluding non-call branch, executed.
88H
20H
BR_INST_EXEC.INDIRECT_NEA Counts indirect near calls, including both register
R_CALL
and memory indirect, executed.
88H
30H
BR_INST_EXEC.NEAR_CALLS
Counts all near call branches executed, but not
necessarily retired.
88H
40H
BR_INST_EXEC.TAKEN
Counts taken near branches executed, but not
necessarily retired.
88H
7FH
BR_INST_EXEC.ANY
Counts all near executed branches (not necessarily
retired). This includes only instructions and not
micro-op branches. Frequent branching is not
necessarily a major performance issue. However
frequent branch mispredictions may be a problem.
19-94 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
89H
01H
BR_MISP_EXEC.COND
Counts the number of mispredicted conditional near
branch instructions executed, but not necessarily
retired.
89H
02H
BR_MISP_EXEC.DIRECT
Counts mispredicted macro unconditional near
branch instructions, excluding calls and indirect
branches (should always be 0).
89H
04H
BR_MISP_EXEC.INDIRECT_NO
N_CALL
Counts the number of executed mispredicted
indirect near branch instructions that are not calls.
89H
07H
BR_MISP_EXEC.NON_CALLS
Counts mispredicted non-call near branches
executed, but not necessarily retired.
89H
08H
BR_MISP_EXEC.RETURN_NEA
R
Counts mispredicted indirect branches that have a
rear return mnemonic.
89H
10H
BR_MISP_EXEC.DIRECT_NEAR Counts mispredicted non-indirect near calls
_CALL
executed, (should always be 0).
89H
20H
BR_MISP_EXEC.INDIRECT_NE
AR_CALL
Counts mispredicted indirect near calls executed,
including both register and memory indirect.
89H
30H
BR_MISP_EXEC.NEAR_CALLS
Counts all mispredicted near call branches executed,
but not necessarily retired.
89H
40H
BR_MISP_EXEC.TAKEN
Counts executed mispredicted near branches that
are taken, but not necessarily retired.
89H
7FH
BR_MISP_EXEC.ANY
Counts the number of mispredicted near branch
instructions that were executed, but not
necessarily retired.
A2H
01H
RESOURCE_STALLS.ANY
Counts the number of Allocator resource related
stalls. Includes register renaming buffer entries,
memory buffer entries. In addition to resource
related stalls, this event counts some other events.
Includes stalls arising during branch misprediction
recovery, such as if retirement of the mispredicted
branch is delayed and stalls arising while store
buffer is draining from synchronizing operations.
A2H
02H
RESOURCE_STALLS.LOAD
Counts the cycles of stall due to lack of load buffer
for load operation.
A2H
04H
RESOURCE_STALLS.RS_FULL
This event counts the number of cycles when the
number of instructions in the pipeline waiting for
execution reaches the limit the processor can
handle. A high count of this event indicates that
there are long latency operations in the pipe
(possibly load and store operations that miss the L2
cache, or instructions dependent upon instructions
further down the pipeline that have yet to retire.
A2H
08H
RESOURCE_STALLS.STORE
This event counts the number of cycles that a
resource related stall will occur due to the number
of store instructions reaching the limit of the
pipeline, (i.e. all store buffers are used). The stall
ends when a store instruction commits its data to
the cache or memory.
A2H
10H
RESOURCE_STALLS.ROB_FULL Counts the cycles of stall due to re-order buffer full.
Comment
Does not include stalls
due to SuperQ (off core)
queue full, too many
cache misses, etc.
When RS is full, new
instructions cannot enter
the reservation station
and start execution.
Vol. 3B 19-95
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
A2H
20H
RESOURCE_STALLS.FPCW
Counts the number of cycles while execution was
stalled due to writing the floating-point unit (FPU)
control word.
A2H
40H
RESOURCE_STALLS.MXCSR
Stalls due to the MXCSR register rename occurring
to close to a previous MXCSR rename. The MXCSR
provides control and status for the MMX registers.
A2H
80H
RESOURCE_STALLS.OTHER
Counts the number of cycles while execution was
stalled due to other resource issues.
A6H
01H
MACRO_INSTS.FUSIONS_DECO Counts the number of instructions decoded that are
DED
macro-fused but not necessarily executed or
retired.
A7H
01H
BACLEAR_FORCE_IQ
Counts number of times a BACLEAR was forced by
the Instruction Queue. The IQ is also responsible for
providing conditional branch prediction direction
based on a static scheme and dynamic data
provided by the L2 Branch Prediction Unit. If the
conditional branch target is not found in the Target
Array and the IQ predicts that the branch is taken,
then the IQ will force the Branch Address Calculator
to issue a BACLEAR. Each BACLEAR asserted by the
BAC generates approximately an 8 cycle bubble in
the instruction fetch pipeline.
A8H
01H
LSD.UOPS
Counts the number of micro-ops delivered by loop
stream detector.
AEH
01H
ITLB_FLUSH
Counts the number of ITLB flushes.
B0H
01H
OFFCORE_REQUESTS.DEMAN
D.READ_DATA
Counts number of offcore demand data read
requests. Does not count L2 prefetch requests.
B0H
02H
OFFCORE_REQUESTS.DEMAN
D.READ_CODE
Counts number of offcore demand code read
requests. Does not count L2 prefetch requests.
B0H
04H
OFFCORE_REQUESTS.DEMAN
D.RFO
Counts number of offcore demand RFO requests.
Does not count L2 prefetch requests.
B0H
08H
OFFCORE_REQUESTS.ANY.REA Counts number of offcore read requests. Includes
D
L2 prefetch requests.
B0H
10H
OFFCORE_REQUESTS.ANY.RFO Counts number of offcore RFO requests. Includes L2
prefetch requests.
B0H
40H
OFFCORE_REQUESTS.L1D_WR Counts number of L1D writebacks to the uncore.
ITEBACK
B0H
80H
OFFCORE_REQUESTS.ANY
Counts all offcore requests.
B1H
01H
UOPS_EXECUTED.PORT0
Counts number of uops executed that were issued
on port 0. Port 0 handles integer arithmetic, SIMD
and FP add uops.
B1H
02H
UOPS_EXECUTED.PORT1
Counts number of uops executed that were issued
on port 1. Port 1 handles integer arithmetic, SIMD,
integer shift, FP multiply and FP divide uops.
B1H
04H
UOPS_EXECUTED.PORT2_COR Counts number of uops executed that were issued
E
on port 2. Port 2 handles the load uops. This is a
core count only and cannot be collected per thread.
19-96 Vol. 3B
Comment
Use cmask=1 and invert
to count cycles.
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
B1H
08H
UOPS_EXECUTED.PORT3_COR Counts number of uops executed that were issued
E
on port 3. Port 3 handles store uops. This is a core
count only and cannot be collected per thread.
B1H
10H
UOPS_EXECUTED.PORT4_COR Counts number of uops executed that where issued
E
on port 4. Port 4 handles the value to be stored for
the store uops issued on port 3. This is a core count
only and cannot be collected per thread.
B1H
1FH
UOPS_EXECUTED.CORE_ACTI
VE_CYCLES_NO_PORT5
Counts number of cycles there are one or more
uops being executed and were issued on ports 0-4.
This is a core count only and cannot be collected per
thread.
B1H
20H
UOPS_EXECUTED.PORT5
Counts number of uops executed that where issued
on port 5.
B1H
3FH
UOPS_EXECUTED.CORE_ACTI
VE_CYCLES
Counts number of cycles there are one or more
uops being executed on any ports. This is a core
count only and cannot be collected per thread.
B1H
40H
UOPS_EXECUTED.PORT015
Counts number of uops executed that where issued Use cmask=1, invert=1
on port 0, 1, or 5.
to count stall cycles.
B1H
80H
UOPS_EXECUTED.PORT234
Counts number of uops executed that where issued
on port 2, 3, or 4.
B2H
01H
OFFCORE_REQUESTS_SQ_FUL Counts number of cycles the SQ is full to handle offL
core requests.
B3H
01H
SNOOPQ_REQUESTS_OUTSTA Counts weighted cycles of snoopq requests for
NDING.DATA
data. Counter 0 only.
Use cmask=1 to count
cycles not empty.
B3H
02H
SNOOPQ_REQUESTS_OUTSTA Counts weighted cycles of snoopq invalidate
NDING.INVALIDATE
requests. Counter 0 only.
Use cmask=1 to count
cycles not empty.
B3H
04H
SNOOPQ_REQUESTS_OUTSTA Counts weighted cycles of snoopq requests for
NDING.CODE
code. Counter 0 only.
Use cmask=1 to count
cycles not empty.
Event Mask Mnemonic
Description
B4H
01H
SNOOPQ_REQUESTS.CODE
Counts the number of snoop code requests.
B4H
02H
SNOOPQ_REQUESTS.DATA
Counts the number of snoop data requests.
B4H
04H
SNOOPQ_REQUESTS.INVALID
ATE
Counts the number of snoop invalidate requests.
B7H
01H
OFF_CORE_RESPONSE_0
See Section 18.8.1.3, “Off-core Response
Performance Monitoring in the Processor Core”.
B8H
01H
SNOOP_RESPONSE.HIT
Counts HIT snoop response sent by this thread in
response to a snoop request.
B8H
02H
SNOOP_RESPONSE.HITE
Counts HIT E snoop response sent by this thread in
response to a snoop request.
B8H
04H
SNOOP_RESPONSE.HITM
Counts HIT M snoop response sent by this thread in
response to a snoop request.
BBH
01H
OFF_CORE_RESPONSE_1
See Section 18.8.1.3, “Off-core Response
Performance Monitoring in the Processor Core”.
Comment
Requires programming
MSR 01A6H.
Use MSR 01A7H.
Vol. 3B 19-97
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment
C0H
00H
INST_RETIRED.ANY_P
See Table 19-1.
Counting: Faulting
executions of
GETSEC/VM entry/VM
Exit/MWait will not count
as retired instructions.
Notes: INST_RETIRED.ANY is counted by a
designated fixed counter. INST_RETIRED.ANY_P is
counted by a programmable counter and is an
architectural performance event. Event is
supported if CPUID.A.EBX[1] = 0.
C0H
02H
INST_RETIRED.X87
Counts the number of floating point computational
operations retired: floating point computational
operations executed by the assist handler and suboperations of complex floating point instructions
like transcendental instructions.
C0H
04H
INST_RETIRED.MMX
Counts the number of retired: MMX instructions.
C2H
01H
UOPS_RETIRED.ANY
Counts the number of micro-ops retired, (macroUse cmask=1 and invert
fused=1, micro-fused=2, others=1; maximum count to count active cycles or
of 8 per cycle). Most instructions are composed of
stalled cycles.
one or two micro-ops. Some instructions are
decoded into longer sequences such as repeat
instructions, floating point transcendental
instructions, and assists.
C2H
02H
UOPS_RETIRED.RETIRE_SLOT
S
Counts the number of retirement slots used each
cycle.
C2H
04H
UOPS_RETIRED.MACRO_FUSE
D
Counts number of macro-fused uops retired.
C3H
01H
MACHINE_CLEARS.CYCLES
Counts the cycles machine clear is asserted.
C3H
02H
MACHINE_CLEARS.MEM_ORDE Counts the number of machine clears due to
R
memory order conflicts.
C3H
04H
MACHINE_CLEARS.SMC
C4H
00H
BR_INST_RETIRED.ALL_BRAN Branch instructions at retirement.
CHES
C4H
01H
BR_INST_RETIRED.CONDITION Counts the number of conditional branch
AL
instructions retired.
C4H
02H
BR_INST_RETIRED.NEAR_CAL Counts the number of direct & indirect near
L
unconditional calls retired.
C5H
00H
BR_MISP_RETIRED.ALL_BRAN Mispredicted branch instructions at retirement.
CHES
C5H
01H
BR_MISP_RETIRED.CONDITION Counts mispredicted conditional retired calls.
AL
C5H
02H
BR_MISP_RETIRED.NEAR_CAL Counts mispredicted direct & indirect near
L
unconditional retired calls.
C5H
04H
BR_MISP_RETIRED.ALL_BRAN Counts all mispredicted retired calls.
CHES
C7H
01H
SSEX_UOPS_RETIRED.PACKED Counts SIMD packed single-precision floating-point
_SINGLE
uops retired.
19-98 Vol. 3B
Counts the number of times that a program writes
to a code section. Self-modifying code causes a
severe penalty in all Intel 64 and IA-32 processors.
The modified cache line is written back to the L2
and L3caches.
See Table 19-1.
See Table 19-1.
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
C7H
02H
SSEX_UOPS_RETIRED.SCALAR Counts SIMD scalar single-precision floating-point
_SINGLE
uops retired.
C7H
04H
SSEX_UOPS_RETIRED.PACKED Counts SIMD packed double-precision floating-point
_DOUBLE
uops retired.
C7H
08H
SSEX_UOPS_RETIRED.SCALAR Counts SIMD scalar double-precision floating-point
_DOUBLE
uops retired.
C7H
10H
SSEX_UOPS_RETIRED.VECTOR Counts 128-bit SIMD vector integer uops retired.
_INTEGER
C8H
20H
ITLB_MISS_RETIRED
CBH
01H
MEM_LOAD_RETIRED.L1D_HIT Counts number of retired loads that hit the L1 data
cache.
CBH
02H
MEM_LOAD_RETIRED.L2_HIT
Counts number of retired loads that hit the L2 data
cache.
CBH
04H
MEM_LOAD_RETIRED.L3_UNS
HARED_HIT
Counts number of retired loads that hit their own,
unshared lines in the L3 cache.
CBH
08H
MEM_LOAD_RETIRED.OTHER_ Counts number of retired loads that hit in a sibling
CORE_L2_HIT_HITM
core's L2 (on die core). Since the L3 is inclusive of all
cores on the package, this is an L3 hit. This counts
both clean and modified hits.
CBH
10H
MEM_LOAD_RETIRED.L3_MISS Counts number of retired loads that miss the L3
cache. The load was satisfied by a remote socket,
local memory or an IOH.
CBH
40H
MEM_LOAD_RETIRED.HIT_LFB Counts number of retired loads that miss the L1D
and the address is located in an allocated line fill
buffer and will soon be committed to cache. This is
counting secondary L1D misses.
CBH
80H
MEM_LOAD_RETIRED.DTLB_MI Counts the number of retired loads that missed the
SS
DTLB. The DTLB miss is not counted if the load
operation causes a fault. This event counts loads
from cacheable memory only. The event does not
count loads by software prefetches. Counts both
primary and secondary misses to the TLB.
CCH
01H
FP_MMX_TRANS.TO_FP
Counts the first floating-point instruction following
any MMX instruction. You can use this event to
estimate the penalties for the transitions between
floating-point and MMX technology states.
CCH
02H
FP_MMX_TRANS.TO_MMX
Counts the first MMX instruction following a
floating-point instruction. You can use this event to
estimate the penalties for the transitions between
floating-point and MMX technology states.
CCH
03H
FP_MMX_TRANS.ANY
Counts all transitions from floating point to MMX
instructions and from MMX instructions to floating
point instructions. You can use this event to
estimate the penalties for the transitions between
floating-point and MMX technology states.
D0H
01H
MACRO_INSTS.DECODED
Counts the number of instructions decoded, (but not
necessarily executed or retired).
Event Mask Mnemonic
Description
Comment
Counts the number of retired instructions that
missed the ITLB when the instruction was fetched.
Vol. 3B 19-99
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
D1H
01H
UOPS_DECODED.STALL_CYCLE Counts the cycles of decoder stalls. INV=1, Cmask=
S
1.
D1H
02H
UOPS_DECODED.MS
Counts the number of Uops decoded by the
Microcode Sequencer, MS. The MS delivers uops
when the instruction is more than 4 uops long or a
microcode assist is occurring.
D1H
04H
UOPS_DECODED.ESP_FOLDIN
G
Counts number of stack pointer (ESP) instructions
decoded: push, pop, call, ret, etc. ESP instructions do
not generate a Uop to increment or decrement ESP.
Instead, they update an ESP_Offset register that
keeps track of the delta to the current value of the
ESP register.
D1H
08H
UOPS_DECODED.ESP_SYNC
Counts number of stack pointer (ESP) sync
operations where an ESP instruction is corrected by
adding the ESP offset register to the current value
of the ESP register.
D2H
01H
RAT_STALLS.FLAGS
Counts the number of cycles during which
execution stalled due to several reasons, one of
which is a partial flag register stall. A partial register
stall may occur when two conditions are met: 1) an
instruction modifies some, but not all, of the flags in
the flag register and 2) the next instruction, which
depends on flags, depends on flags that were not
modified by this instruction.
D2H
02H
RAT_STALLS.REGISTERS
This event counts the number of cycles instruction
execution latency became longer than the defined
latency because the instruction used a register that
was partially written by previous instruction.
D2H
04H
RAT_STALLS.ROB_READ_POR
T
Counts the number of cycles when ROB read port
stalls occurred, which did not allow new micro-ops
to enter the out-of-order pipeline. Note that, at this
stage in the pipeline, additional stalls may occur at
the same cycle and prevent the stalled micro-ops
from entering the pipe. In such a case, micro-ops
retry entering the execution pipe in the next cycle
and the ROB-read port stall is counted again.
D2H
08H
RAT_STALLS.SCOREBOARD
Counts the cycles where we stall due to
microarchitecturally required serialization.
Microcode scoreboarding stalls.
D2H
0FH
RAT_STALLS.ANY
Counts all Register Allocation Table stall cycles due
to: Cycles when ROB read port stalls occurred,
which did not allow new micro-ops to enter the
execution pipe, Cycles when partial register stalls
occurred, Cycles when flag stalls occurred, Cycles
floating-point unit (FPU) status word stalls occurred.
To count each of these conditions separately use
the events: RAT_STALLS.ROB_READ_PORT,
RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and
RAT_STALLS.FPSW.
19-100 Vol. 3B
Event Mask Mnemonic
Description
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
D4H
01H
SEG_RENAME_STALLS
Counts the number of stall cycles due to the lack of
renaming resources for the ES, DS, FS, and GS
segment registers. If a segment is renamed but not
retired and a second update to the same segment
occurs, a stall occurs in the front end of the pipeline
until the renamed segment retires.
D5H
01H
ES_REG_RENAMES
Counts the number of times the ES segment
register is renamed.
DBH
01H
UOP_UNFUSION
Counts unfusion events due to floating point
exception to a fused uop.
E0H
01H
BR_INST_DECODED
Counts the number of branch instructions decoded.
E5H
01H
BPU_MISSED_CALL_RET
Counts number of times the Branch Prediction Unit
missed predicting a call or return branch.
E6H
01H
BACLEAR.CLEAR
Counts the number of times the front end is
resteered, mainly when the Branch Prediction Unit
cannot provide a correct prediction and this is
corrected by the Branch Address Calculator at the
front end. This can occur if the code has many
branches such that they cannot be consumed by
the BPU. Each BACLEAR asserted by the BAC
generates approximately an 8 cycle bubble in the
instruction fetch pipeline. The effect on total
execution time depends on the surrounding code.
E6H
02H
BACLEAR.BAD_TARGET
Counts number of Branch Address Calculator clears
(BACLEAR) asserted due to conditional branch
instructions in which there was a target hit but the
direction was wrong. Each BACLEAR asserted by
the BAC generates approximately an 8 cycle bubble
in the instruction fetch pipeline.
E8H
01H
BPU_CLEARS.EARLY
Counts early (normal) Branch Prediction Unit clears: The BPU clear leads to 2
BPU predicted a taken branch after incorrectly
cycle bubble in the front
assuming that it was not taken.
end.
E8H
02H
BPU_CLEARS.LATE
Counts late Branch Prediction Unit clears due to
Most Recently Used conflicts. The PBU clear leads
to a 3 cycle bubble in the front end.
ECH
01H
THREAD_ACTIVE
Counts cycles threads are active.
F0H
01H
L2_TRANSACTIONS.LOAD
Counts L2 load operations due to HW prefetch or
demand loads.
F0H
02H
L2_TRANSACTIONS.RFO
Counts L2 RFO operations due to HW prefetch or
demand RFOs.
F0H
04H
L2_TRANSACTIONS.IFETCH
Counts L2 instruction fetch operations due to HW
prefetch or demand ifetch.
F0H
08H
L2_TRANSACTIONS.PREFETC
H
Counts L2 prefetch operations.
F0H
10H
L2_TRANSACTIONS.L1D_WB
Counts L1D writeback operations to the L2.
F0H
20H
L2_TRANSACTIONS.FILL
Counts L2 cache line fill operations due to load, RFO,
L1D writeback or prefetch.
F0H
40H
L2_TRANSACTIONS.WB
Counts L2 writeback operations to the L3.
Comment
Vol. 3B 19-101
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
F0H
80H
L2_TRANSACTIONS.ANY
Counts all L2 cache operations.
F1H
02H
L2_LINES_IN.S_STATE
Counts the number of cache lines allocated in the L2
cache in the S (shared) state.
F1H
04H
L2_LINES_IN.E_STATE
Counts the number of cache lines allocated in the L2
cache in the E (exclusive) state.
F1H
07H
L2_LINES_IN.ANY
Counts the number of cache lines allocated in the L2
cache.
F2H
01H
L2_LINES_OUT.DEMAND_CLEA Counts L2 clean cache lines evicted by a demand
N
request.
F2H
02H
L2_LINES_OUT.DEMAND_DIRT Counts L2 dirty (modified) cache lines evicted by a
Y
demand request.
F2H
04H
L2_LINES_OUT.PREFETCH_CL
EAN
F2H
08H
L2_LINES_OUT.PREFETCH_DIR Counts L2 modified cache line evicted by a prefetch
TY
request.
F2H
0FH
L2_LINES_OUT.ANY
Counts all L2 cache lines evicted for any reason.
F4H
04H
SQ_MISC.LRU_HINTS
Counts number of Super Queue LRU hints sent to
L3.
F4H
10H
SQ_MISC.SPLIT_LOCK
Counts the number of SQ lock splits across a cache
line.
F6H
01H
SQ_FULL_STALL_CYCLES
Counts cycles the Super Queue is full. Neither of the
threads on this core will be able to access the
uncore.
F7H
01H
FP_ASSIST.ALL
Counts the number of floating point operations
executed that required micro-code assist
intervention. Assists are required in the following
cases: SSE instructions, (Denormal input when the
DAZ flag is off or Underflow result when the FTZ
flag is off): x87 instructions, (NaN or denormal are
loaded to a register or used as input from memory,
Division by 0 or Underflow output).
F7H
02H
FP_ASSIST.OUTPUT
Counts number of floating point micro-code assist
when the output value (destination register) is
invalid.
F7H
04H
FP_ASSIST.INPUT
Counts number of floating point micro-code assist
when the input value (one of the source operands
to an FP instruction) is invalid.
FDH
01H
SIMD_INT_64.PACKED_MPY
Counts number of SID integer 64 bit packed multiply
operations.
FDH
02H
SIMD_INT_64.PACKED_SHIFT
Counts number of SID integer 64 bit packed shift
operations.
FDH
04H
SIMD_INT_64.PACK
Counts number of SID integer 64 bit pack
operations.
FDH
08H
SIMD_INT_64.UNPACK
Counts number of SID integer 64 bit unpack
operations.
FDH
10H
SIMD_INT_64.PACKED_LOGICA Counts number of SID integer 64 bit logical
L
operations.
19-102 Vol. 3B
Counts L2 clean cache line evicted by a prefetch
request.
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-19. Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
FDH
20H
SIMD_INT_64.PACKED_ARITH
Counts number of SID integer 64 bit arithmetic
operations.
FDH
40H
SIMD_INT_64.SHUFFLE_MOVE Counts number of SID integer 64 bit shift or move
operations.
Comment
Non-architectural Performance monitoring events of the uncore sub-system for processors with CPUID signature of
DisplayFamily_DisplayModel 06_25H, 06_2CH, and 06_1FH support performance events listed in Table 19-20.
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere
Event
Num.
Umask
Value
00H
01H
UNC_GQ_CYCLES_FULL.READ_ Uncore cycles Global Queue read tracker is full.
TRACKER
00H
02H
UNC_GQ_CYCLES_FULL.WRITE Uncore cycles Global Queue write tracker is full.
_TRACKER
00H
04H
UNC_GQ_CYCLES_FULL.PEER_ Uncore cycles Global Queue peer probe tracker is full.
PROBE_TRACKER
The peer probe tracker queue tracks snoops from the
IOH and remote sockets.
01H
01H
UNC_GQ_CYCLES_NOT_EMPTY Uncore cycles were Global Queue read tracker has at
.READ_TRACKER
least one valid entry.
01H
02H
UNC_GQ_CYCLES_NOT_EMPTY Uncore cycles were Global Queue write tracker has at
.WRITE_TRACKER
least one valid entry.
01H
04H
UNC_GQ_CYCLES_NOT_EMPTY Uncore cycles were Global Queue peer probe tracker
.PEER_PROBE_TRACKER
has at least one valid entry. The peer probe tracker
queue tracks IOH and remote socket snoops.
02H
01H
UNC_GQ_OCCUPANCY.READ_T Increments the number of queue entries (code read,
RACKER
data read, and RFOs) in the tread tracker. The GQ read
tracker allocate to deallocate occupancy count is
divided by the count to obtain the average read tracker
latency.
03H
01H
UNC_GQ_ALLOC.READ_TRACK
ER
Counts the number of tread tracker allocate to
deallocate entries. The GQ read tracker allocate to
deallocate occupancy count is divided by the count to
obtain the average read tracker latency.
03H
02H
UNC_GQ_ALLOC.RT_L3_MISS
Counts the number GQ read tracker entries for which a
full cache line read has missed the L3. The GQ read
tracker L3 miss to fill occupancy count is divided by
this count to obtain the average cache line read L3
miss latency. The latency represents the time after
which the L3 has determined that the cache line has
missed. The time between a GQ read tracker allocation
and the L3 determining that the cache line has missed
is the average L3 hit latency. The total L3 cache line
read miss latency is the hit latency + L3 miss latency.
Event Mask Mnemonic
Description
Comment
Vol. 3B 19-103
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
03H
04H
UNC_GQ_ALLOC.RT_TO_L3_RE Counts the number of GQ read tracker entries that are
SP
allocated in the read tracker queue that hit or miss the
L3. The GQ read tracker L3 hit occupancy count is
divided by this count to obtain the average L3 hit
latency.
03H
08H
UNC_GQ_ALLOC.RT_TO_RTID_ Counts the number of GQ read tracker entries that are
ACQUIRED
allocated in the read tracker, have missed in the L3 and
have not acquired a Request Transaction ID. The GQ
read tracker L3 miss to RTID acquired occupancy count
is divided by this count to obtain the average latency
for a read L3 miss to acquire an RTID.
03H
10H
UNC_GQ_ALLOC.WT_TO_RTID_ Counts the number of GQ write tracker entries that are
ACQUIRED
allocated in the write tracker, have missed in the L3
and have not acquired a Request Transaction ID. The
GQ write tracker L3 miss to RTID occupancy count is
divided by this count to obtain the average latency for
a write L3 miss to acquire an RTID.
03H
20H
UNC_GQ_ALLOC.WRITE_TRAC
KER
Counts the number of GQ write tracker entries that are
allocated in the write tracker queue that miss the L3.
The GQ write tracker occupancy count is divided by
this count to obtain the average L3 write miss latency.
03H
40H
UNC_GQ_ALLOC.PEER_PROBE
_TRACKER
Counts the number of GQ peer probe tracker (snoop)
entries that are allocated in the peer probe tracker
queue that miss the L3. The GQ peer probe occupancy
count is divided by this count to obtain the average L3
peer probe miss latency.
04H
01H
UNC_GQ_DATA.FROM_QPI
Cycles Global Queue Quickpath Interface input data
port is busy importing data from the Quickpath
Interface. Each cycle the input port can transfer 8 or
16 bytes of data.
04H
02H
UNC_GQ_DATA.FROM_QMC
Cycles Global Queue Quickpath Memory Interface input
data port is busy importing data from the Quickpath
Memory Interface. Each cycle the input port can
transfer 8 or 16 bytes of data.
04H
04H
UNC_GQ_DATA.FROM_L3
Cycles GQ L3 input data port is busy importing data
from the Last Level Cache. Each cycle the input port
can transfer 32 bytes of data.
04H
08H
UNC_GQ_DATA.FROM_CORES_ Cycles GQ Core 0 and 2 input data port is busy
02
importing data from processor cores 0 and 2. Each
cycle the input port can transfer 32 bytes of data.
04H
10H
UNC_GQ_DATA.FROM_CORES_ Cycles GQ Core 1 and 3 input data port is busy
13
importing data from processor cores 1 and 3. Each
cycle the input port can transfer 32 bytes of data.
05H
01H
UNC_GQ_DATA.TO_QPI_QMC
Cycles GQ QPI and QMC output data port is busy
sending data to the Quickpath Interface or Quickpath
Memory Interface. Each cycle the output port can
transfer 32 bytes of data.
05H
02H
UNC_GQ_DATA.TO_L3
Cycles GQ L3 output data port is busy sending data to
the Last Level Cache. Each cycle the output port can
transfer 32 bytes of data.
19-104 Vol. 3B
Event Mask Mnemonic
Description
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
05H
04H
UNC_GQ_DATA.TO_CORES
Cycles GQ Core output data port is busy sending data
to the Cores. Each cycle the output port can transfer
32 bytes of data.
06H
01H
UNC_SNP_RESP_TO_LOCAL_H Number of snoop responses to the local home that L3
OME.I_STATE
does not have the referenced cache line.
06H
02H
UNC_SNP_RESP_TO_LOCAL_H Number of snoop responses to the local home that L3
OME.S_STATE
has the referenced line cached in the S state.
06H
04H
UNC_SNP_RESP_TO_LOCAL_H Number of responses to code or data read snoops to
OME.FWD_S_STATE
the local home that the L3 has the referenced cache
line in the E state. The L3 cache line state is changed
to the S state and the line is forwarded to the local
home in the S state.
06H
08H
UNC_SNP_RESP_TO_LOCAL_H Number of responses to read invalidate snoops to the
OME.FWD_I_STATE
local home that the L3 has the referenced cache line in
the M state. The L3 cache line state is invalidated and
the line is forwarded to the local home in the M state.
06H
10H
UNC_SNP_RESP_TO_LOCAL_H Number of conflict snoop responses sent to the local
OME.CONFLICT
home.
06H
20H
UNC_SNP_RESP_TO_LOCAL_H Number of responses to code or data read snoops to
OME.WB
the local home that the L3 has the referenced line
cached in the M state.
07H
01H
UNC_SNP_RESP_TO_REMOTE_ Number of snoop responses to a remote home that L3
HOME.I_STATE
does not have the referenced cache line.
07H
02H
UNC_SNP_RESP_TO_REMOTE_ Number of snoop responses to a remote home that L3
HOME.S_STATE
has the referenced line cached in the S state.
07H
04H
UNC_SNP_RESP_TO_REMOTE_ Number of responses to code or data read snoops to a
HOME.FWD_S_STATE
remote home that the L3 has the referenced cache
line in the E state. The L3 cache line state is changed
to the S state and the line is forwarded to the remote
home in the S state.
07H
08H
UNC_SNP_RESP_TO_REMOTE_ Number of responses to read invalidate snoops to a
HOME.FWD_I_STATE
remote home that the L3 has the referenced cache
line in the M state. The L3 cache line state is
invalidated and the line is forwarded to the remote
home in the M state.
07H
10H
UNC_SNP_RESP_TO_REMOTE_ Number of conflict snoop responses sent to the local
HOME.CONFLICT
home.
07H
20H
UNC_SNP_RESP_TO_REMOTE_ Number of responses to code or data read snoops to a
HOME.WB
remote home that the L3 has the referenced line
cached in the M state.
07H
24H
UNC_SNP_RESP_TO_REMOTE_ Number of HITM snoop responses to a remote home.
HOME.HITM
08H
01H
UNC_L3_HITS.READ
Number of code read, data read and RFO requests that
hit in the L3.
08H
02H
UNC_L3_HITS.WRITE
Number of writeback requests that hit in the L3.
Writebacks from the cores will always result in L3 hits
due to the inclusive property of the L3.
Comment
Vol. 3B 19-105
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
08H
04H
UNC_L3_HITS.PROBE
Number of snoops from IOH or remote sockets that hit
in the L3.
08H
03H
UNC_L3_HITS.ANY
Number of reads and writes that hit the L3.
09H
01H
UNC_L3_MISS.READ
Number of code read, data read and RFO requests that
miss the L3.
09H
02H
UNC_L3_MISS.WRITE
Number of writeback requests that miss the L3.
Should always be zero as writebacks from the cores
will always result in L3 hits due to the inclusive
property of the L3.
09H
04H
UNC_L3_MISS.PROBE
Number of snoops from IOH or remote sockets that
miss the L3.
09H
03H
UNC_L3_MISS.ANY
Number of reads and writes that miss the L3.
0AH
01H
UNC_L3_LINES_IN.M_STATE
Counts the number of L3 lines allocated in M state. The
only time a cache line is allocated in the M state is
when the line was forwarded in M state is forwarded
due to a Snoop Read Invalidate Own request.
0AH
02H
UNC_L3_LINES_IN.E_STATE
Counts the number of L3 lines allocated in E state.
0AH
04H
UNC_L3_LINES_IN.S_STATE
Counts the number of L3 lines allocated in S state.
0AH
08H
UNC_L3_LINES_IN.F_STATE
Counts the number of L3 lines allocated in F state.
0AH
0FH
UNC_L3_LINES_IN.ANY
Counts the number of L3 lines allocated in any state.
0BH
01H
UNC_L3_LINES_OUT.M_STATE
Counts the number of L3 lines victimized that were in
the M state. When the victim cache line is in M state,
the line is written to its home cache agent which can
be either local or remote.
0BH
02H
UNC_L3_LINES_OUT.E_STATE
Counts the number of L3 lines victimized that were in
the E state.
0BH
04H
UNC_L3_LINES_OUT.S_STATE
Counts the number of L3 lines victimized that were in
the S state.
0BH
08H
UNC_L3_LINES_OUT.I_STATE
Counts the number of L3 lines victimized that were in
the I state.
0BH
10H
UNC_L3_LINES_OUT.F_STATE
Counts the number of L3 lines victimized that were in
the F state.
Comment
0BH
1FH
UNC_L3_LINES_OUT.ANY
Counts the number of L3 lines victimized in any state.
0CH
01H
UNC_GQ_SNOOP.GOTO_S
Counts the number of remote snoops that have
requested a cache line be set to the S state.
0CH
02H
UNC_GQ_SNOOP.GOTO_I
Counts the number of remote snoops that have
requested a cache line be set to the I state.
0CH
04H
UNC_GQ_SNOOP.GOTO_S_HIT_ Counts the number of remote snoops that have
E
requested a cache line be set to the S state from E
state.
Requires writing MSR
301H with mask = 2H.
0CH
04H
UNC_GQ_SNOOP.GOTO_S_HIT_ Counts the number of remote snoops that have
F
requested a cache line be set to the S state from F
(forward) state.
Requires writing MSR
301H with mask = 8H.
0CH
04H
UNC_GQ_SNOOP.GOTO_S_HIT_ Counts the number of remote snoops that have
M
requested a cache line be set to the S state from M
state.
Requires writing MSR
301H with mask = 1H.
19-106 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
0CH
04H
UNC_GQ_SNOOP.GOTO_S_HIT_ Counts the number of remote snoops that have
S
requested a cache line be set to the S state from S
state.
Requires writing MSR
301H with mask = 4H.
0CH
08H
UNC_GQ_SNOOP.GOTO_I_HIT_ Counts the number of remote snoops that have
E
requested a cache line be set to the I state from E
state.
Requires writing MSR
301H with mask = 2H.
0CH
08H
UNC_GQ_SNOOP.GOTO_I_HIT_ Counts the number of remote snoops that have
F
requested a cache line be set to the I state from F
(forward) state.
Requires writing MSR
301H with mask = 8H.
0CH
08H
UNC_GQ_SNOOP.GOTO_I_HIT_ Counts the number of remote snoops that have
M
requested a cache line be set to the I state from M
state.
Requires writing MSR
301H with mask = 1H.
0CH
08H
UNC_GQ_SNOOP.GOTO_I_HIT_ Counts the number of remote snoops that have
S
requested a cache line be set to the I state from S
state.
Requires writing MSR
301H with mask = 4H.
20H
01H
UNC_QHL_REQUESTS.IOH_RE
ADS
20H
02H
UNC_QHL_REQUESTS.IOH_WRI Counts number of Quickpath Home Logic write
TES
requests from the IOH.
20H
04H
UNC_QHL_REQUESTS.REMOTE Counts number of Quickpath Home Logic read requests
_READS
from a remote socket.
20H
08H
UNC_QHL_REQUESTS.REMOTE Counts number of Quickpath Home Logic write
_WRITES
requests from a remote socket.
20H
10H
UNC_QHL_REQUESTS.LOCAL_
READS
Counts number of Quickpath Home Logic read requests
from the local socket.
20H
20H
UNC_QHL_REQUESTS.LOCAL_
WRITES
Counts number of Quickpath Home Logic write
requests from the local socket.
21H
01H
UNC_QHL_CYCLES_FULL.IOH
Counts uclk cycles all entries in the Quickpath Home
Logic IOH are full.
21H
02H
UNC_QHL_CYCLES_FULL.REMO Counts uclk cycles all entries in the Quickpath Home
TE
Logic remote tracker are full.
21H
04H
UNC_QHL_CYCLES_FULL.LOCA Counts uclk cycles all entries in the Quickpath Home
L
Logic local tracker are full.
22H
01H
UNC_QHL_CYCLES_NOT_EMPT Counts uclk cycles all entries in the Quickpath Home
Y.IOH
Logic IOH is busy.
22H
02H
UNC_QHL_CYCLES_NOT_EMPT Counts uclk cycles all entries in the Quickpath Home
Y.REMOTE
Logic remote tracker is busy.
22H
04H
UNC_QHL_CYCLES_NOT_EMPT Counts uclk cycles all entries in the Quickpath Home
Y.LOCAL
Logic local tracker is busy.
23H
01H
UNC_QHL_OCCUPANCY.IOH
23H
02H
UNC_QHL_OCCUPANCY.REMOT QHL remote tracker allocate to deallocate read
E
occupancy.
23H
04H
UNC_QHL_OCCUPANCY.LOCAL
Event Mask Mnemonic
Description
Comment
Counts number of Quickpath Home Logic read requests
from the IOH.
QHL IOH tracker allocate to deallocate read occupancy.
QHL local tracker allocate to deallocate read
occupancy.
Vol. 3B 19-107
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
24H
02H
UNC_QHL_ADDRESS_CONFLIC
TS.2WAY
Counts number of QHL Active Address Table (AAT)
entries that saw a max of 2 conflicts. The AAT is a
structure that tracks requests that are in conflict. The
requests themselves are in the home tracker entries.
The count is reported when an AAT entry deallocates.
24H
04H
UNC_QHL_ADDRESS_CONFLIC
TS.3WAY
Counts number of QHL Active Address Table (AAT)
entries that saw a max of 3 conflicts. The AAT is a
structure that tracks requests that are in conflict. The
requests themselves are in the home tracker entries.
The count is reported when an AAT entry deallocates.
25H
01H
UNC_QHL_CONFLICT_CYCLES.I Counts cycles the Quickpath Home Logic IOH Tracker
OH
contains two or more requests with an address
conflict. A max of 3 requests can be in conflict.
25H
02H
UNC_QHL_CONFLICT_CYCLES.
REMOTE
25H
04H
UNC_QHL_CONFLICT_CYCLES.L Counts cycles the Quickpath Home Logic Local Tracker
OCAL
contains two or more requests with an address
conflict. A max of 3 requests can be in conflict.
26H
01H
UNC_QHL_TO_QMC_BYPASS
Counts number or requests to the Quickpath Memory
Controller that bypass the Quickpath Home Logic. All
local accesses can be bypassed. For remote requests,
only read requests can be bypassed.
28H
01H
UNC_QMC_ISOC_FULL.READ.C
H0
Counts cycles all the entries in the DRAM channel 0
high priority queue are occupied with isochronous read
requests.
28H
02H
UNC_QMC_ISOC_FULL.READ.C
H1
Counts cycles all the entries in the DRAM channel
1high priority queue are occupied with isochronous
read requests.
28H
04H
UNC_QMC_ISOC_FULL.READ.C
H2
Counts cycles all the entries in the DRAM channel 2
high priority queue are occupied with isochronous read
requests.
28H
08H
UNC_QMC_ISOC_FULL.WRITE.C Counts cycles all the entries in the DRAM channel 0
H0
high priority queue are occupied with isochronous
write requests.
28H
10H
UNC_QMC_ISOC_FULL.WRITE.C Counts cycles all the entries in the DRAM channel 1
H1
high priority queue are occupied with isochronous
write requests.
28H
20H
UNC_QMC_ISOC_FULL.WRITE.C Counts cycles all the entries in the DRAM channel 2
H2
high priority queue are occupied with isochronous
write requests.
29H
01H
UNC_QMC_BUSY.READ.CH0
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding read request to DRAM channel
0.
29H
02H
UNC_QMC_BUSY.READ.CH1
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding read request to DRAM channel
1.
19-108 Vol. 3B
Counts cycles the Quickpath Home Logic Remote
Tracker contains two or more requests with an
address conflict. A max of 3 requests can be in conflict.
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
29H
04H
UNC_QMC_BUSY.READ.CH2
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding read request to DRAM channel
2.
29H
08H
UNC_QMC_BUSY.WRITE.CH0
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding write request to DRAM channel
0.
29H
10H
UNC_QMC_BUSY.WRITE.CH1
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding write request to DRAM channel
1.
29H
20H
UNC_QMC_BUSY.WRITE.CH2
Counts cycles where Quickpath Memory Controller has
at least 1 outstanding write request to DRAM channel
2.
2AH
01H
UNC_QMC_OCCUPANCY.CH0
IMC channel 0 normal read request occupancy.
2AH
02H
UNC_QMC_OCCUPANCY.CH1
IMC channel 1 normal read request occupancy.
2AH
04H
UNC_QMC_OCCUPANCY.CH2
IMC channel 2 normal read request occupancy.
2AH
07H
UNC_QMC_OCCUPANCY.ANY
Normal read request occupancy for any channel.
2BH
01H
UNC_QMC_ISSOC_OCCUPANCY. IMC channel 0 issoc read request occupancy.
CH0
2BH
02H
UNC_QMC_ISSOC_OCCUPANCY. IMC channel 1 issoc read request occupancy.
CH1
2BH
04H
UNC_QMC_ISSOC_OCCUPANCY. IMC channel 2 issoc read request occupancy.
CH2
2BH
07H
UNC_QMC_ISSOC_READS.ANY
IMC issoc read request occupancy.
2CH
01H
UNC_QMC_NORMAL_READS.C
H0
Counts the number of Quickpath Memory Controller
channel 0 medium and low priority read requests. The
QMC channel 0 normal read occupancy divided by this
count provides the average QMC channel 0 read
latency.
2CH
02H
UNC_QMC_NORMAL_READS.C
H1
Counts the number of Quickpath Memory Controller
channel 1 medium and low priority read requests. The
QMC channel 1 normal read occupancy divided by this
count provides the average QMC channel 1 read
latency.
2CH
04H
UNC_QMC_NORMAL_READS.C
H2
Counts the number of Quickpath Memory Controller
channel 2 medium and low priority read requests. The
QMC channel 2 normal read occupancy divided by this
count provides the average QMC channel 2 read
latency.
2CH
07H
UNC_QMC_NORMAL_READS.A
NY
Counts the number of Quickpath Memory Controller
medium and low priority read requests. The QMC
normal read occupancy divided by this count provides
the average QMC read latency.
2DH
01H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.CH0
channel 0 high priority isochronous read requests.
2DH
02H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.CH1
channel 1 high priority isochronous read requests.
Comment
Vol. 3B 19-109
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
2DH
04H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.CH2
channel 2 high priority isochronous read requests.
2DH
07H
UNC_QMC_HIGH_PRIORITY_RE Counts the number of Quickpath Memory Controller
ADS.ANY
high priority isochronous read requests.
2EH
01H
UNC_QMC_CRITICAL_PRIORITY Counts the number of Quickpath Memory Controller
_READS.CH0
channel 0 critical priority isochronous read requests.
2EH
02H
UNC_QMC_CRITICAL_PRIORITY Counts the number of Quickpath Memory Controller
_READS.CH1
channel 1 critical priority isochronous read requests.
2EH
04H
UNC_QMC_CRITICAL_PRIORITY Counts the number of Quickpath Memory Controller
_READS.CH2
channel 2 critical priority isochronous read requests.
2EH
07H
UNC_QMC_CRITICAL_PRIORITY Counts the number of Quickpath Memory Controller
_READS.ANY
critical priority isochronous read requests.
2FH
01H
UNC_QMC_WRITES.FULL.CH0
Counts number of full cache line writes to DRAM
channel 0.
2FH
02H
UNC_QMC_WRITES.FULL.CH1
Counts number of full cache line writes to DRAM
channel 1.
2FH
04H
UNC_QMC_WRITES.FULL.CH2
Counts number of full cache line writes to DRAM
channel 2.
2FH
07H
UNC_QMC_WRITES.FULL.ANY
Counts number of full cache line writes to DRAM.
2FH
08H
UNC_QMC_WRITES.PARTIAL.C
H0
Counts number of partial cache line writes to DRAM
channel 0.
2FH
10H
UNC_QMC_WRITES.PARTIAL.C
H1
Counts number of partial cache line writes to DRAM
channel 1.
2FH
20H
UNC_QMC_WRITES.PARTIAL.C
H2
Counts number of partial cache line writes to DRAM
channel 2.
2FH
38H
UNC_QMC_WRITES.PARTIAL.A
NY
Counts number of partial cache line writes to DRAM.
30H
01H
UNC_QMC_CANCEL.CH0
Counts number of DRAM channel 0 cancel requests.
30H
02H
UNC_QMC_CANCEL.CH1
Counts number of DRAM channel 1 cancel requests.
30H
04H
UNC_QMC_CANCEL.CH2
Counts number of DRAM channel 2 cancel requests.
30H
07H
UNC_QMC_CANCEL.ANY
Counts number of DRAM cancel requests.
31H
01H
UNC_QMC_PRIORITY_UPDATE
S.CH0
Counts number of DRAM channel 0 priority updates. A
priority update occurs when an ISOC high or critical
request is received by the QHL and there is a matching
request with normal priority that has already been
issued to the QMC. In this instance, the QHL will send a
priority update to QMC to expedite the request.
31H
02H
UNC_QMC_PRIORITY_UPDATE
S.CH1
Counts number of DRAM channel 1 priority updates. A
priority update occurs when an ISOC high or critical
request is received by the QHL and there is a matching
request with normal priority that has already been
issued to the QMC. In this instance, the QHL will send a
priority update to QMC to expedite the request.
19-110 Vol. 3B
Event Mask Mnemonic
Description
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
31H
04H
UNC_QMC_PRIORITY_UPDATE
S.CH2
Counts number of DRAM channel 2 priority updates. A
priority update occurs when an ISOC high or critical
request is received by the QHL and there is a matching
request with normal priority that has already been
issued to the QMC. In this instance, the QHL will send a
priority update to QMC to expedite the request.
31H
07H
UNC_QMC_PRIORITY_UPDATE
S.ANY
Counts number of DRAM priority updates. A priority
update occurs when an ISOC high or critical request is
received by the QHL and there is a matching request
with normal priority that has already been issued to
the QMC. In this instance, the QHL will send a priority
update to QMC to expedite the request.
32H
01H
UNC_IMC_RETRY.CH0
Counts number of IMC DRAM channel 0 retries. DRAM
retry only occurs when configured in RAS mode.
32H
02H
UNC_IMC_RETRY.CH1
Counts number of IMC DRAM channel 1 retries. DRAM
retry only occurs when configured in RAS mode.
32H
04H
UNC_IMC_RETRY.CH2
Counts number of IMC DRAM channel 2 retries. DRAM
retry only occurs when configured in RAS mode.
32H
07H
UNC_IMC_RETRY.ANY
Counts number of IMC DRAM retries from any channel.
DRAM retry only occurs when configured in RAS mode.
33H
01H
UNC_QHL_FRC_ACK_CNFLTS.I
OH
Counts number of Force Acknowledge Conflict
messages sent by the Quickpath Home Logic to the
IOH.
33H
02H
UNC_QHL_FRC_ACK_CNFLTS.R Counts number of Force Acknowledge Conflict
EMOTE
messages sent by the Quickpath Home Logic to the
remote home.
33H
04H
UNC_QHL_FRC_ACK_CNFLTS.L Counts number of Force Acknowledge Conflict
OCAL
messages sent by the Quickpath Home Logic to the
local home.
33H
07H
UNC_QHL_FRC_ACK_CNFLTS.A Counts number of Force Acknowledge Conflict
NY
messages sent by the Quickpath Home Logic.
34H
01H
UNC_QHL_SLEEPS.IOH_ORDER Counts number of occurrences a request was put to
sleep due to IOH ordering (write after read) conflicts.
While in the sleep state, the request is not eligible to
be scheduled to the QMC.
34H
02H
UNC_QHL_SLEEPS.REMOTE_O
RDER
34H
04H
UNC_QHL_SLEEPS.LOCAL_ORD Counts number of occurrences a request was put to
ER
sleep due to local socket ordering (write after read)
conflicts. While in the sleep state, the request is not
eligible to be scheduled to the QMC.
34H
08H
UNC_QHL_SLEEPS.IOH_CONFLI Counts number of occurrences a request was put to
CT
sleep due to IOH address conflicts. While in the sleep
state, the request is not eligible to be scheduled to the
QMC.
Comment
Counts number of occurrences a request was put to
sleep due to remote socket ordering (write after read)
conflicts. While in the sleep state, the request is not
eligible to be scheduled to the QMC.
Vol. 3B 19-111
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
34H
10H
UNC_QHL_SLEEPS.REMOTE_C
ONFLICT
Counts number of occurrences a request was put to
sleep due to remote socket address conflicts. While in
the sleep state, the request is not eligible to be
scheduled to the QMC.
34H
20H
UNC_QHL_SLEEPS.LOCAL_CON Counts number of occurrences a request was put to
FLICT
sleep due to local socket address conflicts. While in the
sleep state, the request is not eligible to be scheduled
to the QMC.
35H
01H
UNC_ADDR_OPCODE_MATCH.I
OH
Counts number of requests from the IOH,
address/opcode of request is qualified by mask value
written to MSR 396H. The following mask values are
supported:
Comment
Match opcode/address
by writing MSR 396H
with mask supported
mask value.
0: NONE
40000000_00000000H:RSPFWDI
40001A00_00000000H:RSPFWDS
40001D00_00000000H:RSPIWB
35H
02H
UNC_ADDR_OPCODE_MATCH.R Counts number of requests from the remote socket,
EMOTE
address/opcode of request is qualified by mask value
written to MSR 396H. The following mask values are
supported:
Match opcode/address
by writing MSR 396H
with mask supported
mask value.
0: NONE
40000000_00000000H:RSPFWDI
40001A00_00000000H:RSPFWDS
40001D00_00000000H:RSPIWB
35H
04H
UNC_ADDR_OPCODE_MATCH.L Counts number of requests from the local socket,
OCAL
address/opcode of request is qualified by mask value
written to MSR 396H. The following mask values are
supported:
0: NONE
40000000_00000000H:RSPFWDI
40001A00_00000000H:RSPFWDS
40001D00_00000000H:RSPIWB
40H
01H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.HOME.LINK_0
Counts cycles the Quickpath outbound link 0 HOME
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
02H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.SNOOP.LINK_0
Counts cycles the Quickpath outbound link 0 SNOOP
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
04H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.NDR.LINK_0
Counts cycles the Quickpath outbound link 0 non-data
response virtual channel is stalled due to lack of a VNA
and VN0 credit. Note that this event does not filter out
when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
19-112 Vol. 3B
Match opcode/address
by writing MSR 396H
with mask supported
mask value.
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
40H
08H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.HOME.LINK_1
Counts cycles the Quickpath outbound link 1 HOME
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
10H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.SNOOP.LINK_1
Counts cycles the Quickpath outbound link 1 SNOOP
virtual channel is stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
20H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.NDR.LINK_1
Counts cycles the Quickpath outbound link 1 non-data
response virtual channel is stalled due to lack of a VNA
and VN0 credit. Note that this event does not filter out
when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
40H
07H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.LINK_0
Counts cycles the Quickpath outbound link 0 virtual
channels are stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
40H
38H
UNC_QPI_TX_STALLED_SINGL
E_FLIT.LINK_1
Counts cycles the Quickpath outbound link 1 virtual
channels are stalled due to lack of a VNA and VN0
credit. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
41H
01H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 Data
_FLIT.DRS.LINK_0
Response virtual channel is stalled due to lack of VNA
and VN0 credits. Note that this event does not filter
out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
02H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 Non_FLIT.NCB.LINK_0
Coherent Bypass virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
04H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 Non_FLIT.NCS.LINK_0
Coherent Standard virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
08H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 Data
_FLIT.DRS.LINK_1
Response virtual channel is stalled due to lack of VNA
and VN0 credits. Note that this event does not filter
out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
Comment
Vol. 3B 19-113
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
41H
10H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 Non_FLIT.NCB.LINK_1
Coherent Bypass virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
20H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 Non_FLIT.NCS.LINK_1
Coherent Standard virtual channel is stalled due to lack
of VNA and VN0 credits. Note that this event does not
filter out when a flit would not have been selected for
arbitration because another virtual channel is getting
arbitrated.
41H
07H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 0 virtual
_FLIT.LINK_0
channels are stalled due to lack of VNA and VN0
credits. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
41H
38H
UNC_QPI_TX_STALLED_MULTI Counts cycles the Quickpath outbound link 1 virtual
_FLIT.LINK_1
channels are stalled due to lack of VNA and VN0
credits. Note that this event does not filter out when a
flit would not have been selected for arbitration
because another virtual channel is getting arbitrated.
42H
01H
UNC_QPI_TX_HEADER.FULL.LI Number of cycles that the header buffer in the
NK_0
Quickpath Interface outbound link 0 is full.
42H
02H
UNC_QPI_TX_HEADER.BUSY.LI Number of cycles that the header buffer in the
NK_0
Quickpath Interface outbound link 0 is busy.
42H
04H
UNC_QPI_TX_HEADER.FULL.LI Number of cycles that the header buffer in the
NK_1
Quickpath Interface outbound link 1 is full.
42H
08H
UNC_QPI_TX_HEADER.BUSY.LI Number of cycles that the header buffer in the
NK_1
Quickpath Interface outbound link 1 is busy.
43H
01H
UNC_QPI_RX_NO_PPT_CREDI
T.STALLS.LINK_0
Number of cycles that snoop packets incoming to the
Quickpath Interface link 0 are stalled and not sent to
the GQ because the GQ Peer Probe Tracker (PPT) does
not have any available entries.
43H
02H
UNC_QPI_RX_NO_PPT_CREDI
T.STALLS.LINK_1
Number of cycles that snoop packets incoming to the
Quickpath Interface link 1 are stalled and not sent to
the GQ because the GQ Peer Probe Tracker (PPT) does
not have any available entries.
60H
01H
UNC_DRAM_OPEN.CH0
Counts number of DRAM Channel 0 open commands
issued either for read or write. To read or write data,
the referenced DRAM page must first be opened.
60H
02H
UNC_DRAM_OPEN.CH1
Counts number of DRAM Channel 1 open commands
issued either for read or write. To read or write data,
the referenced DRAM page must first be opened.
60H
04H
UNC_DRAM_OPEN.CH2
Counts number of DRAM Channel 2 open commands
issued either for read or write. To read or write data,
the referenced DRAM page must first be opened.
19-114 Vol. 3B
Event Mask Mnemonic
Description
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
61H
01H
UNC_DRAM_PAGE_CLOSE.CH0 DRAM channel 0 command issued to CLOSE a page due
to page idle timer expiration. Closing a page is done by
issuing a precharge.
61H
02H
UNC_DRAM_PAGE_CLOSE.CH1 DRAM channel 1 command issued to CLOSE a page due
to page idle timer expiration. Closing a page is done by
issuing a precharge.
61H
04H
UNC_DRAM_PAGE_CLOSE.CH2 DRAM channel 2 command issued to CLOSE a page due
to page idle timer expiration. Closing a page is done by
issuing a precharge.
62H
01H
UNC_DRAM_PAGE_MISS.CH0
Counts the number of precharges (PRE) that were
issued to DRAM channel 0 because there was a page
miss. A page miss refers to a situation in which a page
is currently open and another page from the same
bank needs to be opened. The new page experiences a
page miss. Closing of the old page is done by issuing a
precharge.
62H
02H
UNC_DRAM_PAGE_MISS.CH1
Counts the number of precharges (PRE) that were
issued to DRAM channel 1 because there was a page
miss. A page miss refers to a situation in which a page
is currently open and another page from the same
bank needs to be opened. The new page experiences a
page miss. Closing of the old page is done by issuing a
precharge.
62H
04H
UNC_DRAM_PAGE_MISS.CH2
Counts the number of precharges (PRE) that were
issued to DRAM channel 2 because there was a page
miss. A page miss refers to a situation in which a page
is currently open and another page from the same
bank needs to be opened. The new page experiences a
page miss. Closing of the old page is done by issuing a
precharge.
63H
01H
UNC_DRAM_READ_CAS.CH0
Counts the number of times a read CAS command was
issued on DRAM channel 0.
63H
02H
UNC_DRAM_READ_CAS.AUTO
PRE_CH0
Counts the number of times a read CAS command was
issued on DRAM channel 0 where the command issued
used the auto-precharge (auto page close) mode.
63H
04H
UNC_DRAM_READ_CAS.CH1
Counts the number of times a read CAS command was
issued on DRAM channel 1.
63H
08H
UNC_DRAM_READ_CAS.AUTO
PRE_CH1
Counts the number of times a read CAS command was
issued on DRAM channel 1 where the command issued
used the auto-precharge (auto page close) mode.
63H
10H
UNC_DRAM_READ_CAS.CH2
Counts the number of times a read CAS command was
issued on DRAM channel 2.
63H
20H
UNC_DRAM_READ_CAS.AUTO
PRE_CH2
Counts the number of times a read CAS command was
issued on DRAM channel 2 where the command issued
used the auto-precharge (auto page close) mode.
64H
01H
UNC_DRAM_WRITE_CAS.CH0
Counts the number of times a write CAS command was
issued on DRAM channel 0.
Event Mask Mnemonic
Description
Comment
Vol. 3B 19-115
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
64H
02H
UNC_DRAM_WRITE_CAS.AUTO Counts the number of times a write CAS command was
PRE_CH0
issued on DRAM channel 0 where the command issued
used the auto-precharge (auto page close) mode.
64H
04H
UNC_DRAM_WRITE_CAS.CH1
64H
08H
UNC_DRAM_WRITE_CAS.AUTO Counts the number of times a write CAS command was
PRE_CH1
issued on DRAM channel 1 where the command issued
used the auto-precharge (auto page close) mode.
64H
10H
UNC_DRAM_WRITE_CAS.CH2
64H
20H
UNC_DRAM_WRITE_CAS.AUTO Counts the number of times a write CAS command was
PRE_CH2
issued on DRAM channel 2 where the command issued
used the auto-precharge (auto page close) mode.
65H
01H
UNC_DRAM_REFRESH.CH0
Counts number of DRAM channel 0 refresh commands.
DRAM loses data content over time. In order to keep
correct data content, the data values have to be
refreshed periodically.
65H
02H
UNC_DRAM_REFRESH.CH1
Counts number of DRAM channel 1 refresh commands.
DRAM loses data content over time. In order to keep
correct data content, the data values have to be
refreshed periodically.
65H
04H
UNC_DRAM_REFRESH.CH2
Counts number of DRAM channel 2 refresh commands.
DRAM loses data content over time. In order to keep
correct data content, the data values have to be
refreshed periodically.
66H
01H
UNC_DRAM_PRE_ALL.CH0
Counts number of DRAM Channel 0 precharge-all
(PREALL) commands that close all open pages in a rank.
PREALL is issued when the DRAM needs to be
refreshed or needs to go into a power down mode.
66H
02H
UNC_DRAM_PRE_ALL.CH1
Counts number of DRAM Channel 1 precharge-all
(PREALL) commands that close all open pages in a rank.
PREALL is issued when the DRAM needs to be
refreshed or needs to go into a power down mode.
66H
04H
UNC_DRAM_PRE_ALL.CH2
Counts number of DRAM Channel 2 precharge-all
(PREALL) commands that close all open pages in a rank.
PREALL is issued when the DRAM needs to be
refreshed or needs to go into a power down mode.
67H
01H
UNC_DRAM_THERMAL_THROT Uncore cycles DRAM was throttled due to its
TLED
temperature being above the thermal throttling
threshold.
80H
01H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 0 is above the
TEMP.CORE_0
thermal throttling threshold temperature.
80H
02H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 1 is above the
TEMP.CORE_1
thermal throttling threshold temperature.
80H
04H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 2 is above the
TEMP.CORE_2
thermal throttling threshold temperature.
80H
08H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 3 is above the
TEMP.CORE_3
thermal throttling threshold temperature.
19-116 Vol. 3B
Event Mask Mnemonic
Description
Counts the number of times a write CAS command was
issued on DRAM channel 1.
Counts the number of times a write CAS command was
issued on DRAM channel 2.
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-20. Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
81H
01H
UNC_THERMAL_THROTTLED_
TEMP.CORE_0
Cycles that the PCU records that core 0 is in the power
throttled state due to core’s temperature being above
the thermal throttling threshold.
81H
02H
UNC_THERMAL_THROTTLED_
TEMP.CORE_1
Cycles that the PCU records that core 1 is in the power
throttled state due to core’s temperature being above
the thermal throttling threshold.
81H
04H
UNC_THERMAL_THROTTLED_
TEMP.CORE_2
Cycles that the PCU records that core 2 is in the power
throttled state due to core’s temperature being above
the thermal throttling threshold.
81H
08H
UNC_THERMAL_THROTTLED_
TEMP.CORE_3
Cycles that the PCU records that core 3 is in the power
throttled state due to core’s temperature being above
the thermal throttling threshold.
82H
01H
UNC_PROCHOT_ASSERTION
Number of system assertions of PROCHOT indicating
the entire processor has exceeded the thermal limit.
83H
01H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 0 is a low power
PROCHOT.CORE_0
state due to the system asserting PROCHOT the entire
processor has exceeded the thermal limit.
83H
02H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 1 is a low power
PROCHOT.CORE_1
state due to the system asserting PROCHOT the entire
processor has exceeded the thermal limit.
83H
04H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 2 is a low power
PROCHOT.CORE_2
state due to the system asserting PROCHOT the entire
processor has exceeded the thermal limit.
83H
08H
UNC_THERMAL_THROTTLING_ Cycles that the PCU records that core 3 is a low power
PROCHOT.CORE_3
state due to the system asserting PROCHOT the entire
processor has exceeded the thermal limit.
84H
01H
UNC_TURBO_MODE.CORE_0
Uncore cycles that core 0 is operating in turbo mode.
84H
02H
UNC_TURBO_MODE.CORE_1
Uncore cycles that core 1 is operating in turbo mode.
84H
04H
UNC_TURBO_MODE.CORE_2
Uncore cycles that core 2 is operating in turbo mode.
84H
08H
UNC_TURBO_MODE.CORE_3
Uncore cycles that core 3 is operating in turbo mode.
85H
02H
UNC_CYCLES_UNHALTED_L3_
FLL_ENABLE
Uncore cycles that at least one core is unhalted and all
L3 ways are enabled.
86H
01H
UNC_CYCLES_UNHALTED_L3_
FLL_DISABLE
Uncore cycles that at least one core is unhalted and all
L3 ways are disabled.
19.9
Comment
PERFORMANCE MONITORING EVENTS FOR INTEL® XEON® PROCESSOR
5200, 5400 SERIES AND INTEL® CORE™2 EXTREME PROCESSORS QX
9000 SERIES
Processors based on the Enhanced Intel Core microarchitecture support the architectural and non-architectural
performance-monitoring events listed in Table 19-1 and Table 19-23. In addition, they also support the following
non-architectural performance-monitoring events listed in Table 19-21. Fixed counters support the architecture
events defined in Table 19-22.
Vol. 3B 19-117
PERFORMANCE-MONITORING EVENTS
Table 19-21. Non-Architectural Performance Events for Processors Based on Enhanced Intel Core
Microarchitecture
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
C0H
08H
INST_RETIRED.VM_HOST
Instruction retired while in VMX root operations.
D2H
10H
RAT_STAALS.OTHER_SERIALIZ
ATION_STALLS
This event counts the number of stalls due to other
RAT resource serialization not counted by Umask
value 0FH.
19.10
Comment
PERFORMANCE MONITORING EVENTS FOR INTEL® XEON® PROCESSOR
3000, 3200, 5100, 5300 SERIES AND INTEL® CORE™2 DUO PROCESSORS
Processors based on the Intel® Core™ microarchitecture support architectural and non-architectural performancemonitoring events.
Fixed-function performance counters are introduced first on processors based on Intel Core microarchitecture.
Table 19-22 lists pre-defined performance events that can be counted using fixed-function performance counters.
Table 19-22. Fixed-Function Performance Counter and Pre-defined Performance Events
Fixed-Function Performance
Counter
Address
Event Mask Mnemonic
Description
MSR_PERF_FIXED_
CTR0/IA32_PERF_FIXED_CTR0
309H
Inst_Retired.Any
This event counts the number of instructions that
retire execution. For instructions that consist of
multiple micro-ops, this event counts the retirement
of the last micro-op of the instruction. The counter
continues counting during hardware interrupts, traps,
and inside interrupt handlers.
MSR_PERF_FIXED_
CTR1/IA32_PERF_FIXED_CTR1
30AH
CPU_CLK_UNHALTED.CORE This event counts the number of core cycles while the
core is not in a halt state. The core enters the halt
state when it is running the HLT instruction. This
event is a component in many key event ratios.
The core frequency may change from time to time
due to transitions associated with Enhanced Intel
SpeedStep Technology or TM2. For this reason this
event may have a changing ratio with regards to time.
When the core frequency is constant, this event can
approximate elapsed time while the core was not in
halt state.
MSR_PERF_FIXED_
CTR2/IA32_PERF_FIXED_CTR2
30BH
CPU_CLK_UNHALTED.REF
This event counts the number of reference cycles
when the core is not in a halt state and not in a TM
stop-clock state. The core enters the halt state when
it is running the HLT instruction or the MWAIT
instruction.
This event is not affected by core frequency changes
(e.g., P states) but counts at the same frequency as
the time stamp counter. This event can approximate
elapsed time while the core was not in halt state and
not in a TM stop-clock state.
This event has a constant ratio with the
CPU_CLK_UNHALTED.BUS event.
19-118 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23 lists general-purpose non-architectural performance-monitoring events supported in processors based
on Intel® Core™ microarchitecture. For convenience, Table 19-23 also includes architectural events and describes
minor model-specific behavior where applicable. Software must use a general-purpose performance counter to
count events listed in Table 19-23.
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture
Event
Num
Umask
Value
Event Name
Definition
03H
02H
LOAD_BLOCK.STA
Loads blocked by a
preceding store with
unknown address.
Description and
Comment
This event indicates that loads are blocked by preceding
stores. A load is blocked when there is a preceding store to
an address that is not yet calculated. The number of events
is greater or equal to the number of load operations that
were blocked.
If the load and the store are always to different addresses,
check why the memory disambiguation mechanism is not
working. To avoid such blocks, increase the distance
between the store and the following load so that the store
address is known at the time the load is dispatched.
03H
04H
LOAD_BLOCK.STD
Loads blocked by a
preceding store with
unknown data.
This event indicates that loads are blocked by preceding
stores. A load is blocked when there is a preceding store to
the same address and the stored data value is not yet
known. The number of events is greater or equal to the
number of load operations that were blocked.
To avoid such blocks, increase the distance between the
store and the dependent load, so that the store data is
known at the time the load is dispatched.
03H
08H
LOAD_BLOCK.
OVERLAP_STORE
Loads that partially
overlap an earlier
store, or 4-Kbyte
aliased with a previous
store.
This event indicates that loads are blocked due to a variety
of reasons. Some of the triggers for this event are when a
load is blocked by a preceding store, in one of the following:
• Some of the loaded byte locations are written by the
preceding store and some are not.
• The load is from bytes written by the preceding store,
the store is aligned to its size and either:
• The load’s data size is one or two bytes and it is not
aligned to the store.
• The load’s data size is of four or eight bytes and the load
is misaligned.
• The load is from bytes written by the preceding store,
the store is misaligned and the load is not aligned on the
beginning of the store.
• The load is split over an eight byte boundary (excluding
16-byte loads).
• The load and store have the same offset relative to the
beginning of different 4-KByte pages. This case is also
called 4-KByte aliasing.
• In all these cases the load is blocked until after the
blocking store retires and the stored data is committed to
the cache hierarchy.
03H
10H
LOAD_BLOCK.
UNTIL_RETIRE
Loads blocked until
retirement.
This event indicates that load operations were blocked until
retirement. The number of events is greater or equal to the
number of load operations that were blocked.
This includes mainly uncacheable loads and split loads (loads
that cross the cache line boundary) but may include other
cases where loads are blocked until retirement.
Vol. 3B 19-119
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
Description and
Comment
03H
20H
LOAD_BLOCK.L1D
Loads blocked by the
L1 data cache.
This event indicates that loads are blocked due to one or
more reasons. Some triggers for this event are:
• The number of L1 data cache misses exceeds the
maximum number of outstanding misses supported by
the processor. This includes misses generated as result of
demand fetches, software prefetches or hardware
prefetches.
• Cache line split loads.
• Partial reads, such as reads to un-cacheable memory, I/O
instructions and more.
• A locked load operation is in progress. The number of
events is greater or equal to the number of load
operations that were blocked.
04H
01H
SB_DRAIN_
CYCLES
Cycles while stores are This event counts every cycle during which the store buffer
blocked due to store
is draining. This includes:
buffer drain.
• Serializing operations such as CPUID
• Synchronizing operations such as XCHG
• Interrupt acknowledgment
• Other conditions, such as cache flushing
04H
02H
STORE_BLOCK.
ORDER
Cycles while store is
waiting for a
preceding store to be
globally observed.
This event counts the total duration, in number of cycles,
which stores are waiting for a preceding stored cache line to
be observed by other cores.
This situation happens as a result of the strong store
ordering behavior, as defined in “Memory Ordering,” Chapter
8, Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
The stall may occur and be noticeable if there are many
cases when a store either misses the L1 data cache or hits a
cache line in the Shared state. If the store requires a bus
transaction to read the cache line then the stall ends when
snoop response for the bus transaction arrives.
04H
08H
STORE_BLOCK.
SNOOP
A store is blocked due
to a conflict with an
external or internal
snoop.
This event counts the number of cycles the store port was
used for snooping the L1 data cache and a store was stalled
by the snoop. The store is typically resubmitted one cycle
later.
06H
00H
SEGMENT_REG_
LOADS
Number of segment
register loads.
This event counts the number of segment register load
operations. Instructions that load new values into segment
registers cause a penalty.
This event indicates performance issues in 16-bit code. If
this event occurs frequently, it may be useful to calculate
the number of instructions retired per segment register
load. If the resulting calculation is low (on average a small
number of instructions are executed between segment
register loads), then the code’s segment register usage
should be optimized.
As a result of branch misprediction, this event is speculative
and may include segment register loads that do not actually
occur. However, most segment register loads are internally
serialized and such speculative effects are minimized.
19-120 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
07H
Description and
Comment
Event Name
Definition
00H
SSE_PRE_EXEC.
NTA
Streaming SIMD
This event counts the number of times the SSE instruction
Extensions (SSE)
prefetchNTA is executed.
Prefetch NTA
This instruction prefetches the data to the L1 data cache.
instructions executed.
07H
01H
SSE_PRE_EXEC.L1
This event counts the number of times the SSE instruction
Streaming SIMD
Extensions (SSE)
prefetchT0 is executed. This instruction prefetches the data
to the L1 data cache and L2 cache.
PrefetchT0
instructions executed.
07H
02H
SSE_PRE_EXEC.L2
Streaming SIMD
This event counts the number of times the SSE instructions
Extensions (SSE)
prefetchT1 and prefetchT2 are executed. These
PrefetchT1 and
instructions prefetch the data to the L2 cache.
PrefetchT2
instructions executed.
07H
03H
SSE_PRE_
EXEC.STORES
Streaming SIMD
This event counts the number of times SSE non-temporal
Extensions (SSE)
store instructions are executed.
Weakly-ordered store
instructions executed.
08H
01H
DTLB_MISSES.
ANY
Memory accesses that This event counts the number of Data Table Lookaside
missed the DTLB.
Buffer (DTLB) misses. The count includes misses detected
as a result of speculative accesses.
Typically a high count for this event indicates that the code
accesses a large number of data pages.
08H
02H
DTLB_MISSES
.MISS_LD
DTLB misses due to
load operations.
This event counts the number of Data Table Lookaside
Buffer (DTLB) misses due to load operations.
This count includes misses detected as a result of
speculative accesses.
08H
04H
DTLB_MISSES.L0_MISS_LD
L0 DTLB misses due to This event counts the number of level 0 Data Table
load operations.
Lookaside Buffer (DTLB0) misses due to load operations.
This count includes misses detected as a result of
speculative accesses. Loads that miss that DTLB0 and hit
the DTLB1 can incur two-cycle penalty.
08H
08H
DTLB_MISSES.
MISS_ST
TLB misses due to
store operations.
This event counts the number of Data Table Lookaside
Buffer (DTLB) misses due to store operations.
This count includes misses detected as a result of
speculative accesses. Address translation for store
operations is performed in the DTLB1.
09H
01H
MEMORY_
DISAMBIGUATION.RESET
Memory
disambiguation reset
cycles.
This event counts the number of cycles during which
memory disambiguation misprediction occurs. As a result
the execution pipeline is cleaned and execution of the
mispredicted load instruction and all succeeding instructions
restarts.
This event occurs when the data address accessed by a load
instruction, collides infrequently with preceding stores, but
usually there is no collision. It happens rarely, and may have
a penalty of about 20 cycles.
09H
02H
MEMORY_DISAMBIGUATIO
N.SUCCESS
Number of loads
successfully
disambiguated.
This event counts the number of load operations that were
successfully disambiguated. Loads are preceded by a store
with an unknown address, but they are not blocked.
Vol. 3B 19-121
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
0CH
01H
Description and
Comment
Event Name
Definition
PAGE_WALKS
.COUNT
Number of page-walks This event counts the number of page-walks executed due
executed.
to either a DTLB or ITLB miss.
The page walk duration, PAGE_WALKS.CYCLES, divided by
number of page walks is the average duration of a page
walk. The average can hint whether most of the page-walks
are satisfied by the caches or cause an L2 cache miss.
0CH
02H
PAGE_WALKS.
CYCLES
Duration of pagewalks in core cycles.
This event counts the duration of page-walks in core cycles.
The paging mode in use typically affects the duration of
page walks.
Page walk duration divided by number of page walks is the
average duration of page-walks. The average can hint at
whether most of the page-walks are satisfied by the caches
or cause an L2 cache miss.
10H
11H
00H
00H
FP_COMP_OPS
_EXE
FP_ASSIST
Floating point
computational microops executed.
This event counts the number of floating point
computational micro-ops executed.
Floating point assists.
This event counts the number of floating point operations
executed that required micro-code assist intervention.
Assists are required in the following cases:
Use IA32_PMC0 only.
• Streaming SIMD Extensions (SSE) instructions:
• Denormal input when the DAZ (Denormals Are Zeros) flag
is off
• Underflow result when the FTZ (Flush To Zero) flag is off
• X87 instructions:
• NaN or denormal are loaded to a register or used as input
from memory
• Division by 0
• Underflow output
Use IA32_PMC1 only.
12H
00H
MUL
Multiply operations
executed.
This event counts the number of multiply operations
executed. This includes integer as well as floating point
multiply operations.
Use IA32_PMC1 only.
13H
00H
DIV
Divide operations
executed.
This event counts the number of divide operations
executed. This includes integer divides, floating point
divides and square-root operations executed.
Use IA32_PMC1 only.
14H
00H
CYCLES_DIV
_BUSY
Cycles the divider
busy.
18H
00H
IDLE_DURING
_DIV
Cycles the divider is
busy and all other
execution units are
idle.
This event counts the number of cycles the divider is busy
executing divide or square root operations. The divide can
be integer, X87 or Streaming SIMD Extensions (SSE). The
square root operation can be either X87 or SSE.
Use IA32_PMC0 only.
This event counts the number of cycles the divider is busy
(with a divide or a square root operation) and no other
execution unit or load operation is in progress.
Load operations are assumed to hit the L1 data cache. This
event considers only micro-ops dispatched after the divider
started operating.
Use IA32_PMC0 only.
19-122 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
19H
00H
Event Name
Definition
DELAYED_
BYPASS.FP
Delayed bypass to FP
operation.
Description and
Comment
This event counts the number of times floating point
operations use data immediately after the data was
generated by a non-floating point execution unit. Such cases
result in one penalty cycle due to data bypass between the
units.
Use IA32_PMC1 only.
19H
01H
DELAYED_
BYPASS.SIMD
Delayed bypass to
SIMD operation.
This event counts the number of times SIMD operations use
data immediately after the data was generated by a nonSIMD execution unit. Such cases result in one penalty cycle
due to data bypass between the units.
Use IA32_PMC1 only.
19H
02H
DELAYED_
BYPASS.LOAD
Delayed bypass to
load operation.
This event counts the number of delayed bypass penalty
cycles that a load operation incurred.
When load operations use data immediately after the data
was generated by an integer execution unit, they may
(pending on certain dynamic internal conditions) incur one
penalty cycle due to delayed data bypass between the units.
Use IA32_PMC1 only.
21H
See
Table
18-3
L2_ADS.(Core)
Cycles L2 address bus
is in use.
This event counts the number of cycles the L2 address bus
is being used for accesses to the L2 cache or bus queue. It
can count occurrences for this core or both cores.
23H
See
Table
18-3
L2_DBUS_BUSY
_RD.(Core)
Cycles the L2
transfers data to the
core.
This event counts the number of cycles during which the L2
data bus is busy transferring data from the L2 cache to the
core. It counts for all L1 cache misses (data and instruction)
that hit the L2 cache.
This event can count occurrences for this core or both cores.
24H
25H
26H
27H
Combined
mask
from
Table
18-3
and
Table
18-5
L2_LINES_IN.
(Core, Prefetch)
See
Table
18-3
L2_M_LINES_IN.
(Core)
See
Table
18-3
and
Table
18-5
L2_LINES_OUT.
(Core, Prefetch)
L2 cache lines evicted. This event counts the number of L2 cache lines evicted.
See
Table
18-3
and
Table
18-5
L2_M_LINES_OUT.(Core,
Prefetch)
Modified lines evicted
from the L2 cache.
L2 cache misses.
This event counts the number of cache lines allocated in the
L2 cache. Cache lines are allocated in the L2 cache as a
result of requests from the L1 data and instruction caches
and the L2 hardware prefetchers to cache lines that are
missing in the L2 cache.
This event can count occurrences for this core or both cores.
It can also count demand requests and L2 hardware
prefetch requests together or separately.
L2 cache line
modifications.
This event counts whenever a modified cache line is written
back from the L1 data cache to the L2 cache.
This event can count occurrences for this core or both cores.
This event can count occurrences for this core or both cores.
It can also count evictions due to demand requests and L2
hardware prefetch requests together or separately.
This event counts the number of L2 modified cache lines
evicted. These lines are written back to memory unless they
also exist in a modified-state in one of the L1 data caches.
This event can count occurrences for this core or both cores.
It can also count evictions due to demand requests and L2
hardware prefetch requests together or separately.
Vol. 3B 19-123
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
28H
Combined
mask
from
Table
18-3
and
Table
18-6
29H
2AH
2BH
2EH
2EH
Event Name
Definition
L2_IFETCH.(Core, Cache
Line State)
L2 cacheable
instruction fetch
requests.
Description and
Comment
This event counts the number of instruction cache line
requests from the IFU. It does not include fetch requests
from uncacheable memory. It does not include ITLB miss
accesses.
This event can count occurrences for this core or both cores.
It can also count accesses to cache lines at different MESI
states.
Combin L2_LD.(Core, Prefetch,
ed mask Cache Line State)
from
Table
18-3,
Table
18-5,
and
Table
18-6
L2 cache reads.
See
Table
18-3
and
Table
18-6
L2_ST.(Core, Cache Line
State)
L2 store requests.
See
Table
18-3
and
Table
18-6
L2_LOCK.(Core, Cache Line
State)
See
Table
18-3,
Table
18-5,
and
Table
18-6
L2_RQSTS.(Core, Prefetch,
Cache Line State)
41H
L2_RQSTS.SELF.
DEMAND.I_STATE
This event counts L2 cache read requests coming from the
L1 data cache and L2 prefetchers.
The event can count occurrences:
• For this core or both cores.
• Due to demand requests and L2 hardware prefetch
requests together or separately.
• Of accesses to cache lines at different MESI states.
This event counts all store operations that miss the L1 data
cache and request the data from the L2 cache.
The event can count occurrences for this core or both cores.
It can also count accesses to cache lines at different MESI
states.
L2 locked accesses.
This event counts all locked accesses to cache lines that
miss the L1 data cache.
The event can count occurrences for this core or both cores.
It can also count accesses to cache lines at different MESI
states.
L2 cache requests.
This event counts all completed L2 cache requests. This
includes L1 data cache reads, writes, and locked accesses,
L1 data prefetch requests, instruction fetches, and all L2
hardware prefetch requests.
This event can count occurrences:
• For this core or both cores.
• Due to demand requests and L2 hardware prefetch
requests together, or separately.
• Of accesses to cache lines at different MESI states.
L2 cache demand
requests from this
core that missed the
L2.
This event counts all completed L2 cache demand requests
from this core that miss the L2 cache. This includes L1 data
cache reads, writes, and locked accesses, L1 data prefetch
requests, and instruction fetches.
This is an architectural performance event.
2EH
4FH
L2_RQSTS.SELF.
DEMAND.MESI
L2 cache demand
requests from this
core.
This event counts all completed L2 cache demand requests
from this core. This includes L1 data cache reads, writes,
and locked accesses, L1 data prefetch requests, and
instruction fetches.
This is an architectural performance event.
19-124 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
30H
See
Table
18-3,
Table
18-5,
and
Table
18-6
Event Name
Definition
L2_REJECT_BUSQ.(Core,
Rejected L2 cache
Prefetch, Cache Line State) requests.
Description and
Comment
This event indicates that a pending L2 cache request that
requires a bus transaction is delayed from moving to the bus
queue. Some of the reasons for this event are:
• The bus queue is full.
• The bus queue already holds an entry for a cache line in
the same set.
The number of events is greater or equal to the number of
requests that were rejected.
• For this core or both cores.
• Due to demand requests and L2 hardware prefetch
requests together, or separately.
• Of accesses to cache lines at different MESI states.
32H
See
Table
18-3
L2_NO_REQ.(Core)
Cycles no L2 cache
requests are pending.
This event counts the number of cycles that no L2 cache
requests were pending from a core. When using the
BOTH_CORE modifier, the event counts only if none of the
cores have a pending request. The event counts also when
one core is halted and the other is not halted.
The event can count occurrences for this core or both cores.
3AH
00H
EIST_TRANS
Number of Enhanced
Intel SpeedStep
Technology (EIST)
transitions.
This event counts the number of transitions that include a
frequency change, either with or without voltage change.
This includes Enhanced Intel SpeedStep Technology (EIST)
and TM2 transitions.
The event is incremented only while the counting core is in
C0 state. Since transitions to higher-numbered CxE states
and TM2 transitions include a frequency change or voltage
transition, the event is incremented accordingly.
3BH
C0H
THERMAL_TRIP
Number of thermal
trips.
This event counts the number of thermal trips. A thermal
trip occurs whenever the processor temperature exceeds
the thermal trip threshold temperature.
Following a thermal trip, the processor automatically
reduces frequency and voltage. The processor checks the
temperature every millisecond and returns to normal when
the temperature falls below the thermal trip threshold
temperature.
3CH
00H
CPU_CLK_
UNHALTED.
CORE_P
Core cycles when core This event counts the number of core cycles while the core
is not halted.
is not in a halt state. The core enters the halt state when it
is running the HLT instruction. This event is a component in
many key event ratios.
The core frequency may change due to transitions
associated with Enhanced Intel SpeedStep Technology or
TM2. For this reason, this event may have a changing ratio in
regard to time.
When the core frequency is constant, this event can give
approximate elapsed time while the core not in halt state.
This is an architectural performance event.
Vol. 3B 19-125
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
3CH
01H
Event Name
Definition
CPU_CLK_
UNHALTED.BUS
Bus cycles when core
is not halted.
Description and
Comment
This event counts the number of bus cycles while the core is
not in the halt state. This event can give a measurement of
the elapsed time while the core was not in the halt state.
The core enters the halt state when it is running the HLT
instruction.
The event also has a constant ratio with
CPU_CLK_UNHALTED.REF event, which is the maximum bus
to processor frequency ratio.
Non-halted bus cycles are a component in many key event
ratios.
3CH
02H
CPU_CLK_
UNHALTED.NO
_OTHER
Bus cycles when core This event counts the number of bus cycles during which
is active and the other the core remains non-halted and the other core on the
is halted.
processor is halted.
This event can be used to determine the amount of
parallelism exploited by an application or a system. Divide
this event count by the bus frequency to determine the
amount of time that only one core was in use.
40H
See
Table
18-6
L1D_CACHE_LD.
(Cache Line State)
L1 cacheable data
reads.
This event counts the number of data reads from cacheable
memory. Locked reads are not counted.
41H
See
Table
18-6
L1D_CACHE_ST.
(Cache Line State)
L1 cacheable data
writes.
This event counts the number of data writes to cacheable
memory. Locked writes are not counted.
42H
See
Table
18-6
L1D_CACHE_
LOCK.(Cache Line State)
L1 data cacheable
locked reads.
This event counts the number of locked data reads from
cacheable memory.
42H
10H
L1D_CACHE_
LOCK_DURATION
Duration of L1 data
cacheable locked
operation.
This event counts the number of cycles during which any
cache line is locked by any locking instruction.
43H
01H
L1D_ALL_REF
All references to the
L1 data cache.
Locking happens at retirement and therefore the event does
not occur for instructions that are speculatively executed.
Locking duration is shorter than locked instruction execution
duration.
This event counts all references to the L1 data cache,
including all loads and stores with any memory types.
The event counts memory accesses only when they are
actually performed. For example, a load blocked by unknown
store address and later performed is only counted once.
The event includes non-cacheable accesses, such as I/O
accesses.
43H
02H
L1D_ALL_
CACHE_REF
L1 Data cacheable
reads and writes.
This event counts the number of data reads and writes from
cacheable memory, including locked operations.
This event is a sum of:
• L1D_CACHE_LD.MESI
• L1D_CACHE_ST.MESI
• L1D_CACHE_LOCK.MESI
45H
0FH
L1D_REPL
Cache lines allocated
in the L1 data cache.
This event counts the number of lines brought into the L1
data cache.
46H
00H
L1D_M_REPL
Modified cache lines
allocated in the L1
data cache.
This event counts the number of modified lines brought into
the L1 data cache.
19-126 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
Description and
Comment
47H
00H
L1D_M_EVICT
Modified cache lines
evicted from the L1
data cache.
This event counts the number of modified lines evicted from
the L1 data cache, whether due to replacement or by snoop
HITM intervention.
48H
00H
L1D_PEND_
MISS
Total number of
outstanding L1 data
cache misses at any
cycle.
This event counts the number of outstanding L1 data cache
misses at any cycle. An L1 data cache miss is outstanding
from the cycle on which the miss is determined until the
first chunk of data is available. This event counts:
• All cacheable demand requests.
• L1 data cache hardware prefetch requests.
• Requests to write through memory.
• Requests to write combine memory.
Uncacheable requests are not counted. The count of this
event divided by the number of L1 data cache misses,
L1D_REPL, is the average duration in core cycles of an L1
data cache miss.
49H
01H
L1D_SPLIT.LOADS
Cache line split loads
from the L1 data
cache.
This event counts the number of load operations that span
two cache lines. Such load operations are also called split
loads. Split load operations are executed at retirement.
49H
02H
L1D_SPLIT.
STORES
Cache line split stores
to the L1 data cache.
This event counts the number of store operations that span
two cache lines.
4BH
00H
SSE_PRE_
MISS.NTA
Streaming SIMD
Extensions (SSE)
Prefetch NTA
instructions missing all
cache levels.
This event counts the number of times the SSE instructions
prefetchNTA were executed and missed all cache levels.
Streaming SIMD
Extensions (SSE)
PrefetchT0
instructions missing all
cache levels.
This event counts the number of times the SSE instructions
prefetchT0 were executed and missed all cache levels.
Streaming SIMD
Extensions (SSE)
PrefetchT1 and
PrefetchT2
instructions missing all
cache levels.
This event counts the number of times the SSE instructions
prefetchT1 and prefetchT2 were executed and missed all
cache levels.
This event counts load operations sent to the L1 data cache
while a previous Streaming SIMD Extensions (SSE) prefetch
instruction to the same cache line has started prefetching
but has not yet finished.
4BH
4BH
01H
02H
SSE_PRE_
MISS.L1
SSE_PRE_
MISS.L2
Due to speculation an executed instruction might not retire.
This instruction prefetches the data to the L1 data cache.
Due to speculation executed instruction might not retire.
The prefetchT0 instruction prefetches data to the L2 cache
and L1 data cache.
Due to speculation, an executed instruction might not retire.
The prefetchT1 and PrefetchNT2 instructions prefetch data
to the L2 cache.
4CH
00H
LOAD_HIT_PRE
Load operations
conflicting with a
software prefetch to
the same address.
4EH
10H
L1D_PREFETCH.
REQUESTS
L1 data cache prefetch This event counts the number of times the L1 data cache
requests.
requested to prefetch a data cache line. Requests can be
rejected when the L2 cache is busy and resubmitted later or
lost.
All requests are counted, including those that are rejected.
Vol. 3B 19-127
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
60H
61H
Description and
Comment
Event Name
Definition
See
Table
18-3
and
Table
18-4.
BUS_REQUEST_
OUTSTANDING.
(Core and Bus Agents)
Outstanding cacheable This event counts the number of pending full cache line read
data read bus
transactions on the bus occurring in each cycle. A read
requests duration.
transaction is pending from the cycle it is sent on the bus
until the full cache line is received by the processor.
See
Table
18-4.
BUS_BNR_DRV.
(Bus Agents)
The event counts only full-line cacheable read requests from
either the L1 data cache or the L2 prefetchers. It does not
count Read for Ownership transactions, instruction byte
fetch transactions, or any other bus transaction.
Number of Bus Not
Ready signals
asserted.
This event counts the number of Bus Not Ready (BNR)
signals that the processor asserts on the bus to suspend
additional bus requests by other bus agents.
A bus agent asserts the BNR signal when the number of
data and snoop transactions is close to the maximum that
the bus can handle. To obtain the number of bus cycles
during which the BNR signal is asserted, multiply the event
count by two.
While this signal is asserted, new transactions cannot be
submitted on the bus. As a result, transaction latency may
have higher impact on program performance.
62H
See
Table
18-4.
BUS_DRDY_
CLOCKS.(Bus Agents)
Bus cycles when data
is sent on the bus.
This event counts the number of bus cycles during which
the DRDY (Data Ready) signal is asserted on the bus. The
DRDY signal is asserted when data is sent on the bus. With
the 'THIS_AGENT' mask this event counts the number of bus
cycles during which this agent (the processor) writes data
on the bus back to memory or to other bus agents. This
includes all explicit and implicit data writebacks, as well as
partial writes.
With the 'ALL_AGENTS' mask, this event counts the number
of bus cycles during which any bus agent sends data on the
bus. This includes all data reads and writes on the bus.
See
Table
18-3
and
Table
18-4.
BUS_LOCK_
CLOCKS.(Core and Bus
Agents)
64H
See
Table
18-3.
BUS_DATA_
RCV.(Core)
Bus cycles while
processor receives
data.
This event counts the number of bus cycles during which
the processor is busy receiving data.
65H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_BRD.(Core
and Bus Agents)
Burst read bus
transactions.
This event counts the number of burst read transactions
including:
63H
19-128 Vol. 3B
Bus cycles when a
LOCK signal asserted.
This event counts the number of bus cycles, during which
the LOCK signal is asserted on the bus. A LOCK signal is
asserted when there is a locked memory access, due to:
• Uncacheable memory.
• Locked operation that spans two cache lines.
• Page-walk from an uncacheable page table.
Bus locks have a very high performance penalty and it is
highly recommended to avoid such accesses.
• L1 data cache read misses (and L1 data cache hardware
prefetches).
• L2 hardware prefetches by the DPL and L2 streamer.
• IFU read misses of cacheable lines.
It does not include RFO transactions.
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
66H
Description and
Comment
Event Name
Definition
See
Table
18-3
and
Table
18-4.
BUS_TRANS_RFO.(Core
and Bus Agents)
RFO bus transactions.
This event counts the number of Read For Ownership (RFO)
bus transactions, due to store operations that miss the L1
data cache and the L2 cache. It also counts RFO bus
transactions due to locked operations.
67H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_WB.
(Core and Bus Agents)
Explicit writeback bus
transactions.
This event counts all explicit writeback bus transactions due
to dirty line evictions. It does not count implicit writebacks
due to invalidation by a snoop request.
68H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_
IFETCH.(Core and Bus
Agents)
Instruction-fetch bus
transactions.
This event counts all instruction fetch full cache line bus
transactions.
69H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_
INVAL.(Core and Bus
Agents)
Invalidate bus
transactions.
This event counts all invalidate transactions. Invalidate
transactions are generated when:
6AH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_
Partial write bus
PWR.(Core and Bus Agents) transaction.
This event counts partial write bus transactions.
6BH
See
Table
18-3
and
Table
18-4.
BUS_TRANS
_P.(Core and Bus Agents)
Partial bus
transactions.
This event counts all (read and write) partial bus
transactions.
6CH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_IO.(Core and
Bus Agents)
IO bus transactions.
This event counts the number of completed I/O bus
transactions as a result of IN and OUT instructions. The
count does not include memory mapped IO.
6DH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_
DEF.(Core and Bus Agents)
Deferred bus
transactions.
This event counts the number of deferred transactions.
• A store operation hits a shared line in the L2 cache.
• A full cache line write misses the L2 cache or hits a
shared line in the L2 cache.
Vol. 3B 19-129
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
6EH
6FH
70H
77H
78H
Event Name
Definition
Description and
Comment
See
Table
18-3
and
Table
18-4.
BUS_TRANS_
BURST.(Core and Bus
Agents)
Burst (full cache-line)
bus transactions.
This event counts burst (full cache line) transactions
including:
See
Table
18-3
and
Table
18-4.
BUS_TRANS_
Memory bus
MEM.(Core and Bus Agents) transactions.
This event counts all memory bus transactions including:
See
Table
18-3
and
Table
18-4.
BUS_TRANS_
All bus transactions.
ANY.(Core and Bus Agents)
This event counts all bus transactions. This includes:
See
Table
18-3
and
Table
18-7.
EXT_SNOOP.
(Bus Agents, Snoop
Response)
This event counts the snoop responses to bus transactions.
Responses can be counted separately by type and by bus
agent.
See
Table
18-3
and
Table
18-8.
CMP_SNOOP.(Core, Snoop
Type)
•
•
•
•
External snoops.
Burst reads.
RFOs.
Explicit writebacks.
Write combine lines.
• Burst transactions.
• Partial reads and writes - invalidate transactions.
The BUS_TRANS_MEM count is the sum of
BUS_TRANS_BURST, BUS_TRANS_P and BUS_TRANS_IVAL.
•
•
•
•
Memory transactions.
IO transactions (non memory-mapped).
Deferred transaction completion.
Other less frequent transactions, such as interrupts.
With the 'THIS_AGENT' mask, the event counts snoop
responses from this processor to bus transactions sent by
this processor. With the 'ALL_AGENTS' mask the event
counts all snoop responses seen on the bus.
L1 data cache
This event counts the number of times the L1 data cache is
snooped by other core. snooped for a cache line that is needed by the other core in
the same processor. The cache line is either missing in the
L1 instruction or data caches of the other core, or is
available for reading only and the other core wishes to write
the cache line.
The snoop operation may change the cache line state. If the
other core issued a read request that hit this core in E state,
typically the state changes to S state in this core. If the
other core issued a read for ownership request (due a write
miss or hit to S state) that hits this core's cache line in E or S
state, this typically results in invalidation of the cache line in
this core. If the snoop hits a line in M state, the state is
changed at a later opportunity.
These snoops are performed through the L1 data cache
store port. Therefore, frequent snoops may conflict with
extensive stores to the L1 data cache, which may increase
store latency and impact performance.
7AH
7BH
See
Table
18-4.
BUS_HIT_DRV.
See
Table
18-4.
BUS_HITM_DRV.
19-130 Vol. 3B
HIT signal asserted.
This event counts the number of bus cycles during which
the processor drives the HIT# pin to signal HIT snoop
response.
HITM signal asserted.
This event counts the number of bus cycles during which
the processor drives the HITM# pin to signal HITM snoop
response.
(Bus Agents)
(Bus Agents)
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
7DH
See
Table
18-3.
Event Name
Definition
BUSQ_EMPTY.
Bus queue empty.
(Core)
Description and
Comment
This event counts the number of cycles during which the
core did not have any pending transactions in the bus queue.
It also counts when the core is halted and the other core is
not halted.
This event can count occurrences for this core or both cores.
7EH
7FH
See
Table
18-3
and
Table
18-4.
SNOOP_STALL_
Bus stalled for snoops. This event counts the number of times that the bus snoop
DRV.(Core and Bus Agents)
stall signal is asserted. To obtain the number of bus cycles
during which snoops on the bus are prohibited, multiply the
event count by two.
See
Table
18-3.
BUS_IO_WAIT.
(Core)
During the snoop stall cycles, no new bus transactions
requiring a snoop response can be initiated on the bus. A
bus agent asserts a snoop stall signal if it cannot response
to a snoop request within three bus cycles.
IO requests waiting in
the bus queue.
This event counts the number of core cycles during which IO
requests wait in the bus queue. With the SELF modifier this
event counts IO requests per core.
With the BOTH_CORE modifier, this event increments by one
for any cycle for which there is a request from either core.
80H
00H
L1I_READS
Instruction fetches.
This event counts all instruction fetches, including
uncacheable fetches that bypass the Instruction Fetch Unit
(IFU).
81H
00H
L1I_MISSES
Instruction Fetch Unit
misses.
This event counts all instruction fetches that miss the
Instruction Fetch Unit (IFU) or produce memory requests.
This includes uncacheable fetches.
An instruction fetch miss is counted only once and not once
for every cycle it is outstanding.
82H
02H
ITLB.SMALL_MISS
ITLB small page
misses.
This event counts the number of instruction fetches from
small pages that miss the ITLB.
82H
10H
ITLB.LARGE_MISS
ITLB large page
misses.
This event counts the number of instruction fetches from
large pages that miss the ITLB.
82H
40H
ITLB.FLUSH
ITLB flushes.
This event counts the number of ITLB flushes. This usually
happens upon CR3 or CR0 writes, which are executed by
the operating system during process switches.
82H
12H
ITLB.MISSES
ITLB misses.
This event counts the number of instruction fetches from
either small or large pages that miss the ITLB.
83H
02H
INST_QUEUE.FULL
Cycles during which
the instruction queue
is full.
This event counts the number of cycles during which the
instruction queue is full. In this situation, the core front end
stops fetching more instructions. This is an indication of
very long stalls in the back-end pipeline stages.
86H
00H
CYCLES_L1I_
MEM_STALLED
Cycles during which
instruction fetches
stalled.
This event counts the number of cycles for which an
instruction fetch stalls, including stalls due to any of the
following reasons:
• Instruction Fetch Unit cache misses.
• Instruction TLB misses.
• Instruction TLB faults.
87H
00H
ILD_STALL
Instruction Length
Decoder stall cycles
due to a length
changing prefix.
This event counts the number of cycles during which the
instruction length decoder uses the slow length decoder.
Usually, instruction length decoding is done in one cycle.
When the slow decoder is used, instruction decoding
requires 6 cycles.
Vol. 3B 19-131
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
Description and
Comment
The slow decoder is used in the following cases:
• Operand override prefix (66H) preceding an instruction
with immediate data.
• Address override prefix (67H) preceding an instruction
with a modr/m in real, big real, 16-bit protected or 32-bit
protected modes.
To avoid instruction length decoding stalls, generate code
using imm8 or imm32 values instead of imm16 values. If
you must use an imm16 value, store the value in a register
using “mov reg, imm32” and use the register format of the
instruction.
88H
00H
BR_INST_EXEC
Branch instructions
executed.
This event counts all executed branches (not necessarily
retired). This includes only instructions and not micro-op
branches.
Frequent branching is not necessarily a major performance
issue. However frequent branch mispredictions may be a
problem.
89H
00H
BR_MISSP_EXEC
Mispredicted branch
This event counts the number of mispredicted branch
instructions executed. instructions that were executed.
8AH
00H
BR_BAC_
MISSP_EXEC
Branch instructions
mispredicted at
decoding.
8BH
00H
BR_CND_EXEC
Conditional branch
This event counts the number of conditional branch
instructions executed. instructions executed, but not necessarily retired.
8CH
00H
BR_CND_
MISSP_EXEC
Mispredicted
This event counts the number of mispredicted conditional
conditional branch
branch instructions that were executed.
instructions executed.
8DH
00H
BR_IND_EXEC
Indirect branch
This event counts the number of indirect branch instructions
instructions executed. that were executed.
8EH
00H
BR_IND_MISSP
_EXEC
Mispredicted indirect
branch instructions
executed.
This event counts the number of mispredicted indirect
branch instructions that were executed.
8FH
00H
BR_RET_EXEC
RET instructions
executed.
This event counts the number of RET instructions that were
executed.
90H
00H
BR_RET_
MISSP_EXEC
Mispredicted RET
This event counts the number of mispredicted RET
instructions executed. instructions that were executed.
91H
00H
BR_RET_BAC_
MISSP_EXEC
RET instructions
This event counts the number of RET instructions that were
executed mispredicted executed and were mispredicted at decoding.
at decoding.
92H
00H
BR_CALL_EXEC
CALL instructions
executed.
93H
00H
BR_CALL_
MISSP_EXEC
Mispredicted CALL
This event counts the number of mispredicted CALL
instructions executed. instructions that were executed.
94H
00H
BR_IND_CALL_
EXEC
Indirect CALL
This event counts the number of indirect CALL instructions
instructions executed. that were executed.
19-132 Vol. 3B
This event counts the number of branch instructions that
were mispredicted at decoding.
This event counts the number of CALL instructions
executed.
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
97H
00H
Event Name
Definition
BR_TKN_
BUBBLE_1
Branch predicted
taken with bubble 1.
Description and
Comment
The events BR_TKN_BUBBLE_1 and BR_TKN_BUBBLE_2
together count the number of times a taken branch
prediction incurred a one-cycle penalty. The penalty incurs
when:
• Too many taken branches are placed together. To avoid
this, unroll loops and add a non-taken branch in the
middle of the taken sequence.
• The branch target is unaligned. To avoid this, align the
branch target.
98H
00H
BR_TKN_
BUBBLE_2
Branch predicted
taken with bubble 2.
The events BR_TKN_BUBBLE_1 and BR_TKN_BUBBLE_2
together count the number of times a taken branch
prediction incurred a one-cycle penalty. The penalty incurs
when:
• Too many taken branches are placed together. To avoid
this, unroll loops and add a non-taken branch in the
middle of the taken sequence.
• The branch target is unaligned. To avoid this, align the
branch target.
A0H
00H
RS_UOPS_
DISPATCHED
Micro-ops dispatched
for execution.
This event counts the number of micro-ops dispatched for
execution. Up to six micro-ops can be dispatched in each
cycle.
A1H
01H
RS_UOPS_
DISPATCHED.PORT0
Cycles micro-ops
dispatched for
execution on port 0.
This event counts the number of cycles for which micro-ops
dispatched for execution. Each cycle, at most one micro-op
can be dispatched on the port. Issue Ports are described in
Intel® 64 and IA-32 Architectures Optimization Reference
Manual. Use IA32_PMC0 only.
A1H
02H
RS_UOPS_
DISPATCHED.PORT1
Cycles micro-ops
dispatched for
execution on port 1.
This event counts the number of cycles for which micro-ops
dispatched for execution. Each cycle, at most one micro-op
can be dispatched on the port. Use IA32_PMC0 only.
A1H
04H
RS_UOPS_
DISPATCHED.PORT2
Cycles micro-ops
dispatched for
execution on port 2.
This event counts the number of cycles for which micro-ops
dispatched for execution. Each cycle, at most one micro-op
can be dispatched on the port. Use IA32_PMC0 only.
A1H
08H
RS_UOPS_
DISPATCHED.PORT3
Cycles micro-ops
dispatched for
execution on port 3.
This event counts the number of cycles for which micro-ops
dispatched for execution. Each cycle, at most one micro-op
can be dispatched on the port. Use IA32_PMC0 only.
A1H
10H
RS_UOPS_
DISPATCHED.PORT4
Cycles micro-ops
dispatched for
execution on port 4.
This event counts the number of cycles for which micro-ops
dispatched for execution. Each cycle, at most one micro-op
can be dispatched on the port. Use IA32_PMC0 only.
A1H
20H
RS_UOPS_
DISPATCHED.PORT5
Cycles micro-ops
dispatched for
execution on port 5.
This event counts the number of cycles for which micro-ops
dispatched for execution. Each cycle, at most one micro-op
can be dispatched on the port. Use IA32_PMC0 only.
AAH
01H
MACRO_INSTS.
DECODED
Instructions decoded.
This event counts the number of instructions decoded (but
not necessarily executed or retired).
AAH
08H
MACRO_INSTS.
CISC_DECODED
CISC Instructions
decoded.
This event counts the number of complex instructions
decoded. Complex instructions usually have more than four
micro-ops. Only one complex instruction can be decoded at a
time.
Vol. 3B 19-133
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
ABH
01H
ESP.SYNCH
ESP register content
synchron-ization.
Description and
Comment
This event counts the number of times that the ESP register
is explicitly used in the address expression of a load or store
operation, after it is implicitly used, for example by a push or
a pop instruction.
ESP synch micro-op uses resources from the rename pipestage and up to retirement. The expected ratio of this event
divided by the number of ESP implicit changes is 0,2. If the
ratio is higher, consider rearranging your code to avoid ESP
synchronization events.
ABH
02H
ESP.ADDITIONS
ESP register automatic This event counts the number of ESP additions performed
additions.
automatically by the decoder. A high count of this event is
good, since each automatic addition performed by the
decoder saves a micro-op from the execution units.
To maximize the number of ESP additions performed
automatically by the decoder, choose instructions that
implicitly use the ESP, such as PUSH, POP, CALL, and RET
instructions whenever possible.
B0H
00H
SIMD_UOPS_EXEC
SIMD micro-ops
executed (excluding
stores).
This event counts all the SIMD micro-ops executed. It does
not count MOVQ and MOVD stores from register to memory.
B1H
00H
SIMD_SAT_UOP_
EXEC
SIMD saturated
arithmetic micro-ops
executed.
This event counts the number of SIMD saturated arithmetic
micro-ops executed.
B3H
01H
SIMD_UOP_
TYPE_EXEC.MUL
SIMD packed multiply
micro-ops executed.
This event counts the number of SIMD packed multiply
micro-ops executed.
B3H
02H
SIMD_UOP_TYPE_EXEC.SHI SIMD packed shift
FT
micro-ops executed.
This event counts the number of SIMD packed shift microops executed.
B3H
04H
SIMD_UOP_TYPE_EXEC.PA
CK
This event counts the number of SIMD pack micro-ops
executed.
B3H
08H
SIMD_UOP_TYPE_EXEC.UN SIMD unpack microPACK
ops executed.
This event counts the number of SIMD unpack micro-ops
executed.
B3H
10H
SIMD_UOP_TYPE_EXEC.LO
GICAL
This event counts the number of SIMD packed logical microops executed.
B3H
20H
SIMD_UOP_TYPE_EXEC.ARI SIMD packed
THMETIC
arithmetic micro-ops
executed.
This event counts the number of SIMD packed arithmetic
micro-ops executed.
C0H
00H
INST_RETIRED.
ANY_P
This event counts the number of instructions that retire
execution. For instructions that consist of multiple microops, this event counts the retirement of the last micro-op of
the instruction. The counter continues counting during
hardware interrupts, traps, and inside interrupt handlers.
SIMD pack micro-ops
executed.
SIMD packed logical
micro-ops executed.
Instructions retired.
INST_RETIRED.ANY_P is an architectural performance
event.
C0H
01H
INST_RETIRED.
LOADS
Instructions retired,
which contain a load.
This event counts the number of instructions retired that
contain a load operation.
C0H
02H
INST_RETIRED.
STORES
Instructions retired,
which contain a store.
This event counts the number of instructions retired that
contain a store operation.
19-134 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
C0H
Description and
Comment
Event Name
Definition
04H
INST_RETIRED.
OTHER
Instructions retired,
with no load or store
operation.
This event counts the number of instructions retired that do
not contain a load or a store operation.
C1H
01H
X87_OPS_
RETIRED.FXCH
FXCH instructions
retired.
This event counts the number of FXCH instructions retired.
Modern compilers generate more efficient code and are less
likely to use this instruction. If you obtain a high count for
this event consider recompiling the code.
C1H
FEH
X87_OPS_
RETIRED.ANY
Retired floating-point
computational
operations (precise
event).
This event counts the number of floating-point
computational operations retired. It counts:
• Floating point computational operations executed by the
assist handler.
• Sub-operations of complex floating-point instructions like
transcendental instructions.
This event does not count:
• Floating-point computational operations that cause traps
or assists.
• Floating-point loads and stores.
When this event is captured with the precise event
mechanism, the collected samples contain the address of
the instruction that was executed immediately after the
instruction that caused the event.
C2H
01H
UOPS_RETIRED.
LD_IND_BR
Fused load+op or
load+indirect branch
retired.
This event counts the number of retired micro-ops that
fused a load with another operation. This includes:
• Fusion of a load and an arithmetic operation, such as with
the following instruction: ADD EAX, [EBX] where the
content of the memory location specified by EBX register
is loaded, added to EXA register, and the result is stored
in EAX.
• Fusion of a load and a branch in an indirect branch
operation, such as with the following instructions:
• JMP [RDI+200]
• RET
• Fusion decreases the number of micro-ops in the
processor pipeline. A high value for this event count
indicates that the code is using the processor resources
effectively.
C2H
02H
UOPS_RETIRED.
STD_STA
Fused store address + This event counts the number of store address calculations
data retired.
that are fused with store data emission into one micro-op.
Traditionally, each store operation required two micro-ops.
This event counts fusion of retired micro-ops only. Fusion
decreases the number of micro-ops in the processor
pipeline. A high value for this event count indicates that the
code is using the processor resources effectively.
C2H
04H
UOPS_RETIRED.
MACRO_FUSION
Retired instruction
pairs fused into one
micro-op.
This event counts the number of times CMP or TEST
instructions were fused with a conditional branch
instruction into one micro-op. It counts fusion by retired
micro-ops only.
Fusion decreases the number of micro-ops in the processor
pipeline. A high value for this event count indicates that the
code uses the processor resources more effectively.
Vol. 3B 19-135
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
C2H
07H
Event Name
Definition
Description and
Comment
UOPS_RETIRED.
FUSED
Fused micro-ops
retired.
This event counts the total number of retired fused microops. The counts include the following fusion types:
• Fusion of load operation with an arithmetic operation or
with an indirect branch (counted by event
UOPS_RETIRED.LD_IND_BR)
• Fusion of store address and data (counted by event
UOPS_RETIRED.STD_STA)
• Fusion of CMP or TEST instruction with a conditional
branch instruction (counted by event
UOPS_RETIRED.MACRO_FUSION)
Fusion decreases the number of micro-ops in the processor
pipeline. A high value for this event count indicates that the
code is using the processor resources effectively.
C2H
08H
UOPS_RETIRED.
NON_FUSED
Non-fused micro-ops
retired.
This event counts the number of micro-ops retired that
were not fused.
C2H
0FH
UOPS_RETIRED.
ANY
Micro-ops retired.
This event counts the number of micro-ops retired. The
processor decodes complex macro instructions into a
sequence of simpler micro-ops. Most instructions are
composed of one or two micro-ops.
Some instructions are decoded into longer sequences such
as repeat instructions, floating point transcendental
instructions, and assists. In some cases micro-op sequences
are fused or whole instructions are fused into one micro-op.
See other UOPS_RETIRED events for differentiating retired
fused and non-fused micro-ops.
C3H
01H
MACHINE_
NUKES.SMC
Self-Modifying Code
detected.
This event counts the number of times that a program
writes to a code section. Self-modifying code causes a
severe penalty in all Intel 64 and IA-32 processors.
C3H
04H
MACHINE_NUKES.MEM_OR
DER
Execution pipeline
restart due to memory
ordering conflict or
memory
disambiguation
misprediction.
This event counts the number of times the pipeline is
restarted due to either multi-threaded memory ordering
conflicts or memory disambiguation misprediction.
A multi-threaded memory ordering conflict occurs when a
store, which is executed in another core, hits a load that is
executed out of order in this core but not yet retired. As a
result, the load needs to be restarted to satisfy the memory
ordering model.
See Chapter 8, “Multiple-Processor Management” in the
Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
To count memory disambiguation mispredictions, use the
event MEMORY_DISAMBIGUATION.RESET.
00H
BR_INST_RETIRED.ANY
C4H
01H
BR_INST_RETIRED.PRED_N Retired branch
This event counts the number of branch instructions retired
OT_
instructions that were that were correctly predicted to be not-taken.
TAKEN
predicted not-taken.
C4H
02H
BR_INST_RETIRED.MISPRE
D_NOT_
TAKEN
19-136 Vol. 3B
Retired branch
instructions.
This event counts the number of branch instructions retired.
This is an architectural performance event.
C4H
This event counts the number of branch instructions retired
Retired branch
instructions that were that were mispredicted and not-taken.
mispredicted nottaken.
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
C4H
04H
BR_INST_RETIRED.PRED_T Retired branch
This event counts the number of branch instructions retired
AKEN
instructions that were that were correctly predicted to be taken.
predicted taken.
C4H
08H
BR_INST_RETIRED.MISPRE
D_TAKEN
Retired branch
This event counts the number of branch instructions retired
instructions that were that were mispredicted and taken.
mispredicted taken.
C4H
0CH
BR_INST_RETIRED.TAKEN
Retired taken branch
instructions.
This event counts the number of branches retired that were
taken.
C5H
00H
BR_INST_RETIRED.MISPRE
D
Retired mispredicted
branch instructions.
(precise event)
This event counts the number of retired branch instructions
that were mispredicted by the processor. A branch
misprediction occurs when the processor predicts that the
branch would be taken, but it is not, or vice-versa.
Event Name
Definition
Description and
Comment
This is an architectural performance event.
C6H
01H
CYCLES_INT_
MASKED
Cycles during which
interrupts are
disabled.
This event counts the number of cycles during which
interrupts are disabled.
C6H
02H
CYCLES_INT_
PENDING_AND
_MASKED
Cycles during which
This event counts the number of cycles during which there
interrupts are pending are pending interrupts but interrupts are disabled.
and disabled.
C7H
01H
SIMD_INST_
RETIRED.PACKED_SINGLE
Retired SSE packedsingle instructions.
This event counts the number of SSE packed-single
instructions retired.
C7H
02H
SIMD_INST_
RETIRED.SCALAR_SINGLE
Retired SSE scalarsingle instructions.
This event counts the number of SSE scalar-single
instructions retired.
C7H
04H
SIMD_INST_
RETIRED.PACKED_DOUBLE
Retired SSE2 packeddouble instructions.
This event counts the number of SSE2 packed-double
instructions retired.
C7H
08H
SIMD_INST_
RETIRED.SCALAR_DOUBLE
Retired SSE2 scalardouble instructions.
This event counts the number of SSE2 scalar-double
instructions retired.
C7H
10H
SIMD_INST_
RETIRED.VECTOR
Retired SSE2 vector
integer instructions.
This event counts the number of SSE2 vector integer
instructions retired.
C7H
1FH
SIMD_INST_
RETIRED.ANY
Retired Streaming
SIMD instructions
(precise event).
This event counts the overall number of retired SIMD
instructions that use XMM registers. To count each type of
SIMD instruction separately, use the following events:
• SIMD_INST_RETIRED.PACKED_SINGLE
• SIMD_INST_RETIRED.SCALAR_SINGLE
• SIMD_INST_RETIRED.PACKED_DOUBLE
• SIMD_INST_RETIRED.SCALAR_DOUBLE
• and SIMD_INST_RETIRED.VECTOR
When this event is captured with the precise event
mechanism, the collected samples contain the address of
the instruction that was executed immediately after the
instruction that caused the event.
C8H
00H
HW_INT_RCV
Hardware interrupts
received.
This event counts the number of hardware interrupts
received by the processor.
C9H
00H
ITLB_MISS_
RETIRED
Retired instructions
that missed the ITLB.
This event counts the number of retired instructions that
missed the ITLB when they were fetched.
Vol. 3B 19-137
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
CAH
01H
Description and
Comment
Event Name
Definition
SIMD_COMP_
INST_RETIRED.
PACKED_SINGLE
Retired computational This event counts the number of computational SSE packedSSE packed-single
single instructions retired. Computational instructions
instructions.
perform arithmetic computations (for example: add, multiply
and divide).
Instructions that perform load and store operations or
logical operations, like XOR, OR, and AND are not counted by
this event.
CAH
02H
SIMD_COMP_
INST_RETIRED.
SCALAR_SINGLE
Retired computational This event counts the number of computational SSE scalarSSE scalar-single
single instructions retired. Computational instructions
instructions.
perform arithmetic computations (for example: add, multiply
and divide).
Instructions that perform load and store operations or
logical operations, like XOR, OR, and AND are not counted by
this event.
CAH
04H
SIMD_COMP_
INST_RETIRED.
PACKED_DOUBLE
Retired computational This event counts the number of computational SSE2
SSE2 packed-double
packed-double instructions retired. Computational
instructions perform arithmetic computations (for example:
instructions.
add, multiply and divide).
Instructions that perform load and store operations or
logical operations, like XOR, OR, and AND are not counted by
this event.
CAH
08H
SIMD_COMP_INST_RETIRE
D.SCALAR_DOUBLE
Retired computational This event counts the number of computational SSE2 scalarSSE2 scalar-double
double instructions retired. Computational instructions
instructions.
perform arithmetic computations (for example: add, multiply
and divide).
Instructions that perform load and store operations or
logical operations, like XOR, OR, and AND are not counted by
this event.
CBH
01H
MEM_LOAD_
RETIRED.L1D
_MISS
Retired loads that miss This event counts the number of retired load operations
the L1 data cache
that missed the L1 data cache. This includes loads from
(precise event).
cache lines that are currently being fetched, due to a
previous L1 data cache miss to the same cache line.
This event counts loads from cacheable memory only. The
event does not count loads by software prefetches.
When this event is captured with the precise event
mechanism, the collected samples contain the address of
the instruction that was executed immediately after the
instruction that caused the event.
Use IA32_PMC0 only.
CBH
02H
MEM_LOAD_
RETIRED.L1D_
LINE_MISS
L1 data cache line
missed by retired
loads (precise event).
This event counts the number of load operations that miss
the L1 data cache and send a request to the L2 cache to
fetch the missing cache line. That is the missing cache line
fetching has not yet started.
The event count is equal to the number of cache lines
fetched from the L2 cache by retired loads.
This event counts loads from cacheable memory only. The
event does not count loads by software prefetches.
The event might not be counted if the load is blocked (see
LOAD_BLOCK events).
19-138 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
Description and
Comment
When this event is captured with the precise event
mechanism, the collected samples contain the address of
the instruction that was executed immediately after the
instruction that caused the event.
Use IA32_PMC0 only.
CBH
04H
MEM_LOAD_
RETIRED.L2_MISS
Retired loads that miss This event counts the number of retired load operations
the L2 cache (precise that missed the L2 cache.
event).
This event counts loads from cacheable memory only. It
does not count loads by software prefetches.
When this event is captured with the precise event
mechanism, the collected samples contain the address of
the instruction that was executed immediately after the
instruction that caused the event.
Use IA32_PMC0 only.
CBH
08H
MEM_LOAD_
RETIRED.L2_LINE_MISS
L2 cache line missed
by retired loads
(precise event).
This event counts the number of load operations that miss
the L2 cache and result in a bus request to fetch the missing
cache line. That is the missing cache line fetching has not
yet started.
This event count is equal to the number of cache lines
fetched from memory by retired loads.
This event counts loads from cacheable memory only. The
event does not count loads by software prefetches.
The event might not be counted if the load is blocked (see
LOAD_BLOCK events).
When this event is captured with the precise event
mechanism, the collected samples contain the address of
the instruction that was executed immediately after the
instruction that caused the event.
Use IA32_PMC0 only.
CBH
10H
MEM_LOAD_
RETIRED.DTLB_
MISS
Retired loads that miss This event counts the number of retired loads that missed
the DTLB (precise
the DTLB. The DTLB miss is not counted if the load
event).
operation causes a fault.
This event counts loads from cacheable memory only. The
event does not count loads by software prefetches.
When this event is captured with the precise event
mechanism, the collected samples contain the address of
the instruction that was executed immediately after the
instruction that caused the event.
Use IA32_PMC0 only.
CCH
01H
FP_MMX_TRANS_TO_MMX Transitions from
This event counts the first MMX instructions following a
Floating Point to MMX floating-point instruction. Use this event to estimate the
Instructions.
penalties for the transitions between floating-point and
MMX states.
CCH
02H
FP_MMX_TRANS_TO_FP
Transitions from MMX
Instructions to
Floating Point
Instructions.
This event counts the first floating-point instructions
following any MMX instruction. Use this event to estimate
the penalties for the transitions between floating-point and
MMX states.
Vol. 3B 19-139
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
CDH
00H
SIMD_ASSIST
SIMD assists invoked.
This event counts the number of SIMD assists invoked. SIMD
assists are invoked when an EMMS instruction is executed,
changing the MMX state in the floating point stack.
CEH
00H
SIMD_INSTR_
RETIRED
SIMD Instructions
retired.
This event counts the number of retired SIMD instructions
that use MMX registers.
CFH
00H
SIMD_SAT_INSTR_RETIRED Saturated arithmetic
instructions retired.
This event counts the number of saturated arithmetic SIMD
instructions that retired.
D2H
01H
RAT_STALLS.
ROB_READ_PORT
This event counts the number of cycles when ROB read port
stalls occurred, which did not allow new micro-ops to enter
the out-of-order pipeline.
ROB read port stalls
cycles.
Description and
Comment
Note that, at this stage in the pipeline, additional stalls may
occur at the same cycle and prevent the stalled micro-ops
from entering the pipe. In such a case, micro-ops retry
entering the execution pipe in the next cycle and the ROBread-port stall is counted again.
D2H
02H
RAT_STALLS.
PARTIAL_CYCLES
Partial register stall
cycles.
This event counts the number of cycles instruction
execution latency became longer than the defined latency
because the instruction uses a register that was partially
written by previous instructions.
D2H
04H
RAT_STALLS.
FLAGS
Flag stall cycles.
This event counts the number of cycles during which
execution stalled due to several reasons, one of which is a
partial flag register stall.
A partial register stall may occur when two conditions are
met:
• An instruction modifies some, but not all, of the flags in
the flag register.
• The next instruction, which depends on flags, depends on
flags that were not modified by this instruction.
D2H
08H
RAT_STALLS.
FPSW
FPU status word stall.
This event indicates that the FPU status word (FPSW) is
written. To obtain the number of times the FPSW is written
divide the event count by 2.
The FPSW is written by instructions with long latency; a
small count may indicate a high penalty.
D2H
0FH
RAT_STALLS.
ANY
All RAT stall cycles.
This event counts the number of stall cycles due to
conditions described by:
•
•
•
•
RAT_STALLS.ROB_READ_PORT
RAT_STALLS.PARTIAL
RAT_STALLS.FLAGS
RAT_STALLS.FPSW.
D4H
01H
SEG_RENAME_
STALLS.ES
Segment rename stalls This event counts the number of stalls due to the lack of
- ES.
renaming resources for the ES segment register. If a
segment is renamed, but not retired and a second update to
the same segment occurs, a stall occurs in the front end of
the pipeline until the renamed segment retires.
D4H
02H
SEG_RENAME_
STALLS.DS
Segment rename stalls This event counts the number of stalls due to the lack of
- DS.
renaming resources for the DS segment register. If a
segment is renamed, but not retired and a second update to
the same segment occurs, a stall occurs in the front end of
the pipeline until the renamed segment retires.
19-140 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
D4H
04H
Description and
Comment
Event Name
Definition
SEG_RENAME_
STALLS.FS
Segment rename stalls This event counts the number of stalls due to the lack of
- FS.
renaming resources for the FS segment register.
If a segment is renamed, but not retired and a second
update to the same segment occurs, a stall occurs in the
front end of the pipeline until the renamed segment retires.
D4H
08H
SEG_RENAME_
STALLS.GS
Segment rename stalls This event counts the number of stalls due to the lack of
- GS.
renaming resources for the GS segment register.
If a segment is renamed, but not retired and a second
update to the same segment occurs, a stall occurs in the
front end of the pipeline until the renamed segment retires.
D4H
0FH
SEG_RENAME_
STALLS.ANY
Any (ES/DS/FS/GS)
This event counts the number of stalls due to the lack of
segment rename stall. renaming resources for the ES, DS, FS, and GS segment
registers.
If a segment is renamed but not retired and a second update
to the same segment occurs, a stall occurs in the front end
of the pipeline until the renamed segment retires.
D5H
01H
SEG_REG_
RENAMES.ES
Segment renames ES.
This event counts the number of times the ES segment
register is renamed.
D5H
02H
SEG_REG_
RENAMES.DS
Segment renames DS.
This event counts the number of times the DS segment
register is renamed.
D5H
04H
SEG_REG_
RENAMES.FS
Segment renames FS.
This event counts the number of times the FS segment
register is renamed.
D5H
08H
SEG_REG_
RENAMES.GS
Segment renames GS.
This event counts the number of times the GS segment
register is renamed.
D5H
0FH
SEG_REG_
RENAMES.ANY
Any (ES/DS/FS/GS)
segment rename.
This event counts the number of times any of the four
segment registers (ES/DS/FS/GS) is renamed.
DCH
01H
RESOURCE_
STALLS.ROB_FULL
Cycles during which
the ROB full.
This event counts the number of cycles when the number of
instructions in the pipeline waiting for retirement reaches
the limit the processor can handle.
A high count for this event indicates that there are long
latency operations in the pipe (possibly load and store
operations that miss the L2 cache, and other instructions
that depend on these cannot execute until the former
instructions complete execution). In this situation new
instructions cannot enter the pipe and start execution.
DCH
02H
RESOURCE_
STALLS.RS_FULL
Cycles during which
the RS full.
This event counts the number of cycles when the number of
instructions in the pipeline waiting for execution reaches
the limit the processor can handle.
A high count of this event indicates that there are long
latency operations in the pipe (possibly load and store
operations that miss the L2 cache, and other instructions
that depend on these cannot execute until the former
instructions complete execution). In this situation new
instructions cannot enter the pipe and start execution.
Vol. 3B 19-141
PERFORMANCE-MONITORING EVENTS
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
DCH
Description and
Comment
Event Name
Definition
04
RESOURCE_
STALLS.LD_ST
Cycles during which
This event counts the number of cycles while resourcethe pipeline has
related stalls occur due to:
exceeded load or store • The number of load instructions in the pipeline reached
limit or waiting to
the limit the processor can handle. The stall ends when a
commit all stores.
loading instruction retires.
• The number of store instructions in the pipeline reached
the limit the processor can handle. The stall ends when a
storing instruction commits its data to the cache or
memory.
• There is an instruction in the pipe that can be executed
only when all previous stores complete and their data is
committed in the caches or memory. For example, the
SFENCE and MFENCE instructions require this behavior.
DCH
08H
RESOURCE_
STALLS.FPCW
Cycles stalled due to
FPU control word
write.
This event counts the number of cycles while execution was
stalled due to writing the floating-point unit (FPU) control
word.
DCH
10H
RESOURCE_
STALLS.BR_MISS_CLEAR
Cycles stalled due to
branch misprediction.
This event counts the number of cycles after a branch
misprediction is detected at execution until the branch and
all older micro-ops retire. During this time new micro-ops
cannot enter the out-of-order pipeline.
DCH
1FH
RESOURCE_
STALLS.ANY
Resource related
stalls.
This event counts the number of cycles while resourcerelated stalls occurs for any conditions described by the
following events:
•
•
•
•
•
RESOURCE_STALLS.ROB_FULL
RESOURCE_STALLS.RS_FULL
RESOURCE_STALLS.LD_ST
RESOURCE_STALLS.FPCW
RESOURCE_STALLS.BR_MISS_CLEAR
E0H
00H
BR_INST_
DECODED
Branch instructions
decoded.
This event counts the number of branch instructions
decoded.
E4H
00H
BOGUS_BR
Bogus branches.
This event counts the number of byte sequences that were
mistakenly detected as taken branch instructions.
This results in a BACLEAR event. This occurs mainly after
task switches.
E6H
00H
BACLEARS
BACLEARS asserted.
This event counts the number of times the front end is
resteered, mainly when the BPU cannot provide a correct
prediction and this is corrected by other branch handling
mechanisms at the front and. This can occur if the code has
many branches such that they cannot be consumed by the
BPU.
Each BACLEAR asserted costs approximately 7 cycles of
instruction fetch. The effect on total execution time
depends on the surrounding code.
This event counts the number of upward prefetches issued
from the Data Prefetch Logic (DPL) to the L2 cache. A
prefetch request issued to the L2 cache cannot be cancelled
and the requested cache line is fetched to the L2 cache.
F0H
00H
PREF_RQSTS_UP
Upward prefetches
issued from DPL.
F8H
00H
PREF_RQSTS_DN
Downward prefetches This event counts the number of downward prefetches
issued from DPL.
issued from the Data Prefetch Logic (DPL) to the L2 cache. A
prefetch request issued to the L2 cache cannot be cancelled
and the requested cache line is fetched to the L2 cache.
19-142 Vol. 3B
PERFORMANCE-MONITORING EVENTS
19.11
PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON THE
GOLDMONT MICROARCHITECTURE
Next Generation Intel Atom processors based on the Goldmont microarchitecture support the architectural performance-monitoring events listed in Table 19-1 and fixed-function performance events using a fixed counter. In addition, they also support the following non-architectural performance-monitoring events listed in Table 19-24. These
events also apply to processors with CPUID signatures of 06_5CH and 06_5FH.
Performance monitoring event descriptions may refer to terminology described in Section B.2, “Intel® Xeon®
processor 5500 Series,” in Appendix B of the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
In Goldmont microarchitecture, performance monitoring events that support Processor Event Based Sampling
(PEBS) and PEBS records that contain processor state information that are associated with at-retirement tagging
are marked by “Precise Event”.
Table 19-24. Non-Architectural Performance Events for the Goldmont Microarchitecture
Event
Num.
Umask
Value
Event Name
03H
10H
LD_BLOCKS.ALL_BLOCK Counts anytime a load that retires is blocked for any reason.
Precise Event
03H
08H
LD_BLOCKS.UTLB_MISS Counts loads blocked because they are unable to find their physical
address in the micro TLB (UTLB).
Precise Event
03H
02H
LD_BLOCKS.STORE_FO
RWARD
Counts a load blocked from using a store forward because of an
address/size mismatch; only one of the loads blocked from each store
will be counted.
Precise Event
03H
01H
LD_BLOCKS.DATA_UNK
NOWN
Counts a load blocked from using a store forward, but did not occur
Precise Event
because the store data was not available at the right time. The forward
might occur subsequently when the data is available.
03H
04H
LD_BLOCKS.4K_ALIAS
Counts loads that block because their address modulo 4K matches a
pending store.
05H
01H
PAGE_WALKS.D_SIDE_C Counts every core cycle when a Data-side (walks due to data operation)
YCLES
page walk is in progress.
05H
02H
PAGE_WALKS.I_SIDE_CY Counts every core cycle when an Instruction-side (walks due to an
CLES
instruction fetch) page walk is in progress.
05H
03H
PAGE_WALKS.CYCLES
Counts every core cycle a page-walk is in progress due to either a data
memory operation, or an instruction fetch.
0EH
00H
UOPS_ISSUED.ANY
Counts uops issued by the front end and allocated into the back end of
the machine. This event counts uops that retire as well as uops that
were speculatively executed but didn't retire. The sort of speculative
uops that might be counted includes, but is not limited to those uops
issued in the shadow of a mispredicted branch, those uops that are
inserted during an assist (such as for a denormal floating-point result),
and (previously allocated) uops that might be canceled during a
machine clear.
13H
02H
MISALIGN_MEM_REF.LO Counts when a memory load of a uop that spans a page boundary (a
AD_PAGE_SPLIT
split) is retired.
Precise Event
13H
04H
MISALIGN_MEM_REF.ST Counts when a memory store of a uop that spans a page boundary (a
ORE_PAGE_SPLIT
split) is retired.
Precise Event
2EH
4FH
LONGEST_LAT_CACHE.
REFERENCE
Counts memory requests originating from the core that reference a
cache line in the L2 cache.
2EH
41H
LONGEST_LAT_CACHE.
MISS
Counts memory requests originating from the core that miss in the L2
cache.
Description
Comment
Precise Event
Vol. 3B 19-143
PERFORMANCE-MONITORING EVENTS
Table 19-24. Non-Architectural Performance Events for the Goldmont Microarchitecture (Contd.)
Event
Num.
Umask
Value
Event Name
Description
30H
00H
L2_REJECT_XQ.ALL
Counts the number of demand and prefetch transactions that the L2
XQ rejects due to a full or near full condition which likely indicates back
pressure from the intra-die interconnect (IDI) fabric. The XQ may reject
transactions from the L2Q (non-cacheable requests), L2 misses and L2
write-back victims.
31H
00H
CORE_REJECT_L2Q.ALL
Counts the number of demand and L1 prefetcher requests rejected by
the L2Q due to a full or nearly full condition which likely indicates back
pressure from L2Q. It also counts requests that would have gone
directly to the XQ, but are rejected due to a full or nearly full condition,
indicating back pressure from the IDI link. The L2Q may also reject
transactions from a core to ensure fairness between cores, or to delay
a core's dirty eviction when the address conflicts with incoming
external snoops.
3CH
00H
CPU_CLK_UNHALTED.C
ORE_P
Core cycles when core is not halted. This event uses a programmable
general purpose performance counter.
3CH
01H
CPU_CLK_UNHALTED.R
EF
Reference cycles when core is not halted. This event uses a
programmable general purpose performance counter.
51H
01H
DL1.DIRTY_EVICTION
Counts when a modified (dirty) cache line is evicted from the data L1
cache and needs to be written back to memory. No count will occur if
the evicted line is clean, and hence does not require a writeback.
80H
01H
ICACHE.HIT
Counts requests to the Instruction Cache (ICache) for one or more
bytes in an ICache Line and that cache line is in the Icache (hit). The
event strives to count on a cache line basis, so that multiple accesses
which hit in a single cache line count as one ICACHE.HIT. Specifically, the
event counts when straight line code crosses the cache line boundary,
or when a branch target is to a new line, and that cache line is in the
ICache. This event counts differently than Intel processors based on
the Silvermont microarchitecture.
80H
02H
ICACHE.MISSES
Counts requests to the Instruction Cache (ICache) for one or more
bytes in an ICache Line and that cache line is not in the Icache (miss).
The event strives to count on a cache line basis, so that multiple
accesses which miss in a single cache line count as one ICACHE.MISS.
Specifically, the event counts when straight line code crosses the cache
line boundary, or when a branch target is to a new line, and that cache
line is not in the ICache. This event counts differently than Intel
processors based on the Silvermont microarchitecture.
80H
03H
ICACHE.ACCESSES
Counts requests to the Instruction Cache (ICache) for one or more
bytes in an ICache Line. The event strives to count on a cache line basis,
so that multiple fetches to a single cache line count as one
ICACHE.ACCESS. Specifically, the event counts when accesses from
straight line code crosses the cache line boundary, or when a branch
target is to a new line. This event counts differently than Intel
processors based on the Silvermont microarchitecture.
81H
04H
ITLB.MISS
Counts the number of times the machine was unable to find a
translation in the Instruction Translation Lookaside Buffer (ITLB) for a
linear address of an instruction fetch. It counts when new translations
are filled into the ITLB. The event is speculative in nature, but will not
count translations (page walks) that are begun and not finished, or
translations that are finished but not filled into the ITLB.
19-144 Vol. 3B
Comment
PERFORMANCE-MONITORING EVENTS
Table 19-24. Non-Architectural Performance Events for the Goldmont Microarchitecture (Contd.)
Event
Num.
Umask
Value
86H
02H
FETCH_STALL.ICACHE_F Counts cycles that an ICache miss is outstanding, and instruction fetch
ILL_PENDING_CYCLES
is stalled. That is, the decoder queue is able to accept bytes, but the
fetch unit is unable to provide bytes, while an Icache miss is
outstanding. Note this event is not the same as cycles to retrieve an
instruction due to an Icache miss. Rather, it is the part of the
Instruction Cache (ICache) miss time where no bytes are available for
the decoder.
9CH
00H
UOPS_NOT_DELIVERED. This event is used to measure front-end inefficiencies, i.e., when the
ANY
front end of the machine is not delivering uops to the back end and the
back end has not stalled. This event can be used to identify if the
machine is truly front-end bound. When this event occurs, it is an
indication that the front end of the machine is operating at less than its
theoretical peak performance.
Event Name
Description
Comment
Background: We can think of the processor pipeline as being divided
into 2 broader parts: the front end and the back end. The front end is
responsible for fetching the instruction, decoding into uops in machine
understandable format and putting them into a uop queue to be
consumed by the back end. The back end then takes these uops and
allocates the required resources. When all resources are ready, uops are
executed. If the back end is not ready to accept uops from the front
end, then we do not want to count these as front-end bottlenecks.
However, whenever we have bottlenecks in the back end, we will have
allocation unit stalls and eventually force the front end to wait until the
back end is ready to receive more uops. This event counts only when
the back end is requesting more micro-uops and the front end is not
able to provide them. When 3 uops are requested and no uops are
delivered, the event counts 3. When 3 are requested, and only 1 is
delivered, the event counts 2. When only 2 are delivered, the event
counts 1. Alternatively stated, the event will not count if 3 uops are
delivered, or if the back end is stalled and not requesting any uops at
all. Counts indicate missed opportunities for the front end to deliver a
uop to the back end. Some examples of conditions that cause front-end
efficiencies are: Icache misses, ITLB misses, and decoder restrictions
that limit the front-end bandwidth.
Known Issues: Some uops require multiple allocation slots. These uops
will not be charged as a front end 'not delivered' opportunity, and will
be regarded as a back-end problem. For example, the INC instruction
has one uop that requires 2 issue slots. A stream of INC instructions will
not count as UOPS_NOT_DELIVERED, even though only one instruction
can be issued per clock. The low uop issue rate for a stream of INC
instructions is considered to be a back-end issue.
B7H
01H,
02H
OFFCORE_RESPONSE
Requires MSR_OFFCORE_RESP[0,1] to specify request type and
response. (Duplicated for both MSRs.)
C0H
00H
INST_RETIRED.ANY_P
Counts the number of instructions that retire execution. For
Precise Event
instructions that consist of multiple uops, this event counts the
retirement of the last uop of the instruction. The event continues
counting during hardware interrupts, traps, and inside interrupt
handlers. This is an architectural performance event. This event uses a
programmable general purpose performance counter. *This event is a
Precise Event: the EventingRIP field in the PEBS record is precise to the
address of the instruction which caused the event.
Note: Because PEBS records can be collected only on IA32_PMC0, only
one event can use the PEBS facility at a time.
Vol. 3B 19-145
PERFORMANCE-MONITORING EVENTS
Table 19-24. Non-Architectural Performance Events for the Goldmont Microarchitecture (Contd.)
Event
Num.
Umask
Value
Event Name
Description
Comment
C2H
00H
UOPS_RETIRED.ANY
Counts uops which have retired.
Precise Event
C2H
01H
UOPS_RETIRED.MS
Counts uops retired that are from the complex flows issued by the
micro-sequencer (MS). Counts both the uops from a micro-coded
instruction, and the uops that might be generated from a micro-coded
assist.
Precise Event
C3H
01H
MACHINE_CLEARS.SMC
Counts the number of times that the processor detects that a program
is writing to a code section and has to perform a machine clear because
of that modification. Self-modifying code (SMC) causes a severe penalty
in all Intel architecture processors.
C3H
02H
MACHINE_CLEARS.MEM Counts machine clears due to memory ordering issues. This occurs
ORY_ORDERING
when a snoop request happens and the machine is uncertain if memory
ordering will be preserved as another core is in the process of
modifying the data.
C3H
04H
MACHINE_CLEARS.FP_A Counts machine clears due to floating-point (FP) operations needing
SSIST
assists. For instance, if the result was a floating-point denormal, the
hardware clears the pipeline and reissues uops to produce the correct
IEEE compliant denormal result.
C3H
08H
MACHINE_CLEARS.DISA Counts machine clears due to memory disambiguation. Memory
MBIGUATION
disambiguation happens when a load which has been issued conflicts
with a previous un-retired store in the pipeline whose address was not
known at issue time, but is later resolved to be the same as the load
address.
C3H
00H
MACHINE_CLEARS.ALL
C4H
00H
BR_INST_RETIRED.ALL_ Counts branch instructions retired for all branch types. This is an
BRANCHES
architectural performance event.
Precise Event
C4H
7EH
BR_INST_RETIRED.JCC
Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met)
branch instructions retired, including both when the branch was taken
and when it was not taken.
Precise Event
C4H
FEH
BR_INST_RETIRED.TAK
EN_JCC
Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch
instructions retired that were taken and does not count when the Jcc
branch instruction were not taken.
Precise Event
Counts machine clears for any reason.
C4H
F9H
BR_INST_RETIRED.CALL Counts near CALL branch instructions retired.
Precise Event
C4H
FDH
BR_INST_RETIRED.REL_ Counts near relative CALL branch instructions retired.
CALL
Precise Event
C4H
FBH
BR_INST_RETIRED.IND_ Counts near indirect CALL branch instructions retired.
CALL
Precise Event
C4H
F7H
BR_INST_RETIRED.RET
URN
Precise Event
C4H
EBH
BR_INST_RETIRED.NON Counts near indirect call or near indirect jmp branch instructions retired. Precise Event
_RETURN_IND
C4H
BFH
BR_INST_RETIRED.FAR
_BRANCH
Counts far branch instructions retired. This includes far jump, far call
and return, and Interrupt call and return.
Precise Event
C5H
00H
BR_MISP_RETIRED.ALL
_BRANCHES
Counts mispredicted branch instructions retired including all branch
types.
Precise Event
C5H
7EH
BR_MISP_RETIRED.JCC
Precise Event
Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if
Condition is Met) branch instructions retired, including both when the
branch was supposed to be taken and when it was not supposed to be
taken (but the processor predicted the opposite condition).
19-146 Vol. 3B
Counts near return branch instructions retired.
PERFORMANCE-MONITORING EVENTS
Table 19-24. Non-Architectural Performance Events for the Goldmont Microarchitecture (Contd.)
Event
Num.
Umask
Value
Event Name
Description
Comment
C5H
FEH
BR_MISP_RETIRED.TAK
EN_JCC
Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if
Condition is Met) branch instructions retired that were supposed to be
taken but the processor predicted that it would not be taken.
Precise Event
C5H
FBH
BR_MISP_RETIRED.IND_ Counts mispredicted near indirect CALL branch instructions retired,
Precise Event
CALL
where the target address taken was not what the processor predicted.
C5H
F7H
BR_MISP_RETIRED.RET
URN
C5H
EBH
BR_MISP_RETIRED.NON Counts mispredicted branch instructions retired that were near indirect Precise Event
_RETURN_IND
call or near indirect jmp, where the target address taken was not what
the processor predicted.
CAH
01H
ISSUE_SLOTS_NOT_CO Counts the number of issue slots per core cycle that were not
NSUMED.RESOURCE_FU consumed because of a full resource in the back end. Including but not
LL
limited to resources include the Re-order Buffer (ROB), reservation
stations (RS), load/store buffers, physical registers, or any other
needed machine resource that is currently unavailable. Note that uops
must be available for consumption in order for this event to fire. If a
uop is not available (Instruction Queue is empty), this event will not
count.
CAH
02H
ISSUE_SLOTS_NOT_CO
NSUMED.RECOVERY
Counts the number of issue slots per core cycle that were not
consumed by the back end because allocation is stalled waiting for a
mispredicted jump to retire or other branch-like conditions (e.g. the
event is relevant during certain microcode flows). Counts all issue slots
blocked while within this window, including slots where uops were not
available in the Instruction Queue.
CAH
00H
ISSUE_SLOTS_NOT_CO
NSUMED.ANY
Counts the number of issue slots per core cycle that were not
consumed by the back end due to either a full resource in the back end
(RESOURCE_FULL), or due to the processor recovering from some
event (RECOVERY).
CBH
01H
HW_INTERRUPTS.RECEI Counts hardware interrupts received by the processor.
VED
CBH
04H
HW_INTERRUPTS.PENDI Counts core cycles during which there are pending interrupts, but
NG_AND_MASKED
interrupts are masked (EFLAGS.IF = 0).
CDH
00H
CYCLES_DIV_BUSY.ALL
Counts core cycles if either divide unit is busy.
CDH
01H
CYCLES_DIV_BUSY.IDIV
Counts core cycles if the integer divide unit is busy.
CDH
02H
CYCLES_DIV_BUSY.FPDI Counts core cycles if the floating point divide unit is busy.
V
D0H
81H
MEM_UOPS_RETIRED.A
LL_LOADS
Counts the number of load uops retired.
Precise Event
D0H
82H
MEM_UOPS_RETIRED.A
LL_STORES
Counts the number of store uops retired.
Precise Event
D0H
83H
MEM_UOPS_RETIRED.A
LL
Counts the number of memory uops retired that are either a load or a
store or both.
Precise Event
D0H
11H
MEM_UOPS_RETIRED.D
TLB_MISS_LOADS
Counts load uops retired that caused a DTLB miss.
Precise Event
D0H
12H
MEM_UOPS_RETIRED.D
TLB_MISS_STORES
Counts store uops retired that caused a DTLB miss.
Precise Event
Counts mispredicted near RET branch instructions retired, where the
return address taken was not what the processor predicted.
Precise Event
Vol. 3B 19-147
PERFORMANCE-MONITORING EVENTS
Table 19-24. Non-Architectural Performance Events for the Goldmont Microarchitecture (Contd.)
Event
Num.
Umask
Value
D0H
13H
Event Name
Description
Comment
MEM_UOPS_RETIRED.D
TLB_MISS
Counts uops retired that had a DTLB miss on load, store or either.
Precise Event
Note that when two distinct memory operations to the same page miss
the DTLB, only one of them will be recorded as a DTLB miss.
D0H
21H
MEM_UOPS_RETIRED.L
OCK_LOADS
Counts locked memory uops retired. This includes 'regular' locks and
Precise Event
bus locks. To specifically count bus locks only, see the offcore response
event. A locked access is one with a lock prefix, or an exchange to
memory.
D0H
41H
MEM_UOPS_RETIRED.S
PLIT_LOADS
Counts load uops retired where the data requested spans a 64 byte
cache line boundary.
Precise Event
D0H
42H
MEM_UOPS_RETIRED.S
PLIT_STORES
Counts store uops retired where the data requested spans a 64 byte
cache line boundary.
Precise Event
D0H
43H
MEM_UOPS_RETIRED.S
PLIT
Counts memory uops retired where the data requested spans a 64
byte cache line boundary.
Precise Event
D1H
01H
MEM_LOAD_UOPS_RETI Counts load uops retired that hit the L1 data cache.
RED.L1_HIT
Precise Event
D1H
08H
MEM_LOAD_UOPS_RETI Counts load uops retired that miss the L1 data cache.
RED.L1_MISS
Precise Event
D1H
02H
MEM_LOAD_UOPS_RETI Counts load uops retired that hit in the L2 cache.
RED.L2_HIT
Precise Event
0xD1H
10H
MEM_LOAD_UOPS_RETI Counts load uops retired that miss in the L2 cache.
RED.L2_MISS
Precise Event
D1H
20H
MEM_LOAD_UOPS_RETI Counts load uops retired where the cache line containing the data was Precise Event
RED.HITM
in the modified state of another core or modules cache (HITM). More
specifically, this means that when the load address was checked by
other caching agents (typically another processor) in the system, one
of those caching agents indicated that they had a dirty copy of the
data. Loads that obtain a HITM response incur greater latency than
most that is typical for a load. In addition, since HITM indicates that
some other processor had this data in its cache, it implies that the data
was shared between processors, or potentially was a lock or
semaphore value. This event is useful for locating sharing, false
sharing, and contended locks.
D1H
40H
MEM_LOAD_UOPS_RETI Counts memory load uops retired where the data is retrieved from the Precise Event
RED.WCB_HIT
WCB (or fill buffer), indicating that the load found its data while that
data was in the process of being brought into the L1 cache. Typically a
load will receive this indication when some other load or prefetch
missed the L1 cache and was in the process of retrieving the cache line
containing the data, but that process had not yet finished (and written
the data back to the cache). For example, consider load X and Y, both
referencing the same cache line that is not in the L1 cache. If load X
misses cache first, it obtains and WCB (or fill buffer) begins the process
of requesting the data. When load Y requests the data, it will either hit
the WCB, or the L1 cache, depending on exactly what time the request
to Y occurs.
D1H
80H
Precise Event
MEM_LOAD_UOPS_RETI Counts memory load uops retired where the data is retrieved from
RED.DRAM_HIT
DRAM. Event is counted at retirement, so the speculative loads are
ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the
L2 cache, hit DRAM, hit in the WCB or receive a HITM response.
19-148 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-24. Non-Architectural Performance Events for the Goldmont Microarchitecture (Contd.)
Event
Num.
Umask
Value
Event Name
Description
E6H
01H
BACLEARS.ALL
Counts the number of times a BACLEAR is signaled for any reason,
including, but not limited to indirect branch/call, Jcc (Jump on Conditional
Code/Jump if Condition is Met) branch, unconditional branch/call, and
returns.
E6H
08H
BACLEARS.RETURN
Counts BACLEARS on return instructions.
E6H
10H
BACLEARS.COND
Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is
Met) branches.
E7H
01H
MS_DECODED.MS_ENTR Counts the number of times the Microcode Sequencer (MS) starts a
Y
flow of uops from the MSROM. It does not count every time a uop is
read from the MSROM. The most common case that this counts is when
a micro-coded instruction is encountered by the front end of the
machine. Other cases include when an instruction encounters a fault,
trap, or microcode assist of any sort that initiates a flow of uops. The
event will count MS startups for uops that are speculative, and
subsequently cleared by branch mispredict or a machine clear.
E9H
01H
DECODE_RESTRICTION.
PREDECODE_WRONG
19.12
Comment
Counts the number of times the prediction (from the pre-decode cache)
for instruction length is incorrect.
PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON THE
SILVERMONT MICROARCHITECTURE
Processors based on the Silvermont microarchitecture support the architectural performance-monitoring events
listed in Table 19-1 and fixed-function performance events using fixed counter. In addition, they also support the
following non-architectural performance-monitoring events listed in Table 19-25. These processors have the CPUID
signatures of 06_37H, 06_4AH, 06_4DH, 06_5AH, and 06_5DH.
Performance monitoring event descriptions may refer to terminology described in Section B.2, “Intel® Xeon®
processor 5500 Series,” in Appendix B of the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
Table 19-25. Performance Events for Silvermont Microarchitecture
Event
Num.
Umask
Value
03H
Event Name
Definition
Description and Comment
01H
REHABQ.LD_BLOCK_S
T_FORWARD
Loads blocked due to
store forward
restriction.
This event counts the number of retired loads that were
prohibited from receiving forwarded data from the store
because of address mismatch.
03H
02H
REHABQ.LD_BLOCK_S
TD_NOTREADY
Loads blocked due to
store data not ready.
This event counts the cases where a forward was technically
possible, but did not occur because the store data was not
available at the right time.
03H
04H
REHABQ.ST_SPLITS
Store uops that split
cache line boundary.
This event counts the number of retire stores that experienced
cache line boundary splits.
03H
08H
REHABQ.LD_SPLITS
Load uops that split
cache line boundary.
This event counts the number of retire loads that experienced
cache line boundary splits.
03H
10H
REHABQ.LOCK
Uops with lock
semantics.
This event counts the number of retired memory operations
with lock semantics. These are either implicit locked instructions
such as the XCHG instruction or instructions with an explicit
LOCK prefix (F0H).
03H
20H
REHABQ.STA_FULL
Store address buffer
full.
This event counts the number of retired stores that are delayed
because there is not a store address buffer available.
Vol. 3B 19-149
PERFORMANCE-MONITORING EVENTS
Table 19-25. Performance Events for Silvermont Microarchitecture
Event
Num.
Umask
Value
Event Name
Definition
03H
40H
REHABQ.ANY_LD
Any reissued load uops. This event counts the number of load uops reissued from
Rehabq.
03H
80H
REHABQ.ANY_ST
Any reissued store
uops.
04H
01H
MEM_UOPS_RETIRED.L Loads retired that
1_MISS_LOADS
missed L1 data cache.
This event counts the number of load ops retired that miss in L1
Data cache. Note that prefetch misses will not be counted.
04H
02H
MEM_UOPS_RETIRED.L Loads retired that hit
2_HIT_LOADS
L2.
This event counts the number of load micro-ops retired that hit
L2.
04H
04H
MEM_UOPS_RETIRED.L Loads retired that
2_MISS_LOADS
missed L2.
This event counts the number of load micro-ops retired that
missed L2.
04H
08H
MEM_UOPS_RETIRED.
DTLB_MISS_LOADS
Loads missed DTLB.
This event counts the number of load ops retired that had DTLB
miss.
04H
10H
MEM_UOPS_RETIRED.
UTLB_MISS
Loads missed UTLB.
This event counts the number of load ops retired that had UTLB
miss.
04H
20H
MEM_UOPS_RETIRED.
HITM
Cross core or cross
module hitm.
This event counts the number of load ops retired that got data
from the other core or from the other module.
04H
40H
MEM_UOPS_RETIRED.
ALL_LOADS
All Loads.
This event counts the number of load ops retired.
04H
80H
MEM_UOP_RETIRED.A
LL_STORES
All Stores.
This event counts the number of store ops retired.
05H
01H
PAGE_WALKS.D_SIDE_
CYCLES
Duration of D-side
page-walks in core
cycles.
This event counts every cycle when a D-side (walks due to a
load) page walk is in progress. Page walk duration divided by
number of page walks is the average duration of page-walks.
Description and Comment
This event counts the number of store uops reissued from
Rehabq.
Edge trigger bit must be cleared. Set Edge to count the number
of page walks.
05H
02H
PAGE_WALKS.I_SIDE_C Duration of I-side page- This event counts every cycle when an I-side (walks due to an
YCLES
walks in core cycles.
instruction fetch) page walk is in progress. Page walk duration
divided by number of page walks is the average duration of
page-walks.
Edge trigger bit must be cleared. Set Edge to count the number
of page walks.
05H
03H
PAGE_WALKS.WALKS
Total number of pagewalks that are
completed (I-side and
D-side).
This event counts when a data (D) page walk or an instruction (I)
page walk is completed or started. Since a page walk implies a
TLB miss, the number of TLB misses can be counted by counting
the number of pagewalks.
Edge trigger bit must be set. Clear Edge to count the number of
cycles.
2EH
41H
LONGEST_LAT_CACHE. L2 cache request
MISS
misses.
This event counts the total number of L2 cache references and
the number of L2 cache misses respectively.
L3 is not supported in Silvermont microarchitecture.
2EH
4FH
LONGEST_LAT_CACHE. L2 cache requests
from this core.
REFERENCE
This event counts requests originating from the core that
references a cache line in the L2 cache.
L3 is not supported in Silvermont microarchitecture.
30H
00H
19-150 Vol. 3B
L2_REJECT_XQ.ALL
Counts the number of
request from the L2
that were not accepted
into the XQ.
This event counts the number of demand and prefetch
transactions that the L2 XQ rejects due to a full or near full
condition which likely indicates back pressure from the IDI link.
The XQ may reject transactions from the L2Q (non-cacheable
requests), BBS (L2 misses) and WOB (L2 write-back victims).
PERFORMANCE-MONITORING EVENTS
Table 19-25. Performance Events for Silvermont Microarchitecture
Event
Num.
Umask
Value
31H
00H
CORE_REJECT_L2Q.ALL Counts the number of
request that were not
accepted into the L2Q
because the L2Q is
FULL.
This event counts the number of demand and L1 prefetcher
requests rejected by the L2Q due to a full or nearly full condition
which likely indicates back pressure from L2Q. It also counts
requests that would have gone directly to the XQ, but are
rejected due to a full or nearly full condition, indicating back
pressure from the IDI link. The L2Q may also reject transactions
from a core to insure fairness between cores, or to delay a core's
dirty eviction when the address conflicts incoming external
snoops. (Note that L2 prefetcher requests that are dropped are
not counted by this event.).
3CH
00H
CPU_CLK_UNHALTED.C Core cycles when core
ORE_P
is not halted.
This event counts the number of core cycles while the core is not
in a halt state. The core enters the halt state when it is running
the HLT instruction. In mobile systems the core frequency may
change from time to time. For this reason this event may have a
changing ratio with regards to time.
N/A
N/A
CPU_CLK_UNHALTED.C Instructions retired.
ORE
This uses the fixed counter 1 to count the same condition as
CPU_CLK_UNHALTED.CORE_P does.
3CH
01H
CPU_CLK_UNHALTED.R Reference cycles when This event counts the number of reference cycles that the core
EF_P
core is not halted.
is not in a halt state. The core enters the halt state when it is
running the HLT instruction.
Event Name
Definition
Description and Comment
In mobile systems the core frequency may change from time.
This event is not affected by core frequency changes but counts
as if the core is running at the maximum frequency all the time.
N/A
N/A
CPU_CLK_UNHALTED.R Instructions retired.
EF_TSC
This uses the fixed counter 2 to count the same condition as
CPU_CLK_UNHALTED.REF_P does.
80H
01H
ICACHE.HIT
Instruction fetches
from Icache.
This event counts all instruction fetches from the instruction
cache.
80H
02H
ICACHE.MISSES
Icache miss.
This event counts all instruction fetches that miss the
Instruction cache or produce memory requests. This includes
uncacheable fetches. An instruction fetch miss is counted only
once and not once for every cycle it is outstanding.
80H
03H
ICACHE.ACCESSES
Instruction fetches.
This event counts all instruction fetches, including uncacheable
fetches.
B7H
01H
OFFCORE_RESPONSE_ See Section 18.6.2.
0
Requires MSR_OFFCORE_RESP0 to specify request type and
response.
B7H
02H
OFFCORE_RESPONSE_ See Section 18.6.2.
1
Requires MSR_OFFCORE_RESP1 to specify request type and
response.
C0H
00H
INST_RETIRED.ANY_P
Instructions retired
(PEBS supported with
IA32_PMC0).
This event counts the number of instructions that retire
execution. For instructions that consist of multiple micro-ops,
this event counts the retirement of the last micro-op of the
instruction. The counter continues counting during hardware
interrupts, traps, and inside interrupt handlers.
N/A
N/A
INST_RETIRED.ANY
Instructions retired.
This uses the fixed counter 0 to count the same condition as
INST_RETIRED.ANY_P does.
C2H
01H
UOPS_RETIRED.MS
MSROM micro-ops
retired.
This event counts the number of micro-ops retired that were
supplied from MSROM.
C2H
10H
UOPS_RETIRED.ALL
Micro-ops retired.
This event counts the number of micro-ops retired.
C3H
01H
MACHINE_CLEARS.SMC Self-Modifying Code
detected.
This event counts the number of times that a program writes to
a code section. Self-modifying code causes a severe penalty in all
Intel® architecture processors.
Vol. 3B 19-151
PERFORMANCE-MONITORING EVENTS
Table 19-25. Performance Events for Silvermont Microarchitecture
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
C3H
02H
MACHINE_CLEARS.ME
MORY_ORDERING
Stalls due to Memory
ordering.
This event counts the number of times that pipeline was cleared
due to memory ordering issues.
C3H
04H
MACHINE_CLEARS.FP_ Stalls due to FP assists. This event counts the number of times that pipeline stalled due
ASSIST
to FP operations needing assists.
C3H
08H
MACHINE_CLEARS.ALL Stalls due to any
causes.
This event counts the number of times that pipeline stalled due
to due to any causes (including SMC, MO, FP assist, etc.).
C4H
00H
BR_INST_RETIRED.ALL Retired branch
_BRANCHES
instructions.
This event counts the number of branch instructions retired.
C4H
7EH
BR_INST_RETIRED.JCC
This event counts the number of branch instructions retired that
were conditional jumps.
C4H
BFH
BR_INST_RETIRED.FAR Retired far branch
_BRANCH
instructions.
This event counts the number of far branch instructions retired.
C4H
EBH
BR_INST_RETIRED.NO
N_RETURN_IND
This event counts the number of branch instructions retired that
were near indirect call or near indirect jmp.
C4H
F7H
BR_INST_RETIRED.RET Retired near return
URN
instructions.
This event counts the number of near RET branch instructions
retired.
C4H
F9H
BR_INST_RETIRED.CAL Retired near call
L
instructions.
This event counts the number of near CALL branch instructions
retired.
C4H
FBH
BR_INST_RETIRED.IND Retired near indirect
_CALL
call instructions.
This event counts the number of near indirect CALL branch
instructions retired.
C4H
FDH
BR_INST_RETIRED.REL Retired near relative
_CALL
call instructions.
This event counts the number of near relative CALL branch
instructions retired.
C4H
FEH
BR_INST_RETIRED.TAK Retired conditional
EN_JCC
jumps that were
predicted taken.
This event counts the number of branch instructions retired that
were conditional jumps and predicted taken.
C5H
00H
BR_MISP_RETIRED.ALL Retired mispredicted
_BRANCHES
branch instructions.
This event counts the number of mispredicted branch
instructions retired.
C5H
7EH
BR_MISP_RETIRED.JCC
Retired mispredicted
conditional jumps.
This event counts the number of mispredicted branch
instructions retired that were conditional jumps.
C5H
BFH
BR_MISP_RETIRED.FA
R
Retired mispredicted
This event counts the number of mispredicted far branch
far branch instructions. instructions retired.
C5H
EBH
BR_MISP_RETIRED.NO
N_RETURN_IND
Retired mispredicted
instructions of near
indirect Jmp or call.
This event counts the number of mispredicted branch
instructions retired that were near indirect call or near indirect
jmp.
C5H
F7H
BR_MISP_RETIRED.RE
TURN
Retired mispredicted
near return
instructions.
This event counts the number of mispredicted near RET branch
instructions retired.
C5H
F9H
BR_MISP_RETIRED.CAL Retired mispredicted
L
near call instructions.
This event counts the number of mispredicted near CALL branch
instructions retired.
C5H
FBH
BR_MISP_RETIRED.IND Retired mispredicted
_CALL
near indirect call
instructions.
This event counts the number of mispredicted near indirect CALL
branch instructions retired.
C5H
FDH
BR_MISP_RETIRED.REL Retired mispredicted
_CALL
near relative call
instructions
This event counts the number of mispredicted near relative CALL
branch instructions retired.
19-152 Vol. 3B
Retired branch
instructions that were
conditional jumps.
Retired instructions of
near indirect Jmp or
call.
PERFORMANCE-MONITORING EVENTS
Table 19-25. Performance Events for Silvermont Microarchitecture
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
C5H
FEH
BR_MISP_RETIRED.TA
KEN_JCC
Retired mispredicted
conditional jumps that
were predicted taken.
This event counts the number of mispredicted branch
instructions retired that were conditional jumps and predicted
taken.
CAH
01H
NO_ALLOC_CYCLES.RO Counts the number of
B_FULL
cycles when no uops
are allocated and the
ROB is full (less than 2
entries available).
Counts the number of cycles when no uops are allocated and the
ROB is full (less than 2 entries available).
CAH
20H
NO_ALLOC_CYCLES.RA Counts the number of
T_STALL
cycles when no uops
are allocated and a
RATstall is asserted.
Counts the number of cycles when no uops are allocated and a
RATstall is asserted.
CAH
3FH
NO_ALLOC_CYCLES.AL
L
This event counts the number of cycles when the front end does
not provide any instructions to be allocated for any reason.
CAH
50H
NO_ALLOC_CYCLES.NO Front end not
This event counts the number of cycles when the front end does
T_DELIVERED
delivering back end not not provide any instructions to be allocated but the back end is
stalled.
not stalled.
CBH
01H
RS_FULL_STALL.MEC
MEC RS full.
This event counts the number of cycles the allocation pipe line
stalled due to the RS for the MEC cluster is full.
CBH
1FH
RS_FULL_STALL.ALL
Any RS full.
This event counts the number of cycles that the allocation pipe
line stalled due to any one of the RS is full.
CDH
01H
CYCLES_DIV_BUSY.AN
Y
Divider Busy.
This event counts the number of cycles the divider is busy.
E6H
01H
BACLEARS.ALL
BACLEARS asserted for This event counts the number of baclears for any type of branch.
any branch.
E6H
08H
BACLEARS.RETURN
BACLEARS asserted for This event counts the number of baclears for return branches.
return branch.
E6H
10H
BACLEARS.COND
BACLEARS asserted for This event counts the number of baclears for conditional
conditional branch.
branches.
E7H
01H
MS_DECODED.MS_ENT MS Decode starts.
RY
Front end not
delivering.
This event counts the number of times the MSROM starts a flow
of UOPS.
19.12.1 Performance Monitoring Events for Processors Based on the Airmont
Microarchitecture
Intel processors based on the Airmont microarchitecture support the same architectural and the non-architectural
performance monitoring events as processors based on the Silvermont microarchitecture. All of the events listed
in Table 19-25 apply. These processors have the CPUID signatures that include 06_4CH.
Vol. 3B 19-153
PERFORMANCE-MONITORING EVENTS
19.13
PERFORMANCE MONITORING EVENTS FOR 45 NM AND 32 NM
INTEL® ATOM™ PROCESSORS
45 nm and 32 nm processors based on the Intel® Atom™ microarchitecture support the architectural performancemonitoring events listed in Table 19-1 and fixed-function performance events using fixed counter listed in Table
19-22. In addition, they also support the following non-architectural performance-monitoring events listed in Table
19-26.
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors
Event
Num.
Umask
Value
02H
81H
STORe_FORWARDS.GO Good store forwards.
OD
This event counts the number of times store data was
forwarded directly to a load.
06H
00H
SEGMENT_REG_
LOADS.ANY
This event counts the number of segment register load
operations. Instructions that load new values into segment
registers cause a penalty. This event indicates performance
issues in 16-bit code. If this event occurs frequently, it may be
useful to calculate the number of instructions retired per
segment register load. If the resulting calculation is low (on
average a small number of instructions are executed between
segment register loads), then the code’s segment register
usage should be optimized.
Event Name
Definition
Number of segment
register loads.
Description and Comment
As a result of branch misprediction, this event is speculative and
may include segment register loads that do not actually occur.
However, most segment register loads are internally serialized
and such speculative effects are minimized.
07H
01H
PREFETCH.PREFETCHT Streaming SIMD
0
Extensions (SSE)
PrefetchT0
instructions executed.
This event counts the number of times the SSE instruction
prefetchT0 is executed. This instruction prefetches the data to
the L1 data cache and L2 cache.
07H
06H
PREFETCH.SW_L2
This event counts the number of times the SSE instructions
prefetchT1 and prefetchT2 are executed. These instructions
prefetch the data to the L2 cache.
07H
08H
PREFETCH.PREFETCHN Streaming SIMD
TA
Extensions (SSE)
Prefetch NTA
instructions executed.
This event counts the number of times the SSE instruction
prefetchNTA is executed. This instruction prefetches the data
to the L1 data cache.
08H
07H
DATA_TLB_MISSES.DT
LB_MISS
Memory accesses that
missed the DTLB.
This event counts the number of Data Table Lookaside Buffer
(DTLB) misses. The count includes misses detected as a result
of speculative accesses. Typically a high count for this event
indicates that the code accesses a large number of data pages.
08H
05H
DATA_TLB_MISSES.DT
LB_MISS_LD
DTLB misses due to
load operations.
This event counts the number of Data Table Lookaside Buffer
(DTLB) misses due to load operations. This count includes
misses detected as a result of speculative accesses.
08H
09H
DATA_TLB_MISSES.L0
_DTLB_MISS_LD
L0_DTLB misses due to This event counts the number of L0_DTLB misses due to load
load operations.
operations. This count includes misses detected as a result of
speculative accesses.
08H
06H
DATA_TLB_MISSES.DT
LB_MISS_ST
DTLB misses due to
store operations.
19-154 Vol. 3B
Streaming SIMD
Extensions (SSE)
PrefetchT1 and
PrefetchT2
instructions executed.
This event counts the number of Data Table Lookaside Buffer
(DTLB) misses due to store operations. This count includes
misses detected as a result of speculative accesses.
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
0CH
03H
PAGE_WALKS.WALKS
Number of page-walks
executed.
This event counts the number of page-walks executed due to
either a DTLB or ITLB miss. The page walk duration,
PAGE_WALKS.CYCLES, divided by number of page walks is the
average duration of a page walk. This can hint to whether most
of the page-walks are satisfied by the caches or cause an L2
cache miss.
0CH
03H
PAGE_WALKS.CYCLES
Duration of page-walks This event counts the duration of page-walks in core cycles. The
in core cycles.
paging mode in use typically affects the duration of page walks.
Page walk duration divided by number of page walks is the
average duration of page-walks. This can hint at whether most
of the page-walks are satisfied by the caches or cause an L2
cache miss.
Edge trigger bit must be set.
Edge trigger bit must be cleared.
10H
01H
X87_COMP_OPS_EXE.
ANY.S
Floating point
computational microops executed.
This event counts the number of x87 floating point
computational micro-ops executed.
10H
81H
X87_COMP_OPS_EXE.
ANY.AR
Floating point
computational microops retired.
This event counts the number of x87 floating point
computational micro-ops retired.
11H
01H
FP_ASSIST
Floating point assists.
This event counts the number of floating point operations
executed that required micro-code assist intervention. These
assists are required in the following cases.
X87 instructions:
1. NaN or denormal are loaded to a register or used as input
from memory.
2. Division by 0.
3. Underflow output.
11H
81H
FP_ASSIST.AR
Floating point assists.
This event counts the number of floating point operations
executed that required micro-code assist intervention. These
assists are required in the following cases.
X87 instructions:
1. NaN or denormal are loaded to a register or used as input
from memory.
2. Division by 0.
3. Underflow output.
12H
01H
MUL.S
Multiply operations
executed.
This event counts the number of multiply operations executed.
This includes integer as well as floating point multiply
operations.
12H
81H
MUL.AR
Multiply operations
retired.
This event counts the number of multiply operations retired.
This includes integer as well as floating point multiply
operations.
13H
01H
DIV.S
Divide operations
executed.
This event counts the number of divide operations executed.
This includes integer divides, floating point divides and squareroot operations executed.
13H
81H
DIV.AR
Divide operations
retired.
This event counts the number of divide operations retired. This
includes integer divides, floating point divides and square-root
operations executed.
Vol. 3B 19-155
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
14H
01H
CYCLES_DIV_BUSY
Cycles the driver is
busy.
This event counts the number of cycles the divider is busy
executing divide or square root operations. The divide can be
integer, X87 or Streaming SIMD Extensions (SSE). The square
root operation can be either X87 or SSE.
21H
See
Table
18-3
L2_ADS
Cycles L2 address bus
is in use.
This event counts the number of cycles the L2 address bus is
being used for accesses to the L2 cache or bus queue.
22H
See
Table
18-3
L2_DBUS_BUSY
Cycles the L2 cache
data bus is busy.
This event counts core cycles during which the L2 cache data
bus is busy transferring data from the L2 cache to the core. It
counts for all L1 cache misses (data and instruction) that hit the
L2 cache. The count will increment by two for a full cache-line
request.
24H
See
Table
18-3
and
Table
18-5
L2_LINES_IN
L2 cache misses.
This event counts the number of cache lines allocated in the L2
cache. Cache lines are allocated in the L2 cache as a result of
requests from the L1 data and instruction caches and the L2
hardware prefetchers to cache lines that are missing in the L2
cache.
See
Table
18-3
L2_M_LINES_IN
See
Table
18-3
and
Table
18-5
L2_LINES_OUT
See
Table
18-3
and
Table
18-5
L2_M_LINES_OUT
See
Table
18-3
and
Table
18-6
L2_IFETCH
25H
26H
27H
28H
19-156 Vol. 3B
This event can count occurrences for this core or both cores.
This event can count occurrences for this core or both cores.
This event can also count demand requests and L2 hardware
prefetch requests together or separately.
L2 cache line
modifications.
This event counts whenever a modified cache line is written
back from the L1 data cache to the L2 cache.
This event can count occurrences for this core or both cores.
L2 cache lines evicted.
This event counts the number of L2 cache lines evicted.
This event can count occurrences for this core or both cores.
This event can also count evictions due to demand requests and
L2 hardware prefetch requests together or separately.
Modified lines evicted
from the L2 cache.
This event counts the number of L2 modified cache lines
evicted. These lines are written back to memory unless they
also exist in a shared-state in one of the L1 data caches.
This event can count occurrences for this core or both cores.
This event can also count evictions due to demand requests and
L2 hardware prefetch requests together or separately.
L2 cacheable
instruction fetch
requests.
This event counts the number of instruction cache line requests
from the ICache. It does not include fetch requests from
uncacheable memory. It does not include ITLB miss accesses.
This event can count occurrences for this core or both cores.
This event can also count accesses to cache lines at different
MESI states.
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
29H
See
Table
18-3,
Table
18-5
and
Table
18-6
Event Name
Definition
Description and Comment
L2_LD
L2 cache reads.
This event counts L2 cache read requests coming from the L1
data cache and L2 prefetchers.
This event can count occurrences for this core or both cores.
This event can count occurrences
- for this core or both cores.
- due to demand requests and L2 hardware prefetch requests
together or separately.
- of accesses to cache lines at different MESI states.
2AH
2BH
2EH
See
Table
18-3
and
Table
18-6
L2_ST
See
Table
18-3
and
Table
18-6
L2_LOCK
See
Table
18-3,
Table
18-5
and
Table
18-6
L2_RQSTS
41H
L2_RQSTS.SELF.DEMA
ND.I_STATE
L2 store requests.
This event counts all store operations that miss the L1 data
cache and request the data from the L2 cache.
This event can count occurrences for this core or both cores.
This event can also count accesses to cache lines at different
MESI states.
L2 locked accesses.
This event counts all locked accesses to cache lines that miss
the L1 data cache.
This event can count occurrences for this core or both cores.
This event can also count accesses to cache lines at different
MESI states.
L2 cache requests.
This event counts all completed L2 cache requests. This
includes L1 data cache reads, writes, and locked accesses, L1
data prefetch requests, instruction fetches, and all L2 hardware
prefetch requests.
This event can count occurrences
- for this core or both cores.
- due to demand requests and L2 hardware prefetch requests
together, or separately.
- of accesses to cache lines at different MESI states.
2EH
L2 cache demand
This event counts all completed L2 cache demand requests
requests from this core from this core that miss the L2 cache. This includes L1 data
that missed the L2.
cache reads, writes, and locked accesses, L1 data prefetch
requests, and instruction fetches.
This is an architectural performance event.
2EH
4FH
L2_RQSTS.SELF.DEMA
ND.MESI
L2 cache demand
requests from this
core.
This event counts all completed L2 cache demand requests
from this core. This includes L1 data cache reads, writes, and
locked accesses, L1 data prefetch requests, and instruction
fetches.
This is an architectural performance event.
Vol. 3B 19-157
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
30H
See
Table
18-3,
Table
18-5
and
Table
18-6
Event Name
Definition
Description and Comment
L2_REJECT_BUSQ
Rejected L2 cache
requests.
This event indicates that a pending L2 cache request that
requires a bus transaction is delayed from moving to the bus
queue. Some of the reasons for this event are:
- The bus queue is full.
- The bus queue already holds an entry for a cache line in the
same set.
The number of events is greater or equal to the number of
requests that were rejected.
- For this core or both cores.
- Due to demand requests and L2 hardware prefetch requests
together, or separately.
- Of accesses to cache lines at different MESI states.
32H
See
Table
18-3
L2_NO_REQ
Cycles no L2 cache
requests are pending.
This event counts the number of cycles that no L2 cache
requests are pending.
3AH
00H
EIST_TRANS
Number of Enhanced
Intel SpeedStep(R)
Technology (EIST)
transitions.
This event counts the number of Enhanced Intel SpeedStep(R)
Technology (EIST) transitions that include a frequency change,
either with or without VID change. This event is incremented
only while the counting core is in C0 state. In situations where
an EIST transition was caused by hardware as a result of CxE
state transitions, those EIST transitions will also be registered
in this event.
Enhanced Intel Speedstep Technology transitions are commonly
initiated by OS, but can be initiated by HW internally. For
example: CxE states are C-states (C1,C2,C3…) which not only
place the CPU into a sleep state by turning off the clock and
other components, but also lower the voltage (which reduces
the leakage power consumption). The same is true for thermal
throttling transition which uses Enhanced Intel Speedstep
Technology internally.
3BH
C0H
19-158 Vol. 3B
THERMAL_TRIP
Number of thermal
trips.
This event counts the number of thermal trips. A thermal trip
occurs whenever the processor temperature exceeds the
thermal trip threshold temperature. Following a thermal trip,
the processor automatically reduces frequency and voltage.
The processor checks the temperature every millisecond, and
returns to normal when the temperature falls below the
thermal trip threshold temperature.
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
3CH
00H
Event Name
Definition
CPU_CLK_UNHALTED.C Core cycles when core
ORE_P
is not halted.
Description and Comment
This event counts the number of core cycles while the core is
not in a halt state. The core enters the halt state when it is
running the HLT instruction. This event is a component in many
key event ratios.
In mobile systems the core frequency may change from time to
time. For this reason this event may have a changing ratio with
regards to time. In systems with a constant core frequency, this
event can give you a measurement of the elapsed time while
the core was not in halt state by dividing the event count by the
core frequency.
-This is an architectural performance event.
- The event CPU_CLK_UNHALTED.CORE_P is counted by a
programmable counter.
- The event CPU_CLK_UNHALTED.CORE is counted by a
designated fixed counter, leaving the two programmable
counters available for other events.
3CH
01H
CPU_CLK_UNHALTED.B Bus cycles when core is This event counts the number of bus cycles while the core is not
US
not halted.
in the halt state. This event can give you a measurement of the
elapsed time while the core was not in the halt state, by
dividing the event count by the bus frequency. The core enters
the halt state when it is running the HLT instruction.
The event also has a constant ratio with
CPU_CLK_UNHALTED.REF event, which is the maximum bus to
processor frequency ratio.
Non-halted bus cycles are a component in many key event
ratios.
3CH
02H
CPU_CLK_UNHALTED.
NO_OTHER
Bus cycles when core is This event counts the number of bus cycles during which the
active and the other is core remains non-halted, and the other core on the processor is
halted.
halted.
This event can be used to determine the amount of parallelism
exploited by an application or a system. Divide this event count
by the bus frequency to determine the amount of time that
only one core was in use.
40H
21H
L1D_CACHE.LD
L1 Cacheable Data
Reads.
This event counts the number of data reads from cacheable
memory.
40H
22H
L1D_CACHE.ST
L1 Cacheable Data
Writes.
This event counts the number of data writes to cacheable
memory.
60H
See
Table
18-3
and
Table
18-4.
BUS_REQUEST_OUTST Outstanding cacheable This event counts the number of pending full cache line read
ANDING
data read bus requests transactions on the bus occurring in each cycle. A read
duration.
transaction is pending from the cycle it is sent on the bus until
the full cache line is received by the processor. NOTE: This
event is thread-independent and will not provide a count per
logical processor when AnyThr is disabled.
Vol. 3B 19-159
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
61H
See
Table
18-4.
Event Name
Definition
BUS_BNR_DRV
Number of Bus Not
This event counts the number of Bus Not Ready (BNR) signals
Ready signals asserted. that the processor asserts on the bus to suspend additional bus
requests by other bus agents. A bus agent asserts the BNR
signal when the number of data and snoop transactions is close
to the maximum that the bus can handle.
Description and Comment
While this signal is asserted, new transactions cannot be
submitted on the bus. As a result, transaction latency may have
higher impact on program performance. NOTE: This event is
thread-independent and will not provide a count per logical
processor when AnyThr is disabled.
62H
See
Table
18-4.
BUS_DRDY_CLOCKS
Bus cycles when data
is sent on the bus.
This event counts the number of bus cycles during which the
DRDY (Data Ready) signal is asserted on the bus. The DRDY
signal is asserted when data is sent on the bus.
This event counts the number of bus cycles during which this
agent (the processor) writes data on the bus back to memory or
to other bus agents. This includes all explicit and implicit data
writebacks, as well as partial writes.
Note: This event is thread-independent and will not provide a
count per logical processor when AnyThr is disabled.
63H
See
Table
18-3
and
Table
18-4.
BUS_LOCK_CLOCKS
Bus cycles when a
This event counts the number of bus cycles, during which the
LOCK signal is asserted. LOCK signal is asserted on the bus. A LOCK signal is asserted
when there is a locked memory access, due to:
- Uncacheable memory.
- Locked operation that spans two cache lines.
- Page-walk from an uncacheable page table.
Bus locks have a very high performance penalty and it is highly
recommended to avoid such accesses. NOTE: This event is
thread-independent and will not provide a count per logical
processor when AnyThr is disabled.
64H
See
Table
18-3.
BUS_DATA_RCV
Bus cycles while
processor receives
data.
This event counts the number of cycles during which the
processor is busy receiving data. NOTE: This event is threadindependent and will not provide a count per logical processor
when AnyThr is disabled.
65H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_BRD
Burst read bus
transactions.
This event counts the number of burst read transactions
including:
- L1 data cache read misses (and L1 data cache hardware
prefetches).
- L2 hardware prefetches by the DPL and L2 streamer.
- IFU read misses of cacheable lines.
It does not include RFO transactions.
66H
See
Table
18-3
and
Table
18-4.
19-160 Vol. 3B
BUS_TRANS_RFO
RFO bus transactions.
This event counts the number of Read For Ownership (RFO) bus
transactions, due to store operations that miss the L1 data
cache and the L2 cache. This event also counts RFO bus
transactions due to locked operations.
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
67H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_WB
Explicit writeback bus
transactions.
This event counts all explicit writeback bus transactions due to
dirty line evictions. It does not count implicit writebacks due to
invalidation by a snoop request.
68H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_IFETCH
Instruction-fetch bus
transactions.
This event counts all instruction fetch full cache line bus
transactions.
69H
See
Table
18-3
and
Table
18-4.
BUS_TRANS_INVAL
Invalidate bus
transactions.
This event counts all invalidate transactions. Invalidate
transactions are generated when:
6AH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_PWR
Partial write bus
transaction.
This event counts partial write bus transactions.
6BH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_P
Partial bus
transactions.
This event counts all (read and write) partial bus transactions.
6CH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_IO
IO bus transactions.
This event counts the number of completed I/O bus
transactions as a result of IN and OUT instructions. The count
does not include memory mapped IO.
6DH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_DEF
Deferred bus
transactions.
This event counts the number of deferred transactions.
6EH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_BURST
Burst (full cache-line)
bus transactions.
This event counts burst (full cache line) transactions including:
- A store operation hits a shared line in the L2 cache.
- A full cache line write misses the L2 cache or hits a shared line
in the L2 cache.
- Burst reads.
- RFOs.
- Explicit writebacks.
- Write combine lines.
Vol. 3B 19-161
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
6FH
See
Table
18-3
and
Table
18-4.
BUS_TRANS_MEM
Memory bus
transactions.
This event counts all memory bus transactions including:
See
Table
18-3
and
Table
18-4.
BUS_TRANS_ANY
See
Table
18-3
and
Table
18-6.
EXT_SNOOP
See
Table
18-4.
BUS_HIT_DRV
7BH
See
Table
18-4.
BUS_HITM_DRV
HITM signal asserted.
This event counts the number of bus cycles during which the
processor drives the HITM# pin to signal HITM snoop response.
NOTE: This event is thread-independent and will not provide a
count per logical processor when AnyThr is disabled.
7DH
See
Table
18-3.
BUSQ_EMPTY
Bus queue is empty.
This event counts the number of cycles during which the core
did not have any pending transactions in the bus queue.
See
Table
18-3
and
Table
18-4.
SNOOP_STALL_DRV
7FH
See
Table
18-3.
BUS_IO_WAIT
IO requests waiting in
the bus queue.
This event counts the number of core cycles during which IO
requests wait in the bus queue. This event counts IO requests
from the core.
80H
03H
ICACHE.ACCESSES
Instruction fetches.
This event counts all instruction fetches, including uncacheable
fetches.
80H
02H
ICACHE.MISSES
Icache miss.
This event counts all instruction fetches that miss the
Instruction cache or produce memory requests. This includes
uncacheable fetches. An instruction fetch miss is counted only
once and not once for every cycle it is outstanding.
82H
04H
ITLB.FLUSH
ITLB flushes.
This event counts the number of ITLB flushes.
82H
02H
ITLB.MISSES
ITLB misses.
This event counts the number of instruction fetches that miss
the ITLB.
70H
77H
7AH
7EH
19-162 Vol. 3B
- Burst transactions.
- Partial reads and writes.
- Invalidate transactions.
The BUS_TRANS_MEM count is the sum of
BUS_TRANS_BURST, BUS_TRANS_P and BUS_TRANS_INVAL.
All bus transactions.
This event counts all bus transactions. This includes:
- Memory transactions.
- IO transactions (non memory-mapped).
- Deferred transaction completion.
- Other less frequent transactions, such as interrupts.
External snoops.
This event counts the snoop responses to bus transactions.
Responses can be counted separately by type and by bus agent.
Note: This event is thread-independent and will not provide a
count per logical processor when AnyThr is disabled.
HIT signal asserted.
This event counts the number of bus cycles during which the
processor drives the HIT# pin to signal HIT snoop response.
Note: This event is thread-independent and will not provide a
count per logical processor when AnyThr is disabled.
Note: This event is thread-independent and will not provide a
count per logical processor when AnyThr is disabled.
Bus stalled for snoops.
This event counts the number of times that the bus snoop stall
signal is asserted. During the snoop stall cycles no new bus
transactions requiring a snoop response can be initiated on the
bus.
Note: This event is thread-independent and will not provide a
count per logical processor when AnyThr is disabled.
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
AAH
02H
MACRO_INSTS.CISC_DE CISC macro instructions This event counts the number of complex instructions decoded,
CODED
decoded.
but not necessarily executed or retired. Only one complex
instruction can be decoded at a time.
AAH
03H
MACRO_INSTS.ALL_DE All Instructions
CODED
decoded.
This event counts the number of instructions decoded.
B0H
00H
SIMD_UOPS_EXEC.S
SIMD micro-ops
executed (excluding
stores).
This event counts all the SIMD micro-ops executed. This event
does not count MOVQ and MOVD stores from register to
memory.
B0H
80H
SIMD_UOPS_EXEC.AR
SIMD micro-ops retired This event counts the number of SIMD saturated arithmetic
(excluding stores).
micro-ops executed.
B1H
00H
SIMD_SAT_UOP_EXEC. SIMD saturated
S
arithmetic micro-ops
executed.
This event counts the number of SIMD saturated arithmetic
micro-ops executed.
B1H
80H
SIMD_SAT_UOP_EXEC. SIMD saturated
AR
arithmetic micro-ops
retired.
This event counts the number of SIMD saturated arithmetic
micro-ops retired.
B3H
01H
SIMD_UOP_TYPE_EXE
C.MUL.S
SIMD packed multiply
micro-ops executed.
This event counts the number of SIMD packed multiply microops executed.
B3H
81H
SIMD_UOP_TYPE_EXE
C.MUL.AR
SIMD packed multiply
micro-ops retired.
This event counts the number of SIMD packed multiply microops retired.
B3H
02H
SIMD_UOP_TYPE_EXE
C.SHIFT.S
SIMD packed shift
micro-ops executed.
This event counts the number of SIMD packed shift micro-ops
executed.
B3H
82H
SIMD_UOP_TYPE_EXE
C.SHIFT.AR
SIMD packed shift
micro-ops retired.
This event counts the number of SIMD packed shift micro-ops
retired.
B3H
04H
SIMD_UOP_TYPE_EXE
C.PACK.S
SIMD pack micro-ops
executed.
This event counts the number of SIMD pack micro-ops executed.
B3H
84H
SIMD_UOP_TYPE_EXE
C.PACK.AR
SIMD pack micro-ops
retired.
This event counts the number of SIMD pack micro-ops retired.
B3H
08H
SIMD_UOP_TYPE_EXE
C.UNPACK.S
SIMD unpack micro-ops This event counts the number of SIMD unpack micro-ops
executed.
executed.
B3H
88H
SIMD_UOP_TYPE_EXE
C.UNPACK.AR
SIMD unpack micro-ops This event counts the number of SIMD unpack micro-ops retired.
retired.
B3H
10H
SIMD_UOP_TYPE_EXE
C.LOGICAL.S
SIMD packed logical
micro-ops executed.
This event counts the number of SIMD packed logical micro-ops
executed.
B3H
90H
SIMD_UOP_TYPE_EXE
C.LOGICAL.AR
SIMD packed logical
micro-ops retired.
This event counts the number of SIMD packed logical micro-ops
retired.
B3H
20H
SIMD_UOP_TYPE_EXE
C.ARITHMETIC.S
SIMD packed arithmetic This event counts the number of SIMD packed arithmetic micromicro-ops executed.
ops executed.
B3H
A0H
SIMD_UOP_TYPE_EXE
C.ARITHMETIC.AR
SIMD packed arithmetic This event counts the number of SIMD packed arithmetic micromicro-ops retired.
ops retired.
C0H
00H
INST_RETIRED.ANY_P
Instructions retired
(precise event).
Event Name
Definition
Description and Comment
This event counts the number of instructions that retire
execution. For instructions that consist of multiple micro-ops,
this event counts the retirement of the last micro-op of the
instruction. The counter continues counting during hardware
interrupts, traps, and inside interrupt handlers.
Vol. 3B 19-163
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
N/A
00H
INST_RETIRED.ANY
Instructions retired.
This event counts the number of instructions that retire
execution. For instructions that consist of multiple micro-ops,
this event counts the retirement of the last micro-op of the
instruction. The counter continues counting during hardware
interrupts, traps, and inside interrupt handlers.
C2H
10H
UOPS_RETIRED.ANY
Micro-ops retired.
This event counts the number of micro-ops retired. The
processor decodes complex macro instructions into a sequence
of simpler micro-ops. Most instructions are composed of one or
two micro-ops. Some instructions are decoded into longer
sequences such as repeat instructions, floating point
transcendental instructions, and assists. In some cases micro-op
sequences are fused or whole instructions are fused into one
micro-op. See other UOPS_RETIRED events for differentiating
retired fused and non-fused micro-ops.
C3H
01H
MACHINE_CLEARS.SMC Self-Modifying Code
detected.
This event counts the number of times that a program writes to
a code section. Self-modifying code causes a severe penalty in
all Intel® architecture processors.
C4H
00H
BR_INST_RETIRED.AN
Y
This event counts the number of branch instructions retired.
Retired branch
instructions.
This is an architectural performance event.
C4H
01H
BR_INST_RETIRED.PRE Retired branch
D_NOT_TAKEN
instructions that were
predicted not-taken.
This event counts the number of branch instructions retired
that were correctly predicted to be not-taken.
C4H
02H
BR_INST_RETIRED.MIS Retired branch
PRED_NOT_TAKEN
instructions that were
mispredicted nottaken.
This event counts the number of branch instructions retired
that were mispredicted and not-taken.
C4H
04H
BR_INST_RETIRED.PRE Retired branch
D_TAKEN
instructions that were
predicted taken.
This event counts the number of branch instructions retired
that were correctly predicted to be taken.
C4H
08H
BR_INST_RETIRED.MIS Retired branch
PRED_TAKEN
instructions that were
mispredicted taken.
This event counts the number of branch instructions retired
that were mispredicted and taken.
C4H
0AH
BR_INST_RETIRED.MIS Retired mispredicted
PRED
branch instructions
(precise event).
This event counts the number of retired branch instructions
that were mispredicted by the processor. A branch
misprediction occurs when the processor predicts that the
branch would be taken, but it is not, or vice-versa. Mispredicted
branches degrade the performance because the processor
starts executing instructions along a wrong path it predicts.
When the misprediction is discovered, all the instructions
executed in the wrong path must be discarded, and the
processor must start again on the correct path.
Using the Profile-Guided Optimization (PGO) features of the
Intel® C++ compiler may help reduce branch mispredictions. See
the compiler documentation for more information on this
feature.
19-164 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
Event Name
Definition
Description and Comment
To determine the branch misprediction ratio, divide the
BR_INST_RETIRED.MISPRED event count by the number of
BR_INST_RETIRED.ANY event count. To determine the number
of mispredicted branches per instruction, divide the number of
mispredicted branches by the INST_RETIRED.ANY event count.
To measure the impact of the branch mispredictions use the
event RESOURCE_STALLS.BR_MISS_CLEAR.
Tips:
- See the optimization guide for tips on reducing branch
mispredictions.
- PGO's purpose is to have straight line code for the most
frequent execution paths, reducing branches taken and
increasing the “basic block” size, possibly also reducing the code
footprint or working-set.
C4H
0CH
BR_INST_RETIRED.TAK Retired taken branch
EN
instructions.
This event counts the number of branches retired that were
taken.
C4H
0FH
BR_INST_RETIRED.AN
Y1
This event counts the number of branch instructions retired
that were mispredicted. This event is a duplicate of
BR_INST_RETIRED.MISPRED.
C5H
00H
BR_INST_RETIRED.MIS Retired mispredicted
PRED
branch instructions
(precise event).
Retired branch
instructions.
This event counts the number of retired branch instructions
that were mispredicted by the processor. A branch
misprediction occurs when the processor predicts that the
branch would be taken, but it is not, or vice-versa. Mispredicted
branches degrade the performance because the processor
starts executing instructions along a wrong path it predicts.
When the misprediction is discovered, all the instructions
executed in the wrong path must be discarded, and the
processor must start again on the correct path.
Using the Profile-Guided Optimization (PGO) features of the
Intel® C++ compiler may help reduce branch mispredictions. See
the compiler documentation for more information on this
feature.
To determine the branch misprediction ratio, divide the
BR_INST_RETIRED.MISPRED event count by the number of
BR_INST_RETIRED.ANY event count. To determine the number
of mispredicted branches per instruction, divide the number of
mispredicted branches by the INST_RETIRED.ANY event count.
To measure the impact of the branch mispredictions use the
event RESOURCE_STALLS.BR_MISS_CLEAR.
Tips:
- See the optimization guide for tips on reducing branch
mispredictions.
- PGO's purpose is to have straight line code for the most
frequent execution paths, reducing branches taken and
increasing the “basic block” size, possibly also reducing the code
footprint or working-set.
C6H
01H
CYCLES_INT_MASKED.
CYCLES_INT_MASKED
Cycles during which
This event counts the number of cycles during which interrupts
interrupts are disabled. are disabled.
C6H
02H
CYCLES_INT_MASKED.
CYCLES_INT_PENDING
_AND_MASKED
Cycles during which
interrupts are pending
and disabled.
This event counts the number of cycles during which there are
pending interrupts but interrupts are disabled.
Vol. 3B 19-165
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
C7H
01H
SIMD_INST_RETIRED.P Retired Streaming
ACKED_SINGLE
SIMD Extensions (SSE)
packed-single
instructions.
This event counts the number of SSE packed-single instructions
retired.
C7H
02H
SIMD_INST_RETIRED.S Retired Streaming
CALAR_SINGLE
SIMD Extensions (SSE)
scalar-single
instructions.
This event counts the number of SSE scalar-single instructions
retired.
C7H
04H
SIMD_INST_RETIRED.P Retired Streaming
ACKED_DOUBLE
SIMD Extensions 2
(SSE2) packed-double
instructions.
This event counts the number of SSE2 packed-double
instructions retired.
C7H
08H
SIMD_INST_RETIRED.S Retired Streaming
CALAR_DOUBLE
SIMD Extensions 2
(SSE2) scalar-double
instructions.
This event counts the number of SSE2 scalar-double
instructions retired.
C7H
10H
SIMD_INST_RETIRED.V Retired Streaming
ECTOR
SIMD Extensions 2
(SSE2) vector
instructions.
This event counts the number of SSE2 vector instructions
retired.
C7H
1FH
SIMD_INST_RETIRED.A Retired Streaming
NY
SIMD instructions.
This event counts the overall number of SIMD instructions
retired. To count each type of SIMD instruction separately, use
the following events:
Event Name
Definition
Description and Comment
SIMD_INST_RETIRED.PACKED_SINGLE
SIMD_INST_RETIRED.SCALAR_SINGLE
SIMD_INST_RETIRED.PACKED_DOUBLE
SIMD_INST_RETIRED.SCALAR_DOUBLE
SIMD_INST_RETIRED.VECTOR.
C8H
00H
HW_INT_RCV
CAH
01H
SIMD_COMP_INST_RET Retired computational
IRED.PACKED_SINGLE Streaming SIMD
Extensions (SSE)
packed-single
instructions.
This event counts the number of computational SSE packedsingle instructions retired. Computational instructions perform
arithmetic computations, like add, multiply and divide.
Instructions that perform load and store operations or logical
operations, like XOR, OR, and AND are not counted by this
event.
CAH
02H
SIMD_COMP_INST_RET Retired computational
IRED.SCALAR_SINGLE Streaming SIMD
Extensions (SSE)
scalar-single
instructions.
This event counts the number of computational SSE scalarsingle instructions retired. Computational instructions perform
arithmetic computations, like add, multiply and divide.
Instructions that perform load and store operations or logical
operations, like XOR, OR, and AND are not counted by this
event.
CAH
04H
SIMD_COMP_INST_RET Retired computational
IRED.PACKED_DOUBLE Streaming SIMD
Extensions 2 (SSE2)
packed-double
instructions.
This event counts the number of computational SSE2 packeddouble instructions retired. Computational instructions perform
arithmetic computations, like add, multiply and divide.
Instructions that perform load and store operations or logical
operations, like XOR, OR, and AND are not counted by this
event.
19-166 Vol. 3B
Hardware interrupts
received.
This event counts the number of hardware interrupts received
by the processor. This event will count twice for dual-pipe
micro-ops.
PERFORMANCE-MONITORING EVENTS
Table 19-26. Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors (Contd.)
Event
Num.
Umask
Value
CAH
08H
SIMD_COMP_INST_RET Retired computational
IRED.SCALAR_DOUBLE Streaming SIMD
Extensions 2 (SSE2)
scalar-double
instructions.
This event counts the number of computational SSE2 scalardouble instructions retired. Computational instructions perform
arithmetic computations, like add, multiply and divide.
Instructions that perform load and store operations or logical
operations, like XOR, OR, and AND are not counted by this
event.
CBH
01H
MEM_LOAD_RETIRED.L Retired loads that hit
2_HIT
the L2 cache (precise
event).
This event counts the number of retired load operations that
missed the L1 data cache and hit the L2 cache.
CBH
02H
MEM_LOAD_RETIRED.L Retired loads that miss This event counts the number of retired load operations that
2_MISS
the L2 cache (precise
missed the L2 cache.
event).
CBH
04H
MEM_LOAD_RETIRED.D Retired loads that miss This event counts the number of retired loads that missed the
DTLB. The DTLB miss is not counted if the load operation causes
TLB_MISS
the DTLB (precise
a fault.
event).
CDH
00H
SIMD_ASSIST
Event Name
Definition
SIMD assists invoked.
Description and Comment
This event counts the number of SIMD assists invoked. SIMD
assists are invoked when an EMMS instruction is executed after
MMX™ technology code has changed the MMX state in the
floating point stack. For example, these assists are required in
the following cases.
Streaming SIMD Extensions (SSE) instructions:
1. Denormal input when the DAZ (Denormals Are Zeros) flag is
off.
2. Underflow result when the FTZ (Flush To Zero) flag is off.
CEH
00H
SIMD_INSTR_RETIRED
SIMD Instructions
retired.
This event counts the number of SIMD instructions that retired.
CFH
00H
SIMD_SAT_INSTR_RETI Saturated arithmetic
RED
instructions retired.
This event counts the number of saturated arithmetic SIMD
instructions that retired.
E0H
01H
BR_INST_DECODED
Branch instructions
decoded.
This event counts the number of branch instructions decoded.
E4H
01H
BOGUS_BR
Bogus branches.
This event counts the number of byte sequences that were
mistakenly detected as taken branch instructions. This results
in a BACLEAR event and the BTB is flushed. This occurs mainly
after task switches.
E6H
01H
BACLEARS.ANY
BACLEARS asserted.
This event counts the number of times the front end is
redirected for a branch prediction, mainly when an early branch
prediction is corrected by other branch handling mechanisms in
the front end. This can occur if the code has many branches
such that they cannot be consumed by the branch predictor.
Each Baclear asserted costs approximately 7 cycles. The effect
on total execution time depends on the surrounding code.
Vol. 3B 19-167
PERFORMANCE-MONITORING EVENTS
19.14
PERFORMANCE MONITORING EVENTS FOR INTEL® CORE™ SOLO AND
INTEL® CORE™ DUO PROCESSORS
Table 19-27 lists non-architectural performance events for Intel® Core™ Duo processors. If a non-architectural
event requires qualification in core specificity, it is indicated in the comment column. Table 19-27 also applies to
Intel® Core™ Solo processors; bits in the unit mask corresponding to core-specificity are reserved and should be
00B.
Table 19-27. Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors
Event
Num.
Event Mask
Mnemonic
Umask
Value
Description
03H
LD_Blocks
00H
Load operations delayed due to store buffer blocks.
Comment
The preceding store may be blocked due to
unknown address, unknown data, or conflict due to
partial overlap between the load and store.
04H
SD_Drains
00H
Cycles while draining store buffers.
05H
Misalign_Mem_Ref
00H
Misaligned data memory references (MOB splits of
loads and stores).
06H
Seg_Reg_Loads
00H
Segment register loads.
07H
SSE_PrefNta_Ret
00H
SSE software prefetch instruction PREFETCHNTA
retired.
07H
SSE_PrefT1_Ret
01H
SSE software prefetch instruction PREFETCHT1
retired.
07H
SSE_PrefT2_Ret
02H
SSE software prefetch instruction PREFETCHT2
retired.
07H
SSE_NTStores_Ret
03H
SSE streaming store instruction retired.
10H
FP_Comps_Op_Exe
00H
FP computational Instruction executed. FADD,
FSUB, FCOM, FMULs, MUL, IMUL, FDIVs, DIV, IDIV,
FPREMs, FSQRT are included; but exclude FADD or
FMUL used in the middle of a transcendental
instruction.
11H
FP_Assist
00H
FP exceptions experienced microcode assists.
IA32_PMC1 only.
12H
Mul
00H
Multiply operations (a speculative count, including
FP and integer multiplies).
IA32_PMC1 only.
13H
Div
00H
Divide operations (a speculative count, including FP IA32_PMC1 only.
and integer divisions).
14H
Cycles_Div_Busy
00H
Cycles the divider is busy.
IA32_PMC0 only.
21H
L2_ADS
00H
L2 Address strobes.
Requires corespecificity.
22H
Dbus_Busy
00H
Core cycle during which data bus was busy
(increments by 4).
Requires corespecificity.
23H
Dbus_Busy_Rd
00H
Cycles data bus is busy transferring data to a core
(increments by 4).
Requires corespecificity.
24H
L2_Lines_In
00H
L2 cache lines allocated.
Requires core-specificity
and HW prefetch
qualification.
25H
L2_M_Lines_In
00H
L2 Modified-state cache lines allocated.
Requires corespecificity.
19-168 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-27. Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors (Contd.)
Event
Num.
Event Mask
Mnemonic
Umask
Value
Description
Comment
26H
L2_Lines_Out
00H
L2 cache lines evicted.
27H
L2_M_Lines_Out
00H
L2 Modified-state cache lines evicted.
Requires core-specificity
and HW prefetch
qualification.
28H
L2_IFetch
Requires MESI
qualification
L2 instruction fetches from instruction fetch unit
(includes speculative fetches).
Requires corespecificity.
29H
L2_LD
Requires MESI
qualification
L2 cache reads.
Requires corespecificity.
2AH
L2_ST
Requires MESI
qualification
L2 cache writes (includes speculation).
Requires corespecificity.
2EH
L2_Rqsts
Requires MESI
qualification
L2 cache reference requests.
30H
L2_Reject_Cycles
Requires MESI
qualification
Cycles L2 is busy and rejecting new requests.
Requires corespecificity, HW prefetch
qualification.
32H
L2_No_Request_
Cycles
Requires MESI
qualification
Cycles there is no request to access L2.
3AH
EST_Trans_All
00H
Any Intel Enhanced SpeedStep(R) Technology
transitions.
3AH
EST_Trans_All
10H
Intel Enhanced SpeedStep Technology frequency
transitions.
3BH
Thermal_Trip
C0H
Duration in a thermal trip based on the current core Use edge trigger to
clock.
count occurrence.
3CH
NonHlt_Ref_Cycles
01H
Non-halted bus cycles.
3CH
Serial_Execution_
Cycles
02H
Non-halted bus cycles of this core executing code
while the other core is halted.
40H
DCache_Cache_LD
Requires MESI
qualification
L1 cacheable data read operations.
41H
DCache_Cache_ST
Requires MESI
qualification
L1 cacheable data write operations.
42H
DCache_Cache_
Lock
Requires MESI
qualification
L1 cacheable lock read operations to invalid state.
43H
Data_Mem_Ref
01H
L1 data read and writes of cacheable and noncacheable types.
44H
Data_Mem_Cache_
Ref
02H
L1 data cacheable read and write operations.
45H
DCache_Repl
0FH
L1 data cache line replacements.
46H
DCache_M_Repl
00H
L1 data M-state cache line allocated.
47H
DCache_M_Evict
00H
L1 data M-state cache line evicted.
48H
DCache_Pend_Miss
00H
Weighted cycles of L1 miss outstanding.
49H
Dtlb_Miss
00H
Data references that missed TLB.
4BH
SSE_PrefNta_Miss
00H
PREFETCHNTA missed all caches.
4BH
SSE_PrefT1_Miss
01H
PREFETCHT1 missed all caches.
4BH
SSE_PrefT2_Miss
02H
PREFETCHT2 missed all caches.
4BH
SSE_NTStores_
Miss
03H
SSE streaming store instruction missed all caches.
Use Cmask =1 to count
duration.
Vol. 3B 19-169
PERFORMANCE-MONITORING EVENTS
Table 19-27. Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors (Contd.)
Event
Num.
Event Mask
Mnemonic
Umask
Value
Description
Comment
4FH
L1_Pref_Req
00H
L1 prefetch requests due to DCU cache misses.
May overcount if
request re-submitted.
60H
Bus_Req_
Outstanding
00; Requires coreWeighted cycles of cacheable bus data read
specificity, and agent requests. This event counts full-line read request
specificity
from DCU or HW prefetcher, but not RFO, write,
instruction fetches, or others.
Use Cmask =1 to count
duration.
Use Umask bit 12 to
include HWP or exclude
HWP separately.
61H
Bus_BNR_Clocks
00H
External bus cycles while BNR asserted.
62H
Bus_DRDY_Clocks
00H
External bus cycles while DRDY asserted.
Requires agent
specificity.
63H
Bus_Locks_Clocks
00H
External bus cycles while bus lock signal asserted.
Requires core
specificity.
64H
Bus_Data_Rcv
40H
Number of data chunks received by this processor.
65H
Bus_Trans_Brd
See comment.
Burst read bus transactions (data or code).
Requires core
specificity.
66H
Bus_Trans_RFO
See comment.
Completed read for ownership (RFO) transactions.
68H
Bus_Trans_Ifetch
See comment.
Completed instruction fetch transactions.
Requires agent
specificity.
69H
Bus_Trans_Inval
See comment.
Completed invalidate transactions.
6AH
Bus_Trans_Pwr
See comment.
Completed partial write transactions.
6BH
Bus_Trans_P
See comment.
6CH
Bus_Trans_IO
See comment.
6DH
Bus_Trans_Def
20H
Requires core
specificity.
Each transaction counts
Completed partial transactions (include partial read its address strobe.
+ partial write + line write).
Retried transaction may
be counted more than
Completed I/O transactions (read and write).
once.
Completed defer transactions.
Requires core
specificity.
Retried transaction may
be counted more than
once.
67H
Bus_Trans_WB
C0H
Completed writeback transactions from DCU (does
not include L2 writebacks).
Requires agent
specificity.
6EH
Bus_Trans_Burst
C0H
6FH
Bus_Trans_Mem
C0H
70H
Bus_Trans_Any
C0H
Completed burst transactions (full line transactions Each transaction counts
its address strobe.
include reads, write, RFO, and writebacks).
Retried transaction may
Completed memory transactions. This includes
Bus_Trans_Burst + Bus_Trans_P+Bus_Trans_Inval. be counted more than
once.
Any completed bus transactions.
77H
Bus_Snoops
00H
Counts any snoop on the bus.
Requires MESI
qualification.
Requires agent
specificity.
78H
DCU_Snoop_To_
Share
01H
DCU snoops to share-state L1 cache line due to L1
misses.
Requires core
specificity.
7DH
Bus_Not_In_Use
00H
Number of cycles there is no transaction from the
core.
Requires core
specificity.
7EH
Bus_Snoop_Stall
00H
Number of bus cycles while bus snoop is stalled.
19-170 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-27. Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors (Contd.)
Event
Num.
Event Mask
Mnemonic
Umask
Value
80H
ICache_Reads
00H
Number of instruction fetches from ICache,
streaming buffers (both cacheable and uncacheable
fetches).
81H
ICache_Misses
00H
Number of instruction fetch misses from ICache,
streaming buffers.
85H
ITLB_Misses
00H
Number of iITLB misses.
86H
IFU_Mem_Stall
00H
Cycles IFU is stalled while waiting for data from
memory.
87H
ILD_Stall
00H
Number of instruction length decoder stalls (Counts
number of LCP stalls).
88H
Br_Inst_Exec
00H
Branch instruction executed (includes speculation).
89H
Br_Missp_Exec
00H
Branch instructions executed and mispredicted at
execution (includes branches that do not have
prediction or mispredicted).
8AH
Br_BAC_Missp_
Exec
00H
Branch instructions executed that were
mispredicted at front end.
8BH
Br_Cnd_Exec
00H
Conditional branch instructions executed.
8CH
Br_Cnd_Missp_
Exec
00H
Conditional branch instructions executed that were
mispredicted.
8DH
Br_Ind_Exec
00H
Indirect branch instructions executed.
8EH
Br_Ind_Missp_Exec
00H
Indirect branch instructions executed that were
mispredicted.
8FH
Br_Ret_Exec
00H
Return branch instructions executed.
90H
Br_Ret_Missp_Exec
00H
Return branch instructions executed that were
mispredicted.
91H
Br_Ret_BAC_Missp_
Exec
00H
Return branch instructions executed that were
mispredicted at the front end.
92H
Br_Call_Exec
00H
Return call instructions executed.
93H
Br_Call_Missp_Exec
00H
Return call instructions executed that were
mispredicted.
94H
Br_Ind_Call_Exec
00H
Indirect call branch instructions executed.
A2H
Resource_Stall
00H
Cycles while there is a resource related stall
(renaming, buffer entries) as seen by allocator.
B0H
MMX_Instr_Exec
00H
Number of MMX instructions executed (does not
include MOVQ and MOVD stores).
B1H
SIMD_Int_Sat_Exec
00H
Number of SIMD Integer saturating instructions
executed.
B3H
SIMD_Int_Pmul_
Exec
01H
Number of SIMD Integer packed multiply
instructions executed.
B3H
SIMD_Int_Psft_Exec
02H
Number of SIMD Integer packed shift instructions
executed.
B3H
SIMD_Int_Pck_Exec
04H
Number of SIMD Integer pack operations instruction
executed.
B3H
SIMD_Int_Upck_
Exec
08H
Number of SIMD Integer unpack instructions
executed.
Description
Comment
Vol. 3B 19-171
PERFORMANCE-MONITORING EVENTS
Table 19-27. Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors (Contd.)
Event
Num.
Event Mask
Mnemonic
Umask
Value
B3H
SIMD_Int_Plog_
Exec
10H
Number of SIMD Integer packed logical instructions
executed.
B3H
SIMD_Int_Pari_Exec
20H
Number of SIMD Integer packed arithmetic
instructions executed.
C0H
Instr_Ret
00H
Number of instruction retired (Macro fused
instruction count as 2).
C1H
FP_Comp_Instr_Ret
00H
Number of FP compute instructions retired (X87
instruction or instruction that contains X87
operations).
C2H
Uops_Ret
00H
Number of micro-ops retired (include fused uops).
C3H
SMC_Detected
00H
Number of times self-modifying code condition
detected.
C4H
Br_Instr_Ret
00H
Number of branch instructions retired.
C5H
Br_MisPred_Ret
00H
Number of mispredicted branch instructions retired.
C6H
Cycles_Int_Masked
00H
Cycles while interrupt is disabled.
C7H
Cycles_Int_Pedning_ 00H
Masked
Cycles while interrupt is disabled and interrupts are
pending.
C8H
HW_Int_Rx
00H
Number of hardware interrupts received.
C9H
Br_Taken_Ret
00H
Number of taken branch instruction retired.
CAH
Br_MisPred_Taken_
Ret
00H
Number of taken and mispredicted branch
instructions retired.
CCH
MMX_FP_Trans
00H
Number of transitions from MMX to X87.
CCH
FP_MMX_Trans
01H
Number of transitions from X87 to MMX.
CDH
MMX_Assist
00H
Number of EMMS executed.
CEH
MMX_Instr_Ret
00H
Number of MMX instruction retired.
D0H
Instr_Decoded
00H
Number of instruction decoded.
D7H
ESP_Uops
00H
Number of ESP folding instruction decoded.
D8H
SIMD_FP_SP_Ret
00H
Number of SSE/SSE2 single precision instructions
retired (packed and scalar).
D8H
SIMD_FP_SP_S_
Ret
01H
Number of SSE/SSE2 scalar single precision
instructions retired.
D8H
SIMD_FP_DP_P_
Ret
02H
Number of SSE/SSE2 packed double precision
instructions retired.
D8H
SIMD_FP_DP_S_
Ret
03H
Number of SSE/SSE2 scalar double precision
instructions retired.
D8H
SIMD_Int_128_Ret
04H
Number of SSE2 128 bit integer instructions
retired.
D9H
SIMD_FP_SP_P_
Comp_Ret
00H
Number of SSE/SSE2 packed single precision
compute instructions retired (does not include AND,
OR, XOR).
D9H
SIMD_FP_SP_S_
Comp_Ret
01H
Number of SSE/SSE2 scalar single precision
compute instructions retired (does not include AND,
OR, XOR).
19-172 Vol. 3B
Description
Comment
Use IA32_PMC0 only.
PERFORMANCE-MONITORING EVENTS
Table 19-27. Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors (Contd.)
Event
Num.
Event Mask
Mnemonic
Umask
Value
D9H
SIMD_FP_DP_P_
Comp_Ret
02H
Number of SSE/SSE2 packed double precision
compute instructions retired (does not include AND,
OR, XOR).
D9H
SIMD_FP_DP_S_
Comp_Ret
03H
Number of SSE/SSE2 scalar double precision
compute instructions retired (does not include AND,
OR, XOR).
DAH
Fused_Uops_Ret
00H
All fused uops retired.
DAH
Fused_Ld_Uops_
Ret
01H
Fused load uops retired.
DAH
Fused_St_Uops_Ret
02H
Fused store uops retired.
DBH
Unfusion
00H
Number of unfusion events in the ROB (due to
exception).
E0H
Br_Instr_Decoded
00H
Branch instructions decoded.
E2H
BTB_Misses
00H
Number of branches the BTB did not produce a
prediction.
E4H
Br_Bogus
00H
Number of bogus branches.
Description
E6H
BAClears
00H
Number of BAClears asserted.
F0H
Pref_Rqsts_Up
00H
Number of hardware prefetch requests issued in
forward streams.
F8H
Pref_Rqsts_Dn
00H
Number of hardware prefetch requests issued in
backward streams.
19.15
Comment
PENTIUM® 4 AND INTEL® XEON® PROCESSOR PERFORMANCEMONITORING EVENTS
Tables 19-28, 19-29 and 19-30 list performance-monitoring events that can be counted or sampled on processors
based on Intel NetBurst® microarchitecture. Table 19-28 lists the non-retirement events, and Table 19-29 lists the
at-retirement events. Tables 19-31, 19-32, and 19-33 describes three sets of parameters that are available for
three of the at-retirement counting events defined in Table 19-29. Table 19-34 shows which of the non-retirement
and at retirement events are logical processor specific (TS) (see Section 18.16.4, “Performance Monitoring
Events”) and which are non-logical processor specific (TI).
Some of the Pentium 4 and Intel Xeon processor performance-monitoring events may be available only to specific
models. The performance-monitoring events listed in Tables 19-28 and 19-29 apply to processors with CPUID
signature that matches family encoding 15, model encoding 0, 1, 2 3, 4, or 6. Table applies to processors with a
CPUID signature that matches family encoding 15, model encoding 3, 4 or 6.
The functionality of performance-monitoring events in Pentium 4 and Intel Xeon processors is also available when
IA-32e mode is enabled.
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting
Event Name
TC_deliver_mode
Event Parameters
Parameter Value
Description
This event counts the duration (in clock cycles) of the operating
modes of the trace cache and decode engine in the processor
package. The mode is specified by one or more of the event mask
bits.
Vol. 3B 19-173
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
ESCR restrictions
Parameter Value
Description
MSR_TC_ESCR0
MSR_TC_ESCR1
Counter numbers
per ESCR
ESCR0: 4, 5
ESCR Event Select
01H
ESCR1: 6, 7
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
0: DD
Both logical processors are in deliver mode.
1: DB
Logical processor 0 is in deliver mode and logical processor 1 is in
build mode.
2: DI
Logical processor 0 is in deliver mode and logical processor 1 is
either halted, under a machine clear condition or transitioning to a
long microcode flow.
3: BD
Logical processor 0 is in build mode and logical processor 1 is in
deliver mode.
4: BB
Both logical processors are in build mode.
5: BI
Logical processor 0 is in build mode and logical processor 1 is either
halted, under a machine clear condition or transitioning to a long
microcode flow.
6: ID
Logical processor 0 is either halted, under a machine clear condition
or transitioning to a long microcode flow. Logical processor 1 is in
deliver mode.
7: IB
Logical processor 0 is either halted, under a machine clear condition
or transitioning to a long microcode flow. Logical processor 1 is in
build mode.
01H
CCCR[15:13]
Event Specific
Notes
If only one logical processor is available from a physical processor
package, the event mask should be interpreted as logical processor 1
is halted. Event mask bit 2 was previously known as “DELIVER”, bit 5
was previously known as “BUILD”.
BPU_fetch_
request
19-174 Vol. 3B
This event counts instruction fetch requests of specified request
type by the Branch Prediction unit. Specify one or more mask bits to
qualify the request type(s).
ESCR restrictions
MSR_BPU_ESCR0
MSR_BPU_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
03H
ESCR1: 2, 3
ESCR[31:25]
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
ESCR Event Mask
CCCR Select
Description
ESCR[24:9]
Bit 0: TCMISS
Trace cache lookup miss
00H
CCCR[15:13]
ITLB_reference
This event counts translations using the Instruction Translation
Look-aside Buffer (ITLB).
ESCR restrictions
MSR_ITLB_ESCR0
MSR_ITLB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
18H
ESCR1: 2, 3
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
0: HIT
ITLB hit
1: MISS
ITLB miss
2: HIT_UC
Uncacheable ITLB hit
03H
CCCR[15:13]
Event Specific
Notes
All page references regardless of the page size are looked up as
actual 4-KByte pages. Use the page_walk_type event with the
ITMISS mask for a more conservative count.
memory_cancel
This event counts the canceling of various type of request in the
Data cache Address Control unit (DAC). Specify one or more mask
bits to select the type of requests that are canceled.
ESCR restrictions
MSR_DAC_ESCR0
MSR_DAC_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
02H
ESCR1: 10, 11
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
2: ST_RB_FULL
3: 64K_CONF
CCCR Select
05H
Event Specific
Notes
Replayed because no store request buffer is available.
Conflicts due to 64-KByte aliasing.
CCCR[15:13]
All_CACHE_MISS includes uncacheable memory in count.
memory_
complete
This event counts the completion of a load split, store split,
uncacheable (UC) split, or UC load. Specify one or more mask bits to
select the operations to be counted.
ESCR restrictions
MSR_SAAT_ESCR0
MSR_SAAT_ESCR1
Vol. 3B 19-175
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
08H
Description
ESCR1: 10, 11
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
0: LSC
Load split completed, excluding UC/WC loads.
Any split stores completed.
1: SSC
CCCR Select
02H
load_port_replay
CCCR[15:13]
This event counts replayed events at the load port. Specify one or
more mask bits to select the cause of the replay.
ESCR restrictions
MSR_SAAT_ESCR0
MSR_SAAT_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
04H
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
ESCR[31:25]
ESCR[24:9]
Bit 1: SPLIT_LD
Split load.
02H
CCCR[15:13]
Event Specific
Notes
Must use ESCR1 for at-retirement counting.
store_port_replay
This event counts replayed events at the store port. Specify one or
more mask bits to select the cause of the replay.
ESCR restrictions
MSR_SAAT_ESCR0
MSR_SAAT_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
05H
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
ESCR[31:25]
ESCR[24:9]
Bit 1: SPLIT_ST
Split store
02H
CCCR[15:13]
Event Specific
Notes
Must use ESCR1 for at-retirement counting.
MOB_load_replay
This event triggers if the memory order buffer (MOB) caused a load
operation to be replayed. Specify one or more mask bits to select the
cause of the replay.
ESCR restrictions
MSR_MOB_ESCR0
MSR_MOB_ESCR1
19-176 Vol. 3B
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
03H
ESCR1: 2, 3
ESCR[31:25]
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
ESCR Event Mask
Description
ESCR[24:9]
Bit
1: NO_STA
Replayed because of unknown store address.
Replayed because of unknown store data.
3: NO_STD
4: PARTIAL_DATA
CCCR Select
Replayed because of partially overlapped data access between the
load and store operations.
5: UNALGN_ADDR
Replayed because the lower 4 bits of the linear address do not
match between the load and store operations.
02H
CCCR[15:13]
page_walk_type
This event counts various types of page walks that the page miss
handler (PMH) performs.
ESCR restrictions
MSR_PMH_
ESCR0
MSR_PMH_
ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
01H
ESCR1: 2, 3
ESCR Event Mask
ESCR[31:25]
ESCR[24:9]
Bit
0: DTMISS
Page walk for a data TLB miss (either load or store).
Page walk for an instruction TLB miss.
1: ITMISS
CCCR Select
04H
BSQ_cache
_reference
CCCR[15:13]
This event counts cache references (2nd level cache or 3rd level
cache) as seen by the bus unit.
Specify one or more mask bit to select an access according to the
access type (read type includes both load and RFO, write type
includes writebacks and evictions) and the access result (hit, misses).
ESCR restrictions
MSR_BSU_
ESCR0
MSR_BSU_
ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
0CH
ESCR1: 2, 3
ESCR[31:25]
Vol. 3B 19-177
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
ESCR[24:9]
Bit
0: RD_2ndL_HITS
Read 2nd level cache hit Shared (includes load and RFO).
1: RD_2ndL_HITE
Read 2nd level cache hit Exclusive (includes load and RFO).
2: RD_2ndL_HITM
Read 2nd level cache hit Modified (includes load and RFO).
3: RD_3rdL_HITS
Read 3rd level cache hit Shared (includes load and RFO).
4: RD_3rdL_HITE
Read 3rd level cache hit Exclusive (includes load and RFO).
5: RD_3rdL_HITM
ESCR Event Mask
CCCR Select
Event Specific
Notes
Read 3rd level cache hit Modified (includes load and RFO).
8: RD_2ndL_MISS
Read 2nd level cache miss (includes load and RFO).
9: RD_3rdL_MISS
Read 3rd level cache miss (includes load and RFO).
10: WR_2ndL_MISS
A Writeback lookup from DAC misses the 2nd level cache (unlikely to
happen).
07H
CCCR[15:13]
1: The implementation of this event in current Pentium 4 and Xeon
processors treats either a load operation or a request for
ownership (RFO) request as a “read” type operation.
2: Currently this event causes both over and undercounting by as
much as a factor of two due to an erratum.
3: It is possible for a transaction that is started as a prefetch to
change the transaction's internal status, making it no longer a
prefetch. or change the access result status (hit, miss) as seen by
this event.
IOQ_allocation
This event counts the various types of transactions on the bus. A
count is generated each time a transaction is allocated into the IOQ
that matches the specified mask bits. An allocated entry can be a
sector (64 bytes) or a chunks of 8 bytes.
Requests are counted once per retry. The event mask bits constitute
4 bit fields. A transaction type is specified by interpreting the values
of each bit field.
Specify one or more event mask bits in a bit field to select the value
of the bit field.
Each field (bits 0-4 are one field) are independent of and can be
ORed with the others. The request type field is further combined
with bit 5 and 6 to form a binary expression. Bits 7 and 8 form a bit
field to specify the memory type of the target address.
Bits 13 and 14 form a bit field to specify the source agent of the
request. Bit 15 affects read operation only. The event is triggered by
evaluating the logical expression: (((Request type) OR Bit 5 OR Bit 6)
OR (Memory type)) AND (Source agent).
19-178 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
ESCR restrictions
MSR_FSB_ESCR0,
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1;
ESCR Event Select
03H
Description
ESCR1: 2, 3
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bits
CCCR Select
Event Specific
Notes
0-4 (single field)
Bus request type (use 00001 for invalid or default).
5: ALL_READ
Count read entries.
6: ALL_WRITE
Count write entries.
7: MEM_UC
Count UC memory access entries.
8: MEM_WC
Count WC memory access entries.
9: MEM_WT
Count write-through (WT) memory access entries.
10: MEM_WP
Count write-protected (WP) memory access entries.
11: MEM_WB
Count WB memory access entries.
13: OWN
Count all store requests driven by processor, as opposed to other
processor or DMA.
14: OTHER
Count all requests driven by other processors or DMA.
15: PREFETCH
Include HW and SW prefetch requests in the count.
06H
CCCR[15:13]
1: If PREFETCH bit is cleared, sectors fetched using prefetch are
excluded in the counts. If PREFETCH bit is set, all sectors or chunks
read are counted.
2: Specify the edge trigger in CCCR to avoid double counting.
3: The mapping of interpreted bit field values to transaction types
may differ with different processor model implementations of the
Pentium 4 processor family. Applications that program
performance monitoring events should use CPUID to determine
processor models when using this event. The logic equations that
trigger the event are model-specific (see 4a and 4b below).
4a:For Pentium 4 and Xeon Processors starting with CPUID Model
field encoding equal to 2 or greater, this event is triggered by
evaluating the logical expression ((Request type) and (Bit 5 or Bit
6) and (Memory type) and (Source agent)).
4b:For Pentium 4 and Xeon Processors with CPUID Model field
encoding less than 2, this event is triggered by evaluating the
logical expression [((Request type) or Bit 5 or Bit 6) or (Memory
type)] and (Source agent). Note that event mask bits for memory
type are ignored if either ALL_READ or ALL_WRITE is specified.
5: This event is known to ignore CPL in early implementations of
Pentium 4 and Xeon Processors. Both user requests and OS
requests are included in the count. This behavior is fixed starting
with Pentium 4 and Xeon Processors with CPUID signature F27H
(Family 15, Model 2, Stepping 7).
Vol. 3B 19-179
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
6: For write-through (WT) and write-protected (WP) memory types,
this event counts reads as the number of 64-byte sectors. Writes
are counted by individual chunks.
7: For uncacheable (UC) memory types, this event counts the
number of 8-byte chunks allocated.
8: For Pentium 4 and Xeon Processors with CPUID Signature less
than F27H, only MSR_FSB_ESCR0 is available.
IOQ_active_
entries
This event counts the number of entries (clipped at 15) in the IOQ
that are active. An allocated entry can be a sector (64 bytes) or a
chunks of 8 bytes.
The event must be programmed in conjunction with IOQ_allocation.
Specify one or more event mask bits to select the transactions that
is counted.
ESCR restrictions
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR1: 2, 3
ESCR Event Select
01AH
ESCR[30:25]
ESCR[24:9]
ESCR Event Mask
Bits
CCCR Select
Event Specific
Notes
0-4 (single field)
Bus request type (use 00001 for invalid or default).
5: ALL_READ
Count read entries.
6: ALL_WRITE
Count write entries.
7: MEM_UC
Count UC memory access entries.
8: MEM_WC
Count WC memory access entries.
9: MEM_WT
Count write-through (WT) memory access entries.
10: MEM_WP
Count write-protected (WP) memory access entries.
11: MEM_WB
Count WB memory access entries.
13: OWN
Count all store requests driven by processor, as opposed to other
processor or DMA.
14: OTHER
Count all requests driven by other processors or DMA.
15: PREFETCH
Include HW and SW prefetch requests in the count.
06H
CCCR[15:13]
1: Specified desired mask bits in ESCR0 and ESCR1.
2: See the ioq_allocation event for descriptions of the mask bits.
3: Edge triggering should not be used when counting cycles.
4: The mapping of interpreted bit field values to transaction types
may differ across different processor model implementations of
the Pentium 4 processor family. Applications that programs
performance monitoring events should use the CPUID instruction
to detect processor models when using this event. The logical
expression that triggers this event as describe below:
5a:For Pentium 4 and Xeon Processors starting with CPUID MODEL
field encoding equal to 2 or greater, this event is triggered by
evaluating the logical expression ((Request type) and (Bit 5 or Bit
6) and (Memory type) and (Source agent)).
19-180 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
5b:For Pentium 4 and Xeon Processors starting with CPUID MODEL
field encoding less than 2, this event is triggered by evaluating
the logical expression [((Request type) or Bit 5 or Bit 6) or
(Memory type)] and (Source agent). Event mask bits for memory
type are ignored if either ALL_READ or ALL_WRITE is specified.
5c: This event is known to ignore CPL in the current implementations
of Pentium 4 and Xeon Processors Both user requests and OS
requests are included in the count.
6: An allocated entry can be a full line (64 bytes) or in individual
chunks of 8 bytes.
FSB_data_
activity
This event increments once for each DRDY or DBSY event that
occurs on the front side bus. The event allows selection of a specific
DRDY or DBSY event.
ESCR restrictions
MSR_FSB_ESCR0
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
17H
ESCR1: 2, 3
ESCR Event Mask
ESCR[31:25]
ESCR[24:9]
Bit 0:
DRDY_DRV
Count when this processor drives data onto the bus - includes writes
and implicit writebacks.
Asserted two processor clock cycles for partial writes and 4
processor clocks (usually in consecutive bus clocks) for full line
writes.
1: DRDY_OWN
Count when this processor reads data from the bus - includes loads
and some PIC transactions. Asserted two processor clock cycles for
partial reads and 4 processor clocks (usually in consecutive bus
clocks) for full line reads.
Count DRDY events that we drive.
Count DRDY events sampled that we own.
2: DRDY_OTHER
Count when data is on the bus but not being sampled by the
processor. It may or may not be being driven by this processor.
Asserted two processor clock cycles for partial transactions and 4
processor clocks (usually in consecutive bus clocks) for full line
transactions.
3: DBSY_DRV
Count when this processor reserves the bus for use in the next bus
cycle in order to drive data. Asserted for two processor clock cycles
for full line writes and not at all for partial line writes.
May be asserted multiple times (in consecutive bus clocks) if we stall
the bus waiting for a cache lock to complete.
4: DBSY_OWN
Count when some agent reserves the bus for use in the next bus
cycle to drive data that this processor will sample.
Asserted for two processor clock cycles for full line writes and not at
all for partial line writes. May be asserted multiple times (all one bus
clock apart) if we stall the bus for some reason.
Vol. 3B 19-181
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
5:DBSY_OTHER
Count when some agent reserves the bus for use in the next bus
cycle to drive data that this processor will NOT sample. It may or may
not be being driven by this processor.
Asserted two processor clock cycles for partial transactions and 4
processor clocks (usually in consecutive bus clocks) for full line
transactions.
CCCR Select
06H
Event Specific
Notes
CCCR[15:13]
Specify edge trigger in the CCCR MSR to avoid double counting.
DRDY_OWN and DRDY_OTHER are mutually exclusive; similarly for
DBSY_OWN and DBSY_OTHER.
BSQ_allocation
This event counts allocations in the Bus Sequence Unit (BSQ)
according to the specified mask bit encoding. The event mask bits
consist of four sub-groups:
•
•
•
•
Request type.
Request length.
Memory type.
Sub-group consisting mostly of independent bits (bits 5, 6, 7, 8, 9,
and 10).
Specify an encoding for each sub-group.
ESCR restrictions
MSR_BSU_ESCR0
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
05H
ESCR[31:25]
ESCR Event Mask
19-182 Vol. 3B
Bit
ESCR[24:9]
0: REQ_TYPE0
1: REQ_TYPE1
Request type encoding (bit 0 and 1) are:
2: REQ_LEN0
3: REQ_LEN1
Request length encoding (bit 2, 3) are:
5: REQ_IO_TYPE
Request type is input or output.
6: REQ_LOCK_
TYPE
Request type is bus lock.
7: REQ_CACHE_
TYPE
Request type is cacheable.
8: REQ_SPLIT_
TYPE
9: REQ_DEM_TYPE
Request type is a bus 8-byte chunk split across 8-byte boundary.
10: REQ_ORD_
TYPE
Request is an ordered type.
0 – Read (excludes read invalidate).
1 – Read invalidate.
2 – Write (other than writebacks).
3 – Writeback (evicted from cache). (public)
0 – 0 chunks
1 – 1 chunks
3 – 8 chunks
Request type is a demand if set. Request type is HW.SW prefetch
if 0.
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
CCCR Select
Parameter Value
Description
11: MEM_TYPE0
12: MEM_TYPE1
13: MEM_TYPE2
Memory type encodings (bit 11-13) are:
07H
CCCR[15:13]
Event Specific
Notes
0 – UC
1 – WC
4 – WT
5 – WP
6 – WB
1: Specify edge trigger in CCCR to avoid double counting.
2: A writebacks to 3rd level cache from 2nd level cache counts as a
separate entry, this is in additional to the entry allocated for a
request to the bus.
3: A read request to WB memory type results in a request to the
64-byte sector, containing the target address, followed by a
prefetch request to an adjacent sector.
4: For Pentium 4 and Xeon processors with CPUID model encoding
value equals to 0 and 1, an allocated BSQ entry includes both the
demand sector and prefetched 2nd sector.
5: An allocated BSQ entry for a data chunk is any request less than
64 bytes.
6a:This event may undercount for requests of split type transactions
if the data address straddled across modulo-64 byte boundary.
6b:This event may undercount for requests of read request of
16-byte operands from WC or UC address.
6c: This event may undercount WC partial requests originated from
store operands that are
dwords.
bsq_active_
entries
This event represents the number of BSQ entries (clipped at 15)
currently active (valid) which meet the subevent mask criteria during
allocation in the BSQ. Active request entries are allocated on the BSQ
until de-allocated.
De-allocation of an entry does not necessarily imply the request is
filled. This event must be programmed in conjunction with
BSQ_allocation. Specify one or more event mask bits to select the
transactions that is counted.
ESCR restrictions
ESCR1
Counter numbers
per ESCR
ESCR1: 2, 3
ESCR Event Select
06H
ESCR Event Mask
CCCR Select
Event Specific
Notes
ESCR[30:25]
ESCR[24:9]
07H
CCCR[15:13]
1: Specified desired mask bits in ESCR0 and ESCR1.
2: See the BSQ_allocation event for descriptions of the mask bits.
3: Edge triggering should not be used when counting cycles.
4: This event can be used to estimate the latency of a transaction
from allocation to de-allocation in the BSQ. The latency observed
by BSQ_allocation includes the latency of FSB, plus additional
overhead.
Vol. 3B 19-183
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
5: Additional overhead may include the time it takes to issue two
requests (the sector by demand and the adjacent sector via
prefetch). Since adjacent sector prefetches have lower priority
that demand fetches, on a heavily used system there is a high
probability that the adjacent sector prefetch will have to wait
until the next bus arbitration.
6: For Pentium 4 and Xeon processors with CPUID model encoding
value less than 3, this event is updated every clock.
7: For Pentium 4 and Xeon processors with CPUID model encoding
value equals to 3 or 4, this event is updated every other clock.
SSE_input_assist
This event counts the number of times an assist is requested to
handle problems with input operands for SSE/SSE2/SSE3 operations;
most notably denormal source operands when the DAZ bit is not set.
Set bit 15 of the event mask to use this event.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
34H
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
ESCR[31:25]
ESCR[24:9]
15: ALL
Count assists for SSE/SSE2/SSE3 μops.
01H
CCCR[15:13]
Event Specific
Notes
1: Not all requests for assists are actually taken. This event is known
to overcount in that it counts requests for assists from
instructions on the non-retired path that do not incur a
performance penalty. An assist is actually taken only for nonbogus μops. Any appreciable counts for this event are an
indication that the DAZ or FTZ bit should be set and/or the source
code should be changed to eliminate the condition.
2: Two common situations for an SSE/SSE2/SSE3 operation needing
an assist are: (1) when a denormal constant is used as an input and
the Denormals-Are-Zero (DAZ) mode is not set, (2) when the input
operand uses the underflowed result of a previous
SSE/SSE2/SSE3 operation and neither the DAZ nor Flush-To-Zero
(FTZ) modes are set.
3: Enabling the DAZ mode prevents SSE/SSE2/SSE3 operations from
needing assists in the first situation. Enabling the FTZ mode
prevents SSE/SSE2/SSE3 operations from needing assists in the
second situation.
packed_SP_uop
19-184 Vol. 3B
This event increments for each packed single-precision μop,
specified through the event mask for detection.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
08H
ESCR1: 10, 11
ESCR[31:25]
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
ESCR Event Mask
CCCR Select
Description
ESCR[24:9]
Bit 15: ALL
Count all μops operating on packed single-precision operands.
01H
CCCR[15:13]
Event Specific
Notes
1: If an instruction contains more than one packed SP μops, each
packed SP μop that is specified by the event mask will be counted.
2: This metric counts instances of packed memory μops in a repeat
move string.
packed_DP_uop
This event increments for each packed double-precision μop,
specified through the event mask for detection.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
0CH
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
ESCR[31:25]
ESCR[24:9]
Bit 15: ALL
Count all μops operating on packed double-precision operands.
01H
CCCR[15:13]
Event Specific
Notes
If an instruction contains more than one packed DP μops, each
packed DP μop that is specified by the event mask will be counted.
scalar_SP_uop
This event increments for each scalar single-precision μop, specified
through the event mask for detection.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
0AH
ESCR1: 10, 11
ESCR Event Mask
ESCR[24:9]
Bit 15: ALL
CCCR Select
ESCR[31:25]
01H
Event Specific
Notes
Count all μops operating on scalar single-precision operands.
CCCR[15:13]
If an instruction contains more than one scalar SP μops, each scalar
SP μop that is specified by the event mask will be counted.
scalar_DP_uop
This event increments for each scalar double-precision μop, specified
through the event mask for detection.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
0EH
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
ESCR[31:25]
ESCR[24:9]
Bit 15: ALL
Count all μops operating on scalar double-precision operands.
01H
CCCR[15:13]
Vol. 3B 19-185
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Event Specific
Notes
Description
If an instruction contains more than one scalar DP μops, each scalar
DP μop that is specified by the event mask is counted.
64bit_MMX_uop
This event increments for each MMX instruction, which operate on
64-bit SIMD operands.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
02H
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
ESCR[31:25]
ESCR[24:9]
Bit 15: ALL
Count all μops operating on 64- bit SIMD integer operands in memory
or MMX registers.
01H
CCCR[15:13]
Event Specific
Notes
If an instruction contains more than one 64-bit MMX μops, each 64bit MMX μop that is specified by the event mask will be counted.
128bit_MMX_uop
This event increments for each integer SIMD SSE2 instruction, which
operate on 128-bit SIMD operands.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
1AH
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
ESCR[24:9]
Bit 15: ALL
Count all μops operating on 128-bit SIMD integer operands in
memory or XMM registers.
01H
CCCR[15:13]
Event Specific
Notes
If an instruction contains more than one 128-bit MMX μops, each
128-bit MMX μop that is specified by the event mask will be counted.
x87_FP_uop
This event increments for each x87 floating-point μop, specified
through the event mask for detection.
ESCR restrictions
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
04H
ESCR1: 10, 11
ESCR Event Mask
CCCR Select
19-186 Vol. 3B
ESCR[31:25]
ESCR[31:25]
ESCR[24:9]
Bit 15: ALL
Count all x87 FP μops.
01H
CCCR[15:13]
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Event Specific
Notes
Description
1: If an instruction contains more than one x87 FP μops, each x87
FP μop that is specified by the event mask will be counted.
2: This event does not count x87 FP μop for load, store, move
between registers.
TC_misc
This event counts miscellaneous events detected by the TC. The
counter will count twice for each occurrence.
ESCR restrictions
MSR_TC_ESCR0
MSR_TC_ESCR1
Counter numbers
per ESCR
ESCR0: 4, 5
ESCR Event Select
06H
ESCR[31:25]
CCCR Select
01H
CCCR[15:13]
ESCR1: 6, 7
ESCR Event Mask
ESCR[24:9]
Bit 4: FLUSH
global_power
_events
Number of flushes
This event accumulates the time during which a processor is not
stopped.
ESCR restrictions
MSR_FSB_ESCR0
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
013H
ESCR Event Mask
Bit 0: Running
ESCR1: 2, 3
ESCR[31:25]
ESCR[24:9]
The processor is active (includes the handling of HLT STPCLK and
throttling.
CCCR Select
06H
tc_ms_xfer
CCCR[15:13]
This event counts the number of times that uop delivery changed
from TC to MS ROM.
ESCR restrictions
MSR_MS_ESCR0
MSR_MS_ESCR1
Counter numbers
per ESCR
ESCR0: 4, 5
ESCR Event Select
05H
ESCR1: 6, 7
ESCR Event Mask
CCCR Select
ESCR[31:25]
ESCR[24:9]
Bit 0: CISC
A TC to MS transfer occurred.
0H
CCCR[15:13]
uop_queue_
writes
This event counts the number of valid uops written to the uop
queue. Specify one or more mask bits to select the source type of
writes.
ESCR restrictions
MSR_MS_ESCR0
MSR_MS_ESCR1
Counter numbers
per ESCR
ESCR0: 4, 5
ESCR1: 6, 7
Vol. 3B 19-187
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
ESCR Event Select
09H
ESCR[31:25]
ESCR Event Mask
ESCR[24:9]
Bit
0: FROM_TC_
BUILD
The uops being written are from TC build mode.
1: FROM_TC_
DELIVER
The uops being written are from TC deliver mode.
2: FROM_ROM
CCCR Select
0H
retired_mispred
The uops being written are from microcode ROM.
CCCR[15:13]
This event counts retiring mispredicted branches by type.
_branch_type
ESCR restrictions
MSR_TBPU_ESCR0
MSR_TBPU_ESCR1
Counter numbers
per ESCR
ESCR0: 4, 5
ESCR Event Select
05H
ESCR1: 6, 7
ESCR[30:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
1: CONDITIONAL
Conditional jumps.
2: CALL
Indirect call branches.
3: RETURN
Return branches.
4: INDIRECT
Returns, indirect calls, or indirect jumps.
02H
CCCR[15:13]
Event Specific
Notes
This event may overcount conditional branches if:
• Mispredictions cause the trace cache and delivery engine to build
new traces.
• When the processor's pipeline is being cleared.
retired_branch
This event counts retiring branches by type. Specify one or more
mask bits to qualify the branch by its type.
_type
ESCR restrictions
MSR_TBPU_ESCR0
MSR_TBPU_ESCR1
Counter numbers
per ESCR
ESCR0: 4, 5
ESCR Event Select
04H
ESCR1: 6, 7
ESCR[30:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
19-188 Vol. 3B
1: CONDITIONAL
Conditional jumps.
2: CALL
Direct or indirect calls.
3: RETURN
Return branches.
4: INDIRECT
Returns, indirect calls, or indirect jumps.
02H
CCCR[15:13]
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Event Specific
Notes
Description
This event may overcount conditional branches if :
• Mispredictions cause the trace cache and delivery engine to build
new traces.
• When the processor's pipeline is being cleared.
resource_stall
This event monitors the occurrence or latency of stalls in the
Allocator.
ESCR restrictions
MSR_ALF_ESCR0
MSR_ALF_ESCR1
Counter numbers
per ESCR
ESCR0: 12, 13, 16
ESCR1: 14, 15, 17
ESCR Event Select
01H
Event Masks
ESCR[30:25]
ESCR[24:9]
Bit
CCCR Select
5: SBFULL
A Stall due to lack of store buffers.
01H
CCCR[15:13]
Event Specific
Notes
This event may not be supported in all models of the processor
family.
WC_Buffer
This event counts Write Combining Buffer operations that are
selected by the event mask.
ESCR restrictions
MSR_DAC_ESCR0
MSR_DAC_ESCR1
Counter numbers
per ESCR
ESCR0: 8, 9
ESCR Event Select
05H
ESCR1: 10, 11
Event Masks
ESCR[30:25]
ESCR[24:9]
Bit
CCCR Select
0: WCB_EVICTS
WC Buffer evictions of all causes.
1: WCB_FULL_
EVICT
WC Buffer eviction: no WC buffer is available.
05H
CCCR[15:13]
Event Specific
Notes
This event is useful for detecting the subset of 64K aliasing cases
that are more costly (i.e. 64K aliasing cases involving stores) as long
as there are no significant contributions due to write combining
buffer full or hit-modified conditions.
b2b_cycles
This event can be configured to count the number back-to-back bus
cycles using sub-event mask bits 1 through 6.
ESCR restrictions
MSR_FSB_ESCR0
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
016H
ESCR[30:25]
Event Masks
Bit
ESCR[24:9]
ESCR1: 2, 3
Vol. 3B 19-189
PERFORMANCE-MONITORING EVENTS
Table 19-28. Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
CCCR Select
03H
CCCR[15:13]
Event Specific
Notes
This event may not be supported in all models of the processor
family.
bnr
This event can be configured to count bus not ready conditions using
sub-event mask bits 0 through 2.
ESCR restrictions
MSR_FSB_ESCR0
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
08H
ESCR[30:25]
Event Masks
Bit
ESCR[24:9]
CCCR Select
03H
CCCR[15:13]
ESCR1: 2, 3
Event Specific
Notes
This event may not be supported in all models of the processor
family.
snoop
This event can be configured to count snoop hit modified bus traffic
using sub-event mask bits 2, 6 and 7.
ESCR restrictions
MSR_FSB_ESCR0
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
06H
ESCR[30:25]
Event Masks
Bit
ESCR[24:9]
CCCR Select
03H
CCCR[15:13]
ESCR1: 2, 3
Event Specific
Notes
This event may not be supported in all models of the processor
family.
Response
This event can be configured to count different types of responses
using sub-event mask bits 1,2, 8, and 9.
ESCR restrictions
MSR_FSB_ESCR0
MSR_FSB_ESCR1
Counter numbers
per ESCR
ESCR0: 0, 1
ESCR Event Select
04H
ESCR[30:25]
Event Masks
Bit
ESCR[24:9]
CCCR Select
03H
CCCR[15:13]
Event Specific
Notes
19-190 Vol. 3B
ESCR1: 2, 3
This event may not be supported in all models of the processor
family.
PERFORMANCE-MONITORING EVENTS
Table 19-29. Performance Monitoring Events For Intel NetBurst® Microarchitecture
for At-Retirement Counting
Event Name
Event Parameters
Parameter Value
front_end_event
Description
This event counts the retirement of tagged μops, which are specified
through the front-end tagging mechanism. The event mask specifies
bogus or non-bogus μops.
ESCR restrictions
MSR_CRU_ESCR2
MSR_CRU_ESCR3
Counter numbers
per ESCR
ESCR2: 12, 13, 16
ESCR Event Select
08H
ESCR3: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
0: NBOGUS
The marked μops are not bogus.
1: BOGUS
The marked μops are bogus.
CCCR Select
05H
CCCR[15:13]
Can Support PEBS
Yes
Require Additional
MSRs for tagging
Selected ESCRs
and/or MSR_TC_
PRECISE_EVENT
execution_event
See list of metrics supported by Front_end tagging in Table A-3
This event counts the retirement of tagged μops, which are specified
through the execution tagging mechanism.
The event mask allows from one to four types of μops to be
specified as either bogus or non-bogus μops to be tagged.
ESCR restrictions
MSR_CRU_ESCR2
MSR_CRU_ESCR3
Counter numbers
per ESCR
ESCR2: 12, 13, 16
ESCR Event Select
0CH
ESCR3: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
0: NBOGUS0
The marked μops are not bogus.
1: NBOGUS1
The marked μops are not bogus.
2: NBOGUS2
The marked μops are not bogus.
3: NBOGUS3
The marked μops are not bogus.
4: BOGUS0
The marked μops are bogus.
5: BOGUS1
The marked μops are bogus.
6: BOGUS2
The marked μops are bogus.
7: BOGUS3
The marked μops are bogus.
05H
CCCR[15:13]
Event Specific
Notes
Can Support PEBS
Each of the 4 slots to specify the bogus/non-bogus μops must be
coordinated with the 4 TagValue bits in the ESCR (for example,
NBOGUS0 must accompany a ‘1’ in the lowest bit of the TagValue
field in ESCR, NBOGUS1 must accompany a ‘1’ in the next but lowest
bit of the TagValue field).
Yes
Vol. 3B 19-191
PERFORMANCE-MONITORING EVENTS
Table 19-29. Performance Monitoring Events For Intel NetBurst® Microarchitecture
for At-Retirement Counting (Contd.)
Event Name
Event Parameters
Require Additional
MSRs for tagging
Parameter Value
An ESCR for an
upstream event
replay_event
Description
See list of metrics supported by execution tagging in Table A-4.
This event counts the retirement of tagged μops, which are specified
through the replay tagging mechanism. The event mask specifies
bogus or non-bogus μops.
ESCR restrictions
MSR_CRU_ESCR2
MSR_CRU_ESCR3
Counter numbers
per ESCR
ESCR2: 12, 13, 16
ESCR Event Select
09H
ESCR3: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
0: NBOGUS
The marked μops are not bogus.
1: BOGUS
The marked μops are bogus.
05H
CCCR[15:13]
Event Specific
Notes
Supports counting tagged μops with additional MSRs.
Can Support PEBS
Yes
Require Additional
MSRs for tagging
IA32_PEBS_
ENABLE
See list of metrics supported by replay tagging in Table A-5.
MSR_PEBS_
MATRIX_VERT
Selected ESCR
instr_retired
This event counts instructions that are retired during a clock cycle.
Mask bits specify bogus or non-bogus (and whether they are tagged
using the front-end tagging mechanism).
ESCR restrictions
MSR_CRU_ESCR0
MSR_CRU_ESCR1
Counter numbers
per ESCR
ESCR0: 12, 13, 16
ESCR Event Select
02H
ESCR1: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
0: NBOGUSNTAG
1: NBOGUSTAG
2: BOGUSNTAG
3: BOGUSTAG
CCCR Select
Event Specific
Notes
04H
Non-bogus instructions that are not tagged.
Non-bogus instructions that are tagged.
Bogus instructions that are not tagged.
Bogus instructions that are tagged.
CCCR[15:13]
1: The event count may vary depending on the microarchitectural
states of the processor when the event detection is enabled.
2: The event may count more than once for some instructions with
complex uop flows and were interrupted before retirement.
19-192 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-29. Performance Monitoring Events For Intel NetBurst® Microarchitecture
for At-Retirement Counting (Contd.)
Event Name
Event Parameters
Can Support PEBS
Parameter Value
Description
No
uops_retired
This event counts μops that are retired during a clock cycle. Mask bits
specify bogus or non-bogus.
ESCR restrictions
MSR_CRU_ESCR0
MSR_CRU_ESCR1
Counter numbers
per ESCR
ESCR0: 12, 13, 16
ESCR Event Select
01H
ESCR1: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
0: NBOGUS
The marked μops are not bogus.
1: BOGUS
The marked μops are bogus.
04H
CCCR[15:13]
Event Specific
Notes
Can Support PEBS
P6: EMON_UOPS_RETIRED
No
uop_type
This event is used in conjunction with the front-end at-retirement
mechanism to tag load and store μops.
ESCR restrictions
MSR_RAT_ESCR0
MSR_RAT_ESCR1
Counter numbers
per ESCR
ESCR0: 12, 13, 16
ESCR Event Select
02H
ESCR1: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
1: TAGLOADS
The μop is a load operation.
2: TAGSTORES
The μop is a store operation.
02H
CCCR[15:13]
Event Specific
Notes
Can Support PEBS
Setting the TAGLOADS and TAGSTORES mask bits does not cause a
counter to increment. They are only used to tag uops.
No
branch_retired
This event counts the retirement of a branch. Specify one or more
mask bits to select any combination of taken, not-taken, predicted
and mispredicted.
ESCR restrictions
MSR_CRU_ESCR2
MSR_CRU_ESCR3
See Table 18-63 for the addresses of the ESCR MSRs
Counter numbers
per ESCR
ESCR2: 12, 13, 16
ESCR3: 14, 15, 17
The counter numbers associated with each ESCR are provided. The
performance counters and corresponding CCCRs can be obtained
from Table 18-63.
ESCR Event Select
06H
ESCR[31:25]
Vol. 3B 19-193
PERFORMANCE-MONITORING EVENTS
Table 19-29. Performance Monitoring Events For Intel NetBurst® Microarchitecture
for At-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
Description
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
0: MMNP
Branch not-taken predicted
1: MMNM
Branch not-taken mispredicted
2: MMTP
Branch taken predicted
3: MMTM
Branch taken mispredicted
05H
CCCR[15:13]
Event Specific
Notes
Can Support PEBS
P6: EMON_BR_INST_RETIRED
No
mispred_branch_
retired
This event represents the retirement of mispredicted branch
instructions.
ESCR restrictions
MSR_CRU_ESCR0
MSR_CRU_ESCR1
Counter numbers
per ESCR
ESCR0: 12, 13, 16
ESCR Event Select
03H
ESCR1: 14, 15, 17
ESCR Event Mask
ESCR[31:25]
ESCR[24:9]
Bit 0: NBOGUS
The retired instruction is not bogus.
CCCR Select
04H
CCCR[15:13]
Can Support PEBS
No
x87_assist
This event counts the retirement of x87 instructions that required
special handling.
Specifies one or more event mask bits to select the type of
assistance.
ESCR restrictions
MSR_CRU_ESCR2
MSR_CRU_ESCR3
Counter numbers
per ESCR
ESCR2: 12, 13, 16
ESCR Event Select
03H
ESCR3: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
19-194 Vol. 3B
0: FPSU
Handle FP stack underflow.
1: FPSO
Handle FP stack overflow.
2: POAO
Handle x87 output overflow.
3: POAU
Handle x87 output underflow.
4: PREA
Handle x87 input assist.
CCCR Select
05H
CCCR[15:13]
Can Support PEBS
No
PERFORMANCE-MONITORING EVENTS
Table 19-29. Performance Monitoring Events For Intel NetBurst® Microarchitecture
for At-Retirement Counting (Contd.)
Event Name
Event Parameters
Parameter Value
machine_clear
Description
This event increments according to the mask bit specified while the
entire pipeline of the machine is cleared. Specify one of the mask bit
to select the cause.
ESCR restrictions
MSR_CRU_ESCR2
MSR_CRU_ESCR3
Counter numbers
per ESCR
ESCR2: 12, 13, 16
ESCR Event Select
02H
ESCR3: 14, 15, 17
ESCR Event Mask
ESCR[31:25]
ESCR[24:9]
Bit
0: CLEAR
Counts for a portion of the many cycles while the machine is cleared
for any cause. Use Edge triggering for this bit only to get a count of
occurrence versus a duration.
2: MOCLEAR
Increments each time the machine is cleared due to memory ordering
issues.
6: SMCLEAR
Increments each time the machine is cleared due to self-modifying
code issues.
CCCR Select
05H
CCCR[15:13]
Can Support PEBS
No
Table 19-30. Intel NetBurst® Microarchitecture Model-Specific Performance Monitoring Events
(For Model Encoding 3, 4 or 6)
Event Name
Event Parameters
Parameter Value
instr_completed
Description
This event counts instructions that have completed and retired
during a clock cycle. Mask bits specify whether the instruction is
bogus or non-bogus and whether they are:
ESCR restrictions
MSR_CRU_ESCR0
MSR_CRU_ESCR1
Counter numbers
per ESCR
ESCR0: 12, 13, 16
ESCR Event Select
07H
ESCR1: 14, 15, 17
ESCR[31:25]
ESCR[24:9]
ESCR Event Mask
Bit
CCCR Select
0: NBOGUS
Non-bogus instructions
1: BOGUS
Bogus instructions
04H
CCCR[15:13]
Event Specific
Notes
Can Support PEBS
This metric differs from instr_retired, since it counts instructions
completed, rather than the number of times that instructions started.
No
Vol. 3B 19-195
PERFORMANCE-MONITORING EVENTS
Table 19-31. List of Metrics Available for Front_end Tagging (For Front_end Event Only)
Front-end metric1
MSR_
TC_PRECISE_EVENT
MSR Bit field
Additional MSR
Event mask value for
Front_end_event
memory_loads
None
Set TAGLOADS bit in ESCR corresponding to
event Uop_Type.
NBOGUS
memory_stores
None
Set TAGSTORES bit in the ESCR corresponding
to event Uop_Type.
NBOGUS
NOTES:
1. There may be some undercounting of front end events when there is an overflow or underflow of the floating point stack.
Table 19-32. List of Metrics Available for Execution Tagging (For Execution Event Only)
Execution metric
Upstream ESCR
TagValue in
Upstream ESCR
Event mask value for
execution_event
packed_SP_retired
Set ALL bit in event mask, TagUop bit in ESCR of
packed_SP_uop.
1
NBOGUS0
packed_DP_retired
Set ALL bit in event mask, TagUop bit in ESCR of
packed_DP_uop.
1
NBOGUS0
scalar_SP_retired
Set ALL bit in event mask, TagUop bit in ESCR of
scalar_SP_uop.
1
NBOGUS0
scalar_DP_retired
Set ALL bit in event mask, TagUop bit in ESCR of
scalar_DP_uop.
1
NBOGUS0
128_bit_MMX_retired
Set ALL bit in event mask, TagUop bit in ESCR of
128_bit_MMX_uop.
1
NBOGUS0
64_bit_MMX_retired
Set ALL bit in event mask, TagUop bit in ESCR of
64_bit_MMX_uop.
1
NBOGUS0
X87_FP_retired
Set ALL bit in event mask, TagUop bit in ESCR of
x87_FP_uop.
1
NBOGUS0
1
NBOGUS0
X87_SIMD_memory_m Set ALLP0, ALLP2 bits in event mask, TagUop bit in
oves_retired
ESCR of X87_SIMD_ moves_uop.
Table 19-33. List of Metrics Available for Replay Tagging (For Replay Event Only)
Replay metric1
IA32_PEBS_
ENABLE Field
to Set
MSR_PEBS_
MATRIX_VERT Bit
Field to Set
Additional MSR/ Event
Event Mask Value for
Replay_event
1stL_cache_load
_miss_retired
Bit 0, Bit 24,
Bit 25
Bit 0
None
NBOGUS
2ndL_cache_load
_miss_retired2
Bit 1, Bit 24,
Bit 25
Bit 0
None
NBOGUS
DTLB_load_miss
_retired
Bit 2, Bit 24,
Bit 25
Bit 0
None
NBOGUS
DTLB_store_miss
_retired
Bit 2, Bit 24,
Bit 25
Bit 1
None
NBOGUS
DTLB_all_miss
_retired
Bit 2, Bit 24,
Bit 25
Bit 0, Bit 1
None
NBOGUS
Tagged_mispred_
branch
Bit 15, Bit 16, Bit 24,
Bit 25
Bit 4
None
NBOGUS
19-196 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-33. List of Metrics Available for Replay Tagging (For Replay Event Only) (Contd.)
Replay metric1
IA32_PEBS_
ENABLE Field
to Set
MSR_PEBS_
MATRIX_VERT Bit
Field to Set
MOB_load
_replay_retired3
Bit 9, Bit 24,
Bit 25
Bit 0
Select MOB_load_replay
event and set
PARTIAL_DATA and
UNALGN_ADDR bit.
NBOGUS
split_load_retired
Bit 10, Bit 24,
Bit 25
Bit 0
Select load_port_replay
event with the
MSR_SAAT_ESCR1 MSR
and set the SPLIT_LD mask
bit.
NBOGUS
split_store_retired
Bit 10, Bit 24,
Bit 25
Bit 1
Select store_port_replay
event with the
MSR_SAAT_ESCR0 MSR
and set the SPLIT_ST mask
bit.
NBOGUS
Additional MSR/ Event
Event Mask Value for
Replay_event
NOTES:
1. Certain kinds of μops cannot be tagged. These include I/O operations, UC and locked accesses, returns, and far transfers.
2. 2nd-level misses retired does not count all 2nd-level misses. It only includes those references that are found to be misses by the fast
detection logic and not those that are later found to be misses.
3. While there are several causes for a MOB replay, the event counted with this event mask setting is the case where the data from a
load that would otherwise be forwarded is not an aligned subset of the data from a preceding store.
Vol. 3B 19-197
PERFORMANCE-MONITORING EVENTS
Table 19-34. Event Mask Qualification for Logical Processors
Event Type
Event Name
Event Masks, ESCR[24:9]
Non-Retirement
BPU_fetch_request
Bit 0: TCMISS
Non-Retirement
BSQ_allocation
Bit
Non-Retirement
Non-Retirement
BSQ_cache_reference
memory_cancel
TS or TI
TS
0: REQ_TYPE0
TS
1: REQ_TYPE1
TS
2: REQ_LEN0
TS
3: REQ_LEN1
TS
5: REQ_IO_TYPE
TS
6: REQ_LOCK_TYPE
TS
7: REQ_CACHE_TYPE
TS
8: REQ_SPLIT_TYPE
TS
9: REQ_DEM_TYPE
TS
10: REQ_ORD_TYPE
TS
11: MEM_TYPE0
TS
12: MEM_TYPE1
TS
13: MEM_TYPE2
TS
Bit
0: RD_2ndL_HITS
TS
1: RD_2ndL_HITE
TS
2: RD_2ndL_HITM
TS
3: RD_3rdL_HITS
TS
4: RD_3rdL_HITE
TS
5: RD_3rdL_HITM
TS
6: WR_2ndL_HIT
TS
7: WR_3rdL_HIT
TS
8: RD_2ndL_MISS
TS
9: RD_3rdL_MISS
TS
10: WR_2ndL_MISS
TS
11: WR_3rdL_MISS
TS
Bit
2: ST_RB_FULL
TS
3: 64K_CONF
TS
Non-Retirement
SSE_input_assist
Bit 15: ALL
TI
Non-Retirement
64bit_MMX_uop
Bit 15: ALL
TI
Non-Retirement
packed_DP_uop
Bit 15: ALL
TI
Non-Retirement
packed_SP_uop
Bit 15: ALL
TI
Non-Retirement
scalar_DP_uop
Bit 15: ALL
TI
Non-Retirement
scalar_SP_uop
Bit 15: ALL
TI
Non-Retirement
128bit_MMX_uop
Bit 15: ALL
TI
Non-Retirement
x87_FP_uop
Bit 15: ALL
TI
19-198 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-34. Event Mask Qualification for Logical Processors (Contd.)
Event Type
Event Name
Non-Retirement
x87_SIMD_moves_uop
Non-Retirement
FSB_data_activity
Event Masks, ESCR[24:9]
Bit
3: ALLP0
TI
4: ALLP2
TI
Bit
0: DRDY_DRV
Non-Retirement
Non-Retirement
IOQ_allocation
IOQ_active_entries
TS or TI
TI
1: DRDY_OWN
TI
2: DRDY_OTHER
TI
3: DBSY_DRV
TI
4: DBSY_OWN
TI
5: DBSY_OTHER
TI
Bit
0: ReqA0
TS
1: ReqA1
TS
2: ReqA2
TS
3: ReqA3
TS
4: ReqA4
TS
5: ALL_READ
TS
6: ALL_WRITE
TS
7: MEM_UC
TS
8: MEM_WC
TS
9: MEM_WT
TS
10: MEM_WP
TS
11: MEM_WB
TS
13: OWN
TS
14: OTHER
TS
15: PREFETCH
TS
Bit
TS
0: ReqA0
1:ReqA1
TS
2: ReqA2
TS
3: ReqA3
TS
4: ReqA4
TS
5: ALL_READ
TS
6: ALL_WRITE
TS
7: MEM_UC
TS
8: MEM_WC
TS
9: MEM_WT
TS
10: MEM_WP
TS
11: MEM_WB
TS
Vol. 3B 19-199
PERFORMANCE-MONITORING EVENTS
Table 19-34. Event Mask Qualification for Logical Processors (Contd.)
Event Type
Event Name
Event Masks, ESCR[24:9]
13: OWN
TS
14: OTHER
TS
15: PREFETCH
TS
TS
Non-Retirement
global_power_events
Bit 0: RUNNING
Non-Retirement
ITLB_reference
Bit
Non-Retirement
Non-Retirement
Non-Retirement
MOB_load_replay
page_walk_type
uop_type
TS or TI
0: HIT
TS
1: MISS
TS
2: HIT_UC
TS
Bit
1: NO_STA
TS
3: NO_STD
TS
4: PARTIAL_DATA
TS
5: UNALGN_ADDR
TS
Bit
0: DTMISS
TI
1: ITMISS
TI
Bit
1: TAGLOADS
TS
2: TAGSTORES
TS
Non-Retirement
load_port_replay
Bit 1: SPLIT_LD
TS
Non-Retirement
store_port_replay
Bit 1: SPLIT_ST
TS
Non-Retirement
memory_complete
Non-Retirement
Non-Retirement
19-200 Vol. 3B
retired_mispred_branch_
type
retired_branch_type
Bit
0: LSC
TS
1: SSC
TS
2: USC
TS
3: ULC
TS
Bit
0: UNCONDITIONAL
TS
1: CONDITIONAL
TS
2: CALL
TS
3: RETURN
TS
4: INDIRECT
TS
Bit
0: UNCONDITIONAL
TS
1: CONDITIONAL
TS
2: CALL
TS
3: RETURN
TS
4: INDIRECT
TS
PERFORMANCE-MONITORING EVENTS
Table 19-34. Event Mask Qualification for Logical Processors (Contd.)
Event Type
Event Name
Event Masks, ESCR[24:9]
Non-Retirement
tc_ms_xfer
Bit
0: CISC
Non-Retirement
tc_misc
Bit
4: FLUSH
Non-Retirement
Non-Retirement
TC_deliver_mode
uop_queue_writes
Bit
TS or TI
TS
TS
0: DD
TI
1: DB
TI
2: DI
TI
3: BD
TI
4: BB
TI
5: BI
TI
6: ID
TI
7: IB
TI
Bit
0: FROM_TC_BUILD
TS
1: FROM_TC_DELIVER
TS
2: FROM_ROM
TS
Non-Retirement
resource_stall
Bit 5: SBFULL
TS
Non-Retirement
WC_Buffer
Bit
TI
At Retirement
At Retirement
At Retirement
At Retirement
At Retirement
instr_retired
machine_clear
front_end_event
replay_event
execution_event
0: WCB_EVICTS
TI
1: WCB_FULL_EVICT
TI
2: WCB_HITM_EVICT
TI
Bit
0: NBOGUSNTAG
TS
1: NBOGUSTAG
TS
2: BOGUSNTAG
TS
3: BOGUSTAG
TS
Bit
0: CLEAR
TS
2: MOCLEAR
TS
6: SMCCLEAR
TS
Bit
0: NBOGUS
TS
1: BOGUS
TS
Bit
0: NBOGUS
TS
1: BOGUS
TS
Bit
0: NONBOGUS0
TS
1: NONBOGUS1
TS
Vol. 3B 19-201
PERFORMANCE-MONITORING EVENTS
Table 19-34. Event Mask Qualification for Logical Processors (Contd.)
Event Type
Event Name
At Retirement
At Retirement
x87_assist
branch_retired
At Retirement
mispred_branch_retired
At Retirement
uops_retired
At Retirement
19.16
instr_completed
Event Masks, ESCR[24:9]
TS or TI
2: NONBOGUS2
TS
3: NONBOGUS3
TS
4: BOGUS0
TS
5: BOGUS1
TS
6: BOGUS2
TS
7: BOGUS3
TS
Bit
0: FPSU
TS
1: FPSO
TS
2: POAO
TS
3: POAU
TS
4: PREA
TS
Bit
0: MMNP
TS
1: MMNM
TS
2: MMTP
TS
3: MMTM
TS
Bit 0: NBOGUS
TS
Bit
0: NBOGUS
TS
1: BOGUS
TS
Bit
0: NBOGUS
TS
1: BOGUS
TS
PERFORMANCE MONITORING EVENTS FOR INTEL® PENTIUM® M
PROCESSORS
The Pentium M processor’s performance-monitoring events are based on monitoring events for the P6 family of
processors. All of these performance events are model specific for the Pentium M processor and are not available in
this form in other processors. Table 19-35 lists the Performance-Monitoring events that were added in the Pentium
M processor.
19-202 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-35. Performance Monitoring Events on Intel® Pentium® M Processors
Name
Hex Values
Descriptions
Power Management
EMON_EST_TRANS
58H
Number of Enhanced Intel SpeedStep technology transitions:
Mask = 00H - All transitions
Mask = 02H - Only Frequency transitions
EMON_THERMAL_TRIP
59H
Duration/Occurrences in thermal trip; to count number of thermal trips: bit
22 in PerfEvtSel0/1 needs to be set to enable edge detect.
BR_INST_EXEC
88H
Branch instructions that were executed (not necessarily retired).
BR_MISSP_EXEC
89H
Branch instructions executed that were mispredicted at execution.
BR_BAC_MISSP_EXEC
8AH
Branch instructions executed that were mispredicted at front end (BAC).
BR_CND_EXEC
8BH
Conditional branch instructions that were executed.
BR_CND_MISSP_EXEC
8CH
Conditional branch instructions executed that were mispredicted.
BR_IND_EXEC
8DH
Indirect branch instructions executed.
BR_IND_MISSP_EXEC
8EH
Indirect branch instructions executed that were mispredicted.
BR_RET_EXEC
8FH
Return branch instructions executed.
BR_RET_MISSP_EXEC
90H
Return branch instructions executed that were mispredicted at execution.
BR_RET_BAC_MISSP_EXEC
91H
Return branch instructions executed that were mispredicted at front end
(BAC).
BR_CALL_EXEC
92H
CALL instruction executed.
BR_CALL_MISSP_EXEC
93H
CALL instruction executed and miss predicted.
BR_IND_CALL_EXEC
94H
Indirect CALL instructions executed.
EMON_SIMD_INSTR_RETIRED
CEH
Number of retired MMX instructions.
EMON_SYNCH_UOPS
D3H
Sync micro-ops
EMON_ESP_UOPS
D7H
Total number of micro-ops
EMON_FUSED_UOPS_RET
DAH
Number of retired fused micro-ops:
BPU
Decoder
Mask = 0 - Fused micro-ops
Mask = 1 - Only load+Op micro-ops
Mask = 2 - Only std+sta micro-ops
EMON_UNFUSION
DBH
Number of unfusion events in the ROB, happened on a FP exception to a
fused µop.
EMON_PREF_RQSTS_UP
F0H
Number of upward prefetches issued.
EMON_PREF_RQSTS_DN
F8H
Number of downward prefetches issued.
Prefetcher
Vol. 3B 19-203
PERFORMANCE-MONITORING EVENTS
A number of P6 family processor performance monitoring events are modified for the Pentium M processor. Table
19-36 lists the performance monitoring events that were changed in the Pentium M processor, and differ from
performance monitoring events for the P6 family of processors.
Table 19-36. Performance Monitoring Events Modified on Intel® Pentium® M Processors
Name
Hex
Values
Descriptions
CPU_CLK_UNHALTED
79H
Number of cycles during which the processor is not halted, and not in a thermal trip.
EMON_SSE_SSE2_INST_
RETIRED
D8H
Streaming SIMD Extensions Instructions Retired:
Mask = 0 – SSE packed single and scalar single
Mask = 1 – SSE scalar-single
Mask = 2 – SSE2 packed-double
Mask = 3 – SSE2 scalar-double
EMON_SSE_SSE2_COMP_INST_
RETIRED
D9H
Computational SSE Instructions Retired:
Mask = 0 – SSE packed single
Mask = 1 – SSE Scalar-single
Mask = 2 – SSE2 packed-double
Mask = 3 – SSE2 scalar-double
L2_LD
29H
L2 data loads
Mask[0] = 1 – count I state lines
L2_LINES_IN
24H
L2 lines allocated
Mask[1] = 1 – count S state lines
L2_LINES_OUT
26H
L2 lines evicted
Mask[2] = 1 – count E state lines
L2_M_LINES_OUT
27H
Lw M-state lines evicted
Mask[3] = 1 – count M state lines
Mask[5:4]:
00H – Excluding hardware-prefetched lines
01H - Hardware-prefetched lines only
02H/03H – All (HW-prefetched lines and non HW -Prefetched lines)
19.17
P6 FAMILY PROCESSOR PERFORMANCE-MONITORING EVENTS
Table 19-37 lists the events that can be counted with the performance-monitoring counters and read with the
RDPMC instruction for the P6 family processors. The unit column gives the microarchitecture or bus unit that
produces the event; the event number column gives the hexadecimal number identifying the event; the mnemonic
event name column gives the name of the event; the unit mask column gives the unit mask required (if any); the
description column describes the event; and the comments column gives additional information about the event.
All of these performance events are model specific for the P6 family processors and are not available in this form in
the Pentium 4 processors or the Pentium processors. Some events (such as those added in later generations of the
P6 family processors) are only available in specific processors in the P6 family. All performance event encodings not
listed in Table 19-37 are reserved and their use will result in undefined counter results.
See the end of the table for notes related to certain entries in the table.
19-204 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters
Unit
Data Cache
Unit (DCU)
Event Mnemonic Event
Num. Name
Unit
Mask
43H
00H
DATA_MEM_REFS
Description
Comments
All loads from any memory type. All stores
to any memory type. Each part of a split is
counted separately. The internal logic counts
not only memory loads and stores, but also
internal retries.
80-bit floating-point accesses are double
counted, since they are decomposed into a
16-bit exponent load and a 64-bit mantissa
load. Memory accesses are only counted
when they are actually performed (such as a
load that gets squashed because a previous
cache miss is outstanding to the same
address, and which finally gets performed, is
only counted once).
Does not include I/O accesses, or other
nonmemory accesses.
45H
DCU_LINES_IN
00H
Total lines allocated in DCU.
46H
DCU_M_LINES_IN
00H
Number of M state lines allocated in DCU.
47H
DCU_M_LINES_
OUT
00H
DCU_MISS_
OUTSTANDING
00H
48H
Number of M state lines evicted from DCU.
This includes evictions via snoop HITM,
intervention or replacement.
Weighted number of cycles while a DCU miss
is outstanding, incremented by the number
of outstanding cache misses at any
particular time.
An access that also misses the L2
is short-changed by 2 cycles (i.e., if
counts N cycles, should be N+2
cycles).
Cacheable read requests only are
considered.
Subsequent loads to the same
cache line will not result in any
additional counts.
Uncacheable requests are excluded.
Read-for-ownerships are counted, as well as
line fills, invalidates, and stores.
Instruction
Fetch Unit
(IFU)
80H
IFU_IFETCH
00H
Number of instruction fetches, both
cacheable and noncacheable, including UC
fetches.
81H
IFU_IFETCH_
MISS
00H
Number of instruction fetch misses
85H
ITLB_MISS
00H
Number of ITLB misses.
86H
IFU_MEM_STALL
00H
Number of cycles instruction fetch is stalled,
for any reason.
Count value not precise, but still
useful.
All instruction fetches that do not hit the IFU
(i.e., that produce memory requests). This
includes UC accesses.
Includes IFU cache misses, ITLB misses, ITLB
faults, and other minor stalls.
L2 Cache1
87H
ILD_STALL
00H
Number of cycles that the instruction length
decoder is stalled.
28H
L2_IFETCH
MESI
0FH
Number of L2 instruction fetches.
This event indicates that a normal
instruction fetch was received by the L2.
Vol. 3B 19-205
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Unit
Event Mnemonic Event
Num. Name
Unit
Mask
Description
Comments
The count includes only L2 cacheable
instruction fetches; it does not include UC
instruction fetches.
It does not include ITLB miss accesses.
29H
L2_LD
MESI
0FH
Number of L2 data loads.
This event indicates that a normal, unlocked,
load memory access was received by the L2.
It includes only L2 cacheable memory
accesses; it does not include I/O accesses,
other nonmemory accesses, or memory
accesses such as UC/WT memory accesses.
It does include L2 cacheable TLB miss
memory accesses.
2AH
L2_ST
MESI
0FH
Number of L2 data stores.
This event indicates that a normal, unlocked,
store memory access was received by the
L2.
it indicates that the DCU sent a read-forownership request to the L2. It also includes
Invalid to Modified requests sent by the DCU
to the L2.
It includes only L2 cacheable memory
accesses; it does not include I/O accesses,
other nonmemory accesses, or memory
accesses such as UC/WT memory accesses.
It includes TLB miss memory accesses.
External
Bus Logic
(EBL)2
19-206 Vol. 3B
24H
L2_LINES_IN
00H
Number of lines allocated in the L2.
26H
L2_LINES_OUT
00H
Number of lines removed from the L2 for
any reason.
25H
L2_M_LINES_INM
00H
Number of modified lines allocated in the L2.
27H
L2_M_LINES_
OUTM
00H
Number of modified lines removed from the
L2 for any reason.
2EH
L2_RQSTS
MESI
0FH
Total number of L2 requests.
21H
L2_ADS
00H
Number of L2 address strobes.
22H
L2_DBUS_BUSY
00H
Number of cycles during which the L2 cache
data bus was busy.
23H
L2_DBUS_BUSY_
RD
00H
Number of cycles during which the data bus
was busy transferring read data from L2 to
the processor.
62H
BUS_DRDY_
CLOCKS
00H
(Self)
Number of clocks during which DRDY# is
asserted.
20H
(Any)
Utilization of the external system data bus
during data transfers.
Unit Mask = 00H counts bus clocks
when the processor is driving
DRDY#.
Unit Mask = 20H counts in
processor clocks when any agent is
driving DRDY#.
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Unit
Event Mnemonic Event
Num. Name
Unit
Mask
Description
Comments
63H
00H
(Self)
Number of clocks during which LOCK# is
asserted on the external system bus.3
Always counts in processor clocks.
Counts only DCU full-line cacheable
reads, not RFOs, writes, instruction
fetches, or anything else. Counts
“waiting for bus to complete” (last
data chunk received).
BUS_LOCK_
CLOCKS
20H
(Any)
60H
65H
BUS_REQ_
OUTSTANDING
00H
(Self)
Number of bus requests outstanding.
BUS_TRAN_BRD
00H
(Self)
Number of burst read transactions.
This counter is incremented by the number
of cacheable read bus requests outstanding
in any given cycle.
20H
(Any)
66H
BUS_TRAN_RFO
00H
(Self)
Number of completed read for ownership
transactions.
20H
(Any)
67H
BUS_TRANS_WB
00H
(Self)
Number of completed write back
transactions.
20H
(Any)
68H
BUS_TRAN_
IFETCH
00H
(Self)
Number of completed instruction fetch
transactions.
20H
(Any)
69H
BUS_TRAN_INVA
L
00H
(Self)
Number of completed invalidate
transactions.
20H
(Any)
6AH
BUS_TRAN_PWR
00H
(Self)
Number of completed partial write
transactions.
20H
(Any)
6BH
BUS_TRANS_P
00H
(Self)
Number of completed partial transactions.
20H
(Any)
6CH
BUS_TRANS_IO
00H
(Self)
Number of completed I/O transactions.
20H
(Any)
6DH
BUS_TRAN_DEF
00H
(Self)
Number of completed deferred transactions.
20H
(Any)
Vol. 3B 19-207
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Unit
Event Mnemonic Event
Num. Name
Unit
Mask
6EH
00H
(Self)
BUS_TRAN_
BURST
Description
Comments
Number of completed burst transactions.
20H
(Any)
70H
BUS_TRAN_ANY
00H
(Self)
20H
(Any)
Number of all completed bus transactions.
Address bus utilization can be calculated
knowing the minimum address bus
occupancy.
Includes special cycles, etc.
6FH
BUS_TRAN_MEM
00H
(Self)
Number of completed memory transactions.
20H
(Any)
64H
BUS_DATA_RCV
00H
(Self)
Number of bus clock cycles during which this
processor is receiving data.
61H
BUS_BNR_DRV
00H
(Self)
Number of bus clock cycles during which this
processor is driving the BNR# pin.
7AH
BUS_HIT_DRV
00H
(Self)
Number of bus clock cycles during which this
processor is driving the HIT# pin.
Includes cycles due to snoop stalls.
The event counts correctly, but
BPMi (breakpoint monitor) pins
function as follows based on the
setting of the PC bits (bit 19 in the
PerfEvtSel0 and PerfEvtSel1
registers):
• If the core-clock-to- bus-clock
ratio is 2:1 or 3:1, and a PC bit is
set, the BPMi pins will be
asserted for a single clock when
the counters overflow.
• If the PC bit is clear, the
processor toggles the BPMi pins
when the counter overflows.
• If the clock ratio is not 2:1 or 3:1,
the BPMi pins will not function
for these performancemonitoring counter events.
7BH
BUS_HITM_DRV
00H
(Self)
Number of bus clock cycles during which this
processor is driving the HITM# pin.
Includes cycles due to snoop stalls.
The event counts correctly, but
BPMi (breakpoint monitor) pins
function as follows based on the
setting of the PC bits (bit 19 in the
PerfEvtSel0 and PerfEvtSel1
registers):
• If the core-clock-to- bus-clock
ratio is 2:1 or 3:1, and a PC bit is
set, the BPMi pins will be
asserted for a single clock when
the counters overflow.
19-208 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Unit
Event Mnemonic Event
Num. Name
Unit
Mask
Description
Comments
• If the PC bit is clear, the
processor toggles the BPMipins
when the counter overflows.
• If the clock ratio is not 2:1 or 3:1,
the BPMi pins will not function
for these performancemonitoring counter events.
FloatingPoint Unit
7EH
BUS_SNOOP_
STALL
00H
(Self)
Number of clock cycles during which the bus
is snoop stalled.
C1H
FLOPS
00H
Number of computational floating-point
operations retired.
Counter 0 only.
Excludes floating-point computational
operations that cause traps or assists.
Includes floating-point computational
operations executed by the assist handler.
Includes internal sub-operations for complex
floating-point instructions like
transcendentals.
Excludes floating-point loads and stores.
10H
FP_COMP_OPS_
EXE
00H
Number of computational floating-point
operations executed.
Counter 0 only.
The number of FADD, FSUB, FCOM, FMULs,
integer MULs and IMULs, FDIVs, FPREMs,
FSQRTS, integer DIVs, and IDIVs.
This number does not include the number of
cycles, but the number of operations.
This event does not distinguish an FADD
used in the middle of a transcendental flow
from a separate FADD instruction.
11H
12H
FP_ASSIST
MUL
00H
00H
Number of floating-point exception cases
handled by microcode.
Counter 1 only.
Number of multiplies.
Counter 1 only.
This event includes counts due to
speculative execution.
This count includes integer as well as FP
multiplies and is speculative.
13H
DIV
00H
Number of divides.
Counter 1 only.
This count includes integer as well as FP
divides and is speculative.
14H
CYCLES_DIV_
BUSY
00H
Number of cycles during which the divider is
busy, and cannot accept new divides.
Counter 0 only.
This includes integer and FP divides, FPREM,
FPSQRT, etc. and is speculative.
Vol. 3B 19-209
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Unit
Memory
Ordering
Event Mnemonic Event
Num. Name
Unit
Mask
03H
00H
LD_BLOCKS
Description
Comments
Number of load operations delayed due to
store buffer blocks.
Includes counts caused by preceding stores
whose addresses are unknown, preceding
stores whose addresses are known but
whose data is unknown, and preceding
stores that conflicts with the load but which
incompletely overlap the load.
04H
SB_DRAINS
00H
Number of store buffer drain cycles.
Incremented every cycle the store buffer is
draining.
Draining is caused by serializing operations
like CPUID, synchronizing operations like
XCHG, interrupt acknowledgment, as well as
other conditions (such as cache flushing).
05H
MISALIGN_
MEM_REF
00H
Number of misaligned data memory
references.
Incremented by 1 every cycle, during which
either the processor’s load or store pipeline
dispatches a misaligned μop.
Counting is performed if it is the first or
second half, or if it is blocked, squashed, or
missed.
MISALIGN_MEM_
REF is only an approximation to the
true number of misaligned memory
references.
The value returned is roughly
proportional to the number of
misaligned memory accesses (the
size of the problem).
In this context, misaligned means crossing a
64-bit boundary.
07H
EMON_KNI_PREF
_DISPATCHED
Number of Streaming SIMD extensions
prefetch/weakly-ordered instructions
dispatched (speculative prefetches are
included in counting):
00H
0: prefetch NTA
01H
1: prefetch T1
02H
2: prefetch T2
03H
4BH
Instruction
Decoding
and
Retirement
C0H
EMON_KNI_PREF
_MISS
INST_RETIRED
Counters 0 and 1. Pentium III
processor only.
3: weakly ordered stores
Number of prefetch/weakly-ordered
instructions that miss all caches:
00H
0: prefetch NTA
01H
1: prefetch T1
02H
2: prefetch T2
03H
3: weakly ordered stores
00H
Number of instructions retired.
Counters 0 and 1. Pentium III
processor only.
A hardware interrupt received
during/after the last iteration of
the REP STOS flow causes the
counter to undercount by 1
instruction.
An SMI received while executing a
HLT instruction will cause the
performance counter to not count
the RSM instruction and
undercount by 1.
19-210 Vol. 3B
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Unit
Event Mnemonic Event
Num. Name
Unit
Mask
Description
C2H
UOPS_RETIRED
00H
Number of μops retired.
D0H
INST_DECODED
00H
D8H
EMON_KNI_INST_
RETIRED
D9H
Number of instructions decoded.
Number of Streaming SIMD extensions
retired:
00H
0: packed & scalar
01H
1: scalar
EMON_KNI_
COMP_
INST_RET
Comments
Number of Streaming SIMD extensions
computation instructions retired:
Counters 0 and 1. Pentium III
processor only.
Counters 0 and 1. Pentium III
processor only.
0: packed and scalar
00H
1: scalar
01H
Interrupts
Branches
C8H
HW_INT_RX
00H
Number of hardware interrupts received.
C6H
CYCLES_INT_
MASKED
00H
Number of processor cycles for which
interrupts are disabled.
C7H
CYCLES_INT_
PENDING_
AND_MASKED
00H
Number of processor cycles for which
interrupts are disabled and interrupts are
pending.
C4H
BR_INST_
RETIRED
00H
Number of branch instructions retired.
C5H
BR_MISS_PRED_
RETIRED
00H
Number of mispredicted branches retired.
C9H
BR_TAKEN_
RETIRED
00H
Number of taken branches retired.
CAH
BR_MISS_PRED_
TAKEN_RET
00H
Number of taken mispredictions branches
retired.
E0H
BR_INST_
DECODED
00H
Number of branch instructions decoded.
E2H
BTB_MISSES
00H
Number of branches for which the BTB did
not produce a prediction.
E4H
BR_BOGUS
00H
Number of bogus branches.
E6H
BACLEARS
00H
Number of times BACLEAR is asserted.
This is the number of times that a static
branch prediction was made, in which the
branch decoder decided to make a branch
prediction because the BTB did not.
Stalls
A2H
RESOURCE_
STALLS
00H
Incremented by 1 during every cycle for
which there is a resource related stall.
Includes register renaming buffer entries,
memory buffer entries.
Vol. 3B 19-211
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Unit
Event Mnemonic Event
Num. Name
Unit
Mask
Description
Comments
Does not include stalls due to bus queue full,
too many cache misses, etc.
In addition to resource related stalls, this
event counts some other events.
Includes stalls arising during branch
misprediction recovery, such as if retirement
of the mispredicted branch is delayed and
stalls arising while store buffer is draining
from synchronizing operations.
D2H
PARTIAL_RAT_
STALLS
00H
Number of cycles or events for partial stalls.
This includes flag partial stalls.
Segment
Register
Loads
06H
SEGMENT_REG_
LOADS
00H
Number of segment register loads.
Clocks
79H
CPU_CLK_
UNHALTED
00H
Number of cycles during which the
processor is not halted.
MMX Unit
B0H
MMX_INSTR_
EXEC
00H
Number of MMX Instructions Executed.
Available in Intel Celeron, Pentium II
and Pentium II Xeon processors
only.
Does not account for MOVQ and
MOVD stores from register to
memory.
B1H
MMX_SAT_
INSTR_EXEC
00H
Number of MMX Saturating Instructions
Executed.
Available in Pentium II and Pentium
III processors only.
B2H
MMX_UOPS_
EXEC
0FH
Number of MMX μops Executed.
Available in Pentium II and Pentium
III processors only.
B3H
MMX_INSTR_
TYPE_EXEC
01H
MMX packed multiply instructions executed.
Available in Pentium II and Pentium
III processors only.
02H
MMX packed shift instructions executed.
MMX pack operation instructions executed.
04H
CCH
FP_MMX_TRANS
08H
MMX unpack operation instructions
executed.
10H
MMX packed logical instructions executed.
20H
MMX packed arithmetic instructions
executed.
00H
01H
Segment
Register
Renaming
19-212 Vol. 3B
Transitions from MMX instruction to
floating-point instructions.
Available in Pentium II and Pentium
III processors only.
Transitions from floating-point instructions
to MMX instructions.
CDH
MMX_ASSIST
00H
Number of MMX Assists (that is, the number
of EMMS instructions executed).
Available in Pentium II and Pentium
III processors only.
CEH
MMX_INSTR_RET
00H
Number of MMX Instructions Retired.
Available in Pentium II processors
only.
D4H
SEG_RENAME_
STALLS
Number of Segment Register Renaming
Stalls:
Available in Pentium II and Pentium
III processors only.
PERFORMANCE-MONITORING EVENTS
Table 19-37. Events That Can Be Counted with the P6 Family Performance-Monitoring Counters (Contd.)
Event Mnemonic Event
Num. Name
Unit
Unit
Mask
Description
02H
Segment register ES
04H
Segment register DS
08H
Segment register FS
0FH
Segment register FS
Comments
Segment registers
ES + DS + FS + GS
D5H
D6H
SEG_REG_
RENAMES
RET_SEG_
RENAMES
Number of Segment Register Renames:
01H
Segment register ES
02H
Segment register DS
04H
Segment register FS
08H
Segment register FS
0FH
Segment registers
ES + DS + FS + GS
00H
Number of segment register rename events
retired.
Available in Pentium II and Pentium
III processors only.
Available in Pentium II and Pentium
III processors only.
NOTES:
1. Several L2 cache events, where noted, can be further qualified using the Unit Mask (UMSK) field in the PerfEvtSel0 and
PerfEvtSel1 registers. The lower 4 bits of the Unit Mask field are used in conjunction with L2 events to indicate the cache state or
cache states involved.
The P6 family processors identify cache states using the “MESI” protocol and consequently each bit in the Unit Mask field represents one of the four states: UMSK[3] = M (8H) state, UMSK[2] = E (4H) state, UMSK[1] = S (2H) state, and UMSK[0] = I (1H) state.
UMSK[3:0] = MESI” (FH) should be used to collect data for all states; UMSK = 0H, for the applicable events, will result in nothing
being counted.
2. All of the external bus logic (EBL) events, except where noted, can be further qualified using the Unit Mask (UMSK) field in the
PerfEvtSel0 and PerfEvtSel1 registers.
Bit 5 of the UMSK field is used in conjunction with the EBL events to indicate whether the processor should count transactions that
are self- generated (UMSK[5] = 0) or transactions that result from any processor on the bus (UMSK[5] = 1).
3. L2 cache locks, so it is possible to have a zero count.
19.18
PENTIUM PROCESSOR PERFORMANCE-MONITORING EVENTS
Table 19-38 lists the events that can be counted with the performance-monitoring counters for the Pentium
processor. The Event Number column gives the hexadecimal code that identifies the event and that is entered in
the ES0 or ES1 (event select) fields of the CESR MSR. The Mnemonic Event Name column gives the name of the
event, and the Description and Comments columns give detailed descriptions of the events. Most events can be
counted with either counter 0 or counter 1; however, some events can only be counted with only counter 0 or only
counter 1 (as noted).
NOTE
The events in the table that are shaded are implemented only in the Pentium processor with MMX
technology.
Vol. 3B 19-213
PERFORMANCE-MONITORING EVENTS
Table 19-38. Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters
Event
Num.
Mnemonic Event
Name
Description
Comments
00H
DATA_READ
Number of memory data reads
(internal data cache hit and miss
combined).
Split cycle reads are counted individually. Data Memory
Reads that are part of TLB miss processing are not
included. These events may occur at a maximum of two
per clock. I/O is not included.
01H
DATA_WRITE
Number of memory data writes
(internal data cache hit and miss
combined); I/O not included.
Split cycle writes are counted individually. These events
may occur at a maximum of two per clock. I/O is not
included.
0H2
DATA_TLB_MISS
Number of misses to the data cache
translation look-aside buffer.
03H
DATA_READ_MISS
Number of memory read accesses that
miss the internal data cache whether
or not the access is cacheable or
noncacheable.
Additional reads to the same cache line after the first
BRDY# of the burst line fill is returned but before the final
(fourth) BRDY# has been returned, will not cause the
counter to be incremented additional times.
Data accesses that are part of TLB miss processing are
not included. Accesses directed to I/O space are not
included.
04H
DATA WRITE MISS
Number of memory write accesses
that miss the internal data cache
whether or not the access is cacheable
or noncacheable.
Data accesses that are part of TLB miss processing are
not included. Accesses directed to I/O space are not
included.
05H
WRITE_HIT_TO_
M-_OR_ESTATE_LINES
Number of write hits to exclusive or
modified lines in the data cache.
These are the writes that may be held up if EWBE# is
inactive. These events may occur a maximum of two per
clock.
06H
DATA_CACHE_
LINES_
WRITTEN_BACK
Number of dirty lines (all) that are
written back, regardless of the cause.
Replacements and internal and external snoops can all
cause writeback and are counted.
07H
EXTERNAL_
SNOOPS
Number of accepted external snoops
whether they hit in the code cache or
data cache or neither.
Assertions of EADS# outside of the sampling interval are
not counted, and no internal snoops are counted.
08H
EXTERNAL_DATA_
CACHE_SNOOP_
HITS
Number of external snoops to the data
cache.
Snoop hits to a valid line in either the data cache, the data
line fill buffer, or one of the write back buffers are all
counted as hits.
09H
MEMORY ACCESSES
IN BOTH PIPES
Number of data memory reads or
writes that are paired in both pipes of
the pipeline.
These accesses are not necessarily run in parallel due to
cache misses, bank conflicts, etc.
0AH
BANK CONFLICTS
Number of actual bank conflicts.
0BH
MISALIGNED DATA
MEMORY OR I/O
REFERENCES
Number of memory or I/O reads or
writes that are misaligned.
0CH
CODE READ
Number of instruction reads; whether Individual 8-byte noncacheable instruction reads are
the read is cacheable or noncacheable. counted.
0DH
CODE TLB MISS
Number of instruction reads that miss
the code TLB whether the read is
cacheable or noncacheable.
Individual 8-byte noncacheable instruction reads are
counted.
0EH
CODE CACHE MISS
Number of instruction reads that miss
the internal code cache; whether the
read is cacheable or noncacheable.
Individual 8-byte noncacheable instruction reads are
counted.
19-214 Vol. 3B
A 2- or 4-byte access is misaligned when it crosses a 4byte boundary; an 8-byte access is misaligned when it
crosses an 8-byte boundary. Ten byte accesses are
treated as two separate accesses of 8 and 2 bytes each.
PERFORMANCE-MONITORING EVENTS
Table 19-38. Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters (Contd.)
Event
Num.
Mnemonic Event
Name
0FH
ANY SEGMENT
REGISTER LOADED
10H
Reserved
11H
Reserved
12H
Branches
Description
Comments
Number of writes into any segment
register in real or protected mode
including the LDTR, GDTR, IDTR, and
TR.
Segment loads are caused by explicit segment register
load instructions, far control transfers, and task switches.
Far control transfers and task switches causing a privilege
level change will signal this event twice. Interrupts and
exceptions may initiate a far control transfer.
Number of taken and not taken
branches, including: conditional
branches, jumps, calls, returns,
software interrupts, and interrupt
returns.
Also counted as taken branches are serializing
instructions, VERR and VERW instructions, some segment
descriptor loads, hardware interrupts (including FLUSH#),
and programmatic exceptions that invoke a trap or fault
handler. The pipe is not necessarily flushed.
The number of branches actually executed is measured,
not the number of predicted branches.
13H
BTB_HITS
Number of BTB hits that occur.
Hits are counted only for those instructions that are
actually executed.
14H
TAKEN_BRANCH_
OR_BTB_HIT
Number of taken branches or BTB hits
that occur.
This event type is a logical OR of taken branches and BTB
hits. It represents an event that may cause a hit in the
BTB. Specifically, it is either a candidate for a space in the
BTB or it is already in the BTB.
15H
PIPELINE FLUSHES
Number of pipeline flushes that occur
The counter will not be incremented for serializing
instructions (serializing instructions cause the prefetch
queue to be flushed but will not trigger the Pipeline
Flushed event counter) and software interrupts (software
interrupts do not flush the pipeline).
Pipeline flushes are caused by BTB
misses on taken branches,
mispredictions, exceptions, interrupts,
and some segment descriptor loads.
16H
INSTRUCTIONS_
EXECUTED
Number of instructions executed (up
to two per clock).
Invocations of a fault handler are considered instructions.
All hardware and software interrupts and exceptions will
also cause the count to be incremented. Repeat prefixed
string instructions will only increment this counter once
despite the fact that the repeat loop executes the same
instruction multiple times until the loop criteria is
satisfied.
This applies to all the Repeat string instruction prefixes
(i.e., REP, REPE, REPZ, REPNE, and REPNZ). This counter
will also only increment once per each HLT instruction
executed regardless of how many cycles the processor
remains in the HALT state.
17H
INSTRUCTIONS_
EXECUTED_ V PIPE
Number of instructions executed in
the V_pipe.
The event indicates the number of
instructions that were paired.
18H
BUS_CYCLE_
DURATION
Number of clocks while a bus cycle is in
progress.
This event is the same as the 16H event except it only
counts the number of instructions actually executed in
the V-pipe.
The count includes HLDA, AHOLD, and BOFF# clocks.
This event measures bus use.
19H
WRITE_BUFFER_
FULL_STALL_
DURATION
Number of clocks while the pipeline is
stalled due to full write buffers.
Full write buffers stall data memory read misses, data
memory write misses, and data memory write hits to Sstate lines. Stalls on I/O accesses are not included.
Vol. 3B 19-215
PERFORMANCE-MONITORING EVENTS
Table 19-38. Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters (Contd.)
Event
Num.
Mnemonic Event
Name
Description
Comments
Data TLB Miss processing is also included in the count. The
pipeline stalls while a data memory read is in progress
including attempts to read that are not bypassed while a
line is being filled.
1AH
WAITING_FOR_
DATA_MEMORY_
READ_STALL_
DURATION
Number of clocks while the pipeline is
stalled while waiting for data memory
reads.
1BH
STALL ON WRITE
TO AN E- OR MSTATE LINE
Number of stalls on writes to E- or Mstate lines.
1CH
LOCKED BUS CYCLE
Number of locked bus cycles that occur
as the result of the LOCK prefix or
LOCK instruction, page-table updates,
and descriptor table updates.
Only the read portion of the locked read-modify-write is
counted. Split locked cycles (SCYC active) count as two
separate accesses. Cycles restarted due to BOFF# are not
re-counted.
1DH
I/O READ OR WRITE
CYCLE
Number of bus cycles directed to I/O
space.
Misaligned I/O accesses will generate two bus cycles. Bus
cycles restarted due to BOFF# are not re-counted.
1EH
NONCACHEABLE_
MEMORY_READS
Number of noncacheable instruction or
data memory read bus cycles.
Cycles restarted due to BOFF# are not re-counted.
The count includes read cycles caused
by TLB misses, but does not include
read cycles to I/O space.
1FH
PIPELINE_AGI_
STALLS
Number of address generation
interlock (AGI) stalls.
An AGI occurring in both the U- and Vpipelines in the same clock signals this
event twice.
20H
Reserved
21H
Reserved
22H
FLOPS
Number of floating-point operations
that occur.
An AGI occurs when the instruction in the execute stage
of either of U- or V-pipelines is writing to either the index
or base address register of an instruction in the D2
(address generation) stage of either the U- or V- pipelines.
Number of floating-point adds, subtracts, multiplies,
divides, remainders, and square roots are counted. The
transcendental instructions consist of multiple adds and
multiplies and will signal this event multiple times.
Instructions generating the divide-by-zero, negative
square root, special operand, or stack exceptions will not
be counted.
Instructions generating all other floating-point exceptions
will be counted. The integer multiply instructions and
other instructions which use the x87 FPU will be counted.
23H
BREAKPOINT
MATCH ON DR0
REGISTER
Number of matches on register DR0
breakpoint.
The counters is incremented regardless if the breakpoints
are enabled or not. However, if breakpoints are not
enabled, code breakpoint matches will not be checked for
instructions executed in the V-pipe and will not cause this
counter to be incremented. (They are checked on
instruction executed in the U-pipe only when breakpoints
are not enabled.)
These events correspond to the signals driven on the
BP[3:0] pins. Refer to Chapter 17, “Debug, Branch Profile,
TSC, and Resource Monitoring Features” for more
information.
24H
BREAKPOINT
MATCH ON DR1
REGISTER
19-216 Vol. 3B
Number of matches on register DR1
breakpoint.
See comment for 23H event.
PERFORMANCE-MONITORING EVENTS
Table 19-38. Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters (Contd.)
Event
Num.
Mnemonic Event
Name
Description
Comments
25H
BREAKPOINT
MATCH ON DR2
REGISTER
Number of matches on register DR2
breakpoint.
See comment for 23H event.
26H
BREAKPOINT
MATCH ON DR3
REGISTER
Number of matches on register DR3
breakpoint.
See comment for 23H event.
27H
HARDWARE
INTERRUPTS
Number of taken INTR and NMI
interrupts.
28H
DATA_READ_OR_
WRITE
Number of memory data reads and/or
writes (internal data cache hit and
miss combined).
Split cycle reads and writes are counted individually. Data
Memory Reads that are part of TLB miss processing are
not included. These events may occur at a maximum of
two per clock. I/O is not included.
29H
DATA_READ_MISS
OR_WRITE MISS
Number of memory read and/or write
accesses that miss the internal data
cache, whether or not the access is
cacheable or noncacheable.
Additional reads to the same cache line after the first
BRDY# of the burst line fill is returned but before the final
(fourth) BRDY# has been returned, will not cause the
counter to be incremented additional times.
Data accesses that are part of TLB miss processing are
not included. Accesses directed to I/O space are not
included.
2AH
BUS_OWNERSHIP_
LATENCY
(Counter 0)
The time from LRM bus ownership
request to bus ownership granted
(that is, the time from the earlier of a
PBREQ (0), PHITM# or HITM#
assertion to a PBGNT assertion)
The ratio of the 2AH events counted on counter 0 and
counter 1 is the average stall time due to bus ownership
conflict.
2AH
BUS OWNERSHIP
TRANSFERS
(Counter 1)
The number of buss ownership
transfers (that is, the number of
PBREQ (0) assertions
The ratio of the 2AH events counted on counter 0 and
counter 1 is the average stall time due to bus ownership
conflict.
2BH
MMX_
INSTRUCTIONS_
EXECUTED_
U-PIPE (Counter 0)
Number of MMX instructions executed
in the U-pipe
2BH
MMX_
INSTRUCTIONS_
EXECUTED_
V-PIPE (Counter 1)
Number of MMX instructions executed
in the V-pipe
2CH
CACHE_MSTATE_LINE_
SHARING
(Counter 0)
Number of times a processor identified
a hit to a modified line due to a
memory access in the other processor
(PHITM (O))
2CH
CACHE_LINE_
SHARING
(Counter 1)
Number of shared data lines in the L1
cache (PHIT (O))
2DH
EMMS_
INSTRUCTIONS_
EXECUTED (Counter
0)
Number of EMMS instructions
executed
If the average memory latencies of the system are known,
this event enables the user to count the Write Backs on
PHITM(O) penalty and the Latency on Hit Modified(I)
penalty.
Vol. 3B 19-217
PERFORMANCE-MONITORING EVENTS
Table 19-38. Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters (Contd.)
Event
Num.
2DH
Mnemonic Event
Name
Description
Comments
TRANSITIONS_
BETWEEN_MMX_
AND_FP_
INSTRUCTIONS
(Counter 1)
Number of transitions between MMX
and floating-point instructions or vice
versa
This event counts the first floating-point instruction
following an MMX instruction or first MMX instruction
following a floating-point instruction.
An even count indicates the processor
is in MMX state. an odd count indicates
it is in FP state.
The count may be used to estimate the penalty in
transitions between floating-point state and MMX state.
2EH
BUS_UTILIZATION_
DUE_TO_
PROCESSOR_
ACTIVITY
(Counter 0)
Number of clocks the bus is busy due
to the processor’s own activity (the
bus activity that is caused by the
processor)
2EH
WRITES_TO_
NONCACHEABLE_
MEMORY
(Counter 1)
Number of write accesses to
noncacheable memory
2FH
SATURATING_
MMX_
INSTRUCTIONS_
EXECUTED (Counter
0)
Number of saturating MMX
instructions executed, independently
of whether they actually saturated.
2FH
SATURATIONS_
PERFORMED
(Counter 1)
Number of MMX instructions that used
saturating arithmetic when at least
one of its results actually saturated
If an MMX instruction operating on 4 doublewords
saturated in three out of the four results, the counter will
be incremented by one only.
30H
NUMBER_OF_
CYCLES_NOT_IN_
HALT_STATE
(Counter 0)
Number of cycles the processor is not
idle due to HLT instruction
This event will enable the user to calculate “net CPI”. Note
that during the time that the processor is executing the
HLT instruction, the Time-Stamp Counter is not disabled.
Since this event is controlled by the Counter Controls CC0,
CC1 it can be used to calculate the CPI at CPL=3, which
the TSC cannot provide.
30H
DATA_CACHE_
TLB_MISS_
STALL_DURATION
(Counter 1)
Number of clocks the pipeline is stalled
due to a data cache translation lookaside buffer (TLB) miss
31H
MMX_
INSTRUCTION_
DATA_READS
(Counter 0)
Number of MMX instruction data reads
31H
MMX_
INSTRUCTION_
DATA_READ_
MISSES
(Counter 1)
Number of MMX instruction data read
misses
32H
FLOATING_POINT_S Number of clocks while pipe is stalled
TALLS_DURATION
due to a floating-point freeze
(Counter 0)
32H
TAKEN_BRANCHES
(Counter 1)
19-218 Vol. 3B
The count includes write cycles caused by TLB misses and
I/O write cycles.
Cycles restarted due to BOFF# are not re-counted.
Number of taken branches
PERFORMANCE-MONITORING EVENTS
Table 19-38. Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters (Contd.)
Event
Num.
Mnemonic Event
Name
Description
Comments
33H
D1_STARVATION_
AND_FIFO_IS_
EMPTY
(Counter 0)
Number of times D1 stage cannot
issue ANY instructions since the FIFO
buffer is empty
The D1 stage can issue 0, 1, or 2 instructions per clock if
those are available in an instructions FIFO buffer.
33H
D1_STARVATION_
AND_ONLY_ONE_
INSTRUCTION_IN_
FIFO
(Counter 1)
Number of times the D1 stage issues a
single instruction (since the FIFO
buffer had just one instruction ready)
The D1 stage can issue 0, 1, or 2 instructions per clock if
those are available in an instructions FIFO buffer.
34H
MMX_
INSTRUCTION_
DATA_WRITES
(Counter 0)
Number of data writes caused by MMX
instructions
34H
MMX_
INSTRUCTION_
DATA_WRITE_
MISSES
(Counter 1)
Number of data write misses caused
by MMX instructions
35H
PIPELINE_
FLUSHES_DUE_
TO_WRONG_
BRANCH_
PREDICTIONS
(Counter 0)
Number of pipeline flushes due to
wrong branch predictions resolved in
either the E-stage or the WB-stage
35H
PIPELINE_
FLUSHES_DUE_
TO_WRONG_
BRANCH_
PREDICTIONS_
RESOLVED_IN_
WB-STAGE
(Counter 1)
Number of pipeline flushes due to
wrong branch predictions resolved in
the WB-stage
36H
MISALIGNED_
DATA_MEMORY_
REFERENCE_ON_
MMX_
INSTRUCTIONS
(Counter 0)
Number of misaligned data memory
references when executing MMX
instructions
36H
PIPELINE_
ISTALL_FOR_MMX_
INSTRUCTION_
DATA_MEMORY_
READS
(Counter 1)
Number clocks during pipeline stalls
caused by waits form MMX instruction
data memory reads
When combined with the previously defined events,
Instruction Executed (16H) and Instruction Executed in
the V-pipe (17H), this event enables the user to calculate
the numbers of time pairing rules prevented issuing of
two instructions.
The count includes any pipeline flush due to a branch that
the pipeline did not follow correctly. It includes cases
where a branch was not in the BTB, cases where a branch
was in the BTB but was mispredicted, and cases where a
branch was correctly predicted but to the wrong address.
Branches are resolved in either the Execute stage
(E-stage) or the Writeback stage (WB-stage). In the later
case, the misprediction penalty is larger by one clock. The
difference between the 35H event count in counter 0 and
counter 1 is the number of E-stage resolved branches.
See note for event 35H (Counter 0).
T3:
Vol. 3B 19-219
PERFORMANCE-MONITORING EVENTS
Table 19-38. Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters (Contd.)
Event
Num.
Mnemonic Event
Name
Description
Comments
37H
MISPREDICTED_
OR_
UNPREDICTED_
RETURNS
(Counter 1)
Number of returns predicted
incorrectly or not predicted at all
The count is the difference between the total number of
executed returns and the number of returns that were
correctly predicted. Only RET instructions are counted (for
example, IRET instructions are not counted).
37H
PREDICTED_
RETURNS
(Counter 1)
Number of predicted returns (whether
they are predicted correctly and
incorrectly
Only RET instructions are counted (for example, IRET
instructions are not counted).
38H
MMX_MULTIPLY_
UNIT_INTERLOCK
(Counter 0)
Number of clocks the pipe is stalled
since the destination of previous MMX
multiply instruction is not ready yet
The counter will not be incremented if there is another
cause for a stall. For each occurrence of a multiply
interlock, this event will be counted twice (if the stalled
instruction comes on the next clock after the multiply) or
by once (if the stalled instruction comes two clocks after
the multiply).
38H
MOVD/MOVQ_
STORE_STALL_
DUE_TO_
PREVIOUS_MMX_
OPERATION
(Counter 1)
Number of clocks a MOVD/MOVQ
instruction store is stalled in D2 stage
due to a previous MMX operation with
a destination to be used in the store
instruction.
39H
RETURNS
(Counter 0)
Number or returns executed.
Only RET instructions are counted; IRET instructions are
not counted. Any exception taken on a RET instruction
and any interrupt recognized by the processor on the
instruction boundary prior to the execution of the RET
instruction will also cause this counter to be incremented.
39H
Reserved
3AH
BTB_FALSE_
ENTRIES
(Counter 0)
Number of false entries in the Branch
Target Buffer
False entries are causes for misprediction other than a
wrong prediction.
3AH
BTB_MISS_
PREDICTION_ON_
NOT-TAKEN_
BRANCH
(Counter 1)
Number of times the BTB predicted a
not-taken branch as taken
3BH
FULL_WRITE_
BUFFER_STALL_
DURATION_
WHILE_
EXECUTING_MMX_I
NSTRUCTIONS
(Counter 0)
Number of clocks while the pipeline is
stalled due to full write buffers while
executing MMX instructions
3BH
STALL_ON_MMX_
INSTRUCTION_
WRITE_TO E-_OR_
M-STATE_LINE
(Counter 1)
Number of clocks during stalls on MMX
instructions writing to E- or M-state
lines
19-220 Vol. 3B
CHAPTER 20
8086 EMULATION
IA-32 processors (beginning with the Intel386 processor) provide two ways to execute new or legacy programs
that are assembled and/or compiled to run on an Intel 8086 processor:
•
•
Real-address mode.
Virtual-8086 mode.
Figure 2-3 shows the relationship of these operating modes to protected mode and system management mode
(SMM).
When the processor is powered up or reset, it is placed in the real-address mode. This operating mode almost
exactly duplicates the execution environment of the Intel 8086 processor, with some extensions. Virtually any
program assembled and/or compiled to run on an Intel 8086 processor will run on an IA-32 processor in this mode.
When running in protected mode, the processor can be switched to virtual-8086 mode to run 8086 programs. This
mode also duplicates the execution environment of the Intel 8086 processor, with extensions. In virtual-8086
mode, an 8086 program runs as a separate protected-mode task. Legacy 8086 programs are thus able to run
under an operating system (such as Microsoft Windows*) that takes advantage of protected mode and to use
protected-mode facilities, such as the protected-mode interrupt- and exception-handling facilities. Protected-mode
multitasking permits multiple virtual-8086 mode tasks (with each task running a separate 8086 program) to be run
on the processor along with other non-virtual-8086 mode tasks.
This section describes both the basic real-address mode execution environment and the virtual-8086-mode execution environment, available on the IA-32 processors beginning with the Intel386 processor.
20.1
REAL-ADDRESS MODE
The IA-32 architecture’s real-address mode runs programs written for the Intel 8086, Intel 8088, Intel 80186, and
Intel 80188 processors, or for the real-address mode of the Intel 286, Intel386, Intel486, Pentium, P6 family,
Pentium 4, and Intel Xeon processors.
The execution environment of the processor in real-address mode is designed to duplicate the execution environment of the Intel 8086 processor. To an 8086 program, a processor operating in real-address mode behaves like a
high-speed 8086 processor. The principal features of this architecture are defined in Chapter 3, “Basic Execution
Environment”, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
The following is a summary of the core features of the real-address mode execution environment as would be seen
by a program written for the 8086:
•
The processor supports a nominal 1-MByte physical address space (see Section 20.1.1, “Address Translation in
Real-Address Mode”, for specific details). This address space is divided into segments, each of which can be up
to 64 KBytes in length. The base of a segment is specified with a 16-bit segment selector, which is zero
extended to form a 20-bit offset from address 0 in the address space. An operand within a segment is
addressed with a 16-bit offset from the base of the segment. A physical address is thus formed by adding the
offset to the 20-bit segment base (see Section 20.1.1, “Address Translation in Real-Address Mode”).
•
All operands in “native 8086 code” are 8-bit or 16-bit values. (Operand size override prefixes can be used to
access 32-bit operands.)
•
Eight 16-bit general-purpose registers are provided: AX, BX, CX, DX, SP, BP, SI, and DI. The extended 32 bit
registers (EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI) are accessible to programs that explicitly perform a size
override operation.
•
Four segment registers are provided: CS, DS, SS, and ES. (The FS and GS registers are accessible to programs
that explicitly access them.) The CS register contains the segment selector for the code segment; the DS and
ES registers contain segment selectors for data segments; and the SS register contains the segment selector
for the stack segment.
•
The 8086 16-bit instruction pointer (IP) is mapped to the lower 16-bits of the EIP register. Note this register is
a 32-bit register and unintentional address wrapping may occur.
Vol. 3B 20-1
8086 EMULATION
•
The 16-bit FLAGS register contains status and control flags. (This register is mapped to the 16 least significant
bits of the 32-bit EFLAGS register.)
•
All of the Intel 8086 instructions are supported (see Section 20.1.3, “Instructions Supported in Real-Address
Mode”).
•
A single, 16-bit-wide stack is provided for handling procedure calls and invocations of interrupt and exception
handlers. This stack is contained in the stack segment identified with the SS register. The SP (stack pointer)
register contains an offset into the stack segment. The stack grows down (toward lower segment offsets) from
the stack pointer. The BP (base pointer) register also contains an offset into the stack segment that can be used
as a pointer to a parameter list. When a CALL instruction is executed, the processor pushes the current
instruction pointer (the 16 least-significant bits of the EIP register and, on far calls, the current value of the CS
register) onto the stack. On a return, initiated with a RET instruction, the processor pops the saved instruction
pointer from the stack into the EIP register (and CS register on far returns). When an implicit call to an interrupt
or exception handler is executed, the processor pushes the EIP, CS, and EFLAGS (low-order 16-bits only)
registers onto the stack. On a return from an interrupt or exception handler, initiated with an IRET instruction,
the processor pops the saved instruction pointer and EFLAGS image from the stack into the EIP, CS, and
EFLAGS registers.
•
A single interrupt table, called the “interrupt vector table” or “interrupt table,” is provided for handling
interrupts and exceptions (see Figure 20-2). The interrupt table (which has 4-byte entries) takes the place of
the interrupt descriptor table (IDT, with 8-byte entries) used when handling protected-mode interrupts and
exceptions. Interrupt and exception vector numbers provide an index to entries in the interrupt table. Each
entry provides a pointer (called a “vector”) to an interrupt- or exception-handling procedure. See Section
20.1.4, “Interrupt and Exception Handling”, for more details. It is possible for software to relocate the IDT by
means of the LIDT instruction on IA-32 processors beginning with the Intel386 processor.
•
The x87 FPU is active and available to execute x87 FPU instructions in real-address mode. Programs written to
run on the Intel 8087 and Intel 287 math coprocessors can be run in real-address mode without modification.
The following extensions to the Intel 8086 execution environment are available in the IA-32 architecture’s realaddress mode. If backwards compatibility to Intel 286 and Intel 8086 processors is required, these features should
not be used in new programs written to run in real-address mode.
•
•
Two additional segment registers (FS and GS) are available.
•
The 32-bit operand prefix can be used in real-address mode programs to execute the 32-bit forms of instructions. This prefix also allows real-address mode programs to use the processor’s 32-bit general-purpose
registers.
•
The 32-bit address prefix can be used in real-address mode programs, allowing 32-bit offsets.
Many of the integer and system instructions that have been added to later IA-32 processors can be executed in
real-address mode (see Section 20.1.3, “Instructions Supported in Real-Address Mode”).
The following sections describe address formation, registers, available instructions, and interrupt and exception
handling in real-address mode. For information on I/O in real-address mode, see Chapter 18, “Input/Output”, of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
20.1.1
Address Translation in Real-Address Mode
In real-address mode, the processor does not interpret segment selectors as indexes into a descriptor table;
instead, it uses them directly to form linear addresses as the 8086 processor does. It shifts the segment selector
left by 4 bits to form a 20-bit base address (see Figure 20-1). The offset into a segment is added to the base
address to create a linear address that maps directly to the physical address space.
When using 8086-style address translation, it is possible to specify addresses larger than 1 MByte. For example,
with a segment selector value of FFFFH and an offset of FFFFH, the linear (and physical) address would be 10FFEFH
(1 megabyte plus 64 KBytes). The 8086 processor, which can form addresses only up to 20 bits long, truncates the
high-order bit, thereby “wrapping” this address to FFEFH. When operating in real-address mode, however, the
processor does not truncate such an address and uses it as a physical address. (Note, however, that for IA-32
processors beginning with the Intel486 processor, the A20M# signal can be used in real-address mode to mask
address line A20, thereby mimicking the 20-bit wrap-around behavior of the 8086 processor.) Care should be take
to ensure that A20M# based address wrapping is handled correctly in multiprocessor based system.
20-2 Vol. 3B
8086 EMULATION
19
4 3
Base
+
Offset
=
16-bit Segment Selector
19
0
0 0 0 0
16 15
0 0 0 0
0
16-bit Effective Address
19
Linear
Address
0
20-bit Linear Address
Figure 20-1. Real-Address Mode Address Translation
The IA-32 processors beginning with the Intel386 processor can generate 32-bit offsets using an address override
prefix; however, in real-address mode, the value of a 32-bit offset may not exceed FFFFH without causing an
exception.
For full compatibility with Intel 286 real-address mode, pseudo-protection faults (interrupt 12 or 13) occur if a 32bit offset is generated outside the range 0 through FFFFH.
20.1.2
Registers Supported in Real-Address Mode
The register set available in real-address mode includes all the registers defined for the 8086 processor plus the
new registers introduced in later IA-32 processors, such as the FS and GS segment registers, the debug registers,
the control registers, and the floating-point unit registers. The 32-bit operand prefix allows a real-address mode
program to use the 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI).
20.1.3
Instructions Supported in Real-Address Mode
The following instructions make up the core instruction set for the 8086 processor. If backwards compatibility to
the Intel 286 and Intel 8086 processors is required, only these instructions should be used in a new program
written to run in real-address mode.
•
Move (MOV) instructions that move operands between general-purpose registers, segment registers, and
between memory and general-purpose registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The exchange (XCHG) instruction.
Load segment register instructions LDS and LES.
Arithmetic instructions ADD, ADC, SUB, SBB, MUL, IMUL, DIV, IDIV, INC, DEC, CMP, and NEG.
Logical instructions AND, OR, XOR, and NOT.
Decimal instructions DAA, DAS, AAA, AAS, AAM, and AAD.
Stack instructions PUSH and POP (to general-purpose registers and segment registers).
Type conversion instructions CWD, CDQ, CBW, and CWDE.
Shift and rotate instructions SAL, SHL, SHR, SAR, ROL, ROR, RCL, and RCR.
TEST instruction.
Control instructions JMP, Jcc, CALL, RET, LOOP, LOOPE, and LOOPNE.
Interrupt instructions INT n, INTO, and IRET.
EFLAGS control instructions STC, CLC, CMC, CLD, STD, LAHF, SAHF, PUSHF, and POPF.
I/O instructions IN, INS, OUT, and OUTS.
Load effective address (LEA) instruction, and translate (XLATB) instruction.
Vol. 3B 20-3
8086 EMULATION
•
•
•
•
LOCK prefix.
Repeat prefixes REP, REPE, REPZ, REPNE, and REPNZ.
Processor halt (HLT) instruction.
No operation (NOP) instruction.
The following instructions, added to later IA-32 processors (some in the Intel 286 processor and the remainder in
the Intel386 processor), can be executed in real-address mode, if backwards compatibility to the Intel 8086
processor is not required.
•
•
•
•
•
•
•
•
•
•
Move (MOV) instructions that operate on the control and debug registers.
•
•
•
•
•
•
Double shift instructions SHLD and SHRD.
Load segment register instructions LSS, LFS, and LGS.
Generalized multiply instructions and multiply immediate data.
Shift and rotate by immediate counts.
Stack instructions PUSHA, PUSHAD, POPA and POPAD, and PUSH immediate data.
Move with sign extension instructions MOVSX and MOVZX.
Long-displacement Jcc instructions.
Exchange instructions CMPXCHG, CMPXCHG8B, and XADD.
String instructions MOVS, CMPS, SCAS, LODS, and STOS.
Bit test and bit scan instructions BT, BTS, BTR, BTC, BSF, and BSR; the byte-set-on condition instruction SETcc;
and the byte swap (BSWAP) instruction.
EFLAGS control instructions PUSHF and POPF.
ENTER and LEAVE control instructions.
BOUND instruction.
CPU identification (CPUID) instruction.
System instructions CLTS, INVD, WINVD, INVLPG, LGDT, SGDT, LIDT, SIDT, LMSW, SMSW, RDMSR, WRMSR,
RDTSC, and RDPMC.
Execution of any of the other IA-32 architecture instructions (not given in the previous two lists) in real-address
mode result in an invalid-opcode exception (#UD) being generated.
20.1.4
Interrupt and Exception Handling
When operating in real-address mode, software must provide interrupt and exception-handling facilities that are
separate from those provided in protected mode. Even during the early stages of processor initialization when the
processor is still in real-address mode, elementary real-address mode interrupt and exception-handling facilities
must be provided to insure reliable operation of the processor, or the initialization code must insure that no interrupts or exceptions will occur.
The IA-32 processors handle interrupts and exceptions in real-address mode similar to the way they handle them
in protected mode. When a processor receives an interrupt or generates an exception, it uses the vector number of
the interrupt or exception as an index into the interrupt table. (In protected mode, the interrupt table is called the
interrupt descriptor table (IDT), but in real-address mode, the table is usually called the interrupt vector
table, or simply the interrupt table.) The entry in the interrupt vector table provides a pointer to an interrupt- or
exception-handler procedure. (The pointer consists of a segment selector for a code segment and a 16-bit offset
into the segment.) The processor performs the following actions to make an implicit call to the selected handler:
1. Pushes the current values of the CS and EIP registers onto the stack. (Only the 16 least-significant bits of the
EIP register are pushed.)
2. Pushes the low-order 16 bits of the EFLAGS register onto the stack.
3. Clears the IF flag in the EFLAGS register to disable interrupts.
4. Clears the TF, RF, and AC flags, in the EFLAGS register.
20-4 Vol. 3B
8086 EMULATION
5. Transfers program control to the location specified in the interrupt vector table.
An IRET instruction at the end of the handler procedure reverses these steps to return program control to the interrupted program. Exceptions do not return error codes in real-address mode.
The interrupt vector table is an array of 4-byte entries (see Figure 20-2). Each entry consists of a far pointer to a
handler procedure, made up of a segment selector and an offset. The processor scales the interrupt or exception
vector by 4 to obtain an offset into the interrupt table. Following reset, the base of the interrupt vector table is
located at physical address 0 and its limit is set to 3FFH. In the Intel 8086 processor, the base address and limit of
the interrupt vector table cannot be changed. In the later IA-32 processors, the base address and limit of the interrupt vector table are contained in the IDTR register and can be changed using the LIDT instruction.
(For backward compatibility to Intel 8086 processors, the default base address and limit of the interrupt vector
table should not be changed.)
Up to Entry 255
Entry 3
12
Entry 2
8
Entry 1
4
Interrupt Vector 0*
Segment Selector
2
Offset
0
15
* Interrupt vector number 0 selects entry 0
(called “interrupt vector 0”) in the interrupt
vector table. Interrupt vector 0 in turn
points to the start of the interrupt handler
for interrupt 0.
0
IDTR
Figure 20-2. Interrupt Vector Table in Real-Address Mode
Table 20-1 shows the interrupt and exception vectors that can be generated in real-address mode and virtual-8086
mode, and in the Intel 8086 processor. See Chapter 6, “Interrupt and Exception Handling”, for a description of the
exception conditions.
20.2
VIRTUAL-8086 MODE
Virtual-8086 mode is actually a special type of a task that runs in protected mode. When the operating-system or
executive switches to a virtual-8086-mode task, the processor emulates an Intel 8086 processor. The execution
environment of the processor while in the 8086-emulation state is the same as is described in Section 20.1, “RealAddress Mode” for real-address mode, including the extensions. The major difference between the two modes is
that in virtual-8086 mode the 8086 emulator uses some protected-mode services (such as the protected-mode
interrupt and exception-handling and paging facilities).
Vol. 3B 20-5
8086 EMULATION
As in real-address mode, any new or legacy program that has been assembled and/or compiled to run on an Intel
8086 processor will run in a virtual-8086-mode task. And several 8086 programs can be run as virtual-8086-mode
tasks concurrently with normal protected-mode tasks, using the processor’s multitasking facilities.
Table 20-1. Real-Address Mode Exceptions and Interrupts
Vector
No.
Description
Real-Address Mode
Virtual-8086 Mode
Intel 8086 Processor
0
Divide Error (#DE)
Yes
Yes
Yes
1
Debug Exception (#DB)
Yes
Yes
No
2
NMI Interrupt
Yes
Yes
Yes
3
Breakpoint (#BP)
Yes
Yes
Yes
4
Overflow (#OF)
Yes
Yes
Yes
5
BOUND Range Exceeded (#BR)
Yes
Yes
Reserved
6
Invalid Opcode (#UD)
Yes
Yes
Reserved
7
Device Not Available (#NM)
Yes
Yes
Reserved
8
Double Fault (#DF)
Yes
Yes
Reserved
9
(Intel reserved. Do not use.)
Reserved
Reserved
Reserved
10
Invalid TSS (#TS)
Reserved
Yes
Reserved
11
Segment Not Present (#NP)
Reserved
Yes
Reserved
12
Stack Fault (#SS)
Yes
Yes
Reserved
13
General Protection (#GP)*
Yes
Yes
Reserved
14
Page Fault (#PF)
Reserved
Yes
Reserved
15
(Intel reserved. Do not use.)
Reserved
Reserved
Reserved
16
Floating-Point Error (#MF)
Yes
Yes
Reserved
17
Alignment Check (#AC)
Reserved
Yes
Reserved
18
Machine Check (#MC)
Yes
Yes
Reserved
19-31
(Intel reserved. Do not use.)
Reserved
Reserved
Reserved
32-255
User Defined Interrupts
Yes
Yes
Yes
NOTE:
* In the real-address mode, vector 13 is the segment overrun exception. In protected and virtual-8086 modes, this exception covers all general-protection error conditions, including traps to the virtual-8086 monitor from virtual-8086 mode.
20.2.1
Enabling Virtual-8086 Mode
The processor runs in virtual-8086 mode when the VM (virtual machine) flag in the EFLAGS register is set. This flag
can only be set when the processor switches to a new protected-mode task or resumes virtual-8086 mode via an
IRET instruction.
System software cannot change the state of the VM flag directly in the EFLAGS register (for example, by using the
POPFD instruction). Instead it changes the flag in the image of the EFLAGS register stored in the TSS or on the
stack following a call to an interrupt- or exception-handler procedure. For example, software sets the VM flag in the
EFLAGS image in the TSS when first creating a virtual-8086 task.
The processor tests the VM flag under three general conditions:
•
•
When loading segment registers, to determine whether to use 8086-style address translation.
When decoding instructions, to determine which instructions are not supported in virtual-8086 mode and which
instructions are sensitive to IOPL.
20-6 Vol. 3B
8086 EMULATION
•
When checking privileged instructions, on page accesses, or when performing other permission checks.
(Virtual-8086 mode always executes at CPL 3.)
20.2.2
Structure of a Virtual-8086 Task
A virtual-8086-mode task consists of the following items:
•
•
•
•
A 32-bit TSS for the task.
The 8086 program.
A virtual-8086 monitor.
8086 operating-system services.
The TSS of the new task must be a 32-bit TSS, not a 16-bit TSS, because the 16-bit TSS does not load the mostsignificant word of the EFLAGS register, which contains the VM flag. All TSS’s, stacks, data, and code used to handle
exceptions when in virtual-8086 mode must also be 32-bit segments.
The processor enters virtual-8086 mode to run the 8086 program and returns to protected mode to run the virtual8086 monitor.
The virtual-8086 monitor is a 32-bit protected-mode code module that runs at a CPL of 0. The monitor consists of
initialization, interrupt- and exception-handling, and I/O emulation procedures that emulate a personal computer
or other 8086-based platform. Typically, the monitor is either part of or closely associated with the protected-mode
general-protection (#GP) exception handler, which also runs at a CPL of 0. As with any protected-mode code
module, code-segment descriptors for the virtual-8086 monitor must exist in the GDT or in the task’s LDT. The
virtual-8086 monitor also may need data-segment descriptors so it can examine the IDT or other parts of the 8086
program in the first 1 MByte of the address space. The linear addresses above 10FFEFH are available for the
monitor, the operating system, and other system software.
The 8086 operating-system services consists of a kernel and/or operating-system procedures that the 8086
program makes calls to. These services can be implemented in either of the following two ways:
•
They can be included in the 8086 program. This approach is desirable for either of the following reasons:
— The 8086 program code modifies the 8086 operating-system services.
— There is not sufficient development time to merge the 8086 operating-system services into main operating
system or executive.
•
They can be implemented or emulated in the virtual-8086 monitor. This approach is desirable for any of the
following reasons:
— The 8086 operating-system procedures can be more easily coordinated among several virtual-8086 tasks.
— Memory can be saved by not duplicating 8086 operating-system procedure code for several virtual-8086
tasks.
— The 8086 operating-system procedures can be easily emulated by calls to the main operating system or
executive.
The approach chosen for implementing the 8086 operating-system services may result in different virtual-8086mode tasks using different 8086 operating-system services.
20.2.3
Paging of Virtual-8086 Tasks
Even though a program running in virtual-8086 mode can use only 20-bit linear addresses, the processor converts
these addresses into 32-bit linear addresses before mapping them to the physical address space. If paging is being
used, the 8086 address space for a program running in virtual-8086 mode can be paged and located in a set of
pages in physical address space. If paging is used, it is transparent to the program running in virtual-8086 mode
just as it is for any task running on the processor.
Paging is not necessary for a single virtual-8086-mode task, but paging is useful or necessary in the following situations:
Vol. 3B 20-7
8086 EMULATION
•
When running multiple virtual-8086-mode tasks. Here, paging allows the lower 1 MByte of the linear address
space for each virtual-8086-mode task to be mapped to a different physical address location.
•
When emulating the 8086 address-wraparound that occurs at 1 MByte. When using 8086-style address translation, it is possible to specify addresses larger than 1 MByte. These addresses automatically wraparound in the
Intel 8086 processor (see Section 20.1.1, “Address Translation in Real-Address Mode”). If any 8086 programs
depend on address wraparound, the same effect can be achieved in a virtual-8086-mode task by mapping the
linear addresses between 100000H and 110000H and linear addresses between 0 and 10000H to the same
physical addresses.
•
When sharing the 8086 operating-system services or ROM code that is common to several 8086 programs
running as different 8086-mode tasks.
•
When redirecting or trapping references to memory-mapped I/O devices.
20.2.4
Protection within a Virtual-8086 Task
Protection is not enforced between the segments of an 8086 program. Either of the following techniques can be
used to protect the system software running in a virtual-8086-mode task from the 8086 program:
•
Reserve the first 1 MByte plus 64 KBytes of each task’s linear address space for the 8086 program. An 8086
processor task cannot generate addresses outside this range.
•
Use the U/S flag of page-table entries to protect the virtual-8086 monitor and other system software in the
virtual-8086 mode task space. When the processor is in virtual-8086 mode, the CPL is 3. Therefore, an 8086
processor program has only user privileges. If the pages of the virtual-8086 monitor have supervisor privilege,
they cannot be accessed by the 8086 program.
20.2.5
Entering Virtual-8086 Mode
Figure 20-3 summarizes the methods of entering and leaving virtual-8086 mode. The processor switches to
virtual-8086 mode in either of the following situations:
•
Task switch when the VM flag is set to 1 in the EFLAGS register image stored in the TSS for the task. Here the
task switch can be initiated in either of two ways:
— A CALL or JMP instruction.
— An IRET instruction, where the NT flag in the EFLAGS image is set to 1.
•
Return from a protected-mode interrupt or exception handler when the VM flag is set to 1 in the EFLAGS
register image on the stack.
When a task switch is used to enter virtual-8086 mode, the TSS for the virtual-8086-mode task must be a 32-bit
TSS. (If the new TSS is a 16-bit TSS, the upper word of the EFLAGS register is not in the TSS, causing the processor
to clear the VM flag when it loads the EFLAGS register.) The processor updates the VM flag prior to loading the
segment registers from their images in the new TSS. The new setting of the VM flag determines whether the
processor interprets the contents of the segment registers as 8086-style segment selectors or protected-mode
segment selectors. When the VM flag is set, the segment registers are loaded from the TSS, using 8086-style
address translation to form base addresses.
See Section 20.3, “Interrupt and Exception Handling in Virtual-8086 Mode”, for information on entering virtual8086 mode on a return from an interrupt or exception handler.
20-8 Vol. 3B
8086 EMULATION
Real Mode
Code
Real-Address
Mode
PE=0 or
RESET
PE=1
Protected
Mode
ProtectedMode Tasks
Task Switch1
Task Switch
VM=0
ProtectedMode Interrupt
and Exception
Handlers
CALL
Virtual-8086
Monitor
RET
VM = 0
VM = 1
Virtual-8086
Mode
Interrupt or
Exception2
RESET
Virtual-8086
Mode Tasks
(8086
Programs)
#GP Exception3
IRET4
IRET5
Redirect Interrupt to 8086 Program
Interrupt or Exception Handler6
NOTES:
1. Task switch carried out in either of two ways:
- CALL or JMP where the VM flag in the EFLAGS image is 1.
- IRET where VM is 1 and NT is 1.
2. Hardware interrupt or exception; software interrupt (INT n) when IOPL is 3.
3. General-protection exception caused by software interrupt (INT n), IRET,
POPF, PUSHF, IN, or OUT when IOPL is less than 3.
4. Normal return from protected-mode interrupt or exception handler.
5. A return from the 8086 monitor to redirect an interrupt or exception back
to an interrupt or exception handler in the 8086 program running in virtual8086 mode.
6. Internal redirection of a software interrupt (INT n) when VME is 1,
IOPL is <3, and the redirection bit is 1.
Figure 20-3. Entering and Leaving Virtual-8086 Mode
20.2.6
Leaving Virtual-8086 Mode
The processor can leave the virtual-8086 mode only through an interrupt or exception. The following are situations
where an interrupt or exception will lead to the processor leaving virtual-8086 mode (see Figure 20-3):
•
The processor services a hardware interrupt generated to signal the suspension of execution of the virtual8086 application. This hardware interrupt may be generated by a timer or other external mechanism. Upon
receiving the hardware interrupt, the processor enters protected mode and switches to a protected-mode (or
another virtual-8086 mode) task either through a task gate in the protected-mode IDT or through a trap or
interrupt gate that points to a handler that initiates a task switch. A task switch from a virtual-8086 task to
another task loads the EFLAGS register from the TSS of the new task. The value of the VM flag in the new
EFLAGS determines if the new task executes in virtual-8086 mode or not.
•
The processor services an exception caused by code executing the virtual-8086 task or services a hardware
interrupt that “belongs to” the virtual-8086 task. Here, the processor enters protected mode and services the
Vol. 3B 20-9
8086 EMULATION
exception or hardware interrupt through the protected-mode IDT (normally through an interrupt or trap gate)
and the protected-mode exception- and interrupt-handlers. The processor may handle the exception or
interrupt within the context of the virtual 8086 task and return to virtual-8086 mode on a return from the
handler procedure. The processor may also execute a task switch and handle the exception or interrupt in the
context of another task.
•
The processor services a software interrupt generated by code executing in the virtual-8086 task (such as a
software interrupt to call a MS-DOS* operating system routine). The processor provides several methods of
handling these software interrupts, which are discussed in detail in Section 20.3.3, “Class 3—Software
Interrupt Handling in Virtual-8086 Mode”. Most of them involve the processor entering protected mode, often
by means of a general-protection (#GP) exception. In protected mode, the processor can send the interrupt to
the virtual-8086 monitor for handling and/or redirect the interrupt back to the application program running in
virtual-8086 mode task for handling.
IA-32 processors that incorporate the virtual mode extension (enabled with the VME flag in control register
CR4) are capable of redirecting software-generated interrupts back to the program’s interrupt handlers without
leaving virtual-8086 mode. See Section 20.3.3.4, “Method 5: Software Interrupt Handling”, for more
information on this mechanism.
•
A hardware reset initiated by asserting the RESET or INIT pin is a special kind of interrupt. When a RESET or
INIT is signaled while the processor is in virtual-8086 mode, the processor leaves virtual-8086 mode and enters
real-address mode.
•
Execution of the HLT instruction in virtual-8086 mode will cause a general-protection (GP#) fault, which the
protected-mode handler generally sends to the virtual-8086 monitor. The virtual-8086 monitor then
determines the correct execution sequence after verifying that it was entered as a result of a HLT execution.
See Section 20.3, “Interrupt and Exception Handling in Virtual-8086 Mode”, for information on leaving virtual-8086
mode to handle an interrupt or exception generated in virtual-8086 mode.
20.2.7
Sensitive Instructions
When an IA-32 processor is running in virtual-8086 mode, the CLI, STI, PUSHF, POPF, INT n, and IRET instructions
are sensitive to IOPL. The IN, INS, OUT, and OUTS instructions, which are sensitive to IOPL in protected mode, are
not sensitive in virtual-8086 mode.
The CPL is always 3 while running in virtual-8086 mode; if the IOPL is less than 3, an attempt to use the IOPLsensitive instructions listed above triggers a general-protection exception (#GP). These instructions are sensitive
to IOPL to give the virtual-8086 monitor a chance to emulate the facilities they affect.
20.2.8
Virtual-8086 Mode I/O
Many 8086 programs written for non-multitasking systems directly access I/O ports. This practice may cause problems in a multitasking environment. If more than one program accesses the same port, they may interfere with
each other. Most multitasking systems require application programs to access I/O ports through the operating
system. This results in simplified, centralized control.
The processor provides I/O protection for creating I/O that is compatible with the environment and transparent to
8086 programs. Designers may take any of several possible approaches to protecting I/O ports:
•
•
•
•
Protect the I/O address space and generate exceptions for all attempts to perform I/O directly.
Let the 8086 program perform I/O directly.
Generate exceptions on attempts to access specific I/O ports.
Generate exceptions on attempts to access specific memory-mapped I/O ports.
The method of controlling access to I/O ports depends upon whether they are I/O-port mapped or memory
mapped.
20-10 Vol. 3B
8086 EMULATION
20.2.8.1
I/O-Port-Mapped I/O
The I/O permission bit map in the TSS can be used to generate exceptions on attempts to access specific I/O port
addresses. The I/O permission bit map of each virtual-8086-mode task determines which I/O addresses generate
exceptions for that task. Because each task may have a different I/O permission bit map, the addresses that
generate exceptions for one task may be different from the addresses for another task. This differs from protected
mode in which, if the CPL is less than or equal to the IOPL, I/O access is allowed without checking the I/O permission bit map. See Chapter 18, “Input/Output”, in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, for more information about the I/O permission bit map.
20.2.8.2
Memory-Mapped I/O
In systems which use memory-mapped I/O, the paging facilities of the processor can be used to generate exceptions for attempts to access I/O ports. The virtual-8086 monitor may use paging to control memory-mapped I/O in
these ways:
•
Map part of the linear address space of each task that needs to perform I/O to the physical address space
where I/O ports are placed. By putting the I/O ports at different addresses (in different pages), the paging
mechanism can enforce isolation between tasks.
•
Map part of the linear address space to pages that are not-present. This generates an exception whenever a
task attempts to perform I/O to those pages. System software then can interpret the I/O operation being
attempted.
Software emulation of the I/O space may require too much operating system intervention under some conditions.
In these cases, it may be possible to generate an exception for only the first attempt to access I/O. The system
software then may determine whether a program can be given exclusive control of I/O temporarily, the protection
of the I/O space may be lifted, and the program allowed to run at full speed.
20.2.8.3
Special I/O Buffers
Buffers of intelligent controllers (for example, a bit-mapped frame buffer) also can be emulated using page
mapping. The linear space for the buffer can be mapped to a different physical space for each virtual-8086-mode
task. The virtual-8086 monitor then can control which virtual buffer to copy onto the real buffer in the physical
address space.
20.3
INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE
When the processor receives an interrupt or detects an exception condition while in virtual-8086 mode, it invokes
an interrupt or exception handler, just as it does in protected or real-address mode. The interrupt or exception
handler that is invoked and the mechanism used to invoke it depends on the class of interrupt or exception that has
been detected or generated and the state of various system flags and fields.
In virtual-8086 mode, the interrupts and exceptions are divided into three classes for the purposes of handling:
•
Class 1 — All processor-generated exceptions and all hardware interrupts, including the NMI interrupt and the
hardware interrupts sent to the processor’s external interrupt delivery pins. All class 1 exceptions and
interrupts are handled by the protected-mode exception and interrupt handlers.
•
Class 2 — Special case for maskable hardware interrupts (Section 6.3.2, “Maskable Hardware Interrupts”)
when the virtual mode extensions are enabled.
•
Class 3 — All software-generated interrupts, that is interrupts generated with the INT n instruction1.
The method the processor uses to handle class 2 and 3 interrupts depends on the setting of the following flags and
fields:
•
IOPL field (bits 12 and 13 in the EFLAGS register) — Controls how class 3 software interrupts are handled
when the processor is in virtual-8086 mode (see Section 2.3, “System Flags and Fields in the EFLAGS
1. The INT 3 instruction is a special case (see the description of the INT n instruction in Chapter 3, “Instruction Set Reference, A-L”, of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).
Vol. 3B 20-11
8086 EMULATION
Register”). This field also controls the enabling of the VIF and VIP flags in the EFLAGS register when the VME
flag is set. The VIF and VIP flags are provided to assist in the handling of class 2 maskable hardware interrupts.
•
VME flag (bit 0 in control register CR4) — Enables the virtual mode extension for the processor when set
(see Section 2.5, “Control Registers”).
•
Software interrupt redirection bit map (32 bytes in the TSS, see Figure 20-5) — Contains 256 flags
that indicates how class 3 software interrupts should be handled when they occur in virtual-8086 mode. A
software interrupt can be directed either to the interrupt and exception handlers in the currently running 8086
program or to the protected-mode interrupt and exception handlers.
•
The virtual interrupt flag (VIF) and virtual interrupt pending flag (VIP) in the EFLAGS register —
Provides virtual interrupt support for the handling of class 2 maskable hardware interrupts (see Section
20.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt
Mechanism”).
NOTE
The VME flag, software interrupt redirection bit map, and VIF and VIP flags are only available in IA32 processors that support the virtual mode extensions. These extensions were introduced in the
IA-32 architecture with the Pentium processor.
The following sections describe the actions that processor takes and the possible actions of interrupt and exception
handlers for the two classes of interrupts described in the previous paragraphs. These sections describe three
possible types of interrupt and exception handlers:
•
Protected-mode interrupt and exceptions handlers — These are the standard handlers that the processor
calls through the protected-mode IDT.
•
Virtual-8086 monitor interrupt and exception handlers — These handlers are resident in the virtual-8086
monitor, and they are commonly accessed through a general-protection exception (#GP, interrupt 13) that is
directed to the protected-mode general-protection exception handler.
•
8086 program interrupt and exception handlers — These handlers are part of the 8086 program that is
running in virtual-8086 mode.
The following sections describe how these handlers are used, depending on the selected class and method of interrupt and exception handling.
20.3.1
Class 1—Hardware Interrupt and Exception Handling in Virtual-8086 Mode
In virtual-8086 mode, the Pentium, P6 family, Pentium 4, and Intel Xeon processors handle hardware interrupts
and exceptions in the same manner as they are handled by the Intel486 and Intel386 processors. They invoke the
protected-mode interrupt or exception handler that the interrupt or exception vector points to in the IDT. Here, the
IDT entry must contain either a 32-bit trap or interrupt gate or a task gate. The following sections describe various
ways that a virtual-8086 mode interrupt or exception can be handled after the protected-mode handler has been
invoked.
See Section 20.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism”, for a description of the virtual interrupt mechanism that is available for handling maskable hardware interrupts while in virtual-8086 mode. When this mechanism is either not available or not enabled, maskable
hardware interrupts are handled in the same manner as exceptions, as described in the following sections.
20.3.1.1
Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate
When an interrupt or exception vector points to a 32-bit trap or interrupt gate in the IDT, the gate must in turn
point to a nonconforming, privilege-level 0, code segment. When accessing this code segment, processor performs
the following steps.
1. Switches to 32-bit protected mode and privilege level 0.
2. Saves the state of the processor on the privilege-level 0 stack. The states of the EIP, CS, EFLAGS, ESP, SS, ES,
DS, FS, and GS registers are saved (see Figure 20-4).
20-12 Vol. 3B
8086 EMULATION
3. Clears the segment registers. Saving the DS, ES, FS, and GS registers on the stack and then clearing the
registers lets the interrupt or exception handler safely save and restore these registers regardless of the type
segment selectors they contain (protected-mode or 8086-style). The interrupt and exception handlers, which
may be called in the context of either a protected-mode task or a virtual-8086-mode task, can use the same
code sequences for saving and restoring the registers for any task. Clearing these registers before execution of
the IRET instruction does not cause a trap in the interrupt handler. Interrupt procedures that expect values in
the segment registers or that return values in the segment registers must use the register images saved on the
stack for privilege level 0.
4. Clears VM, NT, RF and TF flags (in the EFLAGS register). If the gate is an interrupt gate, clears the IF flag.
5. Begins executing the selected interrupt or exception handler.
If the trap or interrupt gate references a procedure in a conforming segment or in a segment at a privilege level
other than 0, the processor generates a general-protection exception (#GP). Here, the error code is the segment
selector of the code segment to which a call was attempted.
Without Error Code
Unused
With Error Code
ESP from
TSS
Unused
Old GS
Old GS
Old FS
Old FS
Old DS
Old DS
Old ES
Old ES
Old SS
Old SS
Old ESP
Old ESP
Old EFLAGS
Old EFLAGS
Old CS
Old EIP
ESP from
TSS
Old CS
New ESP
Old EIP
Error Code
New ESP
Figure 20-4. Privilege Level 0 Stack After Interrupt or
Exception in Virtual-8086 Mode
Interrupt and exception handlers can examine the VM flag on the stack to determine if the interrupted procedure
was running in virtual-8086 mode. If so, the interrupt or exception can be handled in one of three ways:
•
•
The protected-mode interrupt or exception handler that was called can handle the interrupt or exception.
•
The virtual-8086 monitor (if called) can in turn pass control back to the 8086 program’s interrupt and exception
handler.
The protected-mode interrupt or exception handler can call the virtual-8086 monitor to handle the interrupt or
exception.
If the interrupt or exception is handled with a protected-mode handler, the handler can return to the interrupted
program in virtual-8086 mode by executing an IRET instruction. This instruction loads the EFLAGS and segment
registers from the images saved in the privilege level 0 stack (see Figure 20-4). A set VM flag in the EFLAGS image
causes the processor to switch back to virtual-8086 mode. The CPL at the time the IRET instruction is executed
must be 0, otherwise the processor does not change the state of the VM flag.
Vol. 3B 20-13
8086 EMULATION
The virtual-8086 monitor runs at privilege level 0, like the protected-mode interrupt and exception handlers. It is
commonly closely tied to the protected-mode general-protection exception (#GP, vector 13) handler. If the
protected-mode interrupt or exception handler calls the virtual-8086 monitor to handle the interrupt or exception,
the return from the virtual-8086 monitor to the interrupted virtual-8086 mode program requires two return
instructions: a RET instruction to return to the protected-mode handler and an IRET instruction to return to the
interrupted program.
The virtual-8086 monitor has the option of directing the interrupt and exception back to an interrupt or exception
handler that is part of the interrupted 8086 program, as described in Section 20.3.1.2, “Handling an Interrupt or
Exception With an 8086 Program Interrupt or Exception Handler”.
20.3.1.2
Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler
Because it was designed to run on an 8086 processor, an 8086 program running in a virtual-8086-mode task
contains an 8086-style interrupt vector table, which starts at linear address 0. If the virtual-8086 monitor correctly
directs an interrupt or exception vector back to the virtual-8086-mode task it came from, the handlers in the 8086
program can handle the interrupt or exception. The virtual-8086 monitor must carry out the following steps to send
an interrupt or exception back to the 8086 program:
1. Use the 8086 interrupt vector to locate the appropriate handler procedure in the 8086 program interrupt table.
2. Store the EFLAGS (low-order 16 bits only), CS and EIP values of the 8086 program on the privilege-level 3
stack. This is the stack that the virtual-8086-mode task is using. (The 8086 handler may use or modify this
information.)
3. Change the return link on the privilege-level 0 stack to point to the privilege-level 3 handler procedure.
4. Execute an IRET instruction to pass control to the 8086 program handler.
5. When the IRET instruction from the privilege-level 3 handler triggers a general-protection exception (#GP) and
thus effectively again calls the virtual-8086 monitor, restore the return link on the privilege-level 0 stack to
point to the original, interrupted, privilege-level 3 procedure.
6. Copy the low order 16 bits of the EFLAGS image from the privilege-level 3 stack to the privilege-level 0 stack
(because some 8086 handlers modify these flags to return information to the code that caused the interrupt).
7. Execute an IRET instruction to pass control back to the interrupted 8086 program.
Note that if an operating system intends to support all 8086 MS-DOS-based programs, it is necessary to use the
actual 8086 interrupt and exception handlers supplied with the program. The reason for this is that some programs
modify their own interrupt vector table to substitute (or hook in series) their own specialized interrupt and exception handlers.
20.3.1.3
Handling an Interrupt or Exception Through a Task Gate
When an interrupt or exception vector points to a task gate in the IDT, the processor performs a task switch to the
selected interrupt- or exception-handling task. The following actions are carried out as part of this task switch:
1. The EFLAGS register with the VM flag set is saved in the current TSS.
2. The link field in the TSS of the called task is loaded with the segment selector of the TSS for the interrupted
virtual-8086-mode task.
3. The EFLAGS register is loaded from the image in the new TSS, which clears the VM flag and causes the
processor to switch to protected mode.
4. The NT flag in the EFLAGS register is set.
5. The processor begins executing the selected interrupt- or exception-handler task.
When an IRET instruction is executed in the handler task and the NT flag in the EFLAGS register is set, the processors switches from a protected-mode interrupt- or exception-handler task back to a virtual-8086-mode task. Here,
the EFLAGS and segment registers are loaded from images saved in the TSS for the virtual-8086-mode task. If the
VM flag is set in the EFLAGS image, the processor switches back to virtual-8086 mode on the task switch. The CPL
at the time the IRET instruction is executed must be 0, otherwise the processor does not change the state of the
VM flag.
20-14 Vol. 3B
8086 EMULATION
20.3.2
Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the
Virtual Interrupt Mechanism
Maskable hardware interrupts are those interrupts that are delivered through the INTR# pin or through an interrupt request to the local APIC (see Section 6.3.2, “Maskable Hardware Interrupts”). These interrupts can be inhibited (masked) from interrupting an executing program or task by clearing the IF flag in the EFLAGS register.
When the VME flag in control register CR4 is set and the IOPL field in the EFLAGS register is less than 3, two additional flags are activated in the EFLAGS register:
•
•
VIF (virtual interrupt) flag, bit 19 of the EFLAGS register.
VIP (virtual interrupt pending) flag, bit 20 of the EFLAGS register.
These flags provide the virtual-8086 monitor with more efficient control over handling maskable hardware interrupts that occur during virtual-8086 mode tasks. They also reduce interrupt-handling overhead, by eliminating the
need for all IF related operations (such as PUSHF, POPF, CLI, and STI instructions) to trap to the virtual-8086
monitor. The purpose and use of these flags are as follows.
NOTE
The VIF and VIP flags are only available in IA-32 processors that support the virtual mode
extensions. These extensions were introduced in the IA-32 architecture with the Pentium
processor. When this mechanism is either not available or not enabled, maskable hardware
interrupts are handled as class 1 interrupts. Here, if VIF and VIP flags are needed, the virtual-8086
monitor can implement them in software.
Existing 8086 programs commonly set and clear the IF flag in the EFLAGS register to enable and disable maskable
hardware interrupts, respectively; for example, to disable interrupts while handling another interrupt or an exception. This practice works well in single task environments, but can cause problems in multitasking and multipleprocessor environments, where it is often desirable to prevent an application program from having direct control
over the handling of hardware interrupts. When using earlier IA-32 processors, this problem was often solved by
creating a virtual IF flag in software. The IA-32 processors (beginning with the Pentium processor) provide hardware support for this virtual IF flag through the VIF and VIP flags.
The VIF flag is a virtualized version of the IF flag, which an application program running from within a virtual-8086
task can used to control the handling of maskable hardware interrupts. When the VIF flag is enabled, the CLI and
STI instructions operate on the VIF flag instead of the IF flag. When an 8086 program executes the CLI instruction,
the processor clears the VIF flag to request that the virtual-8086 monitor inhibit maskable hardware interrupts
from interrupting program execution; when it executes the STI instruction, the processor sets the VIF flag
requesting that the virtual-8086 monitor enable maskable hardware interrupts for the 8086 program. But actually
the IF flag, managed by the operating system, always controls whether maskable hardware interrupts are enabled.
Also, if under these circumstances an 8086 program tries to read or change the IF flag using the PUSHF or POPF
instructions, the processor will change the VIF flag instead, leaving IF unchanged.
The VIP flag provides software a means of recording the existence of a deferred (or pending) maskable hardware
interrupt. This flag is read by the processor but never explicitly written by the processor; it can only be written by
software.
If the IF flag is set and the VIF and VIP flags are enabled, and the processor receives a maskable hardware interrupt (interrupt vector 0 through 255), the processor performs and the interrupt handler software should perform
the following operations:
1. The processor invokes the protected-mode interrupt handler for the interrupt received, as described in the
following steps. These steps are almost identical to those described for method 1 interrupt and exception
handling in Section 20.3.1.1, “Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt
Gate”:
a. Switches to 32-bit protected mode and privilege level 0.
b. Saves the state of the processor on the privilege-level 0 stack. The states of the EIP, CS, EFLAGS, ESP, SS,
ES, DS, FS, and GS registers are saved (see Figure 20-4).
c.
Clears the segment registers.
Vol. 3B 20-15
8086 EMULATION
d. Clears the VM flag in the EFLAGS register.
e. Begins executing the selected protected-mode interrupt handler.
2. The recommended action of the protected-mode interrupt handler is to read the VM flag from the EFLAGS
image on the stack. If this flag is set, the handler makes a call to the virtual-8086 monitor.
3. The virtual-8086 monitor should read the VIF flag in the EFLAGS register.
— If the VIF flag is clear, the virtual-8086 monitor sets the VIP flag in the EFLAGS image on the stack to
indicate that there is a deferred interrupt pending and returns to the protected-mode handler.
— If the VIF flag is set, the virtual-8086 monitor can handle the interrupt if it “belongs” to the 8086 program
running in the interrupted virtual-8086 task; otherwise, it can call the protected-mode interrupt handler to
handle the interrupt.
4. The protected-mode handler executes a return to the program executing in virtual-8086 mode.
5. Upon returning to virtual-8086 mode, the processor continues execution of the 8086 program.
When the 8086 program is ready to receive maskable hardware interrupts, it executes the STI instruction to set the
VIF flag (enabling maskable hardware interrupts). Prior to setting the VIF flag, the processor automatically checks
the VIP flag and does one of the following, depending on the state of the flag:
•
•
If the VIP flag is clear (indicating no pending interrupts), the processor sets the VIF flag.
If the VIP flag is set (indicating a pending interrupt), the processor generates a general-protection exception
(#GP).
The recommended action of the protected-mode general-protection exception handler is to then call the virtual8086 monitor and let it handle the pending interrupt. After handling the pending interrupt, the typical action of the
virtual-8086 monitor is to clear the VIP flag and set the VIF flag in the EFLAGS image on the stack, and then
execute a return to the virtual-8086 mode. The next time the processor receives a maskable hardware interrupt, it
will then handle it as described in steps 1 through 5 earlier in this section.
If the processor finds that both the VIF and VIP flags are set at the beginning of an instruction, it generates a
general-protection exception. This action allows the virtual-8086 monitor to handle the pending interrupt for the
virtual-8086 mode task for which the VIF flag is enabled. Note that this situation can only occur immediately
following execution of a POPF or IRET instruction or upon entering a virtual-8086 mode task through a task switch.
Note that the states of the VIF and VIP flags are not modified in real-address mode or during transitions between
real-address and protected modes.
NOTE
The virtual interrupt mechanism described in this section is also available for use in protected
mode, see Section 20.4, “Protected-Mode Virtual Interrupts”.
20.3.3
Class 3—Software Interrupt Handling in Virtual-8086 Mode
When the processor receives a software interrupt (an interrupt generated with the INT n instruction) while in
virtual-8086 mode, it can use any of six different methods to handle the interrupt. The method selected depends
on the settings of the VME flag in control register CR4, the IOPL field in the EFLAGS register, and the software interrupt redirection bit map in the TSS. Table 20-2 lists the six methods of handling software interrupts in virtual-8086
mode and the respective settings of the VME flag, IOPL field, and the bits in the interrupt redirection bit map for
each method. The table also summarizes the various actions the processor takes for each method.
The VME flag enables the virtual mode extensions for the Pentium and later IA-32 processors. When this flag is
clear, the processor responds to interrupts and exceptions in virtual-8086 mode in the same manner as an Intel386
or Intel486 processor does. When this flag is set, the virtual mode extension provides the following enhancements
to virtual-8086 mode:
•
Speeds up the handling of software-generated interrupts in virtual-8086 mode by allowing the processor to
bypass the virtual-8086 monitor and redirect software interrupts back to the interrupt handlers that are part of
the currently running 8086 program.
•
Supports virtual interrupts for software written to run on the 8086 processor.
20-16 Vol. 3B
8086 EMULATION
The IOPL value interacts with the VME flag and the bits in the interrupt redirection bit map to determine how
specific software interrupts should be handled.
The software interrupt redirection bit map (see Figure 20-5) is a 32-byte field in the TSS. This map is located
directly below the I/O permission bit map in the TSS. Each bit in the interrupt redirection bit map is mapped to an
interrupt vector. Bit 0 in the interrupt redirection bit map (which maps to vector zero in the interrupt table) is
located at the I/O base map address in the TSS minus 32 bytes. When a bit in this bit map is set, it indicates that
the associated software interrupt (interrupt generated with an INT n instruction) should be handled through the
protected-mode IDT and interrupt and exception handlers. When a bit in this bit map is clear, the processor redirects the associated software interrupt back to the interrupt table in the 8086 program (located at linear address 0
in the program’s address space).
NOTE
The software interrupt redirection bit map does not affect hardware generated interrupts and
exceptions. Hardware generated interrupts and exceptions are always handled by the protectedmode interrupt and exception handlers.
Table 20-2. Software Interrupt Handling Methods While in Virtual-8086 Mode
Method VME
1
0
Bit in
Redir.
IOPL Bitmap*
3
X
Processor Action
Interrupt directed to a protected-mode interrupt handler:
•
•
•
•
•
•
•
Switches to privilege-level 0 stack
Pushes GS, FS, DS and ES onto privilege-level 0 stack
Pushes SS, ESP, EFLAGS, CS and EIP of interrupted task onto privilege-level 0 stack
Clears VM, RF, NT, and TF flags
If serviced through interrupt gate, clears IF flag
Clears GS, FS, DS and ES to 0
Sets CS and EIP from interrupt gate
2
0
<3
X
Interrupt directed to protected-mode general-protection exception (#GP) handler.
3
1
<3
1
Interrupt directed to a protected-mode general-protection exception (#GP) handler; VIF and VIP
flag support for handling class 2 maskable hardware interrupts.
4
1
3
1
Interrupt directed to protected-mode interrupt handler: (see method 1 processor action).
5
1
3
0
Interrupt redirected to 8086 program interrupt handler:
•
•
•
•
•
6
1
<3
0
Pushes EFLAGS
Pushes CS and EIP (lower 16 bits only)
Clears IF flag
Clears TF flag
Loads CS and EIP (lower 16 bits only) from selected entry in the interrupt vector table of the
current virtual-8086 task
Interrupt redirected to 8086 program interrupt handler; VIF and VIP flag support for handling class
2 maskable hardware interrupts:
•
•
•
•
•
Pushes EFLAGS with IOPL set to 3 and VIF copied to IF
Pushes CS and EIP (lower 16 bits only)
Clears the VIF flag
Clears TF flag
Loads CS and EIP (lower 16 bits only) from selected entry in the interrupt vector table of the
current virtual-8086 task
NOTE:
* When set to 0, software interrupt is redirected back to the 8086 program interrupt handler; when set to 1, interrupt is directed to
protected-mode handler.
Vol. 3B 20-17
8086 EMULATION
Last byte of
bit
31
24 23
Task-State Segment (TSS)
0
1 1 1 1 1 1 1 1
map must be
I/O Permission Bit Map
Software Interrupt Redirection Bit Map (32 Bytes)
I/O map
base must
not exceed
DFFFH.
I/O Map Base
64H
0
Figure 20-5. Software Interrupt Redirection Bit Map in TSS
Redirecting software interrupts back to the 8086 program potentially speeds up interrupt handling because a
switch back and forth between virtual-8086 mode and protected mode is not required. This latter interrupthandling technique is particularly useful for 8086 operating systems (such as MS-DOS) that use the INT n instruction to call operating system procedures.
The CPUID instruction can be used to verify that the virtual mode extension is implemented on the processor. Bit 1
of the feature flags register (EDX) indicates the availability of the virtual mode extension (see “CPUID—CPU Identification” in Chapter 3, “Instruction Set Reference, A-L”, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).
The following sections describe the six methods (or mechanisms) for handling software interrupts in virtual-8086
mode. See Section 20.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual
Interrupt Mechanism”, for a description of the use of the VIF and VIP flags in the EFLAGS register for handling
maskable hardware interrupts.
20.3.3.1
Method 1: Software Interrupt Handling
When the VME flag in control register CR4 is clear and the IOPL field is 3, a Pentium or later IA-32 processor
handles software interrupts in the same manner as they are handled by an Intel386 or Intel486 processor. It
executes an implicit call to the interrupt handler in the protected-mode IDT pointed to by the interrupt vector. See
Section 20.3.1, “Class 1—Hardware Interrupt and Exception Handling in Virtual-8086 Mode”, for a complete
description of this mechanism and its possible uses.
20.3.3.2
Methods 2 and 3: Software Interrupt Handling
When a software interrupt occurs in virtual-8086 mode and the method 2 or 3 conditions are present, the processor
generates a general-protection exception (#GP). Method 2 is enabled when the VME flag is set to 0 and the IOPL
value is less than 3. Here the IOPL value is used to bypass the protected-mode interrupt handlers and cause any
software interrupt that occurs in virtual-8086 mode to be treated as a protected-mode general-protection exception (#GP). The general-protection exception handler calls the virtual-8086 monitor, which can then emulate an
8086-program interrupt handler or pass control back to the 8086 program’s handler, as described in Section
20.3.1.2, “Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler”.
Method 3 is enabled when the VME flag is set to 1, the IOPL value is less than 3, and the corresponding bit for the
software interrupt in the software interrupt redirection bit map is set to 1. Here, the processor performs the same
20-18 Vol. 3B
8086 EMULATION
operation as it does for method 2 software interrupt handling. If the corresponding bit for the software interrupt in
the software interrupt redirection bit map is set to 0, the interrupt is handled using method 6 (see Section
20.3.3.5, “Method 6: Software Interrupt Handling”).
20.3.3.3
Method 4: Software Interrupt Handling
Method 4 handling is enabled when the VME flag is set to 1, the IOPL value is 3, and the bit for the interrupt vector
in the redirection bit map is set to 1. Method 4 software interrupt handling allows method 1 style handling when the
virtual mode extension is enabled; that is, the interrupt is directed to a protected-mode handler (see Section
20.3.3.1, “Method 1: Software Interrupt Handling”).
20.3.3.4
Method 5: Software Interrupt Handling
Method 5 software interrupt handling provides a streamlined method of redirecting software interrupts (invoked
with the INT n instruction) that occur in virtual 8086 mode back to the 8086 program’s interrupt vector table and
its interrupt handlers. Method 5 handling is enabled when the VME flag is set to 1, the IOPL value is 3, and the bit
for the interrupt vector in the redirection bit map is set to 0. The processor performs the following actions to make
an implicit call to the selected 8086 program interrupt handler:
1. Pushes the low-order 16 bits of the EFLAGS register onto the stack.
2. Pushes the current values of the CS and EIP registers onto the current stack. (Only the 16 least-significant bits
of the EIP register are pushed and no stack switch occurs.)
3. Clears the IF flag in the EFLAGS register to disable interrupts.
4. Clears the TF flag, in the EFLAGS register.
5. Locates the 8086 program interrupt vector table at linear address 0 for the 8086-mode task.
6. Loads the CS and EIP registers with values from the interrupt vector table entry pointed to by the interrupt
vector number. Only the 16 low-order bits of the EIP are loaded and the 16 high-order bits are set to 0. The
interrupt vector table is assumed to be at linear address 0 of the current virtual-8086 task.
7. Begins executing the selected interrupt handler.
An IRET instruction at the end of the handler procedure reverses these steps to return program control to the interrupted 8086 program.
Note that with method 5 handling, a mode switch from virtual-8086 mode to protected mode does not occur. The
processor remains in virtual-8086 mode throughout the interrupt-handling operation.
The method 5 handling actions are virtually identical to the actions the processor takes when handling software
interrupts in real-address mode. The benefit of using method 5 handling to access the 8086 program handlers is
that it avoids the overhead of methods 2 and 3 handling, which requires first going to the virtual-8086 monitor,
then to the 8086 program handler, then back again to the virtual-8086 monitor, before returning to the interrupted
8086 program (see Section 20.3.1.2, “Handling an Interrupt or Exception With an 8086 Program Interrupt or
Exception Handler”).
NOTE
Methods 1 and 4 handling can handle a software interrupt in a virtual-8086 task with a regular
protected-mode handler, but this approach requires all virtual-8086 tasks to use the same software
interrupt handlers, which generally does not give sufficient latitude to the programs running in the
virtual-8086 tasks, particularly MS-DOS programs.
20.3.3.5
Method 6: Software Interrupt Handling
Method 6 handling is enabled when the VME flag is set to 1, the IOPL value is less than 3, and the bit for the interrupt or exception vector in the redirection bit map is set to 0. With method 6 interrupt handling, software interrupts
are handled in the same manner as was described for method 5 handling (see Section 20.3.3.4, “Method 5: Software Interrupt Handling”).
Vol. 3B 20-19
8086 EMULATION
Method 6 differs from method 5 in that with the IOPL value set to less than 3, the VIF and VIP flags in the EFLAGS
register are enabled, providing virtual interrupt support for handling class 2 maskable hardware interrupts (see
Section 20.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt
Mechanism”). These flags provide the virtual-8086 monitor with an efficient means of handling maskable hardware
interrupts that occur during a virtual-8086 mode task. Also, because the IOPL value is less than 3 and the VIF flag
is enabled, the information pushed on the stack by the processor when invoking the interrupt handler is slightly
different between methods 5 and 6 (see Table 20-2).
20.4
PROTECTED-MODE VIRTUAL INTERRUPTS
The IA-32 processors (beginning with the Pentium processor) also support the VIF and VIP flags in the EFLAGS
register in protected mode by setting the PVI (protected-mode virtual interrupt) flag in the CR4 register. Setting
the PVI flag allows applications running at privilege level 3 to execute the CLI and STI instructions without causing
a general-protection exception (#GP) or affecting hardware interrupts.
When the PVI flag is set to 1, the CPL is 3, and the IOPL is less than 3, the STI and CLI instructions set and clear
the VIF flag in the EFLAGS register, leaving IF unaffected. In this mode of operation, an application running in
protected mode and at a CPL of 3 can inhibit interrupts in the same manner as is described in Section 20.3.2, “Class
2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism”, for a
virtual-8086 mode task. When the application executes the CLI instruction, the processor clears the VIF flag. If the
processor receives a maskable hardware interrupt, the processor invokes the protected-mode interrupt handler.
This handler checks the state of the VIF flag in the EFLAGS register. If the VIF flag is clear (indicating that the active
task does not want to have interrupts handled now), the handler sets the VIP flag in the EFLAGS image on the stack
and returns to the privilege-level 3 application, which continues program execution. When the application executes
a STI instruction to set the VIF flag, the processor automatically invokes the general-protection exception handler,
which can then handle the pending interrupt. After handing the pending interrupt, the handler typically sets the VIF
flag and clears the VIP flag in the EFLAGS image on the stack and executes a return to the application program. The
next time the processor receives a maskable hardware interrupt, the processor will handle it in the normal manner
for interrupts received while the processor is operating at a CPL of 3.
As with the virtual mode extension (enabled with the VME flag in the CR4 register), the protected-mode virtual
interrupt extension only affects maskable hardware interrupts (interrupt vectors 32 through 255). NMI interrupts
and exceptions are handled in the normal manner.
When protected-mode virtual interrupts are disabled (that is, when the PVI flag in control register CR4 is set to 0,
the CPL is less than 3, or the IOPL value is 3), then the CLI and STI instructions execute in a manner compatible
with the Intel486 processor. That is, if the CPL is greater (less privileged) than the I/O privilege level (IOPL), a
general-protection exception occurs. If the IOPL value is 3, CLI and STI clear or set the IF flag, respectively.
PUSHF, POPF, IRET and INT are executed like in the Intel486 processor, regardless of whether protected-mode
virtual interrupts are enabled.
It is only possible to enter virtual-8086 mode through a task switch or the execution of an IRET instruction, and it
is only possible to leave virtual-8086 mode by faulting to a protected-mode interrupt handler (typically the generalprotection exception handler, which in turn calls the virtual 8086-mode monitor). In both cases, the EFLAGS
register is saved and restored. This is not true, however, in protected mode when the PVI flag is set and the
processor is not in virtual-8086 mode. Here, it is possible to call a procedure at a different privilege level, in which
case the EFLAGS register is not saved or modified. However, the states of VIF and VIP flags are never examined by
the processor when the CPL is not 3.
20-20 Vol. 3B
CHAPTER 21
MIXING 16-BIT AND 32-BIT CODE
Program modules written to run on IA-32 processors can be either 16-bit modules or 32-bit modules. Table 21-1
shows the characteristic of 16-bit and 32-bit modules.
Table 21-1. Characteristics of 16-Bit and 32-Bit Program Modules
Characteristic
16-Bit Program Modules
32-Bit Program Modules
Segment Size
0 to 64 KBytes
0 to 4 GBytes
Operand Sizes
8 bits and 16 bits
8 bits and 32 bits
Pointer Offset Size (Address Size)
16 bits
32 bits
Stack Pointer Size
16 Bits
32 Bits
Control Transfers Allowed to Code Segments
of This Size
16 Bits
32 Bits
The IA-32 processors function most efficiently when executing 32-bit program modules. They can, however, also
execute 16-bit program modules, in any of the following ways:
•
•
•
•
In real-address mode.
•
•
By integrating 16-bit and 32-bit segments into a single protected-mode task.
In virtual-8086 mode.
System management mode (SMM).
As a protected-mode task, when the code, data, and stack segments for the task are all configured as a 16-bit
segments.
By integrating 16-bit operations into 32-bit code segments.
Real-address mode, virtual-8086 mode, and SMM are native 16-bit modes. A legacy program assembled and/or
compiled to run on an Intel 8086 or Intel 286 processor should run in real-address mode or virtual-8086 mode
without modification. Sixteen-bit program modules can also be written to run in real-address mode for handling
system initialization or to run in SMM for handling system management functions. See Chapter 20, “8086 Emulation,” for detailed information on real-address mode and virtual-8086 mode; see Chapter 34, “System Management Mode,” for information on SMM.
This chapter describes how to integrate 16-bit program modules with 32-bit program modules when operating in
protected mode and how to mix 16-bit and 32-bit code within 32-bit code segments.
21.1
DEFINING 16-BIT AND 32-BIT PROGRAM MODULES
The following IA-32 architecture mechanisms are used to distinguish between and support 16-bit and 32-bit
segments and operations:
•
•
•
•
•
The D (default operand and address size) flag in code-segment descriptors.
The B (default stack size) flag in stack-segment descriptors.
16-bit and 32-bit call gates, interrupt gates, and trap gates.
Operand-size and address-size instruction prefixes.
16-bit and 32-bit general-purpose registers.
The D flag in a code-segment descriptor determines the default operand-size and address-size for the instructions
of a code segment. (In real-address mode and virtual-8086 mode, which do not use segment descriptors, the
default is 16 bits.) A code segment with its D flag set is a 32-bit segment; a code segment with its D flag clear is a
16-bit segment.
Vol. 3B 21-1
MIXING 16-BIT AND 32-BIT CODE
The B flag in the stack-segment descriptor specifies the size of stack pointer (the 32-bit ESP register or the 16-bit
SP register) used by the processor for implicit stack references. The B flag for all data descriptors also controls
upper address range for expand down segments.
When transferring program control to another code segment through a call gate, interrupt gate, or trap gate, the
operand size used during the transfer is determined by the type of gate used (16-bit or 32-bit), (not by the D-flag
or prefix of the transfer instruction). The gate type determines how return information is saved on the stack (or
stacks).
For most efficient and trouble-free operation of the processor, 32-bit programs or tasks should have the D flag in
the code-segment descriptor and the B flag in the stack-segment descriptor set, and 16-bit programs or tasks
should have these flags clear. Program control transfers from 16-bit segments to 32-bit segments (and vice versa)
are handled most efficiently through call, interrupt, or trap gates.
Instruction prefixes can be used to override the default operand size and address size of a code segment. These
prefixes can be used in real-address mode as well as in protected mode and virtual-8086 mode. An operand-size or
address-size prefix only changes the size for the duration of the instruction.
21.2
MIXING 16-BIT AND 32-BIT OPERATIONS WITHIN A CODE SEGMENT
The following two instruction prefixes allow mixing of 32-bit and 16-bit operations within one segment:
•
•
The operand-size prefix (66H)
The address-size prefix (67H)
These prefixes reverse the default size selected by the D flag in the code-segment descriptor. For example, the
processor can interpret the (MOV mem, reg) instruction in any of four ways:
•
In a 32-bit code segment:
— Moves 32 bits from a 32-bit register to memory using a 32-bit effective address.
— If preceded by an operand-size prefix, moves 16 bits from a 16-bit register to memory using a 32-bit
effective address.
— If preceded by an address-size prefix, moves 32 bits from a 32-bit register to memory using a 16-bit
effective address.
— If preceded by both an address-size prefix and an operand-size prefix, moves 16 bits from a 16-bit register
to memory using a 16-bit effective address.
•
In a 16-bit code segment:
— Moves 16 bits from a 16-bit register to memory using a 16-bit effective address.
— If preceded by an operand-size prefix, moves 32 bits from a 32-bit register to memory using a 16-bit
effective address.
— If preceded by an address-size prefix, moves 16 bits from a 16-bit register to memory using a 32-bit
effective address.
— If preceded by both an address-size prefix and an operand-size prefix, moves 32 bits from a 32-bit register
to memory using a 32-bit effective address.
The previous examples show that any instruction can generate any combination of operand size and address size
regardless of whether the instruction is in a 16- or 32-bit segment. The choice of the 16- or 32-bit default for a code
segment is normally based on the following criteria:
•
Performance — Always use 32-bit code segments when possible. They run much faster than 16-bit code
segments on P6 family processors, and somewhat faster on earlier IA-32 processors.
•
The operating system the code segment will be running on — If the operating system is a 16-bit
operating system, it may not support 32-bit program modules.
•
Mode of operation — If the code segment is being designed to run in real-address mode, virtual-8086 mode,
or SMM, it must be a 16-bit code segment.
21-2 Vol. 3B
MIXING 16-BIT AND 32-BIT CODE
•
Backward compatibility to earlier IA-32 processors — If a code segment must be able to run on an Intel
8086 or Intel 286 processor, it must be a 16-bit code segment.
21.3
SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS
Data segments can be accessed from both 16-bit and 32-bit code segments. When a data segment that is larger
than 64 KBytes is to be shared among 16- and 32-bit code segments, the data that is to be accessed from the 16bit code segments must be located within the first 64 KBytes of the data segment. The reason for this is that 16bit pointers by definition can only point to the first 64 KBytes of a segment.
A stack that spans less than 64 KBytes can be shared by both 16- and 32-bit code segments. This class of stacks
includes:
•
•
•
Stacks in expand-up segments with the G (granularity) and B (big) flags in the stack-segment descriptor clear.
Stacks in expand-down segments with the G and B flags clear.
Stacks in expand-up segments with the G flag set and the B flag clear and where the stack is contained
completely within the lower 64 KBytes. (Offsets greater than FFFFH can be used for data, other than the stack,
which is not shared.)
See Section 3.4.5, “Segment Descriptors,” for a description of the G and B flags and the expand-down stack type.
The B flag cannot, in general, be used to change the size of stack used by a 16-bit code segment. This flag controls
the size of the stack pointer only for implicit stack references such as those caused by interrupts, exceptions, and
the PUSH, POP, CALL, and RET instructions. It does not control explicit stack references, such as accesses to
parameters or local variables. A 16-bit code segment can use a 32-bit stack only if the code is modified so that all
explicit references to the stack are preceded by the 32-bit address-size prefix, causing those references to use 32bit addressing and explicit writes to the stack pointer are preceded by a 32-bit operand-size prefix.
In 32-bit, expand-down segments, all offsets may be greater than 64 KBytes; therefore, 16-bit code cannot use
this kind of stack segment unless the code segment is modified to use 32-bit addressing.
21.4
TRANSFERRING CONTROL AMONG MIXED-SIZE CODE SEGMENTS
There are three ways for a procedure in a 16-bit code segment to safely make a call to a 32-bit code segment:
•
•
Make the call through a 32-bit call gate.
•
Modify the 16-bit procedure, inserting an operand-size prefix before the call, to change it to a 32-bit call.
Make a 16-bit call to a 32-bit interface procedure. The interface procedure then makes a 32-bit call to the
intended destination.
Likewise, there are three ways for procedure in a 32-bit code segment to safely make a call to a 16-bit code
segment:
•
•
Make the call through a 16-bit call gate. Here, the EIP value at the CALL instruction cannot exceed FFFFH.
•
Modify the 32-bit procedure, inserting an operand-size prefix before the call, changing it to a 16-bit call. Be
certain that the return offset does not exceed FFFFH.
Make a 32-bit call to a 16-bit interface procedure. The interface procedure then makes a 16-bit call to the
intended destination.
These methods of transferring program control overcome the following architectural limitations imposed on calls
between 16-bit and 32-bit code segments:
•
Pointers from 16-bit code segments (which by default can only be 16 bits) cannot be used to address data or
code located beyond FFFFH in a 32-bit segment.
•
The operand-size attributes for a CALL and its companion RETURN instruction must be the same to maintain
stack coherency. This is also true for implicit calls to interrupt and exception handlers and their companion IRET
instructions.
•
A 32-bit parameters (particularly a pointer parameter) greater than FFFFH cannot be squeezed into a 16-bit
parameter location on a stack.
Vol. 3B 21-3
MIXING 16-BIT AND 32-BIT CODE
•
The size of the stack pointer (SP or ESP) changes when switching between 16-bit and 32-bit code segments.
These limitations are discussed in greater detail in the following sections.
21.4.1
Code-Segment Pointer Size
For control-transfer instructions that use a pointer to identify the next instruction (that is, those that do not use
gates), the operand-size attribute determines the size of the offset portion of the pointer. The implications of this
rule are as follows:
•
A JMP, CALL, or RET instruction from a 32-bit segment to a 16-bit segment is always possible using a 32-bit
operand size, providing the 32-bit pointer does not exceed FFFFH.
•
A JMP, CALL, or RET instruction from a 16-bit segment to a 32-bit segment cannot address a destination greater
than FFFFH, unless the instruction is given an operand-size prefix.
See Section 21.4.5, “Writing Interface Procedures,” for an interface procedure that can transfer program control
from 16-bit segments to destinations in 32-bit segments beyond FFFFH.
21.4.2
Stack Management for Control Transfer
Because the stack is managed differently for 16-bit procedure calls than for 32-bit calls, the operand-size attribute
of the RET instruction must match that of the CALL instruction (see Figure 21-1). On a 16-bit call, the processor
pushes the contents of the 16-bit IP register and (for calls between privilege levels) the 16-bit SP register. The
matching RET instruction must also use a 16-bit operand size to pop these 16-bit values from the stack into the 16bit registers.
A 32-bit CALL instruction pushes the contents of the 32-bit EIP register and (for inter-privilege-level calls) the 32bit ESP register. Here, the matching RET instruction must use a 32-bit operand size to pop these 32-bit values from
the stack into the 32-bit registers. If the two parts of a CALL/RET instruction pair do not have matching operand
sizes, the stack will not be managed correctly and the values of the instruction pointer and stack pointer will not be
restored to correct values.
21-4 Vol. 3B
MIXING 16-BIT AND 32-BIT CODE
Without Privilege Transition
After 16-bit Call
31
Stack
Growth
After 32-bit Call
0
31
PARM 2 PARM 1
CS
PARM 2
SP
IP
0
PARM 1
CS
EIP
ESP
With Privilege Transition
After 16-bit Call
31
SS
Stack
Growth
After 32-bit Call
0
31
0
SP
SS
PARM 2 PARM 1
CS
IP
ESP
SP
PARM 2
PARM 1
CS
EIP
ESP
Undefined
Figure 21-1. Stack after Far 16- and 32-Bit Calls
While executing 32-bit code, if a call is made to a 16-bit code segment which is at the same or a more privileged
level (that is, the DPL of the called code segment is less than or equal to the CPL of the calling code segment)
through a 16-bit call gate, then the upper 16-bits of the ESP register may be unreliable upon returning to the 32bit code segment (that is, after executing a RET in the 16-bit code segment).
When the CALL instruction and its matching RET instruction are in code segments that have D flags with the same
values (that is, both are 32-bit code segments or both are 16-bit code segments), the default settings may be
used. When the CALL instruction and its matching RET instruction are in segments which have different D-flag
settings, an operand-size prefix must be used.
21.4.2.1
Controlling the Operand-Size Attribute For a Call
Three things can determine the operand-size of a call:
•
•
•
The D flag in the segment descriptor for the calling code segment.
An operand-size instruction prefix.
The type of call gate (16-bit or 32-bit), if a call is made through a call gate.
When a call is made with a pointer (rather than a call gate), the D flag for the calling code segment determines the
operand-size for the CALL instruction. This operand-size attribute can be overridden by prepending an operandsize prefix to the CALL instruction. So, for example, if the D flag for a code segment is set for 16 bits and the
operand-size prefix is used with a CALL instruction, the processor will cause the information stored on the stack to
Vol. 3B 21-5
MIXING 16-BIT AND 32-BIT CODE
be stored in 32-bit format. If the call is to a 32-bit code segment, the instructions in that code segment will be able
to read the stack coherently. Also, a RET instruction from the 32-bit code segment without an operand-size prefix
will maintain stack coherency with the 16-bit code segment being returned to.
When a CALL instruction references a call-gate descriptor, the type of call is determined by the type of call gate (16bit or 32-bit). The offset to the destination in the code segment being called is taken from the gate descriptor;
therefore, if a 32-bit call gate is used, a procedure in a 16-bit code segment can call a procedure located more than
64 KBytes from the base of a 32-bit code segment, because a 32-bit call gate uses a 32-bit offset.
Note that regardless of the operand size of the call and how it is determined, the size of the stack pointer used (SP
or ESP) is always controlled by the B flag in the stack-segment descriptor currently in use (that is, when B is clear,
SP is used, and when B is set, ESP is used).
An unmodified 16-bit code segment that has run successfully on an 8086 processor or in real-mode on a later IA32 architecture processor will have its D flag clear and will not use operand-size override prefixes. As a result, all
CALL instructions in this code segment will use the 16-bit operand-size attribute. Procedures in these code
segments can be modified to safely call procedures to 32-bit code segments in either of two ways:
•
Relink the CALL instruction to point to 32-bit call gates (see Section 21.4.2.2, “Passing Parameters With a
Gate”).
•
Add a 32-bit operand-size prefix to each CALL instruction.
21.4.2.2
Passing Parameters With a Gate
When referencing 32-bit gates with 16-bit procedures, it is important to consider the number of parameters passed
in each procedure call. The count field of the gate descriptor specifies the size of the parameter string to copy from
the current stack to the stack of a more privileged (numerically lower privilege level) procedure. The count field of
a 16-bit gate specifies the number of 16-bit words to be copied, whereas the count field of a 32-bit gate specifies
the number of 32-bit doublewords to be copied. The count field for a 32-bit gate must thus be half the size of the
number of words being placed on the stack by a 16-bit procedure. Also, the 16-bit procedure must use an even
number of words as parameters.
21.4.3
Interrupt Control Transfers
A program-control transfer caused by an exception or interrupt is always carried out through an interrupt or trap
gate (located in the IDT). Here, the type of the gate (16-bit or 32-bit) determines the operand-size attribute used
in the implicit call to the exception or interrupt handler procedure in another code segment.
A 32-bit interrupt or trap gate provides a safe interface to a 32-bit exception or interrupt handler when the exception or interrupt occurs in either a 32-bit or a 16-bit code segment. It is sometimes impractical, however, to place
exception or interrupt handlers in 16-bit code segments, because only 16-bit return addresses are saved on the
stack. If an exception or interrupt occurs in a 32-bit code segment when the EIP was greater than FFFFH, the 16bit handler procedure cannot provide the correct return address.
21.4.4
Parameter Translation
When segment offsets or pointers (which contain segment offsets) are passed as parameters between 16-bit and
32-bit procedures, some translation is required. If a 32-bit procedure passes a pointer to data located beyond 64
KBytes to a 16-bit procedure, the 16-bit procedure cannot use it. Except for this limitation, interface code can
perform any format conversion between 32-bit and 16-bit pointers that may be needed.
Parameters passed by value between 32-bit and 16-bit code also may require translation between 32-bit and 16bit formats. The form of the translation is application-dependent.
21.4.5
Writing Interface Procedures
Placing interface code between 32-bit and 16-bit procedures can be the solution to the following interface problems:
21-6 Vol. 3B
MIXING 16-BIT AND 32-BIT CODE
•
Allowing procedures in 16-bit code segments to call procedures with offsets greater than FFFFH in 32-bit code
segments.
•
•
Matching operand-size attributes between companion CALL and RET instructions.
•
The possible invalidation of the upper bits of the ESP register.
Translating parameters (data), including managing parameter strings with a variable count or an odd number
of 16-bit words.
The interface procedure is simplified where these rules are followed.
1. The interface procedure must reside in a 32-bit code segment (the D flag for the code-segment descriptor is
set).
2. All procedures that may be called by 16-bit procedures must have offsets not greater than FFFFH.
3. All return addresses saved by 16-bit procedures must have offsets not greater than FFFFH.
The interface procedure becomes more complex if any of these rules are violated. For example, if a 16-bit procedure calls a 32-bit procedure with an entry point beyond FFFFH, the interface procedure will need to provide the
offset to the entry point. The mapping between 16- and 32-bit addresses is only performed automatically when a
call gate is used, because the gate descriptor for a call gate contains a 32-bit address. When a call gate is not used,
the interface code must provide the 32-bit address.
The structure of the interface procedure depends on the types of calls it is going to support, as follows:
•
Calls from 16-bit procedures to 32-bit procedures — Calls to the interface procedure from a 16-bit code
segment are made with 16-bit CALL instructions (by default, because the D flag for the calling code-segment
descriptor is clear), and 16-bit operand-size prefixes are used with RET instructions to return from the interface
procedure to the calling procedure. Calls from the interface procedure to 32-bit procedures are performed with
32-bit CALL instructions (by default, because the D flag for the interface procedure’s code segment is set), and
returns from the called procedures to the interface procedure are performed with 32-bit RET instructions (also
by default).
•
Calls from 32-bit procedures to 16-bit procedures — Calls to the interface procedure from a 32-bit code
segment are made with 32-bit CALL instructions (by default), and returns to the calling procedure from the
interface procedure are made with 32-bit RET instructions (also by default). Calls from the interface procedure
to 16-bit procedures require the CALL instructions to have the operand-size prefixes, and returns from the
called procedures to the interface procedure are performed with 16-bit RET instructions (by default).
Vol. 3B 21-7
MIXING 16-BIT AND 32-BIT CODE
21-8 Vol. 3B
CHAPTER 22
ARCHITECTURE COMPATIBILITY
Intel 64 and IA-32 processors are binary compatible. Compatibility means that, within limited constraints,
programs that execute on previous generations of processors will produce identical results when executed on later
processors. The compatibility constraints and any implementation differences between the Intel 64 and IA-32
processors are described in this chapter.
Each new processor has enhanced the software visible architecture from that found in earlier Intel 64 and IA-32
processors. Those enhancements have been defined with consideration for compatibility with previous and future
processors. This chapter also summarizes the compatibility considerations for those extensions.
22.1
PROCESSOR FAMILIES AND CATEGORIES
IA-32 processors are referred to in several different ways in this chapter, depending on the type of compatibility
information being related, as described in the following:
•
IA-32 Processors — All the Intel processors based on the Intel IA-32 Architecture, which include the
8086/88, Intel 286, Intel386, Intel486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium 4, and Intel
Xeon processors.
•
32-bit Processors — All the IA-32 processors that use a 32-bit architecture, which include the Intel386,
Intel486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium 4, and Intel Xeon processors.
•
16-bit Processors — All the IA-32 processors that use a 16-bit architecture, which include the 8086/88 and
Intel 286 processors.
•
P6 Family Processors — All the IA-32 processors that are based on the P6 microarchitecture, which include
the Pentium Pro, Pentium II, and Pentium III processors.
•
Pentium® 4 Processors — A family of IA-32 and Intel 64 processors that are based on the Intel NetBurst®
microarchitecture.
•
Intel® Pentium® M Processors — A family of IA-32 processors that are based on the Intel Pentium M
processor microarchitecture.
•
Intel® Core™ Duo and Solo Processors — Families of IA-32 processors that are based on an improved Intel
Pentium M processor microarchitecture.
•
Intel® Xeon® Processors — A family of IA-32 and Intel 64 processors that are based on the Intel NetBurst
microarchitecture. This family includes the Intel Xeon processor and the Intel Xeon processor MP based on the
Intel NetBurst microarchitecture. Intel Xeon processors 3000, 3100, 3200, 3300, 3200, 5100, 5200, 5300,
5400, 7200, 7300 series are based on Intel Core microarchitectures and support Intel 64 architecture.
•
Pentium® D Processors — A family of dual-core Intel 64 processors that provides two processor cores in a
physical package. Each core is based on the Intel NetBurst microarchitecture.
•
Pentium® Processor Extreme Editions — A family of dual-core Intel 64 processors that provides two
processor cores in a physical package. Each core is based on the Intel NetBurst microarchitecture and supports
Intel Hyper-Threading Technology.
•
Intel® Core™ 2 Processor family— A family of Intel 64 processors that are based on the Intel Core microarchitecture. Intel Pentium Dual-Core processors are also based on the Intel Core microarchitecture.
•
Intel® Atom™ Processors — A family of IA-32 and Intel 64 processors. 45 nm Intel Atom processors are
based on the Intel Atom microarchitecture. 32 nm Intel Atom processors are based on newer microarchitectures including the Silvermont microarchitecture and the Airmont microarchitecture. Each generation of Intel
Atom processors can be identified by the CPUID’s DisplayFamily_DisplayModel signature; see Table 35-1
“CPUID Signature Values of DisplayFamily_DisplayModel”.
Vol. 3B 22-1
ARCHITECTURE COMPATIBILITY
22.2
RESERVED BITS
Throughout this manual, certain bits are marked as reserved in many register and memory layout descriptions.
When bits are marked as undefined or reserved, it is essential for compatibility with future processors that software
treat these bits as having a future, though unknown effect. Software should follow these guidelines in dealing with
reserved bits:
•
Do not depend on the states of any reserved bits when testing the values of registers or memory locations that
contain such bits. Mask out the reserved bits before testing.
•
•
•
Do not depend on the states of any reserved bits when storing them to memory or to a register.
Do not depend on the ability to retain information written into any reserved bits.
When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or
reload them with values previously read from the same register.
Software written for existing IA-32 processor that handles reserved bits correctly will port to future IA-32 processors without generating protection exceptions.
22.3
ENABLING NEW FUNCTIONS AND MODES
Most of the new control functions defined for the P6 family and Pentium processors are enabled by new mode flags
in the control registers (primarily register CR4). This register is undefined for IA-32 processors earlier than the
Pentium processor. Attempting to access this register with an Intel486 or earlier IA-32 processor results in an
invalid-opcode exception (#UD). Consequently, programs that execute correctly on the Intel486 or earlier IA-32
processor cannot erroneously enable these functions. Attempting to set a reserved bit in register CR4 to a value
other than its original value results in a general-protection exception (#GP). So, programs that execute on the P6
family and Pentium processors cannot erroneously enable functions that may be implemented in future IA-32
processors.
The P6 family and Pentium processors do not check for attempts to set reserved bits in model-specific registers;
however these bits may be checked on more recent processors. It is the obligation of the software writer to enforce
this discipline. These reserved bits may be used in future Intel processors.
22.4
DETECTING THE PRESENCE OF NEW FEATURES THROUGH SOFTWARE
Software can check for the presence of new architectural features and extensions in either of two ways:
1. Test for the presence of the feature or extension. Software can test for the presence of new flags in the EFLAGS
register and control registers. If these flags are reserved (meaning not present in the processor executing the
test), an exception is generated. Likewise, software can attempt to execute a new instruction, which results in
an invalid-opcode exception (#UD) being generated if it is not supported.
2. Execute the CPUID instruction. The CPUID instruction (added to the IA-32 in the Pentium processor) indicates
the presence of new features directly.
See Chapter 19, “Processor Identification and Feature Determination,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for detailed information on detecting new processor features and extensions.
22.5
INTEL MMX TECHNOLOGY
The Pentium processor with MMX technology introduced the MMX technology and a set of MMX instructions to the
IA-32. The MMX instructions are described in Chapter 9, “Programming with Intel® MMX™ Technology,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, and in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D. The MMX technology and MMX instructions are
also included in the Pentium II, Pentium III, Pentium 4, and Intel Xeon processors.
22-2 Vol. 3B
ARCHITECTURE COMPATIBILITY
22.6
STREAMING SIMD EXTENSIONS (SSE)
The Streaming SIMD Extensions (SSE) were introduced in the Pentium III processor. The SSE extensions consist of
a new set of instructions and a new set of registers. The new registers include the eight 128-bit XMM registers and
the 32-bit MXCSR control and status register. These instructions and registers are designed to allow SIMD computations to be made on single-precision floating-point numbers. Several of these new instructions also operate in the
MMX registers. SSE instructions and registers are described in Section 10, “Programming with Streaming SIMD
Extensions (SSE),” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, and in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D.
22.7
STREAMING SIMD EXTENSIONS 2 (SSE2)
The Streaming SIMD Extensions 2 (SSE2) were introduced in the Pentium 4 and Intel Xeon processors. They
consist of a new set of instructions that operate on the XMM and MXCSR registers and perform SIMD operations on
double-precision floating-point values and on integer values. Several of these new instructions also operate in the
MMX registers. SSE2 instructions and registers are described in Chapter 11, “Programming with Streaming SIMD
Extensions 2 (SSE2),” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, and in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D.
22.8
STREAMING SIMD EXTENSIONS 3 (SSE3)
The Streaming SIMD Extensions 3 (SSE3) were introduced in Pentium 4 processors supporting Intel HyperThreading Technology and Intel Xeon processors. SSE3 extensions include 13 instructions. Ten of these 13 instructions support the single instruction multiple data (SIMD) execution model used with SSE/SSE2 extensions. One
SSE3 instruction accelerates x87 style programming for conversion to integer. The remaining two instructions
(MONITOR and MWAIT) accelerate synchronization of threads. SSE3 instructions are described in Chapter 12,
“Programming with SSE3, SSSE3 and SSE4,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, and in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C
& 2D.
22.9
ADDITIONAL STREAMING SIMD EXTENSIONS
The Supplemental Streaming SIMD Extensions 3 (SSSE3) were introduced in the Intel Core 2 processor and Intel
Xeon processor 5100 series. Streaming SIMD Extensions 4 provided 54 new instructions introduced in 45 nm Intel
Xeon processors and Intel Core 2 processors. SSSE3, SSE4.1 and SSE4.2 instructions are described in Chapter 12,
“Programming with SSE3, SSSE3 and SSE4,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, and in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C
& 2D.
22.10
INTEL HYPER-THREADING TECHNOLOGY
Intel Hyper-Threading Technology provides two logical processors that can execute two separate code streams
(called threads) concurrently by using shared resources in a single processor core or in a physical package.
This feature was introduced in the Intel Xeon processor MP and later steppings of the Intel Xeon processor, and
Pentium 4 processors supporting Intel Hyper-Threading Technology. The feature is also found in the Pentium
processor Extreme Edition. See also: Section 8.7, “Intel® Hyper-Threading Technology Architecture.”
45 nm and 32 nm Intel Atom processors support Intel Hyper-Threading Technology.
Intel Atom processors based on Silvermont and Airmont microarchitectures do not support Intel Hyper-Threading
Technology
Vol. 3B 22-3
ARCHITECTURE COMPATIBILITY
22.11
MULTI-CORE TECHNOLOGY
The Pentium D processor and Pentium processor Extreme Edition provide two processor cores in each physical
processor package. See also: Section 8.5, “Intel® Hyper-Threading Technology and Intel® Multi-Core Technology,”
and Section 8.8, “Multi-Core Architecture.” Intel Core 2 Duo, Intel Pentium Dual-Core processors, Intel Xeon
processors 3000, 3100, 5100, 5200 series provide two processor cores in each physical processor package. Intel
Core 2 Extreme, Intel Core 2 Quad processors, Intel Xeon processors 3200, 3300, 5300, 5400, 7300 series provide
two processor cores in each physical processor package.
22.12
SPECIFIC FEATURES OF DUAL-CORE PROCESSOR
Dual-core processors may have some processor-specific features. Use CPUID feature flags to detect the availability
features. Note the following:
•
CPUID Brand String — On Pentium processor Extreme Edition, the process will report the correct brand string
only after the correct microcode updates are loaded.
•
Enhanced Intel SpeedStep Technology — This feature is supported in Pentium D processor but not in
Pentium processor Extreme Edition.
22.13
NEW INSTRUCTIONS IN THE PENTIUM AND LATER IA-32 PROCESSORS
Table 22-1 identifies the instructions introduced into the IA-32 in the Pentium processor and later IA-32 processors.
22.13.1 Instructions Added Prior to the Pentium Processor
The following instructions were added in the Intel486 processor:
•
•
•
•
•
•
BSWAP (byte swap) instruction.
XADD (exchange and add) instruction.
CMPXCHG (compare and exchange) instruction.
ΙNVD (invalidate cache) instruction.
WBINVD (write-back and invalidate cache) instruction.
INVLPG (invalidate TLB entry) instruction.
Table 22-1. New Instruction in the Pentium Processor and Later IA-32 Processors
Instruction
CPUID Identification Bits
CMOVcc (conditional move)
EDX, Bit 15
FCMOVcc (floating-point conditional move)
EDX, Bits 0 and 15
FCOMI (floating-point compare and set EFLAGS)
EDX, Bits 0 and 15
RDPMC (read performance monitoring counters)
EAX, Bits 8-11, set to 6H;
see Note 1
UD2 (undefined)
EAX, Bits 8-11, set to 6H
CMPXCHG8B (compare and exchange 8 bytes)
EDX, Bit 8
CPUID (CPU identification)
None; see Note 2
RDTSC (read time-stamp counter)
EDX, Bit 4
RDMSR (read model-specific register)
EDX, Bit 5
WRMSR (write model-specific register)
EDX, Bit 5
MMX Instructions
EDX, Bit 23
22-4 Vol. 3B
Introduced In
Pentium Pro processor
Pentium processor
ARCHITECTURE COMPATIBILITY
Table 22-1. New Instruction in the Pentium Processor and Later IA-32 Processors (Contd.)
Instruction
CPUID Identification Bits
Introduced In
NOTES:
1. The RDPMC instruction was introduced in the P6 family of processors and added to later model Pentium processors. This instruction is model specific in nature and not architectural.
2. The CPUID instruction is available in all Pentium and P6 family processors and in later models of the Intel486 processors. The ability
to set and clear the ID flag (bit 21) in the EFLAGS register indicates the availability of the CPUID instruction.
The following instructions were added in the Intel386 processor:
•
•
•
•
•
•
•
•
•
•
•
•
LSS, LFS, and LGS (load SS, FS, and GS registers).
Long-displacement conditional jumps.
Single-bit instructions.
Bit scan instructions.
Double-shift instructions.
Byte set on condition instruction.
Move with sign/zero extension.
Generalized multiply instruction.
MOV to and from control registers.
MOV to and from test registers (now obsolete).
MOV to and from debug registers.
RSM (resume from SMM). This instruction was introduced in the Intel386 SL and Intel486 SL processors.
The following instructions were added in the Intel 387 math coprocessor:
•
•
FPREM1.
FUCOM, FUCOMP, and FUCOMPP.
22.14
OBSOLETE INSTRUCTIONS
The MOV to and from test registers instructions were removed from the Pentium processor and future IA-32
processors. Execution of these instructions generates an invalid-opcode exception (#UD).
22.15
UNDEFINED OPCODES
All new instructions defined for IA-32 processors use binary encodings that were reserved on earlier-generation
processors. Attempting to execute a reserved opcode always results in an invalid-opcode (#UD) exception being
generated. Consequently, programs that execute correctly on earlier-generation processors cannot erroneously
execute these instructions and thereby produce unexpected results when executed on later IA-32 processors.
22.16
NEW FLAGS IN THE EFLAGS REGISTER
The section titled “EFLAGS Register” in Chapter 3, “Basic Execution Environment,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, shows the configuration of flags in the EFLAGS register for
the P6 family processors. No new flags have been added to this register in the P6 family processors. The flags
added to this register in the Pentium and Intel486 processors are described in the following sections.
The following flags were added to the EFLAGS register in the Pentium processor:
•
•
VIF (virtual interrupt flag), bit 19.
VIP (virtual interrupt pending), bit 20.
Vol. 3B 22-5
ARCHITECTURE COMPATIBILITY
•
ID (identification flag), bit 21.
The AC flag (bit 18) was added to the EFLAGS register in the Intel486 processor.
22.16.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors
The following bits in the EFLAGS register that can be used to differentiate between the 32-bit IA-32 processors:
•
Bit 18 (the AC flag) can be used to distinguish an Intel386 processor from the P6 family, Pentium, and Intel486
processors. Since it is not implemented on the Intel386 processor, it will always be clear.
•
Bit 21 (the ID flag) indicates whether an application can execute the CPUID instruction. The ability to set and
clear this bit indicates that the processor is a P6 family or Pentium processor. The CPUID instruction can then
be used to determine which processor.
•
Bits 19 (the VIF flag) and 20 (the VIP flag) will always be zero on processors that do not support virtual mode
extensions, which includes all 32-bit processors prior to the Pentium processor.
See Chapter 19, “Processor Identification and Feature Determination,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for more information on identifying processors.
22.17
STACK OPERATIONS
This section identifies the differences in stack implementation between the various IA-32 processors.
22.17.1
PUSH SP
The P6 family, Pentium, Intel486, Intel386, and Intel 286 processors push a different value on the stack for a PUSH
SP instruction than the 8086 processor. The 32-bit processors push the value of the SP register before it is decremented as part of the push operation; the 8086 processor pushes the value of the SP register after it is decremented. If the value pushed is important, replace PUSH SP instructions with the following three instructions:
PUSH BP
MOV BP, SP
XCHG BP, [BP]
This code functions as the 8086 processor PUSH SP instruction on the P6 family, Pentium, Intel486, Intel386, and
Intel 286 processors.
22.17.2
EFLAGS Pushed on the Stack
The setting of the stored values of bits 12 through 15 (which includes the IOPL field and the NT flag) in the EFLAGS
register by the PUSHF instruction, by interrupts, and by exceptions is different with the 32-bit IA-32 processors
than with the 8086 and Intel 286 processors. The differences are as follows:
•
•
•
8086 processor—bits 12 through 15 are always set.
Intel 286 processor—bits 12 through 15 are always cleared in real-address mode.
32-bit processors in real-address mode—bit 15 (reserved) is always cleared, and bits 12 through 14 have the
last value loaded into them.
22.18
X87 FPU
This section addresses the issues that must be faced when porting floating-point software designed to run on
earlier IA-32 processors and math coprocessors to a Pentium 4, Intel Xeon, P6 family, or Pentium processor with
integrated x87 FPU. To software, a Pentium 4, Intel Xeon, or P6 family processor looks very much like a Pentium
processor. Floating-point software which runs on a Pentium or Intel486 DX processor, or on an Intel486 SX
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ARCHITECTURE COMPATIBILITY
processor/Intel 487 SX math coprocessor system or an Intel386 processor/Intel 387 math coprocessor system,
will run with at most minor modifications on a Pentium 4, Intel Xeon, or P6 family processor. To port code directly
from an Intel 286 processor/Intel 287 math coprocessor system or an Intel 8086 processor/8087 math coprocessor system to a Pentium 4, Intel Xeon, P6 family, or Pentium processor, certain additional issues must be
addressed.
In the following sections, the term “32-bit x87 FPUs” refers to the P6 family, Pentium, and Intel486 DX processors,
and to the Intel 487 SX and Intel 387 math coprocessors; the term “16-bit IA-32 math coprocessors” refers to the
Intel 287 and 8087 math coprocessors.
22.18.1 Control Register CR0 Flags
The ET, NE, and MP flags in control register CR0 control the interface between the integer unit of an IA-32 processor
and either its internal x87 FPU or an external math coprocessor. The effect of these flags in the various IA-32
processors are described in the following paragraphs.
The ET (extension type) flag (bit 4 of the CR0 register) is used in the Intel386 processor to indicate whether the
math coprocessor in the system is an Intel 287 math coprocessor (flag is clear) or an Intel 387 DX math coprocessor (flag is set). This bit is hardwired to 1 in the P6 family, Pentium, and Intel486 processors.
The NE (Numeric Exception) flag (bit 5 of the CR0 register) is used in the P6 family, Pentium, and Intel486 processors to determine whether unmasked floating-point exceptions are reported internally through interrupt vector 16
(flag is set) or externally through an external interrupt (flag is clear). On a hardware reset, the NE flag is initialized
to 0, so software using the automatic internal error-reporting mechanism must set this flag to 1. This flag is nonexistent on the Intel386 processor.
As on the Intel 286 and Intel386 processors, the MP (monitor coprocessor) flag (bit 1 of register CR0) determines
whether the WAIT/FWAIT instructions or waiting-type floating-point instructions trap when the context of the x87
FPU is different from that of the currently-executing task. If the MP and TS flag are set, then a WAIT/FWAIT instruction and waiting instructions will cause a device-not-available exception (interrupt vector 7). The MP flag is used on
the Intel 286 and Intel386 processors to support the use of a WAIT/FWAIT instruction to wait on a device other
than a math coprocessor. The device reports its status through the BUSY# pin. Since the P6 family, Pentium, and
Intel486 processors do not have such a pin, the MP flag has no relevant use and should be set to 1 for normal operation.
22.18.2 x87 FPU Status Word
This section identifies differences to the x87 FPU status word for the different IA-32 processors and math coprocessors, the reason for the differences, and their impact on software.
22.18.2.1 Condition Code Flags (C0 through C3)
The following information pertains to differences in the use of the condition code flags (C0 through C3) located in
bits 8, 9, 10, and 14 of the x87 FPU status word.
After execution of an FINIT instruction or a hardware reset on a 32-bit x87 FPU, the condition code flags are set to
0. The same operations on a 16-bit IA-32 math coprocessor leave these flags intact (they contain their prior value).
This difference in operation has no impact on software and provides a consistent state after reset.
Transcendental instruction results in the core range of the P6 family and Pentium processors may differ from the
Intel486 DX processor and Intel 487 SX math coprocessor by 2 to 3 units in the last place (ulps)—(see “Transcendental Instruction Accuracy” in Chapter 8, “Programming with the x87 FPU,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). As a result, the value saved in the C1 flag may also differ.
After an incomplete FPREM/FPREM1 instruction, the C0, C1, and C3 flags are set to 0 on the 32-bit x87 FPUs. After
the same operation on a 16-bit IA-32 math coprocessor, these flags are left intact.
On the 32-bit x87 FPUs, the C2 flag serves as an incomplete flag for the FTAN instruction. On the 16-bit IA-32 math
coprocessors, the C2 flag is undefined for the FPTAN instruction. This difference has no impact on software,
because Intel 287 or 8087 programs do not check C2 after an FPTAN instruction. The use of this flag on later
processors allows fast checking of operand range.
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22.18.2.2 Stack Fault Flag
When unmasked stack overflow or underflow occurs on a 32-bit x87 FPU, the IE flag (bit 0) and the SF flag (bit 6)
of the x87 FPU status word are set to indicate a stack fault and condition code flag C1 is set or cleared to indicate
overflow or underflow, respectively. When unmasked stack overflow or underflow occurs on a 16-bit IA-32 math
coprocessor, only the IE flag is set. Bit 6 is reserved on these processors. The addition of the SF flag on a 32-bit x87
FPU has no impact on software. Existing exception handlers need not change, but may be upgraded to take advantage of the additional information.
22.18.3 x87 FPU Control Word
Only affine closure is supported for infinity control on a 32-bit x87 FPU. The infinity control flag (bit 12 of the x87
FPU control word) remains programmable on these processors, but has no effect. This change was made to
conform to the IEEE Standard 754 for Binary Floating-Point Arithmetic. On a 16-bit IA-32 math coprocessor, both
affine and projective closures are supported, as determined by the setting of bit 12. After a hardware reset, the
default value of bit 12 is projective. Software that requires projective infinity arithmetic may give different results.
22.18.4 x87 FPU Tag Word
When loading the tag word of a 32-bit x87 FPU, using an FLDENV, FRSTOR, or FXRSTOR (Pentium III processor only)
instruction, the processor examines the incoming tag and classifies the location only as empty or non-empty. Thus,
tag values of 00, 01, and 10 are interpreted by the processor to indicate a non-empty location. The tag value of 11
is interpreted by the processor to indicate an empty location. Subsequent operations on a non-empty register
always examine the value in the register, not the value in its tag. The FSTENV, FSAVE, and FXSAVE (Pentium III
processor only) instructions examine the non-empty registers and put the correct values in the tags before storing
the tag word.
The corresponding tag for a 16-bit IA-32 math coprocessor is checked before each register access to determine the
class of operand in the register; the tag is updated after every change to a register so that the tag always reflects
the most recent status of the register. Software can load a tag with a value that disagrees with the contents of a
register (for example, the register contains a valid value, but the tag says special). Here, the 16-bit IA-32 math
coprocessors honor the tag and do not examine the register.
Software written to run on a 16-bit IA-32 math coprocessor may not operate correctly on a 16-bit x87 FPU, if it uses
the FLDENV, FRSTOR, or FXRSTOR instructions to change tags to values (other than to empty) that are different
from actual register contents.
The encoding in the tag word for the 32-bit x87 FPUs for unsupported data formats (including pseudo-zero and
unnormal) is special (10B), to comply with IEEE Standard 754. The encoding in the 16-bit IA-32 math coprocessors
for pseudo-zero and unnormal is valid (00B) and the encoding for other unsupported data formats is special (10B).
Code that recognizes the pseudo-zero or unnormal format as valid must therefore be changed if it is ported to a 32bit x87 FPU.
22.18.5 Data Types
This section discusses the differences of data types for the various x87 FPUs and math coprocessors.
22.18.5.1 NaNs
The 32-bit x87 FPUs distinguish between signaling NaNs (SNaNs) and quiet NaNs (QNaNs). These x87 FPUs only
generate QNaNs and normally do not generate an exception upon encountering a QNaN. An invalid-operation
exception (#I) is generated only upon encountering a SNaN, except for the FCOM, FIST, and FBSTP instructions,
which also generates an invalid-operation exceptions for a QNaNs. This behavior matches IEEE Standard 754.
The 16-bit IA-32 math coprocessors only generate one kind of NaN (the equivalent of a QNaN), but the raise an
invalid-operation exception upon encountering any kind of NaN.
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When porting software written to run on a 16-bit IA-32 math coprocessor to a 32-bit x87 FPU, uninitialized memory
locations that contain QNaNs should be changed to SNaNs to cause the x87 FPU or math coprocessor to fault when
uninitialized memory locations are referenced.
22.18.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats
The 32-bit x87 FPUs neither generate nor support the pseudo-zero, pseudo-NaN, pseudo-infinity, and unnormal
formats. Whenever they encounter them in an arithmetic operation, they raise an invalid-operation exception. The
16-bit IA-32 math coprocessors define and support special handling for these formats. Support for these formats
was dropped to conform with IEEE Standard 754 for Binary Floating-Point Arithmetic.
This change should not impact software ported from 16-bit IA-32 math coprocessors to 32-bit x87 FPUs. The 32bit x87 FPUs do not generate these formats, and therefore will not encounter them unless software explicitly loads
them in the data registers. The only affect may be in how software handles the tags in the tag word (see also:
Section 22.18.4, “x87 FPU Tag Word”).
22.18.6 Floating-Point Exceptions
This section identifies the implementation differences in exception handling for floating-point instructions in the
various x87 FPUs and math coprocessors.
22.18.6.1 Denormal Operand Exception (#D)
When the denormal operand exception is masked, the 32-bit x87 FPUs automatically normalize denormalized
numbers when possible; whereas, the 16-bit IA-32 math coprocessors return a denormal result. A program written
to run on a 16-bit IA-32 math coprocessor that uses the denormal exception solely to normalize denormalized
operands is redundant when run on the 32-bit x87 FPUs. If such a program is run on 32-bit x87 FPUs, performance
can be improved by masking the denormal exception. Floating-point programs run faster when the FPU performs
normalization of denormalized operands.
The denormal operand exception is not raised for transcendental instructions and the FXTRACT instruction on the
16-bit IA-32 math coprocessors. This exception is raised for these instructions on the 32-bit x87 FPUs. The exception handlers ported to these latter processors need to be changed only if the handlers gives special treatment to
different opcodes.
22.18.6.2 Numeric Overflow Exception (#O)
On the 32-bit x87 FPUs, when the numeric overflow exception is masked and the rounding mode is set to chop
(toward 0), the result is the largest positive or smallest negative number. The 16-bit IA-32 math coprocessors do
not signal the overflow exception when the masked response is not ∞; that is, they signal overflow only when the
rounding control is not set to round to 0. If rounding is set to chop (toward 0), the result is positive or negative ∞.
Under the most common rounding modes, this difference has no impact on existing software.
If rounding is toward 0 (chop), a program on a 32-bit x87 FPU produces, under overflow conditions, a result that is
different in the least significant bit of the significand, compared to the result on a 16-bit IA-32 math coprocessor.
The reason for this difference is IEEE Standard 754 compatibility.
When the overflow exception is not masked, the precision exception is flagged on the 32-bit x87 FPUs. When the
result is stored in the stack, the significand is rounded according to the precision control (PC) field of the FPU
control word or according to the opcode. On the 16-bit IA-32 math coprocessors, the precision exception is not
flagged and the significand is not rounded. The impact on existing software is that if the result is stored on the
stack, a program running on a 32-bit x87 FPU produces a different result under overflow conditions than on a 16bit IA-32 math coprocessor. The difference is apparent only to the exception handler. This difference is for IEEE
Standard 754 compatibility.
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22.18.6.3 Numeric Underflow Exception (#U)
When the underflow exception is masked on the 32-bit x87 FPUs, the underflow exception is signaled when the
result is tiny and inexact (see Section 4.9.1.5, “Numeric Underflow Exception (#U)” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). When the underflow exception is unmasked and the instruction
is supposed to store the result on the stack, the significand is rounded to the appropriate precision (according to
the PC flag in the FPU control word, for those instructions controlled by PC, otherwise to extended precision), after
adjusting the exponent.
22.18.6.4 Exception Precedence
There is no difference in the precedence of the denormal-operand exception on the 32-bit x87 FPUs, whether it be
masked or not. When the denormal-operand exception is not masked on the 16-bit IA-32 math coprocessors, it
takes precedence over all other exceptions. This difference causes no impact on existing software, but some
unneeded normalization of denormalized operands is prevented on the Intel486 processor and Intel 387 math
coprocessor.
22.18.6.5 CS and EIP For FPU Exceptions
On the Intel 32-bit x87 FPUs, the values from the CS and EIP registers saved for floating-point exceptions point to
any prefixes that come before the floating-point instruction. On the 8087 math coprocessor, the saved CS and IP
registers points to the floating-point instruction.
22.18.6.6 FPU Error Signals
The floating-point error signals to the P6 family, Pentium, and Intel486 processors do not pass through an interrupt
controller; an INT# signal from an Intel 387, Intel 287 or 8087 math coprocessors does. If an 8086 processor uses
another exception for the 8087 interrupt, both exception vectors should call the floating-point-error exception
handler. Some instructions in a floating-point-error exception handler may need to be deleted if they use the interrupt controller. The P6 family, Pentium, and Intel486 processors have signals that, with the addition of external
logic, support reporting for emulation of the interrupt mechanism used in many personal computers.
On the P6 family, Pentium, and Intel486 processors, an undefined floating-point opcode will cause an invalidopcode exception (#UD, interrupt vector 6). Undefined floating-point opcodes, like legal floating-point opcodes,
cause a device not available exception (#NM, interrupt vector 7) when either the TS or EM flag in control register
CR0 is set. The P6 family, Pentium, and Intel486 processors do not check for floating-point error conditions on
encountering an undefined floating-point opcode.
22.18.6.7 Assertion of the FERR# Pin
When using the MS-DOS compatibility mode for handing floating-point exceptions, the FERR# pin must be
connected to an input to an external interrupt controller. An external interrupt is then generated when the FERR#
output drives the input to the interrupt controller and the interrupt controller in turn drives the INTR pin on the
processor.
For the P6 family and Intel386 processors, an unmasked floating-point exception always causes the FERR# pin to
be asserted upon completion of the instruction that caused the exception. For the Pentium and Intel486 processors, an unmasked floating-point exception may cause the FERR# pin to be asserted either at the end of the
instruction causing the exception or immediately before execution of the next floating-point instruction. (Note that
the next floating-point instruction would not be executed until the pending unmasked exception has been handled.)
See Appendix D, “Guidelines for Writing x87 FPU Extension Handlers,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for a complete description of the required mechanism for handling
floating-point exceptions using the MS-DOS compatibility mode.
Using FERR# and IGNNE# to handle floating-point exception is deprecated by modern operating systems; this
approach also limits newer processors to operate with one logical processor active.
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22.18.6.8 Invalid Operation Exception On Denormals
An invalid-operation exception is not generated on the 32-bit x87 FPUs upon encountering a denormal value when
executing a FSQRT, FDIV, or FPREM instruction or upon conversion to BCD or to integer. The operation proceeds by
first normalizing the value. On the 16-bit IA-32 math coprocessors, upon encountering this situation, the invalidoperation exception is generated. This difference has no impact on existing software. Software running on the 32bit x87 FPUs continues to execute in cases where the 16-bit IA-32 math coprocessors trap. The reason for this
change was to eliminate an exception from being raised.
22.18.6.9 Alignment Check Exceptions (#AC)
If alignment checking is enabled, a misaligned data operand on the P6 family, Pentium, and Intel486 processors
causes an alignment check exception (#AC) when a program or procedure is running at privilege-level 3, except
for the stack portion of the FSAVE/FNSAVE, FXSAVE, FRSTOR, and FXRSTOR instructions.
22.18.6.10 Segment Not Present Exception During FLDENV
On the Intel486 processor, when a segment not present exception (#NP) occurs in the middle of an FLDENV
instruction, it can happen that part of the environment is loaded and part not. In such cases, the FPU control word
is left with a value of 007FH. The P6 family and Pentium processors ensure the internal state is correct at all times
by attempting to read the first and last bytes of the environment before updating the internal state.
22.18.6.11 Device Not Available Exception (#NM)
The device-not-available exception (#NM, interrupt 7) will occur in the P6 family, Pentium, and Intel486 processors
as described in Section 2.5, “Control Registers,” Table 2-2, and Chapter 6, “Interrupt 7—Device Not Available
Exception (#NM).”
22.18.6.12 Coprocessor Segment Overrun Exception
The coprocessor segment overrun exception (interrupt 9) does not occur in the P6 family, Pentium, and Intel486
processors. In situations where the Intel 387 math coprocessor would cause an interrupt 9, the P6 family, Pentium,
and Intel486 processors simply abort the instruction. To avoid undetected segment overruns, it is recommended
that the floating-point save area be placed in the same page as the TSS. This placement will prevent the FPU environment from being lost if a page fault occurs during the execution of an FLDENV, FRSTOR, or FXRSTOR instruction
while the operating system is performing a task switch.
22.18.6.13 General Protection Exception (#GP)
A general-protection exception (#GP, interrupt 13) occurs if the starting address of a floating-point operand falls
outside a segment’s size. An exception handler should be included to report these programming errors.
22.18.6.14 Floating-Point Error Exception (#MF)
In real mode and protected mode (not including virtual-8086 mode), interrupt vector 16 must point to the floatingpoint exception handler. In virtual-8086 mode, the virtual-8086 monitor can be programmed to accommodate a
different location of the interrupt vector for floating-point exceptions.
22.18.7 Changes to Floating-Point Instructions
This section identifies the differences in floating-point instructions for the various Intel FPU and math coprocessor
architectures, the reason for the differences, and their impact on software.
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22.18.7.1 FDIV, FPREM, and FSQRT Instructions
The 32-bit x87 FPUs support operations on denormalized operands and, when detected, an underflow exception
can occur, for compatibility with the IEEE Standard 754. The 16-bit IA-32 math coprocessors do not operate on
denormalized operands or return underflow results. Instead, they generate an invalid-operation exception when
they detect an underflow condition. An existing underflow exception handler will require change only if it gives
different treatment to different opcodes. Also, it is possible that fewer invalid-operation exceptions will occur.
22.18.7.2 FSCALE Instruction
With the 32-bit x87 FPUs, the range of the scaling operand is not restricted. If (0 < | ST(1) < 1), the scaling factor
is 0; therefore, ST(0) remains unchanged. If the rounded result is not exact or if there was a loss of accuracy
(masked underflow), the precision exception is signaled. With the 16-bit IA-32 math coprocessors, the range of the
scaling operand is restricted. If (0 < | ST(1) | < 1), the result is undefined and no exception is signaled. The
impact of this difference on exiting software is that different results are delivered on the 32-bit and 16-bit FPUs and
math coprocessors when (0 < | ST(1) | < 1).
22.18.7.3 FPREM1 Instruction
The 32-bit x87 FPUs compute a partial remainder according to IEEE Standard 754. This instruction does not exist
on the 16-bit IA-32 math coprocessors. The availability of the FPREM1 instruction has is no impact on existing software.
22.18.7.4 FPREM Instruction
On the 32-bit x87 FPUs, the condition code flags C0, C3, C1 in the status word correctly reflect the three low-order
bits of the quotient following execution of the FPREM instruction. On the 16-bit IA-32 math coprocessors, the
quotient bits are incorrect when performing a reduction of (64N + M) when (N ≥ 1) and M is 1 or 2. This difference
does not affect existing software; software that works around the bug should not be affected.
22.18.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions
When executing the FUCOM, FUCOMP, and FUCOMPP instructions, the 32-bit x87 FPUs perform unordered compare
according to IEEE Standard 754. These instructions do not exist on the 16-bit IA-32 math coprocessors. The availability of these new instructions has no impact on existing software.
22.18.7.6 FPTAN Instruction
On the 32-bit x87 FPUs, the range of the operand for the FPTAN instruction is much less restricted (| ST(0) | < 263)
than on earlier math coprocessors. The instruction reduces the operand internally using an internal π/4 constant
that is more accurate. The range of the operand is restricted to (| ST(0) | < π/4) on the 16-bit IA-32 math coprocessors; the operand must be reduced to this range using FPREM. This change has no impact on existing software.
See also sections 8.3.8 and section 8.3.10 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1 for more information on the accuracy of the FPTAN instruction.
22.18.7.7 Stack Overflow
On the 32-bit x87 FPUs, if an FPU stack overflow occurs when the invalid-operation exception is masked, the FPU
returns the real, integer, or BCD-integer indefinite value to the destination operand, depending on the instruction
being executed. On the 16-bit IA-32 math coprocessors, the original operand remains unchanged following a stack
overflow, but it is loaded into register ST(1). This difference has no impact on existing software.
22.18.7.8 FSIN, FCOS, and FSINCOS Instructions
On the 32-bit x87 FPUs, these instructions perform three common trigonometric functions. These instructions do
not exist on the 16-bit IA-32 math coprocessors. The availability of these instructions has no impact on existing
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software, but using them provides a performance upgrade. See also sections 8.3.8 and section 8.3.10 of the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for more information on the accuracy of the
FSIN, FCOS, and FSINCOS instructions.
22.18.7.9 FPATAN Instruction
On the 32-bit x87 FPUs, the range of operands for the FPATAN instruction is unrestricted. On the 16-bit IA-32 math
coprocessors, the absolute value of the operand in register ST(0) must be smaller than the absolute value of the
operand in register ST(1). This difference has impact on existing software.
22.18.7.10 F2XM1 Instruction
The 32-bit x87 FPUs support a wider range of operands (–1 < ST (0) < + 1) for the F2XM1 instruction. The
supported operand range for the 16-bit IA-32 math coprocessors is (0 ≤ ST(0) ≤ 0.5). This difference has no impact
on existing software.
22.18.7.11 FLD Instruction
On the 32-bit x87 FPUs, when using the FLD instruction to load an extended-real value, a denormal-operand
exception is not generated because the instruction is not arithmetic. The 16-bit IA-32 math coprocessors do report
a denormal-operand exception in this situation. This difference does not affect existing software.
On the 32-bit x87 FPUs, loading a denormal value that is in single- or double-real format causes the value to be
converted to extended-real format. Loading a denormal value on the 16-bit IA-32 math coprocessors causes the
value to be converted to an unnormal. If the next instruction is FXTRACT or FXAM, the 32-bit x87 FPUs will give a
different result than the 16-bit IA-32 math coprocessors. This change was made for IEEE Standard 754 compatibility.
On the 32-bit x87 FPUs, loading an SNaN that is in single- or double-real format causes the FPU to generate an
invalid-operation exception. The 16-bit IA-32 math coprocessors do not raise an exception when loading a
signaling NaN. The invalid-operation exception handler for 16-bit math coprocessor software needs to be updated
to handle this condition when porting software to 32-bit FPUs. This change was made for IEEE Standard 754
compatibility.
22.18.7.12 FXTRACT Instruction
On the 32-bit x87 FPUs, if the operand is 0 for the FXTRACT instruction, the divide-by-zero exception is reported
and –∞ is delivered to register ST(1). If the operand is +∞, no exception is reported. If the operand is 0 on the 16bit IA-32 math coprocessors, 0 is delivered to register ST(1) and no exception is reported. If the operand is +∞, the
invalid-operation exception is reported. These differences have no impact on existing software. Software usually
bypasses 0 and ∞. This change is due to the IEEE Standard 754 recommendation to fully support the “logb” function.
22.18.7.13 Load Constant Instructions
On 32-bit x87 FPUs, rounding control is in effect for the load constant instructions. Rounding control is not in effect
for the 16-bit IA-32 math coprocessors. Results for the FLDPI, FLDLN2, FLDLG2, and FLDL2E instructions are the
same as for the 16-bit IA-32 math coprocessors when rounding control is set to round to nearest or round to +∞.
They are the same for the FLDL2T instruction when rounding control is set to round to nearest, round to –∞, or
round to zero. Results are different from the 16-bit IA-32 math coprocessors in the least significant bit of the
mantissa if rounding control is set to round to –∞ or round to 0 for the FLDPI, FLDLN2, FLDLG2, and FLDL2E instructions; they are different for the FLDL2T instruction if round to +∞ is specified. These changes were implemented for
compatibility with IEEE Standard 754 for Floating-Point Arithmetic recommendations.
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22.18.7.14 FSETPM Instruction
With the 32-bit x87 FPUs, the FSETPM instruction is treated as NOP (no operation). This instruction informs the
Intel 287 math coprocessor that the processor is in protected mode. This change has no impact on existing software. The 32-bit x87 FPUs handle all addressing and exception-pointer information, whether in protected mode or
not.
22.18.7.15 FXAM Instruction
With the 32-bit x87 FPUs, if the FPU encounters an empty register when executing the FXAM instruction, it not
generate combinations of C0 through C3 equal to 1101 or 1111. The 16-bit IA-32 math coprocessors may generate
these combinations, among others. This difference has no impact on existing software; it provides a performance
upgrade to provide repeatable results.
22.18.7.16 FSAVE and FSTENV Instructions
With the 32-bit x87 FPUs, the address of a memory operand pointer stored by FSAVE or FSTENV is undefined if the
previous floating-point instruction did not refer to memory
22.18.8 Transcendental Instructions
The floating-point results of the P6 family and Pentium processors for transcendental instructions in the core range
may differ from the Intel486 processors by about 2 or 3 ulps (see “Transcendental Instruction Accuracy” in Chapter
8, “Programming with the x87 FPU,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1). Condition code flag C1 of the status word may differ as a result. The exact threshold for underflow and
overflow will vary by a few ulps. The P6 family and Pentium processors’ results will have a worst case error of less
than 1 ulp when rounding to the nearest-even and less than 1.5 ulps when rounding in other modes. The transcendental instructions are guaranteed to be monotonic, with respect to the input operands, throughout the domain
supported by the instruction.
Transcendental instructions may generate different results in the round-up flag (C1) on the 32-bit x87 FPUs. The
round-up flag is undefined for these instructions on the 16-bit IA-32 math coprocessors. This difference has no
impact on existing software.
22.18.9 Obsolete Instructions
The 8087 math coprocessor instructions FENI and FDISI and the Intel 287 math coprocessor instruction FSETPM
are treated as integer NOP instructions in the 32-bit x87 FPUs. If these opcodes are detected in the instruction
stream, no specific operation is performed and no internal states are affected.
22.18.10 WAIT/FWAIT Prefix Differences
On the Intel486 processor, when a WAIT/FWAIT instruction precedes a floating-point instruction (one which itself
automatically synchronizes with the previous floating-point instruction), the WAIT/FWAIT instruction is treated as
a no-op. Pending floating-point exceptions from a previous floating-point instruction are processed not on the
WAIT/FWAIT instruction but on the floating-point instruction following the WAIT/FWAIT instruction. In such a case,
the report of a floating-point exception may appear one instruction later on the Intel486 processor than on a P6
family or Pentium FPU, or on Intel 387 math coprocessor.
22.18.11 Operands Split Across Segments and/or Pages
On the P6 family, Pentium, and Intel486 processor FPUs, when the first half of an operand to be written is inside a
page or segment and the second half is outside, a memory fault can cause the first half to be stored but not the
second half. In this situation, the Intel 387 math coprocessor stores nothing.
22-14 Vol. 3B
ARCHITECTURE COMPATIBILITY
22.18.12 FPU Instruction Synchronization
On the 32-bit x87 FPUs, all floating-point instructions are automatically synchronized; that is, the processor automatically waits until the previous floating-point instruction has completed before completing the next floating-point
instruction. No explicit WAIT/FWAIT instructions are required to assure this synchronization. For the 8087 math
coprocessors, explicit waits are required before each floating-point instruction to ensure synchronization. Although
8087 programs having explicit WAIT instructions execute perfectly on the 32-bit IA-32 processors without reassembly, these WAIT instructions are unnecessary.
22.19
SERIALIZING INSTRUCTIONS
Certain instructions have been defined to serialize instruction execution to ensure that modifications to flags, registers and memory are completed before the next instruction is executed (or in P6 family processor terminology
“committed to machine state”). Because the P6 family processors use branch-prediction and out-of-order execution techniques to improve performance, instruction execution is not generally serialized until the results of an
executed instruction are committed to machine state (see Chapter 2, “Intel® 64 and IA-32 Architectures,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
As a result, at places in a program or task where it is critical to have execution completed for all previous instructions before executing the next instruction (for example, at a branch, at the end of a procedure, or in multiprocessor dependent code), it is useful to add a serializing instruction. See Section 8.3, “Serializing Instructions,” for
more information on serializing instructions.
22.20
FPU AND MATH COPROCESSOR INITIALIZATION
Table 9-1 shows the states of the FPUs in the P6 family, Pentium, Intel486 processors and of the Intel 387 math
coprocessor and Intel 287 coprocessor following a power-up, reset, or INIT, or following the execution of an
FINIT/FNINIT instruction. The following is some additional compatibility information concerning the initialization of
x87 FPUs and math coprocessors.
22.20.1 Intel® 387 and Intel® 287 Math Coprocessor Initialization
Following an Intel386 processor reset, the processor identifies its coprocessor type (Intel® 287 or Intel® 387 DX
math coprocessor) by sampling its ERROR# input some time after the falling edge of RESET# signal and before
execution of the first floating-point instruction. The Intel 287 coprocessor keeps its ERROR# output in inactive
state after hardware reset; the Intel 387 coprocessor keeps its ERROR# output in active state after hardware
reset.
Upon hardware reset or execution of the FINIT/FNINIT instruction, the Intel 387 math coprocessor signals an error
condition. The P6 family, Pentium, and Intel486 processors, like the Intel 287 coprocessor, do not.
22.20.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization
When initializing an Intel486 SX processor and an Intel 487 SX math coprocessor, the initialization routine should
check the presence of the math coprocessor and should set the FPU related flags (EM, MP, and NE) in control
register CR0 accordingly (see Section 2.5, “Control Registers,” for a complete description of these flags). Table
22-2 gives the recommended settings for these flags when the math coprocessor is present. The FSTCW instruction
will give a value of FFFFH for the Intel486 SX microprocessor and 037FH for the Intel 487 SX math coprocessor.
Vol. 3B 22-15
ARCHITECTURE COMPATIBILITY
Table 22-2. Recommended Values of the EM, MP, and NE Flags for Intel486 SX Microprocessor/Intel 487 SX Math
Coprocessor System
CR0 Flags
Intel486 SX Processor Only
EM
1
Intel 487 SX Math Coprocessor Present
0
MP
0
1
NE
1
0, for MS-DOS* systems
1, for user-defined exception handler
The EM and MP flags in register CR0 are interpreted as shown in Table 22-3.
Table 22-3. EM and MP Flag Interpretation
EM
MP
Interpretation
0
0
Floating-point instructions are passed to FPU; WAIT/FWAIT and other waiting-type instructions
ignore TS.
0
1
Floating-point instructions are passed to FPU; WAIT/FWAIT and other waiting-type instructions
test TS.
1
0
Floating-point instructions trap to emulator; WAIT/FWAIT and other waiting-type instructions
ignore TS.
1
1
Floating-point instructions trap to emulator; WAIT/FWAIT and other waiting-type instructions
test TS.
Following is an example code sequence to initialize the system and check for the presence of Intel486 SX
processor/Intel 487 SX math coprocessor.
fninit
fstcw mem_loc
mov ax, mem_loc
cmp ax, 037fh
jz Intel487_SX_Math_CoProcessor_present
jmp Intel486_SX_microprocessor_present
;ax=037fh
;ax=ffffh
If the Intel 487 SX math coprocessor is not present, the following code can be run to set the CR0 register for the
Intel486 SX processor.
mov eax, cr0
and eax, fffffffdh ;make MP=0
or eax, 0024h
;make EM=1, NE=1
mov cr0, eax
This initialization will cause any floating-point instruction to generate a device not available exception (#NH), interrupt 7. The software emulation will then take control to execute these instructions. This code is not required if an
Intel 487 SX math coprocessor is present in the system. In that case, the typical initialization routine for the
Intel486 SX microprocessor will be adequate.
Also, when designing an Intel486 SX processor based system with an Intel 487 SX math coprocessor, timing loops
should be independent of frequency and clocks per instruction. One way to attain this is to implement these loops
in hardware and not in software (for example, BIOS).
22.21
CONTROL REGISTERS
The following sections identify the new control registers and control register flags and fields that were introduced
to the 32-bit IA-32 in various processor families. See Figure 2-7 for the location of these flags and fields in the
control registers.
22-16 Vol. 3B
ARCHITECTURE COMPATIBILITY
The Pentium III processor introduced one new control flag in control register CR4:
•
OSXMMEXCPT (bit 10) — The OS will set this bit if it supports unmasked SIMD floating-point exceptions.
The Pentium II processor introduced one new control flag in control register CR4:
•
OSFXSR (bit 9) — The OS supports saving and restoring the Pentium III processor state during context
switches.
The Pentium Pro processor introduced three new control flags in control register CR4:
•
PAE (bit 5) — Physical address extension. Enables paging mechanism to reference extended physical addresses
when set; restricts physical addresses to 32 bits when clear (see also: Section 22.22.1.1, “Physical Memory
Addressing Extension”).
•
PGE (bit 7) — Page global enable. Inhibits flushing of frequently-used or shared pages on CR3 writes (see also:
Section 22.22.1.2, “Global Pages”).
•
PCE (bit 8) — Performance-monitoring counter enable. Enables execution of the RDPMC instruction at any
protection level.
The content of CR4 is 0H following a hardware reset.
Control register CR4 was introduced in the Pentium processor. This register contains flags that enable certain new
extensions provided in the Pentium processor:
•
VME — Virtual-8086 mode extensions. Enables support for a virtual interrupt flag in virtual-8086 mode (see
Section 20.3, “Interrupt and Exception Handling in Virtual-8086 Mode”).
•
PVI — Protected-mode virtual interrupts. Enables support for a virtual interrupt flag in protected mode (see
Section 20.4, “Protected-Mode Virtual Interrupts”).
•
TSD — Time-stamp disable. Restricts the execution of the RDTSC instruction to procedures running at
privileged level 0.
•
DE — Debugging extensions. Causes an undefined opcode (#UD) exception to be generated when debug
registers DR4 and DR5 are references for improved performance (see Section 22.23.3, “Debug Registers DR4
and DR5”).
•
PSE — Page size extensions. Enables 4-MByte pages with 32-bit paging when set (see Section 4.3, “32-Bit
Paging”).
•
MCE — Machine-check enable. Enables the machine-check exception, allowing exception handling for certain
hardware error conditions (see Chapter 15, “Machine-Check Architecture”).
The Intel486 processor introduced five new flags in control register CR0:
•
•
•
NE — Numeric error. Enables the normal mechanism for reporting floating-point numeric errors.
•
NW — Not write-through. Enables write-throughs and cache invalidation cycles when clear and disables invalidation cycles and write-throughs that hit in the cache when set.
•
CD — Cache disable. Enables the internal cache when clear and disables the cache when set.
WP — Write protect. Write-protects read-only pages against supervisor-mode accesses.
AM — Alignment mask. Controls whether alignment checking is performed. Operates in conjunction with the AC
(Alignment Check) flag.
The Intel486 processor introduced two new flags in control register CR3:
•
PCD — Page-level cache disable. The state of this flag is driven on the PCD# pin during bus cycles that are not
paged, such as interrupt acknowledge cycles, when paging is enabled. The PCD# pin is used to control caching
in an external cache on a cycle-by-cycle basis.
•
PWT — Page-level write-through. The state of this flag is driven on the PWT# pin during bus cycles that are not
paged, such as interrupt acknowledge cycles, when paging is enabled. The PWT# pin is used to control write
through in an external cache on a cycle-by-cycle basis.
Vol. 3B 22-17
ARCHITECTURE COMPATIBILITY
22.22
MEMORY MANAGEMENT FACILITIES
The following sections describe the new memory management facilities available in the various IA-32 processors
and some compatibility differences.
22.22.1 New Memory Management Control Flags
The Pentium Pro processor introduced three new memory management features: physical memory addressing
extension, the global bit in page-table entries, and general support for larger page sizes. These features are only
available when operating in protected mode.
22.22.1.1 Physical Memory Addressing Extension
The new PAE (physical address extension) flag in control register CR4, bit 5, may enable additional address lines on
the processor, allowing extended physical addresses. This option can only be used when paging is enabled, using a
new page-table mechanism provided to support the larger physical address range (see Section 4.1, “Paging Modes
and Control Bits”).
22.22.1.2 Global Pages
The new PGE (page global enable) flag in control register CR4, bit 7, provides a mechanism for preventing
frequently used pages from being flushed from the translation lookaside buffer (TLB). When this flag is set,
frequently used pages (such as pages containing kernel procedures or common data tables) can be marked global
by setting the global flag in a page-directory or page-table entry.
On a task switch or a write to control register CR3 (which normally causes the TLBs to be flushed), the entries in
the TLB marked global are not flushed. Marking pages global in this manner prevents unnecessary reloading of the
TLB due to TLB misses on frequently used pages. See Section 4.10, “Caching Translation Information” for a detailed
description of this mechanism.
22.22.1.3 Larger Page Sizes
The P6 family processors support large page sizes. For 32-bit paging, this facility is enabled with the PSE (page size
extension) flag in control register CR4, bit 4. When this flag is set, the processor supports either 4-KByte or 4MByte page sizes. PAE paging and IA-32e paging support 2-MByte pages regardless of the value of CR4.PSE (see
Section 4.4, “PAE Paging” and Section 4.5, “IA-32e Paging”). See Chapter 4, “Paging,” for more information about
large page sizes.
22.22.2 CD and NW Cache Control Flags
The CD and NW flags in control register CR0 were introduced in the Intel486 processor. In the P6 family and
Pentium processors, these flags are used to implement a writeback strategy for the data cache; in the Intel486
processor, they implement a write-through strategy. See Table 11-5 for a comparison of these bits on the P6 family,
Pentium, and Intel486 processors. For complete information on caching, see Chapter 11, “Memory Cache Control.”
22.22.3 Descriptor Types and Contents
Operating-system code that manages space in descriptor tables often contains an invalid value in the access-rights
field of descriptor-table entries to identify unused entries. Access rights values of 80H and 00H remain invalid for
the P6 family, Pentium, Intel486, Intel386, and Intel 286 processors. Other values that were invalid on the Intel
286 processor may be valid on the 32-bit processors because uses for these bits have been defined.
22-18 Vol. 3B
ARCHITECTURE COMPATIBILITY
22.22.4 Changes in Segment Descriptor Loads
On the Intel386 processor, loading a segment descriptor always causes a locked read and write to set the accessed
bit of the descriptor. On the P6 family, Pentium, and Intel486 processors, the locked read and write occur only if the
bit is not already set.
22.23
DEBUG FACILITIES
The P6 family and Pentium processors include extensions to the Intel486 processor debugging support for breakpoints. To use the new breakpoint features, it is necessary to set the DE flag in control register CR4.
22.23.1 Differences in Debug Register DR6
It is not possible to write a 1 to reserved bit 12 in debug status register DR6 on the P6 family and Pentium processors; however, it is possible to write a 1 in this bit on the Intel486 processor. See Table 9-1 for the different setting
of this register following a power-up or hardware reset.
22.23.2 Differences in Debug Register DR7
The P6 family and Pentium processors determines the type of breakpoint access by the R/W0 through R/W3 fields
in debug control register DR7 as follows:
00
Break on instruction execution only.
01
Break on data writes only.
10
Undefined if the DE flag in control register CR4 is cleared; break on I/O reads or writes but not instruction
fetches if the DE flag in control register CR4 is set.
11
Break on data reads or writes but not instruction fetches.
On the P6 family and Pentium processors, reserved bits 11, 12, 14 and 15 are hard-wired to 0. On the Intel486
processor, however, bit 12 can be set. See Table 9-1 for the different settings of this register following a power-up
or hardware reset.
22.23.3 Debug Registers DR4 and DR5
Although the DR4 and DR5 registers are documented as reserved, previous generations of processors aliased
references to these registers to debug registers DR6 and DR7, respectively. When debug extensions are not
enabled (the DE flag in control register CR4 is cleared), the P6 family and Pentium processors remain compatible
with existing software by allowing these aliased references. When debug extensions are enabled (the DE flag is
set), attempts to reference registers DR4 or DR5 will result in an invalid-opcode exception (#UD).
22.24
RECOGNITION OF BREAKPOINTS
For the Pentium processor, it is recommended that debuggers execute the LGDT instruction before returning to the
program being debugged to ensure that breakpoints are detected. This operation does not need to be performed
on the P6 family, Intel486, or Intel386 processors.
The implementation of test registers on the Intel486 processor used for testing the cache and TLB has been redesigned using MSRs on the P6 family and Pentium processors. (Note that MSRs used for this function are different
on the P6 family and Pentium processors.) The MOV to and from test register instructions generate invalid-opcode
exceptions (#UD) on the P6 family processors.
Vol. 3B 22-19
ARCHITECTURE COMPATIBILITY
22.25
EXCEPTIONS AND/OR EXCEPTION CONDITIONS
This section describes the new exceptions and exception conditions added to the 32-bit IA-32 processors and
implementation differences in existing exception handling. See Chapter 6, “Interrupt and Exception Handling,” for
a detailed description of the IA-32 exceptions.
The Pentium III processor introduced new state with the XMM registers. Computations involving data in these registers can produce exceptions. A new MXCSR control/status register is used to determine which exception or exceptions have occurred. When an exception associated with the XMM registers occurs, an interrupt is generated.
•
SIMD floating-point exception (#XM, interrupt 19) — New exceptions associated with the SIMD floating-point
registers and resulting computations.
No new exceptions were added with the Pentium Pro and Pentium II processors. The set of available exceptions is
the same as for the Pentium processor. However, the following exception condition was added to the IA-32 with the
Pentium Pro processor:
•
Machine-check exception (#MC, interrupt 18) — New exception conditions. Many exception conditions have
been added to the machine-check exception and a new architecture has been added for handling and reporting
on hardware errors. See Chapter 15, “Machine-Check Architecture,” for a detailed description of the new
conditions.
The following exceptions and/or exception conditions were added to the IA-32 with the Pentium processor:
•
Machine-check exception (#MC, interrupt 18) — New exception. This exception reports parity and other
hardware errors. It is a model-specific exception and may not be implemented or implemented differently in
future processors. The MCE flag in control register CR4 enables the machine-check exception. When this bit is
clear (which it is at reset), the processor inhibits generation of the machine-check exception.
•
General-protection exception (#GP, interrupt 13) — New exception condition added. An attempt to write a 1 to
a reserved bit position of a special register causes a general-protection exception to be generated.
•
Page-fault exception (#PF, interrupt 14) — New exception condition added. When a 1 is detected in any of the
reserved bit positions of a page-table entry, page-directory entry, or page-directory pointer during address
translation, a page-fault exception is generated.
The following exception was added to the Intel486 processor:
•
Alignment-check exception (#AC, interrupt 17) — New exception. Reports unaligned memory references when
alignment checking is being performed.
The following exceptions and/or exception conditions were added to the Intel386 processor:
•
Divide-error exception (#DE, interrupt 0)
— Change in exception handling. Divide-error exceptions on the Intel386 processors always leave the saved
CS:IP value pointing to the instruction that failed. On the 8086 processor, the CS:IP value points to the next
instruction.
— Change in exception handling. The Intel386 processors can generate the largest negative number as a
quotient for the IDIV instruction (80H and 8000H). The 8086 processor generates a divide-error exception
instead.
•
Invalid-opcode exception (#UD, interrupt 6) — New exception condition added. Improper use of the LOCK
instruction prefix can generate an invalid-opcode exception.
•
Page-fault exception (#PF, interrupt 14) — New exception condition added. If paging is enabled in a 16-bit
program, a page-fault exception can be generated as follows. Paging can be used in a system with 16-bit tasks
if all tasks use the same page directory. Because there is no place in a 16-bit TSS to store the PDBR register,
switching to a 16-bit task does not change the value of the PDBR register. Tasks ported from the Intel 286
processor should be given 32-bit TSSs so they can make full use of paging.
•
General-protection exception (#GP, interrupt 13) — New exception condition added. The Intel386 processor
sets a limit of 15 bytes on instruction length. The only way to violate this limit is by putting redundant prefixes
before an instruction. A general-protection exception is generated if the limit on instruction length is violated.
The 8086 processor has no instruction length limit.
22-20 Vol. 3B
ARCHITECTURE COMPATIBILITY
22.25.1 Machine-Check Architecture
The Pentium Pro processor introduced a new architecture to the IA-32 for handling and reporting on machinecheck exceptions. This machine-check architecture (described in detail in Chapter 15, “MachineCheck Architecture”) greatly expands the ability of the processor to report on internal hardware errors.
22.25.2 Priority of Exceptions
The priority of exceptions are broken down into several major categories:
1. Traps on the previous instruction
2. External interrupts
3. Faults on fetching the next instruction
4. Faults in decoding the next instruction
5. Faults on executing an instruction
There are no changes in the priority of these major categories between the different processors, however, exceptions within these categories are implementation dependent and may change from processor to processor.
22.25.3 Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers
MMX instructions and a subset of SSE, SSE2, SSSE3 instructions operate on MMX registers. The exception conditions of these instructions are described in the following tables.
Real
Virtual-8086
Protected and
Compatibility
64-bit
Table 22-4. Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment
X
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
X
X
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H)
X
X
X
X
If any corresponding CPUID feature flag is ‘0’
#MF
X
X
X
X
If there is a pending X87 FPU exception
#NM
X
X
X
X
If CR0.TS[bit 3]=1
Exception
Invalid Opcode,
#UD
X
Stack, SS(0)
X
X
X
#PF(fault-code)
Applicable
Instructions
For an illegal address in the SS segment
X
If a memory address referencing the SS segment is in a non-canonical form
X
Legacy SSE: Memory operand is not 16-byte aligned
X
If the memory address is in a non-canonical form.
X
General Protection, #GP(0)
#XM
X
X
Cause of Exception
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
If any part of the operand lies outside the effective address space from 0 to FFFFH
X
X
X
For a page fault
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1
CVTPD2PI, CVTTPD2PI
Vol. 3B 22-21
ARCHITECTURE COMPATIBILITY
Virtual-8086
Protected and
Compatibility
64-bit
Exception
Real
Table 22-5. Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception
X
X
X
X
Cause of Exception
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
X
X
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H)
X
X
X
X
If any corresponding CPUID feature flag is ‘0’
#MF
X
X
X
X
If there is a pending X87 FPU exception
#NM
X
X
X
X
If CR0.TS[bit 3]=1
Invalid Opcode, #UD
X
Stack, SS(0)
For an illegal address in the SS segment
X
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH
X
#PF(fault-code)
X
X
X
For a page fault
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made while
the current privilege level is 3.
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1
SIMD Floating-point
Exception, #XM
Applicable Instructions
22-22 Vol. 3B
X
CVTPI2PS, CVTPS2PI, CVTTPS2PI
ARCHITECTURE COMPATIBILITY
Real
Virtual-8086
Protected and
Compatibility
64-bit
Table 22-6. Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception
X
X
X
X
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H)
X
X
X
X
If any corresponding CPUID feature flag is ‘0’
#MF1
X
X
X
X
If there is a pending X87 FPU exception
#NM
X
X
X
X
If CR0.TS[bit 3]=1
Exception
Invalid Opcode, #UD
X
Stack, SS(0)
For an illegal address in the SS segment
X
X
X
If a memory address referencing the SS segment is in a non-canonical form
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
Cause of Exception
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH
X
#PF(fault-code)
X
X
X
For a page fault
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made
while the current privilege level is 3.
Applicable Instructions
CVTPI2PD
NOTES:
1. Applies to “CVTPI2PD xmm, mm” but not “CVTPI2PD xmm, m64”.
Vol. 3B 22-23
ARCHITECTURE COMPATIBILITY
Invalid Opcode, #UD
64-bit
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 22-7. Exception Conditions for SIMD/MMX Instructions with Memory Reference
Cause of Exception
X
X
X
X
If CR0.EM[bit 2] = 1.
X
X
X
X
If preceded by a LOCK prefix (F0H)
X
X
X
X
If any corresponding CPUID feature flag is ‘0’
#MF
X
X
X
X
If there is a pending X87 FPU exception
#NM
X
X
X
X
If CR0.TS[bit 3]=1
X
Stack, SS(0)
For an illegal address in the SS segment
X
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH
#PF(fault-code)
X
X
X
For a page fault
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made while
the current privilege level is 3.
Applicable Instructions
22-24 Vol. 3B
PABSB, PABSD, PABSW, PACKSSWB, PACKSSDW, PACKUSWB, PADDB, PADDD, PADDQ, PADDW, PADDSB,
PADDSW, PADDUSB, PADDUSW, PALIGNR, PAND, PANDN, PAVGB, PAVGW, PCMPEQB, PCMPEQD, PCMPEQW,
PCMPGTB, PCMPGTD, PCMPGTW, PHADDD, PHADDW, PHADDSW, PHSUBD, PHSUBW, PHSUBSW, PINSRW,
PMADDUBSW, PMADDWD, PMAXSW, PMAXUB, PMINSW, PMINUB, PMULHRSW, PMULHUW, PMULHW, PMULLW,
PMULUDQ, PSADBW, PSHUFB, PSHUFW, PSIGNB PSIGND PSIGNW, PSLLW, PSLLD, PSLLQ, PSRAD, PSRAW,
PSRLW, PSRLD, PSRLQ, PSUBB, PSUBD, PSUBQ, PSUBW, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW,
PUNPCKHBW, PUNPCKHWD, PUNPCKHDQ, PUNPCKLBW, PUNPCKLWD, PUNPCKLDQ, PXOR
ARCHITECTURE COMPATIBILITY
Real
Virtual-8086
Protected and
Compatibility
64-bit
Table 22-8. Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception
X
X
X
X
If CR0.EM[bit 2] = 1.
If ModR/M.mod ≠ 11b1
X
X
X
X
If preceded by a LOCK prefix (F0H)
X
X
X
X
If any corresponding CPUID feature flag is ‘0’
#MF
X
X
X
X
If there is a pending X87 FPU exception
#NM
X
X
X
X
If CR0.TS[bit 3]=1
Exception
Invalid Opcode, #UD
X
Stack, SS(0)
For an illegal address in the SS segment
X
If a memory address referencing the SS segment is in a non-canonical form
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the destination operand is in a non-writable segment.2
If the DS, ES, FS, or GS register contains a NULL segment selector.3
X
#GP(0)
X
X
Cause of Exception
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH
#PF(fault-code)
X
X
X
For a page fault
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made while
the current privilege level is 3.
Applicable Instructions
MASKMOVQ, MOVNTQ, “MOVQ (mmreg)”
NOTES:
1. Applies to MASKMOVQ only.
2. Applies to MASKMOVQ and MOVQ (mmreg) only.
3. Applies to MASKMOVQ only.
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ARCHITECTURE COMPATIBILITY
Invalid Opcode, #UD
64-bit
X
X
X
If CR0.EM[bit 2] = 1.
X
X
X
X
If preceded by a LOCK prefix (F0H)
X
X
X
X
If any corresponding CPUID feature flag is ‘0’
X
X
#NM
22.26
Cause of Exception
X
#MF
Applicable Instructions
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 22-9. Exception Conditions for Legacy SIMD/MMX Instructions without Memory Reference
X
X
If there is a pending X87 FPU exception
X
X
If CR0.TS[bit 3]=1
PEXTRW, PMOVMSKB
INTERRUPTS
The following differences in handling interrupts are found among the IA-32
processors.
22.26.1 Interrupt Propagation Delay
External hardware interrupts may be recognized on different instruction boundaries on the P6 family, Pentium,
Intel486, and Intel386 processors, due to the superscaler designs of the P6 family and Pentium processors. Therefore, the EIP pushed onto the stack when servicing an interrupt may be different for the P6 family, Pentium,
Intel486, and Intel386 processors.
22.26.2 NMI Interrupts
After an NMI interrupt is recognized by the P6 family, Pentium, Intel486, Intel386, and Intel 286 processors, the
NMI interrupt is masked until the first IRET instruction is executed, unlike the 8086 processor.
22.26.3 IDT Limit
The LIDT instruction can be used to set a limit on the size of the IDT. A double-fault exception (#DF) is generated
if an interrupt or exception attempts to read a vector beyond the limit. Shutdown then occurs on the 32-bit IA-32
processors if the double-fault handler vector is beyond the limit. (The 8086 processor does not have a shutdown
mode nor a limit.)
22.27
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The Advanced Programmable Interrupt Controller (APIC), referred to in this book as the local APIC, was introduced into the IA-32 processors with the Pentium processor (beginning with the 735/90 and 815/100 models) and
is included in the Pentium 4, Intel Xeon, and P6 family processors. The features and functions of the local APIC are
derived from the Intel 82489DX external APIC, which was used with the Intel486 and early Pentium processors.
Additional refinements of the local APIC architecture were incorporated in the Pentium 4 and Intel Xeon processors.
22-26 Vol. 3B
ARCHITECTURE COMPATIBILITY
22.27.1
Software Visible Differences Between the Local APIC and the 82489DX
The following features in the local APIC features differ from those found in the 82489DX external APIC:
•
When the local APIC is disabled by clearing the APIC software enable/disable flag in the spurious-interrupt
vector MSR, the state of its internal registers are unaffected, except that the mask bits in the LVT are all set to
block local interrupts to the processor. Also, the local APIC ceases accepting IPIs except for INIT, SMI, NMI, and
start-up IPIs. In the 82489DX, when the local unit is disabled, all the internal registers including the IRR, ISR
and TMR are cleared and the mask bits in the LVT are set. In this state, the 82489DX local unit will accept only
the reset deassert message.
•
In the local APIC, NMI and INIT (except for INIT deassert) are always treated as edge triggered interrupts,
even if programmed otherwise. In the 82489DX, these interrupts are always level triggered.
•
In the local APIC, IPIs generated through the ICR are always treated as edge triggered (except INIT Deassert).
In the 82489DX, the ICR can be used to generate either edge or level triggered IPIs.
•
•
•
In the local APIC, the logical destination register supports 8 bits; in the 82489DX, it supports 32 bits.
•
For the 82489DX, in the lowest priority delivery mode, all the target local APICs specified by the destination
field participate in the lowest priority arbitration. For the local APIC, only those local APICs which have free
interrupt slots will participate in the lowest priority arbitration.
In the local APIC, the APIC ID register is 4 bits wide; in the 82489DX, it is 8 bits wide.
The remote read delivery mode provided in the 82489DX and local APIC for Pentium processors is not
supported in the local APIC in the Pentium 4, Intel Xeon, and P6 family processors.
22.27.2
New Features Incorporated in the Local APIC for the P6 Family and Pentium
Processors
The local APIC in the Pentium and P6 family processors have the following new features not found in the 82489DX
external APIC.
•
•
•
•
•
Cluster addressing is supported in logical destination mode.
Focus processor checking can be enabled/disabled.
Interrupt input signal polarity can be programmed for the LINT0 and LINT1 pins.
An SMI IPI is supported through the ICR and I/O redirection table.
An error status register is incorporated into the LVT to log and report APIC errors.
In the P6 family processors, the local APIC incorporates an additional LVT register to handle performance monitoring counter interrupts.
22.27.3
New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon
Processors
The local APIC in the Pentium 4 and Intel Xeon processors has the following new features not found in the P6 family
and Pentium processors and in the 82489DX.
•
•
•
•
The local APIC ID is extended to 8 bits.
An thermal sensor register is incorporated into the LVT to handle thermal sensor interrupts.
The the ability to deliver lowest-priority interrupts to a focus processor is no longer supported.
The flat cluster logical destination mode is not supported.
22.28
TASK SWITCHING AND TSS
This section identifies the implementation differences of task switching, additions to the TSS and the handling of
TSSs and TSS segment selectors.
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ARCHITECTURE COMPATIBILITY
22.28.1 P6 Family and Pentium Processor TSS
When the virtual mode extensions are enabled (by setting the VME flag in control register CR4), the TSS in the P6
family and Pentium processors contain an interrupt redirection bit map, which is used in virtual-8086 mode to redirect interrupts back to an 8086 program.
22.28.2 TSS Selector Writes
During task state saves, the Intel486 processor writes 2-byte segment selectors into a 32-bit TSS, leaving the
upper 16 bits undefined. For performance reasons, the P6 family and Pentium processors write 4-byte segment
selectors into the TSS, with the upper 2 bytes being 0. For compatibility reasons, code should not depend on the
value of the upper 16 bits of the selector in the TSS.
22.28.3 Order of Reads/Writes to the TSS
The order of reads and writes into the TSS is processor dependent. The P6 family and Pentium processors may
generate different page-fault addresses in control register CR2 in the same TSS area than the Intel486 and
Intel386 processors, if a TSS crosses a page boundary (which is not recommended).
22.28.4 Using A 16-Bit TSS with 32-Bit Constructs
Task switches using 16-bit TSSs should be used only for pure 16-bit code. Any new code written using 32-bit
constructs (operands, addressing, or the upper word of the EFLAGS register) should use only 32-bit TSSs. This is
due to the fact that the 32-bit processors do not save the upper 16 bits of EFLAGS to a 16-bit TSS. A task switch
back to a 16-bit task that was executing in virtual mode will never re-enable the virtual mode, as this flag was not
saved in the upper half of the EFLAGS value in the TSS. Therefore, it is strongly recommended that any code using
32-bit constructs use a 32-bit TSS to ensure correct behavior in a multitasking environment.
22.28.5 Differences in I/O Map Base Addresses
The Intel486 processor considers the TSS segment to be a 16-bit segment and wraps around the 64K boundary.
Any I/O accesses check for permission to access this I/O address at the I/O base address plus the I/O offset. If the
I/O map base address exceeds the specified limit of 0DFFFH, an I/O access will wrap around and obtain the permission for the I/O address at an incorrect location within the TSS. A TSS limit violation does not occur in this situation
on the Intel486 processor. However, the P6 family and Pentium processors consider the TSS to be a 32-bit segment
and a limit violation occurs when the I/O base address plus the I/O offset is greater than the TSS limit. By following
the recommended specification for the I/O base address to be less than 0DFFFH, the Intel486 processor will not
wrap around and access incorrect locations within the TSS for I/O port validation and the P6 family and Pentium
processors will not experience general-protection exceptions (#GP). Figure 22-1 demonstrates the different areas
accessed by the Intel486 and the P6 family and Pentium processors.
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ARCHITECTURE COMPATIBILITY
Intel486 Processor
P6 family and Pentium Processors
FFFFH + 10H = Outside Segment
for I/O Validation
FFFFH
I/O Map
Base Addres
FFFFH
FFFFH
I/O Map
Base Addres
FFFFH
FFFFH + 10H = FH
for I/O Validation
0H
I/O access at port 10H checks
bitmap at I/O map base address
FFFFH + 10H = offset 10H.
Offset FH from beginning of
TSS segment results because
wraparound occurs.
0H
I/O access at port 10H checks
bitmap at I/O address FFFFH + 10H,
which exceeds segment limit.
Wrap around does not occur,
general-protection exception (#GP)
occurs.
Figure 22-1. I/O Map Base Address Differences
22.29
CACHE MANAGEMENT
The P6 family processors include two levels of internal caches: L1 (level 1) and L2 (level 2). The L1 cache is divided
into an instruction cache and a data cache; the L2 cache is a general-purpose cache. See Section 11.1, “Internal
Caches, TLBs, and Buffers,” for a description of these caches. (Note that although the Pentium II processor L2
cache is physically located on a separate chip in the cassette, it is considered an internal cache.)
The Pentium processor includes separate level 1 instruction and data caches. The data cache supports a writeback
(or alternatively write-through, on a line by line basis) policy for memory updates.
The Intel486 processor includes a single level 1 cache for both instructions and data.
The meaning of the CD and NW flags in control register CR0 have been redefined for the P6 family and Pentium
processors. For these processors, the recommended value (00B) enables writeback for the data cache of the
Pentium processor and for the L1 data cache and L2 cache of the P6 family processors. In the Intel486 processor,
setting these flags to (00B) enables write-through for the cache.
External system hardware can force the Pentium processor to disable caching or to use the write-through cache
policy should that be required. In the P6 family processors, the MTRRs can be used to override the CD and NW flags
(see Table 11-6).
The P6 family and Pentium processors support page-level cache management in the same manner as the Intel486
processor by using the PCD and PWT flags in control register CR3, the page-directory entries, and the page-table
entries. The Intel486 processor, however, is not affected by the state of the PWT flag since the internal cache of the
Intel486 processor is a write-through cache.
22.29.1 Self-Modifying Code with Cache Enabled
On the Intel486 processor, a write to an instruction in the cache will modify it in both the cache and memory. If the
instruction was prefetched before the write, however, the old version of the instruction could be the one executed.
To prevent this problem, it is necessary to flush the instruction prefetch unit of the Intel486 processor by coding a
jump instruction immediately after any write that modifies an instruction. The P6 family and Pentium processors,
however, check whether a write may modify an instruction that has been prefetched for execution. This check is
based on the linear address of the instruction. If the linear address of an instruction is found to be present in the
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ARCHITECTURE COMPATIBILITY
prefetch queue, the P6 family and Pentium processors flush the prefetch queue, eliminating the need to code a
jump instruction after any writes that modify an instruction.
Because the linear address of the write is checked against the linear address of the instructions that have been
prefetched, special care must be taken for self-modifying code to work correctly when the physical addresses of the
instruction and the written data are the same, but the linear addresses differ. In such cases, it is necessary to
execute a serializing operation to flush the prefetch queue after the write and before executing the modified
instruction. See Section 8.3, “Serializing Instructions,” for more information on serializing instructions.
NOTE
The check on linear addresses described above is not in practice a concern for compatibility. Applications that include self-modifying code use the same linear address for modifying and fetching the
instruction. System software, such as a debugger, that might possibly modify an instruction using
a different linear address than that used to fetch the instruction must execute a serializing
operation, such as IRET, before the modified instruction is executed.
22.29.2 Disabling the L3 Cache
A unified third-level (L3) cache in processors based on Intel NetBurst microarchitecture (see Section 11.1,
“Internal Caches, TLBs, and Buffers”) provides the third-level cache disable flag, bit 6 of the IA32_MISC_ENABLE
MSR. The third-level cache disable flag allows the L3 cache to be disabled and enabled, independently of the L1 and
L2 caches (see Section 11.5.4, “Disabling and Enabling the L3 Cache”). The third-level cache disable flag applies
only to processors based on Intel NetBurst microarchitecture. Processors with L3 and based on other microarchitectures do not support the third-level cache disable flag.
22.30
PAGING
This section identifies enhancements made to the paging mechanism and implementation differences in the paging
mechanism for various IA-32 processors.
22.30.1 Large Pages
The Pentium processor extended the memory management/paging facilities of the IA-32 to allow large (4 MBytes)
pages sizes (see Section 4.3, “32-Bit Paging”). The first P6 family processor (the Pentium Pro processor) added a 2
MByte page size to the IA-32 in conjunction with the physical address extension (PAE) feature (see Section 4.4,
“PAE Paging”).
The availability of large pages with 32-bit paging on any IA-32 processor can be determined via feature bit 3 (PSE)
of register EDX after the CPUID instruction has been execution with an argument of 1. (Large pages are always
available with PAE paging and IA-32e paging.) Intel processors that do not support the CPUID instruction support
only 32-bit paging and do not support page size enhancements. (See “CPUID—CPU Identification” in Chapter 3,
“Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2A for more information on the CPUID instruction.)
22.30.2 PCD and PWT Flags
The PCD and PWT flags were introduced to the IA-32 in the Intel486 processor to control the caching of pages:
•
•
PCD (page-level cache disable) flag—Controls caching on a page-by-page basis.
PWT (page-level write-through) flag—Controls the write-through/writeback caching policy on a page-by-page
basis. Since the internal cache of the Intel486 processor is a write-through cache, it is not affected by the state
of the PWT flag.
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ARCHITECTURE COMPATIBILITY
22.30.3 Enabling and Disabling Paging
Paging is enabled and disabled by loading a value into control register CR0 that modifies the PG flag. For backward
and forward compatibility with all IA-32 processors, Intel recommends that the following operations be performed
when enabling or disabling paging:
1. Execute a MOV CR0, REG instruction to either set (enable paging) or clear (disable paging) the PG flag.
2. Execute a near JMP instruction.
The sequence bounded by the MOV and JMP instructions should be identity mapped (that is, the instructions should
reside on a page whose linear and physical addresses are identical).
For the P6 family processors, the MOV CR0, REG instruction is serializing, so the jump operation is not required.
However, for backwards compatibility, the JMP instruction should still be included.
22.31
STACK OPERATIONS
This section identifies the differences in the stack mechanism for the various IA-32 processors.
22.31.1 Selector Pushes and Pops
When pushing a segment selector onto the stack, the Pentium 4, Intel Xeon, P6 family, and Intel486 processors
decrement the ESP register by the operand size and then write 2 bytes. If the operand size is 32-bits, the upper
two bytes of the write are not modified. The Pentium processor decrements the ESP register by the operand size
and determines the size of the write by the operand size. If the operand size is 32-bits, the upper two bytes are
written as 0s.
When popping a segment selector from the stack, the Pentium 4, Intel Xeon, P6 family, and Intel486 processors
read 2 bytes and increment the ESP register by the operand size of the instruction. The Pentium processor determines the size of the read from the operand size and increments the ESP register by the operand size.
It is possible to align a 32-bit selector push or pop such that the operation generates an exception on a Pentium
processor and not on an Pentium 4, Intel Xeon, P6 family, or Intel486 processor. This could occur if the third and/or
fourth byte of the operation lies beyond the limit of the segment or if the third and/or fourth byte of the operation
is locate on a non-present or inaccessible page.
For a POP-to-memory instruction that meets the following conditions:
•
•
•
The stack segment size is 16-bit.
Any 32-bit addressing form with the SIB byte specifying ESP as the base register.
The initial stack pointer is FFFCH (32-bit operand) or FFFEH (16-bit operand) and will wrap around to 0H as a
result of the POP operation.
The result of the memory write is implementation-specific. For example, in P6 family processors, the result of the
memory write is SS:0H plus any scaled index and displacement. In Pentium processors, the result of the memory
write may be either a stack fault (real mode or protected mode with stack segment size of 64 KByte), or write to
SS:10000H plus any scaled index and displacement (protected mode and stack segment size exceeds 64 KByte).
22.31.2 Error Code Pushes
The Intel486 processor implements the error code pushed on the stack as a 16-bit value. When pushed onto a 32bit stack, the Intel486 processor only pushes 2 bytes and updates ESP by 4. The P6 family and Pentium processors’
error code is a full 32 bits with the upper 16 bits set to zero. The P6 family and Pentium processors, therefore, push
4 bytes and update ESP by 4. Any code that relies on the state of the upper 16 bits may produce inconsistent
results.
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ARCHITECTURE COMPATIBILITY
22.31.3 Fault Handling Effects on the Stack
During the handling of certain instructions, such as CALL and PUSHA, faults may occur in different sequences for
the different processors. For example, during far calls, the Intel486 processor pushes the old CS and EIP before a
possible branch fault is resolved. A branch fault is a fault from a branch instruction occurring from a segment limit
or access rights violation. If a branch fault is taken, the Intel486 and P6 family processors will have corrupted
memory below the stack pointer. However, the ESP register is backed up to make the instruction restartable. The
P6 family processors issue the branch before the pushes. Therefore, if a branch fault does occur, these processors
do not corrupt memory below the stack pointer. This implementation difference, however, does not constitute a
compatibility problem, as only values at or above the stack pointer are considered to be valid. Other operations that
encounter faults may also corrupt memory below the stack pointer and this behavior may vary on different implementations.
22.31.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
If a call or interrupt is made from a 32-bit stack environment through a 16-bit gate, only 16 bits of the old ESP can
be pushed onto the stack. On the subsequent RET/IRET, the 16-bit ESP is popped but the full 32-bit ESP is updated
since control is being resumed in a 32-bit stack environment. The Intel486 processor writes the SS selector into the
upper 16 bits of ESP. The P6 family and Pentium processors write zeros into the upper 16 bits.
22.32
MIXING 16- AND 32-BIT SEGMENTS
The features of the 16-bit Intel 286 processor are an object-code compatible subset of those of the 32-bit IA-32
processors. The D (default operation size) flag in segment descriptors indicates whether the processor treats a
code or data segment as a 16-bit or 32-bit segment; the B (default stack size) flag in segment descriptors indicates
whether the processor treats a stack segment as a 16-bit or 32-bit segment.
The segment descriptors used by the Intel 286 processor are supported by the 32-bit IA-32 processors if the Intelreserved word (highest word) of the descriptor is clear. On the 32-bit IA-32 processors, this word includes the
upper bits of the base address and the segment limit.
The segment descriptors for data segments, code segments, local descriptor tables (there are no descriptors for
global descriptor tables), and task gates are the same for the 16- and 32-bit processors. Other 16-bit descriptors
(TSS segment, call gate, interrupt gate, and trap gate) are supported by the 32-bit processors.
The 32-bit processors also have descriptors for TSS segments, call gates, interrupt gates, and trap gates that
support the 32-bit architecture. Both kinds of descriptors can be used in the same system.
For those segment descriptors common to both 16- and 32-bit processors, clear bits in the reserved word cause the
32-bit processors to interpret these descriptors exactly as an Intel 286 processor does, that is:
•
•
•
Base Address — The upper 8 bits of the 32-bit base address are clear, which limits base addresses to 24 bits.
Limit — The upper 4 bits of the limit field are clear, restricting the value of the limit field to 64 KBytes.
Granularity bit — The G (granularity) flag is clear, indicating the value of the 16-bit limit is interpreted in units
of 1 byte.
•
Big bit — In a data-segment descriptor, the B flag is clear in the segment descriptor used by the 32-bit
processors, indicating the segment is no larger than 64 KBytes.
•
Default bit — In a code-segment descriptor, the D flag is clear, indicating 16-bit addressing and operands are
the default. In a stack-segment descriptor, the D flag is clear, indicating use of the SP register (instead of the
ESP register) and a 64-KByte maximum segment limit.
For information on mixing 16- and 32-bit code in applications, see Chapter 21, “Mixing 16-Bit and 32-Bit Code.”
22.33
SEGMENT AND ADDRESS WRAPAROUND
This section discusses differences in segment and address wraparound between the P6 family, Pentium, Intel486,
Intel386, Intel 286, and 8086 processors.
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ARCHITECTURE COMPATIBILITY
22.33.1 Segment Wraparound
On the 8086 processor, an attempt to access a memory operand that crosses offset 65,535 or 0FFFFH or offset 0
(for example, moving a word to offset 65,535 or pushing a word when the stack pointer is set to 1) causes the
offset to wrap around modulo 65,536 or 010000H. With the Intel 286 processor, any base and offset combination
that addresses beyond 16 MBytes wraps around to the 1 MByte of the address space. The P6 family, Pentium,
Intel486, and Intel386 processors in real-address mode generate an exception in these cases:
•
A general-protection exception (#GP) if the segment is a data segment (that is, if the CS, DS, ES, FS, or GS
register is being used to address the segment).
•
A stack-fault exception (#SS) if the segment is a stack segment (that is, if the SS register is being used).
An exception to this behavior occurs when a stack access is data aligned, and the stack pointer is pointing to the
last aligned piece of data that size at the top of the stack (ESP is FFFFFFFCH). When this data is popped, no
segment limit violation occurs and the stack pointer will wrap around to 0.
The address space of the P6 family, Pentium, and Intel486 processors may wraparound at 1 MByte in real-address
mode. An external A20M# pin forces wraparound if enabled. On Intel 8086 processors, it is possible to specify
addresses greater than 1 MByte. For example, with a selector value FFFFH and an offset of FFFFH, the effective
address would be 10FFEFH (1 MByte plus 65519 bytes). The 8086 processor, which can form addresses up to 20
bits long, truncates the uppermost bit, which “wraps” this address to FFEFH. However, the P6 family, Pentium, and
Intel486 processors do not truncate this bit if A20M# is not enabled.
If a stack operation wraps around the address limit, shutdown occurs. (The 8086 processor does not have a shutdown mode or a limit.)
The behavior when executing near the limit of a 4-GByte selector (limit = FFFFFFFFH) is different between the
Pentium Pro and the Pentium 4 family of processors. On the Pentium Pro, instructions which cross the limit -- for
example, a two byte instruction such as INC EAX that is encoded as FFH C0H starting exactly at the limit faults for
a segment violation (a one byte instruction at FFFFFFFFH does not cause an exception). Using the Pentium 4 microprocessor family, neither of these situations causes a fault.
Segment wraparound and the functionality of A20M# is used primarily by older operating systems and not used by
modern operating systems. On newer Intel 64 processors, A20M# may be absent.
22.34
STORE BUFFERS AND MEMORY ORDERING
The Pentium 4, Intel Xeon, and P6 family processors provide a store buffer for temporary storage of writes (stores)
to memory (see Section 11.10, “Store Buffer”). Writes stored in the store buffer(s) are always written to memory
in program order, with the exception of “fast string” store operations (see Section 8.2.4, “Fast-String Operation and
Out-of-Order Stores”).
The Pentium processor has two store buffers, one corresponding to each of the pipelines. Writes in these buffers
are always written to memory in the order they were generated by the processor core.
It should be noted that only memory writes are buffered and I/O writes are not. The Pentium 4, Intel Xeon, P6
family, Pentium, and Intel486 processors do not synchronize the completion of memory writes on the bus and
instruction execution after a write. An I/O, locked, or serializing instruction needs to be executed to synchronize
writes with the next instruction (see Section 8.3, “Serializing Instructions”).
The Pentium 4, Intel Xeon, and P6 family processors use processor ordering to maintain consistency in the order
that data is read (loaded) and written (stored) in a program and the order the processor actually carries out the
reads and writes. With this type of ordering, reads can be carried out speculatively and in any order, reads can pass
buffered writes, and writes to memory are always carried out in program order. (See Section 8.2, “Memory
Ordering,” for more information about processor ordering.) The Pentium III processor introduced a new instruction
to serialize writes and make them globally visible. Memory ordering issues can arise between a producer and a
consumer of data. The SFENCE instruction provides a performance-efficient way of ensuring ordering between
routines that produce weakly-ordered results and routines that consume this data.
No re-ordering of reads occurs on the Pentium processor, except under the condition noted in Section 8.2.1,
“Memory Ordering in the Intel® Pentium® and Intel486™ Processors,” and in the following paragraph describing
the Intel486 processor.
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ARCHITECTURE COMPATIBILITY
Specifically, the store buffers are flushed before the IN instruction is executed. No reads (as a result of cache miss)
are reordered around previously generated writes sitting in the store buffers. The implication of this is that the
store buffers will be flushed or emptied before a subsequent bus cycle is run on the external bus.
On both the Intel486 and Pentium processors, under certain conditions, a memory read will go onto the external
bus before the pending memory writes in the buffer even though the writes occurred earlier in the program execution. A memory read will only be reordered in front of all writes pending in the buffers if all writes pending in the
buffers are cache hits and the read is a cache miss. Under these conditions, the Intel486 and Pentium processors
will not read from an external memory location that needs to be updated by one of the pending writes.
During a locked bus cycle, the Intel486 processor will always access external memory, it will never look for the
location in the on-chip cache. All data pending in the Intel486 processor's store buffers will be written to memory
before a locked cycle is allowed to proceed to the external bus. Thus, the locked bus cycle can be used for eliminating the possibility of reordering read cycles on the Intel486 processor. The Pentium processor does check its
cache on a read-modify-write access and, if the cache line has been modified, writes the contents back to memory
before locking the bus. The P6 family processors write to their cache on a read-modify-write operation (if the
access does not split across a cache line) and does not write back to system memory. If the access does split across
a cache line, it locks the bus and accesses system memory.
I/O reads are never reordered in front of buffered memory writes on an IA-32 processor. This ensures an update of
all memory locations before reading the status from an I/O device.
22.35
BUS LOCKING
The Intel 286 processor performs the bus locking differently than the Intel P6 family, Pentium, Intel486, and
Intel386 processors. Programs that use forms of memory locking specific to the Intel 286 processor may not run
properly when run on later processors.
A locked instruction is guaranteed to lock only the area of memory defined by the destination operand, but may
lock a larger memory area. For example, typical 8086 and Intel 286 configurations lock the entire physical memory
space. Programmers should not depend on this.
On the Intel 286 processor, the LOCK prefix is sensitive to IOPL. If the CPL is greater than the IOPL, a generalprotection exception (#GP) is generated. On the Intel386 DX, Intel486, and Pentium, and P6 family processors, no
check against IOPL is performed.
The Pentium processor automatically asserts the LOCK# signal when acknowledging external interrupts. After
signaling an interrupt request, an external interrupt controller may use the data bus to send the interrupt vector to
the processor. After receiving the interrupt request signal, the processor asserts LOCK# to insure that no other
data appears on the data bus until the interrupt vector is received. This bus locking does not occur on the P6 family
processors.
22.36
BUS HOLD
Unlike the 8086 and Intel 286 processors, but like the Intel386 and Intel486 processors, the P6 family and Pentium
processors respond to requests for control of the bus from other potential bus masters, such as DMA controllers,
between transfers of parts of an unaligned operand, such as two words which form a doubleword. Unlike the
Intel386 processor, the P6 family, Pentium and Intel486 processors respond to bus hold during reset initialization.
22.37
MODEL-SPECIFIC EXTENSIONS TO THE IA-32
Certain extensions to the IA-32 are specific to a processor or family of IA-32 processors and may not be implemented or implemented in the same way in future processors. The following sections describe these model-specific
extensions. The CPUID instruction indicates the availability of some of the model-specific features.
22-34 Vol. 3B
ARCHITECTURE COMPATIBILITY
22.37.1
Model-Specific Registers
The Pentium processor introduced a set of model-specific registers (MSRs) for use in controlling hardware functions and performance monitoring. To access these MSRs, two new instructions were added to the IA-32 architecture: read MSR (RDMSR) and write MSR (WRMSR). The MSRs in the Pentium processor are not guaranteed to be
duplicated or provided in the next generation IA-32 processors.
The P6 family processors greatly increased the number of MSRs available to software. See Chapter 35, “ModelSpecific Registers (MSRs),” for a complete list of the available MSRs. The new registers control the debug extensions, the performance counters, the machine-check exception capability, the machine-check architecture, and the
MTRRs. These registers are accessible using the RDMSR and WRMSR instructions. Specific information on some of
these new MSRs is provided in the following sections. As with the Pentium processor MSR, the P6 family processor
MSRs are not guaranteed to be duplicated or provided in the next generation IA-32 processors.
22.37.2
RDMSR and WRMSR Instructions
The RDMSR (read model-specific register) and WRMSR (write model-specific register) instructions recognize a
much larger number of model-specific registers in the P6 family processors. (See “RDMSR—Read from Model
Specific Register” and “WRMSR—Write to Model Specific Register” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D for more information.)
22.37.3
Memory Type Range Registers
Memory type range registers (MTRRs) are a new feature introduced into the IA-32 in the Pentium Pro processor.
MTRRs allow the processor to optimize memory operations for different types of memory, such as RAM, ROM,
frame buffer memory, and memory-mapped I/O.
MTRRs are MSRs that contain an internal map of how physical address ranges are mapped to various types of
memory. The processor uses this internal memory map to determine the cacheability of various physical memory
locations and the optimal method of accessing memory locations. For example, if a memory location is specified in
an MTRR as write-through memory, the processor handles accesses to this location as follows. It reads data from
that location in lines and caches the read data or maps all writes to that location to the bus and updates the cache
to maintain cache coherency. In mapping the physical address space with MTRRs, the processor recognizes five
types of memory: uncacheable (UC), uncacheable, speculatable, write-combining (WC), write-through (WT),
write-protected (WP), and writeback (WB).
Earlier IA-32 processors (such as the Intel486 and Pentium processors) used the KEN# (cache enable) pin and
external logic to maintain an external memory map and signal cacheable accesses to the processor. The MTRR
mechanism simplifies hardware designs by eliminating the KEN# pin and the external logic required to drive it.
See Chapter 9, “Processor Management and Initialization,” and Chapter 35, “Model-Specific Registers (MSRs),” for
more information on the MTRRs.
22.37.4
Machine-Check Exception and Architecture
The Pentium processor introduced a new exception called the machine-check exception (#MC, interrupt 18). This
exception is used to detect hardware-related errors, such as a parity error on a read cycle.
The P6 family processors extend the types of errors that can be detected and that generate a machine-check
exception. It also provides a new machine-check architecture for recording information about a machine-check
error and provides extended recovery capability.
The machine-check architecture provides several banks of reporting registers for recording machine-check errors.
Each bank of registers is associated with a specific hardware unit in the processor. The primary focus of the
machine checks is on bus and interconnect operations; however, checks are also made of translation lookaside
buffer (TLB) and cache operations.
The machine-check architecture can correct some errors automatically and allow for reliable restart of instruction
execution. It also collects sufficient information for software to use in correcting other machine errors not corrected
by hardware.
Vol. 3B 22-35
ARCHITECTURE COMPATIBILITY
See Chapter 15, “Machine-Check Architecture,” for more information on the machine-check exception and the
machine-check architecture.
22.37.5
Performance-Monitoring Counters
The P6 family and Pentium processors provide two performance-monitoring counters for use in monitoring internal
hardware operations. The number of performance monitoring counters and associated programming interfaces
may be implementation specific for Pentium 4 processors, Pentium M processors. Later processors may have
implemented these as part of an architectural performance monitoring feature. The architectural and non-architectural performance monitoring interfaces for different processor families are described in Chapter 18, “Performance
Monitoring,”. Chapter 19, “Performance Monitoring Events.” lists all the events that can be counted for architectural
performance monitoring events and non-architectural events. The counters are set up, started, and stopped using
two MSRs and the RDMSR and WRMSR instructions. For the P6 family processors, the current count for a particular
counter can be read using the new RDPMC instruction.
The performance-monitoring counters are useful for debugging programs, optimizing code, diagnosing system failures, or refining hardware designs. See Chapter 18, “Performance Monitoring,” for more information on these
counters.
22.38
TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS
When porting 16-bit programs to run on 32-bit IA-32 processors, there are two approaches to consider:
•
Porting an entire 16-bit software system to a 32-bit processor, complete with the old operating system, loader,
and system builder. Here, all tasks will have 16-bit TSSs. The 32-bit processor is being used as if it were a faster
version of the 16-bit processor.
•
Porting selected 16-bit applications to run in a 32-bit processor environment with a 32-bit operating system,
loader, and system builder. Here, the TSSs used to represent 286 tasks should be changed to 32-bit TSSs. It is
possible to mix 16 and 32-bit TSSs, but the benefits are small and the problems are great. All tasks in a 32-bit
software system should have 32-bit TSSs. It is not necessary to change the 16-bit object modules themselves;
TSSs are usually constructed by the operating system, by the loader, or by the system builder. See Chapter 21,
“Mixing 16-Bit and 32-Bit Code,” for more detailed information about mixing 16-bit and 32-bit code.
Because the 32-bit processors use the contents of the reserved word of 16-bit segment descriptors, 16-bit
programs that place values in this word may not run correctly on the 32-bit processors.
22.39
INITIAL STATE OF PENTIUM, PENTIUM PRO AND PENTIUM 4 PROCESSORS
Table 22-10 shows the state of the flags and other registers following power-up for the Pentium, Pentium Pro and
Pentium 4 processors. The state of control register CR0 is 60000010H (see Figure 9-1 “Contents of CR0 Register
after Reset” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). This places the
processor in real-address mode with paging disabled.
Table 22-10. Processor State Following Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors
Register
Pentium 4 Processor
Pentium Pro Processor
Pentium Processor
EFLAGS1
00000002H
00000002H
00000002H
EIP
0000FFF0H
0000FFF0H
0000FFF0H
CR0
60000010H2
60000010H2
60000010H2
CR2, CR3, CR4
00000000H
00000000H
00000000H
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ARCHITECTURE COMPATIBILITY
Table 22-10. Processor State Following Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors
Register
Pentium 4 Processor
Pentium Pro Processor
CS
Selector = F000H
Base = FFFF0000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = F000H
Base = FFFF0000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = F000H
Base = FFFF0000H
Limit = FFFFH
AR = Present, R/W, Accessed
SS, DS, ES, FS, GS
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W, Accessed
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W, Accessed
EDX
00000FxxH
000n06xxH3
000005xxH
4
4
Pentium Processor
04
EAX
0
0
EBX, ECX, ESI, EDI, EBP,
ESP
00000000H
00000000H
00000000H
ST0 through ST75
Pwr up or Reset: +0.0
FINIT/FNINIT: Unchanged
Pwr up or Reset: +0.0
FINIT/FNINIT: Unchanged
Pwr up or Reset: +0.0
FINIT/FNINIT: Unchanged
x87 FPU Control
Word5
Pwr up or Reset: 0040H
FINIT/FNINIT: 037FH
Pwr up or Reset: 0040H
FINIT/FNINIT: 037FH
Pwr up or Reset: 0040H
FINIT/FNINIT: 037FH
x87 FPU Status Word5 Pwr up or Reset: 0000H
FINIT/FNINIT: 0000H
Pwr up or Reset: 0000H
FINIT/FNINIT: 0000H
Pwr up or Reset: 0000H
FINIT/FNINIT: 0000H
x87 FPU Tag Word5
Pwr up or Reset: 5555H
FINIT/FNINIT: FFFFH
Pwr up or Reset: 5555H
FINIT/FNINIT: FFFFH
Pwr up or Reset: 5555H
FINIT/FNINIT: FFFFH
x87 FPU Data
Operand and CS Seg.
Selectors5
Pwr up or Reset: 0000H
FINIT/FNINIT: 0000H
Pwr up or Reset: 0000H
FINIT/FNINIT: 0000H
Pwr up or Reset: 0000H
FINIT/FNINIT: 0000H
x87 FPU Data
Operand and Inst.
Pointers5
Pwr up or Reset:
00000000H
FINIT/FNINIT: 00000000H
Pwr up or Reset:
00000000H
FINIT/FNINIT: 00000000H
Pwr up or Reset:
00000000H
FINIT/FNINIT: 00000000H
MM0 through MM75
Pwr up or Reset:
0000000000000000H
INIT or FINIT/FNINIT:
Unchanged
Pentium II and Pentium III
Processors Only—
Pentium with MMX Technology
Only—
Pwr up or Reset:
0000000000000000H
INIT or FINIT/FNINIT:
Unchanged
Pwr up or Reset:
0000000000000000H
INIT or FINIT/FNINIT:
Unchanged
Pwr up or Reset: 0H
INIT: Unchanged
If CPUID.01H:SSE is 1 —
NA
Pwr up or Reset: 1F80H
INIT: Unchanged
Pentium III processor only-
GDTR, IDTR
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
LDTR, Task Register
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W
DR0, DR1, DR2, DR3
00000000H
00000000H
00000000H
DR6
FFFF0FF0H
FFFF0FF0H
FFFF0FF0H
XMM0 through XMM7
MXCSR
Pwr up or Reset: 0H
INIT: Unchanged
NA
Pwr up or Reset: 1F80H
INIT: Unchanged
Vol. 3B 22-37
ARCHITECTURE COMPATIBILITY
Table 22-10. Processor State Following Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors
Register
Pentium 4 Processor
Pentium Pro Processor
Pentium Processor
DR7
00000400H
00000400H
00000400H
Time-Stamp Counter
Power up or Reset: 0H
INIT: Unchanged
Power up or Reset: 0H
INIT: Unchanged
Power up or Reset: 0H
INIT: Unchanged
Perf. Counters and
Event Select
Power up or Reset: 0H
INIT: Unchanged
Power up or Reset: 0H
INIT: Unchanged
Power up or Reset: 0H
INIT: Unchanged
All Other MSRs
Pwr up or Reset:
Undefined
INIT: Unchanged
Pwr up or Reset:
Undefined
INIT: Unchanged
Pwr up or Reset:
Undefined
INIT: Unchanged
Data and Code Cache,
TLBs
Invalid6
Invalid6
Invalid6
Fixed MTRRs
Pwr up or Reset: Disabled
INIT: Unchanged
Pwr up or Reset: Disabled
INIT: Unchanged
Not Implemented
Variable MTRRs
Pwr up or Reset: Disabled
INIT: Unchanged
Pwr up or Reset: Disabled
INIT: Unchanged
Not Implemented
Machine-Check
Architecture
Pwr up or Reset:
Undefined
INIT: Unchanged
Pwr up or Reset:
Undefined
INIT: Unchanged
Not Implemented
APIC
Pwr up or Reset: Enabled
INIT: Unchanged
Pwr up or Reset: Enabled
INIT: Unchanged
Pwr up or Reset: Enabled
INIT: Unchanged
R8-R157
0000000000000000H
0000000000000000H
N.A.
XMM8-XMM157
Pwr up or Reset: 0H
INIT: Unchanged
Pwr up or Reset: 0H
INIT: Unchanged
N.A.
NOTES:
1. The 10 most-significant bits of the EFLAGS register are undefined following a reset. Software should not depend on the states of
any of these bits.
2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits are cleared.
3. Where “n” is the Extended Model Value for the respective processor.
4. If Built-In Self-Test (BIST) is invoked on power up or reset, EAX is 0 only if all tests passed. (BIST cannot be invoked during an INIT.)
5. The state of the x87 FPU and MMX registers is not changed by the execution of an INIT.
6. Internal caches are invalid after power-up and RESET, but left unchanged with an INIT.
7. If the processor supports IA-32e mode.
22-38 Vol. 3B
CHAPTER 23
INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
23.1
OVERVIEW
This chapter describes the basics of virtual machine architecture and an overview of the virtual-machine extensions
(VMX) that support virtualization of processor hardware for multiple software environments.
Information about VMX instructions is provided in Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B. Other aspects of VMX and system programming considerations are described in chapters of Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3B.
23.2
VIRTUAL MACHINE ARCHITECTURE
Virtual-machine extensions define processor-level support for virtual machines on IA-32 processors. Two principal
classes of software are supported:
•
Virtual-machine monitors (VMM) — A VMM acts as a host and has full control of the processor(s) and other
platform hardware. A VMM presents guest software (see next paragraph) with an abstraction of a virtual
processor and allows it to execute directly on a logical processor. A VMM is able to retain selective control of
processor resources, physical memory, interrupt management, and I/O.
•
Guest software — Each virtual machine (VM) is a guest software environment that supports a stack consisting
of operating system (OS) and application software. Each operates independently of other virtual machines and
uses on the same interface to processor(s), memory, storage, graphics, and I/O provided by a physical
platform. The software stack acts as if it were running on a platform with no VMM. Software executing in a
virtual machine must operate with reduced privilege so that the VMM can retain control of platform resources.
23.3
INTRODUCTION TO VMX OPERATION
Processor support for virtualization is provided by a form of processor operation called VMX operation. There are
two kinds of VMX operation: VMX root operation and VMX non-root operation. In general, a VMM will run in VMX
root operation and guest software will run in VMX non-root operation. Transitions between VMX root operation and
VMX non-root operation are called VMX transitions. There are two kinds of VMX transitions. Transitions into VMX
non-root operation are called VM entries. Transitions from VMX non-root operation to VMX root operation are called
VM exits.
Processor behavior in VMX root operation is very much as it is outside VMX operation. The principal differences are
that a set of new instructions (the VMX instructions) is available and that the values that can be loaded into certain
control registers are limited (see Section 23.8).
Processor behavior in VMX non-root operation is restricted and modified to facilitate virtualization. Instead of their
ordinary operation, certain instructions (including the new VMCALL instruction) and events cause VM exits to the
VMM. Because these VM exits replace ordinary behavior, the functionality of software in VMX non-root operation is
limited. It is this limitation that allows the VMM to retain control of processor resources.
There is no software-visible bit whose setting indicates whether a logical processor is in VMX non-root operation.
This fact may allow a VMM to prevent guest software from determining that it is running in a virtual machine.
Because VMX operation places restrictions even on software running with current privilege level (CPL) 0, guest
software can run at the privilege level for which it was originally designed. This capability may simplify the development of a VMM.
Vol. 3C 23-1
INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
23.4
LIFE CYCLE OF VMM SOFTWARE
Figure 23-1 illustrates the life cycle of a VMM and its guest software as well as the interactions between them. The
following items summarize that life cycle:
•
•
Software enters VMX operation by executing a VMXON instruction.
•
VM exits transfer control to an entry point specified by the VMM. The VMM can take action appropriate to the
cause of the VM exit and can then return to the virtual machine using a VM entry.
•
Eventually, the VMM may decide to shut itself down and leave VMX operation. It does so by executing the
VMXOFF instruction.
Using VM entries, a VMM can then enter guests into virtual machines (one at a time). The VMM effects a
VM entry using instructions VMLAUNCH and VMRESUME; it regains control using VM exits.
Guest 0
VM Exit
VMXON
Guest 1
VM Entry
VM Monitor
VM Exit
VMXOFF
Figure 23-1. Interaction of a Virtual-Machine Monitor and Guests
23.5
VIRTUAL-MACHINE CONTROL STRUCTURE
VMX non-root operation and VMX transitions are controlled by a data structure called a virtual-machine control
structure (VMCS).
Access to the VMCS is managed through a component of processor state called the VMCS pointer (one per logical
processor). The value of the VMCS pointer is the 64-bit address of the VMCS. The VMCS pointer is read and written
using the instructions VMPTRST and VMPTRLD. The VMM configures a VMCS using the VMREAD, VMWRITE, and
VMCLEAR instructions.
A VMM could use a different VMCS for each virtual machine that it supports. For a virtual machine with multiple
logical processors (virtual processors), the VMM could use a different VMCS for each virtual processor.
23.6
DISCOVERING SUPPORT FOR VMX
Before system software enters into VMX operation, it must discover the presence of VMX support in the processor.
System software can determine whether a processor supports VMX operation using CPUID. If
CPUID.1:ECX.VMX[bit 5] = 1, then VMX operation is supported. See Chapter 3, “Instruction Set Reference, A-L” of
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
The VMX architecture is designed to be extensible so that future processors in VMX operation can support additional features not present in first-generation implementations of the VMX architecture. The availability of extensible VMX features is reported to software using a set of VMX capability MSRs (see Appendix A, “VMX Capability
Reporting Facility”).
23-2 Vol. 3C
INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
23.7
ENABLING AND ENTERING VMX OPERATION
Before system software can enter VMX operation, it enables VMX by setting CR4.VMXE[bit 13] = 1. VMX operation
is then entered by executing the VMXON instruction. VMXON causes an invalid-opcode exception (#UD) if executed
with CR4.VMXE = 0. Once in VMX operation, it is not possible to clear CR4.VMXE (see Section 23.8). System software leaves VMX operation by executing the VMXOFF instruction. CR4.VMXE can be cleared outside of VMX operation after executing of VMXOFF.
VMXON is also controlled by the IA32_FEATURE_CONTROL MSR (MSR address 3AH). This MSR is cleared to zero
when a logical processor is reset. The relevant bits of the MSR are:
•
Bit 0 is the lock bit. If this bit is clear, VMXON causes a general-protection exception. If the lock bit is set,
WRMSR to this MSR causes a general-protection exception; the MSR cannot be modified until a power-up reset
condition. System BIOS can use this bit to provide a setup option for BIOS to disable support for VMX. To
enable VMX support in a platform, BIOS must set bit 1, bit 2, or both (see below), as well as the lock bit.
•
Bit 1 enables VMXON in SMX operation. If this bit is clear, execution of VMXON in SMX operation causes a
general-protection exception. Attempts to set this bit on logical processors that do not support both VMX
operation (see Section 23.6) and SMX operation (see Chapter 6, “Safer Mode Extensions Reference,” in Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 2D) cause general-protection exceptions.
•
Bit 2 enables VMXON outside SMX operation. If this bit is clear, execution of VMXON outside SMX
operation causes a general-protection exception. Attempts to set this bit on logical processors that do not
support VMX operation (see Section 23.6) cause general-protection exceptions.
NOTE
A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last
execution of GETSEC[SENTER]. A logical processor is outside SMX operation if GETSEC[SENTER]
has not been executed or if GETSEC[SEXIT] was executed after the last execution of
GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2D.
Before executing VMXON, software should allocate a naturally aligned 4-KByte region of memory that a logical
processor may use to support VMX operation.1 This region is called the VMXON region. The address of the VMXON
region (the VMXON pointer) is provided in an operand to VMXON. Section 24.11.5, “VMXON Region,” details how
software should initialize and access the VMXON region.
23.8
RESTRICTIONS ON VMX OPERATION
VMX operation places restrictions on processor operation. These are detailed below:
•
In VMX operation, processors may fix certain bits in CR0 and CR4 to specific values and not support other
values. VMXON fails if any of these bits contains an unsupported value (see “VMXON—Enter VMX Operation” in
Chapter 30). Any attempt to set one of these bits to an unsupported value while in VMX operation (including
VMX root operation) using any of the CLTS, LMSW, or MOV CR instructions causes a general-protection
exception. VM entry or VM exit cannot set any of these bits to an unsupported value. Software should consult
the VMX capability MSRs IA32_VMX_CR0_FIXED0 and IA32_VMX_CR0_FIXED1 to determine how bits in CR0
are fixed (see Appendix A.7). For CR4, software should consult the VMX capability MSRs
IA32_VMX_CR4_FIXED0 and IA32_VMX_CR4_FIXED1 (see Appendix A.8).
NOTES
The first processors to support VMX operation require that the following bits be 1 in VMX operation:
CR0.PE, CR0.NE, CR0.PG, and CR4.VMXE. The restrictions on CR0.PE and CR0.PG imply that VMX
operation is supported only in paged protected mode (including IA-32e mode). Therefore, guest
software cannot be run in unpaged protected mode or in real-address mode. See Section 31.2,
1. Future processors may require that a different amount of memory be reserved. If so, this fact is reported to software using the
VMX capability-reporting mechanism.
Vol. 3C 23-3
INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
“Supporting Processor Operating Modes in Guest Environments,” for a discussion of how a VMM
might support guest software that expects to run in unpaged protected mode or in real-address
mode.
Later processors support a VM-execution control called “unrestricted guest” (see Section 24.6.2).
If this control is 1, CR0.PE and CR0.PG may be 0 in VMX non-root operation (even if the capability
MSR IA32_VMX_CR0_FIXED0 reports otherwise).1 Such processors allow guest software to run in
unpaged protected mode or in real-address mode.
•
VMXON fails if a logical processor is in A20M mode (see “VMXON—Enter VMX Operation” in Chapter 30). Once
the processor is in VMX operation, A20M interrupts are blocked. Thus, it is impossible to be in A20M mode in
VMX operation.
•
The INIT signal is blocked whenever a logical processor is in VMX root operation. It is not blocked in VMX nonroot operation. Instead, INITs cause VM exits (see Section 25.2, “Other Causes of VM Exits”).
•
Intel® Processor Trace (Intel PT) can be used in VMX operation only if IA32_VMX_MISC[14] is read as 1 (see
Appendix A.6). On processors that support Intel PT but which do not allow it to be used in VMX operation,
execution of VMXON clears IA32_RTIT_CTL.TraceEn (see “VMXON—Enter VMX Operation” in Chapter 30); any
attempt to set that bit while in VMX operation (including VMX root operation) using the WRMSR instruction
causes a general-protection exception.
1. “Unrestricted guest” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VMX non-root operation functions as if the “unrestricted guest” VM-execution control were 0. See Section 24.6.2.
23-4 Vol. 3C
CHAPTER 24
VIRTUAL MACHINE CONTROL STRUCTURES
24.1
OVERVIEW
A logical processor uses virtual-machine control data structures (VMCSs) while it is in VMX operation. These
manage transitions into and out of VMX non-root operation (VM entries and VM exits) as well as processor behavior
in VMX non-root operation. This structure is manipulated by the new instructions VMCLEAR, VMPTRLD, VMREAD,
and VMWRITE.
A VMM can use a different VMCS for each virtual machine that it supports. For a virtual machine with multiple
logical processors (virtual processors), the VMM can use a different VMCS for each virtual processor.
A logical processor associates a region in memory with each VMCS. This region is called the VMCS region.1 Software references a specific VMCS using the 64-bit physical address of the region (a VMCS pointer). VMCS pointers
must be aligned on a 4-KByte boundary (bits 11:0 must be zero). These pointers must not set bits beyond the
processor’s physical-address width.2,3
A logical processor may maintain a number of VMCSs that are active. The processor may optimize VMX operation
by maintaining the state of an active VMCS in memory, on the processor, or both. At any given time, at most one
of the active VMCSs is the current VMCS. (This document frequently uses the term “the VMCS” to refer to the
current VMCS.) The VMLAUNCH, VMREAD, VMRESUME, and VMWRITE instructions operate only on the current
VMCS.
The following items describe how a logical processor determines which VMCSs are active and which is current:
•
The memory operand of the VMPTRLD instruction is the address of a VMCS. After execution of the instruction,
that VMCS is both active and current on the logical processor. Any other VMCS that had been active remains so,
but no other VMCS is current.
•
The VMCS link pointer field in the current VMCS (see Section 24.4.2) is itself the address of a VMCS. If VM entry
is performed successfully with the 1-setting of the “VMCS shadowing” VM-execution control, the VMCS
referenced by the VMCS link pointer field becomes active on the logical processor. The identity of the current
VMCS does not change.
•
The memory operand of the VMCLEAR instruction is also the address of a VMCS. After execution of the
instruction, that VMCS is neither active nor current on the logical processor. If the VMCS had been current on
the logical processor, the logical processor no longer has a current VMCS.
The VMPTRST instruction stores the address of the logical processor’s current VMCS into a specified memory location (it stores the value FFFFFFFF_FFFFFFFFH if there is no current VMCS).
The launch state of a VMCS determines which VM-entry instruction should be used with that VMCS: the
VMLAUNCH instruction requires a VMCS whose launch state is “clear”; the VMRESUME instruction requires a VMCS
whose launch state is “launched”. A logical processor maintains a VMCS’s launch state in the corresponding VMCS
region. The following items describe how a logical processor manages the launch state of a VMCS:
•
If the launch state of the current VMCS is “clear”, successful execution of the VMLAUNCH instruction changes
the launch state to “launched”.
•
The memory operand of the VMCLEAR instruction is the address of a VMCS. After execution of the instruction,
the launch state of that VMCS is “clear”.
•
There are no other ways to modify the launch state of a VMCS (it cannot be modified using VMWRITE) and there
is no direct way to discover it (it cannot be read using VMREAD).
1. The amount of memory required for a VMCS region is at most 4 KBytes. The exact size is implementation specific and can be determined by consulting the VMX capability MSR IA32_VMX_BASIC to determine the size of the VMCS region (see Appendix A.1).
2. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
3. If IA32_VMX_BASIC[48] is read as 1, these pointers must not set any bits in the range 63:32; see Appendix A.1.
Vol. 3C 24-1
VIRTUAL MACHINE CONTROL STRUCTURES
Figure 24-1 illustrates the different states of a VMCS. It uses “X” to refer to the VMCS and “Y” to refer to any other
VMCS. Thus: “VMPTRLD X” always makes X current and active; “VMPTRLD Y” always makes X not current (because
it makes Y current); VMLAUNCH makes the launch state of X “launched” if X was current and its launch state was
“clear”; and VMCLEAR X always makes X inactive and not current and makes its launch state “clear”.
The figure does not illustrate operations that do not modify the VMCS state relative to these parameters (e.g.,
execution of VMPTRLD X when X is already current). Note that VMCLEAR X makes X “inactive, not current, and
clear,” even if X’s current state is not defined (e.g., even if X has not yet been initialized). See Section 24.11.3.
VMCLEAR X
VMCLEAR X
X
VMLAUNCH
VMPTRLD Y
R
Anything
Else
Active
Not Current
Launched
VMPTRLD X
VMCLEAR X
A
LE
Active
Current
Clear
Inactive
Not Current
Clear
C
VM
VMPTRLD Y
VMPTRLD X
V
VM M P
CL TR
EA LD
R X
X
Active
Not Current
Clear
Active
Current
Launched
Figure 24-1. States of VMCS X
Because a shadow VMCS (see Section 24.10) cannot be used for VM entry, the launch state of a shadow VMCS is
not meaningful. Figure 24-1 does not illustrate all the ways in which a shadow VMCS may be made active.
24.2
FORMAT OF THE VMCS REGION
A VMCS region comprises up to 4-KBytes.1 The format of a VMCS region is given in Table 24-1.
Table 24-1. Format of the VMCS Region
Byte Offset
0
Contents
Bits 30:0: VMCS revision identifier
Bit 31: shadow-VMCS indicator (see Section 24.10)
4
VMX-abort indicator
8
VMCS data (implementation-specific format)
The first 4 bytes of the VMCS region contain the VMCS revision identifier at bits 30:0.2 Processors that maintain
VMCS data in different formats (see below) use different VMCS revision identifiers. These identifiers enable soft-
1. The exact size is implementation specific and can be determined by consulting the VMX capability MSR IA32_VMX_BASIC to determine the size of the VMCS region (see Appendix A.1).
24-2 Vol. 3C
VIRTUAL MACHINE CONTROL STRUCTURES
ware to avoid using a VMCS region formatted for one processor on a processor that uses a different format.1 Bit 31
of this 4-byte region indicates whether the VMCS is a shadow VMCS (see Section 24.10).
Software should write the VMCS revision identifier to the VMCS region before using that region for a VMCS. The
VMCS revision identifier is never written by the processor; VMPTRLD fails if its operand references a VMCS region
whose VMCS revision identifier differs from that used by the processor. (VMPTRLD also fails if the shadow-VMCS
indicator is 1 and the processor does not support the 1-setting of the “VMCS shadowing” VM-execution control; see
Section 24.6.2) Software can discover the VMCS revision identifier that a processor uses by reading the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1).
Software should clear or set the shadow-VMCS indicator depending on whether the VMCS is to be an ordinary
VMCS or a shadow VMCS (see Section 24.10). VMPTRLD fails if the shadow-VMCS indicator is set and the processor
does not support the 1-setting of the “VMCS shadowing” VM-execution control. Software can discover support for
this setting by reading the VMX capability MSR IA32_VMX_PROCBASED_CTLS2 (see Appendix A.3.3).
The next 4 bytes of the VMCS region are used for the VMX-abort indicator. The contents of these bits do not
control processor operation in any way. A logical processor writes a non-zero value into these bits if a VMX abort
occurs (see Section 27.7). Software may also write into this field.
The remainder of the VMCS region is used for VMCS data (those parts of the VMCS that control VMX non-root
operation and the VMX transitions). The format of these data is implementation-specific. VMCS data are discussed
in Section 24.3 through Section 24.9. To ensure proper behavior in VMX operation, software should maintain the
VMCS region and related structures (enumerated in Section 24.11.4) in writeback cacheable memory. Future
implementations may allow or require a different memory type2. Software should consult the VMX capability MSR
IA32_VMX_BASIC (see Appendix A.1).
24.3
ORGANIZATION OF VMCS DATA
The VMCS data are organized into six logical groups:
•
Guest-state area. Processor state is saved into the guest-state area on VM exits and loaded from there on
VM entries.
•
•
Host-state area. Processor state is loaded from the host-state area on VM exits.
•
•
•
VM-exit control fields. These fields control VM exits.
VM-execution control fields. These fields control processor behavior in VMX non-root operation. They
determine in part the causes of VM exits.
VM-entry control fields. These fields control VM entries.
VM-exit information fields. These fields receive information on VM exits and describe the cause and the
nature of VM exits. On some processors, these fields are read-only.3
The VM-execution control fields, the VM-exit control fields, and the VM-entry control fields are sometimes referred
to collectively as VMX controls.
2. Earlier versions of this manual specified that the VMCS revision identifier was a 32-bit field. For all processors produced prior to this
change, bit 31 of the VMCS revision identifier was 0.
1. Logical processors that use the same VMCS revision identifier use the same size for VMCS regions.
2. Alternatively, software may map any of these regions or structures with the UC memory type. Doing so is strongly discouraged
unless necessary as it will cause the performance of transitions using those structures to suffer significantly. In addition, the processor will continue to use the memory type reported in the VMX capability MSR IA32_VMX_BASIC with exceptions noted in Appendix A.1.
3.
Software can discover whether these fields can be written by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6).
Vol. 3C 24-3
VIRTUAL MACHINE CONTROL STRUCTURES
24.4
GUEST-STATE AREA
This section describes fields contained in the guest-state area of the VMCS. As noted earlier, processor state is
loaded from these fields on every VM entry (see Section 26.3.2) and stored into these fields on every VM exit (see
Section 27.3).
24.4.1
Guest Register State
The following fields in the guest-state area correspond to processor registers:
•
Control registers CR0, CR3, and CR4 (64 bits each; 32 bits on processors that do not support Intel 64 architecture).
•
•
•
Debug register DR7 (64 bits; 32 bits on processors that do not support Intel 64 architecture).
RSP, RIP, and RFLAGS (64 bits each; 32 bits on processors that do not support Intel 64 architecture).1
The following fields for each of the registers CS, SS, DS, ES, FS, GS, LDTR, and TR:
— Selector (16 bits).
— Base address (64 bits; 32 bits on processors that do not support Intel 64 architecture). The base-address
fields for CS, SS, DS, and ES have only 32 architecturally-defined bits; nevertheless, the corresponding
VMCS fields have 64 bits on processors that support Intel 64 architecture.
— Segment limit (32 bits). The limit field is always a measure in bytes.
— Access rights (32 bits). The format of this field is given in Table 24-2 and detailed as follows:
•
The low 16 bits correspond to bits 23:8 of the upper 32 bits of a 64-bit segment descriptor. While bits
19:16 of code-segment and data-segment descriptors correspond to the upper 4 bits of the segment
limit, the corresponding bits (bits 11:8) are reserved in this VMCS field.
•
Bit 16 indicates an unusable segment. Attempts to use such a segment fault except in 64-bit mode.
In general, a segment register is unusable if it has been loaded with a null selector.2
•
Bits 31:17 are reserved.
Table 24-2. Format of Access Rights
Bit Position(s)
Field
3:0
Segment type
4
S — Descriptor type (0 = system; 1 = code or data)
6:5
DPL — Descriptor privilege level
7
P — Segment present
11:8
Reserved
12
AVL — Available for use by system software
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX operation also support Intel 64 architecture. For processors that do not support Intel 64 architecture, this notation refers to the 32-bit
forms of those registers (EAX, EIP, ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to lower 32
bits of the indicated register.
2. There are a few exceptions to this statement. For example, a segment with a non-null selector may be unusable following a task
switch that fails after its commit point; see “Interrupt 10—Invalid TSS Exception (#TS)” in Section 6.14, “Exception and Interrupt
Handling in 64-bit Mode,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. In contrast, the TR register is usable after processor reset despite having a null selector; see Table 10-1 in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A.
24-4 Vol. 3C
VIRTUAL MACHINE CONTROL STRUCTURES
Table 24-2. Format of Access Rights (Contd.)
Bit Position(s)
Field
13
Reserved (except for CS)
L — 64-bit mode active (for CS only)
14
D/B — Default operation size (0 = 16-bit segment; 1 = 32-bit segment)
15
G — Granularity
16
Segment unusable (0 = usable; 1 = unusable)
31:17
Reserved
The base address, segment limit, and access rights compose the “hidden” part (or “descriptor cache”) of each
segment register. These data are included in the VMCS because it is possible for a segment register’s descriptor
cache to be inconsistent with the segment descriptor in memory (in the GDT or the LDT) referenced by the
segment register’s selector.
The value of the DPL field for SS is always equal to the logical processor’s current privilege level (CPL).1
•
The following fields for each of the registers GDTR and IDTR:
— Base address (64 bits; 32 bits on processors that do not support Intel 64 architecture).
— Limit (32 bits). The limit fields contain 32 bits even though these fields are specified as only 16 bits in the
architecture.
•
The following MSRs:
— IA32_DEBUGCTL (64 bits)
— IA32_SYSENTER_CS (32 bits)
— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP (64 bits; 32 bits on processors that do not support Intel 64
architecture)
— IA32_PERF_GLOBAL_CTRL (64 bits). This field is supported only on processors that support the 1-setting
of the “load IA32_PERF_GLOBAL_CTRL” VM-entry control.
— IA32_PAT (64 bits). This field is supported only on processors that support either the 1-setting of the “load
IA32_PAT” VM-entry control or that of the “save IA32_PAT” VM-exit control.
— IA32_EFER (64 bits). This field is supported only on processors that support either the 1-setting of the “load
IA32_EFER” VM-entry control or that of the “save IA32_EFER” VM-exit control.
— IA32_BNDCFGS (64 bits). This field is supported only on processors that support either the 1-setting of the
“load IA32_BNDCFGS” VM-entry control or that of the “clear IA32_BNDCFGS” VM-exit control.
•
The register SMBASE (32 bits). This register contains the base address of the logical processor’s SMRAM image.
24.4.2
Guest Non-Register State
In addition to the register state described in Section 24.4.1, the guest-state area includes the following fields that
characterize guest state but which do not correspond to processor registers:
•
Activity state (32 bits). This field identifies the logical processor’s activity state. When a logical processor is
executing instructions normally, it is in the active state. Execution of certain instructions and the occurrence
of certain events may cause a logical processor to transition to an inactive state in which it ceases to execute
instructions.
The following activity states are defined:2
— 0: Active. The logical processor is executing instructions normally.
1. In protected mode, CPL is also associated with the RPL field in the CS selector. However, the RPL fields are not meaningful in realaddress mode or in virtual-8086 mode.
Vol. 3C 24-5
VIRTUAL MACHINE CONTROL STRUCTURES
— 1: HLT. The logical processor is inactive because it executed the HLT instruction.
— 2: Shutdown. The logical processor is inactive because it incurred a triple fault1 or some other serious
error.
— 3: Wait-for-SIPI. The logical processor is inactive because it is waiting for a startup-IPI (SIPI).
Future processors may include support for other activity states. Software should read the VMX capability MSR
IA32_VMX_MISC (see Appendix A.6) to determine what activity states are supported.
•
Interruptibility state (32 bits). The IA-32 architecture includes features that permit certain events to be
blocked for a period of time. This field contains information about such blocking. Details and the format of this
field are given in Table 24-3.
Table 24-3. Format of Interruptibility State
Bit
Position(s)
Bit Name
Notes
0
Blocking by STI
See the “STI—Set Interrupt Flag” section in Chapter 4 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 2B.
Execution of STI with RFLAGS.IF = 0 blocks interrupts (and, optionally, other events) for one
instruction after its execution. Setting this bit indicates that this blocking is in effect.
1
Blocking by
MOV SS
See the “MOV—Move a Value from the Stack” from Chapter 4 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2B, and “POP—Pop a Value from the
Stack” from Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B, and Section 6.8.3 in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
Execution of a MOV to SS or a POP to SS blocks interrupts for one instruction after its
execution. In addition, certain debug exceptions are inhibited between a MOV to SS or a POP to
SS and a subsequent instruction. Setting this bit indicates that the blocking of all these events
is in effect. This document uses the term “blocking by MOV SS,” but it applies equally to POP SS.
2
Blocking by SMI
See Section 34.2. System-management interrupts (SMIs) are disabled while the processor is in
system-management mode (SMM). Setting this bit indicates that blocking of SMIs is in effect.
3
Blocking by NMI
See Section 6.7.1 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A and Section 34.8.
Delivery of a non-maskable interrupt (NMI) or a system-management interrupt (SMI) blocks
subsequent NMIs until the next execution of IRET. See Section 25.3 for how this behavior of
IRET may change in VMX non-root operation. Setting this bit indicates that blocking of NMIs is
in effect. Clearing this bit does not imply that NMIs are not (temporarily) blocked for other
reasons.
If the “virtual NMIs” VM-execution control (see Section 24.6.1) is 1, this bit does not control the
blocking of NMIs. Instead, it refers to “virtual-NMI blocking” (the fact that guest software is not
ready for an NMI).
•
4
Enclave
interruption
A VM exit saves this bit as 1 to indicate that the VM exit was incident to enclave mode.
31:5
Reserved
VM entry will fail if these bits are not 0. See Section 26.3.1.5.
Pending debug exceptions (64 bits; 32 bits on processors that do not support Intel 64 architecture). IA-32
processors may recognize one or more debug exceptions without immediately delivering them.2 This field
contains information about such exceptions. This field is described in Table 24-4.
2. Execution of the MWAIT instruction may put a logical processor into an inactive state. However, this VMCS field never reflects this
state. See Section 27.1.
1. A triple fault occurs when a logical processor encounters an exception while attempting to deliver a double fault.
24-6 Vol. 3C
VIRTUAL MACHINE CONTROL STRUCTURES
Table 24-4. Format of Pending-Debug-Exceptions
Bit
Position(s)
Bit Name
Notes
3:0
B3 – B0
When set, each of these bits indicates that the corresponding breakpoint condition was met.
Any of these bits may be set even if the corresponding enabling bit in DR7 is not set.
11:4
Reserved
VM entry fails if these bits are not 0. See Section 26.3.1.5.
12
Enabled
breakpoint
When set, this bit indicates that at least one data or I/O breakpoint was met and was enabled in
DR7.
13
Reserved
VM entry fails if this bit is not 0. See Section 26.3.1.5.
14
BS
When set, this bit indicates that a debug exception would have been triggered by single-step
execution mode.
15
Reserved
VM entry fails if this bit is not 0. See Section 26.3.1.5.
16
RTM
When set, this bit indicates that a debug exception (#DB) or a breakpoint exception (#BP)
occurred inside an RTM region while advanced debugging of RTM transactional regions was
enabled (see Section 16.3.7, “RTM-Enabled Debugger Support,” of Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1).1
63:17
Reserved
VM entry fails if these bits are not 0. See Section 26.3.1.5. Bits 63:32 exist only on processors
that support Intel 64 architecture.
NOTES:
1. In general, the format of this field matches that of DR6. However, DR6 clears bit 16 to indicate an RTM-related exception, while this
field sets the bit to indicate that condition.
•
VMCS link pointer (64 bits). If the “VMCS shadowing” VM-execution control is 1, the VMREAD and VMWRITE
instructions access the VMCS referenced by this pointer (see Section 24.10). Otherwise, software should set
this field to FFFFFFFF_FFFFFFFFH to avoid VM-entry failures (see Section 26.3.1.5).
•
VMX-preemption timer value (32 bits). This field is supported only on processors that support the 1-setting
of the “activate VMX-preemption timer” VM-execution control. This field contains the value that the VMXpreemption timer will use following the next VM entry with that setting. See Section 25.5.1 and Section 26.6.4.
•
Page-directory-pointer-table entries (PDPTEs; 64 bits each). These four (4) fields (PDPTE0, PDPTE1,
PDPTE2, and PDPTE3) are supported only on processors that support the 1-setting of the “enable EPT” VMexecution control. They correspond to the PDPTEs referenced by CR3 when PAE paging is in use (see Section
4.4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). They are used only if
the “enable EPT” VM-execution control is 1.
•
Guest interrupt status (16 bits). This field is supported only on processors that support the 1-setting of the
“virtual-interrupt delivery” VM-execution control. It characterizes part of the guest’s virtual-APIC state and
does not correspond to any processor or APIC registers. It comprises two 8-bit subfields:
— Requesting virtual interrupt (RVI). This is the low byte of the guest interrupt status. The processor
treats this value as the vector of the highest priority virtual interrupt that is requesting service. (The value
0 implies that there is no such interrupt.)
— Servicing virtual interrupt (SVI). This is the high byte of the guest interrupt status. The processor
treats this value as the vector of the highest priority virtual interrupt that is in service. (The value 0 implies
that there is no such interrupt.)
2. For example, execution of a MOV to SS or a POP to SS may inhibit some debug exceptions for one instruction. See Section 6.8.3 of
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. In addition, certain events incident to an instruction
(for example, an INIT signal) may take priority over debug traps generated by that instruction. See Table 6-2 in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A.
Vol. 3C 24-7
VIRTUAL MACHINE CONTROL STRUCTURES
See Chapter 29 for more information on the use of this field.
•
PML index (16 bits). This field is supported only on processors that support the 1-setting of the “enable PML”
VM-execution control. It contains the logical index of the next entry in the page-modification log. Because the
page-modification log comprises 512 entries, the PML index is typically a value in the range 0–511. Details of
the page-modification log and use of the PML index are given in Section 28.2.5.
24.5
HOST-STATE AREA
This section describes fields contained in the host-state area of the VMCS. As noted earlier, processor state is
loaded from these fields on every VM exit (see Section 27.5).
All fields in the host-state area correspond to processor registers:
•
•
•
CR0, CR3, and CR4 (64 bits each; 32 bits on processors that do not support Intel 64 architecture).
•
Base-address fields for FS, GS, TR, GDTR, and IDTR (64 bits each; 32 bits on processors that do not support
Intel 64 architecture).
•
The following MSRs:
RSP and RIP (64 bits each; 32 bits on processors that do not support Intel 64 architecture).
Selector fields (16 bits each) for the segment registers CS, SS, DS, ES, FS, GS, and TR. There is no field in the
host-state area for the LDTR selector.
— IA32_SYSENTER_CS (32 bits)
— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP (64 bits; 32 bits on processors that do not support Intel 64
architecture).
— IA32_PERF_GLOBAL_CTRL (64 bits). This field is supported only on processors that support the 1-setting of
the “load IA32_PERF_GLOBAL_CTRL” VM-exit control.
— IA32_PAT (64 bits). This field is supported only on processors that support the 1-setting of the “load
IA32_PAT” VM-exit control.
— IA32_EFER (64 bits). This field is supported only on processors that support the 1-setting of the “load
IA32_EFER” VM-exit control.
In addition to the state identified here, some processor state components are loaded with fixed values on every
VM exit; there are no fields corresponding to these components in the host-state area. See Section 27.5 for details
of how state is loaded on VM exits.
24.6
VM-EXECUTION CONTROL FIELDS
The VM-execution control fields govern VMX non-root operation. These are described in Section 24.6.1 through
Section 24.6.8.
24.6.1
Pin-Based VM-Execution Controls
The pin-based VM-execution controls constitute a 32-bit vector that governs the handling of asynchronous events
(for example: interrupts).1 Table 24-5 lists the controls. See Chapter 27 for how these controls affect processor
behavior in VMX non-root operation.
1. Some asynchronous events cause VM exits regardless of the settings of the pin-based VM-execution controls (see Section 25.2).
24-8 Vol. 3C
VIRTUAL MACHINE CONTROL STRUCTURES
Table 24-5. Definitions of Pin-Based VM-Execution Controls
Bit Position(s) Name
Description
0
External-interrupt
exiting
If this control is 1, external interrupts cause VM exits. Otherwise, they are delivered normally
through the guest interrupt-descriptor table (IDT). If this control is 1, the value of RFLAGS.IF
does not affect interrupt blocking.
3
NMI exiting
If this control is 1, non-maskable interrupts (NMIs) cause VM exits. Otherwise, they are
delivered normally using descriptor 2 of the IDT. This control also determines interactions
between IRET and blocking by NMI (see Section 25.3).
5
Virtual NMIs
If this control is 1, NMIs are never blocked and the “blocking by NMI” bit (bit 3) in the
interruptibility-state field indicates “virtual-NMI blocking” (see Table 24-3). This control also
interacts with the “NMI-window exiting” VM-execution control (see Section 24.6.2).
6
Activate VMXpreemption timer
If this control is 1, the VMX-preemption timer counts down in VMX non-root operation; see
Section 25.5.1. A VM exit occurs when the timer counts down to zero; see Section 25.2.
7
Process posted
interrupts
If this control is 1, the processor treats interrupts with the posted-interrupt notification vector
(see Section 24.6.8) specially, updating the virtual-APIC page with posted-interrupt requests
(see Section 29.6).
All other bits in this field are reserved, some to 0 and some to 1. Software should consult the VMX capability MSRs
IA32_VMX_PINBASED_CTLS and IA32_VMX_TRUE_PINBASED_CTLS (see Appendix A.3.1) to determine how to
set reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section 26.2.1.1).
The first processors to support the virtual-machine extensions supported only the 1-settings of bits 1, 2, and 4.
The VMX capability MSR IA32_VMX_PINBASED_CTLS will always report that these bits must be 1. Logical processors that support the 0-settings of any of these bits will support the VMX capability MSR
IA32_VMX_TRUE_PINBASED_CTLS MSR, and software should consult this MSR to discover support for the 0settings of these bits. Software that is not aware of the functionality of any one of these bits should set that bit to 1.
24.6.2
Processor-Based VM-Execution Controls
The processor-based VM-execution controls constitute two 32-bit vectors that govern the handling of synchronous
events, mainly those caused by the execution of specific instructions.1 These are the primary processor-based
VM-execution controls and the secondary processor-based VM-execution controls.
Table 24-6 lists the primary processor-based VM-execution controls. See Chapter 25 for more details of how these
controls affect processor behavior in VMX non-root operation.
Table 24-6. Definitions of Primary Processor-Based VM-Execution Controls
Bit Position(s) Name
Description
2
Interrupt-window
exiting
If this control is 1, a VM exit occurs at the beginning of any instruction if RFLAGS.IF = 1 and
there are no other blocking of interrupts (see Section 24.4.2).
3
Use TSC offsetting
This control determines whether executions of RDTSC, executions of RDTSCP, and executions
of RDMSR that read from the IA32_TIME_STAMP_COUNTER MSR return a value modified by
the TSC offset field (see Section 24.6.5 and Section 25.3).
7
HLT exiting
This control determines whether executions of HLT cause VM exits.
9
INVLPG exiting
This determines whether executions of INVLPG cause VM exits.
10
MWAIT exiting
This control determines whether executions of MWAIT cause VM exits.
11
RDPMC exiting
This control determines whether executions of RDPMC cause VM exits.
12
RDTSC exiting
This control determines whether executions of RDTSC and RDTSCP cause VM exits.
1. Some instructions cause VM exits regardless of the settings of the processor-based VM-execution controls (see Section 25.1.2), as
do task switches (see Section 25.2).
Vol. 3C 24-9
VIRTUAL MACHINE CONTROL STRUCTURES
Table 24-6. Definitions of Primary Processor-Based VM-Execution Controls (Contd.)
Bit Position(s) Name
Description
15
In conjunction with the CR3-target controls (see Section 24.6.7), this control determines
whether executions of MOV to CR3 cause VM exits. See Section 25.1.3.
CR3-load exiting
The first processors to support the virtual-machine extensions supported only the 1-setting
of this control.
16
CR3-store exiting
This control determines whether executions of MOV from CR3 cause VM exits.
The first processors to support the virtual-machine extensions supported only the 1-setting
of this control.
19
CR8-load exiting
This control determines whether executions of MOV to CR8 cause VM exits.
20
CR8-store exiting
This control determines whether executions of MOV from CR8 cause VM exits.
21
Use TPR shadow
Setting this control to 1 enables TPR virtualization and other APIC-virtualization features. See
Chapter 29.
22
NMI-window
exiting
If this control is 1, a VM exit occurs at the beginning of any instruction if there is no virtualNMI blocking (see Section 24.4.2).
23
MOV-DR exiting
This control determines whether executions of MOV DR cause VM exits.
24
Unconditional I/O
exiting
This control determines whether executions of I/O instructions (IN, INS/INSB/INSW/INSD, OUT,
and OUTS/OUTSB/OUTSW/OUTSD) cause VM exits.
25
Use I/O bitmaps
This control determines whether I/O bitmaps are used to restrict executions of I/O instructions
(see Section 24.6.4 and Section 25.1.3).
For this control, “0” means “do not use I/O bitmaps” and “1” means “use I/O bitmaps.” If the I/O
bitmaps are used, the setting of the “unconditional I/O exiting” control is ignored.
27
Monitor trap flag
If this control is 1, the monitor trap flag debugging feature is enabled. See Section 25.5.2.
28
Use MSR bitmaps
This control determines whether MSR bitmaps are used to control execution of the RDMSR
and WRMSR instructions (see Section 24.6.9 and Section 25.1.3).
For this control, “0” means “do not use MSR bitmaps” and “1” means “use MSR bitmaps.” If the
MSR bitmaps are not used, all executions of the RDMSR and WRMSR instructions cause
VM exits.
29
MONITOR exiting
This control determines whether executions of MONITOR cause VM exits.
30
PAUSE exiting
This control determines whether executions of PAUSE cause VM exits.
31
Activate secondary This control determines whether the secondary processor-based VM-execution controls are
controls
used. If this control is 0, the logical processor operates as if all the secondary processor-based
VM-execution controls were also 0.
All other bits in this field are reserved, some to 0 and some to 1. Software should consult the VMX capability MSRs
IA32_VMX_PROCBASED_CTLS and IA32_VMX_TRUE_PROCBASED_CTLS (see Appendix A.3.2) to determine how
to set reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section
26.2.1.1).
The first processors to support the virtual-machine extensions supported only the 1-settings of bits 1, 4–6, 8, 13–
16, and 26. The VMX capability MSR IA32_VMX_PROCBASED_CTLS will always report that these bits must be 1.
Logical processors that support the 0-settings of any of these bits will support the VMX capability MSR
IA32_VMX_TRUE_PROCBASED_CTLS MSR, and software should consult this MSR to discover support for the 0settings of these bits. Software that is not aware of the functionality of any one of these bits should set that bit to 1.
Bit 31 of the primary processor-based VM-execution controls determines whether the secondary processor-based
VM-execution controls are used. If that bit is 0, VM entry and VMX non-root operation function as if all the
secondary processor-based VM-execution controls were 0. Processors that support only the 0-setting of bit 31 of
the primary processor-based VM-execution controls do not support the secondary processor-based VM-execution
controls.
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VIRTUAL MACHINE CONTROL STRUCTURES
Table 24-7 lists the secondary processor-based VM-execution controls. See Chapter 25 for more details of how
these controls affect processor behavior in VMX non-root operation.
Table 24-7. Definitions of Secondary Processor-Based VM-Execution Controls
Bit Position(s) Name
Description
0
Virtualize APIC
accesses
If this control is 1, the logical processor treats specially accesses to the page with the APICaccess address. See Section 29.4.
1
Enable EPT
If this control is 1, extended page tables (EPT) are enabled. See Section 28.2.
2
Descriptor-table
exiting
This control determines whether executions of LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, and
STR cause VM exits.
3
Enable RDTSCP
If this control is 0, any execution of RDTSCP causes an invalid-opcode exception (#UD).
4
Virtualize x2APIC
mode
If this control is 1, the logical processor treats specially RDMSR and WRMSR to APIC MSRs (in
the range 800H–8FFH). See Section 29.5.
5
Enable VPID
If this control is 1, cached translations of linear addresses are associated with a virtualprocessor identifier (VPID). See Section 28.1.
6
WBINVD exiting
This control determines whether executions of WBINVD cause VM exits.
7
Unrestricted guest
This control determines whether guest software may run in unpaged protected mode or in realaddress mode.
8
APIC-register
virtualization
If this control is 1, the logical processor virtualizes certain APIC accesses. See Section 29.4 and
Section 29.5.
9
Virtual-interrupt
delivery
This controls enables the evaluation and delivery of pending virtual interrupts as well as the
emulation of writes to the APIC registers that control interrupt prioritization.
10
PAUSE-loop exiting This control determines whether a series of executions of PAUSE can cause a VM exit (see
Section 24.6.13 and Section 25.1.3).
11
RDRAND exiting
This control determines whether executions of RDRAND cause VM exits.
12
Enable INVPCID
If this control is 0, any execution of INVPCID causes a #UD.
13
Enable
VM functions
Setting this control to 1 enables use of the VMFUNC instruction in VMX non-root operation. See
Section 25.5.5.
14
VMCS shadowing
If this control is 1, executions of VMREAD and VMWRITE in VMX non-root operation may access
a shadow VMCS (instead of causing VM exits). See Section 24.10 and Section 30.3.
15
Enable ENCLS
exiting
If this control is 1, executions of ENCLS consult the ENCLS-exiting bitmap to determine whether
the instruction causes a VM exit. See Section 24.6.16 and Section 25.1.3.
16
RDSEED exiting
This control determines whether executions of RDSEED cause VM exits.
17
Enable PML
If this control is 1, an access to a guest-physical address that sets an EPT dirty bit first adds an
entry to the page-modification log. See Section 28.2.5.
18
EPT-violation #VE
If this control is 1, EPT violations may cause virtualization exceptions (#VE) instead of VM exits.
See Section 25.5.6.
19
Conceal VMX non- If this control is 1, Intel Processor Trace suppresses data packets that indicate the use of
root operation from virtualization (see Chapter 36).
Intel PT
20
Enable
XSAVES/XRSTORS
22
Mode-based
If this control is 1, EPT execute permissions are based on whether the linear address being
execute control for accessed is supervisor mode or user mode. See Chapter 28.
EPT
25
Use TSC scaling
If this control is 0, any execution of XSAVES or XRSTORS causes a #UD.
This control determines whether executions of RDTSC, executions of RDTSCP, and executions
of RDMSR that read from the IA32_TIME_STAMP_COUNTER MSR return a value modified by the
TSC multiplier field (see Section 24.6.5 and Section 25.3).
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All other bits in this field are reserved to 0. Software should consult the VMX capability MSR
IA32_VMX_PROCBASED_CTLS2 (see Appendix A.3.3) to determine which bits may be set to 1. Failure to clear
reserved bits causes subsequent VM entries to fail (see Section 26.2.1.1).
24.6.3
Exception Bitmap
The exception bitmap is a 32-bit field that contains one bit for each exception. When an exception occurs, its
vector is used to select a bit in this field. If the bit is 1, the exception causes a VM exit. If the bit is 0, the exception
is delivered normally through the IDT, using the descriptor corresponding to the exception’s vector.
Whether a page fault (exception with vector 14) causes a VM exit is determined by bit 14 in the exception bitmap
as well as the error code produced by the page fault and two 32-bit fields in the VMCS (the page-fault error-code
mask and page-fault error-code match). See Section 25.2 for details.
24.6.4
I/O-Bitmap Addresses
The VM-execution control fields include the 64-bit physical addresses of I/O bitmaps A and B (each of which are
4 KBytes in size). I/O bitmap A contains one bit for each I/O port in the range 0000H through 7FFFH; I/O bitmap B
contains bits for ports in the range 8000H through FFFFH.
A logical processor uses these bitmaps if and only if the “use I/O bitmaps” control is 1. If the bitmaps are used,
execution of an I/O instruction causes a VM exit if any bit in the I/O bitmaps corresponding to a port it accesses is
1. See Section 25.1.3 for details. If the bitmaps are used, their addresses must be 4-KByte aligned.
24.6.5
Time-Stamp Counter Offset and Multiplier
The VM-execution control fields include a 64-bit TSC-offset field. If the “RDTSC exiting” control is 0 and the “use
TSC offsetting” control is 1, this field controls executions of the RDTSC and RDTSCP instructions. It also controls
executions of the RDMSR instruction that read from the IA32_TIME_STAMP_COUNTER MSR. For all of these, the
value of the TSC offset is added to the value of the time-stamp counter, and the sum is returned to guest software
in EDX:EAX.
Processors that support the 1-setting of the “use TSC scaling” control also support a 64-bit TSC-multiplier field.
If this control is 1 (and the “RDTSC exiting” control is 0 and the “use TSC offsetting” control is 1), this field also
affects the executions of the RDTSC, RDTSCP, and RDMSR instructions identified above. Specifically, the contents
of the time-stamp counter is first multiplied by the TSC multiplier before adding the TSC offset.
See Chapter 27 for a detailed treatment of the behavior of RDTSC, RDTSCP, and RDMSR in VMX non-root operation.
24.6.6
Guest/Host Masks and Read Shadows for CR0 and CR4
VM-execution control fields include guest/host masks and read shadows for the CR0 and CR4 registers. These
fields control executions of instructions that access those registers (including CLTS, LMSW, MOV CR, and SMSW).
They are 64 bits on processors that support Intel 64 architecture and 32 bits on processors that do not.
In general, bits set to 1 in a guest/host mask correspond to bits “owned” by the host:
•
Guest attempts to set them (using CLTS, LMSW, or MOV to CR) to values differing from the corresponding bits
in the corresponding read shadow cause VM exits.
•
Guest reads (using MOV from CR or SMSW) return values for these bits from the corresponding read shadow.
Bits cleared to 0 correspond to bits “owned” by the guest; guest attempts to modify them succeed and guest reads
return values for these bits from the control register itself.
See Chapter 27 for details regarding how these fields affect VMX non-root operation.
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VIRTUAL MACHINE CONTROL STRUCTURES
24.6.7
CR3-Target Controls
The VM-execution control fields include a set of 4 CR3-target values and a CR3-target count. The CR3-target
values each have 64 bits on processors that support Intel 64 architecture and 32 bits on processors that do not.
The CR3-target count has 32 bits on all processors.
An execution of MOV to CR3 in VMX non-root operation does not cause a VM exit if its source operand matches one
of these values. If the CR3-target count is n, only the first n CR3-target values are considered; if the CR3-target
count is 0, MOV to CR3 always causes a VM exit
There are no limitations on the values that can be written for the CR3-target values. VM entry fails (see Section
26.2) if the CR3-target count is greater than 4.
Future processors may support a different number of CR3-target values. Software should read the VMX capability
MSR IA32_VMX_MISC (see Appendix A.6) to determine the number of values supported.
24.6.8
Controls for APIC Virtualization
There are three mechanisms by which software accesses registers of the logical processor’s local APIC:
•
If the local APIC is in xAPIC mode, it can perform memory-mapped accesses to addresses in the 4-KByte page
referenced by the physical address in the IA32_APIC_BASE MSR (see Section 10.4.4, “Local APIC Status and
Location” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A and Intel® 64
Architecture Processor Topology Enumeration).1
•
If the local APIC is in x2APIC mode, it can accesses the local APIC’s registers using the RDMSR and WRMSR
instructions (see Intel® 64 Architecture Processor Topology Enumeration).
•
In 64-bit mode, it can access the local APIC’s task-priority register (TPR) using the MOV CR8 instruction.
There are five processor-based VM-execution controls (see Section 24.6.2) that control such accesses. There are
“use TPR shadow”, “virtualize APIC accesses”, “virtualize x2APIC mode”, “virtual-interrupt delivery”, and “APICregister virtualization”. These controls interact with the following fields:
•
APIC-access address (64 bits). This field contains the physical address of the 4-KByte APIC-access page.
If the “virtualize APIC accesses” VM-execution control is 1, access to this page may cause VM exits or be
virtualized by the processor. See Section 29.4.
The APIC-access address exists only on processors that support the 1-setting of the “virtualize APIC accesses”
VM-execution control.
•
Virtual-APIC address (64 bits). This field contains the physical address of the 4-KByte virtual-APIC page.
The processor uses the virtual-APIC page to virtualize certain accesses to APIC registers and to manage virtual
interrupts; see Chapter 29.
Depending on the setting of the controls indicated earlier, the virtual-APIC page may be accessed by the
following operations:
— The MOV CR8 instructions (see Section 29.3).
— Accesses to the APIC-access page if, in addition, the “virtualize APIC accesses” VM-execution control is 1
(see Section 29.4).
— The RDMSR and WRMSR instructions if, in addition, the value of ECX is in the range 800H–8FFH (indicating
an APIC MSR) and the “virtualize x2APIC mode” VM-execution control is 1 (see Section 29.5).
If the “use TPR shadow” VM-execution control is 1, VM entry ensures that the virtual-APIC address is 4-KByte
aligned. The virtual-APIC address exists only on processors that support the 1-setting of the “use TPR shadow”
VM-execution control.
•
TPR threshold (32 bits). Bits 3:0 of this field determine the threshold below which bits 7:4 of VTPR (see
Section 29.1.1) cannot fall. If the “virtual-interrupt delivery” VM-execution control is 0, a VM exit occurs after
an operation (e.g., an execution of MOV to CR8) that reduces the value of those bits below the TPR threshold.
See Section 29.1.2.
1. If the local APIC does not support x2APIC mode, it is always in xAPIC mode.
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The TPR threshold exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution
control.
•
EOI-exit bitmap (4 fields; 64 bits each). These fields are supported only on processors that support the 1setting of the “virtual-interrupt delivery” VM-execution control. They are used to determine which virtualized
writes to the APIC’s EOI register cause VM exits:
— EOI_EXIT0 contains bits for vectors from 0 (bit 0) to 63 (bit 63).
— EOI_EXIT1 contains bits for vectors from 64 (bit 0) to 127 (bit 63).
— EOI_EXIT2 contains bits for vectors from 128 (bit 0) to 191 (bit 63).
— EOI_EXIT3 contains bits for vectors from 192 (bit 0) to 255 (bit 63).
See Section 29.1.4 for more information on the use of this field.
•
Posted-interrupt notification vector (16 bits). This field is supported only on processors that support the 1setting of the “process posted interrupts” VM-execution control. Its low 8 bits contain the interrupt vector that
is used to notify a logical processor that virtual interrupts have been posted. See Section 29.6 for more
information on the use of this field.
•
Posted-interrupt descriptor address (64 bits). This field is supported only on processors that support the
1-setting of the “process posted interrupts” VM-execution control. It is the physical address of a 64-byte
aligned posted interrupt descriptor. See Section 29.6 for more information on the use of this field.
24.6.9
MSR-Bitmap Address
On processors that support the 1-setting of the “use MSR bitmaps” VM-execution control, the VM-execution control
fields include the 64-bit physical address of four contiguous MSR bitmaps, which are each 1-KByte in size. This
field does not exist on processors that do not support the 1-setting of that control. The four bitmaps are:
•
Read bitmap for low MSRs (located at the MSR-bitmap address). This contains one bit for each MSR address
in the range 00000000H to 00001FFFH. The bit determines whether an execution of RDMSR applied to that
MSR causes a VM exit.
•
Read bitmap for high MSRs (located at the MSR-bitmap address plus 1024). This contains one bit for each
MSR address in the range C0000000H toC0001FFFH. The bit determines whether an execution of RDMSR
applied to that MSR causes a VM exit.
•
Write bitmap for low MSRs (located at the MSR-bitmap address plus 2048). This contains one bit for each
MSR address in the range 00000000H to 00001FFFH. The bit determines whether an execution of WRMSR
applied to that MSR causes a VM exit.
•
Write bitmap for high MSRs (located at the MSR-bitmap address plus 3072). This contains one bit for each
MSR address in the range C0000000H toC0001FFFH. The bit determines whether an execution of WRMSR
applied to that MSR causes a VM exit.
A logical processor uses these bitmaps if and only if the “use MSR bitmaps” control is 1. If the bitmaps are used, an
execution of RDMSR or WRMSR causes a VM exit if the value of RCX is in neither of the ranges covered by the
bitmaps or if the appropriate bit in the MSR bitmaps (corresponding to the instruction and the RCX value) is 1. See
Section 25.1.3 for details. If the bitmaps are used, their address must be 4-KByte aligned.
24.6.10 Executive-VMCS Pointer
The executive-VMCS pointer is a 64-bit field used in the dual-monitor treatment of system-management interrupts
(SMIs) and system-management mode (SMM). SMM VM exits save this field as described in Section 34.15.2.
VM entries that return from SMM use this field as described in Section 34.15.4.
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VIRTUAL MACHINE CONTROL STRUCTURES
24.6.11 Extended-Page-Table Pointer (EPTP)
The extended-page-table pointer (EPTP) contains the address of the base of EPT PML4 table (see Section
28.2.2), as well as other EPT configuration information. The format of this field is shown in Table 24-8.
Table 24-8. Format of Extended-Page-Table Pointer
Bit
Position(s)
Field
2:0
EPT paging-structure memory type (see Section 28.2.6):
0 = Uncacheable (UC)
6 = Write-back (WB)
Other values are reserved.1
5:3
This value is 1 less than the EPT page-walk length (see Section 28.2.2)
6
Setting this control to 1 enables accessed and dirty flags for EPT (see Section 28.2.4)2
11:7
Reserved
N–1:12
Bits N–1:12 of the physical address of the 4-KByte aligned EPT PML4 table3
63:N
Reserved
NOTES:
1. Software should read the VMX capability MSR IA32_VMX_EPT_VPID_CAP (see Appendix A.10) to determine what EPT paging-structure memory types are supported.
2. Not all processors support accessed and dirty flags for EPT. Software should read the VMX capability MSR
IA32_VMX_EPT_VPID_CAP (see Appendix A.10) to determine whether the processor supports this feature.
3. N is the physical-address width supported by the logical processor. Software can determine a processor’s physical-address width by
executing CPUID with 80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX.
The EPTP exists only on processors that support the 1-setting of the “enable EPT” VM-execution control.
24.6.12 Virtual-Processor Identifier (VPID)
The virtual-processor identifier (VPID) is a 16-bit field. It exists only on processors that support the 1-setting
of the “enable VPID” VM-execution control. See Section 28.1 for details regarding the use of this field.
24.6.13 Controls for PAUSE-Loop Exiting
On processors that support the 1-setting of the “PAUSE-loop exiting” VM-execution control, the VM-execution
control fields include the following 32-bit fields:
•
PLE_Gap. Software can configure this field as an upper bound on the amount of time between two successive
executions of PAUSE in a loop.
•
PLE_Window. Software can configure this field as an upper bound on the amount of time a guest is allowed to
execute in a PAUSE loop.
These fields measure time based on a counter that runs at the same rate as the timestamp counter (TSC). See
Section 25.1.3 for more details regarding PAUSE-loop exiting.
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VIRTUAL MACHINE CONTROL STRUCTURES
24.6.14 VM-Function Controls
The VM-function controls constitute a 64-bit vector that governs use of the VMFUNC instruction in VMX non-root
operation. This field is supported only on processors that support the 1-settings of both the “activate secondary
controls” primary processor-based VM-execution control and the “enable VM functions” secondary processorbased VM-execution control.
Table 24-9 lists the VM-function controls. See Section 25.5.5 for more details of how these controls affect processor
behavior in VMX non-root operation.
Table 24-9. Definitions of VM-Function Controls
Bit Position(s) Name
Description
0
The EPTP-switching VM function changes the EPT pointer to a value chosen from the EPTP list.
See Section 25.5.5.3.
EPTP switching
All other bits in this field are reserved to 0. Software should consult the VMX capability MSR IA32_VMX_VMFUNC
(see Appendix A.11) to determine which bits are reserved. Failure to clear reserved bits causes subsequent
VM entries to fail (see Section 26.2.1.1).
Processors that support the 1-setting of the “EPTP switching” VM-function control also support a 64-bit field called
the EPTP-list address. This field contains the physical address of the 4-KByte EPTP list. The EPTP list comprises
512 8-Byte entries (each an EPTP value) and is used by the EPTP-switching VM function (see Section 25.5.5.3).
24.6.15 VMCS Shadowing Bitmap Addresses
On processors that support the 1-setting of the “VMCS shadowing” VM-execution control, the VM-execution control
fields include the 64-bit physical addresses of the VMREAD bitmap and the VMWRITE bitmap. Each bitmap is 4
KBytes in size and thus contains 32 KBits. The addresses are the VMREAD-bitmap address and the VMWRITEbitmap address.
If the “VMCS shadowing” VM-execution control is 1, executions of VMREAD and VMWRITE may consult these
bitmaps (see Section 24.10 and Section 30.3).
24.6.16 ENCLS-Exiting Bitmap
The ENCLS-exiting bitmap is a 64-bit field. If the “enable ENCLS exiting” VM-execution control is 1, execution of
ENCLS causes a VM exit if the bit in this field corresponding to the value of EAX is 1. If the bit is 0, the instruction
executes normally. See Section 25.1.3 for more information.
24.6.17 Control Field for Page-Modification Logging
The PML address is a 64-bit field. It is the 4-KByte aligned address of the page-modification log. The pagemodification log consists of 512 64-bit entries. It is used for the page-modification logging feature. Details of the
page-modification logging are given in Section 28.2.5.
If the “enable PML” VM-execution control is 1, VM entry ensures that the PML address is 4-KByte aligned. The PML
address exists only on processors that support the 1-setting of the “enable PML” VM-execution control.
24.6.18 Controls for Virtualization Exceptions
On processors that support the 1-setting of the “EPT-violation #VE” VM-execution control, the VM-execution
control fields include the following:
•
Virtualization-exception information address (64 bits). This field contains the physical address of the
virtualization-exception information area. When a logical processor encounters a virtualization exception,
it saves virtualization-exception information at the virtualization-exception information address; see Section
25.5.6.2.
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VIRTUAL MACHINE CONTROL STRUCTURES
•
EPTP index (16 bits). When an EPT violation causes a virtualization exception, the processor writes the value
of this field to the virtualization-exception information area. The EPTP-switching VM function updates this field
(see Section 25.5.5.3).
24.6.19 XSS-Exiting Bitmap
On processors that support the 1-setting of the “enable XSAVES/XRSTORS” VM-execution control, the VM-execution control fields include a 64-bit XSS-exiting bitmap. If the “enable XSAVES/XRSTORS” VM-execution control is
1, executions of XSAVES and XRSTORS may consult this bitmap (see Section 25.1.3 and Section 25.3).
24.7
VM-EXIT CONTROL FIELDS
The VM-exit control fields govern the behavior of VM exits. They are discussed in Section 24.7.1 and Section
24.7.2.
24.7.1
VM-Exit Controls
The VM-exit controls constitute a 32-bit vector that governs the basic operation of VM exits. Table 24-10 lists the
controls supported. See Chapter 27 for complete details of how these controls affect VM exits.
Table 24-10. Definitions of VM-Exit Controls
Bit Position(s) Name
Description
2
Save debug
controls
This control determines whether DR7 and the IA32_DEBUGCTL MSR are saved on VM exit.
9
Host addressspace size
On processors that support Intel 64 architecture, this control determines whether a logical
processor is in 64-bit mode after the next VM exit. Its value is loaded into CS.L,
IA32_EFER.LME, and IA32_EFER.LMA on every VM exit.1
12
Load
IA32_PERF_GLOB
AL_CTRL
This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit.
15
Acknowledge
interrupt on exit
This control affects VM exits due to external interrupts:
18
Save IA32_PAT
This control determines whether the IA32_PAT MSR is saved on VM exit.
19
Load IA32_PAT
This control determines whether the IA32_PAT MSR is loaded on VM exit.
The first processors to support the virtual-machine extensions supported only the 1-setting
of this control.
This control must be 0 on processors that do not support Intel 64 architecture.
• If such a VM exit occurs and this control is 1, the logical processor acknowledges the
interrupt controller, acquiring the interrupt’s vector. The vector is stored in the VM-exit
interruption-information field, which is marked valid.
• If such a VM exit occurs and this control is 0, the interrupt is not acknowledged and the
VM-exit interruption-information field is marked invalid.
20
Save IA32_EFER
This control determines whether the IA32_EFER MSR is saved on VM exit.
21
Load IA32_EFER
This control determines whether the IA32_EFER MSR is loaded on VM exit.
22
Save VMXpreemption timer
value
This control determines whether the value of the VMX-preemption timer is saved on VM exit.
23
Clear
IA32_BNDCFGS
This control determines whether the IA32_BNDCFGS MSR is cleared on VM exit.
24
Conceal VM exits
from Intel PT
If this control is 1, Intel Processor Trace does not produce a paging information packet (PIP) on
a VM exit (see Chapter 36).
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NOTES:
1. Since Intel 64 architecture specifies that IA32_EFER.LMA is always set to the logical-AND of CR0.PG and IA32_EFER.LME, and since
CR0.PG is always 1 in VMX operation, IA32_EFER.LMA is always identical to IA32_EFER.LME in VMX operation.
All other bits in this field are reserved, some to 0 and some to 1. Software should consult the VMX capability MSRs
IA32_VMX_EXIT_CTLS and IA32_VMX_TRUE_EXIT_CTLS (see Appendix A.4) to determine how it should set the
reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section 26.2.1.2).
The first processors to support the virtual-machine extensions supported only the 1-settings of bits 0–8, 10, 11,
13, 14, 16, and 17. The VMX capability MSR IA32_VMX_EXIT_CTLS always reports that these bits must be 1.
Logical processors that support the 0-settings of any of these bits will support the VMX capability MSR
IA32_VMX_TRUE_EXIT_CTLS MSR, and software should consult this MSR to discover support for the 0-settings of
these bits. Software that is not aware of the functionality of any one of these bits should set that bit to 1.
24.7.2
VM-Exit Controls for MSRs
A VMM may specify lists of MSRs to be stored and loaded on VM exits. The following VM-exit control fields determine how MSRs are stored on VM exits:
•
VM-exit MSR-store count (32 bits). This field specifies the number of MSRs to be stored on VM exit. It is
recommended that this count not exceed 512 bytes.1 Otherwise, unpredictable processor behavior (including a
machine check) may result during VM exit.
•
VM-exit MSR-store address (64 bits). This field contains the physical address of the VM-exit MSR-store area.
The area is a table of entries, 16 bytes per entry, where the number of entries is given by the VM-exit MSR-store
count. The format of each entry is given in Table 24-11. If the VM-exit MSR-store count is not zero, the address
must be 16-byte aligned.
Table 24-11. Format of an MSR Entry
Bit Position(s)
Contents
31:0
MSR index
63:32
Reserved
127:64
MSR data
See Section 27.4 for how this area is used on VM exits.
The following VM-exit control fields determine how MSRs are loaded on VM exits:
•
VM-exit MSR-load count (32 bits). This field contains the number of MSRs to be loaded on VM exit. It is
recommended that this count not exceed 512 bytes. Otherwise, unpredictable processor behavior (including a
machine check) may result during VM exit.2
•
VM-exit MSR-load address (64 bits). This field contains the physical address of the VM-exit MSR-load area.
The area is a table of entries, 16 bytes per entry, where the number of entries is given by the VM-exit MSR-load
count (see Table 24-11). If the VM-exit MSR-load count is not zero, the address must be 16-byte aligned.
See Section 27.6 for how this area is used on VM exits.
24.8
VM-ENTRY CONTROL FIELDS
The VM-entry control fields govern the behavior of VM entries. They are discussed in Sections 24.8.1 through
24.8.3.
1. Future implementations may allow more MSRs to be stored reliably. Software should consult the VMX capability MSR
IA32_VMX_MISC to determine the number supported (see Appendix A.6).
2. Future implementations may allow more MSRs to be loaded reliably. Software should consult the VMX capability MSR
IA32_VMX_MISC to determine the number supported (see Appendix A.6).
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24.8.1
VM-Entry Controls
The VM-entry controls constitute a 32-bit vector that governs the basic operation of VM entries. Table 24-12 lists
the controls supported. See Chapter 24 for how these controls affect VM entries.
Table 24-12. Definitions of VM-Entry Controls
Bit Position(s) Name
Description
2
This control determines whether DR7 and the IA32_DEBUGCTL MSR are loaded on VM entry.
Load debug
controls
9
The first processors to support the virtual-machine extensions supported only the 1-setting of
this control.
IA-32e mode guest On processors that support Intel 64 architecture, this control determines whether the logical
processor is in IA-32e mode after VM entry. Its value is loaded into IA32_EFER.LMA as part of
VM entry.1
This control must be 0 on processors that do not support Intel 64 architecture.
10
Entry to SMM
This control determines whether the logical processor is in system-management mode (SMM)
after VM entry. This control must be 0 for any VM entry from outside SMM.
11
Deactivate dualmonitor treatment
If set to 1, the default treatment of SMIs and SMM is in effect after the VM entry (see Section
34.15.7). This control must be 0 for any VM entry from outside SMM.
13
Load
This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry.
IA32_PERF_GLOBA
L_CTRL
14
Load IA32_PAT
This control determines whether the IA32_PAT MSR is loaded on VM entry.
15
Load IA32_EFER
This control determines whether the IA32_EFER MSR is loaded on VM entry.
16
Load
IA32_BNDCFGS
This control determines whether the IA32_BNDCFGS MSR is loaded on VM entry.
17
Conceal VM entries If this control is 1, Intel Processor Trace does not produce a paging information packet (PIP) on
from Intel PT
a VM entry (see Chapter 36).
NOTES:
1. Bit 5 of the IA32_VMX_MISC MSR is read as 1 on any logical processor that supports the 1-setting of the “unrestricted guest” VMexecution control. If it is read as 1, every VM exit stores the value of IA32_EFER.LMA into the “IA-32e mode guest” VM-entry control
(see Section 27.2).
All other bits in this field are reserved, some to 0 and some to 1. Software should consult the VMX capability MSRs
IA32_VMX_ENTRY_CTLS and IA32_VMX_TRUE_ENTRY_CTLS (see Appendix A.5) to determine how it should set
the reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section 26.2.1.3).
The first processors to support the virtual-machine extensions supported only the 1-settings of bits 0–8 and 12.
The VMX capability MSR IA32_VMX_ENTRY_CTLS always reports that these bits must be 1. Logical processors that
support the 0-settings of any of these bits will support the VMX capability MSR IA32_VMX_TRUE_ENTRY_CTLS
MSR, and software should consult this MSR to discover support for the 0-settings of these bits. Software that is not
aware of the functionality of any one of these bits should set that bit to 1.
24.8.2
VM-Entry Controls for MSRs
A VMM may specify a list of MSRs to be loaded on VM entries. The following VM-entry control fields manage this
functionality:
•
VM-entry MSR-load count (32 bits). This field contains the number of MSRs to be loaded on VM entry. It is
recommended that this count not exceed 512 bytes. Otherwise, unpredictable processor behavior (including a
machine check) may result during VM entry.1
1. Future implementations may allow more MSRs to be loaded reliably. Software should consult the VMX capability MSR
IA32_VMX_MISC to determine the number supported (see Appendix A.6).
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•
VM-entry MSR-load address (64 bits). This field contains the physical address of the VM-entry MSR-load
area. The area is a table of entries, 16 bytes per entry, where the number of entries is given by the VM-entry
MSR-load count. The format of entries is described in Table 24-11. If the VM-entry MSR-load count is not zero,
the address must be 16-byte aligned.
See Section 26.4 for details of how this area is used on VM entries.
24.8.3
VM-Entry Controls for Event Injection
VM entry can be configured to conclude by delivering an event through the IDT (after all guest state and MSRs have
been loaded). This process is called event injection and is controlled by the following three VM-entry control
fields:
•
VM-entry interruption-information field (32 bits). This field provides details about the event to be injected.
Table 24-13 describes the field.
Table 24-13. Format of the VM-Entry Interruption-Information Field
Bit Position(s)
Content
7:0
Vector of interrupt or exception
10:8
Interruption type:
0: External interrupt
1: Reserved
2: Non-maskable interrupt (NMI)
3: Hardware exception
4: Software interrupt
5: Privileged software exception
6: Software exception
7: Other event
11
Deliver error code (0 = do not deliver; 1 = deliver)
30:12
Reserved
31
Valid
— The vector (bits 7:0) determines which entry in the IDT is used or which other event is injected.
— The interruption type (bits 10:8) determines details of how the injection is performed. In general, a VMM
should use the type hardware exception for all exceptions other than breakpoint exceptions (#BP;
generated by INT3) and overflow exceptions (#OF; generated by INTO); it should use the type software
exception for #BP and #OF. The type other event is used for injection of events that are not delivered
through the IDT.
— For exceptions, the deliver-error-code bit (bit 11) determines whether delivery pushes an error code on
the guest stack.
— VM entry injects an event if and only if the valid bit (bit 31) is 1. The valid bit in this field is cleared on
every VM exit (see Section 27.2).
•
VM-entry exception error code (32 bits). This field is used if and only if the valid bit (bit 31) and the delivererror-code bit (bit 11) are both set in the VM-entry interruption-information field.
•
VM-entry instruction length (32 bits). For injection of events whose type is software interrupt, software
exception, or privileged software exception, this field is used to determine the value of RIP that is pushed on
the stack.
See Section 26.5 for details regarding the mechanics of event injection, including the use of the interruption type
and the VM-entry instruction length.
VM exits clear the valid bit (bit 31) in the VM-entry interruption-information field.
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24.9
VM-EXIT INFORMATION FIELDS
The VMCS contains a section of fields that contain information about the most recent VM exit.
On some processors, attempts to write to these fields with VMWRITE fail (see “VMWRITE—Write Field to VirtualMachine Control Structure” in Chapter 30).1
24.9.1
Basic VM-Exit Information
The following VM-exit information fields provide basic information about a VM exit:
•
Exit reason (32 bits). This field encodes the reason for the VM exit and has the structure given in Table 24-14.
Table 24-14. Format of Exit Reason
Bit Position(s)
Contents
15:0
Basic exit reason
26:16
Reserved (cleared to 0)
27
A VM exit saves this bit as 1 to indicate that the VM exit was incident to enclave mode.
28
Pending MTF VM exit
29
VM exit from VMX root operation
30
Reserved (cleared to 0)
31
VM-entry failure (0 = true VM exit; 1 = VM-entry failure)
— Bits 15:0 provide basic information about the cause of the VM exit (if bit 31 is clear) or of the VM-entry
failure (if bit 31 is set). Appendix C enumerates the basic exit reasons.
— Bit 28 is set only by an SMM VM exit (see Section 34.15.2) that took priority over an MTF VM exit (see
Section 25.5.2) that would have occurred had the SMM VM exit not occurred. See Section 34.15.2.3.
— Bit 29 is set if and only if the processor was in VMX root operation at the time the VM exit occurred. This can
happen only for SMM VM exits. See Section 34.15.2.
— Because some VM-entry failures load processor state from the host-state area (see Section 26.7), software
must be able to distinguish such cases from true VM exits. Bit 31 is used for that purpose.
•
Exit qualification (64 bits; 32 bits on processors that do not support Intel 64 architecture). This field contains
additional information about the cause of VM exits due to the following: debug exceptions; page-fault
exceptions; start-up IPIs (SIPIs); task switches; INVEPT; INVLPG;INVVPID; LGDT; LIDT; LLDT; LTR; SGDT;
SIDT; SLDT; STR; VMCLEAR; VMPTRLD; VMPTRST; VMREAD; VMWRITE; VMXON; control-register accesses;
MOV DR; I/O instructions; and MWAIT. The format of the field depends on the cause of the VM exit. See Section
27.2.1 for details.
•
Guest-linear address (64 bits; 32 bits on processors that do not support Intel 64 architecture). This field is
used in the following cases:
— VM exits due to attempts to execute LMSW with a memory operand.
— VM exits due to attempts to execute INS or OUTS.
— VM exits due to system-management interrupts (SMIs) that arrive immediately after retirement of I/O
instructions.
— Certain VM exits due to EPT violations
See Section 27.2.1 and Section 34.15.2.3 for details of when and how this field is used.
1.
Software can discover whether these fields can be written by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6).
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VIRTUAL MACHINE CONTROL STRUCTURES
•
Guest-physical address (64 bits). This field is used VM exits due to EPT violations and EPT misconfigurations.
See Section 27.2.1 for details of when and how this field is used.
24.9.2
Information for VM Exits Due to Vectored Events
Event-specific information is provided for VM exits due to the following vectored events: exceptions (including
those generated by the instructions INT3, INTO, BOUND, and UD2); external interrupts that occur while the
“acknowledge interrupt on exit” VM-exit control is 1; and non-maskable interrupts (NMIs). This information is
provided in the following fields:
•
VM-exit interruption information (32 bits). This field receives basic information associated with the event
causing the VM exit. Table 24-15 describes this field.
Table 24-15. Format of the VM-Exit Interruption-Information Field
Bit Position(s)
Content
7:0
Vector of interrupt or exception
10:8
Interruption type:
0: External interrupt
1: Not used
2: Non-maskable interrupt (NMI)
3: Hardware exception
4 – 5: Not used
6: Software exception
7: Not used
11
Error code valid (0 = invalid; 1 = valid)
12
NMI unblocking due to IRET
30:13
Reserved (cleared to 0)
31
Valid
•
VM-exit interruption error code (32 bits). For VM exits caused by hardware exceptions that would have
delivered an error code on the stack, this field receives that error code.
Section 27.2.2 provides details of how these fields are saved on VM exits.
24.9.3
Information for VM Exits That Occur During Event Delivery
Additional information is provided for VM exits that occur during event delivery in VMX non-root operation.1 This
information is provided in the following fields:
•
IDT-vectoring information (32 bits). This field receives basic information associated with the event that was
being delivered when the VM exit occurred. Table 24-16 describes this field.
1. This includes cases in which the event delivery was caused by event injection as part of VM entry; see Section 26.5.1.2.
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VIRTUAL MACHINE CONTROL STRUCTURES
Table 24-16. Format of the IDT-Vectoring Information Field
Bit Position(s)
Content
7:0
Vector of interrupt or exception
10:8
Interruption type:
0: External interrupt
1: Not used
2: Non-maskable interrupt (NMI)
3: Hardware exception
4: Software interrupt
5: Privileged software exception
6: Software exception
7: Not used
11
Error code valid (0 = invalid; 1 = valid)
12
Undefined
30:13
Reserved (cleared to 0)
31
Valid
•
IDT-vectoring error code (32 bits). For VM exits the occur during delivery of hardware exceptions that would
have delivered an error code on the stack, this field receives that error code.
See Section 27.2.3 provides details of how these fields are saved on VM exits.
24.9.4
Information for VM Exits Due to Instruction Execution
The following fields are used for VM exits caused by attempts to execute certain instructions in VMX non-root operation:
•
VM-exit instruction length (32 bits). For VM exits resulting from instruction execution, this field receives the
length in bytes of the instruction whose execution led to the VM exit.1 See Section 27.2.4 for details of when
and how this field is used.
•
VM-exit instruction information (32 bits). This field is used for VM exits due to attempts to execute INS,
INVEPT, INVVPID, LIDT, LGDT, LLDT, LTR, OUTS, SIDT, SGDT, SLDT, STR, VMCLEAR, VMPTRLD, VMPTRST,
VMREAD, VMWRITE, or VMXON.2 The format of the field depends on the cause of the VM exit. See Section
27.2.4 for details.
The following fields (64 bits each; 32 bits on processors that do not support Intel 64 architecture) are used only for
VM exits due to SMIs that arrive immediately after retirement of I/O instructions. They provide information about
that I/O instruction:
•
•
•
•
I/O RCX. The value of RCX before the I/O instruction started.
I/O RSI. The value of RSI before the I/O instruction started.
I/O RDI. The value of RDI before the I/O instruction started.
I/O RIP. The value of RIP before the I/O instruction started (the RIP that addressed the I/O instruction).
24.9.5
VM-Instruction Error Field
The 32-bit VM-instruction error field does not provide information about the most recent VM exit. In fact, it is
not modified on VM exits. Instead, it provides information about errors encountered by a non-faulting execution of
one of the VMX instructions.
1. This field is also used for VM exits that occur during the delivery of a software interrupt or software exception.
2. Whether the processor provides this information on VM exits due to attempts to execute INS or OUTS can be determined by consulting the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1).
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VIRTUAL MACHINE CONTROL STRUCTURES
24.10
VMCS TYPES: ORDINARY AND SHADOW
Every VMCS is either an ordinary VMCS or a shadow VMCS. A VMCS’s type is determined by the shadow-VMCS
indicator in the VMCS region (this is the value of bit 31 of the first 4 bytes of the VMCS region; see Table 24-1): 0
indicates an ordinary VMCS, while 1 indicates a shadow VMCS. Shadow VMCSs are supported only on processors
that support the 1-setting of the “VMCS shadowing” VM-execution control (see Section 24.6.2).
A shadow VMCS differs from an ordinary VMCS in two ways:
•
An ordinary VMCS can be used for VM entry but a shadow VMCS cannot. Attempts to perform VM entry when
the current VMCS is a shadow VMCS fail (see Section 26.1).
•
The VMREAD and VMWRITE instructions can be used in VMX non-root operation to access a shadow VMCS but
not an ordinary VMCS. This fact results from the following:
— If the “VMCS shadowing” VM-execution control is 0, execution of the VMREAD and VMWRITE instructions in
VMX non-root operation always cause VM exits (see Section 25.1.3).
— If the “VMCS shadowing” VM-execution control is 1, execution of the VMREAD and VMWRITE instructions in
VMX non-root operation can access the VMCS referenced by the VMCS link pointer (see Section 30.3).
— If the “VMCS shadowing” VM-execution control is 1, VM entry ensures that any VMCS referenced by the
VMCS link pointer is a shadow VMCS (see Section 26.3.1.5).
In VMX root operation, both types of VMCSs can be accessed with the VMREAD and VMWRITE instructions.
Software should not modify the shadow-VMCS indicator in the VMCS region of a VMCS that is active. Doing so may
cause the VMCS to become corrupted (see Section 24.11.1). Before modifying the shadow-VMCS indicator, software should execute VMCLEAR for the VMCS to ensure that it is not active.
24.11
SOFTWARE USE OF THE VMCS AND RELATED STRUCTURES
This section details guidelines that software should observe when using a VMCS and related structures. It also
provides descriptions of consequences for failing to follow guidelines.
24.11.1 Software Use of Virtual-Machine Control Structures
To ensure proper processor behavior, software should observe certain guidelines when using an active VMCS.
No VMCS should ever be active on more than one logical processor. If a VMCS is to be “migrated” from one logical
processor to another, the first logical processor should execute VMCLEAR for the VMCS (to make it inactive on that
logical processor and to ensure that all VMCS data are in memory) before the other logical processor executes
VMPTRLD for the VMCS (to make it active on the second logical processor).1 A VMCS that is made active on more
than one logical processor may become corrupted (see below).
Software should not modify the shadow-VMCS indicator (see Table 24-1) in the VMCS region of a VMCS that is
active. Doing so may cause the VMCS to become corrupted. Before modifying the shadow-VMCS indicator, software
should execute VMCLEAR for the VMCS to ensure that it is not active.
Software should use the VMREAD and VMWRITE instructions to access the different fields in the current VMCS (see
Section 24.11.2). Software should never access or modify the VMCS data of an active VMCS using ordinary
memory operations, in part because the format used to store the VMCS data is implementation-specific and not
architecturally defined, and also because a logical processor may maintain some VMCS data of an active VMCS on
the processor and not in the VMCS region. The following items detail some of the hazards of accessing VMCS data
using ordinary memory operations:
•
Any data read from a VMCS with an ordinary memory read does not reliably reflect the state of the VMCS.
Results may vary from time to time or from logical processor to logical processor.
1. As noted in Section 24.1, execution of the VMPTRLD instruction makes a VMCS is active. In addition, VM entry makes active any
shadow VMCS referenced by the VMCS link pointer in the current VMCS. If a shadow VMCS is made active by VM entry, it is necessary to execute VMCLEAR for that VMCS before allowing that VMCS to become active on another logical processor.
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VIRTUAL MACHINE CONTROL STRUCTURES
•
Writing to a VMCS with an ordinary memory write is not guaranteed to have a deterministic effect on the VMCS.
Doing so may cause the VMCS to become corrupted (see below).
(Software can avoid these hazards by removing any linear-address mappings to a VMCS region before executing a
VMPTRLD for that region and by not remapping it until after executing VMCLEAR for that region.)
If a logical processor leaves VMX operation, any VMCSs active on that logical processor may be corrupted (see
below). To prevent such corruption of a VMCS that may be used either after a return to VMX operation or on
another logical processor, software should execute VMCLEAR for that VMCS before executing the VMXOFF instruction or removing power from the processor (e.g., as part of a transition to the S3 and S4 power states).
This section has identified operations that may cause a VMCS to become corrupted. These operations may cause
the VMCS’s data to become undefined. Behavior may be unpredictable if that VMCS used subsequently on any
logical processor. The following items detail some hazards of VMCS corruption:
•
•
VM entries may fail for unexplained reasons or may load undesired processor state.
•
VM exits may load undesired processor state, save incorrect state into the VMCS, or cause the logical processor
to transition to a shutdown state.
The processor may not correctly support VMX non-root operation as documented in Chapter 27 and may
generate unexpected VM exits.
24.11.2 VMREAD, VMWRITE, and Encodings of VMCS Fields
Every field of the VMCS is associated with a 32-bit value that is its encoding. The encoding is provided in an
operand to VMREAD and VMWRITE when software wishes to read or write that field. These instructions fail if given,
in 64-bit mode, an operand that sets an encoding bit beyond bit 32. See Chapter 30 for a description of these
instructions.
The structure of the 32-bit encodings of the VMCS components is determined principally by the width of the fields
and their function in the VMCS. See Table 24-17.
Table 24-17. Structure of VMCS Component Encoding
Bit Position(s)
Contents
0
Access type (0 = full; 1 = high); must be full for 16-bit, 32-bit, and natural-width fields
9:1
Index
11:10
Type:
0: control
1: VM-exit information
2: guest state
3: host state
12
Reserved (must be 0)
14:13
Width:
0: 16-bit
1: 64-bit
2: 32-bit
3: natural-width
31:15
Reserved (must be 0)
The following items detail the meaning of the bits in each encoding:
•
Field width. Bits 14:13 encode the width of the field.
— A value of 0 indicates a 16-bit field.
— A value of 1 indicates a 64-bit field.
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VIRTUAL MACHINE CONTROL STRUCTURES
— A value of 2 indicates a 32-bit field.
— A value of 3 indicates a natural-width field. Such fields have 64 bits on processors that support Intel 64
architecture and 32 bits on processors that do not.
Fields whose encodings use value 1 are specially treated to allow 32-bit software access to all 64 bits of the
field. Such access is allowed by defining, for each such field, an encoding that allows direct access to the high
32 bits of the field. See below.
•
Field type. Bits 11:10 encode the type of VMCS field: control, guest-state, host-state, or VM-exit information.
(The last category also includes the VM-instruction error field.)
•
•
Index. Bits 9:1 distinguish components with the same field width and type.
Access type. Bit 0 must be 0 for all fields except for 64-bit fields (those with field-width 1; see above). A
VMREAD or VMWRITE using an encoding with this bit cleared to 0 accesses the entire field. For a 64-bit field
with field-width 1, a VMREAD or VMWRITE using an encoding with this bit set to 1 accesses only the high 32 bits
of the field.
Appendix B gives the encodings of all fields in the VMCS.
The following describes the operation of VMREAD and VMWRITE based on processor mode, VMCS-field width, and
access type:
•
16-bit fields:
— A VMREAD returns the value of the field in bits 15:0 of the destination operand; other bits of the destination
operand are cleared to 0.
— A VMWRITE writes the value of bits 15:0 of the source operand into the VMCS field; other bits of the source
operand are not used.
•
32-bit fields:
— A VMREAD returns the value of the field in bits 31:0 of the destination operand; in 64-bit mode, bits 63:32
of the destination operand are cleared to 0.
— A VMWRITE writes the value of bits 31:0 of the source operand into the VMCS field; in 64-bit mode,
bits 63:32 of the source operand are not used.
•
64-bit fields and natural-width fields using the full access type outside IA-32e mode.
— A VMREAD returns the value of bits 31:0 of the field in its destination operand; bits 63:32 of the field are
ignored.
— A VMWRITE writes the value of its source operand to bits 31:0 of the field and clears bits 63:32 of the field.
•
64-bit fields and natural-width fields using the full access type in 64-bit mode (only on processors that support
Intel 64 architecture).
— A VMREAD returns the value of the field in bits 63:0 of the destination operand
— A VMWRITE writes the value of bits 63:0 of the source operand into the VMCS field.
•
64-bit fields using the high access type.
— A VMREAD returns the value of bits 63:32 of the field in bits 31:0 of the destination operand; in 64-bit
mode, bits 63:32 of the destination operand are cleared to 0.
— A VMWRITE writes the value of bits 31:0 of the source operand to bits 63:32 of the field; in 64-bit mode,
bits 63:32 of the source operand are not used.
Software seeking to read a 64-bit field outside IA-32e mode can use VMREAD with the full access type (reading
bits 31:0 of the field) and VMREAD with the high access type (reading bits 63:32 of the field); the order of the two
VMREAD executions is not important. Software seeking to modify a 64-bit field outside IA-32e mode should first
use VMWRITE with the full access type (establishing bits 31:0 of the field while clearing bits 63:32) and then use
VMWRITE with the high access type (establishing bits 63:32 of the field).
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VIRTUAL MACHINE CONTROL STRUCTURES
24.11.3 Initializing a VMCS
Software should initialize fields in a VMCS (using VMWRITE) before using the VMCS for VM entry. Failure to do so
may result in unpredictable behavior; for example, a VM entry may fail for unexplained reasons, or a successful
transition (VM entry or VM exit) may load processor state with unexpected values.
It is not necessary to initialize fields that the logical processor will not use. (For example, it is not necessary to
unitize the MSR-bitmap address if the “use MSR bitmaps” VM-execution control is 0.)
A processor maintains some VMCS information that cannot be modified with the VMWRITE instruction; this
includes a VMCS’s launch state (see Section 24.1). Such information may be stored in the VMCS data portion of a
VMCS region. Because the format of this information is implementation-specific, there is no way for software to
know, when it first allocates a region of memory for use as a VMCS region, how the processor will determine this
information from the contents of the memory region.
In addition to its other functions, the VMCLEAR instruction initializes any implementation-specific information in
the VMCS region referenced by its operand. To avoid the uncertainties of implementation-specific behavior, software should execute VMCLEAR on a VMCS region before making the corresponding VMCS active with VMPTRLD for
the first time. (Figure 24-1 illustrates how execution of VMCLEAR puts a VMCS into a well-defined state.)
The following software usage is consistent with these limitations:
•
•
VMCLEAR should be executed for a VMCS before it is used for VM entry for the first time.
•
VMRESUME should be used for any subsequent VM entry using a VMCS (until the next execution of VMCLEAR
for the VMCS).
VMLAUNCH should be used for the first VM entry using a VMCS after VMCLEAR has been executed for that
VMCS.
It is expected that, in general, VMRESUME will have lower latency than VMLAUNCH. Since “migrating” a VMCS from
one logical processor to another requires use of VMCLEAR (see Section 24.11.1), which sets the launch state of the
VMCS to “clear”, such migration requires the next VM entry to be performed using VMLAUNCH. Software developers can avoid the performance cost of increased VM-entry latency by avoiding unnecessary migration of a VMCS
from one logical processor to another.
24.11.4 Software Access to Related Structures
In addition to data in the VMCS region itself, VMX non-root operation can be controlled by data structures that are
referenced by pointers in a VMCS (for example, the I/O bitmaps). While the pointers to these data structures are
parts of the VMCS, the data structures themselves are not. They are not accessible using VMREAD and VMWRITE
but by ordinary memory writes.
Software should ensure that each such data structure is modified only when no logical processor with a current
VMCS that references it is in VMX non-root operation. Doing otherwise may lead to unpredictable behavior
(including behaviors identified in Section 24.11.1).
24.11.5 VMXON Region
Before executing VMXON, software allocates a region of memory (called the VMXON region)1 that the logical
processor uses to support VMX operation. The physical address of this region (the VMXON pointer) is provided in
an operand to VMXON. The VMXON pointer is subject to the limitations that apply to VMCS pointers:
•
•
The VMXON pointer must be 4-KByte aligned (bits 11:0 must be zero).
The VMXON pointer must not set any bits beyond the processor’s physical-address width.2,3
1. The amount of memory required for the VMXON region is the same as that required for a VMCS region. This size is implementation
specific and can be determined by consulting the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1).
2. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
3. If IA32_VMX_BASIC[48] is read as 1, the VMXON pointer must not set any bits in the range 63:32; see Appendix A.1.
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VIRTUAL MACHINE CONTROL STRUCTURES
Before executing VMXON, software should write the VMCS revision identifier (see Section 24.2) to the VMXON
region. (Specifically, it should write the 31-bit VMCS revision identifier to bits 30:0 of the first 4 bytes of the VMXON
region; bit 31 should be cleared to 0.) It need not initialize the VMXON region in any other way. Software should
use a separate region for each logical processor and should not access or modify the VMXON region of a logical
processor between execution of VMXON and VMXOFF on that logical processor. Doing otherwise may lead to unpredictable behavior (including behaviors identified in Section 24.11.1).
24-28 Vol. 3C
CHAPTER 25
VMX NON-ROOT OPERATION
In a virtualized environment using VMX, the guest software stack typically runs on a logical processor in VMX nonroot operation. This mode of operation is similar to that of ordinary processor operation outside of the virtualized
environment. This chapter describes the differences between VMX non-root operation and ordinary processor operation with special attention to causes of VM exits (which bring a logical processor from VMX non-root operation to
root operation). The differences between VMX non-root operation and ordinary processor operation are described
in the following sections:
•
•
•
•
•
•
Section 25.1, “Instructions That Cause VM Exits”
Section 25.2, “Other Causes of VM Exits”
Section 25.3, “Changes to Instruction Behavior in VMX Non-Root Operation”
Section 25.4, “Other Changes in VMX Non-Root Operation”
Section 25.5, “Features Specific to VMX Non-Root Operation”
Section 25.6, “Unrestricted Guests”
Chapter 26, “VM Entries,” describes the data control structures that govern VMX non-root operation. Chapter 26,
“VM Entries,” describes the operation of VM entries by which the processor transitions from VMX root operation to
VMX non-root operation. Chapter 25, “VMX Non-Root Operation,” describes the operation of VM exits by which the
processor transitions from VMX non-root operation to VMX root operation.
Chapter 28, “VMX Support for Address Translation,” describes two features that support address translation in VMX
non-root operation. Chapter 29, “APIC Virtualization and Virtual Interrupts,” describes features that support virtualization of interrupts and the Advanced Programmable Interrupt Controller (APIC) in VMX non-root operation.
25.1
INSTRUCTIONS THAT CAUSE VM EXITS
Certain instructions may cause VM exits if executed in VMX non-root operation. Unless otherwise specified, such
VM exits are “fault-like,” meaning that the instruction causing the VM exit does not execute and no processor state
is updated by the instruction. Section 27.1 details architectural state in the context of a VM exit.
Section 25.1.1 defines the prioritization between faults and VM exits for instructions subject to both. Section
25.1.2 identifies instructions that cause VM exits whenever they are executed in VMX non-root operation (and thus
can never be executed in VMX non-root operation). Section 25.1.3 identifies instructions that cause VM exits
depending on the settings of certain VM-execution control fields (see Section 24.6).
25.1.1
Relative Priority of Faults and VM Exits
The following principles describe the ordering between existing faults and VM exits:
•
Certain exceptions have priority over VM exits. These include invalid-opcode exceptions, faults based on
privilege level,1 and general-protection exceptions that are based on checking I/O permission bits in the taskstate segment (TSS). For example, execution of RDMSR with CPL = 3 generates a general-protection exception
and not a VM exit.2
•
Faults incurred while fetching instruction operands have priority over VM exits that are conditioned based on
the contents of those operands (see LMSW in Section 25.1.3).
•
VM exits caused by execution of the INS and OUTS instructions (resulting either because the “unconditional I/O
exiting” VM-execution control is 1 or because the “use I/O bitmaps control is 1) have priority over the following
faults:
1. These include faults generated by attempts to execute, in virtual-8086 mode, privileged instructions that are not recognized in that
mode.
2. MOV DR is an exception to this rule; see Section 25.1.3.
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VMX NON-ROOT OPERATION
— A general-protection fault due to the relevant segment (ES for INS; DS for OUTS unless overridden by an
instruction prefix) being unusable
— A general-protection fault due to an offset beyond the limit of the relevant segment
— An alignment-check exception
•
Fault-like VM exits have priority over exceptions other than those mentioned above. For example, RDMSR of a
non-existent MSR with CPL = 0 generates a VM exit and not a general-protection exception.
When Section 25.1.2 or Section 25.1.3 (below) identify an instruction execution that may lead to a VM exit, it is
assumed that the instruction does not incur a fault that takes priority over a VM exit.
25.1.2
Instructions That Cause VM Exits Unconditionally
The following instructions cause VM exits when they are executed in VMX non-root operation: CPUID, GETSEC,1
INVD, and XSETBV. This is also true of instructions introduced with VMX, which include: INVEPT, INVVPID,
VMCALL,2 VMCLEAR, VMLAUNCH, VMPTRLD, VMPTRST, VMRESUME, VMXOFF, and VMXON.
25.1.3
Instructions That Cause VM Exits Conditionally
Certain instructions cause VM exits in VMX non-root operation depending on the setting of the VM-execution
controls. The following instructions can cause “fault-like” VM exits based on the conditions described:3
•
CLTS. The CLTS instruction causes a VM exit if the bits in position 3 (corresponding to CR0.TS) are set in both
the CR0 guest/host mask and the CR0 read shadow.
•
ENCLS. The ENCLS instruction causes a VM exit if the “enable ENCLS exiting” VM-execution control is 1 and
one of the following is true:
— The value of EAX is less than 63 and the corresponding bit in the ENCLS-exiting bitmap is 1 (see Section
24.6.16).
— The value of EAX is greater than or equal to 63 and bit 63 in the ENCLS-exiting bitmap is 1.
•
•
HLT. The HLT instruction causes a VM exit if the “HLT exiting” VM-execution control is 1.
IN, INS/INSB/INSW/INSD, OUT, OUTS/OUTSB/OUTSW/OUTSD. The behavior of each of these instructions is determined by the settings of the “unconditional I/O exiting” and “use I/O bitmaps” VM-execution
controls:
— If both controls are 0, the instruction executes normally.
— If the “unconditional I/O exiting” VM-execution control is 1 and the “use I/O bitmaps” VM-execution control
is 0, the instruction causes a VM exit.
— If the “use I/O bitmaps” VM-execution control is 1, the instruction causes a VM exit if it attempts to access
an I/O port corresponding to a bit set to 1 in the appropriate I/O bitmap (see Section 24.6.4). If an I/O
operation “wraps around” the 16-bit I/O-port space (accesses ports FFFFH and 0000H), the I/O instruction
causes a VM exit (the “unconditional I/O exiting” VM-execution control is ignored if the “use I/O bitmaps”
VM-execution control is 1).
See Section 25.1.1 for information regarding the priority of VM exits relative to faults that may be caused by
the INS and OUTS instructions.
•
•
INVLPG. The INVLPG instruction causes a VM exit if the “INVLPG exiting” VM-execution control is 1.
INVPCID. The INVPCID instruction causes a VM exit if the “INVLPG exiting” and “enable INVPCID”
VM-execution controls are both 1.
1. An execution of GETSEC in VMX non-root operation causes a VM exit if CR4.SMXE[Bit 14] = 1 regardless of the value of CPL or RAX.
An execution of GETSEC causes an invalid-opcode exception (#UD) if CR4.SMXE[Bit 14] = 0.
2. Under the dual-monitor treatment of SMIs and SMM, executions of VMCALL cause SMM VM exits in VMX root operation outside SMM.
See Section 34.15.2.
3. Many of the items in this section refer to secondary processor-based VM-execution controls. If bit 31 of the primary processorbased VM-execution controls is 0, VMX non-root operation functions as if these controls were all 0. See Section 24.6.2.
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VMX NON-ROOT OPERATION
•
LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, STR. These instructions cause VM exits if the “descriptor-table
exiting” VM-execution control is 1.
•
LMSW. In general, the LMSW instruction causes a VM exit if it would write, for any bit set in the low 4 bits of
the CR0 guest/host mask, a value different than the corresponding bit in the CR0 read shadow. LMSW never
clears bit 0 of CR0 (CR0.PE); thus, LMSW causes a VM exit if either of the following are true:
— The bits in position 0 (corresponding to CR0.PE) are set in both the CR0 guest/mask and the source
operand, and the bit in position 0 is clear in the CR0 read shadow.
— For any bit position in the range 3:1, the bit in that position is set in the CR0 guest/mask and the values of
the corresponding bits in the source operand and the CR0 read shadow differ.
•
•
MONITOR. The MONITOR instruction causes a VM exit if the “MONITOR exiting” VM-execution control is 1.
•
MOV from CR8. The MOV from CR8 instruction causes a VM exit if the “CR8-store exiting” VM-execution
control is 1.
•
MOV to CR0. The MOV to CR0 instruction causes a VM exit unless the value of its source operand matches, for
the position of each bit set in the CR0 guest/host mask, the corresponding bit in the CR0 read shadow. (If every
bit is clear in the CR0 guest/host mask, MOV to CR0 cannot cause a VM exit.)
•
MOV to CR3. The MOV to CR3 instruction causes a VM exit unless the “CR3-load exiting” VM-execution control
is 0 or the value of its source operand is equal to one of the CR3-target values specified in the VMCS. If the
CR3-target count in n, only the first n CR3-target values are considered; if the CR3-target count is 0, MOV to
CR3 always causes a VM exit.
MOV from CR3. The MOV from CR3 instruction causes a VM exit if the “CR3-store exiting” VM-execution
control is 1. The first processors to support the virtual-machine extensions supported only the 1-setting of this
control.
The first processors to support the virtual-machine extensions supported only the 1-setting of the “CR3-load
exiting” VM-execution control. These processors always consult the CR3-target controls to determine whether
an execution of MOV to CR3 causes a VM exit.
•
MOV to CR4. The MOV to CR4 instruction causes a VM exit unless the value of its source operand matches, for
the position of each bit set in the CR4 guest/host mask, the corresponding bit in the CR4 read shadow.
•
•
MOV to CR8. The MOV to CR8 instruction causes a VM exit if the “CR8-load exiting” VM-execution control is 1.
•
MWAIT. The MWAIT instruction causes a VM exit if the “MWAIT exiting” VM-execution control is 1. If this
control is 0, the behavior of the MWAIT instruction may be modified (see Section 25.3).
•
PAUSE. The behavior of each of this instruction depends on CPL and the settings of the “PAUSE exiting” and
“PAUSE-loop exiting” VM-execution controls:
MOV DR. The MOV DR instruction causes a VM exit if the “MOV-DR exiting” VM-execution control is 1. Such
VM exits represent an exception to the principles identified in Section 25.1.1 in that they take priority over the
following: general-protection exceptions based on privilege level; and invalid-opcode exceptions that occur
because CR4.DE=1 and the instruction specified access to DR4 or DR5.
— CPL = 0.
•
If the “PAUSE exiting” and “PAUSE-loop exiting” VM-execution controls are both 0, the PAUSE
instruction executes normally.
•
If the “PAUSE exiting” VM-execution control is 1, the PAUSE instruction causes a VM exit (the “PAUSEloop exiting” VM-execution control is ignored if CPL = 0 and the “PAUSE exiting” VM-execution control
is 1).
•
If the “PAUSE exiting” VM-execution control is 0 and the “PAUSE-loop exiting” VM-execution control is
1, the following treatment applies.
The processor determines the amount of time between this execution of PAUSE and the previous
execution of PAUSE at CPL 0. If this amount of time exceeds the value of the VM-execution control field
PLE_Gap, the processor considers this execution to be the first execution of PAUSE in a loop. (It also
does so for the first execution of PAUSE at CPL 0 after VM entry.)
Otherwise, the processor determines the amount of time since the most recent execution of PAUSE that
was considered to be the first in a loop. If this amount of time exceeds the value of the VM-execution
control field PLE_Window, a VM exit occurs.
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VMX NON-ROOT OPERATION
For purposes of these computations, time is measured based on a counter that runs at the same rate as
the timestamp counter (TSC).
— CPL > 0.
•
•
If the “PAUSE exiting” VM-execution control is 0, the PAUSE instruction executes normally.
If the “PAUSE exiting” VM-execution control is 1, the PAUSE instruction causes a VM exit.
The “PAUSE-loop exiting” VM-execution control is ignored if CPL > 0.
•
RDMSR. The RDMSR instruction causes a VM exit if any of the following are true:
— The “use MSR bitmaps” VM-execution control is 0.
— The value of ECX is not in the ranges 00000000H – 00001FFFH and C0000000H – C0001FFFH.
— The value of ECX is in the range 00000000H – 00001FFFH and bit n in read bitmap for low MSRs is 1, where
n is the value of ECX.
— The value of ECX is in the range C0000000H – C0001FFFH and bit n in read bitmap for high MSRs is 1,
where n is the value of ECX & 00001FFFH.
See Section 24.6.9 for details regarding how these bitmaps are identified.
•
•
•
•
•
RDPMC. The RDPMC instruction causes a VM exit if the “RDPMC exiting” VM-execution control is 1.
•
•
RSM. The RSM instruction causes a VM exit if executed in system-management mode (SMM).1
RDRAND. The RDRAND instruction causes a VM exit if the “RDRAND exiting” VM-execution control is 1.
RDSEED. The RDSEED instruction causes a VM exit if the “RDSEED exiting” VM-execution control is 1.
RDTSC. The RDTSC instruction causes a VM exit if the “RDTSC exiting” VM-execution control is 1.
RDTSCP. The RDTSCP instruction causes a VM exit if the “RDTSC exiting” and “enable RDTSCP” VM-execution
controls are both 1.
VMREAD. The VMREAD instruction causes a VM exit if any of the following are true:
— The “VMCS shadowing” VM-execution control is 0.
— Bits 63:15 (bits 31:15 outside 64-bit mode) of the register source operand are not all 0.
— Bit n in VMREAD bitmap is 1, where n is the value of bits 14:0 of the register source operand. See Section
24.6.15 for details regarding how the VMREAD bitmap is identified.
If the VMREAD instruction does not cause a VM exit, it reads from the VMCS referenced by the VMCS link
pointer. See Chapter 30, “VMREAD—Read Field from Virtual-Machine Control Structure” for details of the
operation of the VMREAD instruction.
•
VMWRITE. The VMWRITE instruction causes a VM exit if any of the following are true:
— The “VMCS shadowing” VM-execution control is 0.
— Bits 63:15 (bits 31:15 outside 64-bit mode) of the register source operand are not all 0.
— Bit n in VMWRITE bitmap is 1, where n is the value of bits 14:0 of the register source operand. See Section
24.6.15 for details regarding how the VMWRITE bitmap is identified.
If the VMWRITE instruction does not cause a VM exit, it writes to the VMCS referenced by the VMCS link
pointer. See Chapter 30, “VMWRITE—Write Field to Virtual-Machine Control Structure” for details of the
operation of the VMWRITE instruction.
•
•
WBINVD. The WBINVD instruction causes a VM exit if the “WBINVD exiting” VM-execution control is 1.
WRMSR. The WRMSR instruction causes a VM exit if any of the following are true:
— The “use MSR bitmaps” VM-execution control is 0.
— The value of ECX is not in the ranges 00000000H – 00001FFFH and C0000000H – C0001FFFH.
— The value of ECX is in the range 00000000H – 00001FFFH and bit n in write bitmap for low MSRs is 1,
where n is the value of ECX.
1. Execution of the RSM instruction outside SMM causes an invalid-opcode exception regardless of whether the processor is in VMX
operation. It also does so in VMX root operation in SMM; see Section 34.15.3.
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VMX NON-ROOT OPERATION
— The value of ECX is in the range C0000000H – C0001FFFH and bit n in write bitmap for high MSRs is 1,
where n is the value of ECX & 00001FFFH.
See Section 24.6.9 for details regarding how these bitmaps are identified.
•
XRSTORS. The XRSTORS instruction causes a VM exit if the “enable XSAVES/XRSTORS” VM-execution control
is 1and any bit is set in the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the
XSS-exiting bitmap (see Section 24.6.19).
•
XSAVES. The XSAVES instruction causes a VM exit if the “enable XSAVES/XRSTORS” VM-execution control is
1 and any bit is set in the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the XSSexiting bitmap (see Section 24.6.19).
25.2
OTHER CAUSES OF VM EXITS
In addition to VM exits caused by instruction execution, the following events can cause VM exits:
•
Exceptions. Exceptions (faults, traps, and aborts) cause VM exits based on the exception bitmap (see Section
24.6.3). If an exception occurs, its vector (in the range 0–31) is used to select a bit in the exception bitmap. If
the bit is 1, a VM exit occurs; if the bit is 0, the exception is delivered normally through the guest IDT. This use
of the exception bitmap applies also to exceptions generated by the instructions INT3, INTO, BOUND, and UD2.
Page faults (exceptions with vector 14) are specially treated. When a page fault occurs, a processor consults
(1) bit 14 of the exception bitmap; (2) the error code produced with the page fault [PFEC]; (3) the page-fault
error-code mask field [PFEC_MASK]; and (4) the page-fault error-code match field [PFEC_MATCH]. It checks if
PFEC & PFEC_MASK = PFEC_MATCH. If there is equality, the specification of bit 14 in the exception bitmap is
followed (for example, a VM exit occurs if that bit is set). If there is inequality, the meaning of that bit is
reversed (for example, a VM exit occurs if that bit is clear).
Thus, if software desires VM exits on all page faults, it can set bit 14 in the exception bitmap to 1 and set the
page-fault error-code mask and match fields each to 00000000H. If software desires VM exits on no page
faults, it can set bit 14 in the exception bitmap to 1, the page-fault error-code mask field to 00000000H, and
the page-fault error-code match field to FFFFFFFFH.
•
Triple fault. A VM exit occurs if the logical processor encounters an exception while attempting to call the
double-fault handler and that exception itself does not cause a VM exit due to the exception bitmap. This
applies to the case in which the double-fault exception was generated within VMX non-root operation, the case
in which the double-fault exception was generated during event injection by VM entry, and to the case in which
VM entry is injecting a double-fault exception.
•
External interrupts. An external interrupt causes a VM exit if the “external-interrupt exiting” VM-execution
control is 1. (See Section 25.6 for an exception.) Otherwise, the interrupt is delivered normally through the
IDT. (If a logical processor is in the shutdown state or the wait-for-SIPI state, external interrupts are blocked.
The interrupt is not delivered through the IDT and no VM exit occurs.)
•
Non-maskable interrupts (NMIs). An NMI causes a VM exit if the “NMI exiting” VM-execution control is 1.
Otherwise, it is delivered using descriptor 2 of the IDT. (If a logical processor is in the wait-for-SIPI state, NMIs
are blocked. The NMI is not delivered through the IDT and no VM exit occurs.)
•
INIT signals. INIT signals cause VM exits. A logical processor performs none of the operations normally
associated with these events. Such exits do not modify register state or clear pending events as they would
outside of VMX operation. (If a logical processor is in the wait-for-SIPI state, INIT signals are blocked. They do
not cause VM exits in this case.)
•
Start-up IPIs (SIPIs). SIPIs cause VM exits. If a logical processor is not in the wait-for-SIPI activity state
when a SIPI arrives, no VM exit occurs and the SIPI is discarded. VM exits due to SIPIs do not perform any of
the normal operations associated with those events: they do not modify register state as they would outside of
VMX operation. (If a logical processor is not in the wait-for-SIPI state, SIPIs are blocked. They do not cause
VM exits in this case.)
•
Task switches. Task switches are not allowed in VMX non-root operation. Any attempt to effect a task switch
in VMX non-root operation causes a VM exit. See Section 25.4.2.
•
System-management interrupts (SMIs). If the logical processor is using the dual-monitor treatment of
SMIs and system-management mode (SMM), SMIs cause SMM VM exits. See Section 34.15.2.1
Vol. 3C 25-5
VMX NON-ROOT OPERATION
•
VMX-preemption timer. A VM exit occurs when the timer counts down to zero. See Section 25.5.1 for details
of operation of the VMX-preemption timer.
Debug-trap exceptions and higher priority events take priority over VM exits caused by the VMX-preemption
timer. VM exits caused by the VMX-preemption timer take priority over VM exits caused by the “NMI-window
exiting” VM-execution control and lower priority events.
These VM exits wake a logical processor from the same inactive states as would a non-maskable interrupt.
Specifically, they wake a logical processor from the shutdown state and from the states entered using the HLT
and MWAIT instructions. These VM exits do not occur if the logical processor is in the wait-for-SIPI state.
In addition, there are controls that cause VM exits based on the readiness of guest software to receive interrupts:
•
If the “interrupt-window exiting” VM-execution control is 1, a VM exit occurs before execution of any instruction
if RFLAGS.IF = 1 and there is no blocking of events by STI or by MOV SS (see Table 24-3). Such a VM exit
occurs immediately after VM entry if the above conditions are true (see Section 26.6.5).
Non-maskable interrupts (NMIs) and higher priority events take priority over VM exits caused by this control.
VM exits caused by this control take priority over external interrupts and lower priority events.
These VM exits wake a logical processor from the same inactive states as would an external interrupt. Specifically, they wake a logical processor from the states entered using the HLT and MWAIT instructions. These
VM exits do not occur if the logical processor is in the shutdown state or the wait-for-SIPI state.
•
If the “NMI-window exiting” VM-execution control is 1, a VM exit occurs before execution of any instruction if
there is no virtual-NMI blocking and there is no blocking of events by MOV SS (see Table 24-3). (A logical
processor may also prevent such a VM exit if there is blocking of events by STI.) Such a VM exit occurs
immediately after VM entry if the above conditions are true (see Section 26.6.6).
VM exits caused by the VMX-preemption timer and higher priority events take priority over VM exits caused by
this control. VM exits caused by this control take priority over non-maskable interrupts (NMIs) and lower
priority events.
These VM exits wake a logical processor from the same inactive states as would an NMI. Specifically, they wake
a logical processor from the shutdown state and from the states entered using the HLT and MWAIT instructions.
These VM exits do not occur if the logical processor is in the wait-for-SIPI state.
25.3
CHANGES TO INSTRUCTION BEHAVIOR IN VMX NON-ROOT OPERATION
The behavior of some instructions is changed in VMX non-root operation. Some of these changes are determined
by the settings of certain VM-execution control fields. The following items detail such changes:1
•
CLTS. Behavior of the CLTS instruction is determined by the bits in position 3 (corresponding to CR0.TS) in the
CR0 guest/host mask and the CR0 read shadow:
— If bit 3 in the CR0 guest/host mask is 0, CLTS clears CR0.TS normally (the value of bit 3 in the CR0 read
shadow is irrelevant in this case), unless CR0.TS is fixed to 1 in VMX operation (see Section 23.8), in which
case CLTS causes a general-protection exception.
— If bit 3 in the CR0 guest/host mask is 1 and bit 3 in the CR0 read shadow is 0, CLTS completes but does not
change the contents of CR0.TS.
— If the bits in position 3 in the CR0 guest/host mask and the CR0 read shadow are both 1, CLTS causes a
VM exit.
•
INVPCID. Behavior of the INVPCID instruction is determined first by the setting of the “enable INVPCID”
VM-execution control:
— If the “enable INVPCID” VM-execution control is 0, INVPCID causes an invalid-opcode exception (#UD).
This exception takes priority over any other exception the instruction may incur.
1. Under the dual-monitor treatment of SMIs and SMM, SMIs also cause SMM VM exits if they occur in VMX root operation outside SMM.
If the processor is using the default treatment of SMIs and SMM, SMIs are delivered as described in Section 34.14.1.
1. Some of the items in this section refer to secondary processor-based VM-execution controls. If bit 31 of the primary processorbased VM-execution controls is 0, VMX non-root operation functions as if these controls were all 0. See Section 24.6.2.
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VMX NON-ROOT OPERATION
— If the “enable INVPCID” VM-execution control is 1, treatment is based on the setting of the “INVLPG
exiting” VM-execution control:
•
•
•
If the “INVLPG exiting” VM-execution control is 0, INVPCID operates normally.
If the “INVLPG exiting” VM-execution control is 1, INVPCID causes a VM exit.
IRET. Behavior of IRET with regard to NMI blocking (see Table 24-3) is determined by the settings of the “NMI
exiting” and “virtual NMIs” VM-execution controls:
— If the “NMI exiting” VM-execution control is 0, IRET operates normally and unblocks NMIs. (If the “NMI
exiting” VM-execution control is 0, the “virtual NMIs” control must be 0; see Section 26.2.1.1.)
— If the “NMI exiting” VM-execution control is 1, IRET does not affect blocking of NMIs. If, in addition, the
“virtual NMIs” VM-execution control is 1, the logical processor tracks virtual-NMI blocking. In this case,
IRET removes any virtual-NMI blocking.
The unblocking of NMIs or virtual NMIs specified above occurs even if IRET causes a fault.
•
LMSW. Outside of VMX non-root operation, LMSW loads its source operand into CR0[3:0], but it does not clear
CR0.PE if that bit is set. In VMX non-root operation, an execution of LMSW that does not cause a VM exit (see
Section 25.1.3) leaves unmodified any bit in CR0[3:0] corresponding to a bit set in the CR0 guest/host mask.
An attempt to set any other bit in CR0[3:0] to a value not supported in VMX operation (see Section 23.8)
causes a general-protection exception. Attempts to clear CR0.PE are ignored without fault.
•
MOV from CR0. The behavior of MOV from CR0 is determined by the CR0 guest/host mask and the CR0 read
shadow. For each position corresponding to a bit clear in the CR0 guest/host mask, the destination operand is
loaded with the value of the corresponding bit in CR0. For each position corresponding to a bit set in the CR0
guest/host mask, the destination operand is loaded with the value of the corresponding bit in the CR0 read
shadow. Thus, if every bit is cleared in the CR0 guest/host mask, MOV from CR0 reads normally from CR0; if
every bit is set in the CR0 guest/host mask, MOV from CR0 returns the value of the CR0 read shadow.
Depending on the contents of the CR0 guest/host mask and the CR0 read shadow, bits may be set in the
destination that would never be set when reading directly from CR0.
•
MOV from CR3. If the “enable EPT” VM-execution control is 1 and an execution of MOV from CR3 does not
cause a VM exit (see Section 25.1.3), the value loaded from CR3 is a guest-physical address; see Section
28.2.1.
•
MOV from CR4. The behavior of MOV from CR4 is determined by the CR4 guest/host mask and the CR4 read
shadow. For each position corresponding to a bit clear in the CR4 guest/host mask, the destination operand is
loaded with the value of the corresponding bit in CR4. For each position corresponding to a bit set in the CR4
guest/host mask, the destination operand is loaded with the value of the corresponding bit in the CR4 read
shadow. Thus, if every bit is cleared in the CR4 guest/host mask, MOV from CR4 reads normally from CR4; if
every bit is set in the CR4 guest/host mask, MOV from CR4 returns the value of the CR4 read shadow.
Depending on the contents of the CR4 guest/host mask and the CR4 read shadow, bits may be set in the
destination that would never be set when reading directly from CR4.
•
MOV from CR8. If the MOV from CR8 instruction does not cause a VM exit (see Section 25.1.3), its behavior
is modified if the “use TPR shadow” VM-execution control is 1; see Section 29.3.
•
MOV to CR0. An execution of MOV to CR0 that does not cause a VM exit (see Section 25.1.3) leaves
unmodified any bit in CR0 corresponding to a bit set in the CR0 guest/host mask. Treatment of attempts to
modify other bits in CR0 depends on the setting of the “unrestricted guest” VM-execution control:
— If the control is 0, MOV to CR0 causes a general-protection exception if it attempts to set any bit in CR0 to
a value not supported in VMX operation (see Section 23.8).
— If the control is 1, MOV to CR0 causes a general-protection exception if it attempts to set any bit in CR0
other than bit 0 (PE) or bit 31 (PG) to a value not supported in VMX operation. It remains the case,
however, that MOV to CR0 causes a general-protection exception if it would result in CR0.PE = 0 and
CR0.PG = 1 or if it would result in CR0.PG = 1, CR4.PAE = 0, and IA32_EFER.LME = 1.
•
MOV to CR3. If the “enable EPT” VM-execution control is 1 and an execution of MOV to CR3 does not cause a
VM exit (see Section 25.1.3), the value loaded into CR3 is treated as a guest-physical address; see Section
28.2.1.
— If PAE paging is not being used, the instruction does not use the guest-physical address to access memory
and it does not cause it to be translated through EPT.1
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VMX NON-ROOT OPERATION
— If PAE paging is being used, the instruction translates the guest-physical address through EPT and uses the
result to load the four (4) page-directory-pointer-table entries (PDPTEs). The instruction does not use the
guest-physical addresses the PDPTEs to access memory and it does not cause them to be translated
through EPT.
•
MOV to CR4. An execution of MOV to CR4 that does not cause a VM exit (see Section 25.1.3) leaves
unmodified any bit in CR4 corresponding to a bit set in the CR4 guest/host mask. Such an execution causes a
general-protection exception if it attempts to set any bit in CR4 (not corresponding to a bit set in the CR4
guest/host mask) to a value not supported in VMX operation (see Section 23.8).
•
MOV to CR8. If the MOV to CR8 instruction does not cause a VM exit (see Section 25.1.3), its behavior is
modified if the “use TPR shadow” VM-execution control is 1; see Section 29.3.
•
MWAIT. Behavior of the MWAIT instruction (which always causes an invalid-opcode exception—#UD—if
CPL > 0) is determined by the setting of the “MWAIT exiting” VM-execution control:
— If the “MWAIT exiting” VM-execution control is 1, MWAIT causes a VM exit.
— If the “MWAIT exiting” VM-execution control is 0, MWAIT operates normally if one of the following are true:
(1) ECX[0] is 0; (2) RFLAGS.IF = 1; or both of the following are true: (a) the “interrupt-window exiting” VMexecution control is 0; and (b) the logical processor has not recognized a pending virtual interrupt (see
Section 29.2.1).
— If the “MWAIT exiting” VM-execution control is 0, ECX[0] = 1, and RFLAGS.IF = 0, MWAIT does not cause
the processor to enter an implementation-dependent optimized state if either the “interrupt-window
exiting” VM-execution control is 1 or the logical processor has recognized a pending virtual interrupt;
instead, control passes to the instruction following the MWAIT instruction.
•
RDMSR. Section 25.1.3 identifies when executions of the RDMSR instruction cause VM exits. If such an
execution causes neither a fault due to CPL > 0 nor a VM exit, the instruction’s behavior may be modified for
certain values of ECX:
— If ECX contains 10H (indicating the IA32_TIME_STAMP_COUNTER MSR), the value returned by the
instruction is determined by the setting of the “use TSC offsetting” VM-execution control:
•
If the control is 0, RDMSR operates normally, loading EAX:EDX with the value of the
IA32_TIME_STAMP_COUNTER MSR.
•
If the control is 1, the value returned is determined by the setting of the “use TSC scaling” VM-execution
control:
—
If the control is 0, RDMSR loads EAX:EDX with the sum of the value of the
IA32_TIME_STAMP_COUNTER MSR and the value of the TSC offset.
—
If the control is 1, RDMSR first computes the product of the value of the
IA32_TIME_STAMP_COUNTER MSR and the value of the TSC multiplier. It then shifts the value of
the product right 48 bits and loads EAX:EDX with the sum of that shifted value and the value of the
TSC offset.
The 1-setting of the “use TSC-offsetting” VM-execution control does not affect executions of RDMSR if ECX
contains 6E0H (indicating the IA32_TSC_DEADLINE MSR). Such executions return the APIC-timer deadline
relative to the actual timestamp counter without regard to the TSC offset.
— If ECX is in the range 800H–8FFH (indicating an APIC MSR), instruction behavior may be modified if the
“virtualize x2APIC mode” VM-execution control is 1; see Section 29.5.
•
RDPID. Behavior of the RDPID instruction is determined first by the setting of the “enable RDTSCP”
VM-execution control:
— If the “enable RDTSCP” VM-execution control is 0, RDPID causes an invalid-opcode exception (#UD).
— If the “enable RDTSCP” VM-execution control is 1, RDPID operates normally.
•
RDTSC. Behavior of the RDTSC instruction is determined by the settings of the “RDTSC exiting” and “use TSC
offsetting” VM-execution controls:
1. A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1 and IA32_EFER.LMA = 0. See Section 4.4 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A.
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VMX NON-ROOT OPERATION
— If both controls are 0, RDTSC operates normally.
— If the “RDTSC exiting” VM-execution control is 0 and the “use TSC offsetting” VM-execution control is 1, the
value returned is determined by the setting of the “use TSC scaling” VM-execution control:
•
If the control is 0, RDTSC loads EAX:EDX with the sum of the value of the IA32_TIME_STAMP_COUNTER
MSR and the value of the TSC offset.
•
If the control is 1, RDTSC first computes the product of the value of the IA32_TIME_STAMP_COUNTER
MSR and the value of the TSC multiplier. It then shifts the value of the product right 48 bits and loads
EAX:EDX with the sum of that shifted value and the value of the TSC offset.
— If the “RDTSC exiting” VM-execution control is 1, RDTSC causes a VM exit.
•
RDTSCP. Behavior of the RDTSCP instruction is determined first by the setting of the “enable RDTSCP”
VM-execution control:
— If the “enable RDTSCP” VM-execution control is 0, RDTSCP causes an invalid-opcode exception (#UD). This
exception takes priority over any other exception the instruction may incur.
— If the “enable RDTSCP” VM-execution control is 1, treatment is based on the settings of the “RDTSC exiting”
and “use TSC offsetting” VM-execution controls:
•
•
If both controls are 0, RDTSCP operates normally.
If the “RDTSC exiting” VM-execution control is 0 and the “use TSC offsetting” VM-execution control is 1,
the value returned is determined by the setting of the “use TSC scaling” VM-execution control:
—
If the control is 0, RDTSCP loads EAX:EDX with the sum of the value of the
IA32_TIME_STAMP_COUNTER MSR and the value of the TSC offset.
—
If the control is 1, RDTSCP first computes the product of the value of the
IA32_TIME_STAMP_COUNTER MSR and the value of the TSC multiplier. It then shifts the value of
the product right 48 bits and loads EAX:EDX with the sum of that shifted value and the value of the
TSC offset.
In either case, RDTSCP also loads ECX with the value of bits 31:0 of the IA32_TSC_AUX MSR.
•
•
If the “RDTSC exiting” VM-execution control is 1, RDTSCP causes a VM exit.
SMSW. The behavior of SMSW is determined by the CR0 guest/host mask and the CR0 read shadow. For each
position corresponding to a bit clear in the CR0 guest/host mask, the destination operand is loaded with the
value of the corresponding bit in CR0. For each position corresponding to a bit set in the CR0 guest/host mask,
the destination operand is loaded with the value of the corresponding bit in the CR0 read shadow. Thus, if every
bit is cleared in the CR0 guest/host mask, MOV from CR0 reads normally from CR0; if every bit is set in the CR0
guest/host mask, MOV from CR0 returns the value of the CR0 read shadow.
Note the following: (1) for any memory destination or for a 16-bit register destination, only the low 16 bits of
the CR0 guest/host mask and the CR0 read shadow are used (bits 63:16 of a register destination are left
unchanged); (2) for a 32-bit register destination, only the low 32 bits of the CR0 guest/host mask and the CR0
read shadow are used (bits 63:32 of the destination are cleared); and (3) depending on the contents of the
CR0 guest/host mask and the CR0 read shadow, bits may be set in the destination that would never be set
when reading directly from CR0.
•
WRMSR. Section 25.1.3 identifies when executions of the WRMSR instruction cause VM exits. If such an
execution neither a fault due to CPL > 0 nor a VM exit, the instruction’s behavior may be modified for certain
values of ECX:
— If ECX contains 79H (indicating IA32_BIOS_UPDT_TRIG MSR), no microcode update is loaded, and control
passes to the next instruction. This implies that microcode updates cannot be loaded in VMX non-root
operation.
— On processors that support Intel PT but which do not allow it to be used in VMX operation, if ECX contains
570H (indicating the IA32_RTIT_CTL MSR), the instruction causes a general-protection exception if it
attempts IA32_RTIT_CTL.TraceEn.1
1. Software should read the VMX capability MSR IA32_VMX_MISC to determine whether the processor allows Intel PT to be used in
VMX operation (see Appendix A.6).
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VMX NON-ROOT OPERATION
— If ECX contains 808H (indicating the TPR MSR), 80BH (the EOI MSR), or 83FH (self-IPI MSR), instruction
behavior may modified if the “virtualize x2APIC mode” VM-execution control is 1; see Section 29.5.
•
XRSTORS. Behavior of the XRSTORS instruction is determined first by the setting of the “enable
XSAVES/XRSTORS” VM-execution control:
— If the “enable XSAVES/XRSTORS” VM-execution control is 0, XRSTORS causes an invalid-opcode exception
(#UD).
— If the “enable XSAVES/XRSTORS” VM-execution control is 1, treatment is based on the value of the XSSexiting bitmap (see Section 24.6.19):
•
•
XRSTORS causes a VM exit if any bit is set in the logical-AND of the following three values: EDX:EAX,
the IA32_XSS MSR, and the XSS-exiting bitmap.
•
Otherwise, XRSTORS operates normally.
XSAVES. Behavior of the XSAVES instruction is determined first by the setting of the “enable
XSAVES/XRSTORS” VM-execution control:
— If the “enable XSAVES/XRSTORS” VM-execution control is 0, XSAVES causes an invalid-opcode exception
(#UD).
— If the “enable XSAVES/XRSTORS” VM-execution control is 1, treatment is based on the value of the XSSexiting bitmap (see Section 24.6.19):
•
XSAVES causes a VM exit if any bit is set in the logical-AND of the following three values: EDX:EAX, the
IA32_XSS MSR, and the XSS-exiting bitmap.
•
Otherwise, XSAVES operates normally.
25.4
OTHER CHANGES IN VMX NON-ROOT OPERATION
Treatments of event blocking and of task switches differ in VMX non-root operation as described in the following
sections.
25.4.1
Event Blocking
Event blocking is modified in VMX non-root operation as follows:
•
If the “external-interrupt exiting” VM-execution control is 1, RFLAGS.IF does not control the blocking of
external interrupts. In this case, an external interrupt that is not blocked for other reasons causes a VM exit
(even if RFLAGS.IF = 0).
•
If the “external-interrupt exiting” VM-execution control is 1, external interrupts may or may not be blocked by
STI or by MOV SS (behavior is implementation-specific).
•
If the “NMI exiting” VM-execution control is 1, non-maskable interrupts (NMIs) may or may not be blocked by
STI or by MOV SS (behavior is implementation-specific).
25.4.2
Treatment of Task Switches
Task switches are not allowed in VMX non-root operation. Any attempt to effect a task switch in VMX non-root operation causes a VM exit. However, the following checks are performed (in the order indicated), possibly resulting in
a fault, before there is any possibility of a VM exit due to task switch:
1. If a task gate is being used, appropriate checks are made on its P bit and on the proper values of the relevant
privilege fields. The following cases detail the privilege checks performed:
a. If CALL, INT n, or JMP accesses a task gate in IA-32e mode, a general-protection exception occurs.
b. If CALL, INT n, INT3, INTO, or JMP accesses a task gate outside IA-32e mode, privilege-levels checks are
performed on the task gate but, if they pass, privilege levels are not checked on the referenced task-state
segment (TSS) descriptor.
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VMX NON-ROOT OPERATION
c.
If CALL or JMP accesses a TSS descriptor directly in IA-32e mode, a general-protection exception occurs.
d. If CALL or JMP accesses a TSS descriptor directly outside IA-32e mode, privilege levels are checked on the
TSS descriptor.
e. If a non-maskable interrupt (NMI), an exception, or an external interrupt accesses a task gate in the IDT in
IA-32e mode, a general-protection exception occurs.
f.
If a non-maskable interrupt (NMI), an exception other than breakpoint exceptions (#BP) and overflow
exceptions (#OF), or an external interrupt accesses a task gate in the IDT outside IA-32e mode, no
privilege checks are performed.
g. If IRET is executed with RFLAGS.NT = 1 in IA-32e mode, a general-protection exception occurs.
h. If IRET is executed with RFLAGS.NT = 1 outside IA-32e mode, a TSS descriptor is accessed directly and no
privilege checks are made.
2. Checks are made on the new TSS selector (for example, that is within GDT limits).
3. The new TSS descriptor is read. (A page fault results if a relevant GDT page is not present).
4. The TSS descriptor is checked for proper values of type (depends on type of task switch), P bit, S bit, and limit.
Only if checks 1–4 all pass (do not generate faults) might a VM exit occur. However, the ordering between a VM exit
due to a task switch and a page fault resulting from accessing the old TSS or the new TSS is implementationspecific. Some processors may generate a page fault (instead of a VM exit due to a task switch) if accessing either
TSS would cause a page fault. Other processors may generate a VM exit due to a task switch even if accessing
either TSS would cause a page fault.
If an attempt at a task switch through a task gate in the IDT causes an exception (before generating a VM exit due
to the task switch) and that exception causes a VM exit, information about the event whose delivery that accessed
the task gate is recorded in the IDT-vectoring information fields and information about the exception that caused
the VM exit is recorded in the VM-exit interruption-information fields. See Section 27.2. The fact that a task gate
was being accessed is not recorded in the VMCS.
If an attempt at a task switch through a task gate in the IDT causes VM exit due to the task switch, information
about the event whose delivery accessed the task gate is recorded in the IDT-vectoring fields of the VMCS. Since
the cause of such a VM exit is a task switch and not an interruption, the valid bit for the VM-exit interruption information field is 0. See Section 27.2.
25.5
FEATURES SPECIFIC TO VMX NON-ROOT OPERATION
Some VM-execution controls support features that are specific to VMX non-root operation. These are the VMXpreemption timer (Section 25.5.1) and the monitor trap flag (Section 25.5.2), translation of guest-physical
addresses (Section 25.5.3), VM functions (Section 25.5.5), and virtualization exceptions (Section 25.5.6).
25.5.1
VMX-Preemption Timer
If the last VM entry was performed with the 1-setting of “activate VMX-preemption timer” VM-execution control,
the VMX-preemption timer counts down (from the value loaded by VM entry; see Section 26.6.4) in VMX nonroot operation. When the timer counts down to zero, it stops counting down and a VM exit occurs (see Section
25.2).
The VMX-preemption timer counts down at rate proportional to that of the timestamp counter (TSC). Specifically,
the timer counts down by 1 every time bit X in the TSC changes due to a TSC increment. The value of X is in the
range 0–31 and can be determined by consulting the VMX capability MSR IA32_VMX_MISC (see Appendix A.6).
The VMX-preemption timer operates in the C-states C0, C1, and C2; it also operates in the shutdown and wait-forSIPI states. If the timer counts down to zero in any state other than the wait-for SIPI state, the logical processor
transitions to the C0 C-state and causes a VM exit; the timer does not cause a VM exit if it counts down to zero in
the wait-for-SIPI state. The timer is not decremented in C-states deeper than C2.
Treatment of the timer in the case of system management interrupts (SMIs) and system-management mode
(SMM) depends on whether the treatment of SMIs and SMM:
Vol. 3C 25-11
VMX NON-ROOT OPERATION
•
If the default treatment of SMIs and SMM (see Section 34.14) is active, the VMX-preemption timer counts
across an SMI to VMX non-root operation, subsequent execution in SMM, and the return from SMM via the RSM
instruction. However, the timer can cause a VM exit only from VMX non-root operation. If the timer expires
during SMI, in SMM, or during RSM, a timer-induced VM exit occurs immediately after RSM with its normal
priority unless it is blocked based on activity state (Section 25.2).
•
If the dual-monitor treatment of SMIs and SMM (see Section 34.15) is active, transitions into and out of SMM
are VM exits and VM entries, respectively. The treatment of the VMX-preemption timer by those transitions is
mostly the same as for ordinary VM exits and VM entries; Section 34.15.2 and Section 34.15.4 detail some
differences.
25.5.2
Monitor Trap Flag
The monitor trap flag is a debugging feature that causes VM exits to occur on certain instruction boundaries in
VMX non-root operation. Such VM exits are called MTF VM exits. An MTF VM exit may occur on an instruction
boundary in VMX non-root operation as follows:
•
If the “monitor trap flag” VM-execution control is 1 and VM entry is injecting a vectored event (see Section
26.5.1), an MTF VM exit is pending on the instruction boundary before the first instruction following the
VM entry.
•
If VM entry is injecting a pending MTF VM exit (see Section 26.5.2), an MTF VM exit is pending on the
instruction boundary before the first instruction following the VM entry. This is the case even if the “monitor
trap flag” VM-execution control is 0.
•
If the “monitor trap flag” VM-execution control is 1, VM entry is not injecting an event, and a pending event
(e.g., debug exception or interrupt) is delivered before an instruction can execute, an MTF VM exit is pending
on the instruction boundary following delivery of the event (or any nested exception).
•
Suppose that the “monitor trap flag” VM-execution control is 1, VM entry is not injecting an event, and the first
instruction following VM entry is a REP-prefixed string instruction:
— If the first iteration of the instruction causes a fault, an MTF VM exit is pending on the instruction boundary
following delivery of the fault (or any nested exception).
— If the first iteration of the instruction does not cause a fault, an MTF VM exit is pending on the instruction
boundary after that iteration.
•
Suppose that the “monitor trap flag” VM-execution control is 1, VM entry is not injecting an event, and the first
instruction following VM entry is the XBEGIN instruction. In this case, an MTF VM exit is pending at the fallback
instruction address of the XBEGIN instruction. This behavior applies regardless of whether advanced debugging
of RTM transactional regions has been enabled (see Section 16.3.7, “RTM-Enabled Debugger Support,” of
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
•
Suppose that the “monitor trap flag” VM-execution control is 1, VM entry is not injecting an event, and the first
instruction following VM entry is neither a REP-prefixed string instruction or the XBEGIN instruction:
— If the instruction causes a fault, an MTF VM exit is pending on the instruction boundary following delivery of
the fault (or any nested exception).1
— If the instruction does not cause a fault, an MTF VM exit is pending on the instruction boundary following
execution of that instruction. If the instruction is INT3 or INTO, this boundary follows delivery of any
software exception. If the instruction is INT n, this boundary follows delivery of a software interrupt. If the
instruction is HLT, the MTF VM exit will be from the HLT activity state.
No MTF VM exit occurs if another VM exit occurs before reaching the instruction boundary on which an MTF VM exit
would be pending (e.g., due to an exception or triple fault).
An MTF VM exit occurs on the instruction boundary on which it is pending unless a higher priority event takes
precedence or the MTF VM exit is blocked due to the activity state:
•
System-management interrupts (SMIs), INIT signals, and higher priority events take priority over MTF
VM exits. MTF VM exits take priority over debug-trap exceptions and lower priority events.
1. This item includes the cases of an invalid opcode exception—#UD— generated by the UD2 instruction and a BOUND-range exceeded
exception—#BR—generated by the BOUND instruction.
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VMX NON-ROOT OPERATION
•
No MTF VM exit occurs if the processor is in either the shutdown activity state or wait-for-SIPI activity state. If
a non-maskable interrupt subsequently takes the logical processor out of the shutdown activity state without
causing a VM exit, an MTF VM exit is pending after delivery of that interrupt.
Special treatment may apply to Intel SGX instructions or if the logical processor is in enclave mode. See Section
43.2 for details.
25.5.3
Translation of Guest-Physical Addresses Using EPT
The extended page-table mechanism (EPT) is a feature that can be used to support the virtualization of physical
memory. When EPT is in use, certain physical addresses are treated as guest-physical addresses and are not used
to access memory directly. Instead, guest-physical addresses are translated by traversing a set of EPT paging
structures to produce physical addresses that are used to access memory.
Details of the EPT mechanism are given in Section 28.2.
25.5.4
APIC Virtualization
APIC virtualization is a collection of features that can be used to support the virtualization of interrupts and the
Advanced Programmable Interrupt Controller (APIC). When APIC virtualization is enabled, the processor emulates
many accesses to the APIC, tracks the state of the virtual APIC, and delivers virtual interrupts — all in VMX nonroot operation without a VM exit.
Details of the APIC virtualization are given in Chapter 29.
25.5.5
VM Functions
A VM function is an operation provided by the processor that can be invoked from VMX non-root operation
without a VM exit. VM functions are enabled and configured by the settings of different fields in the VMCS. Software in VMX non-root operation invokes a VM function with the VMFUNC instruction; the value of EAX selects the
specific VM function being invoked.
Section 25.5.5.1 explains how VM functions are enabled. Section 25.5.5.2 specifies the behavior of the VMFUNC
instruction. Section 25.5.5.3 describes a specific VM function called EPTP switching.
25.5.5.1
Enabling VM Functions
Software enables VM functions generally by setting the “enable VM functions” VM-execution control. A specific
VM function is enabled by setting the corresponding VM-function control.
Suppose, for example, that software wants to enable EPTP switching (VM function 0; see Section 24.6.14).To do
so, it must set the “activate secondary controls” VM-execution control (bit 31 of the primary processor-based VMexecution controls), the “enable VM functions” VM-execution control (bit 13 of the secondary processor-based VMexecution controls) and the “EPTP switching” VM-function control (bit 0 of the VM-function controls).
25.5.5.2
General Operation of the VMFUNC Instruction
The VMFUNC instruction causes an invalid-opcode exception (#UD) if the “enable VM functions” VM-execution
controls is 01 or the value of EAX is greater than 63 (only VM functions 0–63 can be enable). Otherwise, the
instruction causes a VM exit if the bit at position EAX is 0 in the VM-function controls (the selected VM function is
not enabled). If such a VM exit occurs, the basic exit reason used is 59 (3BH), indicating “VMFUNC”, and the length
of the VMFUNC instruction is saved into the VM-exit instruction-length field. If the instruction causes neither an
invalid-opcode exception nor a VM exit due to a disabled VM function, it performs the functionality of the
VM function specified by the value in EAX.
1. “Enable VM functions” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VMX non-root operation functions as if the “enable VM functions” VM-execution control were 0. See Section 24.6.2.
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VMX NON-ROOT OPERATION
Individual VM functions may perform additional fault checking (e.g., one might cause a general-protection exception if CPL > 0). In addition, specific VM functions may include checks that might result in a VM exit. If such a
VM exit occurs, VM-exit information is saved as described in the previous paragraph. The specification of a
VM function may indicate that additional VM-exit information is provided.
The specific behavior of the EPTP-switching VM function (including checks that result in VM exits) is given in
Section 25.5.5.3.
25.5.5.3
EPTP Switching
EPTP switching is VM function 0. This VM function allows software in VMX non-root operation to load a new value
for the EPT pointer (EPTP), thereby establishing a different EPT paging-structure hierarchy (see Section 28.2 for
details of the operation of EPT). Software is limited to selecting from a list of potential EPTP values configured in
advance by software in VMX root operation.
Specifically, the value of ECX is used to select an entry from the EPTP list, the 4-KByte structure referenced by the
EPTP-list address (see Section 24.6.14; because this structure contains 512 8-Byte entries, VMFUNC causes a
VM exit if ECX ≥ 512). If the selected entry is a valid EPTP value (it would not cause VM entry to fail; see Section
26.2.1.1), it is stored in the EPTP field of the current VMCS and is used for subsequent accesses using guest-physical addresses. The following pseudocode provides details:
IF ECX ≥ 512
THEN VM exit;
ELSE
tent_EPTP ← 8 bytes from EPTP-list address + 8 * ECX;
IF tent_EPTP is not a valid EPTP value (would cause VM entry to fail if in EPTP)
THEN VMexit;
ELSE
write tent_EPTP to the EPTP field in the current VMCS;
use tent_EPTP as the new EPTP value for address translation;
IF processor supports the 1-setting of the “EPT-violation #VE” VM-execution control
THEN
write ECX[15:0] to EPTP-index field in current VMCS;
use ECX[15:0] as EPTP index for subsequent EPT-violation virtualization exceptions (see Section 25.5.6.2);
FI;
FI;
FI;
Execution of the EPTP-switching VM function does not modify the state of any registers; no flags are modified.
As noted in Section 25.5.5.2, an execution of the EPTP-switching VM function that causes a VM exit (as specified
above), uses the basic exit reason 59, indicating “VMFUNC”. The length of the VMFUNC instruction is saved into the
VM-exit instruction-length field. No additional VM-exit information is provided.
An execution of VMFUNC loads EPTP from the EPTP list (and thus does not cause a fault or VM exit) is called an
EPTP-switching VMFUNC. After an EPTP-switching VMFUNC, control passes to the next instruction. The logical
processor starts creating and using guest-physical and combined mappings associated with the new value of bits
51:12 of EPTP; the combined mappings created and used are associated with the current VPID and PCID (these are
not changed by VMFUNC).1 If the “enable VPID” VM-execution control is 0, an EPTP-switching VMFUNC invalidates
combined mappings associated with VPID 0000H (for all PCIDs and for all EP4TA values, where EP4TA is the value
of bits 51:12 of EPTP).
Because an EPTP-switching VMFUNC may change the translation of guest-physical addresses, it may affect use of
the guest-physical address in CR3. The EPTP-switching VMFUNC cannot itself cause a VM exit due to an EPT violation or an EPT misconfiguration due to the translation of that guest-physical address through the new EPT paging
structures. The following items provide details that apply if CR0.PG = 1:
•
If 32-bit paging or IA-32e paging is in use (either CR4.PAE = 0 or IA32_EFER.LMA = 1), the next memory
access with a linear address uses the translation of the guest-physical address in CR3 through the new EPT
1. If the “enable VPID” VM-execution control is 0, the current VPID is 0000H; if CR4.PCIDE = 0, the current PCID is 000H.
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VMX NON-ROOT OPERATION
paging structures. As a result, this access may cause a VM exit due to an EPT violation or an EPT misconfiguration encountered during that translation.
•
If PAE paging is in use (CR4.PAE = 1 and IA32_EFER.LMA = 0), an EPTP-switching VMFUNC does not load the
four page-directory-pointer-table entries (PDPTEs) from the guest-physical address in CR3. The logical
processor continues to use the four guest-physical addresses already present in the PDPTEs. The guestphysical address in CR3 is not translated through the new EPT paging structures (until some operation that
would load the PDPTEs).
The EPTP-switching VMFUNC cannot itself cause a VM exit due to an EPT violation or an EPT misconfiguration
encountered during the translation of a guest-physical address in any of the PDPTEs. A subsequent memory
access with a linear address uses the translation of the guest-physical address in the appropriate PDPTE
through the new EPT paging structures. As a result, such an access may cause a VM exit due to an EPT
violation or an EPT misconfiguration encountered during that translation.
If an EPTP-switching VMFUNC establishes an EPTP value that enables accessed and dirty flags for EPT (by setting
bit 6), subsequent memory accesses may fail to set those flags as specified if there has been no appropriate execution of INVEPT since the last use of an EPTP value that does not enable accessed and dirty flags for EPT (because
bit 6 is clear) and that is identical to the new value on bits 51:12.
IF the processor supports the 1-setting of the “EPT-violation #VE” VM-execution control, an EPTP-switching
VMFUNC loads the value in ECX[15:0] into to EPTP-index field in current VMCS. Subsequent EPT-violation virtualization exceptions will save this value into the virtualization-exception information area (see Section 25.5.6.2);
25.5.6
Virtualization Exceptions
A virtualization exception is a new processor exception. It uses vector 20 and is abbreviated #VE.
A virtualization exception can occur only in VMX non-root operation. Virtualization exceptions occur only with
certain settings of certain VM-execution controls. Generally, these settings imply that certain conditions that would
normally cause VM exits instead cause virtualization exceptions
In particular, the 1-setting of the “EPT-violation #VE” VM-execution control causes some EPT violations to generate
virtualization exceptions instead of VM exits. Section 25.5.6.1 provides the details of how the processor determines whether an EPT violation causes a virtualization exception or a VM exit.
When the processor encounters a virtualization exception, it saves information about the exception to the virtualization-exception information area; see Section 25.5.6.2.
After saving virtualization-exception information, the processor delivers a virtualization exception as it would any
other exception; see Section 25.5.6.3 for details.
25.5.6.1
Convertible EPT Violations
If the “EPT-violation #VE” VM-execution control is 0 (e.g., on processors that do not support this feature), EPT
violations always cause VM exits. If instead the control is 1, certain EPT violations may be converted to cause virtualization exceptions instead; such EPT violations are convertible.
The values of certain EPT paging-structure entries determine which EPT violations are convertible. Specifically,
bit 63 of certain EPT paging-structure entries may be defined to mean suppress #VE:
•
If bits 2:0 of an EPT paging-structure entry are all 0, the entry is not present. If the processor encounters
such an entry while translating a guest-physical address, it causes an EPT violation. The EPT violation is
convertible if and only if bit 63 of the entry is 0.
•
If bits 2:0 of an EPT paging-structure entry are not all 0, the following cases apply:
— If the value of the EPT paging-structure entry is not supported, the entry is misconfigured. If the
processor encounters such an entry while translating a guest-physical address, it causes an EPT misconfiguration (not an EPT violation). EPT misconfigurations always cause VM exits.
— If the value of the EPT paging-structure entry is supported, the following cases apply:
Vol. 3C 25-15
VMX NON-ROOT OPERATION
•
If bit 7 of the entry is 1, or if the entry is an EPT PTE, the entry maps a page. If the processor uses such
an entry to translate a guest-physical address, and if an access to that address causes an EPT violation,
the EPT violation is convertible if and only if bit 63 of the entry is 0.
•
If bit 7 of the entry is 0 and the entry is not an EPT PTE, the entry references another EPT paging
structure. The processor does not use the value of bit 63 of the entry to determine whether any
subsequent EPT violation is convertible.
If an access to a guest-physical address causes an EPT violation, bit 63 of exactly one of the EPT paging-structure
entries used to translate that address is used to determine whether the EPT violation is convertible: either a entry
that is not present (if the guest-physical address does not translate to a physical address) or an entry that maps a
page (if it does).
A convertible EPT violation instead causes a virtualization exception if the following all hold:
•
•
•
CR0.PE = 1;
the logical processor is not in the process of delivering an event through the IDT; and
the 32 bits at offset 4 in the virtualization-exception information area are all 0.
Delivery of virtualization exceptions writes the value FFFFFFFFH to offset 4 in the virtualization-exception information area (see Section 25.5.6.2). Thus, once a virtualization exception occurs, another can occur only if software
clears this field.
25.5.6.2
Virtualization-Exception Information
Virtualization exceptions save data into the virtualization-exception information area (see Section 24.6.18).
Table 25-1 enumerates the data saved and the format of the area.
Table 25-1. Format of the Virtualization-Exception Information Area
Byte Offset
Contents
0
The 32-bit value that would have been saved into the VMCS as an exit reason had a VM exit occurred
instead of the virtualization exception. For EPT violations, this value is 48 (00000030H)
4
FFFFFFFFH
8
The 64-bit value that would have been saved into the VMCS as an exit qualification had a VM exit
occurred instead of the virtualization exception
16
The 64-bit value that would have been saved into the VMCS as a guest-linear address had a VM exit
occurred instead of the virtualization exception
24
The 64-bit value that would have been saved into the VMCS as a guest-physical address had a VM
exit occurred instead of the virtualization exception
32
The current 16-bit value of the EPTP index VM-execution control (see Section 24.6.18 and Section
25.5.5.3)
25.5.6.3
Delivery of Virtualization Exceptions
After saving virtualization-exception information, the processor treats a virtualization exception as it does other
exceptions:
•
If bit 20 (#VE) is 1 in the exception bitmap in the VMCS, a virtualization exception causes a VM exit (see
below). If the bit is 0, the virtualization exception is delivered using gate descriptor 20 in the IDT.
•
Virtualization exceptions produce no error code. Delivery of a virtualization exception pushes no error code on
the stack.
•
With respect to double faults, virtualization exceptions have the same severity as page faults. If delivery of a
virtualization exception encounters a nested fault that is either contributory or a page fault, a double fault
25-16 Vol. 3C
VMX NON-ROOT OPERATION
(#DF) is generated. See Chapter 6, “Interrupt 8—Double Fault Exception (#DF)” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
It is not possible for a virtualization exception to be encountered while delivering another exception (see
Section 25.5.6.1).
If a virtualization exception causes a VM exit directly (because bit 20 is 1 in the exception bitmap), information
about the exception is saved normally in the VM-exit interruption information field in the VMCS (see Section
27.2.2). Specifically, the event is reported as a hardware exception with vector 20 and no error code. Bit 12 of the
field (NMI unblocking due to IRET) is set normally.
If a virtualization exception causes a VM exit indirectly (because bit 20 is 0 in the exception bitmap and delivery of
the exception generates an event that causes a VM exit), information about the exception is saved normally in the
IDT-vectoring information field in the VMCS (see Section 27.2.3). Specifically, the event is reported as a hardware
exception with vector 20 and no error code.
25.6
UNRESTRICTED GUESTS
The first processors to support VMX operation require CR0.PE and CR0.PG to be 1 in VMX operation (see Section
23.8). This restriction implies that guest software cannot be run in unpaged protected mode or in real-address
mode. Later processors support a VM-execution control called “unrestricted guest”.1 If this control is 1, CR0.PE and
CR0.PG may be 0 in VMX non-root operation. Such processors allow guest software to run in unpaged protected
mode or in real-address mode. The following items describe the behavior of such software:
•
The MOV CR0 instructions does not cause a general-protection exception simply because it would set either
CR0.PE and CR0.PG to 0. See Section 25.3 for details.
•
A logical processor treats the values of CR0.PE and CR0.PG in VMX non-root operation just as it does outside
VMX operation. Thus, if CR0.PE = 0, the processor operates as it does normally in real-address mode (for
example, it uses the 16-bit interrupt table to deliver interrupts and exceptions). If CR0.PG = 0, the processor
operates as it does normally when paging is disabled.
•
Processor operation is modified by the fact that the processor is in VMX non-root operation and by the settings
of the VM-execution controls just as it is in protected mode or when paging is enabled. Instructions, interrupts,
and exceptions that cause VM exits in protected mode or when paging is enabled also do so in real-address
mode or when paging is disabled. The following examples should be noted:
— If CR0.PG = 0, page faults do not occur and thus cannot cause VM exits.
— If CR0.PE = 0, invalid-TSS exceptions do not occur and thus cannot cause VM exits.
— If CR0.PE = 0, the following instructions cause invalid-opcode exceptions and do not cause VM exits:
INVEPT, INVVPID, LLDT, LTR, SLDT, STR, VMCLEAR, VMLAUNCH, VMPTRLD, VMPTRST, VMREAD,
VMRESUME, VMWRITE, VMXOFF, and VMXON.
•
If CR0.PG = 0, each linear address is passed directly to the EPT mechanism for translation to a physical
address.2 The guest memory type passed on to the EPT mechanism is WB (writeback).
1. “Unrestricted guest” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VMX non-root operation functions as if the “unrestricted guest” VM-execution control were 0. See Section 24.6.2.
2. As noted in Section 26.2.1.1, the “enable EPT” VM-execution control must be 1 if the “unrestricted guest” VM-execution control is 1.
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VM ENTRIES
Software can enter VMX non-root operation using either of the VM-entry instructions VMLAUNCH and VMRESUME.
VMLAUNCH can be used only with a VMCS whose launch state is clear and VMRESUME can be used only with a
VMCS whose the launch state is launched. VMLAUNCH should be used for the first VM entry after VMCLEAR; VMRESUME should be used for subsequent VM entries with the same VMCS.
Each VM entry performs the following steps in the order indicated:
1. Basic checks are performed to ensure that VM entry can commence
(Section 26.1).
2. The control and host-state areas of the VMCS are checked to ensure that they are proper for supporting VMX
non-root operation and that the VMCS is correctly configured to support the next VM exit (Section 26.2).
3. The following may be performed in parallel or in any order (Section 26.3):
•
The guest-state area of the VMCS is checked to ensure that, after the VM entry completes, the state of the
logical processor is consistent with IA-32 and Intel 64 architectures.
•
•
Processor state is loaded from the guest-state area and based on controls in the VMCS.
Address-range monitoring is cleared.
4. MSRs are loaded from the VM-entry MSR-load area (Section 26.4).
5. If VMLAUNCH is being executed, the launch state of the VMCS is set to “launched.”
6. An event may be injected in the guest context (Section 26.5).
Steps 1–4 above perform checks that may cause VM entry to fail. Such failures occur in one of the following three
ways:
•
Some of the checks in Section 26.1 may generate ordinary faults (for example, an invalid-opcode exception).
Such faults are delivered normally.
•
Some of the checks in Section 26.1 and all the checks in Section 26.2 cause control to pass to the instruction
following the VM-entry instruction. The failure is indicated by setting RFLAGS.ZF1 (if there is a current VMCS)
or RFLAGS.CF (if there is no current VMCS). If there is a current VMCS, an error number indicating the cause of
the failure is stored in the VM-instruction error field. See Chapter 30 for the error numbers.
•
The checks in Section 26.3 and Section 26.4 cause processor state to be loaded from the host-state area of the
VMCS (as would be done on a VM exit). Information about the failure is stored in the VM-exit information fields.
See Section 26.7 for details.
EFLAGS.TF = 1 causes a VM-entry instruction to generate a single-step debug exception only if failure of one of the
checks in Section 26.1 and Section 26.2 causes control to pass to the following instruction. A VM-entry does not
generate a single-step debug exception in any of the following cases: (1) the instruction generates a fault; (2)
failure of one of the checks in Section 26.3 or in loading MSRs causes processor state to be loaded from the hoststate area of the VMCS; or (3) the instruction passes all checks in Section 26.1, Section 26.2, and Section 26.3 and
there is no failure in loading MSRs.
Section 34.15 describes the dual-monitor treatment of system-management interrupts (SMIs) and systemmanagement mode (SMM). Under this treatment, code running in SMM returns using VM entries instead of the
RSM instruction. A VM entry returns from SMM if it is executed in SMM and the “entry to SMM” VM-entry control
is 0. VM entries that return from SMM differ from ordinary VM entries in ways that are detailed in Section 34.15.4.
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX operation also support Intel 64 architecture. For IA-32 processors, this notation refers to the 32-bit forms of those registers (EAX, EIP,
ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to lower 32 bits of the indicated register.
Vol. 3C 26-1
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26.1
BASIC VM-ENTRY CHECKS
Before a VM entry commences, the current state of the logical processor is checked in the following order:
1. If the logical processor is in virtual-8086 mode or compatibility mode, an invalid-opcode exception is
generated.
2. If the current privilege level (CPL) is not zero, a general-protection exception is generated.
3. If there is no current VMCS, RFLAGS.CF is set to 1 and control passes to the next instruction.
4. If there is a current VMCS but the current VMCS is a shadow VMCS (see Section 24.10), RFLAGS.CF is set to 1
and control passes to the next instruction.
5. If there is a current VMCS that is not a shadow VMCS, the following conditions are evaluated in order; any of
these cause VM entry to fail:
a. if there is MOV-SS blocking (see Table 24-3)
b. if the VM entry is invoked by VMLAUNCH and the VMCS launch state is not clear
c.
if the VM entry is invoked by VMRESUME and the VMCS launch state is not launched
If any of these checks fail, RFLAGS.ZF is set to 1 and control passes to the next instruction. An error number
indicating the cause of the failure is stored in the VM-instruction error field. See Chapter 30 for the error
numbers.
26.2
CHECKS ON VMX CONTROLS AND HOST-STATE AREA
If the checks in Section 26.1 do not cause VM entry to fail, the control and host-state areas of the VMCS are
checked to ensure that they are proper for supporting VMX non-root operation, that the VMCS is correctly configured to support the next VM exit, and that, after the next VM exit, the processor’s state is consistent with the Intel
64 and IA-32 architectures.
VM entry fails if any of these checks fail. When such failures occur, control is passed to the next instruction,
RFLAGS.ZF is set to 1 to indicate the failure, and the VM-instruction error field is loaded with an error number that
indicates whether the failure was due to the controls or the host-state area (see Chapter 30).
These checks may be performed in any order. Thus, an indication by error number of one cause (for example, host
state) does not imply that there are not also other errors. Different processors may thus give different error
numbers for the same VMCS. Some checks prevent establishment of settings (or combinations of settings) that are
currently reserved. Future processors may allow such settings (or combinations) and may not perform the corresponding checks. The correctness of software should not rely on VM-entry failures resulting from the checks documented in this section.
The checks on the controls and the host-state area are presented in Section 26.2.1 through Section 26.2.4. These
sections reference VMCS fields that correspond to processor state. Unless otherwise stated, these references are
to fields in the host-state area.
26.2.1
Checks on VMX Controls
This section identifies VM-entry checks on the VMX control fields.
26.2.1.1
VM-Execution Control Fields
VM entries perform the following checks on the VM-execution control fields:1
•
Reserved bits in the pin-based VM-execution controls must be set properly. Software may consult the VMX
capability MSRs to determine the proper settings (see Appendix A.3.1).
1. If the “activate secondary controls” primary processor-based VM-execution control is 0, VM entry operates as if each secondary processor-based VM-execution control were 0.
26-2 Vol. 3C
VM ENTRIES
•
Reserved bits in the primary processor-based VM-execution controls must be set properly. Software may
consult the VMX capability MSRs to determine the proper settings (see Appendix A.3.2).
•
If the “activate secondary controls” primary processor-based VM-execution control is 1, reserved bits in the
secondary processor-based VM-execution controls must be cleared. Software may consult the VMX capability
MSRs to determine which bits are reserved (see Appendix A.3.3).
If the “activate secondary controls” primary processor-based VM-execution control is 0 (or if the processor
does not support the 1-setting of that control), no checks are performed on the secondary processor-based
VM-execution controls. The logical processor operates as if all the secondary processor-based VM-execution
controls were 0.
•
The CR3-target count must not be greater than 4. Future processors may support a different number of CR3target values. Software should read the VMX capability MSR IA32_VMX_MISC to determine the number of
values supported (see Appendix A.6).
•
If the “use I/O bitmaps” VM-execution control is 1, bits 11:0 of each I/O-bitmap address must be 0. Neither
address should set any bits beyond the processor’s physical-address width.1,2
•
If the “use MSR bitmaps” VM-execution control is 1, bits 11:0 of the MSR-bitmap address must be 0. The
address should not set any bits beyond the processor’s physical-address width.3
•
If the “use TPR shadow” VM-execution control is 1, the virtual-APIC address must satisfy the following checks:
— Bits 11:0 of the address must be 0.
— The address should not set any bits beyond the processor’s physical-address width.4
If all of the above checks are satisfied and the “use TPR shadow” VM-execution control is 1, bytes 3:1 of VTPR
(see Section 29.1.1) may be cleared (behavior may be implementation-specific).
The clearing of these bytes may occur even if the VM entry fails. This is true either if the failure causes control
to pass to the instruction following the VM-entry instruction or if it causes processor state to be loaded from
the host-state area of the VMCS.
•
If the “use TPR shadow” VM-execution control is 1 and the “virtual-interrupt delivery” VM-execution control is
0, bits 31:4 of the TPR threshold VM-execution control field must be 0.5
•
The following check is performed if the “use TPR shadow” VM-execution control is 1 and the “virtualize APIC
accesses” and “virtual-interrupt delivery” VM-execution controls are both 0: the value of bits 3:0 of the TPR
threshold VM-execution control field should not be greater than the value of bits 7:4 of VTPR (see Section
29.1.1).
•
•
•
If the “NMI exiting” VM-execution control is 0, the “virtual NMIs” VM-execution control must be 0.
If the “virtual NMIs” VM-execution control is 0, the “NMI-window exiting” VM-execution control must be 0.
If the “virtualize APIC-accesses” VM-execution control is 1, the APIC-access address must satisfy the following
checks:
— Bits 11:0 of the address must be 0.
— The address should not set any bits beyond the processor’s physical-address width.6
•
If the “use TPR shadow” VM-execution control is 0, the following VM-execution controls must also be 0:
“virtualize x2APIC mode”, “APIC-register virtualization”, and “virtual-interrupt delivery”.7
1. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
2. If IA32_VMX_BASIC[48] is read as 1, these addresses must not set any bits in the range 63:32; see Appendix A.1.
3. If IA32_VMX_BASIC[48] is read as 1, this address must not set any bits in the range 63:32; see Appendix A.1.
4. If IA32_VMX_BASIC[48] is read as 1, this address must not set any bits in the range 63:32; see Appendix A.1.
5. “Virtual-interrupt delivery” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls is 0, VM entry functions as if the “virtual-interrupt delivery” VM-execution control were 0. See Section 24.6.2.
6. If IA32_VMX_BASIC[48] is read as 1, this address must not set any bits in the range 63:32; see Appendix A.1.
7. “Virtualize x2APIC mode” and “APIC-register virtualization” are secondary processor-based VM-execution controls. If bit 31 of the
primary processor-based VM-execution controls is 0, VM entry functions as if these controls were 0. See Section 24.6.2.
Vol. 3C 26-3
VM ENTRIES
•
If the “virtualize x2APIC mode” VM-execution control is 1, the “virtualize APIC accesses” VM-execution control
must be 0.
•
If the “virtual-interrupt delivery” VM-execution control is 1, the “external-interrupt exiting” VM-execution
control must be 1.
•
If the “process posted interrupts” VM-execution control is 1, the following must be true:1
— The “virtual-interrupt delivery” VM-execution control is 1.
— The “acknowledge interrupt on exit” VM-exit control is 1.
— The posted-interrupt notification vector has a value in the range 0–255 (bits 15:8 are all 0).
— Bits 5:0 of the posted-interrupt descriptor address are all 0.
— The posted-interrupt descriptor address does not set any bits beyond the processor's physical-address
width.2
•
If the “enable VPID” VM-execution control is 1, the value of the VPID VM-execution control field must not be
0000H.3
•
If the “enable EPT” VM-execution control is 1, the EPTP VM-execution control field (see Table 24-8 in Section
24.6.11) must satisfy the following checks:4
— The EPT memory type (bits 2:0) must be a value supported by the processor as indicated in the
IA32_VMX_EPT_VPID_CAP MSR (see Appendix A.10).
— Bits 5:3 (1 less than the EPT page-walk length) must be 3, indicating an EPT page-walk length of 4; see
Section 28.2.2.
— Bit 6 (enable bit for accessed and dirty flags for EPT) must be 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP
MSR (see Appendix A.10) is read as 0, indicating that the processor does not support accessed and dirty
flags for EPT.
— Reserved bits 11:7 and 63:N (where N is the processor’s physical-address width) must all be 0.
•
If the “enable PML” VM-execution control is 1, the “enable EPT” VM-execution control must also be 1.5 In
addition, the PML address must satisfy the following checks:
— Bits 11:0 of the address must be 0.
— The address should not set any bits beyond the processor’s physical-address width.6
•
If either the “unrestricted guest” VM-execution control or the “mode-based execute control for EPT” VMexecution control is 1, the “enable EPT” VM-execution control must also be 1.7
•
If the “enable VM functions” processor-based VM-execution control is 1, reserved bits in the VM-function
controls must be clear.8 Software may consult the VMX capability MSRs to determine which bits are reserved
(see Appendix A.11). In addition, the following check is performed based on the setting of bits in the VMfunction controls (see Section 24.6.14):
1. “Process posted interrupts” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls is 0, VM entry functions as if the “process posted interrupts” VM-execution control were 0. See Section 24.6.2.
2. If IA32_VMX_BASIC[48] is read as 1, this address must not set any bits in the range 63:32; see Appendix A.1.
3. “Enable VPID” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls
is 0, VM entry functions as if the “enable VPID” VM-execution control were 0. See Section 24.6.2.
4. “Enable EPT” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls
is 0, VM entry functions as if the “enable EPT” VM-execution control were 0. See Section 24.6.2.
5. “Enable PML” and “enable EPT” are both secondary processor-based VM-execution controls. If bit 31 of the primary processor-based
VM-execution controls is 0, VM entry functions as if both these controls were 0. See Section 24.6.2.
6. If IA32_VMX_BASIC[48] is read as 1, this address must not set any bits in the range 63:32; see Appendix A.1.
7. All these controls are secondary processor-based VM-execution controls. If bit 31 of the primary processor-based VM-execution controls is 0, VM entry functions as if all these controls were 0. See Section 24.6.2.
8. “Enable VM functions” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VM entry functions as if the “enable VM functions” VM-execution control were 0. See Section 24.6.2.
26-4 Vol. 3C
VM ENTRIES
— If “EPTP switching” VM-function control is 1, the “enable EPT” VM-execution control must also be 1. In
addition, the EPTP-list address must satisfy the following checks:
•
•
Bits 11:0 of the address must be 0.
The address must not set any bits beyond the processor’s physical-address width.
If the “enable VM functions” processor-based VM-execution control is 0, no checks are performed on the VMfunction controls.
•
If the “VMCS shadowing” VM-execution control is 1, the VMREAD-bitmap and VMWRITE-bitmap addresses
must each satisfy the following checks:1
— Bits 11:0 of the address must be 0.
— The address must not set any bits beyond the processor’s physical-address width.
•
If the “EPT-violation #VE” VM-execution control is 1, the virtualization-exception information address must
satisfy the following checks:2
— Bits 11:0 of the address must be 0.
— The address must not set any bits beyond the processor’s physical-address width.
26.2.1.2
VM-Exit Control Fields
VM entries perform the following checks on the VM-exit control fields.
•
Reserved bits in the VM-exit controls must be set properly. Software may consult the VMX capability MSRs to
determine the proper settings (see Appendix A.4).
•
If the “activate VMX-preemption timer” VM-execution control is 0, the “save VMX-preemption timer value” VMexit control must also be 0.
•
The following checks are performed for the VM-exit MSR-store address if the VM-exit MSR-store count field is
non-zero:
— The lower 4 bits of the VM-exit MSR-store address must be 0. The address should not set any bits beyond
the processor’s physical-address width.3
— The address of the last byte in the VM-exit MSR-store area should not set any bits beyond the processor’s
physical-address width. The address of this last byte is VM-exit MSR-store address + (MSR count * 16) –
1. (The arithmetic used for the computation uses more bits than the processor’s physical-address width.)
If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits in the range 63:32; see Appendix
A.1.
•
The following checks are performed for the VM-exit MSR-load address if the VM-exit MSR-load count field is
non-zero:
— The lower 4 bits of the VM-exit MSR-load address must be 0. The address should not set any bits beyond
the processor’s physical-address width.
— The address of the last byte in the VM-exit MSR-load area should not set any bits beyond the processor’s
physical-address width. The address of this last byte is VM-exit MSR-load address + (MSR count * 16) – 1.
(The arithmetic used for the computation uses more bits than the processor’s physical-address width.)
If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits in the range 63:32; see Appendix
A.1.
1. “VMCS shadowing” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VM entry functions as if the “VMCS shadowing” VM-execution control were 0. See Section 24.6.2.
2. “EPT-violation #VE” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VM entry functions as if the “EPT-violation #VE” VM-execution control were 0. See Section 24.6.2.
3. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
Vol. 3C 26-5
VM ENTRIES
26.2.1.3
VM-Entry Control Fields
VM entries perform the following checks on the VM-entry control fields.
•
Reserved bits in the VM-entry controls must be set properly. Software may consult the VMX capability MSRs to
determine the proper settings (see Appendix A.5).
•
Fields relevant to VM-entry event injection must be set properly. These fields are the VM-entry interruptioninformation field (see Table 24-13 in Section 24.8.3), the VM-entry exception error code, and the VM-entry
instruction length. If the valid bit (bit 31) in the VM-entry interruption-information field is 1, the following must
hold:
— The field’s interruption type (bits 10:8) is not set to a reserved value. Value 1 is reserved on all logical
processors; value 7 (other event) is reserved on logical processors that do not support the 1-setting of the
“monitor trap flag” VM-execution control.
— The field’s vector (bits 7:0) is consistent with the interruption type:
•
•
•
If the interruption type is non-maskable interrupt (NMI), the vector is 2.
If the interruption type is hardware exception, the vector is at most 31.
If the interruption type is other event, the vector is 0 (pending MTF VM exit).
— The field's deliver-error-code bit (bit 11) is 1 if and only if (1) either (a) the "unrestricted guest" VMexecution control is 0; or (b) bit 0 (corresponding to CR0.PE) is set in the CR0 field in the guest-state area;
(2) the interruption type is hardware exception; and (3) the vector indicates an exception that would
normally deliver an error code (8 = #DF; 10 = TS; 11 = #NP; 12 = #SS; 13 = #GP; 14 = #PF; or 17 =
#AC).
— Reserved bits in the field (30:12) are 0.
— If the deliver-error-code bit (bit 11) is 1, bits 31:15 of the VM-entry exception error-code field are 0.
— If the interruption type is software interrupt, software exception, or privileged software exception, the
VM-entry instruction-length field is in the range 0–15. A VM-entry instruction length of 0 is allowed only if
IA32_VMX_MISC[30] is read as 1; see Appendix A.6.
•
The following checks are performed for the VM-entry MSR-load address if the VM-entry MSR-load count field is
non-zero:
— The lower 4 bits of the VM-entry MSR-load address must be 0. The address should not set any bits beyond
the processor’s physical-address width.1
— The address of the last byte in the VM-entry MSR-load area should not set any bits beyond the processor’s
physical-address width. The address of this last byte is VM-entry MSR-load address + (MSR count * 16) –
1. (The arithmetic used for the computation uses more bits than the processor’s physical-address width.)
If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits in the range 63:32; see Appendix
A.1.
•
If the processor is not in SMM, the “entry to SMM” and “deactivate dual-monitor treatment” VM-entry controls
must be 0.
•
The “entry to SMM” and “deactivate dual-monitor treatment” VM-entry controls cannot both be 1.
26.2.2
Checks on Host Control Registers and MSRs
The following checks are performed on fields in the host-state area that correspond to control registers and MSRs:
•
•
The CR0 field must not set any bit to a value not supported in VMX operation (see Section 23.8).2
The CR4 field must not set any bit to a value not supported in VMX operation (see Section 23.8).
1. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
2. The bits corresponding to CR0.NW (bit 29) and CR0.CD (bit 30) are never checked because the values of these bits are not changed
by VM exit; see Section 27.5.1.
26-6 Vol. 3C
VM ENTRIES
•
On processors that support Intel 64 architecture, the CR3 field must be such that bits 63:52 and bits in the
range 51:32 beyond the processor’s physical-address width must be 0.1,2
•
On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP
field must each contain a canonical address.
•
If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, bits reserved in the IA32_PERF_GLOBAL_CTRL
MSR must be 0 in the field for that register (see Figure 18-3).
•
If the “load IA32_PAT” VM-exit control is 1, the value of the field for the IA32_PAT MSR must be one that could
be written by WRMSR without fault at CPL 0. Specifically, each of the 8 bytes in the field must have one of the
values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6 (WB), or 7 (UC-).
•
If the “load IA32_EFER” VM-exit control is 1, bits reserved in the IA32_EFER MSR must be 0 in the field for that
register. In addition, the values of the LMA and LME bits in the field must each be that of the “host addressspace size” VM-exit control.
26.2.3
Checks on Host Segment and Descriptor-Table Registers
The following checks are performed on fields in the host-state area that correspond to segment and descriptortable registers:
•
In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the RPL (bits 1:0) and the TI flag (bit 2) must
be 0.
•
•
•
The selector fields for CS and TR cannot be 0000H.
The selector field for SS cannot be 0000H if the “host address-space size” VM-exit control is 0.
On processors that support Intel 64 architecture, the base-address fields for FS, GS, GDTR, IDTR, and TR must
contain canonical addresses.
26.2.4
Checks Related to Address-Space Size
On processors that support Intel 64 architecture, the following checks related to address-space size are performed
on VMX controls and fields in the host-state area:
•
If the logical processor is outside IA-32e mode (if IA32_EFER.LMA = 0) at the time of VM entry, the following
must hold:
— The “IA-32e mode guest” VM-entry control is 0.
— The “host address-space size” VM-exit control is 0.
•
If the logical processor is in IA-32e mode (if IA32_EFER.LMA = 1) at the time of VM entry, the “host addressspace size” VM-exit control must be 1.
•
If the “host address-space size” VM-exit control is 0, the following must hold:
— The “IA-32e mode guest” VM-entry control is 0.
— Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0.
— Bits 63:32 in the RIP field is 0.
•
If the “host address-space size” VM-exit control is 1, the following must hold:
— Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1.
— The RIP field contains a canonical address.
On processors that do not support Intel 64 architecture, checks are performed to ensure that the “IA-32e mode
guest” VM-entry control and the “host address-space size” VM-exit control are both 0.
1. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
2. Bit 63 of the CR3 field in the host-state area must be 0. This is true even though, If CR4.PCIDE = 1, bit 63 of the source operand to
MOV to CR3 is used to determine whether cached translation information is invalidated.
Vol. 3C 26-7
VM ENTRIES
26.3 CHECKING AND LOADING GUEST STATE
If all checks on the VMX controls and the host-state area pass (see Section 26.2), the following operations take
place concurrently: (1) the guest-state area of the VMCS is checked to ensure that, after the VM entry completes,
the state of the logical processor is consistent with IA-32 and Intel 64 architectures; (2) processor state is loaded
from the guest-state area or as specified by the VM-entry control fields; and (3) address-range monitoring is
cleared.
Because the checking and the loading occur concurrently, a failure may be discovered only after some state has
been loaded. For this reason, the logical processor responds to such failures by loading state from the host-state
area, as it would for a VM exit. See Section 26.7.
26.3.1
Checks on the Guest State Area
This section describes checks performed on fields in the guest-state area. These checks may be performed in any
order. Some checks prevent establishment of settings (or combinations of settings) that are currently reserved.
Future processors may allow such settings (or combinations) and may not perform the corresponding checks. The
correctness of software should not rely on VM-entry failures resulting from the checks documented in this section.
The following subsections reference fields that correspond to processor state. Unless otherwise stated, these references are to fields in the guest-state area.
26.3.1.1
Checks on Guest Control Registers, Debug Registers, and MSRs
The following checks are performed on fields in the guest-state area corresponding to control registers, debug
registers, and MSRs:
•
The CR0 field must not set any bit to a value not supported in VMX operation (see Section 23.8). The following
are exceptions:
— Bit 0 (corresponding to CR0.PE) and bit 31 (PG) are not checked if the “unrestricted guest” VM-execution
control is 1.1
— Bit 29 (corresponding to CR0.NW) and bit 30 (CD) are never checked because the values of these bits are
not changed by VM entry; see Section 26.3.2.1.
•
•
•
If bit 31 in the CR0 field (corresponding to PG) is 1, bit 0 in that field (PE) must also be 1.2
•
The following checks are performed on processors that support Intel 64 architecture:
The CR4 field must not set any bit to a value not supported in VMX operation (see Section 23.8).
If the “load debug controls” VM-entry control is 1, bits reserved in the IA32_DEBUGCTL MSR must be 0 in the
field for that register. The first processors to support the virtual-machine extensions supported only the 1setting of this control and thus performed this check unconditionally.
— If the “IA-32e mode guest” VM-entry control is 1, bit 31 in the CR0 field (corresponding to CR0.PG) and
bit 5 in the CR4 field (corresponding to CR4.PAE) must each be 1.3
— If the “IA-32e mode guest” VM-entry control is 0, bit 17 in the CR4 field (corresponding to CR4.PCIDE)
must be 0.
— The CR3 field must be such that bits 63:52 and bits in the range 51:32 beyond the processor’s physicaladdress width are 0.4,5
1. “Unrestricted guest” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VM entry functions as if the “unrestricted guest” VM-execution control were 0. See Section 24.6.2.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, bit 0 in the CR0 field must be 1
unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
3. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, bit 31 in the CR0 field must be 1
unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
4. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
26-8 Vol. 3C
VM ENTRIES
— If the “load debug controls” VM-entry control is 1, bits 63:32 in the DR7 field must be 0. The first
processors to support the virtual-machine extensions supported only the 1-setting of this control and thus
performed this check unconditionally (if they supported Intel 64 architecture).
— The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field must each contain a canonical address.
•
If the “load IA32_PERF_GLOBAL_CTRL” VM-entry control is 1, bits reserved in the IA32_PERF_GLOBAL_CTRL
MSR must be 0 in the field for that register (see Figure 18-3).
•
If the “load IA32_PAT” VM-entry control is 1, the value of the field for the IA32_PAT MSR must be one that could
be written by WRMSR without fault at CPL 0. Specifically, each of the 8 bytes in the field must have one of the
values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6 (WB), or 7 (UC-).
•
If the “load IA32_EFER” VM-entry control is 1, the following checks are performed on the field for the
IA32_EFER MSR :
— Bits reserved in the IA32_EFER MSR must be 0.
— Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of the “IA-32e mode guest” VM-entry
control. It must also be identical to bit 8 (LME) if bit 31 in the CR0 field (corresponding to CR0.PG) is 1.1
•
If the “load IA32_BNDCFGS” VM-entry control is 1, the following checks are performed on the field for the
IA32_BNDCFGS MSR :
— Bits reserved in the IA32_BNDCFGS MSR must be 0.
— The linear address in bits 63:12 must be canonical.
26.3.1.2
Checks on Guest Segment Registers
This section specifies the checks on the fields for CS, SS, DS, ES, FS, GS, TR, and LDTR. The following terms are
used in defining these checks:
•
•
The guest will be virtual-8086 if the VM flag (bit 17) is 1 in the RFLAGS field in the guest-state area.
•
Any one of these registers is said to be usable if the unusable bit (bit 16) is 0 in the access-rights field for that
register.
The guest will be IA-32e mode if the “IA-32e mode guest” VM-entry control is 1. (This is possible only on
processors that support Intel 64 architecture.)
The following are the checks on these fields:
•
Selector fields.
— TR. The TI flag (bit 2) must be 0.
— LDTR. If LDTR is usable, the TI flag (bit 2) must be 0.
— SS. If the guest will not be virtual-8086 and the “unrestricted guest” VM-execution control is 0, the RPL
(bits 1:0) must equal the RPL of the selector field for CS.2
•
Base-address fields.
— CS, SS, DS, ES, FS, GS. If the guest will be virtual-8086, the address must be the selector field shifted left
4 bits (multiplied by 16).
— The following checks are performed on processors that support Intel 64 architecture:
•
•
•
TR, FS, GS. The address must be canonical.
LDTR. If LDTR is usable, the address must be canonical.
CS. Bits 63:32 of the address must be zero.
5. Bit 63 of the CR3 field in the guest-state area must be 0. This is true even though, If CR4.PCIDE = 1, bit 63 of the source operand to
MOV to CR3 is used to determine whether cached translation information is invalidated.
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, bit 31 in the CR0 field must be 1
unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
2. “Unrestricted guest” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VM entry functions as if the “unrestricted guest” VM-execution control were 0. See Section 24.6.2.
Vol. 3C 26-9
VM ENTRIES
•
•
•
SS, DS, ES. If the register is usable, bits 63:32 of the address must be zero.
Limit fields for CS, SS, DS, ES, FS, GS. If the guest will be virtual-8086, the field must be 0000FFFFH.
Access-rights fields.
— CS, SS, DS, ES, FS, GS.
•
If the guest will be virtual-8086, the field must be 000000F3H. This implies the following:
— Bits 3:0 (Type) must be 3, indicating an expand-up read/write accessed data segment.
— Bit 4 (S) must be 1.
— Bits 6:5 (DPL) must be 3.
— Bit 7 (P) must be 1.
— Bits 11:8 (reserved), bit 12 (software available), bit 13 (reserved/L), bit 14 (D/B), bit 15 (G),
bit 16 (unusable), and bits 31:17 (reserved) must all be 0.
•
If the guest will not be virtual-8086, the different sub-fields are considered separately:
— Bits 3:0 (Type).
•
CS. The values allowed depend on the setting of the “unrestricted guest” VM-execution
control:
— If the control is 0, the Type must be 9, 11, 13, or 15 (accessed code segment).
— If the control is 1, the Type must be either 3 (read/write accessed expand-up data
segment) or one of 9, 11, 13, and 15 (accessed code segment).
•
•
SS. If SS is usable, the Type must be 3 or 7 (read/write, accessed data segment).
DS, ES, FS, GS. The following checks apply if the register is usable:
— Bit 0 of the Type must be 1 (accessed).
— If bit 3 of the Type is 1 (code segment), then bit 1 of the Type must be 1 (readable).
— Bit 4 (S). If the register is CS or if the register is usable, S must be 1.
— Bits 6:5 (DPL).
•
CS.
— If the Type is 3 (read/write accessed expand-up data segment), the DPL must be 0. The
Type can be 3 only if the “unrestricted guest” VM-execution control is 1.
— If the Type is 9 or 11 (non-conforming code segment), the DPL must equal the DPL in the
access-rights field for SS.
— If the Type is 13 or 15 (conforming code segment), the DPL cannot be greater than the
DPL in the access-rights field for SS.
•
SS.
— If the “unrestricted guest” VM-execution control is 0, the DPL must equal the RPL from the
selector field.
— The DPL must be 0 either if the Type in the access-rights field for CS is 3 (read/write
accessed expand-up data segment) or if bit 0 in the CR0 field (corresponding to CR0.PE) is
0.1
•
DS, ES, FS, GS. The DPL cannot be less than the RPL in the selector field if (1) the
“unrestricted guest” VM-execution control is 0; (2) the register is usable; and (3) the Type in
the access-rights field is in the range 0 – 11 (data segment or non-conforming code segment).
— Bit 7 (P). If the register is CS or if the register is usable, P must be 1.
1. The following apply if either the “unrestricted guest” VM-execution control or bit 31 of the primary processor-based VM-execution
controls is 0: (1) bit 0 in the CR0 field must be 1 if the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in
VMX operation; and (2) the Type in the access-rights field for CS cannot be 3.
26-10 Vol. 3C
VM ENTRIES
— Bits 11:8 (reserved). If the register is CS or if the register is usable, these bits must all be 0.
— Bit 14 (D/B). For CS, D/B must be 0 if the guest will be IA-32e mode and the L bit (bit 13) in the
access-rights field is 1.
— Bit 15 (G). The following checks apply if the register is CS or if the register is usable:
•
•
If any bit in the limit field in the range 11:0 is 0, G must be 0.
If any bit in the limit field in the range 31:20 is 1, G must be 1.
— Bits 31:17 (reserved). If the register is CS or if the register is usable, these bits must all be 0.
— TR. The different sub-fields are considered separately:
•
Bits 3:0 (Type).
— If the guest will not be IA-32e mode, the Type must be 3 (16-bit busy TSS) or 11 (32-bit busy
TSS).
— If the guest will be IA-32e mode, the Type must be 11 (64-bit busy TSS).
•
•
•
•
Bit 4 (S). S must be 0.
Bit 7 (P). P must be 1.
Bits 11:8 (reserved). These bits must all be 0.
Bit 15 (G).
— If any bit in the limit field in the range 11:0 is 0, G must be 0.
— If any bit in the limit field in the range 31:20 is 1, G must be 1.
•
•
Bit 16 (Unusable). The unusable bit must be 0.
Bits 31:17 (reserved). These bits must all be 0.
— LDTR. The following checks on the different sub-fields apply only if LDTR is usable:
•
•
•
•
•
Bits 3:0 (Type). The Type must be 2 (LDT).
Bit 4 (S). S must be 0.
Bit 7 (P). P must be 1.
Bits 11:8 (reserved). These bits must all be 0.
Bit 15 (G).
— If any bit in the limit field in the range 11:0 is 0, G must be 0.
— If any bit in the limit field in the range 31:20 is 1, G must be 1.
•
26.3.1.3
Bits 31:17 (reserved). These bits must all be 0.
Checks on Guest Descriptor-Table Registers
The following checks are performed on the fields for GDTR and IDTR:
•
•
On processors that support Intel 64 architecture, the base-address fields must contain canonical addresses.
Bits 31:16 of each limit field must be 0.
26.3.1.4
Checks on Guest RIP and RFLAGS
The following checks are performed on fields in the guest-state area corresponding to RIP and RFLAGS:
•
RIP. The following checks are performed on processors that support Intel 64 architecture:
— Bits 63:32 must be 0 if the “IA-32e mode guest” VM-entry control is 0 or if the L bit (bit 13) in the accessrights field for CS is 0.
— If the processor supports N < 64 linear-address bits, bits 63:N must be identical if the “IA-32e mode guest”
VM-entry control is 1 and the L bit in the access-rights field for CS is 1.1 (No check applies if the processor
supports 64 linear-address bits.)
Vol. 3C 26-11
VM ENTRIES
•
RFLAGS.
— Reserved bits 63:22 (bits 31:22 on processors that do not support Intel 64 architecture), bit 15, bit 5 and
bit 3 must be 0 in the field, and reserved bit 1 must be 1.
— The VM flag (bit 17) must be 0 either if the “IA-32e mode guest” VM-entry control is 1 or if bit 0 in the CR0
field (corresponding to CR0.PE) is 0.1
— The IF flag (RFLAGS[bit 9]) must be 1 if the valid bit (bit 31) in the VM-entry interruption-information field
is 1 and the interruption type (bits 10:8) is external interrupt.
26.3.1.5
Checks on Guest Non-Register State
The following checks are performed on fields in the guest-state area corresponding to non-register state:
•
Activity state.
— The activity-state field must contain a value in the range 0 – 3, indicating an activity state supported by the
implementation (see Section 24.4.2). Future processors may include support for other activity states.
Software should read the VMX capability MSR IA32_VMX_MISC (see Appendix A.6) to determine what
activity states are supported.
— The activity-state field must not indicate the HLT state if the DPL (bits 6:5) in the access-rights field for SS
is not 0.2
— The activity-state field must indicate the active state if the interruptibility-state field indicates blocking by
either MOV-SS or by STI (if either bit 0 or bit 1 in that field is 1).
— If the valid bit (bit 31) in the VM-entry interruption-information field is 1, the interruption to be delivered
(as defined by interruption type and vector) must not be one that would normally be blocked while a logical
processor is in the activity state corresponding to the contents of the activity-state field. The following
items enumerate the interruptions (as specified in the VM-entry interruption-information field) whose
injection is allowed for the different activity states:
•
•
Active. Any interruption is allowed.
HLT. The only events allowed are the following:
— Those with interruption type external interrupt or non-maskable interrupt (NMI).
— Those with interruption type hardware exception and vector 1 (debug exception) or vector 18
(machine-check exception).
— Those with interruption type other event and vector 0 (pending MTF VM exit).
See Table 24-13 in Section 24.8.3 for details regarding the format of the VM-entry interruptioninformation field.
•
•
Shutdown. Only NMIs and machine-check exceptions are allowed.
Wait-for-SIPI. No interruptions are allowed.
— The activity-state field must not indicate the wait-for-SIPI state if the “entry to SMM” VM-entry control is 1.
•
Interruptibility state.
— The reserved bits (bits 31:5) must be 0.
— The field cannot indicate blocking by both STI and MOV SS (bits 0 and 1 cannot both be 1).
— Bit 0 (blocking by STI) must be 0 if the IF flag (bit 9) is 0 in the RFLAGS field.
1. Software can determine the number N by executing CPUID with 80000008H in EAX. The number of linear-address bits supported is
returned in bits 15:8 of EAX.
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, bit 0 in the CR0 field must be 1
unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
2. As noted in Section 24.4.1, SS.DPL corresponds to the logical processor’s current privilege level (CPL).
26-12 Vol. 3C
VM ENTRIES
— Bit 0 (blocking by STI) and bit 1 (blocking by MOV-SS) must both be 0 if the valid bit (bit 31) in the
VM-entry interruption-information field is 1 and the interruption type (bits 10:8) in that field has value 0,
indicating external interrupt.
— Bit 1 (blocking by MOV-SS) must be 0 if the valid bit (bit 31) in the VM-entry interruption-information field
is 1 and the interruption type (bits 10:8) in that field has value 2, indicating non-maskable interrupt (NMI).
— Bit 2 (blocking by SMI) must be 0 if the processor is not in SMM.
— Bit 2 (blocking by SMI) must be 1 if the “entry to SMM” VM-entry control is 1.
— A processor may require bit 0 (blocking by STI) to be 0 if the valid bit (bit 31) in the VM-entry interruptioninformation field is 1 and the interruption type (bits 10:8) in that field has value 2, indicating NMI. Other
processors may not make this requirement.
— Bit 3 (blocking by NMI) must be 0 if the “virtual NMIs” VM-execution control is 1, the valid bit (bit 31) in the
VM-entry interruption-information field is 1, and the interruption type (bits 10:8) in that field has value 2
(indicating NMI).
— If bit 4 (enclave interruption) is 1, bit 1 (blocking by MOV-SS) must be 0 and the processor must support
for SGX by enumerating CPUID.(EAX=07H,ECX=0):EBX.SGX[bit 2] as 1.
NOTE
If the “virtual NMIs” VM-execution control is 0, there is no requirement that bit 3 be 0 if the valid
bit in the VM-entry interruption-information field is 1 and the interruption type in that field has
value 2.
•
Pending debug exceptions.
— Bits 11:4, bit 13, bit 15, and bits 63:17 (bits 31:17 on processors that do not support Intel 64 architecture) must be 0.
— The following checks are performed if any of the following holds: (1) the interruptibility-state field indicates
blocking by STI (bit 0 in that field is 1); (2) the interruptibility-state field indicates blocking by MOV SS
(bit 1 in that field is 1); or (3) the activity-state field indicates HLT:
•
Bit 14 (BS) must be 1 if the TF flag (bit 8) in the RFLAGS field is 1 and the BTF flag (bit 1) in the
IA32_DEBUGCTL field is 0.
•
Bit 14 (BS) must be 0 if the TF flag (bit 8) in the RFLAGS field is 0 or the BTF flag (bit 1) in the
IA32_DEBUGCTL field is 1.
— The following checks are performed if bit 16 (RTM) is 1:
•
•
Bits 11:0, bits 15:13, and bits 63:17 (bits 31:17 on processors that do not support Intel 64 architecture) must be 0; bit 12 must be 1.
•
•
The processor must support for RTM by enumerating CPUID.(EAX=07H,ECX=0):EBX[bit 11] as 1.
The interruptibility-state field must not indicate blocking by MOV SS (bit 1 in that field must be 0).
VMCS link pointer. The following checks apply if the field contains a value other than FFFFFFFF_FFFFFFFFH:
— Bits 11:0 must be 0.
— Bits beyond the processor’s physical-address width must be 0.1,2
— The 4 bytes located in memory referenced by the value of the field (as a physical address) must satisfy the
following:
•
Bits 30:0 must contain the processor’s VMCS revision identifier (see Section 24.2).3
1. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
2. If IA32_VMX_BASIC[48] is read as 1, this field must not set any bits in the range 63:32; see Appendix A.1.
3. Earlier versions of this manual specified that the VMCS revision identifier was a 32-bit field. For all processors produced prior to this
change, bit 31 of the VMCS revision identifier was 0.
Vol. 3C 26-13
VM ENTRIES
•
Bit 31 must contain the setting of the “VMCS shadowing” VM-execution control.1 This implies that the
referenced VMCS is a shadow VMCS (see Section 24.10) if and only if the “VMCS shadowing” VMexecution control is 1.
— If the processor is not in SMM or the “entry to SMM” VM-entry control is 1, the field must not contain the
current VMCS pointer.
— If the processor is in SMM and the “entry to SMM” VM-entry control is 0, the field must differ from the
executive-VMCS pointer.
26.3.1.6
Checks on Guest Page-Directory-Pointer-Table Entries
If CR0.PG =1, CR4.PAE = 1, and IA32_EFER.LME = 0, the logical processor uses PAE paging (see Section 4.4 in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).2 When PAE paging is in use, the
physical address in CR3 references a table of page-directory-pointer-table entries (PDPTEs). A MOV to CR3
when PAE paging is in use checks the validity of the PDPTEs.
A VM entry is to a guest that uses PAE paging if (1) bit 31 (corresponding to CR0.PG) is set in the CR0 field in the
guest-state area; (2) bit 5 (corresponding to CR4.PAE) is set in the CR4 field; and (3) the “IA-32e mode guest”
VM-entry control is 0. Such a VM entry checks the validity of the PDPTEs:
•
If the “enable EPT” VM-execution control is 0, VM entry checks the validity of the PDPTEs referenced by the CR3
field in the guest-state area if either (1) PAE paging was not in use before the VM entry; or (2) the value of CR3
is changing as a result of the VM entry. VM entry may check their validity even if neither (1) nor (2) hold.3
•
If the “enable EPT” VM-execution control is 1, VM entry checks the validity of the PDPTE fields in the guest-state
area (see Section 24.4.2).
A VM entry to a guest that does not use PAE paging does not check the validity of any PDPTEs.
A VM entry that checks the validity of the PDPTEs uses the same checks that are used when CR3 is loaded with
MOV to CR3 when PAE paging is in use.4 If MOV to CR3 would cause a general-protection exception due to the
PDPTEs that would be loaded (e.g., because a reserved bit is set), the VM entry fails.
26.3.2 Loading Guest State
Processor state is updated on VM entries in the following ways:
•
•
•
Some state is loaded from the guest-state area.
Some state is determined by VM-entry controls.
The page-directory pointers are loaded based on the values of certain control registers.
This loading may be performed in any order and in parallel with the checking of VMCS contents (see Section
26.3.1).
The loading of guest state is detailed in Section 26.3.2.1 to Section 26.3.2.4. These sections reference VMCS fields
that correspond to processor state. Unless otherwise stated, these references are to fields in the guest-state area.
In addition to the state loading described in this section, VM entries may load MSRs from the VM-entry MSR-load
area (see Section 26.4). This loading occurs only after the state loading described in this section and the checking
of VMCS contents described in Section 26.3.1.
1. “VMCS shadowing” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VM entry functions as if the “VMCS shadowing” VM-execution control were 0. See Section 24.6.2.
2. On processors that support Intel 64 architecture, the physical-address extension may support more than 36 physical-address bits.
Software can determine the number physical-address bits supported by executing CPUID with 80000008H in EAX. The physicaladdress width is returned in bits 7:0 of EAX.
3. “Enable EPT” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls
is 0, VM entry functions as if the “enable EPT” VM-execution control were 0. See Section 24.6.2.
4. This implies that (1) bits 11:9 in each PDPTE are ignored; and (2) if bit 0 (present) is clear in one of the PDPTEs, bits 63:1 of that
PDPTE are ignored.
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26.3.2.1
Loading Guest Control Registers, Debug Registers, and MSRs
The following items describe how guest control registers, debug registers, and MSRs are loaded on VM entry:
•
CR0 is loaded from the CR0 field with the exception of the following bits, which are never modified on VM entry:
ET (bit 4); reserved bits 15:6, 17, and 28:19; NW (bit 29) and CD (bit 30).1 The values of these bits in the CR0
field are ignored.
•
•
CR3 and CR4 are loaded from the CR3 field and the CR4 field, respectively.
If the “load debug controls” VM-entry control is 1, DR7 is loaded from the DR7 field with the exception that
bit 12 and bits 15:14 are always 0 and bit 10 is always 1. The values of these bits in the DR7 field are ignored.
The first processors to support the virtual-machine extensions supported only the 1-setting of the “load
debug controls” VM-entry control and thus always loaded DR7 from the DR7 field.
•
The following describes how certain MSRs are loaded using fields in the guest-state area:
— If the “load debug controls” VM-entry control is 1, the IA32_DEBUGCTL MSR is loaded from the
IA32_DEBUGCTL field. The first processors to support the virtual-machine extensions supported only the 1setting of this control and thus always loaded the IA32_DEBUGCTL MSR from the IA32_DEBUGCTL field.
— The IA32_SYSENTER_CS MSR is loaded from the IA32_SYSENTER_CS field. Since this field has only 32
bits, bits 63:32 of the MSR are cleared to 0.
— The IA32_SYSENTER_ESP and IA32_SYSENTER_EIP MSRs are loaded from the IA32_SYSENTER_ESP field
and the IA32_SYSENTER_EIP field, respectively. On processors that do not support Intel 64 architecture,
these fields have only 32 bits; bits 63:32 of the MSRs are cleared to 0.
— The following are performed on processors that support Intel 64 architecture:
•
The MSRs FS.base and GS.base are loaded from the base-address fields for FS and GS, respectively
(see Section 26.3.2.2).
•
If the “load IA32_EFER” VM-entry control is 0, bits in the IA32_EFER MSR are modified as follows:
— IA32_EFER.LMA is loaded with the setting of the “IA-32e mode guest” VM-entry control.
— If CR0 is being loaded so that CR0.PG = 1, IA32_EFER.LME is also loaded with the setting of the
“IA-32e mode guest” VM-entry control.2 Otherwise, IA32_EFER.LME is unmodified.
See below for the case in which the “load IA32_EFER” VM-entry control is 1
— If the “load IA32_PERF_GLOBAL_CTRL” VM-entry control is 1, the IA32_PERF_GLOBAL_CTRL MSR is loaded
from the IA32_PERF_GLOBAL_CTRL field.
— If the “load IA32_PAT” VM-entry control is 1, the IA32_PAT MSR is loaded from the IA32_PAT field.
— If the “load IA32_EFER” VM-entry control is 1, the IA32_EFER MSR is loaded from the IA32_EFER field.
— If the “load IA32_BNDCFGS” VM-entry control is 1, the IA32_BNDCFGS MSR is loaded from the
IA32_BNDCFGS field.
With the exception of FS.base and GS.base, any of these MSRs is subsequently overwritten if it appears in the
VM-entry MSR-load area. See Section 26.4.
•
The SMBASE register is unmodified by all VM entries except those that return from SMM.
1. Bits 15:6, bit 17, and bit 28:19 of CR0 and CR0.ET are unchanged by executions of MOV to CR0. Bits 15:6, bit 17, and bit 28:19 of
CR0 are always 0 and CR0.ET is always 1.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, VM entry must be loading CR0 so
that CR0.PG = 1 unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
Vol. 3C 26-15
VM ENTRIES
26.3.2.2
Loading Guest Segment Registers and Descriptor-Table Registers
For each of CS, SS, DS, ES, FS, GS, TR, and LDTR, fields are loaded from the guest-state area as follows:
•
The unusable bit is loaded from the access-rights field. This bit can never be set for TR (see Section 26.3.1.2).
If it is set for one of the other registers, the following apply:
— For each of CS, SS, DS, ES, FS, and GS, uses of the segment cause faults (general-protection exception or
stack-fault exception) outside 64-bit mode, just as they would had the segment been loaded using a null
selector. This bit does not cause accesses to fault in 64-bit mode.
— If this bit is set for LDTR, uses of LDTR cause general-protection exceptions in all modes, just as they would
had LDTR been loaded using a null selector.
If this bit is clear for any of CS, SS, DS, ES, FS, GS, TR, and LDTR, a null selector value does not cause a fault
(general-protection exception or stack-fault exception).
•
•
TR. The selector, base, limit, and access-rights fields are loaded.
CS.
— The following fields are always loaded: selector, base address, limit, and (from the access-rights field) the
L, D, and G bits.
— For the other fields, the unusable bit of the access-rights field is consulted:
•
•
•
If the unusable bit is 0, all of the access-rights field is loaded.
If the unusable bit is 1, the remainder of CS access rights are undefined after VM entry.
SS, DS, ES, FS, GS, and LDTR.
— The selector fields are loaded.
— For the other fields, the unusable bit of the corresponding access-rights field is consulted:
•
•
If the unusable bit is 0, the base-address, limit, and access-rights fields are loaded.
If the unusable bit is 1, the base address, the segment limit, and the remainder of the access rights are
undefined after VM entry with the following exceptions:
— Bits 3:0 of the base address for SS are cleared to 0.
— SS.DPL is always loaded from the SS access-rights field. This will be the current privilege level
(CPL) after the VM entry completes.
— SS.B is always set to 1.
— The base addresses for FS and GS are loaded from the corresponding fields in the VMCS. On
processors that support Intel 64 architecture, the values loaded for base addresses for FS and GS
are also manifest in the FS.base and GS.base MSRs.
— On processors that support Intel 64 architecture, the base address for LDTR is set to an undefined
but canonical value.
— On processors that support Intel 64 architecture, bits 63:32 of the base addresses for SS, DS, and
ES are cleared to 0.
GDTR and IDTR are loaded using the base and limit fields.
26.3.2.3
Loading Guest RIP, RSP, and RFLAGS
RSP, RIP, and RFLAGS are loaded from the RSP field, the RIP field, and the RFLAGS field, respectively. The following
items regard the upper 32 bits of these fields on VM entries that are not to 64-bit mode:
•
Bits 63:32 of RSP are undefined outside 64-bit mode. Thus, a logical processor may ignore the contents of
bits 63:32 of the RSP field on VM entries that are not to 64-bit mode.
•
As noted in Section 26.3.1.4, bits 63:32 of the RIP and RFLAGS fields must be 0 on VM entries that are not to
64-bit mode.
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26.3.2.4
Loading Page-Directory-Pointer-Table Entries
As noted in Section 26.3.1.6, the logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1, and
IA32_EFER.LME = 0. A VM entry to a guest that uses PAE paging loads the PDPTEs into internal, non-architectural
registers based on the setting of the “enable EPT” VM-execution control:
•
If the control is 0, the PDPTEs are loaded from the page-directory-pointer table referenced by the physical
address in the value of CR3 being loaded by the VM entry (see Section 26.3.2.1). The values loaded are treated
as physical addresses in VMX non-root operation.
•
If the control is 1, the PDPTEs are loaded from corresponding fields in the guest-state area (see Section
24.4.2). The values loaded are treated as guest-physical addresses in VMX non-root operation.
26.3.2.5
Updating Non-Register State
Section 28.3 describes how the VMX architecture controls how a logical processor manages information in the TLBs
and paging-structure caches. The following items detail how VM entries invalidate cached mappings:
•
If the “enable VPID” VM-execution control is 0, the logical processor invalidates linear mappings and combined
mappings associated with VPID 0000H (for all PCIDs); combined mappings for VPID 0000H are invalidated for
all EP4TA values (EP4TA is the value of bits 51:12 of EPTP).
•
VM entries are not required to invalidate any guest-physical mappings, nor are they required to invalidate any
linear mappings or combined mappings if the “enable VPID” VM-execution control is 1.
If the “virtual-interrupt delivery” VM-execution control is 1, VM entry loads the values of RVI and SVI from the
guest interrupt-status field in the VMCS (see Section 24.4.2). After doing so, the logical processor first causes PPR
virtualization (Section 29.1.3) and then evaluates pending virtual interrupts (Section 29.2.1).
If a virtual interrupt is recognized, it may be delivered in VMX non-root operation immediately after VM entry
(including any specified event injection) completes; see Section 26.6.5. See Section 29.2.2 for details regarding
the delivery of virtual interrupts.
26.3.3
Clearing Address-Range Monitoring
The Intel 64 and IA-32 architectures allow software to monitor a specified address range using the MONITOR and
MWAIT instructions. See Section 8.10.4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A. VM entries clear any address-range monitoring that may be in effect.
26.4
LOADING MSRS
VM entries may load MSRs from the VM-entry MSR-load area (see Section 24.8.2). Specifically each entry in that
area (up to the number specified in the VM-entry MSR-load count) is processed in order by loading the MSR
indexed by bits 31:0 with the contents of bits 127:64 as they would be written by WRMSR.1
Processing of an entry fails in any of the following cases:
•
•
The value of bits 31:0 is either C0000100H (the IA32_FS_BASE MSR) or C0000101 (the IA32_GS_BASE MSR).
•
The value of bits 31:0 indicates an MSR that can be written only in system-management mode (SMM) and the
VM entry did not commence in SMM. (IA32_SMM_MONITOR_CTL is an MSR that can be written only in SMM.)
•
The value of bits 31:0 indicates an MSR that cannot be loaded on VM entries for model-specific reasons. A
processor may prevent loading of certain MSRs even if they can normally be written by WRMSR. Such modelspecific behavior is documented in Chapter 35.
•
Bits 63:32 are not all 0.
The value of bits 31:8 is 000008H, meaning that the indexed MSR is one that allows access to an APIC register
when the local APIC is in x2APIC mode.
1. Because attempts to modify the value of IA32_EFER.LMA by WRMSR are ignored, attempts to modify it using the VM-entry MSRload area are also ignored.
Vol. 3C 26-17
VM ENTRIES
•
An attempt to write bits 127:64 to the MSR indexed by bits 31:0 of the entry would cause a general-protection
exception if executed via WRMSR with CPL = 0.1
The VM entry fails if processing fails for any entry. The logical processor responds to such failures by loading state
from the host-state area, as it would for a VM exit. See Section 26.7.
If any MSR is being loaded in such a way that would architecturally require a TLB flush, the TLBs are updated so
that, after VM entry, the logical processor will not use any translations that were cached before the transition.
26.5
EVENT INJECTION
If the valid bit in the VM-entry interruption-information field (see Section 24.8.3) is 1, VM entry causes an event to
be delivered (or made pending) after all components of guest state have been loaded (including MSRs) and after
the VM-execution control fields have been established.
•
If the interruption type in the field is 0 (external interrupt), 2 (non-maskable interrupt); 3 (hardware
exception), 4 (software interrupt), 5 (privileged software exception), or 6 (software exception), the event is
delivered as described in Section 26.5.1.
•
If the interruption type in the field is 7 (other event) and the vector field is 0, an MTF VM exit is pending after
VM entry. See Section 26.5.2.
26.5.1
Vectored-Event Injection
VM entry delivers an injected vectored event within the guest context established by VM entry. This means that
delivery occurs after all components of guest state have been loaded (including MSRs) and after the VM-execution
control fields have been established.2 The event is delivered using the vector in that field to select a descriptor in
the IDT. Since event injection occurs after loading IDTR from the guest-state area, this is the guest IDT.
Section 26.5.1.1 provides details of vectored-event injection. In general, the event is delivered exactly as if it had
been generated normally.
If event delivery encounters a nested exception (for example, a general-protection exception because the vector
indicates a descriptor beyond the IDT limit), the exception bitmap is consulted using the vector of that exception:
•
If the bit for the nested exception is 0, the nested exception is delivered normally. If the nested exception is
benign, it is delivered through the IDT. If it is contributory or a page fault, a double fault may be generated,
depending on the nature of the event whose delivery encountered the nested exception. See Chapter 6,
“Interrupt 8—Double Fault Exception (#DF)” in Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.3
•
If the bit for the nested exception is 1, a VM exit occurs. Section 26.5.1.2 details cases in which event injection
causes a VM exit.
26.5.1.1
Details of Vectored-Event Injection
The event-injection process is controlled by the contents of the VM-entry interruption information field (format
given in Table 24-13), the VM-entry exception error-code field, and the VM-entry instruction-length field. The
following items provide details of the process:
1. If CR0.PG = 1, WRMSR to the IA32_EFER MSR causes a general-protection exception if it would modify the LME bit. If VM entry has
established CR0.PG = 1, the IA32_EFER MSR should not be included in the VM-entry MSR-load area for the purpose of modifying the
LME bit.
2. This does not imply that injection of an exception or interrupt will cause a VM exit due to the settings of VM-execution control fields
(such as the exception bitmap) that would cause a VM exit if the event had occurred in VMX non-root operation. In contrast, a nested
exception encountered during event delivery may cause a VM exit; see Section 26.5.1.1.
3. Hardware exceptions with the following unused vectors are considered benign: 15 and 21–31. A hardware exception with vector 20
is considered benign unless the processor supports the 1-setting of the “EPT-violation #VE” VM-execution control; in that case, it
has the same severity as page faults.
26-18 Vol. 3C
VM ENTRIES
•
The value pushed on the stack for RFLAGS is generally that which was loaded from the guest-state area. The
value pushed for the RF flag is not modified based on the type of event being delivered. However, the pushed
value of RFLAGS may be modified if a software interrupt is being injected into a guest that will be in virtual8086 mode (see below). After RFLAGS is pushed on the stack, the value in the RFLAGS register is modified as
is done normally when delivering an event through the IDT.
•
The instruction pointer that is pushed on the stack depends on the type of event and whether nested
exceptions occur during its delivery. The term current guest RIP refers to the value to be loaded from the
guest-state area. The value pushed is determined as follows:1
— If VM entry successfully injects (with no nested exception) an event with interruption type external
interrupt, NMI, or hardware exception, the current guest RIP is pushed on the stack.
— If VM entry successfully injects (with no nested exception) an event with interruption type software
interrupt, privileged software exception, or software exception, the current guest RIP is incremented by the
VM-entry instruction length before being pushed on the stack.
— If VM entry encounters an exception while injecting an event and that exception does not cause a VM exit,
the current guest RIP is pushed on the stack regardless of event type or VM-entry instruction length. If the
encountered exception does cause a VM exit that saves RIP, the saved RIP is current guest RIP.
•
If the deliver-error-code bit (bit 11) is set in the VM-entry interruption-information field, the contents of the
VM-entry exception error-code field is pushed on the stack as an error code would be pushed during delivery of
an exception.
•
DR6, DR7, and the IA32_DEBUGCTL MSR are not modified by event injection, even if the event has vector 1
(normal deliveries of debug exceptions, which have vector 1, do update these registers).
•
If VM entry is injecting a software interrupt and the guest will be in virtual-8086 mode (RFLAGS.VM = 1), no
general-protection exception can occur due to RFLAGS.IOPL < 3. A VM monitor should check RFLAGS.IOPL
before injecting such an event and, if desired, inject a general-protection exception instead of a software
interrupt.
•
If VM entry is injecting a software interrupt and the guest will be in virtual-8086 mode with virtual-8086 mode
extensions (RFLAGS.VM = CR4.VME = 1), event delivery is subject to VME-based interrupt redirection based
on the software interrupt redirection bitmap in the task-state segment (TSS) as follows:
— If bit n in the bitmap is clear (where n is the number of the software interrupt), the interrupt is directed to
an 8086 program interrupt handler: the processor uses a 16-bit interrupt-vector table (IVT) located at
linear address zero. If the value of RFLAGS.IOPL is less than 3, the following modifications are made to the
value of RFLAGS that is pushed on the stack: IOPL is set to 3, and IF is set to the value of VIF.
— If bit n in the bitmap is set (where n is the number of the software interrupt), the interrupt is directed to a
protected-mode interrupt handler. (In other words, the injection is treated as described in the next item.)
In this case, the software interrupt does not invoke such a handler if RFLAGS.IOPL < 3 (a generalprotection exception occurs instead). However, as noted above, RFLAGS.IOPL cannot cause an injected
software interrupt to cause such a exception. Thus, in this case, the injection invokes a protected-mode
interrupt handler independent of the value of RFLAGS.IOPL.
Injection of events of other types are not subject to this redirection.
•
If VM entry is injecting a software interrupt (not redirected as described above) or software exception, privilege
checking is performed on the IDT descriptor being accessed as would be the case for executions of INT n, INT3,
or INTO (the descriptor’s DPL cannot be less than CPL). There is no checking of RFLAGS.IOPL, even if the guest
will be in virtual-8086 mode. Failure of this check may lead to a nested exception. Injection of an event with
interruption type external interrupt, NMI, hardware exception, and privileged software exception, or with interruption type software interrupt and being redirected as described above, do not perform these checks.
•
If VM entry is injecting a non-maskable interrupt (NMI) and the “virtual NMIs” VM-execution control is 1,
virtual-NMI blocking is in effect after VM entry.
•
The transition causes a last-branch record to be logged if the LBR bit is set in the IA32_DEBUGCTL MSR. This is
true even for events such as debug exceptions, which normally clear the LBR bit before delivery.
1. While these items refer to RIP, the width of the value pushed (16 bits, 32 bits, or 64 bits) is determined normally.
Vol. 3C 26-19
VM ENTRIES
•
The last-exception record MSRs (LERs) may be updated based on the setting of the LBR bit in the
IA32_DEBUGCTL MSR. Events such as debug exceptions, which normally clear the LBR bit before they are
delivered, and therefore do not normally update the LERs, may do so as part of VM-entry event injection.
•
If injection of an event encounters a nested exception that does not itself cause a VM exit, the value of the EXT
bit (bit 0) in any error code pushed on the stack is determined as follows:
— If event being injected has interruption type external interrupt, NMI, hardware exception, or privileged
software exception and encounters a nested exception (but does not produce a double fault), the error code
for the first such exception encountered sets the EXT bit.
— If event being injected is a software interrupt or an software exception and encounters a nested exception
(but does not produce a double fault), the error code for the first such exception encountered clears the EXT
bit.
— If event delivery encounters a nested exception and delivery of that exception encounters another
exception (but does not produce a double fault), the error code for that exception sets the EXT bit. If a
double fault is produced, the error code for the double fault is 0000H (the EXT bit is clear).
26.5.1.2
VM Exits During Event Injection
An event being injected never causes a VM exit directly regardless of the settings of the VM-execution controls. For
example, setting the “NMI exiting” VM-execution control to 1 does not cause a VM exit due to injection of an NMI.
However, the event-delivery process may lead to a VM exit:
•
If the vector in the VM-entry interruption-information field identifies a task gate in the IDT, the attempted task
switch may cause a VM exit just as it would had the injected event occurred during normal execution in VMX
non-root operation (see Section 25.4.2).
•
If event delivery encounters a nested exception, a VM exit may occur depending on the contents of the
exception bitmap (see Section 25.2).
•
If event delivery generates a double-fault exception (due to a nested exception); the logical processor
encounters another nested exception while attempting to call the double-fault handler; and that exception does
not cause a VM exit due to the exception bitmap; then a VM exit occurs due to triple fault (see Section 25.2).
•
If event delivery injects a double-fault exception and encounters a nested exception that does not cause a
VM exit due to the exception bitmap, then a VM exit occurs due to triple fault (see Section 25.2).
•
If the “virtualize APIC accesses” VM-execution control is 1 and event delivery generates an access to the APICaccess page, that access is treated as described in Section 29.4 and may cause a VM exit.1
If the event-delivery process does cause a VM exit, the processor state before the VM exit is determined just as it
would be had the injected event occurred during normal execution in VMX non-root operation. If the injected event
directly accesses a task gate that cause a VM exit or if the first nested exception encountered causes a VM exit,
information about the injected event is saved in the IDT-vectoring information field (see Section 27.2.3).
26.5.1.3
Event Injection for VM Entries to Real-Address Mode
If VM entry is loading CR0.PE with 0, any injected vectored event is delivered as would normally be done in realaddress mode.2 Specifically, VM entry uses the vector provided in the VM-entry interruption-information field to
select a 4-byte entry from an interrupt-vector table at the linear address in IDTR.base. Further details are provided
in Section 15.1.4 in Volume 3A of the IA-32 Intel® Architecture Software Developer’s Manual.
Because bit 11 (deliver error code) in the VM-entry interruption-information field must be 0 if CR0.PE will be 0 after
VM entry (see Section 26.2.1.3), vectored events injected with CR0.PE = 0 do not push an error code on the stack.
This is consistent with event delivery in real-address mode.
1. “Virtualize APIC accesses” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls is 0, VM entry functions as if the “virtualize APIC accesses” VM-execution control were 0. See Section 24.6.2.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, VM entry must be loading CR0.PE
with 1 unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are
both 1.
26-20 Vol. 3C
VM ENTRIES
If event delivery encounters a fault (due to a violation of IDTR.limit or of SS.limit), the fault is treated as if it had
occurred during event delivery in VMX non-root operation. Such a fault may lead to a VM exit as discussed in
Section 26.5.1.2.
26.5.2
Injection of Pending MTF VM Exits
If the interruption type in the VM-entry interruption-information field is 7 (other event) and the vector field is 0,
VM entry causes an MTF VM exit to be pending on the instruction boundary following VM entry. This is the case
even if the “monitor trap flag” VM-execution control is 0. See Section 25.5.2 for the treatment of pending MTF
VM exits.
26.6
SPECIAL FEATURES OF VM ENTRY
This section details a variety of features of VM entry. It uses the following terminology: a VM entry is vectoring if
the valid bit (bit 31) of the VM-entry interruption information field is 1 and the interruption type in the field is 0
(external interrupt), 2 (non-maskable interrupt); 3 (hardware exception), 4 (software interrupt), 5 (privileged
software exception), or 6 (software exception).
26.6.1
Interruptibility State
The interruptibility-state field in the guest-state area (see Table 24-3) contains bits that control blocking by STI,
blocking by MOV SS, and blocking by NMI. This field impacts event blocking after VM entry as follows:
•
If the VM entry is vectoring, there is no blocking by STI or by MOV SS following the VM entry, regardless of the
contents of the interruptibility-state field.
•
If the VM entry is not vectoring, the following apply:
— Events are blocked by STI if and only if bit 0 in the interruptibility-state field is 1. This blocking is cleared
after the guest executes one instruction or incurs an exception (including a debug exception made pending
by VM entry; see Section 26.6.3).
— Events are blocked by MOV SS if and only if bit 1 in the interruptibility-state field is 1. This may affect the
treatment of pending debug exceptions; see Section 26.6.3. This blocking is cleared after the guest
executes one instruction or incurs an exception (including a debug exception made pending by VM entry).
•
The blocking of non-maskable interrupts (NMIs) is determined as follows:
— If the “virtual NMIs” VM-execution control is 0, NMIs are blocked if and only if bit 3 (blocking by NMI) in the
interruptibility-state field is 1. If the “NMI exiting” VM-execution control is 0, execution of the IRET
instruction removes this blocking (even if the instruction generates a fault). If the “NMI exiting” control is
1, IRET does not affect this blocking.
— The following items describe the use of bit 3 (blocking by NMI) in the interruptibility-state field if the
“virtual NMIs” VM-execution control is 1:
•
The bit’s value does not affect the blocking of NMIs after VM entry. NMIs are not blocked in VMX nonroot operation (except for ordinary blocking for other reasons, such as by the MOV SS instruction, the
wait-for-SIPI state, etc.)
•
The bit’s value determines whether there is virtual-NMI blocking after VM entry. If the bit is 1, virtualNMI blocking is in effect after VM entry. If the bit is 0, there is no virtual-NMI blocking after VM entry
unless the VM entry is injecting an NMI (see Section 26.5.1.1). Execution of IRET removes virtual-NMI
blocking (even if the instruction generates a fault).
If the “NMI exiting” VM-execution control is 0, the “virtual NMIs” control must be 0; see Section 26.2.1.1.
•
Blocking of system-management interrupts (SMIs) is determined as follows:
— If the VM entry was not executed in system-management mode (SMM), SMI blocking is unchanged by
VM entry.
Vol. 3C 26-21
VM ENTRIES
— If the VM entry was executed in SMM, SMIs are blocked after VM entry if and only if the bit 2 in the interruptibility-state field is 1.
26.6.2
Activity State
The activity-state field in the guest-state area controls whether, after VM entry, the logical processor is active or in
one of the inactive states identified in Section 24.4.2. The use of this field is determined as follows:
•
If the VM entry is vectoring, the logical processor is in the active state after VM entry. While the consistency
checks described in Section 26.3.1.5 on the activity-state field do apply in this case, the contents of the
activity-state field do not determine the activity state after VM entry.
•
If the VM entry is not vectoring, the logical processor ends VM entry in the activity state specified in the gueststate area. If VM entry ends with the logical processor in an inactive activity state, the VM entry generates any
special bus cycle that is normally generated when that activity state is entered from the active state. If
VM entry would end with the logical processor in the shutdown state and the logical processor is in SMX
operation,1 an Intel® TXT shutdown condition occurs. The error code used is 0000H, indicating “legacy
shutdown.” See Intel® Trusted Execution Technology Preliminary Architecture Specification.
•
Some activity states unconditionally block certain events. The following blocking is in effect after any VM entry
that puts the processor in the indicated state:
— The active state blocks start-up IPIs (SIPIs). SIPIs that arrive while a logical processor is in the active state
and in VMX non-root operation are discarded and do not cause VM exits.
— The HLT state blocks start-up IPIs (SIPIs). SIPIs that arrive while a logical processor is in the HLT state and
in VMX non-root operation are discarded and do not cause VM exits.
— The shutdown state blocks external interrupts and SIPIs. External interrupts that arrive while a logical
processor is in the shutdown state and in VMX non-root operation do not cause VM exits even if the
“external-interrupt exiting” VM-execution control is 1. SIPIs that arrive while a logical processor is in the
shutdown state and in VMX non-root operation are discarded and do not cause VM exits.
— The wait-for-SIPI state blocks external interrupts, non-maskable interrupts (NMIs), INIT signals, and
system-management interrupts (SMIs). Such events do not cause VM exits if they arrive while a logical
processor is in the wait-for-SIPI state and in VMX non-root operation do not cause VM exits regardless of
the settings of the pin-based VM-execution controls.
26.6.3
Delivery of Pending Debug Exceptions after VM Entry
The pending debug exceptions field in the guest-state area indicates whether there are debug exceptions that have
not yet been delivered (see Section 24.4.2). This section describes how these are treated on VM entry.
There are no pending debug exceptions after VM entry if any of the following are true:
•
The VM entry is vectoring with one of the following interruption types: external interrupt, non-maskable
interrupt (NMI), hardware exception, or privileged software exception.
•
The interruptibility-state field does not indicate blocking by MOV SS and the VM entry is vectoring with either
of the following interruption type: software interrupt or software exception.
•
The VM entry is not vectoring and the activity-state field indicates either shutdown or wait-for-SIPI.
If none of the above hold, the pending debug exceptions field specifies the debug exceptions that are pending for
the guest. There are valid pending debug exceptions if either the BS bit (bit 14) or the enable-breakpoint bit
(bit 12) is 1. If there are valid pending debug exceptions, they are handled as follows:
•
If the VM entry is not vectoring, the pending debug exceptions are treated as they would had they been
encountered normally in guest execution:
— If the logical processor is not blocking such exceptions (the interruptibility-state field indicates no blocking
by MOV SS), a debug exception is delivered after VM entry (see below).
1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. See
Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
26-22 Vol. 3C
VM ENTRIES
— If the logical processor is blocking such exceptions (due to blocking by MOV SS), the pending debug
exceptions are held pending or lost as would normally be the case.
•
If the VM entry is vectoring (with interruption type software interrupt or software exception and with blocking
by MOV SS), the following items apply:
— For injection of a software interrupt or of a software exception with vector 3 (#BP) or vector 4 (#OF), the
pending debug exceptions are treated as they would had they been encountered normally in guest
execution if the corresponding instruction (INT3 or INTO) were executed after a MOV SS that encountered
a debug trap.
— For injection of a software exception with a vector other than 3 and 4, the pending debug exceptions may
be lost or they may be delivered after injection (see below).
If there are no valid pending debug exceptions (as defined above), no pending debug exceptions are delivered after
VM entry.
If a pending debug exception is delivered after VM entry, it has the priority of “traps on the previous instruction”
(see Section 6.9 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). Thus, INIT
signals and system-management interrupts (SMIs) take priority of such an exception, as do VM exits induced by
the TPR threshold (see Section 26.6.7) and pending MTF VM exits (see Section 26.6.8. The exception takes priority
over any pending non-maskable interrupt (NMI) or external interrupt and also over VM exits due to the 1-settings
of the “interrupt-window exiting” and “NMI-window exiting” VM-execution controls.
A pending debug exception delivered after VM entry causes a VM exit if the bit 1 (#DB) is 1 in the exception
bitmap. If it does not cause a VM exit, it updates DR6 normally.
26.6.4
VMX-Preemption Timer
If the “activate VMX-preemption timer” VM-execution control is 1, VM entry starts the VMX-preemption timer with
the unsigned value in the VMX-preemption timer-value field.
It is possible for the VMX-preemption timer to expire during VM entry (e.g., if the value in the VMX-preemption
timer-value field is zero). If this happens (and if the VM entry was not to the wait-for-SIPI state), a VM exit occurs
with its normal priority after any event injection and before execution of any instruction following VM entry. For
example, any pending debug exceptions established by VM entry (see Section 26.6.3) take priority over a timerinduced VM exit. (The timer-induced VM exit will occur after delivery of the debug exception, unless that exception
or its delivery causes a different VM exit.)
See Section 25.5.1 for details of the operation of the VMX-preemption timer in VMX non-root operation, including
the blocking and priority of the VM exits that it causes.
26.6.5
Interrupt-Window Exiting and Virtual-Interrupt Delivery
If “interrupt-window exiting” VM-execution control is 1, an open interrupt window may cause a VM exit immediately after VM entry (see Section 25.2 for details). If the “interrupt-window exiting” VM-execution control is 0 but
the “virtual-interrupt delivery” VM-execution control is 1, a virtual interrupt may be delivered immediately after
VM entry (see Section 26.3.2.5 and Section 29.2.1).
The following items detail the treatment of these events:
•
•
These events occur after any event injection specified for VM entry.
•
These events wake the logical processor if it just entered the HLT state because of a VM entry (see Section
26.6.2). They do not occur if the logical processor just entered the shutdown state or the wait-for-SIPI state.
Non-maskable interrupts (NMIs) and higher priority events take priority over these events. These events take
priority over external interrupts and lower priority events.
26.6.6
NMI-Window Exiting
The “NMI-window exiting” VM-execution control may cause a VM exit to occur immediately after VM entry (see
Section 25.2 for details).
Vol. 3C 26-23
VM ENTRIES
The following items detail the treatment of these VM exits:
•
•
These VM exits follow event injection if such injection is specified for VM entry.
•
VM exits caused by this control wake the logical processor if it just entered either the HLT state or the shutdown
state because of a VM entry (see Section 26.6.2). They do not occur if the logical processor just entered the
wait-for-SIPI state.
Debug-trap exceptions (see Section 26.6.3) and higher priority events take priority over VM exits caused by
this control. VM exits caused by this control take priority over non-maskable interrupts (NMIs) and lower
priority events.
26.6.7
VM Exits Induced by the TPR Threshold
If the “use TPR shadow” and “virtualize APIC accesses” VM-execution controls are both 1 and the “virtual-interrupt
delivery” VM-execution control is 0, a VM exit occurs immediately after VM entry if the value of bits 3:0 of the TPR
threshold VM-execution control field is greater than the value of bits 7:4 of VTPR (see Section 29.1.1).1
The following items detail the treatment of these VM exits:
•
The VM exits are not blocked if RFLAGS.IF = 0 or by the setting of bits in the interruptibility-state field in gueststate area.
•
•
The VM exits follow event injection if such injection is specified for VM entry.
•
These VM exits wake the logical processor if it just entered the HLT state as part of a VM entry (see Section
26.6.2). They do not occur if the logical processor just entered the shutdown state or the wait-for-SIPI state.
VM exits caused by this control take priority over system-management interrupts (SMIs), INIT signals, and
lower priority events. They thus have priority over the VM exits described in Section 26.6.5, Section 26.6.6,
and Section 26.6.8, as well as any interrupts or debug exceptions that may be pending at the time of VM entry.
If such a VM exit is suppressed because the processor just entered the shutdown state, it occurs after the
delivery of any event that cause the logical processor to leave the shutdown state while remaining in VMX
non-root operation (e.g., due to an NMI that occurs while the “NMI-exiting” VM-execution control is 0).
•
The basic exit reason is “TPR below threshold.”
26.6.8
Pending MTF VM Exits
As noted in Section 26.5.2, VM entry may cause an MTF VM exit to be pending immediately after VM entry. The
following items detail the treatment of these VM exits:
•
System-management interrupts (SMIs), INIT signals, and higher priority events take priority over these
VM exits. These VM exits take priority over debug-trap exceptions and lower priority events.
•
These VM exits wake the logical processor if it just entered the HLT state because of a VM entry (see Section
26.6.2). They do not occur if the logical processor just entered the shutdown state or the wait-for-SIPI state.
26.6.9
VM Entries and Advanced Debugging Features
VM entries are not logged with last-branch records, do not produce branch-trace messages, and do not update the
branch-trace store.
1. “Virtualize APIC accesses” and “virtual-interrupt delivery” are secondary processor-based VM-execution controls. If bit 31 of the primary processor-based VM-execution controls is 0, VM entry functions as if these controls were 0. See Section 24.6.2.
26-24 Vol. 3C
VM ENTRIES
26.7
VM-ENTRY FAILURES DURING OR AFTER LOADING GUEST STATE
VM-entry failures due to the checks identified in Section 26.3.1 and failures during the MSR loading identified in
Section 26.4 are treated differently from those that occur earlier in VM entry. In these cases, the following steps
take place:
1. Information about the VM-entry failure is recorded in the VM-exit information fields:
— Exit reason.
•
Bits 15:0 of this field contain the basic exit reason. It is loaded with a number indicating the general
cause of the VM-entry failure. The following numbers are used:
33. VM-entry failure due to invalid guest state. A VM entry failed one of the checks identified in Section
26.3.1.
34. VM-entry failure due to MSR loading. A VM entry failed in an attempt to load MSRs (see Section
26.4).
41. VM-entry failure due to machine-check event. A machine-check event occurred during VM entry
(see Section 26.8).
•
•
Bit 31 is set to 1 to indicate a VM-entry failure.
The remainder of the field (bits 30:16) is cleared.
— Exit qualification. This field is set based on the exit reason.
•
VM-entry failure due to invalid guest state. In most cases, the exit qualification is cleared to 0. The
following non-zero values are used in the cases indicated:
1. Not used.
2. Failure was due to a problem loading the PDPTEs (see Section 26.3.1.6).
3. Failure was due to an attempt to inject a non-maskable interrupt (NMI) into a guest that is blocking
events through the STI blocking bit in the interruptibility-state field. Such failures are implementation-specific (see Section 26.3.1.5).
4. Failure was due to an invalid VMCS link pointer (see Section 26.3.1.5).
VM-entry checks on guest-state fields may be performed in any order. Thus, an indication by exit
qualification of one cause does not imply that there are not also other errors. Different processors
may give different exit qualifications for the same VMCS.
•
VM-entry failure due to MSR loading. The exit qualification is loaded to indicate which entry in the
VM-entry MSR-load area caused the problem (1 for the first entry, 2 for the second, etc.).
— All other VM-exit information fields are unmodified.
2. Processor state is loaded as would be done on a VM exit (see Section 27.5). If this results in
[CR4.PAE & CR0.PG & ~IA32_EFER.LMA] = 1, page-directory-pointer-table entries (PDPTEs) may be checked
and loaded (see Section 27.5.4).
3. The state of blocking by NMI is what it was before VM entry.
4. MSRs are loaded as specified in the VM-exit MSR-load area (see Section 27.6).
Although this process resembles that of a VM exit, many steps taken during a VM exit do not occur for these
VM-entry failures:
•
•
•
•
Most VM-exit information fields are not updated (see step 1 above).
The valid bit in the VM-entry interruption-information field is not cleared.
The guest-state area is not modified.
No MSRs are saved into the VM-exit MSR-store area.
26.8
MACHINE-CHECK EVENTS DURING VM ENTRY
If a machine-check event occurs during a VM entry, one of the following occurs:
Vol. 3C 26-25
VM ENTRIES
•
The machine-check event is handled as if it occurred before the VM entry:
— If CR4.MCE = 0, operation of the logical processor depends on whether the logical processor is in SMX
operation:1
•
If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs. The error code
used is 000CH, indicating “unrecoverable machine-check condition.”
•
If the logical processor is outside SMX operation, it goes to the shutdown state.
— If CR4.MCE = 1, a machine-check exception (#MC) is delivered through the IDT.
•
The machine-check event is handled after VM entry completes:
— If the VM entry ends with CR4.MCE = 0, operation of the logical processor depends on whether the logical
processor is in SMX operation:
•
If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs with error code
000CH (unrecoverable machine-check condition).
•
If the logical processor is outside SMX operation, it goes to the shutdown state.
— If the VM entry ends with CR4.MCE = 1, a machine-check exception (#MC) is generated:
•
•
•
If bit 18 (#MC) of the exception bitmap is 0, the exception is delivered through the guest IDT.
If bit 18 of the exception bitmap is 1, the exception causes a VM exit.
A VM-entry failure occurs as described in Section 26.7. The basic exit reason is 41, for “VM-entry failure due to
machine-check event.”
The first option is not used if the machine-check event occurs after any guest state has been loaded. The second
option is used only if VM entry is able to load all guest state.
1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last
execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B.
26-26 Vol. 3C
CHAPTER 27
VM EXITS
VM exits occur in response to certain instructions and events in VMX non-root operation as detailed in Section 25.1
through Section 25.2. VM exits perform the following operations:
1. Information about the cause of the VM exit is recorded in the VM-exit information fields and VM-entry control
fields are modified as described in Section 27.2.
2. Processor state is saved in the guest-state area (Section 27.3).
3. MSRs may be saved in the VM-exit MSR-store area (Section 27.4). This step is not performed for SMM VM exits
that activate the dual-monitor treatment of SMIs and SMM.
4. The following may be performed in parallel and in any order (Section 27.5):
— Processor state is loaded based in part on the host-state area and some VM-exit controls. This step is not
performed for SMM VM exits that activate the dual-monitor treatment of SMIs and SMM. See Section
34.15.6 for information on how processor state is loaded by such VM exits.
— Address-range monitoring is cleared.
5. MSRs may be loaded from the VM-exit MSR-load area (Section 27.6). This step is not performed for SMM
VM exits that activate the dual-monitor treatment of SMIs and SMM.
VM exits are not logged with last-branch records, do not produce branch-trace messages, and do not update the
branch-trace store.
Section 27.1 clarifies the nature of the architectural state before a VM exit begins. The steps described above are
detailed in Section 27.2 through Section 27.6.
Section 34.15 describes the dual-monitor treatment of system-management interrupts (SMIs) and systemmanagement mode (SMM). Under this treatment, ordinary transitions to SMM are replaced by VM exits to a separate SMM monitor. Called SMM VM exits, these are caused by the arrival of an SMI or the execution of VMCALL in
VMX root operation. SMM VM exits differ from other VM exits in ways that are detailed in Section 34.15.2.
27.1
ARCHITECTURAL STATE BEFORE A VM EXIT
This section describes the architectural state that exists before a VM exit, especially for VM exits caused by events
that would normally be delivered through the IDT. Note the following:
•
An exception causes a VM exit directly if the bit corresponding to that exception is set in the exception bitmap.
A non-maskable interrupt (NMI) causes a VM exit directly if the “NMI exiting” VM-execution control is 1. An
external interrupt causes a VM exit directly if the “external-interrupt exiting” VM-execution control is 1. A startup IPI (SIPI) that arrives while a logical processor is in the wait-for-SIPI activity state causes a VM exit directly.
INIT signals that arrive while the processor is not in the wait-for-SIPI activity state cause VM exits directly.
•
An exception, NMI, external interrupt, or software interrupt causes a VM exit indirectly if it does not do so
directly but delivery of the event causes a nested exception, double fault, task switch, APIC access (see Section
27.4), EPT violation, EPT misconfiguration, or page-modification log-full event that causes a VM exit.
•
An event results in a VM exit if it causes a VM exit (directly or indirectly).
The following bullets detail when architectural state is and is not updated in response to VM exits:
•
If an event causes a VM exit directly, it does not update architectural state as it would have if it had it not
caused the VM exit:
— A debug exception does not update DR6, DR7.GD, or IA32_DEBUGCTL.LBR. (Information about the nature
of the debug exception is saved in the exit qualification field.)
— A page fault does not update CR2. (The linear address causing the page fault is saved in the exit-qualification field.)
— An NMI causes subsequent NMIs to be blocked, but only after the VM exit completes.
Vol. 3C 27-1
VM EXITS
— An external interrupt does not acknowledge the interrupt controller and the interrupt remains pending,
unless the “acknowledge interrupt on exit” VM-exit control is 1. In such a case, the interrupt controller is
acknowledged and the interrupt is no longer pending.
— The flags L0 – L3 in DR7 (bit 0, bit 2, bit 4, and bit 6) are not cleared when a task switch causes a VM exit.
— If a task switch causes a VM exit, none of the following are modified by the task switch: old task-state
segment (TSS); new TSS; old TSS descriptor; new TSS descriptor; RFLAGS.NT1; or the TR register.
— No last-exception record is made if the event that would do so directly causes a VM exit.
— If a machine-check exception causes a VM exit directly, this does not prevent machine-check MSRs from
being updated. These are updated by the machine-check event itself and not the resulting machine-check
exception.
— If the logical processor is in an inactive state (see Section 24.4.2) and not executing instructions, some
events may be blocked but others may return the logical processor to the active state. Unblocked events
may cause VM exits.2 If an unblocked event causes a VM exit directly, a return to the active state occurs
only after the VM exit completes.3 The VM exit generates any special bus cycle that is normally generated
when the active state is entered from that activity state.
MTF VM exits (see Section 25.5.2 and Section 26.6.8) are not blocked in the HLT activity state. If an MTF
VM exit occurs in the HLT activity state, the logical processor returns to the active state only after the
VM exit completes. MTF VM exits are blocked the shutdown state and the wait-for-SIPI state.
•
If an event causes a VM exit indirectly, the event does update architectural state:
— A debug exception updates DR6, DR7, and the IA32_DEBUGCTL MSR. No debug exceptions are considered
pending.
— A page fault updates CR2.
— An NMI causes subsequent NMIs to be blocked before the VM exit commences.
— An external interrupt acknowledges the interrupt controller and the interrupt is no longer pending.
— If the logical processor had been in an inactive state, it enters the active state and, before the VM exit
commences, generates any special bus cycle that is normally generated when the active state is entered
from that activity state.
— There is no blocking by STI or by MOV SS when the VM exit commences.
— Processor state that is normally updated as part of delivery through the IDT (CS, RIP, SS, RSP, RFLAGS) is
not modified. However, the incomplete delivery of the event may write to the stack.
— The treatment of last-exception records is implementation dependent:
•
•
Some processors make a last-exception record when beginning the delivery of an event through the IDT
(before it can encounter a nested exception). Such processors perform this update even if the event
encounters a nested exception that causes a VM exit (including the case where nested exceptions lead
to a triple fault).
•
Other processors delay making a last-exception record until event delivery has reached some event
handler successfully (perhaps after one or more nested exceptions). Such processors do not update the
last-exception record if a VM exit or triple fault occurs before an event handler is reached.
If the “virtual NMIs” VM-execution control is 1, VM entry injects an NMI, and delivery of the NMI causes a
nested exception, double fault, task switch, or APIC access that causes a VM exit, virtual-NMI blocking is in
effect before the VM exit commences.
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX operation also support Intel 64 architecture. For processors that do not support Intel 64 architecture, this notation refers to the 32-bit
forms of those registers (EAX, EIP, ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to lower 32
bits of the indicated register.
2. If a VM exit takes the processor from an inactive state resulting from execution of a specific instruction (HLT or MWAIT), the value
saved for RIP by that VM exit will reference the following instruction.
3. An exception is made if the logical processor had been inactive due to execution of MWAIT; in this case, it is considered to have
become active before the VM exit.
27-2 Vol. 3C
VM EXITS
•
If a VM exit results from a fault, EPT violation, EPT misconfiguration, or page-modification log-full event is
encountered during execution of IRET and the “NMI exiting” VM-execution control is 0, any blocking by NMI is
cleared before the VM exit commences. However, the previous state of blocking by NMI may be recorded in the
VM-exit interruption-information field; see Section 27.2.2.
•
If a VM exit results from a fault, EPT violation, EPT misconfiguration, or page-modification log-full event is
encountered during execution of IRET and the “virtual NMIs” VM-execution control is 1, virtual-NMI blocking is
cleared before the VM exit commences. However, the previous state of virtual-NMI blocking may be recorded
in the VM-exit interruption-information field; see Section 27.2.2.
•
Suppose that a VM exit is caused directly by an x87 FPU Floating-Point Error (#MF) or by any of the following
events if the event was unblocked due to (and given priority over) an x87 FPU Floating-Point Error: an INIT
signal, an external interrupt, an NMI, an SMI; or a machine-check exception. In these cases, there is no
blocking by STI or by MOV SS when the VM exit commences.
•
Normally, a last-branch record may be made when an event is delivered through the IDT. However, if such an
event results in a VM exit before delivery is complete, no last-branch record is made.
•
If machine-check exception results in a VM exit, processor state is suspect and may result in suspect state
being saved to the guest-state area. A VM monitor should consult the RIPV and EIPV bits in the
IA32_MCG_STATUS MSR before resuming a guest that caused a VM exit resulting from a machine-check
exception.
•
If a VM exit results from a fault, APIC access (see Section 29.4), EPT violation, EPT misconfiguration, or pagemodification log-full event is encountered while executing an instruction, data breakpoints due to that
instruction may have been recognized and information about them may be saved in the pending debug
exceptions field (see Section 27.3.4).
•
The following VM exits are considered to happen after an instruction is executed:
— VM exits resulting from debug traps (single-step, I/O breakpoints, and data breakpoints).
— VM exits resulting from debug exceptions whose recognition was delayed by blocking by MOV SS.
— VM exits resulting from some machine-check exceptions.
— Trap-like VM exits due to execution of MOV to CR8 when the “CR8-load exiting” VM-execution control is 0
and the “use TPR shadow” VM-execution control is 1 (see Section 29.3). (Such VM exits can occur only from
64-bit mode and thus only on processors that support Intel 64 architecture.)
— Trap-like VM exits due to execution of WRMSR when the “use MSR bitmaps” VM-execution control is 1; the
value of ECX is in the range 800H–8FFH; and the bit corresponding to the ECX value in write bitmap for low
MSRs is 0; and the “virtualize x2APIC mode” VM-execution control is 1. See Section 29.5.
— VM exits caused by APIC-write emulation (see Section 29.4.3.2) that result from APIC accesses as part of
instruction execution.
For these VM exits, the instruction’s modifications to architectural state complete before the VM exit occurs.
Such modifications include those to the logical processor’s interruptibility state (see Table 24-3). If there had
been blocking by MOV SS, POP SS, or STI before the instruction executed, such blocking is no longer in effect.
A VM exit that occurs in enclave mode sets bit 27 of the exit-reason field and bit 4 of the guest interruptibility-state
field. Before such a VM exit is delivered, an Asynchronous Enclave Exit (AEX) occurs (see Chapter 40, “Enclave
Exiting Events”). An AEX modifies architectural state (Section 40.3). In particular, the processor establishes the
following architectural state as indicated:
•
•
•
•
The following bits in RFLAGS are cleared: CF, PF, AF, ZF, SF, OF, and RF.
FS and GS are restored to the values they had prior to the most recent enclave entry.
RIP is loaded with the AEP of interrupted enclave thread.
RSP is loaded from the URSP field in the enclave’s state-save area (SSA).
Vol. 3C 27-3
VM EXITS
27.2
RECORDING VM-EXIT INFORMATION AND UPDATING VM-ENTRY CONTROL
FIELDS
VM exits begin by recording information about the nature of and reason for the VM exit in the VM-exit information
fields. Section 27.2.1 to Section 27.2.4 detail the use of these fields.
In addition to updating the VM-exit information fields, the valid bit (bit 31) is cleared in the VM-entry interruptioninformation field. If bit 5 of the IA32_VMX_MISC MSR (index 485H) is read as 1 (see Appendix A.6), the value of
IA32_EFER.LMA is stored into the “IA-32e mode guest” VM-entry control.1
27.2.1
Basic VM-Exit Information
Section 24.9.1 defines the basic VM-exit information fields. The following items detail their use.
•
Exit reason.
— Bits 15:0 of this field contain the basic exit reason. It is loaded with a number indicating the general cause
of the VM exit. Appendix C lists the numbers used and their meaning.
— Bit 27 of this field is set to 1 if the VM exit occurred while the logical processor was in enclave mode.
Such VM exits includes those caused by interrupts, non-maskable interrupts, system-management
interrupts, INIT signals, and exceptions occurring in enclave mode as well as exceptions encountered
during the delivery of such events incident to enclave mode.
A VM exit also sets this bit if it is incident to delivery of an event injected by VM entry and the guest interruptibility-state field indicates an enclave interrupt (bit 4 of the field is 1).
— The remainder of the field (bits 31:28 and bits 26:16) is cleared to 0 (certain SMM VM exits may set some
of these bits; see Section 34.15.2.3).2
•
Exit qualification. This field is saved for VM exits due to the following causes: debug exceptions; page-fault
exceptions; start-up IPIs (SIPIs); system-management interrupts (SMIs) that arrive immediately after the
retirement of I/O instructions; task switches; INVEPT; INVLPG; INVPCID; INVVPID; LGDT; LIDT; LLDT; LTR;
SGDT; SIDT; SLDT; STR; VMCLEAR; VMPTRLD; VMPTRST; VMREAD; VMWRITE; VMXON; XRSTORS; XSAVES;
control-register accesses; MOV DR; I/O instructions; MWAIT; accesses to the APIC-access page (see Section
29.4); EPT violations; EOI virtualization (see Section 29.1.4); APIC-write emulation (see Section 29.4.3.3);
and page-modification log full (see Section 28.2.5). For all other VM exits, this field is cleared. The following
items provide details:
— For a debug exception, the exit qualification contains information about the debug exception. The
information has the format given in Table 27-1.
Table 27-1. Exit Qualification for Debug Exceptions
Bit Position(s)
Contents
3:0
B3 – B0. When set, each of these bits indicates that the corresponding breakpoint condition was met. Any of
these bits may be set even if its corresponding enabling bit in DR7 is not set.
12:4
Reserved (cleared to 0).
13
BD. When set, this bit indicates that the cause of the debug exception is “debug register access detected.”
14
BS. When set, this bit indicates that the cause of the debug exception is either the execution of a single
instruction (if RFLAGS.TF = 1 and IA32_DEBUGCTL.BTF = 0) or a taken branch (if
RFLAGS.TF = DEBUGCTL.BTF = 1).
63:15
Reserved (cleared to 0). Bits 63:32 exist only on processors that support Intel 64 architecture.
1. Bit 5 of the IA32_VMX_MISC MSR is read as 1 on any logical processor that supports the 1-setting of the “unrestricted guest” VMexecution control.
2. Bit 31 of this field is set on certain VM-entry failures; see Section 26.7.
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VM EXITS
— For a page-fault exception, the exit qualification contains the linear address that caused the page fault. On
processors that support Intel 64 architecture, bits 63:32 are cleared if the logical processor was not in 64bit mode before the VM exit.
If the page-fault exception occurred during execution of an instruction in enclave mode (and not during
delivery of an event incident to enclave mode), bits 11:0 of the exit qualification are cleared.
— For a start-up IPI (SIPI), the exit qualification contains the SIPI vector information in bits 7:0. Bits 63:8 of
the exit qualification are cleared to 0.
— For a task switch, the exit qualification contains details about the task switch, encoded as shown in
Table 27-2.
— For INVLPG, the exit qualification contains the linear-address operand of the instruction.
•
On processors that support Intel 64 architecture, bits 63:32 are cleared if the logical processor was not
in 64-bit mode before the VM exit.
•
If the INVLPG source operand specifies an unusable segment, the linear address specified in the exit
qualification will match the linear address that the INVLPG would have used if no VM exit occurred. This
address is not architecturally defined and may be implementation-specific.
Table 27-2. Exit Qualification for Task Switch
Bit Position(s)
Contents
15:0
Selector of task-state segment (TSS) to which the guest attempted to switch
29:16
Reserved (cleared to 0)
31:30
Source of task switch initiation:
0: CALL instruction
1: IRET instruction
2: JMP instruction
3: Task gate in IDT
63:32
Reserved (cleared to 0). These bits exist only on processors that support Intel 64 architecture.
— For INVEPT, INVPCID, INVVPID, LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, STR, VMCLEAR, VMPTRLD,
VMPTRST, VMREAD, VMWRITE, VMXON, XRSTORS, and XSAVES, the exit qualification receives the value of
the instruction’s displacement field, which is sign-extended to 64 bits if necessary (32 bits on processors
that do not support Intel 64 architecture). If the instruction has no displacement (for example, has a
register operand), zero is stored into the exit qualification.
On processors that support Intel 64 architecture, an exception is made for RIP-relative addressing (used
only in 64-bit mode). Such addressing causes an instruction to use an address that is the sum of the
displacement field and the value of RIP that references the following instruction. In this case, the exit
qualification is loaded with the sum of the displacement field and the appropriate RIP value.
In all cases, bits of this field beyond the instruction’s address size are undefined. For example, suppose
that the address-size field in the VM-exit instruction-information field (see Section 24.9.4 and Section
27.2.4) reports an n-bit address size. Then bits 63:n (bits 31:n on processors that do not support Intel 64
architecture) of the instruction displacement are undefined.
— For a control-register access, the exit qualification contains information about the access and has the
format given in Table 27-3.
— For MOV DR, the exit qualification contains information about the instruction and has the format given in
Table 27-4.
— For an I/O instruction, the exit qualification contains information about the instruction and has the format
given in Table 27-5.
Vol. 3C 27-5
VM EXITS
— For MWAIT, the exit qualification contains a value that indicates whether address-range monitoring
hardware was armed. The exit qualification is set either to 0 (if address-range monitoring hardware is not
armed) or to 1 (if address-range monitoring hardware is armed).
— For an APIC-access VM exit resulting from a linear access or a guest-physical access to the APIC-access
page (see Section 29.4), the exit qualification contains information about the access and has the format
given in Table 27-6.1
If the access to the APIC-access page occurred during execution of an instruction in enclave mode (and not
during delivery of an event incident to enclave mode), bits 11:0 of the exit qualification are cleared.
Such a VM exit that set bits 15:12 of the exit qualification to 0000b (data read during instruction execution)
or 0001b (data write during instruction execution) set bit 12—which distinguishes data read from data
write—to that which would have been stored in bit 1—W/R—of the page-fault error code had the access
caused a page fault instead of an APIC-access VM exit. This implies the following:
•
For an APIC-access VM exit caused by the CLFLUSH and CLFLUSHOPT instructions, the access type is
“data read during instruction execution.”
•
For an APIC-access VM exit caused by the ENTER instruction, the access type is “data write during
instruction execution.”
Table 27-3. Exit Qualification for Control-Register Accesses
Bit Positions
Contents
3:0
Number of control register (0 for CLTS and LMSW). Bit 3 is always 0 on processors that do not support Intel 64
architecture as they do not support CR8.
5:4
Access type:
0 = MOV to CR
1 = MOV from CR
2 = CLTS
3 = LMSW
6
LMSW operand type:
0 = register
1 = memory
For CLTS and MOV CR, cleared to 0
7
Reserved (cleared to 0)
11:8
For MOV CR, the general-purpose register:
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)
For CLTS and LMSW, cleared to 0
15:12
Reserved (cleared to 0)
1. The exit qualification is undefined if the access was part of the logging of a branch record or a precise-event-based-sampling (PEBS)
record to the DS save area. It is recommended that software configure the paging structures so that no address in the DS save area
translates to an address on the APIC-access page.
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VM EXITS
Table 27-3. Exit Qualification for Control-Register Accesses (Contd.)
Bit Positions
31:16
Contents
For LMSW, the LMSW source data
For CLTS and MOV CR, cleared to 0
63:32
Reserved (cleared to 0). These bits exist only on processors that support Intel 64 architecture.
•
For an APIC-access VM exit caused by the MASKMOVQ instruction or the MASKMOVDQU instruction, the
access type is “data write during instruction execution.”
•
For an APIC-access VM exit caused by the MONITOR instruction, the access type is “data read during
instruction execution.”
Such a VM exit stores 1 for bit 31 for IDT-vectoring information field (see Section 27.2.3) if and only if it
sets bits 15:12 of the exit qualification to 0011b (linear access during event delivery) or 1010b (guestphysical access during event delivery).
See Section 29.4.4 for further discussion of these instructions and APIC-access VM exits.
For APIC-access VM exits resulting from physical accesses to the APIC-access page (see Section 29.4.6),
the exit qualification is undefined.
— For an EPT violation, the exit qualification contains information about the access causing the EPT violation
and has the format given in Table 27-7.
As noted in that table, the format and meaning of the exit qualification depends on the setting of the
“mode-based execute control for EPT” VM-execution control and whether the processor supports advanced
VM-exit information for EPT violations.1
An EPT violation that occurs during as a result of execution of a read-modify-write operation sets bit 1 (data
write). Whether it also sets bit 0 (data read) is implementation-specific and, for a given implementation,
may differ for different kinds of read-modify-write operations.
Table 27-4. Exit Qualification for MOV DR
Bit Position(s)
Contents
2:0
Number of debug register
3
Reserved (cleared to 0)
4
Direction of access (0
7:5
Reserved (cleared to 0)
11:8
General-purpose register:
= MOV to DR; 1 = MOV from DR)
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8 –15 = R8 – R15, respectively
63:12
Reserved (cleared to 0)
1. Software can determine whether advanced VM-exit information for EPT violations is supported by consulting the VMX capability
MSR IA32_VMX_EPT_VPID_CAP (see Appendix A.10).
Vol. 3C 27-7
VM EXITS
Table 27-5. Exit Qualification for I/O Instructions
Bit Position(s)
Contents
2:0
Size of access:
0 = 1-byte
1 = 2-byte
3 = 4-byte
Other values not used
3
Direction of the attempted access (0 = OUT, 1
4
String instruction (0 = not string; 1 = string)
5
REP prefixed (0 = not REP; 1 = REP)
6
Operand encoding (0 = DX, 1 = immediate)
15:7
Reserved (cleared to 0)
31:16
Port number (as specified in DX or in an immediate operand)
63:32
Reserved (cleared to 0). These bits exist only on processors that support Intel 64 architecture.
= IN)
Bit 12 is undefined in any of the following cases:
•
•
If the “NMI exiting” VM-execution control is 1 and the “virtual NMIs” VM-execution control is 0.
If the VM exit sets the valid bit in the IDT-vectoring information field (see Section 27.2.3).
Otherwise, bit 12 is defined as follows:
•
If the “virtual NMIs” VM-execution control is 0, the EPT violation was caused by a memory access as
part of execution of the IRET instruction, and blocking by NMI (see Table 24-3) was in effect before
execution of IRET, bit 12 is set to 1.
Table 27-6. Exit Qualification for APIC-Access VM Exits from Linear Accesses and Guest-Physical Accesses
Bit Position(s)
Contents
11:0
• If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page.
• Undefined if the APIC-access VM exit is due a guest-physical access
15:12
Access type:
0 = linear access for a data read during instruction execution
1 = linear access for a data write during instruction execution
2 = linear access for an instruction fetch
3 = linear access (read or write) during event delivery
10 = guest-physical access during event delivery
15 = guest-physical access for an instruction fetch or during instruction execution
Other values not used
63:16
27-8 Vol. 3C
Reserved (cleared to 0). Bits 63:32 exist only on processors that support Intel 64 architecture.
VM EXITS
•
If the “virtual NMIs” VM-execution control is 1,the EPT violation was caused by a memory access as part
of execution of the IRET instruction, and virtual-NMI blocking was in effect before execution of IRET,
bit 12 is set to 1.
•
For all other relevant VM exits, bit 12 is cleared to 0.
— For VM exits caused as part of EOI virtualization (Section 29.1.4), bits 7:0 of the exit qualification are set
to vector of the virtual interrupt that was dismissed by the EOI virtualization. Bits above bit 7 are cleared.
— For APIC-write VM exits (Section 29.4.3.3), bits 11:0 of the exit qualification are set to the page offset of
the write access that caused the VM exit.1 Bits above bit 11 are cleared.
— For a VM exit due to a page-modification log-full event (Section 28.2.5), only bit 12 of the exit qualification
is defined, and only in some cases. It is undefined in the following cases:
•
•
If the “NMI exiting” VM-execution control is 1 and the “virtual NMIs” VM-execution control is 0.
If the VM exit sets the valid bit in the IDT-vectoring information field (see Section 27.2.3).
Otherwise, it is defined as follows:
•
If the “virtual NMIs” VM-execution control is 0, the page-modification log-full event was caused by a
memory access as part of execution of the IRET instruction, and blocking by NMI (see Table 24-3) was
in effect before execution of IRET, bit 12 is set to 1.
•
If the “virtual NMIs” VM-execution control is 1,the page-modification log-full event was caused by a
memory access as part of execution of the IRET instruction, and virtual-NMI blocking was in effect
before execution of IRET, bit 12 is set to 1.
•
For all other relevant VM exits, bit 12 is cleared to 0.
For these VM exits, all bits other than bit 12 are undefined.
•
Guest-linear address. For some VM exits, this field receives a linear address that pertains to the VM exit. The
field is set for different VM exits as follows:
— VM exits due to attempts to execute LMSW with a memory operand. In these cases, this field receives the
linear address of that operand. Bits 63:32 are cleared if the logical processor was not in 64-bit mode before
the VM exit.
— VM exits due to attempts to execute INS or OUTS for which the relevant segment is usable (if the relevant
segment is not usable, the value is undefined). (ES is always the relevant segment for INS; for OUTS, the
relevant segment is DS unless overridden by an instruction prefix.) The linear address is the base address
of relevant segment plus (E)DI (for INS) or (E)SI (for OUTS). Bits 63:32 are cleared if the logical processor
was not in 64-bit mode before the VM exit.
Table 27-7. Exit Qualification for EPT Violations
Bit Position(s)
Contents
0
Set if the access causing the EPT violation was a data read.1
1
Set if the access causing the EPT violation was a data write.1
2
Set if the access causing the EPT violation was an instruction fetch.
3
The logical-AND of bit 0 in the EPT paging-structure entries used to translate the guest-physical address of the
access causing the EPT violation (indicates whether the guest-physical address was readable).2
4
The logical-AND of bit 1 in the EPT paging-structure entries used to translate the guest-physical address of the
access causing the EPT violation (indicates whether the guest-physical address was writeable).
1. Execution of WRMSR with ECX = 83FH (self-IPI MSR) can lead to an APIC-write VM exit; the exit qualification for such an APIC-write
VM exit is 3F0H.
Vol. 3C 27-9
VM EXITS
Table 27-7. Exit Qualification for EPT Violations (Contd.)
Bit Position(s)
Contents
5
The logical-AND of bit 2 in the EPT paging-structure entries used to translate the guest-physical address of the
access causing the EPT violation.
If the “mode-based execute control for EPT” VM-execution control is 0, this indicates whether the guest-physical
address was executable. If that control is 1, this indicates whether the guest-physical address was executable
for supervisor-mode linear addresses.
6
If the “mode-based execute control” VM-execution control is 0, the value of this bit is undefined. If that control is
1, this bit is the logical-AND of bit 10 in the EPT paging-structures entries used to translate the guest-physical
address of the access causing the EPT violation. In this case, it indicates whether the guest-physical address was
executable for user-mode linear addresses.
7
Set if the guest linear-address field is valid.
The guest linear-address field is valid for all EPT violations except those resulting from an attempt to load the
guest PDPTEs as part of the execution of the MOV CR instruction.
8
If bit 7 is 1:
• Set if the access causing the EPT violation is to a guest-physical address that is the translation of a linear
address.
• Clear if the access causing the EPT violation is to a paging-structure entry as part of a page walk or the
update of an accessed or dirty bit.
Reserved if bit 7 is 0 (cleared to 0).
9
If bit 7 is 1, bit 8 is 1, and the processor supports advanced VM-exit information for EPT violations,3 this bit is 0
if the linear address is a supervisor-mode linear address and 1 if it is a user-mode linear address. (If CR0.PG = 0,
the translation of every linear address is a user-mode linear address and thus this bit will be 1.) Otherwise, this
bit is undefined.
10
If bit 7 is 1, bit 8 is 1, and the processor supports advanced VM-exit information for EPT violations,3 this bit is 0
if paging translates the linear address to a read-only page and 1 if it translates to a read/write page. (If CR0.PG =
0, every linear address is read/write and thus this bit will be 1.) Otherwise, this bit is undefined.
11
If bit 7 is 1, bit 8 is 1, and the processor supports advanced VM-exit information for EPT violations,3 this bit is 0
if paging translates the linear address to an executable page and 1 if it translates to an execute-disable page. (If
CR0.PG = 0, CR4.PAE = 0, or IA32_EFER.NXE = 0, every linear address is executable and thus this bit will be 0.)
Otherwise, this bit is undefined.
12
NMI unblocking due to IRET
63:13
Reserved (cleared to 0).
NOTES:
1. If accessed and dirty flags for EPT are enabled, processor accesses to guest paging-structure entries are treated as writes with
regard to EPT violations (see Section 28.2.3.2). If such an access causes an EPT violation, the processor sets both bit 0 and bit 1 of
the exit qualification.
2. Bits 5:3 are cleared to 0 if any of EPT paging-structure entries used to translate the guest-physical address of the access causing the
EPT violation is not present (see Section 28.2.2).
3. Software can determine whether advanced VM-exit information for EPT violations is supported by consulting the VMX capability
MSR IA32_VMX_EPT_VPID_CAP (see Appendix A.10).
— VM exits due to EPT violations that set bit 7 of the exit qualification (see Table 27-7; these are all EPT
violations except those resulting from an attempt to load the PDPTEs as of execution of the MOV CR
instruction). The linear address may translate to the guest-physical address whose access caused the EPT
violation. Alternatively, translation of the linear address may reference a paging-structure entry whose
access caused the EPT violation. Bits 63:32 are cleared if the logical processor was not in 64-bit mode
before the VM exit.
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VM EXITS
If the EPT violation occurred during execution of an instruction in enclave mode (and not during delivery of
an event incident to enclave mode), bits 11:0 of this field are cleared.
— For all other VM exits, the field is undefined.
•
Guest-physical address. For a VM exit due to an EPT violation or an EPT misconfiguration, this field receives
the guest-physical address that caused the EPT violation or EPT misconfiguration. For all other VM exits, the
field is undefined.
If the EPT violation or EPT misconfiguration occurred during execution of an instruction in enclave mode (and
not during delivery of an event incident to enclave mode), bits 11:0 of this field are cleared.
27.2.2
Information for VM Exits Due to Vectored Events
Section 24.9.2 defines fields containing information for VM exits due to the following events: exceptions (including
those generated by the instructions INT3, INTO, BOUND, and UD2); external interrupts that occur while the
“acknowledge interrupt on exit” VM-exit control is 1; and non-maskable interrupts (NMIs). Such VM exits include
those that occur on an attempt at a task switch that causes an exception before generating the VM exit due to the
task switch that causes the VM exit.
The following items detail the use of these fields:
•
VM-exit interruption information (format given in Table 24-15). The following items detail how this field is
established for VM exits due to these events:
— For an exception, bits 7:0 receive the exception vector (at most 31). For an NMI, bits 7:0 are set to 2. For
an external interrupt, bits 7:0 receive the vector.
— Bits 10:8 are set to 0 (external interrupt), 2 (non-maskable interrupt), 3 (hardware exception), or 6
(software exception). Hardware exceptions comprise all exceptions except breakpoint exceptions (#BP;
generated by INT3) and overflow exceptions (#OF; generated by INTO); these are software exceptions. (A
#BP that occurs in enclave mode is considered a hardware exception.) BOUND-range exceeded exceptions
(#BR; generated by BOUND) and invalid opcode exceptions (#UD) generated by UD2 are hardware
exceptions.
— Bit 11 is set to 1 if the VM exit is caused by a hardware exception that would have delivered an error code
on the stack. This bit is always 0 if the VM exit occurred while the logical processor was in real-address
mode (CR0.PE=0).1 If bit 11 is set to 1, the error code is placed in the VM-exit interruption error code (see
below).
— Bit 12 is undefined in any of the following cases:
•
•
•
If the “NMI exiting” VM-execution control is 1 and the “virtual NMIs” VM-execution control is 0.
If the VM exit sets the valid bit in the IDT-vectoring information field (see Section 27.2.3).
If the VM exit is due to a double fault (the interruption type is hardware exception and the vector is 8).
Otherwise, bit 12 is defined as follows:
•
If the “virtual NMIs” VM-execution control is 0, the VM exit is due to a fault on the IRET instruction
(other than a debug exception for an instruction breakpoint), and blocking by NMI (see Table 24-3) was
in effect before execution of IRET, bit 12 is set to 1.
•
If the “virtual NMIs” VM-execution control is 1, the VM exit is due to a fault on the IRET instruction
(other than a debug exception for an instruction breakpoint), and virtual-NMI blocking was in effect
before execution of IRET, bit 12 is set to 1.
•
For all other relevant VM exits, bit 12 is cleared to 0.2
— Bits 30:13 are always set to 0.
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, a logical processor cannot be in realaddress mode unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
2. The conditions imply that, if the “NMI exiting” VM-execution control is 0 or the “virtual NMIs” VM-execution control is 1, bit 12 is
always cleared to 0 by VM exits due to debug exceptions.
Vol. 3C 27-11
VM EXITS
— Bit 31 is always set to 1.
For other VM exits (including those due to external interrupts when the “acknowledge interrupt on exit” VM-exit
control is 0), the field is marked invalid (by clearing bit 31) and the remainder of the field is undefined.
•
VM-exit interruption error code.
— For VM exits that set both bit 31 (valid) and bit 11 (error code valid) in the VM-exit interruption-information
field, this field receives the error code that would have been pushed on the stack had the event causing the
VM exit been delivered normally through the IDT. The EXT bit is set in this field exactly when it would be set
normally. For exceptions that occur during the delivery of double fault (if the IDT-vectoring information field
indicates a double fault), the EXT bit is set to 1, assuming that (1) that the exception would produce an
error code normally (if not incident to double-fault delivery) and (2) that the error code uses the EXT bit
(not for page faults, which use a different format).
— For other VM exits, the value of this field is undefined.
27.2.3
Information for VM Exits During Event Delivery
Section 24.9.3 defined fields containing information for VM exits that occur while delivering an event through the
IDT and as a result of any of the following cases:1
•
A fault occurs during event delivery and causes a VM exit (because the bit associated with the fault is set to 1
in the exception bitmap).
•
A task switch is invoked through a task gate in the IDT. The VM exit occurs due to the task switch only after the
initial checks of the task switch pass (see Section 25.4.2).
•
•
Event delivery causes an APIC-access VM exit (see Section 29.4).
An EPT violation, EPT misconfiguration, or page-modification log-full event that occurs during event delivery.
These fields are used for VM exits that occur during delivery of events injected as part of VM entry (see Section
26.5.1.2).
A VM exit is not considered to occur during event delivery in any of the following circumstances:
•
The original event causes the VM exit directly (for example, because the original event is a non-maskable
interrupt (NMI) and the “NMI exiting” VM-execution control is 1).
•
•
•
The original event results in a double-fault exception that causes the VM exit directly.
The VM exit occurred as a result of fetching the first instruction of the handler invoked by the event delivery.
The VM exit is caused by a triple fault.
The following items detail the use of these fields:
•
IDT-vectoring information (format given in Table 24-16). The following items detail how this field is established
for VM exits that occur during event delivery:
— If the VM exit occurred during delivery of an exception, bits 7:0 receive the exception vector (at most 31).
If the VM exit occurred during delivery of an NMI, bits 7:0 are set to 2. If the VM exit occurred during
delivery of an external interrupt, bits 7:0 receive the vector.
— Bits 10:8 are set to indicate the type of event that was being delivered when the VM exit occurred: 0
(external interrupt), 2 (non-maskable interrupt), 3 (hardware exception), 4 (software interrupt), 5
(privileged software interrupt), or 6 (software exception).
Hardware exceptions comprise all exceptions except breakpoint exceptions (#BP; generated by INT3) and
overflow exceptions (#OF; generated by INTO); these are software exceptions. (A #BP that occurs in
enclave mode is considered a hardware exception.) BOUND-range exceeded exceptions (#BR; generated
by BOUND) and invalid opcode exceptions (#UD) generated by UD2 are hardware exceptions.
Bits 10:8 may indicate privileged software interrupt if such an event was injected as part of VM entry.
1. This includes the case in which a VM exit occurs while delivering a software interrupt (INT n) through the 16-bit IVT (interrupt vector table) that is used in virtual-8086 mode with virtual-machine extensions (if RFLAGS.VM = CR4.VME = 1).
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VM EXITS
— Bit 11 is set to 1 if the VM exit occurred during delivery of a hardware exception that would have delivered
an error code on the stack. This bit is always 0 if the VM exit occurred while the logical processor was in
real-address mode (CR0.PE=0).1 If bit 11 is set to 1, the error code is placed in the IDT-vectoring error
code (see below).
— Bit 12 is undefined.
— Bits 30:13 are always set to 0.
— Bit 31 is always set to 1.
For other VM exits, the field is marked invalid (by clearing bit 31) and the remainder of the field is undefined.
•
IDT-vectoring error code.
— For VM exits that set both bit 31 (valid) and bit 11 (error code valid) in the IDT-vectoring information field,
this field receives the error code that would have been pushed on the stack by the event that was being
delivered through the IDT at the time of the VM exit. The EXT bit is set in this field when it would be set
normally.
— For other VM exits, the value of this field is undefined.
27.2.4
Information for VM Exits Due to Instruction Execution
Section 24.9.4 defined fields containing information for VM exits that occur due to instruction execution. (The VMexit instruction length is also used for VM exits that occur during the delivery of a software interrupt or software
exception.) The following items detail their use.
•
VM-exit instruction length. This field is used in the following cases:
— For fault-like VM exits due to attempts to execute one of the following instructions that cause VM exits
unconditionally (see Section 25.1.2) or based on the settings of VM-execution controls (see Section
25.1.3): CLTS, CPUID, ENCLS, GETSEC, HLT, IN, INS, INVD, INVEPT, INVLPG, INVPCID, INVVPID, LGDT,
LIDT, LLDT, LMSW, LTR, MONITOR, MOV CR, MOV DR, MWAIT, OUT, OUTS, PAUSE, RDMSR, RDPMC,
RDRAND, RDSEED, RDTSC, RDTSCP, RSM, SGDT, SIDT, SLDT, STR, VMCALL, VMCLEAR, VMLAUNCH,
VMPTRLD, VMPTRST, VMREAD, VMRESUME, VMWRITE, VMXOFF, VMXON, WBINVD, WRMSR, XRSTORS,
XSETBV, and XSAVES.2
— For VM exits due to software exceptions (those generated by executions of INT3 or INTO).
— For VM exits due to faults encountered during delivery of a software interrupt, privileged software
exception, or software exception.
— For VM exits due to attempts to effect a task switch via instruction execution. These are VM exits that
produce an exit reason indicating task switch and either of the following:
•
•
An exit qualification indicating execution of CALL, IRET, or JMP instruction.
An exit qualification indicating a task gate in the IDT and an IDT-vectoring information field indicating
that the task gate was encountered during delivery of a software interrupt, privileged software
exception, or software exception.
— For APIC-access VM exits resulting from accesses (see Section 29.4) during delivery of a software
interrupt, privileged software exception, or software exception.3
— For VM exits due executions of VMFUNC that fail because one of the following is true:
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, a logical processor cannot be in realaddress mode unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
2. This item applies only to fault-like VM exits. It does not apply to trap-like VM exits following executions of the MOV to CR8 instruction when the “use TPR shadow” VM-execution control is 1 or to those following executions of the WRMSR instruction when the
“virtualize x2APIC mode” VM-execution control is 1.
3. The VM-exit instruction-length field is not defined following APIC-access VM exits resulting from physical accesses (see Section
29.4.6) even if encountered during delivery of a software interrupt, privileged software exception, or software exception.
Vol. 3C 27-13
VM EXITS
•
EAX indicates a VM function that is not enabled (the bit at position EAX is 0 in the VM-function controls;
see Section 25.5.5.2).
•
EAX = 0 and either ECX ≥ 512 or the value of ECX selects an invalid tentative EPTP value (see Section
25.5.5.3).
In all the above cases, this field receives the length in bytes (1–15) of the instruction (including any instruction
prefixes) whose execution led to the VM exit (see the next paragraph for one exception).
The cases of VM exits encountered during delivery of a software interrupt, privileged software exception, or
software exception include those encountered during delivery of events injected as part of VM entry (see
Section 26.5.1.2). If the original event was injected as part of VM entry, this field receives the value of the VMentry instruction length.
All VM exits other than those listed in the above items leave this field undefined.
If the VM exit occurred in enclave mode, this field is cleared (none of the previous items apply).
Table 27-8. Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS
Bit Position(s) Content
6:0
Undefined.
9:7
Address size:
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors that support Intel 64 architecture)
Other values not used.
14:10
Undefined.
17:15
Segment register:
0: ES
1: CS
2: SS
3: DS
4: FS
5: GS
Other values not used. Undefined for VM exits due to execution of INS.
31:18
•
Undefined.
VM-exit instruction information. For VM exits due to attempts to execute INS, INVEPT, INVPCID, INVVPID,
LIDT, LGDT, LLDT, LTR, OUTS, RDRAND, RDSEED, SIDT, SGDT, SLDT, STR, VMCLEAR, VMPTRLD, VMPTRST,
VMREAD, VMWRITE, VMXON, XRSTORS, or XSAVES, this field receives information about the instruction that
caused the VM exit. The format of the field depends on the identity of the instruction causing the VM exit:
— For VM exits due to attempts to execute INS or OUTS, the field has the format is given in Table 27-8.1
— For VM exits due to attempts to execute INVEPT, INVPCID, or INVVPID, the field has the format is given in
Table 27-9.
— For VM exits due to attempts to execute LIDT, LGDT, SIDT, or SGDT, the field has the format is given in
Table 27-10.
— For VM exits due to attempts to execute LLDT, LTR, SLDT, or STR, the field has the format is given in
Table 27-11.
— For VM exits due to attempts to execute RDRAND or RDSEED, the field has the format is given in
Table 27-12.
1. The format of the field was undefined for these VM exits on the first processors to support the virtual-machine extensions. Software can determine whether the format specified in Table 27-8 is used by consulting the VMX capability MSR IA32_VMX_BASIC
(see Appendix A.1).
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VM EXITS
— For VM exits due to attempts to execute VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, or XSAVES,
the field has the format is given in Table 27-13.
— For VM exits due to attempts to execute VMREAD or VMWRITE, the field has the format is given in
Table 27-14.
For all other VM exits, the field is undefined, unless the VM exit occurred in enclave mode, in which case the
field is cleared.
•
I/O RCX, I/O RSI, I/O RDI, I/O RIP. These fields are undefined except for SMM VM exits due to systemmanagement interrupts (SMIs) that arrive immediately after retirement of I/O instructions. See Section
34.15.2.3. Note that, if the VM exit occurred in enclave mode, these fields are all cleared.
Table 27-9. Format of the VM-Exit Instruction-Information Field as Used for INVEPT, INVPCID, and INVVPID
Bit Position(s) Content
1:0
Scaling:
0: no scaling
1: scale by 2
2: scale by 4
3: scale by 8 (used only on processors that support Intel 64 architecture)
Undefined for instructions with no index register (bit 22 is set).
6:2
Undefined.
9:7
Address size:
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors that support Intel 64 architecture)
Other values not used.
10
Cleared to 0.
14:11
Undefined.
17:15
Segment register:
0: ES
1: CS
2: SS
3: DS
4: FS
5: GS
Other values not used.
21:18
IndexReg:
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)
Undefined for instructions with no index register (bit 22 is set).
22
IndexReg invalid (0 = valid; 1 = invalid)
26:23
BaseReg (encoded as IndexReg above)
Undefined for memory instructions with no base register (bit 27 is set).
27
BaseReg invalid (0 = valid; 1 = invalid)
31:28
Reg2 (same encoding as IndexReg above)
Vol. 3C 27-15
VM EXITS
Table 27-10. Format of the VM-Exit Instruction-Information Field as Used for LIDT, LGDT, SIDT, or SGDT
Bit Position(s) Content
1:0
Scaling:
0: no scaling
1: scale by 2
2: scale by 4
3: scale by 8 (used only on processors that support Intel 64 architecture)
Undefined for instructions with no index register (bit 22 is set).
6:2
Undefined.
9:7
Address size:
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors that support Intel 64 architecture)
Other values not used.
10
Cleared to 0.
11
Operand size:
0: 16-bit
1: 32-bit
Undefined for VM exits from 64-bit mode.
14:12
Undefined.
17:15
Segment register:
0: ES
1: CS
2: SS
3: DS
4: FS
5: GS
Other values not used.
21:18
IndexReg:
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)
Undefined for instructions with no index register (bit 22 is set).
22
IndexReg invalid (0 = valid; 1 = invalid)
26:23
BaseReg (encoded as IndexReg above)
27
BaseReg invalid (0 = valid; 1 = invalid)
29:28
Instruction identity:
Undefined for instructions with no base register (bit 27 is set).
0: SGDT
1: SIDT
2: LGDT
3: LIDT
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VM EXITS
Table 27-10. Format of the VM-Exit Instruction-Information Field as Used for LIDT, LGDT, SIDT, or SGDT (Contd.)
Bit Position(s) Content
31:30
Undefined.
Table 27-11. Format of the VM-Exit Instruction-Information Field as Used for LLDT, LTR, SLDT, and STR
Bit Position(s) Content
1:0
Scaling:
0: no scaling
1: scale by 2
2: scale by 4
3: scale by 8 (used only on processors that support Intel 64 architecture)
Undefined for register instructions (bit 10 is set) and for memory instructions with no index register (bit 10 is clear
and bit 22 is set).
2
Undefined.
6:3
Reg1:
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)
Undefined for memory instructions (bit 10 is clear).
9:7
Address size:
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors that support Intel 64 architecture)
Other values not used. Undefined for register instructions (bit 10 is set).
10
Mem/Reg (0 = memory; 1 = register).
14:11
Undefined.
17:15
Segment register:
0: ES
1: CS
2: SS
3: DS
4: FS
5: GS
Other values not used. Undefined for register instructions (bit 10 is set).
21:18
IndexReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no index register (bit 10 is clear
and bit 22 is set).
22
IndexReg invalid (0 = valid; 1 = invalid)
Undefined for register instructions (bit 10 is set).
26:23
BaseReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no base register (bit 10 is clear
and bit 27 is set).
Vol. 3C 27-17
VM EXITS
Table 27-11. Format of the VM-Exit Instruction-Information Field as Used for LLDT, LTR, SLDT, and STR (Contd.)
Bit Position(s) Content
27
BaseReg invalid (0 = valid; 1 = invalid)
Undefined for register instructions (bit 10 is set).
29:28
Instruction identity:
0: SLDT
1: STR
2: LLDT
3: LTR
31:30
Undefined.
Table 27-12. Format of the VM-Exit Instruction-Information Field as Used for RDRAND and RDSEED
Bit Position(s) Content
2:0
Undefined.
6:3
Destination register:
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)
10:7
Undefined.
12:11
Operand size:
0: 16-bit
1: 32-bit
2: 64-bit
The value 3 is not used.
31:13
Undefined.
Table 27-13. Format of the VM-Exit Instruction-Information Field as Used for VMCLEAR, VMPTRLD, VMPTRST,
VMXON, XRSTORS, and XSAVES
Bit Position(s) Content
1:0
Scaling:
0: no scaling
1: scale by 2
2: scale by 4
3: scale by 8 (used only on processors that support Intel 64 architecture)
Undefined for instructions with no index register (bit 22 is set).
6:2
Undefined.
9:7
Address size:
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors that support Intel 64 architecture)
Other values not used.
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VM EXITS
Table 27-13. Format of the VM-Exit Instruction-Information Field as Used for VMCLEAR, VMPTRLD, VMPTRST,
VMXON, XRSTORS, and XSAVES (Contd.)
Bit Position(s) Content
10
Cleared to 0.
14:11
Undefined.
17:15
Segment register:
0: ES
1: CS
2: SS
3: DS
4: FS
5: GS
Other values not used.
21:18
IndexReg:
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)
Undefined for instructions with no index register (bit 22 is set).
22
IndexReg invalid (0 = valid; 1 = invalid)
26:23
BaseReg (encoded as IndexReg above)
Undefined for instructions with no base register (bit 27 is set).
27
BaseReg invalid (0 = valid; 1 = invalid)
31:28
Undefined.
Table 27-14. Format of the VM-Exit Instruction-Information Field as Used for VMREAD and VMWRITE
Bit Position(s) Content
1:0
Scaling:
0: no scaling
1: scale by 2
2: scale by 4
3: scale by 8 (used only on processors that support Intel 64 architecture)
Undefined for register instructions (bit 10 is set) and for memory instructions with no index register (bit 10 is clear
and bit 22 is set).
2
Undefined.
Vol. 3C 27-19
VM EXITS
Table 27-14. Format of the VM-Exit Instruction-Information Field as Used for VMREAD and VMWRITE (Contd.)
Bit Position(s) Content
6:3
Reg1:
0 = RAX
1 = RCX
2 = RDX
3 = RBX
4 = RSP
5 = RBP
6 = RSI
7 = RDI
8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)
Undefined for memory instructions (bit 10 is clear).
9:7
Address size:
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors that support Intel 64 architecture)
Other values not used. Undefined for register instructions (bit 10 is set).
10
Mem/Reg (0 = memory; 1 = register).
14:11
Undefined.
17:15
Segment register:
0: ES
1: CS
2: SS
3: DS
4: FS
5: GS
Other values not used. Undefined for register instructions (bit 10 is set).
21:18
IndexReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no index register (bit 10 is clear
and bit 22 is set).
22
IndexReg invalid (0 = valid; 1 = invalid)
Undefined for register instructions (bit 10 is set).
26:23
BaseReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no base register (bit 10 is clear
and bit 27 is set).
27
BaseReg invalid (0 = valid; 1 = invalid)
31:28
Reg2 (same encoding as Reg1 above)
Undefined for register instructions (bit 10 is set).
27.3
SAVING GUEST STATE
Each field in the guest-state area of the VMCS (see Section 24.4) is written with the corresponding component of
processor state. On processors that support Intel 64 architecture, the full values of each natural-width field (see
Section 24.11.2) is saved regardless of the mode of the logical processor before and after the VM exit.
In general, the state saved is that which was in the logical processor at the time the VM exit commences. See
Section 27.1 for a discussion of which architectural updates occur at that time.
Section 27.3.1 through Section 27.3.4 provide details for how certain components of processor state are saved.
These sections reference VMCS fields that correspond to processor state. Unless otherwise stated, these references
are to fields in the guest-state area.
27-20 Vol. 3C
VM EXITS
27.3.1
Saving Control Registers, Debug Registers, and MSRs
Contents of certain control registers, debug registers, and MSRs is saved as follows:
•
The contents of CR0, CR3, CR4, and the IA32_SYSENTER_CS, IA32_SYSENTER_ESP, and IA32_SYSENTER_EIP
MSRs are saved into the corresponding fields. Bits 63:32 of the IA32_SYSENTER_CS MSR are not saved. On
processors that do not support Intel 64 architecture, bits 63:32 of the IA32_SYSENTER_ESP and
IA32_SYSENTER_EIP MSRs are not saved.
•
If the “save debug controls” VM-exit control is 1, the contents of DR7 and the IA32_DEBUGCTL MSR are saved
into the corresponding fields. The first processors to support the virtual-machine extensions supported only the
1-setting of this control and thus always saved data into these fields.
•
If the “save IA32_PAT” VM-exit control is 1, the contents of the IA32_PAT MSR are saved into the corresponding
field.
•
If the “save IA32_EFER” VM-exit control is 1, the contents of the IA32_EFER MSR are saved into the corresponding field.
•
If the processor supports either the 1-setting of the “load IA32_BNDCFGS” VM-entry control or that of the
“clear IA32_BNDCFGS” VM-exit control, the contents of the IA32_BNDCFGS MSR are saved into the corresponding field.
•
The value of the SMBASE field is undefined after all VM exits except SMM VM exits. See Section 34.15.2.
27.3.2
Saving Segment Registers and Descriptor-Table Registers
For each segment register (CS, SS, DS, ES, FS, GS, LDTR, or TR), the values saved for the base-address, segmentlimit, and access rights are based on whether the register was unusable (see Section 24.4.1) before the VM exit:
•
If the register was unusable, the values saved into the following fields are undefined: (1) base address;
(2) segment limit; and (3) bits 7:0 and bits 15:12 in the access-rights field. The following exceptions apply:
— CS.
•
•
The base-address and segment-limit fields are saved.
The L, D, and G bits are saved in the access-rights field.
— SS.
•
•
DPL is saved in the access-rights field.
On processors that support Intel 64 architecture, bits 63:32 of the value saved for the base address are
always zero.
— DS and ES. On processors that support Intel 64 architecture, bits 63:32 of the values saved for the base
addresses are always zero.
— FS and GS. The base-address field is saved.
— LDTR. The value saved for the base address is always canonical.
•
If the register was not unusable, the values saved into the following fields are those which were in the register
before the VM exit: (1) base address; (2) segment limit; and (3) bits 7:0 and bits 15:12 in access rights.
•
Bits 31:17 and 11:8 in the access-rights field are always cleared. Bit 16 is set to 1 if and only if the segment is
unusable.
The contents of the GDTR and IDTR registers are saved into the corresponding base-address and limit fields.
27.3.3
Saving RIP, RSP, and RFLAGS
The contents of the RIP, RSP, and RFLAGS registers are saved as follows:
•
The value saved in the RIP field is determined by the nature and cause of the VM exit:
— If the VM exit occurred in enclave mode, the value saved is the AEP of interrupted enclave thread (the
remaining items do not apply).
Vol. 3C 27-21
VM EXITS
— If the VM exit occurs due to by an attempt to execute an instruction that causes VM exits unconditionally or
that has been configured to cause a VM exit via the VM-execution controls, the value saved references that
instruction.
— If the VM exit is caused by an occurrence of an INIT signal, a start-up IPI (SIPI), or system-management
interrupt (SMI), the value saved is that which was in RIP before the event occurred.
— If the VM exit occurs due to the 1-setting of either the “interrupt-window exiting” VM-execution control or
the “NMI-window exiting” VM-execution control, the value saved is that which would be in the register had
the VM exit not occurred.
— If the VM exit is due to an external interrupt, non-maskable interrupt (NMI), or hardware exception (as
defined in Section 27.2.2), the value saved is the return pointer that would have been saved (either on the
stack had the event been delivered through a trap or interrupt gate,1 or into the old task-state segment had
the event been delivered through a task gate).
— If the VM exit is due to a triple fault, the value saved is the return pointer that would have been saved
(either on the stack had the event been delivered through a trap or interrupt gate, or into the old task-state
segment had the event been delivered through a task gate) had delivery of the double fault not
encountered the nested exception that caused the triple fault.
— If the VM exit is due to a software exception (due to an execution of INT3 or INTO), the value saved
references the INT3 or INTO instruction that caused that exception.
— Suppose that the VM exit is due to a task switch that was caused by execution of CALL, IRET, or JMP or by
execution of a software interrupt (INT n) or software exception (due to execution of INT3 or INTO) that
encountered a task gate in the IDT. The value saved references the instruction that caused the task switch
(CALL, IRET, JMP, INT n, INT3, or INTO).
— Suppose that the VM exit is due to a task switch that was caused by a task gate in the IDT that was
encountered for any reason except the direct access by a software interrupt or software exception. The
value saved is that which would have been saved in the old task-state segment had the task switch
completed normally.
— If the VM exit is due to an execution of MOV to CR8 or WRMSR that reduced the value of bits 7:4 of VTPR
(see Section 29.1.1) below that of TPR threshold VM-execution control field (see Section 29.1.2), the value
saved references the instruction following the MOV to CR8 or WRMSR.
— If the VM exit was caused by APIC-write emulation (see Section 29.4.3.2) that results from an APIC access
as part of instruction execution, the value saved references the instruction following the one whose
execution caused the APIC-write emulation.
•
•
The contents of the RSP register are saved into the RSP field.
With the exception of the resume flag (RF; bit 16), the contents of the RFLAGS register is saved into the
RFLAGS field. RFLAGS.RF is saved as follows:
— If the VM exit occurred in enclave mode, the value saved is 0 (the remaining items do not apply).
— If the VM exit is caused directly by an event that would normally be delivered through the IDT, the value
saved is that which would appear in the saved RFLAGS image (either that which would be saved on the
stack had the event been delivered through a trap or interrupt gate2 or into the old task-state segment had
the event been delivered through a task gate) had the event been delivered through the IDT. See below for
VM exits due to task switches caused by task gates in the IDT.
— If the VM exit is caused by a triple fault, the value saved is that which the logical processor would have in
RF in the RFLAGS register had the triple fault taken the logical processor to the shutdown state.
— If the VM exit is caused by a task switch (including one caused by a task gate in the IDT), the value saved
is that which would have been saved in the RFLAGS image in the old task-state segment (TSS) had the task
switch completed normally without exception.
1. The reference here is to the full value of RIP before any truncation that would occur had the stack width been only 32 bits or 16
bits.
2. The reference here is to the full value of RFLAGS before any truncation that would occur had the stack width been only 32 bits or
16 bits.
27-22 Vol. 3C
VM EXITS
— If the VM exit is caused by an attempt to execute an instruction that unconditionally causes VM exits or one
that was configured to do with a VM-execution control, the value saved is 0.1
— For APIC-access VM exits and for VM exits caused by EPT violations EPT misconfigurations, and pagemodification log-full events, the value saved depends on whether the VM exit occurred during delivery of an
event through the IDT:
•
If the VM exit stored 0 for bit 31 for IDT-vectoring information field (because the VM exit did not occur
during delivery of an event through the IDT; see Section 27.2.3), the value saved is 1.
•
If the VM exit stored 1 for bit 31 for IDT-vectoring information field (because the VM exit did occur
during delivery of an event through the IDT), the value saved is the value that would have appeared in
the saved RFLAGS image had the event been delivered through the IDT (see above).
— For all other VM exits, the value saved is the value RFLAGS.RF had before the VM exit occurred.
27.3.4
Saving Non-Register State
Information corresponding to guest non-register state is saved as follows:
•
The activity-state field is saved with the logical processor’s activity state before the VM exit.2 See Section 27.1
for details of how events leading to a VM exit may affect the activity state.
•
The interruptibility-state field is saved to reflect the logical processor’s interruptibility before the VM exit.
— See Section 27.1 for details of how events leading to a VM exit may affect this state.
— VM exits that end outside system-management mode (SMM) save bit 2 (blocking by SMI) as 0 regardless
of the state of such blocking before the VM exit.
— Bit 3 (blocking by NMI) is treated specially if the “virtual NMIs” VM-execution control is 1. In this case, the
value saved for this field does not indicate the blocking of NMIs but rather the state of virtual-NMI blocking.
— Bit 4 (enclave interruption) is set to 1 if the VM exit occurred while the logical processor was in enclave
mode.
Such VM exits includes those caused by interrupts, non-maskable interrupts, system-management
interrupts, INIT signals, and exceptions occurring in enclave mode as well as exceptions encountered
during the delivery of such events incident to enclave mode.
A VM exit that is incident to delivery of an event injected by VM entry leaves this bit unmodified.
•
The pending debug exceptions field is saved as clear for all VM exits except the following:
— A VM exit caused by an INIT signal, a machine-check exception, or a system-management interrupt (SMI).
— A VM exit with basic exit reason “TPR below threshold”,3 “virtualized EOI”, “APIC write”, or “monitor trap
flag.”
— VM exits that are not caused by debug exceptions and that occur while there is MOV-SS blocking of debug
exceptions.
For VM exits that do not clear the field, the value saved is determined as follows:
— Each of bits 3:0 may be set if it corresponds to a matched breakpoint. This may be true even if the corresponding breakpoint is not enabled in DR7.
— Suppose that a VM exit is due to an INIT signal, a machine-check exception, or an SMI; or that a VM exit
has basic exit reason “TPR below threshold” or “monitor trap flag.” In this case, the value saved sets bits
corresponding to the causes of any debug exceptions that were pending at the time of the VM exit.
1. This is true even if RFLAGS.RF was 1 before the instruction was executed. If, in response to such a VM exit, a VM monitor re-enters
the guest to re-execute the instruction that caused the VM exit (for example, after clearing the VM-execution control that caused
the VM exit), the instruction may encounter a code breakpoint that has already been processed. A VM monitor can avoid this by setting the guest value of RFLAGS.RF to 1 before resuming guest software.
2. If this activity state was an inactive state resulting from execution of a specific instruction (HLT or MWAIT), the value saved for RIP
by that VM exit will reference the following instruction.
3. This item includes VM exits that occur as a result of certain VM entries (Section 26.6.7).
Vol. 3C 27-23
VM EXITS
If the VM exit occurs immediately after VM entry, the value saved may match that which was loaded on
VM entry (see Section 26.6.3). Otherwise, the following items apply:
•
Bit 12 (enabled breakpoint) is set to 1 in any of the following cases:
— If there was at least one matched data or I/O breakpoint that was enabled in DR7.
— If it had been set on VM entry, causing there to be valid pending debug exceptions (see Section
26.6.3) and the VM exit occurred before those exceptions were either delivered or lost.
— If the XBEGIN instruction was executed immediately before the VM exit and advanced debugging of
RTM transactional regions had been enabled (see Section 16.3.7, “RTM-Enabled Debugger
Support,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). (This does
not apply to VM exits with basic exit reason “monitor trap flag.”)
In other cases, bit 12 is cleared to 0.
•
Bit 14 (BS) is set if RFLAGS.TF = 1 in either of the following cases:
— IA32_DEBUGCTL.BTF = 0 and the cause of a pending debug exception was the execution of a single
instruction.
— IA32_DEBUGCTL.BTF = 1 and the cause of a pending debug exception was a taken branch.
•
Bit 16 (RTM) is set if a debug exception (#DB) or a breakpoint exception (#BP) occurred inside an RTM
region while advanced debugging of RTM transactional regions had been enabled. (This does not apply
to VM exits with basic exit reason “monitor trap flag.”)
— Suppose that a VM exit is due to another reason (but not a debug exception) and occurs while there is MOVSS blocking of debug exceptions. In this case, the value saved sets bits corresponding to the causes of any
debug exceptions that were pending at the time of the VM exit. If the VM exit occurs immediately after
VM entry (no instructions were executed in VMX non-root operation), the value saved may match that
which was loaded on VM entry (see Section 26.6.3). Otherwise, the following items apply:
•
Bit 12 (enabled breakpoint) is set to 1 if there was at least one matched data or I/O breakpoint that was
enabled in DR7. Bit 12 is also set if it had been set on VM entry, causing there to be valid pending debug
exceptions (see Section 26.6.3) and the VM exit occurred before those exceptions were either delivered
or lost. In other cases, bit 12 is cleared to 0.
•
The setting of bit 14 (BS) is implementation-specific. However, it is not set if RFLAGS.TF = 0 or
IA32_DEBUGCTL.BTF = 1.
— The reserved bits in the field are cleared.
•
If the “save VMX-preemption timer value” VM-exit control is 1, the value of timer is saved into the VMXpreemption timer-value field. This is the value loaded from this field on VM entry as subsequently decremented
(see Section 25.5.1). VM exits due to timer expiration save the value 0. Other VM exits may also save the value
0 if the timer expired during VM exit. (If the “save VMX-preemption timer value” VM-exit control is 0, VM exit
does not modify the value of the VMX-preemption timer-value field.)
•
If the logical processor supports the 1-setting of the “enable EPT” VM-execution control, values are saved into
the four (4) PDPTE fields as follows:
— If the “enable EPT” VM-execution control is 1 and the logical processor was using PAE paging at the time of
the VM exit, the PDPTE values currently in use are saved:1
•
•
The values saved into bits 11:9 of each of the fields is undefined.
•
If the value saved into one of the fields has bit 0 (present) set, the value saved into bits 63:12 of the
field is a guest-physical address.
If the value saved into one of the fields has bit 0 (present) clear, the value saved into bits 63:1 of that
field is undefined. That value need not correspond to the value that was loaded by VM entry or to any
value that might have been loaded in VMX non-root operation.
1. A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1 and IA32_EFER.LMA = 0. See Section 4.4 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A. “Enable EPT” is a secondary processor-based VM-execution control. If bit 31
of the primary processor-based VM-execution controls is 0, VM exit functions as if the “enable EPT” VM-execution control were 0.
See Section 24.6.2.
27-24 Vol. 3C
VM EXITS
— If the “enable EPT” VM-execution control is 0 or the logical processor was not using PAE paging at the time
of the VM exit, the values saved are undefined.
27.4
SAVING MSRS
After processor state is saved to the guest-state area, values of MSRs may be stored into the VM-exit MSR-store
area (see Section 24.7.2). Specifically each entry in that area (up to the number specified in the VM-exit MSR-store
count) is processed in order by storing the value of the MSR indexed by bits 31:0 (as they would be read by
RDMSR) into bits 127:64. Processing of an entry fails in either of the following cases:
•
The value of bits 31:8 is 000008H, meaning that the indexed MSR is one that allows access to an APIC register
when the local APIC is in x2APIC mode.
•
The value of bits 31:0 indicates an MSR that can be read only in system-management mode (SMM) and the
VM exit will not end in SMM. (IA32_SMBASE is an MSR that can be read only in SMM.)
•
The value of bits 31:0 indicates an MSR that cannot be saved on VM exits for model-specific reasons. A
processor may prevent certain MSRs (based on the value of bits 31:0) from being stored on VM exits, even if
they can normally be read by RDMSR. Such model-specific behavior is documented in Chapter 35.
•
•
Bits 63:32 of the entry are not all 0.
An attempt to read the MSR indexed by bits 31:0 would cause a general-protection exception if executed via
RDMSR with CPL = 0.
A VMX abort occurs if processing fails for any entry. See Section 27.7.
27.5
LOADING HOST STATE
Processor state is updated on VM exits in the following ways:
•
•
•
•
Some state is loaded from or otherwise determined by the contents of the host-state area.
Some state is determined by VM-exit controls.
Some state is established in the same way on every VM exit.
The page-directory pointers are loaded based on the values of certain control registers.
This loading may be performed in any order.
On processors that support Intel 64 architecture, the full values of each 64-bit field loaded (for example, the base
address for GDTR) is loaded regardless of the mode of the logical processor before and after the VM exit.
The loading of host state is detailed in Section 27.5.1 to Section 27.5.5. These sections reference VMCS fields that
correspond to processor state. Unless otherwise stated, these references are to fields in the host-state area.
A logical processor is in IA-32e mode after a VM exit only if the “host address-space size” VM-exit control is 1. If
the logical processor was in IA-32e mode before the VM exit and this control is 0, a VMX abort occurs. See Section
27.7.
In addition to loading host state, VM exits clear address-range monitoring (Section 27.5.6).
After the state loading described in this section, VM exits may load MSRs from the VM-exit MSR-load area (see
Section 27.6). This loading occurs only after the state loading described in this section.
27.5.1
Loading Host Control Registers, Debug Registers, MSRs
VM exits load new values for controls registers, debug registers, and some MSRs:
•
CR0, CR3, and CR4 are loaded from the CR0 field, the CR3 field, and the CR4 field, respectively, with the
following exceptions:
— The following bits are not modified:
Vol. 3C 27-25
VM EXITS
•
For CR0, ET, CD, NW; bits 63:32 (on processors that support Intel 64 architecture), 28:19, 17, and
15:6; and any bits that are fixed in VMX operation (see Section 23.8).1
•
For CR3, bits 63:52 and bits in the range 51:32 beyond the processor’s physical-address width (they
are cleared to 0).2 (This item applies only to processors that support Intel 64 architecture.)
•
For CR4, any bits that are fixed in VMX operation (see Section 23.8).
— CR4.PAE is set to 1 if the “host address-space size” VM-exit control is 1.
— CR4.PCIDE is set to 0 if the “host address-space size” VM-exit control is 0.
•
•
DR7 is set to 400H.
The following MSRs are established as follows:
— The IA32_DEBUGCTL MSR is cleared to 00000000_00000000H.
— The IA32_SYSENTER_CS MSR is loaded from the IA32_SYSENTER_CS field. Since that field has only 32
bits, bits 63:32 of the MSR are cleared to 0.
— IA32_SYSENTER_ESP MSR and IA32_SYSENTER_EIP MSR are loaded from the IA32_SYSENTER_ESP field
and the IA32_SYSENTER_EIP field, respectively.
If the processor does not support the Intel 64 architecture, these fields have only 32 bits; bits 63:32 of the
MSRs are cleared to 0.
If the processor does support the Intel 64 architecture and the processor supports N < 64 linear-address
bits, each of bits 63:N is set to the value of bit N–1.3
— The following steps are performed on processors that support Intel 64 architecture:
•
The MSRs FS.base and GS.base are loaded from the base-address fields for FS and GS, respectively
(see Section 27.5.2).
•
The LMA and LME bits in the IA32_EFER MSR are each loaded with the setting of the “host addressspace size” VM-exit control.
— If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, the IA32_PERF_GLOBAL_CTRL MSR is loaded
from the IA32_PERF_GLOBAL_CTRL field. Bits that are reserved in that MSR are maintained with their
reserved values.
— If the “load IA32_PAT” VM-exit control is 1, the IA32_PAT MSR is loaded from the IA32_PAT field. Bits that
are reserved in that MSR are maintained with their reserved values.
— If the “load IA32_EFER” VM-exit control is 1, the IA32_EFER MSR is loaded from the IA32_EFER field. Bits
that are reserved in that MSR are maintained with their reserved values.
— If the “clear IA32_BNDCFGS” VM-exit control is 1, the IA32_BNDCFGS MSR is cleared to
00000000_00000000H; otherwise, it is not modified.
With the exception of FS.base and GS.base, any of these MSRs is subsequently overwritten if it appears in the
VM-exit MSR-load area. See Section 27.6.
27.5.2
Loading Host Segment and Descriptor-Table Registers
Each of the registers CS, SS, DS, ES, FS, GS, and TR is loaded as follows (see below for the treatment of LDTR):
•
The selector is loaded from the selector field. The segment is unusable if its selector is loaded with zero. The
checks specified Section 26.3.1.2 limit the selector values that may be loaded. In particular, CS and TR are
never loaded with zero and are thus never unusable. SS can be loaded with zero only on processors that
1. Bits 28:19, 17, and 15:6 of CR0 and CR0.ET are unchanged by executions of MOV to CR0. CR0.ET is always 1 and the other bits are
always 0.
2. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
3. Software can determine the number N by executing CPUID with 80000008H in EAX. The number of linear-address bits supported is
returned in bits 15:8 of EAX.
27-26 Vol. 3C
VM EXITS
support Intel 64 architecture and only if the VM exit is to 64-bit mode (64-bit mode allows use of segments
marked unusable).
•
The base address is set as follows:
— CS. Cleared to zero.
— SS, DS, and ES. Undefined if the segment is unusable; otherwise, cleared to zero.
— FS and GS. Undefined (but, on processors that support Intel 64 architecture, canonical) if the segment is
unusable and the VM exit is not to 64-bit mode; otherwise, loaded from the base-address field.
If the processor supports the Intel 64 architecture and the processor supports N < 64 linear-address bits,
each of bits 63:N is set to the value of bit N–1.1 The values loaded for base addresses for FS and GS are
also manifest in the FS.base and GS.base MSRs.
— TR. Loaded from the host-state area. If the processor supports the Intel 64 architecture and the processor
supports N < 64 linear-address bits, each of bits 63:N is set to the value of bit N–1.
•
The segment limit is set as follows:
— CS. Set to FFFFFFFFH (corresponding to a descriptor limit of FFFFFH and a G-bit setting of 1).
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to FFFFFFFFH.
— TR. Set to 00000067H.
•
The type field and S bit are set as follows:
— CS. Type set to 11 and S set to 1 (execute/read, accessed, non-conforming code segment).
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, type set to 3 and S set to 1
(read/write, accessed, expand-up data segment).
— TR. Type set to 11 and S set to 0 (busy 32-bit task-state segment).
•
The DPL is set as follows:
— CS, SS, and TR. Set to 0. The current privilege level (CPL) will be 0 after the VM exit completes.
— DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 0.
•
The P bit is set as follows:
— CS, TR. Set to 1.
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.
•
On processors that support Intel 64 architecture, CS.L is loaded with the setting of the “host address-space
size” VM-exit control. Because the value of this control is also loaded into IA32_EFER.LMA (see Section 27.5.1),
no VM exit is ever to compatibility mode (which requires IA32_EFER.LMA = 1 and CS.L = 0).
•
D/B.
— CS. Loaded with the inverse of the setting of the “host address-space size” VM-exit control. For example, if
that control is 0, indicating a 32-bit guest, CS.D/B is set to 1.
— SS. Set to 1.
— DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.
— TR. Set to 0.
•
G.
— CS. Set to 1.
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.
— TR. Set to 0.
1. Software can determine the number N by executing CPUID with 80000008H in EAX. The number of linear-address bits supported is
returned in bits 15:8 of EAX.
Vol. 3C 27-27
VM EXITS
The host-state area does not contain a selector field for LDTR. LDTR is established as follows on all VM exits: the
selector is cleared to 0000H, the segment is marked unusable and is otherwise undefined (although the base
address is always canonical).
The base addresses for GDTR and IDTR are loaded from the GDTR base-address field and the IDTR base-address
field, respectively. If the processor supports the Intel 64 architecture and the processor supports N < 64 linearaddress bits, each of bits 63:N of each base address is set to the value of bit N–1 of that base address. The GDTR
and IDTR limits are each set to FFFFH.
27.5.3
Loading Host RIP, RSP, and RFLAGS
RIP and RSP are loaded from the RIP field and the RSP field, respectively. RFLAGS is cleared, except bit 1, which is
always set.
27.5.4
Checking and Loading Host Page-Directory-Pointer-Table Entries
If CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LMA = 0, the logical processor uses PAE paging. See Section 4.4 of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.1 When in PAE paging is in use, the
physical address in CR3 references a table of page-directory-pointer-table entries (PDPTEs). A MOV to CR3
when PAE paging is in use checks the validity of the PDPTEs and, if they are valid, loads them into the processor
(into internal, non-architectural registers).
A VM exit is to a VMM that uses PAE paging if (1) bit 5 (corresponding to CR4.PAE) is set in the CR4 field in the hoststate area of the VMCS; and (2) the “host address-space size” VM-exit control is 0. Such a VM exit may check the
validity of the PDPTEs referenced by the CR3 field in the host-state area of the VMCS. Such a VM exit must check
their validity if either (1) PAE paging was not in use before the VM exit; or (2) the value of CR3 is changing as a
result of the VM exit. A VM exit to a VMM that does not use PAE paging must not check the validity of the PDPTEs.
A VM exit that checks the validity of the PDPTEs uses the same checks that are used when CR3 is loaded with
MOV to CR3 when PAE paging is in use. If MOV to CR3 would cause a general-protection exception due to the
PDPTEs that would be loaded (e.g., because a reserved bit is set), a VMX abort occurs (see Section 27.7). If a
VM exit to a VMM that uses PAE does not cause a VMX abort, the PDPTEs are loaded into the processor as would
MOV to CR3, using the value of CR3 being load by the VM exit.
27.5.5
Updating Non-Register State
VM exits affect the non-register state of a logical processor as follows:
•
•
A logical processor is always in the active state after a VM exit.
Event blocking is affected as follows:
— There is no blocking by STI or by MOV SS after a VM exit.
— VM exits caused directly by non-maskable interrupts (NMIs) cause blocking by NMI (see Table 24-3). Other
VM exits do not affect blocking by NMI. (See Section 27.1 for the case in which an NMI causes a VM exit
indirectly.)
•
There are no pending debug exceptions after a VM exit.
Section 28.3 describes how the VMX architecture controls how a logical processor manages information in the TLBs
and paging-structure caches. The following items detail how VM exits invalidate cached mappings:
•
If the “enable VPID” VM-execution control is 0, the logical processor invalidates linear mappings and combined
mappings associated with VPID 0000H (for all PCIDs); combined mappings for VPID 0000H are invalidated for
all EP4TA values (EP4TA is the value of bits 51:12 of EPTP).
1. On processors that support Intel 64 architecture, the physical-address extension may support more than 36 physical-address bits.
Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
27-28 Vol. 3C
VM EXITS
•
VM exits are not required to invalidate any guest-physical mappings, nor are they required to invalidate any
linear mappings or combined mappings if the “enable VPID” VM-execution control is 1.
27.5.6
Clearing Address-Range Monitoring
The Intel 64 and IA-32 architectures allow software to monitor a specified address range using the MONITOR and
MWAIT instructions. See Section 8.10.4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A. VM exits clear any address-range monitoring that may be in effect.
27.6
LOADING MSRS
VM exits may load MSRs from the VM-exit MSR-load area (see Section 24.7.2). Specifically each entry in that area
(up to the number specified in the VM-exit MSR-load count) is processed in order by loading the MSR indexed by
bits 31:0 with the contents of bits 127:64 as they would be written by WRMSR.
Processing of an entry fails in any of the following cases:
•
The value of bits 31:0 is either C0000100H (the IA32_FS_BASE MSR) or C0000101H (the IA32_GS_BASE
MSR).
•
The value of bits 31:8 is 000008H, meaning that the indexed MSR is one that allows access to an APIC register
when the local APIC is in x2APIC mode.
•
The value of bits 31:0 indicates an MSR that can be written only in system-management mode (SMM) and the
VM exit will not end in SMM. (IA32_SMM_MONITOR_CTL is an MSR that can be written only in SMM.)
•
The value of bits 31:0 indicates an MSR that cannot be loaded on VM exits for model-specific reasons. A
processor may prevent loading of certain MSRs even if they can normally be written by WRMSR. Such modelspecific behavior is documented in Chapter 35.
•
•
Bits 63:32 are not all 0.
An attempt to write bits 127:64 to the MSR indexed by bits 31:0 of the entry would cause a general-protection
exception if executed via WRMSR with CPL = 0.1
If processing fails for any entry, a VMX abort occurs. See Section 27.7.
If any MSR is being loaded in such a way that would architecturally require a TLB flush, the TLBs are updated so
that, after VM exit, the logical processor does not use any translations that were cached before the transition.
27.7
VMX ABORTS
A problem encountered during a VM exit leads to a VMX abort. A VMX abort takes a logical processor into a shutdown state as described below.
A VMX abort does not modify the VMCS data in the VMCS region of any active VMCS. The contents of these data
are thus suspect after the VMX abort.
On a VMX abort, a logical processor saves a nonzero 32-bit VMX-abort indicator field at byte offset 4 in the VMCS
region of the VMCS whose misconfiguration caused the failure (see Section 24.2). The following values are used:
1. There was a failure in saving guest MSRs (see Section 27.4).
2. Host checking of the page-directory-pointer-table entries (PDPTEs) failed (see Section 27.5.4).
3. The current VMCS has been corrupted (through writes to the corresponding VMCS region) in such a way that
the logical processor cannot complete the VM exit properly.
4. There was a failure on loading host MSRs (see Section 27.6).
1. Note the following about processors that support Intel 64 architecture. If CR0.PG = 1, WRMSR to the IA32_EFER MSR causes a general-protection exception if it would modify the LME bit. Since CR0.PG is always 1 in VMX operation, the IA32_EFER MSR should not
be included in the VM-exit MSR-load area for the purpose of modifying the LME bit.
Vol. 3C 27-29
VM EXITS
5. There was a machine-check event during VM exit (see Section 27.8).
6. The logical processor was in IA-32e mode before the VM exit and the “host address-space size” VM-entry
control was 0 (see Section 27.5).
Some of these causes correspond to failures during the loading of state from the host-state area. Because the
loading of such state may be done in any order (see Section 27.5) a VM exit that might lead to a VMX abort for
multiple reasons (for example, the current VMCS may be corrupt and the host PDPTEs might not be properly
configured). In such cases, the VMX-abort indicator could correspond to any one of those reasons.
A logical processor never reads the VMX-abort indicator in a VMCS region and writes it only with one of the nonzero values mentioned above. The VMX-abort indicator allows software on one logical processor to diagnose the
VMX-abort on another. For this reason, it is recommended that software running in VMX root operation zero the
VMX-abort indicator in the VMCS region of any VMCS that it uses.
After saving the VMX-abort indicator, operation of a logical processor experiencing a VMX abort depends on
whether the logical processor is in SMX operation:1
•
If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs. The error code used is
000DH, indicating “VMX abort.” See Intel® Trusted Execution Technology Measured Launched Environment
Programming Guide.
•
If the logical processor is outside SMX operation, it issues a special bus cycle (to notify the chipset) and enters
the VMX-abort shutdown state. RESET is the only event that wakes a logical processor from the VMX-abort
shutdown state. The following events do not affect a logical processor in this state: machine-check events; INIT
signals; external interrupts; non-maskable interrupts (NMIs); start-up IPIs (SIPIs); and system-management
interrupts (SMIs).
27.8
MACHINE-CHECK EVENTS DURING VM EXIT
If a machine-check event occurs during VM exit, one of the following occurs:
•
The machine-check event is handled as if it occurred before the VM exit:
— If CR4.MCE = 0, operation of the logical processor depends on whether the logical processor is in SMX
operation:2
•
If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs. The error code
used is 000CH, indicating “unrecoverable machine-check condition.”
•
If the logical processor is outside SMX operation, it goes to the shutdown state.
— If CR4.MCE = 1, a machine-check exception (#MC) is generated:
•
•
•
If bit 18 (#MC) of the exception bitmap is 0, the exception is delivered through the guest IDT.
If bit 18 of the exception bitmap is 1, the exception causes a VM exit.
The machine-check event is handled after VM exit completes:
— If the VM exit ends with CR4.MCE = 0, operation of the logical processor depends on whether the logical
processor is in SMX operation:
•
If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs with error code
000CH (unrecoverable machine-check condition).
•
If the logical processor is outside SMX operation, it goes to the shutdown state.
1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last
execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B.
2. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last
execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B.
27-30 Vol. 3C
VM EXITS
— If the VM exit ends with CR4.MCE = 1, a machine-check exception (#MC) is delivered through the host IDT.
•
A VMX abort is generated (see Section 27.7). The logical processor blocks events as done normally in
VMX abort. The VMX abort indicator is 5, for “machine-check event during VM exit.”
The first option is not used if the machine-check event occurs after any host state has been loaded. The second
option is used only if VM entry is able to load all host state.
Vol. 3C 27-31
VM EXITS
27-32 Vol. 3C
CHAPTER 28
VMX SUPPORT FOR ADDRESS TRANSLATION
The architecture for VMX operation includes two features that support address translation: virtual-processor identifiers (VPIDs) and the extended page-table mechanism (EPT). VPIDs are a mechanism for managing translations
of linear addresses. EPT defines a layer of address translation that augments the translation of linear addresses.
Section 28.1 details the architecture of VPIDs. Section 28.2 provides the details of EPT. Section 28.3 explains how
a logical processor may cache information from the paging structures, how it may use that cached information, and
how software can managed the cached information.
28.1
VIRTUAL PROCESSOR IDENTIFIERS (VPIDS)
The original architecture for VMX operation required VMX transitions to flush the TLBs and paging-structure caches.
This ensured that translations cached for the old linear-address space would not be used after the transition.
Virtual-processor identifiers (VPIDs) introduce to VMX operation a facility by which a logical processor may cache
information for multiple linear-address spaces. When VPIDs are used, VMX transitions may retain cached information and the logical processor switches to a different linear-address space.
Section 28.3 details the mechanisms by which a logical processor manages information cached for multiple address
spaces. A logical processor may tag some cached information with a 16-bit VPID. This section specifies how the
current VPID is determined at any point in time:
•
The current VPID is 0000H in the following situations:
— Outside VMX operation. (This includes operation in system-management mode under the default treatment
of SMIs and SMM with VMX operation; see Section 34.14.)
— In VMX root operation.
— In VMX non-root operation when the “enable VPID” VM-execution control is 0.
•
If the logical processor is in VMX non-root operation and the “enable VPID” VM-execution control is 1, the
current VPID is the value of the VPID VM-execution control field in the VMCS. (VM entry ensures that this value
is never 0000H; see Section 26.2.1.1.)
VPIDs and PCIDs (see Section 4.10.1) can be used concurrently. When this is done, the processor associates
cached information with both a VPID and a PCID. Such information is used only if the current VPID and PCID both
match those associated with the cached information.
28.2
THE EXTENDED PAGE TABLE MECHANISM (EPT)
The extended page-table mechanism (EPT) is a feature that can be used to support the virtualization of physical
memory. When EPT is in use, certain addresses that would normally be treated as physical addresses (and used to
access memory) are instead treated as guest-physical addresses. Guest-physical addresses are translated by
traversing a set of EPT paging structures to produce physical addresses that are used to access memory.
•
•
•
•
Section 28.2.1 gives an overview of EPT.
Section 28.2.2 describes operation of EPT-based address translation.
Section 28.2.3 discusses VM exits that may be caused by EPT.
Section 28.2.6 describes interactions between EPT and memory typing.
28.2.1
EPT Overview
EPT is used when the “enable EPT” VM-execution control is 1.1 It translates the guest-physical addresses used in
VMX non-root operation and those used by VM entry for event injection.
Vol. 3C 28-1
VMX SUPPORT FOR ADDRESS TRANSLATION
The translation from guest-physical addresses to physical addresses is determined by a set of EPT paging structures. The EPT paging structures are similar to those used to translate linear addresses while the processor is in
IA-32e mode. Section 28.2.2 gives the details of the EPT paging structures.
If CR0.PG = 1, linear addresses are translated through paging structures referenced through control register CR3.
While the “enable EPT” VM-execution control is 1, these are called guest paging structures. There are no guest
paging structures if CR0.PG = 0.1
When the “enable EPT” VM-execution control is 1, the identity of guest-physical addresses depends on the value
of CR0.PG:
•
•
If CR0.PG = 0, each linear address is treated as a guest-physical address.
If CR0.PG = 1, guest-physical addresses are those derived from the contents of control register CR3 and the
guest paging structures. (This includes the values of the PDPTEs, which logical processors store in internal,
non-architectural registers.) The latter includes (in page-table entries and in other paging-structure entries for
which bit 7—PS—is 1) the addresses to which linear addresses are translated by the guest paging structures.
If CR0.PG = 1, the translation of a linear address to a physical address requires multiple translations of guest-physical addresses using EPT. Assume, for example, that CR4.PAE = CR4.PSE = 0. The translation of a 32-bit linear
address then operates as follows:
•
Bits 31:22 of the linear address select an entry in the guest page directory located at the guest-physical
address in CR3. The guest-physical address of the guest page-directory entry (PDE) is translated through EPT
to determine the guest PDE’s physical address.
•
Bits 21:12 of the linear address select an entry in the guest page table located at the guest-physical address in
the guest PDE. The guest-physical address of the guest page-table entry (PTE) is translated through EPT to
determine the guest PTE’s physical address.
•
Bits 11:0 of the linear address is the offset in the page frame located at the guest-physical address in the guest
PTE. The guest-physical address determined by this offset is translated through EPT to determine the physical
address to which the original linear address translates.
In addition to translating a guest-physical address to a physical address, EPT specifies the privileges that software
is allowed when accessing the address. Attempts at disallowed accesses are called EPT violations and cause
VM exits. See Section 28.2.3.
A processor uses EPT to translate guest-physical addresses only when those addresses are used to access memory.
This principle implies the following:
•
The MOV to CR3 instruction loads CR3 with a guest-physical address. Whether that address is translated
through EPT depends on whether PAE paging is being used.2
— If PAE paging is not being used, the instruction does not use that address to access memory and does not
cause it to be translated through EPT. (If CR0.PG = 1, the address will be translated through EPT on the
next memory accessing using a linear address.)
— If PAE paging is being used, the instruction loads the four (4) page-directory-pointer-table entries (PDPTEs)
from that address and it does cause the address to be translated through EPT.
•
Section 4.4.1 identifies executions of MOV to CR0 and MOV to CR4 that load the PDPTEs from the guestphysical address in CR3. Such executions cause that address to be translated through EPT.
•
The PDPTEs contain guest-physical addresses. The instructions that load the PDPTEs (see above) do not use
those addresses to access memory and do not cause them to be translated through EPT. The address in a
PDPTE will be translated through EPT on the next memory accessing using a linear address that uses that
PDPTE.
1. “Enable EPT” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls
is 0, the logical processor operates as if the “enable EPT” VM-execution control were 0. See Section 24.6.2.
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG can be 0 in VMX non-root
operation only if the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are
both 1.
2. A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1 and IA32_EFER.LMA = 0. See Section 4.4 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A.
28-2 Vol. 3C
VMX SUPPORT FOR ADDRESS TRANSLATION
28.2.2
EPT Translation Mechanism
The EPT translation mechanism uses only bits 47:0 of each guest-physical address.1 It uses a page-walk length of
4, meaning that at most 4 EPT paging-structure entries are accessed to translate a guest-physical address.2
These 48 bits are partitioned by the logical processor to traverse the EPT paging structures:
•
A 4-KByte naturally aligned EPT PML4 table is located at the physical address specified in bits 51:12 of the
extended-page-table pointer (EPTP), a VM-execution control field (see Table 24-8 in Section 24.6.11). An EPT
PML4 table comprises 512 64-bit entries (EPT PML4Es). An EPT PML4E is selected using the physical address
defined as follows:
— Bits 63:52 are all 0.
— Bits 51:12 are from the EPTP.
— Bits 11:3 are bits 47:39 of the guest-physical address.
— Bits 2:0 are all 0.
Because an EPT PML4E is identified using bits 47:39 of the guest-physical address, it controls access to a 512GByte region of the guest-physical-address space. The format of an EPT PML4E is given in Table 28-1.
Table 28-1. Format of an EPT PML4 Entry (PML4E) that References an EPT Page-Directory-Pointer Table
Bit
Position(s)
Contents
0
Read access; indicates whether reads are allowed from the 512-GByte region controlled by this entry
1
Write access; indicates whether writes are allowed from the 512-GByte region controlled by this entry
2
If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether instruction
fetches are allowed from the 512-GByte region controlled by this entry
If that control is 1, execute access for supervisor-mode linear addresses; indicates whether instruction fetches are
allowed from supervisor-mode linear addresses in the 512-GByte region controlled by this entry
7:3
Reserved (must be 0)
8
If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 512-GByte region
controlled by this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
9
Ignored
10
Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is
1, indicates whether instruction fetches are allowed from user-mode linear addresses in the 512-GByte region
controlled by this entry. If that control is 0, this bit is ignored.
11
Ignored
(N–1):12
Physical address of 4-KByte aligned EPT page-directory-pointer table referenced by this entry1
51:N
Reserved (must be 0)
63:52
Ignored
1. No processors supporting the Intel 64 architecture support more than 48 physical-address bits. Thus, no such processor can produce a guest-physical address with more than 48 bits. An attempt to use such an address causes a page fault. An attempt to load
CR3 with such an address causes a general-protection fault. If PAE paging is being used, an attempt to load CR3 that would load a
PDPTE with such an address causes a general-protection fault.
2. Future processors may include support for other EPT page-walk lengths. Software should read the VMX capability MSR
IA32_VMX_EPT_VPID_CAP (see Appendix A.10) to determine what EPT page-walk lengths are supported.
Vol. 3C 28-3
VMX SUPPORT FOR ADDRESS TRANSLATION
NOTES:
1. N is the physical-address width supported by the processor. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX.
•
A 4-KByte naturally aligned EPT page-directory-pointer table is located at the physical address specified in
bits 51:12 of the EPT PML4E. An EPT page-directory-pointer table comprises 512 64-bit entries (EPT PDPTEs).
An EPT PDPTE is selected using the physical address defined as follows:
— Bits 63:52 are all 0.
— Bits 51:12 are from the EPT PML4E.
— Bits 11:3 are bits 38:30 of the guest-physical address.
— Bits 2:0 are all 0.
Because an EPT PDPTE is identified using bits 47:30 of the guest-physical address, it controls access to a 1-GByte
region of the guest-physical-address space. Use of the EPT PDPTE depends on the value of bit 7 in that entry:1
•
If bit 7 of the EPT PDPTE is 1, the EPT PDPTE maps a 1-GByte page. The final physical address is computed as
follows:
— Bits 63:52 are all 0.
— Bits 51:30 are from the EPT PDPTE.
— Bits 29:0 are from the original guest-physical address.
The format of an EPT PDPTE that maps a 1-GByte page is given in Table 28-2.
•
If bit 7 of the EPT PDPTE is 0, a 4-KByte naturally aligned EPT page directory is located at the physical address
specified in bits 51:12 of the EPT PDPTE. The format of an EPT PDPTE that references an EPT page directory is
given in Table 28-3.
1. Not all processors allow bit 7 of an EPT PDPTE to be set to 1. Software should read the VMX capability MSR
IA32_VMX_EPT_VPID_CAP (see Appendix A.10) to determine whether this is allowed.
28-4 Vol. 3C
VMX SUPPORT FOR ADDRESS TRANSLATION
Table 28-2. Format of an EPT Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
Bit
Position(s)
Contents
0
Read access; indicates whether reads are allowed from the 1-GByte page referenced by this entry
1
Write access; indicates whether writes are allowed from the 1-GByte page referenced by this entry
2
If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether
instruction fetches are allowed from the 1-GByte page controlled by this entry
If that control is 1, execute access for supervisor-mode linear addresses; indicates whether instruction fetches are
allowed from supervisor-mode linear addresses in the 1-GByte page controlled by this entry
5:3
EPT memory type for this 1-GByte page (see Section 28.2.6)
6
Ignore PAT memory type for this 1-GByte page (see Section 28.2.6)
7
Must be 1 (otherwise, this entry references an EPT page directory)
8
If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 1-GByte page referenced
by this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
9
If bit 6 of EPTP is 1, dirty flag for EPT; indicates whether software has written to the 1-GByte page referenced by
this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
10
Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is
1, indicates whether instruction fetches are allowed from user-mode linear addresses in the 1-GByte page controlled
by this entry. If that control is 0, this bit is ignored.
11
Ignored
29:12
Reserved (must be 0)
(N–1):30
Physical address of the 1-GByte page referenced by this entry1
51:N
Reserved (must be 0)
62:52
Ignored
63
Suppress #VE. If the “EPT-violation #VE” VM-execution control is 1, EPT violations caused by accesses to this page
are convertible to virtualization exceptions only if this bit is 0 (see Section 25.5.6.1). If “EPT-violation #VE” VMexecution control is 0, this bit is ignored.
NOTES:
1. N is the physical-address width supported by the logical processor.
Vol. 3C 28-5
VMX SUPPORT FOR ADDRESS TRANSLATION
Table 28-3. Format of an EPT Page-Directory-Pointer-Table Entry (PDPTE) that References an EPT Page Directory
Bit
Position(s)
Contents
0
Read access; indicates whether reads are allowed from the 1-GByte region controlled by this entry
1
Write access; indicates whether writes are allowed from the 1-GByte region controlled by this entry
2
If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether instruction
fetches are allowed from the 1-GByte region controlled by this entry
If that control is 1, execute access for supervisor-mode linear addresses; indicates whether instruction fetches are
allowed from supervisor-mode linear addresses in the 1-GByte region controlled by this entry
7:3
Reserved (must be 0)
8
If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 1-GByte region controlled
by this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
9
Ignored
10
Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is
1, indicates whether instruction fetches are allowed from user-mode linear addresses in the 1-GByte region
controlled by this entry. If that control is 0, this bit is ignored.
11
Ignored
(N–1):12
Physical address of 4-KByte aligned EPT page directory referenced by this entry1
51:N
Reserved (must be 0)
63:52
Ignored
NOTES:
1. N is the physical-address width supported by the logical processor.
An EPT page-directory comprises 512 64-bit entries (PDEs). An EPT PDE is selected using the physical address
defined as follows:
— Bits 63:52 are all 0.
— Bits 51:12 are from the EPT PDPTE.
— Bits 11:3 are bits 29:21 of the guest-physical address.
— Bits 2:0 are all 0.
Because an EPT PDE is identified using bits 47:21 of the guest-physical address, it controls access to a 2-MByte
region of the guest-physical-address space. Use of the EPT PDE depends on the value of bit 7 in that entry:
•
If bit 7 of the EPT PDE is 1, the EPT PDE maps a 2-MByte page. The final physical address is computed as
follows:
— Bits 63:52 are all 0.
— Bits 51:21 are from the EPT PDE.
— Bits 20:0 are from the original guest-physical address.
The format of an EPT PDE that maps a 2-MByte page is given in Table 28-4.
•
If bit 7 of the EPT PDE is 0, a 4-KByte naturally aligned EPT page table is located at the physical address
specified in bits 51:12 of the EPT PDE. The format of an EPT PDE that references an EPT page table is given in
Table 28-5.
An EPT page table comprises 512 64-bit entries (PTEs). An EPT PTE is selected using a physical address defined
as follows:
— Bits 63:52 are all 0.
28-6 Vol. 3C
VMX SUPPORT FOR ADDRESS TRANSLATION
Table 28-4. Format of an EPT Page-Directory Entry (PDE) that Maps a 2-MByte Page
Bit
Position(s)
Contents
0
Read access; indicates whether reads are allowed from the 2-MByte page referenced by this entry
1
Write access; indicates whether writes are allowed from the 2-MByte page referenced by this entry
2
If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether instruction
fetches are allowed from the 2-MByte page controlled by this entry
If that control is 1, execute access for supervisor-mode linear addresses; indicates whether instruction fetches are
allowed from supervisor-mode linear addresses in the 2-MByte page controlled by this entry
5:3
EPT memory type for this 2-MByte page (see Section 28.2.6)
6
Ignore PAT memory type for this 2-MByte page (see Section 28.2.6)
7
Must be 1 (otherwise, this entry references an EPT page table)
8
If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 2-MByte page referenced
by this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
9
If bit 6 of EPTP is 1, dirty flag for EPT; indicates whether software has written to the 2-MByte page referenced by
this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
10
Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is
1, indicates whether instruction fetches are allowed from user-mode linear addresses in the 2-MByte page controlled
by this entry. If that control is 0, this bit is ignored.
11
Ignored
20:12
Reserved (must be 0)
(N–1):21
Physical address of the 2-MByte page referenced by this entry1
51:N
Reserved (must be 0)
62:52
Ignored
63
Suppress #VE. If the “EPT-violation #VE” VM-execution control is 1, EPT violations caused by accesses to this page
are convertible to virtualization exceptions only if this bit is 0 (see Section 25.5.6.1). If “EPT-violation #VE” VMexecution control is 0, this bit is ignored.
NOTES:
1. N is the physical-address width supported by the logical processor.
— Bits 51:12 are from the EPT PDE.
— Bits 11:3 are bits 20:12 of the guest-physical address.
— Bits 2:0 are all 0.
•
Because an EPT PTE is identified using bits 47:12 of the guest-physical address, every EPT PTE maps a 4-KByte
page. The final physical address is computed as follows:
— Bits 63:52 are all 0.
— Bits 51:12 are from the EPT PTE.
— Bits 11:0 are from the original guest-physical address.
The format of an EPT PTE is given in Table 28-6.
An EPT paging-structure entry is present if any of bits 2:0 is 1; otherwise, the entry is not present. The processor
ignores bits 62:3 and uses the entry neither to reference another EPT paging-structure entry nor to produce a
physical address. A reference using a guest-physical address whose translation encounters an EPT paging-strucVol. 3C 28-7
VMX SUPPORT FOR ADDRESS TRANSLATION
ture that is not present causes an EPT violation (see Section 28.2.3.2). (If the “EPT-violation #VE” VM-execution
control is 1, the EPT violation is convertible to a virtualization exception only if bit 63 is 0; see Section 25.5.6.1. If
the “EPT-violation #VE” VM-execution control is 0, this bit is ignored.)
Table 28-5. Format of an EPT Page-Directory Entry (PDE) that References an EPT Page Table
Bit
Position(s)
Contents
0
Read access; indicates whether reads are allowed from the 2-MByte region controlled by this entry
1
Write access; indicates whether writes are allowed from the 2-MByte region controlled by this entry
2
If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether instruction
fetches are allowed from the 2-MByte region controlled by this entry
If that control is 1, execute access for supervisor-mode linear addresses; indicates whether instruction fetches are
allowed from supervisor-mode linear addresses in the 2-MByte region controlled by this entry
6:3
Reserved (must be 0)
7
Must be 0 (otherwise, this entry maps a 2-MByte page)
8
If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 2-MByte region controlled
by this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
9
Ignored
10
Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is
1, indicates whether instruction fetches are allowed from user-mode linear addresses in the 2-MByte region
controlled by this entry. If that control is 0, this bit is ignored.
11
Ignored
(N–1):12
Physical address of 4-KByte aligned EPT page table referenced by this entry1
51:N
Reserved (must be 0)
63:52
Ignored
NOTES:
1. N is the physical-address width supported by the logical processor.
NOTE
If the “mode-based execute control for EPT” VM-execution control is 1, an EPT paging-structure
entry is present if any of bits 2:0 or bit 10 is 1. If bits 2:0 are all 0 but bit 10 is 1, the entry is used
normally to reference another EPT paging-structure entry or to produce a physical address.
The discussion above describes how the EPT paging structures reference each other and how the logical processor
traverses those structures when translating a guest-physical address. It does not cover all details of the translation
process. Additional details are provided as follows:
•
Situations in which the translation process may lead to VM exits (sometimes before the process completes) are
described in Section 28.2.3.
•
Interactions between the EPT translation mechanism and memory typing are described in Section 28.2.6.
Figure 28-1 gives a summary of the formats of the EPTP and the EPT paging-structure entries. For the EPT paging
structure entries, it identifies separately the format of entries that map pages, those that reference other EPT
paging structures, and those that do neither because they are not present; bits 2:0 and bit 7 are highlighted
because they determine how a paging-structure entry is used. (Figure 28-1 does not comprehend the fact that, if
the “mode-based execute control for EPT” VM-execution control is 1, an entry is present if any of bits 2:0 or bit 10
is 1.)
28-8 Vol. 3C
VMX SUPPORT FOR ADDRESS TRANSLATION
28.2.3
EPT-Induced VM Exits
Accesses using guest-physical addresses may cause VM exits due to EPT misconfigurations, EPT violations, and
page-modification log-full events. An EPT misconfiguration occurs when, in the course of translating a guestphysical address, the logical processor encounters an EPT paging-structure entry that contains an unsupported
value (see Section 28.2.3.1). An EPT violation occurs when there is no EPT misconfiguration but the EPT pagingstructure entries disallow an access using the guest-physical address (see Section 28.2.3.2). A page-modifica-
Table 28-6. Format of an EPT Page-Table Entry that Maps a 4-KByte Page
Bit
Position(s)
Contents
0
Read access; indicates whether reads are allowed from the 4-KByte page referenced by this entry
1
Write access; indicates whether writes are allowed from the 4-KByte page referenced by this entry
2
If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether
instruction fetches are allowed from the 4-KByte page controlled by this entry
If that control is 1, execute access for supervisor-mode linear addresses; indicates whether instruction fetches are
allowed from supervisor-mode linear addresses in the 4-KByte page controlled by this entry
5:3
EPT memory type for this 4-KByte page (see Section 28.2.6)
6
Ignore PAT memory type for this 4-KByte page (see Section 28.2.6)
7
Ignored
8
If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 4-KByte page referenced
by this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
9
If bit 6 of EPTP is 1, dirty flag for EPT; indicates whether software has written to the 4-KByte page referenced by
this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0
10
Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is
1, indicates whether instruction fetches are allowed from user-mode linear addresses in the 4-KByte page controlled
by this entry. If that control is 0, this bit is ignored.
11
Ignored
(N–1):12
Physical address of the 4-KByte page referenced by this entry1
51:N
Reserved (must be 0)
62:52
Ignored
63
Suppress #VE. If the “EPT-violation #VE” VM-execution control is 1, EPT violations caused by accesses to this page
are convertible to virtualization exceptions only if this bit is 0 (see Section 25.5.6.1). If “EPT-violation #VE” VMexecution control is 0, this bit is ignored.
NOTES:
1. N is the physical-address width supported by the logical processor.
tion log-full event occurs when the logical processor determines a need to create a page-modification log entry
and the current log is full (see Section 28.2.5).
These events occur only due to an attempt to access memory with a guest-physical address. Loading CR3 with a
guest-physical address with the MOV to CR3 instruction can cause neither an EPT configuration nor an EPT violation
until that address is used to access a paging structure.1
If the “EPT-violation #VE” VM-execution control is 1, certain EPT violations may cause virtualization exceptions
instead of VM exits. See Section 25.5.6.1.
Vol. 3C 28-9
VMX SUPPORT FOR ADDRESS TRANSLATION
28.2.3.1
EPT Misconfigurations
An EPT misconfiguration occurs if translation of a guest-physical address encounters an EPT paging-structure that
meets any of the following conditions:
•
Bit 0 of the entry is clear (indicating that data reads are not allowed) and bit 1 is set (indicating that data writes
are allowed).
•
Either of the following if the processor does not support execute-only translations:
— Bit 0 of the entry is clear (indicating that data reads are not allowed) and bit 2 is set (indicating that
instruction fetches are allowed).1
— The “mode-based execute control for EPT” VM-execution control is 1, bit 0 of the entry is clear (indicating
that data reads are not allowed), and bit 10 is set (indicating that instruction fetches are allowed from usermode linear addresses).
Software should read the VMX capability MSR IA32_VMX_EPT_VPID_CAP to determine whether execute-only
translations are supported (see Appendix A.10).
•
The entry is present (see Section 28.2.2) and one of the following holds:
— A reserved bit is set. This includes the setting of a bit in the range 51:12 that is beyond the logical
processor’s physical-address width.2 See Section 28.2.2 for details of which bits are reserved in which EPT
paging-structure entries.
— The entry is the last one used to translate a guest physical address (either an EPT PDE with bit 7 set to 1 or
an EPT PTE) and the value of bits 5:3 (EPT memory type) is 2, 3, or 7 (these values are reserved).
EPT misconfigurations result when an EPT paging-structure entry is configured with settings reserved for future
functionality. Software developers should be aware that such settings may be used in the future and that an EPT
paging-structure entry that causes an EPT misconfiguration on one processor might not do so in the future.
28.2.3.2
EPT Violations
An EPT violation may occur during an access using a guest-physical address whose translation does not cause an
EPT misconfiguration. An EPT violation occurs in any of the following situations:
•
Translation of the guest-physical address encounters an EPT paging-structure entry that is not present (see
Section 28.2.2).
•
The access is a data read and, for any byte to be read, bit 0 (read access) was clear in any of the EPT pagingstructure entries used to translate the guest-physical address of the byte. Reads by the logical processor of
guest paging structures to translate a linear address are considered to be data reads.
1. If the logical processor is using PAE paging—because CR0.PG = CR4.PAE = 1 and IA32_EFER.LMA = 0—the MOV to CR3 instruction
loads the PDPTEs from memory using the guest-physical address being loaded into CR3. In this case, therefore, the MOV to CR3
instruction may cause an EPT misconfiguration, an EPT violation, or a page-modification log-full event.
1. If the “mode-based execute control for EPT” VM-execution control is 1, setting bit 2 indicates that instruction fetches are allowed
from supervisor-mode linear addresses.
2. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
28-10 Vol. 3C
VMX SUPPORT FOR ADDRESS TRANSLATION
6666555555555
3210987654321
M1 M-1
Reserved
Ignored
Rsvd.
33322222222221111111111
210987654321098765432109876543210
A EPT EPT
Address of EPT PML4 table
Rsvd.
/ PWL– PS
D 1
MT
Address of EPT page-directory-pointer table
S
V
E6
S
V
E
Ignored
Rsvd.
Rsvd.
S
V
E
S
V
E
Ignored
Rsvd.
Rsvd.
S
V
E
S
V
E
000
PML4E:
not
present
Physical
address of
1GB page
Reserved
I
Ig X D A 1 P EPT X W R
n. U
A MT
T
PDPTE:
1GB
page
Address of EPT page directory
Ig X Ig A 0 Rsvd. X W R PDPTE:
page
n. U n.
directory
Ignored
Ignored
S
V
E
Ig X
Ig A Reserved X W R PML4E:
4
n. U
present5
3 n.
Ignored
Ignored
Physical address
of 2MB page
000
Reserved
Address of EPT page table
Rsvd.
Physical address of 4KB page
PDTPE:
not
present
I
Ig X D A 1 P EPT X W R
n. U
A MT
T
PDE:
2MB
page
Ig X Ig A 0 Rsvd. X W R
n. U n.
PDE:
page
table
Ignored
Ignored
EPTP2
000
I
Ig X D A gI P EPT X W R
n. U
MT
n A
T
Ignored
000
PDE:
not
present
PTE:
4KB
page
PTE:
not
present
Figure 28-1. Formats of EPTP and EPT Paging-Structure Entries
NOTES:
1. M is an abbreviation for MAXPHYADDR.
2. See Section 24.6.11 for details of the EPTP.
3. Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is 0, this bit is
ignored.
4. Execute access. If the “mode-based execute control for EPT” VM-execution control is 1, this bit controls execute access for supervisor-mode linear addresses.
5. If the “mode-based execute control for EPT” VM-execution control is 1, an EPT paging-structure entry is present if any of bits 2:0 or
bit 10 is 1. This table does not comprehend that fact.
6. Suppress #VE. If the “EPT-violation #VE” VM-execution control is 0, this bit is ignored.
•
The access is a data write, for any byte to be written, bit 1 (write access) was clear in any of the EPT pagingstructure entries used to translate the guest-physical address of the byte. Writes by the logical processor to
guest paging structures to update accessed and dirty flags are considered to be data writes.
If bit 6 of the EPT pointer (EPTP) is 1 (enabling accessed and dirty flags for EPT), processor accesses to guest
paging-structure entries are treated as writes with regard to EPT violations. Thus, if bit 1 is clear in any of the
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EPT paging-structure entries used to translate the guest-physical address of a guest paging-structure entry, an
attempt to use that entry to translate a linear address causes an EPT violation.
(This does not apply to loads of the PDPTE registers by the MOV to CR instruction for PAE paging; see Section
4.4.1. Those loads of guest PDPTEs are treated as reads and do not cause EPT violations due to a guest-physical
address not being writable.)
•
The access is an instruction fetch and the EPT paging structures prevent execute access to any of the bytes
being fetched. Whether this occurs depends upon the setting of the “mode-based execute control for EPT” VMexecution control:
— If the control is 0, an instruction fetch from a byte is prevented if bit 2 (execute access) was clear in any of
the EPT paging-structure entries used to translate the guest-physical address of the byte.
— If the control is 1, an instruction fetch from a byte is prevented in either of the following cases:
•
Paging maps the linear address of the byte as a supervisor-mode address and bit 2 (execute access for
supervisor-mode linear addresses) was clear in any of the EPT paging-structure entries used to
translate the guest-physical address of the byte.
Paging maps a linear address as a supervisor-mode address if the U/S flag (bit 2) is 0 in at least one of
the paging-structure entries controlling the translation of the linear address.
•
Paging maps the linear address of the byte as a user-mode address and bit 10 (execute access for usermode linear addresses) was clear in any of the EPT paging-structure entries used to translate the guestphysical address of the byte.
Paging maps a linear address as a user-mode address if the U/S flag is 1 in all of the paging-structure
entries controlling the translation of the linear address. If paging is disabled (CR0.PG = 0), every linear
address is a user-mode address.
28.2.3.3
Prioritization of EPT Misconfigurations and EPT Violations
The translation of a linear address to a physical address requires one or more translations of guest-physical
addresses using EPT (see Section 28.2.1). This section specifies the relative priority of EPT-induced VM exits with
respect to each other and to other events that may be encountered when accessing memory using a linear address.
For an access to a guest-physical address, determination of whether an EPT misconfiguration or an EPT violation
occurs is based on an iterative process:1
1. An EPT paging-structure entry is read (initially, this is an EPT PML4 entry):
a. If the entry is not present (see Section 28.2.2), an EPT violation occurs.
b. If the entry is present but its contents are not configured properly (see Section 28.2.3.1), an EPT misconfiguration occurs.
c.
If the entry is present and its contents are configured properly, operation depends on whether the entry
references another EPT paging structure (whether it is an EPT PDE with bit 7 set to 1 or an EPT PTE):
i)
If the entry does reference another EPT paging structure, an entry from that structure is accessed;
step 1 is executed for that other entry.
ii) Otherwise, the entry is used to produce the ultimate physical address (the translation of the original
guest-physical address); step 2 is executed.
2. Once the ultimate physical address is determined, the privileges determined by the EPT paging-structure
entries are evaluated:
a. If the access to the guest-physical address is not allowed by these privileges (see Section 28.2.3.2), an EPT
violation occurs.
b. If the access to the guest-physical address is allowed by these privileges, memory is accessed using the
ultimate physical address.
If CR0.PG = 1, the translation of a linear address is also an iterative process, with the processor first accessing an
entry in the guest paging structure referenced by the guest-physical address in CR3 (or, if PAE paging is in use, the
1. This is a simplification of the more detailed description given in Section 28.2.2.
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guest-physical address in the appropriate PDPTE register), then accessing an entry in another guest paging structure referenced by the guest-physical address in the first guest paging-structure entry, etc. Each guest-physical
address is itself translated using EPT and may cause an EPT-induced VM exit. The following items detail how page
faults and EPT-induced VM exits are recognized during this iterative process:
1. An attempt is made to access a guest paging-structure entry with a guest-physical address (initially, the
address in CR3 or PDPTE register).
a. If the access fails because of an EPT misconfiguration or an EPT violation (see above), an EPT-induced
VM exit occurs.
b. If the access does not cause an EPT-induced VM exit, bit 0 (the present flag) of the entry is consulted:
i)
If the present flag is 0 or any reserved bit is set, a page fault occurs.
ii) If the present flag is 1, no reserved bit is set, operation depends on whether the entry references
another guest paging structure (whether it is a guest PDE with PS = 1 or a guest PTE):
•
If the entry does reference another guest paging structure, an entry from that structure is
accessed; step 1 is executed for that other entry.
•
Otherwise, the entry is used to produce the ultimate guest-physical address (the translation of the
original linear address); step 2 is executed.
2. Once the ultimate guest-physical address is determined, the privileges determined by the guest pagingstructure entries are evaluated:
a. If the access to the linear address is not allowed by these privileges (e.g., it was a write to a read-only
page), a page fault occurs.
b. If the access to the linear address is allowed by these privileges, an attempt is made to access memory at
the ultimate guest-physical address:
i)
If the access fails because of an EPT misconfiguration or an EPT violation (see above), an EPT-induced
VM exit occurs.
ii) If the access does not cause an EPT-induced VM exit, memory is accessed using the ultimate physical
address (the translation, using EPT, of the ultimate guest-physical address).
If CR0.PG = 0, a linear address is treated as a guest-physical address and is translated using EPT (see above). This
process, if it completes without an EPT violation or EPT misconfiguration, produces a physical address and determines the privileges allowed by the EPT paging-structure entries. If these privileges do not allow the access to the
physical address (see Section 28.2.3.2), an EPT violation occurs. Otherwise, memory is accessed using the physical address.
28.2.4
Accessed and Dirty Flags for EPT
The Intel 64 architecture supports accessed and dirty flags in ordinary paging-structure entries (see Section
4.8). Some processors also support corresponding flags in EPT paging-structure entries. Software should read the
VMX capability MSR IA32_VMX_EPT_VPID_CAP (see Appendix A.10) to determine whether the processor supports
this feature.
Software can enable accessed and dirty flags for EPT using bit 6 of the extended-page-table pointer (EPTP), a VMexecution control field (see Table 24-8 in Section 24.6.11). If this bit is 1, the processor will set the accessed and
dirty flags for EPT as described below. In addition, setting this flag causes processor accesses to guest pagingstructure entries to be treated as writes (see below and Section 28.2.3.2).
For any EPT paging-structure entry that is used during guest-physical-address translation, bit 8 is the accessed
flag. For a EPT paging-structure entry that maps a page (as opposed to referencing another EPT paging structure),
bit 9 is the dirty flag.
Whenever the processor uses an EPT paging-structure entry as part of guest-physical-address translation, it sets
the accessed flag in that entry (if it is not already set).
Whenever there is a write to a guest-physical address, the processor sets the dirty flag (if it is not already set) in
the EPT paging-structure entry that identifies the final physical address for the guest-physical address (either an
EPT PTE or an EPT paging-structure entry in which bit 7 is 1).
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When accessed and dirty flags for EPT are enabled, processor accesses to guest paging-structure entries are
treated as writes (see Section 28.2.3.2). Thus, such an access will cause the processor to set the dirty flag in the
EPT paging-structure entry that identifies the final physical address of the guest paging-structure entry.
(This does not apply to loads of the PDPTE registers for PAE paging by the MOV to CR instruction; see Section 4.4.1.
Those loads of guest PDPTEs are treated as reads and do not cause the processor to set the dirty flag in any EPT
paging-structure entry.)
These flags are “sticky,” meaning that, once set, the processor does not clear them; only software can clear them.
A processor may cache information from the EPT paging-structure entries in TLBs and paging-structure caches (see
Section 28.3). This fact implies that, if software changes an accessed flag or a dirty flag from 1 to 0, the processor
might not set the corresponding bit in memory on a subsequent access using an affected guest-physical address.
28.2.5
Page-Modification Logging
When accessed and dirty flags for EPT are enabled, software can track writes to guest-physical addresses using a
feature called page-modification logging.
Software can enable page-modification logging by setting the “enable PML” VM-execution control (see Table 24-7
in Section 24.6.2). When this control is 1, the processor adds entries to the page-modification log as described
below. The page-modification log is a 4-KByte region of memory located at the physical address in the PML address
VM-execution control field. The page-modification log consists of 512 64-bit entries; the PML index VM-execution
control field indicates the next entry to use.
Before allowing a guest-physical access, the processor may determine that it first needs to set an accessed or dirty
flag for EPT (see Section 28.2.4). When this happens, the processor examines the PML index. If the PML index is
not in the range 0–511, there is a page-modification log-full event and a VM exit occurs. In this case, the
accessed or dirty flag is not set, and the guest-physical access that triggered the event does not occur.
If instead the PML index is in the range 0–511, the processor proceeds to update accessed or dirty flags for EPT as
described in Section 28.2.4. If the processor updated a dirty flag for EPT (changing it from 0 to 1), it then operates
as follows:
1. The guest-physical address of the access is written to the page-modification log. Specifically, the guest-physical
address is written to physical address determined by adding 8 times the PML index to the PML address.
Bits 11:0 of the value written are always 0 (the guest-physical address written is thus 4-KByte aligned).
2. The PML index is decremented by 1 (this may cause the value to transition from 0 to FFFFH).
Because the processor decrements the PML index with each log entry, the value may transition from 0 to FFFFH. At
that point, no further logging will occur, as the processor will determine that the PML index is not in the range 0–
511 and will generate a page-modification log-full event (see above).
28.2.6
EPT and Memory Typing
This section specifies how a logical processor determines the memory type use for a memory access while EPT is in
use. (See Chapter 11, “Memory Cache Control” of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A for details of memory typing in the Intel 64 architecture.) Section 28.2.6.1 explains how the memory
type is determined for accesses to the EPT paging structures. Section 28.2.6.2 explains how the memory type is
determined for an access using a guest-physical address that is translated using EPT.
28.2.6.1
Memory Type Used for Accessing EPT Paging Structures
This section explains how the memory type is determined for accesses to the EPT paging structures. The determination is based first on the value of bit 30 (cache disable—CD) in control register CR0:
•
If CR0.CD = 0, the memory type used for any such reference is the EPT paging-structure memory type, which
is specified in bits 2:0 of the extended-page-table pointer (EPTP), a VM-execution control field (see Section
24.6.11). A value of 0 indicates the uncacheable type (UC), while a value of 6 indicates the write-back type
(WB). Other values are reserved.
•
If CR0.CD = 1, the memory type used for any such reference is uncacheable (UC).
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The MTRRs have no effect on the memory type used for an access to an EPT paging structure.
28.2.6.2
Memory Type Used for Translated Guest-Physical Addresses
The effective memory type of a memory access using a guest-physical address (an access that is translated
using EPT) is the memory type that is used to access memory. The effective memory type is based on the value of
bit 30 (cache disable—CD) in control register CR0; the last EPT paging-structure entry used to translate the guestphysical address (either an EPT PDE with bit 7 set to 1 or an EPT PTE); and the PAT memory type (see below):
•
The PAT memory type depends on the value of CR0.PG:
— If CR0.PG = 0, the PAT memory type is WB (writeback).1
— If CR0.PG = 1, the PAT memory type is the memory type selected from the IA32_PAT MSR as specified in
Section 11.12.3, “Selecting a Memory Type from the PAT”.2
•
The EPT memory type is specified in bits 5:3 of the last EPT paging-structure entry: 0 = UC; 1 = WC; 4 =
WT; 5 = WP; and 6 = WB. Other values are reserved and cause EPT misconfigurations (see Section 28.2.3).
•
If CR0.CD = 0, the effective memory type depends upon the value of bit 6 of the last EPT paging-structure
entry:
— If the value is 0, the effective memory type is the combination of the EPT memory type and the PAT
memory type specified in Table 11-7 in Section 11.5.2.2, using the EPT memory type in place of the MTRR
memory type.
— If the value is 1, the memory type used for the access is the EPT memory type. The PAT memory type is
ignored.
•
If CR0.CD = 1, the effective memory type is UC.
The MTRRs have no effect on the memory type used for an access to a guest-physical address.
28.3
CACHING TRANSLATION INFORMATION
Processors supporting Intel® 64 and IA-32 architectures may accelerate the address-translation process by
caching on the processor data from the structures in memory that control that process. Such caching is discussed
in Section 4.10, “Caching Translation Information” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A. The current section describes how this caching interacts with the VMX architecture.
The VPID and EPT features of the architecture for VMX operation augment this caching architecture. EPT defines
the guest-physical address space and defines translations to that address space (from the linear-address space)
and from that address space (to the physical-address space). Both features control the ways in which a logical
processor may create and use information cached from the paging structures.
Section 28.3.1 describes the different kinds of information that may be cached. Section 28.3.2 specifies when such
information may be cached and how it may be used. Section 28.3.3 details how software can invalidate cached
information.
28.3.1
Information That May Be Cached
Section 4.10, “Caching Translation Information” in Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A identifies two kinds of translation-related information that may be cached by a logical
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG can be 0 in VMX non-root
operation only if the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls
are both 1.
2. Table 11-11 in Section 11.12.3, “Selecting a Memory Type from the PAT” illustrates how the PAT memory type is selected based on
the values of the PAT, PCD, and PWT bits in a page-table entry (or page-directory entry with PS = 1). For accesses to a guest pagingstructure entry X, the PAT memory type is selected from the table by using a value of 0 for the PAT bit with the values of PCD and
PWT from the paging-structure entry Y that references X (or from CR3 if X is in the root paging structure). With PAE paging, the PAT
memory type for accesses to the PDPTEs is WB.
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processor: translations, which are mappings from linear page numbers to physical page frames, and pagingstructure caches, which map the upper bits of a linear page number to information from the paging-structure
entries used to translate linear addresses matching those upper bits.
The same kinds of information may be cached when VPIDs and EPT are in use. A logical processor may cache and
use such information based on its function. Information with different functionality is identified as follows:
•
Linear mappings.1 There are two kinds:
— Linear translations. Each of these is a mapping from a linear page number to the physical page frame to
which it translates, along with information about access privileges and memory typing.
— Linear paging-structure-cache entries. Each of these is a mapping from the upper portion of a linear
address to the physical address of the paging structure used to translate the corresponding region of the
linear-address space, along with information about access privileges. For example, bits 47:39 of a linear
address would map to the address of the relevant page-directory-pointer table.
Linear mappings do not contain information from any EPT paging structure.
•
Guest-physical mappings.2 There are two kinds:
— Guest-physical translations. Each of these is a mapping from a guest-physical page number to the physical
page frame to which it translates, along with information about access privileges and memory typing.
— Guest-physical paging-structure-cache entries. Each of these is a mapping from the upper portion of a
guest-physical address to the physical address of the EPT paging structure used to translate the corresponding region of the guest-physical address space, along with information about access privileges.
The information in guest-physical mappings about access privileges and memory typing is derived from EPT
paging structures.
•
Combined mappings.3 There are two kinds:
— Combined translations. Each of these is a mapping from a linear page number to the physical page frame to
which it translates, along with information about access privileges and memory typing.
— Combined paging-structure-cache entries. Each of these is a mapping from the upper portion of a linear
address to the physical address of the paging structure used to translate the corresponding region of the
linear-address space, along with information about access privileges.
The information in combined mappings about access privileges and memory typing is derived from both guest
paging structures and EPT paging structures.
28.3.2
Creating and Using Cached Translation Information
The following items detail the creation of the mappings described in the previous section:4
•
The following items describe the creation of mappings while EPT is not in use (including execution outside VMX
non-root operation):
— Linear mappings may be created. They are derived from the paging structures referenced (directly or
indirectly) by the current value of CR3 and are associated with the current VPID and the current PCID.
— No linear mappings are created with information derived from paging-structure entries that are not present
(bit 0 is 0) or that set reserved bits. For example, if a PTE is not present, no linear mapping are created for
any linear page number whose translation would use that PTE.
— No guest-physical or combined mappings are created while EPT is not in use.
•
The following items describe the creation of mappings while EPT is in use:
1. Earlier versions of this manual used the term “VPID-tagged” to identify linear mappings.
2. Earlier versions of this manual used the term “EPTP-tagged” to identify guest-physical mappings.
3. Earlier versions of this manual used the term “dual-tagged” to identify combined mappings.
4. This section associated cached information with the current VPID and PCID. If PCIDs are not supported or are not being used (e.g.,
because CR4.PCIDE = 0), all the information is implicitly associated with PCID 000H; see Section 4.10.1, “Process-Context Identifiers
(PCIDs),” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
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— Guest-physical mappings may be created. They are derived from the EPT paging structures referenced
(directly or indirectly) by bits 51:12 of the current EPTP. These 40 bits contain the address of the EPT-PML4table. (the notation EP4TA refers to those 40 bits). Newly created guest-physical mappings are associated
with the current EP4TA.
— Combined mappings may be created. They are derived from the EPT paging structures referenced (directly
or indirectly) by the current EP4TA. If CR0.PG = 1, they are also derived from the paging structures
referenced (directly or indirectly) by the current value of CR3. They are associated with the current VPID,
the current PCID, and the current EP4TA.1 No combined paging-structure-cache entries are created if
CR0.PG = 0.2
— No guest-physical mappings or combined mappings are created with information derived from EPT pagingstructure entries that are not present (see Section 28.2.2) or that are misconfigured (see Section
28.2.3.1).
— No combined mappings are created with information derived from guest paging-structure entries that are
not present or that set reserved bits.
— No linear mappings are created while EPT is in use.
The following items detail the use of the various mappings:
•
If EPT is not in use (e.g., when outside VMX non-root operation), a logical processor may use cached mappings
as follows:
— For accesses using linear addresses, it may use linear mappings associated with the current VPID and the
current PCID. It may also use global TLB entries (linear mappings) associated with the current VPID and
any PCID.
— No guest-physical or combined mappings are used while EPT is not in use.
•
If EPT is in use, a logical processor may use cached mappings as follows:
— For accesses using linear addresses, it may use combined mappings associated with the current VPID, the
current PCID, and the current EP4TA. It may also use global TLB entries (combined mappings) associated
with the current VPID, the current EP4TA, and any PCID.
— For accesses using guest-physical addresses, it may use guest-physical mappings associated with the
current EP4TA.
— No linear mappings are used while EPT is in use.
28.3.3
Invalidating Cached Translation Information
Software modifications of paging structures (including EPT paging structures) may result in inconsistencies
between those structures and the mappings cached by a logical processor. Certain operations invalidate information cached by a logical processor and can be used to eliminate such inconsistencies.
28.3.3.1
Operations that Invalidate Cached Mappings
The following operations invalidate cached mappings as indicated:
•
Operations that architecturally invalidate entries in the TLBs or paging-structure caches independent of VMX
operation (e.g., the INVLPG and INVPCID instructions) invalidate linear mappings and combined mappings.3
They are required to do so only for the current VPID (but, for combined mappings, all EP4TAs). Linear
1. At any given time, a logical processor may be caching combined mappings for a VPID and a PCID that are associated with different
EP4TAs. Similarly, it may be caching combined mappings for an EP4TA that are associated with different VPIDs and PCIDs.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG can be 0 in VMX non-root
operation only if the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls
are both 1.
3. See Section 4.10.4, “Invalidation of TLBs and Paging-Structure Caches,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A for an enumeration of operations that architecturally invalidate entries in the TLBs and paging-structure
caches independent of VMX operation.
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mappings for the current VPID are invalidated even if EPT is in use.1 Combined mappings for the current
VPID are invalidated even if EPT is not in use.2
•
An EPT violation invalidates any guest-physical mappings (associated with the current EP4TA) that would be
used to translate the guest-physical address that caused the EPT violation. If that guest-physical address was
the translation of a linear address, the EPT violation also invalidates any combined mappings for that linear
address associated with the current PCID, the current VPID and the current EP4TA.
•
If the “enable VPID” VM-execution control is 0, VM entries and VM exits invalidate linear mappings and
combined mappings associated with VPID 0000H (for all PCIDs). Combined mappings for VPID 0000H are
invalidated for all EP4TAs.
•
Execution of the INVVPID instruction invalidates linear mappings and combined mappings. Invalidation is
based on instruction operands, called the INVVPID type and the INVVPID descriptor. Four INVVPID types are
currently defined:
— Individual-address. If the INVVPID type is 0, the logical processor invalidates linear mappings and
combined mappings associated with the VPID specified in the INVVPID descriptor and that would be used
to translate the linear address specified in of the INVVPID descriptor. Linear mappings and combined
mappings for that VPID and linear address are invalidated for all PCIDs and, for combined mappings, all
EP4TAs. (The instruction may also invalidate mappings associated with other VPIDs and for other linear
addresses.)
— Single-context. If the INVVPID type is 1, the logical processor invalidates all linear mappings and
combined mappings associated with the VPID specified in the INVVPID descriptor. Linear mappings and
combined mappings for that VPID are invalidated for all PCIDs and, for combined mappings, all EP4TAs.
(The instruction may also invalidate mappings associated with other VPIDs.)
— All-context. If the INVVPID type is 2, the logical processor invalidates linear mappings and combined
mappings associated with all VPIDs except VPID 0000H and with all PCIDs. (The instruction may also
invalidate linear mappings with VPID 0000H.) Combined mappings are invalidated for all EP4TAs.
— Single-context-retaining-globals. If the INVVPID type is 3, the logical processor invalidates linear
mappings and combined mappings associated with the VPID specified in the INVVPID descriptor. Linear
mappings and combined mappings for that VPID are invalidated for all PCIDs and, for combined mappings,
all EP4TAs. The logical processor is not required to invalidate information that was used for global translations (although it may do so). See Section 4.10, “Caching Translation Information” for details regarding
global translations. (The instruction may also invalidate mappings associated with other VPIDs.)
See Chapter 30 for details of the INVVPID instruction. See Section 28.3.3.3 for guidelines regarding use of this
instruction.
•
Execution of the INVEPT instruction invalidates guest-physical mappings and combined mappings. Invalidation
is based on instruction operands, called the INVEPT type and the INVEPT descriptor. Two INVEPT types are
currently defined:
— Single-context. If the INVEPT type is 1, the logical processor invalidates all guest-physical mappings and
combined mappings associated with the EP4TA specified in the INVEPT descriptor. Combined mappings for
that EP4TA are invalidated for all VPIDs and all PCIDs. (The instruction may invalidate mappings associated
with other EP4TAs.)
— All-context. If the INVEPT type is 2, the logical processor invalidates guest-physical mappings and
combined mappings associated with all EP4TAs (and, for combined mappings, for all VPIDs and PCIDs).
See Chapter 30 for details of the INVEPT instruction. See Section 28.3.3.4 for guidelines regarding use of this
instruction.
•
A power-up or a reset invalidates all linear mappings, guest-physical mappings, and combined mappings.
1. While no linear mappings are created while EPT is in use, a logical processor may retain, while EPT is in use, linear mappings (for the
same VPID as the current one) there were created earlier, when EPT was not in use.
2. While no combined mappings are created while EPT is not in use, a logical processor may retain, while EPT is in not use, combined
mappings (for the same VPID as the current one) there were created earlier, when EPT was in use.
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28.3.3.2
Operations that Need Not Invalidate Cached Mappings
The following items detail cases of operations that are not required to invalidate certain cached mappings:
•
Operations that architecturally invalidate entries in the TLBs or paging-structure caches independent of VMX
operation are not required to invalidate any guest-physical mappings.
•
•
•
The INVVPID instruction is not required to invalidate any guest-physical mappings.
•
The VMXOFF and VMXON instructions are not required to invalidate any linear mappings, guest-physical
mappings, or combined mappings.
The INVEPT instruction is not required to invalidate any linear mappings.
VMX transitions are not required to invalidate any guest-physical mappings. If the “enable VPID” VM-execution
control is 1, VMX transitions are not required to invalidate any linear mappings or combined mappings.
A logical processor may invalidate any cached mappings at any time. For this reason, the operations identified
above may invalidate the indicated mappings despite the fact that doing so is not required.
28.3.3.3
Guidelines for Use of the INVVPID Instruction
The need for VMM software to use the INVVPID instruction depends on how that software is virtualizing memory
(e.g., see Section 32.3, “Memory Virtualization”).
If EPT is not in use, it is likely that the VMM is virtualizing the guest paging structures. Such a VMM may configure
the VMCS so that all or some of the operations that invalidate entries the TLBs and the paging-structure caches
(e.g., the INVLPG instruction) cause VM exits. If VMM software is emulating these operations, it may be necessary
to use the INVVPID instruction to ensure that the logical processor’s TLBs and the paging-structure caches are
appropriately invalidated.
Requirements of when software should use the INVVPID instruction depend on the specific algorithm being used
for page-table virtualization. The following items provide guidelines for software developers:
•
Emulation of the INVLPG instruction may require execution of the INVVPID instruction as follows:
— The INVVPID type is individual-address (0).
— The VPID in the INVVPID descriptor is the one assigned to the virtual processor whose execution is being
emulated.
— The linear address in the INVVPID descriptor is that of the operand of the INVLPG instruction being
emulated.
•
Some instructions invalidate all entries in the TLBs and paging-structure caches—except for global translations.
An example is the MOV to CR3 instruction. (See Section 4.10, “Caching Translation Information” in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A for details regarding global translations.)
Emulation of such an instruction may require execution of the INVVPID instruction as follows:
— The INVVPID type is single-context-retaining-globals (3).
— The VPID in the INVVPID descriptor is the one assigned to the virtual processor whose execution is being
emulated.
•
Some instructions invalidate all entries in the TLBs and paging-structure caches—including for global translations. An example is the MOV to CR4 instruction if the value of value of bit 4 (page global enable—PGE) is
changing. Emulation of such an instruction may require execution of the INVVPID instruction as follows:
— The INVVPID type is single-context (1).
— The VPID in the INVVPID descriptor is the one assigned to the virtual processor whose execution is being
emulated.
If EPT is not in use, the logical processor associates all mappings it creates with the current VPID, and it will use
such mappings to translate linear addresses. For that reason, a VMM should not use the same VPID for different
non-EPT guests that use different page tables. Doing so may result in one guest using translations that pertain to
the other.
If EPT is in use, the instructions enumerated above might not be configured to cause VM exits and the VMM might
not be emulating them. In that case, executions of the instructions by guest software properly invalidate the
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VMX SUPPORT FOR ADDRESS TRANSLATION
required entries in the TLBs and paging-structure caches (see Section 28.3.3.1); execution of the INVVPID instruction is not required.
If EPT is in use, the logical processor associates all mappings it creates with the value of bits 51:12 of current EPTP.
If a VMM uses different EPTP values for different guests, it may use the same VPID for those guests. Doing so
cannot result in one guest using translations that pertain to the other.
The following guidelines apply more generally and are appropriate even if EPT is in use:
•
As detailed in Section 29.4.5, an access to the APIC-access page might not cause an APIC-access VM exit if
software does not properly invalidate information that may be cached from the paging structures. If, at one
time, the current VPID on a logical processor was a non-zero value X, it is recommended that software use the
INVVPID instruction with the “single-context” INVVPID type and with VPID X in the INVVPID descriptor before
a VM entry on the same logical processor that establishes VPID X and either (a) the “virtualize APIC accesses”
VM-execution control was changed from 0 to 1; or (b) the value of the APIC-access address was changed.
•
Software can use the INVVPID instruction with the “all-context” INVVPID type immediately after execution of
the VMXON instruction or immediately prior to execution of the VMXOFF instruction. Either prevents potentially
undesired retention of information cached from paging structures between separate uses of VMX operation.
28.3.3.4
Guidelines for Use of the INVEPT Instruction
The following items provide guidelines for use of the INVEPT instruction to invalidate information cached from the
EPT paging structures.
•
Software should use the INVEPT instruction with the “single-context” INVEPT type after making any of the
following changes to an EPT paging-structure entry (the INVEPT descriptor should contain an EPTP value that
references — directly or indirectly — the modified EPT paging structure):
— Changing any of the privilege bits 2:0 from 1 to 0.1
— Changing the physical address in bits 51:12.
— Clearing bit 8 (the accessed flag) if accessed and dirty flags for EPT will be enabled.
— For an EPT PDPTE or an EPT PDE, changing bit 7 (which determines whether the entry maps a page).
— For the last EPT paging-structure entry used to translate a guest-physical address (an EPT PDPTE with bit 7
set to 1, an EPT PDE with bit 7 set to 1, or an EPT PTE), changing either bits 5:3 or bit 6. (These bits
determine the effective memory type of accesses using that EPT paging-structure entry; see Section
28.2.6.)
— For the last EPT paging-structure entry used to translate a guest-physical address (an EPT PDPTE with bit 7
set to 1, an EPT PDE with bit 7 set to 1, or an EPT PTE), clearing bit 9 (the dirty flag) if accessed and dirty
flags for EPT will be enabled.
•
Software should use the INVEPT instruction with the “single-context” INVEPT type before a VM entry with an
EPTP value X such that X[6] = 1 (accessed and dirty flags for EPT are enabled) if the logical processor had
earlier been in VMX non-root operation with an EPTP value Y such that Y[6] = 0 (accessed and dirty flags for
EPT are not enabled) and Y[51:12] = X[51:12].
•
Software may use the INVEPT instruction after modifying a present EPT paging-structure entry (see Section
28.2.2) to change any of the privilege bits 2:0 from 0 to 1.2 Failure to do so may cause an EPT violation that
would not otherwise occur. Because an EPT violation invalidates any mappings that would be used by the access
that caused the EPT violation (see Section 28.3.3.1), an EPT violation will not recur if the original access is
performed again, even if the INVEPT instruction is not executed.
•
Because a logical processor does not cache any information derived from EPT paging-structure entries that are
not present (see Section 28.2.2) or misconfigured (see Section 28.2.3.1), it is not necessary to execute INVEPT
following modification of an EPT paging-structure entry that had been not present or misconfigured.
1. If the “mode-based execute control for EPT” VM-execution control is 1, software should use the INVEPT instruction changing privilege bit 10 from 1 to 0.
2. If the “mode-based execute control for EPT” VM-execution control is 1, software may use the INVEPT instruction after modifying a
present EPT paging-structure entry to change privilege bit 10 from 0 to 1.
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VMX SUPPORT FOR ADDRESS TRANSLATION
•
As detailed in Section 29.4.5, an access to the APIC-access page might not cause an APIC-access VM exit if
software does not properly invalidate information that may be cached from the EPT paging structures. If EPT
was in use on a logical processor at one time with EPTP X, it is recommended that software use the INVEPT
instruction with the “single-context” INVEPT type and with EPTP X in the INVEPT descriptor before a VM entry
on the same logical processor that enables EPT with EPTP X and either (a) the “virtualize APIC accesses” VMexecution control was changed from 0 to 1; or (b) the value of the APIC-access address was changed.
•
Software can use the INVEPT instruction with the “all-context” INVEPT type immediately after execution of the
VMXON instruction or immediately prior to execution of the VMXOFF instruction. Either prevents potentially
undesired retention of information cached from EPT paging structures between separate uses of VMX
operation.
In a system containing more than one logical processor, software must account for the fact that information from
an EPT paging-structure entry may be cached on logical processors other than the one that modifies that entry. The
process of propagating the changes to a paging-structure entry is commonly referred to as “TLB shootdown.” A
discussion of TLB shootdown appears in Section 4.10.5, “Propagation of Paging-Structure Changes to Multiple
Processors,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
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28-22 Vol. 3C
CHAPTER 29
APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
The VMCS includes controls that enable the virtualization of interrupts and the Advanced Programmable Interrupt
Controller (APIC).
When these controls are used, the processor will emulate many accesses to the APIC, track the state of the virtual
APIC, and deliver virtual interrupts — all in VMX non-root operation with out a VM exit.1
The processor tracks the state of the virtual APIC using a virtual-APIC page identified by the virtual-machine
monitor (VMM). Section 29.1 discusses the virtual-APIC page and how the processor uses it to track the state of the
virtual APIC.
The following are the VM-execution controls relevant to APIC virtualization and virtual interrupts (see Section 24.6
for information about the locations of these controls):
•
Virtual-interrupt delivery. This controls enables the evaluation and delivery of pending virtual interrupts
(Section 29.2). It also enables the emulation of writes (memory-mapped or MSR-based, as enabled) to the
APIC registers that control interrupt prioritization.
•
Use TPR shadow. This control enables emulation of accesses to the APIC’s task-priority register (TPR) via CR8
(Section 29.3) and, if enabled, via the memory-mapped or MSR-based interfaces.
•
Virtualize APIC accesses. This control enables virtualization of memory-mapped accesses to the APIC
(Section 29.4) by causing VM exits on accesses to a VMM-specified APIC-access page. Some of the other
controls, if set, may cause some of these accesses to be emulated rather than causing VM exits.
•
Virtualize x2APIC mode. This control enables virtualization of MSR-based accesses to the APIC (Section
29.5).
•
APIC-register virtualization. This control allows memory-mapped and MSR-based reads of most APIC
registers (as enabled) by satisfying them from the virtual-APIC page. It directs memory-mapped writes to the
APIC-access page to the virtual-APIC page, following them by VM exits for VMM emulation.
•
Process posted interrupts. This control allows software to post virtual interrupts in a data structure and send
a notification to another logical processor; upon receipt of the notification, the target processor will process the
posted interrupts by copying them into the virtual-APIC page (Section 29.6).
“Virtualize APIC accesses”, “virtualize x2APIC mode”, “virtual-interrupt delivery”, and “APIC-register virtualization”
are all secondary processor-based VM-execution controls. If bit 31 of the primary processor-based VM-execution
controls is 0, the processor operates as if these controls were all 0. See Section 24.6.2.
29.1
VIRTUAL APIC STATE
The virtual-APIC page is a 4-KByte region of memory that the processor uses to virtualize certain accesses to
APIC registers and to manage virtual interrupts. The physical address of the virtual-APIC page is the virtual-APIC
address, a 64-bit VM-execution control field in the VMCS (see Section 24.6.8).
Depending on the settings of certain VM-execution controls, the processor may virtualize certain fields on the
virtual-APIC page with functionality analogous to that performed by the local APIC. Section 29.1.1 identifies and
defines these fields. Section 29.1.2, Section 29.1.3, Section 29.1.4, and Section 29.1.5 detail the actions taken to
virtualize updates to some of these fields.
29.1.1
Virtualized APIC Registers
Depending on the setting of certain VM-execution controls, a logical processor may virtualize certain accesses to
APIC registers using the following fields on the virtual-APIC page:
•
Virtual task-priority register (VTPR): the 32-bit field located at offset 080H on the virtual-APIC page.
1. In most cases, it is not necessary for a virtual-machine monitor (VMM) to inject virtual interrupts as part of VM entry.
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•
Virtual processor-priority register (VPPR): the 32-bit field located at offset 0A0H on the virtual-APIC
page.
•
•
Virtual end-of-interrupt register (VEOI): the 32-bit field located at offset 0B0H on the virtual-APIC page.
•
Virtual interrupt-request register (VIRR): the 256-bit value comprising eight non-contiguous 32-bit fields
at offsets 200H, 210H, 220H, 230H, 240H, 250H, 260H, and 270H on the virtual-APIC page. Bit x of the VIRR
is at bit position (x & 1FH) at offset (200H | ((x & E0H) » 1)). The processor uses only the low 4 bytes of each
of the 16-Byte fields at offsets 200H, 210H, 220H, 230H, 240H, 250H, 260H, and 270H.
•
Virtual interrupt-command register (VICR_LO): the 32-bit field located at offset 300H on the virtual-APIC
page
•
Virtual interrupt-command register (VICR_HI): the 32-bit field located at offset 310H on the virtual-APIC
page.
Virtual interrupt-service register (VISR): the 256-bit value comprising eight non-contiguous 32-bit fields
at offsets 100H, 110H, 120H, 130H, 140H, 150H, 160H, and 170H on the virtual-APIC page. Bit x of the VISR
is at bit position (x & 1FH) at offset (100H | ((x & E0H) » 1)). The processor uses only the low 4 bytes of each
of the 16-byte fields at offsets 100H, 110H, 120H, 130H, 140H, 150H, 160H, and 170H.
29.1.2
TPR Virtualization
The processor performs TPR virtualization in response to the following operations: (1) virtualization of the MOV
to CR8 instruction; (2) virtualization of a write to offset 080H on the APIC-access page; and (3) virtualization of the
WRMSR instruction with ECX = 808H. See Section 29.3, Section 29.4.3, and Section 29.5 for details of when TPR
virtualization is performed.
The following pseudocode details the behavior of TPR virtualization:
IF “virtual-interrupt delivery” is 0
THEN
IF VTPR[7:4] < TPR threshold (see Section 24.6.8)
THEN cause VM exit due to TPR below threshold;
FI;
ELSE
perform PPR virtualization (see Section 29.1.3);
evaluate pending virtual interrupts (see Section 29.2.1);
FI;
Any VM exit caused by TPR virtualization is trap-like: the instruction causing TPR virtualization completes before
the VM exit occurs (for example, the value of CS:RIP saved in the guest-state area of the VMCS references the next
instruction).
29.1.3
PPR Virtualization
The processor performs PPR virtualization in response to the following operations: (1) VM entry; (2) TPR virtualization; and (3) EOI virtualization. See Section 26.3.2.5, Section 29.1.2, and Section 29.1.4 for details of when
PPR virtualization is performed.
PPR virtualization uses the guest interrupt status (specifically, SVI; see Section 24.4.2) and VTPR. The following
pseudocode details the behavior of PPR virtualization:
IF VTPR[7:4] ≥ SVI[7:4]
THEN VPPR ← VTPR & FFH;
ELSE VPPR ← SVI & F0H;
FI;
PPR virtualization always clears bytes 3:1 of VPPR.
PPR virtualization is caused only by TPR virtualization, EOI virtualization, and VM entry. Delivery of a virtual interrupt also modifies VPPR, but in a different way (see Section 29.2.2). No other operations modify VPPR, even if they
modify SVI, VISR, or VTPR.
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
29.1.4
EOI Virtualization
The processor performs EOI virtualization in response to the following operations: (1) virtualization of a write to
offset 0B0H on the APIC-access page; and (2) virtualization of the WRMSR instruction with ECX = 80BH. See
Section 29.4.3 and Section 29.5 for details of when EOI virtualization is performed. EOI virtualization occurs only
if the “virtual-interrupt delivery” VM-execution control is 1.
EOI virtualization uses and updates the guest interrupt status (specifically, SVI; see Section 24.4.2). The following
pseudocode details the behavior of EOI virtualization:
Vector ← SVI;
VISR[Vector] ← 0; (see Section 29.1.1 for definition of VISR)
IF any bits set in VISR
THEN SVI ← highest index of bit set in VISR
ELSE SVI ← 0;
FI;
perform PPR virtualiation (see Section 29.1.3);
IF EOI_exit_bitmap[Vector] = 1 (see Section 24.6.8 for definition of EOI_exit_bitmap)
THEN cause EOI-induced VM exit with Vector as exit qualification;
ELSE evaluate pending virtual interrupts; (see Section 29.2.1)
FI;
Any VM exit caused by EOI virtualization is trap-like: the instruction causing EOI virtualization completes before
the VM exit occurs (for example, the value of CS:RIP saved in the guest-state area of the VMCS references the next
instruction).
29.1.5
Self-IPI Virtualization
The processor performs self-IPI virtualization in response to the following operations: (1) virtualization of a
write to offset 300H on the APIC-access page; and (2) virtualization of the WRMSR instruction with ECX = 83FH.
See Section 29.4.3 and Section 29.5 for details of when self-IPI virtualization is performed. Self-IPI virtualization
occurs only if the “virtual-interrupt delivery” VM-execution control is 1.
Each operation that leads to self-IPI virtualization provides an 8-bit vector (see Section 29.4.3 and Section 29.5).
Self-IPI virtualization updates the guest interrupt status (specifically, RVI; see Section 24.4.2). The following
pseudocode details the behavior of self-IPI virtualization:
VIRR[Vector] ← 1; (see Section 29.1.1 for definition of VIRR)
RVI ← max{RVI,Vector};
evaluate pending virtual interrupts; (see Section 29.2.1)
29.2
EVALUATION AND DELIVERY OF VIRTUAL INTERRUPTS
If the “virtual-interrupt delivery” VM-execution control is 1, certain actions in VMX non-root operation or during
VM entry cause the processor to evaluate and deliver virtual interrupts.
Evaluation of virtual interrupts is triggered by certain actions change the state of the virtual-APIC page and is
described in Section 29.2.1. This evaluation may result in recognition of a virtual interrupt. Once a virtual interrupt
is recognized, the processor may deliver it within VMX non-root operation without a VM exit. Virtual-interrupt
delivery is described in Section 29.2.2.
29.2.1
Evaluation of Pending Virtual Interrupts
If the “virtual-interrupt delivery” VM-execution control is 1, certain actions cause a logical processor to evaluate
pending virtual interrupts.
The following actions cause the evaluation of pending virtual interrupts: VM entry; TPR virtualization; EOI virtualization; self-IPI virtualization; and posted-interrupt processing. See Section 26.3.2.5, Section 29.1.2, Section
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
29.1.4, Section 29.1.5, and Section 29.6 for details of when evaluation of pending virtual interrupts is performed.
No other operations cause the evaluation of pending virtual interrupts, even if they modify RVI or VPPR.
Evaluation of pending virtual interrupts uses the guest interrupt status (specifically, RVI; see Section 24.4.2). The
following pseudocode details the evaluation of pending virtual interrupts:
IF “interrupt-window exiting” is 0 AND
RVI[7:4] > VPPR[7:4] (see Section 29.1.1 for definition of VPPR)
THEN recognize a pending virtual interrupt;
ELSE
do not recognize a pending virtual interrupt;
FI;
Once recognized, a virtual interrupt may be delivered in VMX non-root operation; see Section 29.2.2.
Evaluation of pending virtual interrupts is caused only by VM entry, TPR virtualization, EOI virtualization, self-IPI
virtualization, and posted-interrupt processing. No other operations do so, even if they modify RVI or VPPR. The
logical processor ceases recognition of a pending virtual interrupt following the delivery of a virtual interrupt.
29.2.2
Virtual-Interrupt Delivery
If a virtual interrupt has been recognized (see Section 29.2.1), it is delivered at an instruction boundary when the
following conditions all hold: (1) RFLAGS.IF = 1; (2) there is no blocking by STI; (3) there is no blocking by MOV
SS or by POP SS; and (4) the “interrupt-window exiting” VM-execution control is 0.
Virtual-interrupt delivery has the same priority as that of VM exits due to the 1-setting of the “interrupt-window
exiting” VM-execution control.1 Thus, non-maskable interrupts (NMIs) and higher priority events take priority over
delivery of a virtual interrupt; delivery of a virtual interrupt takes priority over external interrupts and lower priority
events.
Virtual-interrupt delivery wakes a logical processor from the same inactive activity states as would an external
interrupt. Specifically, it wakes a logical processor from the states entered using the HLT and MWAIT instructions.
It does not wake a logical processor in the shutdown state or in the wait-for-SIPI state.
Virtual-interrupt delivery updates the guest interrupt status (both RVI and SVI; see Section 24.4.2) and delivers an
event within VMX non-root operation without a VM exit. The following pseudocode details the behavior of virtualinterrupt delivery (see Section 29.1.1 for definition of VISR, VIRR, and VPPR):
Vector ← RVI;
VISR[Vector] ← 1;
SVI ← Vector;
VPPR ← Vector & F0H;
VIRR[Vector] ← 0;
IF any bits set in VIRR
THEN RVI ← highest index of bit set in VIRR
ELSE RVI ← 0;
FI;
deliver interrupt with Vector through IDT;
cease recognition of any pending virtual interrupt;
If a logical processor is in enclave mode, an Asynchronous Enclave Exit (AEX) occurs before delivery of a virtual
interrupt (see Chapter 40, “Enclave Exiting Events”).
1. A logical processor never recognizes or delivers a virtual interrupt if the “interrupt-window exiting” VM-execution control is 1.
Because of this, the relative priority of virtual-interrupt delivery and VM exits due to the 1-setting of that control is not defined.
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29.3
VIRTUALIZING CR8-BASED TPR ACCESSES
In 64-bit mode, software can access the local APIC’s task-priority register (TPR) through CR8. Specifically, software
uses the MOV from CR8 and MOV to CR8 instructions (see Section 10.8.6, “Task Priority in IA-32e Mode”). This
section describes how these accesses can be virtualized.
A virtual-machine monitor can virtualize these CR8-based APIC accesses by setting the “CR8-load exiting” and
“CR8-store exiting” VM-execution controls, ensuring that the accesses cause VM exits (see Section 25.1.3). Alternatively, there are methods for virtualizing some CR8-based APIC accesses without VM exits.
Normally, an execution of MOV from CR8 or MOV to CR8 that does not fault or cause a VM exit accesses the APIC’s
TPR. However, such an execution are treated specially if the “use TPR shadow” VM-execution control is 1. The
following items provide details:
•
MOV from CR8. The instruction loads bits 3:0 of its destination operand with bits 7:4 of VTPR (see Section
29.1.1). Bits 63:4 of the destination operand are cleared.
•
MOV to CR8. The instruction stores bits 3:0 of its source operand into bits 7:4 of VTPR; the remainder of VTPR
(bits 3:0 and bits 31:8) are cleared. Following this, the processor performs TPR virtualization (see Section
29.1.2).
29.4
VIRTUALIZING MEMORY-MAPPED APIC ACCESSES
When the local APIC is in xAPIC mode, software accesses the local APIC’s control registers using a memorymapped interface. Specifically, software uses linear addresses that translate to physical addresses on page frame
indicated by the base address in the IA32_APIC_BASE MSR (see Section 10.4.4, “Local APIC Status and Location”).
This section describes how these accesses can be virtualized.
A virtual-machine monitor (VMM) can virtualize these memory-mapped APIC accesses by ensuring that any access
to a linear address that would access the local APIC instead causes a VM exit. This could be done using paging or
the extended page-table mechanism (EPT). Another way is by using the 1-setting of the “virtualize APIC accesses”
VM-execution control.
If the “virtualize APIC accesses” VM-execution control is 1, the logical processor treats specially memory accesses
using linear addresses that translate to physical addresses in the 4-KByte APIC-access page.1 (The APIC-access
page is identified by the APIC-access address, a field in the VMCS; see Section 24.6.8.)
In general, an access to the APIC-access page causes an APIC-access VM exit. APIC-access VM exits provide a
VMM with information about the access causing the VM exit. Section 29.4.1 discusses the priority of APIC-access
VM exits.
Certain VM-execution controls enable the processor to virtualize certain accesses to the APIC-access page without
a VM exit. In general, this virtualization causes these accesses to be made to the virtual-APIC page instead of the
APIC-access page.
NOTES
Unless stated otherwise, this section characterizes only linear accesses to the APIC-access page;
an access to the APIC-access page is a linear access if (1) it results from a memory access using a
linear address; and (2) the access’s physical address is the translation of that linear address.
Section 29.4.6 discusses accesses to the APIC-access page that are not linear accesses.
The distinction between the APIC-access page and the virtual-APIC page allows a VMM to share
paging structures or EPT paging structures among the virtual processors of a virtual machine (the
shared paging structures referencing the same APIC-access address, which appears in the VMCS of
1. Even when addresses are translated using EPT (see Section 28.2), the determination of whether an APIC-access VM exit occurs
depends on an access’s physical address, not its guest-physical address. Even when CR0.PG = 0, ordinary memory accesses by software use linear addresses; the fact that CR0.PG = 0 means only that the identity translation is used to convert linear addresses to
physical (or guest-physical) addresses.
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
all the virtual processors) while giving each virtual processor its own virtual APIC (the VMCS of each
virtual processor will have a unique virtual-APIC address).
Section 29.4.2 discusses when and how the processor may virtualize read accesses from the APIC-access page.
Section 29.4.3 does the same for write accesses. When virtualizing a write to the APIC-access page, the processor
typically takes actions in addition to passing the write through to the virtual-APIC page.
The discussion in those sections uses the concept of an operation within which these memory accesses may occur.
For those discussions, an “operation” can be an iteration of a REP-prefixed string instruction, an execution of any
other instruction, or delivery of an event through the IDT.
The 1-setting of the “virtualize APIC accesses” VM-execution control may also affect accesses to the APIC-access
page that do not result directly from linear addresses. This is discussed in Section 29.4.6.
Special treatment may apply to Intel SGX instructions or if the logical processor is in enclave mode. See Section
42.5.3 for details.
29.4.1
Priority of APIC-Access VM Exits
The following items specify the priority of APIC-access VM exits relative to other events.
•
The priority of an APIC-access VM exit due to a memory access is below that of any page fault or EPT violation
that that access may incur. That is, an access does not cause an APIC-access VM exit if it would cause a page
fault or an EPT violation.
•
A memory access does not cause an APIC-access VM exit until after the accessed flags are set in the paging
structures (including EPT paging structures, if enabled).
•
A write access does not cause an APIC-access VM exit until after the dirty flags are set in the appropriate paging
structure and EPT paging structure (if enabled).
•
With respect to all other events, any APIC-access VM exit due to a memory access has the same priority as any
page fault or EPT violation that the access could cause. (This item applies to other events that the access may
generate as well as events that may be generated by other accesses by the same operation.)
These principles imply, among other things, that an APIC-access VM exit may occur during the execution of a
repeated string instruction (including INS and OUTS). Suppose, for example, that the first n iterations (n may be
0) of such an instruction do not access the APIC-access page and that the next iteration does access that page. As
a result, the first n iterations may complete and be followed by an APIC-access VM exit. The instruction pointer
saved in the VMCS references the repeated string instruction and the values of the general-purpose registers
reflect the completion of n iterations.
29.4.2
Virtualizing Reads from the APIC-Access Page
A read access from the APIC-access page causes an APIC-access VM exit if any of the following are true:
•
•
•
•
The “use TPR shadow” VM-execution control is 0.
•
The access is not entirely contained within the low 4 bytes of a naturally aligned 16-byte region. That is, bits
3:2 of the access’s address are 0, and the same is true of the address of the highest byte accessed.
The access is for an instruction fetch.
The access is more than 32 bits in size.
The access is part of an operation for which the processor has already virtualized a write to the APIC-access
page.
If none of the above are true, whether a read access is virtualized depends on the setting of the “APIC-register
virtualization” VM-execution control:
•
If “APIC-register virtualization” is 0, a read access is virtualized if its page offset is 080H (task priority);
otherwise, the access causes an APIC-access VM exit.
•
If “APIC-register virtualization is 1, a read access is virtualized if it is entirely within one the following ranges of
offsets:
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
— 020H–023H (local APIC ID);
— 030H–033H (local APIC version);
— 080H–083H (task priority);
— 0B0H–0B3H (end of interrupt);
— 0D0H–0D3H (logical destination);
— 0E0H–0E3H (destination format);
— 0F0H–0F3H (spurious-interrupt vector);
— 100H–103H, 110H–113H, 120H–123H, 130H–133H, 140H–143H, 150H–153H, 160H–163H, or 170H–
173H (in-service);
— 180H–183H, 190H–193H, 1A0H–1A3H, 1B0H–1B3H, 1C0H–1C3H, 1D0H–1D3H, 1E0H–1E3H, or 1F0H–
1F3H (trigger mode);
— 200H–203H, 210H–213H, 220H–223H, 230H–233H, 240H–243H, 250H–253H, 260H–263H, or 270H–
273H (interrupt request);
— 280H–283H (error status);
— 300H–303H or 310H–313H (interrupt command);
— 320H–323H, 330H–333H, 340H–343H, 350H–353H, 360H–363H, or 370H–373H (LVT entries);
— 380H–383H (initial count); or
— 3E0H–3E3H (divide configuration).
In all other cases, the access causes an APIC-access VM exit.
A read access from the APIC-access page that is virtualized returns data from the corresponding page offset on the
virtual-APIC page.1
29.4.3
Virtualizing Writes to the APIC-Access Page
Whether a write access to the APIC-access page is virtualized depends on the settings of the VM-execution controls
and the page offset of the access. Section 29.4.3.1 details when APIC-write virtualization occurs.
Unlike reads, writes to the local APIC have side effects; because of this, virtualization of writes to the APIC-access
page may require emulation specific to the access’s page offset (which identifies the APIC register being accessed).
Section 29.4.3.2 describes this APIC-write emulation.
For some page offsets, it is necessary for software to complete the virtualization after a write completes. In these
cases, the processor causes an APIC-write VM exit to invoke VMM software. Section 29.4.3.3 discusses APICwrite VM exits.
29.4.3.1
Determining Whether a Write Access is Virtualized
A write access to the APIC-access page causes an APIC-access VM exit if any of the following are true:
•
•
•
The “use TPR shadow” VM-execution control is 0.
•
The access is not entirely contained within the low 4 bytes of a naturally aligned 16-byte region. That is, bits
3:2 of the access’s address are 0, and the same is true of the address of the highest byte accessed.
The access is more than 32 bits in size.
The access is part of an operation for which the processor has already virtualized a write (with a different page
offset or a different size) to the APIC-access page.
If none of the above are true, whether a write access is virtualized depends on the settings of the “APIC-register
virtualization” and “virtual-interrupt delivery” VM-execution controls:
1. The memory type used for accesses that read from the virtual-APIC page is reported in bits 53:50 of the IA32_VMX_BASIC MSR
(see Appendix A.1).
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•
If the “APIC-register virtualization” and “virtual-interrupt delivery” VM-execution controls are both 0, a write
access is virtualized if its page offset is 080H; otherwise, the access causes an APIC-access VM exit.
•
If the “APIC-register virtualization” VM-execution control is 0 and the “virtual-interrupt delivery” VM-execution
control is 1, a write access is virtualized if its page offset is 080H (task priority), 0B0H (end of interrupt), and
300H (interrupt command — low); otherwise, the access causes an APIC-access VM exit.
•
If “APIC-register virtualization is 1, a write access is virtualized if it is entirely within one the following ranges of
offsets:
— 020H–023H (local APIC ID);
— 080H–083H (task priority);
— 0B0H–0B3H (end of interrupt);
— 0D0H–0D3H (logical destination);
— 0E0H–0E3H (destination format);
— 0F0H–0F3H (spurious-interrupt vector);
— 280H–283H (error status);
— 300H–303H or 310H–313H (interrupt command);
— 320H–323H, 330H–333H, 340H–343H, 350H–353H, 360H–363H, or 370H–373H (LVT entries);
— 380H–383H (initial count); or
— 3E0H–3E3H (divide configuration).
In all other cases, the access causes an APIC-access VM exit.
The processor virtualizes a write access to the APIC-access page by writing data to the corresponding page offset
on the virtual-APIC page.1 Following this, the processor performs certain actions after completion of the operation
of which the access was a part.2 APIC-write emulation is described in Section 29.4.3.2.
29.4.3.2
APIC-Write Emulation
If the processor virtualizes a write access to the APIC-access page, it performs additional actions after completion
of an operation of which the access was a part. These actions are called APIC-write emulation.
The details of APIC-write emulation depend upon the page offset of the virtualized write access:3
•
080H (task priority). The processor clears bytes 3:1 of VTPR and then causes TPR virtualization (Section
29.1.2).
•
0B0H (end of interrupt). If the “virtual-interrupt delivery” VM-execution control is 1, the processor clears VEOI
and then causes EOI virtualization (Section 29.1.4); otherwise, the processor causes an APIC-write VM exit
(Section 29.4.3.3).
•
300H (interrupt command — low). If the “virtual-interrupt delivery” VM-execution control is 1, the processor
checks the value of VICR_LO to determine whether the following are all true:
— Reserved bits (31:20, 17:16, 13) and bit 12 (delivery status) are all 0.
— Bits 19:18 (destination shorthand) are 01B (self).
— Bit 15 (trigger mode) is 0 (edge).
— Bits 10:8 (delivery mode) are 000B (fixed).
— Bits 7:4 (the upper half of the vector) are not 0000B.
1. The memory type used for accesses that write to the virtual-APIC page is reported in bits 53:50 of the IA32_VMX_BASIC MSR (see
Appendix A.1).
2. Recall that, for the purposes of this discussion, an operation is an iteration of a REP-prefixed string instruction, an execution of any
other instruction, or delivery of an event through the IDT.
3. For any operation, there can be only one page offset for which a write access was virtualized. This is because a write access is not
virtualized if the processor has already virtualized a write access for the same operation with a different page offset.
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If all of the items above are true, the processor performs self-IPI virtualization using the 8-bit vector in byte 0
of VICR_LO (Section 29.1.5).
If the “virtual-interrupt delivery” VM-execution control is 0, or if any of the items above are false, the
processor causes an APIC-write VM exit (Section 29.4.3.3).
•
310H–313H (interrupt command — high). The processor clears bytes 2:0 of VICR_HI. No other virtualization or
VM exit occurs.
•
Any other page offset. The processor causes an APIC-write VM exit (Section 29.4.3.3).
APIC-write emulation takes priority over system-management interrupts (SMIs), INIT signals, and lower priority
events. APIC-write emulation is not blocked if RFLAGS.IF = 0 or by the MOV SS, POP SS, or STI instructions.
If an operation causes a fault after a write access to the APIC-access page and before APIC-write emulation, and
that fault is delivered without a VM exit, APIC-write emulation occurs after the fault is delivered and before the fault
handler can execute. If an operation causes a VM exit (perhaps due to a fault) after a write access to the APICaccess page and before APIC-write emulation, the APIC-write emulation does not occur.
29.4.3.3
APIC-Write VM Exits
In certain cases, VMM software must be invoked to complete the virtualization of a write access to the APIC-access
page. In this case, APIC-write emulation causes an APIC-write VM exit. (Section 29.4.3.2 details the cases that
causes APIC-write VM exits.)
APIC-write VM exits are invoked by APIC-write emulation, and APIC-write emulation occurs after an operation that
performs a write access to the APIC-access page. Because of this, every APIC-write VM exit is trap-like: it occurs
after completion of the operation containing the write access that caused the VM exit (for example, the value of
CS:RIP saved in the guest-state area of the VMCS references the next instruction).
The basic exit reason for an APIC-write VM exit is “APIC write.” The exit qualification is the page offset of the write
access that led to the VM exit.
As noted in Section 29.5, execution of WRMSR with ECX = 83FH (self-IPI MSR) can lead to an APIC-write VM exit
if the “virtual-interrupt delivery” VM-execution control is 1. The exit qualification for such an APIC-write VM exit is
3F0H.
29.4.4
Instruction-Specific Considerations
Certain instructions that use linear address may cause page faults even though they do not use those addresses to
access memory. The APIC-virtualization features may affect these instructions as well:
•
CLFLUSH, CLFLUSHOPT. With regard to faulting, the processor operates as if each of these instructions reads
from the linear address in its source operand. If that address translates to one on the APIC-access page, the
instruction may cause an APIC-access VM exit. If it does not, it will flush the corresponding cache line on the
virtual-APIC page instead of the APIC-access page.
•
ENTER. With regard to faulting, the processor operates if ENTER writes to the byte referenced by the final
value of the stack pointer (even though it does not if its size operand is non-zero). If that value translates to an
address on the APIC-access page, the instruction may cause an APIC-access VM exit. If it does not, it will cause
the APIC-write emulation appropriate to the address’s page offset.
•
MASKMOVQ and MAKSMOVDQU. Even if the instruction’s mask is zero, the processor may operate with
regard to faulting as if MASKMOVQ or MASKMOVDQU writes to memory (the behavior is implementationspecific). In such a situation, an APIC-access VM exit may occur.
•
MONITOR. With regard to faulting, the processor operates as if MONITOR reads from the effective address in
RAX. If the resulting linear address translates to one on the APIC-access page, the instruction may cause an
APIC-access VM exit.1 If it does not, it will monitor the corresponding address on the virtual-APIC page instead
of the APIC-access page.
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX operation also support Intel 64 architecture. For IA-32 processors, this notation refers to the 32-bit forms of those registers (EAX, EIP,
ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to lower 32 bits of the indicated register.
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•
PREFETCH. An execution of the PREFETCH instruction that would result in an access to the APIC-access page
does not cause an APIC-access VM exit. Such an access may prefetch data; if so, it is from the corresponding
address on the virtual-APIC page.
Virtualization of accesses to the APIC-access page is principally intended for basic instructions such as AND, MOV,
OR, TEST, XCHG, and XOR. Use of an instruction that normally operates on floating-point, SSE, AVX, or AVX-512
registers may cause an APIC-access VM exit unconditionally regardless of the page offset it accesses on the APICaccess page.
29.4.5
Issues Pertaining to Page Size and TLB Management
The 1-setting of the “virtualize APIC accesses” VM-execution is guaranteed to apply only if translations to the APICaccess address use a 4-KByte page. The following items provide details:
•
If EPT is not in use, any linear address that translates to an address on the APIC-access page should use a 4KByte page. Any access to a linear address that translates to the APIC-access page using a larger page may
operate as if the “virtualize APIC accesses” VM-execution control were 0.
•
If EPT is in use, any guest-physical address that translates to an address on the APIC-access page should use a
4-KByte page. Any access to a linear address that translates to a guest-physical address that in turn translates
to the APIC-access page using a larger page may operate as if the “virtualize APIC accesses” VM-execution
control were 0. (This is true also for guest-physical accesses to the APIC-access page; see Section 29.4.6.1.)
In addition, software should perform appropriate TLB invalidation when making changes that may affect APICvirtualization. The specifics depend on whether VPIDs or EPT is being used:
•
VPIDs being used but EPT not being used. Suppose that there is a VPID that has been used before and that
software has since made either of the following changes: (1) set the “virtualize APIC accesses” VM-execution
control when it had previously been 0; or (2) changed the paging structures so that some linear address
translates to the APIC-access address when it previously did not. In that case, software should execute
INVVPID (see “INVVPID— Invalidate Translations Based on VPID” in Section 30.3) before performing on the
same logical processor and with the same VPID.1
•
EPT being used. Suppose that there is an EPTP value that has been used before and that software has since
made either of the following changes: (1) set the “virtualize APIC accesses” VM-execution control when it had
previously been 0; or (2) changed the EPT paging structures so that some guest-physical address translates to
the APIC-access address when it previously did not. In that case, software should execute INVEPT (see
“INVEPT— Invalidate Translations Derived from EPT” in Section 30.3) before performing on the same logical
processor and with the same EPTP value.2
•
Neither VPIDs nor EPT being used. No invalidation is required.
Failure to perform the appropriate TLB invalidation may result in the logical processor operating as if the “virtualize
APIC accesses” VM-execution control were 0 in responses to accesses to the affected address. (No invalidation is
necessary if neither VPIDs nor EPT is being used.)
29.4.6
APIC Accesses Not Directly Resulting From Linear Addresses
Section 29.4 has described the treatment of accesses that use linear addresses that translate to addresses on the
APIC-access page. This section considers memory accesses that do not result directly from linear addresses.
•
An access is called a guest-physical access if (1) CR0.PG = 1;3 (2) the “enable EPT” VM-execution control is
1;4 (3) the access’s physical address is the result of an EPT translation; and (4) either (a) the access was not
generated by a linear address; or (b) the access’s guest-physical address is not the translation of the access’s
linear address. Section 29.4.6.1 discusses the treatment of guest-physical accesses to the APIC-access page.
1. INVVPID should use either (1) the all-contexts INVVPID type; (2) the single-context INVVPID type with the VPID in the INVVPID
descriptor; or (3) the individual-address INVVPID type with the linear address and the VPID in the INVVPID descriptor.
2. INVEPT should use either (1) the global INVEPT type; or (2) the single-context INVEPT type with the EPTP value in the INVEPT
descriptor.
3. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG must be 1 unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•
An access is called a physical access if (1) either (a) the “enable EPT” VM-execution control is 0; or (b) the
access’s physical address is not the result of a translation through the EPT paging structures; and (2) either
(a) the access is not generated by a linear address; or (b) the access’s physical address is not the translation
of its linear address. Section 29.4.6.2 discusses the treatment of physical accesses to the APIC-access page.
29.4.6.1
Guest-Physical Accesses to the APIC-Access Page
Guest-physical accesses include the following when guest-physical addresses are being translated using EPT:
•
Reads from the guest paging structures when translating a linear address (such an access uses a guestphysical address that is not the translation of that linear address).
•
Loads of the page-directory-pointer-table entries by MOV to CR when the logical processor is using (or that
causes the logical processor to use) PAE paging (see Section 4.4).
•
Updates to the accessed and dirty flags in the guest paging structures when using a linear address (such an
access uses a guest-physical address that is not the translation of that linear address).
Every guest-physical access to an address on the APIC-access page causes an APIC-access VM exit. Such accesses
are never virtualized regardless of the page offset.
The following items specify the priority relative to other events of APIC-access VM exits caused by guest-physical
accesses to the APIC-access page.
•
The priority of an APIC-access VM exit caused by a guest-physical access to memory is below that of any EPT
violation that that access may incur. That is, a guest-physical access does not cause an APIC-access VM exit if
it would cause an EPT violation.
•
With respect to all other events, any APIC-access VM exit caused by a guest-physical access has the same
priority as any EPT violation that the guest-physical access could cause.
29.4.6.2
Physical Accesses to the APIC-Access Page
Physical accesses include the following:
•
If the “enable EPT” VM-execution control is 0:
— Reads from the paging structures when translating a linear address.
— Loads of the page-directory-pointer-table entries by MOV to CR when the logical processor is using (or that
causes the logical processor to use) PAE paging (see Section 4.4).
— Updates to the accessed and dirty flags in the paging structures.
•
If the “enable EPT” VM-execution control is 1, accesses to the EPT paging structures (including updates to the
accessed and dirty flags for EPT).
•
Any of the following accesses made by the processor to support VMX non-root operation:
— Accesses to the VMCS region.
— Accesses to data structures referenced (directly or indirectly) by physical addresses in VM-execution
control fields in the VMCS. These include the I/O bitmaps, the MSR bitmaps, and the virtual-APIC page.
•
Accesses that effect transitions into and out of SMM.1 These include the following:
— Accesses to SMRAM during SMI delivery and during execution of RSM.
— Accesses during SMM VM exits (including accesses to MSEG) and during VM entries that return from SMM.
A physical access to the APIC-access page may or may not cause an APIC-access VM exit. If it does not cause an
APIC-access VM exit, it may access the APIC-access page or the virtual-APIC page. Physical write accesses to the
APIC-access page may or may not cause APIC-write emulation or APIC-write VM exits.
4. “Enable EPT” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls
is 0, VMX non-root operation functions as if the “enable EPT” VM-execution control were 0. See Section 24.6.2.
1. Technically, these accesses do not occur in VMX non-root operation. They are included here for clarity.
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APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
The priority of an APIC-access VM exit caused by physical access is not defined relative to other events that the
access may cause.
It is recommended that software not set the APIC-access address to any of the addresses used by physical memory
accesses (identified above). For example, it should not set the APIC-access address to the physical address of any
of the active paging structures if the “enable EPT” VM-execution control is 0.
29.5
VIRTUALIZING MSR-BASED APIC ACCESSES
When the local APIC is in x2APIC mode, software accesses the local APIC’s control registers using the MSR interface. Specifically, software uses the RDMSR and WRMSR instructions, setting ECX (identifying the MSR being
accessed) to values in the range 800H–8FFH (see Section 10.12, “Extended XAPIC (x2APIC)”). This section
describes how these accesses can be virtualized.
A virtual-machine monitor can virtualize these MSR-based APIC accesses by configuring the MSR bitmaps (see
Section 24.6.9) to ensure that the accesses cause VM exits (see Section 25.1.3). Alternatively, there are methods
for virtualizing some MSR-based APIC accesses without VM exits.
Normally, an execution of RDMSR or WRMSR that does not fault or cause a VM exit accesses the MSR indicated in
ECX. However, such an execution treats some values of ECX in the range 800H–8FFH specially if the “virtualize
x2APIC mode” VM-execution control is 1. The following items provide details:
•
RDMSR. The instruction’s behavior depends on the setting of the “APIC-register virtualization” VM-execution
control.
— If the “APIC-register virtualization” VM-execution control is 0, behavior depends upon the value of ECX.
•
If ECX contains 808H (indicating the TPR MSR), the instruction reads the 8 bytes from offset 080H on
the virtual-APIC page (VTPR and the 4 bytes above it) into EDX:EAX. This occurs even if the local APIC
is not in x2APIC mode (no general-protection fault occurs because the local APIC is not x2APIC mode).
•
If ECX contains any other value in the range 800H–8FFH, the instruction operates normally. If the local
APIC is in x2APIC mode and ECX indicates a readable APIC register, EDX and EAX are loaded with the
value of that register. If the local APIC is not in x2APIC mode or ECX does not indicate a readable APIC
register, a general-protection fault occurs.
— If “APIC-register virtualization” is 1 and ECX contains a value in the range 800H–8FFH, the instruction reads
the 8 bytes from offset X on the virtual-APIC page into EDX:EAX, where X = (ECX & FFH) « 4. This occurs
even if the local APIC is not in x2APIC mode (no general-protection fault occurs because the local APIC is
not in x2APIC mode).
•
WRMSR. The instruction’s behavior depends on the value of ECX and the setting of the “virtual-interrupt
delivery” VM-execution control.
Special processing applies in the following cases: (1) ECX contains 808H (indicating the TPR MSR); (2) ECX
contains 80BH (indicating the EOI MSR) and the “virtual-interrupt delivery” VM-execution control is 1; and
(3) ECX contains 83FH (indicating the self-IPI MSR) and the “virtual-interrupt delivery” VM-execution control
is 1.
If special processing applies, no general-protection exception is produced due to the fact that the local APIC is
in xAPIC mode. However, WRMSR does perform the normal reserved-bit checking:
— If ECX contains 808H or 83FH, a general-protection fault occurs if either EDX or EAX[31:8] is non-zero.
— If ECX contains 80BH, a general-protection fault occurs if either EDX or EAX is non-zero.
If there is no fault, WRMSR stores EDX:EAX at offset X on the virtual-APIC page, where X = (ECX & FFH) « 4.
Following this, the processor performs an operation depending on the value of ECX:
— If ECX contains 808H, the processor performs TPR virtualization (see Section 29.1.2).
— If ECX contains 80BH, the processor performs EOI virtualization (see Section 29.1.4).
— If ECX contains 83FH, the processor then checks the value of EAX[7:4] and proceeds as follows:
•
29-12 Vol. 3C
If the value is non-zero, the logical processor performs self-IPI virtualization with the 8-bit vector in
EAX[7:0] (see Section 29.1.5).
APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•
If the value is zero, the logical processor causes an APIC-write VM exit as if there had been a write
access to page offset 3F0H on the APIC-access page (see Section 29.4.3.3).
If special processing does not apply, the instruction operates normally. If the local APIC is in x2APIC mode
and ECX indicates a writable APIC register, the value in EDX:EAX is written to that register. If the local APIC is
not in x2APIC mode or ECX does not indicate a writable APIC register, a general-protection fault occurs.
29.6
POSTED-INTERRUPT PROCESSING
Posted-interrupt processing is a feature by which a processor processes the virtual interrupts by recording them as
pending on the virtual-APIC page.
Posted-interrupt processing is enabled by setting the “process posted interrupts” VM-execution control. The
processing is performed in response to the arrival of an interrupt with the posted-interrupt notification vector.
In response to such an interrupt, the processor processes virtual interrupts recorded in a data structure called a
posted-interrupt descriptor. The posted-interrupt notification vector and the address of the posted-interrupt
descriptor are fields in the VMCS; see Section 24.6.8.
If the “process posted interrupts” VM-execution control is 1, a logical processor uses a 64-byte posted-interrupt
descriptor located at the posted-interrupt descriptor address. The posted-interrupt descriptor has the following
format:
Table 29-1. Format of Posted-Interrupt Descriptor
Bit
Position(s)
Name
Description
255:0
Posted-interrupt requests
One bit for each interrupt vector. There is a posted-interrupt request for a vector if
the corresponding bit is 1
256
Outstanding notification
If this bit is set, there is a notification outstanding for one or more posted interrupts
in bits 255:0
511:257
Reserved for software and
other agents
These bits may be used by software and by other agents in the system (e.g.,
chipset). The processor does not modify these bits.
The notation PIR (posted-interrupt requests) refers to the 256 posted-interrupt bits in the posted-interrupt
descriptor.
Use of the posted-interrupt descriptor differs from that of other data structures that are referenced by pointers in
a VMCS. There is a general requirement that software ensure that each such data structure is modified only when
no logical processor with a current VMCS that references it is in VMX non-root operation. That requirement does
not apply to the posted-interrupt descriptor. There is a requirement, however, that such modifications be done
using locked read-modify-write instructions.
If the “external-interrupt exiting” VM-execution control is 1, any unmasked external interrupt causes a VM exit
(see Section 25.2). If the “process posted interrupts” VM-execution control is also 1, this behavior is changed and
the processor handles an external interrupt as follows:1
1. The local APIC is acknowledged; this provides the processor core with an interrupt vector, called here the
physical vector.
2. If the physical vector equals the posted-interrupt notification vector, the logical processor continues to the next
step. Otherwise, a VM exit occurs as it would normally due to an external interrupt; the vector is saved in the
VM-exit interruption-information field.
3. The processor clears the outstanding-notification bit in the posted-interrupt descriptor. This is done atomically
so as to leave the remainder of the descriptor unmodified (e.g., with a locked AND operation).
4. The processor writes zero to the EOI register in the local APIC; this dismisses the interrupt with the postedinterrupt notification vector from the local APIC.
1. VM entry ensures that the “process posted interrupts” VM-execution control is 1 only if the “external-interrupt exiting” VM-execution control is also 1. SeeSection 26.2.1.1.
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5. The logical processor performs a logical-OR of PIR into VIRR and clears PIR. No other agent can read or write a
PIR bit (or group of bits) between the time it is read (to determine what to OR into VIRR) and when it is cleared.
6. The logical processor sets RVI to be the maximum of the old value of RVI and the highest index of all bits that
were set in PIR; if no bit was set in PIR, RVI is left unmodified.
7. The logical processor evaluates pending virtual interrupts as described in Section 29.2.1.
The logical processor performs the steps above in an uninterruptible manner. If step #7 leads to recognition of a
virtual interrupt, the processor may deliver that interrupt immediately.
Steps #1 to #7 above occur when the interrupt controller delivers an unmasked external interrupt to the CPU core.
The following items consider certain cases of interrupt delivery:
•
Interrupt delivery can occur between iterations of a REP-prefixed instruction (after at least one iteration has
completed but before all iterations have completed). If this occurs, the following items characterize processor
state after posted-interrupt processing completes and before guest execution resumes:
— RIP references the REP-prefixed instruction;
— RCX, RSI, and RDI are updated to reflect the iterations completed; and
— RFLAGS.RF = 1.
•
Interrupt delivery can occur when the logical processor is in the active, HLT, or MWAIT states. If the logical
processor had been in the active or MWAIT state before the arrival of the interrupt, it is in the active state
following completion of step #7; if it had been in the HLT state, it returns to the HLT state after step #7 (if a
pending virtual interrupt was recognized, the logical processor may immediately wake from the HLT state).
•
Interrupt delivery can occur while the logical processor is in enclave mode. If the logical processor had been in
enclave mode before the arrival of the interrupt, an Asynchronous Enclave Exit (AEX) may occur before the
steps #1 to #7 (see Chapter 40, “Enclave Exiting Events”). If no AEX occurs before step #1 and a VM exit
occurs at step #2, an AEX occurs before the VM exit is delivered.
29-14 Vol. 3C
CHAPTER 30
VMX INSTRUCTION REFERENCE
NOTE
This chapter was previously located in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2B as chapter 5.
30.1
OVERVIEW
This chapter describes the virtual-machine extensions (VMX) for the Intel 64 and IA-32 architectures. VMX is
intended to support virtualization of processor hardware and a system software layer acting as a host to multiple
guest software environments. The virtual-machine extensions (VMX) includes five instructions that manage the
virtual-machine control structure (VMCS), four instructions that manage VMX operation, two TLB-management
instructions, and two instructions for use by guest software. Additional details of VMX are described in Chapter 23
through Chapter 29.
The behavior of the VMCS-maintenance instructions is summarized below:
•
VMPTRLD — This instruction takes a single 64-bit source operand that is in memory. It makes the referenced
VMCS active and current, loading the current-VMCS pointer with this operand and establishes the current VMCS
based on the contents of VMCS-data area in the referenced VMCS region. Because this makes the referenced
VMCS active, a logical processor may start maintaining on the processor some of the VMCS data for the VMCS.
•
VMPTRST — This instruction takes a single 64-bit destination operand that is in memory. The current-VMCS
pointer is stored into the destination operand.
•
VMCLEAR — This instruction takes a single 64-bit operand that is in memory. The instruction sets the launch
state of the VMCS referenced by the operand to “clear”, renders that VMCS inactive, and ensures that data for
the VMCS have been written to the VMCS-data area in the referenced VMCS region. If the operand is the same
as the current-VMCS pointer, that pointer is made invalid.
•
VMREAD — This instruction reads a component from a VMCS (the encoding of that field is given in a register
operand) and stores it into a destination operand that may be a register or in memory.
•
VMWRITE — This instruction writes a component to a VMCS (the encoding of that field is given in a register
operand) from a source operand that may be a register or in memory.
The behavior of the VMX management instructions is summarized below:
•
VMLAUNCH — This instruction launches a virtual machine managed by the VMCS. A VM entry occurs, transferring control to the VM.
•
VMRESUME — This instruction resumes a virtual machine managed by the VMCS. A VM entry occurs, transferring control to the VM.
•
•
VMXOFF — This instruction causes the processor to leave VMX operation.
VMXON — This instruction takes a single 64-bit source operand that is in memory. It causes a logical processor
to enter VMX root operation and to use the memory referenced by the operand to support VMX operation.
The behavior of the VMX-specific TLB-management instructions is summarized below:
•
INVEPT — This instruction invalidates entries in the TLBs and paging-structure caches that were derived from
extended page tables (EPT).
•
INVVPID — This instruction invalidates entries in the TLBs and paging-structure caches based on a VirtualProcessor Identifier (VPID).
None of the instructions above can be executed in compatibility mode; they generate invalid-opcode exceptions if
executed in compatibility mode.
The behavior of the guest-available instructions is summarized below:
•
VMCALL — This instruction allows software in VMX non-root operation to call the VMM for service. A VM exit
occurs, transferring control to the VMM.
Vol. 3C 30-1
VMX INSTRUCTION REFERENCE
•
VMFUNC — This instruction allows software in VMX non-root operation to invoke a VM function (processor
functionality enabled and configured by software in VMX root operation) without a VM exit.
30.2
CONVENTIONS
The operation sections for the VMX instructions in Section 30.3 use the pseudo-function VMexit, which indicates
that the logical processor performs a VM exit.
The operation sections also use the pseudo-functions VMsucceed, VMfail, VMfailInvalid, and VMfailValid. These
pseudo-functions signal instruction success or failure by setting or clearing bits in RFLAGS and, in some cases, by
writing the VM-instruction error field. The following pseudocode fragments detail these functions:
VMsucceed:
CF ← 0;
PF ← 0;
AF ← 0;
ZF ← 0;
SF ← 0;
OF ← 0;
VMfail(ErrorNumber):
IF VMCS pointer is valid
THEN VMfailValid(ErrorNumber);
ELSE VMfailInvalid;
FI;
VMfailInvalid:
CF ← 1;
PF ← 0;
AF ← 0;
ZF ← 0;
SF ← 0;
OF ← 0;
VMfailValid(ErrorNumber):// executed only if there is a current VMCS
CF ← 0;
PF ← 0;
AF ← 0;
ZF ← 1;
SF ← 0;
OF ← 0;
Set the VM-instruction error field to ErrorNumber;
The different VM-instruction error numbers are enumerated in Section 30.4, “VM Instruction Error Numbers”.
30.3
VMX INSTRUCTIONS
This section provides detailed descriptions of the VMX instructions.
30-2 Vol. 3C
VMX INSTRUCTION REFERENCE
INVEPT— Invalidate Translations Derived from EPT
Opcode
Instruction
Description
66 0F 38 80
INVEPT r64, m128
Invalidates EPT-derived entries in the TLBs and paging-structure caches (in 64bit mode)
66 0F 38 80
INVEPT r32, m128
Invalidates EPT-derived entries in the TLBs and paging-structure caches (outside
64-bit mode)
Description
Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches that were derived
from extended page tables (EPT). (See Chapter 28, “VMX Support for Address Translation”.) Invalidation is based
on the INVEPT type specified in the register operand and the INVEPT descriptor specified in the memory
operand.
Outside IA-32e mode, the register operand is always 32 bits, regardless of the value of CS.D; in 64-bit mode, the
register operand has 64 bits (the instruction cannot be executed in compatibility mode).
The INVEPT types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see
Appendix A, “VMX Capability Reporting Facility”). There are two INVEPT types currently defined:
•
Single-context invalidation. If the INVEPT type is 1, the logical processor invalidates all mappings associated
with bits 51:12 of the EPT pointer (EPTP) specified in the INVEPT descriptor. It may invalidate other mappings
as well.
•
Global invalidation: If the INVEPT type is 2, the logical processor invalidates mappings associated with all
EPTPs.
If an unsupported INVEPT type is specified, the instruction fails.
INVEPT invalidates all the specified mappings for the indicated EPTP(s) regardless of the VPID and PCID values with
which those mappings may be associated.
The INVEPT descriptor comprises 128 bits and contains a 64-bit EPTP value in bits 63:0 (see Figure 30-1).
127
64 63
Reserved (must be zero)
0
EPT pointer (EPTP)
Figure 30-1. INVEPT Descriptor
Operation
IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VM exit;
ELSIF CPL > 0
THEN #GP(0);
ELSE
INVEPT_TYPE ← value of register operand;
IF IA32_VMX_EPT_VPID_CAP MSR indicates that processor does not support INVEPT_TYPE
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
// INVEPT_TYPE must be 1 or 2
INVEPT_DESC ← value of memory operand;
EPTP ← INVEPT_DESC[63:0];
Vol. 3C 30-3
VMX INSTRUCTION REFERENCE
CASE INVEPT_TYPE OF
1:
// single-context invalidation
IF VM entry with the “enable EPT“ VM execution control set to 1
would fail due to the EPTP value
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate mappings associated with EPTP[51:12];
VMsucceed;
FI;
BREAK;
2:
// global invalidation
Invalidate mappings associated with all EPTPs;
VMsucceed;
BREAK;
ESAC;
FI;
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the source operand is located in an execute-only code segment.
#PF(fault-code)
If a page fault occurs in accessing the memory operand.
#SS(0)
If the memory operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If not in VMX operation.
If the logical processor does not support EPT (IA32_VMX_PROCBASED_CTLS2[33]=0).
If the logical processor supports EPT (IA32_VMX_PROCBASED_CTLS2[33]=1) but does not
support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0).
Real-Address Mode Exceptions
#UD
The INVEPT instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The INVEPT instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The INVEPT instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is
in a non-canonical form.
#PF(fault-code)
If a page fault occurs in accessing the memory operand.
#SS(0)
If the memory operand is in the SS segment and the memory address is in a non-canonical
form.
30-4 Vol. 3C
VMX INSTRUCTION REFERENCE
#UD
If not in VMX operation.
If the logical processor does not support EPT (IA32_VMX_PROCBASED_CTLS2[33]=0).
If the logical processor supports EPT (IA32_VMX_PROCBASED_CTLS2[33]=1) but does not
support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0).
Vol. 3C 30-5
VMX INSTRUCTION REFERENCE
INVVPID— Invalidate Translations Based on VPID
Opcode
Instruction
Description
66 0F 38 81
INVVPID r64, m128
Invalidates entries in the TLBs and paging-structure caches based on VPID (in
64-bit mode)
66 0F 38 81
INVVPID r32, m128
Invalidates entries in the TLBs and paging-structure caches based on VPID
(outside 64-bit mode)
Description
Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on virtualprocessor identifier (VPID). (See Chapter 28, “VMX Support for Address Translation”.) Invalidation is based on
the INVVPID type specified in the register operand and the INVVPID descriptor specified in the memory
operand.
Outside IA-32e mode, the register operand is always 32 bits, regardless of the value of CS.D; in 64-bit mode, the
register operand has 64 bits (the instruction cannot be executed in compatibility mode).
The INVVPID types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see
Appendix A, “VMX Capability Reporting Facility”). There are four INVVPID types currently defined:
•
Individual-address invalidation: If the INVVPID type is 0, the logical processor invalidates mappings for the
linear address and VPID specified in the INVVPID descriptor. In some cases, it may invalidate mappings for
other linear addresses (or other VPIDs) as well.
•
Single-context invalidation: If the INVVPID type is 1, the logical processor invalidates all mappings tagged with
the VPID specified in the INVVPID descriptor. In some cases, it may invalidate mappings for other VPIDs as
well.
•
All-contexts invalidation: If the INVVPID type is 2, the logical processor invalidates all mappings tagged with all
VPIDs except VPID 0000H. In some cases, it may invalidate translations with VPID 0000H as well.
•
Single-context invalidation, retaining global translations: If the INVVPID type is 3, the logical processor
invalidates all mappings tagged with the VPID specified in the INVVPID descriptor except global translations. In
some cases, it may invalidate global translations (and mappings with other VPIDs) as well. See the “Caching
Translation Information” section in Chapter 4 of the IA-32 Intel Architecture Software Developer’s Manual,
Volumes 3A for information about global translations.
If an unsupported INVVPID type is specified, the instruction fails.
INVVPID invalidates all the specified mappings for the indicated VPID(s) regardless of the EPTP and PCID values
with which those mappings may be associated.
The INVVPID descriptor comprises 128 bits and consists of a VPID and a linear address as shown in Figure 30-2.
127
64 63
Linear Address
Reserved (must be zero)
Figure 30-2. INVVPID Descriptor
30-6 Vol. 3C
16 15
VPID
0
VMX INSTRUCTION REFERENCE
Operation
IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VM exit;
ELSIF CPL > 0
THEN #GP(0);
ELSE
INVVPID_TYPE ← value of register operand;
IF IA32_VMX_EPT_VPID_CAP MSR indicates that processor does not support
INVVPID_TYPE
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
// INVVPID_TYPE must be in the range 0–3
INVVPID_DESC ← value of memory operand;
IF INVVPID_DESC[63:16] ≠ 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
CASE INVVPID_TYPE OF
0:
// individual-address invalidation
VPID ← INVVPID_DESC[15:0];
IF VPID = 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
GL_ADDR ← INVVPID_DESC[127:64];
IF (GL_ADDR is not in a canonical form)
THEN
VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate mappings for GL_ADDR tagged with VPID;
VMsucceed;
FI;
FI;
BREAK;
1:
// single-context invalidation
VPID ← INVVPID_DESC[15:0];
IF VPID = 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate all mappings tagged with VPID;
VMsucceed;
FI;
BREAK;
2:
// all-context invalidation
Invalidate all mappings tagged with all non-zero VPIDs;
VMsucceed;
BREAK;
3:
// single-context invalidation retaining globals
VPID ← INVVPID_DESC[15:0];
IF VPID = 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate all mappings tagged with VPID except global translations;
VMsucceed;
Vol. 3C 30-7
VMX INSTRUCTION REFERENCE
FI;
BREAK;
ESAC;
FI;
FI;
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the source operand is located in an execute-only code segment.
#PF(fault-code)
If a page fault occurs in accessing the memory operand.
#SS(0)
If the memory operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If not in VMX operation.
If the logical processor does not support VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0).
If the logical processor supports VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=1) but does not
support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).
Real-Address Mode Exceptions
#UD
The INVVPID instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The INVVPID instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The INVVPID instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is
in a non-canonical form.
#PF(fault-code)
If a page fault occurs in accessing the memory operand.
#SS(0)
If the memory destination operand is in the SS segment and the memory address is in a noncanonical form.
#UD
If not in VMX operation.
If the logical processor does not support VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0).
If the logical processor supports VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=1) but does not
support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).
30-8 Vol. 3C
VMX INSTRUCTION REFERENCE
VMCALL—Call to VM Monitor
Opcode
Instruction
Description
0F 01 C1
VMCALL
Call to VM monitor by causing VM exit.
Description
This instruction allows guest software can make a call for service into an underlying VM monitor. The details of the
programming interface for such calls are VMM-specific; this instruction does nothing more than cause a VM exit,
registering the appropriate exit reason.
Use of this instruction in VMX root operation invokes an SMM monitor (see Section 34.15.2). This invocation will
activate the dual-monitor treatment of system-management interrupts (SMIs) and system-management mode
(SMM) if it is not already active (see Section 34.15.6).
Operation
IF not in VMX operation
THEN #UD;
ELSIF in VMX non-root operation
THEN VM exit;
ELSIF (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF CPL > 0
THEN #GP(0);
ELSIF in SMM or the logical processor does not support the dual-monitor treatment of SMIs and SMM or the valid bit in the
IA32_SMM_MONITOR_CTL MSR is clear
THEN VMfail (VMCALL executed in VMX root operation);
ELSIF dual-monitor treatment of SMIs and SMM is active
THEN perform an SMM VM exit (see Section 34.15.2);
ELSIF current-VMCS pointer is not valid
THEN VMfailInvalid;
ELSIF launch state of current VMCS is not clear
THEN VMfailValid(VMCALL with non-clear VMCS);
ELSIF VM-exit control fields are not valid (see Section 34.15.6.1)
THEN VMfailValid (VMCALL with invalid VM-exit control fields);
ELSE
enter SMM;
read revision identifier in MSEG;
IF revision identifier does not match that supported by processor
THEN
leave SMM;
VMfailValid(VMCALL with incorrect MSEG revision identifier);
ELSE
read SMM-monitor features field in MSEG (see Section 34.15.6.1);
IF features field is invalid
THEN
leave SMM;
VMfailValid(VMCALL with invalid SMM-monitor features);
ELSE activate dual-monitor treatment of SMIs and SMM (see Section 34.15.6);
FI;
FI;
FI;
Vol. 3C 30-9
VMX INSTRUCTION REFERENCE
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0 and the logical processor is in VMX root operation.
#UD
If executed outside VMX operation.
Real-Address Mode Exceptions
#UD
If executed outside VMX operation.
Virtual-8086 Mode Exceptions
#UD
If executed outside VMX non-root operation.
Compatibility Mode Exceptions
#UD
If executed outside VMX non-root operation.
64-Bit Mode Exceptions
#UD
30-10 Vol. 3C
If executed outside VMX operation.
VMX INSTRUCTION REFERENCE
VMCLEAR—Clear Virtual-Machine Control Structure
Opcode
Instruction
Description
66 0F C7 /6
VMCLEAR m64
Copy VMCS data to VMCS region in memory.
Description
This instruction applies to the VMCS whose VMCS region resides at the physical address contained in the instruction operand. The instruction ensures that VMCS data for that VMCS (some of these data may be currently maintained on the processor) are copied to the VMCS region in memory. It also initializes parts of the VMCS region (for
example, it sets the launch state of that VMCS to clear). See Chapter 24, “Virtual-Machine Control Structures”.
The operand of this instruction is always 64 bits and is always in memory. If the operand is the current-VMCS
pointer, then that pointer is made invalid (set to FFFFFFFF_FFFFFFFFH).
Note that the VMCLEAR instruction might not explicitly write any VMCS data to memory; the data may be already
resident in memory before the VMCLEAR is executed.
Operation
IF (register operand) or (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VM exit;
ELSIF CPL > 0
THEN #GP(0);
ELSE
addr ← contents of 64-bit in-memory operand;
IF addr is not 4KB-aligned OR
addr sets any bits beyond the physical-address width1
THEN VMfail(VMCLEAR with invalid physical address);
ELSIF addr = VMXON pointer
THEN VMfail(VMCLEAR with VMXON pointer);
ELSE
ensure that data for VMCS referenced by the operand is in memory;
initialize implementation-specific data in VMCS region;
launch state of VMCS referenced by the operand ← “clear”
IF operand addr = current-VMCS pointer
THEN current-VMCS pointer ← FFFFFFFF_FFFFFFFFH;
FI;
VMsucceed;
FI;
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the operand is located in an execute-only code segment.
1. If IA32_VMX_BASIC[48] is read as 1, VMfail occurs if addr sets any bits in the range 63:32; see Appendix A.1.
Vol. 3C 30-11
VMX INSTRUCTION REFERENCE
#PF(fault-code)
#SS(0)
If a page fault occurs in accessing the memory operand.
If the memory operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If operand is a register.
If not in VMX operation.
Real-Address Mode Exceptions
#UD
The VMCLEAR instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMCLEAR instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The VMCLEAR instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in
a non-canonical form.
#PF(fault-code)
If a page fault occurs in accessing the memory operand.
#SS(0)
If the source operand is in the SS segment and the memory address is in a non-canonical
form.
#UD
If operand is a register.
If not in VMX operation.
30-12 Vol. 3C
VMX INSTRUCTION REFERENCE
VMFUNC—Invoke VM function
Opcode
Instruction
Description
0F 01 D4
VMFUNC
Invoke VM function specified in EAX.
Description
This instruction allows software in VMX non-root operation to invoke a VM function, which is processor functionality
enabled and configured by software in VMX root operation. The value of EAX selects the specific VM function being
invoked.
The behavior of each VM function (including any additional fault checking) is specified in Section 25.5.5,
“VM Functions”.
Operation
Perform functionality of the VM function specified in EAX;
Flags Affected
Depends on the VM function specified in EAX. See Section 25.5.5, “VM Functions”.
Protected Mode Exceptions (not including those defined by specific VM functions)
#UD
If executed outside VMX non-root operation.
If “enable VM functions” VM-execution control is 0.
If EAX ≥ 64.
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Same exceptions as in protected mode.
Vol. 3C 30-13
VMX INSTRUCTION REFERENCE
VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine
Opcode
Instruction
Description
0F 01 C2
VMLAUNCH
Launch virtual machine managed by current VMCS.
0F 01 C3
VMRESUME
Resume virtual machine managed by current VMCS.
Description
Effects a VM entry managed by the current VMCS.
•
VMLAUNCH fails if the launch state of current VMCS is not “clear”. If the instruction is successful, it sets the
launch state to “launched.”
•
VMRESUME fails if the launch state of the current VMCS is not “launched.”
If VM entry is attempted, the logical processor performs a series of consistency checks as detailed in Chapter 26,
“VM Entries”. Failure to pass checks on the VMX controls or on the host-state area passes control to the instruction
following the VMLAUNCH or VMRESUME instruction. If these pass but checks on the guest-state area fail, the logical
processor loads state from the host-state area of the VMCS, passing control to the instruction referenced by the RIP
field in the host-state area.
VM entry is not allowed when events are blocked by MOV SS or POP SS. Neither VMLAUNCH nor VMRESUME should
be used immediately after either MOV to SS or POP to SS.
Operation
IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VMexit;
ELSIF CPL > 0
THEN #GP(0);
ELSIF current-VMCS pointer is not valid
THEN VMfailInvalid;
ELSIF events are being blocked by MOV SS
THEN VMfailValid(VM entry with events blocked by MOV SS);
ELSIF (VMLAUNCH and launch state of current VMCS is not “clear”)
THEN VMfailValid(VMLAUNCH with non-clear VMCS);
ELSIF (VMRESUME and launch state of current VMCS is not “launched”)
THEN VMfailValid(VMRESUME with non-launched VMCS);
ELSE
Check settings of VMX controls and host-state area;
IF invalid settings
THEN VMfailValid(VM entry with invalid VMX-control field(s)) or
VMfailValid(VM entry with invalid host-state field(s)) or
VMfailValid(VM entry with invalid executive-VMCS pointer)) or
VMfailValid(VM entry with non-launched executive VMCS) or
VMfailValid(VM entry with executive-VMCS pointer not VMXON pointer) or
VMfailValid(VM entry with invalid VM-execution control fields in executive
VMCS)
as appropriate;
ELSE
Attempt to load guest state and PDPTRs as appropriate;
clear address-range monitoring;
IF failure in checking guest state or PDPTRs
THEN VM entry fails (see Section 26.7);
30-14 Vol. 3C
VMX INSTRUCTION REFERENCE
ELSE
Attempt to load MSRs from VM-entry MSR-load area;
IF failure
THEN VM entry fails
(see Section 26.7);
ELSE
IF VMLAUNCH
THEN launch state of VMCS ← “launched”;
FI;
IF in SMM and “entry to SMM” VM-entry control is 0
THEN
IF “deactivate dual-monitor treatment” VM-entry
control is 0
THEN SMM-transfer VMCS pointer ←
current-VMCS pointer;
FI;
IF executive-VMCS pointer is VMXON pointer
THEN current-VMCS pointer ←
VMCS-link pointer;
ELSE current-VMCS pointer ←
executive-VMCS pointer;
FI;
leave SMM;
FI;
VM entry succeeds;
FI;
FI;
FI;
FI;
Further details of the operation of the VM-entry appear in Chapter 26.
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If executed outside VMX operation.
Real-Address Mode Exceptions
#UD
The VMLAUNCH and VMRESUME instructions are not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMLAUNCH and VMRESUME instructions are not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The VMLAUNCH and VMRESUME instructions are not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If executed outside VMX operation.
Vol. 3C 30-15
VMX INSTRUCTION REFERENCE
VMPTRLD—Load Pointer to Virtual-Machine Control Structure
Opcode
Instruction
Description
0F C7 /6
VMPTRLD m64
Loads the current VMCS pointer from memory.
Description
Marks the current-VMCS pointer valid and loads it with the physical address in the instruction operand. The instruction fails if its operand is not properly aligned, sets unsupported physical-address bits, or is equal to the VMXON
pointer. In addition, the instruction fails if the 32 bits in memory referenced by the operand do not match the VMCS
revision identifier supported by this processor.2
The operand of this instruction is always 64 bits and is always in memory.
Operation
IF (register operand) or (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VMexit;
ELSIF CPL > 0
THEN #GP(0);
ELSE
addr ← contents of 64-bit in-memory source operand;
IF addr is not 4KB-aligned OR
addr sets any bits beyond the physical-address width3
THEN VMfail(VMPTRLD with invalid physical address);
ELSIF addr = VMXON pointer
THEN VMfail(VMPTRLD with VMXON pointer);
ELSE
rev ← 32 bits located at physical address addr;
IF rev[30:0] ≠ VMCS revision identifier supported by processor OR
rev[31] = 1 AND processor does not support 1-setting of “VMCS shadowing”
THEN VMfail(VMPTRLD with incorrect VMCS revision identifier);
ELSE
current-VMCS pointer ← addr;
VMsucceed;
FI;
FI;
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory source operand effective address is outside the CS, DS, ES, FS, or GS segment
limit.
If the DS, ES, FS, or GS register contains an unusable segment.
2. Software should consult the VMX capability MSR VMX_BASIC to discover the VMCS revision identifier supported by this processor
(see Appendix A, “VMX Capability Reporting Facility”).
3. If IA32_VMX_BASIC[48] is read as 1, VMfail occurs if addr sets any bits in the range 63:32; see Appendix A.1.
30-16 Vol. 3C
VMX INSTRUCTION REFERENCE
If the source operand is located in an execute-only code segment.
#PF(fault-code)
If a page fault occurs in accessing the memory source operand.
#SS(0)
If the memory source operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If operand is a register.
If not in VMX operation.
Real-Address Mode Exceptions
#UD
The VMPTRLD instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMPTRLD instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The VMPTRLD instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in
a non-canonical form.
#PF(fault-code)
If a page fault occurs in accessing the memory source operand.
#SS(0)
If the source operand is in the SS segment and the memory address is in a non-canonical
form.
#UD
If operand is a register.
If not in VMX operation.
Vol. 3C 30-17
VMX INSTRUCTION REFERENCE
VMPTRST—Store Pointer to Virtual-Machine Control Structure
Opcode
Instruction
Description
0F C7 /7
VMPTRST m64
Stores the current VMCS pointer into memory.
Description
Stores the current-VMCS pointer into a specified memory address. The operand of this instruction is always 64 bits
and is always in memory.
Operation
IF (register operand) or (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VMexit;
ELSIF CPL > 0
THEN #GP(0);
ELSE
64-bit in-memory destination operand ← current-VMCS pointer;
VMsucceed;
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory destination operand effective address is outside the CS, DS, ES, FS, or GS
segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the destination operand is located in a read-only data segment or any code segment.
#PF(fault-code)
If a page fault occurs in accessing the memory destination operand.
#SS(0)
If the memory destination operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If operand is a register.
If not in VMX operation.
Real-Address Mode Exceptions
#UD
The VMPTRST instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMPTRST instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
30-18 Vol. 3C
The VMPTRST instruction is not recognized in compatibility mode.
VMX INSTRUCTION REFERENCE
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the destination operand is in the CS, DS, ES, FS, or GS segments and the memory address
is in a non-canonical form.
#PF(fault-code)
If a page fault occurs in accessing the memory destination operand.
#SS(0)
If the destination operand is in the SS segment and the memory address is in a non-canonical
form.
#UD
If operand is a register.
If not in VMX operation.
Vol. 3C 30-19
VMX INSTRUCTION REFERENCE
VMREAD—Read Field from Virtual-Machine Control Structure
Opcode
Instruction
Description
0F 78
VMREAD r/m64, r64
Reads a specified VMCS field (in 64-bit mode).
0F 78
VMREAD r/m32, r32
Reads a specified VMCS field (outside 64-bit mode).
Description
Reads a specified field from a VMCS and stores it into a specified destination operand (register or memory). In VMX
root operation, the instruction reads from the current VMCS. If executed in VMX non-root operation, the instruction
reads from the VMCS referenced by the VMCS link pointer field in the current VMCS.
The VMCS field is specified by the VMCS-field encoding contained in the register source operand. Outside IA-32e
mode, the source operand has 32 bits, regardless of the value of CS.D. In 64-bit mode, the source operand has 64
bits.
The effective size of the destination operand, which may be a register or in memory, is always 32 bits outside IA32e mode (the setting of CS.D is ignored with respect to operand size) and 64 bits in 64-bit mode. If the VMCS field
specified by the source operand is shorter than this effective operand size, the high bits of the destination operand
are cleared to 0. If the VMCS field is longer, then the high bits of the field are not read.
Note that any faults resulting from accessing a memory destination operand can occur only after determining, in
the operation section below, that the relevant VMCS pointer is valid and that the specified VMCS field is supported.
Operation
IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation AND (“VMCS shadowing” is 0 OR source operand sets bits in range 63:15 OR
VMREAD bit corresponding to bits 14:0 of source operand is 1)4
THEN VMexit;
ELSIF CPL > 0
THEN #GP(0);
ELSIF (in VMX root operation AND current-VMCS pointer is not valid) OR
(in VMX non-root operation AND VMCS link pointer is not valid)
THEN VMfailInvalid;
ELSIF source operand does not correspond to any VMCS field
THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component);
ELSE
IF in VMX root operation
THEN destination operand ← contents of field indexed by source operand in current VMCS;
ELSE destination operand ← contents of field indexed by source operand in VMCS referenced by VMCS link pointer;
FI;
VMsucceed;
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
4. The VMREAD bit for a source operand is defined as follows. Let x be the value of bits 14:0 of the source operand and let addr be the
VMREAD-bitmap address. The corresponding VMREAD bit is in bit position x & 7 of the byte at physical address addr | (x » 3).
30-20 Vol. 3C
VMX INSTRUCTION REFERENCE
If a memory destination operand effective address is outside the CS, DS, ES, FS, or GS
segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the destination operand is located in a read-only data segment or any code segment.
#PF(fault-code)
If a page fault occurs in accessing a memory destination operand.
#SS(0)
If a memory destination operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If not in VMX operation.
Real-Address Mode Exceptions
#UD
The VMREAD instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMREAD instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The VMREAD instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory destination operand is in the CS, DS, ES, FS, or GS segments and the memory
address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs in accessing a memory destination operand.
#SS(0)
If the memory destination operand is in the SS segment and the memory address is in a noncanonical form.
#UD
If not in VMX operation.
Vol. 3C 30-21
VMX INSTRUCTION REFERENCE
VMRESUME—Resume Virtual Machine
See VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine.
30-22 Vol. 3C
VMX INSTRUCTION REFERENCE
VMWRITE—Write Field to Virtual-Machine Control Structure
Opcode
Instruction
Description
0F 79
VMWRITE r64, r/m64
Writes a specified VMCS field (in 64-bit mode)
0F 79
VMWRITE r32, r/m32
Writes a specified VMCS field (outside 64-bit mode)
Description
Writes the contents of a primary source operand (register or memory) to a specified field in a VMCS. In VMX root
operation, the instruction writes to the current VMCS. If executed in VMX non-root operation, the instruction writes
to the VMCS referenced by the VMCS link pointer field in the current VMCS.
The VMCS field is specified by the VMCS-field encoding contained in the register secondary source operand.
Outside IA-32e mode, the secondary source operand is always 32 bits, regardless of the value of CS.D. In 64-bit
mode, the secondary source operand has 64 bits.
The effective size of the primary source operand, which may be a register or in memory, is always 32 bits outside
IA-32e mode (the setting of CS.D is ignored with respect to operand size) and 64 bits in 64-bit mode. If the VMCS
field specified by the secondary source operand is shorter than this effective operand size, the high bits of the
primary source operand are ignored. If the VMCS field is longer, then the high bits of the field are cleared to 0.
Note that any faults resulting from accessing a memory source operand occur after determining, in the operation
section below, that the relevant VMCS pointer is valid but before determining if the destination VMCS field is
supported.
Operation
IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation AND (“VMCS shadowing” is 0 OR secondary source operand sets bits in range 63:15 OR
VMWRITE bit corresponding to bits 14:0 of secondary source operand is 1)5
THEN VMexit;
ELSIF CPL > 0
THEN #GP(0);
ELSIF (in VMX root operation AND current-VMCS pointer is not valid) OR
(in VMX non-root operation AND VMCS-link pointer is not valid)
THEN VMfailInvalid;
ELSIF secondary source operand does not correspond to any VMCS field
THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component);
ELSIF VMCS field indexed by secondary source operand is a VM-exit information field AND
processor does not support writing to such fields6
THEN VMfailValid(VMWRITE to read-only VMCS component);
ELSE
IF in VMX root operation
THEN field indexed by secondary source operand in current VMCS ← primary source operand;
ELSE field indexed by secondary source operand in VMCS referenced by VMCS link pointer ← primary source operand;
FI;
VMsucceed;
FI;
5. The VMWRITE bit for a secondary source operand is defined as follows. Let x be the value of bits 14:0 of the secondary source operand and let addr be the VMWRITE-bitmap address. The corresponding VMWRITE bit is in bit position x & 7 of the byte at physical
address addr | (x » 3).
6. Software can discover whether these fields can be written by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6).
Vol. 3C 30-23
VMX INSTRUCTION REFERENCE
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If a memory source operand effective address is outside the CS, DS, ES, FS, or GS segment
limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the source operand is located in an execute-only code segment.
#PF(fault-code)
If a page fault occurs in accessing a memory source operand.
#SS(0)
If a memory source operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If not in VMX operation.
Real-Address Mode Exceptions
#UD
The VMWRITE instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMWRITE instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The VMWRITE instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the memory source operand is in the CS, DS, ES, FS, or GS segments and the memory
address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs in accessing a memory source operand.
#SS(0)
If the memory source operand is in the SS segment and the memory address is in a noncanonical form.
#UD
If not in VMX operation.
30-24 Vol. 3C
VMX INSTRUCTION REFERENCE
VMXOFF—Leave VMX Operation
Opcode
Instruction
Description
0F 01 C4
VMXOFF
Leaves VMX operation.
Description
Takes the logical processor out of VMX operation, unblocks INIT signals, conditionally re-enables A20M, and clears
any address-range monitoring.7
Operation
IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VMexit;
ELSIF CPL > 0
THEN #GP(0);
ELSIF dual-monitor treatment of SMIs and SMM is active
THEN VMfail(VMXOFF under dual-monitor treatment of SMIs and SMM);
ELSE
leave VMX operation;
unblock INIT;
IF IA32_SMM_MONITOR_CTL[2] = 08
THEN unblock SMIs;
IF outside SMX operation9
THEN unblock and enable A20M;
FI;
clear address-range monitoring;
VMsucceed;
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If executed in VMX root operation with CPL > 0.
#UD
If executed outside VMX operation.
Real-Address Mode Exceptions
#UD
The VMXOFF instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMXOFF instruction is not recognized in virtual-8086 mode.
7. See the information on MONITOR/MWAIT in Chapter 8, “Multiple-Processor Management,” of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A.
8. Setting IA32_SMM_MONITOR_CTL[bit 2] to 1 prevents VMXOFF from unblocking SMIs regardless of the value of the register’s value
bit (bit 0). Not all processors allow this bit to be set to 1. Software should consult the VMX capability MSR IA32_VMX_MISC (see
Appendix A.6) to determine whether this is allowed.
9. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the
last execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference.”
Vol. 3C 30-25
VMX INSTRUCTION REFERENCE
Compatibility Mode Exceptions
#UD
The VMXOFF instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If executed in VMX root operation with CPL > 0.
#UD
If executed outside VMX operation.
30-26 Vol. 3C
VMX INSTRUCTION REFERENCE
VMXON—Enter VMX Operation
Opcode
Instruction
Description
F3 0F C7 /6
VMXON m64
Enter VMX root operation.
Description
Puts the logical processor in VMX operation with no current VMCS, blocks INIT signals, disables A20M, and clears
any address-range monitoring established by the MONITOR instruction.10
The operand of this instruction is a 4KB-aligned physical address (the VMXON pointer) that references the VMXON
region, which the logical processor may use to support VMX operation. This operand is always 64 bits and is always
in memory.
Operation
IF (register operand) or (CR0.PE = 0) or (CR4.VMXE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF not in VMX operation
THEN
IF (CPL > 0) or (in A20M mode) or
(the values of CR0 and CR4 are not supported in VMX operation; see Section 23.8) or
(bit 0 (lock bit) of IA32_FEATURE_CONTROL MSR is clear) or
(in SMX operation11 and bit 1 of IA32_FEATURE_CONTROL MSR is clear) or
(outside SMX operation and bit 2 of IA32_FEATURE_CONTROL MSR is clear)
THEN #GP(0);
ELSE
addr ← contents of 64-bit in-memory source operand;
IF addr is not 4KB-aligned or
addr sets any bits beyond the physical-address width12
THEN VMfailInvalid;
ELSE
rev ← 32 bits located at physical address addr;
IF rev[30:0] ≠ VMCS revision identifier supported by processor OR rev[31] = 1
THEN VMfailInvalid;
ELSE
current-VMCS pointer ← FFFFFFFF_FFFFFFFFH;
enter VMX operation;
block INIT signals;
block and disable A20M;
clear address-range monitoring;
IF the processor supports Intel PT but does not allow it to be used in VMX operation13
THEN IA32_RTIT_CTL.TraceEn ← 0;
FI;
VMsucceed;
10. See the information on MONITOR/MWAIT in Chapter 8, “Multiple-Processor Management,” of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A.
11. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last
execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference.”
12. If IA32_VMX_BASIC[48] is read as 1, VMfailInvalid occurs if addr sets any bits in the range 63:32; see Appendix A.1.
13. Software should read the VMX capability MSR IA32_VMX_MISC to determine whether the processor allows Intel PT to be used in
VMX operation (see Appendix A.6).
Vol. 3C 30-27
VMX INSTRUCTION REFERENCE
FI;
FI;
FI;
ELSIF in VMX non-root operation
THEN VMexit;
ELSIF CPL > 0
THEN #GP(0);
ELSE VMfail(“VMXON executed in VMX root operation”);
FI;
Flags Affected
See the operation section and Section 30.2.
Protected Mode Exceptions
#GP(0)
If executed outside VMX operation with CPL>0 or with invalid CR0 or CR4 fixed bits.
If executed in A20M mode.
If the memory source operand effective address is outside the CS, DS, ES, FS, or GS segment
limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the source operand is located in an execute-only code segment.
If the value of the IA32_FEATURE_CONTROL MSR does not support entry to VMX operation in
the current processor mode.
#PF(fault-code)
If a page fault occurs in accessing the memory source operand.
#SS(0)
If the memory source operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#UD
If operand is a register.
If executed with CR4.VMXE = 0.
Real-Address Mode Exceptions
#UD
The VMXON instruction is not recognized in real-address mode.
Virtual-8086 Mode Exceptions
#UD
The VMXON instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
The VMXON instruction is not recognized in compatibility mode.
64-Bit Mode Exceptions
#GP(0)
If executed outside VMX operation with CPL > 0 or with invalid CR0 or CR4 fixed bits.
If executed in A20M mode.
If the source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in
a non-canonical form.
If the value of the IA32_FEATURE_CONTROL MSR does not support entry to VMX operation in
the current processor mode.
#PF(fault-code)
If a page fault occurs in accessing the memory source operand.
#SS(0)
If the source operand is in the SS segment and the memory address is in a non-canonical
form.
#UD
If operand is a register.
If executed with CR4.VMXE = 0.
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VMX INSTRUCTION REFERENCE
30.4
VM INSTRUCTION ERROR NUMBERS
For certain error conditions, the VM-instruction error field is loaded with an error number to indicate the source of
the error. Table 30-1 lists VM-instruction error numbers.
Table 30-1. VM-Instruction Error Numbers
Error
Description
Number
1
VMCALL executed in VMX root operation
2
VMCLEAR with invalid physical address
3
VMCLEAR with VMXON pointer
4
VMLAUNCH with non-clear VMCS
5
VMRESUME with non-launched VMCS
6
VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME)1
7
VM entry with invalid control field(s)2,3
8
VM entry with invalid host-state field(s)2
9
VMPTRLD with invalid physical address
10
VMPTRLD with VMXON pointer
11
VMPTRLD with incorrect VMCS revision identifier
12
VMREAD/VMWRITE from/to unsupported VMCS component
13
VMWRITE to read-only VMCS component
15
VMXON executed in VMX root operation
16
VM entry with invalid executive-VMCS pointer2
17
VM entry with non-launched executive VMCS2
18
VM entry with executive-VMCS pointer not VMXON pointer (when attempting to deactivate the dual-monitor treatment of
SMIs and SMM)2
19
VMCALL with non-clear VMCS (when attempting to activate the dual-monitor treatment of SMIs and SMM)
20
VMCALL with invalid VM-exit control fields
22
VMCALL with incorrect MSEG revision identifier (when attempting to activate the dual-monitor treatment of SMIs and SMM)
23
VMXOFF under dual-monitor treatment of SMIs and SMM
24
VMCALL with invalid SMM-monitor features (when attempting to activate the dual-monitor treatment of SMIs and SMM)
25
VM entry with invalid VM-execution control fields in executive VMCS (when attempting to return from SMM)2,3
26
VM entry with events blocked by MOV SS.
28
Invalid operand to INVEPT/INVVPID.
NOTES:
1. Earlier versions of this manual described this error as “VMRESUME with a corrupted VMCS”.
2. VM-entry checks on control fields and host-state fields may be performed in any order. Thus, an indication by error number of one
cause does not imply that there are not also other errors. Different processors may give different error numbers for the same VMCS.
3. Error number 7 is not used for VM entries that return from SMM that fail due to invalid VM-execution control fields in the executive
VMCS. Error number 25 is used for these cases.
Vol. 3C 30-29
VMX INSTRUCTION REFERENCE
30-30 Vol. 3C
CHAPTER 31
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
31.1
VMX SYSTEM PROGRAMMING OVERVIEW
The Virtual Machine Monitor (VMM) is a software class used to manage virtual machines (VM). This chapter
describes programming considerations for VMMs.
Each VM behaves like a complete physical machine and can run operating system (OS) and applications. The VMM
software layer runs at the most privileged level and has complete ownership of the underlying system hardware.
The VMM controls creation of a VM, transfers control to a VM, and manages situations that can cause transitions
between the guest VMs and host VMM. The VMM allows the VMs to share the underlying hardware and yet provides
isolation between the VMs. The guest software executing in a VM is unaware of any transitions that might have
occurred between the VM and its host.
31.2
SUPPORTING PROCESSOR OPERATING MODES IN GUEST ENVIRONMENTS
Typically, VMMs transfer control to a VM using VMX transitions referred to as VM entries. The boundary conditions
that define what a VM is allowed to execute in isolation are specified in a virtual-machine control structure (VMCS).
As noted in Section 23.8, processors may fix certain bits in CR0 and CR4 to specific values and not support other
values. The first processors to support VMX operation require that CR0.PE and CR0.PG be 1 in VMX operation. Thus,
a VM entry is allowed only to guests with paging enabled that are in protected mode or in virtual-8086 mode. Guest
execution in other processor operating modes need to be specially handled by the VMM.
One example of such a condition is guest execution in real-mode. A VMM could support guest real-mode execution
using at least two approaches:
•
•
By using a fast instruction set emulator in the VMM.
By using the similarity between real-mode and virtual-8086 mode to support real-mode guest execution in a
virtual-8086 container. The virtual-8086 container may be implemented as a virtual-8086 container task within
a monitor that emulates real-mode guest state and instructions, or by running the guest VM as the virtual-8086
container (by entering the guest with RFLAGS.VM1 set). Attempts by real-mode code to access privileged state
outside the virtual-8086 container would trap to the VMM and would also need to be emulated.
Another example of such a condition is guest execution in protected mode with paging disabled. A VMM could
support such guest execution by using “identity” page tables to emulate unpaged protected mode.
31.2.1
Using Unrestricted Guest Mode
Processors which support the “unrestricted guest” VM-execution control allow VM software to run in real-address
mode and unpaged protected mode. Since these modes do not use paging, VMM software must virtualize guest
memory using EPT.
Special notes for 64-bit VMM software using the 1-setting of the “unrestricted guest” VM-execution control:
•
It is recommended that 64-bit VMM software use the 1-settings of the "load IA32_EFER" VM entry control and
the "save IA32_EFER" VM-exit control. If VM entry is establishing CR0.PG=0 and if the "IA-32e mode guest"
and "load IA32_EFER" VM entry controls are both 0, VM entry leaves IA32_EFER.LME unmodified (i.e., the host
value will persist in the guest).
•
It is not necessary for VMM software to track guest transitions into and out of IA-32e mode for the purpose of
maintaining the correct setting of the "IA-32e mode guest" VM entry control. This is because VM exits on
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX operation also support Intel 64 architecture. For processors that do not support Intel 64 architecture, this notation refers to the 32-bit
forms of those registers (EAX, EIP, ESP, EFLAGS, etc.).
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VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
processors supporting the 1-setting of the "unrestricted guest" VM-execution control save the (guest) value of
IA32_EFER.LMA into the "IA-32e mode guest" VM entry control.
31.3
MANAGING VMCS REGIONS AND POINTERS
A VMM must observe necessary procedures when working with a VMCS, the associated VMCS pointer, and the
VMCS region. It must also not assume the state of persistency for VMCS regions in memory or cache.
Before entering VMX operation, the host VMM allocates a VMXON region. A VMM can host several virtual machines
and have many VMCSs active under its management. A unique VMCS region is required for each virtual machine;
a VMXON region is required for the VMM itself.
A VMM determines the VMCS region size by reading IA32_VMX_BASIC MSR; it creates VMCS regions of this size
using a 4-KByte-aligned area of physical memory. Each VMCS region needs to be initialized with a VMCS revision
identifier (at byte offset 0) identical to the revision reported by the processor in the VMX capability MSR.
NOTE
Software must not read or write directly to the VMCS data region as the format is not architecturally
defined. Consequently, Intel recommends that the VMM remove any linear-address mappings to
VMCS regions before loading.
System software does not need to do special preparation to the VMXON region before entering into VMX operation.
The address of the VMXON region for the VMM is provided as an operand to VMXON instruction. Once in VMX root
operation, the VMM needs to prepare data fields in the VMCS that control the execution of a VM upon a VM entry.
The VMM can make a VMCS the current VMCS by using the VMPTRLD instruction. VMCS data fields must be read or
written only through VMREAD and VMWRITE commands respectively.
Every component of the VMCS is identified by a 32-bit encoding that is provided as an operand to VMREAD and
VMWRITE. Appendix B provides the encodings. A VMM must properly initialize all fields in a VMCS before using the
current VMCS for VM entry.
A VMCS is referred to as a controlling VMCS if it is the current VMCS on a logical processor in VMX non-root operation. A current VMCS for controlling a logical processor in VMX non-root operation may be referred to as a working
VMCS if the logical processor is not in VMX non-root operation. The relationship of active, current (i.e. working) and
controlling VMCS during VMX operation is shown in Figure 31-1.
NOTE
As noted in Section 24.1, the processor may optimize VMX operation by maintaining the state of an
active VMCS (one for which VMPTRLD has been executed) on the processor. Before relinquishing
control to other system software that may, without informing the VMM, remove power from the
processor (e.g., for transitions to S3 or S4) or leave VMX operation, a VMM must VMCLEAR all active
VMCSs. This ensures that all VMCS data cached by the processor are flushed to memory and that
no other software can corrupt the current VMM’s VMCS data. It is also recommended that the VMM
execute VMXOFF after such executions of VMCLEAR.
The VMX capability MSR IA32_VMX_BASIC reports the memory type used by the processor for accessing a VMCS
or any data structures referenced through pointers in the VMCS. Software must maintain the VMCS structures in
cache-coherent memory. Software must always map the regions hosting the I/O bitmaps, MSR bitmaps, VM-exit
MSR-store area, VM-exit MSR-load area, and VM-entry MSR-load area to the write-back (WB) memory type.
Mapping these regions to uncacheable (UC) memory type is supported, but strongly discouraged due to negative
impact on performance.
31.4
USING VMX INSTRUCTIONS
VMX instructions are allowed only in VMX root operation. An attempt to execute a VMX instruction in VMX non-root
operation causes a VM exit.
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VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
(a) VMX Operation and VMX Transitions
VM Entry
VM Entry
VM Entry
VM Entry
VMXOFF
Processor
Operation
VMXON
VM Exit
VM Exit
VM Exit
VM Exit
Legend:
VMX Root
Operation
Outside
VMX
Operation
VMX
Non-Root
Operation
(b) State of VMCS and VMX Operation
VMLAUNCH
VMPTRLD B
VMRESUME
VMCLEAR B
VM Exit
VM Exit
VMCS B
VMCS A
VMPTRLD A
VMPTRLD A
VM Exit
VMLAUNCH
Legend:
Inactive
VMCS
Current VMCS
(working)
Active VMCS
(not current)
VM Exit
VMRESUME
VMCLEAR A
Current VMCS
(controlling)
Figure 31-1. VMX Transitions and States of VMCS in a Logical Processor
Processors perform various checks while executing any VMX instruction. They follow well-defined error handling on
failures. VMX instruction execution failures detected before loading of a guest state are handled by the processor
as follows:
•
•
If the working-VMCS pointer is not valid, the instruction fails by setting RFLAGS.CF to 1.
If the working-VMCS pointer is valid, RFLAGS.ZF is set to 1 and the proper error-code is saved in the VMinstruction error field of the working-VMCS.
Software is required to check RFLAGS.CF and RFLAGS.ZF to determine the success or failure of VMX instruction
executions.
The following items provide details regarding use of the VM-entry instructions (VMLAUNCH and VMRESUME):
•
If the working-VMCS pointer is valid, the state of the working VMCS may cause the VM-entry instruction to fail.
RFLAGS.ZF is set to 1 and one of the following values is saved in the VM-instruction error field:
— 4: VMLAUNCH with non-clear VMCS.
If this error occurs, software can avoid the error by executing VMRESUME.
— 5: VMRESUME with non-launched VMCS.
If this error occurs, software can avoid the error by executing VMLAUNCH.
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— 6: VMRESUME after VMXOFF.1
If this error occurs, software can avoid the error by executing the following sequence of instructions:
VMPTRST working-VMCS pointer
VMCLEAR working-VMCS pointer
VMPTRLD working-VMCS pointer
VMLAUNCH
(VMPTRST may not be necessary is software already knows the working-VMCS pointer.)
•
If none of the above errors occur, the processor checks on the VMX controls and host-state area. If any of these
checks fail, the VM-entry instruction fails. RFLAGS.ZF is set to 1 and either 7 (VM entry with invalid control
field(s)) or 8 (VM entry with invalid host-state field(s)) is saved in the VM-instruction error field.
•
After a VM-entry instruction (VMRESUME or VMLAUNCH) successfully completes the general checks and checks
on VMX controls and the host-state area (see Section 26.2), any errors encountered while loading of gueststate (due to bad guest-state or bad MSR loading) causes the processor to load state from the host-state area
of the working VMCS as if a VM exit had occurred (see Section 31.7).
This failure behavior differs from that of VM exits in that no guest-state is saved to the guest-state area. A VMM
can detect its VM-exit handler was invoked by such a failure by checking bit 31 (for 1) in the exit reason field of
the working VMCS and further identify the failure by using the exit qualification field.
See Chapter 26 for more details about the VM-entry instructions.
31.5
VMM SETUP & TEAR DOWN
VMMs need to ensure that the processor is running in protected mode with paging before entering VMX operation.
The following list describes the minimal steps required to enter VMX root operation with a VMM running at CPL = 0.
•
•
Check VMX support in processor using CPUID.
Determine the VMX capabilities supported by the processor through the VMX capability MSRs. See Section
31.5.1 and Appendix A.
•
Create a VMXON region in non-pageable memory of a size specified by IA32_VMX_BASIC MSR and aligned to a
4-KByte boundary. Software should read the capability MSRs to determine width of the physical addresses that
may be used for the VMXON region and ensure the entire VMXON region can be addressed by addresses with
that width. Also, software must ensure that the VMXON region is hosted in cache-coherent memory.
•
Initialize the version identifier in the VMXON region (the first 31 bits) with the VMCS revision identifier reported
by capability MSRs. Clear bit 31 of the first 4 bytes of the VMXON region.
•
Ensure the current processor operating mode meets the required CR0 fixed bits (CR0.PE = 1, CR0.PG = 1).
Other required CR0 fixed bits can be detected through the IA32_VMX_CR0_FIXED0 and
IA32_VMX_CR0_FIXED1 MSRs.
•
Enable VMX operation by setting CR4.VMXE = 1. Ensure the resultant CR4 value supports all the CR4 fixed bits
reported in the IA32_VMX_CR4_FIXED0 and IA32_VMX_CR4_FIXED1 MSRs.
•
Ensure that the IA32_FEATURE_CONTROL MSR (MSR index 3AH) has been properly programmed and that its
lock bit is set (Bit 0 = 1). This MSR is generally configured by the BIOS using WRMSR.
•
Execute VMXON with the physical address of the VMXON region as the operand. Check successful execution of
VMXON by checking if RFLAGS.CF = 0.
Upon successful execution of the steps above, the processor is in VMX root operation.
A VMM executing in VMX root operation and CPL = 0 leaves VMX operation by executing VMXOFF and verifies
successful execution by checking if RFLAGS.CF = 0 and RFLAGS.ZF = 0.
If an SMM monitor has been configured to service SMIs while in VMX operation (see Section 34.15), the SMM
monitor needs to be torn down before the executive monitor can leave VMX operation (see Section 34.15.7).
VMXOFF fails for the executive monitor (a VMM that entered VMX operation by way of issuing VMXON) if SMM
monitor is configured.
1. Earlier versions of this manual described this error as “VMRESUME with a corrupted VMCS”.
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31.5.1
Algorithms for Determining VMX Capabilities
As noted earlier, a VMM should determine the VMX capabilities supported by the processor by reading the VMX
capability MSRs. The architecture for these MSRs is detailed in Appendix A.
As noted in Chapter 26, “VM Entries”, certain VMX controls are reserved and must be set to a specific value (0 or
1) determined by the processor. The specific value to which a reserved control must be set is its default setting.
Most controls have a default setting of 0; Appendix A.2 identifies those controls that have a default setting of 1. The
term default1 describes the class of controls whose default setting is 1. The are controls in this class from the pinbased VM-execution controls, the primary processor-based VM-execution controls, the VM-exit controls, and the
VM-entry controls. There are no secondary processor-based VM-execution controls in the default1 class.
Future processors may define new functionality for one or more reserved controls. Such processors would allow
each newly defined control to be set either to 0 or to 1. Software that does not desire a control’s new functionality
should set the control to its default setting.
The capability MSRs IA32_VMX_PINBASED_CTLS, IA32_VMX_PROCBASED_CTLS, IA32_VMX_EXIT_CTLS, and
IA32_VMX_ENTRY_CTLS report, respectively, on the allowed settings of most of the pin-based VM-execution
controls, the primary processor-based VM-execution controls, the VM-exit controls, and the VM-entry controls.
However, they will always report that any control in the default1 class must be 1. If a logical processor allows any
control in the default1 class to be 0, it indicates this fact by returning 1 for the value of bit 55 of the
IA32_VMX_BASIC MSR. If this bit is 1, the logical processor supports the capability MSRs
IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
IA32_VMX_TRUE_ENTRY_CTLS. These capability MSRs report, respectively, on the allowed settings of all of the
pin-based VM-execution controls, the primary processor-based VM-execution controls, the VM-exit controls, and
the VM-entry controls.
Software may use one of the following high-level algorithms to determine the correct default control settings:1
1. The following algorithm does not use the details given in Appendix A.2:
a. Ignore bit 55 of the IA32_VMX_BASIC MSR.
b. Using RDMSR, read the VMX capability MSRs IA32_VMX_PINBASED_CTLS, IA32_VMX_PROCBASED_CTLS,
IA32_VMX_EXIT_CTLS, and IA32_VMX_ENTRY_CTLS.
c.
Set the VMX controls as follows:
i)
If the relevant VMX capability MSR reports that a control has a single setting, use that setting.
ii) If (1) the relevant VMX capability MSR reports that a control can be set to 0 or 1; and (2) the control’s
meaning is known to the VMM; then set the control based on functionality desired.
iii) If (1) the relevant VMX capability MSR reports that a control can be set to 0 or 1; and (2) the control’s
meaning is not known to the VMM; then set the control to 0.
A VMM using this algorithm will set to 1 all controls in the default1 class (in step (c)(i)). It will operate
correctly even on processors that allow some controls in the default1 class to be 0. However, such a VMM will
not be able to use the new features enabled by the 0-setting of such controls. For that reason, this algorithm
is not recommended.
2. The following algorithm uses the details given in Appendix A.2. This algorithm requires software to know the
identity of the controls in the default1 class:
a. Using RDMSR, read the IA32_VMX_BASIC MSR.
b. Use bit 55 of that MSR as follows:
i)
If bit 55 is 0, use RDMSR to read the VMX capability MSRs IA32_VMX_PINBASED_CTLS,
IA32_VMX_PROCBASED_CTLS, IA32_VMX_EXIT_CTLS, and IA32_VMX_ENTRY_CTLS.
ii) If bit 55 is 1, use RDMSR to read the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
IA32_VMX_TRUE_ENTRY_CTLS.
1. These algorithms apply only to the pin-based VM-execution controls, the primary processor-based VM-execution controls, the VMexit controls, and the VM-entry controls. Because there are no secondary processor-based VM-execution controls in the default1
class, a VMM can always set to 0 any such control whose meaning is unknown to it.
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c.
Set the VMX controls as follows:
i)
If the relevant VMX capability MSR reports that a control has a single setting, use that setting.
ii) If (1) the relevant VMX capability MSR reports that a control can be set to 0 or 1; and (2) the control’s
meaning is known to the VMM; then set the control based on functionality desired.
iii) If (1) the relevant VMX capability MSR reports that a control can be set to 0 or 1; (2) the control’s
meaning is not known to the VMM; and (3) the control is not in the default1 class; then set the control
to 0.
iv) If (1) the relevant VMX capability MSR reports that a control can be set to 0 or 1; (2) the control’s
meaning is not known to the VMM; and (3) the control is in the default1 class; then set the control to 1.
A VMM using this algorithm will set to 1 all controls in default1 class whose meaning it does not know (either
in step (c)(i) or step (c)(iv)). It will operate correctly even on processors that allow some controls in the
default1 class to be 0. Unlike a VMM using Algorithm 1, a VMM using Algorithm 2 will be able to use the new
features enabled by the 0-setting of such controls.
3. The following algorithm uses the details given in Appendix A.2. This algorithm does not require software to
know the identity of the controls in the default1 class:
a. Using RDMSR, read the VMX capability MSRs IA32_VMX_BASIC, IA32_VMX_PINBASED_CTLS,
IA32_VMX_PROCBASED_CTLS, IA32_VMX_EXIT_CTLS, and IA32_VMX_ENTRY_CTLS.
b. If bit 55 of the IA32_VMX_BASIC MSR is 0, set the VMX controls as follows:
i)
If the relevant VMX capability MSR reports that a control has a single setting, use that setting.
ii) If (1) the relevant VMX capability MSR reports that a control can be set to 0 or 1; and (2) the control’s
meaning is known to the VMM; then set the control based on functionality desired.
iii) If (1) the relevant VMX capability MSR reports that a control can be set to 0 or 1; and (2) the control’s
meaning is not known to the VMM; then set the control to 0.
c.
If bit 55 of the IA32_VMX_BASIC MSR is 1, use RDMSR to read the VMX capability MSRs
IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS,
and IA32_VMX_TRUE_ENTRY_CTLS. Set the VMX controls as follows:
i)
If the relevant VMX capability MSR just read reports that a control has a single setting, use that
setting.
ii) If (1) the relevant VMX capability MSR just read reports that a control can be set to 0 or 1; and (2) the
control’s meaning is known to the VMM; then set the control based on functionality desired.
iii) If (1) the relevant VMX capability MSR just read reports that a control can be set to 0 or 1; (2) the
control’s meaning is not known to the VMM; and (3) the relevant VMX capability MSR as read in step (a)
reports that a control can be set to 0; then set the control to 0.
iv) If (1) the relevant VMX capability MSR just read reports that a control can be set to 0 or 1; (2) the
control’s meaning is not known to the VMM; and (3) the relevant VMX capability MSR as read in step (a)
reports that a control must be 1; then set the control to 1.
A VMM using this algorithm will set to 1 all controls in the default1 class whose meaning it does not know (in
step (b)(i), step (c)(i), or step (c)(iv)). It will operate correctly even on processors that allow some controls
in the default1 class to be 0. Unlike a VMM using Algorithm 1, a VMM using Algorithm 3 will be able to use the
new features enabled by the 0-setting of such controls. Unlike a VMM using Algorithm 2, a VMM using
Algorithm 3 need not know the identities of the controls in the default1 class.
31.6
PREPARATION AND LAUNCHING A VIRTUAL MACHINE
The following list describes the minimal steps required by the VMM to set up and launch a guest VM.
•
Create a VMCS region in non-pageable memory of size specified by the VMX capability MSR IA32_VMX_BASIC
and aligned to 4-KBytes. Software should read the capability MSRs to determine width of the physical
addresses that may be used for a VMCS region and ensure the entire VMCS region can be addressed by
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addresses with that width. The term “guest-VMCS address” refers to the physical address of the new VMCS
region for the following steps.
•
Initialize the version identifier in the VMCS (first 31 bits) with the VMCS revision identifier reported by the VMX
capability MSR IA32_VMX_BASIC. Clear bit 31 of the first 4 bytes of the VMCS region.
•
Execute the VMCLEAR instruction by supplying the guest-VMCS address. This will initialize the new VMCS
region in memory and set the launch state of the VMCS to “clear”. This action also invalidates the workingVMCS pointer register to FFFFFFFF_FFFFFFFFH. Software should verify successful execution of VMCLEAR by
checking if RFLAGS.CF = 0 and RFLAGS.ZF = 0.
•
Execute the VMPTRLD instruction by supplying the guest-VMCS address. This initializes the working-VMCS
pointer with the new VMCS region’s physical address.
•
Issue a sequence of VMWRITEs to initialize various host-state area fields in the working VMCS. The initialization
sets up the context and entry-points to the VMM upon subsequent VM exits from the guest. Host-state fields
include control registers (CR0, CR3 and CR4), selector fields for the segment registers (CS, SS, DS, ES, FS, GS
and TR), and base-address fields (for FS, GS, TR, GDTR and IDTR; RSP, RIP and the MSRs that control fast
system calls).
Chapter 27 describes the host-state consistency checking done by the processor for VM entries. The VMM is
required to set up host-state that comply with these consistency checks. For example, VMX requires the hostarea to have a task register (TR) selector with TI and RPL fields set to 0 and pointing to a valid TSS.
•
Use VMWRITEs to set up the various VM-exit control fields, VM-entry control fields, and VM-execution control
fields in the VMCS. Care should be taken to make sure the settings of individual fields match the allowed 0 and
1 settings for the respective controls as reported by the VMX capability MSRs (see Appendix A). Any settings
inconsistent with the settings reported by the capability MSRs will cause VM entries to fail.
•
Use VMWRITE to initialize various guest-state area fields in the working VMCS. This sets up the context and
entry-point for guest execution upon VM entry. Chapter 27 describes the guest-state loading and checking
done by the processor for VM entries to protected and virtual-8086 guest execution.
•
The VMM is required to set up guest-state that complies with these consistency checks:
— If the VMM design requires the initial VM launch to cause guest software (typically the guest virtual BIOS)
execution from the guest’s reset vector, it may need to initialize the guest execution state to reflect the
state of a physical processor at power-on reset (described in Chapter 9, Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A).
— The VMM may need to initialize additional guest execution state that is not captured in the VMCS gueststate area by loading them directly on the respective processor registers. Examples include general
purpose registers, the CR2 control register, debug registers, floating point registers and so forth. VMM may
support lazy loading of FPU, MMX, SSE, and SSE2 states with CR0.TS = 1 (described in Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A).
•
Execute VMLAUNCH to launch the guest VM. If VMLAUNCH fails due to any consistency checks before gueststate loading, RFLAGS.CF or RFLAGS.ZF will be set and the VM-instruction error field (see Section 24.9.5) will
contain the error-code. If guest-state consistency checks fail upon guest-state loading, the processor loads
state from the host-state area as if a VM exit had occurred (see Section 31.6).
VMLAUNCH updates the controlling-VMCS pointer with the working-VMCS pointer and saves the old value of
controlling-VMCS as the parent pointer. In addition, the launch state of the guest VMCS is changed to “launched”
from “clear”. Any programmed exit conditions will cause the guest to VM exit to the VMM. The VMM should execute
VMRESUME instruction for subsequent VM entries to guests in a “launched” state.
31.7
HANDLING OF VM EXITS
This section provides examples of software steps involved in a VMM’s handling of VM-exit conditions:
•
Determine the exit reason through a VMREAD of the exit-reason field in the working-VMCS. Appendix C
describes exit reasons and their encodings.
•
VMREAD the exit-qualification from the VMCS if the exit-reason field provides a valid qualification. The exitqualification field provides additional details on the VM-exit condition. For example, in case of page faults, the
exit-qualification field provides the guest linear address that caused the page fault.
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•
Depending on the exit reason, fetch other relevant fields from the VMCS. Appendix C lists the various exit
reasons.
•
Handle the VM-exit condition appropriately in the VMM. This may involve the VMM emulating one or more guest
instructions, programming the underlying host hardware resources, and then re-entering the VM to continue
execution.
31.7.1
Handling VM Exits Due to Exceptions
As noted in Section 25.2, an exception causes a VM exit if the bit corresponding to the exception’s vector is set in
the exception bitmap. (For page faults, the error code also determines whether a VM exit occurs.) This section
provide some guidelines of how a VMM might handle such exceptions.
Exceptions result when a logical processor encounters an unusual condition that software may not have expected.
When guest software encounters an exception, it may be the case that the condition was caused by the guest software. For example, a guest application may attempt to access a page that is restricted to supervisor access. Alternatively, the condition causing the exception may have been established by the VMM. For example, a guest OS may
attempt to access a page that the VMM has chosen to make not present.
When the condition causing an exception was established by guest software, the VMM may choose to reflect the
exception to guest software. When the condition was established by the VMM itself, the VMM may choose to
resume guest software after removing the condition.
31.7.1.1
Reflecting Exceptions to Guest Software
If the VMM determines that a VM exit was caused by an exception due to a condition established by guest software,
it may reflect that exception to guest software. The VMM would cause the exception to be delivered to guest software, where it can be handled as it would be if the guest were running on a physical machine. This section
describes how that may be done.
In general, the VMM can deliver the exception to guest software using VM-entry event injection as described in
Section 26.5. The VMM can copy (using VMREAD and VMWRITE) the contents of the VM-exit interruption-information field (which is valid, since the VM exit was caused by an exception) to the VM-entry interruption-information
field (which, if valid, will cause the exception to be delivered as part of the next VM entry). The VMM would also
copy the contents of the VM-exit interruption error-code field to the VM-entry exception error-code field; this need
not be done if bit 11 (error code valid) is clear in the VM-exit interruption-information field. After this, the VMM can
execute VMRESUME.
The following items provide details that may qualify the general approach:
•
Care should be taken to ensure that reserved bits 30:12 in the VM-entry interruption-information field are 0. In
particular, some VM exits may set bit 12 in the VM-exit interruption-information field to indicate NMI
unblocking due to IRET. If this bit is copied as 1 into the VM-entry interruption-information field, the next
VM entry will fail because that bit should be 0.
•
Bit 31 (valid) of the IDT-vectoring information field indicates, if set, that the exception causing the VM exit
occurred while another event was being delivered to guest software. If this is the case, it may not be
appropriate simply to reflect that exception to guest software. To provide proper virtualization of the exception
architecture, a VMM should handle nested events as a physical processor would. Processor handling is
described in Chapter 6, “Interrupt 8—Double Fault Exception (#DF)” in Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A.
— The VMM should reflect the exception causing the VM exit to guest software in any of the following cases:
•
The value of bits 10:8 (interruption type) of the IDT-vectoring information field is anything other than 3
(hardware exception).
•
The value of bits 7:0 (vector) of the IDT-vectoring information field indicates a benign exception (1, 2,
3, 4, 5, 6, 7, 9, 16, 17, 18, or 19).
•
The value of bits 7:0 (vector) of the VM-exit interruption-information field indicates a benign exception.
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VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
•
The value of bits 7:0 of the IDT-vectoring information field indicates a contributory exception (0, 10,
11, 12, or 13) and the value of bits 7:0 of the VM-exit interruption-information field indicates a page
fault (14).
— If the value of bits 10:8 of the IDT-vectoring information field is 3 (hardware exception), the VMM should
reflect a double-fault exception to guest software in any of the following cases:
•
The value of bits 7:0 of the IDT-vectoring information field and the value of bits 7:0 of the VM-exit
interruption-information field each indicates a contributory exception.
•
The value of bits 7:0 of the IDT-vectoring information field indicates a page fault and the value of
bits 7:0 of the VM-exit interruption-information field indicates either a contributory exception or a page
fault.
A VMM can reflect a double-fault exception to guest software by setting the VM-entry interruptioninformation and VM-entry exception error-code fields as follows:
•
•
•
•
•
•
Set bits 7:0 (vector) of the VM-entry interruption-information field to 8 (#DF).
Set bits 10:8 (interruption type) of the VM-entry interruption-information field to 3 (hardware
exception).
Set bit 11 (deliver error code) of the VM-entry interruption-information field to 1.
Clear bits 30:12 (reserved) of VM-entry interruption-information field.
Set bit 31 (valid) of VM-entry interruption-information field.
Set the VM-entry exception error-code field to zero.
— If the value of bits 10:8 of the IDT-vectoring information field is 3 (hardware exception) and the value of
bits 7:0 is 8 (#DF), guest software would have encountered a triple fault. Event injection should not be
used in this case. The VMM may choose to terminate the guest, or it might choose to enter the guest in the
shutdown activity state.
31.7.1.2
Resuming Guest Software after Handling an Exception
If the VMM determines that a VM exit was caused by an exception due to a condition established by the VMM itself,
it may choose to resume guest software after removing the condition. The approach for removing the condition
may be specific to the VMM’s software architecture. and algorithms This section describes how guest software may
be resumed after removing the condition.
In general, the VMM can resume guest software simply by executing VMRESUME. The following items provide
details of cases that may require special handling:
•
If the “NMI exiting” VM-execution control is 0, bit 12 of the VM-exit interruption-information field indicates that
the VM exit was due to a fault encountered during an execution of the IRET instruction that unblocked nonmaskable interrupts (NMIs). In particular, it provides this indication if the following are both true:
— Bit 31 (valid) in the IDT-vectoring information field is 0.
— The value of bits 7:0 (vector) of the VM-exit interruption-information field is not 8 (the VM exit is not due
to a double-fault exception).
If both are true and bit 12 of the VM-exit interruption-information field is 1, NMIs were blocked before guest
software executed the IRET instruction that caused the fault that caused the VM exit. The VMM should set bit 3
(blocking by NMI) in the interruptibility-state field (using VMREAD and VMWRITE) before resuming guest
software.
•
If the “virtual NMIs” VM-execution control is 1, bit 12 of the VM-exit interruption-information field indicates
that the VM exit was due to a fault encountered during an execution of the IRET instruction that removed
virtual-NMI blocking. In particular, it provides this indication if the following are both true:
— Bit 31 (valid) in the IDT-vectoring information field is 0.
— The value of bits 7:0 (vector) of the VM-exit interruption-information field is not 8 (the VM exit is not due
to a double-fault exception).
If both are true and bit 12 of the VM-exit interruption-information field is 1, there was virtual-NMI blocking
before guest software executed the IRET instruction that caused the fault that caused the VM exit. The VMM
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should set bit 3 (blocking by NMI) in the interruptibility-state field (using VMREAD and VMWRITE) before
resuming guest software.
•
Bit 31 (valid) of the IDT-vectoring information field indicates, if set, that the exception causing the VM exit
occurred while another event was being delivered to guest software. The VMM should ensure that the other
event is delivered when guest software is resumed. It can do so using the VM-entry event injection described
in Section 26.5 and detailed in the following paragraphs:
— The VMM can copy (using VMREAD and VMWRITE) the contents of the IDT-vectoring information field
(which is presumed valid) to the VM-entry interruption-information field (which, if valid, will cause the
exception to be delivered as part of the next VM entry).
•
The VMM should ensure that reserved bits 30:12 in the VM-entry interruption-information field are 0. In
particular, the value of bit 12 in the IDT-vectoring information field is undefined after all VM exits. If this
bit is copied as 1 into the VM-entry interruption-information field, the next VM entry will fail because the
bit should be 0.
•
If the “virtual NMIs” VM-execution control is 1 and the value of bits 10:8 (interruption type) in the IDTvectoring information field is 2 (indicating NMI), the VM exit occurred during delivery of an NMI that had
been injected as part of the previous VM entry. In this case, bit 3 (blocking by NMI) will be 1 in the interruptibility-state field in the VMCS. The VMM should clear this bit; otherwise, the next VM entry will fail
(see Section 26.3.1.5).
— The VMM can also copy the contents of the IDT-vectoring error-code field to the VM-entry exception errorcode field. This need not be done if bit 11 (error code valid) is clear in the IDT-vectoring information field.
— The VMM can also copy the contents of the VM-exit instruction-length field to the VM-entry instructionlength field. This need be done only if bits 10:8 (interruption type) in the IDT-vectoring information field
indicate either software interrupt, privileged software exception, or software exception.
31.8
MULTI-PROCESSOR CONSIDERATIONS
The most common VMM design will be the symmetric VMM. This type of VMM runs the same VMM binary on all
logical processors. Like a symmetric operating system, the symmetric VMM is written to ensure all critical data is
updated by only one processor at a time, IO devices are accessed sequentially, and so forth. Asymmetric VMM
designs are possible. For example, an asymmetric VMM may run its scheduler on one processor and run just
enough of the VMM on other processors to allow the correct execution of guest VMs. The remainder of this section
focuses on the multi-processor considerations for a symmetric VMM.
A symmetric VMM design does not preclude asymmetry in its operations. For example, a symmetric VMM can
support asymmetric allocation of logical processor resources to guests. Multiple logical processors can be brought
into a single guest environment to support an MP-aware guest OS. Because an active VMCS can not control more
than one logical processor simultaneously, a symmetric VMM must make copies of its VMCS to control the VM allocated to support an MP-aware guest OS. Care must be taken when accessing data structures shared between these
VMCSs. See Section 31.8.4.
Although it may be easier to develop a VMM that assumes a fully-symmetric view of hardware capabilities (with all
processors supporting the same processor feature sets, including the same revision of VMX), there are advantages
in developing a VMM that comprehends different levels of VMX capability (reported by VMX capability MSRs). One
possible advantage of such an approach could be that an existing software installation (VMM and guest software
stack) could continue to run without requiring software upgrades to the VMM, when the software installation is
upgraded to run on hardware with enhancements in the processor’s VMX capabilities. Another advantage could be
that a single software installation image, consisting of a VMM and guests, could be deployed to multiple hardware
platforms with varying VMX capabilities. In such cases, the VMM could fall back to a common subset of VMX
features supported by all VMX revisions, or choose to understand the asymmetry of the VMX capabilities and assign
VMs accordingly.
This section outlines some of the considerations to keep in mind when developing an MP-aware VMM.
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31.8.1
Initialization
Before enabling VMX, an MP-aware VMM must check to make sure that all processors in the system are compatible
and support features required. This can be done by:
•
Checking the CPUID on each logical processor to ensure VMX is supported and that the overall feature set of
each logical processor is compatible.
•
•
Checking VMCS revision identifiers on each logical processor.
Checking each of the “allowed-1” or “allowed-0” fields of the VMX capability MSR’s on each processor.
31.8.2
Moving a VMCS Between Processors
An MP-aware VMM is free to assign any logical processor to a VM. But for performance considerations, moving a
guest VMCS to another logical processor is slower than resuming that guest VMCS on the same logical processor.
Certain VMX performance features (such as caching of portions of the VMCS in the processor) are optimized for a
guest VMCS that runs on the same logical processor.
The reasons are:
•
To restart a guest on the same logical processor, a VMM can use VMRESUME. VMRESUME is expected to be
faster than VMLAUNCH in general.
•
To migrate a VMCS to another logical processor, a VMM must use the sequence of VMCLEAR, VMPTRLD and
VMLAUNCH.
•
Operations involving VMCLEAR can impact performance negatively. See
Section 24.11.3.
A VMM scheduler should make an effort to schedule a guest VMCS to run on the logical processor where it last ran.
Such a scheduler might also benefit from doing lazy VMCLEARs (that is: performing a VMCLEAR on a VMCS only
when the scheduler knows the VMCS is being moved to a new logical processor). The remainder of this section
describes the steps a VMM must take to move a VMCS from one processor to another.
A VMM must check the VMCS revision identifier in the VMX capability MSR IA32_VMX_BASIC to determine if the
VMCS regions are identical between all logical processors. If the VMCS regions are identical (same revision ID) the
following sequence can be used to move or copy the VMCS from one logical processor to another:
•
Perform a VMCLEAR operation on the source logical processor. This ensures that all VMCS data that may be
cached by the processor are flushed to memory.
•
Copy the VMCS region from one memory location to another location. This is an optional step assuming the
VMM wishes to relocate the VMCS or move the VMCS to another system.
•
Perform a VMPTRLD of the physical address of VMCS region on the destination processor to establish its current
VMCS pointer.
If the revision identifiers are different, each field must be copied to an intermediate structure using individual reads
(VMREAD) from the source fields and writes (VMWRITE) to destination fields. Care must be taken on fields that are
hard-wired to certain values on some processor implementations.
31.8.3
Paired Index-Data Registers
A VMM may need to virtualize hardware that is visible to software using paired index-data registers. Paired indexdata register interfaces, such as those used in PCI (CF8, CFC), require special treatment in cases where a VM
performing writes to these pairs can be moved during execution. In this case, the index (e.g. CF8) should be part
of the virtualized state. If the VM is moved during execution, writes to the index should be redone so subsequent
data reads/writes go to the right location.
31.8.4
External Data Structures
Certain fields in the VMCS point to external data structures (for example: the MSR bitmap, the I/O bitmaps). If a
logical processor is in VMX non-root operation, none of the external structures referenced by that logical
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processor's current VMCS should be modified by any logical processor or DMA. Before updating one of these structures, the VMM must ensure that no logical processor whose current VMCS references the structure is in VMX nonroot operation.
If a VMM uses multiple VMCS with each VMCS using separate external structures, and these structures must be
kept synchronized, the VMM must apply the same care to updating these structures.
31.8.5
CPUID Emulation
CPUID reports information that is used by OS and applications to detect hardware features. It also provides multithreading/multi-core configuration information. For example, MP-aware OSs rely on data reported by CPUID to
discover the topology of logical processors in a platform (see Section 8.9, “Programming Considerations for Hardware Multi-Threading Capable Processors,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A).
If a VMM is to support asymmetric allocation of logical processor resources to guest OSs that are MP aware, then
the VMM must emulate CPUID for its guests. The emulation of CPUID by the VMM must ensure the guest’s view of
CPUID leaves are consistent with the logical processor allocation committed by the VMM to each guest OS.
31.9
32-BIT AND 64-BIT GUEST ENVIRONMENTS
For the most part, extensions provided by VMX to support virtualization are orthogonal to the extensions provided
by Intel 64 architecture. There are considerations that impact VMM designs. These are described in the following
subsections.
31.9.1
Operating Modes of Guest Environments
For Intel 64 processors, VMX operation supports host and guest environments that run in IA-32e mode or without
IA-32e mode. VMX operation also supports host and guest environments on IA-32 processors.
A VMM entering VMX operation while IA-32e mode is active is considered to be an IA-32e mode host. A VMM
entering VMX operation while IA-32e mode is not activated or not available is referred to as a 32-bit VMM. The type
of guest operations such VMMs support are summarized in Table 31-1.
Table 31-1. Operating Modes for Host and Guest Environments
Capability
Guest Operation
in IA-32e mode
Guest Operation
Not Requiring IA-32e Mode
IA-32e mode VMM
Yes
Yes
32-bit VMM
Not supported
Yes
A VM exit may occur to an IA-32e mode guest in either 64-bit sub-mode or compatibility sub-mode of IA-32e
mode. VMMs may resume guests in either mode. The sub-mode in which an IA-32e mode guest resumes VMX nonroot operation is determined by the attributes of the code segment which experienced the VM exit. If CS.L = 1, the
guest is executing in 64-bit mode; if CS.L = 0, the guest is executing in compatibility mode (see Section 31.9.5).
Not all of an IA-32e mode VMM must run in 64-bit mode. While some parts of an IA-32e mode VMM must run in 64bit mode, there are only a few restrictions preventing a VMM from executing in compatibility mode. The most
notable restriction is that most VMX instructions cause exceptions when executed in compatibility mode.
31.9.2
Handling Widths of VMCS Fields
Individual VMCS control fields must be accessed using VMREAD or VMWRITE instructions. Outside of 64-Bit mode,
VMREAD and VMWRITE operate on 32 bits of data. The widths of VMCS control fields may vary depending on
whether a processor supports Intel 64 architecture.
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Many VMCS fields are architected to extend transparently on processors supporting Intel 64 architecture (64 bits
on processors that support Intel 64 architecture, 32 bits on processors that do not). Some VMCS fields are 64-bits
wide regardless of whether the processor supports Intel 64 architecture or is in IA-32e mode.
31.9.2.1
Natural-Width VMCS Fields
Many VMCS fields operate using natural width. Such fields return (on reads) and set (on writes) 32-bits when operating in 32-bit mode and 64-bits when operating in 64-bit mode. For the most part, these fields return the naturally
expected data widths. The “Guest RIP” field in the VMCS guest-state area is an example of this type of field.
31.9.2.2
64-Bit VMCS Fields
Unlike natural width fields, these fields are fixed to 64-bit width on all processors. When in 64-bit mode, reads of
these fields return 64-bit wide data and writes to these fields write 64-bits. When outside of 64-bit mode, reads of
these fields return the low 32-bits and writes to these fields write the low 32-bits and zero the upper 32-bits.
Should a non-IA-32e mode host require access to the upper 32-bits of these fields, a separate VMCS encoding is
used when issuing VMREAD/VMWRITE instructions.
The VMCS control field “MSR bitmap address” (which contains the physical address of a region of memory which
specifies which MSR accesses should generate VM-exits) is an example of this type of field. Specifying encoding
00002004H to VMREAD returns the lower 32-bits to non-IA-32e mode hosts and returns 64-bits to 64-bit hosts.
The separate encoding 00002005H returns only the upper 32-bits.
31.9.3
IA-32e Mode Hosts
An IA-32e mode host is required to support 64-bit guest environments. Because activating IA-32e mode currently
requires that paging be disabled temporarily and VMX entry requires paging to be enabled, IA-32e mode must be
enabled before entering VMX operation. For this reason, it is not possible to toggle in and out of IA-32e mode in a
VMM.
Section 31.5 describes the steps required to launch a VMM. An IA-32e mode host is also required to set the “host
address-space size” VMCS VM-exit control to 1. The value of this control is then loaded in the IA32_EFER.LME/LMA
and CS.L bits on each VM exit. This establishes a 64-bit host environment as execution transfers to the VMM entry
point. At a minimum, the entry point is required to be in a 64-bit code segment. Subsequently, the VMM can, if it
chooses, switch to 32-bit compatibility mode on a code-segment basis (see Section 31.9.1). Note, however, that
VMX instructions other than VMCALL and VMFUNC are not supported in compatibility mode; they generate an
invalid opcode exception if used.
The following VMCS controls determine the value of IA32_EFER when a VM exit occurs: the “host address-space
size” control (described above), the “load IA32_EFER” VM-exit control, the “VM-exit MSR-load count,” and the “VMexit MSR-load address” (see Section 27.3).
If the “load IA32_EFER” VM-exit control is 1, the value of the LME and LMA bits in the IA32_EFER field in the hoststate area must be the value of the “host address-space size” VM-exit control.
The loading of IA32_EFER.LME/LMA and CS.L bits established by the “host address-space size” control precede any
loading of the IA32_EFER MSR due from the VM-exit MSR-load area. If IA32_EFER is specified in the VM-exit MSRload area, the value of the LME bit in the load image of IA32_EFER should match the setting of the “host addressspace size” control. Otherwise the attempt to modify the LME bit (while paging is enabled) will lead to a VMX-abort.
However, IA32_EFER.LMA is always set by the processor to equal IA32_EFER.LME & CR0.PG; the value specified
for LMA in the load image of the IA32_EFER MSR is ignored. For these and performance reasons, VMM writers may
choose to not use the VM-exit/entry MSR-load/save areas for IA32_EFER.
On a VMM teardown, VMX operation should be exited before deactivating IA-32e mode if the latter is required.
31.9.4
IA-32e Mode Guests
A 32-bit guest can be launched by either IA-32e-mode hosts or non-IA-32e-mode hosts. A 64-bit guests can only
be launched by a IA-32e-mode host.
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In addition to the steps outlined in Section 31.6, VMM writers need to:
•
Set the “IA-32e-mode guest” VM-entry control to 1 in the VMCS to assure VM-entry (VMLAUNCH or
VMRESUME) will establish a 64-bit (or 32-bit compatible) guest operating environment.
•
•
Enable paging (CR0.PG) and PAE mode (CR4.PAE) to assure VM-entry to a 64-bit guest will succeed.
Ensure that the host to be in IA-32e mode (the IA32_EFER.LMA must be set to 1) and the setting of the VM-exit
“host address-space size” control bit in the VMCS must also be set to 1.
If each of the above conditions holds true, then VM-entry will copy the value of the VM-entry “IA-32e-mode guest”
control bit into the guests IA32_EFER.LME bit, which will result in subsequent activation of IA-32e mode. If any of
the above conditions is false, the VM-entry will fail and load state from the host-state area of the working VMCS as
if a VM exit had occurred (see Section 26.7).
The following VMCS controls determine the value of IA32_EFER on a VM entry: the “IA-32e-mode guest” VM-entry
control (described above), the “load IA32_EFER” VM-entry control, the “VM-entry MSR-load count,” and the “VMentry MSR-load address” (see Section 26.4).
If the “load IA32_EFER” VM-entry control is 1, the value of the LME and LMA bits in the IA32_EFER field in the
guest-state area must be the value of the “IA-32e-mode guest” VM-entry control. Otherwise, the VM entry fails.
The loading of IA32_EFER.LME bit (described above) precedes any loading of the IA32_EFER MSR from the VMentry MSR-load area of the VMCS. If loading of IA32_EFER is specified in the VM-entry MSR-load area, the value of
the LME bit in the load image should be match the setting of the “IA-32e-mode guest” VM-entry control. Otherwise,
the attempt to modify the LME bit (while paging is enabled) results in a failed VM entry. However, IA32_EFER.LMA
is always set by the processor to equal IA32_EFER.LME & CR0.PG; the value specified for LMA in the load image of
the IA32_EFER MSR is ignored. For these and performance reasons, VMM writers may choose to not use the VMexit/entry MSR-load/save areas for IA32_EFER MSR.
Note that the VMM can control the processor’s architectural state when transferring control to a VM. VMM writers
may choose to launch guests in protected mode and subsequently allow the guest to activate IA-32e mode or they
may allow guests to toggle in and out of IA-32e mode. In this case, the VMM should require VM exit on accesses to
the IA32_EFER MSR to detect changes in the operating mode and modify the VM-entry “IA-32e-mode guest”
control accordingly.
A VMM should save/restore the extended (full 64-bit) contents of the guest general-purpose registers, the new
general-purpose registers (R8-R15) and the SIMD registers introduced in 64-bit mode should it need to modify
these upon VM exit.
31.9.5
32-Bit Guests
To launch or resume a 32-bit guest, VMM writers can follow the steps outlined in Section 31.6, making sure that the
“IA-32e-mode guest” VM-entry control bit is set to 0. Then the “IA-32e-mode guest” control bit is copied into the
guest IA32_EFER.LME bit, establishing IA32_EFER.LMA as 0.
31.10
HANDLING MODEL SPECIFIC REGISTERS
Model specific registers (MSR) provide a wide range of functionality. They affect processor features, control the
programming interfaces, or are used in conjunction with specific instructions. As part of processor virtualization, a
VMM may wish to protect some or all MSR resources from direct guest access.
VMX operation provides the following features to virtualize processor MSRs.
31.10.1 Using VM-Execution Controls
Processor-based VM-execution controls provide two levels of support for handling guest access to processor MSRs
using RDMSR and WRMSR:
•
MSR bitmaps: In VMX implementations that support a 1-setting (see Appendix A) of the user-MSR-bitmaps
execution control bit, MSR bitmaps can be used to provide flexibility in managing guest MSR accesses. The
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MSR-bitmap-address in the guest VMCS can be programmed by VMM to point to a bitmap region which
specifies VM-exit behavior when reading and writing individual MSRs.
MSR bitmaps form a 4-KByte region in physical memory and are required to be aligned to a 4-KByte boundary.
The first 1-KByte region manages read control of MSRs in the range 00000000H-00001FFFH; the second 1KByte region covers read control of MSR addresses in the range C0000000H-C0001FFFH. The bitmaps for write
control of these MSRs are located in the 2-KByte region immediately following the read control bitmaps. While
the MSR bitmap address is part of VMCS, the MSR bitmaps themselves are not. This implies MSR bitmaps are
not accessible through VMREAD and VMWRITE instructions but rather by using ordinary memory writes. Also,
they are not specially cached by the processor and may be placed in normal cache-coherent memory by the
VMM.
When MSR bitmap addresses are properly programmed and the use-MSR-bitmap control (see Section 24.6.2)
is set, the processor consults the associated bit in the appropriate bitmap on guest MSR accesses to the corresponding MSR and causes a VM exit if the bit in the bitmap is set. Otherwise, the access is permitted to
proceed. This level of protection may be utilized by VMMs to selectively allow guest access to some MSRs while
virtualizing others.
•
Default MSR protection: If the use-MSR-bitmap control is not set, an attempt by a guest to access any MSR
causes a VM exit. This also occurs for any attempt to access an MSR outside the ranges identified above (even
if the use-MSR-bitmap control is set).
VM exits due to guest MSR accesses may be identified by the VMM through VM-exit reason codes. The MSR-read
exit reason implies guest software attempted to read an MSR protected either by default or through MSR bitmaps.
The MSR-write exit reason implies guest software attempting to write a MSR protected through the VM-execution
controls. Upon VM exits caused by MSR accesses, the VMM may virtualize the guest MSR access through emulation
of RDMSR/WRMSR.
31.10.2 Using VM-Exit Controls for MSRs
If a VMM allows its guest to access MSRs directly, the VMM may need to store guest MSR values and load host MSR
values for these MSRs on VM exits. This is especially true if the VMM uses the same MSRs while in VMX root operation.
A VMM can use the VM-exit MSR-store-address and the VM-exit MSR-store-count exit control fields (see Section
24.7.2) to manage how MSRs are stored on VM exits. The VM-exit MSR-store-address field contains the physical
address (16-byte aligned) of the VM-exit MSR-store area (a table of entries with 16 bytes per entry). Each table
entry specifies an MSR whose value needs to be stored on VM exits. The VM-exit MSR-store-count contains the
number of entries in the table.
Similarly the VM-exit MSR-load-address and VM-exit MSR-load-count fields point to the location and size of the VMexit MSR load area. The entries in the VM-exit MSR-load area contain the host expected values of specific MSRs
when a VM exit occurs.
Upon VM-exit, bits 127:64 of each entry in the VM-exit MSR-store area is updated with the contents of the MSR
indexed by bits 31:0. Also, bits 127:64 of each entry in the VM-exit MSR-load area is updated by loading with
values from bits 127:64 the contents of the MSR indexed by bits 31:0.
31.10.3 Using VM-Entry Controls for MSRs
A VMM may require specific MSRs to be loaded explicitly on VM entries while launching or resuming guest execution. The VM-entry MSR-load-address and VM-entry MSR-load-count entry control fields determine how MSRs are
loaded on VM-entries. The VM-entry MSR-load-address and count fields are similar in structure and function to the
VM-exit MSR-load address and count fields, except the MSR loading is done on VM-entries.
31.10.4 Handling Special-Case MSRs and Instructions
A number of instructions make use of designated MSRs in their operation. The VMM may need to consider saving
the states of those MSRs. Instructions that merit such consideration include SYSENTER/SYSEXIT,
SYSCALL/SYSRET, SWAPGS.
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31.10.4.1 Handling IA32_EFER MSR
The IA32_EFER MSR includes bit fields that allow system software to enable processor features. For example: the
SCE bit enables SYSCALL/SYSRET and the NXE bit enables the execute-disable bits in the paging-structure entries.
VMX provides hardware support to load the IA32_EFER MSR on VMX transitions and to save it on VM exits. Because
of this, VMM software need not use the RDMSR and WRMSR instruction to give the register different values during
host and guest execution.
31.10.4.2 Handling the SYSENTER and SYSEXIT Instructions
The SYSENTER and SYSEXIT instructions use three dedicated MSRs (IA32_SYSENTER_CS, IA32_SYSENTER_ESP
and IA32_SYSENTER_EIP) to manage fast system calls. These MSRs may be utilized by both the VMM and the
guest OS to manage system calls in VMX root operation and VMX non-root operation respectively.
VM entries load these MSRs from fields in the guest-state area of the VMCS. VM exits save the values of these MSRs
into those fields and loads the MSRs from fields in the host-state area.
31.10.4.3 Handling the SYSCALL and SYSRET Instructions
The SYSCALL/SYSRET instructions are similar to SYSENTER/SYSEXIT but are designed to operate within the
context of a 64-bit flat code segment. They are available only in 64-bit mode and only when the SCE bit of the
IA32_EFER MSR is set. SYSCALL/SYSRET invocations can occur from either 32-bit compatibility mode application
code or from 64-bit application code. Three related MSR registers (IA32_STAR, IA32_LSTAR, IA32_FMASK) are
used in conjunction with fast system calls/returns that use these instructions.
64-Bit hosts which make use of these instructions in the VMM environment will need to save the guest state of the
above registers on VM exit, load the host state, and restore the guest state on VM entry. One possible approach is
to use the VM-exit MSR-save and MSR-load areas and the VM-entry MSR-load area defined by controls in the VMCS.
A disadvantage to this approach, however, is that the approach results in the unconditional saving, loading, and
restoring of MSR registers on each VM exit or VM entry.
Depending on the design of the VMM, it is likely that many VM-exits will require no fast system call support but the
VMM will be burdened with the additional overhead of saving and restoring MSRs if the VMM chooses to support fast
system call uniformly. Further, even if the host intends to support fast system calls during a VM-exit, some of the
MSR values (such as the setting of the SCE bit in IA32_EFER) may not require modification as they may already be
set to the appropriate value in the guest.
For performance reasons, a VMM may perform lazy save, load, and restore of these MSR values on certain VM exits
when it is determined that this is acceptable. The lazy-save-load-restore operation can be carried out “manually”
using RDMSR and WRMSR.
31.10.4.4 Handling the SWAPGS Instruction
The SWAPGS instruction is available only in 64-bit mode. It swaps the contents of two specific MSRs
(IA32_GS_BASE and IA32_KERNEL_GS_BASE). The IA32_GS_BASE MSR shadows the base address portion of the
GS descriptor register; the IA32_KERNEL_GS_BASE MSR holds the base address of the GS segment used by the
kernel (typically it houses kernel structures). SWAPGS is intended for use with fast system calls when in 64-bit
mode to allow immediate access to kernel structures on transition to kernel mode.
Similar to SYSCALL/SYSRET, IA-32e mode hosts which use fast system calls may need to save, load, and restore
these MSR registers on VM exit and VM entry using the guidelines discussed in previous paragraphs.
31.10.4.5 Implementation Specific Behavior on Writing to Certain MSRs
As noted in Section 26.4 and Section 27.4, a processor may prevent writing to certain MSRs when loading guest
states on VM entries or storing guest states on VM exits. This is done to ensure consistent operation. The subset
and number of MSRs subject to restrictions are implementation specific. For initial VMX implementations, there are
two MSRs: IA32_BIOS_UPDT_TRIG and IA32_BIOS_SIGN_ID (see Chapter 35).
31-16 Vol. 3C
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
31.10.5 Handling Accesses to Reserved MSR Addresses
Privileged software (either a VMM or a guest OS) can access a model specific register by specifying addresses in
MSR address space. VMMs, however, must prevent a guest from accessing reserved MSR addresses in MSR address
space.
Consult Chapter 35 for lists of supported MSRs and their usage. Use the MSR bitmap control to cause a VM exit
when a guest attempts to access a reserved MSR address. The response to such a VM exit should be to reflect
#GP(0) back to the guest.
31.11
HANDLING ACCESSES TO CONTROL REGISTERS
Bit fields in control registers (CR0, CR4) control various aspects of processor operation. The VMM must prevent
guests from modifying bits in CR0 or CR4 that are reserved at the time the VMM is written.
Guest/host masks should be used by the VMM to cause VM exits when a guest attempts to modify reserved bits.
Read shadows should be used to ensure that the guest always reads the reserved value (usually 0) for such bits.
The VMM response to VM exits due to attempts from a guest to modify reserved bits should be to emulate the
response which the processor would have normally produced (usually a #GP(0)).
31.12
PERFORMANCE CONSIDERATIONS
VMX provides hardware features that may be used for improving processor virtualization performance. VMMs must
be designed to use this support properly. The basic idea behind most of these performance optimizations of the
VMM is to reduce the number of VM exits while executing a guest VM.
This section lists ways that VMMs can take advantage of the performance enhancing features in VMX.
•
Read Access to Control Registers. Analysis of common client workloads with common PC operating systems
in a virtual machine shows a large number of VM-exits are caused by control register read accesses (particularly CR0). Reads of CR0 and CR4 does not cause VM exits. Instead, they return values from the CR0/CR4 readshadows configured by the VMM in the guest controlling-VMCS with the guest-expected values.
•
Write Access to Control Registers. Most VMM designs require only certain bits of the control registers to be
protected from direct guest access. Write access to CR0/CR4 registers can be reduced by defining the hostowned and guest-owned bits in them through the CR0/CR4 host/guest masks in the VMCS. CR0/CR4 write
values by the guest are qualified with the mask bits. If they change only guest-owned bits, they are allowed
without causing VM exits. Any write that cause changes to host-owned bits cause VM exits and need to be
handled by the VMM.
•
Access Rights based Page Table protection. For VMM that implement access-rights-based page table
protection, the VMCS provides a CR3 target value list that can be consulted by the processor to determine if a
VM exit is required. Loading of CR3 with a value matching an entry in the CR3 target-list are allowed to proceed
without VM exits. The VMM can utilize the CR3 target-list to save page-table hierarchies whose state is
previously verified by the VMM.
•
Page-fault handling. Another common cause for a VM exit is due to page-faults induced by guest address
remapping done through virtual memory virtualization. VMX provides page-fault error-code mask and match
fields in the VMCS to filter VM exits due to page-faults based on their cause (reflected in the error-code).
31.13
USE OF THE VMX-PREEMPTION TIMER
The VMX-preemption timer allows VMM software to preempt guest VM execution after a specified amount of time.
Typical VMX-preemption timer usage is to program the initial VM quantum into the timer, save the timer value on
each successive VM-exit (using the VM-exit control “save preemption timer value”) and run the VM until the timer
expires.
In an alternative scenario, the VMM may use another timer (e.g. the TSC) to track the amount of time the VM has
run while still using the VMX-preemption timer for VM preemption. In this scenario the VMM would not save the
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VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
VMX-preemption timer on each VM-exit but instead would reload the VMX-preemption timer with initial VM
quantum less the time the VM has already run. This scenario includes all the VM-entry and VM-exit latencies in the
VM run time.
In both scenarios, on each successive VM-entry the VMX-preemption timer contains a smaller value until the VM
quantum ends. If the VMX-preemption timer is loaded with a value smaller than the VM-entry latency then the VM
will not execute any instructions before the timer expires. The VMM must ensure the initial VM quantum is greater
than the VM-entry latency; otherwise the VM will make no forward progress.
31-18 Vol. 3C
CHAPTER 32
VIRTUALIZATION OF SYSTEM RESOURCES
32.1
OVERVIEW
When a VMM is hosting multiple guest environments (VMs), it must monitor potential interactions between software components using the same system resources. These interactions can require the virtualization of resources.
This chapter describes the virtualization of system resources. These include: debugging facilities, address translation, physical memory, and microcode update facilities.
32.2
VIRTUALIZATION SUPPORT FOR DEBUGGING FACILITIES
The Intel 64 and IA-32 debugging facilities (see Chapter 17) provide breakpoint instructions, exception conditions,
register flags, debug registers, control registers and storage buffers for functions related to debugging system and
application software. In VMX operation, a VMM can support debugging system and application software from within
virtual machines if the VMM properly virtualizes debugging facilities. The following list describes features relevant
to virtualizing these facilities.
•
The VMM can program the exception-bitmap (see Section 24.6.3) to ensure it gets control on debug functions
(like breakpoint exceptions occurring while executing guest code such as INT3 instructions). Normally, debug
exceptions modify debug registers (such as DR6, DR7, IA32_DEBUGCTL). However, if debug exceptions cause
VM exits, exiting occurs before register modification.
•
The VMM may utilize the VM-entry event injection facilities described in Section 26.5 to inject debug or
breakpoint exceptions to the guest. See Section 32.2.1 for a more detailed discussion.
•
The MOV-DR exiting control bit in the processor-based VM-execution control field (see Section 24.6.2) can be
enabled by the VMM to cause VM exits on explicit guest access of various processor debug registers (for
example, MOV to/from DR0-DR7). These exits would always occur on guest access of DR0-DR7 registers
regardless of the values in CPL, DR4.DE or DR7.GD. Since all guest task switches cause VM exits, a VMM can
control any indirect guest access or modification of debug registers during guest task switches.
•
Guest software access to debug-related model-specific registers (such as IA32_DEBUGCTL MSR) can be
trapped by the VMM through MSR access control features (such as the MSR-bitmaps that are part of processorbased VM-execution controls). See Section 31.10 for details on MSR virtualization.
•
Debug registers such as DR7 and the IA32_DEBUGCTL MSR may be explicitly modified by the guest (through
MOV-DR or WRMSR instructions) or modified implicitly by the processor as part of generating debug
exceptions. The current values of DR7 and the IA32_DEBUGCTL MSR are saved to guest-state area of VMCS on
every VM exit. Pending debug exceptions are debug exceptions that are recognized by the processor but not yet
delivered. See Section 26.6.3 for details on pending debug exceptions.
•
DR7 and the IA32-DEBUGCTL MSR are loaded from values in the guest-state area of the VMCS on every VM
entry. This allows the VMM to properly virtualize debug registers when injecting debug exceptions to guest.
Similarly, the RFLAGS1 register is loaded on every VM entry (or pushed to stack if injecting a virtual event) from
guest-state area of the VMCS. Pending debug exceptions are also loaded from guest-state area of VMCS so that
they may be delivered after VM entry is completed.
32.2.1
Debug Exceptions
If a VMM emulates a guest instruction that would encounter a debug trap (single step or data or I/O breakpoint), it
should cause that trap to be delivered. The VMM should not inject the debug exception using VM-entry event injection, but should set the appropriate bits in the pending debug exceptions field. This method will give the trap the
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX operation also support Intel 64 architecture. For processors that do not support Intel 64 architecture, this notation refers to the 32-bit
forms of those registers (EAX, EIP, ESP, EFLAGS, etc.).
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VIRTUALIZATION OF SYSTEM RESOURCES
right priority with respect to other events. (If the exception bitmap was programmed to cause VM exits on debug
exceptions, the debug trap will cause a VM exit. At this point, the trap can be injected during VM entry with the
proper priority.)
There is a valid pending debug exception if the BS bit (see Table 24-4) is set, regardless of the values of RFLAGS.TF
or IA32_DEBUGCTL.BTF. The values of these bits do not impact the delivery of pending debug exceptions.
VMMs should exercise care when emulating a guest write (attempted using WRMSR) to IA32_DEBUGCTL to modify
BTF if this is occurring with RFLAGS.TF = 1 and after a MOV SS or POP SS instruction (for example: while debug
exceptions are blocked). Note the following:
•
Normally, if WRMSR clears BTF while RFLAGS.TF = 1 and with debug exceptions blocked, a single-step trap will
occur after WRMSR. A VMM emulating such an instruction should set the BS bit (see Table 24-4) in the pending
debug exceptions field before VM entry.
•
Normally, if WRMSR sets BTF while RFLAGS.TF = 1 and with debug exceptions blocked, neither a single-step
trap nor a taken-branch trap can occur after WRMSR. A VMM emulating such an instruction should clear the BS
bit (see Table 24-4) in the pending debug exceptions field before VM entry.
32.3
MEMORY VIRTUALIZATION
VMMs must control physical memory to ensure VM isolation and to remap guest physical addresses in host physical
address space for virtualization. Memory virtualization allows the VMM to enforce control of physical memory and
yet support guest OSs’ expectation to manage memory address translation.
32.3.1
Processor Operating Modes & Memory Virtualization
Memory virtualization is required to support guest execution in various processor operating modes. This includes:
protected mode with paging, protected mode with no paging, real-mode and any other transient execution modes.
VMX allows guest operation in protected-mode with paging enabled and in virtual-8086 mode (with paging
enabled) to support guest real-mode execution. Guest execution in transient operating modes (such as in real
mode with one or more segment limits greater than 64-KByte) must be emulated by the VMM.
Since VMX operation requires processor execution in protected mode with paging (through CR0 and CR4 fixed bits),
the VMM may utilize paging structures to support memory virtualization. To support guest real-mode execution,
the VMM may establish a simple flat page table for guest linear to host physical address mapping. Memory virtualization algorithms may also need to capture other guest operating conditions (such as guest performing A20M#
address masking) to map the resulting 20-bit effective guest physical addresses.
32.3.2
Guest & Host Physical Address Spaces
Memory virtualization provides guest software with contiguous guest physical address space starting zero and
extending to the maximum address supported by the guest virtual processor’s physical address width. The VMM
utilizes guest physical to host physical address mapping to locate all or portions of the guest physical address space
in host memory. The VMM is responsible for the policies and algorithms for this mapping which may take into
account the host system physical memory map and the virtualized physical memory map exposed to a guest by the
VMM. The memory virtualization algorithm needs to accommodate various guest memory uses (such as: accessing
DRAM, accessing memory-mapped registers of virtual devices or core logic functions and so forth). For example:
•
To support guest DRAM access, the VMM needs to map DRAM-backed guest physical addresses to host-DRAM
regions. The VMM also requires the guest to host memory mapping to be at page granularity.
•
Virtual devices (I/O devices or platform core logic) emulated by the VMM may claim specific regions in the guest
physical address space to locate memory-mapped registers. Guest access to these virtual registers may be
configured to cause page-fault induced VM-exits by marking these regions as always not present. The VMM
may handle these VM exits by invoking appropriate virtual device emulation code.
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VIRTUALIZATION OF SYSTEM RESOURCES
32.3.3
Virtualizing Virtual Memory by Brute Force
VMX provides the hardware features required to fully virtualize guest virtual memory accesses. VMX allows the
VMM to trap guest accesses to the PAT (Page Attribute Table) MSR and the MTRR (Memory Type Range Registers).
This control allows the VMM to virtualize the specific memory type of a guest memory. The VMM may control
caching by controlling the guest CR0.CRD and CR0.NW bits, as well as by trapping guest execution of the INVD
instruction. The VMM can trap guest CR3 loads and stores, and it may trap guest execution of INVLPG.
Because a VMM must retain control of physical memory, it must also retain control over the processor’s addresstranslation mechanisms. Specifically, this means that only the VMM can access CR3 (which contains the base of the
page directory) and can execute INVLPG (the only other instruction that directly manipulates the TLB).
At the same time that the VMM controls address translation, a guest operating system will also expect to perform
normal memory management functions. It will access CR3, execute INVLPG, and modify (what it believes to be)
page directories and page tables. Virtualization of address translation must tolerate and support guest attempts to
control address translation.
A simple-minded way to do this would be to ensure that all guest attempts to access address-translation hardware
trap to the VMM where such operations can be properly emulated. It must ensure that accesses to page directories
and page tables also get trapped. This may be done by protecting these in-memory structures with conventional
page-based protection. The VMM can do this because it can locate the page directory because its base address is
in CR3 and the VMM receives control on any change to CR3; it can locate the page tables because their base
addresses are in the page directory.
Such a straightforward approach is not necessarily desirable. Protection of the in-memory translation structures
may be cumbersome. The VMM may maintain these structures with different values (e.g., different page base
addresses) than guest software. This means that there must be traps on guest attempt to read these structures
and that the VMM must maintain, in auxiliary data structures, the values to return to these reads. There must also
be traps on modifications to these structures even if the translations they effect are never used. All this implies
considerable overhead that should be avoided.
32.3.4
Alternate Approach to Memory Virtualization
Guest software is allowed to freely modify the guest page-table hierarchy without causing traps to the VMM.
Because of this, the active page-table hierarchy might not always be consistent with the guest hierarchy. Any
potential problems arising from inconsistencies can be solved using techniques analogous to those used by the
processor and its TLB.
This section describes an alternative approach that allows guest software to freely access page directories and
page tables. Traps occur on CR3 accesses and executions of INVLPG. They also occur when necessary to ensure
that guest modifications to the translation structures actually take effect. The software mechanisms to support this
approach are collectively called virtual TLB. This is because they emulate the functionality of the processor’s physical translation look-aside buffer (TLB).
The basic idea behind the virtual TLB is similar to that behind the processor TLB. While the page-table hierarchy
defines the relationship between physical to linear address, it does not directly control the address translation of
each memory access. Instead, translation is controlled by the TLB, which is occasionally filled by the processor with
translations derived from the page-table hierarchy. With a virtual TLB, the page-table hierarchy established by
guest software (specifically, the guest operating system) does not control translation, either directly or indirectly.
Instead, translation is controlled by the processor (through its TLB) and by the VMM (through a page-table hierarchy that it maintains).
Specifically, the VMM maintains an alternative page-table hierarchy that effectively caches translations derived
from the hierarchy maintained by guest software. The remainder of this document refers to the former as the
active page-table hierarchy (because it is referenced by CR3 and may be used by the processor to load its TLB) and
the latter as the guest page-table hierarchy (because it is maintained by guest software). The entries in the active
hierarchy may resemble the corresponding entries in the guest hierarchy in some ways and may differ in others.
Guest software is allowed to freely modify the guest page-table hierarchy without causing VM exits to the VMM.
Because of this, the active page-table hierarchy might not always be consistent with the guest hierarchy. Any
potential problems arising from any inconsistencies can be solved using techniques analogous to those used by the
processor and its TLB. Note the following:
Vol. 3C 32-3
VIRTUALIZATION OF SYSTEM RESOURCES
•
Suppose the guest page-table hierarchy allows more access than active hierarchy (for example: there is a
translation for a linear address in the guest hierarchy but not in the active hierarchy); this is analogous to a
situation in which the TLB allows less access than the page-table hierarchy. If an access occurs that would be
allowed by the guest hierarchy but not the active one, a page fault occurs; this is analogous to a TLB miss. The
VMM gains control (as it handles all page faults) and can update the active page-table hierarchy appropriately;
this corresponds to a TLB fill.
•
Suppose the guest page-table hierarchy allows less access than the active hierarchy; this is analogous to a
situation in which the TLB allows more access than the page-table hierarchy. This situation can occur only if the
guest operating system has modified a page-table entry to reduce access (for example: by marking it notpresent). Because the older, more permissive translation may have been cached in the TLB, the processor is
architecturally permitted to use the older translation and allow more access. Thus, the VMM may (through the
active page-table hierarchy) also allow greater access. For the new, less permissive translation to take effect,
guest software should flush any older translations from the TLB either by executing INVLPG or by loading CR3.
Because both these operations will cause a trap to the VMM, the VMM will gain control and can remove from the
active page-table hierarchy the translations indicated by guest software (the translation of a specific linear
address for INVLPG or all translations for a load of CR3).
As noted previously, the processor reads the page-table hierarchy to cache translations in the TLB. It also writes to
the hierarchy to main the accessed (A) and dirty (D) bits in the PDEs and PTEs. The virtual TLB emulates this
behavior as follows:
•
When a page is accessed by guest software, the A bit in the corresponding PTE (or PDE for a 4-MByte page) in
the active page-table hierarchy will be set by the processor (the same is true for PDEs when active page tables
are accessed by the processor). For guest software to operate properly, the VMM should update the A bit in the
guest entry at this time. It can do this reliably if it keeps the active PTE (or PDE) marked not-present until it has
set the A bit in the guest entry.
•
When a page is written by guest software, the D bit in the corresponding PTE (or PDE for a 4-MByte page) in
the active page-table hierarchy will be set by the processor. For guest software to operate properly, the VMM
should update the D bit in the guest entry at this time. It can do this reliably if it keeps the active PTE (or PDE)
marked read-only until it has set the D bit in the guest entry. This solution is valid for guest software running at
privilege level 3; support for more privileged guest software is described in Section 32.3.5.
32.3.5
Details of Virtual TLB Operation
This section describes in more detail how a VMM could support a virtual TLB. It explains how an active page-table
hierarchy is initialized and how it is maintained in response to page faults, uses of INVLPG, and accesses to CR3.
The mechanisms described here are the minimum necessary. They may not result in the best performance.
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VIRTUALIZATION OF SYSTEM RESOURCES
"Virtual TLB"
Active Page-Table Hierarchy
Guest Page-Table Hierarchy
Guest
Active
F
CR3
TLB
refill on
TLB miss
set dirty
accessed
PT
F
PD
F
F
CR3
refill on
page fault
set accessed
and dirty bits
PT
PT
INVLPG
MOV to
CR3
task switch
F
PD
F
PT
F
F
INVLPG
MOV to CR3
task switch
PD = page directory
PT = page table
F = page frame
OM19040
Figure 32-1. Virtual TLB Scheme
As noted above, the VMM maintains an active page-table hierarchy for each virtual machine that it supports. It also
maintains, for each machine, values that the machine expects for control registers CR0, CR2, CR3, and CR4 (they
control address translation). These values are called the guest control registers.
In general, the VMM selects the physical-address space that is allocated to guest software. The term guest address
refers to an address installed by guest software in the guest CR3, in a guest PDE (as a page table base address or
a page base address), or in a guest PTE (as a page base address). While guest software considers these to be
specific physical addresses, the VMM may map them differently.
32.3.5.1
Initialization of Virtual TLB
To enable the Virtual TLB scheme, the VMCS must be set up to trigger VM exits on:
•
All writes to CR3 (the CR3-target count should be 0) or the paging-mode bits in CR0 and CR4 (using the CR0
and CR4 guest/host masks)
•
•
Page-fault (#PF) exceptions
Execution of INVLPG
When guest software first enables paging, the VMM creates an aligned 4-KByte active page directory that is invalid
(all entries marked not-present). This invalid directory is analogous to an empty TLB.
32.3.5.2
Response to Page Faults
Page faults can occur for a variety of reasons. In some cases, the page fault alerts the VMM to an inconsistency
between the active and guest page-table hierarchy. In such cases, the VMM can update the former and re-execute
the faulting instruction. In other cases, the hierarchies are already consistent and the fault should be handled by
the guest operating system. The VMM can detect this and use an established mechanism for raising a page fault to
guest software.
The VMM can handle a page fault by following these steps (The steps below assume the guest is operating in a
paging mode without PAE. Analogous steps to handle address translation using PAE or four-level paging mechaVol. 3C 32-5
VIRTUALIZATION OF SYSTEM RESOURCES
nisms can be derived by VMM developers according to the paging behavior defined in Chapter 3 of the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3A):
1. First consult the active PDE, which can be located using the upper 10 bits of the faulting address and the
current value of CR3. The active PDE is the source of the fault if it is marked not present or if its R/W bit and
U/S bits are inconsistent with the attempted guest access (the guest privilege level and the values of CR0.WP
and CR4.SMEP should also be taken into account).
2. If the active PDE is the source of the fault, consult the corresponding guest PDE using the same 10 bits from the
faulting address and the physical address that corresponds to the guest address in the guest CR3. If the guest
PDE would cause a page fault (for example: it is marked not present), then raise a page fault to the guest
operating system.
The following steps assume that the guest PDE would not have caused a page fault.
3. If the active PDE is the source of the fault and the guest PDE contains, as page-table base address (if PS = 0)
or page base address (PS = 1), a guest address that the VMM has chosen not to support; then raise a machine
check (or some other abort) to the guest operating system.
The following steps assume that the guest address in the guest PDE is supported for the virtual machine.
4. If the active PDE is marked not-present, then set the active PDE to correspond to guest PDE as follows:
a. If the active PDE contains a page-table base address (if PS = 0), then allocate an aligned 4-KByte active
page table marked completely invalid and set the page-table base address in the active PDE to be the
physical address of the newly allocated page table.
b. If the active PDE contains a page base address (if PS = 1), then set the page base address in the active PDE
to be the physical page base address that corresponds to the guest address in the guest PDE.
c.
Set the P, U/S, and PS bits in the active PDE to be identical to those in the guest PDE.
d. Set the PWT, PCD, and G bits according to the policy of the VMM.
e. Set A = 1 in the guest PDE.
f.
If D = 1 in the guest PDE or PS = 0 (meaning that this PDE refers to a page table), then set the R/W bit in
the active PDE as in the guest PDE.
g. If D = 0 in the guest PDE, PS = 1 (this is a 4-MByte page), and the attempted access is a write; then set
R/W in the active PDE as in the guest PDE and set D = 1 in the guest PDE.
h. If D = 0 in the guest PDE, PS = 1, and the attempted access is not a write; then set R/W = 0 in the active
PDE.
i.
After modifying the active PDE, re-execute the faulting instruction.
The remaining steps assume that the active PDE is already marked present.
5. If the active PDE is the source of the fault, the active PDE refers to a 4-MByte page (PS = 1), the attempted
access is a write; D = 0 in the guest PDE, and the active PDE has caused a fault solely because it has R/W = 0;
then set R/W in the active PDE as in the guest PDE; set D = 1 in the guest PDE, and re-execute the faulting
instruction.
6. If the active PDE is the source of the fault and none of the above cases apply, then raise a page fault of the
guest operating system.
The remaining steps assume that the source of the original page fault is not the active PDE.
NOTE
It is possible that the active PDE might be causing a fault even though the guest PDE would not.
However, this can happen only if the guest operating system increased access in the guest PDE and
did not take action to ensure that older translations were flushed from the TLB. Such translations
might have caused a page fault if the guest software were running on bare hardware.
7. If the active PDE refers to a 4-MByte page (PS = 1) but is not the source of the fault, then the fault resulted
from an inconsistency between the active page-table hierarchy and the processor’s TLB. Since the transition to
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VIRTUALIZATION OF SYSTEM RESOURCES
the VMM caused an address-space change and flushed the processor’s TLB, the VMM can simply re-execute the
faulting instruction.
The remaining steps assume that PS = 0 in the active and guest PDEs.
8. Consult the active PTE, which can be located using the next 10 bits of the faulting address (bits 21–12) and the
physical page-table base address in the active PDE. The active PTE is the source of the fault if it is marked notpresent or if its R/W bit and U/S bits are inconsistent with the attempted guest access (the guest privilege level
and the values of CR0.WP and CR4.SMEP should also be taken into account).
9. If the active PTE is not the source of the fault, then the fault has resulted from an inconsistency between the
active page-table hierarchy and the processor’s TLB. Since the transition to the VMM caused an address-space
change and flushed the processor’s TLB, the VMM simply re-executes the faulting instruction.
The remaining steps assume that the active PTE is the source of the fault.
10. Consult the corresponding guest PTE using the same 10 bits from the faulting address and the physical address
that correspond to the guest page-table base address in the guest PDE. If the guest PTE would cause a page
fault (it is marked not-present), the raise a page fault to the guest operating system.
The following steps assume that the guest PTE would not have caused a page fault.
11. If the guest PTE contains, as page base address, a physical address that is not valid for the virtual machine
being supported; then raise a machine check (or some other abort) to the guest operating system.
The following steps assume that the address in the guest PTE is valid for the virtual machine.
12. If the active PTE is marked not-present, then set the active PTE to correspond to guest PTE:
a. Set the page base address in the active PTE to be the physical address that corresponds to the guest page
base address in the guest PTE.
b. Set the P, U/S, and PS bits in the active PTE to be identical to those in the guest PTE.
c.
Set the PWT, PCD, and G bits according to the policy of the VMM.
d. Set A = 1 in the guest PTE.
e. If D = 1 in the guest PTE, then set the R/W bit in the active PTE as in the guest PTE.
f.
If D = 0 in the guest PTE and the attempted access is a write, then set R/W in the active PTE as in the guest
PTE and set D = 1 in the guest PTE.
g. If D = 0 in the guest PTE and the attempted access is not a write, then set R/W = 0 in the active PTE.
h. After modifying the active PTE, re-execute the faulting instruction.
The remaining steps assume that the active PTE is already marked present.
13. If the attempted access is a write, D = 0 (not dirty) in the guest PTE and the active PTE has caused a fault
solely because it has R/W = 0 (read-only); then set R/W in the active PTE as in the guest PTE, set D = 1 in the
guest PTE and re-execute the faulting instruction.
14. If none of the above cases apply, then raise a page fault of the guest operating system.
32.3.5.3
Response to Uses of INVLPG
Operating-systems can use INVLPG to flush entries from the TLB. This instruction takes a linear address as an
operand and software expects any cached translations for the address to be flushed. A VMM should set the
processor-based VM-execution control “INVLPG exiting” to 1 so that any attempts by a privileged guest to execute
INVLPG will trap to the VMM. The VMM can then modify the active page-table hierarchy to emulate the desired
effect of the INVLPG.
The following steps are performed. Note that these steps are performed only if the guest invocation of INVLPG
would not fault and only if the guest software is running at privilege level 0:
1. Locate the relevant active PDE using the upper 10 bits of the operand address and the current value of CR3. If
the PDE refers to a 4-MByte page (PS = 1), then set P = 0 in the PDE.
2. If the PDE is marked present and refers to a page table (PS = 0), locate the relevant active PTE using the next
10 bits of the operand address (bits 21–12) and the page-table base address in the PDE. Set P = 0 in the PTE.
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VIRTUALIZATION OF SYSTEM RESOURCES
Examine all PTEs in the page table; if they are now all marked not-present, de-allocate the page table and set
P = 0 in the PDE (this step may be optional).
32.3.5.4
Response to CR3 Writes
A guest operating system may attempt to write to CR3. Any write to CR3 implies a TLB flush and a possible page
table change. The following steps are performed:
1. The VMM notes the new CR3 value (used later to walk guest page tables) and emulates the write.
2. The VMM allocates a new PD page, with all invalid entries.
3. The VMM sets actual processor CR3 register to point to the new PD page.
The VMM may, at this point, speculatively fill in VTLB mappings for performance reasons.
32.4
MICROCODE UPDATE FACILITY
The microcode code update facility may be invoked at various points during the operation of a platform. Typically,
the BIOS invokes the facility on all processors during the BIOS boot process. This is sufficient to boot the BIOS and
operating system. As a microcode update more current than the system BIOS may be available, system software
should provide another mechanism for invoking the microcode update facility. The implications of the microcode
update mechanism on the design of the VMM are described in this section.
NOTE
Microcode updates must not be performed during VMX non-root operation. Updates performed in
VMX non-root operation may result in unpredictable system behavior.
32.4.1
Early Load of Microcode Updates
The microcode update facility may be invoked early in the VMM or guest OS boot process. Loading the microcode
update early provides the opportunity to correct errata affecting the boot process but the technique generally
requires a reboot of the software.
A microcode update may be loaded from the OS or VMM image loader. Typically, such image loaders do not run on
every logical processor, so this method effects only one logical processor. Later in the VMM or OS boot process,
after bringing all application processors on-line, the VMM or OS needs to invoke the microcode update facility for all
application processors.
Depending on the order of the VMM and the guest OS boot, the microcode update facility may be invoked by the
VMM or the guest OS. For example, if the guest OS boots first and then loads the VMM, the guest OS may invoke
the microcode update facility on all the logical processors. If a VMM boots before its guests, then the VMM may
invoke the microcode update facility during its boot process. In both cases, the VMM or OS should invoke the microcode update facilities soon after performing the multiprocessor startup.
In the early load scenario, microcode updates may be contained in the VMM or OS image or, the VMM or OS may
manage a separate database or file of microcode updates. Maintaining a separate microcode update image database has the advantage of reducing the number of required VMM or OS releases as a result of microcode update
releases.
32.4.2
Late Load of Microcode Updates
A microcode update may be loaded during normal system operation. This allows system software to activate the
microcode update at anytime without requiring a system reboot. This scenario does not allow the microcode update
to correct errata which affect the processor’s boot process but does allow high-availability systems to activate
microcode updates without interrupting the availability of the system. In this late load scenario, either the VMM or
a designated guest may load the microcode update. If the guest is loading the microcode update, the VMM must
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make sure that the entire guest memory buffer (which contains the microcode update image) will not cause a page
fault when accessed.
If the VMM loads the microcode update, then the VMM must have access to the current set of microcode updates.
These updates could be part of the VMM image or could be contained in a separate microcode update image database (for example: a database file on disk or in memory). Again, maintaining a separate microcode update image
database has the advantage of reducing the number of required VMM or OS releases as a result of microcode
update releases.
The VMM may wish to prevent a guest from loading a microcode update or may wish to support the microcode
update requested by a guest using emulation (without actually loading the microcode update). To prevent microcode update loading, the VMM may return a microcode update signature value greater than the value of
IA32_BIOS_SIGN_ID MSR. A well behaved guest will not attempt to load an older microcode update. The VMM may
also drop the guest attempts to write to IA32_BIOS_UPDT_TRIG MSR, preventing the guest from loading any
microcode updates. Later, when the guest queries IA32_BIOS_SIGN_ID MSR, the VMM could emulate the microcode update signature that the guest expects.
In general, loading a microcode update later will limit guest software’s visibility of features that may be enhanced
by a microcode update.
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32-10 Vol. 3C
CHAPTER 33
HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITOR
33.1
OVERVIEW
This chapter describes what a VMM must consider when handling exceptions, interrupts, error conditions, and transitions between activity states.
33.2
INTERRUPT HANDLING IN VMX OPERATION
The following bullets summarize VMX support for handling interrupts:
•
Control of processor exceptions. The VMM can get control on specific guest exceptions through the
exception-bitmap in the guest controlling VMCS. The exception bitmap is a 32-bit field that allows the VMM to
specify processor behavior on specific exceptions (including traps, faults, and aborts). Setting a specific bit in
the exception bitmap implies VM exits will be generated when the corresponding exception occurs. Any
exceptions that are programmed not to cause VM exits are delivered directly to the guest through the guest
IDT. The exception bitmap also controls execution of relevant instructions such as BOUND, INTO and INT3. VM
exits on page-faults are treated in such a way the page-fault error code is qualified through the page-faulterror-code mask and match fields in the VMCS.
•
Control over triple faults. If a fault occurs while attempting to call a double-fault handler in the guest and
that fault is not configured to cause a VM exit in the exception bitmap, the resulting triple fault causes a
VM exit.
•
Control of external interrupts. VMX allows both host and guest control of external interrupts through the
“external-interrupt exiting” VM execution control. If the control is 0, external-interrupts do not cause VM exits
and the interrupt delivery is masked by the guest programmed RFLAGS.IF value.1 If the control is 1, externalinterrupts causes VM exits and are not masked by RFLAGS.IF. The VMM can identify VM exits due to external
interrupts by checking the exit reason for an “external interrupt” (value = 1).
•
Control of other events. There is a pin-based VM-execution control that controls system behavior (exit or noexit) for NMI events. Most VMM usages will need handling of NMI external events in the VMM and hence will
specify host control of these events.
Some processors also support a pin-based VM-execution control called “virtual NMIs.” When this control is set,
NMIs cause VM exits, but the processor tracks guest readiness for virtual NMIs. This control interacts with the
“NMI-window exiting” VM-execution control (see below).
INIT and SIPI events always cause VM exits.
•
Acknowledge interrupt on exit. The “acknowledge interrupt on exit” VM-exit control in the controlling VMCS
controls processor behavior for external interrupt acknowledgement. If the control is 1, the processor acknowledges the interrupt controller to acquire the interrupt vector upon VM exit, and stores the vector in the VM-exit
interruption-information field. If the control is 0, the external interrupt is not acknowledged during VM exit.
Since RFLAGS.IF is automatically cleared on VM exits due to external interrupts, VMM re-enabling of interrupts
(setting RFLAGS.IF = 1) initiates the external interrupt acknowledgement and vectoring of the external
interrupt through the monitor/host IDT.
•
Event-masking Support. VMX captures the masking conditions of specific events while in VMX non-root
operation through the interruptibility-state field in the guest-state area of the VMCS.
This feature allows proper virtualization of various interrupt blocking states, such as: (a) blocking of external
interrupts for the instruction following STI; (b) blocking of interrupts for the instruction following a MOV-SS or
POP-SS instruction; (c) SMI blocking of subsequent SMIs until the next execution of RSM; and (d) NMI/SMI
blocking of NMIs until the next execution of IRET or RSM.
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX operation also support Intel 64 architecture. For processors that do not support Intel 64 architecture, this notation refers to the 32-bit
forms of those registers (EAX, EIP, ESP, EFLAGS, etc.).
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HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITOR
INIT and SIPI events are treated specially. INIT assertions are always blocked in VMX root operation and while
in SMM, and unblocked otherwise. SIPI events are always blocked in VMX root operation.
The interruptibility state is loaded from the VMCS guest-state area on every VM entry and saved into the VMCS
on every VM exit.
•
Event injection. VMX operation allows injecting interruptions to a guest virtual machine through the use of
VM-entry interrupt-information field in VMCS. Injectable interruptions include external interrupts, NMI,
processor exceptions, software generated interrupts, and software traps. If the interrupt-information field
indicates a valid interrupt, exception or trap event upon the next VM entry; the processor will use the
information in the field to vector a virtual interruption through the guest IDT after all guest state and MSRs are
loaded. Delivery through the guest IDT emulates vectoring in non-VMX operation by doing the normal privilege
checks and pushing appropriate entries to the guest stack (entries may include RFLAGS, EIP and exception
error code). A VMM with host control of NMI and external interrupts can use the event-injection facility to
forward virtual interruptions to various guest virtual machines.
•
Interrupt-window exiting. When set to 1, the “interrupt-window exiting” VM-execution control (Section
24.6.2) causes VM exits when guest RFLAGS.IF is 1 and no other conditions block external interrupts. A VM exit
occurs at the beginning of any instruction at which RFLAGS.IF = 1 and on which the interruptibility state of the
guest would allow delivery of an interrupt. For example: when the guest executes an STI instruction,
RFLAGS = 1, and if at the completion of next instruction the interruptibility state masking due to STI is
removed; a VM exit occurs if the “interrupt-window exiting” VM-execution control is 1. This feature allows a
VMM to queue a virtual interrupt to the guest when the guest is not in an interruptible state. The VMM can set
the “interrupt-window exiting” VM-execution control for the guest and depend on a VM exit to know when the
guest becomes interruptible (and, therefore, when it can inject a virtual interrupt). The VMM can detect such
VM exits by checking for the basic exit reason “interrupt-window” (value = 7). If this feature is not used, the
VMM will need to poll and check the interruptibility state of the guest to deliver virtual interrupts.
•
NMI-window exiting. If the “virtual NMIs” VM-execution is set, the processor tracks virtual-NMI blocking.
The “NMI-window exiting” VM-execution control (Section 24.6.2) causes VM exits when there is no virtual-NMI
blocking. For example, after execution of the IRET instruction, a VM exit occurs if the “NMI-window exiting” VMexecution control is 1. This feature allows a VMM to queue a virtual NMI to a guest when the guest is not ready
to receive NMIs. The VMM can set the “NMI-window exiting” VM-execution control for the guest and depend on
a VM exit to know when the guest becomes ready for NMIs (and, therefore, when it can inject a virtual NMI).
The VMM can detect such VM exits by checking for the basic exit reason “NMI window” (value = 8). If this
feature is not used, the VMM will need to poll and check the interruptibility state of the guest to deliver virtual
NMIs.
•
VM-exit information. The VM-exit information fields provide details on VM exits due to exceptions and
interrupts. This information is provided through the exit-qualification, VM-exit-interruption-information,
instruction-length and interruption-error-code fields. Also, for VM exits that occur in the course of vectoring
through the guest IDT, information about the event that was being vectored through the guest IDT is provided
in the IDT-vectoring-information and IDT-vectoring-error-code fields. These information fields allow the VMM to
identify the exception cause and to handle it properly.
33.3
EXTERNAL INTERRUPT VIRTUALIZATION
VMX operation allows both host and guest control of external interrupts. While guest control of external interrupts
might be suitable for partitioned usages (different CPU cores/threads and I/O devices partitioned to independent
virtual machines), most VMMs built upon VMX are expected to utilize host control of external interrupts. The rest of
this section describes a general host-controlled interrupt virtualization architecture for standard PC platforms
through the use of VMX supported features.
With host control of external interrupts, the VMM (or the host OS in a hosted VMM model) manages the physical
interrupt controllers in the platform and the interrupts generated through them. The VMM exposes softwareemulated virtual interrupt controller devices (such as PIC and APIC) to each guest virtual machine instance.
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33.3.1
Virtualization of Interrupt Vector Space
The Intel 64 and IA-32 architectures use 8-bit vectors of which 224 (20H – FFH) are available for external interrupts. Vectors are used to select the appropriate entry in the interrupt descriptor table (IDT). VMX operation allows
each guest to control its own IDT. Host vectors refer to vectors delivered by the platform to the processor during
the interrupt acknowledgement cycle. Guest vectors refer to vectors programmed by a guest to select an entry in
its guest IDT. Depending on the I/O resource management models supported by the VMM design, the guest vector
space may or may not overlap with the underlying host vector space.
•
Interrupts from virtual devices: Guest vector numbers for virtual interrupts delivered to guests on behalf of
emulated virtual devices have no direct relation to the host vector numbers of interrupts from physical devices
on which they are emulated. A guest-vector assigned for a virtual device by the guest operating environment
is saved by the VMM and utilized when injecting virtual interrupts on behalf of the virtual device.
•
Interrupts from assigned physical devices: Hardware support for I/O device assignment allows physical I/O
devices in the host platform to be assigned (direct-mapped) to VMs. Guest vectors for interrupts from directmapped physical devices take up equivalent space from the host vector space, and require the VMM to perform
host-vector to guest-vector mapping for interrupts.
Figure 33-1 illustrates the functional relationship between host external interrupts and guest virtual external interrupts. Device A is owned by the host and generates external interrupts with host vector X. The host IDT is set up
such that the interrupt service routine (ISR) for device driver A is hooked to host vector X as normal. VMM
emulates (over device A) virtual device C in software which generates virtual interrupts to the VM with guest
expected vector P. Device B is assigned to a VM and generates external interrupts with host vector Y. The host IDT
is programmed to hook the VMM interrupt service routine (ISR) for assigned devices for vector Y, and the VMM
handler injects virtual interrupt with guest vector Q to the VM. The guest operating system programs the guest to
hook appropriate guest driver’s ISR to vectors P and Q.
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HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITOR
VM
Device Driver C
Guest IDT
Device Driver B
Guest
Vector P
Guest
Vector Q
Guest IDTR
Virtual Interrupt
Virtual Interrupt
Virtual Device C
Emulation
Host IDT
Monitor Handler
Platform Interrupt
Vector Y
Host
Virtual Machine Monitor (VMM)
Host
Host IDTR
Vector X
Device Driver A
Platform Interrupt
Hardware
Device A
Device B
OM19041
Figure 33-1. Host External Interrupts and Guest Virtual Interrupts
33.3.2
Control of Platform Interrupts
To meet the interrupt virtualization requirements, the VMM needs to take ownership of the physical interrupts and
the various interrupt controllers in the platform. VMM control of physical interrupts may be enabled through the
host-control settings of the “external-interrupt exiting” VM-execution control. To take ownership of the platform
interrupt controllers, the VMM needs to expose the virtual interrupt controller devices to the virtual machines and
restrict guest access to the platform interrupt controllers.
Intel 64 and IA-32 platforms can support three types of external interrupt control mechanisms: Programmable
Interrupt Controllers (PIC), Advanced Programmable Interrupt Controllers (APIC), and Message Signaled Interrupts (MSI). The following sections provide information on the virtualization of each of these mechanisms.
33.3.2.1
PIC Virtualization
Typical PIC-enabled platform implementations support dual 8259 interrupt controllers cascaded as master and
slave controllers. They supporting up to 15 possible interrupt inputs. The 8259 controllers are programmed
through initialization command words (ICWx) and operation command words (OCWx) accessed through specific
I/O ports. The various interrupt line states are captured in the PIC through interrupt requests, interrupt service
routines and interrupt mask registers.
Guest access to the PIC I/O ports can be restricted by activating I/O bitmaps in the guest controlling-VMCS (activate-I/O-bitmap bit in VM-execution control field set to 1) and pointing the I/O-bitmap physical addresses to valid
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bitmap regions. Bits corresponding to the PIC I/O ports can be cleared to cause a VM exit on guest access to these
ports.
If the VMM is not supporting direct access to any I/O ports from a guest, it can set the unconditional-I/O-exiting in
the VM-execution control field instead of activating I/O bitmaps. The exit-reason field in VM-exit information allows
identification of VM exits due to I/O access and can provide an exit-qualification to identify details about the guest
I/O operation that caused the VM exit.
The VMM PIC virtualization needs to emulate the platform PIC functionality including interrupt priority, mask,
request and service states, and specific guest programmed modes of PIC operation.
33.3.2.2
xAPIC Virtualization
Most modern Intel 64 and IA-32 platforms include support for an APIC. While the standard PIC is intended for use
on uniprocessor systems, APIC can be used in either uniprocessor or multi-processor systems.
APIC based interrupt control consists of two physical components: the interrupt acceptance unit (Local APIC) which
is integrated with the processor, and the interrupt delivery unit (I/O APIC) which is part of the I/O subsystem. APIC
virtualization involves protecting the platform’s local and I/O APICs and emulating them for the guest.
33.3.2.3
Local APIC Virtualization
The local APIC is responsible for the local interrupt sources, interrupt acceptance, dispensing interrupts to the
logical processor, and generating inter-processor interrupts. Software interacts with the local APIC by reading and
writing its memory-mapped registers residing within a 4-KByte uncached memory region with base address stored
in the IA32_APIC_BASE MSR. Since the local APIC registers are memory-mapped, the VMM can utilize memory
virtualization techniques (such as page-table virtualization) to trap guest accesses to the page frame hosting the
virtual local APIC registers.
Local APIC virtualization in the VMM needs to emulate the various local APIC operations and registers, such as:
APIC identification/format registers, the local vector table (LVT), the interrupt command register (ICR), interrupt
capture registers (TMR, IRR and ISR), task and processor priority registers (TPR, PPR), the EOI register and the
APIC-timer register. Since local APICs are designed to operate with non-specific EOI, local APIC emulation also
needs to emulate broadcast of EOI to the guest’s virtual I/O APICs for level triggered virtual interrupts.
A local APIC allows interrupt masking at two levels: (1) mask bit in the local vector table entry for local interrupts
and (2) raising processor priority through the TPR registers for masking lower priority external interrupts. The VMM
needs to comprehend these virtual local APIC mask settings as programmed by the guest in addition to the guest
virtual processor interruptibility state (when injecting APIC routed external virtual interrupts to a guest VM).
VMX provides several features which help the VMM to virtualize the local APIC. These features allow many of guest
TPR accesses (using CR8 only) to occur without VM exits to the VMM:
•
The VMCS contains a “virtual-APIC address” field. This 64-bit field is the physical address of the 4-KByte virtual
APIC page (4-KByte aligned). The virtual-APIC page contains a TPR shadow, which is accessed by the MOV CR8
instruction. The TPR shadow comprises bits 7:4 in byte 80H of the virtual-APIC page.
•
The TPR threshold: bits 3:0 of this 32-bit field determine the threshold below which the TPR shadow cannot fall.
A VM exit will occur after an execution of MOV CR8 that reduces the TPR shadow below this value.
•
The processor-based VM-execution controls field contains a “use TPR shadow” bit and a “CR8-store exiting” bit.
If the “use TPR shadow” VM-execution control is 1 and the “CR8-store exiting” VM-execution control is 0, then
a MOV from CR8 reads from the TPR shadow. If the “CR8-store exiting” VM-execution control is 1, then MOV
from CR8 causes a VM exit; the “use TPR shadow” VM-execution control is ignored in this case.
•
The processor-based VM-execution controls field contains a “CR8-load exiting” bit. If the “use TPR shadow”
VM-execution control is set and the “CR8-load exiting” VM-execution control is clear, then MOV to CR8 writes to
the “TPR shadow”. A VM exit will occur after this write if the value written is below the TPR threshold. If the
“CR8-load exiting” VM-execution control is set, then MOV to CR8 causes a VM exit; the “use TPR shadow” VMexecution control is ignored in this case.
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33.3.2.4
I/O APIC Virtualization
The I/O APIC registers are typically mapped to a 1 MByte region where each I/O APIC is allocated a 4K address
window within this range. The VMM may utilize physical memory virtualization to trap guest accesses to the virtual
I/O APIC memory-mapped registers. The I/O APIC virtualization needs to emulate the various I/O APIC operations
and registers such as identification/version registers, indirect-I/O-access registers, EOI register, and the I/O redirection table. I/O APIC virtualization also need to emulate various redirection table entry settings such as delivery
mode, destination mode, delivery status, polarity, masking, and trigger mode programmed by the guest and track
remote-IRR state on guest EOI writes to various virtual local APICs.
33.3.2.5
Virtualization of Message Signaled Interrupts
The PCI Local Bus Specification (Rev. 2.2) introduces the concept of message signaled interrupts (MSI). MSI enable
PCI devices to request service by writing a system-specified message to a system specified address. The transaction address specifies the message destination while the transaction data specifies the interrupt vector, trigger
mode and delivery mode. System software is expected to configure the message data and address during MSI
device configuration, allocating one or more no-shared messages to MSI capable devices. Chapter 10, “Advanced
Programmable Interrupt Controller (APIC),” specifies the MSI message address and data register formats to be
followed on Intel 64 and IA-32 platforms. While MSI is optional for conventional PCI devices, it is the preferred
interrupt mechanism for PCI-Express devices.
Since the MSI address and data are configured through PCI configuration space, to control these physical interrupts
the VMM needs to assume ownership of PCI configuration space. This allows the VMM to capture the guest configuration of message address and data for MSI-capable virtual and assigned guest devices. PCI configuration transactions on PC-compatible systems are generated by software through two different methods:
1. The standard CONFIG_ADDRESS/CONFIG_DATA register mechanism (CFCH/CF8H ports) as defined in the PCI
Local Bus Specification.
2. The enhanced flat memory-mapped (MEMCFG) configuration mechanism as defined in the PCI-Express Base
Specification (Rev. 1.0a.).
The CFCH/CF8H configuration access from guests can be trapped by the VMM through use of I/O-bitmap VMexecution controls. The memory-mapped PCI-Express MEMCFG guest configuration accesses can be trapped by
VMM through physical memory virtualization.
33.3.3
Examples of Handling of External Interrupts
The following sections illustrate interrupt processing in a VMM (when used to support the external interrupt virtualization requirements).
33.3.3.1
Guest Setup
The VMM sets up the guest to cause a VM exit to the VMM on external interrupts. This is done by setting the
“external-interrupt exiting” VM-execution control in the guest controlling-VMCS.
33.3.3.2
Processor Treatment of External Interrupt
Interrupts are automatically masked by hardware in the processor on VM exit by clearing RFLAGS.IF. The exitreason field in VMCS is set to 1 to indicate an external interrupt as the exit reason.
If the VMM is utilizing the acknowledge-on-exit feature (by setting the “acknowledge interrupt on exit” VM-exit
control), the processor acknowledges the interrupt, retrieves the host vector, and saves the interrupt in the VMexit-interruption-information field (in the VM-exit information region of the VMCS) before transitioning control to
the VMM.
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33.3.3.3
Processing of External Interrupts by VMM
Upon VM exit, the VMM can determine the exit cause of an external interrupt by checking the exit-reason field
(value = 1) in VMCS. If the acknowledge-interrupt-on-exit control (see Section 24.7.1) is enabled, the VMM can
use the saved host vector (in the exit-interruption-information field) to switch to the appropriate interrupt handler.
If the “acknowledge interrupt on exit” VM-exit control is 0, the VMM may re-enable interrupts (by setting
RFLAGS.IF) to allow vectoring of external interrupts through the monitor/host IDT.
The following steps may need to be performed by the VMM to process an external interrupt:
•
Host Owned I/O Devices: For host-owned I/O devices, the interrupting device is owned by the VMM (or
hosting OS in a hosted VMM). In this model, the interrupt service routine in the VMM/host driver is invoked and,
upon ISR completion, the appropriate write sequences (TPR updates, EOI etc.) to respective interrupt
controllers are performed as normal. If the work completion indicated by the driver implies virtual device
activity, the VMM runs the virtual device emulation. Depending on the device class, physical device activity
could imply activity by multiple virtual devices mapped over the device. For each affected virtual device, the
VMM injects a virtual external interrupt event to respective guest virtual machines. The guest driver interacts
with the emulated virtual device to process the virtual interrupt. The interrupt controller emulation in the VMM
supports various guest accesses to the VMM’s virtual interrupt controller.
•
Guest Assigned I/O Devices: For assigned I/O devices, either the VMM uses a software proxy or it can
directly map the physical device to the assigned VM. In both cases, servicing of the interrupt condition on the
physical device is initiated by the driver running inside the guest VM. With host control of external interrupts,
interrupts from assigned physical devices cause VM exits to the VMM and vectoring through the host IDT to the
registered VMM interrupt handler. To unblock delivery of other low priority platform interrupts, the VMM
interrupt handler must mask the interrupt source (for level triggered interrupts) and issue the appropriate EOI
write sequences.
Once the physical interrupt source is masked and the platform EOI generated, the VMM can map the host vector to
its corresponding guest vector to inject the virtual interrupt into the assigned VM. The guest software does EOI
write sequences to its virtual interrupt controller after completing interrupt processing. For level triggered interrupts, these EOI writes to the virtual interrupt controller may be trapped by the VMM which may in turn unmask
the previously masked interrupt source.
33.3.3.4
Generation of Virtual Interrupt Events by VMM
The following provides some of the general steps that need to be taken by VMM designs when generating virtual
interrupts:
1. Check virtual processor interruptibility state. The virtual processor interruptibility state is reflected in the guest
RFLAGS.IF flag and the processor interruptibility-state saved in the guest state area of the controlling-VMCS. If
RFLAGS.IF is set and the interruptibility state indicates readiness to take external interrupts (STI-masking and
MOV-SS/POP-SS-masking bits are clear), the guest virtual processor is ready to take external interrupts. If the
VMM design supports non-active guest sleep states, the VMM needs to make sure the current guest sleep state
allows injection of external interrupt events.
2. If the guest virtual processor state is currently not interruptible, a VMM may utilize the “interrupt-window
exiting” VM-execution to notify the VMM (through a VM exit) when the virtual processor state changes to interruptible state.
3. Check the virtual interrupt controller state. If the guest VM exposes a virtual local APIC, the current value of its
processor priority register specifies if guest software allows dispensing an external virtual interrupt with a
specific priority to the virtual processor. If the virtual interrupt is routed through the local vector table (LVT)
entry of the local APIC, the mask bits in the corresponding LVT entry specifies if the interrupt is currently
masked. Similarly, the virtual interrupt controller’s current mask (IO-APIC or PIC) and priority settings reflect
guest state to accept specific external interrupts. The VMM needs to check both the virtual processor and
interrupt controller states to verify its guest interruptibility state. If the guest is currently interruptible, the
VMM can inject the virtual interrupt. If the current guest state does not allow injecting a virtual interrupt, the
interrupt needs to be queued by the VMM until it can be delivered.
4. Prioritize the use of VM-entry event injection. A VMM may use VM-entry event injection to deliver various
virtual events (such as external interrupts, exceptions, traps, and so forth). VMM designs may prioritize use of
virtual-interrupt injection between these event types. Since each VM entry allows injection of one event,
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depending on the VMM event priority policies, the VMM may need to queue the external virtual interrupt if a
higher priority event is to be delivered on the next VM entry. Since the VMM has masked this particular interrupt
source (if it was level triggered) and done EOI to the platform interrupt controller, other platform interrupts can
be serviced while this virtual interrupt event is queued for later delivery to the VM.
5. Update the virtual interrupt controller state. When the above checks have passed, before generating the virtual
interrupt to the guest, the VMM updates the virtual interrupt controller state (Local-APIC, IO-APIC and/or PIC)
to reflect assertion of the virtual interrupt. This involves updating the various interrupt capture registers, and
priority registers as done by the respective hardware interrupt controllers. Updating the virtual interrupt
controller state is required for proper interrupt event processing by guest software.
6. Inject the virtual interrupt on VM entry. To inject an external virtual interrupt to a guest VM, the VMM sets up
the VM-entry interruption-information field in the guest controlling-VMCS before entry to guest using
VMRESUME. Upon VM entry, the processor will use this vector to access the gate in guest’s IDT and the value of
RFLAGS and EIP in guest-state area of controlling-VMCS is pushed on the guest stack. If the guest RFLAGS.IF
is clear, the STI-masking bit is set, or the MOV- SS/POP-SS-masking bit is set, the VM entry will fail and the
processor will load state from the host-state area of the working VMCS as if a VM exit had occurred (see Section
26.7).
33.4
ERROR HANDLING BY VMM
Error conditions may occur during VM entries and VM exits and a few other situations. This section describes how
VMM should handle these error conditions, including triple faults and machine-check exceptions.
33.4.1
VM-Exit Failures
All VM exits load processor state from the host-state area of the VMCS that was the controlling VMCS before the VM
exit. This state is checked for consistency while being loaded. Because the host-state is checked on VM entry, these
checks will generally succeed. Failure is possible only if host software is incorrect or if VMCS data in the VMCS
region in memory has been written by guest software (or by I/O DMA) since the last VM entry. VM exits may fail for
the following reasons:
•
•
•
There was a failure on storing guest MSRs.
•
•
There was a failure on loading host MSRs.
There was failure in loading a PDPTR.
The controlling VMCS has been corrupted (through writes to the corresponding VMCS region) in such a way that
the implementation cannot complete the VM exit.
A machine-check event occurred.
If one of these problems occurs on a VM exit, a VMX abort results.
33.4.2
Machine-Check Considerations
The following sequence determine how machine-check events are handled during VMXON, VMXOFF, VM entries,
and VM exits:
•
VMXOFF and VMXON:
If a machine-check event occurs during VMXOFF or VMXON and CR4.MCE = 1, a machine-check exception
(#MC) is generated. If CR4.MCE = 0, the processor goes to shutdown state.
•
VM entry:
If a machine-check event occurs during VM entry, one of the following three treatments must occur:
a. Normal delivery before VM entry. If CR4.MCE = 1 before VM entry, delivery of a machine-check exception
(#MC) through the host IDT occurs. If CR4.MCE = 0, the processor goes to shutdown state.
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HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITOR
b. Normal delivery after VM entry. If CR4.MCE = 1 after VM entry, delivery of a machine-check exception
(#MC) through the guest IDT occurs (alternatively, this exception may cause a VM exit). If CR4.MCE = 0,
the processor goes to shutdown state.
c.
Load state from the host-state area of the working VMCS as if a VM exit had occurred (see Section 26.7).
The basic exit reason will be “VM-entry failure due to machine-check event.”
If the machine-check event occurs after any guest state has been loaded, option a above will not be used; it
may be used if the machine-check event occurs while checking host state and VMX controls (or while reporting
a failure due to such checks). An implementation may use option b only if all guest state has been loaded
properly.
•
VM exit:
If a machine-check event occurs during VM exit, one of the following three treatments must occur:
a. Normal delivery before VM exit. If CR4.MCE = 1 before the VM exit, delivery of a machine-check exception
(#MC) through the guest IDT (alternatively, this may cause a VM exit). If CR4.MCE = 0, the processor goes
to shutdown state.
b. Normal delivery after VM exit. If CR4.MCE = 1 after the VM exit, delivery of a machine-check exception
(#MC) through the host IDT. If CR4.MCE = 0, the processor goes to shutdown state.
c.
Fail the VM exit. If the VM exit is to VMX root operation, a VMX abort will result; it will block events as done
normally in VMX abort. The VMX abort indicator will show that a machine-check event induced the abort
operation.
If a machine-check event is induced by an action in VMX non-root operation before any determination is made
that the inducing action may cause a VM exit, that machine-check event should be considered as happening
during guest execution in VMX non-root operation. This is the case even if the part of the action that caused the
machine-check event was VMX-specific (for example, the processor’s consulting an I/O bitmap). If a machinecheck exception occurs and if bit 12H of the exception bitmap is cleared to 0, the exception is delivered to the
guest through gate 12H of its IDT; if the bit is set to 1, the machine-check exception causes a VM exit.
NOTE
The state saved in the guest-state area on VM exits due to machine-check exceptions should be
considered suspect. A VMM should consult the RIPV and EIPV bits in the IA32_MCG_STATUS MSR
before resuming a guest that caused a VM exit due to a machine-check exception.
33.4.3
MCA Error Handling Guidelines for VMM
Section 33.4.2 covers general requirements for VMMs to handle machine-check exceptions, when normal operation
of the guest machine and/or the VMM is no longer possible. enhancements of machine-check architecture in newer
processors may support software recovery of uncorrected MC errors (UCR) signaled through either machine-check
exceptions or corrected machine-check interrupt (CMCI). Section 15.5 and Section 15.6 describes details of these
more recent enhancements of machine-check architecture.
In general, Virtual Machine Monitor (VMM) error handling should follow the recommendations for OS error handling
described in Section 15.3, Section 15.6, Section 15.9, and Section 15.10. This section describes additional guidelines for hosted and native hypervisor-based VMM implementations to support corrected MC errors and recoverable
uncorrected MC errors.
Because a hosted VMM provides virtualization services in the context of an existing standard host OS, the host OS
controls platform hardware through the host OS services such as the standard OS device drivers. In hosted VMMs.
MCA errors will be handled by the host OS error handling software.
In native VMMs, the hypervisor runs on the hardware directly, and may provide only a limited set of platform
services for guest VMs. Most platform services may instead be provided by a “control OS”. In hypervisor-based
VMMs, MCA errors will either be delivered directly to the VMM MCA handler (when the error is signaled while in the
VMM context) or cause by a VM exit from a guest VM or be delivered to the MCA intercept handler. There are two
general approaches the hypervisor can use to handle the MCA error: either within the hypervisor itself or by
forwarding the error to the control OS.
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33.4.3.1
VMM Error Handling Strategies
Broadly speaking, there are two strategies that VMMs may take for error handling:
•
Basic error handling: in this approach the guest VM is treated as any other thread of execution. If the error
recovery action does not support restarting the thread after handling the error, the guest VM should be
terminated.
•
MCA virtualization: in this approach, the VMM virtualizes the MCA events and hardware. This enables the VMM
to intercept MCA events and inject an MCA into the guest VM. The guest VM then has the opportunity to attempt
error recovery actions, rather than being terminated by the VMM.
Details of these approaches and implementation considerations for hosted and native VMMs are discussed below.
33.4.3.2
Basic VMM MCA error recovery handling
The simplest approach is for the VMM to treat the guest VM as any other thread of execution:
•
MCE's that occur outside the stream of execution of a virtual machine guest will cause an MCE abort and may
be handled by the MCA error handler following the recovery actions and guidelines described in Section 15.9,
and Section 15.10. This includes logging the error and taking appropriate recovery actions when necessary. The
VMM must not resume the interrupted thread of execution or another VM until it has taken the appropriate
recovery action or, in the case of fatal MCAs, reset the system.
•
MCE's that occur while executing in the context of a virtual machine will be intercepted by the VMM. The MCA
intercept handler may follow the error handling guidelines listed in Section 15.9 and Section 15.10 for SRAO
and SRAR errors. For SRAR errors, terminating the thread of execution will involve terminating the affected
guest VM. For fatal errors the MCA handler should log the error and reset the system -- the VMM should not
resume execution of the interrupted VM.
33.4.3.3
Implementation Considerations for the Basic Model
For hosted VMMs, the host OS MCA error handling code will perform error analysis and initiate the appropriate
recovery actions. For the basic model this flow does not change when terminating a guest VM although the specific
actions needed to terminate a guest VM may be different than terminating an application or user process.
For native, hypervisor-based VMMs, MCA errors will either be delivered directly to the VMM MCA handler (when the
error is signaled while in the VMM context) or cause a VM exit from a guest VM or be delivered to the MCA intercept
handler. There are two general approaches the hypervisor can use to handle the MCA error: either by forwarding
the error to the control OS or within the hypervisor itself. These approaches are described in the following paragraphs.
The hypervisor may forward the error to the control OS for handling errors. This approach simplifies the hypervisor
error handling since it relies on the control OS to implement the basic error handling model. The control OS error
handling code will be similar to the error handling code in the hosted VMM. Errors can be forwarded to the control
OS via an OS callback or by injecting an MCE event into the control OS. Injecting an MCE will cause the control OS
MCA error handler to be invoked. The control OS is responsible for terminating the affected guest VM, if necessary,
which may require cooperation from the hypervisor.
Alternatively, the error may be handled completely in the hypervisor. The hypervisor error handler is enhanced to
implement the basic error handling model and the hypervisor error handler has the capability to fully analyze the
error information and take recovery actions based on the guidelines. In this case error handling steps in the hypervisor are similar to those for the hosted VMM described above (where the hypervisor replaces the host OS actions).
The hypervisor is responsible for terminating the affected guest VM, if necessary.
In all cases, if a fatal error is detected the VMM error handler should log the error and reset the system. The VMM
error handler must ensure that guest VMs are not resumed after a fatal error is detected to ensure error containment is maintained.
33.4.3.4
MCA Virtualization
A more sophisticated approach for handling errors is to virtualize the MCA. This involves virtualizing the MCA hardware and intercepting the MCA event in the VMM when a guest VM is interrupted by an MCA. After analyzing the
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error, the VMM error handler may then decide to inject an MCE abort into the guest VM for attempted guest VM
error recovery. This would enable the guest OS the opportunity to take recovery actions specific to that guest.
For MCA virtualization, the VMM must provide the guest physical address for memory errors instead of the system
physical address when reporting the errors to the guest VM. To compute the guest physical address, the VMM
needs to maintain a reverse mapping of system physical page addresses to guest physical page addresses.
When the MCE is injected into the guest VM, the guest OS MCA handler would be invoked. The guest OS implements the MCA handling guidelines and it could potentially terminate the interrupted thread of execution within the
guest instead of terminating the VM. The guest OS may also disable use of the affected page by the guest. When
disabling the page the VMM error handler may handle the case where a page is shared by the VMM and a guest or
by two guests. In these cases the page use must be disabled in both contexts to ensure no subsequent consumption errors are generated.
33.4.3.5
Implementation Considerations for the MCA Virtualization Model
MCA virtualization may be done in either hosted VMMs or hypervisor-based VMMs. The error handling flow is
similar to the flow described in the basic handling case. The major difference is that the recovery action includes
injecting the MCE abort into the guest VM to enable recovery by the guest OS when the MCA interrupts the execution of a guest VM.
33.5
HANDLING ACTIVITY STATES BY VMM
A VMM might place a logic processor in the wait-for-SIPI activity state if supporting certain guest operating system
using the multi-processor (MP) start-up algorithm. A guest with direct access to the physical local APIC and using
the MP start-up algorithm sends an INIT-SIPI-SIPI IPI sequence to start the application processor. In order to trap
the SIPIs, the VMM must start the logic processor which is the target of the SIPIs in wait-for-SIPI mode.
Vol. 3C 33-11
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33-12 Vol. 3C
CHAPTER 34
SYSTEM MANAGEMENT MODE
This chapter describes aspects of IA-64 and IA-32 architecture used in system management mode (SMM).
SMM provides an alternate operating environment that can be used to monitor and manage various system
resources for more efficient energy usage, to control system hardware, and/or to run proprietary code. It was
introduced into the IA-32 architecture in the Intel386 SL processor (a mobile specialized version of the Intel386
processor). It is also available in the Pentium M, Pentium 4, Intel Xeon, P6 family, and Pentium and Intel486
processors (beginning with the enhanced versions of the Intel486 SL and Intel486 processors).
34.1
SYSTEM MANAGEMENT MODE OVERVIEW
SMM is a special-purpose operating mode provided for handling system-wide functions like power management,
system hardware control, or proprietary OEM-designed code. It is intended for use only by system firmware, not by
applications software or general-purpose systems software. The main benefit of SMM is that it offers a distinct and
easily isolated processor environment that operates transparently to the operating system or executive and software applications.
When SMM is invoked through a system management interrupt (SMI), the processor saves the current state of the
processor (the processor’s context), then switches to a separate operating environment defined by a new address
space. The system management software executive (SMI handler) starts execution in that environment, and the
critical code and data of the SMI handler reside in a physical memory region (SMRAM) within that address space.
While in SMM, the processor executes SMI handler code to perform operations such as powering down unused disk
drives or monitors, executing proprietary code, or placing the whole system in a suspended state. When the SMI
handler has completed its operations, it executes a resume (RSM) instruction. This instruction causes the processor
to reload the saved context of the processor, switch back to protected or real mode, and resume executing the
interrupted application or operating-system program or task.
The following SMM mechanisms make it transparent to applications programs and operating systems:
•
•
The only way to enter SMM is by means of an SMI.
•
•
•
Upon entering SMM, the processor saves the context of the interrupted program or task.
The processor executes SMM code in a separate address space that can be made inaccessible from the other
operating modes.
All interrupts normally handled by the operating system are disabled upon entry into SMM.
The RSM instruction can be executed only in SMM.
Section 34.3 describes transitions into and out of SMM. The execution environment after entering SMM is in realaddress mode with paging disabled (CR0.PE = CR0.PG = 0). In this initial execution environment, the SMI handler
can address up to 4 GBytes of memory and can execute all I/O and system instructions. Section 34.5 describes in
detail the initial SMM execution environment for an SMI handler and operation within that environment. The SMI
handler may subsequently switch to other operating modes while remaining in SMM.
NOTES
Software developers should be aware that, even if a logical processor was using the physicaladdress extension (PAE) mechanism (introduced in the P6 family processors) or was in IA-32e
mode before an SMI, this will not be the case after the SMI is delivered. This is because delivery of
an SMI disables paging (see Table 34-4). (This does not apply if the dual-monitor treatment of SMIs
and SMM is active; see Section 34.15.)
34.1.1
System Management Mode and VMX Operation
Traditionally, SMM services system management interrupts and then resumes program execution (back to the software stack consisting of executive and application software; see Section 34.2 through Section 34.13).
Vol. 3C 34-1
SYSTEM MANAGEMENT MODE
A virtual machine monitor (VMM) using VMX can act as a host to multiple virtual machines and each virtual machine
can support its own software stack of executive and application software. On processors that support VMX, virtualmachine extensions may use system-management interrupts (SMIs) and system-management mode (SMM) in one
of two ways:
•
Default treatment. System firmware handles SMIs. The processor saves architectural states and critical
states relevant to VMX operation upon entering SMM. When the firmware completes servicing SMIs, it uses
RSM to resume VMX operation.
•
Dual-monitor treatment. Two VM monitors collaborate to control the servicing of SMIs: one VMM operates
outside of SMM to provide basic virtualization in support for guests; the other VMM operates inside SMM (while
in VMX operation) to support system-management functions. The former is referred to as executive monitor,
the latter SMM-transfer monitor (STM).1
The default treatment is described in Section 34.14, “Default Treatment of SMIs and SMM with VMX Operation and
SMX Operation”. Dual-monitor treatment of SMM is described in Section 34.15, “Dual-Monitor Treatment of SMIs
and SMM”.
34.2
SYSTEM MANAGEMENT INTERRUPT (SMI)
The only way to enter SMM is by signaling an SMI through the SMI# pin on the processor or through an SMI
message received through the APIC bus. The SMI is a nonmaskable external interrupt that operates independently
from the processor’s interrupt- and exception-handling mechanism and the local APIC. The SMI takes precedence
over an NMI and a maskable interrupt. SMM is non-reentrant; that is, the SMI is disabled while the processor is in
SMM.
NOTES
In the Pentium 4, Intel Xeon, and P6 family processors, when a processor that is designated as an
application processor during an MP initialization sequence is waiting for a startup IPI (SIPI), it is in
a mode where SMIs are masked. However if a SMI is received while an application processor is in
the wait for SIPI mode, the SMI will be pended. The processor then responds on receipt of a SIPI by
immediately servicing the pended SMI and going into SMM before handling the SIPI.
An SMI may be blocked for one instruction following execution of STI, MOV to SS, or POP into SS.
34.3
SWITCHING BETWEEN SMM AND THE OTHER
PROCESSOR OPERATING MODES
Figure 2-3 shows how the processor moves between SMM and the other processor operating modes (protected,
real-address, and virtual-8086). Signaling an SMI while the processor is in real-address, protected, or virtual-8086
modes always causes the processor to switch to SMM. Upon execution of the RSM instruction, the processor always
returns to the mode it was in when the SMI occurred.
34.3.1
Entering SMM
The processor always handles an SMI on an architecturally defined “interruptible” point in program execution
(which is commonly at an IA-32 architecture instruction boundary). When the processor receives an SMI, it waits
for all instructions to retire and for all stores to complete. The processor then saves its current context in SMRAM
(see Section 34.4), enters SMM, and begins to execute the SMI handler.
Upon entering SMM, the processor signals external hardware that SMI handling has begun. The signaling mechanism used is implementation dependent. For the P6 family processors, an SMI acknowledge transaction is gener-
1. The dual-monitor treatment may not be supported by all processors. Software should consult the VMX capability MSR
IA32_VMX_BASIC (see Appendix A.1) to determine whether it is supported.
34-2 Vol. 3C
SYSTEM MANAGEMENT MODE
ated on the system bus and the multiplexed status signal EXF4 is asserted each time a bus transaction is generated
while the processor is in SMM. For the Pentium and Intel486 processors, the SMIACT# pin is asserted.
An SMI has a greater priority than debug exceptions and external interrupts. Thus, if an NMI, maskable hardware
interrupt, or a debug exception occurs at an instruction boundary along with an SMI, only the SMI is handled.
Subsequent SMI requests are not acknowledged while the processor is in SMM. The first SMI interrupt request that
occurs while the processor is in SMM (that is, after SMM has been acknowledged to external hardware) is latched
and serviced when the processor exits SMM with the RSM instruction. The processor will latch only one SMI while
in SMM.
See Section 34.5 for a detailed description of the execution environment when in SMM.
34.3.2
Exiting From SMM
The only way to exit SMM is to execute the RSM instruction. The RSM instruction is only available to the SMI
handler; if the processor is not in SMM, attempts to execute the RSM instruction result in an invalid-opcode exception (#UD) being generated.
The RSM instruction restores the processor’s context by loading the state save image from SMRAM back into the
processor’s registers. The processor then returns an SMIACK transaction on the system bus and returns program
control back to the interrupted program.
Upon successful completion of the RSM instruction, the processor signals external hardware that SMM has been
exited. For the P6 family processors, an SMI acknowledge transaction is generated on the system bus and the
multiplexed status signal EXF4 is no longer generated on bus cycles. For the Pentium and Intel486 processors, the
SMIACT# pin is deserted.
If the processor detects invalid state information saved in the SMRAM, it enters the shutdown state and generates
a special bus cycle to indicate it has entered shutdown state. Shutdown happens only in the following situations:
•
A reserved bit in control register CR4 is set to 1 on a write to CR4. This error should not happen unless SMI
handler code modifies reserved areas of the SMRAM saved state map (see Section 34.4.1). CR4 is saved in the
state map in a reserved location and cannot be read or modified in its saved state.
•
An illegal combination of bits is written to control register CR0, in particular PG set to 1 and PE set to 0, or NW
set to 1 and CD set to 0.
•
•
CR4.PCIDE would be set to 1 and IA32_EFER.LMA to 0.
(For the Pentium and Intel486 processors only.) If the address stored in the SMBASE register when an RSM
instruction is executed is not aligned on a 32-KByte boundary. This restriction does not apply to the P6 family
processors.
In the shutdown state, Intel processors stop executing instructions until a RESET#, INIT# or NMI# is asserted.
While Pentium family processors recognize the SMI# signal in shutdown state, P6 family and Intel486 processors
do not. Intel does not support using SMI# to recover from shutdown states for any processor family; the response
of processors in this circumstance is not well defined. On Pentium 4 and later processors, shutdown will inhibit
INTR and A20M but will not change any of the other inhibits. On these processors, NMIs will be inhibited if no action
is taken in the SMI handler to uninhibit them (see Section 34.8).
If the processor is in the HALT state when the SMI is received, the processor handles the return from SMM slightly
differently (see Section 34.10). Also, the SMBASE address can be changed on a return from SMM (see Section
34.11).
34.4
SMRAM
Upon entering SMM, the processor switches to a new address space. Because paging is disabled upon entering
SMM, this initial address space maps all memory accesses to the low 4 GBytes of the processor's physical address
space. The SMI handler's critical code and data reside in a memory region referred to as system-management RAM
(SMRAM). The processor uses a pre-defined region within SMRAM to save the processor's pre-SMI context. SMRAM
can also be used to store system management information (such as the system configuration and specific information about powered-down devices) and OEM-specific information.
Vol. 3C 34-3
SYSTEM MANAGEMENT MODE
The default SMRAM size is 64 KBytes beginning at a base physical address in physical memory called the SMBASE
(see Figure 34-1). The SMBASE default value following a hardware reset is 30000H. The processor looks for the
first instruction of the SMI handler at the address [SMBASE + 8000H]. It stores the processor’s state in the area
from [SMBASE + FE00H] to [SMBASE + FFFFH]. See Section 34.4.1 for a description of the mapping of the state
save area.
The system logic is minimally required to decode the physical address range for the SMRAM from [SMBASE +
8000H] to [SMBASE + FFFFH]. A larger area can be decoded if needed. The size of this SMRAM can be between 32
KBytes and 4 GBytes.
The location of the SMRAM can be changed by changing the SMBASE value (see Section 34.11). It should be noted
that all processors in a multiple-processor system are initialized with the same SMBASE value (30000H). Initialization software must sequentially place each processor in SMM and change its SMBASE so that it does not overlap
those of other processors.
The actual physical location of the SMRAM can be in system memory or in a separate RAM memory. The processor
generates an SMI acknowledge transaction (P6 family processors) or asserts the SMIACT# pin (Pentium and
Intel486 processors) when the processor receives an SMI (see Section 34.3.1).
System logic can use the SMI acknowledge transaction or the assertion of the SMIACT# pin to decode accesses to
the SMRAM and redirect them (if desired) to specific SMRAM memory. If a separate RAM memory is used for
SMRAM, system logic should provide a programmable method of mapping the SMRAM into system memory space
when the processor is not in SMM. This mechanism will enable start-up procedures to initialize the SMRAM space
(that is, load the SMI handler) before executing the SMI handler during SMM.
34.4.1
SMRAM State Save Map
When an IA-32 processor that does not support Intel 64 architecture initially enters SMM, it writes its state to the
state save area of the SMRAM. The state save area begins at [SMBASE + 8000H + 7FFFH] and extends down to
[SMBASE + 8000H + 7E00H]. Table 34-1 shows the state save map. The offset in column 1 is relative to the
SMBASE value plus 8000H. Reserved spaces should not be used by software.
Some of the registers in the SMRAM state save area (marked YES in column 3) may be read and changed by the
SMI handler, with the changed values restored to the processor registers by the RSM instruction. Some register
images are read-only, and must not be modified (modifying these registers will result in unpredictable behavior).
An SMI handler should not rely on any values stored in an area that is marked as reserved.
SMRAM
SMBASE + FFFFH
SMBASE + 8000H
Start of State Save Area
SMI Handler Entry Point
SMBASE
Figure 34-1. SMRAM Usage
34-4 Vol. 3C
SYSTEM MANAGEMENT MODE
Table 34-1. SMRAM State Save Map
Offset
(Added to SMBASE + 8000H)
Register
Writable?
7FFCH
CR0
No
7FF8H
CR3
No
7FF4H
EFLAGS
Yes
7FF0H
EIP
Yes
7FECH
EDI
Yes
7FE8H
ESI
Yes
7FE4H
EBP
Yes
7FE0H
ESP
Yes
7FDCH
EBX
Yes
7FD8H
EDX
Yes
7FD4H
ECX
Yes
7FD0H
EAX
Yes
7FCCH
DR6
No
7FC8H
DR7
No
7FC4H
TR
1
No
7FC0H
Reserved
No
7FBCH
GS1
No
7FB8H
1
No
7FB4H
DS
1
No
7FB0H
SS1
No
7FACH
1
No
1
FS
CS
7FA8H
ES
No
7FA4H
I/O State Field, see Section 34.7
No
7FA0H
I/O Memory Address Field, see Section 34.7
No
7F9FH-7F03H
Reserved
No
7F02H
Auto HALT Restart Field (Word)
Yes
7F00H
I/O Instruction Restart Field (Word)
Yes
7EFCH
SMM Revision Identifier Field (Doubleword)
No
7EF8H
SMBASE Field (Doubleword)
Yes
7EF7H - 7E00H
Reserved
No
NOTE:
1. The two most significant bytes are reserved.
The following registers are saved (but not readable) and restored upon exiting SMM:
•
•
Control register CR4. (This register is cleared to all 0s when entering SMM).
The hidden segment descriptor information stored in segment registers CS, DS, ES, FS, GS, and SS.
If an SMI request is issued for the purpose of powering down the processor, the values of all reserved locations in
the SMM state save must be saved to nonvolatile memory.
The following state is not automatically saved and restored following an SMI and the RSM instruction, respectively:
Vol. 3C 34-5
SYSTEM MANAGEMENT MODE
•
•
•
•
•
Debug registers DR0 through DR3.
•
•
•
•
The state of the trap controller.
The x87 FPU registers.
The MTRRs.
Control register CR2.
The model-specific registers (for the P6 family and Pentium processors) or test registers TR3 through TR7 (for
the Pentium and Intel486 processors).
The machine-check architecture registers.
The APIC internal interrupt state (ISR, IRR, etc.).
The microcode update state.
If an SMI is used to power down the processor, a power-on reset will be required before returning to SMM, which
will reset much of this state back to its default values. So an SMI handler that is going to trigger power down should
first read these registers listed above directly, and save them (along with the rest of RAM) to nonvolatile storage.
After the power-on reset, the continuation of the SMI handler should restore these values, along with the rest of
the system's state. Anytime the SMI handler changes these registers in the processor, it must also save and restore
them.
NOTES
A small subset of the MSRs (such as, the time-stamp counter and performance-monitoring
counters) are not arbitrarily writable and therefore cannot be saved and restored. SMM-based
power-down and restoration should only be performed with operating systems that do not use or
rely on the values of these registers.
Operating system developers should be aware of this fact and insure that their operating-system
assisted power-down and restoration software is immune to unexpected changes in these register
values.
34.4.1.1
SMRAM State Save Map and Intel 64 Architecture
When the processor initially enters SMM, it writes its state to the state save area of the SMRAM. The state save area
on an Intel 64 processor at [SMBASE + 8000H + 7FFFH] and extends to [SMBASE + 8000H + 7C00H].
Support for Intel 64 architecture is reported by CPUID.80000001:EDX[29] = 1. The layout of the SMRAM state save
map is shown in Table 34-3.
Additionally, the SMRAM state save map shown in Table 34-3 also applies to processors with the following CPUID
signatures listed in Table 34-2, irrespective of the value in CPUID.80000001:EDX[29].
Table 34-2. Processor Signatures and 64-bit SMRAM State Save Map Format
DisplayFamily_DisplayModel Processor Families/Processor Number Series
06_17H
Intel Xeon Processor 5200, 5400 series, Intel Core 2 Quad processor Q9xxx, Intel Core 2 Duo
processors E8000, T9000,
06_0FH
Intel Xeon Processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad, Intel Core 2 Extreme,
Intel Core 2 Duo processors, Intel Pentium dual-core processors
06_1CH
45 nm Intel® Atom™ processors
34-6 Vol. 3C
SYSTEM MANAGEMENT MODE
Table 34-3. SMRAM State Save Map for Intel 64 Architecture
Offset
(Added to SMBASE + 8000H)
Register
Writable?
7FF8H
CR0
No
7FF0H
CR3
No
7FE8H
RFLAGS
Yes
7FE0H
IA32_EFER
Yes
7FD8H
RIP
Yes
7FD0H
DR6
No
7FC8H
DR7
7FC4H
No
TR SEL
1
No
1
7FC0H
LDTR SEL
7FBCH
1
GS SEL
No
7FB8H
FS SEL1
No
7FB4H
1
No
7FB0H
SS SEL
1
No
7FACH
CS SEL1
No
7FA8H
1
ES SEL
No
7FA4H
IO_MISC
No
7F9CH
IO_MEM_ADDR
No
7F94H
RDI
Yes
7F8CH
RSI
Yes
7F84H
RBP
Yes
7F7CH
RSP
Yes
7F74H
RBX
Yes
7F6CH
RDX
Yes
7F64H
RCX
Yes
7F5CH
RAX
Yes
7F54H
R8
Yes
7F4CH
R9
Yes
7F44H
R10
Yes
7F3CH
R11
Yes
7F34H
R12
Yes
7F2CH
R13
Yes
7F24H
R14
Yes
7F1CH
R15
Yes
7F1BH-7F04H
Reserved
No
7F02H
Auto HALT Restart Field (Word)
Yes
7F00H
I/O Instruction Restart Field (Word)
Yes
7EFCH
SMM Revision Identifier Field (Doubleword)
No
7EF8H
SMBASE Field (Doubleword)
Yes
DS SEL
No
Vol. 3C 34-7
SYSTEM MANAGEMENT MODE
Table 34-3. SMRAM State Save Map for Intel 64 Architecture (Contd.)
Offset
(Added to SMBASE + 8000H)
Register
Writable?
7EF7H - 7EE4H
Reserved
No
7EE0H
Setting of “enable EPT” VM-execution control
No
7ED8H
Value of EPTP VM-execution control field
No
7ED7H - 7EA0H
Reserved
No
7E9CH
LDT Base (lower 32 bits)
No
7E98H
Reserved
No
7E94H
IDT Base (lower 32 bits)
No
7E90H
Reserved
No
7E8CH
GDT Base (lower 32 bits)
No
7E8BH - 7E44H
Reserved
No
7E40H
CR4
No
7E3FH - 7DF0H
Reserved
No
7DE8H
IO_RIP
Yes
7DE7H - 7DDCH
Reserved
No
7DD8H
IDT Base (Upper 32 bits)
No
7DD4H
LDT Base (Upper 32 bits)
No
7DD0H
GDT Base (Upper 32 bits)
No
7DCFH - 7C00H
Reserved
No
NOTE:
1. The two most significant bytes are reserved.
34.4.2
SMRAM Caching
An IA-32 processor does not automatically write back and invalidate its caches before entering SMM or before
exiting SMM. Because of this behavior, care must be taken in the placement of the SMRAM in system memory and
in the caching of the SMRAM to prevent cache incoherence when switching back and forth between SMM and
protected mode operation. Either of the following three methods of locating the SMRAM in system memory will
guarantee cache coherency:
•
Place the SRAM in a dedicated section of system memory that the operating system and applications are
prevented from accessing. Here, the SRAM can be designated as cacheable (WB, WT, or WC) for optimum
processor performance, without risking cache incoherence when entering or exiting SMM.
•
Place the SRAM in a section of memory that overlaps an area used by the operating system (such as the video
memory), but designate the SMRAM as uncacheable (UC). This method prevents cache access when in SMM to
maintain cache coherency, but the use of uncacheable memory reduces the performance of SMM code.
•
Place the SRAM in a section of system memory that overlaps an area used by the operating system and/or
application code, but explicitly flush (write back and invalidate) the caches upon entering and exiting SMM
mode. This method maintains cache coherency, but incurs the overhead of two complete cache flushes.
For Pentium 4, Intel Xeon, and P6 family processors, a combination of the first two methods of locating the SMRAM
is recommended. Here the SMRAM is split between an overlapping and a dedicated region of memory. Upon
entering SMM, the SMRAM space that is accessed overlaps video memory (typically located in low memory). This
SMRAM section is designated as UC memory. The initial SMM code then jumps to a second SMRAM section that is
located in a dedicated region of system memory (typically in high memory). This SMRAM section can be cached for
optimum processor performance.
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SYSTEM MANAGEMENT MODE
For systems that explicitly flush the caches upon entering SMM (the third method described above), the cache flush
can be accomplished by asserting the FLUSH# pin at the same time as the request to enter SMM (generally initiated by asserting the SMI# pin). The priorities of the FLUSH# and SMI# pins are such that the FLUSH# is serviced
first. To guarantee this behavior, the processor requires that the following constraints on the interaction of FLUSH#
and SMI# be met. In a system where the FLUSH# and SMI# pins are synchronous and the set up and hold times
are met, then the FLUSH# and SMI# pins may be asserted in the same clock. In asynchronous systems, the
FLUSH# pin must be asserted at least one clock before the SMI# pin to guarantee that the FLUSH# pin is serviced
first.
Upon leaving SMM (for systems that explicitly flush the caches), the WBINVD instruction should be executed prior
to leaving SMM to flush the caches.
NOTES
In systems based on the Pentium processor that use the FLUSH# pin to write back and invalidate
cache contents before entering SMM, the processor will prefetch at least one cache line in between
when the Flush Acknowledge cycle is run and the subsequent recognition of SMI# and the assertion
of SMIACT#.
It is the obligation of the system to ensure that these lines are not cached by returning KEN#
inactive to the Pentium processor.
34.4.2.1
System Management Range Registers (SMRR)
SMI handler code and data stored by SMM code resides in SMRAM. The SMRR interface is an enhancement in Intel
64 architecture to limit cacheable reference of addresses in SMRAM to code running in SMM. The SMRR interface
can be configured only by code running in SMM. Details of SMRR is described in Section 11.11.2.4.
34.5
SMI HANDLER EXECUTION ENVIRONMENT
Section 34.5.1 describes the initial execution environment for an SMI handler. An SMI handler may re-configure its
execution environment to other supported operating modes. Section 34.5.2 discusses modifications an SMI
handler can make to its execution environment.
34.5.1
Initial SMM Execution Environment
After saving the current context of the processor, the processor initializes its core registers to the values shown in
Table 34-4. Upon entering SMM, the PE and PG flags in control register CR0 are cleared, which places the processor
in an environment similar to real-address mode. The differences between the SMM execution environment and the
real-address mode execution environment are as follows:
•
•
•
The addressable address space ranges from 0 to FFFFFFFFH (4 GBytes).
The normal 64-KByte segment limit for real-address mode is increased to 4 GBytes.
The default operand and address sizes are set to 16 bits, which restricts the addressable SMRAM address space
to the 1-MByte real-address mode limit for native real-address-mode code. However, operand-size and
address-size override prefixes can be used to access the address space beyond the 1-MByte.
Table 34-4. Processor Register Initialization in SMM
Register
Contents
General-purpose registers
Undefined
EFLAGS
00000002H
EIP
00008000H
CS selector
SMM Base shifted right 4 bits (default 3000H)
CS base
SMM Base (default 30000H)
DS, ES, FS, GS, SS Selectors
0000H
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SYSTEM MANAGEMENT MODE
Table 34-4. Processor Register Initialization in SMM
DS, ES, FS, GS, SS Bases
000000000H
DS, ES, FS, GS, SS Limits
0FFFFFFFFH
CR0
PE, EM, TS, and PG flags set to 0; others unmodified
CR4
Cleared to zero
DR6
Undefined
DR7
00000400H
•
Near jumps and calls can be made to anywhere in the 4-GByte address space if a 32-bit operand-size override
prefix is used. Due to the real-address-mode style of base-address formation, a far call or jump cannot transfer
control to a segment with a base address of more than 20 bits (1 MByte). However, since the segment limit in
SMM is 4 GBytes, offsets into a segment that go beyond the 1-MByte limit are allowed when using 32-bit
operand-size override prefixes. Any program control transfer that does not have a 32-bit operand-size override
prefix truncates the EIP value to the 16 low-order bits.
•
Data and the stack can be located anywhere in the 4-GByte address space, but can be accessed only with a 32bit address-size override if they are located above 1 MByte. As with the code segment, the base address for a
data or stack segment cannot be more than 20 bits.
The value in segment register CS is automatically set to the default of 30000H for the SMBASE shifted 4 bits to the
right; that is, 3000H. The EIP register is set to 8000H. When the EIP value is added to shifted CS value (the
SMBASE), the resulting linear address points to the first instruction of the SMI handler.
The other segment registers (DS, SS, ES, FS, and GS) are cleared to 0 and their segment limits are set to 4 GBytes.
In this state, the SMRAM address space may be treated as a single flat 4-GByte linear address space. If a segment
register is loaded with a 16-bit value, that value is then shifted left by 4 bits and loaded into the segment base
(hidden part of the segment register). The limits and attributes are not modified.
Maskable hardware interrupts, exceptions, NMI interrupts, SMI interrupts, A20M interrupts, single-step traps,
breakpoint traps, and INIT operations are inhibited when the processor enters SMM. Maskable hardware interrupts,
exceptions, single-step traps, and breakpoint traps can be enabled in SMM if the SMM execution environment
provides and initializes an interrupt table and the necessary interrupt and exception handlers (see Section 34.6).
34.5.2
SMI Handler Operating Mode Switching
Within SMM, an SMI handler may change the processor's operating mode (e.g., to enable PAE paging, enter 64-bit
mode, etc.) after it has made proper preparation and initialization to do so. For example, if switching to 32-bit
protected mode, the SMI handler should follow the guidelines provided in Chapter 9, “Processor Management and
Initialization”. If the SMI handler does wish to change operating mode, it is responsible for executing the appropriate mode-transition code after each SMI.
It is recommended that the SMI handler make use of all means available to protect the integrity of its critical code
and data. In particular, it should use the system-management range register (SMRR) interface if it is available (see
Section 11.11.2.4). The SMRR interface can protect only the first 4 GBytes of the physical address space. The SMI
handler should take that fact into account if it uses operating modes that allow access to physical addresses beyond
that 4-GByte limit (e.g. PAE paging or 64-bit mode).
Execution of the RSM instruction restores the pre-SMI processor state from the SMRAM state-state map (see
Section 34.4.1) into which it was stored when the processor entered SMM. (The SMBASE field in the SMRAM statesave map does not determine the state following RSM but rather the initial environment following the next entry to
SMM.) Any required change to operating mode is performed by the RSM instruction; there is no need for the SMI
handler to change modes explicitly prior to executing RSM.
34.6
EXCEPTIONS AND INTERRUPTS WITHIN SMM
When the processor enters SMM, all hardware interrupts are disabled in the following manner:
34-10 Vol. 3C
SYSTEM MANAGEMENT MODE
•
The IF flag in the EFLAGS register is cleared, which inhibits maskable hardware interrupts from being
generated.
•
•
The TF flag in the EFLAGS register is cleared, which disables single-step traps.
•
NMI, SMI, and A20M interrupts are blocked by internal SMM logic. (See Section 34.8 for more information
about how NMIs are handled in SMM.)
Debug register DR7 is cleared, which disables breakpoint traps. (This action prevents a debugger from accidentally breaking into an SMI handler if a debug breakpoint is set in normal address space that overlays code or
data in SMRAM.)
Software-invoked interrupts and exceptions can still occur, and maskable hardware interrupts can be enabled by
setting the IF flag. Intel recommends that SMM code be written in so that it does not invoke software interrupts
(with the INT n, INTO, INT 3, or BOUND instructions) or generate exceptions.
If the SMI handler requires interrupt and exception handling, an SMM interrupt table and the necessary exception
and interrupt handlers must be created and initialized from within SMM. Until the interrupt table is correctly initialized (using the LIDT instruction), exceptions and software interrupts will result in unpredictable processor
behavior.
The following restrictions apply when designing SMM interrupt and exception-handling facilities:
•
The interrupt table should be located at linear address 0 and must contain real-address mode style interrupt
vectors (4 bytes containing CS and IP).
•
Due to the real-address mode style of base address formation, an interrupt or exception cannot transfer control
to a segment with a base address of more that 20 bits.
•
•
An interrupt or exception cannot transfer control to a segment offset of more than 16 bits (64 KBytes).
•
The SMBASE relocation feature affects the way the processor will return from an interrupt or exception
generated while the SMI handler is executing. For example, if the SMBASE is relocated to above 1 MByte, but
the exception handlers are below 1 MByte, a normal return to the SMI handler is not possible. One solution is
to provide the exception handler with a mechanism for calculating a return address above 1 MByte from the 16bit return address on the stack, then use a 32-bit far call to return to the interrupted procedure.
•
If an SMI handler needs access to the debug trap facilities, it must insure that an SMM accessible debug handler
is available and save the current contents of debug registers DR0 through DR3 (for later restoration). Debug
registers DR0 through DR3 and DR7 must then be initialized with the appropriate values.
•
If an SMI handler needs access to the single-step mechanism, it must insure that an SMM accessible singlestep handler is available, and then set the TF flag in the EFLAGS register.
•
If the SMI design requires the processor to respond to maskable hardware interrupts or software-generated
interrupts while in SMM, it must ensure that SMM accessible interrupt handlers are available and then set the
IF flag in the EFLAGS register (using the STI instruction). Software interrupts are not blocked upon entry to
SMM, so they do not need to be enabled.
When an exception or interrupt occurs, only the 16 least-significant bits of the return address (EIP) are pushed
onto the stack. If the offset of the interrupted procedure is greater than 64 KBytes, it is not possible for the
interrupt/exception handler to return control to that procedure. (One solution to this problem is for a handler
to adjust the return address on the stack.)
34.7
MANAGING SYNCHRONOUS AND ASYNCHRONOUS
SYSTEM MANAGEMENT INTERRUPTS
When coding for a multiprocessor system or a system with Intel HT Technology, it was not always possible for an
SMI handler to distinguish between a synchronous SMI (triggered during an I/O instruction) and an asynchronous
SMI. To facilitate the discrimination of these two events, incremental state information has been added to the SMM
state save map.
Processors that have an SMM revision ID of 30004H or higher have the incremental state information described
below.
Vol. 3C 34-11
SYSTEM MANAGEMENT MODE
34.7.1
I/O State Implementation
Within the extended SMM state save map, a bit (IO_SMI) is provided that is set only when an SMI is either taken
immediately after a successful I/O instruction or is taken after a successful iteration of a REP I/O instruction (the
successful notion pertains to the processor point of view; not necessarily to the corresponding platform function).
When set, the IO_SMI bit provides a strong indication that the corresponding SMI was synchronous. In this case,
the SMM State Save Map also supplies the port address of the I/O operation. The IO_SMI bit and the I/O Port
Address may be used in conjunction with the information logged by the platform to confirm that the SMI was
indeed synchronous.
The IO_SMI bit by itself is a strong indication, not a guarantee, that the SMI is synchronous. This is because an
asynchronous SMI might coincidentally be taken after an I/O instruction. In such a case, the IO_SMI bit would still
be set in the SMM state save map.
Information characterizing the I/O instruction is saved in two locations in the SMM State Save Map (Table 34-5).
The IO_SMI bit also serves as a valid bit for the rest of the I/O information fields. The contents of these I/O information fields are not defined when the IO_SMI bit is not set.
Table 34-5. I/O Instruction Information in the SMM State Save Map
State (SMM Rev. ID: 30004H or higher)
Format
31
15
8
I/O Memory Address
When IO_SMI is set, the other fields may be interpreted as follows:
I/O length:
•
•
•
•
001 – Byte
010 – Word
100 – Dword
I/O instruction type (Table 34-6)
Table 34-6. I/O Instruction Type Encodings
Instruction
Encoding
IN Immediate
1001
IN DX
0001
OUT Immediate
1000
OUT DX
0000
INS
0011
OUTS
0010
REP INS
0111
REP OUTS
0110
34-12 Vol. 3C
0
0
SMRAM offset 7FA0
•
1
IO_SMI
I/O Memory Address Field
3
I/O Length
31
4
I/O Type
SMRAM offset 7FA4
7
Reserved
I/O Port
I/0 State Field
16
SYSTEM MANAGEMENT MODE
34.8
NMI HANDLING WHILE IN SMM
NMI interrupts are blocked upon entry to the SMI handler. If an NMI request occurs during the SMI handler, it is
latched and serviced after the processor exits SMM. Only one NMI request will be latched during the SMI handler.
If an NMI request is pending when the processor executes the RSM instruction, the NMI is serviced before the next
instruction of the interrupted code sequence. This assumes that NMIs were not blocked before the SMI occurred. If
NMIs were blocked before the SMI occurred, they are blocked after execution of RSM.
Although NMI requests are blocked when the processor enters SMM, they may be enabled through software by
executing an IRET instruction. If the SMI handler requires the use of NMI interrupts, it should invoke a dummy
interrupt service routine for the purpose of executing an IRET instruction. Once an IRET instruction is executed,
NMI interrupt requests are serviced in the same “real mode” manner in which they are handled outside of SMM.
A special case can occur if an SMI handler nests inside an NMI handler and then another NMI occurs. During NMI
interrupt handling, NMI interrupts are disabled, so normally NMI interrupts are serviced and completed with an
IRET instruction one at a time. When the processor enters SMM while executing an NMI handler, the processor
saves the SMRAM state save map but does not save the attribute to keep NMI interrupts disabled. Potentially, an
NMI could be latched (while in SMM or upon exit) and serviced upon exit of SMM even though the previous NMI
handler has still not completed. One or more NMIs could thus be nested inside the first NMI handler. The NMI interrupt handler should take this possibility into consideration.
Also, for the Pentium processor, exceptions that invoke a trap or fault handler will enable NMI interrupts from inside
of SMM. This behavior is implementation specific for the Pentium processor and is not part of the IA-32 architecture.
34.9
SMM REVISION IDENTIFIER
The SMM revision identifier field is used to indicate the version of SMM and the SMM extensions that are supported
by the processor (see Figure 34-2). The SMM revision identifier is written during SMM entry and can be examined
in SMRAM space at offset 7EFCH. The lower word of the SMM revision identifier refers to the version of the base
SMM architecture.
Register Offset
7EFCH
31
0
18 17 16 15
Reserved
SMM Revision Identifier
SMBASE Relocation
I/O Instruction Restart
Figure 34-2. SMM Revision Identifier
The upper word of the SMM revision identifier refers to the extensions available. If the I/O instruction restart flag
(bit 16) is set, the processor supports the I/O instruction restart (see Section 34.12); if the SMBASE relocation flag
(bit 17) is set, SMRAM base address relocation is supported (see Section 34.11).
34.10
AUTO HALT RESTART
If the processor is in a HALT state (due to the prior execution of a HLT instruction) when it receives an SMI, the
processor records the fact in the auto HALT restart flag in the saved processor state (see Figure 34-3). (This flag is
located at offset 7F02H and bit 0 in the state save area of the SMRAM.)
If the processor sets the auto HALT restart flag upon entering SMM (indicating that the SMI occurred when the
processor was in the HALT state), the SMI handler has two options:
Vol. 3C 34-13
SYSTEM MANAGEMENT MODE
•
It can leave the auto HALT restart flag set, which instructs the RSM instruction to return program control to the
HLT instruction. This option in effect causes the processor to re-enter the HALT state after handling the SMI.
(This is the default operation.)
•
It can clear the auto HALT restart flag, which instructs the RSM instruction to return program control to the
instruction following the HLT instruction.
15
1 0
Reserved
Register Offset
7F02H
Auto HALT Restart
Figure 34-3. Auto HALT Restart Field
These options are summarized in Table 34-7. If the processor was not in a HALT state when the SMI was received
(the auto HALT restart flag is cleared), setting the flag to 1 will cause unpredictable behavior when the RSM instruction is executed.
Table 34-7. Auto HALT Restart Flag Values
Value of Flag After
Entry to SMM
Value of Flag When
Exiting SMM
Action of Processor When Exiting SMM
0
0
Returns to next instruction in interrupted program or task.
0
1
Unpredictable.
1
0
Returns to next instruction after HLT instruction.
1
1
Returns to HALT state.
If the HLT instruction is restarted, the processor will generate a memory access to fetch the HLT instruction (if it is
not in the internal cache), and execute a HLT bus transaction. This behavior results in multiple HLT bus transactions
for the same HLT instruction.
34.10.1 Executing the HLT Instruction in SMM
The HLT instruction should not be executed during SMM, unless interrupts have been enabled by setting the IF flag
in the EFLAGS register. If the processor is halted in SMM, the only event that can remove the processor from this
state is a maskable hardware interrupt or a hardware reset.
34.11
SMBASE RELOCATION
The default base address for the SMRAM is 30000H. This value is contained in an internal processor register called
the SMBASE register. The operating system or executive can relocate the SMRAM by setting the SMBASE field in the
saved state map (at offset 7EF8H) to a new value (see Figure 34-4). The RSM instruction reloads the internal
SMBASE register with the value in the SMBASE field each time it exits SMM. All subsequent SMI requests will use
the new SMBASE value to find the starting address for the SMI handler (at SMBASE + 8000H) and the SMRAM state
save area (from SMBASE + FE00H to SMBASE + FFFFH). (The processor resets the value in its internal SMBASE
register to 30000H on a RESET, but does not change it on an INIT.)
34-14 Vol. 3C
SYSTEM MANAGEMENT MODE
31
0
Register Offset
7EF8H
SMM Base
Figure 34-4. SMBASE Relocation Field
In multiple-processor systems, initialization software must adjust the SMBASE value for each processor so that the
SMRAM state save areas for each processor do not overlap. (For Pentium and Intel486 processors, the SMBASE
values must be aligned on a 32-KByte boundary or the processor will enter shutdown state during the execution of
a RSM instruction.)
If the SMBASE relocation flag in the SMM revision identifier field is set, it indicates the ability to relocate the
SMBASE (see Section 34.9).
34.12
I/O INSTRUCTION RESTART
If the I/O instruction restart flag in the SMM revision identifier field is set (see Section 34.9), the I/O instruction
restart mechanism is present on the processor. This mechanism allows an interrupted I/O instruction to be reexecuted upon returning from SMM mode. For example, if an I/O instruction is used to access a powered-down I/O
device, a chip set supporting this device can intercept the access and respond by asserting SMI#. This action
invokes the SMI handler to power-up the device. Upon returning from the SMI handler, the I/O instruction restart
mechanism can be used to re-execute the I/O instruction that caused the SMI.
The I/O instruction restart field (at offset 7F00H in the SMM state-save area, see Figure 34-5) controls I/O instruction restart. When an RSM instruction is executed, if this field contains the value FFH, then the EIP register is modified to point to the I/O instruction that received the SMI request. The processor will then automatically re-execute
the I/O instruction that the SMI trapped. (The processor saves the necessary machine state to insure that reexecution of the instruction is handled coherently.)
15
0
I/O Instruction Restart Field
Register Offset
7F00H
Figure 34-5. I/O Instruction Restart Field
If the I/O instruction restart field contains the value 00H when the RSM instruction is executed, then the processor
begins program execution with the instruction following the I/O instruction. (When a repeat prefix is being used,
the next instruction may be the next I/O instruction in the repeat loop.) Not re-executing the interrupted I/O
instruction is the default behavior; the processor automatically initializes the I/O instruction restart field to 00H
upon entering SMM. Table 34-8 summarizes the states of the I/O instruction restart field.
Table 34-8. I/O Instruction Restart Field Values
Value of Flag After
Entry to SMM
Value of Flag When
Exiting SMM
Action of Processor When Exiting SMM
00H
00H
Does not re-execute trapped I/O instruction.
00H
FFH
Re-executes trapped I/O instruction.
The I/O instruction restart mechanism does not indicate the cause of the SMI. It is the responsibility of the SMI
handler to examine the state of the processor to determine the cause of the SMI and to determine if an I/O instruction was interrupted and should be restarted upon exiting SMM. If an SMI interrupt is signaled on a non-I/O
instruction boundary, setting the I/O instruction restart field to FFH prior to executing the RSM instruction will likely
result in a program error.
Vol. 3C 34-15
SYSTEM MANAGEMENT MODE
34.12.1 Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used
If an SMI interrupt is signaled while the processor is servicing an SMI interrupt that occurred on an I/O instruction
boundary, the processor will service the new SMI request before restarting the originally interrupted I/O instruction. If the I/O instruction restart field is set to FFH prior to returning from the second SMI handler, the EIP will point
to an address different from the originally interrupted I/O instruction, which will likely lead to a program error. To
avoid this situation, the SMI handler must be able to recognize the occurrence of back-to-back SMI interrupts when
I/O instruction restart is being used and insure that the handler sets the I/O instruction restart field to 00H prior to
returning from the second invocation of the SMI handler.
34.13
SMM MULTIPLE-PROCESSOR CONSIDERATIONS
The following should be noted when designing multiple-processor systems:
•
•
•
Any processor in a multiprocessor system can respond to an SMM.
•
•
The SMI handler will need to initialize the SMBASE for each processor.
•
•
Two or more processors can be executing in SMM at the same time.
Each processor needs its own SMRAM space. This space can be in system memory or in a separate RAM.
The SMRAMs for different processors can be overlapped in the same memory space. The only stipulation is that
each processor needs its own state save area and its own dynamic data storage area. (Also, for the Pentium
and Intel486 processors, the SMBASE address must be located on a 32-KByte boundary.) Code and static data
can be shared among processors. Overlapping SMRAM spaces can be done more efficiently with the P6 family
processors because they do not require that the SMBASE address be on a 32-KByte boundary.
Processors can respond to local SMIs through their SMI# pins or to SMIs received through the APIC interface.
The APIC interface can distribute SMIs to different processors.
When operating Pentium processors in dual processing (DP) mode, the SMIACT# pin is driven only by the MRM
processor and should be sampled with ADS#. For additional details, see Chapter 14 of the Pentium Processor
Family User’s Manual, Volume 1.
SMM is not re-entrant, because the SMRAM State Save Map is fixed relative to the SMBASE. If there is a need to
support two or more processors in SMM mode at the same time then each processor should have dedicated SMRAM
spaces. This can be done by using the SMBASE Relocation feature (see Section 34.11).
34.14
DEFAULT TREATMENT OF SMIS AND SMM WITH VMX OPERATION AND
SMX OPERATION
Under the default treatment, the interactions of SMIs and SMM with VMX operation are few. This section details
those interactions. It also explains how this treatment affects SMX operation.
34.14.1 Default Treatment of SMI Delivery
Ordinary SMI delivery saves processor state into SMRAM and then loads state based on architectural definitions.
Under the default treatment, processors that support VMX operation perform SMI delivery as follows:
enter SMM;
save the following internal to the processor:
CR4.VMXE
an indication of whether the logical processor was in VMX operation (root or non-root)
IF the logical processor is in VMX operation
THEN
save current VMCS pointer internal to the processor;
leave VMX operation;
save VMX-critical state defined below;
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FI;
IF the logical processor supports SMX operation
THEN
save internal to the logical processor an indication of whether the Intel® TXT private space is locked;
IF the TXT private space is unlocked
THEN lock the TXT private space;
FI;
FI;
CR4.VMXE ← 0;
perform ordinary SMI delivery:
save processor state in SMRAM;
set processor state to standard SMM values;1
invalidate linear mappings and combined mappings associated with VPID 0000H (for all PCIDs); combined mappings for VPID 0000H
are invalidated for all EP4TA values (EP4TA is the value of bits 51:12 of EPTP; see Section 28.3);
The pseudocode above makes reference to the saving of VMX-critical state. This state consists of the following:
(1) SS.DPL (the current privilege level); (2) RFLAGS.VM2; (3) the state of blocking by STI and by MOV SS (see
Table 24-3 in Section 24.4.2); (4) the state of virtual-NMI blocking (only if the processor is in VMX non-root operation and the “virtual NMIs” VM-execution control is 1); and (5) an indication of whether an MTF VM exit is pending
(see Section 25.5.2). These data may be saved internal to the processor or in the VMCS region of the current
VMCS. Processors that do not support SMI recognition while there is blocking by STI or by MOV SS need not save
the state of such blocking.
If the logical processor supports the 1-setting of the “enable EPT” VM-execution control and the logical processor
was in VMX non-root operation at the time of an SMI, it saves the value of that control into bit 0 of the 32-bit field
at offset SMBASE + 8000H + 7EE0H (SMBASE + FEE0H; see Table 34-3).3 If the logical processor was not in VMX
non-root operation at the time of the SMI, it saves 0 into that bit. If the logical processor saves 1 into that bit (it
was in VMX non-root operation and the “enable EPT” VM-execution control was 1), it saves the value of the EPT
pointer (EPTP) into the 64-bit field at offset SMBASE + 8000H + 7ED8H (SMBASE + FED8H).
Because SMI delivery causes a logical processor to leave VMX operation, all the controls associated with VMX nonroot operation are disabled in SMM and thus cannot cause VM exits while the logical processor in SMM.
34.14.2 Default Treatment of RSM
Ordinary execution of RSM restores processor state from SMRAM. Under the default treatment, processors that
support VMX operation perform RSM as follows:
IF VMXE = 1 in CR4 image in SMRAM
THEN fail and enter shutdown state;
ELSE
restore state normally from SMRAM;
invalidate linear mappings and combined mappings associated with all VPIDs and all PCIDs; combined mappings are invalidated
for all EP4TA values (EP4TA is the value of bits 51:12 of EPTP; see Section 28.3);
IF the logical processor supports SMX operation andthe Intel® TXT private space was unlocked at the time of the last SMI (as
saved)
THEN unlock the TXT private space;
FI;
CR4.VMXE ← value stored internally;
1. This causes the logical processor to block INIT signals, NMIs, and SMIs.
2. Section 34.14 and Section 34.15 use the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that
support VMX operation also support Intel 64 architecture. For processors that do not support Intel 64 architecture, this notation
refers to the 32-bit forms of these registers (EAX, EIP, ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to the lower 32 bits of the register.
3. “Enable EPT” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution controls
is 0, SMI functions as the “enable EPT” VM-execution control were 0. See Section 24.6.2.
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IF internal storage indicates that the logical processor
had been in VMX operation (root or non-root)
THEN
enter VMX operation (root or non-root);
restore VMX-critical state as defined in Section 34.14.1;
set to their fixed values any bits in CR0 and CR4 whose values must be fixed in VMX operation (see Section 23.8);1
IF RFLAGS.VM = 0 AND (in VMX root operation OR the “unrestricted guest” VM-execution control is 0)2
THEN
CS.RPL ← SS.DPL;
SS.RPL ← SS.DPL;
FI;
restore current VMCS pointer;
FI;
leave SMM;
IF logical processor will be in VMX operation or in SMX operation after RSM
THEN block A20M and leave A20M mode;
FI;
FI;
RSM unblocks SMIs. It restores the state of blocking by NMI (see Table 24-3 in Section 24.4.2) as follows:
•
If the RSM is not to VMX non-root operation or if the “virtual NMIs” VM-execution control will be 0, the state of
NMI blocking is restored normally.
•
If the RSM is to VMX non-root operation and the “virtual NMIs” VM-execution control will be 1, NMIs are not
blocked after RSM. The state of virtual-NMI blocking is restored as part of VMX-critical state.
INIT signals are blocked after RSM if and only if the logical processor will be in VMX root operation.
If RSM returns a logical processor to VMX non-root operation, it re-establishes the controls associated with the
current VMCS. If the “interrupt-window exiting” VM-execution control is 1, a VM exit occurs immediately after RSM
if the enabling conditions apply. The same is true for the “NMI-window exiting” VM-execution control. Such
VM exits occur with their normal priority. See Section 25.2.
If an MTF VM exit was pending at the time of the previous SMI, an MTF VM exit is pending on the instruction
boundary following execution of RSM. The following items detail the treatment of MTF VM exits that may be
pending following RSM:
•
System-management interrupts (SMIs), INIT signals, and higher priority events take priority over these MTF
VM exits. These MTF VM exits take priority over debug-trap exceptions and lower priority events.
•
These MTF VM exits wake the logical processor if RSM caused the logical processor to enter the HLT state (see
Section 34.10). They do not occur if the logical processor just entered the shutdown state.
34.14.3 Protection of CR4.VMXE in SMM
Under the default treatment, CR4.VMXE is treated as a reserved bit while a logical processor is in SMM. Any
attempt by software running in SMM to set this bit causes a general-protection exception. In addition, software
cannot use VMX instructions or enter VMX operation while in SMM.
34.14.4 VMXOFF and SMI Unblocking
The VMXOFF instruction can be executed only with the default treatment (see Section 34.15.1) and only outside
SMM. If SMIs are blocked when VMXOFF is executed, VMXOFF unblocks them unless
1. If the RSM is to VMX non-root operation and both the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls will be 1, CR0.PE and CR0.PG retain the values that were loaded from SMRAM regardless of what is
reported in the capability MSR IA32_VMX_CR0_FIXED0.
2. “Unrestricted guest” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution
controls is 0, VM entry functions as if the “unrestricted guest” VM-execution control were 0. See Section 24.6.2.
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IA32_SMM_MONITOR_CTL[bit 2] is 1 (see Section 34.15.5 for details regarding this MSR).1 Section 34.15.7 identifies a case in which SMIs may be blocked when VMXOFF is executed.
Not all processors allow this bit to be set to 1. Software should consult the VMX capability MSR IA32_VMX_MISC
(see Appendix A.6) to determine whether this is allowed.
34.15
DUAL-MONITOR TREATMENT OF SMIs AND SMM
Dual-monitor treatment is activated through the cooperation of the executive monitor (the VMM that operates
outside of SMM to provide basic virtualization) and the SMM-transfer monitor (STM; the VMM that operates
inside SMM—while in VMX operation—to support system-management functions). Control is transferred to the STM
through VM exits; VM entries are used to return from SMM.
The dual-monitor treatment may not be supported by all processors. Software should consult the VMX capability
MSR IA32_VMX_BASIC (see Appendix A.1) to determine whether it is supported.
34.15.1 Dual-Monitor Treatment Overview
The dual-monitor treatment uses an executive monitor and an SMM-transfer monitor (STM). Transitions from the
executive monitor or its guests to the STM are called SMM VM exits and are discussed in Section 34.15.2. SMM
VM exits are caused by SMIs as well as executions of VMCALL in VMX root operation. The latter allow the executive
monitor to call the STM for service.
The STM runs in VMX root operation and uses VMX instructions to establish a VMCS and perform VM entries to its
own guests. This is done all inside SMM (see Section 34.15.3). The STM returns from SMM, not by using the RSM
instruction, but by using a VM entry that returns from SMM. Such VM entries are described in Section 34.15.4.
Initially, there is no STM and the default treatment (Section 34.14) is used. The dual-monitor treatment is not used
until it is enabled and activated. The steps to do this are described in Section 34.15.5 and Section 34.15.6.
It is not possible to leave VMX operation under the dual-monitor treatment; VMXOFF will fail if executed. The dualmonitor treatment must be deactivated first. The STM deactivates dual-monitor treatment using a VM entry that
returns from SMM with the “deactivate dual-monitor treatment” VM-entry control set to 1 (see Section 34.15.7).
The executive monitor configures any VMCS that it uses for VM exits to the executive monitor. SMM VM exits, which
transfer control to the STM, use a different VMCS. Under the dual-monitor treatment, each logical processor uses
a separate VMCS called the SMM-transfer VMCS. When the dual-monitor treatment is active, the logical
processor maintains another VMCS pointer called the SMM-transfer VMCS pointer. The SMM-transfer VMCS
pointer is established when the dual-monitor treatment is activated.
34.15.2 SMM VM Exits
An SMM VM exit is a VM exit that begins outside SMM and that ends in SMM.
Unlike other VM exits, SMM VM exits can begin in VMX root operation. SMM VM exits result from the arrival of an
SMI outside SMM or from execution of VMCALL in VMX root operation outside SMM. Execution of VMCALL in VMX
root operation causes an SMM VM exit only if the valid bit is set in the IA32_SMM_MONITOR_CTL MSR (see Section
34.15.5).
Execution of VMCALL in VMX root operation causes an SMM VM exit even under the default treatment. This SMM
VM exit activates the dual-monitor treatment (see Section 34.15.6).
Differences between SMM VM exits and other VM exits are detailed in Sections 34.15.2.1 through 34.15.2.5.
Differences between SMM VM exits that activate the dual-monitor treatment and other SMM VM exits are described
in Section 34.15.6.
1. Setting IA32_SMM_MONITOR_CTL[bit 2] to 1 prevents VMXOFF from unblocking SMIs regardless of the value of the register’s valid
bit (bit 0).
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34.15.2.1 Architectural State Before a VM Exit
System-management interrupts (SMIs) that cause SMM VM exits always do so directly. They do not save state to
SMRAM as they do under the default treatment.
34.15.2.2 Updating the Current-VMCS and Executive-VMCS Pointers
SMM VM exits begin by performing the following steps:
1. The executive-VMCS pointer field in the SMM-transfer VMCS is loaded as follows:
— If the SMM VM exit commenced in VMX non-root operation, it receives the current-VMCS pointer.
— If the SMM VM exit commenced in VMX root operation, it receives the VMXON pointer.
2. The current-VMCS pointer is loaded with the value of the SMM-transfer VMCS pointer.
The last step ensures that the current VMCS is the SMM-transfer VMCS. VM-exit information is recorded in that
VMCS, and VM-entry control fields in that VMCS are updated. State is saved into the guest-state area of that VMCS.
The VM-exit controls and host-state area of that VMCS determine how the VM exit operates.
34.15.2.3 Recording VM-Exit Information
SMM VM exits differ from other VM exit with regard to the way they record VM-exit information. The differences
follow.
•
Exit reason.
— Bits 15:0 of this field contain the basic exit reason. The field is loaded with the reason for the SMM VM exit:
I/O SMI (an SMI arrived immediately after retirement of an I/O instruction), other SMI, or VMCALL. See
Appendix C, “VMX Basic Exit Reasons”.
— SMM VM exits are the only VM exits that may occur in VMX root operation. Because the SMM-transfer
monitor may need to know whether it was invoked from VMX root or VMX non-root operation, this
information is stored in bit 29 of the exit-reason field (see Table 24-14 in Section 24.9.1). The bit is set by
SMM VM exits from VMX root operation.
— If the SMM VM exit occurred in VMX non-root operation and an MTF VM exit was pending, bit 28 of the exitreason field is set; otherwise, it is cleared.
— Bits 27:16 and bits 31:30 are cleared.
•
Exit qualification. For an SMM VM exit due an SMI that arrives immediately after the retirement of an I/O
instruction, the exit qualification contains information about the I/O instruction that retired immediately before
the SMI. It has the format given in Table 34-9.
Table 34-9. Exit Qualification for SMIs That Arrive Immediately After the Retirement of an I/O Instruction
Bit Position(s)
Contents
2:0
Size of access:
0 = 1-byte
1 = 2-byte
3 = 4-byte
Other values not used.
3
Direction of the attempted access (0 = OUT, 1 = IN)
4
String instruction (0 = not string; 1 = string)
5
REP prefixed (0 = not REP; 1 = REP)
6
Operand encoding (0 = DX, 1 = immediate)
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Table 34-9. Exit Qualification for SMIs That Arrive Immediately After the Retirement of an I/O Instruction (Contd.)
Bit Position(s)
Contents
15:7
Reserved (cleared to 0)
31:16
Port number (as specified in the I/O instruction)
63:32
Reserved (cleared to 0). These bits exist only on processors
that support Intel 64 architecture.
•
Guest linear address. This field is used for VM exits due to SMIs that arrive immediately after the retirement
of an INS or OUTS instruction for which the relevant segment (ES for INS; DS for OUTS unless overridden by
an instruction prefix) is usable. The field receives the value of the linear address generated by ES:(E)DI (for
INS) or segment:(E)SI (for OUTS; the default segment is DS but can be overridden by a segment override
prefix) at the time the instruction started. If the relevant segment is not usable, the value is undefined. On
processors that support Intel 64 architecture, bits 63:32 are clear if the logical processor was not in 64-bit
mode before the VM exit.
•
I/O RCX, I/O RSI, I/O RDI, and I/O RIP. For an SMM VM exit due an SMI that arrives immediately after
the retirement of an I/O instruction, these fields receive the values that were in RCX, RSI, RDI, and RIP, respectively, before the I/O instruction executed. Thus, the value saved for I/O RIP addresses the I/O instruction.
34.15.2.4 Saving Guest State
SMM VM exits save the contents of the SMBASE register into the corresponding field in the guest-state area.
The value of the VMX-preemption timer is saved into the corresponding field in the guest-state area if the “save
VMX-preemption timer value” VM-exit control is 1. That field becomes undefined if, in addition, either the SMM
VM exit is from VMX root operation or the SMM VM exit is from VMX non-root operation and the “activate VMXpreemption timer” VM-execution control is 0.
34.15.2.5 Updating Non-Register State
SMM VM exits affect the non-register state of a logical processor as follows:
•
SMM VM exits cause non-maskable interrupts (NMIs) to be blocked; they may be unblocked through execution
of IRET or through a VM entry (depending on the value loaded for the interruptibility state and the setting of
the “virtual NMIs” VM-execution control).
•
SMM VM exits cause SMIs to be blocked; they may be unblocked by a VM entry that returns from SMM (see
Section 34.15.4).
SMM VM exits invalidate linear mappings and combined mappings associated with VPID 0000H for all PCIDs.
Combined mappings for VPID 0000H are invalidated for all EP4TA values (EP4TA is the value of bits 51:12 of EPTP;
see Section 28.3). (Ordinary VM exits are not required to perform such invalidation if the “enable VPID” VM-execution control is 1; see Section 27.5.5.)
34.15.3 Operation of the SMM-Transfer Monitor
Once invoked, the SMM-transfer monitor (STM) is in VMX root operation and can use VMX instructions to configure
VMCSs and to cause VM entries to virtual machines supported by those structures. As noted in Section 34.15.1, the
VMXOFF instruction cannot be used under the dual-monitor treatment and thus cannot be used by the STM.
The RSM instruction also cannot be used under the dual-monitor treatment. As noted in Section 25.1.3, it causes
a VM exit if executed in SMM in VMX non-root operation. If executed in VMX root operation, it causes an invalidopcode exception. The STM uses VM entries to return from SMM (see Section 34.15.4).
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34.15.4 VM Entries that Return from SMM
The SMM-transfer monitor (STM) returns from SMM using a VM entry with the “entry to SMM” VM-entry control
clear. VM entries that return from SMM reverse the effects of an SMM VM exit (see Section 34.15.2).
VM entries that return from SMM may differ from other VM entries in that they do not necessarily enter VMX nonroot operation. If the executive-VMCS pointer field in the current VMCS contains the VMXON pointer, the logical
processor remains in VMX root operation after VM entry.
For differences between VM entries that return from SMM and other VM entries see Sections 34.15.4.1 through
34.15.4.10.
34.15.4.1 Checks on the Executive-VMCS Pointer Field
VM entries that return from SMM perform the following checks on the executive-VMCS pointer field in the current
VMCS:
•
•
•
Bits 11:0 must be 0.
The pointer must not set any bits beyond the processor’s physical-address width.1,2
The 32 bits located in memory referenced by the physical address in the pointer must contain the processor’s
VMCS revision identifier (see Section 24.2).
The checks above are performed before the checks described in Section 34.15.4.2 and before any of the following
checks:
•
'If the “deactivate dual-monitor treatment” VM-entry control is 0 and the executive-VMCS pointer field does not
contain the VMXON pointer, the launch state of the executive VMCS (the VMCS referenced by the executiveVMCS pointer field) must be launched (see Section 24.11.3).
•
If the “deactivate dual-monitor treatment” VM-entry control is 1, the executive-VMCS pointer field must
contain the VMXON pointer (see Section 34.15.7).3
34.15.4.2 Checks on VM-Execution Control Fields
VM entries that return from SMM differ from other VM entries with regard to the checks performed on the VMexecution control fields specified in Section 26.2.1.1. They do not apply the checks to the current VMCS. Instead,
VM-entry behavior depends on whether the executive-VMCS pointer field contains the VMXON pointer:
•
If the executive-VMCS pointer field contains the VMXON pointer (the VM entry remains in VMX root operation),
the checks are not performed at all.
•
If the executive-VMCS pointer field does not contain the VMXON pointer (the VM entry enters VMX non-root
operation), the checks are performed on the VM-execution control fields in the executive VMCS (the VMCS
referenced by the executive-VMCS pointer field in the current VMCS). These checks are performed after
checking the executive-VMCS pointer field itself (for proper alignment).
Other VM entries ensure that, if “activate VMX-preemption timer” VM-execution control is 0, the “save VMXpreemption timer value” VM-exit control is also 0. This check is not performed by VM entries that return from SMM.
34.15.4.3 Checks on VM-Entry Control Fields
VM entries that return from SMM differ from other VM entries with regard to the checks performed on the VM-entry
control fields specified in Section 26.2.1.3.
1. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address
width is returned in bits 7:0 of EAX.
2. If IA32_VMX_BASIC[48] is read as 1, this pointer must not set any bits in the range 63:32; see Appendix A.1.
3. The STM can determine the VMXON pointer by reading the executive-VMCS pointer field in the current VMCS after the SMM VM exit
that activates the dual-monitor treatment.
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Specifically, if the executive-VMCS pointer field contains the VMXON pointer (the VM entry remains in VMX root
operation), the VM-entry interruption-information field must not indicate injection of a pending MTF VM exit (see
Section 26.5.2). Specifically, the following cannot all be true for that field:
•
•
•
the valid bit (bit 31) is 1
the interruption type (bits 10:8) is 7 (other event); and
the vector (bits 7:0) is 0 (pending MTF VM exit).
34.15.4.4 Checks on the Guest State Area
Section 26.3.1 specifies checks performed on fields in the guest-state area of the VMCS. Some of these checks are
conditioned on the settings of certain VM-execution controls (e.g., “virtual NMIs” or “unrestricted guest”).
VM entries that return from SMM modify these checks based on whether the executive-VMCS pointer field contains
the VMXON pointer:1
•
If the executive-VMCS pointer field contains the VMXON pointer (the VM entry remains in VMX root operation),
the checks are performed as all relevant VM-execution controls were 0. (As a result, some checks may not be
performed at all.)
•
If the executive-VMCS pointer field does not contain the VMXON pointer (the VM entry enters VMX non-root
operation), this check is performed based on the settings of the VM-execution controls in the executive VMCS
(the VMCS referenced by the executive-VMCS pointer field in the current VMCS).
For VM entries that return from SMM, the activity-state field must not indicate the wait-for-SIPI state if the executive-VMCS pointer field contains the VMXON pointer (the VM entry is to VMX root operation).
34.15.4.5 Loading Guest State
VM entries that return from SMM load the SMBASE register from the SMBASE field.
VM entries that return from SMM invalidate linear mappings and combined mappings associated with all VPIDs.
Combined mappings are invalidated for all EP4TA values (EP4TA is the value of bits 51:12 of EPTP; see Section
28.3). (Ordinary VM entries are required to perform such invalidation only for VPID 0000H and are not required to
do even that if the “enable VPID” VM-execution control is 1; see Section 26.3.2.5.)
34.15.4.6 VMX-Preemption Timer
A VM entry that returns from SMM activates the VMX-preemption timer only if the executive-VMCS pointer field
does not contain the VMXON pointer (the VM entry enters VMX non-root operation) and the “activate VMX-preemption timer” VM-execution control is 1 in the executive VMCS (the VMCS referenced by the executive-VMCS pointer
field). In this case, VM entry starts the VMX-preemption timer with the value in the VMX-preemption timer-value
field in the current VMCS.
34.15.4.7 Updating the Current-VMCS and SMM-Transfer VMCS Pointers
Successful VM entries (returning from SMM) load the SMM-transfer VMCS pointer with the current-VMCS pointer.
Following this, they load the current-VMCS pointer from a field in the current VMCS:
•
If the executive-VMCS pointer field contains the VMXON pointer (the VM entry remains in VMX root operation),
the current-VMCS pointer is loaded from the VMCS-link pointer field.
•
If the executive-VMCS pointer field does not contain the VMXON pointer (the VM entry enters VMX non-root
operation), the current-VMCS pointer is loaded with the value of the executive-VMCS pointer field.
If the VM entry successfully enters VMX non-root operation, the VM-execution controls in effect after the VM entry
are those from the new current VMCS. This includes any structures external to the VMCS referenced by VM-execution control fields.
1. The STM can determine the VMXON pointer by reading the executive-VMCS pointer field in the current VMCS after the SMM VM exit
that activates the dual-monitor treatment.
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The updating of these VMCS pointers occurs before event injection. Event injection is determined, however, by the
VM-entry control fields in the VMCS that was current when the VM entry commenced.
34.15.4.8 VM Exits Induced by VM Entry
Section 26.5.1.2 describes how the event-delivery process invoked by event injection may lead to a VM exit.
Section 26.6.3 to Section 26.6.7 describe other situations that may cause a VM exit to occur immediately after a
VM entry.
Whether these VM exits occur is determined by the VM-execution control fields in the current VMCS. For VM entries
that return from SMM, they can occur only if the executive-VMCS pointer field does not contain the VMXON pointer
(the VM entry enters VMX non-root operation).
In this case, determination is based on the VM-execution control fields in the VMCS that is current after the
VM entry. This is the VMCS referenced by the value of the executive-VMCS pointer field at the time of the VM entry
(see Section 34.15.4.7). This VMCS also controls the delivery of such VM exits. Thus, VM exits induced by a
VM entry returning from SMM are to the executive monitor and not to the STM.
34.15.4.9 SMI Blocking
VM entries that return from SMM determine the blocking of system-management interrupts (SMIs) as follows:
•
If the “deactivate dual-monitor treatment” VM-entry control is 0, SMIs are blocked after VM entry if and only if
the bit 2 in the interruptibility-state field is 1.
•
If the “deactivate dual-monitor treatment” VM-entry control is 1, the blocking of SMIs depends on whether the
logical processor is in SMX operation:1
— If the logical processor is in SMX operation, SMIs are blocked after VM entry.
— If the logical processor is outside SMX operation, SMIs are unblocked after VM entry.
VM entries that return from SMM and that do not deactivate the dual-monitor treatment may leave SMIs blocked.
This feature exists to allow the STM to invoke functionality outside of SMM without unblocking SMIs.
34.15.4.10 Failures of VM Entries That Return from SMM
Section 26.7 describes the treatment of VM entries that fail during or after loading guest state. Such failures record
information in the VM-exit information fields and load processor state as would be done on a VM exit. The VMCS
used is the one that was current before the VM entry commenced. Control is thus transferred to the STM and the
logical processor remains in SMM.
34.15.5 Enabling the Dual-Monitor Treatment
Code and data for the SMM-transfer monitor (STM) reside in a region of SMRAM called the monitor segment
(MSEG). Code running in SMM determines the location of MSEG and establishes its content. This code is also
responsible for enabling the dual-monitor treatment.
SMM code enables the dual-monitor treatment and specifies the location of MSEG by writing to the
IA32_SMM_MONITOR_CTL MSR (index 9BH). The MSR has the following format:
•
Bit 0 is the register’s valid bit. The STM may be invoked using VMCALL only if this bit is 1. Because VMCALL is
used to activate the dual-monitor treatment (see Section 34.15.6), the dual-monitor treatment cannot be
activated if the bit is 0. This bit is cleared when the logical processor is reset.
•
Bit 1 is reserved.
1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last
execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D.
34-24 Vol. 3C
SYSTEM MANAGEMENT MODE
•
Bit 2 determines whether executions of VMXOFF unblock SMIs under the default treatment of SMIs and SMM.
Executions of VMXOFF unblock SMIs unless bit 2 is 1 (the value of bit 0 is irrelevant). See Section 34.14.4.
Certain leaf functions of the GETSEC instruction clear this bit (see Chapter 6, “Safer Mode Extensions
Reference,” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D).
•
•
Bits 11:3 are reserved.
•
Bits 63:32 are reserved.
Bits 31:12 contain a value that, when shifted left 12 bits, is the physical address of MSEG (the MSEG base
address).
The following items detail use of this MSR:
•
The IA32_SMM_MONITOR_CTL MSR is supported only on processors that support the dual-monitor treatment.1
On other processors, accesses to the MSR using RDMSR or WRMSR generate a general-protection fault
(#GP(0)).
•
A write to the IA32_SMM_MONITOR_CTL MSR using WRMSR generates a general-protection fault (#GP(0)) if
executed outside of SMM or if an attempt is made to set any reserved bit. An attempt to write to the
IA32_SMM_MONITOR_CTL MSR fails if made as part of a VM exit that does not end in SMM or part of a
VM entry that does not begin in SMM.
•
Reads from the IA32_SMM_MONITOR_CTL MSR using RDMSR are allowed any time RDMSR is allowed. The
MSR may be read as part of any VM exit.
•
The dual-monitor treatment can be activated only if the valid bit in the MSR is set to 1.
The 32 bytes located at the MSEG base address are called the MSEG header. The format of the MSEG header is
given in Table 34-10 (each field is 32 bits).
Table 34-10. Format of MSEG Header
Byte Offset
Field
0
MSEG-header revision identifier
4
SMM-transfer monitor features
8
GDTR limit
12
GDTR base offset
16
CS selector
20
EIP offset
24
ESP offset
28
CR3 offset
To ensure proper behavior in VMX operation, software should maintain the MSEG header in writeback cacheable
memory. Future implementations may allow or require a different memory type.2 Software should consult the VMX
capability MSR IA32_VMX_BASIC (see Appendix A.1).
SMM code should enable the dual-monitor treatment (by setting the valid bit in IA32_SMM_MONITOR_CTL MSR)
only after establishing the content of the MSEG header as follows:
1. Software should consult the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1) to determine whether the dual-monitor
treatment is supported.
2. Alternatively, software may map the MSEG header with the UC memory type; this may be necessary, depending on how memory is
organized. Doing so is strongly discouraged unless necessary as it will cause the performance of transitions using those structures
to suffer significantly. In addition, the processor will continue to use the memory type reported in the VMX capability MSR
IA32_VMX_BASIC with exceptions noted in Appendix A.1.
Vol. 3C 34-25
SYSTEM MANAGEMENT MODE
•
Bytes 3:0 contain the MSEG revision identifier. Different processors may use different MSEG revision identifiers. These identifiers enable software to avoid using an MSEG header formatted for one processor on a
processor that uses a different format. Software can discover the MSEG revision identifier that a processor uses
by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6).
•
Bytes 7:4 contain the SMM-transfer monitor features field. Bits 31:1 of this field are reserved and must be
zero. Bit 0 of the field is the IA-32e mode SMM feature bit. It indicates whether the logical processor will be
in IA-32e mode after the STM is activated (see Section 34.15.6).
•
Bytes 31:8 contain fields that determine how processor state is loaded when the STM is activated (see Section
34.15.6.5). SMM code should establish these fields so that activating of the STM invokes the STM’s initialization
code.
34.15.6 Activating the Dual-Monitor Treatment
The dual-monitor treatment may be enabled by SMM code as described in Section 34.15.5. The dual-monitor treatment is activated only if it is enabled and only by the executive monitor. The executive monitor activates the dualmonitor treatment by executing VMCALL in VMX root operation.
When VMCALL activates the dual-monitor treatment, it causes an SMM VM exit. Differences between this SMM
VM exit and other SMM VM exits are discussed in Sections 34.15.6.1 through 34.15.6.6. See also “VMCALL—Call to
VM Monitor” in Chapter 30.
34.15.6.1 Initial Checks
An execution of VMCALL attempts to activate the dual-monitor treatment if (1) the processor supports the dualmonitor treatment;1 (2) the logical processor is in VMX root operation; (3) the logical processor is outside SMM and
the valid bit is set in the IA32_SMM_MONITOR_CTL MSR; (4) the logical processor is not in virtual-8086 mode and
not in compatibility mode; (5) CPL = 0; and (6) the dual-monitor treatment is not active.
Such an execution of VMCALL begins with some initial checks. These checks are performed before updating the
current-VMCS pointer and the executive-VMCS pointer field (see Section 34.15.2.2).
The VMCS that manages SMM VM exit caused by this VMCALL is the current VMCS established by the executive
monitor. The VMCALL performs the following checks on the current VMCS in the order indicated:
1. There must be a current VMCS pointer.
2. The launch state of the current VMCS must be clear.
3. Reserved bits in the VM-exit controls in the current VMCS must be set properly. Software may consult the VMX
capability MSR IA32_VMX_EXIT_CTLS to determine the proper settings (see Appendix A.4).
If any of these checks fail, subsequent checks are skipped and VMCALL fails. If all these checks succeed, the logical
processor uses the IA32_SMM_MONITOR_CTL MSR to determine the base address of MSEG. The following checks
are performed in the order indicated:
1. The logical processor reads the 32 bits at the base of MSEG and compares them to the processor’s MSEG
revision identifier.
2. The logical processor reads the SMM-transfer monitor features field:
— Bit 0 of the field is the IA-32e mode SMM feature bit, and it indicates whether the logical processor will be
in IA-32e mode after the SMM-transfer monitor (STM) is activated.
•
If the VMCALL is executed on a processor that does not support Intel 64 architecture, the IA-32e mode
SMM feature bit must be 0.
•
If the VMCALL is executed in 64-bit mode, the IA-32e mode SMM feature bit must be 1.
— Bits 31:1 of this field are currently reserved and must be zero.
If any of these checks fail, subsequent checks are skipped and the VMCALL fails.
1. Software should consult the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1) to determine whether the dual-monitor
treatment is supported.
34-26 Vol. 3C
SYSTEM MANAGEMENT MODE
34.15.6.2 Updating the Current-VMCS and Executive-VMCS Pointers
Before performing the steps in Section 34.15.2.2, SMM VM exits that activate the dual-monitor treatment begin by
loading the SMM-transfer VMCS pointer with the value of the current-VMCS pointer.
34.15.6.3 Saving Guest State
As noted in Section 34.15.2.4, SMM VM exits save the contents of the SMBASE register into the corresponding field
in the guest-state area. While this is true also for SMM VM exits that activate the dual-monitor treatment, the
VMCS used for those VM exits exists outside SMRAM.
The SMM-transfer monitor (STM) can also discover the current value of the SMBASE register by using the RDMSR
instruction to read the IA32_SMBASE MSR (MSR address 9EH). The following items detail use of this MSR:
•
•
The MSR is supported only if IA32_VMX_MISC[15] = 1 (see Appendix A.6).
•
A read from the IA32_SMBASE MSR using RDMSR generates a general-protection fault (#GP(0)) if executed
outside of SMM. An attempt to read from the IA32_SMBASE MSR fails if made as part of a VM exit that does not
end in SMM.
A write to the IA32_SMBASE MSR using WRMSR generates a general-protection fault (#GP(0)). An attempt to
write to the IA32_SMBASE MSR fails if made as part of a VM exit or part of a VM entry.
34.15.6.4 Saving MSRs
The VM-exit MSR-store area is not used by SMM VM exits that activate the dual-monitor treatment. No MSRs are
saved into that area.
34.15.6.5 Loading Host State
The VMCS that is current during an SMM VM exit that activates the dual-monitor treatment was established by the
executive monitor. It does not contain the VM-exit controls and host state required to initialize the STM. For this
reason, such SMM VM exits do not load processor state as described in Section 27.5. Instead, state is set to fixed
values or loaded based on the content of the MSEG header (see Table 34-10):
•
CR0 is set to as follows:
— PG, NE, ET, MP, and PE are all set to 1.
— CD and NW are left unchanged.
— All other bits are cleared to 0.
•
CR3 is set as follows:
— Bits 63:32 are cleared on processors that support IA-32e mode.
— Bits 31:12 are set to bits 31:12 of the sum of the MSEG base address and the CR3-offset field in the MSEG
header.
— Bits 11:5 and bits 2:0 are cleared (the corresponding bits in the CR3-offset field in the MSEG header are
ignored).
— Bits 4:3 are set to bits 4:3 of the CR3-offset field in the MSEG header.
•
CR4 is set as follows:
— MCE, PGE, and PCIDE are cleared.
— PAE is set to the value of the IA-32e mode SMM feature bit.
— If the IA-32e mode SMM feature bit is clear, PSE is set to 1 if supported by the processor; if the bit is set,
PSE is cleared.
— All other bits are unchanged.
•
•
DR7 is set to 400H.
The IA32_DEBUGCTL MSR is cleared to 00000000_00000000H.
Vol. 3C 34-27
SYSTEM MANAGEMENT MODE
•
The registers CS, SS, DS, ES, FS, and GS are loaded as follows:
— All registers are usable.
— CS.selector is loaded from the corresponding field in the MSEG header (the high 16 bits are ignored), with
bits 2:0 cleared to 0. If the result is 0000H, CS.selector is set to 0008H.
— The selectors for SS, DS, ES, FS, and GS are set to CS.selector+0008H. If the result is 0000H (if the CS
selector was FFF8H), these selectors are instead set to 0008H.
— The base addresses of all registers are cleared to zero.
— The segment limits for all registers are set to FFFFFFFFH.
— The AR bytes for the registers are set as follows:
•
•
•
•
•
•
•
•
•
CS.Type is set to 11 (execute/read, accessed, non-conforming code segment).
For SS, DS, ES, FS, and GS, the Type is set to 3 (read/write, accessed, expand-up data segment).
The S bits for all registers are set to 1.
The DPL for each register is set to 0.
The P bits for all registers are set to 1.
On processors that support Intel 64 architecture, CS.L is loaded with the value of the IA-32e mode SMM
feature bit.
CS.D is loaded with the inverse of the value of the IA-32e mode SMM feature bit.
For each of SS, DS, ES, FS, and GS, the D/B bit is set to 1.
The G bits for all registers are set to 1.
•
LDTR is unusable. The LDTR selector is cleared to 0000H, and the register is otherwise undefined (although the
base address is always canonical)
•
GDTR.base is set to the sum of the MSEG base address and the GDTR base-offset field in the MSEG header
(bits 63:32 are always cleared on processors that support IA-32e mode). GDTR.limit is set to the corresponding field in the MSEG header (the high 16 bits are ignored).
•
•
IDTR.base is unchanged. IDTR.limit is cleared to 0000H.
•
RSP is set to the sum of the MSEG base address and the value of the RSP-offset field in the MSEG header
(bits 63:32 are always cleared on logical processor that supports IA-32e mode).
•
•
•
RFLAGS is cleared, except bit 1, which is always set.
RIP is set to the sum of the MSEG base address and the value of the RIP-offset field in the MSEG header
(bits 63:32 are always cleared on logical processors that support IA-32e mode).
The logical processor is left in the active state.
Event blocking after the SMM VM exit is as follows:
— There is no blocking by STI or by MOV SS.
— There is blocking by non-maskable interrupts (NMIs) and by SMIs.
•
•
There are no pending debug exceptions after the SMM VM exit.
For processors that support IA-32e mode, the IA32_EFER MSR is modified so that LME and LMA both contain
the value of the IA-32e mode SMM feature bit.
If any of CR3[63:5], CR4.PAE, CR4.PSE, or IA32_EFER.LMA is changing, the TLBs are updated so that, after
VM exit, the logical processor does not use translations that were cached before the transition. This is not necessary for changes that would not affect paging due to the settings of other bits (for example, changes to CR4.PSE if
IA32_EFER.LMA was 1 before and after the transition).
34.15.6.6 Loading MSRs
The VM-exit MSR-load area is not used by SMM VM exits that activate the dual-monitor treatment. No MSRs are
loaded from that area.
34-28 Vol. 3C
SYSTEM MANAGEMENT MODE
34.15.7 Deactivating the Dual-Monitor Treatment
The SMM-transfer monitor may deactivate the dual-monitor treatment and return the processor to default treatment of SMIs and SMM (see Section 34.14). It does this by executing a VM entry with the “deactivate dual-monitor
treatment” VM-entry control set to 1.
As noted in Section 26.2.1.3 and Section 34.15.4.1, an attempt to deactivate the dual-monitor treatment fails in
the following situations: (1) the processor is not in SMM; (2) the “entry to SMM” VM-entry control is 1; or (3) the
executive-VMCS pointer does not contain the VMXON pointer (the VM entry is to VMX non-root operation).
As noted in Section 34.15.4.9, VM entries that deactivate the dual-monitor treatment ignore the SMI bit in the
interruptibility-state field of the guest-state area. Instead, the blocking of SMIs following such a VM entry depends
on whether the logical processor is in SMX operation:1
•
If the logical processor is in SMX operation, SMIs are blocked after VM entry. SMIs may later be unblocked by
the VMXOFF instruction (see Section 34.14.4) or by certain leaf functions of the GETSEC instruction (see
Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2D).
•
If the logical processor is outside SMX operation, SMIs are unblocked after VM entry.
34.16
SMI AND PROCESSOR EXTENDED STATE MANAGEMENT
On processors that support processor extended states using XSAVE/XRSTOR (see Chapter 13, “Managing State
Using the XSAVE Feature Set” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1),
the processor does not save any XSAVE/XRSTOR related state on an SMI. It is the responsibility of the SMI handler
code to properly preserve the state information (including CR4.OSXSAVE, XCR0, and possibly processor extended
states using XSAVE/XRSTOR). Therefore, the SMI handler must follow the rules described in Chapter 13,
“Managing State Using the XSAVE Feature Set” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1.
34.17
MODEL-SPECIFIC SYSTEM MANAGEMENT ENHANCEMENT
This section describes enhancement of system management features that apply only to the 4th generation Intel
Core processors. These features are model-specific. BIOS and SMM handler must use CPUID to enumerate
DisplayFamily_DisplayModel signature when programming with these interfaces.
34.17.1
SMM Handler Code Access Control
The BIOS may choose to restrict the address ranges of code that SMM handler executes. When SMM handler code
execution check is enabled, an attempt by the SMM handler to execute outside the ranges specified by SMRR (see
Section 34.4.2.1) will cause the assertion of an unrecoverable machine check exception (MCE).
The interface to enable SMM handler code access check resides in a per-package scope model-specific register
MSR_SMM_FEATURE_CONTROL at address 4E0H. An attempt to access MSR_SMM_FEATURE_CONTROL outside of
SMM will cause a #GP. Writes to MSR_SMM_FEATURE_CONTROL is further protected by configuration interface of
MSR_SMM_MCA_CAP at address 17DH.
Details of the interface of MSR_SMM_FEATURE_CONTROL and MSR_SMM_MCA_CAP are described in Table 35-27.
1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last
execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B.
Vol. 3C 34-29
SYSTEM MANAGEMENT MODE
34.17.2
SMI Delivery Delay Reporting
Entry into the system management mode occurs at instruction boundary. In situations where a logical processor is
executing an instruction involving a long flow of internal operations, servicing an SMI by that logical processor will
be delayed. Delayed servicing of SMI of each logical processor due to executing long flows of internal operation in
a physical processor can be queried via a package-scope register MSR_SMM_DELAYED at address 4E2H.
The interface to enable reporting of SMI delivery delay due to long internal flows resides in a per-package scope
model-specific register MSR_SMM_DELAYED. An attempt to access MSR_SMM_DELAYED outside of SMM will cause
a #GP. Availability to MSR_SMM_DELAYED is protected by configuration interface of MSR_SMM_MCA_CAP at
address 17DH.
Details of the interface of MSR_SMM_DELAYED and MSR_SMM_MCA_CAP are described in Table 35-27.
34.17.3
Blocked SMI Reporting
A logical processor may have entered into a state and blocked from servicing other interrupts (including SMI).
Logical processors in a physical processor that are blocked in serving SMI can be queried in a package-scope
register MSR_SMM_BLOCKED at address 4E3H. An attempt to access MSR_SMM_BLOCKED outside of SMM will
cause a #GP.
Details of the interface of MSR_SMM_BLOCKED is described in Table 35-27.
34-30 Vol. 3C
CHAPTER 35
MODEL-SPECIFIC REGISTERS (MSRS)
This chapter lists MSRs across Intel processor families. All MSRs listed can be read with the RDMSR and written with
the WRMSR instructions.
Register addresses are given in both hexadecimal and decimal. The register name is the mnemonic register name
and the bit description describes individual bits in registers.
Model specific registers and its bit-fields may be supported for a finite range of processor families/models. To
distinguish between different processor family and/or models, software must use CPUID.01H leaf function to query
the combination of DisplayFamily and DisplayModel to determine model-specific availability of MSRs (see CPUID
instruction in Chapter 3, “Instruction Set Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). Table 35-1 lists the signature values of DisplayFamily and DisplayModel for various
processor families or processor number series.
Table 35-1. CPUID Signature Values of DisplayFamily_DisplayModel
DisplayFamily_DisplayModel Processor Families/Processor Number Series
06_57H
Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series
06_85H
Future Intel® Xeon Phi™ Processor
06_8EH, 06_9EH
7th generation Intel® Core™ processors based on Kaby Lake microarchitecture
06_55H
Future Intel® Xeon® Processors
06_4EH, 06_5EH
6th generation Intel Core processors and Intel Xeon processor E3-1500m v5 product family and E31200 v5 product family based on Skylake microarchitecture
06_56H
Intel Xeon processor D-1500 product family based on Broadwell microarchitecture
06_4FH
Intel Xeon processor E5 v4 Family based on Broadwell microarchitecture, Intel Xeon processor E7 v4
Family, Intel Core i7-69xx Processor Extreme Edition
06_47H
5th generation Intel Core processors, Intel Xeon processor E3-1200 v4 product family based on
Broadwell microarchitecture
06_3DH
Intel Core M-5xxx Processor, 5th generation Intel Core processors based on Broadwell
microarchitecture
06_3FH
Intel Xeon processor E5-4600/2600/1600 v3 product families, Intel Xeon processor E7 v3 product
families based on Haswell-E microarchitecture, Intel Core i7-59xx Processor Extreme Edition
06_3CH, 06_45H, 06_46H
4th Generation Intel Core processor and Intel Xeon processor E3-1200 v3 product family based on
Haswell microarchitecture
06_3EH
Intel Xeon processor E7-8800/4800/2800 v2 product families based on Ivy Bridge-E
microarchitecture
06_3EH
Intel Xeon processor E5-2600/1600 v2 product families and Intel Xeon processor E5-2400 v2
product family based on Ivy Bridge-E microarchitecture, Intel Core i7-49xx Processor Extreme Edition
06_3AH
3rd Generation Intel Core Processor and Intel Xeon processor E3-1200 v2 product family based on Ivy
Bridge microarchitecture
06_2DH
Intel Xeon processor E5 Family based on Intel microarchitecture code name Sandy Bridge, Intel Core
i7-39xx Processor Extreme Edition
06_2FH
Intel Xeon Processor E7 Family
06_2AH
Intel Xeon processor E3-1200 product family; 2nd Generation Intel Core i7, i5, i3 Processors 2xxx
Series
06_2EH
Intel Xeon processor 7500, 6500 series
06_25H, 06_2CH
Intel Xeon processors 3600, 5600 series, Intel Core i7, i5 and i3 Processors
Vol. 3C 35-1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-1. CPUID Signature (Contd.)Values of DisplayFamily_DisplayModel (Contd.)
DisplayFamily_DisplayModel Processor Families/Processor Number Series
06_1EH, 06_1FH
Intel Core i7 and i5 Processors
06_1AH
Intel Core i7 Processor, Intel Xeon processor 3400, 3500, 5500 series
06_1DH
Intel Xeon processor MP 7400 series
06_17H
Intel Xeon processor 3100, 3300, 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000
series
06_0FH
Intel Xeon processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series,
Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel
Pentium dual-core processors
06_0EH
Intel Core Duo, Intel Core Solo processors
06_0DH
Intel Pentium M processor
06_5FH
Future Intel® Atom™ processors based on Goldmont Microarchitecture (code name Denverton)
06_5CH
Next Generation Intel Atom processors based on Goldmont Microarchitecture
06_4CH
Intel Atom processor X7-Z8000 and X5-Z8000 series based on Airmont Microarchitecture
06_5DH
Intel Atom processor X3-C3000 based on Silvermont Microarchitecture
06_5AH
Intel Atom processor Z3500 series
06_4AH
Intel Atom processor Z3400 series
06_37H
Intel Atom processor E3000 series, Z3600 series, Z3700 series
06_4DH
Intel Atom processor C2000 series
06_36H
Intel Atom processor S1000 Series
06_1CH, 06_26H, 06_27H,
06_35H, 06_36H
Intel Atom processor family, Intel Atom processor D2000, N2000, E2000, Z2000, C1000 series
0F_06H
Intel Xeon processor 7100, 5000 Series, Intel Xeon Processor MP, Intel Pentium 4, Pentium D
processors
0F_03H, 0F_04H
Intel Xeon processor, Intel Xeon processor MP, Intel Pentium 4, Pentium D processors
06_09H
Intel Pentium M processor
0F_02H
Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors
0F_0H, 0F_01H
Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors
06_7H, 06_08H, 06_0AH,
06_0BH
Intel Pentium III Xeon processor, Intel Pentium III processor
06_03H, 06_05H
Intel Pentium II Xeon processor, Intel Pentium II processor
06_01H
Intel Pentium Pro processor
05_01H, 05_02H, 05_04H
Intel Pentium processor, Intel Pentium processor with MMX Technology
The Intel® Quark™ SoC X1000 processor can be identified by the signature of DisplayFamily_DisplayModel = 05_09H and
SteppingID = 0
35.1
ARCHITECTURAL MSRS
Many MSRs have carried over from one generation of IA-32 processors to the next and to Intel 64 processors. A
subset of MSRs and associated bit fields, which do not change on future processor generations, are now considered
architectural MSRs. For historical reasons (beginning with the Pentium 4 processor), these “architectural MSRs”
were given the prefix “IA32_”. Table 35-2 lists the architectural MSRs, their addresses, their current names, their
names in previous IA-32 processors, and bit fields that are considered architectural. MSR addresses outside Table
35-2 and certain bit fields in an MSR address that may overlap with architectural MSR addresses are modelspecific. Code that accesses a machine specified MSR and that is executed on a processor that does not support
that MSR will generate an exception.
35-2 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Architectural MSR or individual bit fields in an architectural MSR may be introduced or transitioned at the granularity of certain processor family/model or the presence of certain CPUID feature flags. The right-most column of
Table 35-2 provides information on the introduction of each architectural MSR or its individual fields. This information is expressed either as signature values of “DF_DM” (see Table 35-1) or via CPUID flags.
Certain bit field position may be related to the maximum physical address width, the value of which is expressed
as “MAXPHYADDR” in Table 35-2. “MAXPHYADDR” is reported by CPUID.8000_0008H leaf.
MSR address range between 40000000H - 400000FFH is marked as a specially reserved range. All existing and
future processors will not implement any features using any MSR in this range.
Table 35-2. IA-32 Architectural MSRs
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
0H
0
IA32_P5_MC_ADDR (P5_MC_ADDR)
See Section 35.22, “MSRs in Pentium
Processors.”
Pentium Processor
(05_01H)
1H
1
IA32_P5_MC_TYPE (P5_MC_TYPE)
See Section 35.22, “MSRs in Pentium
Processors.”
DF_DM = 05_01H
6H
6
IA32_MONITOR_FILTER_SIZE
See Section 8.10.5, “Monitor/Mwait
Address Range Determination.”
0F_03H
10H
16
IA32_TIME_STAMP_
COUNTER (TSC)
See Section 17.15, “Time-Stamp Counter.”
05_01H
17H
23
IA32_PLATFORM_ID
(MSR_PLATFORM_ID )
Platform ID (RO)
The operating system can use this MSR to
determine “slot” information for the
processor and the proper microcode update
to load.
06_01H
49:0
Reserved.
52:50
Platform Id (RO)
Contains information concerning the
intended platform for the processor.
52
0
0
0
0
1
1
1
1
63:53
1BH
27
51
0
0
1
1
0
0
1
1
50
0
1
0
1
0
1
0
1
Processor Flag 0
Processor Flag 1
Processor Flag 2
Processor Flag 3
Processor Flag 4
Processor Flag 5
Processor Flag 6
Processor Flag 7
Reserved.
IA32_APIC_BASE (APIC_BASE)
06_01H
7:0
Reserved
8
BSP flag (R/W)
9
Reserved
10
Enable x2APIC mode
11
APIC Global Enable (R/W)
(MAXPHYADDR - 1):12
APIC Base (R/W)
63: MAXPHYADDR
Reserved
06_1AH
Vol. 3C 35-3
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
3AH
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
58
Comment
MSR/Bit Description
IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor
(R/W)
If any one enumeration
condition for defined bit
field holds
0
Lock bit (R/WO): (1 = locked). When set,
locks this MSR from being written, writes
to this bit will result in GP(0).
If any one enumeration
condition for defined bit
field position greater than
bit 0 holds
Note: Once the Lock bit is set, the contents
of this register cannot be modified.
Therefore the lock bit must be set after
configuring support for Intel Virtualization
Technology and prior to transferring control
to an option ROM or the OS. Hence, once
the Lock bit is set, the entire
IA32_FEATURE_CONTROL contents are
preserved across RESET when PWRGOOD is
not deasserted.
1
Enable VMX inside SMX operation (R/WL):
This bit enables a system executive to use
VMX in conjunction with SMX to support
Intel® Trusted Execution Technology.
If CPUID.01H:ECX[5] = 1
&& CPUID.01H:ECX[6] = 1
BIOS must set this bit only when the CPUID
function 1 returns VMX feature flag and
SMX feature flag set (ECX bits 5 and 6
respectively).
2
Enable VMX outside SMX operation (R/WL):
This bit enables VMX for system executive
that do not require SMX.
If CPUID.01H:ECX[5] = 1
BIOS must set this bit only when the CPUID
function 1 returns VMX feature flag set
(ECX bit 5).
35-4 Vol. 3C
7:3
Reserved
14:8
SENTER Local Function Enables (R/WL):
When set, each bit in the field represents
an enable control for a corresponding
SENTER function. This bit is supported only
if CPUID.1:ECX.[bit 6] is set
If CPUID.01H:ECX[6] = 1
15
SENTER Global Enable (R/WL): This bit must
be set to enable SENTER leaf functions.
This bit is supported only if
CPUID.1:ECX.[bit 6] is set
If CPUID.01H:ECX[6] = 1
16
Reserved
17
SGX Launch Control Enable (R/WL): This bit
must be set to enable runtime
reconfiguration of SGX Launch Control via
IA32_SGXLEPUBKEYHASHn MSR.
If CPUID.(EAX=07H,
ECX=0H): ECX[30] = 1
18
SGX Global Enable (R/WL): This bit must be
set to enable SGX leaf functions.
If CPUID.(EAX=07H,
ECX=0H): EBX[2] = 1
19
Reserved
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
3BH
Decimal
59
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
20
LMCE On (R/WL): When set, system
software can program the MSRs associated
with LMCE to configure delivery of some
machine check exceptions to a single logical
processor.
63:21
Reserved
IA32_TSC_ADJUST
Per Logical Processor TSC Adjust (R/Write
to clear)
63:0
THREAD_ADJUST:
If IA32_MCG_CAP[27] = 1
If CPUID.(EAX=07H,
ECX=0H): EBX[1] = 1
Local offset value of the IA32_TSC for a
logical processor. Reset value is Zero. A
write to IA32_TSC will modify the local
offset in IA32_TSC_ADJUST and the
content of IA32_TSC, but does not affect
the internal invariant TSC hardware.
79H
121
IA32_BIOS_UPDT_TRIG
(BIOS_UPDT_TRIG)
BIOS Update Trigger (W)
06_01H
Executing a WRMSR instruction to this MSR
causes a microcode update to be loaded
into the processor. See Section 9.11.6,
“Microcode Update Loader.”
A processor may prevent writing to this
MSR when loading guest states on VM
entries or saving guest states on VM exits.
8BH
139
IA32_BIOS_SIGN_ID
(BIOS_SIGN/BBL_CR_D3)
BIOS Update Signature (RO)
06_01H
Returns the microcode update signature
following the execution of CPUID.01H.
A processor may prevent writing to this
MSR when loading guest states on VM
entries or saving guest states on VM exits.
31:0
Reserved
63:32
It is recommended that this field be preloaded with 0 prior to executing CPUID.
If the field remains 0 following the
execution of CPUID; this indicates that no
microcode update is loaded. Any non-zero
value is the microcode update signature.
8CH
140
IA32_SGXLEPUBKEYHASH0
IA32_SGXLEPUBKEYHASH[63:0] (R/W)
Bits 63:0 of the SHA256 digest of the
SIGSTRUCT.MODULUS for SGX Launch
Enclave. On reset, the default value is the
digest of Intel’s signing key.
Read permitted If
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1,
Write permitted if
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1 &&
IA32_FEATURE_CONTROL[
17] = 1 &&
IA32_FEATURE_CONTROL[
0] = 1
Vol. 3C 35-5
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
8DH
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
141
IA32_SGXLEPUBKEYHASH1
Comment
MSR/Bit Description
IA32_SGXLEPUBKEYHASH[127:64] (R/W)
Bits 127:64 of the SHA256 digest of the
SIGSTRUCT.MODULUS for SGX Launch
Enclave. On reset, the default value is the
digest of Intel’s signing key.
8EH
142
IA32_SGXLEPUBKEYHASH2
IA32_SGXLEPUBKEYHASH[191:128] (R/W)
Bits 191:128 of the SHA256 digest of the
SIGSTRUCT.MODULUS for SGX Launch
Enclave. On reset, the default value is the
digest of Intel’s signing key.
8FH
143
IA32_SGXLEPUBKEYHASH3
IA32_SGXLEPUBKEYHASH[255:192] (R/W)
Bits 255:192 of the SHA256 digest of the
SIGSTRUCT.MODULUS for SGX Launch
Enclave. On reset, the default value is the
digest of Intel’s signing key.
9BH
155
IA32_SMM_MONITOR_CTL
SMM Monitor Configuration (R/W)
0
Valid (R/W)
1
Reserved
2
Controls SMI unblocking by VMXOFF (see
Section 34.14.4)
11:3
Reserved
31:12
MSEG Base (R/W)
63:32
Reserved
Read permitted If
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1,
Write permitted if
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1 &&
IA32_FEATURE_CONTROL[
17] = 1 &&
IA32_FEATURE_CONTROL[
0] = 1
Read permitted If
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1,
Write permitted if
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1 &&
IA32_FEATURE_CONTROL[
17] = 1 &&
IA32_FEATURE_CONTROL[
0] = 1
If CPUID.01H: ECX[5]=1 ||
CPUID.01H: ECX[6] = 1
If IA32_VMX_MISC[28]
9EH
158
IA32_SMBASE
Base address of the logical processor’s
SMRAM image (RO, SMM only)
If IA32_VMX_MISC[15]
C1H
193
IA32_PMC0 (PERFCTR0)
General Performance Counter 0 (R/W)
If CPUID.0AH: EAX[15:8] >
0
C2H
194
IA32_PMC1 (PERFCTR1)
General Performance Counter 1 (R/W)
If CPUID.0AH: EAX[15:8] >
1
C3H
195
IA32_PMC2
General Performance Counter 2 (R/W)
If CPUID.0AH: EAX[15:8] >
2
C4H
196
IA32_PMC3
General Performance Counter 3 (R/W)
If CPUID.0AH: EAX[15:8] >
3
C5H
197
IA32_PMC4
General Performance Counter 4 (R/W)
If CPUID.0AH: EAX[15:8] >
4
C6H
198
IA32_PMC5
General Performance Counter 5 (R/W)
If CPUID.0AH: EAX[15:8] >
5
C7H
199
IA32_PMC6
General Performance Counter 6 (R/W)
If CPUID.0AH: EAX[15:8] >
6
35-6 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
C8H
200
IA32_PMC7
General Performance Counter 7 (R/W)
If CPUID.0AH: EAX[15:8] >
7
E7H
231
IA32_MPERF
TSC Frequency Clock Counter (R/Write to
clear)
If CPUID.06H: ECX[0] = 1
63:0
C0_MCNT: C0 TSC Frequency Clock Count
Increments at fixed interval (relative to TSC
freq.) when the logical processor is in C0.
Cleared upon overflow / wrap-around of
IA32_APERF.
E8H
232
IA32_APERF
Actual Performance Clock Counter (R/Write
to clear).
63:0
C0_ACNT: C0 Actual Frequency Clock
Count
If CPUID.06H: ECX[0] = 1
Accumulates core clock counts at the
coordinated clock frequency, when the
logical processor is in C0.
Cleared upon overflow / wrap-around of
IA32_MPERF.
FEH
174H
254
372
IA32_MTRRCAP (MTRRcap)
MTRR Capability (RO) Section 11.11.2.1,
“IA32_MTRR_DEF_TYPE MSR.”
7:0
VCNT: The number of variable memory
type ranges in the processor.
8
Fixed range MTRRs are supported when
set.
9
Reserved.
10
WC Supported when set.
11
SMRR Supported when set.
63:12
Reserved.
IA32_SYSENTER_CS
SYSENTER_CS_MSR (R/W)
15:0
CS Selector
63:16
Reserved.
06_01H
06_01H
175H
373
IA32_SYSENTER_ESP
SYSENTER_ESP_MSR (R/W)
06_01H
176H
374
IA32_SYSENTER_EIP
SYSENTER_EIP_MSR (R/W)
06_01H
179H
377
IA32_MCG_CAP (MCG_CAP)
Global Machine Check Capability (RO)
06_01H
7:0
Count: Number of reporting banks.
8
MCG_CTL_P: IA32_MCG_CTL is present if
this bit is set
9
MCG_EXT_P: Extended machine check
state registers are present if this bit is set
10
MCP_CMCI_P: Support for corrected MC
error event is present.
06_01H
Vol. 3C 35-7
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
17AH
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
378
Comment
MSR/Bit Description
11
MCG_TES_P: Threshold-based error status
register are present if this bit is set.
15:12
Reserved
23:16
MCG_EXT_CNT: Number of extended
machine check state registers present.
24
MCG_SER_P: The processor supports
software error recovery if this bit is set.
25
Reserved.
26
MCG_ELOG_P: Indicates that the processor
allows platform firmware to be invoked
when an error is detected so that it may
provide additional platform specific
information in an ACPI format “Generic
Error Data Entry” that augments the data
included in machine check bank registers.
06_3EH
27
MCG_LMCE_P: Indicates that the processor
support extended state in
IA32_MCG_STATUS and associated
MSR necessary to configure Local
Machine Check Exception (LMCE).
06_3EH
63:28
Reserved.
IA32_MCG_STATUS (MCG_STATUS)
Global Machine Check Status (R/W0)
06_01H
0
RIPV. Restart IP valid
06_01H
1
EIPV. Error IP valid
06_01H
2
MCIP. Machine check in progress
06_01H
3
LMCE_S.
If
IA32_MCG_CAP.LMCE_P[2
7] =1
63:4
Reserved.
Global Machine Check Control (R/W)
17BH
379
IA32_MCG_CTL (MCG_CTL)
180H185H
384389
Reserved
186H
390
IA32_PERFEVTSEL0 (PERFEVTSEL0)
Performance Event Select Register 0 (R/W)
7:0
Event Select: Selects a performance event
logic unit.
15:8
UMask: Qualifies the microarchitectural
condition to detect on the selected event
logic.
16
USR: Counts while in privilege level is not
ring 0.
17
OS: Counts while in privilege level is ring 0.
35-8 Vol. 3C
If IA32_MCG_CAP.CTL_P[8]
=1
06_0EH1
If CPUID.0AH: EAX[15:8] >
0
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
18
Edge: Enables edge detection if set.
19
PC: enables pin control.
20
INT: enables interrupt on counter overflow.
21
AnyThread: When set to 1, it enables
counting the associated event conditions
occurring across all logical processors
sharing a processor core. When set to 0, the
counter only increments the associated
event conditions occurring in the logical
processor which programmed the MSR.
22
EN: enables the corresponding performance
counter to commence counting when this
bit is set.
23
INV: invert the CMASK.
31:24
CMASK: When CMASK is not zero, the
corresponding performance counter
increments each cycle if the event count is
greater than or equal to the CMASK.
63:32
Reserved.
187H
391
IA32_PERFEVTSEL1 (PERFEVTSEL1)
Performance Event Select Register 1 (R/W)
If CPUID.0AH: EAX[15:8] >
1
188H
392
IA32_PERFEVTSEL2
Performance Event Select Register 2 (R/W)
If CPUID.0AH: EAX[15:8] >
2
189H
393
IA32_PERFEVTSEL3
Performance Event Select Register 3 (R/W)
If CPUID.0AH: EAX[15:8] >
3
18AH197H
394407
Reserved
198H
408
IA32_PERF_STATUS
(RO)
15:0
Current performance State Value
199H
409
06_0EH2
63:16
Reserved.
IA32_PERF_CTL
(R/W)
15:0
Target performance State Value
31:16
Reserved.
32
IDA Engage. (R/W)
0F_03H
0F_03H
06_0FH (Mobile only)
When set to 1: disengages IDA
63:33
19AH
410
IA32_CLOCK_MODULATION
Reserved.
Clock Modulation Control (R/W)
If CPUID.01H:EDX[22] = 1
See Section 14.7.3, “Software Controlled
Clock Modulation.”
0
Extended On-Demand Clock Modulation
Duty Cycle:
If CPUID.06H:EAX[5] = 1
Vol. 3C 35-9
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
19BH
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
411
Comment
MSR/Bit Description
3:1
On-Demand Clock Modulation Duty Cycle:
Specific encoded values for target duty
cycle modulation.
If CPUID.01H:EDX[22] = 1
4
On-Demand Clock Modulation Enable: Set 1
to enable modulation.
If CPUID.01H:EDX[22] = 1
63:5
Reserved.
IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
If CPUID.01H:EDX[22] = 1
Enables and disables the generation of an
interrupt on temperature transitions
detected with the processor’s thermal
sensors and thermal monitor.
See Section 14.7.2, “Thermal Monitor.”
19CH
412
0
High-Temperature Interrupt Enable
If CPUID.01H:EDX[22] = 1
1
Low-Temperature Interrupt Enable
If CPUID.01H:EDX[22] = 1
2
PROCHOT# Interrupt Enable
If CPUID.01H:EDX[22] = 1
3
FORCEPR# Interrupt Enable
If CPUID.01H:EDX[22] = 1
4
Critical Temperature Interrupt Enable
If CPUID.01H:EDX[22] = 1
7:5
Reserved.
14:8
Threshold #1 Value
If CPUID.01H:EDX[22] = 1
15
Threshold #1 Interrupt Enable
If CPUID.01H:EDX[22] = 1
22:16
Threshold #2 Value
If CPUID.01H:EDX[22] = 1
23
Threshold #2 Interrupt Enable
If CPUID.01H:EDX[22] = 1
24
Power Limit Notification Enable
If CPUID.06H:EAX[4] = 1
63:25
Reserved.
IA32_THERM_STATUS
Thermal Status Information (RO)
If CPUID.01H:EDX[22] = 1
Contains status information about the
processor’s thermal sensor and automatic
thermal monitoring facilities.
See Section 14.7.2, “Thermal Monitor”
35-10 Vol. 3C
0
Thermal Status (RO):
If CPUID.01H:EDX[22] = 1
1
Thermal Status Log (R/W):
If CPUID.01H:EDX[22] = 1
2
PROCHOT # or FORCEPR# event (RO)
If CPUID.01H:EDX[22] = 1
3
PROCHOT # or FORCEPR# log (R/WC0)
If CPUID.01H:EDX[22] = 1
4
Critical Temperature Status (RO)
If CPUID.01H:EDX[22] = 1
5
Critical Temperature Status log (R/WC0)
If CPUID.01H:EDX[22] = 1
6
Thermal Threshold #1 Status (RO)
If CPUID.01H:ECX[8] = 1
7
Thermal Threshold #1 log (R/WC0)
If CPUID.01H:ECX[8] = 1
8
Thermal Threshold #2 Status (RO)
If CPUID.01H:ECX[8] = 1
9
Thermal Threshold #2 log (R/WC0)
If CPUID.01H:ECX[8] = 1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
1A0H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
416
Comment
MSR/Bit Description
10
Power Limitation Status (RO)
If CPUID.06H:EAX[4] = 1
11
Power Limitation log (R/WC0)
If CPUID.06H:EAX[4] = 1
12
Current Limit Status (RO)
If CPUID.06H:EAX[7] = 1
13
Current Limit log (R/WC0)
If CPUID.06H:EAX[7] = 1
14
Cross Domain Limit Status (RO)
If CPUID.06H:EAX[7] = 1
15
Cross Domain Limit log (R/WC0)
If CPUID.06H:EAX[7] = 1
22:16
Digital Readout (RO)
If CPUID.06H:EAX[0] = 1
26:23
Reserved.
30:27
Resolution in Degrees Celsius (RO)
If CPUID.06H:EAX[0] = 1
31
Reading Valid (RO)
If CPUID.06H:EAX[0] = 1
63:32
Reserved.
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to
be enabled and disabled.
0
Fast-Strings Enable
0F_0H
When set, the fast-strings feature (for REP
MOVS and REP STORS) is enabled (default);
when clear, fast-strings are disabled.
2:1
Reserved.
3
Automatic Thermal Control Circuit Enable
(R/W)
0F_0H
1=
Setting this bit enables the thermal
control circuit (TCC) portion of the
Intel Thermal Monitor feature. This
allows the processor to automatically
reduce power consumption in
response to TCC activation.
0 = Disabled.
Note: In some products clearing this bit
might be ignored in critical thermal
conditions, and TM1, TM2 and adaptive
thermal throttling will still be activated.
The default value of this field varies with
product . See respective tables where
default value is listed.
6:4
Reserved
7
Performance Monitoring Available (R)
1=
0=
10:8
0F_0H
Performance monitoring enabled
Performance monitoring disabled
Reserved.
Vol. 3C 35-11
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
11
Comment
MSR/Bit Description
Branch Trace Storage Unavailable (RO)
0F_0H
1 = Processor doesn’t support branch
trace storage (BTS)
0 = BTS is supported
12
Processor Event Based Sampling (PEBS)
Unavailable (RO)
06_0FH
1 = PEBS is not supported;
0 = PEBS is supported.
15:13
Reserved.
16
Enhanced Intel SpeedStep Technology
Enable (R/W)
If CPUID.01H: ECX[7] =1
0=
Enhanced Intel SpeedStep
Technology disabled
1 = Enhanced Intel SpeedStep
Technology enabled
17
Reserved.
18
ENABLE MONITOR FSM (R/W)
When this bit is set to 0, the MONITOR
feature flag is not set (CPUID.01H:ECX[bit
3] = 0). This indicates that
MONITOR/MWAIT are not supported.
Software attempts to execute
MONITOR/MWAIT will cause #UD when this
bit is 0.
When this bit is set to 1 (default),
MONITOR/MWAIT are supported
(CPUID.01H:ECX[bit 3] = 1).
If the SSE3 feature flag ECX[0] is not set
(CPUID.01H:ECX[bit 0] = 0), the OS must
not attempt to alter this bit. BIOS must
leave it in the default state. Writing this bit
when the SSE3 feature flag is set to 0 may
generate a #GP exception.
21:19
35-12 Vol. 3C
Reserved.
0F_03H
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
22
Comment
MSR/Bit Description
Limit CPUID Maxval (R/W)
0F_03H
When this bit is set to 1, CPUID.00H returns
a maximum value in EAX[7:0] of 2.
BIOS should contain a setup question that
allows users to specify when the installed
OS does not support CPUID functions
greater than 2.
Before setting this bit, BIOS must execute
the CPUID.0H and examine the maximum
value returned in EAX[7:0]. If the maximum
value is greater than 2, this bit is
supported.
Otherwise, this bit is not supported. Setting
this bit when the maximum value is not
greater than 2 may generate a #GP
exception.
Setting this bit may cause unexpected
behavior in software that depends on the
availability of CPUID leaves greater than 2.
23
xTPR Message Disable (R/W)
if CPUID.01H:ECX[14] = 1
When set to 1, xTPR messages are
disabled. xTPR messages are optional
messages that allow the processor to
inform the chipset of its priority.
33:24
Reserved.
34
XD Bit Disable (R/W)
When set to 1, the Execute Disable Bit
feature (XD Bit) is disabled and the XD Bit
extended feature flag will be clear
(CPUID.80000001H: EDX[20]=0).
if
CPUID.80000001H:EDX[2
0] = 1
When set to a 0 (default), the Execute
Disable Bit feature (if available) allows the
OS to enable PAE paging and take
advantage of data only pages.
BIOS must not alter the contents of this bit
location, if XD bit is not supported. Writing
this bit to 1 when the XD Bit extended
feature flag is set to 0 may generate a #GP
exception.
1B0H
432
63:35
Reserved.
IA32_ENERGY_PERF_BIAS
Performance Energy Bias Hint (R/W)
3:0
Power Policy Preference:
if CPUID.6H:ECX[3] = 1
0 indicates preference to highest
performance.
15 indicates preference to maximize
energy saving.
63:4
Reserved.
Vol. 3C 35-13
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
1B1H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
433
IA32_PACKAGE_THERM_STATUS
Comment
MSR/Bit Description
Package Thermal Status Information (RO)
If CPUID.06H: EAX[6] = 1
Contains status information about the
package’s thermal sensor.
See Section 14.8, “Package Level Thermal
Management.”
1B2H
434
0
Pkg Thermal Status (RO):
1
Pkg Thermal Status Log (R/W):
2
Pkg PROCHOT # event (RO)
3
Pkg PROCHOT # log (R/WC0)
4
Pkg Critical Temperature Status (RO)
5
Pkg Critical Temperature Status log
(R/WC0)
6
Pkg Thermal Threshold #1 Status (RO)
7
Pkg Thermal Threshold #1 log (R/WC0)
8
Pkg Thermal Threshold #2 Status (RO)
9
Pkg Thermal Threshold #1 log (R/WC0)
10
Pkg Power Limitation Status (RO)
11
Pkg Power Limitation log (R/WC0)
15:12
Reserved.
22:16
Pkg Digital Readout (RO)
63:23
Reserved.
IA32_PACKAGE_THERM_INTERRUPT
Pkg Thermal Interrupt Control (R/W)
Enables and disables the generation of an
interrupt on temperature transitions
detected with the package’s thermal
sensor.
See Section 14.8, “Package Level Thermal
Management.”
35-14 Vol. 3C
0
Pkg High-Temperature Interrupt Enable
1
Pkg Low-Temperature Interrupt Enable
2
Pkg PROCHOT# Interrupt Enable
3
Reserved.
4
Pkg Overheat Interrupt Enable
7:5
Reserved.
14:8
Pkg Threshold #1 Value
15
Pkg Threshold #1 Interrupt Enable
22:16
Pkg Threshold #2 Value
23
Pkg Threshold #2 Interrupt Enable
24
Pkg Power Limit Notification Enable
If CPUID.06H: EAX[6] = 1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
1D9H
1F2H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
473
498
Comment
MSR/Bit Description
63:25
Reserved.
IA32_DEBUGCTL (MSR_DEBUGCTLA,
MSR_DEBUGCTLB)
Trace/Profile Resource Control (R/W)
06_0EH
0
LBR: Setting this bit to 1 enables the
processor to record a running trace of the
most recent branches taken by the
processor in the LBR stack.
06_01H
1
BTF: Setting this bit to 1 enables the
processor to treat EFLAGS.TF as single-step
on branches instead of single-step on
instructions.
06_01H
5:2
Reserved.
6
TR: Setting this bit to 1 enables branch
trace messages to be sent.
06_0EH
7
BTS: Setting this bit enables branch trace
messages (BTMs) to be logged in a BTS
buffer.
06_0EH
8
BTINT: When clear, BTMs are logged in a
BTS buffer in circular fashion. When this bit
is set, an interrupt is generated by the BTS
facility when the BTS buffer is full.
06_0EH
9
1: BTS_OFF_OS: When set, BTS or BTM is
skipped if CPL = 0.
06_0FH
10
BTS_OFF_USR: When set, BTS or BTM is
skipped if CPL > 0.
06_0FH
11
FREEZE_LBRS_ON_PMI: When set, the LBR
stack is frozen on a PMI request.
If CPUID.01H: ECX[15] = 1
&& CPUID.0AH: EAX[7:0] >
1
12
FREEZE_PERFMON_ON_PMI: When set,
each ENABLE bit of the global counter
control MSR are frozen (address 38FH) on a
PMI request
If CPUID.01H: ECX[15] = 1
&& CPUID.0AH: EAX[7:0] >
1
13
ENABLE_UNCORE_PMI: When set, enables
the logical processor to receive and
generate PMI on behalf of the uncore.
06_1AH
14
FREEZE_WHILE_SMM: When set, freezes
perfmon and trace messages while in SMM.
If
IA32_PERF_CAPABILITIES[
12] = 1
15
RTM_DEBUG: When set, enables DR7 debug
bit on XBEGIN
If (CPUID.(EAX=07H,
ECX=0):EBX[11] = 1)
63:16
Reserved.
IA32_SMRR_PHYSBASE
SMRR Base Address (Writeable only in
SMM)
Base address of SMM memory range.
7:0
If
IA32_MTRRCAP.SMRR[11]
=1
Type. Specifies memory type of the range.
Vol. 3C 35-15
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
11:8
Reserved.
31:12
PhysBase.
SMRR physical Base Address.
1F3H
499
63:32
Reserved.
IA32_SMRR_PHYSMASK
SMRR Range Mask. (Writeable only in
SMM)
If IA32_MTRRCAP[SMRR]
=1
Range Mask of SMM memory range.
10:0
Reserved.
11
Valid
Enable range mask.
31:12
PhysMask
SMRR address range mask.
63:32
Reserved.
1F8H
504
IA32_PLATFORM_DCA_CAP
DCA Capability (R)
If CPUID.01H: ECX[18] = 1
1F9H
505
IA32_CPU_DCA_CAP
If set, CPU supports Prefetch-Hint type.
If CPUID.01H: ECX[18] = 1
1FAH
506
IA32_DCA_0_CAP
DCA type 0 Status and Control register.
If CPUID.01H: ECX[18] = 1
0
DCA_ACTIVE: Set by HW when DCA is fuseenabled and no defeatures are set.
2:1
TRANSACTION
6:3
DCA_TYPE
10:7
DCA_QUEUE_SIZE
12:11
Reserved.
16:13
DCA_DELAY: Writes will update the register
but have no HW side-effect.
23:17
Reserved.
24
SW_BLOCK: SW can request DCA block by
setting this bit.
25
Reserved.
26
HW_BLOCK: Set when DCA is blocked by
HW (e.g. CR0.CD = 1).
31:27
Reserved.
200H
512
IA32_MTRR_PHYSBASE0
(MTRRphysBase0)
See Section 11.11.2.3, “Variable Range
MTRRs.”
If CPUID.01H:
EDX.MTRR[12] =1
201H
513
IA32_MTRR_PHYSMASK0
MTRRphysMask0
If CPUID.01H:
EDX.MTRR[12] =1
202H
514
IA32_MTRR_PHYSBASE1
MTRRphysBase1
If CPUID.01H:
EDX.MTRR[12] =1
203H
515
IA32_MTRR_PHYSMASK1
MTRRphysMask1
If CPUID.01H:
EDX.MTRR[12] =1
35-16 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
204H
516
IA32_MTRR_PHYSBASE2
MTRRphysBase2
If CPUID.01H:
EDX.MTRR[12] =1
205H
517
IA32_MTRR_PHYSMASK2
MTRRphysMask2
If CPUID.01H:
EDX.MTRR[12] =1
206H
518
IA32_MTRR_PHYSBASE3
MTRRphysBase3
If CPUID.01H:
EDX.MTRR[12] =1
207H
519
IA32_MTRR_PHYSMASK3
MTRRphysMask3
If CPUID.01H:
EDX.MTRR[12] =1
208H
520
IA32_MTRR_PHYSBASE4
MTRRphysBase4
If CPUID.01H:
EDX.MTRR[12] =1
209H
521
IA32_MTRR_PHYSMASK4
MTRRphysMask4
If CPUID.01H:
EDX.MTRR[12] =1
20AH
522
IA32_MTRR_PHYSBASE5
MTRRphysBase5
If CPUID.01H:
EDX.MTRR[12] =1
20BH
523
IA32_MTRR_PHYSMASK5
MTRRphysMask5
If CPUID.01H:
EDX.MTRR[12] =1
20CH
524
IA32_MTRR_PHYSBASE6
MTRRphysBase6
If CPUID.01H:
EDX.MTRR[12] =1
20DH
525
IA32_MTRR_PHYSMASK6
MTRRphysMask6
If CPUID.01H:
EDX.MTRR[12] =1
20EH
526
IA32_MTRR_PHYSBASE7
MTRRphysBase7
If CPUID.01H:
EDX.MTRR[12] =1
20FH
527
IA32_MTRR_PHYSMASK7
MTRRphysMask7
If CPUID.01H:
EDX.MTRR[12] =1
210H
528
IA32_MTRR_PHYSBASE8
MTRRphysBase8
if IA32_MTRRCAP[7:0] > 8
211H
529
IA32_MTRR_PHYSMASK8
MTRRphysMask8
if IA32_MTRRCAP[7:0] > 8
212H
530
IA32_MTRR_PHYSBASE9
MTRRphysBase9
if IA32_MTRRCAP[7:0] > 9
213H
531
IA32_MTRR_PHYSMASK9
MTRRphysMask9
if IA32_MTRRCAP[7:0] > 9
250H
592
IA32_MTRR_FIX64K_00000
MTRRfix64K_00000
If CPUID.01H:
EDX.MTRR[12] =1
258H
600
IA32_MTRR_FIX16K_80000
MTRRfix16K_80000
If CPUID.01H:
EDX.MTRR[12] =1
259H
601
IA32_MTRR_FIX16K_A0000
MTRRfix16K_A0000
If CPUID.01H:
EDX.MTRR[12] =1
268H
616
IA32_MTRR_FIX4K_C0000
(MTRRfix4K_C0000 )
See Section 11.11.2.2, “Fixed Range
MTRRs.”
If CPUID.01H:
EDX.MTRR[12] =1
269H
617
IA32_MTRR_FIX4K_C8000
MTRRfix4K_C8000
If CPUID.01H:
EDX.MTRR[12] =1
26AH
618
IA32_MTRR_FIX4K_D0000
MTRRfix4K_D0000
If CPUID.01H:
EDX.MTRR[12] =1
26BH
619
IA32_MTRR_FIX4K_D8000
MTRRfix4K_D8000
If CPUID.01H:
EDX.MTRR[12] =1
Vol. 3C 35-17
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
26CH
620
IA32_MTRR_FIX4K_E0000
MTRRfix4K_E0000
If CPUID.01H:
EDX.MTRR[12] =1
26DH
621
IA32_MTRR_FIX4K_E8000
MTRRfix4K_E8000
If CPUID.01H:
EDX.MTRR[12] =1
26EH
622
IA32_MTRR_FIX4K_F0000
MTRRfix4K_F0000
If CPUID.01H:
EDX.MTRR[12] =1
26FH
623
IA32_MTRR_FIX4K_F8000
MTRRfix4K_F8000
If CPUID.01H:
EDX.MTRR[12] =1
277H
631
IA32_PAT
IA32_PAT (R/W)
If CPUID.01H:
EDX.MTRR[16] =1
2:0
PA0
7:3
Reserved.
10:8
PA1
15:11
Reserved.
18:16
PA2
23:19
Reserved.
26:24
PA3
31:27
Reserved.
34:32
PA4
39:35
Reserved.
42:40
PA5
47:43
Reserved.
50:48
PA6
55:51
Reserved.
58:56
PA7
63:59
Reserved.
IA32_MC0_CTL2
(R/W)
14:0
Corrected error count threshold.
29:15
Reserved.
30
CMCI_EN
63:31
Reserved.
280H
640
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
0
281H
641
IA32_MC1_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
1
282H
642
IA32_MC2_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
2
35-18 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
283H
643
IA32_MC3_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
3
284H
644
IA32_MC4_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
4
285H
645
IA32_MC5_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
5
286H
646
IA32_MC6_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
6
287H
647
IA32_MC7_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
7
288H
648
IA32_MC8_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
8
289H
649
IA32_MC9_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
9
28AH
650
IA32_MC10_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
10
28BH
651
IA32_MC11_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
11
28CH
652
IA32_MC12_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
12
28DH
653
IA32_MC13_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
13
28EH
654
IA32_MC14_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
14
28FH
655
IA32_MC15_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
15
290H
656
IA32_MC16_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
16
291H
657
IA32_MC17_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
17
Vol. 3C 35-19
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
292H
658
IA32_MC18_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
18
293H
659
IA32_MC19_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
19
294H
660
IA32_MC20_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
20
295H
661
IA32_MC21_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
21
296H
662
IA32_MC22_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
22
297H
663
IA32_MC23_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
23
298H
664
IA32_MC24_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
24
299H
665
IA32_MC25_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
25
29AH
666
IA32_MC26_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
26
29BH
667
IA32_MC27_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
27
29CH
668
IA32_MC28_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
28
29DH
669
IA32_MC29_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
29
29EH
670
IA32_MC30_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
30
29FH
671
IA32_MC31_CTL2
(R/W) same fields as IA32_MC0_CTL2.
If IA32_MCG_CAP[10] = 1
&& IA32_MCG_CAP[7:0] >
31
2FFH
767
IA32_MTRR_DEF_TYPE
MTRRdefType (R/W)
If CPUID.01H:
EDX.MTRR[12] =1
2:0
Default Memory Type
9:3
Reserved.
35-20 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
10
Fixed Range MTRR Enable
11
MTRR Enable
63:12
Reserved.
309H
777
IA32_FIXED_CTR0
(MSR_PERF_FIXED_CTR0)
Fixed-Function Performance Counter 0
(R/W): Counts Instr_Retired.Any.
If CPUID.0AH: EDX[4:0] > 0
30AH
778
IA32_FIXED_CTR1
(MSR_PERF_FIXED_CTR1)
Fixed-Function Performance Counter 1
(R/W): Counts CPU_CLK_Unhalted.Core
If CPUID.0AH: EDX[4:0] > 1
30BH
779
IA32_FIXED_CTR2
(MSR_PERF_FIXED_CTR2)
Fixed-Function Performance Counter 2
(R/W): Counts CPU_CLK_Unhalted.Ref
If CPUID.0AH: EDX[4:0] > 2
345H
837
IA32_PERF_CAPABILITIES
RO
If CPUID.01H: ECX[15] = 1
5:0
LBR format
38DH
909
6
PEBS Trap
7
PEBSSaveArchRegs
11:8
PEBS Record Format
12
1: Freeze while SMM is supported.
13
1: Full width of counter writable via
IA32_A_PMCx.
63:14
Reserved.
IA32_FIXED_CTR_CTRL
Fixed-Function Performance Counter
Control (R/W)
If CPUID.0AH: EAX[7:0] > 1
Counter increments while the results of
ANDing respective enable bit in
IA32_PERF_GLOBAL_CTRL with the
corresponding OS or USR bits in this MSR is
true.
0
EN0_OS: Enable Fixed Counter 0 to count
while CPL = 0.
1
EN0_Usr: Enable Fixed Counter 0 to count
while CPL > 0.
2
AnyThread: When set to 1, it enables
counting the associated event conditions
occurring across all logical processors
sharing a processor core. When set to 0, the
counter only increments the associated
event conditions occurring in the logical
processor which programmed the MSR.
3
EN0_PMI: Enable PMI when fixed counter 0
overflows.
4
EN1_OS: Enable Fixed Counter 1to count
while CPL = 0.
5
EN1_Usr: Enable Fixed Counter 1to count
while CPL > 0.
If CPUID.0AH:
EAX[7:0] > 2
Vol. 3C 35-21
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
6
38EH
910
35-22 Vol. 3C
Comment
MSR/Bit Description
AnyThread: When set to 1, it enables
counting the associated event conditions
occurring across all logical processors
sharing a processor core. When set to 0, the
counter only increments the associated
event conditions occurring in the logical
processor which programmed the MSR.
7
EN1_PMI: Enable PMI when fixed counter 1
overflows.
8
EN2_OS: Enable Fixed Counter 2 to count
while CPL = 0.
9
EN2_Usr: Enable Fixed Counter 2 to count
while CPL > 0.
10
AnyThread: When set to 1, it enables
counting the associated event conditions
occurring across all logical processors
sharing a processor core. When set to 0, the
counter only increments the associated
event conditions occurring in the logical
processor which programmed the MSR.
If CPUID.0AH:
EAX[7:0] > 2
If CPUID.0AH:
EAX[7:0] > 2
11
EN2_PMI: Enable PMI when fixed counter 2
overflows.
63:12
Reserved.
IA32_PERF_GLOBAL_STATUS
Global Performance Counter Status (RO)
If CPUID.0AH: EAX[7:0] > 0
0
Ovf_PMC0: Overflow status of IA32_PMC0.
If CPUID.0AH: EAX[15:8] >
0
1
Ovf_PMC1: Overflow status of IA32_PMC1.
If CPUID.0AH: EAX[15:8] >
1
2
Ovf_PMC2: Overflow status of IA32_PMC2.
If CPUID.0AH: EAX[15:8] >
2
3
Ovf_PMC3: Overflow status of IA32_PMC3.
If CPUID.0AH: EAX[15:8] >
3
31:4
Reserved.
32
Ovf_FixedCtr0: Overflow status of
IA32_FIXED_CTR0.
If CPUID.0AH: EAX[7:0] > 1
33
Ovf_FixedCtr1: Overflow status of
IA32_FIXED_CTR1.
If CPUID.0AH: EAX[7:0] > 1
34
Ovf_FixedCtr2: Overflow status of
IA32_FIXED_CTR2.
If CPUID.0AH: EAX[7:0] > 1
54:35
Reserved.
55
Trace_ToPA_PMI: A PMI occurred due to a
ToPA entry memory buffer was completely
filled.
57:56
Reserved.
If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) &&
IA32_RTIT_CTL.ToPA = 1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
58
Comment
MSR/Bit Description
LBR_Frz: LBRs are frozen due to
If CPUID.0AH: EAX[7:0] > 3
• IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1,
• The LBR stack overflowed
59
CTR_Frz: Performance counters in the core
PMU are frozen due to
If CPUID.0AH: EAX[7:0] > 3
• IA32_DEBUGCTL.FREEZE_PERFMON_ON_
PMI=1,
• one or more core PMU counters
overflowed.
60
ASCI: Data in the performance counters in
the core PMU may include contributions
from the direct or indirect operation intel
SGX to protect an enclave.
If CPUID.(EAX=07H,
ECX=0):EBX[2] = 1
61
Ovf_Uncore: Uncore counter overflow
status.
If CPUID.0AH: EAX[7:0] > 2
62
OvfBuf: DS SAVE area Buffer overflow
status.
If CPUID.0AH: EAX[7:0] > 0
63
38FH
911
IA32_PERF_GLOBAL_CTRL
CondChgd: status bits of this register has If CPUID.0AH: EAX[7:0] > 0
changed.
Global Performance Counter Control (R/W)
If CPUID.0AH: EAX[7:0] > 0
Counter increments while the result of
ANDing respective enable bit in this MSR
with the corresponding OS or USR bits in
the general-purpose or fixed counter
control MSR is true.
390H
912
0
EN_PMC0
If CPUID.0AH: EAX[15:8] >
0
1
EN_PMC1
If CPUID.0AH: EAX[15:8] >
1
2
EN_PMC2
If CPUID.0AH: EAX[15:8] >
2
n
EN_PMCn
If CPUID.0AH: EAX[15:8] >
n
31:n+1
Reserved.
32
EN_FIXED_CTR0
If CPUID.0AH: EDX[4:0] > 0
33
EN_FIXED_CTR1
If CPUID.0AH: EDX[4:0] > 1
34
EN_FIXED_CTR2
If CPUID.0AH: EDX[4:0] > 2
63:35
Reserved.
IA32_PERF_GLOBAL_OVF_CTRL
Global Performance Counter Overflow
Control (R/W)
If CPUID.0AH: EAX[7:0] > 0
&& CPUID.0AH: EAX[7:0]
<= 3
0
Set 1 to Clear Ovf_PMC0 bit.
If CPUID.0AH: EAX[15:8] >
0
1
Set 1 to Clear Ovf_PMC1 bit.
If CPUID.0AH: EAX[15:8] >
1
Vol. 3C 35-23
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
390H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
912
35-24 Vol. 3C
Comment
MSR/Bit Description
2
Set 1 to Clear Ovf_PMC2 bit.
If CPUID.0AH: EAX[15:8] >
2
n
Set 1 to Clear Ovf_PMCn bit.
If CPUID.0AH: EAX[15:8] >
n
31:n
Reserved.
32
Set 1 to Clear Ovf_FIXED_CTR0 bit.
If CPUID.0AH: EDX[4:0] > 0
33
Set 1 to Clear Ovf_FIXED_CTR1 bit.
If CPUID.0AH: EDX[4:0] > 1
34
Set 1 to Clear Ovf_FIXED_CTR2 bit.
If CPUID.0AH: EDX[4:0] > 2
54:35
Reserved.
55
Set 1 to Clear Trace_ToPA_PMI bit.
60:56
Reserved.
61
Set 1 to Clear Ovf_Uncore bit.
06_2EH
62
Set 1 to Clear OvfBuf: bit.
If CPUID.0AH: EAX[7:0] > 0
63
Set to 1to clear CondChgd: bit.
If CPUID.0AH: EAX[7:0] > 0
IA32_PERF_GLOBAL_STATUS_RESET
Global Performance Counter Overflow
Reset Control (R/W)
If CPUID.0AH: EAX[7:0] > 3
0
Set 1 to Clear Ovf_PMC0 bit.
If CPUID.0AH: EAX[15:8] >
0
1
Set 1 to Clear Ovf_PMC1 bit.
If CPUID.0AH: EAX[15:8] >
1
2
Set 1 to Clear Ovf_PMC2 bit.
If CPUID.0AH: EAX[15:8] >
2
n
Set 1 to Clear Ovf_PMCn bit.
If CPUID.0AH: EAX[15:8] >
n
31:n
Reserved.
32
Set 1 to Clear Ovf_FIXED_CTR0 bit.
If CPUID.0AH: EDX[4:0] > 0
33
Set 1 to Clear Ovf_FIXED_CTR1 bit.
If CPUID.0AH: EDX[4:0] > 1
34
Set 1 to Clear Ovf_FIXED_CTR2 bit.
If CPUID.0AH: EDX[4:0] > 2
54:35
Reserved.
55
Set 1 to Clear Trace_ToPA_PMI bit.
57:56
Reserved.
58
Set 1 to Clear LBR_Frz bit.
If CPUID.0AH: EAX[7:0] > 3
59
Set 1 to Clear CTR_Frz bit.
If CPUID.0AH: EAX[7:0] > 3
58
Set 1 to Clear ASCI bit.
If CPUID.0AH: EAX[7:0] > 3
61
Set 1 to Clear Ovf_Uncore bit.
06_2EH
62
Set 1 to Clear OvfBuf: bit.
If CPUID.0AH: EAX[7:0] > 0
If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) &&
IA32_RTIT_CTL.ToPA = 1
If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) &&
IA32_RTIT_CTL.ToPA[8] =
1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
391H
392H
3F1H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
913
914
1009
Comment
MSR/Bit Description
63
Set to 1to clear CondChgd: bit.
If CPUID.0AH: EAX[7:0] > 0
IA32_PERF_GLOBAL_STATUS_SET
Global Performance Counter Overflow Set
Control (R/W)
If CPUID.0AH: EAX[7:0] > 3
0
Set 1 to cause Ovf_PMC0 = 1.
If CPUID.0AH: EAX[7:0] > 3
1
Set 1 to cause Ovf_PMC1 = 1
If CPUID.0AH: EAX[15:8] >
1
2
Set 1 to cause Ovf_PMC2 = 1
If CPUID.0AH: EAX[15:8] >
2
n
Set 1 to cause Ovf_PMCn = 1
If CPUID.0AH: EAX[15:8] >
n
31:n
Reserved.
32
Set 1 to cause Ovf_FIXED_CTR0 = 1.
If CPUID.0AH: EAX[7:0] > 3
33
Set 1 to cause Ovf_FIXED_CTR1 = 1.
If CPUID.0AH: EAX[7:0] > 3
34
Set 1 to cause Ovf_FIXED_CTR2 = 1.
If CPUID.0AH: EAX[7:0] > 3
54:35
Reserved.
55
Set 1 to cause Trace_ToPA_PMI = 1.
57:56
Reserved.
58
Set 1 to cause LBR_Frz = 1.
If CPUID.0AH: EAX[7:0] > 3
59
Set 1 to cause CTR_Frz = 1.
If CPUID.0AH: EAX[7:0] > 3
58
Set 1 to cause ASCI = 1.
If CPUID.0AH: EAX[7:0] > 3
61
Set 1 to cause Ovf_Uncore = 1.
If CPUID.0AH: EAX[7:0] > 3
62
Set 1 to cause OvfBuf = 1.
If CPUID.0AH: EAX[7:0] > 3
63
Reserved
IA32_PERF_GLOBAL_INUSE
Indicator of core perfmon interface is in use
(RO)
0
IA32_PERFEVTSEL0 in use
1
IA32_PERFEVTSEL1 in use
If CPUID.0AH: EAX[15:8] >
1
2
IA32_PERFEVTSEL2 in use
If CPUID.0AH: EAX[15:8] >
2
n
IA32_PERFEVTSELn in use
If CPUID.0AH: EAX[15:8] >
n
31:n
Reserved.
32
IA32_FIXED_CTR0 in use
33
IA32_FIXED_CTR1 in use
34
IA32_FIXED_CTR2 in use
62:35
Reserved or Model specific.
63
PMI in use.
IA32_PEBS_ENABLE
PEBS Control (R/W)
If CPUID.0AH: EAX[7:0] > 3
If CPUID.0AH: EAX[7:0] > 3
Vol. 3C 35-25
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
0
Enable PEBS on IA32_PMC0.
3:1
Reserved or Model specific.
31:4
Reserved.
35:32
Reserved or Model specific.
63:36
Reserved.
06_0FH
400H
1024
IA32_MC0_CTL
MC0_CTL
If IA32_MCG_CAP.CNT >0
401H
1025
IA32_MC0_STATUS
MC0_STATUS
If IA32_MCG_CAP.CNT >0
402H
1026
IA32_MC0_ADDR1
MC0_ADDR
If IA32_MCG_CAP.CNT >0
403H
1027
IA32_MC0_MISC
MC0_MISC
If IA32_MCG_CAP.CNT >0
404H
1028
IA32_MC1_CTL
MC1_CTL
If IA32_MCG_CAP.CNT >1
405H
1029
IA32_MC1_STATUS
MC1_STATUS
If IA32_MCG_CAP.CNT >1
2
406H
1030
IA32_MC1_ADDR
MC1_ADDR
If IA32_MCG_CAP.CNT >1
407H
1031
IA32_MC1_MISC
MC1_MISC
If IA32_MCG_CAP.CNT >1
408H
1032
IA32_MC2_CTL
MC2_CTL
If IA32_MCG_CAP.CNT >2
409H
1033
IA32_MC2_STATUS
MC2_STATUS
If IA32_MCG_CAP.CNT >2
40AH
1034
IA32_MC2_ADDR1
MC2_ADDR
If IA32_MCG_CAP.CNT >2
40BH
1035
IA32_MC2_MISC
MC2_MISC
If IA32_MCG_CAP.CNT >2
40CH
1036
IA32_MC3_CTL
MC3_CTL
If IA32_MCG_CAP.CNT >3
40DH
1037
IA32_MC3_STATUS
MC3_STATUS
If IA32_MCG_CAP.CNT >3
40EH
1038
IA32_MC3_ADDR1
MC3_ADDR
If IA32_MCG_CAP.CNT >3
40FH
1039
IA32_MC3_MISC
MC3_MISC
If IA32_MCG_CAP.CNT >3
410H
1040
IA32_MC4_CTL
MC4_CTL
If IA32_MCG_CAP.CNT >4
411H
1041
IA32_MC4_STATUS
MC4_STATUS
If IA32_MCG_CAP.CNT >4
412H
1042
IA32_MC4_ADDR1
MC4_ADDR
If IA32_MCG_CAP.CNT >4
413H
1043
IA32_MC4_MISC
MC4_MISC
If IA32_MCG_CAP.CNT >4
414H
1044
IA32_MC5_CTL
MC5_CTL
If IA32_MCG_CAP.CNT >5
415H
1045
IA32_MC5_STATUS
MC5_STATUS
If IA32_MCG_CAP.CNT >5
416H
1046
IA32_MC5_ADDR1
MC5_ADDR
If IA32_MCG_CAP.CNT >5
417H
1047
IA32_MC5_MISC
MC5_MISC
If IA32_MCG_CAP.CNT >5
418H
1048
IA32_MC6_CTL
MC6_CTL
If IA32_MCG_CAP.CNT >6
419H
1049
IA32_MC6_STATUS
MC6_STATUS
If IA32_MCG_CAP.CNT >6
41AH
1050
IA32_MC6_ADDR1
MC6_ADDR
If IA32_MCG_CAP.CNT >6
41BH
1051
IA32_MC6_MISC
MC6_MISC
If IA32_MCG_CAP.CNT >6
41CH
1052
IA32_MC7_CTL
MC7_CTL
If IA32_MCG_CAP.CNT >7
41DH
1053
IA32_MC7_STATUS
MC7_STATUS
If IA32_MCG_CAP.CNT >7
41EH
1054
IA32_MC7_ADDR1
MC7_ADDR
If IA32_MCG_CAP.CNT >7
41FH
1055
IA32_MC7_MISC
MC7_MISC
If IA32_MCG_CAP.CNT >7
35-26 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
420H
1056
IA32_MC8_CTL
421H
1057
IA32_MC8_STATUS
1
Comment
MSR/Bit Description
MC8_CTL
If IA32_MCG_CAP.CNT >8
MC8_STATUS
If IA32_MCG_CAP.CNT >8
422H
1058
IA32_MC8_ADDR
MC8_ADDR
If IA32_MCG_CAP.CNT >8
423H
1059
IA32_MC8_MISC
MC8_MISC
If IA32_MCG_CAP.CNT >8
424H
1060
IA32_MC9_CTL
MC9_CTL
If IA32_MCG_CAP.CNT >9
425H
1061
IA32_MC9_STATUS
MC9_STATUS
If IA32_MCG_CAP.CNT >9
426H
1062
IA32_MC9_ADDR1
MC9_ADDR
If IA32_MCG_CAP.CNT >9
427H
1063
IA32_MC9_MISC
MC9_MISC
If IA32_MCG_CAP.CNT >9
428H
1064
IA32_MC10_CTL
MC10_CTL
If IA32_MCG_CAP.CNT >10
429H
1065
IA32_MC10_STATUS
MC10_STATUS
If IA32_MCG_CAP.CNT >10
42AH
1066
IA32_MC10_ADDR1
MC10_ADDR
If IA32_MCG_CAP.CNT >10
42BH
1067
IA32_MC10_MISC
MC10_MISC
If IA32_MCG_CAP.CNT >10
42CH
1068
IA32_MC11_CTL
MC11_CTL
If IA32_MCG_CAP.CNT >11
42DH
1069
IA32_MC11_STATUS
MC11_STATUS
If IA32_MCG_CAP.CNT >11
42EH
1070
IA32_MC11_ADDR1
MC11_ADDR
If IA32_MCG_CAP.CNT >11
42FH
1071
IA32_MC11_MISC
MC11_MISC
If IA32_MCG_CAP.CNT >11
430H
1072
IA32_MC12_CTL
MC12_CTL
If IA32_MCG_CAP.CNT >12
431H
1073
IA32_MC12_STATUS
MC12_STATUS
If IA32_MCG_CAP.CNT >12
432H
1074
IA32_MC12_ADDR1
MC12_ADDR
If IA32_MCG_CAP.CNT >12
433H
1075
IA32_MC12_MISC
MC12_MISC
If IA32_MCG_CAP.CNT >12
434H
1076
IA32_MC13_CTL
MC13_CTL
If IA32_MCG_CAP.CNT >13
435H
1077
IA32_MC13_STATUS
MC13_STATUS
If IA32_MCG_CAP.CNT >13
436H
1078
IA32_MC13_ADDR1
MC13_ADDR
If IA32_MCG_CAP.CNT >13
437H
1079
IA32_MC13_MISC
MC13_MISC
If IA32_MCG_CAP.CNT >13
438H
1080
IA32_MC14_CTL
MC14_CTL
If IA32_MCG_CAP.CNT >14
439H
1081
IA32_MC14_STATUS
MC14_STATUS
If IA32_MCG_CAP.CNT >14
43AH
1082
IA32_MC14_ADDR1
MC14_ADDR
If IA32_MCG_CAP.CNT >14
43BH
1083
IA32_MC14_MISC
MC14_MISC
If IA32_MCG_CAP.CNT >14
43CH
1084
IA32_MC15_CTL
MC15_CTL
If IA32_MCG_CAP.CNT >15
43DH
1085
IA32_MC15_STATUS
MC15_STATUS
If IA32_MCG_CAP.CNT >15
43EH
1086
IA32_MC15_ADDR1
MC15_ADDR
If IA32_MCG_CAP.CNT >15
43FH
1087
IA32_MC15_MISC
MC15_MISC
If IA32_MCG_CAP.CNT >15
440H
1088
IA32_MC16_CTL
MC16_CTL
If IA32_MCG_CAP.CNT >16
441H
1089
IA32_MC16_STATUS
MC16_STATUS
If IA32_MCG_CAP.CNT >16
442H
1090
IA32_MC16_ADDR1
MC16_ADDR
If IA32_MCG_CAP.CNT >16
443H
1091
IA32_MC16_MISC
MC16_MISC
If IA32_MCG_CAP.CNT >16
444H
1092
IA32_MC17_CTL
MC17_CTL
If IA32_MCG_CAP.CNT >17
Vol. 3C 35-27
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
445H
Decimal
1093
Architectural MSR Name and bit
fields
(Former MSR Name)
IA32_MC17_STATUS
1
Comment
MSR/Bit Description
MC17_STATUS
If IA32_MCG_CAP.CNT >17
446H
1094
IA32_MC17_ADDR
MC17_ADDR
If IA32_MCG_CAP.CNT >17
447H
1095
IA32_MC17_MISC
MC17_MISC
If IA32_MCG_CAP.CNT >17
448H
1096
IA32_MC18_CTL
MC18_CTL
If IA32_MCG_CAP.CNT >18
449H
1097
IA32_MC18_STATUS
MC18_STATUS
If IA32_MCG_CAP.CNT >18
44AH
1098
IA32_MC18_ADDR1
MC18_ADDR
If IA32_MCG_CAP.CNT >18
44BH
1099
IA32_MC18_MISC
MC18_MISC
If IA32_MCG_CAP.CNT >18
44CH
1100
IA32_MC19_CTL
MC19_CTL
If IA32_MCG_CAP.CNT >19
44DH
1101
IA32_MC19_STATUS
MC19_STATUS
If IA32_MCG_CAP.CNT >19
44EH
1102
IA32_MC19_ADDR1
MC19_ADDR
If IA32_MCG_CAP.CNT >19
44FH
1103
IA32_MC19_MISC
MC19_MISC
If IA32_MCG_CAP.CNT >19
450H
1104
IA32_MC20_CTL
MC20_CTL
If IA32_MCG_CAP.CNT >20
451H
1105
IA32_MC20_STATUS
MC20_STATUS
If IA32_MCG_CAP.CNT >20
452H
1106
IA32_MC20_ADDR1
MC20_ADDR
If IA32_MCG_CAP.CNT >20
453H
1107
IA32_MC20_MISC
MC20_MISC
If IA32_MCG_CAP.CNT >20
454H
1108
IA32_MC21_CTL
MC21_CTL
If IA32_MCG_CAP.CNT >21
455H
1109
IA32_MC21_STATUS
MC21_STATUS
If IA32_MCG_CAP.CNT >21
456H
1110
IA32_MC21_ADDR1
MC21_ADDR
If IA32_MCG_CAP.CNT >21
457H
1111
IA32_MC21_MISC
MC21_MISC
If IA32_MCG_CAP.CNT >21
458H
IA32_MC22_CTL
MC22_CTL
If IA32_MCG_CAP.CNT >22
459H
IA32_MC22_STATUS
MC22_STATUS
If IA32_MCG_CAP.CNT >22
45AH
IA32_MC22_ADDR1
MC22_ADDR
If IA32_MCG_CAP.CNT >22
45BH
IA32_MC22_MISC
MC22_MISC
If IA32_MCG_CAP.CNT >22
45CH
IA32_MC23_CTL
MC23_CTL
If IA32_MCG_CAP.CNT >23
45DH
IA32_MC23_STATUS
MC23_STATUS
If IA32_MCG_CAP.CNT >23
45EH
IA32_MC23_ADDR1
MC23_ADDR
If IA32_MCG_CAP.CNT >23
45FH
IA32_MC23_MISC
MC23_MISC
If IA32_MCG_CAP.CNT >23
460H
IA32_MC24_CTL
MC24_CTL
If IA32_MCG_CAP.CNT >24
461H
IA32_MC24_STATUS
MC24_STATUS
If IA32_MCG_CAP.CNT >24
462H
IA32_MC24_ADDR1
MC24_ADDR
If IA32_MCG_CAP.CNT >24
463H
IA32_MC24_MISC
MC24_MISC
If IA32_MCG_CAP.CNT >24
464H
IA32_MC25_CTL
MC25_CTL
If IA32_MCG_CAP.CNT >25
465H
IA32_MC25_STATUS
MC25_STATUS
If IA32_MCG_CAP.CNT >25
466H
IA32_MC25_ADDR1
MC25_ADDR
If IA32_MCG_CAP.CNT >25
467H
IA32_MC25_MISC
MC25_MISC
If IA32_MCG_CAP.CNT >25
468H
IA32_MC26_CTL
MC26_CTL
If IA32_MCG_CAP.CNT >26
469H
IA32_MC26_STATUS
MC26_STATUS
If IA32_MCG_CAP.CNT >26
35-28 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
46AH
IA32_MC26_ADDR1
MC26_ADDR
If IA32_MCG_CAP.CNT >26
46BH
IA32_MC26_MISC
MC26_MISC
If IA32_MCG_CAP.CNT >26
46CH
IA32_MC27_CTL
MC27_CTL
If IA32_MCG_CAP.CNT >27
46DH
IA32_MC27_STATUS
MC27_STATUS
If IA32_MCG_CAP.CNT >27
46EH
IA32_MC27_ADDR1
MC27_ADDR
If IA32_MCG_CAP.CNT >27
46FH
IA32_MC27_MISC
MC27_MISC
If IA32_MCG_CAP.CNT >27
470H
IA32_MC28_CTL
MC28_CTL
If IA32_MCG_CAP.CNT >28
471H
IA32_MC28_STATUS
MC28_STATUS
If IA32_MCG_CAP.CNT >28
472H
IA32_MC28_ADDR1
MC28_ADDR
If IA32_MCG_CAP.CNT >28
473H
IA32_MC28_MISC
MC28_MISC
If IA32_MCG_CAP.CNT >28
Reporting Register of Basic VMX
Capabilities (R/O)
If CPUID.01H:ECX.[5] = 1
480H
1152
IA32_VMX_BASIC
481H
1153
IA32_VMX_PINBASED_CTLS
See Appendix A.1, “Basic VMX Information.”
Capability Reporting Register of Pinbased VM-execution Controls (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.3.1, “Pin-Based VMExecution Controls.”
482H
1154
IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary
Processor-based VM-execution Controls
(R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.3.2, “Primary ProcessorBased VM-Execution Controls.”
483H
1155
IA32_VMX_EXIT_CTLS
484H
1156
IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-exit
Controls (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.4, “VM-Exit Controls.”
Capability Reporting Register of VMentry Controls (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.5, “VM-Entry Controls.”
485H
1157
IA32_VMX_MISC
Reporting Register of Miscellaneous
VMX Capabilities (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.6, “Miscellaneous Data.”
486H
1158
IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits
Fixed to 0 (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits
Fixed to 1 (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits
Fixed to 0 (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.8, “VMX-Fixed Bits in CR4.”
Vol. 3C 35-29
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
489H
1161
IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits
Fixed to 1 (R/O)
48AH
1162
IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS
Field Enumeration (R/O)
If CPUID.01H:ECX.[5] = 1
See Appendix A.8, “VMX-Fixed Bits in CR4.”
If CPUID.01H:ECX.[5] = 1
See Appendix A.9, “VMCS Enumeration.”
48BH
1163
IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of
Secondary Processor-based
VM-execution Controls (R/O)
If ( CPUID.01H:ECX.[5] &&
IA32_VMX_PROCBASED_C
TLS[63])
See Appendix A.3.3, “Secondary ProcessorBased VM-Execution Controls.”
48CH
48DH
1164
1165
IA32_VMX_EPT_VPID_CAP
IA32_VMX_TRUE_PINBASED_CTLS
See Appendix A.10, “VPID and EPT
Capabilities.”
If ( CPUID.01H:ECX.[5] &&
IA32_VMX_PROCBASED_C
TLS[63] && (
IA32_VMX_PROCBASED_C
TLS2[33] ||
IA32_VMX_PROCBASED_C
TLS2[37]) )
Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
If ( CPUID.01H:ECX.[5] = 1
&& IA32_VMX_BASIC[55] )
Capability Reporting Register of EPT and
VPID (R/O)
See Appendix A.3.1, “Pin-Based VMExecution Controls.”
48EH
1166
IA32_VMX_TRUE_PROCBASED_CTLS
Capability Reporting Register of Primary
Processor-based VM-execution Flex
Controls (R/O)
If( CPUID.01H:ECX.[5] = 1
&& IA32_VMX_BASIC[55] )
See Appendix A.3.2, “Primary ProcessorBased VM-Execution Controls.”
48FH
1167
IA32_VMX_TRUE_EXIT_CTLS
Capability Reporting Register of VM-exit
Flex Controls (R/O)
If( CPUID.01H:ECX.[5] = 1
&& IA32_VMX_BASIC[55] )
See Appendix A.4, “VM-Exit Controls.”
490H
1168
IA32_VMX_TRUE_ENTRY_CTLS
Capability Reporting Register of VMentry Flex Controls (R/O)
If( CPUID.01H:ECX.[5] = 1
&& IA32_VMX_BASIC[55] )
See Appendix A.5, “VM-Entry Controls.”
491H
1169
IA32_VMX_VMFUNC
Capability Reporting Register of VMfunction Controls (R/O)
If( CPUID.01H:ECX.[5] = 1
&& IA32_VMX_BASIC[55] )
4C1H
1217
IA32_A_PMC0
Full Width Writable IA32_PMC0 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
0) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C2H
1218
IA32_A_PMC1
Full Width Writable IA32_PMC1 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
1) &&
IA32_PERF_CAPABILITIES[
13] = 1
35-30 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
4C3H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
1219
IA32_A_PMC2
Comment
MSR/Bit Description
Full Width Writable IA32_PMC2 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
2) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C4H
1220
IA32_A_PMC3
Full Width Writable IA32_PMC3 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
3) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C5H
1221
IA32_A_PMC4
Full Width Writable IA32_PMC4 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
4) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C6H
1222
IA32_A_PMC5
Full Width Writable IA32_PMC5 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
5) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C7H
1223
IA32_A_PMC6
Full Width Writable IA32_PMC6 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
6) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C8H
1224
IA32_A_PMC7
Full Width Writable IA32_PMC7 Alias (R/W)
(If CPUID.0AH: EAX[15:8] >
7) &&
IA32_PERF_CAPABILITIES[
13] = 1
4D0H
500H
1232
1280
IA32_MCG_EXT_CTL
(R/W)
If IA32_MCG_CAP.LMCE_P
=1
0
LMCE_EN.
63:1
Reserved.
IA32_SGX_SVN_STATUS
Status and SVN Threshold of SGX Support
for ACM (RO).
If CPUID.(EAX=07H,
ECX=0H): EBX[2] = 1
0
Lock.
See Section 42.11.3,
“Interactions with
Authenticated Code
Modules (ACMs)”.
15:1
Reserved.
23:16
SGX_SVN_SINIT.
63:24
Reserved.
See Section 42.11.3,
“Interactions with
Authenticated Code
Modules (ACMs)”.
Vol. 3C 35-31
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
560H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
1376
570H
1377
1392
35-32 Vol. 3C
MSR/Bit Description
IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W)
6:0
Reserved
3
561H
Comment
MAXPHYADDR -1:7
Base physical address
63:MAXPHYADDR
Reserved.
IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register
(R/W)
6:0
Reserved
31:7
MaskOrTableOffset
63:32
Output Offset.
IA32_RTIT_CTL
Trace Control Register (R/W)
0
TraceEn
1
CYCEn
2
OS
3
User
5:4
Reserved,
6
FabricEn
7
CR3 filter
8
ToPA
9
MTCEn
10
TSCEn
11
DisRETC
12
Reserved, MBZ
13
BranchEn
17:14
MTCFreq
18
Reserved, MBZ
22:19
CYCThresh
23
Reserved, MBZ
If ((CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) && (
(CPUID.(EAX=14H,ECX=0):
ECX[0] = 1) ||
(CPUID.(EAX=14H,ECX=0):
ECX[2] = 1) ) )
If ((CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) && (
(CPUID.(EAX=14H,ECX=0):
ECX[0] = 1) ||
(CPUID.(EAX=14H,ECX=0):
ECX[2] = 1) ) )
If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1)
If (CPUID.(EAX=07H,
ECX=0):EBX[1] = 1)
If (CPUID.(EAX=07H,
ECX=0):ECX[3] = 1)
If (CPUID.(EAX=07H,
ECX=0):EBX[3] = 1)
If (CPUID.(EAX=07H,
ECX=0):EBX[3] = 1)
If (CPUID.(EAX=07H,
ECX=0):EBX[1] = 1)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
571H
572H
580H
581H
582H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
1393
1394
1408
1409
1410
Comment
MSR/Bit Description
27:24
PSBFreq
31:28
Reserved, MBZ
35:32
ADDR0_CFG
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 0)
39:36
ADDR1_CFG
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 1)
43:40
ADDR2_CFG
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 2)
47:44
ADDR3_CFG
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 3)
63:48
Reserved, MBZ.
IA32_RTIT_STATUS
Tracing Status Register (R/W)
If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1)
0
FilterEn, (writes ignored)
If (CPUID.(EAX=07H,
ECX=0):EBX[2] = 1)
1
ContexEn, (writes ignored)
2
TriggerEn, (writes ignored)
3
Reserved
4
Error
5
Stopped
31:6
Reserved, MBZ
48:32
PacketByteCnt
63:49
Reserved.
IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W)
4:0
Reserved
63:5
CR3[63:5] value to match
IA32_RTIT_ADDR0_A
Region 0 Start Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
IA32_RTIT_ADDR0_B
Region 0 End Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
IA32_RTIT_ADDR1_A
Region 1 Start Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
If (CPUID.(EAX=07H,
ECX=0):EBX[1] = 1)
If (CPUID.(EAX=07H,
ECX=0):EBX[1] > 3)
If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1)
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 0)
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 0)
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 1)
Vol. 3C 35-33
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
583H
584H
585H
586H
587H
600H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
1411
1412
1413
1414
1415
1536
Comment
MSR/Bit Description
IA32_RTIT_ADDR1_B
Region 1 End Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
IA32_RTIT_ADDR2_A
Region 2 Start Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
IA32_RTIT_ADDR2_B
Region 2 End Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
IA32_RTIT_ADDR3_A
Region 3 Start Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
IA32_RTIT_ADDR3_B
Region 3 End Address (R/W)
47:0
Virtual Address
63:48
SignExt_VA
IA32_DS_AREA
DS Save Area (R/W)
Points to the linear address of the first
byte of the DS buffer management area,
which is used to manage the BTS and PEBS
buffers.
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 1)
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 2)
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 2)
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 3)
If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 3)
If( CPUID.01H:EDX.DS[21]
=1
See Section 18.15.4, “Debug Store (DS)
Mechanism.”
63:0
The linear address of the first byte of the
DS buffer management area, if IA-32e
mode is active.
31:0
The linear address of the first byte of the
DS buffer management area, if not in IA32e mode.
63:32
Reserved if not in IA-32e mode.
6E0H
1760
IA32_TSC_DEADLINE
TSC Target of Local APIC’s TSC Deadline
Mode (R/W)
If CPUID.01H:ECX.[24] = 1
770H
1904
IA32_PM_ENABLE
Enable/disable HWP (R/W)
If CPUID.06H:EAX.[7] = 1
0
HWP_ENABLE (R/W1-Once).
If CPUID.06H:EAX.[7] = 1
See Section 14.4.2, “Enabling HWP”
771H
1905
35-34 Vol. 3C
63:1
Reserved.
IA32_HWP_CAPABILITIES
HWP Performance Range Enumeration
(RO)
If CPUID.06H:EAX.[7] = 1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
7:0
Comment
MSR/Bit Description
Highest_Performance
If CPUID.06H:EAX.[7] = 1
See Section 14.4.3, “HWP Performance
Range and Dynamic Capabilities”
15:8
Guaranteed_Performance
If CPUID.06H:EAX.[7] = 1
See Section 14.4.3, “HWP Performance
Range and Dynamic Capabilities”
23:16
Most_Efficient_Performance
If CPUID.06H:EAX.[7] = 1
See Section 14.4.3, “HWP Performance
Range and Dynamic Capabilities”
31:24
Lowest_Performance
If CPUID.06H:EAX.[7] = 1
See Section 14.4.3, “HWP Performance
Range and Dynamic Capabilities”
772H
1906
63:32
Reserved.
IA32_HWP_REQUEST_PKG
Power Management Control Hints for All
Logical Processors in a Package (R/W)
If CPUID.06H:EAX.[11] = 1
7:0
Minimum_Performance
If CPUID.06H:EAX.[11] = 1
See Section 14.4.4, “Managing HWP”
15:8
Maximum_Performance
If CPUID.06H:EAX.[11] = 1
See Section 14.4.4, “Managing HWP”
23:16
Desired_Performance
If CPUID.06H:EAX.[11] = 1
See Section 14.4.4, “Managing HWP”
31:24
Energy_Performance_Preference
See Section 14.4.4, “Managing HWP”
41:32
Activity_Window
See Section 14.4.4, “Managing HWP”
773H
1907
If CPUID.06H:EAX.[11] = 1
&&
CPUID.06H:EAX.[10] = 1
If CPUID.06H:EAX.[11] = 1
&&
CPUID.06H:EAX.[9] = 1
63:42
Reserved.
IA32_HWP_INTERRUPT
Control HWP Native Interrupts (R/W)
If CPUID.06H:EAX.[8] = 1
0
EN_Guaranteed_Performance_Change.
If CPUID.06H:EAX.[8] = 1
See Section 14.4.6, “HWP Notifications”
1
EN_Excursion_Minimum.
If CPUID.06H:EAX.[8] = 1
See Section 14.4.6, “HWP Notifications”
774H
1908
63:2
Reserved.
IA32_HWP_REQUEST
Power Management Control Hints to a
Logical Processor (R/W)
If CPUID.06H:EAX.[7] = 1
7:0
Minimum_Performance
If CPUID.06H:EAX.[7] = 1
See Section 14.4.4, “Managing HWP”
15:8
Maximum_Performance
If CPUID.06H:EAX.[7] = 1
See Section 14.4.4, “Managing HWP”
Vol. 3C 35-35
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
23:16
Comment
MSR/Bit Description
Desired_Performance
If CPUID.06H:EAX.[7] = 1
See Section 14.4.4, “Managing HWP”
31:24
Energy_Performance_Preference
See Section 14.4.4, “Managing HWP”
41:32
Activity_Window
See Section 14.4.4, “Managing HWP”
42
Package_Control
See Section 14.4.4, “Managing HWP”
777H
1911
If CPUID.06H:EAX.[7] = 1
&& CPUID.06H:EAX.[10] =
1
If CPUID.06H:EAX.[7] = 1
&& CPUID.06H:EAX.[9] = 1
If CPUID.06H:EAX.[7] = 1
&& CPUID.06H:EAX.[11] =
1
63:43
Reserved.
IA32_HWP_STATUS
Log bits indicating changes to
Guaranteed & excursions to Minimum
(R/W)
If CPUID.06H:EAX.[7] = 1
0
Guaranteed_Performance_Change
(R/WC0).
If CPUID.06H:EAX.[7] = 1
See Section 14.4.5, “HWP Feedback”
1
Reserved.
2
Excursion_To_Minimum (R/WC0).
If CPUID.06H:EAX.[7] = 1
See Section 14.4.5, “HWP Feedback”
802H
2050
63:3
Reserved.
IA32_X2APIC_APICID
x2APIC ID Register (R/O)
See x2APIC Specification
If CPUID.01H:ECX[21] = 1
&& IA32_APIC_BASE.[10]
=1
803H
2051
IA32_X2APIC_VERSION
x2APIC Version Register (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
808H
2056
IA32_X2APIC_TPR
x2APIC Task Priority Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
80AH
2058
IA32_X2APIC_PPR
x2APIC Processor Priority Register (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
80BH
2059
IA32_X2APIC_EOI
x2APIC EOI Register (W/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
80DH
2061
IA32_X2APIC_LDR
x2APIC Logical Destination Register
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
80FH
2063
IA32_X2APIC_SIVR
x2APIC Spurious Interrupt Vector
Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
35-36 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
810H
2064
IA32_X2APIC_ISR0
x2APIC In-Service Register Bits 31:0
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
811H
2065
IA32_X2APIC_ISR1
x2APIC In-Service Register Bits 63:32
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
812H
2066
IA32_X2APIC_ISR2
x2APIC In-Service Register Bits 95:64
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
813H
2067
IA32_X2APIC_ISR3
x2APIC In-Service Register Bits 127:96
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
814H
2068
IA32_X2APIC_ISR4
x2APIC In-Service Register Bits 159:128
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
815H
2069
IA32_X2APIC_ISR5
x2APIC In-Service Register Bits 191:160
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
816H
2070
IA32_X2APIC_ISR6
x2APIC In-Service Register Bits 223:192
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
817H
2071
IA32_X2APIC_ISR7
x2APIC In-Service Register Bits 255:224
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
818H
2072
IA32_X2APIC_TMR0
x2APIC Trigger Mode Register Bits 31:0
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
819H
2073
IA32_X2APIC_TMR1
x2APIC Trigger Mode Register Bits 63:32
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
81AH
2074
IA32_X2APIC_TMR2
x2APIC Trigger Mode Register Bits 95:64
(R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
81BH
2075
IA32_X2APIC_TMR3
x2APIC Trigger Mode Register Bits
127:96 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
81CH
2076
IA32_X2APIC_TMR4
x2APIC Trigger Mode Register Bits
159:128 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
81DH
2077
IA32_X2APIC_TMR5
x2APIC Trigger Mode Register Bits
191:160 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
81EH
2078
IA32_X2APIC_TMR6
x2APIC Trigger Mode Register Bits
223:192 (R/O)
If ( CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
= 1)
Vol. 3C 35-37
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Decimal
Architectural MSR Name and bit
fields
(Former MSR Name)
Comment
MSR/Bit Description
81FH
2079
IA32_X2APIC_TMR7
x2APIC Trigger Mode Register Bits
255:224 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
820H
2080
IA32_X2APIC_IRR0
x2APIC Interrupt Request Register Bits
31:0 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
821H
2081
IA32_X2APIC_IRR1
x2APIC Interrupt Request Register Bits
63:32 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
822H
2082
IA32_X2APIC_IRR2
x2APIC Interrupt Request Register Bits
95:64 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
823H
2083
IA32_X2APIC_IRR3
x2APIC Interrupt Request Register Bits
127:96 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
824H
2084
IA32_X2APIC_IRR4
x2APIC Interrupt Request Register Bits
159:128 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
825H
2085
IA32_X2APIC_IRR5
x2APIC Interrupt Request Register Bits
191:160 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
826H
2086
IA32_X2APIC_IRR6
x2APIC Interrupt Request Register Bits
223:192 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
827H
2087
IA32_X2APIC_IRR7
x2APIC Interrupt Request Register Bits
255:224 (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
828H
2088
IA32_X2APIC_ESR
x2APIC Error Status Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
82FH
2095
IA32_X2APIC_LVT_CMCI
x2APIC LVT Corrected Machine Check
Interrupt Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
830H
2096
IA32_X2APIC_ICR
x2APIC Interrupt Command Register
(R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
832H
2098
IA32_X2APIC_LVT_TIMER
x2APIC LVT Timer Interrupt Register
(R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
833H
2099
IA32_X2APIC_LVT_THERMAL
x2APIC LVT Thermal Sensor Interrupt
Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
834H
2100
IA32_X2APIC_LVT_PMI
x2APIC LVT Performance Monitor
Interrupt Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
35-38 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
835H
2101
IA32_X2APIC_LVT_LINT0
x2APIC LVT LINT0 Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
836H
2102
IA32_X2APIC_LVT_LINT1
x2APIC LVT LINT1 Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
837H
2103
IA32_X2APIC_LVT_ERROR
x2APIC LVT Error Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
838H
2104
IA32_X2APIC_INIT_COUNT
x2APIC Initial Count Register (R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
839H
2105
IA32_X2APIC_CUR_COUNT
x2APIC Current Count Register (R/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
83EH
2110
IA32_X2APIC_DIV_CONF
x2APIC Divide Configuration Register
(R/W)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
83FH
2111
IA32_X2APIC_SELF_IPI
x2APIC Self IPI Register (W/O)
If CPUID.01H:ECX.[21] = 1
&& IA32_APIC_BASE.[10]
=1
C80H
3200
IA32_DEBUG_INTERFACE
Silicon Debug Feature Control (R/W)
If CPUID.01H:ECX.[11] = 1
0
Enable (R/W)
If CPUID.01H:ECX.[11] = 1
BIOS set 1 to enable Silicon debug features.
Default is 0
C81H
3201
29:1
Reserved.
30
Lock (R/W): If 1, locks any further change
to the MSR. The lock bit is set automatically
on the first SMI assertion even if not
explicitly set by BIOS. Default is 0.
If CPUID.01H:ECX.[11] = 1
31
Debug Occurred (R/O): This “sticky bit” is
set by hardware to indicate the status of
bit 0. Default is 0.
If CPUID.01H:ECX.[11] = 1
63:32
Reserved.
IA32_L3_QOS_CFG
L3 QOS Configuration (R/W)
0
Enable (R/W)
If ( CPUID.(EAX=10H,
ECX=1):ECX.[2] = 1 )
Set 1 to enable L3 CAT masks and COS to
operate in Code and Data Prioritization
(CDP) mode
C8DH
3213
63:1
Reserved.
IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
7:0
Event ID: ID of a supported monitoring
event to report via IA32_QM_CTR.
If ( CPUID.(EAX=07H,
ECX=0):EBX.[12] = 1 )
Vol. 3C 35-39
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
C8EH
C8FH
Decimal
3214
3215
C90H D8FH
C90H
C90H+
n
3216
Architectural MSR Name and bit
fields
(Former MSR Name)
35-40 Vol. 3C
MSR/Bit Description
31: 8
Reserved.
N+31:32
Resource Monitoring ID: ID for monitoring
hardware to report monitored data via
IA32_QM_CTR.
63:N+32
Reserved.
IA32_QM_CTR
Monitoring Counter Register (R/O)
61:0
Resource Monitored Data
62
Unavailable: If 1, indicates data for this
RMID is not available or not monitored for
this resource or RMID.
63
Error: If 1, indicates and unsupported RMID
or event type was written to
IA32_PQR_QM_EVTSEL.
IA32_PQR_ASSOC
Resource Association Register (R/W)
If ( (CPUID.(EAX=07H,
ECX=0):EBX[12] =1) or
(CPUID.(EAX=07H,
ECX=0):EBX[15] =1 ) )
N-1:0
Resource Monitoring ID (R/W): ID for
monitoring hardware to track internal
operation, e.g. memory access.
N = Ceil (Log2 (
CPUID.(EAX= 0FH,
ECX=0H).EBX[31:0] +1))
31:N
Reserved
63:32
COS (R/W). The class of service
(COS) to enforce (on writes);
returns the current COS when
read.
Reserved MSR Address Space for CAT
Mask Registers
See Section 17.17.3.1, “Enumeration and
Detection Support of Cache Allocation
Technology”
IA32_L3_MASK_0
L3 CAT Mask for COS0 (R/W)
31:0
Capacity Bit Mask (R/W)
63:32
Reserved.
3216+n IA32_L3_MASK_n
D10H D4FH
Comment
L3 CAT Mask for COSn (R/W)
31:0
Capacity Bit Mask (R/W)
63:32
Reserved.
Reserved MSR Address Space for L2
CAT Mask Registers
See Section 17.17.3.1, “Enumeration and
Detection Support of Cache Allocation
Technology”
N = Ceil (Log2 (
CPUID.(EAX= 0FH,
ECX=0H).EBX[31:0] +1))
If ( CPUID.(EAX=07H,
ECX=0):EBX.[12] = 1 )
If ( CPUID.(EAX=07H,
ECX=0):EBX.[15] = 1 )
If (CPUID.(EAX=10H,
ECX=0H):EBX[1] != 0)
n = CPUID.(EAX=10H,
ECX=1H):EDX[15:0]
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
D10H
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
3344
DA0H
DB0H
3472
3488
3504
MSR/Bit Description
IA32_L2_MASK_0
L2 CAT Mask for COS0 (R/W)
31:0
Capacity Bit Mask (R/W)
63:32
Reserved.
D10H+ 3344+n IA32_L2_MASK_n
n
D90H
Comment
L2 CAT Mask for COSn (R/W)
31:0
Capacity Bit Mask (R/W)
63:32
Reserved.
IA32_BNDCFGS
Supervisor State of MPX Configuration.
(R/W)
0
EN: Enable Intel MPX in supervisor mode
1
BNDPRESERVE: Preserve the bounds
registers for near branch instructions in the
absence of the BND prefix
11:2
Reserved, must be 0
If (CPUID.(EAX=10H,
ECX=0H):EBX[2] != 0)
n = CPUID.(EAX=10H,
ECX=2H):EDX[15:0]
If (CPUID.(EAX=07H,
ECX=0H):EBX[14] = 1)
63:12
Base Address of Bound Directory.
IA32_XSS
Extended Supervisor State Mask (R/W)
7:0
Reserved
8
Trace Packet Configuration State (R/W)
63:9
Reserved.
IA32_PKG_HDC_CTL
Package Level Enable/disable HDC (R/W)
If CPUID.06H:EAX.[13] = 1
0
HDC_Pkg_Enable (R/W)
If CPUID.06H:EAX.[13] = 1
If( CPUID.(0DH, 1):EAX.[3]
=1
Force HDC idling or wake up HDC-idled
logical processors in the package. See
Section 14.5.2, “Package level Enabling
HDC”
DB1H
3505
63:1
Reserved.
IA32_PM_CTL1
Enable/disable HWP (R/W)
If CPUID.06H:EAX.[13] = 1
0
HDC_Allow_Block (R/W)
If CPUID.06H:EAX.[13] = 1
Allow/Block this logical processor for
package level HDC control. See Section
14.5.3
DB2H
3506
63:1
Reserved.
IA32_THREAD_STALL
Per-Logical_Processor HDC Idle
Residency (R/0)
If CPUID.06H:EAX.[13] = 1
63:0
Stall_Cycle_Cnt (R/W)
If CPUID.06H:EAX.[13] = 1
Stalled cycles due to HDC forced idle on this
logical processor. See Section 14.5.4.1
Vol. 3C 35-41
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-2. IA-32 Architectural MSRs (Contd.)
Register
Address
Hex
Architectural MSR Name and bit
fields
(Former MSR Name)
Decimal
Comment
MSR/Bit Description
4000_
0000H
4000_
00FFH
Reserved MSR Address Space
All existing and future processors will
not implement MSR in this range.
C000_
0080H
IA32_EFER
Extended Feature Enables
0
SYSCALL Enable: IA32_EFER.SCE (R/W)
If (
CPUID.80000001H:EDX.[2
0] ||
CPUID.80000001H:EDX.[2
9])
Enables SYSCALL/SYSRET instructions in
64-bit mode.
7:1
Reserved.
8
IA-32e Mode Enable: IA32_EFER.LME
(R/W)
Enables IA-32e mode operation.
9
Reserved.
10
IA-32e Mode Active: IA32_EFER.LMA (R)
Indicates IA-32e mode is active when set.
11
Execute Disable Bit Enable:
IA32_EFER.NXE (R/W)
63:12
Reserved.
C000_
0081H
IA32_STAR
System Call Target Address (R/W)
If
CPUID.80000001:EDX.[29]
=1
C000_
0082H
IA32_LSTAR
IA-32e Mode System Call Target Address
(R/W)
If
CPUID.80000001:EDX.[29]
=1
C000_
0084H
IA32_FMASK
System Call Flag Mask (R/W)
If
CPUID.80000001:EDX.[29]
=1
C000_
0100H
IA32_FS_BASE
Map of BASE Address of FS (R/W)
If
CPUID.80000001:EDX.[29]
=1
C000_
0101H
IA32_GS_BASE
Map of BASE Address of GS (R/W)
If
CPUID.80000001:EDX.[29]
=1
C000_
0102H
IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS
(R/W)
If
CPUID.80000001:EDX.[29]
=1
C000_
0103H
IA32_TSC_AUX
Auxiliary TSC (RW)
If CPUID.80000001H:
EDX[27] = 1
31:0
AUX: Auxiliary signature of TSC
63:32
Reserved.
35-42 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
NOTES:
1. In processors based on Intel NetBurst® microarchitecture, MSR addresses 180H-197H are supported, software must treat them as
model-specific. Starting with Intel Core Duo processors, MSR addresses 180H-185H, 188H-197H are reserved.
2. The *_ADDR MSRs may or may not be present; this depends on flag settings in IA32_MCi_STATUS. See Section 15.3.2.3 and Section
15.3.2.4 for more information.
3. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
35.2
MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY
Table 35-3 lists model-specific registers (MSRs) for Intel Core 2 processor family and for Intel Xeon processors
based on Intel Core microarchitecture, architectural MSR addresses are also included in Table 35-3. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_0FH, see Table 35-1.
MSRs listed in Table 35-2 and Table 35-3 are also supported by processors based on the Enhanced Intel Core
microarchitecture. Processors based on the Enhanced Intel Core microarchitecture have the CPUID signature
DisplayFamily_DisplayModel of 06_17H.
The column “Shared/Unique” applies to multi-core processors based on Intel Core microarchitecture. “Unique”
means each processor core has a separate MSR, or a bit field in an MSR governs only a core independently.
“Shared” means the MSR or the bit field in an MSR address governs the operation of both processor cores.
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Unique
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Unique
See Section 35.22, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_SIZ Unique
E
See Section 8.10.5, “Monitor/Mwait Address Range Determination.”
andTable 35-2.
10H
16
IA32_TIME_STAMP_COUNT
ER
Unique
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
17H
23
IA32_PLATFORM_ID
Shared
Platform ID (R)
See Table 35-2.
17H
23
MSR_PLATFORM_ID
Shared
Model Specific Platform ID (R)
7:0
Reserved.
12:8
Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
49:13
Reserved.
52:50
See Table 35-2.
63:53
Reserved.
1BH
27
IA32_APIC_BASE
Unique
See Section 10.4.4, “Local APIC Status and Location.” and
Table 35-2.
2AH
42
MSR_EBL_CR_POWERON
Shared
Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current
processor configuration.
0
Reserved.
Vol. 3C 35-43
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
1
Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
2
Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
3
MCERR# Drive Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
4
Address Parity Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
5
Reserved.
6
Reserved.
7
BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
8
Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled
9
Execute BIST (R/O)
1 = Enabled; 0 = Disabled
10
MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
11
Intel TXT Capable Chipset. (R/O)
1 = Present; 0 = Not Present
12
BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
13
Reserved.
14
1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes
15
Reserved.
17:16
APIC Cluster ID (R/O)
18
N/2 Non-Integer Bus Ratio (R/O)
0 = Integer ratio; 1 = Non-integer ratio
35-44 Vol. 3C
19
Reserved.
21: 20
Symmetric Arbitration ID (R/O)
26:22
Integer Bus Frequency Ratio (R/O)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Dec
3AH
58
Register Name
MSR_FEATURE_CONTROL
Shared/
Unique
Unique
Bit Description
Control Features in Intel 64Processor (R/W)
See Table 35-2.
3
Unique
SMRR Enable (R/WL)
When this bit is set and the lock bit is set makes the
SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read visible
and writeable while in SMM.
40H
64
MSR_
LASTBRANCH_0_FROM_IP
Unique
Last Branch Record 0 From IP (R/W)
One of four pairs of last branch record registers on the last branch
record stack. The From_IP part of the stack contains pointers to
the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.5
41H
65
MSR_
LASTBRANCH_1_FROM_IP
Unique
42H
66
MSR_
LASTBRANCH_2_FROM_IP
Unique
See description of MSR_LASTBRANCH_0_FROM_IP.
67
MSR_
LASTBRANCH_3_FROM_IP
Unique
60H
96
MSR_
LASTBRANCH_0_TO_IP
Unique
MSR_
LASTBRANCH_1_TO_IP
Unique
MSR_
LASTBRANCH_2_TO_IP
Unique
MSR_
LASTBRANCH_3_TO_IP
Unique
IA32_BIOS_UPDT_TRIG
Unique
62H
63H
79H
97
98
99
121
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
43H
61H
Last Branch Record 1 From IP (R/W)
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 0 To IP (R/W)
One of four pairs of last branch record registers on the last branch
record stack. This To_IP part of the stack contains pointers to the
destination instruction.
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
BIOS Update Trigger Register (W)
See Table 35-2.
8BH
139
IA32_BIOS_SIGN_ID
Unique
BIOS Update Signature ID (RO)
See Table 35-2.
A0H
160
MSR_SMRR_PHYSBASE
Unique
System Management Mode Base Address register (WO in SMM)
Model-specific implementation of SMRR-like interface, read visible
and write only in SMM.
11:0
Reserved.
31:12
PhysBase. SMRR physical Base Address.
63:32
Reserved.
Vol. 3C 35-45
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Dec
A1H
161
Register Name
MSR_SMRR_PHYSMASK
Shared/
Unique
Unique
Bit Description
System Management Mode Physical Address Mask register
(WO in SMM)
Model-specific implementation of SMRR-like interface, read visible
and write only in SMM.
10:0
Reserved.
11
Valid. Physical address base and range mask are valid.
31:12
PhysMask. SMRR physical address range mask.
63:32
C1H
193
IA32_PMC0
Reserved.
Unique
Performance Counter Register
See Table 35-2.
C2H
194
IA32_PMC1
Unique
CDH
205
MSR_FSB_FREQ
Shared
Performance Counter Register
See Table 35-2.
Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock speed for
processors based on Intel Core microarchitecture:
2:0
•
•
•
•
•
•
101B: 100 MHz (FSB 400)
001B: 133 MHz (FSB 533)
011B: 167 MHz (FSB 667)
010B: 200 MHz (FSB 800)
000B: 267 MHz (FSB 1067)
100B: 333 MHz (FSB 1333)
133.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 000B.
333.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 100B.
63:3
CDH
205
MSR_FSB_FREQ
Reserved.
Shared
Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock speed for
processors based on Enhanced Intel Core microarchitecture:
2:0
35-46 Vol. 3C
•
•
•
•
•
•
•
101B: 100 MHz (FSB 400)
001B: 133 MHz (FSB 533)
011B: 167 MHz (FSB 667)
010B: 200 MHz (FSB 800)
000B: 267 MHz (FSB 1067)
100B: 333 MHz (FSB 1333)
110B: 400 MHz (FSB 1600)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
133.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 110B.
333.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 111B.
63:3
E7H
231
IA32_MPERF
Reserved.
Unique
Maximum Performance Frequency Clock Count (RW)
See Table 35-2.
E8H
232
IA32_APERF
Unique
Actual Performance Frequency Clock Count (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Unique
See Table 35-2.
11
Unique
SMRR Capability Using MSR 0A0H and 0A1H (R)
11EH
281
MSR_BBL_CR_CTL3
Shared
0
L2 Hardware Enabled (RO)
1 = If the L2 is hardware-enabled
0 = Indicates if the L2 is hardware-disabled
7:1
Reserved.
8
L2 Enabled (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the WBINVD
instruction or the assertion of the FLUSH# input.
22:9
Reserved.
23
L2 Not Present (RO)
0 = L2 Present
1 = L2 Not Present
63:24
Reserved.
174H
372
IA32_SYSENTER_CS
Unique
See Table 35-2.
175H
373
IA32_SYSENTER_ESP
Unique
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Unique
See Table 35-2.
179H
377
IA32_MCG_CAP
Unique
See Table 35-2.
17AH
378
IA32_MCG_STATUS
Unique
Vol. 3C 35-47
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
0
RIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If cleared, the
program cannot be reliably restarted.
1
EIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, bit indicates that a machine check has been generated. If
a second machine check is detected while this bit is still set, the
processor enters a shutdown state. Software should write this bit
to 0 after processing a machine check exception.
63:3
Reserved.
186H
390
IA32_PERFEVTSEL0
Unique
See Table 35-2.
187H
391
IA32_PERFEVTSEL1
Unique
See Table 35-2.
198H
408
IA32_PERF_STATUS
Shared
See Table 35-2.
198H
408
MSR_PERF_STATUS
Shared
15:0
Current Performance State Value.
30:16
Reserved.
31
XE Operation (R/O).
If set, XE operation is enabled. Default is cleared.
39:32
Reserved.
44:40
Maximum Bus Ratio (R/O)
Indicates maximum bus ratio configured for the processor.
45
Reserved.
46
Non-Integer Bus Ratio (R/O)
Indicates non-integer bus ratio is enabled. Applies processors
based on Enhanced Intel Core microarchitecture.
63:47
Reserved.
199H
409
IA32_PERF_CTL
Unique
See Table 35-2.
19AH
410
IA32_CLOCK_MODULATION
Unique
Clock Modulation (R/W)
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
19BH
411
IA32_THERM_INTERRUPT
Unique
Thermal Interrupt Control (R/W)
See Table 35-2.
19CH
412
IA32_THERM_STATUS
Unique
Thermal Monitor Status (R/W)
See Table 35-2.
35-48 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Dec
19DH
413
Register Name
MSR_THERM2_CTL
Shared/
Unique
Bit Description
Unique
15:0
Reserved.
16
TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of
the stop-clock duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT
has no effect. Neither TM1 nor TM2 are enabled.
1A0H
416
63:16
Reserved.
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0
Fast-Strings Enable
See Table 35-2.
2:1
3
Reserved.
Unique
Automatic Thermal Control Circuit Enable (R/W)
See Table 35-2.
6:4
7
Reserved.
Shared
Performance Monitoring Available (R)
See Table 35-2.
8
Reserved.
9
Hardware Prefetcher Disable (R/W)
When set, disables the hardware prefetcher operation on streams
of data. When clear (default), enables the prefetch queue.
Disabling of the hardware prefetcher may impact processor
performance.
10
Shared
FERR# Multiplexing Enable (R/W)
1=
FERR# asserted by the processor to indicate a pending break
event within the processor
0 = Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model usage.
11
Shared
Branch Trace Storage Unavailable (RO)
See Table 35-2.
12
Shared
Processor Event Based Sampling Unavailable (RO)
See Table 35-2.
Vol. 3C 35-49
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
13
Shared
TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that the
die temperature is at the pre-determined threshold, the Thermal
Monitor 2 mechanism is engaged. TM2 will reduce the bus to core
ratio and voltage according to the value last written to
MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change
the VID signals or the bus to core ratio when the processor enters
a thermally managed state.
The BIOS must enable this feature if the TM2 feature flag
(CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this
feature is not supported and BIOS must not alter the contents of
the TM2 bit location.
The processor is operating out of specification if both this bit and
the TM1 bit are set to 0.
15:14
16
Reserved.
Shared
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 35-2.
18
Shared
19
Shared
ENABLE MONITOR FSM (R/W)
See Table 35-2.
Adjacent Cache Line Prefetch Disable (R/W)
When set to 1, the processor fetches the cache line that contains
data currently required by the processor. When set to 0, the
processor fetches cache lines that comprise a cache line pair (128
bytes).
Single processor platforms should not set this bit. Server platforms
should set or clear this bit based on platform performance
observed in validation and testing.
BIOS may contain a setup option that controls the setting of this
bit.
20
Shared
Enhanced Intel SpeedStep Technology Select Lock (R/WO)
When set, this bit causes the following bits to become read-only:
• Enhanced Intel SpeedStep Technology Select Lock (this bit),
• Enhanced Intel SpeedStep Technology Enable bit.
The bit must be set before an Enhanced Intel SpeedStep
Technology transition is requested. This bit is cleared on reset.
21
22
Reserved.
Shared
Limit CPUID Maxval (R/W)
See Table 35-2.
23
Shared
xTPR Message Disable (R/W)
See Table 35-2.
33:24
35-50 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
34
Unique
XD Bit Disable (R/W)
See Table 35-2.
36:35
37
Reserved.
Unique
DCU Prefetcher Disable (R/W)
When set to 1, The DCU L1 data cache prefetcher is disabled. The
default value after reset is 0. BIOS may write ‘1’ to disable this
feature.
The DCU prefetcher is an L1 data cache prefetcher. When the DCU
prefetcher detects multiple loads from the same line done within a
time limit, the DCU prefetcher assumes the next line will be
required. The next line is prefetched in to the L1 data cache from
memory or L2.
38
Shared
IDA Disable (R/W)
When set to 1 on processors that support IDA, the Intel Dynamic
Acceleration feature (IDA) is disabled and the IDA_Enable feature
flag will be clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H:
EAX[1] reports the processor’s support of IDA is enabled.
Note: the power-on default value is used by BIOS to detect
hardware support of IDA. If power-on default value is 1, IDA is
available in the processor. If power-on default value is 0, IDA is not
available.
39
Unique
IP Prefetcher Disable (R/W)
When set to 1, The IP prefetcher is disabled. The default value
after reset is 0. BIOS may write ‘1’ to disable this feature.
The IP prefetcher is an L1 data cache prefetcher. The IP prefetcher
looks for sequential load history to determine whether to prefetch
the next expected data into the L1 cache from memory or L2.
63:40
1C9H
457
MSR_LASTBRANCH_TOS
Reserved.
Unique
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the
most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
1D9H
473
IA32_DEBUGCTL
Unique
Debug Control (R/W)
See Table 35-2
1DDH
477
MSR_LER_FROM_LIP
Unique
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
1DEH
478
MSR_LER_TO_LIP
Unique
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled.
Vol. 3C 35-51
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec
200H
512
IA32_MTRR_PHYSBASE0
Unique
See Table 35-2.
201H
513
IA32_MTRR_PHYSMASK0
Unique
See Table 35-2.
202H
514
IA32_MTRR_PHYSBASE1
Unique
See Table 35-2.
203H
515
IA32_MTRR_PHYSMASK1
Unique
See Table 35-2.
204H
516
IA32_MTRR_PHYSBASE2
Unique
See Table 35-2.
205H
517
IA32_MTRR_PHYSMASK2
Unique
See Table 35-2.
206H
518
IA32_MTRR_PHYSBASE3
Unique
See Table 35-2.
207H
519
IA32_MTRR_PHYSMASK3
Unique
See Table 35-2.
208H
520
IA32_MTRR_PHYSBASE4
Unique
See Table 35-2.
209H
521
IA32_MTRR_PHYSMASK4
Unique
See Table 35-2.
20AH
522
IA32_MTRR_PHYSBASE5
Unique
See Table 35-2.
20BH
523
IA32_MTRR_PHYSMASK5
Unique
See Table 35-2.
20CH
524
IA32_MTRR_PHYSBASE6
Unique
See Table 35-2.
20DH
525
IA32_MTRR_PHYSMASK6
Unique
See Table 35-2.
20EH
526
IA32_MTRR_PHYSBASE7
Unique
See Table 35-2.
20FH
527
IA32_MTRR_PHYSMASK7
Unique
See Table 35-2.
250H
592
IA32_MTRR_FIX64K_
00000
Unique
See Table 35-2.
258H
600
IA32_MTRR_FIX16K_
80000
Unique
See Table 35-2.
259H
601
IA32_MTRR_FIX16K_
A0000
Unique
See Table 35-2.
268H
616
IA32_MTRR_FIX4K_C0000
Unique
See Table 35-2.
269H
617
IA32_MTRR_FIX4K_C8000
Unique
See Table 35-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Unique
See Table 35-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Unique
See Table 35-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Unique
See Table 35-2.
26DH
621
IA32_MTRR_FIX4K_E8000
Unique
See Table 35-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Unique
See Table 35-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Unique
See Table 35-2.
277H
631
IA32_PAT
Unique
See Table 35-2.
2FFH
767
IA32_MTRR_DEF_TYPE
Unique
Default Memory Types (R/W)
See Table 35-2.
309H
777
IA32_FIXED_CTR0
Unique
Fixed-Function Performance Counter Register 0 (R/W)
See Table 35-2.
309H
777
35-52 Vol. 3C
MSR_PERF_FIXED_CTR0
Unique
Fixed-Function Performance Counter Register 0 (R/W)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Dec
30AH
778
Register Name
IA32_FIXED_CTR1
Shared/
Unique
Unique
Bit Description
Fixed-Function Performance Counter Register 1 (R/W)
See Table 35-2.
30AH
778
MSR_PERF_FIXED_CTR1
Unique
Fixed-Function Performance Counter Register 1 (R/W)
30BH
779
IA32_FIXED_CTR2
Unique
Fixed-Function Performance Counter Register 2 (R/W)
30BH
779
MSR_PERF_FIXED_CTR2
Unique
Fixed-Function Performance Counter Register 2 (R/W)
345H
837
IA32_PERF_CAPABILITIES
Unique
See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”
345H
837
MSR_PERF_CAPABILITIES
Unique
RO. This applies to processors that do not support architectural
perfmon version 2.
See Table 35-2.
38DH
909
5:0
LBR Format. See Table 35-2.
6
PEBS Record Format.
7
PEBSSaveArchRegs. See Table 35-2.
63:8
Reserved.
IA32_FIXED_CTR_CTRL
Unique
Fixed-Function-Counter Control Register (R/W)
See Table 35-2.
38DH
909
MSR_PERF_FIXED_CTR_
CTRL
Unique
Fixed-Function-Counter Control Register (R/W)
38EH
910
IA32_PERF_GLOBAL_
STATUS
Unique
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
38EH
910
MSR_PERF_GLOBAL_STATU Unique
S
See Section 18.4.2, “Global Counter Control Facilities.”
38FH
911
IA32_PERF_GLOBAL_CTRL
Unique
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
38FH
911
MSR_PERF_GLOBAL_CTRL
Unique
See Section 18.4.2, “Global Counter Control Facilities.”
390H
912
IA32_PERF_GLOBAL_OVF_
CTRL
Unique
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
390H
912
MSR_PERF_GLOBAL_OVF_
CTRL
Unique
See Section 18.4.2, “Global Counter Control Facilities.”
3F1H
1009
MSR_PEBS_ENABLE
Unique
See Table 35-2. See Section 18.4.4, “Processor Event Based
Sampling (PEBS).”
0
Enable PEBS on IA32_PMC0. (R/W)
400H
1024
IA32_MC0_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC0_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
Vol. 3C 35-53
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
404H
1028
IA32_MC1_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC1_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
408H
1032
IA32_MC2_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC2_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
40CH
1036
IA32_MC4_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC4_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC4_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
410H
1040
IA32_MC3_CTL
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC3_STATUS
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
IA32_MC3_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC3_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
413H
1043
IA32_MC3_MISC
Unique
414H
1044
IA32_MC5_CTL
Unique
415H
1045
IA32_MC5_STATUS
Unique
416H
1046
IA32_MC5_ADDR
Unique
417H
1047
IA32_MC5_MISC
Unique
419H
1045
IA32_MC6_STATUS
Unique
35-54 Vol. 3C
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” and
Chapter 23.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Dec
480H
1152
Register Name
IA32_VMX_BASIC
Shared/
Unique
Unique
Bit Description
Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_
CTLS
Unique
Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_
CTLS
Unique
483H
1155
IA32_VMX_EXIT_CTLS
Unique
Capability Reporting Register of Primary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Capability Reporting Register of VM-exit Controls (R/O)
See Table 35-2.
See Appendix A.4, “VM-Exit Controls.”
484H
1156
IA32_VMX_ENTRY_CTLS
Unique
Capability Reporting Register of VM-entry Controls (R/O)
See Table 35-2.
See Appendix A.5, “VM-Entry Controls.”
485H
1157
IA32_VMX_MISC
Unique
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.6, “Miscellaneous Data.”
486H
1158
IA32_VMX_CR0_FIXED0
Unique
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Unique
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Unique
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
489H
1161
IA32_VMX_CR4_FIXED1
Unique
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH
1162
IA32_VMX_VMCS_ENUM
Unique
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 35-2.
See Appendix A.9, “VMCS Enumeration.”
48BH
1163
IA32_VMX_PROCBASED_
CTLS2
Unique
Capability Reporting Register of Secondary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Vol. 3C 35-55
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Dec
600H
1536
Register Name
IA32_DS_AREA
Shared/
Unique
Unique
Bit Description
DS Save Area (R/W)
See Table 35-2.
See Section 18.15.4, “Debug Store (DS) Mechanism.”
107CC
H
MSR_EMON_L3_CTR_CTL0
107CD
H
MSR_EMON_L3_CTR_CTL1
107CE
H
MSR_EMON_L3_CTR_CTL2
107CF
H
MSR_EMON_L3_CTR_CTL3
107D0
H
MSR_EMON_L3_CTR_CTL4
107D1
H
MSR_EMON_L3_CTR_CTL5
107D2
H
MSR_EMON_L3_CTR_CTL6
107D3
H
MSR_EMON_L3_CTR_CTL7
107D8
H
MSR_EMON_L3_GL_CTL
C000_
0080H
IA32_EFER
C000_
0081H
IA32_STAR
C000_
0082H
IA32_LSTAR
C000_
0084H
IA32_FMASK
C000_
0100H
IA32_FS_BASE
35-56 Vol. 3C
Unique
GBUSQ Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
GBUSQ Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
GSNPQ Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
GSNPQ Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
FSB Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
FSB Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
FSB Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
FSB Event Control/Counter Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
L3/FSB Common Control Register (R/W)
Apply to Intel Xeon processor 7400 series (processor signature
06_1D) only. See Section 17.2.2
Unique
Extended Feature Enables
See Table 35-2.
Unique
System Call Target Address (R/W)
See Table 35-2.
Unique
IA-32e Mode System Call Target Address (R/W)
See Table 35-2.
Unique
System Call Flag Mask (R/W)
See Table 35-2.
Unique
Map of BASE Address of FS (R/W)
See Table 35-2.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Hex
Register Name
Bit Description
Dec
C000_
0101H
IA32_GS_BASE
C000_
0102H
IA32_KERNEL_GS_BASE
35.3
Shared/
Unique
Unique
Map of BASE Address of GS (R/W)
See Table 35-2.
Unique
Swap Target of BASE Address of GS (R/W) See Table 35-2.
MSRS IN THE 45 NM AND 32 NM INTEL® ATOM™ PROCESSOR FAMILY
Table 35-4 lists model-specific registers (MSRs) for 45 nm and 32 nm Intel Atom processors, architectural MSR
addresses are also included in Table 35-4. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_1CH, 06_26H, 06_27H, 06_35H and 06_36H; see Table 35-1.
The column “Shared/Unique” applies to logical processors sharing the same core in processors based on the Intel
Atom microarchitecture. “Unique” means each logical processor has a separate MSR, or a bit field in an MSR
governs only a logical processor. “Shared” means the MSR or the bit field in an MSR address governs the operation
of both logical processors in the same core.
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Shared
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Shared
See Section 35.22, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_
SIZE
Unique
See Section 8.10.5, “Monitor/Mwait Address Range Determination.”
andTable 35-2
10H
16
IA32_TIME_STAMP_
COUNTER
Unique
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
17H
23
IA32_PLATFORM_ID
Shared
Platform ID (R)
See Table 35-2.
17H
23
MSR_PLATFORM_ID
Shared
Model Specific Platform ID (R)
7:0
Reserved.
12:8
Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
63:13
Reserved.
1BH
27
IA32_APIC_BASE
Unique
See Section 10.4.4, “Local APIC Status and Location,” and
Table 35-2.
2AH
42
MSR_EBL_CR_POWERON
Shared
Processor Hard Power-On Configuration (R/W) Enables and
disables processor features;
(R) indicates current processor configuration.
0
Reserved.
Vol. 3C 35-57
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
1
Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Always 0.
2
Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Always 0.
3
AERR# Drive Enable (R/W)
1 = Enabled; 0 = Disabled
Always 0.
4
BERR# Enable for initiator bus requests (R/W)
1 = Enabled; 0 = Disabled
Always 0.
5
Reserved.
6
Reserved.
7
BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled
Always 0.
8
Reserved.
9
Execute BIST (R/O)
1 = Enabled; 0 = Disabled
10
AERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
Always 0.
11
Reserved.
12
BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
Always 0.
13
Reserved.
14
1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes
15
Reserved
17:16
APIC Cluster ID (R/O)
Always 00B.
19: 18
Reserved.
21: 20
Symmetric Arbitration ID (R/O)
Always 00B.
26:22
3AH
58
IA32_FEATURE_CONTROL
Integer Bus Frequency Ratio (R/O)
Unique
Control Features in Intel 64Processor (R/W)
See Table 35-2.
35-58 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Dec
40H
64
Register Name
MSR_
LASTBRANCH_0_FROM_IP
Shared/
Unique
Unique
Bit Description
Last Branch Record 0 From IP (R/W)
One of eight pairs of last branch record registers on the last branch
record stack. The From_IP part of the stack contains pointers to
the source instruction . See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.5
41H
42H
43H
44H
45H
46H
47H
60H
61H
62H
63H
64H
65H
66H
67H
79H
65
66
67
68
69
70
71
96
97
98
99
100
101
102
103
121
MSR_
LASTBRANCH_1_FROM_IP
Unique
MSR_
LASTBRANCH_2_FROM_IP
Unique
MSR_
LASTBRANCH_3_FROM_IP
Unique
MSR_
LASTBRANCH_4_FROM_IP
Unique
MSR_
LASTBRANCH_5_FROM_IP
Unique
MSR_
LASTBRANCH_6_FROM_IP
Unique
MSR_
LASTBRANCH_7_FROM_IP
Unique
MSR_
LASTBRANCH_0_TO_IP
Unique
MSR_
LASTBRANCH_1_TO_IP
Unique
MSR_
LASTBRANCH_2_TO_IP
Unique
MSR_
LASTBRANCH_3_TO_IP
Unique
MSR_
LASTBRANCH_4_TO_IP
Unique
MSR_
LASTBRANCH_5_TO_IP
Unique
MSR_
LASTBRANCH_6_TO_IP
Unique
MSR_
LASTBRANCH_7_TO_IP
Unique
IA32_BIOS_UPDT_TRIG
Shared
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 0 To IP (R/W)
One of eight pairs of last branch record registers on the last branch
record stack. The To_IP part of the stack contains pointers to the
destination instruction.
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
BIOS Update Trigger Register (W)
See Table 35-2.
Vol. 3C 35-59
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Dec
8BH
139
Register Name
IA32_BIOS_SIGN_ID
Shared/
Unique
Unique
Bit Description
BIOS Update Signature ID (RO)
See Table 35-2.
C1H
193
IA32_PMC0
Unique
Performance counter register
See Table 35-2.
C2H
194
IA32_PMC1
Unique
Performance Counter Register
See Table 35-2.
CDH
205
MSR_FSB_FREQ
Shared
Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock speed for
processors based on Intel Atom microarchitecture:
2:0
•
•
•
•
111B: 083 MHz (FSB 333)
101B: 100 MHz (FSB 400)
001B: 133 MHz (FSB 533)
011B: 167 MHz (FSB 667)
133.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 011B.
63:3
E7H
231
IA32_MPERF
Reserved.
Unique
Maximum Performance Frequency Clock Count (RW)
See Table 35-2.
E8H
232
IA32_APERF
Unique
Actual Performance Frequency Clock Count (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Shared
Memory Type Range Register (R)
See Table 35-2.
11EH
281
MSR_BBL_CR_CTL3
Shared
0
L2 Hardware Enabled (RO)
1 = If the L2 is hardware-enabled
0 = Indicates if the L2 is hardware-disabled
7:1
Reserved.
8
L2 Enabled. (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the WBINVD
instruction or the assertion of the FLUSH# input.
22:9
Reserved.
23
L2 Not Present (RO)
0 = L2 Present
1 = L2 Not Present
63:24
Reserved.
174H
372
IA32_SYSENTER_CS
Unique
See Table 35-2.
175H
373
IA32_SYSENTER_ESP
Unique
See Table 35-2.
35-60 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec
176H
374
IA32_SYSENTER_EIP
Unique
See Table 35-2.
179H
377
IA32_MCG_CAP
Unique
See Table 35-2.
17AH
378
IA32_MCG_STATUS
Unique
0
RIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If cleared, the
program cannot be reliably restarted
1
EIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, bit indicates that a machine check has been generated. If
a second machine check is detected while this bit is still set, the
processor enters a shutdown state. Software should write this bit
to 0 after processing a machine check exception.
63:3
Reserved.
186H
390
IA32_PERFEVTSEL0
Unique
See Table 35-2.
187H
391
IA32_PERFEVTSEL1
Unique
See Table 35-2.
198H
408
IA32_PERF_STATUS
Shared
See Table 35-2.
198H
408
MSR_PERF_STATUS
Shared
15:0
Current Performance State Value.
39:16
Reserved.
44:40
Maximum Bus Ratio (R/O)
Indicates maximum bus ratio configured for the processor.
63:45
Reserved.
199H
409
IA32_PERF_CTL
Unique
See Table 35-2.
19AH
410
IA32_CLOCK_MODULATION
Unique
Clock Modulation (R/W)
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
19BH
411
IA32_THERM_INTERRUPT
Unique
Thermal Interrupt Control (R/W)
See Table 35-2.
19CH
412
IA32_THERM_STATUS
Unique
Thermal Monitor Status (R/W)
See Table 35-2.
19DH
413
MSR_THERM2_CTL
15:0
Shared
Reserved.
Vol. 3C 35-61
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
16
TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of
the stop-clock duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT
has no effect. Neither TM1 nor TM2 are enabled.
63:17
1A0H
416
IA32_MISC_ENABLE
Reserved.
Unique
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0
Fast-Strings Enable
See Table 35-2.
2:1
3
Reserved.
Unique
Automatic Thermal Control Circuit Enable (R/W)
See Table 35-2. Default value is 0.
6:4
7
Reserved.
Shared
Performance Monitoring Available (R)
See Table 35-2.
8
Reserved.
9
Reserved.
10
Shared
FERR# Multiplexing Enable (R/W)
1=
FERR# asserted by the processor to indicate a pending break
event within the processor
0 = Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model usage.
11
Shared
Branch Trace Storage Unavailable (RO)
See Table 35-2.
12
Shared
Processor Event Based Sampling Unavailable (RO)
See Table 35-2.
13
Shared
TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that the
die temperature is at the pre-determined threshold, the Thermal
Monitor 2 mechanism is engaged. TM2 will reduce the bus to core
ratio and voltage according to the value last written to
MSR_THERM2_CTL bits 15:0.
35-62 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
When this bit is clear (0, default), the processor does not change
the VID signals or the bus to core ratio when the processor enters
a thermally managed state.
The BIOS must enable this feature if the TM2 feature flag
(CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this
feature is not supported and BIOS must not alter the contents of
the TM2 bit location.
The processor is operating out of specification if both this bit and
the TM1 bit are set to 0.
15:14
16
Reserved.
Shared
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 35-2.
18
Shared
ENABLE MONITOR FSM (R/W)
See Table 35-2.
19
20
Reserved.
Shared
Enhanced Intel SpeedStep Technology Select Lock (R/WO)
When set, this bit causes the following bits to become read-only:
• Enhanced Intel SpeedStep Technology Select Lock (this bit),
• Enhanced Intel SpeedStep Technology Enable bit.
The bit must be set before an Enhanced Intel SpeedStep
Technology transition is requested. This bit is cleared on reset.
21
Reserved.
22
Unique
23
Shared
Limit CPUID Maxval (R/W)
See Table 35-2.
xTPR Message Disable (R/W)
See Table 35-2.
33:24
34
Reserved.
Unique
XD Bit Disable (R/W)
See Table 35-2.
63:35
1C9H
457
MSR_LASTBRANCH_TOS
Reserved.
Unique
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-2) that points to the MSR containing the
most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
1D9H
473
IA32_DEBUGCTL
Unique
Debug Control (R/W)
See Table 35-2.
1DDH
477
MSR_LER_FROM_LIP
Unique
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
Vol. 3C 35-63
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Dec
1DEH
478
Register Name
MSR_LER_TO_LIP
Shared/
Unique
Unique
Bit Description
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled.
200H
512
IA32_MTRR_PHYSBASE0
Shared
See Table 35-2.
201H
513
IA32_MTRR_PHYSMASK0
Shared
See Table 35-2.
202H
514
IA32_MTRR_PHYSBASE1
Shared
See Table 35-2.
203H
515
IA32_MTRR_PHYSMASK1
Shared
See Table 35-2.
204H
516
IA32_MTRR_PHYSBASE2
Shared
See Table 35-2.
205H
517
IA32_MTRR_PHYSMASK2
Shared
See Table 35-2.
206H
518
IA32_MTRR_PHYSBASE3
Shared
See Table 35-2.
207H
519
IA32_MTRR_PHYSMASK3
Shared
See Table 35-2.
208H
520
IA32_MTRR_PHYSBASE4
Shared
See Table 35-2.
209H
521
IA32_MTRR_PHYSMASK4
Shared
See Table 35-2.
20AH
522
IA32_MTRR_PHYSBASE5
Shared
See Table 35-2.
20BH
523
IA32_MTRR_PHYSMASK5
Shared
See Table 35-2.
20CH
524
IA32_MTRR_PHYSBASE6
Shared
See Table 35-2.
20DH
525
IA32_MTRR_PHYSMASK6
Shared
See Table 35-2.
20EH
526
IA32_MTRR_PHYSBASE7
Shared
See Table 35-2.
20FH
527
IA32_MTRR_PHYSMASK7
Shared
See Table 35-2.
250H
592
IA32_MTRR_FIX64K_
00000
Shared
See Table 35-2.
258H
600
IA32_MTRR_FIX16K_
80000
Shared
See Table 35-2.
259H
601
IA32_MTRR_FIX16K_
A0000
Shared
See Table 35-2.
268H
616
IA32_MTRR_FIX4K_C0000
Shared
See Table 35-2.
269H
617
IA32_MTRR_FIX4K_C8000
Shared
See Table 35-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Shared
See Table 35-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Shared
See Table 35-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Shared
See Table 35-2.
26DH
621
IA32_MTRR_FIX4K_E8000
Shared
See Table 35-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Shared
See Table 35-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Shared
See Table 35-2.
277H
631
IA32_PAT
Unique
See Table 35-2.
309H
777
IA32_FIXED_CTR0
Unique
Fixed-Function Performance Counter Register 0 (R/W)
See Table 35-2.
30AH
778
IA32_FIXED_CTR1
Unique
Fixed-Function Performance Counter Register 1 (R/W)
See Table 35-2.
35-64 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Dec
30BH
779
Register Name
IA32_FIXED_CTR2
Shared/
Unique
Unique
Bit Description
Fixed-Function Performance Counter Register 2 (R/W)
See Table 35-2.
345H
837
IA32_PERF_CAPABILITIES
Shared
See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”
38DH
909
IA32_FIXED_CTR_CTRL
Unique
Fixed-Function-Counter Control Register (R/W)
See Table 35-2.
38EH
910
IA32_PERF_GLOBAL_
STATUS
Unique
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
38FH
911
IA32_PERF_GLOBAL_CTRL
Unique
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
390H
912
IA32_PERF_GLOBAL_OVF_
CTRL
Unique
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
3F1H
1009
MSR_PEBS_ENABLE
Unique
See Table 35-2. See Section 18.4.4, “Processor Event Based
Sampling (PEBS).”
0
Enable PEBS on IA32_PMC0. (R/W)
400H
1024
IA32_MC0_CTL
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Shared
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC0_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
404H
1028
IA32_MC1_CTL
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
408H
1032
IA32_MC2_CTL
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Shared
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC2_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
40CH
1036
IA32_MC3_CTL
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC3_ADDR
Shared
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC3_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
410H
1040
IA32_MC4_CTL
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC4_STATUS
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
Vol. 3C 35-65
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Hex
Dec
412H
1042
Register Name
IA32_MC4_ADDR
Shared/
Unique
Shared
Bit Description
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
480H
1152
IA32_VMX_BASIC
Unique
Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_
CTLS
Unique
Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_
CTLS
Unique
Capability Reporting Register of Primary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
483H
1155
IA32_VMX_EXIT_CTLS
Unique
Capability Reporting Register of VM-exit Controls (R/O)
See Table 35-2.
See Appendix A.4, “VM-Exit Controls.”
484H
1156
IA32_VMX_ENTRY_CTLS
Unique
Capability Reporting Register of VM-entry Controls (R/O)
See Table 35-2.
See Appendix A.5, “VM-Entry Controls.”
485H
1157
IA32_VMX_MISC
Unique
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.6, “Miscellaneous Data.”
486H
1158
IA32_VMX_CR0_FIXED0
Unique
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Unique
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Unique
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
489H
1161
IA32_VMX_CR4_FIXED1
Unique
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH
1162
IA32_VMX_VMCS_ENUM
Unique
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 35-2.
See Appendix A.9, “VMCS Enumeration.”
35-66 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Register Name
Shared/
Unique
Hex
Dec
48BH
1163
IA32_VMX_PROCBASED_
CTLS2
Unique
600H
1536
IA32_DS_AREA
Unique
Bit Description
Capability Reporting Register of Secondary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
DS Save Area (R/W)
See Table 35-2.
See Section 18.15.4, “Debug Store (DS) Mechanism.”
C000_
0080H
IA32_EFER
C000_
0081H
IA32_STAR
C000_
0082H
IA32_LSTAR
C000_
0084H
IA32_FMASK
C000_
0100H
IA32_FS_BASE
C000_
0101H
IA32_GS_BASE
C000_
0102H
IA32_KERNEL_GS_BASE
Unique
Extended Feature Enables
See Table 35-2.
Unique
System Call Target Address (R/W)
See Table 35-2.
Unique
IA-32e Mode System Call Target Address (R/W)
See Table 35-2.
Unique
System Call Flag Mask (R/W)
See Table 35-2.
Unique
Map of BASE Address of FS (R/W)
See Table 35-2.
Unique
Map of BASE Address of GS (R/W)
See Table 35-2.
Unique
Swap Target of BASE Address of GS (R/W) See Table 35-2.
Table 35-5 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor with the CPUID signature with DisplayFamily_DisplayModel of 06_27H.
Table 35-5. MSRs Supported by Intel® Atom™ Processors with CPUID Signature 06_27H
Register
Address
Hex
Dec
3F8H
1016
Register Name
MSR_PKG_C2_RESIDENCY
Scope
Package
Bit Description
Package C2 Residency
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States
63:0
Package
Package C2 Residency Counter. (R/O)
Time that this package is in processor-specific C2 states since last
reset. Counts at 1 Mhz frequency.
3F9H
1017
MSR_PKG_C4_RESIDENCY
Package
Package C4 Residency
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States
63:0
Package
Package C4 Residency Counter. (R/O)
Time that this package is in processor-specific C4 states since last
reset. Counts at 1 Mhz frequency.
Vol. 3C 35-67
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-5. MSRs Supported by Intel® Atom™ Processors (Contd.)with CPUID Signature 06_27H
Register
Address
Hex
Dec
3FAH
1018
Register Name
MSR_PKG_C6_RESIDENCY
Scope
Package
Bit Description
Package C6 Residency
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States
63:0
Package
Package C6 Residency Counter. (R/O)
Time that this package is in processor-specific C6 states since last
reset. Counts at 1 Mhz frequency.
35.4
MSRS IN INTEL PROCESSORS BASED ON SILVERMONT
MICROARCHITECTURE
Table 35-6 lists model-specific registers (MSRs) common to Intel processors based on the Silvermont microarchitecture. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_37H, 06_4AH, 06_4DH,
06_5AH, and 06_5DH; see Table 35-1. The MSRs listed in Table 35-6 are also common to processors based on the
Airmont microarchitecture and newer microarchitectures for next generation Intel Atom processors.
Table 35-7 lists MSRs common to processors based on the Silvermont and Airmont microarchitectures, but not
newer microarchitectures.
Table 35-8, Table 35-9, and Table 35-10 lists MSRs that are model-specific across processors based on the Silvermont microarchitecture.
In the Silvermont microarchitecture, the scope column indicates the following: “Core” means each processor core
has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field
is shared by a pair of processor cores in the physical package. “Package” means all processor cores in the physical
package share the same MSR or bit interface.
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Register Name
Scope
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Module
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Module
See Section 35.22, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_
SIZE
Core
See Section 8.10.5, “Monitor/Mwait Address Range Determination.”
andTable 35-2
10H
16
IA32_TIME_STAMP_
COUNTER
Core
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
1BH
27
IA32_APIC_BASE
Core
See Section 10.4.4, “Local APIC Status and Location,” and
Table 35-2.
2AH
42
MSR_EBL_CR_POWERON
Module
Processor Hard Power-On Configuration (R/W) Writes ignored.
34H
52
MSR_SMI_COUNT
63:0
31:0
Reserved (R/O)
Core
SMI Counter (R/O)
SMI Count (R/O)
Running count of SMI events since last RESET.
63:32
35-68 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Hex
Dec
79H
121
Register Name
IA32_BIOS_UPDT_TRIG
Scope
Core
Bit Description
BIOS Update Trigger Register (W)
See Table 35-2.
8BH
139
IA32_BIOS_SIGN_ID
Core
BIOS Update Signature ID (RO)
See Table 35-2.
C1H
193
IA32_PMC0
Core
Performance counter register
See Table 35-2.
C2H
194
IA32_PMC1
Core
Performance Counter Register
See Table 35-2.
E4H
228
MSR_PMG_IO_CAPTURE_
BASE
Module
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
15:0
LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If
IO MWAIT Redirection is enabled, reads to this address will be
consumed by the power management logic and decoded to MWAIT
instructions. When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
18:16
C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name to
be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
100b - C4 is the max C-State to include
110b - C6 is the max C-State to include
111b - C7 is the max C-State to include
63:19
E7H
231
IA32_MPERF
Reserved.
Core
Maximum Performance Frequency Clock Count (RW)
See Table 35-2.
E8H
232
IA32_APERF
Core
Actual Performance Frequency Clock Count (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Core
Memory Type Range Register (R)
See Table 35-2.
13CH
52
MSR_FEATURE_CONFIG
Core
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle
unsuccessful read of this MSR.
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instruction can be mis-configured
if a privileged agent unintentionally writes 11b.
63:2
Reserved.
Vol. 3C 35-69
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Register Name
Scope
Bit Description
Hex
Dec
174H
372
IA32_SYSENTER_CS
Core
See Table 35-2.
175H
373
IA32_SYSENTER_ESP
Core
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Core
See Table 35-2.
179H
377
IA32_MCG_CAP
Core
See Table 35-2.
17AH
378
IA32_MCG_STATUS
Core
0
RIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If cleared, the
program cannot be reliably restarted
1
EIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, bit indicates that a machine check has been generated. If
a second machine check is detected while this bit is still set, the
processor enters a shutdown state. Software should write this bit
to 0 after processing a machine check exception.
63:3
186H
390
IA32_PERFEVTSEL0
Reserved.
Core
See Table 35-2.
7:0
Event Select
15:8
UMask
16
USR
17
OS
18
Edge
19
PC
20
INT
21
Reserved
22
EN
23
INV
31:24
CMASK
63:32
Reserved.
187H
391
IA32_PERFEVTSEL1
Core
See Table 35-2.
198H
408
IA32_PERF_STATUS
Module
See Table 35-2.
199H
409
IA32_PERF_CTL
Core
See Table 35-2.
19AH
410
IA32_CLOCK_MODULATION
Core
Clock Modulation (R/W)
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
35-70 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Hex
Dec
19BH
411
Register Name
IA32_THERM_INTERRUPT
Scope
Core
Bit Description
Thermal Interrupt Control (R/W)
See Table 35-2.
19CH
412
IA32_THERM_STATUS
Core
Thermal Monitor Status (R/W)
See Table 35-2.
1A2H
418
MSR_
TEMPERATURE_TARGET
Package
15:0
Reserved.
23:16
Temperature Target (R)
The default thermal throttling or PROCHOT# activation
temperature in degree C, The effective temperature for thermal
throttling or PROCHOT# activation is “Temperature Target” +
“Target Offset”
29:24
Target Offset (R/W)
Specifies an offset in degrees C to adjust the throttling and
PROCHOT# activation temperature from the default target
specified in TEMPERATURE_TARGET (bits 23:16).
63:30
Reserved.
1A6H
422
MSR_OFFCORE_RSP_0
Module
Offcore Response Event Select Register (R/W)
1A7H
423
MSR_OFFCORE_RSP_1
Module
Offcore Response Event Select Register (R/W)
1B0H
432
IA32_ENERGY_PERF_BIAS
Core
See Table 35-2.
1D9H
473
IA32_DEBUGCTL
Core
Debug Control (R/W)
See Table 35-2.
1DDH
477
MSR_LER_FROM_LIP
Core
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
1DEH
478
MSR_LER_TO_LIP
Core
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled.
1F2H
498
IA32_SMRR_PHYSBASE
Core
See Table 35-2.
1F3H
499
IA32_SMRR_PHYSMASK
Core
See Table 35-2.
200H
512
IA32_MTRR_PHYSBASE0
Core
See Table 35-2.
201H
513
IA32_MTRR_PHYSMASK0
Core
See Table 35-2.
202H
514
IA32_MTRR_PHYSBASE1
Core
See Table 35-2.
203H
515
IA32_MTRR_PHYSMASK1
Core
See Table 35-2.
204H
516
IA32_MTRR_PHYSBASE2
Core
See Table 35-2.
205H
517
IA32_MTRR_PHYSMASK2
Core
See Table 35-2.
206H
518
IA32_MTRR_PHYSBASE3
Core
See Table 35-2.
207H
519
IA32_MTRR_PHYSMASK3
Core
See Table 35-2.
208H
520
IA32_MTRR_PHYSBASE4
Core
See Table 35-2.
Vol. 3C 35-71
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Hex
Dec
Register Name
Scope
Bit Description
209H
521
IA32_MTRR_PHYSMASK4
Core
See Table 35-2.
20AH
522
IA32_MTRR_PHYSBASE5
Core
See Table 35-2.
20BH
523
IA32_MTRR_PHYSMASK5
Core
See Table 35-2.
20CH
524
IA32_MTRR_PHYSBASE6
Core
See Table 35-2.
20DH
525
IA32_MTRR_PHYSMASK6
Core
See Table 35-2.
20EH
526
IA32_MTRR_PHYSBASE7
Core
See Table 35-2.
20FH
527
IA32_MTRR_PHYSMASK7
Core
See Table 35-2.
250H
592
IA32_MTRR_FIX64K_
00000
Core
See Table 35-2.
258H
600
IA32_MTRR_FIX16K_
80000
Core
See Table 35-2.
259H
601
IA32_MTRR_FIX16K_
A0000
Core
See Table 35-2.
268H
616
IA32_MTRR_FIX4K_C0000
Core
See Table 35-2.
269H
617
IA32_MTRR_FIX4K_C8000
Core
See Table 35-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Core
See Table 35-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Core
See Table 35-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Core
See Table 35-2.
26DH
621
IA32_MTRR_FIX4K_E8000
Core
See Table 35-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Core
See Table 35-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Core
See Table 35-2.
277H
631
IA32_PAT
Core
See Table 35-2.
2FFH
767
IA32_MTRR_DEF_TYPE
Core
Default Memory Types (R/W)
See Table 35-2.
309H
777
IA32_FIXED_CTR0
Core
Fixed-Function Performance Counter Register 0 (R/W)
See Table 35-2.
30AH
778
IA32_FIXED_CTR1
Core
Fixed-Function Performance Counter Register 1 (R/W)
See Table 35-2.
30BH
779
IA32_FIXED_CTR2
Core
Fixed-Function Performance Counter Register 2 (R/W)
See Table 35-2.
345H
837
IA32_PERF_CAPABILITIES
Core
See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”
38DH
909
IA32_FIXED_CTR_CTRL
Core
Fixed-Function-Counter Control Register (R/W)
See Table 35-2.
38FH
911
IA32_PERF_GLOBAL_CTRL
Core
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
3FDH
1021
MSR_CORE_C6_RESIDENCY
Core
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
35-72 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Hex
Register Name
Dec
Scope
63:0
Bit Description
CORE C6 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C6
states. Counts at the TSC Frequency.
400H
1024
IA32_MC0_CTL
Module
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Module
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Module
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC0_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
404H
1028
IA32_MC1_CTL
Module
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Module
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
408H
1032
IA32_MC2_CTL
Module
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Module
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Module
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC2_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
40CH
1036
IA32_MC3_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC3_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC3_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
410H
1040
IA32_MC4_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC4_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
IA32_MC4_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
414H
1044
IA32_MC5_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
415H
1045
IA32_MC5_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
Vol. 3C 35-73
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Hex
Dec
416H
1046
Register Name
IA32_MC5_ADDR
Scope
Package
Bit Description
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
480H
1152
IA32_VMX_BASIC
Core
Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_
CTLS
Core
Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_
CTLS
Core
Capability Reporting Register of Primary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
483H
1155
IA32_VMX_EXIT_CTLS
Core
Capability Reporting Register of VM-exit Controls (R/O)
See Table 35-2.
See Appendix A.4, “VM-Exit Controls.”
484H
1156
IA32_VMX_ENTRY_CTLS
Core
Capability Reporting Register of VM-entry Controls (R/O)
See Table 35-2.
See Appendix A.5, “VM-Entry Controls.”
485H
1157
IA32_VMX_MISC
Core
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.6, “Miscellaneous Data.”
486H
1158
IA32_VMX_CR0_FIXED0
Core
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Core
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Core
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
489H
1161
IA32_VMX_CR4_FIXED1
Core
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH
1162
IA32_VMX_VMCS_ENUM
Core
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 35-2.
See Appendix A.9, “VMCS Enumeration.”
35-74 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Hex
Dec
48BH
1163
Register Name
IA32_VMX_PROCBASED_
CTLS2
Scope
Core
Bit Description
Capability Reporting Register of Secondary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
48CH
1164
IA32_VMX_EPT_VPID_ENU
M
Core
Capability Reporting Register of EPT and VPID (R/O)
See Table 35-2
48DH
1165
IA32_VMX_TRUE_PINBASE
D_CTLS
Core
48EH
1166
IA32_VMX_TRUE_PROCBA
SED_CTLS
Core
Capability Reporting Register of Pin-based VM-execution Flex
Controls (R/O)
See Table 35-2
Capability Reporting Register of Primary Processor-based
VM-execution Flex Controls (R/O)
See Table 35-2
48FH
490H
491H
1167
1168
1169
IA32_VMX_TRUE_EXIT_CT
LS
Core
Capability Reporting Register of VM-exit Flex Controls (R/O)
See Table 35-2
IA32_VMX_TRUE_ENTRY_C Core
TLS
Capability Reporting Register of VM-entry Flex Controls (R/O)
IA32_VMX_FMFUNC
Capability Reporting Register of VM-function Controls (R/O)
Core
See Table 35-2
See Table 35-2
4C1H
1217
IA32_A_PMC0
Core
See Table 35-2.
4C2H
1218
IA32_A_PMC1
Core
See Table 35-2.
600H
1536
IA32_DS_AREA
Core
DS Save Area (R/W)
See Table 35-2.
See Section 18.15.4, “Debug Store (DS) Mechanism.”
660H
1632
MSR_CORE_C1_RESIDENCY
Core
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
CORE C1 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C1
states. Counts at the TSC frequency.
6E0H
1760
IA32_TSC_DEADLINE
Core
TSC Target of Local APIC’s TSC Deadline Mode (R/W)
C000_
0080H
IA32_EFER
Core
Extended Feature Enables
C000_
0081H
IA32_STAR
Core
C000_
0082H
IA32_LSTAR
Core
C000_
0084H
IA32_FMASK
Core
C000_
0100H
IA32_FS_BASE
Core
See Table 35-2
See Table 35-2.
System Call Target Address (R/W)
See Table 35-2.
IA-32e Mode System Call Target Address (R/W)
See Table 35-2.
System Call Flag Mask (R/W)
See Table 35-2.
Map of BASE Address of FS (R/W)
See Table 35-2.
Vol. 3C 35-75
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Hex
Register Name
Dec
Scope
Core
Bit Description
C000_
0101H
IA32_GS_BASE
Map of BASE Address of GS (R/W)
C000_
0102H
IA32_KERNEL_GS_BASE
Core
Swap Target of BASE Address of GS (R/W) See Table 35-2.
C000_
0103H
IA32_TSC_AUX
Core
AUXILIARY TSC Signature. (R/W) See Table 35-2
See Table 35-2.
Table 35-7 lists model-specific registers (MSRs) that are common to Intel® Atom™ processors based on the Silvermont and Airmont microarchitectures but not newer microarchitectures.
Table 35-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Hex
Dec
17H
23
Register Name
MSR_PLATFORM_ID
Scope
Module
Bit Description
Model Specific Platform ID (R)
7:0
Reserved.
13:8
Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
3AH
58
49:13
Reserved.
52:50
See Table 35-2
63:33
Reserved.
IA32_FEATURE_CONTROL
Core
Control Features in Intel 64Processor (R/W)
See Table 35-2.
40H
64
0
Lock (R/WL)
1
Reserved
2
Enable VMX outside SMX operation (R/WL)
MSR_
LASTBRANCH_0_FROM_IP
Core
Last Branch Record 0 From IP (R/W)
One of eight pairs of last branch record registers on the last branch
record stack. The From_IP part of the stack contains pointers to
the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.5 and record format in Section 17.4.8.1
41H
42H
43H
44H
35-76 Vol. 3C
65
66
67
68
MSR_
LASTBRANCH_1_FROM_IP
Core
MSR_
LASTBRANCH_2_FROM_IP
Core
MSR_
LASTBRANCH_3_FROM_IP
Core
MSR_
LASTBRANCH_4_FROM_IP
Core
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Hex
Dec
45H
69
46H
47H
60H
61H
62H
63H
64H
65H
66H
67H
CDH
70
71
96
97
98
99
100
101
102
103
205
Register Name
Scope
MSR_
LASTBRANCH_5_FROM_IP
Core
MSR_
LASTBRANCH_6_FROM_IP
Core
MSR_
LASTBRANCH_7_FROM_IP
Core
MSR_
LASTBRANCH_0_TO_IP
Core
MSR_
LASTBRANCH_1_TO_IP
Core
MSR_
LASTBRANCH_2_TO_IP
Core
MSR_
LASTBRANCH_3_TO_IP
Core
MSR_
LASTBRANCH_4_TO_IP
Core
MSR_
LASTBRANCH_5_TO_IP
Core
MSR_
LASTBRANCH_6_TO_IP
Core
MSR_
LASTBRANCH_7_TO_IP
Core
MSR_FSB_FREQ
Module
Bit Description
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 0 To IP (R/W)
One of eight pairs of last branch record registers on the last branch
record stack. The To_IP part of the stack contains pointers to the
destination instruction.
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock speed for
processors based on Silvermont microarchitecture:
2:0
•
•
•
•
•
63:3
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
100B: 080.0 MHz
000B: 083.3 MHz
001B: 100.0 MHz
010B: 133.3 MHz
011B: 116.7 MHz
Reserved.
Module
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
See http://biosbits.org.
Vol. 3C 35-77
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power). for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0 (no package C-sate support)
001b: C1 (Behavior is the same as 000b)
100b: C4
110b: C6
111b: C7 (Silvermont only).
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register
specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions
14:11
Reserved.
15
CFG Lock (R/WO)
When set, lock bits 15:0 of this register until next reset.
63:16
11EH
281
MSR_BBL_CR_CTL3
Reserved.
Module
0
L2 Hardware Enabled (RO)
1 = If the L2 is hardware-enabled
0 = Indicates if the L2 is hardware-disabled
7:1
Reserved.
8
L2 Enabled. (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the WBINVD
instruction or the assertion of the FLUSH# input.
22:9
Reserved.
23
L2 Not Present (RO)
0 = L2 Present
1 = L2 Not Present
1A0H
416
63:24
Reserved.
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0
Core
Fast-Strings Enable
See Table 35-2.
2:1
3
Reserved.
Module
Automatic Thermal Control Circuit Enable (R/W)
See Table 35-2. Default value is 0.
6:4
35-78 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
7
Core
Performance Monitoring Available (R)
See Table 35-2.
10:8
11
Reserved.
Core
Branch Trace Storage Unavailable (RO)
See Table 35-2.
12
Core
Processor Event Based Sampling Unavailable (RO)
See Table 35-2.
15:13
16
Reserved.
Module
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 35-2.
18
Core
ENABLE MONITOR FSM (R/W)
See Table 35-2.
21:19
22
Reserved.
Core
Limit CPUID Maxval (R/W)
See Table 35-2.
23
Module
xTPR Message Disable (R/W)
See Table 35-2.
33:24
34
Reserved.
Core
XD Bit Disable (R/W)
See Table 35-2.
37:35
38
Reserved.
Module
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost
Technology, the turbo mode feature is disabled and the IDA_Enable
feature flag will be clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H:
EAX[1] reports the processor’s support of turbo mode is enabled.
Note: the power-on default value is used by BIOS to detect
hardware support of turbo mode. If power-on default value is 1,
turbo mode is available in the processor. If power-on default value
is 0, turbo mode is not available.
63:39
1C8H
456
MSR_LBR_SELECT
Reserved.
Core
Last Branch Record Filtering Select Register (R/W)
See Section 17.7.2, “Filtering of Last Branch Records.”
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
Vol. 3C 35-79
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Hex
1C9H
Register Name
Scope
Bit Description
Dec
457
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
63:9
Reserved.
MSR_LASTBRANCH_TOS
Core
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-2) that points to the MSR containing the
most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
38EH
910
IA32_PERF_GLOBAL_
STATUS
Core
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
390H
912
IA32_PERF_GLOBAL_OVF_
CTRL
Core
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
3F1H
1009
MSR_PEBS_ENABLE
Core
See Table 35-2. See Section 18.4.4, “Processor Event Based
Sampling (PEBS).”
0
3FAH
1018
Enable PEBS for precise event on IA32_PMC0. (R/W)
MSR_PKG_C6_RESIDENCY
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C6
states. Counts at the TSC Frequency.
664H
1636
MSR_MC6_RESIDENCY_COU Module
NTER
Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
63:0
Time that this module is in module-specific C6 states since last
reset. Counts at 1 Mhz frequency.
35.4.1
MSRs with Model-Specific Behavior in the Silvermont Microarchitecture
Table 35-8 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor E3000 Series (CPUID
signature with DisplayFamily_DisplayModel of 06_37H) and Intel Atom processors (CPUID signatures with
DisplayFamily_DisplayModel of 06_4AH, 06_5AH, 06_5DH).
Table 35-8. Specific MSRs Supported by Intel® Atom™ Processors with CPUID Signatures 06_37H, 06_4AH,
06_5AH, 06_5DH
Register
Address
Hex
Dec
606H
1542
Register Name
MSR_RAPL_POWER_UNIT
Scope
Package
Bit Description
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 14.9.1, “RAPL Interfaces.”
35-80 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-8. Specific MSRs Supported by Intel® Atom™ Processors with CPUID Signatures 06_37H, 06_4AH,
06_5AH, 06_5DH
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
3:0
Power Units.
Power related information (in milliWatts) is based on the multiplier,
2^PU; where PU is an unsigned integer represented by bits 3:0.
Default value is 0101b, indicating power unit is in 32 milliWatts
increment.
7:4
Reserved
12:8
Energy Status Units.
Energy related information (in microJoules) is based on the
multiplier, 2^ESU; where ESU is an unsigned integer represented
by bits 12:8. Default value is 00101b, indicating energy unit is in
32 microJoules increment.
15:13
Reserved
19:16
Time Unit.
The value is 0000b, indicating time unit is in one second.
63:20
610H
1552
MSR_PKG_POWER_LIMIT
Reserved
Package
14:0
PKG RAPL Power Limit Control (R/W)
Package Power Limit #1. (R/W)
See Section 14.9.3, “Package RAPL Domain.” and
MSR_RAPL_POWER_UNIT in Table 35-8.
15
Enable Power Limit #1. (R/W)
See Section 14.9.3, “Package RAPL Domain.”
16
Package Clamping Limitation #1. (R/W)
23:17
Time Window for Power Limit #1. (R/W)
See Section 14.9.3, “Package RAPL Domain.”
in unit of second. If 0 is specified in bits [23:17], defaults to 1
second window.
611H
1553
63:24
Reserved
MSR_PKG_ENERGY_STATUS Package
PKG Energy Status (R/O)
See Section 14.9.3, “Package RAPL Domain.” and
MSR_RAPL_POWER_UNIT in Table 35-8
639H
1593
MSR_PP0_ENERGY_STATU
S
Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.” and
MSR_RAPL_POWER_UNIT in Table 35-8
Table 35-9 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor E3000 Series (CPUID
signature with DisplayFamily_DisplayModel of 06_37H).
Vol. 3C 35-81
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-9. Specific MSRs Supported by Intel® Atom™ Processor E3000 Series with CPUID Signature 06_37H
Register
Address
Hex
Dec
668H
1640
Register Name
MSR_CC6_DEMOTION_POLI
CY_CONFIG
Scope
Package
63:0
669H
664H
1641
1636
Bit Description
Core C6 demotion policy config MSR
Controls per-core C6 demotion policy. Writing a value of 0 disables
core level HW demotion policy.
MSR_MC6_DEMOTION_POLI
CY_CONFIG
Package
Module C6 demotion policy config MSR
63:0
Controls module (i.e. two cores sharing the second-level cache) C6
demotion policy. Writing a value of 0 disables module level HW
demotion policy.
MSR_MC6_RESIDENCY_COU Module
NTER
Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
63:0
Time that this module is in module-specific C6 states since last
reset. Counts at 1 Mhz frequency.
Table 35-10 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor C2000 Series (CPUID
signature with DisplayFamily_DisplayModel of 06_4DH).
Table 35-10. Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH
Register
Address
Hex
Dec
1A4H
420
Register Name
Scope
MSR_MISC_FEATURE_
CONTROL
0
Bit Description
Miscellaneous Feature Control (R/W)
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional
lines of code or data into the L2 cache.
1
2
Reserved
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
63:3
1ADH
429
Reserved.
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode (RW)
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
35-82 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-10. Specific MSRs Supported by Intel® Atom™ Processor C2000 Series (Contd.)with CPUID Signature
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
55:48
Package
Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.
63:56
Package
Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 14.9.1, “RAPL Interfaces.”
3:0
Power Units.
Power related information (in milliWatts) is based on the multiplier,
2^PU; where PU is an unsigned integer represented by bits 3:0.
Default value is 0101b, indicating power unit is in 32 milliWatts
increment.
7:4
Reserved
12:8
Energy Status Units.
Energy related information (in microJoules) is based on the
multiplier, 2^ESU; where ESU is an unsigned integer represented
by bits 12:8. Default value is 00101b, indicating energy unit is in
32 microJoules increment.
15:13
Reserved
19:16
Time Unit.
The value is 0000b, indicating time unit is in one second.
63:20
610H
1552
MSR_PKG_POWER_LIMIT
Reserved
Package
PKG RAPL Power Limit Control (R/W)
See Section 14.9.3, “Package RAPL Domain.”
66EH
1646
MSR_PKG_POWER_INFO
14:0
Package
PKG RAPL Parameter (R/0)
Thermal Spec Power. (R/0)
The unsigned integer value is the equivalent of thermal
specification power of the package domain. The unit of this field is
specified by the “Power Units” field of MSR_RAPL_POWER_UNIT
63:15
35.4.2
Reserved
MSRs In Intel Atom Processors Based on Airmont Microarchitecture
Intel Atom processor X7-Z8000 and X5-Z8000 series are based on the Airmont microarchitecture. These processors support MSRs listed in Table 35-6, Table 35-7, Table 35-8, and Table 35-11. These processors have a CPUID
signature with DisplayFamily_DisplayModel including 06_4CH; see Table 35-1.
Vol. 3C 35-83
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-11. MSRs in Intel Atom Processors Based on the Airmont Microarchitecture
Address
Hex
Dec
CDH
205
Register Name
MSR_FSB_FREQ
Scope
Module
Bit Description
Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock speed for
processors based on Airmont microarchitecture:
E2H
226
3:0
•
•
•
•
•
•
•
•
•
63:5
Reserved.
MSR_PKG_CST_CONFIG_
CONTROL
Module
0000B: 083.3 MHz
0001B: 100.0 MHz
0010B: 133.3 MHz
0011B: 116.7 MHz
0100B: 080.0 MHz
0101B: 093.3 MHz
0110B: 090.0 MHz
0111B: 088.9 MHz
1000B: 087.5 MHz
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power). for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: No limit
001b: C1
010b: C2
110b: C6
111b: C7
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register
specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions
14:11
Reserved.
15
CFG Lock (R/WO)
When set, lock bits 15:0 of this register until next reset.
63:16
E4H
228
MSR_PMG_IO_CAPTURE_
BASE
15:0
Reserved.
Module
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If
IO MWAIT Redirection is enabled, reads to this address will be
consumed by the power management logic and decoded to MWAIT
instructions. When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
35-84 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-11. MSRs in Intel Atom Processors Based on the Airmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
Scope
18:16
Bit Description
C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name to
be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include
001b - Deep Power Down Technology is the max C-State
010b - C7 is the max C-State to include
63:19
638H
1592
MSR_PP0_POWER_LIMIT
14:0
Reserved.
Package
PP0 RAPL Power Limit Control (R/W)
PP0 Power Limit #1. (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.” and
MSR_RAPL_POWER_UNIT in Table 35-8.
15
Enable Power Limit #1. (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
16
Reserved
23:17
Time Window for Power Limit #1. (R/W)
Specifies the time duration over which the average power must
remain below PP0_POWER_LIMIT #1(14:0). Supported Encodings:
0x0: 1 second time duration.
0x1: 5 second time duration (Default).
0x2: 10 second time duration.
0x3: 15 second time duration.
0x4: 20 second time duration.
0x5: 25 second time duration.
0x6: 30 second time duration.
0x7: 35 second time duration.
0x8: 40 second time duration.
0x9: 45 second time duration.
0xA: 50 second time duration.
0xB-0x7F - reserved.
63:24
35.5
Reserved
MSRS IN NEXT GENERATION INTEL ATOM PROCESSORS
Next Generation Intel Atom processors are based on the Goldmont microarchitecture. These processors support
MSRs listed in Table 35-6 and Table 35-12. These processors have a CPUID signature with
DisplayFamily_DisplayModel including 06_5CH; see Table 35-1.
In the Goldmont microarchitecture, the scope column indicates the following: “Core” means each processor core
has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field
is shared by a pair of processor cores in the physical package. “Package” means all processor cores in the physical
package share the same MSR or bit interface.
Vol. 3C 35-85
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture
Address
Hex
Dec
17H
23
3AH
58
Register Name
MSR_PLATFORM_ID
Scope
Module
Bit Description
Model Specific Platform ID (R)
49:0
Reserved.
52:50
See Table 35-2.
63:33
Reserved.
IA32_FEATURE_CONTROL
Core
Control Features in Intel 64Processor (R/W)
See Table 35-2.
3BH
59
0
Lock (R/WL)
1
Enable VMX inside SMX operation (R/WL)
2
Enable VMX outside SMX operation (R/WL)
14:8
SENTER local functions enables (R/WL)
15
SENTER global functions enable (R/WL)
18
SGX global functions enable (R/WL)
63:19
Reserved.
IA32_TSC_ADJUST
Core
Per-Core TSC ADJUST (R/W)
See Table 35-2.
C3H
195
IA32_PMC2
Core
Performance Counter Register
See Table 35-2.
C4H
196
IA32_PMC3
Core
Performance Counter Register
See Table 35-2.
CEH
206
MSR_PLATFORM_INFO
Package
7:0
15:8
See http://biosbits.org.
Reserved.
Package
Maximum Non-Turbo Ratio (R/O)
The is the ratio of the frequency that invariant TSC runs at.
Frequency = ratio * 100 MHz.
27:16
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limits for Turbo
mode is enabled, and when set to 0, indicates Programmable Ratio
Limits for Turbo mode is disabled.
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limits for Turbo mode are
programmable, and when set to 0, indicates TDP Limit for Turbo
mode is not programmable.
30
Package
Programmable TJ OFFSET (R/O)
When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24]
is valid and writable to specify an temperature offset.
39:31
35-86 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
47:40
Scope
Package
Bit Description
Maximum Efficiency Ratio (R/O)
The is the minimum ratio (maximum efficiency) that the processor
can operates, in units of 100MHz.
63:48
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
Reserved.
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
See http://biosbits.org.
3:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power). for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
0000b: No limit
0001b: C1
0010b: C3
0011b: C6
0100b: C7
0101b: C7S
0110b: C8
0111b: C9
1000b: C10
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register
specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions
14:11
Reserved.
15
CFG Lock (R/WO)
When set, lock bits 15:0 of this register until next reset.
63:16
17DH
381
MSR_SMM_MCA_CAP
Reserved.
Core
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in
SMM.
57:0
Reserved
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is
supported and the MSR_SMM_FEATURE_CONTROL is supported.
59
Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported
and the MSR_SMM_DELAYED is supported.
63:60
188H
392
IA32_PERFEVTSEL2
Reserved
Core
See Table 35-2.
Vol. 3C 35-87
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Register Name
Hex
Dec
189H
393
IA32_PERFEVTSEL3
1A0H
416
IA32_MISC_ENABLE
Scope
Core
Bit Description
See Table 35-2.
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0
Core
Fast-Strings Enable
See Table 35-2.
2:1
3
Reserved.
Package
Automatic Thermal Control Circuit Enable (R/W)
See Table 35-2. Default value is 1.
6:4
7
Reserved.
Core
Performance Monitoring Available (R)
See Table 35-2.
10:8
11
Reserved.
Core
Branch Trace Storage Unavailable (RO)
See Table 35-2.
12
Core
Processor Event Based Sampling Unavailable (RO)
See Table 35-2.
15:13
16
Reserved.
Package
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 35-2.
18
Core
ENABLE MONITOR FSM (R/W)
See Table 35-2.
21:19
22
Reserved.
Core
Limit CPUID Maxval (R/W)
See Table 35-2.
23
Package
xTPR Message Disable (R/W)
See Table 35-2.
33:24
34
Reserved.
Core
XD Bit Disable (R/W)
See Table 35-2.
37:35
38
Reserved.
Package
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost
Technology, the turbo mode feature is disabled and the IDA_Enable
feature flag will be clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H:
EAX[1] reports the processor’s support of turbo mode is enabled.
Note: the power-on default value is used by BIOS to detect
hardware support of turbo mode. If power-on default value is 1,
turbo mode is available in the processor. If power-on default value
is 0, turbo mode is not available.
63:39
35-88 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
1A4H
420
Register Name
Scope
MSR_MISC_FEATURE_
CONTROL
0
Bit Description
Miscellaneous Feature Control (R/W)
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional
lines of code or data into the L2 cache.
1
2
Reserved
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
63:3
1AAH
426
MSR_MISC_PWR_MGMT
Reserved.
Package
0
See http://biosbits.org.
EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced Intel
Speedstep Technology request from processor cores; When 1,
disables hardware coordination of Enhanced Intel Speedstep
Technology requests.
21:1
Reserved.
22
Thermal Interrupt Coordination Enable (R/W)
If set, then thermal interrupt on one core is routed to all cores.
63:23
1ADH
429
MSR_TURBO_RATIO_LIMIT
Reserved.
Package
Maximum Ratio Limit of Turbo Mode by Core Groups (RW)
Specifies Maximum Ratio Limit for each Core Group. Max ratio
for groups with more cores must decrease monotonically.
For groups with less than 4 cores, the max ratio must be 32 or
less. For groups with 4-5 cores, the max ratio must be 22 or
less. For groups with more than 5 cores, the max ratio must be
16 or less.
7:0
Package
Maximum Ratio Limit for Active cores in Group 0
Maximum turbo ratio limit when number of active cores is less or
equal to Group 0 threshold.
15:8
Package
Maximum Ratio Limit for Active cores in Group 1
Maximum turbo ratio limit when number of active cores is less or
equal to Group 1 threshold and greater than Group 0 threshold.
23:16
Package
Maximum Ratio Limit for Active cores in Group 2
Maximum turbo ratio limit when number of active cores is less or
equal to Group 2 threshold and greater than Group 1 threshold.
31:24
Package
Maximum Ratio Limit for Active cores in Group 3
Maximum turbo ratio limit when number of active cores is less or
equal to Group 3 threshold and greater than Group 2 threshold.
39:32
Package
Maximum Ratio Limit for Active cores in Group 4
Maximum turbo ratio limit when number of active cores is less or
equal to Group 4 threshold and greater than Group 3 threshold.
Vol. 3C 35-89
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
47:40
Scope
Package
Bit Description
Maximum Ratio Limit for Active cores in Group 5
Maximum turbo ratio limit when number of active cores is less or
equal to Group 5 threshold and greater than Group 4 threshold.
55:48
Package
Maximum Ratio Limit for Active cores in Group 6
Maximum turbo ratio limit when number of active cores is less or
equal to Group 6 threshold and greater than Group 5 threshold.
63:56
Package
Maximum Ratio Limit for Active cores in Group 7
Maximum turbo ratio limit when number of active cores is less or
equal to Group 7 threshold and greater than Group 6 threshold.
1AEH
430
MSR_TURBO_GROUP_CORE
CNT
Package
7:0
Package
Group Size of Active Cores for Turbo Mode Operation (RW)
Writes of 0 threshold is ignored
Group 0 Core Count Threshold
Maximum number of active cores to operate under Group 0 Max
Turbo Ratio limit.
15:8
Package
Group 1 Core Count Threshold
Maximum number of active cores to operate under Group 1 Max
Turbo Ratio limit. Must be greater than Group 0 Core Count.
23:16
Package
Group 2 Core Count Threshold
Maximum number of active cores to operate under Group 2 Max
Turbo Ratio limit. Must be greater than Group 1 Core Count.
31:24
Package
Group 3 Core Count Threshold
Maximum number of active cores to operate under Group 3 Max
Turbo Ratio limit. Must be greater than Group 2 Core Count.
39:32
Package
Group 4 Core Count Threshold
Maximum number of active cores to operate under Group 4 Max
Turbo Ratio limit. Must be greater than Group 3 Core Count.
47:40
Package
Group 5 Core Count Threshold
Maximum number of active cores to operate under Group 5 Max
Turbo Ratio limit. Must be greater than Group 4 Core Count.
55:48
Package
Group 6 Core Count Threshold
Maximum number of active cores to operate under Group 6 Max
Turbo Ratio limit. Must be greater than Group 5 Core Count.
63:56
Package
Group 7 Core Count Threshold
Maximum number of active cores to operate under Group 7 Max
Turbo Ratio limit. Must be greater than Group 6 Core Count and not
less than the total number of processor cores in the package. E.g.
specify 255.
1C8H
456
MSR_LBR_SELECT
Core
Last Branch Record Filtering Select Register (R/W)
See Section 17.7.2, “Filtering of Last Branch Records.”
35-90 Vol. 3C
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
Scope
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
9
EN_CALL_STACK
63:10
1C9H
457
Bit Description
MSR_LASTBRANCH_TOS
Reserved.
Core
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-4) that points to the MSR containing the
most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
1FCH
508
MSR_POWER_CTL
Core
0
1
Power Control Register. See http://biosbits.org.
Reserved.
Package
C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the Minimum
Enhanced Intel SpeedStep Technology operating point when all
execution cores enter MWAIT (C1).
63:2
Reserved.
210H
528
IA32_MTRR_PHYSBASE8
Core
See Table 35-2.
211H
529
IA32_MTRR_PHYSMASK8
Core
See Table 35-2.
212H
530
IA32_MTRR_PHYSBASE9
Core
See Table 35-2.
213H
531
IA32_MTRR_PHYSMASK9
Core
See Table 35-2.
280H
640
IA32_MC0_CTL2
Module
See Table 35-2.
281H
641
IA32_MC1_CTL2
Module
See Table 35-2.
282H
642
IA32_MC2_CTL2
Core
See Table 35-2.
283H
643
IA32_MC3_CTL2
Module
See Table 35-2.
284H
644
IA32_MC4_CTL2
Package
See Table 35-2.
285H
645
IA32_MC5_CTL2
Package
See Table 35-2.
286H
646
IA32_MC6_CTL2
Package
See Table 35-2.
300H
768
MSR_SGXOWNER0
Package
Lower 64 Bit OwnerEpoch Component of SGX Key (RO).
63:0
301H
769
MSR_SGXOWNER1
Low 64 bits of an 128-bit external entropy value for key
derivation of an enclave.
Package
63:0
38EH
910
IA32_PERF_GLOBAL_
STATUS
Upper 64 Bit OwnerEpoch Component of SGX Key (RO).
Upper 64 bits of an 128-bit external entropy value for key
derivation of an enclave.
Core
See Table 35-2. See Section 18.2.4, “Architectural Performance
Monitoring Version 4.”
0
Ovf_PMC0
1
Ovf_PMC1
2
Ovf_PMC2
Vol. 3C 35-91
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
Scope
3
Ovf_PMC3
31:4
Reserved.
32
Ovf_FixedCtr0
33
Ovf_FixedCtr1
34
Ovf_FixedCtr2
54:35
Reserved.
55
Trace_ToPA_PMI.
57:56
Reserved.
58
LBR_Frz.
59
CTR_Frz.
60
ASCI.
61
Ovf_Uncore
62
Ovf_BufDSSAVE
63
390H
391H
912
913
35-92 Vol. 3C
Bit Description
IA32_PERF_GLOBAL_STAT
US_RESET
CondChgd
Core
See Table 35-2. See Section 18.2.4, “Architectural Performance
Monitoring Version 4.”
0
Set 1 to clear Ovf_PMC0
1
Set 1 to clear Ovf_PMC1
2
Set 1 to clear Ovf_PMC2
3
Set 1 to clear Ovf_PMC3
31:4
Reserved.
32
Set 1 to clear Ovf_FixedCtr0
33
Set 1 to clear Ovf_FixedCtr1
34
Set 1 to clear Ovf_FixedCtr2
54:35
Reserved.
55
Set 1 to clear Trace_ToPA_PMI.
57:56
Reserved.
58
Set 1 to clear LBR_Frz.
59
Set 1 to clear CTR_Frz.
60
Set 1 to clear ASCI.
61
Set 1 to clear Ovf_Uncore
62
Set 1 to clear Ovf_BufDSSAVE
63
Set 1 to clear CondChgd
IA32_PERF_GLOBAL_STAT
US_SET
Core
See Table 35-2. See Section 18.2.4, “Architectural Performance
Monitoring Version 4.”
0
Set 1 to cause Ovf_PMC0 = 1
1
Set 1 to cause Ovf_PMC1 = 1
2
Set 1 to cause Ovf_PMC2 = 1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
Scope
Bit Description
3
Set 1 to cause Ovf_PMC3 = 1
31:4
Reserved.
32
Set 1 to cause Ovf_FixedCtr0 = 1
33
Set 1 to cause Ovf_FixedCtr1 = 1
34
Set 1 to cause Ovf_FixedCtr2 = 1
54:35
Reserved.
55
Set 1 to cause Trace_ToPA_PMI = 1
57:56
Reserved.
58
Set 1 to cause LBR_Frz = 1
59
Set 1 to cause CTR_Frz = 1
60
Set 1 to cause ASCI = 1
61
Set 1 to cause Ovf_Uncore
62
Set 1 to cause Ovf_BufDSSAVE
63
Reserved.
392H
914
IA32_PERF_GLOBAL_INUSE
See Table 35-2.
3F1H
1009
MSR_PEBS_ENABLE
Core
0
3F8H
1016
MSR_PKG_C3_RESIDENCY
See Table 35-2. See Section 18.4.4, “Processor Event Based
Sampling (PEBS).”
Enable PEBS trigger and recording for the programmed event
(precise or otherwise) on IA32_PMC0. (R/W)
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C3 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C3
states. Count at the same frequency as the TSC.
3F9H
1017
MSR_PKG_C6_RESIDENCY
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C6
states. Count at the same frequency as the TSC.
3FCH
1020
MSR_CORE_C3_RESIDENCY
63:0
Core
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
CORE C3 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C3
states. Count at the same frequency as the TSC.
Vol. 3C 35-93
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
406H
1030
Register Name
IA32_MC1_ADDR
Scope
Module
Bit Description
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC2_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
418H
1048
IA32_MC6_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
419H
1049
IA32_MC6_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
41AH
1050
IA32_MC6_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
4C3H
1219
IA32_A_PMC2
Core
See Table 35-2.
4C4H
1220
IA32_A_PMC3
Core
See Table 35-2.
4E0H
1248
MSR_SMM_FEATURE_CONT
ROL
Package
Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible only while in
SMM.
0
Lock (SMM-RWO)
When set to ‘1’ locks this register from further changes
1
Reserved
2
SMM_Code_Chk_En (SMM-RW)
This control bit is available only if MSR_SMM_MCA_CAP[58] == 1.
When set to ‘0’ (default) none of the logical processors are
prevented from executing SMM code outside the ranges defined by
the SMRR.
When set to ‘1’ any logical processor in the package that attempts
to execute SMM code not within the ranges defined by the SMRR
will assert an unrecoverable MCE.
63:3
4E2H
1250
MSR_SMM_DELAYED
Reserved
Package
SMM Delayed (SMM-RO)
Reports the interruptible state of all logical processors in the
package. Available only while in SMM and
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
N-1:0
LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its state in a long flow of
internal operation which delays servicing an interrupt. The
corresponding bit will be set at the start of long events such as:
Microcode Update Load, C6, WBINVD, Ratio Change, Throttle.
The bit is automatically cleared at the end of each long event. The
reset value of this field is 0.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N
4E3H
1251
MSR_SMM_BLOCKED
Reserved
Package
SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in the package.
Available only while in SMM.
35-94 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
Scope
N-1:0
Bit Description
LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its blocked state to service
an SMI. The corresponding bit will be set if the logical processor is
in one of the following states: Wait For SIPI or SENTER Sleep.
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N
500H
1280
IA32_SGX_SVN_STATUS
Reserved
Core
Status and SVN Threshold of SGX Support for ACM (RO).
0
Lock. See Section 42.11.3, “Interactions with Authenticated Code
Modules (ACMs)”
15:1
Reserved.
23:16
SGX_SVN_SINIT. See Section 42.11.3, “Interactions with
Authenticated Code Modules (ACMs)”
63:24
Reserved.
560H
1376
IA32_RTIT_OUTPUT_BASE
Core
Trace Output Base Register (R/W). See Table 35-2.
561H
1377
IA32_RTIT_OUTPUT_MASK
_PTRS
Core
Trace Output Mask Pointers Register (R/W). See Table 35-2.
570H
1392
IA32_RTIT_CTL
Core
Trace Control Register (R/W)
0
TraceEn
1
CYCEn
2
OS
3
User
6:4
Reserved, MBZ
7
CR3 filter
8
ToPA; writing 0 will #GP if also setting TraceEn
9
MTCEn
10
TSCEn
11
DisRETC
12
Reserved, MBZ
13
BranchEn
17:14
MTCFreq
18
Reserved, MBZ
22:19
CYCThresh
23
Reserved, MBZ
27:24
PSBFreq
31:28
Reserved, MBZ
35:32
ADDR0_CFG
39:36
ADDR1_CFG
63:40
Reserved, MBZ.
Vol. 3C 35-95
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
571H
1393
572H
580H
1394
1408
Register Name
IA32_RTIT_STATUS
Scope
Core
FilterEn, writes ignored.
1
ContexEn, writes ignored.
2
TriggerEn, writes ignored.
3
Reserved
4
Error (R/W)
5
Stopped
31:6
Reserved. MBZ
48:32
PacketByteCnt
63:49
Reserved, MBZ.
IA32_RTIT_CR3_MATCH
Core
Reserved
63:5
CR3[63:5] value to match
IA32_RTIT_ADDR0_A
1409
IA32_RTIT_ADDR0_B
582H
1410
IA32_RTIT_ADDR1_A
Core
Core
Region 0 End Address (R/W)
Core
Region 1 Start Address (R/W)
See Table 35-2.
63:0
IA32_RTIT_ADDR1_B
See Table 35-2.
Core
63:0
1542
MSR_RAPL_POWER_UNIT
Region 0 Start Address (R/W)
See Table 35-2.
63:0
606H
Trace Filter CR3 Match Register (R/W)
4:0
581H
1411
Tracing Status Register (R/W)
0
63:0
583H
Bit Description
Region 1 End Address (R/W)
See Table 35-2.
Package
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 14.9.1, “RAPL Interfaces.”
3:0
Power Units.
Power related information (in Watts) is in unit of, 1W/2^PU; where
PU is an unsigned integer represented by bits 3:0. Default value is
1000b, indicating power unit is in 3.9 milliWatts increment.
7:4
Reserved
12:8
Energy Status Units.
Energy related information (in Joules) is in unit of, 1Joule/ (2^ESU);
where ESU is an unsigned integer represented by bits 12:8. Default
value is 01110b, indicating energy unit is in 61 microJoules.
15:13
Reserved
19:16
Time Unit.
Time related information (in seconds) is in unit of, 1S/2^TU; where
TU is an unsigned integer represented by bits 19:16. Default value
is 1010b, indicating power unit is in 0.977 millisecond.
63:20
35-96 Vol. 3C
Reserved
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
60AH
1546
Register Name
MSR_PKGC3_IRTL
Scope
Package
Bit Description
Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C3 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings.
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
60BH
1547
MSR_PKGC_IRTL1
Reserved.
Package
Package C6/C7S Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit used by the
processor to manage transition to package C6 or C7S state.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C6 or C7S state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
60CH
1548
MSR_PKGC_IRTL2
Reserved.
Package
Package C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit used by the
processor to manage transition to package C7 state.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C7 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings
Vol. 3C 35-97
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
Scope
Bit Description
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
60DH
1549
MSR_PKG_C2_RESIDENCY
Reserved.
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C2 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C2
states. Count at the same frequency as the TSC.
610H
1552
MSR_PKG_POWER_LIMIT
Package
PKG RAPL Power Limit Control (R/W)
See Section 14.9.3, “Package RAPL Domain.”
611H
1553
MSR_PKG_ENERGY_STATUS Package
613H
1555
MSR_PKG_PERF_STATUS
PKG Energy Status (R/O)
See Section 14.9.3, “Package RAPL Domain.”
Package
PKG Perf Status (R/O)
See Section 14.9.3, “Package RAPL Domain.”
614H
1556
MSR_PKG_POWER_INFO
Package
14:0
PKG RAPL Parameters (R/W)
Thermal Spec Power (R/W)
See Section 14.9.3, “Package RAPL Domain.”
15
Reserved.
30:16
Minimum Power (R/W)
See Section 14.9.3, “Package RAPL Domain.”
31
Reserved.
46:32
Maximum Power (R/W)
47
Reserved.
54:48
Maximum Time Window (R/W)
See Section 14.9.3, “Package RAPL Domain.”
Specified by 2^Y * (1.0 + Z/4.0) * Time_Unit, where “Y”
is the unsigned integer value represented. by bits
52:48, “Z” is an unsigned integer represented by bits
54:53. “Time_Unit” is specified by the “Time Units” field
of MSR_RAPL_POWER_UNIT
63:55
618H
1560
MSR_DRAM_POWER_LIMIT
Reserved.
Package
DRAM RAPL Power Limit Control (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_
STATUS
Package
DRAM Energy Status (R/O)
See Section 14.9.5, “DRAM RAPL Domain.”
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O) See Section 14.9.5,
“DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
35-98 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
632H
1586
Register Name
MSR_PKG_C10_RESIDENCY
Scope
Package
63:0
Bit Description
Note: C-state values are processor specific C-state code names,
Package C10 Residency Counter. (R/O)
Value since last reset that the entire SOC is in an S0i3 state. Count
at the same frequency as the TSC.
639H
641H
64CH
1593
1601
1612
MSR_PP0_ENERGY_STATU
S
Package
MSR_PP1_ENERGY_STATU
S
Package
MSR_TURBO_ACTIVATION_
RATIO
Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
PP1 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
7:0
ConfigTDP Control (R/W)
MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8
Reserved.
31
TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is locked until a
reset.
64FH
1615
63:32
Reserved.
MSR_CORE_PERF_LIMIT_RE Package
ASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
0
PROCHOT Status (R0)
(frequency refers to processor core frequency)
When set, processor core frequency is reduced below the
operating system request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
2
Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
3
Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
8:4
Reserved.
9
Core Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to domain-level power limiting.
10
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
11
Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system
request due to multi-core turbo limits.
Vol. 3C 35-99
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
12
Scope
Bit Description
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
13
Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system
request due to Turbo transition attenuation. This prevents
performance degradation due to frequent operating ratio changes.
14
Maximum Efficiency Frequency Status (R0)
When set, frequency is reduced below the maximum efficiency
frequency.
15
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18
Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19
Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24:20
Reserved.
25
Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
35-100 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Register Name
Dec
Scope
28
Bit Description
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30
Maximum Efficiency Frequency Log
When set, indicates that the Maximum Efficiency Frequency Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:31
680H
1664
MSR_
LASTBRANCH_0_FROM_IP
Reserved.
Core
Last Branch Record 0 From IP (R/W)
One of 32 pairs of last branch record registers on the last branch
record stack. The From_IP part of the stack contains pointers to
the source instruction . See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.6 and record format in Section 17.4.8.1
681H
682H
683H
684H
685H
686H
687H
688H
689H
68AH
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
0:47
From Linear Address (R/W)
62:48
Signed extension of bits 47:0.
63
Mispred
MSR_
LASTBRANCH_1_FROM_IP
Core
MSR_
LASTBRANCH_2_FROM_IP
Core
MSR_
LASTBRANCH_3_FROM_IP
Core
MSR_
LASTBRANCH_4_FROM_IP
Core
MSR_
LASTBRANCH_5_FROM_IP
Core
MSR_
LASTBRANCH_6_FROM_IP
Core
MSR_
LASTBRANCH_7_FROM_IP
Core
MSR_
LASTBRANCH_8_FROM_IP
Core
MSR_
LASTBRANCH_9_FROM_IP
Core
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
MSR_
Core
LASTBRANCH_10_FROM_IP
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Vol. 3C 35-101
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
68BH
1675
68CH
68DH
68EH
68FH
690H
691H
692H
693H
694H
695H
696H
697H
698H
699H
69AH
69BH
69CH
69DH
69EH
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
35-102 Vol. 3C
Register Name
Scope
Bit Description
MSR_
Core
LASTBRANCH_11_FROM_IP
Last Branch Record 11 From IP (R/W)
MSR_
Core
LASTBRANCH_12_FROM_IP
Last Branch Record 12 From IP (R/W)
MSR_
Core
LASTBRANCH_13_FROM_IP
Last Branch Record 13 From IP (R/W)
MSR_
Core
LASTBRANCH_14_FROM_IP
Last Branch Record 14 From IP (R/W)
MSR_
Core
LASTBRANCH_15_FROM_IP
Last Branch Record 15 From IP (R/W)
MSR_
Core
LASTBRANCH_16_FROM_IP
Last Branch Record 16 From IP (R/W)
MSR_
Core
LASTBRANCH_17_FROM_IP
Last Branch Record 17 From IP (R/W)
MSR_
Core
LASTBRANCH_18_FROM_IP
Last Branch Record 18 From IP (R/W)
MSR_
Core
LASTBRANCH_19_FROM_IP
Last Branch Record 19From IP (R/W)
MSR_
Core
LASTBRANCH_20_FROM_IP
Last Branch Record 20 From IP (R/W)
MSR_
Core
LASTBRANCH_21_FROM_IP
Last Branch Record 21 From IP (R/W)
MSR_
Core
LASTBRANCH_22_FROM_IP
Last Branch Record 22 From IP (R/W)
MSR_
Core
LASTBRANCH_23_FROM_IP
Last Branch Record 23 From IP (R/W)
MSR_
Core
LASTBRANCH_24_FROM_IP
Last Branch Record 24 From IP (R/W)
MSR_
Core
LASTBRANCH_25_FROM_IP
Last Branch Record 25 From IP (R/W)
MSR_
Core
LASTBRANCH_26_FROM_IP
Last Branch Record 26 From IP (R/W)
MSR_
Core
LASTBRANCH_27_FROM_IP
Last Branch Record 27 From IP (R/W)
MSR_
Core
LASTBRANCH_28_FROM_IP
Last Branch Record 28 From IP (R/W)
MSR_
Core
LASTBRANCH_29_FROM_IP
Last Branch Record 29 From IP (R/W)
MSR_
Core
LASTBRANCH_30_FROM_IP
Last Branch Record 30 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
69FH
1695
6C0H
1728
Register Name
Scope
Bit Description
MSR_
Core
LASTBRANCH_31_FROM_IP
Last Branch Record 31 From IP (R/W)
MSR_
LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
Core
See description of MSR_LASTBRANCH_0_FROM_IP.
One of 32 pairs of last branch record registers on the last branch
record stack. The To_IP part of the stack contains pointers to the
Destination instruction and elapsed cycles from last LBR update.
See also:
• Section 17.6
6C1H
6C2H
6C3H
6C4H
6C5H
6C6H
6C7H
6C8H
6C9H
6CAH
6CBH
6CCH
6CDH
6CEH
6CFH
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
0:47
Target Linear Address (R/W)
63:48
Elapsed cycles from last update to the LBR.
MSR_
LASTBRANCH_1_TO_IP
Core
MSR_
LASTBRANCH_2_TO_IP
Core
MSR_
LASTBRANCH_3_TO_IP
Core
MSR_
LASTBRANCH_4_TO_IP
Core
MSR_
LASTBRANCH_5_TO_IP
Core
MSR_
LASTBRANCH_6_TO_IP
Core
MSR_
LASTBRANCH_7_TO_IP
Core
MSR_
LASTBRANCH_8_TO_IP
Core
MSR_
LASTBRANCH_9_TO_IP
Core
MSR_
LASTBRANCH_10_TO_IP
Core
MSR_
LASTBRANCH_11_TO_IP
Core
MSR_
LASTBRANCH_12_TO_IP
Core
MSR_
LASTBRANCH_13_TO_IP
Core
MSR_
LASTBRANCH_14_TO_IP
Core
MSR_
LASTBRANCH_15_TO_IP
Core
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Vol. 3C 35-103
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
6D0H
1744
6D1H
6D2H
6D3H
6D4H
6D5H
6D6H
6D7H
6D8H
6D9H
6DAH
6DBH
6DCH
6DDH
6DEH
6DFH
802H
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
2050
Register Name
Scope
MSR_
LASTBRANCH_16_TO_IP
Core
MSR_
LASTBRANCH_17_TO_IP
Core
MSR_
LASTBRANCH_18_TO_IP
Core
MSR_
LASTBRANCH_19_TO_IP
Core
MSR_
LASTBRANCH_20_TO_IP
Core
MSR_
LASTBRANCH_21_TO_IP
Core
MSR_
LASTBRANCH_22_TO_IP
Core
MSR_
LASTBRANCH_23_TO_IP
Core
MSR_
LASTBRANCH_24_TO_IP
Core
MSR_
LASTBRANCH_25_TO_IP
Core
MSR_
LASTBRANCH_26_TO_IP
Core
MSR_
LASTBRANCH_27_TO_IP
Core
MSR_
LASTBRANCH_28_TO_IP
Core
MSR_
LASTBRANCH_29_TO_IP
Core
MSR_
LASTBRANCH_30_TO_IP
Core
MSR_
LASTBRANCH_31_TO_IP
Core
IA32_X2APIC_APICID
Core
Bit Description
Last Branch Record 16 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 25 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 26 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 27 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 28 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 29 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 30 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 31 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
x2APIC ID register (R/O) See x2APIC Specification.
803H
2051
IA32_X2APIC_VERSION
Core
x2APIC Version register (R/O)
808H
2056
IA32_X2APIC_TPR
Core
x2APIC Task Priority register (R/W)
80AH
2058
IA32_X2APIC_PPR
Core
x2APIC Processor Priority register (R/O)
80BH
2059
IA32_X2APIC_EOI
Core
x2APIC EOI register (W/O)
80DH
2061
IA32_X2APIC_LDR
Core
x2APIC Logical Destination register (R/O)
80FH
2063
IA32_X2APIC_SIVR
Core
x2APIC Spurious Interrupt Vector register (R/W)
35-104 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
Register Name
Scope
Bit Description
810H
2064
IA32_X2APIC_ISR0
Core
x2APIC In-Service register bits [31:0] (R/O)
811H
2065
IA32_X2APIC_ISR1
Core
x2APIC In-Service register bits [63:32] (R/O)
812H
2066
IA32_X2APIC_ISR2
Core
x2APIC In-Service register bits [95:64] (R/O)
813H
2067
IA32_X2APIC_ISR3
Core
x2APIC In-Service register bits [127:96] (R/O)
814H
2068
IA32_X2APIC_ISR4
Core
x2APIC In-Service register bits [159:128] (R/O)
815H
2069
IA32_X2APIC_ISR5
Core
x2APIC In-Service register bits [191:160] (R/O)
816H
2070
IA32_X2APIC_ISR6
Core
x2APIC In-Service register bits [223:192] (R/O)
817H
2071
IA32_X2APIC_ISR7
Core
x2APIC In-Service register bits [255:224] (R/O)
818H
2072
IA32_X2APIC_TMR0
Core
x2APIC Trigger Mode register bits [31:0] (R/O)
819H
2073
IA32_X2APIC_TMR1
Core
x2APIC Trigger Mode register bits [63:32] (R/O)
81AH
2074
IA32_X2APIC_TMR2
Core
x2APIC Trigger Mode register bits [95:64] (R/O)
81BH
2075
IA32_X2APIC_TMR3
Core
x2APIC Trigger Mode register bits [127:96] (R/O)
81CH
2076
IA32_X2APIC_TMR4
Core
x2APIC Trigger Mode register bits [159:128] (R/O)
81DH
2077
IA32_X2APIC_TMR5
Core
x2APIC Trigger Mode register bits [191:160] (R/O)
81EH
2078
IA32_X2APIC_TMR6
Core
x2APIC Trigger Mode register bits [223:192] (R/O)
81FH
2079
IA32_X2APIC_TMR7
Core
x2APIC Trigger Mode register bits [255:224] (R/O)
820H
2080
IA32_X2APIC_IRR0
Core
x2APIC Interrupt Request register bits [31:0] (R/O)
821H
2081
IA32_X2APIC_IRR1
Core
x2APIC Interrupt Request register bits [63:32] (R/O)
822H
2082
IA32_X2APIC_IRR2
Core
x2APIC Interrupt Request register bits [95:64] (R/O)
823H
2083
IA32_X2APIC_IRR3
Core
x2APIC Interrupt Request register bits [127:96] (R/O)
824H
2084
IA32_X2APIC_IRR4
Core
x2APIC Interrupt Request register bits [159:128] (R/O)
825H
2085
IA32_X2APIC_IRR5
Core
x2APIC Interrupt Request register bits [191:160] (R/O)
826H
2086
IA32_X2APIC_IRR6
Core
x2APIC Interrupt Request register bits [223:192] (R/O)
827H
2087
IA32_X2APIC_IRR7
Core
x2APIC Interrupt Request register bits [255:224] (R/O)
828H
2088
IA32_X2APIC_ESR
Core
x2APIC Error Status register (R/W)
82FH
2095
IA32_X2APIC_LVT_CMCI
Core
x2APIC LVT Corrected Machine Check Interrupt register (R/W)
830H
2096
IA32_X2APIC_ICR
Core
x2APIC Interrupt Command register (R/W)
832H
2098
IA32_X2APIC_LVT_TIMER
Core
x2APIC LVT Timer Interrupt register (R/W)
833H
2099
IA32_X2APIC_LVT_THERM
AL
Core
x2APIC LVT Thermal Sensor Interrupt register (R/W)
834H
2100
IA32_X2APIC_LVT_PMI
Core
x2APIC LVT Performance Monitor register (R/W)
835H
2101
IA32_X2APIC_LVT_LINT0
Core
x2APIC LVT LINT0 register (R/W)
836H
2102
IA32_X2APIC_LVT_LINT1
Core
x2APIC LVT LINT1 register (R/W)
837H
2103
IA32_X2APIC_LVT_ERROR
Core
x2APIC LVT Error register (R/W)
838H
2104
IA32_X2APIC_INIT_COUNT
Core
x2APIC Initial Count register (R/W)
839H
2105
IA32_X2APIC_CUR_COUNT
Core
x2APIC Current Count register (R/O)
83EH
2110
IA32_X2APIC_DIV_CONF
Core
x2APIC Divide Configuration register (R/W)
83FH
2111
IA32_X2APIC_SELF_IPI
Core
x2APIC Self IPI register (W/O)
Vol. 3C 35-105
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Hex
Dec
C8FH
3215
Register Name
IA32_PQR_ASSOC
Scope
Core
3344
Resource Association Register (R/W)
31:0
Reserved
33:32
COS (R/W).
63: 34
D10H
Bit Description
IA32_L2_QOS_MASK_0
Reserved
Module
L2 Class Of Service Mask - COS 0 (R/W)
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0
D11H
3345
0:7
CBM: Bit vector of available L2 ways for COS 0 enforcement
63:8
Reserved
IA32_L2_QOS_MASK_1
Module
L2 Class Of Service Mask - COS 1 (R/W)
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1
0:7
CBM: Bit vector of available L2 ways for COS 0 enforcement
63:8
D12H
3346
IA32_L2_QOS_MASK_2
Reserved
Module
L2 Class Of Service Mask - COS 2 (R/W)
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2
D13H
3347
0:7
CBM: Bit vector of available L2 ways for COS 0 enforcement
63:8
Reserved
IA32_L2_QOS_MASK_3
Package
L2 Class Of Service Mask - COS 3 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3
0:19
CBM: Bit vector of available L2 ways for COS 3 enforcement
63:20
Reserved
D90H
3472
IA32_BNDCFGS
Core
See Table 35-2.
DA0H
3488
IA32_XSS
Core
See Table 35-2.
See Table 35-6, and Table 35-12 for MSR definitions applicable to processors with CPUID signature 06_5CH.
35.6
MSRS IN THE INTEL® MICROARCHITECTURE CODE NAME NEHALEM
Table 35-13 lists model-specific registers (MSRs) that are common for Intel® microarchitecture code name
Nehalem. These include Intel Core i7 and i5 processor family. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_1AH, 06_1EH, 06_1FH, 06_2EH, see Table 35-1. Additional MSRs specific to
06_1AH, 06_1EH, 06_1FH are listed in Table 35-14. Some MSRs listed in these tables are used by BIOS. More information about these MSR can be found at http://biosbits.org.
The column “Scope” represents the package/core/thread scope of individual bit field of an MSR. “Thread” means
this bit field must be programmed on each logical processor independently. “Core” means the bit field must be
programmed on each processor core independently, logical processors in the same core will be affected by change
of this bit on the other logical processor in the same core. “Package” means the bit field must be programmed once
for each physical package. Change of a bit filed with a package scope will affect all logical processors in that physical package.
35-106 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Thread
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Thread
See Section 35.22, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_
SIZE
Thread
See Section 8.10.5, “Monitor/Mwait Address Range Determination,”
and Table 35-2.
10H
16
IA32_TIME_
STAMP_COUNTER
Thread
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
17H
23
IA32_PLATFORM_ID
Package
Platform ID (R)
See Table 35-2.
17H
23
MSR_PLATFORM_ID
Package
Model Specific Platform ID (R)
49:0
Reserved.
52:50
See Table 35-2.
63:53
Reserved.
1BH
27
IA32_APIC_BASE
Thread
See Section 10.4.4, “Local APIC Status and Location,” and
Table 35-2.
34H
52
MSR_SMI_COUNT
Thread
SMI Counter (R/O)
31:0
SMI Count (R/O)
Running count of SMI events since last RESET.
63:32
3AH
58
IA32_FEATURE_CONTROL
Reserved.
Thread
Control Features in Intel 64Processor (R/W)
See Table 35-2.
79H
8BH
C1H
121
139
193
IA32_BIOS_
UPDT_TRIG
Core
IA32_BIOS_
SIGN_ID
Thread
IA32_PMC0
Thread
BIOS Update Trigger Register (W)
See Table 35-2.
BIOS Update Signature ID (RO)
See Table 35-2.
Performance Counter Register
See Table 35-2.
C2H
194
IA32_PMC1
Thread
Performance Counter Register
See Table 35-2.
C3H
195
IA32_PMC2
Thread
Performance Counter Register
See Table 35-2.
C4H
196
IA32_PMC3
Thread
Performance Counter Register
See Table 35-2.
CEH
206
MSR_PLATFORM_INFO
7:0
Package
see http://biosbits.org.
Reserved.
Vol. 3C 35-107
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
15:8
Package
Maximum Non-Turbo Ratio (R/O)
The is the ratio of the frequency that invariant TSC runs at. The
invariant TSC frequency can be computed by multiplying this ratio
by 133.33 MHz.
27:16
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limits for Turbo
mode is enabled, and when set to 0, indicates Programmable Ratio
Limits for Turbo mode is disabled.
29
Package
Programmable TDC-TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDC/TDP Limits for Turbo mode are
programmable, and when set to 0, indicates TDC and TDP Limits for
Turbo mode are not programmable.
39:30
47:40
Reserved.
Package
Maximum Efficiency Ratio (R/O)
The is the minimum ratio (maximum efficiency) that the processor
can operates, in units of 133.33MHz.
63:48
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
2:0
Reserved.
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates. See http://biosbits.org.
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power). for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0 (no package C-sate support)
001b: C1 (Behavior is the same as 000b)
010b: C3
011b: C6
100b: C7
101b and 110b: Reserved
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register
specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11
Reserved.
15
CFG Lock (R/WO)
When set, lock bits 15:0 of this register until next reset.
35-108 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
23:16
Reserved.
24
Interrupt filtering enable (R/W)
When set, processor cores in a deep C-State will wake only when
the event message is destined for that core. When 0, all processor
cores in a deep C-State will wake for an event message.
25
C3 state auto demotion enable (R/W)
When set, the processor will conditionally demote C6/C7 requests
to C3 based on uncore auto-demote information.
26
C1 state auto demotion enable (R/W)
When set, the processor will conditionally demote C3/C6/C7
requests to C1 based on uncore auto-demote information.
E4H
228
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Package C State Demotion Enable (R/W)
30
Package C State UnDemotion Enable (R/W)
63:31
Reserved.
MSR_PMG_IO_CAPTURE_
BASE
Core
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
15:0
LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If
IO MWAIT Redirection is enabled, reads to this address will be
consumed by the power management logic and decoded to MWAIT
instructions. When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
18:16
C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name to
be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include
001b - C6 is the max C-State to include
010b - C7 is the max C-State to include
63:19
E7H
231
IA32_MPERF
Reserved.
Thread
Maximum Performance Frequency Clock Count (RW)
See Table 35-2.
E8H
232
IA32_APERF
Thread
Actual Performance Frequency Clock Count (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Thread
See Table 35-2.
174H
372
IA32_SYSENTER_CS
Thread
See Table 35-2.
175H
373
IA32_SYSENTER_ESP
Thread
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Thread
See Table 35-2.
Vol. 3C 35-109
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Register Name
Scope
Hex
Dec
179H
377
IA32_MCG_CAP
Thread
17AH
378
IA32_MCG_STATUS
Thread
0
Bit Description
See Table 35-2.
RIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If cleared, the
program cannot be reliably restarted.
1
EIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, bit indicates that a machine check has been generated. If
a second machine check is detected while this bit is still set, the
processor enters a shutdown state. Software should write this bit
to 0 after processing a machine check exception.
63:3
186H
390
IA32_PERFEVTSEL0
Reserved.
Thread
See Table 35-2.
7:0
Event Select
15:8
UMask
16
USR
17
OS
18
Edge
19
PC
20
INT
21
AnyThread
22
EN
23
INV
31:24
CMASK
63:32
Reserved.
187H
391
IA32_PERFEVTSEL1
Thread
See Table 35-2.
188H
392
IA32_PERFEVTSEL2
Thread
See Table 35-2.
189H
393
IA32_PERFEVTSEL3
Thread
See Table 35-2.
198H
408
IA32_PERF_STATUS
Core
See Table 35-2.
199H
409
35-110 Vol. 3C
15:0
Current Performance State Value.
63:16
Reserved.
IA32_PERF_CTL
Thread
See Table 35-2.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Dec
19AH
410
Register Name
IA32_CLOCK_MODULATION
Scope
Thread
Bit Description
Clock Modulation (R/W)
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
0
Reserved.
3:1
On demand Clock Modulation Duty Cycle (R/W)
4
On demand Clock Modulation Enable (R/W)
63:5
Reserved.
19BH
411
IA32_THERM_INTERRUPT
Core
Thermal Interrupt Control (R/W)
19CH
412
IA32_THERM_STATUS
Core
Thermal Monitor Status (R/W)
See Table 35-2.
See Table 35-2.
1A0H
416
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0
Thread
Fast-Strings Enable
See Table 35-2.
2:1
3
Reserved.
Thread
Automatic Thermal Control Circuit Enable (R/W)
See Table 35-2. Default value is 1.
6:4
7
Reserved.
Thread
Performance Monitoring Available (R)
See Table 35-2.
10:8
Reserved.
11
Thread
12
Thread
Branch Trace Storage Unavailable (RO)
See Table 35-2.
Processor Event Based Sampling Unavailable (RO)
See Table 35-2.
15:13
16
Reserved.
Package
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 35-2.
18
Thread
ENABLE MONITOR FSM. (R/W) See Table 35-2.
Thread
Limit CPUID Maxval (R/W)
21:19
22
Reserved.
See Table 35-2.
23
Thread
xTPR Message Disable (R/W)
See Table 35-2.
33:24
Reserved.
Vol. 3C 35-111
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
34
Thread
XD Bit Disable (R/W)
See Table 35-2.
37:35
38
Reserved.
Package
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost
Technology, the turbo mode feature is disabled and the IDA_Enable
feature flag will be clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H:
EAX[1] reports the processor’s support of turbo mode is enabled.
Note: the power-on default value is used by BIOS to detect
hardware support of turbo mode. If power-on default value is 1,
turbo mode is available in the processor. If power-on default value
is 0, turbo mode is not available.
63:39
1A2H
418
MSR_
TEMPERATURE_TARGET
Reserved.
Thread
15:0
Reserved.
23:16
Temperature Target (R)
The minimum temperature at which PROCHOT# will be asserted.
The value is degree C.
1A4H
420
63:24
Reserved.
MSR_MISC_FEATURE_
CONTROL
Miscellaneous Feature Control (R/W)
0
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional
lines of code or data into the L2 cache.
1
Core
L2 Adjacent Cache Line Prefetcher Disable (R/W)
If 1, disables the adjacent cache line prefetcher, which fetches the
cache line that comprises a cache line pair (128 bytes).
2
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
3
Core
DCU IP Prefetcher Disable (R/W)
If 1, disables the L1 data cache IP prefetcher, which uses
sequential load history (based on instruction Pointer of previous
loads) to determine whether to prefetch additional lines.
63:4
1A6H
422
MSR_OFFCORE_RSP_0
1AAH
426
MSR_MISC_PWR_MGMT
35-112 Vol. 3C
Reserved.
Thread
Offcore Response Event Select Register (R/W)
See http://biosbits.org.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
0
Package
EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced Intel
Speedstep Technology request from processor cores; When 1,
disables hardware coordination of Enhanced Intel Speedstep
Technology requests.
1
Thread
Energy/Performance Bias Enable (R/W)
This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h)
visible to software with Ring 0 privileges. This bit’s status (1 or 0)
is also reflected by CPUID.(EAX=06h):ECX[3].
1ACH
428
63:2
Reserved.
MSR_TURBO_POWER_
CURRENT_LIMIT
See http://biosbits.org.
14:0
Package
TDP Limit (R/W)
TDP limit in 1/8 Watt granularity.
15
Package
TDP Limit Override Enable (R/W)
A value = 0 indicates override is not active, and a value = 1
indicates active.
30:16
Package
TDC Limit (R/W)
TDC limit in 1/8 Amp granularity.
31
Package
TDC Limit Override Enable (R/W)
A value = 0 indicates override is not active, and a value = 1
indicates active.
63:32
1ADH
429
MSR_TURBO_RATIO_LIMIT
Reserved.
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32
1C8H
456
MSR_LBR_SELECT
Reserved.
Core
Last Branch Record Filtering Select Register (R/W)
See Section 17.7.2, “Filtering of Last Branch Records.”
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
Vol. 3C 35-113
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
1C9H
Register Name
Scope
Bit Description
Dec
457
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
63:9
Reserved.
MSR_LASTBRANCH_TOS
Thread
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the
most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 680H).
1D9H
473
IA32_DEBUGCTL
Thread
1DDH
477
MSR_LER_FROM_LIP
Thread
Debug Control (R/W)
See Table 35-2.
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
1DEH
478
MSR_LER_TO_LIP
Thread
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled.
1F2H
498
IA32_SMRR_PHYSBASE
Core
See Table 35-2.
1F3H
499
IA32_SMRR_PHYSMASK
Core
See Table 35-2.
1FCH
508
MSR_POWER_CTL
Core
0
1
Power Control Register. See http://biosbits.org.
Reserved.
Package
C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the Minimum
Enhanced Intel SpeedStep Technology operating point when all
execution cores enter MWAIT (C1).
63:2
Reserved.
200H
512
IA32_MTRR_PHYSBASE0
Thread
See Table 35-2.
201H
513
IA32_MTRR_PHYSMASK0
Thread
See Table 35-2.
202H
514
IA32_MTRR_PHYSBASE1
Thread
See Table 35-2.
203H
515
IA32_MTRR_PHYSMASK1
Thread
See Table 35-2.
204H
516
IA32_MTRR_PHYSBASE2
Thread
See Table 35-2.
205H
517
IA32_MTRR_PHYSMASK2
Thread
See Table 35-2.
206H
518
IA32_MTRR_PHYSBASE3
Thread
See Table 35-2.
35-114 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
207H
519
IA32_MTRR_PHYSMASK3
Thread
See Table 35-2.
208H
520
IA32_MTRR_PHYSBASE4
Thread
See Table 35-2.
209H
521
IA32_MTRR_PHYSMASK4
Thread
See Table 35-2.
20AH
522
IA32_MTRR_PHYSBASE5
Thread
See Table 35-2.
20BH
523
IA32_MTRR_PHYSMASK5
Thread
See Table 35-2.
20CH
524
IA32_MTRR_PHYSBASE6
Thread
See Table 35-2.
20DH
525
IA32_MTRR_PHYSMASK6
Thread
See Table 35-2.
20EH
526
IA32_MTRR_PHYSBASE7
Thread
See Table 35-2.
20FH
527
IA32_MTRR_PHYSMASK7
Thread
See Table 35-2.
210H
528
IA32_MTRR_PHYSBASE8
Thread
See Table 35-2.
211H
529
IA32_MTRR_PHYSMASK8
Thread
See Table 35-2.
212H
530
IA32_MTRR_PHYSBASE9
Thread
See Table 35-2.
213H
531
IA32_MTRR_PHYSMASK9
Thread
See Table 35-2.
250H
592
IA32_MTRR_FIX64K_
00000
Thread
See Table 35-2.
258H
600
IA32_MTRR_FIX16K_
80000
Thread
See Table 35-2.
259H
601
IA32_MTRR_FIX16K_
A0000
Thread
See Table 35-2.
268H
616
IA32_MTRR_FIX4K_C0000
Thread
See Table 35-2.
269H
617
IA32_MTRR_FIX4K_C8000
Thread
See Table 35-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Thread
See Table 35-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Thread
See Table 35-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Thread
See Table 35-2.
26DH
621
IA32_MTRR_FIX4K_E8000
Thread
See Table 35-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Thread
See Table 35-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Thread
See Table 35-2.
277H
631
IA32_PAT
Thread
See Table 35-2.
280H
640
IA32_MC0_CTL2
Package
See Table 35-2.
281H
641
IA32_MC1_CTL2
Package
See Table 35-2.
282H
642
IA32_MC2_CTL2
Core
See Table 35-2.
283H
643
IA32_MC3_CTL2
Core
See Table 35-2.
284H
644
IA32_MC4_CTL2
Core
See Table 35-2.
285H
645
IA32_MC5_CTL2
Core
See Table 35-2.
286H
646
IA32_MC6_CTL2
Package
See Table 35-2.
287H
647
IA32_MC7_CTL2
Package
See Table 35-2.
288H
648
IA32_MC8_CTL2
Package
See Table 35-2.
Vol. 3C 35-115
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Dec
2FFH
767
Register Name
IA32_MTRR_DEF_TYPE
Scope
Thread
Bit Description
Default Memory Types (R/W)
See Table 35-2.
309H
777
IA32_FIXED_CTR0
Thread
Fixed-Function Performance Counter Register 0 (R/W)
See Table 35-2.
30AH
778
IA32_FIXED_CTR1
Thread
Fixed-Function Performance Counter Register 1 (R/W)
See Table 35-2.
30BH
779
IA32_FIXED_CTR2
Thread
Fixed-Function Performance Counter Register 2 (R/W)
See Table 35-2.
345H
38DH
837
909
IA32_PERF_CAPABILITIES
Thread
See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”
5:0
LBR Format. See Table 35-2.
6
PEBS Record Format.
7
PEBSSaveArchRegs. See Table 35-2.
11:8
PEBS_REC_FORMAT. See Table 35-2.
12
SMM_FREEZE. See Table 35-2.
63:13
Reserved.
IA32_FIXED_CTR_CTRL
Thread
Fixed-Function-Counter Control Register (R/W)
See Table 35-2.
38EH
910
IA32_PERF_GLOBAL_
STATUS
Thread
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
38EH
910
MSR_PERF_GLOBAL_STATU Thread
S
(RO)
61
UNC_Ovf
Uncore overflowed if 1.
38FH
911
IA32_PERF_GLOBAL_CTRL
Thread
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
390H
912
IA32_PERF_GLOBAL_OVF_
CTRL
Thread
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
390H
912
MSR_PERF_GLOBAL_OVF_
CTRL
Thread
(R/W)
61
CLR_UNC_Ovf
Set 1 to clear UNC_Ovf.
3F1H
1009
35-116 Vol. 3C
MSR_PEBS_ENABLE
Thread
See Section 18.8.1.1, “Processor Event Based Sampling (PEBS).”
0
Enable PEBS on IA32_PMC0. (R/W)
1
Enable PEBS on IA32_PMC1. (R/W)
2
Enable PEBS on IA32_PMC2. (R/W)
3
Enable PEBS on IA32_PMC3. (R/W)
31:4
Reserved.
32
Enable Load Latency on IA32_PMC0. (R/W)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
3F6H
3F8H
Register Name
Scope
Bit Description
Dec
1014
1016
33
Enable Load Latency on IA32_PMC1. (R/W)
34
Enable Load Latency on IA32_PMC2. (R/W)
35
Enable Load Latency on IA32_PMC3. (R/W)
63:36
Reserved.
MSR_PEBS_LD_LAT
Thread
See Section 18.8.1.2, “Load Latency Performance Monitoring
Facility.”
15:0
Minimum threshold latency value of tagged load operation that will
be counted. (R/W)
63:36
Reserved.
MSR_PKG_C3_RESIDENCY
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C3 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C3
states. Count at the same frequency as the TSC.
3F9H
1017
MSR_PKG_C6_RESIDENCY
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C6
states. Count at the same frequency as the TSC.
3FAH
1018
MSR_PKG_C7_RESIDENCY
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C7 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C7
states. Count at the same frequency as the TSC.
3FCH
1020
MSR_CORE_C3_RESIDENCY
Core
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
CORE C3 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C3
states. Count at the same frequency as the TSC.
3FDH
1021
MSR_CORE_C6_RESIDENCY
Core
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
CORE C6 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C6
states. Count at the same frequency as the TSC.
400H
1024
IA32_MC0_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
Vol. 3C 35-117
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Dec
402H
1026
Register Name
IA32_MC0_ADDR
Scope
Package
Bit Description
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC0_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
403H
1027
IA32_MC0_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
404H
1028
IA32_MC1_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC1_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
407H
1031
IA32_MC1_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
408H
1032
IA32_MC2_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC2_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
40BH
1035
IA32_MC2_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
40CH
1036
IA32_MC3_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC3_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
40FH
1039
IA32_MC3_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
410H
1040
IA32_MC4_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC4_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
IA32_MC4_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC3_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
35-118 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
413H
1043
IA32_MC4_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
414H
1044
IA32_MC5_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
415H
1045
IA32_MC5_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
416H
1046
IA32_MC5_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
417H
1047
IA32_MC5_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
418H
1048
IA32_MC6_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
419H
1049
IA32_MC6_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
41AH
1050
IA32_MC6_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
41BH
1051
IA32_MC6_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
41CH
1052
IA32_MC7_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
41DH
1053
IA32_MC7_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
41EH
1054
IA32_MC7_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
41FH
1055
IA32_MC7_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
420H
1056
IA32_MC8_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
421H
1057
IA32_MC8_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
422H
1058
IA32_MC8_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
423H
1059
IA32_MC8_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
480H
1152
IA32_VMX_BASIC
Thread
Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_
CTLS
Thread
Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_
CTLS
Thread
Capability Reporting Register of Primary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
483H
1155
IA32_VMX_EXIT_CTLS
Thread
Capability Reporting Register of VM-exit Controls (R/O)
See Table 35-2.
See Appendix A.4, “VM-Exit Controls.”
484H
1156
IA32_VMX_ENTRY_CTLS
Thread
Capability Reporting Register of VM-entry Controls (R/O)
See Table 35-2.
See Appendix A.5, “VM-Entry Controls.”
485H
1157
IA32_VMX_MISC
Thread
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.6, “Miscellaneous Data.”
Vol. 3C 35-119
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Dec
486H
1158
Register Name
IA32_VMX_CR0_FIXED0
Scope
Thread
Bit Description
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Thread
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Thread
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
489H
1161
IA32_VMX_CR4_FIXED1
Thread
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH
1162
IA32_VMX_VMCS_ENUM
Thread
Capability Reporting Register of VMCS Field Enumeration
(R/O).
See Table 35-2.
See Appendix A.9, “VMCS Enumeration.”
48BH
1163
IA32_VMX_PROCBASED_
CTLS2
Thread
Capability Reporting Register of Secondary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
600H
1536
IA32_DS_AREA
Thread
DS Save Area (R/W)
See Table 35-2.
See Section 18.15.4, “Debug Store (DS) Mechanism.”
680H
1664
MSR_
LASTBRANCH_0_FROM_IP
Thread
Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on the last
branch record stack. The From_IP part of the stack contains
pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.7.1 and record format in Section 17.4.8.1
681H
682H
683H
684H
685H
686H
1665
1666
1667
1668
1669
1670
35-120 Vol. 3C
MSR_
LASTBRANCH_1_FROM_IP
Thread
MSR_
LASTBRANCH_2_FROM_IP
Thread
MSR_
LASTBRANCH_3_FROM_IP
Thread
MSR_
LASTBRANCH_4_FROM_IP
Thread
MSR_
LASTBRANCH_5_FROM_IP
Thread
MSR_
LASTBRANCH_6_FROM_IP
Thread
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Dec
687H
1671
688H
689H
68AH
68BH
68CH
68DH
68EH
68FH
6C0H
6C1H
6C2H
6C3H
6C4H
6C5H
6C6H
6C7H
6C8H
1672
1673
1674
1675
1676
1677
1678
1679
1728
1729
1730
1731
1732
1733
1734
1735
1736
Register Name
Scope
MSR_
LASTBRANCH_7_FROM_IP
Thread
MSR_
LASTBRANCH_8_FROM_IP
Thread
MSR_
LASTBRANCH_9_FROM_IP
Thread
Bit Description
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
MSR_
Thread
LASTBRANCH_10_FROM_IP
Last Branch Record 10 From IP (R/W)
MSR_
Thread
LASTBRANCH_11_FROM_IP
Last Branch Record 11 From IP (R/W)
MSR_
Thread
LASTBRANCH_12_FROM_IP
Last Branch Record 12 From IP (R/W)
MSR_
Thread
LASTBRANCH_13_FROM_IP
Last Branch Record 13 From IP (R/W)
MSR_
Thread
LASTBRANCH_14_FROM_IP
Last Branch Record 14 From IP (R/W)
MSR_
Thread
LASTBRANCH_15_FROM_IP
Last Branch Record 15 From IP (R/W)
MSR_
LASTBRANCH_0_TO_IP
Thread
Last Branch Record 0 To IP (R/W)
MSR_
LASTBRANCH_1_TO_IP
Thread
MSR_
LASTBRANCH_2_TO_IP
Thread
MSR_
LASTBRANCH_3_TO_IP
Thread
MSR_
LASTBRANCH_4_TO_IP
Thread
MSR_
LASTBRANCH_5_TO_IP
Thread
MSR_
LASTBRANCH_6_TO_IP
Thread
MSR_
LASTBRANCH_7_TO_IP
Thread
MSR_
LASTBRANCH_8_TO_IP
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
One of sixteen pairs of last branch record registers on the last
branch record stack. This part of the stack contains pointers to the
destination instruction.
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Vol. 3C 35-121
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Dec
6C9H
1737
6CAH
6CBH
6CCH
6CDH
6CEH
6CFH
1738
1739
1740
1741
1742
1743
Register Name
Scope
MSR_
LASTBRANCH_9_TO_IP
Thread
MSR_
LASTBRANCH_10_TO_IP
Thread
MSR_
LASTBRANCH_11_TO_IP
Thread
MSR_
LASTBRANCH_12_TO_IP
Thread
MSR_
LASTBRANCH_13_TO_IP
Thread
MSR_
LASTBRANCH_14_TO_IP
Thread
MSR_
LASTBRANCH_15_TO_IP
Thread
Bit Description
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
802H
2050
IA32_X2APIC_APICID
Thread
x2APIC ID register (R/O) See x2APIC Specification.
803H
2051
IA32_X2APIC_VERSION
Thread
x2APIC Version register (R/O)
808H
2056
IA32_X2APIC_TPR
Thread
x2APIC Task Priority register (R/W)
80AH
2058
IA32_X2APIC_PPR
Thread
x2APIC Processor Priority register (R/O)
80BH
2059
IA32_X2APIC_EOI
Thread
x2APIC EOI register (W/O)
80DH
2061
IA32_X2APIC_LDR
Thread
x2APIC Logical Destination register (R/O)
80FH
2063
IA32_X2APIC_SIVR
Thread
x2APIC Spurious Interrupt Vector register (R/W)
810H
2064
IA32_X2APIC_ISR0
Thread
x2APIC In-Service register bits [31:0] (R/O)
811H
2065
IA32_X2APIC_ISR1
Thread
x2APIC In-Service register bits [63:32] (R/O)
812H
2066
IA32_X2APIC_ISR2
Thread
x2APIC In-Service register bits [95:64] (R/O)
813H
2067
IA32_X2APIC_ISR3
Thread
x2APIC In-Service register bits [127:96] (R/O)
814H
2068
IA32_X2APIC_ISR4
Thread
x2APIC In-Service register bits [159:128] (R/O)
815H
2069
IA32_X2APIC_ISR5
Thread
x2APIC In-Service register bits [191:160] (R/O)
816H
2070
IA32_X2APIC_ISR6
Thread
x2APIC In-Service register bits [223:192] (R/O)
817H
2071
IA32_X2APIC_ISR7
Thread
x2APIC In-Service register bits [255:224] (R/O)
818H
2072
IA32_X2APIC_TMR0
Thread
x2APIC Trigger Mode register bits [31:0] (R/O)
819H
2073
IA32_X2APIC_TMR1
Thread
x2APIC Trigger Mode register bits [63:32] (R/O)
81AH
2074
IA32_X2APIC_TMR2
Thread
x2APIC Trigger Mode register bits [95:64] (R/O)
81BH
2075
IA32_X2APIC_TMR3
Thread
x2APIC Trigger Mode register bits [127:96] (R/O)
81CH
2076
IA32_X2APIC_TMR4
Thread
x2APIC Trigger Mode register bits [159:128] (R/O)
81DH
2077
IA32_X2APIC_TMR5
Thread
x2APIC Trigger Mode register bits [191:160] (R/O)
81EH
2078
IA32_X2APIC_TMR6
Thread
x2APIC Trigger Mode register bits [223:192] (R/O)
81FH
2079
IA32_X2APIC_TMR7
Thread
x2APIC Trigger Mode register bits [255:224] (R/O)
35-122 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
820H
2080
IA32_X2APIC_IRR0
Thread
x2APIC Interrupt Request register bits [31:0] (R/O)
821H
2081
IA32_X2APIC_IRR1
Thread
x2APIC Interrupt Request register bits [63:32] (R/O)
822H
2082
IA32_X2APIC_IRR2
Thread
x2APIC Interrupt Request register bits [95:64] (R/O)
823H
2083
IA32_X2APIC_IRR3
Thread
x2APIC Interrupt Request register bits [127:96] (R/O)
824H
2084
IA32_X2APIC_IRR4
Thread
x2APIC Interrupt Request register bits [159:128] (R/O)
825H
2085
IA32_X2APIC_IRR5
Thread
x2APIC Interrupt Request register bits [191:160] (R/O)
826H
2086
IA32_X2APIC_IRR6
Thread
x2APIC Interrupt Request register bits [223:192] (R/O)
827H
2087
IA32_X2APIC_IRR7
Thread
x2APIC Interrupt Request register bits [255:224] (R/O)
828H
2088
IA32_X2APIC_ESR
Thread
x2APIC Error Status register (R/W)
82FH
2095
IA32_X2APIC_LVT_CMCI
Thread
x2APIC LVT Corrected Machine Check Interrupt register (R/W)
830H
2096
IA32_X2APIC_ICR
Thread
x2APIC Interrupt Command register (R/W)
832H
2098
IA32_X2APIC_LVT_TIMER
Thread
x2APIC LVT Timer Interrupt register (R/W)
833H
2099
IA32_X2APIC_LVT_THERM
AL
Thread
x2APIC LVT Thermal Sensor Interrupt register (R/W)
834H
2100
IA32_X2APIC_LVT_PMI
Thread
x2APIC LVT Performance Monitor register (R/W)
835H
2101
IA32_X2APIC_LVT_LINT0
Thread
x2APIC LVT LINT0 register (R/W)
836H
2102
IA32_X2APIC_LVT_LINT1
Thread
x2APIC LVT LINT1 register (R/W)
837H
2103
IA32_X2APIC_LVT_ERROR
Thread
x2APIC LVT Error register (R/W)
838H
2104
IA32_X2APIC_INIT_COUNT
Thread
x2APIC Initial Count register (R/W)
839H
2105
IA32_X2APIC_CUR_COUNT
Thread
x2APIC Current Count register (R/O)
83EH
2110
IA32_X2APIC_DIV_CONF
Thread
x2APIC Divide Configuration register (R/W)
83FH
2111
IA32_X2APIC_SELF_IPI
Thread
x2APIC Self IPI register (W/O)
C000_
0080H
IA32_EFER
Thread
Extended Feature Enables
C000_
0081H
IA32_STAR
Thread
C000_
0082H
IA32_LSTAR
Thread
C000_
0084H
IA32_FMASK
Thread
C000_
0100H
IA32_FS_BASE
Thread
C000_
0101H
IA32_GS_BASE
Thread
C000_
0102H
IA32_KERNEL_GS_BASE
See Table 35-2.
System Call Target Address (R/W)
See Table 35-2.
IA-32e Mode System Call Target Address (R/W)
See Table 35-2.
System Call Flag Mask (R/W)
See Table 35-2.
Map of BASE Address of FS (R/W)
See Table 35-2.
Map of BASE Address of GS (R/W)
See Table 35-2.
Thread
Swap Target of BASE Address of GS (R/W) See Table 35-2.
Vol. 3C 35-123
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Hex
Scope
Bit Description
Dec
C000_
0103H
35.6.1
Register Name
IA32_TSC_AUX
Thread
AUXILIARY TSC Signature. (R/W) See Table 35-2 and Section
17.15.2, “IA32_TSC_AUX Register and RDTSCP Support.”
Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series
Intel Xeon Processor 5500 and 3400 series support additional model-specific registers listed in Table 35-14. These
MSRs also apply to Intel Core i7 and i5 processor family CPUID signature with DisplayFamily_DisplayModel of
06_1AH, 06_1EH and 06_1FH, see Table 35-1.
Table 35-14. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series
Register
Address
Hex
Dec
1ADH
429
Register Name
MSR_TURBO_RATIO_LIMIT
Scope
Package
7:0
Bit Description
Actual maximum turbo frequency is multiplied by 133.33MHz. (not
available to model 06_2EH)
Maximum Turbo Ratio Limit 1C (R/O)
Maximum Turbo mode ratio limit with 1 core active.
15:8
Maximum Turbo Ratio Limit 2C (R/O)
Maximum Turbo mode ratio limit with 2cores active.
23:16
Maximum Turbo Ratio Limit 3C (R/O)
Maximum Turbo mode ratio limit with 3cores active.
31:24
Maximum Turbo Ratio Limit 4C (R/O)
Maximum Turbo mode ratio limit with 4 cores active.
63:32
301H
769
MSR_GQ_SNOOP_MESF
Reserved.
Package
0
From M to S (R/W)
1
From E to S (R/W)
2
From S to S (R/W)
3
From F to S (R/W)
4
From M to I (R/W)
5
From E to I (R/W)
6
From S to I (R/W)
7
From F to I (R/W)
63:8
Reserved.
391H
913
MSR_UNCORE_PERF_
GLOBAL_CTRL
Package
See Section 18.8.2.1, “Uncore Performance Monitoring
Management Facility.”
392H
914
MSR_UNCORE_PERF_
GLOBAL_STATUS
Package
See Section 18.8.2.1, “Uncore Performance Monitoring
Management Facility.”
393H
915
MSR_UNCORE_PERF_
GLOBAL_OVF_CTRL
Package
See Section 18.8.2.1, “Uncore Performance Monitoring
Management Facility.”
35-124 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-14. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
394H
916
MSR_UNCORE_FIXED_CTR0 Package
See Section 18.8.2.1, “Uncore Performance Monitoring
Management Facility.”
395H
917
MSR_UNCORE_FIXED_CTR_
CTRL
Package
See Section 18.8.2.1, “Uncore Performance Monitoring
Management Facility.”
396H
918
MSR_UNCORE_ADDR_
OPCODE_MATCH
Package
See Section 18.8.2.3, “Uncore Address/Opcode Match MSR.”
3B0H
960
MSR_UNCORE_PMC0
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3B1H
961
MSR_UNCORE_PMC1
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3B2H
962
MSR_UNCORE_PMC2
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3B3H
963
MSR_UNCORE_PMC3
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3B4H
964
MSR_UNCORE_PMC4
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3B5H
965
MSR_UNCORE_PMC5
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3B6H
966
MSR_UNCORE_PMC6
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3B7H
967
MSR_UNCORE_PMC7
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C0H
944
MSR_UNCORE_
PERFEVTSEL0
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C1H
945
MSR_UNCORE_
PERFEVTSEL1
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C2H
946
MSR_UNCORE_
PERFEVTSEL2
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C3H
947
MSR_UNCORE_
PERFEVTSEL3
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C4H
948
MSR_UNCORE_
PERFEVTSEL4
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C5H
949
MSR_UNCORE_
PERFEVTSEL5
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C6H
950
MSR_UNCORE_
PERFEVTSEL6
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
3C7H
951
MSR_UNCORE_
PERFEVTSEL7
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
35.6.2
Additional MSRs in the Intel® Xeon® Processor 7500 Series
Intel Xeon Processor 7500 series support MSRs listed in Table 35-13 (except MSR address 1ADH) and additional
model-specific registers listed in Table 35-15. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_2EH.
Vol. 3C 35-125
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series
Register
Address
Hex
Dec
1ADH
429
Register Name
MSR_TURBO_RATIO_LIMIT
Scope
Package
Bit Description
Reserved
Attempt to read/write will cause #UD.
289H
649
IA32_MC9_CTL2
Package
See Table 35-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 35-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 35-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 35-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 35-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 35-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 35-2.
290H
656
IA32_MC16_CTL2
Package
See Table 35-2.
291H
657
IA32_MC17_CTL2
Package
See Table 35-2.
292H
658
IA32_MC18_CTL2
Package
See Table 35-2.
293H
659
IA32_MC19_CTL2
Package
See Table 35-2.
294H
660
IA32_MC20_CTL2
Package
See Table 35-2.
295H
661
IA32_MC21_CTL2
Package
See Table 35-2.
394H
816
MSR_W_PMON_FIXED_CTR
Package
Uncore W-box perfmon fixed counter
395H
817
MSR_W_PMON_FIXED_
CTR_CTL
Package
Uncore U-box perfmon fixed counter control MSR
424H
1060
IA32_MC9_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
425H
1061
IA32_MC9_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
426H
1062
IA32_MC9_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
427H
1063
IA32_MC9_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
428H
1064
IA32_MC10_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
429H
1065
IA32_MC10_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
42AH
1066
IA32_MC10_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
42BH
1067
IA32_MC10_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
42CH
1068
IA32_MC11_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
42DH
1069
IA32_MC11_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
42EH
1070
IA32_MC11_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
42FH
1071
IA32_MC11_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
430H
1072
IA32_MC12_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
431H
1073
IA32_MC12_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
432H
1074
IA32_MC12_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
433H
1075
IA32_MC12_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
434H
1076
IA32_MC13_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
435H
1077
IA32_MC13_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
35-126 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
436H
1078
IA32_MC13_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
437H
1079
IA32_MC13_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
438H
1080
IA32_MC14_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
439H
1081
IA32_MC14_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
43AH
1082
IA32_MC14_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
43BH
1083
IA32_MC14_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
43CH
1084
IA32_MC15_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
43DH
1085
IA32_MC15_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
43EH
1086
IA32_MC15_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
43FH
1087
IA32_MC15_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
440H
1088
IA32_MC16_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
441H
1089
IA32_MC16_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
442H
1090
IA32_MC16_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
443H
1091
IA32_MC16_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
444H
1092
IA32_MC17_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
445H
1093
IA32_MC17_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
446H
1094
IA32_MC17_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
447H
1095
IA32_MC17_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
448H
1096
IA32_MC18_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
449H
1097
IA32_MC18_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
44AH
1098
IA32_MC18_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
44BH
1099
IA32_MC18_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
44CH
1100
IA32_MC19_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
44DH
1101
IA32_MC19_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
44EH
1102
IA32_MC19_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
44FH
1103
IA32_MC19_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
450H
1104
IA32_MC20_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
451H
1105
IA32_MC20_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
452H
1106
IA32_MC20_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
453H
1107
IA32_MC20_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
454H
1108
IA32_MC21_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
455H
1109
IA32_MC21_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
456H
1110
IA32_MC21_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
457H
1111
IA32_MC21_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
C00H
3072
MSR_U_PMON_GLOBAL_
CTRL
Package
Uncore U-box perfmon global control MSR.
Vol. 3C 35-127
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
C01H
3073
MSR_U_PMON_GLOBAL_
STATUS
Package
Uncore U-box perfmon global status MSR.
C02H
3074
MSR_U_PMON_GLOBAL_
OVF_CTRL
Package
Uncore U-box perfmon global overflow control MSR.
C10H
3088
MSR_U_PMON_EVNT_SEL
Package
Uncore U-box perfmon event select MSR.
C11H
3089
MSR_U_PMON_CTR
Package
Uncore U-box perfmon counter MSR.
C20H
3104
MSR_B0_PMON_BOX_CTRL
Package
Uncore B-box 0 perfmon local box control MSR.
C21H
3105
MSR_B0_PMON_BOX_
STATUS
Package
Uncore B-box 0 perfmon local box status MSR.
C22H
3106
MSR_B0_PMON_BOX_OVF_
CTRL
Package
Uncore B-box 0 perfmon local box overflow control MSR.
C30H
3120
MSR_B0_PMON_EVNT_
SEL0
Package
Uncore B-box 0 perfmon event select MSR.
C31H
3121
MSR_B0_PMON_CTR0
Package
Uncore B-box 0 perfmon counter MSR.
C32H
3122
MSR_B0_PMON_EVNT_
SEL1
Package
Uncore B-box 0 perfmon event select MSR.
C33H
3123
MSR_B0_PMON_CTR1
Package
Uncore B-box 0 perfmon counter MSR.
C34H
3124
MSR_B0_PMON_EVNT_
SEL2
Package
Uncore B-box 0 perfmon event select MSR.
C35H
3125
MSR_B0_PMON_CTR2
Package
Uncore B-box 0 perfmon counter MSR.
C36H
3126
MSR_B0_PMON_EVNT_
SEL3
Package
Uncore B-box 0 perfmon event select MSR.
C37H
3127
MSR_B0_PMON_CTR3
Package
Uncore B-box 0 perfmon counter MSR.
C40H
3136
MSR_S0_PMON_BOX_CTRL
Package
Uncore S-box 0 perfmon local box control MSR.
C41H
3137
MSR_S0_PMON_BOX_
STATUS
Package
Uncore S-box 0 perfmon local box status MSR.
C42H
3138
MSR_S0_PMON_BOX_OVF_
CTRL
Package
Uncore S-box 0 perfmon local box overflow control MSR.
C50H
3152
MSR_S0_PMON_EVNT_
SEL0
Package
Uncore S-box 0 perfmon event select MSR.
C51H
3153
MSR_S0_PMON_CTR0
Package
Uncore S-box 0 perfmon counter MSR.
C52H
3154
MSR_S0_PMON_EVNT_
SEL1
Package
Uncore S-box 0 perfmon event select MSR.
C53H
3155
MSR_S0_PMON_CTR1
Package
Uncore S-box 0 perfmon counter MSR.
C54H
3156
MSR_S0_PMON_EVNT_
SEL2
Package
Uncore S-box 0 perfmon event select MSR.
C55H
3157
MSR_S0_PMON_CTR2
Package
Uncore S-box 0 perfmon counter MSR.
35-128 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
C56H
3158
MSR_S0_PMON_EVNT_
SEL3
Package
Uncore S-box 0 perfmon event select MSR.
C57H
3159
MSR_S0_PMON_CTR3
Package
Uncore S-box 0 perfmon counter MSR.
C60H
3168
MSR_B1_PMON_BOX_CTRL
Package
Uncore B-box 1 perfmon local box control MSR.
C61H
3169
MSR_B1_PMON_BOX_
STATUS
Package
Uncore B-box 1 perfmon local box status MSR.
C62H
3170
MSR_B1_PMON_BOX_OVF_
CTRL
Package
Uncore B-box 1 perfmon local box overflow control MSR.
C70H
3184
MSR_B1_PMON_EVNT_
SEL0
Package
Uncore B-box 1 perfmon event select MSR.
C71H
3185
MSR_B1_PMON_CTR0
Package
Uncore B-box 1 perfmon counter MSR.
C72H
3186
MSR_B1_PMON_EVNT_
SEL1
Package
Uncore B-box 1 perfmon event select MSR.
C73H
3187
MSR_B1_PMON_CTR1
Package
Uncore B-box 1 perfmon counter MSR.
C74H
3188
MSR_B1_PMON_EVNT_
SEL2
Package
Uncore B-box 1 perfmon event select MSR.
C75H
3189
MSR_B1_PMON_CTR2
Package
Uncore B-box 1 perfmon counter MSR.
C76H
3190
MSR_B1_PMON_EVNT_
SEL3
Package
Uncore B-box 1vperfmon event select MSR.
C77H
3191
MSR_B1_PMON_CTR3
Package
Uncore B-box 1 perfmon counter MSR.
C80H
3120
MSR_W_PMON_BOX_CTRL
Package
Uncore W-box perfmon local box control MSR.
C81H
3121
MSR_W_PMON_BOX_
STATUS
Package
Uncore W-box perfmon local box status MSR.
C82H
3122
MSR_W_PMON_BOX_OVF_
CTRL
Package
Uncore W-box perfmon local box overflow control MSR.
C90H
3136
MSR_W_PMON_EVNT_SEL0 Package
Uncore W-box perfmon event select MSR.
C91H
3137
MSR_W_PMON_CTR0
Uncore W-box perfmon counter MSR.
C92H
3138
MSR_W_PMON_EVNT_SEL1 Package
Uncore W-box perfmon event select MSR.
C93H
3139
MSR_W_PMON_CTR1
Uncore W-box perfmon counter MSR.
C94H
3140
MSR_W_PMON_EVNT_SEL2 Package
Uncore W-box perfmon event select MSR.
C95H
3141
MSR_W_PMON_CTR2
Uncore W-box perfmon counter MSR.
C96H
3142
MSR_W_PMON_EVNT_SEL3 Package
Uncore W-box perfmon event select MSR.
C97H
3143
MSR_W_PMON_CTR3
Uncore W-box perfmon counter MSR.
Package
Package
Package
Package
Vol. 3C 35-129
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
CA0H
3232
MSR_M0_PMON_BOX_CTRL Package
Uncore M-box 0 perfmon local box control MSR.
CA1H
3233
MSR_M0_PMON_BOX_
STATUS
Package
Uncore M-box 0 perfmon local box status MSR.
CA2H
3234
MSR_M0_PMON_BOX_
OVF_CTRL
Package
Uncore M-box 0 perfmon local box overflow control MSR.
CA4H
3236
MSR_M0_PMON_
TIMESTAMP
Package
Uncore M-box 0 perfmon time stamp unit select MSR.
CA5H
3237
MSR_M0_PMON_DSP
Package
Uncore M-box 0 perfmon DSP unit select MSR.
CA6H
3238
MSR_M0_PMON_ISS
Package
Uncore M-box 0 perfmon ISS unit select MSR.
CA7H
3239
MSR_M0_PMON_MAP
Package
Uncore M-box 0 perfmon MAP unit select MSR.
CA8H
3240
MSR_M0_PMON_MSC_THR
Package
Uncore M-box 0 perfmon MIC THR select MSR.
CA9H
3241
MSR_M0_PMON_PGT
Package
Uncore M-box 0 perfmon PGT unit select MSR.
CAAH
3242
MSR_M0_PMON_PLD
Package
Uncore M-box 0 perfmon PLD unit select MSR.
CABH
3243
MSR_M0_PMON_ZDP
Package
Uncore M-box 0 perfmon ZDP unit select MSR.
CB0H
3248
MSR_M0_PMON_EVNT_
SEL0
Package
Uncore M-box 0 perfmon event select MSR.
CB1H
3249
MSR_M0_PMON_CTR0
Package
Uncore M-box 0 perfmon counter MSR.
CB2H
3250
MSR_M0_PMON_EVNT_
SEL1
Package
Uncore M-box 0 perfmon event select MSR.
CB3H
3251
MSR_M0_PMON_CTR1
Package
Uncore M-box 0 perfmon counter MSR.
CB4H
3252
MSR_M0_PMON_EVNT_
SEL2
Package
Uncore M-box 0 perfmon event select MSR.
CB5H
3253
MSR_M0_PMON_CTR2
Package
Uncore M-box 0 perfmon counter MSR.
CB6H
3254
MSR_M0_PMON_EVNT_
SEL3
Package
Uncore M-box 0 perfmon event select MSR.
CB7H
3255
MSR_M0_PMON_CTR3
Package
Uncore M-box 0 perfmon counter MSR.
CB8H
3256
MSR_M0_PMON_EVNT_
SEL4
Package
Uncore M-box 0 perfmon event select MSR.
CB9H
3257
MSR_M0_PMON_CTR4
Package
Uncore M-box 0 perfmon counter MSR.
CBAH
3258
MSR_M0_PMON_EVNT_
SEL5
Package
Uncore M-box 0 perfmon event select MSR.
CBBH
3259
MSR_M0_PMON_CTR5
Package
Uncore M-box 0 perfmon counter MSR.
CC0H
3264
MSR_S1_PMON_BOX_CTRL
Package
Uncore S-box 1 perfmon local box control MSR.
CC1H
3265
MSR_S1_PMON_BOX_
STATUS
Package
Uncore S-box 1 perfmon local box status MSR.
CC2H
3266
MSR_S1_PMON_BOX_OVF_
CTRL
Package
Uncore S-box 1 perfmon local box overflow control MSR.
35-130 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
CD0H
3280
MSR_S1_PMON_EVNT_
SEL0
Package
Uncore S-box 1 perfmon event select MSR.
CD1H
3281
MSR_S1_PMON_CTR0
Package
Uncore S-box 1 perfmon counter MSR.
CD2H
3282
MSR_S1_PMON_EVNT_
SEL1
Package
Uncore S-box 1 perfmon event select MSR.
CD3H
3283
MSR_S1_PMON_CTR1
Package
Uncore S-box 1 perfmon counter MSR.
CD4H
3284
MSR_S1_PMON_EVNT_
SEL2
Package
Uncore S-box 1 perfmon event select MSR.
CD5H
3285
MSR_S1_PMON_CTR2
Package
Uncore S-box 1 perfmon counter MSR.
CD6H
3286
MSR_S1_PMON_EVNT_
SEL3
Package
Uncore S-box 1 perfmon event select MSR.
CD7H
3287
MSR_S1_PMON_CTR3
Package
Uncore S-box 1 perfmon counter MSR.
CE0H
3296
MSR_M1_PMON_BOX_CTRL Package
Uncore M-box 1 perfmon local box control MSR.
CE1H
3297
MSR_M1_PMON_BOX_
STATUS
Package
Uncore M-box 1 perfmon local box status MSR.
CE2H
3298
MSR_M1_PMON_BOX_
OVF_CTRL
Package
Uncore M-box 1 perfmon local box overflow control MSR.
CE4H
3300
MSR_M1_PMON_
TIMESTAMP
Package
Uncore M-box 1 perfmon time stamp unit select MSR.
CE5H
3301
MSR_M1_PMON_DSP
Package
Uncore M-box 1 perfmon DSP unit select MSR.
CE6H
3302
MSR_M1_PMON_ISS
Package
Uncore M-box 1 perfmon ISS unit select MSR.
CE7H
3303
MSR_M1_PMON_MAP
Package
Uncore M-box 1 perfmon MAP unit select MSR.
CE8H
3304
MSR_M1_PMON_MSC_THR
Package
Uncore M-box 1 perfmon MIC THR select MSR.
CE9H
3305
MSR_M1_PMON_PGT
Package
Uncore M-box 1 perfmon PGT unit select MSR.
CEAH
3306
MSR_M1_PMON_PLD
Package
Uncore M-box 1 perfmon PLD unit select MSR.
CEBH
3307
MSR_M1_PMON_ZDP
Package
Uncore M-box 1 perfmon ZDP unit select MSR.
CF0H
3312
MSR_M1_PMON_EVNT_
SEL0
Package
Uncore M-box 1 perfmon event select MSR.
CF1H
3313
MSR_M1_PMON_CTR0
Package
Uncore M-box 1 perfmon counter MSR.
CF2H
3314
MSR_M1_PMON_EVNT_
SEL1
Package
Uncore M-box 1 perfmon event select MSR.
CF3H
3315
MSR_M1_PMON_CTR1
Package
Uncore M-box 1 perfmon counter MSR.
CF4H
3316
MSR_M1_PMON_EVNT_
SEL2
Package
Uncore M-box 1 perfmon event select MSR.
CF5H
3317
MSR_M1_PMON_CTR2
Package
Uncore M-box 1 perfmon counter MSR.
CF6H
3318
MSR_M1_PMON_EVNT_
SEL3
Package
Uncore M-box 1 perfmon event select MSR.
CF7H
3319
MSR_M1_PMON_CTR3
Package
Uncore M-box 1 perfmon counter MSR.
Vol. 3C 35-131
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
CF8H
3320
MSR_M1_PMON_EVNT_
SEL4
Package
Uncore M-box 1 perfmon event select MSR.
CF9H
3321
MSR_M1_PMON_CTR4
Package
Uncore M-box 1 perfmon counter MSR.
CFAH
3322
MSR_M1_PMON_EVNT_
SEL5
Package
Uncore M-box 1 perfmon event select MSR.
CFBH
3323
MSR_M1_PMON_CTR5
Package
Uncore M-box 1 perfmon counter MSR.
D00H
3328
MSR_C0_PMON_BOX_CTRL
Package
Uncore C-box 0 perfmon local box control MSR.
D01H
3329
MSR_C0_PMON_BOX_
STATUS
Package
Uncore C-box 0 perfmon local box status MSR.
D02H
3330
MSR_C0_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 0 perfmon local box overflow control MSR.
D10H
3344
MSR_C0_PMON_EVNT_
SEL0
Package
Uncore C-box 0 perfmon event select MSR.
D11H
3345
MSR_C0_PMON_CTR0
Package
Uncore C-box 0 perfmon counter MSR.
D12H
3346
MSR_C0_PMON_EVNT_
SEL1
Package
Uncore C-box 0 perfmon event select MSR.
D13H
3347
MSR_C0_PMON_CTR1
Package
Uncore C-box 0 perfmon counter MSR.
D14H
3348
MSR_C0_PMON_EVNT_
SEL2
Package
Uncore C-box 0 perfmon event select MSR.
D15H
3349
MSR_C0_PMON_CTR2
Package
Uncore C-box 0 perfmon counter MSR.
D16H
3350
MSR_C0_PMON_EVNT_
SEL3
Package
Uncore C-box 0 perfmon event select MSR.
D17H
3351
MSR_C0_PMON_CTR3
Package
Uncore C-box 0 perfmon counter MSR.
D18H
3352
MSR_C0_PMON_EVNT_
SEL4
Package
Uncore C-box 0 perfmon event select MSR.
D19H
3353
MSR_C0_PMON_CTR4
Package
Uncore C-box 0 perfmon counter MSR.
D1AH
3354
MSR_C0_PMON_EVNT_
SEL5
Package
Uncore C-box 0 perfmon event select MSR.
D1BH
3355
MSR_C0_PMON_CTR5
Package
Uncore C-box 0 perfmon counter MSR.
D20H
3360
MSR_C4_PMON_BOX_CTRL
Package
Uncore C-box 4 perfmon local box control MSR.
D21H
3361
MSR_C4_PMON_BOX_
STATUS
Package
Uncore C-box 4 perfmon local box status MSR.
D22H
3362
MSR_C4_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 4 perfmon local box overflow control MSR.
D30H
3376
MSR_C4_PMON_EVNT_
SEL0
Package
Uncore C-box 4 perfmon event select MSR.
D31H
3377
MSR_C4_PMON_CTR0
Package
Uncore C-box 4 perfmon counter MSR.
35-132 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
D32H
3378
MSR_C4_PMON_EVNT_
SEL1
Package
Uncore C-box 4 perfmon event select MSR.
D33H
3379
MSR_C4_PMON_CTR1
Package
Uncore C-box 4 perfmon counter MSR.
D34H
3380
MSR_C4_PMON_EVNT_
SEL2
Package
Uncore C-box 4 perfmon event select MSR.
D35H
3381
MSR_C4_PMON_CTR2
Package
Uncore C-box 4 perfmon counter MSR.
D36H
3382
MSR_C4_PMON_EVNT_
SEL3
Package
Uncore C-box 4 perfmon event select MSR.
D37H
3383
MSR_C4_PMON_CTR3
Package
Uncore C-box 4 perfmon counter MSR.
D38H
3384
MSR_C4_PMON_EVNT_
SEL4
Package
Uncore C-box 4 perfmon event select MSR.
D39H
3385
MSR_C4_PMON_CTR4
Package
Uncore C-box 4 perfmon counter MSR.
D3AH
3386
MSR_C4_PMON_EVNT_
SEL5
Package
Uncore C-box 4 perfmon event select MSR.
D3BH
3387
MSR_C4_PMON_CTR5
Package
Uncore C-box 4 perfmon counter MSR.
D40H
3392
MSR_C2_PMON_BOX_CTRL
Package
Uncore C-box 2 perfmon local box control MSR.
D41H
3393
MSR_C2_PMON_BOX_
STATUS
Package
Uncore C-box 2 perfmon local box status MSR.
D42H
3394
MSR_C2_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 2 perfmon local box overflow control MSR.
D50H
3408
MSR_C2_PMON_EVNT_
SEL0
Package
Uncore C-box 2 perfmon event select MSR.
D51H
3409
MSR_C2_PMON_CTR0
Package
Uncore C-box 2 perfmon counter MSR.
D52H
3410
MSR_C2_PMON_EVNT_
SEL1
Package
Uncore C-box 2 perfmon event select MSR.
D53H
3411
MSR_C2_PMON_CTR1
Package
Uncore C-box 2 perfmon counter MSR.
D54H
3412
MSR_C2_PMON_EVNT_
SEL2
Package
Uncore C-box 2 perfmon event select MSR.
D55H
3413
MSR_C2_PMON_CTR2
Package
Uncore C-box 2 perfmon counter MSR.
D56H
3414
MSR_C2_PMON_EVNT_
SEL3
Package
Uncore C-box 2 perfmon event select MSR.
D57H
3415
MSR_C2_PMON_CTR3
Package
Uncore C-box 2 perfmon counter MSR.
D58H
3416
MSR_C2_PMON_EVNT_
SEL4
Package
Uncore C-box 2 perfmon event select MSR.
D59H
3417
MSR_C2_PMON_CTR4
Package
Uncore C-box 2 perfmon counter MSR.
D5AH
3418
MSR_C2_PMON_EVNT_
SEL5
Package
Uncore C-box 2 perfmon event select MSR.
D5BH
3419
MSR_C2_PMON_CTR5
Package
Uncore C-box 2 perfmon counter MSR.
Vol. 3C 35-133
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
D60H
3424
MSR_C6_PMON_BOX_CTRL
Package
Uncore C-box 6 perfmon local box control MSR.
D61H
3425
MSR_C6_PMON_BOX_
STATUS
Package
Uncore C-box 6 perfmon local box status MSR.
D62H
3426
MSR_C6_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 6 perfmon local box overflow control MSR.
D70H
3440
MSR_C6_PMON_EVNT_
SEL0
Package
Uncore C-box 6 perfmon event select MSR.
D71H
3441
MSR_C6_PMON_CTR0
Package
Uncore C-box 6 perfmon counter MSR.
D72H
3442
MSR_C6_PMON_EVNT_
SEL1
Package
Uncore C-box 6 perfmon event select MSR.
D73H
3443
MSR_C6_PMON_CTR1
Package
Uncore C-box 6 perfmon counter MSR.
D74H
3444
MSR_C6_PMON_EVNT_
SEL2
Package
Uncore C-box 6 perfmon event select MSR.
D75H
3445
MSR_C6_PMON_CTR2
Package
Uncore C-box 6 perfmon counter MSR.
D76H
3446
MSR_C6_PMON_EVNT_
SEL3
Package
Uncore C-box 6 perfmon event select MSR.
D77H
3447
MSR_C6_PMON_CTR3
Package
Uncore C-box 6 perfmon counter MSR.
D78H
3448
MSR_C6_PMON_EVNT_
SEL4
Package
Uncore C-box 6 perfmon event select MSR.
D79H
3449
MSR_C6_PMON_CTR4
Package
Uncore C-box 6 perfmon counter MSR.
D7AH
3450
MSR_C6_PMON_EVNT_
SEL5
Package
Uncore C-box 6 perfmon event select MSR.
D7BH
3451
MSR_C6_PMON_CTR5
Package
Uncore C-box 6 perfmon counter MSR.
D80H
3456
MSR_C1_PMON_BOX_CTRL
Package
Uncore C-box 1 perfmon local box control MSR.
D81H
3457
MSR_C1_PMON_BOX_
STATUS
Package
Uncore C-box 1 perfmon local box status MSR.
D82H
3458
MSR_C1_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 1 perfmon local box overflow control MSR.
D90H
3472
MSR_C1_PMON_EVNT_
SEL0
Package
Uncore C-box 1 perfmon event select MSR.
D91H
3473
MSR_C1_PMON_CTR0
Package
Uncore C-box 1 perfmon counter MSR.
D92H
3474
MSR_C1_PMON_EVNT_
SEL1
Package
Uncore C-box 1 perfmon event select MSR.
D93H
3475
MSR_C1_PMON_CTR1
Package
Uncore C-box 1 perfmon counter MSR.
D94H
3476
MSR_C1_PMON_EVNT_
SEL2
Package
Uncore C-box 1 perfmon event select MSR.
D95H
3477
MSR_C1_PMON_CTR2
Package
Uncore C-box 1 perfmon counter MSR.
35-134 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
D96H
3478
MSR_C1_PMON_EVNT_
SEL3
Package
Uncore C-box 1 perfmon event select MSR.
D97H
3479
MSR_C1_PMON_CTR3
Package
Uncore C-box 1 perfmon counter MSR.
D98H
3480
MSR_C1_PMON_EVNT_
SEL4
Package
Uncore C-box 1 perfmon event select MSR.
D99H
3481
MSR_C1_PMON_CTR4
Package
Uncore C-box 1 perfmon counter MSR.
D9AH
3482
MSR_C1_PMON_EVNT_
SEL5
Package
Uncore C-box 1 perfmon event select MSR.
D9BH
3483
MSR_C1_PMON_CTR5
Package
Uncore C-box 1 perfmon counter MSR.
DA0H
3488
MSR_C5_PMON_BOX_CTRL
Package
Uncore C-box 5 perfmon local box control MSR.
DA1H
3489
MSR_C5_PMON_BOX_
STATUS
Package
Uncore C-box 5 perfmon local box status MSR.
DA2H
3490
MSR_C5_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 5 perfmon local box overflow control MSR.
DB0H
3504
MSR_C5_PMON_EVNT_
SEL0
Package
Uncore C-box 5 perfmon event select MSR.
DB1H
3505
MSR_C5_PMON_CTR0
Package
Uncore C-box 5 perfmon counter MSR.
DB2H
3506
MSR_C5_PMON_EVNT_
SEL1
Package
Uncore C-box 5 perfmon event select MSR.
DB3H
3507
MSR_C5_PMON_CTR1
Package
Uncore C-box 5 perfmon counter MSR.
DB4H
3508
MSR_C5_PMON_EVNT_
SEL2
Package
Uncore C-box 5 perfmon event select MSR.
DB5H
3509
MSR_C5_PMON_CTR2
Package
Uncore C-box 5 perfmon counter MSR.
DB6H
3510
MSR_C5_PMON_EVNT_
SEL3
Package
Uncore C-box 5 perfmon event select MSR.
DB7H
3511
MSR_C5_PMON_CTR3
Package
Uncore C-box 5 perfmon counter MSR.
DB8H
3512
MSR_C5_PMON_EVNT_
SEL4
Package
Uncore C-box 5 perfmon event select MSR.
DB9H
3513
MSR_C5_PMON_CTR4
Package
Uncore C-box 5 perfmon counter MSR.
DBAH
3514
MSR_C5_PMON_EVNT_
SEL5
Package
Uncore C-box 5 perfmon event select MSR.
DBBH
3515
MSR_C5_PMON_CTR5
Package
Uncore C-box 5 perfmon counter MSR.
DC0H
3520
MSR_C3_PMON_BOX_CTRL
Package
Uncore C-box 3 perfmon local box control MSR.
DC1H
3521
MSR_C3_PMON_BOX_
STATUS
Package
Uncore C-box 3 perfmon local box status MSR.
DC2H
3522
MSR_C3_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 3 perfmon local box overflow control MSR.
Vol. 3C 35-135
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
DD0H
3536
MSR_C3_PMON_EVNT_
SEL0
Package
Uncore C-box 3 perfmon event select MSR.
DD1H
3537
MSR_C3_PMON_CTR0
Package
Uncore C-box 3 perfmon counter MSR.
DD2H
3538
MSR_C3_PMON_EVNT_
SEL1
Package
Uncore C-box 3 perfmon event select MSR.
DD3H
3539
MSR_C3_PMON_CTR1
Package
Uncore C-box 3 perfmon counter MSR.
DD4H
3540
MSR_C3_PMON_EVNT_
SEL2
Package
Uncore C-box 3 perfmon event select MSR.
DD5H
3541
MSR_C3_PMON_CTR2
Package
Uncore C-box 3 perfmon counter MSR.
DD6H
3542
MSR_C3_PMON_EVNT_SEL
3
Package
Uncore C-box 3 perfmon event select MSR.
DD7H
3543
MSR_C3_PMON_CTR3
Package
Uncore C-box 3 perfmon counter MSR.
DD8H
3544
MSR_C3_PMON_EVNT_
SEL4
Package
Uncore C-box 3 perfmon event select MSR.
DD9H
3545
MSR_C3_PMON_CTR4
Package
Uncore C-box 3 perfmon counter MSR.
DDAH
3546
MSR_C3_PMON_EVNT_
SEL5
Package
Uncore C-box 3 perfmon event select MSR.
DDBH
3547
MSR_C3_PMON_CTR5
Package
Uncore C-box 3 perfmon counter MSR.
DE0H
3552
MSR_C7_PMON_BOX_CTRL
Package
Uncore C-box 7 perfmon local box control MSR.
DE1H
3553
MSR_C7_PMON_BOX_
STATUS
Package
Uncore C-box 7 perfmon local box status MSR.
DE2H
3554
MSR_C7_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 7 perfmon local box overflow control MSR.
DF0H
3568
MSR_C7_PMON_EVNT_
SEL0
Package
Uncore C-box 7 perfmon event select MSR.
DF1H
3569
MSR_C7_PMON_CTR0
Package
Uncore C-box 7 perfmon counter MSR.
DF2H
3570
MSR_C7_PMON_EVNT_
SEL1
Package
Uncore C-box 7 perfmon event select MSR.
DF3H
3571
MSR_C7_PMON_CTR1
Package
Uncore C-box 7 perfmon counter MSR.
DF4H
3572
MSR_C7_PMON_EVNT_
SEL2
Package
Uncore C-box 7 perfmon event select MSR.
DF5H
3573
MSR_C7_PMON_CTR2
Package
Uncore C-box 7 perfmon counter MSR.
DF6H
3574
MSR_C7_PMON_EVNT_
SEL3
Package
Uncore C-box 7 perfmon event select MSR.
DF7H
3575
MSR_C7_PMON_CTR3
Package
Uncore C-box 7 perfmon counter MSR.
DF8H
3576
MSR_C7_PMON_EVNT_
SEL4
Package
Uncore C-box 7 perfmon event select MSR.
DF9H
3577
MSR_C7_PMON_CTR4
Package
Uncore C-box 7 perfmon counter MSR.
35-136 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
DFAH
3578
MSR_C7_PMON_EVNT_
SEL5
Package
Uncore C-box 7 perfmon event select MSR.
DFBH
3579
MSR_C7_PMON_CTR5
Package
Uncore C-box 7 perfmon counter MSR.
E00H
3584
MSR_R0_PMON_BOX_CTRL
Package
Uncore R-box 0 perfmon local box control MSR.
E01H
3585
MSR_R0_PMON_BOX_
STATUS
Package
Uncore R-box 0 perfmon local box status MSR.
E02H
3586
MSR_R0_PMON_BOX_OVF_
CTRL
Package
Uncore R-box 0 perfmon local box overflow control MSR.
E04H
3588
MSR_R0_PMON_IPERF0_P0 Package
Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
E05H
3589
MSR_R0_PMON_IPERF0_P1 Package
Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
E06H
3590
MSR_R0_PMON_IPERF0_P2 Package
Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
E07H
3591
MSR_R0_PMON_IPERF0_P3 Package
Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
E08H
3592
MSR_R0_PMON_IPERF0_P4 Package
Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
E09H
3593
MSR_R0_PMON_IPERF0_P5 Package
Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
E0AH
3594
MSR_R0_PMON_IPERF0_P6 Package
Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
E0BH
3595
MSR_R0_PMON_IPERF0_P7 Package
Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
E0CH
3596
MSR_R0_PMON_QLX_P0
Package
Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
E0DH
3597
MSR_R0_PMON_QLX_P1
Package
Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
E0EH
3598
MSR_R0_PMON_QLX_P2
Package
Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
E0FH
3599
MSR_R0_PMON_QLX_P3
Package
Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
E10H
3600
MSR_R0_PMON_EVNT_
SEL0
Package
Uncore R-box 0 perfmon event select MSR.
E11H
3601
MSR_R0_PMON_CTR0
Package
Uncore R-box 0 perfmon counter MSR.
E12H
3602
MSR_R0_PMON_EVNT_
SEL1
Package
Uncore R-box 0 perfmon event select MSR.
E13H
3603
MSR_R0_PMON_CTR1
Package
Uncore R-box 0 perfmon counter MSR.
E14H
3604
MSR_R0_PMON_EVNT_
SEL2
Package
Uncore R-box 0 perfmon event select MSR.
E15H
3605
MSR_R0_PMON_CTR2
Package
Uncore R-box 0 perfmon counter MSR.
E16H
3606
MSR_R0_PMON_EVNT_
SEL3
Package
Uncore R-box 0 perfmon event select MSR.
E17H
3607
MSR_R0_PMON_CTR3
Package
Uncore R-box 0 perfmon counter MSR.
E18H
3608
MSR_R0_PMON_EVNT_
SEL4
Package
Uncore R-box 0 perfmon event select MSR.
E19H
3609
MSR_R0_PMON_CTR4
Package
Uncore R-box 0 perfmon counter MSR.
E1AH
3610
MSR_R0_PMON_EVNT_
SEL5
Package
Uncore R-box 0 perfmon event select MSR.
E1BH
3611
MSR_R0_PMON_CTR5
Package
Uncore R-box 0 perfmon counter MSR.
Vol. 3C 35-137
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
E1CH
3612
MSR_R0_PMON_EVNT_
SEL6
Package
Uncore R-box 0 perfmon event select MSR.
E1DH
3613
MSR_R0_PMON_CTR6
Package
Uncore R-box 0 perfmon counter MSR.
E1EH
3614
MSR_R0_PMON_EVNT_
SEL7
Package
Uncore R-box 0 perfmon event select MSR.
E1FH
3615
MSR_R0_PMON_CTR7
Package
Uncore R-box 0 perfmon counter MSR.
E20H
3616
MSR_R1_PMON_BOX_CTRL
Package
Uncore R-box 1 perfmon local box control MSR.
E21H
3617
MSR_R1_PMON_BOX_
STATUS
Package
Uncore R-box 1 perfmon local box status MSR.
E22H
3618
MSR_R1_PMON_BOX_OVF_
CTRL
Package
Uncore R-box 1 perfmon local box overflow control MSR.
E24H
3620
MSR_R1_PMON_IPERF1_P8 Package
Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
E25H
3621
MSR_R1_PMON_IPERF1_P9 Package
Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
E26H
3622
MSR_R1_PMON_IPERF1_
P10
Package
Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
E27H
3623
MSR_R1_PMON_IPERF1_
P11
Package
Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
E28H
3624
MSR_R1_PMON_IPERF1_
P12
Package
Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
E29H
3625
MSR_R1_PMON_IPERF1_
P13
Package
Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
E2AH
3626
MSR_R1_PMON_IPERF1_
P14
Package
Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
E2BH
3627
MSR_R1_PMON_IPERF1_
P15
Package
Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
E2CH
3628
MSR_R1_PMON_QLX_P4
Package
Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
E2DH
3629
MSR_R1_PMON_QLX_P5
Package
Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
E2EH
3630
MSR_R1_PMON_QLX_P6
Package
Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
E2FH
3631
MSR_R1_PMON_QLX_P7
Package
Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
E30H
3632
MSR_R1_PMON_EVNT_
SEL8
Package
Uncore R-box 1 perfmon event select MSR.
E31H
3633
MSR_R1_PMON_CTR8
Package
Uncore R-box 1 perfmon counter MSR.
E32H
3634
MSR_R1_PMON_EVNT_
SEL9
Package
Uncore R-box 1 perfmon event select MSR.
E33H
3635
MSR_R1_PMON_CTR9
Package
Uncore R-box 1 perfmon counter MSR.
E34H
3636
MSR_R1_PMON_EVNT_
SEL10
Package
Uncore R-box 1 perfmon event select MSR.
E35H
3637
MSR_R1_PMON_CTR10
Package
Uncore R-box 1 perfmon counter MSR.
E36H
3638
MSR_R1_PMON_EVNT_
SEL11
Package
Uncore R-box 1 perfmon event select MSR.
35-138 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-15. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
E37H
3639
MSR_R1_PMON_CTR11
Package
Uncore R-box 1 perfmon counter MSR.
E38H
3640
MSR_R1_PMON_EVNT_
SEL12
Package
Uncore R-box 1 perfmon event select MSR.
E39H
3641
MSR_R1_PMON_CTR12
Package
Uncore R-box 1 perfmon counter MSR.
E3AH
3642
MSR_R1_PMON_EVNT_
SEL13
Package
Uncore R-box 1 perfmon event select MSR.
E3BH
3643
MSR_R1_PMON_CTR13
Package
Uncore R-box 1perfmon counter MSR.
E3CH
3644
MSR_R1_PMON_EVNT_
SEL14
Package
Uncore R-box 1 perfmon event select MSR.
E3DH
3645
MSR_R1_PMON_CTR14
Package
Uncore R-box 1 perfmon counter MSR.
E3EH
3646
MSR_R1_PMON_EVNT_
SEL15
Package
Uncore R-box 1 perfmon event select MSR.
E3FH
3647
MSR_R1_PMON_CTR15
Package
Uncore R-box 1 perfmon counter MSR.
E45H
3653
MSR_B0_PMON_MATCH
Package
Uncore B-box 0 perfmon local box match MSR.
E46H
3654
MSR_B0_PMON_MASK
Package
Uncore B-box 0 perfmon local box mask MSR.
E49H
3657
MSR_S0_PMON_MATCH
Package
Uncore S-box 0 perfmon local box match MSR.
E4AH
3658
MSR_S0_PMON_MASK
Package
Uncore S-box 0 perfmon local box mask MSR.
E4DH
3661
MSR_B1_PMON_MATCH
Package
Uncore B-box 1 perfmon local box match MSR.
E4EH
3662
MSR_B1_PMON_MASK
Package
Uncore B-box 1 perfmon local box mask MSR.
E54H
3668
MSR_M0_PMON_MM_
CONFIG
Package
Uncore M-box 0 perfmon local box address match/mask config MSR.
E55H
3669
MSR_M0_PMON_ADDR_
MATCH
Package
Uncore M-box 0 perfmon local box address match MSR.
E56H
3670
MSR_M0_PMON_ADDR_
MASK
Package
Uncore M-box 0 perfmon local box address mask MSR.
E59H
3673
MSR_S1_PMON_MATCH
Package
Uncore S-box 1 perfmon local box match MSR.
E5AH
3674
MSR_S1_PMON_MASK
Package
Uncore S-box 1 perfmon local box mask MSR.
E5CH
3676
MSR_M1_PMON_MM_
CONFIG
Package
Uncore M-box 1 perfmon local box address match/mask config MSR.
E5DH
3677
MSR_M1_PMON_ADDR_
MATCH
Package
Uncore M-box 1 perfmon local box address match MSR.
E5EH
3678
MSR_M1_PMON_ADDR_
MASK
Package
Uncore M-box 1 perfmon local box address mask MSR.
3B5H
965
MSR_UNCORE_PMC5
Package
See Section 18.8.2.2, “Uncore Performance Event Configuration
Facility.”
Vol. 3C 35-139
MODEL-SPECIFIC REGISTERS (MSRS)
35.7
MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES (BASED ON INTEL®
MICROARCHITECTURE CODE NAME WESTMERE)
Intel® Xeon® Processor 5600 Series (based on Intel® microarchitecture code name Westmere) supports the MSR
interfaces listed in Table 35-13, Table 35-14, plus additional MSR listed in Table 35-16. These MSRs apply to Intel
Core i7, i5 and i3 processor family with CPUID signature DisplayFamily_DisplayModel of 06_25H and 06_2CH, see
Table 35-1.
Table 35-16. Additional MSRs Supported by Intel Processors
(Based on Intel® Microarchitecture Code Name Westmere)
Register
Address
Hex
Dec
13CH
52
Register Name
MSR_FEATURE_CONFIG
Scope
Core
Bit Description
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle
unsuccessful read of this MSR.
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instruction can be mis-configured
if a privileged agent unintentionally writes 11b.
63:2
Reserved.
1A7H
423
MSR_OFFCORE_RSP_1
Thread
Offcore Response Event Select Register (R/W)
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
63:48
1B0H
432
35-140 Vol. 3C
IA32_ENERGY_PERF_BIAS
Reserved.
Package
See Table 35-2.
MODEL-SPECIFIC REGISTERS (MSRS)
35.8
MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY (BASED ON INTEL®
MICROARCHITECTURE CODE NAME WESTMERE)
Intel® Xeon® Processor E7 Family (based on Intel® microarchitecture code name Westmere) supports the MSR
interfaces listed in Table 35-13 (except MSR address 1ADH), Table 35-14, plus additional MSR listed in Table 35-17.
These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_2FH.
Table 35-17. Additional MSRs Supported by Intel® Xeon® Processor E7 Family
Register
Address
Hex
Dec
13CH
52
Register Name
MSR_FEATURE_CONFIG
Scope
Core
Bit Description
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle
unsuccessful read of this MSR.
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instruction can be mis-configured
if a privileged agent unintentionally writes 11b.
63:2
Reserved.
1A7H
423
MSR_OFFCORE_RSP_1
Thread
Offcore Response Event Select Register (R/W)
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Reserved
1B0H
432
IA32_ENERGY_PERF_BIAS
Package
See Table 35-2.
F40H
3904
MSR_C8_PMON_BOX_CTRL
Package
Uncore C-box 8 perfmon local box control MSR.
F41H
3905
MSR_C8_PMON_BOX_
STATUS
Package
Uncore C-box 8 perfmon local box status MSR.
F42H
3906
MSR_C8_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 8 perfmon local box overflow control MSR.
F50H
3920
MSR_C8_PMON_EVNT_
SEL0
Package
Uncore C-box 8 perfmon event select MSR.
F51H
3921
MSR_C8_PMON_CTR0
Package
Uncore C-box 8 perfmon counter MSR.
F52H
3922
MSR_C8_PMON_EVNT_
SEL1
Package
Uncore C-box 8 perfmon event select MSR.
Attempt to read/write will cause #UD.
F53H
3923
MSR_C8_PMON_CTR1
Package
Uncore C-box 8 perfmon counter MSR.
F54H
3924
MSR_C8_PMON_EVNT_
SEL2
Package
Uncore C-box 8 perfmon event select MSR.
F55H
3925
MSR_C8_PMON_CTR2
Package
Uncore C-box 8 perfmon counter MSR.
F56H
3926
MSR_C8_PMON_EVNT_
SEL3
Package
Uncore C-box 8 perfmon event select MSR.
F57H
3927
MSR_C8_PMON_CTR3
Package
Uncore C-box 8 perfmon counter MSR.
Vol. 3C 35-141
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-17. Additional MSRs Supported by Intel® Xeon® Processor E7 Family (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
F58H
3928
MSR_C8_PMON_EVNT_
SEL4
Package
Uncore C-box 8 perfmon event select MSR.
F59H
3929
MSR_C8_PMON_CTR4
Package
Uncore C-box 8 perfmon counter MSR.
F5AH
3930
MSR_C8_PMON_EVNT_
SEL5
Package
Uncore C-box 8 perfmon event select MSR.
F5BH
3931
MSR_C8_PMON_CTR5
Package
Uncore C-box 8 perfmon counter MSR.
FC0H
4032
MSR_C9_PMON_BOX_CTRL
Package
Uncore C-box 9 perfmon local box control MSR.
FC1H
4033
MSR_C9_PMON_BOX_
STATUS
Package
Uncore C-box 9 perfmon local box status MSR.
FC2H
4034
MSR_C9_PMON_BOX_OVF_
CTRL
Package
Uncore C-box 9 perfmon local box overflow control MSR.
FD0H
4048
MSR_C9_PMON_EVNT_
SEL0
Package
Uncore C-box 9 perfmon event select MSR.
FD1H
4049
MSR_C9_PMON_CTR0
Package
Uncore C-box 9 perfmon counter MSR.
FD2H
4050
MSR_C9_PMON_EVNT_
SEL1
Package
Uncore C-box 9 perfmon event select MSR.
FD3H
4051
MSR_C9_PMON_CTR1
Package
Uncore C-box 9 perfmon counter MSR.
FD4H
4052
MSR_C9_PMON_EVNT_
SEL2
Package
Uncore C-box 9 perfmon event select MSR.
FD5H
4053
MSR_C9_PMON_CTR2
Package
Uncore C-box 9 perfmon counter MSR.
FD6H
4054
MSR_C9_PMON_EVNT_
SEL3
Package
Uncore C-box 9 perfmon event select MSR.
FD7H
4055
MSR_C9_PMON_CTR3
Package
Uncore C-box 9 perfmon counter MSR.
FD8H
4056
MSR_C9_PMON_EVNT_
SEL4
Package
Uncore C-box 9 perfmon event select MSR.
FD9H
4057
MSR_C9_PMON_CTR4
Package
Uncore C-box 9 perfmon counter MSR.
FDAH
4058
MSR_C9_PMON_EVNT_
SEL5
Package
Uncore C-box 9 perfmon event select MSR.
FDBH
4059
MSR_C9_PMON_CTR5
Package
Uncore C-box 9 perfmon counter MSR.
35.9
MSRS IN INTEL® PROCESSOR FAMILY BASED ON INTEL®
MICROARCHITECTURE CODE NAME SANDY BRIDGE
Table 35-18 lists model-specific registers (MSRs) that are common to Intel® processor family based on Intel microarchitecture code name Sandy Bridge. These processors have a CPUID signature with DisplayFamily_DisplayModel
of 06_2AH, 06_2DH, see Table 35-1. Additional MSRs specific to 06_2AH are listed in Table 35-19.
35-142 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Thread
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Thread
See Section 35.22, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_
SIZE
Thread
See Section 8.10.5, “Monitor/Mwait Address Range Determination,”
and Table 35-2.
10H
16
IA32_TIME_STAMP_
COUNTER
Thread
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
17H
23
IA32_PLATFORM_ID
Package
Platform ID (R)
See Table 35-2.
1BH
27
IA32_APIC_BASE
Thread
See Section 10.4.4, “Local APIC Status and Location,” and
Table 35-2.
34H
52
MSR_SMI_COUNT
Thread
SMI Counter (R/O)
31:0
SMI Count (R/O)
Count SMIs.
63:32
3AH
58
IA32_FEATURE_CONTROL
Reserved.
Thread
Control Features in Intel 64 Processor (R/W)
See Table 35-2.
79H
121
0
Lock (R/WL)
1
Enable VMX inside SMX operation (R/WL)
2
Enable VMX outside SMX operation (R/WL)
14:8
SENTER local functions enables (R/WL)
15
SENTER global functions enable (R/WL)
IA32_BIOS_UPDT_TRIG
Core
BIOS Update Trigger Register (W)
See Table 35-2.
8BH
139
IA32_BIOS_SIGN_ID
Thread
BIOS Update Signature ID (RO)
See Table 35-2.
C1H
193
IA32_PMC0
Thread
Performance Counter Register
See Table 35-2.
C2H
194
IA32_PMC1
Thread
Performance Counter Register
See Table 35-2.
C3H
195
IA32_PMC2
Thread
Performance Counter Register
See Table 35-2.
C4H
196
IA32_PMC3
Thread
Performance Counter Register
See Table 35-2.
C5H
197
IA32_PMC4
Core
Performance Counter Register (if core not shared by threads)
C6H
198
IA32_PMC5
Core
Performance Counter Register (if core not shared by threads)
C7H
199
IA32_PMC6
Core
Performance Counter Register (if core not shared by threads)
C8H
200
IA32_PMC7
Core
Performance Counter Register (if core not shared by threads)
Vol. 3C 35-143
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
CEH
206
Register Name
MSR_PLATFORM_INFO
Scope
Package
7:0
15:8
Bit Description
See http://biosbits.org.
Reserved.
Package
Maximum Non-Turbo Ratio (R/O)
The is the ratio of the frequency that invariant TSC runs at.
Frequency = ratio * 100 MHz.
27:16
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limits for Turbo
mode is enabled, and when set to 0, indicates Programmable Ratio
Limits for Turbo mode is disabled.
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limits for Turbo mode are
programmable, and when set to 0, indicates TDP Limit for Turbo
mode is not programmable.
39:30
47:40
Reserved.
Package
Maximum Efficiency Ratio (R/O)
The is the minimum ratio (maximum efficiency) that the processor
can operates, in units of 100MHz.
63:48
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
Reserved.
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power). for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register
specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions
14:11
35-144 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
15
CFG Lock (R/WO)
When set, lock bits 15:0 of this register until next reset.
24:16
Reserved.
25
C3 state auto demotion enable (R/W)
When set, the processor will conditionally demote C6/C7 requests
to C3 based on uncore auto-demote information.
26
C1 state auto demotion enable (R/W)
When set, the processor will conditionally demote C3/C6/C7
requests to C1 based on uncore auto-demote information.
27
Enable C3 undemotion (R/W)
When set, enables undemotion from demoted C3.
28
Enable C1 undemotion (R/W)
When set, enables undemotion from demoted C1.
63:29
E4H
228
MSR_PMG_IO_CAPTURE_
BASE
Reserved.
Core
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
15:0
LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If
IO MWAIT Redirection is enabled, reads to this address will be
consumed by the power management logic and decoded to MWAIT
instructions. When IO port address redirection is enabled, this is
the IO port address reported to the OS/software.
18:16
C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name
to be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include
001b - C6 is the max C-State to include
010b - C7 is the max C-State to include
63:19
E7H
231
IA32_MPERF
Reserved.
Thread
Maximum Performance Frequency Clock Count (RW)
See Table 35-2.
E8H
232
IA32_APERF
Thread
Actual Performance Frequency Clock Count (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Thread
See Table 35-2.
13CH
52
MSR_FEATURE_CONFIG
Core
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle
unsuccessful read of this MSR.
Vol. 3C 35-145
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instruction can be mis-configured
if a privileged agent unintentionally writes 11b.
63:2
Reserved.
174H
372
IA32_SYSENTER_CS
Thread
See Table 35-2.
175H
373
IA32_SYSENTER_ESP
Thread
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Thread
See Table 35-2.
179H
377
IA32_MCG_CAP
Thread
See Table 35-2.
17AH
378
IA32_MCG_STATUS
Thread
0
RIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If cleared, the
program cannot be reliably restarted.
1
EIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, bit indicates that a machine check has been generated. If
a second machine check is detected while this bit is still set, the
processor enters a shutdown state. Software should write this bit
to 0 after processing a machine check exception.
63:3
Reserved.
186H
390
IA32_
PERFEVTSEL0
Thread
See Table 35-2.
187H
391
IA32_
PERFEVTSEL1
Thread
See Table 35-2.
188H
392
IA32_
PERFEVTSEL2
Thread
See Table 35-2.
189H
393
IA32_
PERFEVTSEL3
Thread
See Table 35-2.
18AH
394
IA32_
PERFEVTSEL4
Core
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
18BH
395
IA32_
PERFEVTSEL5
Core
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
18CH
396
IA32_
PERFEVTSEL6
Core
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
35-146 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
18DH
397
IA32_
PERFEVTSEL7
Core
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
198H
408
IA32_PERF_STATUS
Package
See Table 35-2.
198H
408
15:0
Current Performance State Value.
63:16
Reserved.
MSR_PERF_STATUS
Package
47:32
Core Voltage (R/O)
P-state core voltage can be computed by
MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
199H
409
IA32_PERF_CTL
Thread
See Table 35-2.
19AH
410
IA32_CLOCK_
MODULATION
Thread
Clock Modulation (R/W)
See Table 35-2
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
3:0
On demand Clock Modulation Duty Cycle (R/W)
In 6.25% increment
19BH
411
4
On demand Clock Modulation Enable (R/W)
63:5
Reserved.
IA32_THERM_INTERRUPT
Core
Thermal Interrupt Control (R/W)
See Table 35-2.
19CH
412
IA32_THERM_STATUS
Core
Thermal Monitor Status (R/W)
See Table 35-2.
0
Thermal status (RO)
See Table 35-2.
1
Thermal status log (R/WC0)
See Table 35-2.
2
PROTCHOT # or FORCEPR# status (RO)
See Table 35-2.
3
PROTCHOT # or FORCEPR# log (R/WC0)
See Table 35-2.
4
Critical Temperature status (RO)
See Table 35-2.
5
Critical Temperature status log (R/WC0)
See Table 35-2.
6
Thermal threshold #1 status (RO)
See Table 35-2.
7
Thermal threshold #1 log (R/WC0)
See Table 35-2.
Vol. 3C 35-147
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
8
Thermal threshold #2 status (RO)
See Table 35-2.
9
Thermal threshold #2 log (R/WC0)
See Table 35-2.
10
Power Limitation status (RO)
See Table 35-2.
11
Power Limitation log (R/WC0)
See Table 35-2.
15:12
Reserved.
22:16
Digital Readout (RO)
See Table 35-2.
26:23
Reserved.
30:27
Resolution in degrees Celsius (RO)
See Table 35-2.
31
Reading Valid (RO)
See Table 35-2.
1A0H
416
63:32
Reserved.
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0
Thread
Fast-Strings Enable
See Table 35-2
6:1
7
Reserved.
Thread
Performance Monitoring Available (R)
See Table 35-2.
10:8
11
Reserved.
Thread
Branch Trace Storage Unavailable (RO)
See Table 35-2.
12
Thread
Processor Event Based Sampling Unavailable (RO)
See Table 35-2.
15:13
16
Reserved.
Package
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 35-2.
18
Thread
21:19
22
ENABLE MONITOR FSM. (R/W) See Table 35-2.
Reserved.
Thread
Limit CPUID Maxval (R/W)
See Table 35-2.
23
Thread
xTPR Message Disable (R/W)
See Table 35-2.
35-148 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
33:24
34
Reserved.
Thread
XD Bit Disable (R/W)
See Table 35-2.
37:35
38
Reserved.
Package
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost
Technology, the turbo mode feature is disabled and the IDA_Enable
feature flag will be clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H:
EAX[1] reports the processor’s support of turbo mode is enabled.
Note: the power-on default value is used by BIOS to detect
hardware support of turbo mode. If power-on default value is 1,
turbo mode is available in the processor. If power-on default value
is 0, turbo mode is not available.
63:39
1A2H
418
MSR_
TEMPERATURE_TARGET
Reserved.
Unique
15:0
Reserved.
23:16
Temperature Target (R)
The minimum temperature at which PROCHOT# will be asserted.
The value is degree C.
1A4H
420
63:24
Reserved.
MSR_MISC_FEATURE_
CONTROL
Miscellaneous Feature Control (R/W)
0
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional
lines of code or data into the L2 cache.
1
Core
L2 Adjacent Cache Line Prefetcher Disable (R/W)
If 1, disables the adjacent cache line prefetcher, which fetches the
cache line that comprises a cache line pair (128 bytes).
2
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
3
Core
DCU IP Prefetcher Disable (R/W)
If 1, disables the L1 data cache IP prefetcher, which uses
sequential load history (based on instruction Pointer of previous
loads) to determine whether to prefetch additional lines.
63:4
Reserved.
1A6H
422
MSR_OFFCORE_RSP_0
Thread
Offcore Response Event Select Register (R/W)
1A7H
422
MSR_OFFCORE_RSP_1
Thread
Offcore Response Event Select Register (R/W)
1AAH
426
MSR_MISC_PWR_MGMT
1B0H
432
IA32_ENERGY_PERF_BIAS
See http://biosbits.org.
Package
See Table 35-2.
Vol. 3C 35-149
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
1B1H
433
IA32_PACKAGE_THERM_
STATUS
Package
See Table 35-2.
1B2H
434
IA32_PACKAGE_THERM_
INTERRUPT
Package
See Table 35-2.
1C8H
456
MSR_LBR_SELECT
Thread
Last Branch Record Filtering Select Register (R/W)
See Section 17.7.2, “Filtering of Last Branch Records.”
1C9H
457
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
63:9
Reserved.
MSR_LASTBRANCH_TOS
Thread
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the
most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 680H).
1D9H
473
IA32_DEBUGCTL
Thread
Debug Control (R/W)
See Table 35-2.
35-150 Vol. 3C
0
LBR: Last Branch Record
1
BTF
5:2
Reserved.
6
TR: Branch Trace
7
BTS: Log Branch Trace Message to BTS buffer
8
BTINT
9
BTS_OFF_OS
10
BTS_OFF_USER
11
FREEZE_LBR_ON_PMI
12
FREEZE_PERFMON_ON_PMI
13
ENABLE_UNCORE_PMI
14
FREEZE_WHILE_SMM
63:15
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
1DDH
477
Register Name
MSR_LER_FROM_LIP
Scope
Thread
Bit Description
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
1DEH
478
MSR_LER_TO_LIP
Thread
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled.
1F2H
498
IA32_SMRR_PHYSBASE
Core
See Table 35-2.
1F3H
499
IA32_SMRR_PHYSMASK
Core
See Table 35-2.
1FCH
508
MSR_POWER_CTL
Core
See http://biosbits.org.
200H
512
IA32_MTRR_PHYSBASE0
Thread
See Table 35-2.
201H
513
IA32_MTRR_PHYSMASK0
Thread
See Table 35-2.
202H
514
IA32_MTRR_PHYSBASE1
Thread
See Table 35-2.
203H
515
IA32_MTRR_PHYSMASK1
Thread
See Table 35-2.
204H
516
IA32_MTRR_PHYSBASE2
Thread
See Table 35-2.
205H
517
IA32_MTRR_PHYSMASK2
Thread
See Table 35-2.
206H
518
IA32_MTRR_PHYSBASE3
Thread
See Table 35-2.
207H
519
IA32_MTRR_PHYSMASK3
Thread
See Table 35-2.
208H
520
IA32_MTRR_PHYSBASE4
Thread
See Table 35-2.
209H
521
IA32_MTRR_PHYSMASK4
Thread
See Table 35-2.
20AH
522
IA32_MTRR_PHYSBASE5
Thread
See Table 35-2.
20BH
523
IA32_MTRR_PHYSMASK5
Thread
See Table 35-2.
20CH
524
IA32_MTRR_PHYSBASE6
Thread
See Table 35-2.
20DH
525
IA32_MTRR_PHYSMASK6
Thread
See Table 35-2.
20EH
526
IA32_MTRR_PHYSBASE7
Thread
See Table 35-2.
20FH
527
IA32_MTRR_PHYSMASK7
Thread
See Table 35-2.
210H
528
IA32_MTRR_PHYSBASE8
Thread
See Table 35-2.
211H
529
IA32_MTRR_PHYSMASK8
Thread
See Table 35-2.
212H
530
IA32_MTRR_PHYSBASE9
Thread
See Table 35-2.
213H
531
IA32_MTRR_PHYSMASK9
Thread
See Table 35-2.
250H
592
IA32_MTRR_FIX64K_
00000
Thread
See Table 35-2.
258H
600
IA32_MTRR_FIX16K_
80000
Thread
See Table 35-2.
259H
601
IA32_MTRR_FIX16K_
A0000
Thread
See Table 35-2.
Vol. 3C 35-151
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
268H
616
IA32_MTRR_FIX4K_C0000
Thread
See Table 35-2.
269H
617
IA32_MTRR_FIX4K_C8000
Thread
See Table 35-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Thread
See Table 35-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Thread
See Table 35-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Thread
See Table 35-2.
26DH
621
IA32_MTRR_FIX4K_E8000
Thread
See Table 35-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Thread
See Table 35-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Thread
See Table 35-2.
277H
631
IA32_PAT
Thread
See Table 35-2.
280H
640
IA32_MC0_CTL2
Core
See Table 35-2.
281H
641
IA32_MC1_CTL2
Core
See Table 35-2.
282H
642
IA32_MC2_CTL2
Core
See Table 35-2.
283H
643
IA32_MC3_CTL2
Core
See Table 35-2.
284H
644
IA32_MC4_CTL2
Package
Always 0 (CMCI not supported).
2FFH
767
IA32_MTRR_DEF_TYPE
Thread
Default Memory Types (R/W)
See Table 35-2.
309H
777
IA32_FIXED_CTR0
Thread
Fixed-Function Performance Counter Register 0 (R/W)
See Table 35-2.
30AH
778
IA32_FIXED_CTR1
Thread
Fixed-Function Performance Counter Register 1 (R/W)
See Table 35-2.
30BH
779
IA32_FIXED_CTR2
Thread
Fixed-Function Performance Counter Register 2 (R/W)
See Table 35-2.
345H
38DH
837
909
IA32_PERF_CAPABILITIES
Thread
See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”
5:0
LBR Format. See Table 35-2.
6
PEBS Record Format.
7
PEBSSaveArchRegs. See Table 35-2.
11:8
PEBS_REC_FORMAT. See Table 35-2.
12
SMM_FREEZE. See Table 35-2.
63:13
Reserved.
IA32_FIXED_CTR_CTRL
Thread
Fixed-Function-Counter Control Register (R/W)
See Table 35-2.
38EH
910
35-152 Vol. 3C
IA32_PERF_GLOBAL_
STATUS
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
0
Thread
Ovf_PMC0
1
Thread
Ovf_PMC1
2
Thread
Ovf_PMC2
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Register Name
Scope
Dec
3
Thread
Ovf_PMC3
4
Core
Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
5
Core
Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6
Core
Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
7
Core
Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
31:8
Reserved.
32
Thread
Ovf_FixedCtr0
33
Thread
Ovf_FixedCtr1
34
Thread
Ovf_FixedCtr2
60:35
38FH
911
Reserved.
61
Thread
Ovf_Uncore
62
Thread
Ovf_BufDSSAVE
63
Thread
CondChgd
IA32_PERF_GLOBAL_CTRL
Thread
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
0
Thread
Set 1 to enable PMC0 to count
1
Thread
Set 1 to enable PMC1 to count
2
Thread
Set 1 to enable PMC2 to count
3
Thread
Set 1 to enable PMC3 to count
4
Core
Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 4)
5
Core
Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 5)
6
Core
Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 6)
7
Core
Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 7)
31:8
390H
Bit Description
912
Reserved.
32
Thread
Set 1 to enable FixedCtr0 to count
33
Thread
Set 1 to enable FixedCtr1 to count
34
Thread
Set 1 to enable FixedCtr2 to count
63:35
Reserved.
IA32_PERF_GLOBAL_OVF_
CTRL
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
0
Thread
Set 1 to clear Ovf_PMC0
1
Thread
Set 1 to clear Ovf_PMC1
2
Thread
Set 1 to clear Ovf_PMC2
3
Thread
Set 1 to clear Ovf_PMC3
4
Core
Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
5
Core
Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6
Core
Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
Vol. 3C 35-153
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Register Name
Scope
Dec
7
Core
31:8
3F6H
3F8H
1009
1014
1016
Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
Reserved.
32
Thread
Set 1 to clear Ovf_FixedCtr0
33
Thread
Set 1 to clear Ovf_FixedCtr1
34
Thread
Set 1 to clear Ovf_FixedCtr2
60:35
3F1H
Bit Description
Reserved.
61
Thread
Set 1 to clear Ovf_Uncore
62
Thread
Set 1 to clear Ovf_BufDSSAVE
63
Thread
Set 1 to clear CondChgd
MSR_PEBS_ENABLE
Thread
See Section 18.8.1.1, “Processor Event Based Sampling (PEBS).”
0
Enable PEBS on IA32_PMC0. (R/W)
1
Enable PEBS on IA32_PMC1. (R/W)
2
Enable PEBS on IA32_PMC2. (R/W)
3
Enable PEBS on IA32_PMC3. (R/W)
31:4
Reserved.
32
Enable Load Latency on IA32_PMC0. (R/W)
33
Enable Load Latency on IA32_PMC1. (R/W)
34
Enable Load Latency on IA32_PMC2. (R/W)
35
Enable Load Latency on IA32_PMC3. (R/W)
62:36
Reserved.
63
Enable Precise Store. (R/W)
MSR_PEBS_LD_LAT
Thread
see See Section 18.8.1.2, “Load Latency Performance Monitoring
Facility.”
15:0
Minimum threshold latency value of tagged load operation that will
be counted. (R/W)
63:36
Reserved.
MSR_PKG_C3_RESIDENCY
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C3 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C3
states. Count at the same frequency as the TSC.
3F9H
1017
MSR_PKG_C6_RESIDENCY
63:0
Package
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C6
states. Count at the same frequency as the TSC.
35-154 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
3FAH
1018
Register Name
MSR_PKG_C7_RESIDENCY
Scope
Package
63:0
Bit Description
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C7 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C7
states. Count at the same frequency as the TSC.
3FCH
1020
MSR_CORE_C3_RESIDENCY
Core
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
CORE C3 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C3
states. Count at the same frequency as the TSC.
3FDH
1021
MSR_CORE_C6_RESIDENCY
Core
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
CORE C6 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C6
states. Count at the same frequency as the TSC.
3FEH
1022
MSR_CORE_C7_RESIDENCY
Core
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
CORE C7 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C7
states. Count at the same frequency as the TSC.
400H
1024
IA32_MC0_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
402H
1026
IA32_MC0_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
403H
1027
IA32_MC0_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
404H
1028
IA32_MC1_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
406H
1030
IA32_MC1_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
407H
1031
IA32_MC1_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
408H
1032
IA32_MC2_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
40AH
1034
IA32_MC2_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
40BH
1035
IA32_MC2_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
40CH
1036
IA32_MC3_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
40EH
1038
IA32_MC3_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
40FH
1039
IA32_MC3_MISC
Core
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
Vol. 3C 35-155
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
410H
1040
Register Name
IA32_MC4_CTL
Scope
Core
0
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
PCU Hardware Error (R/W)
When set, enables signaling of PCU hardware detected errors.
1
PCU Controller Error (R/W)
When set, enables signaling of PCU controller detected errors
2
PCU Firmware Error (R/W)
When set, enables signaling of PCU firmware detected errors
63:2
Reserved.
411H
1041
IA32_MC4_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
480H
1152
IA32_VMX_BASIC
Thread
Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_
CTLS
Thread
Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_
CTLS
Thread
Capability Reporting Register of Primary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
483H
1155
IA32_VMX_EXIT_CTLS
Thread
Capability Reporting Register of VM-exit Controls (R/O)
See Table 35-2.
See Appendix A.4, “VM-Exit Controls.”
484H
1156
IA32_VMX_ENTRY_CTLS
Thread
Capability Reporting Register of VM-entry Controls (R/O)
See Table 35-2.
See Appendix A.5, “VM-Entry Controls.”
485H
1157
IA32_VMX_MISC
Thread
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.6, “Miscellaneous Data.”
486H
1158
IA32_VMX_CR0_FIXED0
Thread
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Thread
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Thread
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
35-156 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
489H
1161
Register Name
IA32_VMX_CR4_FIXED1
Scope
Thread
Bit Description
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH
1162
IA32_VMX_VMCS_ENUM
Thread
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 35-2.
See Appendix A.9, “VMCS Enumeration.”
48BH
1163
IA32_VMX_PROCBASED_
CTLS2
Thread
48CH
1164
IA32_VMX_EPT_VPID_ENU
M
Thread
IA32_VMX_TRUE_PINBASE
D_CTLS
Thread
Capability Reporting Register of Secondary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
48DH
1165
Capability Reporting Register of EPT and VPID (R/O)
See Table 35-2
Capability Reporting Register of Pin-based VM-execution Flex
Controls (R/O)
See Table 35-2
48EH
1166
IA32_VMX_TRUE_PROCBAS
ED_CTLS
Thread
Capability Reporting Register of Primary Processor-based
VM-execution Flex Controls (R/O)
See Table 35-2
48FH
490H
1167
1168
IA32_VMX_TRUE_EXIT_CTL Thread
S
Capability Reporting Register of VM-exit Flex Controls (R/O)
IA32_VMX_TRUE_ENTRY_C
TLS
Thread
Capability Reporting Register of VM-entry Flex Controls (R/O)
See Table 35-2
See Table 35-2
4C1H
1217
IA32_A_PMC0
Thread
See Table 35-2.
4C2H
1218
IA32_A_PMC1
Thread
See Table 35-2.
4C3H
1219
IA32_A_PMC2
Thread
See Table 35-2.
4C4H
1220
IA32_A_PMC3
Thread
See Table 35-2.
4C5H
1221
IA32_A_PMC4
Core
See Table 35-2.
4C6H
1222
IA32_A_PMC5
Core
See Table 35-2.
4C7H
1223
IA32_A_PMC6
Core
See Table 35-2.
4C8H
1224
IA32_A_PMC7
Core
See Table 35-2.
600H
1536
IA32_DS_AREA
Thread
DS Save Area (R/W)
See Table 35-2.
See Section 18.15.4, “Debug Store (DS) Mechanism.”
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 14.9.1, “RAPL Interfaces.”
60AH
1546
MSR_PKGC3_IRTL
Package
Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Vol. 3C 35-157
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C3 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. The following time unit encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
60BH
1547
MSR_PKGC6_IRTL
Reserved.
Package
Package C6 Interrupt Response Limit (R/W)
This MSR defines the budget allocated for the package to exit from
C6 to a C0 state, where interrupt request can be delivered to the
core and serviced. Additional core-exit latency amy be applicable
depending on the actual C-state the core is in.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C6 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. The following time unit encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
35-158 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
60DH
1549
Register Name
MSR_PKG_C2_RESIDENCY
Scope
Package
63:0
Bit Description
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
Package C2 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C2
states. Count at the same frequency as the TSC.
610H
1552
MSR_PKG_POWER_LIMIT
Package
PKG RAPL Power Limit Control (R/W)
See Section 14.9.3, “Package RAPL Domain.”
611H
1553
MSR_PKG_ENERGY_STATUS
Package
PKG Energy Status (R/O)
See Section 14.9.3, “Package RAPL Domain.”
614H
1556
MSR_PKG_POWER_INFO
Package
PKG RAPL Parameters (R/W) See Section 14.9.3, “Package RAPL
Domain.”
638H
1592
MSR_PP0_POWER_LIMIT
Package
PP0 RAPL Power Limit Control (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
680H
1664
MSR_
LASTBRANCH_0_FROM_IP
Thread
Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on the last
branch record stack. This part of the stack contains pointers to the
source instruction. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.7.1 and record format in Section 17.4.8.1
681H
682H
683H
684H
685H
686H
687H
688H
689H
68AH
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
MSR_
LASTBRANCH_1_FROM_IP
Thread
MSR_
LASTBRANCH_2_FROM_IP
Thread
MSR_
LASTBRANCH_3_FROM_IP
Thread
MSR_
LASTBRANCH_4_FROM_IP
Thread
MSR_
LASTBRANCH_5_FROM_IP
Thread
MSR_
LASTBRANCH_6_FROM_IP
Thread
MSR_
LASTBRANCH_7_FROM_IP
Thread
MSR_
LASTBRANCH_8_FROM_IP
Thread
MSR_
LASTBRANCH_9_FROM_IP
Thread
MSR_
LASTBRANCH_10_FROM_IP
Thread
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Vol. 3C 35-159
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
68BH
1675
68CH
68DH
68EH
68FH
6C0H
6C1H
6C2H
6C3H
6C4H
6C5H
6C6H
6C7H
6C8H
6C9H
6CAH
6CBH
6CCH
1676
1677
1678
1679
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
35-160 Vol. 3C
Register Name
Scope
MSR_
LASTBRANCH_11_FROM_IP
Thread
MSR_
LASTBRANCH_12_FROM_IP
Thread
MSR_
LASTBRANCH_13_FROM_IP
Thread
MSR_
LASTBRANCH_14_FROM_IP
Thread
MSR_
LASTBRANCH_15_FROM_IP
Thread
MSR_
LASTBRANCH_0_TO_IP
Thread
MSR_
LASTBRANCH_1_TO_IP
Thread
MSR_
LASTBRANCH_2_TO_IP
Thread
MSR_
LASTBRANCH_3_TO_IP
Thread
MSR_
LASTBRANCH_4_TO_IP
Thread
MSR_
LASTBRANCH_5_TO_IP
Thread
MSR_
LASTBRANCH_6_TO_IP
Thread
MSR_
LASTBRANCH_7_TO_IP
Thread
MSR_
LASTBRANCH_8_TO_IP
Thread
MSR_
LASTBRANCH_9_TO_IP
Thread
MSR_
LASTBRANCH_10_TO_IP
Thread
MSR_
LASTBRANCH_11_TO_IP
Thread
MSR_
LASTBRANCH_12_TO_IP
Thread
Bit Description
Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 0 To IP (R/W)
One of sixteen pairs of last branch record registers on the last
branch record stack. This part of the stack contains pointers to the
destination instruction.
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Hex
Dec
6CDH
1741
Register Name
Scope
Bit Description
MSR_
LASTBRANCH_13_TO_IP
Thread
MSR_
LASTBRANCH_14_TO_IP
Thread
MSR_
LASTBRANCH_15_TO_IP
Thread
IA32_TSC_DEADLINE
Thread
See Table 35-2.
802H83FH
X2APIC MSRs
Thread
See Table 35-2.
C000_
0080H
IA32_EFER
Thread
Extended Feature Enables
C000_
0081H
IA32_STAR
C000_
0082H
IA32_LSTAR
C000_
0084H
IA32_FMASK
C000_
0100H
IA32_FS_BASE
C000_
0101H
IA32_GS_BASE
C000_
0102H
IA32_KERNEL_GS_BASE
C000_
0103H
IA32_TSC_AUX
6CEH
6CFH
6E0H
35.9.1
1742
1743
1760
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
See Table 35-2.
Thread
System Call Target Address (R/W)
See Table 35-2.
Thread
IA-32e Mode System Call Target Address (R/W)
See Table 35-2.
Thread
System Call Flag Mask (R/W)
See Table 35-2.
Thread
Map of BASE Address of FS (R/W)
See Table 35-2.
Thread
Map of BASE Address of GS (R/W)
See Table 35-2.
Thread
Swap Target of BASE Address of GS (R/W)
See Table 35-2.
Thread
AUXILIARY TSC Signature (R/W)
See Table 35-2 and Section 17.15.2, “IA32_TSC_AUX Register and
RDTSCP Support.”
MSRs In 2nd Generation Intel® Core™ Processor Family (Based on Intel®
Microarchitecture Code Name Sandy Bridge)
Table 35-19 and Table 35-20 list model-specific registers (MSRs) that are specific to the 2nd generation Intel®
Core™ processor family (based on Intel microarchitecture code name Sandy Bridge). These processors have a
CPUID signature with DisplayFamily_DisplayModel of 06_2AH; see Table 35-1.
Vol. 3C 35-161
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-19. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy
Bridge)
Register
Address
Hex
Dec
1ADH
429
Register Name
MSR_TURBO_RATIO_LIMIT
Scope
Package
Bit Description
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32
60CH
1548
MSR_PKGC7_IRTL
Reserved.
Package
Package C7 Interrupt Response Limit (R/W)
This MSR defines the budget allocated for the package to exit
from C7 to a C0 state, where interrupt request can be delivered to
the core and serviced. Additional core-exit latency amy be
applicable depending on the actual C-state the core is in.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C7 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. The following time unit encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
639H
1593
MSR_PP0_ENERGY_STATUS
Reserved.
Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
35-162 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-19. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy
Bridge) (Contd.)
Register
Address
Hex
Dec
63AH
1594
Register Name
MSR_PP0_POLICY
Scope
Package
Bit Description
PP0 Balance Policy (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
640H
1600
MSR_PP1_POWER_LIMIT
Package
PP1 RAPL Power Limit Control (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
641H
1601
MSR_PP1_ENERGY_STATUS
Package
PP1 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
642H
1602
MSR_PP1_POLICY
Package
PP1 Balance Policy (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
See Table 35-18, Table 35-19, and Table 35-20 for MSR definitions applicable to processors with CPUID signature 06_2AH.
Table 35-20 lists the MSRs of uncore PMU for Intel processors with CPUID signature 06_2AH.
Table 35-20. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address
Hex
Dec
391H
913
Register Name
MSR_UNC_PERF_GLOBAL_
CTRL
Scope
Package
394H
914
916
Uncore PMU global control
0
Slice 0 select
1
Slice 1 select
2
Slice 2 select
3
Slice 3 select
4
Slice 4 select
18:5
Reserved.
29
Enable all uncore counters
30
Enable wake on PMI
31
Enable Freezing counter when overflow
63:32
392H
Bit Description
MSR_UNC_PERF_GLOBAL_
STATUS
Reserved.
Package
Uncore PMU main status
0
Fixed counter overflowed
1
An ARB counter overflowed
2
Reserved
3
A CBox counter overflowed (on any slice)
63:4
Reserved.
MSR_UNC_PERF_FIXED_
CTRL
Package
Uncore fixed counter control (R/W)
19:0
Reserved
20
Enable overflow propagation
Vol. 3C 35-163
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-20. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address
Hex
395H
396H
Register Name
Scope
Bit Description
Dec
917
918
21
Reserved
22
Enable counting
63:23
Reserved.
MSR_UNC_PERF_FIXED_
CTR
Package
Uncore fixed counter
47:0
Current count
63:48
Reserved.
MSR_UNC_CBO_CONFIG
Package
Uncore C-Box configuration information (R/O)
3:0
Report the number of C-Box units with performance counters,
including processor cores and processor graphics“
63:4
Reserved.
3B0H
946
MSR_UNC_ARB_PERFCTR0
Package
Uncore Arb unit, performance counter 0
3B1H
947
MSR_UNC_ARB_PERFCTR1
Package
Uncore Arb unit, performance counter 1
3B2H
944
MSR_UNC_ARB_
PERFEVTSEL0
Package
Uncore Arb unit, counter 0 event select MSR
3B3H
945
MSR_UNC_ARB_
PERFEVTSEL1
Package
Uncore Arb unit, counter 1 event select MSR
700H
1792
MSR_UNC_CBO_0_
PERFEVTSEL0
Package
Uncore C-Box 0, counter 0 event select MSR
701H
1793
MSR_UNC_CBO_0_
PERFEVTSEL1
Package
Uncore C-Box 0, counter 1 event select MSR
702H
1794
MSR_UNC_CBO_0_
PERFEVTSEL2
Package
Uncore C-Box 0, counter 2 event select MSR.
703H
1795
MSR_UNC_CBO_0_
PERFEVTSEL3
Package
Uncore C-Box 0, counter 3 event select MSR.
705H
1797
MSR_UNC_CBO_0_UNIT_
STATUS
Package
Uncore C-Box 0, unit status for counter 0-3
706H
1798
MSR_UNC_CBO_0_PERFCTR0
Package
Uncore C-Box 0, performance counter 0
707H
1799
MSR_UNC_CBO_0_PERFCTR1
Package
Uncore C-Box 0, performance counter 1
708H
1800
MSR_UNC_CBO_0_PERFCTR2
Package
Uncore C-Box 0, performance counter 2.
709H
1801
MSR_UNC_CBO_0_PERFCTR3
Package
Uncore C-Box 0, performance counter 3.
710H
1808
MSR_UNC_CBO_1_
PERFEVTSEL0
Package
Uncore C-Box 1, counter 0 event select MSR
711H
1809
MSR_UNC_CBO_1_
PERFEVTSEL1
Package
Uncore C-Box 1, counter 1 event select MSR
712H
1810
MSR_UNC_CBO_1_
PERFEVTSEL2
Package
Uncore C-Box 1, counter 2 event select MSR.
713H
1811
MSR_UNC_CBO_1_
PERFEVTSEL3
Package
Uncore C-Box 1, counter 3 event select MSR.
35-164 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-20. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
715H
1813
MSR_UNC_CBO_1_UNIT_
STATUS
Package
Uncore C-Box 1, unit status for counter 0-3
716H
1814
MSR_UNC_CBO_1_PERFCTR0
Package
Uncore C-Box 1, performance counter 0
717H
1815
MSR_UNC_CBO_1_PERFCTR1
Package
Uncore C-Box 1, performance counter 1
718H
1816
MSR_UNC_CBO_1_PERFCTR2
Package
Uncore C-Box 1, performance counter 2.
719H
1817
MSR_UNC_CBO_1_PERFCTR3
Package
Uncore C-Box 1, performance counter 3.
720H
1824
MSR_UNC_CBO_2_
PERFEVTSEL0
Package
Uncore C-Box 2, counter 0 event select MSR
721H
1825
MSR_UNC_CBO_2_
PERFEVTSEL1
Package
Uncore C-Box 2, counter 1 event select MSR
722H
1826
MSR_UNC_CBO_2_
PERFEVTSEL2
Package
Uncore C-Box 2, counter 2 event select MSR.
723H
1827
MSR_UNC_CBO_2_
PERFEVTSEL3
Package
Uncore C-Box 2, counter 3 event select MSR.
725H
1829
MSR_UNC_CBO_2_UNIT_
STATUS
Package
Uncore C-Box 2, unit status for counter 0-3
726H
1830
MSR_UNC_CBO_2_PERFCTR0
Package
Uncore C-Box 2, performance counter 0
727H
1831
MSR_UNC_CBO_2_PERFCTR1
Package
Uncore C-Box 2, performance counter 1
728H
1832
MSR_UNC_CBO_3_PERFCTR2
Package
Uncore C-Box 3, performance counter 2.
729H
1833
MSR_UNC_CBO_3_PERFCTR3
Package
Uncore C-Box 3, performance counter 3.
730H
1840
MSR_UNC_CBO_3_
PERFEVTSEL0
Package
Uncore C-Box 3, counter 0 event select MSR
731H
1841
MSR_UNC_CBO_3_
PERFEVTSEL1
Package
Uncore C-Box 3, counter 1 event select MSR.
732H
1842
MSR_UNC_CBO_3_
PERFEVTSEL2
Package
Uncore C-Box 3, counter 2 event select MSR.
733H
1843
MSR_UNC_CBO_3_
PERFEVTSEL3
Package
Uncore C-Box 3, counter 3 event select MSR.
735H
1845
MSR_UNC_CBO_3_UNIT_
STATUS
Package
Uncore C-Box 3, unit status for counter 0-3
736H
1846
MSR_UNC_CBO_3_PERFCTR0
Package
Uncore C-Box 3, performance counter 0.
737H
1847
MSR_UNC_CBO_3_PERFCTR1
Package
Uncore C-Box 3, performance counter 1.
738H
1848
MSR_UNC_CBO_3_PERFCTR2
Package
Uncore C-Box 3, performance counter 2.
739H
1849
MSR_UNC_CBO_3_PERFCTR3
Package
Uncore C-Box 3, performance counter 3.
740H
1856
MSR_UNC_CBO_4_
PERFEVTSEL0
Package
Uncore C-Box 4, counter 0 event select MSR
741H
1857
MSR_UNC_CBO_4_
PERFEVTSEL1
Package
Uncore C-Box 4, counter 1 event select MSR.
742H
1858
MSR_UNC_CBO_4_
PERFEVTSEL2
Package
Uncore C-Box 4, counter 2 event select MSR.
Vol. 3C 35-165
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-20. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
743H
1859
MSR_UNC_CBO_4_
PERFEVTSEL3
Package
Uncore C-Box 4, counter 3 event select MSR.
745H
1861
MSR_UNC_CBO_4_UNIT_
STATUS
Package
Uncore C-Box 4, unit status for counter 0-3
746H
1862
MSR_UNC_CBO_4_PERFCTR0
Package
Uncore C-Box 4, performance counter 0.
747H
1863
MSR_UNC_CBO_4_PERFCTR1
Package
Uncore C-Box 4, performance counter 1.
748H
1864
MSR_UNC_CBO_4_PERFCTR2
Package
Uncore C-Box 4, performance counter 2.
749H
1865
MSR_UNC_CBO_4_PERFCTR3
Package
Uncore C-Box 4, performance counter 3.
35.9.2
MSRs In Intel® Xeon® Processor E5 Family (Based on Intel® Microarchitecture Code
Name Sandy Bridge)
Table 35-21 lists additional model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5
Family (based on Intel® microarchitecture code name Sandy Bridge). These processors have a CPUID signature
with DisplayFamily_DisplayModel of 06_2DH, and also supports MSRs listed in Table 35-18 and Table 35-22.
Table 35-21. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge
microarchitecture)
Register
Address
Hex
Dec
17FH
383
Register Name
MSR_ERROR_CONTROL
Scope
Package
Bit Description
MC Bank Error Configuration (R/W)
0
Reserved
1
MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info in bits
36:32.
63:2
1ADH
429
MSR_TURBO_RATIO_LIMIT
Reserved.
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
35-166 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-21. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge
microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
55:48
Package
Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.
63:56
Package
Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.
285H
645
IA32_MC5_CTL2
Package
See Table 35-2.
286H
646
IA32_MC6_CTL2
Package
See Table 35-2.
287H
647
IA32_MC7_CTL2
Package
See Table 35-2.
288H
648
IA32_MC8_CTL2
Package
See Table 35-2.
289H
649
IA32_MC9_CTL2
Package
See Table 35-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 35-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 35-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 35-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 35-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 35-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 35-2.
290H
656
IA32_MC16_CTL2
Package
See Table 35-2.
291H
657
IA32_MC17_CTL2
Package
See Table 35-2.
292H
658
IA32_MC18_CTL2
Package
See Table 35-2.
293H
659
IA32_MC19_CTL2
Package
See Table 35-2.
39CH
924
MSR_PEBS_NUM_ALT
Package
0
ENABLE_PEBS_NUM_ALT (RW)
Write 1 to enable alternate PEBS counting logic for specific events
requiring additional configuration, see Table 19-15
63:1
Reserved (must be zero).
414H
1044
IA32_MC5_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
415H
1045
IA32_MC5_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
416H
1046
IA32_MC5_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
417H
1047
IA32_MC5_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
418H
1048
IA32_MC6_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
419H
1049
IA32_MC6_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
41AH
1050
IA32_MC6_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
41BH
1051
IA32_MC6_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
41CH
1052
IA32_MC7_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
41DH
1053
IA32_MC7_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
41EH
1054
IA32_MC7_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
Vol. 3C 35-167
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-21. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge
microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
41FH
1055
IA32_MC7_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
420H
1056
IA32_MC8_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
421H
1057
IA32_MC8_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
422H
1058
IA32_MC8_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
423H
1059
IA32_MC8_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
424H
1060
IA32_MC9_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
425H
1061
IA32_MC9_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
426H
1062
IA32_MC9_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
427H
1063
IA32_MC9_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
428H
1064
IA32_MC10_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
429H
1065
IA32_MC10_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
42AH
1066
IA32_MC10_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
42BH
1067
IA32_MC10_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
42CH
1068
IA32_MC11_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
42DH
1069
IA32_MC11_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
42EH
1070
IA32_MC11_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
42FH
1071
IA32_MC11_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
430H
1072
IA32_MC12_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
431H
1073
IA32_MC12_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
432H
1074
IA32_MC12_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
433H
1075
IA32_MC12_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
434H
1076
IA32_MC13_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
435H
1077
IA32_MC13_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
436H
1078
IA32_MC13_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
437H
1079
IA32_MC13_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
438H
1080
IA32_MC14_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
439H
1081
IA32_MC14_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
43AH
1082
IA32_MC14_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
43BH
1083
IA32_MC14_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
43CH
1084
IA32_MC15_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
43DH
1085
IA32_MC15_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
43EH
1086
IA32_MC15_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
43FH
1087
IA32_MC15_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
440H
1088
IA32_MC16_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
441H
1089
IA32_MC16_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
442H
1090
IA32_MC16_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
35-168 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-21. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge
microarchitecture) (Contd.)
Register
Address
Scope
Register Name
Bit Description
Hex
Dec
443H
1091
IA32_MC16_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
444H
1092
IA32_MC17_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
445H
1093
IA32_MC17_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
446H
1094
IA32_MC17_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
447H
1095
IA32_MC17_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
448H
1096
IA32_MC18_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
449H
1097
IA32_MC18_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
44AH
1098
IA32_MC18_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
44BH
1099
IA32_MC18_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
44CH
1100
IA32_MC19_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
44DH
1101
IA32_MC19_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 16.
44EH
1102
IA32_MC19_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
44FH
1103
IA32_MC19_MISC
Package
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
613H
1555
MSR_PKG_PERF_STATUS
Package
Package RAPL Perf Status (R/O)
618H
1560
MSR_DRAM_POWER_LIMIT
Package
DRAM RAPL Power Limit Control (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_
STATUS
Package
DRAM Energy Status (R/O)
See Section 14.9.5, “DRAM RAPL Domain.”
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O) See Section 14.9.5,
“DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
639H
1593
MSR_PP0_ENERGY_STATU
S
Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
See Table 35-18, Table 35-21, and Table 35-22 for MSR definitions applicable to processors with CPUID signature 06_2DH.
35.9.3
Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family
Intel Xeon Processor E5 family is based on the Sandy Bridge microarchitecture. The MSR-based uncore PMU interfaces are listed in Table 35-22. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 Product
Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_2DH
Table 35-22. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
C08H
MSR_U_PMON_UCLK_FIXED_CTL
Package
Uncore U-box UCLK fixed counter control
C09H
MSR_U_PMON_UCLK_FIXED_CTR
Package
Uncore U-box UCLK fixed counter
Vol. 3C 35-169
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-22. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
C10H
MSR_U_PMON_EVNTSEL0
Package
Uncore U-box perfmon event select for U-box counter 0.
C11H
MSR_U_PMON_EVNTSEL1
Package
Uncore U-box perfmon event select for U-box counter 1.
C16H
MSR_U_PMON_CTR0
Package
Uncore U-box perfmon counter 0
C17H
MSR_U_PMON_CTR1
Package
Uncore U-box perfmon counter 1
C24H
MSR_PCU_PMON_BOX_CTL
Package
Uncore PCU perfmon for PCU-box-wide control
C30H
MSR_PCU_PMON_EVNTSEL0
Package
Uncore PCU perfmon event select for PCU counter 0.
C31H
MSR_PCU_PMON_EVNTSEL1
Package
Uncore PCU perfmon event select for PCU counter 1.
C32H
MSR_PCU_PMON_EVNTSEL2
Package
Uncore PCU perfmon event select for PCU counter 2.
C33H
MSR_PCU_PMON_EVNTSEL3
Package
Uncore PCU perfmon event select for PCU counter 3.
C34H
MSR_PCU_PMON_BOX_FILTER
Package
Uncore PCU perfmon box-wide filter.
C36H
MSR_PCU_PMON_CTR0
Package
Uncore PCU perfmon counter 0.
C37H
MSR_PCU_PMON_CTR1
Package
Uncore PCU perfmon counter 1.
C38H
MSR_PCU_PMON_CTR2
Package
Uncore PCU perfmon counter 2.
C39H
MSR_PCU_PMON_CTR3
Package
Uncore PCU perfmon counter 3.
D04H
MSR_C0_PMON_BOX_CTL
Package
Uncore C-box 0 perfmon local box wide control.
D10H
MSR_C0_PMON_EVNTSEL0
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 0.
D11H
MSR_C0_PMON_EVNTSEL1
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 1.
D12H
MSR_C0_PMON_EVNTSEL2
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 2.
D13H
MSR_C0_PMON_EVNTSEL3
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 3.
D14H
MSR_C0_PMON_BOX_FILTER
Package
Uncore C-box 0 perfmon box wide filter.
D16H
MSR_C0_PMON_CTR0
Package
Uncore C-box 0 perfmon counter 0.
D17H
MSR_C0_PMON_CTR1
Package
Uncore C-box 0 perfmon counter 1.
D18H
MSR_C0_PMON_CTR2
Package
Uncore C-box 0 perfmon counter 2.
D19H
MSR_C0_PMON_CTR3
Package
Uncore C-box 0 perfmon counter 3.
D24H
MSR_C1_PMON_BOX_CTL
Package
Uncore C-box 1 perfmon local box wide control.
D30H
MSR_C1_PMON_EVNTSEL0
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 0.
D31H
MSR_C1_PMON_EVNTSEL1
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 1.
D32H
MSR_C1_PMON_EVNTSEL2
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 2.
D33H
MSR_C1_PMON_EVNTSEL3
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 3.
D34H
MSR_C1_PMON_BOX_FILTER
Package
Uncore C-box 1 perfmon box wide filter.
D36H
MSR_C1_PMON_CTR0
Package
Uncore C-box 1 perfmon counter 0.
D37H
MSR_C1_PMON_CTR1
Package
Uncore C-box 1 perfmon counter 1.
D38H
MSR_C1_PMON_CTR2
Package
Uncore C-box 1 perfmon counter 2.
D39H
MSR_C1_PMON_CTR3
Package
Uncore C-box 1 perfmon counter 3.
D44H
MSR_C2_PMON_BOX_CTL
Package
Uncore C-box 2 perfmon local box wide control.
D50H
MSR_C2_PMON_EVNTSEL0
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 0.
D51H
MSR_C2_PMON_EVNTSEL1
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 1.
35-170 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-22. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
D52H
MSR_C2_PMON_EVNTSEL2
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 2.
D53H
MSR_C2_PMON_EVNTSEL3
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 3.
D54H
MSR_C2_PMON_BOX_FILTER
Package
Uncore C-box 2 perfmon box wide filter.
D56H
MSR_C2_PMON_CTR0
Package
Uncore C-box 2 perfmon counter 0.
D57H
MSR_C2_PMON_CTR1
Package
Uncore C-box 2 perfmon counter 1.
D58H
MSR_C2_PMON_CTR2
Package
Uncore C-box 2 perfmon counter 2.
D59H
MSR_C2_PMON_CTR3
Package
Uncore C-box 2 perfmon counter 3.
D64H
MSR_C3_PMON_BOX_CTL
Package
Uncore C-box 3 perfmon local box wide control.
D70H
MSR_C3_PMON_EVNTSEL0
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 0.
D71H
MSR_C3_PMON_EVNTSEL1
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 1.
D72H
MSR_C3_PMON_EVNTSEL2
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 2.
D73H
MSR_C3_PMON_EVNTSEL3
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 3.
D74H
MSR_C3_PMON_BOX_FILTER
Package
Uncore C-box 3 perfmon box wide filter.
D76H
MSR_C3_PMON_CTR0
Package
Uncore C-box 3 perfmon counter 0.
D77H
MSR_C3_PMON_CTR1
Package
Uncore C-box 3 perfmon counter 1.
D78H
MSR_C3_PMON_CTR2
Package
Uncore C-box 3 perfmon counter 2.
D79H
MSR_C3_PMON_CTR3
Package
Uncore C-box 3 perfmon counter 3.
D84H
MSR_C4_PMON_BOX_CTL
Package
Uncore C-box 4 perfmon local box wide control.
D90H
MSR_C4_PMON_EVNTSEL0
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 0.
D91H
MSR_C4_PMON_EVNTSEL1
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 1.
D92H
MSR_C4_PMON_EVNTSEL2
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 2.
D93H
MSR_C4_PMON_EVNTSEL3
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 3.
D94H
MSR_C4_PMON_BOX_FILTER
Package
Uncore C-box 4 perfmon box wide filter.
D96H
MSR_C4_PMON_CTR0
Package
Uncore C-box 4 perfmon counter 0.
D97H
MSR_C4_PMON_CTR1
Package
Uncore C-box 4 perfmon counter 1.
D98H
MSR_C4_PMON_CTR2
Package
Uncore C-box 4 perfmon counter 2.
D99H
MSR_C4_PMON_CTR3
Package
Uncore C-box 4 perfmon counter 3.
DA4H
MSR_C5_PMON_BOX_CTL
Package
Uncore C-box 5 perfmon local box wide control.
DB0H
MSR_C5_PMON_EVNTSEL0
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 0.
DB1H
MSR_C5_PMON_EVNTSEL1
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 1.
DB2H
MSR_C5_PMON_EVNTSEL2
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 2.
DB3H
MSR_C5_PMON_EVNTSEL3
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 3.
DB4H
MSR_C5_PMON_BOX_FILTER
Package
Uncore C-box 5 perfmon box wide filter.
DB6H
MSR_C5_PMON_CTR0
Package
Uncore C-box 5 perfmon counter 0.
DB7H
MSR_C5_PMON_CTR1
Package
Uncore C-box 5 perfmon counter 1.
DB8H
MSR_C5_PMON_CTR2
Package
Uncore C-box 5 perfmon counter 2.
DB9H
MSR_C5_PMON_CTR3
Package
Uncore C-box 5 perfmon counter 3.
Vol. 3C 35-171
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-22. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address
Hex
Scope
Register Name
Bit Description
Dec
DC4H
MSR_C6_PMON_BOX_CTL
Package
Uncore C-box 6 perfmon local box wide control.
DD0H
MSR_C6_PMON_EVNTSEL0
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 0.
DD1H
MSR_C6_PMON_EVNTSEL1
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 1.
DD2H
MSR_C6_PMON_EVNTSEL2
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 2.
DD3H
MSR_C6_PMON_EVNTSEL3
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 3.
DD4H
MSR_C6_PMON_BOX_FILTER
Package
Uncore C-box 6 perfmon box wide filter.
DD6H
MSR_C6_PMON_CTR0
Package
Uncore C-box 6 perfmon counter 0.
DD7H
MSR_C6_PMON_CTR1
Package
Uncore C-box 6 perfmon counter 1.
DD8H
MSR_C6_PMON_CTR2
Package
Uncore C-box 6 perfmon counter 2.
DD9H
MSR_C6_PMON_CTR3
Package
Uncore C-box 6 perfmon counter 3.
DE4H
MSR_C7_PMON_BOX_CTL
Package
Uncore C-box 7 perfmon local box wide control.
DF0H
MSR_C7_PMON_EVNTSEL0
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 0.
DF1H
MSR_C7_PMON_EVNTSEL1
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 1.
DF2H
MSR_C7_PMON_EVNTSEL2
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 2.
DF3H
MSR_C7_PMON_EVNTSEL3
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 3.
DF4H
MSR_C7_PMON_BOX_FILTER
Package
Uncore C-box 7 perfmon box wide filter.
DF6H
MSR_C7_PMON_CTR0
Package
Uncore C-box 7 perfmon counter 0.
DF7H
MSR_C7_PMON_CTR1
Package
Uncore C-box 7 perfmon counter 1.
DF8H
MSR_C7_PMON_CTR2
Package
Uncore C-box 7 perfmon counter 2.
DF9H
MSR_C7_PMON_CTR3
Package
Uncore C-box 7 perfmon counter 3.
35.10
MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY
(BASED ON INTEL® MICROARCHITECTURE CODE NAME IVY BRIDGE)
The 3rd generation Intel® Core™ processor family and the Intel® Xeon® processor E3-1200v2 product family
(based on Intel microarchitecture code name Ivy Bridge) support the MSR interfaces listed in Table 35-18, Table
35-19, Table 35-20, and Table 35-23. These processors have a CPUID signature with DisplayFamily_DisplayModel
of 06_3AH.
Table 35-23. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel®
microarchitecture code name Ivy Bridge)
Register
Address
Hex
Dec
CEH
206
Register Name
MSR_PLATFORM_INFO
Scope
Package
7:0
15:8
Bit Description
See http://biosbits.org.
Reserved.
Package
Maximum Non-Turbo Ratio (R/O)
The is the ratio of the frequency that invariant TSC runs at.
Frequency = ratio * 100 MHz.
35-172 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-23. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel®
microarchitecture code name Ivy Bridge) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
27:16
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limits for Turbo
mode is enabled, and when set to 0, indicates Programmable Ratio
Limits for Turbo mode is disabled.
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limits for Turbo mode are
programmable, and when set to 0, indicates TDP Limit for Turbo
mode is not programmable.
31:30
32
Reserved.
Package
Low Power Mode Support (LPM) (R/O)
When set to 1, indicates that LPM is supported, and when set to 0,
indicates LPM is not supported.
34:33
Package
Number of ConfigTDP Levels (R/O)
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
11: Reserved
39:35
47:40
Reserved.
Package
Maximum Efficiency Ratio (R/O)
The is the minimum ratio (maximum efficiency) that the processor
can operates, in units of 100MHz.
55:48
Package
Minimum Operating Ratio (R/O)
Contains the minimum supported
operating ratio in units of 100 MHz.
63:56
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
Reserved.
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
See http://biosbits.org.
Vol. 3C 35-173
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-23. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel®
microarchitecture code name Ivy Bridge) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power). for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified
by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions
14:11
Reserved.
15
CFG Lock (R/WO)
When set, lock bits 15:0 of this register until next reset.
24:16
Reserved.
25
C3 state auto demotion enable (R/W)
When set, the processor will conditionally demote C6/C7 requests
to C3 based on uncore auto-demote information.
26
C1 state auto demotion enable (R/W)
When set, the processor will conditionally demote C3/C6/C7
requests to C1 based on uncore auto-demote information.
27
Enable C3 undemotion (R/W)
When set, enables undemotion from demoted C3.
28
Enable C1 undemotion (R/W)
When set, enables undemotion from demoted C1.
639H
1593
63:29
Reserved.
MSR_PP0_ENERGY_STATUS Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
648H
1608
MSR_CONFIG_TDP_
NOMINAL
7:0
Package
Base TDP Ratio (R/O)
Config_TDP_Base
Base TDP level ratio to be used for this specific processor (in units
of 100 MHz).
63:8
35-174 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-23. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel®
microarchitecture code name Ivy Bridge) (Contd.)
Register
Address
Hex
Dec
649H
1609
Register Name
MSR_CONFIG_TDP_LEVEL1
Scope
Package
1610
PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
15
Reserved
23:16
Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used for this
specific processor.
31:24
Reserved
46:32
PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
Level 1.
47
Reserved
62:48
PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
Level 1.
MSR_CONFIG_TDP_LEVEL2
Reserved.
Package
14:0
64BH
1611
ConfigTDP Level 1 ratio and power level (R/O)
14:0
63
64AH
Bit Description
ConfigTDP Level 2 ratio and power level (R/O)
PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
15
Reserved
23:16
Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used for this
specific processor.
31:24
Reserved
46:32
PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
Level 2.
47
Reserved
62:48
PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
Level 2.
63
Reserved.
MSR_CONFIG_TDP_
CONTROL
Package
1:0
ConfigTDP Control (R/W)
TDP_LEVEL (RW/L)
System BIOS can program this field.
30:2
Reserved.
31
Config_TDP_Lock (RW/L)
When this bit is set, the content of this register is locked until a
reset.
63:32
64CH
1612
MSR_TURBO_ACTIVATION_
RATIO
7:0
Reserved.
Package
ConfigTDP Control (R/W)
MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8
Reserved.
Vol. 3C 35-175
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-23. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel®
microarchitecture code name Ivy Bridge) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
31
TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is locked until a
reset.
63:32
Reserved.
See Table 35-18, Table 35-19 and Table 35-20 for other MSR definitions applicable to processors with CPUID signature
06_3AH
35.10.1 MSRs In Intel® Xeon® Processor E5 v2 Product Family (Based on Ivy Bridge-E
Microarchitecture)
Table 35-24 lists model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 v2 Product
Family (based on Ivy Bridge-E microarchitecture). These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_3EH, see Table 35-1. These processors supports the MSR interfaces listed in
Table 35-18, and Table 35-24.
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture)
Register
Address
Hex
Dec
4EH
78
Register Name
MSR_PPIN_CTL
Scope
Package
0
Bit Description
Protected Processor Inventory Number Enable Control (R/W)
LockOut (R/WO)
Set 1to prevent further writes to MSR_PPIN_CTL. Writing 1 to
MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is
clear, Default is 0.
BIOS should provide an opt-in menu to enable the user to turn on
MSR_PPIN_CTL[bit 1] for privileged inventory initialization agent to
access MSR_PPIN. After reading MSR_PPIN, the privileged
inventory initialization agent should write ‘01b’ to MSR_PPIN_CTL
to disable further access to MSR_PPIN and prevent unauthorized
modification to MSR_PPIN_CTL.
1
Enable_PPIN (R/W)
If 1, enables MSR_PPIN to be accessible using RDMSR. Once set,
attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP.
If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0.
63:2
4FH
79
35-176 Vol. 3C
MSR_PPIN
Reserved.
Package
Protected Processor Inventory Number (R/O)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
63:0
Protected Processor Inventory Number (R/O)
A unique value within a given CPUID family/model/stepping
signature that a privileged inventory initialization agent can access
to identify each physical processor, when access to MSR_PPIN is
enabled. Access to MSR_PPIN is permitted only if
MSR_PPIN_CTL[bits 1:0] = ‘10b’
CEH
206
MSR_PLATFORM_INFO
Package
7:0
15:8
See http://biosbits.org.
Reserved.
Package
Maximum Non-Turbo Ratio (R/O)
The is the ratio of the frequency that invariant TSC runs at.
Frequency = ratio * 100 MHz.
22:16
23
Reserved.
Package
PPIN_CAP (R/O)
When set to 1, indicates that Protected Processor Inventory
Number (PPIN) capability can be enabled for privileged system
inventory agent to read PPIN from MSR_PPIN.
When set to 0, PPIN capability is not supported. An attempt to
access MSR_PPIN_CTL or MSR_PPIN will cause #GP.
27:24
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limits for Turbo
mode is enabled, and when set to 0, indicates Programmable Ratio
Limits for Turbo mode is disabled.
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limits for Turbo mode are
programmable, and when set to 0, indicates TDP Limit for Turbo
mode is not programmable.
30
Package
Programmable TJ OFFSET (R/O)
When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24]
is valid and writable to specify an temperature offset.
39:31
47:40
Reserved.
Package
Maximum Efficiency Ratio (R/O)
The is the minimum ratio (maximum efficiency) that the processor
can operates, in units of 100MHz.
63:48
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
Reserved.
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates.
See http://biosbits.org.
Vol. 3C 35-177
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power). for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register
specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions
14:11
Reserved.
15
CFG Lock (R/WO)
When set, lock bits 15:0 of this register until next reset.
63:16
179H
377
IA32_MCG_CAP
Reserved.
Thread
7:0
Count
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved.
23:16
MCG_EXT_CNT
24
MCG_SER_P
25
Reserved.
26
MCG_ELOG_P
63:27
17FH
383
Global Machine Check Capability (R/O)
MSR_ERROR_CONTROL
Reserved.
Package
MC Bank Error Configuration (R/W)
0
Reserved
1
MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info in bits
36:32.
63:2
35-178 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address
Hex
Dec
1A2H
418
Register Name
MSR_
TEMPERATURE_TARGET
Scope
Bit Description
Package
15:0
Reserved.
23:16
Temperature Target (RO)
The minimum temperature at which PROCHOT# will be asserted.
The value is degree C.
27:24
TCC Activation Offset (R/W)
Specifies a temperature offset in degrees C from the temperature
target (bits 23:16). PROCHOT# will assert at the offset target
temperature. Write is permitted only MSR_PLATFORM_INFO.[30] is
set.
63:28
1AEH
430
MSR_TURBO_RATIO_LIMIT
1
Reserved.
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
15:8
Package
Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10core active.
23:16
Package
31:24
Package
Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
63:32
Reserved
285H
645
IA32_MC5_CTL2
Package
See Table 35-2.
286H
646
IA32_MC6_CTL2
Package
See Table 35-2.
287H
647
IA32_MC7_CTL2
Package
See Table 35-2.
288H
648
IA32_MC8_CTL2
Package
See Table 35-2.
289H
649
IA32_MC9_CTL2
Package
See Table 35-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 35-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 35-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 35-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 35-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 35-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 35-2.
290H
656
IA32_MC16_CTL2
Package
See Table 35-2.
291H
657
IA32_MC17_CTL2
Package
See Table 35-2.
292H
658
IA32_MC18_CTL2
Package
See Table 35-2.
293H
659
IA32_MC19_CTL2
Package
See Table 35-2.
Vol. 3C 35-179
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
294H
660
IA32_MC20_CTL2
Package
See Table 35-2.
295H
661
IA32_MC21_CTL2
Package
See Table 35-2.
296H
662
IA32_MC22_CTL2
Package
See Table 35-2.
297H
663
IA32_MC23_CTL2
Package
See Table 35-2.
298H
664
IA32_MC24_CTL2
Package
See Table 35-2.
299H
665
IA32_MC25_CTL2
Package
See Table 35-2.
29AH
666
IA32_MC26_CTL2
Package
See Table 35-2.
29BH
667
IA32_MC27_CTL2
Package
See Table 35-2.
29CH
668
IA32_MC28_CTL2
Package
See Table 35-2.
414H
1044
IA32_MC5_CTL
Package
415H
1045
IA32_MC5_STATUS
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
416H
1046
IA32_MC5_ADDR
Package
417H
1047
IA32_MC5_MISC
Package
418H
1048
IA32_MC6_CTL
Package
419H
1049
IA32_MC6_STATUS
Package
41AH
1050
IA32_MC6_ADDR
Package
41BH
1051
IA32_MC6_MISC
Package
41CH
1052
IA32_MC7_CTL
Package
41DH
1053
IA32_MC7_STATUS
Package
41EH
1054
IA32_MC7_ADDR
Package
41FH
1055
IA32_MC7_MISC
Package
420H
1056
IA32_MC8_CTL
Package
421H
1057
IA32_MC8_STATUS
Package
422H
1058
IA32_MC8_ADDR
Package
423H
1059
IA32_MC8_MISC
Package
424H
1060
IA32_MC9_CTL
Package
425H
1061
IA32_MC9_STATUS
Package
426H
1062
IA32_MC9_ADDR
Package
427H
1063
IA32_MC9_MISC
Package
428H
1064
IA32_MC10_CTL
Package
429H
1065
IA32_MC10_STATUS
Package
42AH
1066
IA32_MC10_ADDR
Package
42BH
1067
IA32_MC10_MISC
Package
42CH
1068
IA32_MC11_CTL
Package
35-180 Vol. 3C
Bank MC5 reports MC error from the Intel QPI module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC6 reports MC error from the integrated I/O module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC7 and MC 8 report MC error from the two home agents.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC7 and MC 8 report MC error from the two home agents.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Hex
Dec
42DH
1069
IA32_MC11_STATUS
Package
42EH
1070
IA32_MC11_ADDR
Package
42FH
1071
IA32_MC11_MISC
Package
430H
1072
IA32_MC12_CTL
Package
431H
1073
IA32_MC12_STATUS
Package
432H
1074
IA32_MC12_ADDR
Package
433H
1075
IA32_MC12_MISC
Package
434H
1076
IA32_MC13_CTL
Package
435H
1077
IA32_MC13_STATUS
Package
436H
1078
IA32_MC13_ADDR
Package
437H
1079
IA32_MC13_MISC
Package
438H
1080
IA32_MC14_CTL
Package
439H
1081
IA32_MC14_STATUS
Package
43AH
1082
IA32_MC14_ADDR
Package
43BH
1083
IA32_MC14_MISC
Package
43CH
1084
IA32_MC15_CTL
Package
43DH
1085
IA32_MC15_STATUS
Package
43EH
1086
IA32_MC15_ADDR
Package
43FH
1087
IA32_MC15_MISC
Package
440H
1088
IA32_MC16_CTL
Package
441H
1089
IA32_MC16_STATUS
Package
442H
1090
IA32_MC16_ADDR
Package
443H
1091
IA32_MC16_MISC
Package
444H
1092
IA32_MC17_CTL
Package
445H
1093
IA32_MC17_STATUS
Package
446H
1094
IA32_MC17_ADDR
Package
447H
1095
IA32_MC17_MISC
Package
448H
1096
IA32_MC18_CTL
Package
449H
1097
IA32_MC18_STATUS
Package
44AH
1098
IA32_MC18_ADDR
Package
44BH
1099
IA32_MC18_MISC
Package
44CH
1100
IA32_MC19_CTL
Package
44DH
1101
IA32_MC19_STATUS
Package
44EH
1102
IA32_MC19_ADDR
Package
44FH
1103
IA32_MC19_MISC
Package
Bit Description
Bank MC11 reports MC error from a specific channel of the
integrated memory controller.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC17 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC18 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC19 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
Vol. 3C 35-181
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
450H
1104
IA32_MC20_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
451H
1105
IA32_MC20_STATUS
Package
452H
1106
IA32_MC20_ADDR
Package
Bank MC20 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
453H
1107
IA32_MC20_MISC
Package
454H
1108
IA32_MC21_CTL
Package
455H
1109
IA32_MC21_STATUS
Package
456H
1110
IA32_MC21_ADDR
Package
457H
1111
IA32_MC21_MISC
Package
458H
1112
IA32_MC22_CTL
Package
459H
1113
IA32_MC22_STATUS
Package
45AH
1114
IA32_MC22_ADDR
Package
45BH
1115
IA32_MC22_MISC
Package
45CH
1116
IA32_MC23_CTL
Package
45DH
1117
IA32_MC23_STATUS
Package
45EH
1118
IA32_MC23_ADDR
Package
45FH
1119
IA32_MC23_MISC
Package
460H
1120
IA32_MC24_CTL
Package
461H
1121
IA32_MC24_STATUS
Package
462H
1122
IA32_MC24_ADDR
Package
463H
1123
IA32_MC24_MISC
Package
464H
1124
IA32_MC25_CTL
Package
465H
1125
IA32_MC25_STATUS
Package
466H
1126
IA32_MC25_ADDR
Package
467H
1127
IA32_MC2MISC
Package
468H
1128
IA32_MC26_CTL
Package
469H
1129
IA32_MC26_STATUS
Package
46AH
1130
IA32_MC26_ADDR
Package
46BH
1131
IA32_MC26_MISC
Package
46CH
1132
IA32_MC27_CTL
Package
46DH
1133
IA32_MC27_STATUS
Package
46EH
1134
IA32_MC27_ADDR
Package
46FH
1135
IA32_MC27_MISC
Package
35-182 Vol. 3C
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC21 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC22 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC23 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC24 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC25 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC26 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC27 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
470H
1136
IA32_MC28_CTL
Package
471H
1137
IA32_MC28_STATUS
Package
472H
1138
IA32_MC28_ADDR
Package
473H
1139
IA32_MC28_MISC
Package
613H
1555
MSR_PKG_PERF_STATUS
Package
Package RAPL Perf Status (R/O)
618H
1560
MSR_DRAM_POWER_LIMIT
Package
DRAM RAPL Power Limit Control (R/W)
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC28 reports MC error from a specific CBo (core broadcast)
and its corresponding slice of L3.
See Section 14.9.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_
STATUS
Package
DRAM Energy Status (R/O)
See Section 14.9.5, “DRAM RAPL Domain.”
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O) See Section 14.9.5,
“DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
639H
1593
MSR_PP0_ENERGY_STATU
S
Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
See Table 35-18, for other MSR definitions applicable to Intel Xeon processor E5 v2 with CPUID signature 06_3EH
35.10.2 Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family
Intel® Xeon® processor E7 v2 family (based on Ivy Bridge-E microarchitecture) with CPUID
DisplayFamily_DisplayModel signature 06_3EH supports the MSR interfaces listed in Table 35-18, Table 35-24, and
Table 35-25.
Table 35-25. Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel
Signature 06_3EH
Register
Address
Hex
Dec
3AH
58
Register Name
IA32_FEATURE_CONTROL
Scope
Thread
Bit Description
Control Features in Intel 64 Processor (R/W)
See Table 35-2.
179H
377
0
Lock (R/WL)
1
Enable VMX inside SMX operation (R/WL)
2
Enable VMX outside SMX operation (R/WL)
14:8
SENTER local functions enables (R/WL)
15
SENTER global functions enable (R/WL)
63:16
Reserved.
IA32_MCG_CAP
Thread
Global Machine Check Capability (R/O)
7:0
Count
8
MCG_CTL_P
Vol. 3C 35-183
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-25. Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel
Signature 06_3EH
Register
Address
Hex
17AH
1AEH
Register Name
Scope
Bit Description
Dec
378
430
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved.
23:16
MCG_EXT_CNT
24
MCG_SER_P
63:25
Reserved.
IA32_MCG_STATUS
Thread
(R/W0)
0
RIPV
1
EIPV
2
MCIP
3
LMCE signaled
63:4
Reserved.
MSR_TURBO_RATIO_LIMIT1 Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
15:8
Package
Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10core active.
23:16
Package
Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
31:24
Package
Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
39:32
Package
Maximum Ratio Limit for 13C
Maximum turbo ratio limit of 13 core active.
47:40
Package
Maximum Ratio Limit for 14C
Maximum turbo ratio limit of 14 core active.
55:48
Package
Maximum Ratio Limit for 15C
Maximum turbo ratio limit of 15 core active.
62:56
63
Reserved
Package
Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).
29DH
669
IA32_MC29_CTL2
Package
See Table 35-2.
29EH
670
IA32_MC30_CTL2
Package
See Table 35-2.
29FH
671
IA32_MC31_CTL2
Package
See Table 35-2.
35-184 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-25. Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel
Signature 06_3EH
Register
Address
Hex
Dec
3F1H
1009
41BH
1051
Register Name
MSR_PEBS_ENABLE
Scope
Thread
Bit Description
See Section 18.8.1.1, “Processor Event Based Sampling (PEBS).”
0
Enable PEBS on IA32_PMC0. (R/W)
1
Enable PEBS on IA32_PMC1. (R/W)
2
Enable PEBS on IA32_PMC2. (R/W)
3
Enable PEBS on IA32_PMC3. (R/W)
31:4
Reserved.
32
Enable Load Latency on IA32_PMC0. (R/W)
33
Enable Load Latency on IA32_PMC1. (R/W)
34
Enable Load Latency on IA32_PMC2. (R/W)
35
Enable Load Latency on IA32_PMC3. (R/W)
63:36
Reserved.
IA32_MC6_MISC
Package
Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4
5:0
Recoverable Address LSB
8:6
Address Mode
15:9
Reserved
31:16
PCI Express Requestor ID
39:32
PCI Express Segment Number
63:32
Reserved
474H
1140
IA32_MC29_CTL
Package
475H
1141
IA32_MC29_STATUS
Package
476H
1142
IA32_MC29_ADDR
Package
477H
1143
IA32_MC29_MISC
Package
478H
1144
IA32_MC30_CTL
Package
479H
1145
IA32_MC30_STATUS
Package
47AH
1146
IA32_MC30_ADDR
Package
47BH
1147
IA32_MC30_MISC
Package
47CH
1148
IA32_MC31_CTL
Package
47DH
1149
IA32_MC31_STATUS
Package
47EH
1150
IA32_MC31_ADDR
Package
47FH
1147
IA32_MC31_MISC
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC29 reports MC error from a specific CBo (core broadcast) and
its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC30 reports MC error from a specific CBo (core broadcast) and
its corresponding slice of L3.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC31 reports MC error from a specific CBo (core broadcast) and
its corresponding slice of L3.
See Table 35-18, Table 35-24 for other MSR definitions applicable to Intel Xeon processor E7 v2 with CPUID signature 06_3AH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
Vol. 3C 35-185
MODEL-SPECIFIC REGISTERS (MSRS)
35.10.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
Intel Xeon Processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture. The MSR-based
uncore PMU interfaces are listed in Table 35-22 and Table 35-26. For complete detail of the uncore PMU, refer to
Intel Xeon Processor E5 v2 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID
signature with DisplayFamily_DisplayModel of 06_3EH.
Table 35-26. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
C00H
MSR_PMON_GLOBAL_CTL
Package
Uncore perfmon per-socket global control.
C01H
MSR_PMON_GLOBAL_STATUS
Package
Uncore perfmon per-socket global status.
C06H
MSR_PMON_GLOBAL_CONFIG
Package
Uncore perfmon per-socket global configuration.
C15H
MSR_U_PMON_BOX_STATUS
Package
Uncore U-box perfmon U-box wide status.
C35H
MSR_PCU_PMON_BOX_STATUS
Package
Uncore PCU perfmon box wide status.
D1AH
MSR_C0_PMON_BOX_FILTER1
Package
Uncore C-box 0 perfmon box wide filter1.
D3AH
MSR_C1_PMON_BOX_FILTER1
Package
Uncore C-box 1 perfmon box wide filter1.
D5AH
MSR_C2_PMON_BOX_FILTER1
Package
Uncore C-box 2 perfmon box wide filter1.
D7AH
MSR_C3_PMON_BOX_FILTER1
Package
Uncore C-box 3 perfmon box wide filter1.
D9AH
MSR_C4_PMON_BOX_FILTER1
Package
Uncore C-box 4 perfmon box wide filter1.
DBAH
MSR_C5_PMON_BOX_FILTER1
Package
Uncore C-box 5 perfmon box wide filter1.
DDAH
MSR_C6_PMON_BOX_FILTER1
Package
Uncore C-box 6 perfmon box wide filter1.
DFAH
MSR_C7_PMON_BOX_FILTER1
Package
Uncore C-box 7 perfmon box wide filter1.
E04H
MSR_C8_PMON_BOX_CTL
Package
Uncore C-box 8 perfmon local box wide control.
E10H
MSR_C8_PMON_EVNTSEL0
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 0.
E11H
MSR_C8_PMON_EVNTSEL1
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 1.
E12H
MSR_C8_PMON_EVNTSEL2
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 2.
E13H
MSR_C8_PMON_EVNTSEL3
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 3.
E14H
MSR_C8_PMON_BOX_FILTER
Package
Uncore C-box 8 perfmon box wide filter.
E16H
MSR_C8_PMON_CTR0
Package
Uncore C-box 8 perfmon counter 0.
E17H
MSR_C8_PMON_CTR1
Package
Uncore C-box 8 perfmon counter 1.
E18H
MSR_C8_PMON_CTR2
Package
Uncore C-box 8 perfmon counter 2.
E19H
MSR_C8_PMON_CTR3
Package
Uncore C-box 8 perfmon counter 3.
E1AH
MSR_C8_PMON_BOX_FILTER1
Package
Uncore C-box 8 perfmon box wide filter1.
E24H
MSR_C9_PMON_BOX_CTL
Package
Uncore C-box 9 perfmon local box wide control.
E30H
MSR_C9_PMON_EVNTSEL0
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 0.
E31H
MSR_C9_PMON_EVNTSEL1
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 1.
E32H
MSR_C9_PMON_EVNTSEL2
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 2.
E33H
MSR_C9_PMON_EVNTSEL3
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 3.
E34H
MSR_C9_PMON_BOX_FILTER
Package
Uncore C-box 9 perfmon box wide filter.
E36H
MSR_C9_PMON_CTR0
Package
Uncore C-box 9 perfmon counter 0.
E37H
MSR_C9_PMON_CTR1
Package
Uncore C-box 9 perfmon counter 1.
35-186 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-26. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
E38H
MSR_C9_PMON_CTR2
Package
Uncore C-box 9 perfmon counter 2.
E39H
MSR_C9_PMON_CTR3
Package
Uncore C-box 9 perfmon counter 3.
E3AH
MSR_C9_PMON_BOX_FILTER1
Package
Uncore C-box 9 perfmon box wide filter1.
E44H
MSR_C10_PMON_BOX_CTL
Package
Uncore C-box 10 perfmon local box wide control.
E50H
MSR_C10_PMON_EVNTSEL0
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 0.
E51H
MSR_C10_PMON_EVNTSEL1
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 1.
E52H
MSR_C10_PMON_EVNTSEL2
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 2.
E53H
MSR_C10_PMON_EVNTSEL3
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 3.
E54H
MSR_C10_PMON_BOX_FILTER
Package
Uncore C-box 10 perfmon box wide filter.
E56H
MSR_C10_PMON_CTR0
Package
Uncore C-box 10 perfmon counter 0.
E57H
MSR_C10_PMON_CTR1
Package
Uncore C-box 10 perfmon counter 1.
E58H
MSR_C10_PMON_CTR2
Package
Uncore C-box 10 perfmon counter 2.
E59H
MSR_C10_PMON_CTR3
Package
Uncore C-box 10 perfmon counter 3.
E5AH
MSR_C10_PMON_BOX_FILTER1
Package
Uncore C-box 10 perfmon box wide filter1.
E64H
MSR_C11_PMON_BOX_CTL
Package
Uncore C-box 11 perfmon local box wide control.
E70H
MSR_C11_PMON_EVNTSEL0
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 0.
E71H
MSR_C11_PMON_EVNTSEL1
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 1.
E72H
MSR_C11_PMON_EVNTSEL2
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 2.
E73H
MSR_C11_PMON_EVNTSEL3
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 3.
E74H
MSR_C11_PMON_BOX_FILTER
Package
Uncore C-box 11 perfmon box wide filter.
E76H
MSR_C11_PMON_CTR0
Package
Uncore C-box 11 perfmon counter 0.
E77H
MSR_C11_PMON_CTR1
Package
Uncore C-box 11 perfmon counter 1.
E78H
MSR_C11_PMON_CTR2
Package
Uncore C-box 11 perfmon counter 2.
E79H
MSR_C11_PMON_CTR3
Package
Uncore C-box 11 perfmon counter 3.
E7AH
MSR_C11_PMON_BOX_FILTER1
Package
Uncore C-box 11 perfmon box wide filter1.
E84H
MSR_C12_PMON_BOX_CTL
Package
Uncore C-box 12 perfmon local box wide control.
E90H
MSR_C12_PMON_EVNTSEL0
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 0.
E91H
MSR_C12_PMON_EVNTSEL1
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 1.
E92H
MSR_C12_PMON_EVNTSEL2
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 2.
E93H
MSR_C12_PMON_EVNTSEL3
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 3.
E94H
MSR_C12_PMON_BOX_FILTER
Package
Uncore C-box 12 perfmon box wide filter.
E96H
MSR_C12_PMON_CTR0
Package
Uncore C-box 12 perfmon counter 0.
E97H
MSR_C12_PMON_CTR1
Package
Uncore C-box 12 perfmon counter 1.
E98H
MSR_C12_PMON_CTR2
Package
Uncore C-box 12 perfmon counter 2.
E99H
MSR_C12_PMON_CTR3
Package
Uncore C-box 12 perfmon counter 3.
E9AH
MSR_C12_PMON_BOX_FILTER1
Package
Uncore C-box 12 perfmon box wide filter1.
EA4H
MSR_C13_PMON_BOX_CTL
Package
Uncore C-box 13 perfmon local box wide control.
Vol. 3C 35-187
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-26. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register
Address
Hex
Scope
Register Name
Bit Description
Dec
EB0H
MSR_C13_PMON_EVNTSEL0
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 0.
EB1H
MSR_C13_PMON_EVNTSEL1
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 1.
EB2H
MSR_C13_PMON_EVNTSEL2
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 2.
EB3H
MSR_C13_PMON_EVNTSEL3
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 3.
EB4H
MSR_C13_PMON_BOX_FILTER
Package
Uncore C-box 13 perfmon box wide filter.
EB6H
MSR_C13_PMON_CTR0
Package
Uncore C-box 13 perfmon counter 0.
EB7H
MSR_C13_PMON_CTR1
Package
Uncore C-box 13 perfmon counter 1.
EB8H
MSR_C13_PMON_CTR2
Package
Uncore C-box 13 perfmon counter 2.
EB9H
MSR_C13_PMON_CTR3
Package
Uncore C-box 13 perfmon counter 3.
EBAH
MSR_C13_PMON_BOX_FILTER1
Package
Uncore C-box 13 perfmon box wide filter1.
EC4H
MSR_C14_PMON_BOX_CTL
Package
Uncore C-box 14 perfmon local box wide control.
ED0H
MSR_C14_PMON_EVNTSEL0
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 0.
ED1H
MSR_C14_PMON_EVNTSEL1
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 1.
ED2H
MSR_C14_PMON_EVNTSEL2
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 2.
ED3H
MSR_C14_PMON_EVNTSEL3
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 3.
ED4H
MSR_C14_PMON_BOX_FILTER
Package
Uncore C-box 14 perfmon box wide filter.
ED6H
MSR_C14_PMON_CTR0
Package
Uncore C-box 14 perfmon counter 0.
ED7H
MSR_C14_PMON_CTR1
Package
Uncore C-box 14 perfmon counter 1.
ED8H
MSR_C14_PMON_CTR2
Package
Uncore C-box 14 perfmon counter 2.
ED9H
MSR_C14_PMON_CTR3
Package
Uncore C-box 14 perfmon counter 3.
EDAH
MSR_C14_PMON_BOX_FILTER1
Package
Uncore C-box 14 perfmon box wide filter1.
35.11
MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS (BASED ON
HASWELL MICROARCHITECTURE)
The 4th generation Intel® Core™ processor family and Intel® Xeon® processor E3-1200v3 product family (based
on Haswell microarchitecture), with CPUID DisplayFamily_DisplayModel signature 06_3CH/06_45H/06_46H,
support the MSR interfaces listed in Table 35-18, Table 35-19, Table 35-20, and Table 35-27. For an MSR listed in
Table 35-18 that also appears in Table 35-27, Table 35-27 supercede Table 35-18.
The MSRs listed in Table 35-27 also apply to processors based on Haswell-E microarchitecture (see Section 35.12).
Table 35-27. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address
Hex
Dec
3BH
59
Register Name
IA32_TSC_ADJUST
Scope
THREAD
Bit Description
Per-Logical-Processor TSC ADJUST (R/W)
See Table 35-2.
CEH
206
MSR_PLATFORM_INFO
7:0
35-188 Vol. 3C
Package
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-27. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
15:8
Package
Maximum Non-Turbo Ratio (R/O)
The is the ratio of the frequency that invariant TSC runs at.
Frequency = ratio * 100 MHz.
27:16
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limits for Turbo
mode is enabled, and when set to 0, indicates Programmable Ratio
Limits for Turbo mode is disabled.
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limits for Turbo mode are
programmable, and when set to 0, indicates TDP Limit for Turbo
mode is not programmable.
31:30
32
Reserved.
Package
Low Power Mode Support (LPM) (R/O)
When set to 1, indicates that LPM is supported, and when set to 0,
indicates LPM is not supported.
34:33
Package
Number of ConfigTDP Levels (R/O)
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
11: Reserved
39:35
47:40
Reserved.
Package
Maximum Efficiency Ratio (R/O)
The is the minimum ratio (maximum efficiency) that the processor
can operates, in units of 100MHz.
55:48
Package
Minimum Operating Ratio (R/O)
Contains the minimum supported
operating ratio in units of 100 MHz.
63:56
186H
390
IA32_PERFEVTSEL0
Reserved.
THREAD
Performance Event Select for Counter 0 (R/W)
Supports all fields described inTable 35-2 and the fields below.
32
IN_TX: see Section 18.11.5.1
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results
187H
391
IA32_PERFEVTSEL1
THREAD
Performance Event Select for Counter 1 (R/W)
Supports all fields described inTable 35-2 and the fields below.
32
IN_TX: see Section 18.11.5.1
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results
188H
392
IA32_PERFEVTSEL2
THREAD
Performance Event Select for Counter 2 (R/W)
Supports all fields described inTable 35-2 and the fields below.
Vol. 3C 35-189
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-27. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
32
IN_TX: see Section 18.11.5.1
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results
33
IN_TXCP: see Section 18.11.5.1
When IN_TXCP=1 & IN_TX=1 and in sampling, spurious PMI may
occur and transactions may continuously abort near overflow
conditions. Software should favor using IN_TXCP for counting over
sampling. If sampling, software should use large “sample-after”
value after clearing the counter configured to use IN_TXCP and
also always reset the counter even when no overflow condition
was reported.
189H
393
IA32_PERFEVTSEL3
THREAD
Performance Event Select for Counter 3 (R/W)
Supports all fields described inTable 35-2 and the fields below.
32
IN_TX: see Section 18.11.5.1
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results
1C8H
1D9H
456
473
MSR_LBR_SELECT
Thread
Last Branch Record Filtering Select Register (R/W)
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
9
EN_CALL_STACK
63:9
Reserved.
IA32_DEBUGCTL
Thread
Debug Control (R/W)
See Table 35-2.
35-190 Vol. 3C
0
LBR: Last Branch Record
1
BTF
5:2
Reserved.
6
TR: Branch Trace
7
BTS: Log Branch Trace Message to BTS buffer
8
BTINT
9
BTS_OFF_OS
10
BTS_OFF_USER
11
FREEZE_LBR_ON_PMI
12
FREEZE_PERFMON_ON_PMI
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-27. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address
Hex
491H
Register Name
Scope
Bit Description
Dec
1169
13
ENABLE_UNCORE_PMI
14
FREEZE_WHILE_SMM
15
RTM_DEBUG
63:15
Reserved.
IA32_VMX_VMFUNC
THREAD
Capability Reporting Register of VM-function Controls (R/O)
See Table 35-2
60BH
1548
MSR_PKGC_IRTL1
Package
Package C6/C7 Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit used by the
processor to manage transition to package C6 or C7 state. The
latency programmed in this register is for the shorter-latency sub
C-states used by an MWAIT hint to C6 or C7 state.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C6 or C7 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings.
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
60CH
1548
MSR_PKGC_IRTL2
Reserved.
Package
Package C6/C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit used by the
processor to manage transition to package C6 or C7 state. The
latency programmed in this register is for the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C6 or C7 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings.
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
Reserved.
Vol. 3C 35-191
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-27. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address
Hex
Dec
613H
1555
Register Name
MSR_PKG_PERF_STATUS
Scope
Package
Bit Description
PKG Perf Status (R/O)
See Section 14.9.3, “Package RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_
STATUS
Package
DRAM Energy Status (R/O)
See Section 14.9.5, “DRAM RAPL Domain.”
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O) See Section 14.9.5,
“DRAM RAPL Domain.”
648H
1608
MSR_CONFIG_TDP_
NOMINAL
Package
Base TDP Ratio (R/O)
7:0
Config_TDP_Base
Base TDP level ratio to be used for this specific processor (in units
of 100 MHz).
63:8
649H
64AH
64BH
1609
1610
1611
MSR_CONFIG_TDP_LEVEL1
Reserved.
Package
ConfigTDP Level 1 ratio and power level (R/O)
14:0
PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
15
Reserved
23:16
Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used for this
specific processor.
31:24
Reserved
46:32
PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
Level 1.
62:47
PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
Level 1.
63
Reserved.
MSR_CONFIG_TDP_LEVEL2
Package
ConfigTDP Level 2 ratio and power level (R/O)
14:0
PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
15
Reserved
23:16
Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used for this
specific processor.
31:24
Reserved
46:32
PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
Level 2.
62:47
PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
Level 2.
63
Reserved.
MSR_CONFIG_TDP_
CONTROL
1:0
Package
ConfigTDP Control (R/W)
TDP_LEVEL (RW/L)
System BIOS can program this field.
30:2
35-192 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-27. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
31
Config_TDP_Lock (RW/L)
When this bit is set, the content of this register is locked until a
reset.
63:32
64CH
1612
Reserved.
MSR_TURBO_ACTIVATION_
RATIO
Package
7:0
ConfigTDP Control (R/W)
MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8
Reserved.
31
TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is locked until a
reset.
63:32
C80H
3200
Reserved.
IA32_DEBUG_INTERFACE
Package
Silicon Debug Feature Control (R/W)
See Table 35-2.
35.11.1 MSRs in 4th Generation Intel® Core™ Processor Family (based on Haswell
Microarchitecture)
Table 35-28 lists model-specific registers (MSRs) that are specific to 4th generation Intel® Core™ processor family
and Intel® Xeon® processor E3-1200 v3 product family (based on Haswell microarchitecture). These processors
have a CPUID signature with DisplayFamily_DisplayModel of 06_3CH/06_45H/06_46H, see Table 35-1.
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture)
Register
Address
Hex
Dec
E2H
226
Register Name
MSR_PKG_CST_CONFIG_
CONTROL
Scope
Core
Bit Description
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI Cstates.
See http://biosbits.org.
Vol. 3C 35-193
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
3:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
Package C states C7 are not available to processor with signature
06_3CH
17DH
390
9:4
Reserved
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved
15
CFG Lock (R/WO)
24:16
Reserved
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
63:29
Reserved
MSR_SMM_MCA_CAP
THREAD
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in
SMM.
57:0
Reserved
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is
supported and the MSR_SMM_FEATURE_CONTROL is supported.
59
Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported
and the MSR_SMM_DELAYED is supported.
63:60
1ADH
429
MSR_TURBO_RATIO_LIMIT
Reserved
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
35-194 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32
391H
392H
394H
395H
396H
3B0H
913
914
916
917
918
946
MSR_UNC_PERF_GLOBAL_
CTRL
Reserved.
Package
Uncore PMU global control
0
Core 0 select
1
Core 1 select
2
Core 2 select
3
Core 3 select
18:4
Reserved.
29
Enable all uncore counters
30
Enable wake on PMI
31
Enable Freezing counter when overflow
63:32
Reserved.
MSR_UNC_PERF_GLOBAL_
STATUS
Package
Uncore PMU main status
0
Fixed counter overflowed
1
An ARB counter overflowed
2
Reserved
3
A CBox counter overflowed (on any slice)
63:4
Reserved.
MSR_UNC_PERF_FIXED_
CTRL
Package
Uncore fixed counter control (R/W)
19:0
Reserved
20
Enable overflow propagation
21
Reserved
22
Enable counting
63:23
Reserved.
MSR_UNC_PERF_FIXED_
CTR
Package
Uncore fixed counter
47:0
Current count
63:48
Reserved.
MSR_UNC_CBO_CONFIG
Package
Uncore C-Box configuration information (R/O)
3:0
Encoded number of C-Box, derive value by “-1“
63:4
Reserved.
MSR_UNC_ARB_PERFCTR0
Package
Uncore Arb unit, performance counter 0
Vol. 3C 35-195
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
3B1H
947
MSR_UNC_ARB_PERFCTR1
Package
Uncore Arb unit, performance counter 1
3B2H
944
MSR_UNC_ARB_
PERFEVTSEL0
Package
Uncore Arb unit, counter 0 event select MSR
3B3H
945
MSR_UNC_ARB_
PERFEVTSEL1
Package
Uncore Arb unit, counter 1 event select MSR
391H
913
MSR_UNC_PERF_GLOBAL_
CTRL
Package
Uncore PMU global control
395H
917
0
Core 0 select
1
Core 1 select
2
Core 2 select
3
Core 3 select
18:4
Reserved.
29
Enable all uncore counters
30
Enable wake on PMI
31
Enable Freezing counter when overflow
63:32
Reserved.
MSR_UNC_PERF_FIXED_
CTR
Package
Uncore fixed counter
47:0
Current count
63:48
Reserved.
3B3H
945
MSR_UNC_ARB_
PERFEVTSEL1
Package
Uncore Arb unit, counter 1 event select MSR
4E0H
1248
MSR_SMM_FEATURE_CONTR
OL
Package
Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible only while in
SMM.
0
Lock (SMM-RWO)
When set to ‘1’ locks this register from further changes
1
Reserved
2
SMM_Code_Chk_En (SMM-RW)
This control bit is available only if MSR_SMM_MCA_CAP[58] == 1.
When set to ‘0’ (default) none of the logical processors are
prevented from executing SMM code outside the ranges defined
by the SMRR.
When set to ‘1’ any logical processor in the package that attempts
to execute SMM code not within the ranges defined by the SMRR
will assert an unrecoverable MCE.
63:3
4E2H
1250
MSR_SMM_DELAYED
Reserved
Package
SMM Delayed (SMM-RO)
Reports the interruptible state of all logical processors in the
package. Available only while in SMM and
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
35-196 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
N-1:0
LOG_PROC_STATE (SMM-RO)
Each bit represents a logical processor of its state in a long flow of
internal operation which delays servicing an interrupt. The
corresponding bit will be set at the start of long events such as:
Microcode Update Load, C6, WBINVD, Ratio Change, Throttle.
The bit is automatically cleared at the end of each long event. The
reset value of this field is 0.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N
4E3H
1251
MSR_SMM_BLOCKED
Reserved
Package
SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in the package.
Available only while in SMM.
N-1:0
LOG_PROC_STATE (SMM-RO)
Each bit represents a logical processor of its blocked state to
service an SMI. The corresponding bit will be set if the logical
processor is in one of the following states: Wait For SIPI or
SENTER Sleep.
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N
606H
1542
Reserved
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
3:0
Package
Power Units
See Section 14.9.1, “RAPL Interfaces.”
7:4
Package
Reserved
12:8
Package
Energy Status Units
Energy related information (in Joules) is based on the multiplier,
1/2^ESU; where ESU is an unsigned integer represented by bits
12:8. Default value is 0EH (or 61 micro-joules)
15:13
Package
Reserved
19:16
Package
Time Units
See Section 14.9.1, “RAPL Interfaces.”
63:20
639H
1593
MSR_PP0_ENERGY_STATUS
Reserved
Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
640H
1600
MSR_PP1_POWER_LIMIT
Package
PP1 RAPL Power Limit Control (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
641H
1601
MSR_PP1_ENERGY_STATUS
Package
PP1 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
642H
1602
MSR_PP1_POLICY
Package
PP1 Balance Policy (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
Vol. 3C 35-197
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Dec
690H
1680
Register Name
MSR_CORE_PERF_LIMIT_REA
SONS
0
Scope
Package
Bit Description
Indicator of Frequency Clipping in Processor Cores (R/W)
(frequency refers to processor core frequency)
PROCHOT Status (R0)
When set, processor core frequency is reduced below the
operating system request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
3:2
Reserved.
4
Graphics Driver Status (R0)
When set, frequency is reduced below the operating system
request due to Processor Graphics driver override.
5
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system
request because the processor has detected that utilization is
low.
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
9
Core Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to domain-level power limiting.
10
Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
11
Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
12
Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system
request due to multi-core turbo limits.
13
Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system
request due to Turbo transition attenuation. This prevents
performance degradation due to frequent operating ratio
changes.
15:14
35-198 Vol. 3C
Reserved
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18
Reserved.
20
Graphics Driver Log
When set, indicates that the Graphics Driver Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-Based
Frequency Control Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26
Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Vol. 3C 35-199
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
6B0H
1712
63:30
Reserved.
MSR_GRAPHICS_PERF_LIMIT_ Package
REASONS
Indicator of Frequency Clipping in the Processor Graphics
(R/W)
(frequency refers to processor graphics frequency)
0
PROCHOT Status (R0)
When set, frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
3:2
Reserved.
4
Graphics Driver Status (R0)
When set, frequency is reduced below the operating system
request due to Processor Graphics driver override.
5
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system
request because the processor has detected that utilization is low
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
9
Graphics Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to domain-level power limiting.
10
Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
11
Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
15:12
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
35-200 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18
Reserved.
20
Graphics Driver Log
When set, indicates that the Graphics Driver Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-Based
Frequency Control Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26
Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Vol. 3C 35-201
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Dec
63:30
6B1H
Bit Description
1713
MSR_RING_PERF_LIMIT_REA
SONS
0
Reserved.
Package
Indicator of Frequency Clipping in the Ring Interconnect (R/W)
(frequency refers to ring interconnect in the uncore)
PROCHOT Status (R0)
When set, frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
5:2
Reserved.
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
9
Reserved.
10
Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
11
Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
15:12
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18
Reserved.
20
Graphics Driver Log
When set, indicates that the Graphics Driver Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
35-202 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-Based
Frequency Control Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26
Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30
Reserved.
700H
1792
MSR_UNC_CBO_0_
PERFEVTSEL0
Package
Uncore C-Box 0, counter 0 event select MSR
701H
1793
MSR_UNC_CBO_0_
PERFEVTSEL1
Package
Uncore C-Box 0, counter 1 event select MSR
706H
1798
MSR_UNC_CBO_0_PERFCTR0
Package
Uncore C-Box 0, performance counter 0
707H
1799
MSR_UNC_CBO_0_PERFCTR1
Package
Uncore C-Box 0, performance counter 1
Vol. 3C 35-203
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
Register
Address
Scope
Register Name
Bit Description
Hex
Dec
710H
1808
MSR_UNC_CBO_1_
PERFEVTSEL0
Package
Uncore C-Box 1, counter 0 event select MSR
711H
1809
MSR_UNC_CBO_1_
PERFEVTSEL1
Package
Uncore C-Box 1, counter 1 event select MSR
716H
1814
MSR_UNC_CBO_1_PERFCTR0
Package
Uncore C-Box 1, performance counter 0
717H
1815
MSR_UNC_CBO_1_PERFCTR1
Package
Uncore C-Box 1, performance counter 1
720H
1824
MSR_UNC_CBO_2_
PERFEVTSEL0
Package
Uncore C-Box 2, counter 0 event select MSR
721H
1824
MSR_UNC_CBO_2_
PERFEVTSEL1
Package
Uncore C-Box 2, counter 1 event select MSR
726H
1830
MSR_UNC_CBO_2_PERFCTR0
Package
Uncore C-Box 2, performance counter 0
727H
1831
MSR_UNC_CBO_2_PERFCTR1
Package
Uncore C-Box 2, performance counter 1
730H
1840
MSR_UNC_CBO_3_
PERFEVTSEL0
Package
Uncore C-Box 3, counter 0 event select MSR
731H
1841
MSR_UNC_CBO_3_
PERFEVTSEL1
Package
Uncore C-Box 3, counter 1 event select MSR.
736H
1846
MSR_UNC_CBO_3_PERFCTR0
Package
Uncore C-Box 3, performance counter 0.
737H
1847
MSR_UNC_CBO_3_PERFCTR1
Package
Uncore C-Box 3, performance counter 1.
See Table 35-18, Table 35-19, Table 35-20, Table 35-23, Table 35-27 for other MSR definitions applicable to processors with CPUID
signatures 063CH, 06_46H.
35.11.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors
The 4th generation Intel® Core™ processor family (based on Haswell microarchitecture) with CPUID
DisplayFamily_DisplayModel signature 06_45H supports the MSR interfaces listed in Table 35-18, Table 35-19,
Table 35-27, Table 35-28, and Table 35-29.
Table 35-29. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with
DisplayFamily_DisplayModel Signature 06_45H
Register
Address
Hex
Dec
E2H
226
Register Name
MSR_PKG_CST_CONFIG_
CONTROL
Scope
Core
Bit Description
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-states.
See http://biosbits.org.
35-204 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-29. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with
DisplayFamily_DisplayModel Signature 06_45H
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
3:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
630H
1584
9:4
Reserved
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved
15
CFG Lock (R/WO)
24:16
Reserved
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
63:29
Reserved
MSR_PKG_C8_RESIDENCY
Package
59:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
Package C8 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C8
states. Count at the same frequency as the TSC.
63:60
631H
1585
MSR_PKG_C9_RESIDENCY
Reserved
Package
59:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
Package C9 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C9
states. Count at the same frequency as the TSC.
63:60
632H
1586
MSR_PKG_C10_RESIDENCY
Reserved
Package
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
Vol. 3C 35-205
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-29. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with
DisplayFamily_DisplayModel Signature 06_45H
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
59:0
Package C10 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C10
states. Count at the same frequency as the TSC.
63:60
Reserved
See Table 35-18, Table 35-19, Table 35-20, Table 35-27, Table 35-28 for other MSR definitions applicable to processors with CPUID
signature 06_45H.
35.12
MSRS IN INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY
Intel® Xeon® processor E5 v3 family and Intel® Xeon® processor E7 v3 family are based on Haswell-E microarchitecture (CPUID DisplayFamily_DisplayModel = 06_3F). These processors supports the MSR interfaces listed in
Table 35-18, Table 35-27, and Table 35-30.
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Dec
35H
53
Register Name
MSR_CORE_THREAD_COUN
T
Scope
Package
Bit Description
Configured State of Enabled Processor Core Count and Logical
Processor Count (RO)
• After a Power-On RESET, enumerates factory configuration of
the number of processor cores and logical processors in the
physical package.
• Following the sequence of (i) BIOS modified a Configuration Mask
which selects a subset of processor cores to be active post
RESET and (ii) a RESET event after the modification, enumerates
the current configuration of enabled processor core count and
logical processor count in the physical package.
15:0
Core_COUNT (RO)
The number of processor cores that are currently enabled (by
either factory configuration or BIOS configuration) in the physical
package.
31:16
THREAD_COUNT (RO)
The number of logical processors that are currently enabled (by
either factory configuration or BIOS configuration) in the physical
package.
63:32
53H
83
MSR_THREAD_ID_INFO
7:0
Reserved
Thread
A Hardware Assigned ID for the Logical Processor (RO)
Logical_Processor_ID (RO)
An implementation-specific numerical. value physically assigned to
each logical processor. This ID is not related to Initial APIC ID or
x2APIC ID, it is unique within a physical package.
63:8
35-206 Vol. 3C
Reserved
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Dec
E2H
226
Register Name
MSR_PKG_CST_CONFIG_
Scope
Core
CONTROL
Bit Description
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-states.
See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the
processor are available.
179H
377
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved
15
CFG Lock (R/WO)
24:16
Reserved
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Package C State Demotion Enable (R/W)
30
Package C State UnDemotion Enable (R/W)
63:31
Reserved
IA32_MCG_CAP
Thread
Global Machine Check Capability (R/O)
7:0
Count
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved.
23:16
MCG_EXT_CNT
24
MCG_SER_P
25
MCG_EM_P
26
MCG_ELOG_P
63:27
Reserved.
Vol. 3C 35-207
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Dec
17DH
390
Register Name
MSR_SMM_MCA_CAP
Scope
THREAD
Bit Description
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in
SMM.
57:0
Reserved
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is
supported and a host-space interface available to SMM handler.
59
Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported
and a host-space interface available to SMM handler.
63:60
17FH
383
MSR_ERROR_CONTROL
Reserved
Package
MC Bank Error Configuration (R/W)
0
Reserved
1
MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info in bits
36:32.
63:2
1ADH
429
MSR_TURBO_RATIO_LIMIT
Reserved.
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
55:48
Package
Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.
63:56
Package
Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.
1AEH
430
MSR_TURBO_RATIO_LIMIT1 Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
35-208 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
7:0
Package
Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
15:8
Package
Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10 core active.
23:16
Package
Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
31:24
Package
Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
39:32
Package
Maximum Ratio Limit for 13C
Maximum turbo ratio limit of 13 core active.
47:40
Package
Maximum Ratio Limit for 14C
Maximum turbo ratio limit of 14 core active.
55:48
Package
Maximum Ratio Limit for 15C
Maximum turbo ratio limit of 15 core active.
63:56
Package
Maximum Ratio Limit for16C
Maximum turbo ratio limit of 16 core active.
1AFH
431
MSR_TURBO_RATIO_LIMIT2 Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 17C
Maximum turbo ratio limit of 17 core active.
15:8
Package
Maximum Ratio Limit for 18C
Maximum turbo ratio limit of 18 core active.
62:16
Package
Reserved
63
Package
Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration (Default).
414H
1044
IA32_MC5_CTL
Package
415H
1045
IA32_MC5_STATUS
Package
416H
1046
IA32_MC5_ADDR
Package
417H
1047
IA32_MC5_MISC
Package
418H
1048
IA32_MC6_CTL
Package
419H
1049
IA32_MC6_STATUS
Package
41AH
1050
IA32_MC6_ADDR
Package
41BH
1051
IA32_MC6_MISC
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC5 reports MC error from the Intel QPI 0 module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC6 reports MC error from the integrated I/O module.
Vol. 3C 35-209
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Register Name
Scope
Hex
Dec
41CH
1052
IA32_MC7_CTL
Package
41DH
1053
IA32_MC7_STATUS
Package
41EH
1054
IA32_MC7_ADDR
Package
41FH
1055
IA32_MC7_MISC
Package
420H
1056
IA32_MC8_CTL
Package
421H
1057
IA32_MC8_STATUS
Package
422H
1058
IA32_MC8_ADDR
Package
423H
1059
IA32_MC8_MISC
Package
424H
1060
IA32_MC9_CTL
Package
425H
1061
IA32_MC9_STATUS
Package
426H
1062
IA32_MC9_ADDR
Package
427H
1063
IA32_MC9_MISC
Package
428H
1064
IA32_MC10_CTL
Package
429H
1065
IA32_MC10_STATUS
Package
42AH
1066
IA32_MC10_ADDR
Package
42BH
1067
IA32_MC10_MISC
Package
42CH
1068
IA32_MC11_CTL
Package
42DH
1069
IA32_MC11_STATUS
Package
42EH
1070
IA32_MC11_ADDR
Package
42FH
1071
IA32_MC11_MISC
Package
430H
1072
IA32_MC12_CTL
Package
431H
1073
IA32_MC12_STATUS
Package
432H
1074
IA32_MC12_ADDR
Package
433H
1075
IA32_MC12_MISC
Package
434H
1076
IA32_MC13_CTL
Package
435H
1077
IA32_MC13_STATUS
Package
436H
1078
IA32_MC13_ADDR
Package
437H
1079
IA32_MC13_MISC
Package
438H
1080
IA32_MC14_CTL
Package
439H
1081
IA32_MC14_STATUS
Package
43AH
1082
IA32_MC14_ADDR
Package
43BH
1083
IA32_MC14_MISC
Package
43CH
1084
IA32_MC15_CTL
Package
43DH
1085
IA32_MC15_STATUS
Package
43EH
1086
IA32_MC15_ADDR
Package
43FH
1087
IA32_MC15_MISC
Package
35-210 Vol. 3C
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC7 reports MC error from the home agent HA 0.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC8 reports MC error from the home agent HA 1.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
440H
1088
IA32_MC16_CTL
Package
441H
1089
IA32_MC16_STATUS
Package
442H
1090
IA32_MC16_ADDR
Package
443H
1091
IA32_MC16_MISC
Package
444H
1092
IA32_MC17_CTL
Package
445H
1093
IA32_MC17_STATUS
Package
446H
1094
IA32_MC17_ADDR
Package
447H
1095
IA32_MC17_MISC
Package
448H
1096
IA32_MC18_CTL
Package
449H
1097
IA32_MC18_STATUS
Package
44AH
1098
IA32_MC18_ADDR
Package
44BH
1099
IA32_MC18_MISC
Package
44CH
1100
IA32_MC19_CTL
Package
44DH
1101
IA32_MC19_STATUS
Package
44EH
1102
IA32_MC19_ADDR
Package
44FH
1103
IA32_MC19_MISC
Package
450H
1104
IA32_MC20_CTL
Package
451H
1105
IA32_MC20_STATUS
Package
452H
1106
IA32_MC20_ADDR
Package
453H
1107
IA32_MC20_MISC
Package
454H
1108
IA32_MC21_CTL
Package
455H
1109
IA32_MC21_STATUS
Package
456H
1110
IA32_MC21_ADDR
Package
457H
1111
IA32_MC21_MISC
Package
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
3:0
Package
Power Units
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC17 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12,
CBo15.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC18 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13,
CBo16.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC19 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14,
CBo17.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC20 reports MC error from the Intel QPI 1 module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC21 reports MC error from the Intel QPI 2 module.
See Section 14.9.1, “RAPL Interfaces.”
7:4
Package
Reserved
12:8
Package
Energy Status Units
Energy related information (in Joules) is based on the multiplier,
1/2^ESU; where ESU is an unsigned integer represented by bits
12:8. Default value is 0EH (or 61 micro-joules)
15:13
Package
Reserved
19:16
Package
Time Units
See Section 14.9.1, “RAPL Interfaces.”
63:20
618H
1560
MSR_DRAM_POWER_LIMIT
Reserved
Package
DRAM RAPL Power Limit Control (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
Vol. 3C 35-211
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Dec
619H
1561
Register Name
MSR_DRAM_ENERGY_
STATUS
Scope
Package
Bit Description
DRAM Energy Status (R/O)
Energy Consumed by DRAM devices.
31:0
Energy in 15.3 micro-joules. Requires BIOS configuration to enable
DRAM RAPL mode 0 (Direct VR).
63:32
Reserved
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O) See Section 14.9.5,
“DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
61EH
1566
MSR_PCIE_PLL_RATIO
Package
Configuration of PCIE PLL Relative to BCLK(R/W)
1:0
Package
PCIE Ratio (R/W)
00b: Use 5:5 mapping for100MHz operation (default)
01b: Use 5:4 mapping for125MHz operation
10b: Use 5:3 mapping for166MHz operation
11b: Use 5:2 mapping for250MHz operation
2
Package
LPLL Select (R/W)
if 1, use configured setting of PCIE Ratio
3
Package
LONG RESET (R/W)
if 1, wait additional time-out before re-locking Gen2/Gen3 PLLs.
639H
1593
63:4
Reserved
MSR_PP0_ENERGY_STATUS Package
Reserved (R/O)
Reads return 0
690H
1680
MSR_CORE_PERF_LIMIT_RE Package
ASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
0
PROCHOT Status (R0)
(frequency refers to processor core frequency)
When set, processor core frequency is reduced below the operating
system request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
2
Power Budget Management Status (R0)
When set, frequency is reduced below the operating system
request due to PBM limit
3
Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating system
request due to PCS limit
4
Reserved.
5
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system
request because the processor has detected that utilization is low
35-212 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
9
Reserved.
10
Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system
request due to Multi-Core Turbo limits
12:11
Reserved.
13
Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1
14
Core Max n-core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency
15
Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system
request.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18
Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19
Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20
Reserved.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Vol. 3C 35-213
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28:27
Reserved.
29
Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30
Core Max n-core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
31
Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:32
C8DH
3213
IA32_QM_EVTSEL
Reserved.
THREAD
Monitoring Event Select Register (R/W).
if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1
7:0
EventID (RW)
Event encoding:
0x0: no monitoring
0x1: L3 occupancy monitoring
all other encoding reserved.
C8EH
3214
31:8
Reserved.
41:32
RMID (RW)
63:42
Reserved.
IA32_QM_CTR
THREAD
Monitoring Counter Register (R/O).
if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1
61:0
35-214 Vol. 3C
Resource Monitored Data
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
C8FH
Scope
Register Name
Bit Description
Dec
3215
62
Unavailable: If 1, indicates data for this RMID is not available or not
monitored for this resource or RMID.
63
Error: If 1, indicates and unsupported RMID or event type was
written to IA32_PQR_QM_EVTSEL.
IA32_PQR_ASSOC
THREAD
Resource Association Register (R/W).
9:0
RMID
63: 10
Reserved
See Table 35-18, Table 35-27 for other MSR definitions applicable to processors with CPUID signature 06_3FH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the factory-set configuration is dependent on features specific to the processor and the platform.
35.12.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
Intel Xeon Processor E5 v3 and E7 v3 family are based on the Haswell-E microarchitecture. The MSR-based uncore
PMU interfaces are listed in Table 35-31. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 v3
Product Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_3FH.
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
700H
MSR_PMON_GLOBAL_CTL
Package
Uncore perfmon per-socket global control.
701H
MSR_PMON_GLOBAL_STATUS
Package
Uncore perfmon per-socket global status.
702H
MSR_PMON_GLOBAL_CONFIG
Package
Uncore perfmon per-socket global configuration.
703H
MSR_U_PMON_UCLK_FIXED_CTL
Package
Uncore U-box UCLK fixed counter control
704H
MSR_U_PMON_UCLK_FIXED_CTR
Package
Uncore U-box UCLK fixed counter
705H
MSR_U_PMON_EVNTSEL0
Package
Uncore U-box perfmon event select for U-box counter 0.
706H
MSR_U_PMON_EVNTSEL1
Package
Uncore U-box perfmon event select for U-box counter 1.
708H
MSR_U_PMON_BOX_STATUS
Package
Uncore U-box perfmon U-box wide status.
709H
MSR_U_PMON_CTR0
Package
Uncore U-box perfmon counter 0
70AH
MSR_U_PMON_CTR1
Package
Uncore U-box perfmon counter 1
710H
MSR_PCU_PMON_BOX_CTL
Package
Uncore PCU perfmon for PCU-box-wide control
711H
MSR_PCU_PMON_EVNTSEL0
Package
Uncore PCU perfmon event select for PCU counter 0.
712H
MSR_PCU_PMON_EVNTSEL1
Package
Uncore PCU perfmon event select for PCU counter 1.
713H
MSR_PCU_PMON_EVNTSEL2
Package
Uncore PCU perfmon event select for PCU counter 2.
714H
MSR_PCU_PMON_EVNTSEL3
Package
Uncore PCU perfmon event select for PCU counter 3.
715H
MSR_PCU_PMON_BOX_FILTER
Package
Uncore PCU perfmon box-wide filter.
716H
MSR_PCU_PMON_BOX_STATUS
Package
Uncore PCU perfmon box wide status.
Vol. 3C 35-215
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
717H
MSR_PCU_PMON_CTR0
Package
Uncore PCU perfmon counter 0.
718H
MSR_PCU_PMON_CTR1
Package
Uncore PCU perfmon counter 1.
719H
MSR_PCU_PMON_CTR2
Package
Uncore PCU perfmon counter 2.
71AH
MSR_PCU_PMON_CTR3
Package
Uncore PCU perfmon counter 3.
720H
MSR_S0_PMON_BOX_CTL
Package
Uncore SBo 0 perfmon for SBo 0 box-wide control
721H
MSR_S0_PMON_EVNTSEL0
Package
Uncore SBo 0 perfmon event select for SBo 0 counter 0.
722H
MSR_S0_PMON_EVNTSEL1
Package
Uncore SBo 0 perfmon event select for SBo 0 counter 1.
723H
MSR_S0_PMON_EVNTSEL2
Package
Uncore SBo 0 perfmon event select for SBo 0 counter 2.
724H
MSR_S0_PMON_EVNTSEL3
Package
Uncore SBo 0 perfmon event select for SBo 0 counter 3.
725H
MSR_S0_PMON_BOX_FILTER
Package
Uncore SBo 0 perfmon box-wide filter.
726H
MSR_S0_PMON_CTR0
Package
Uncore SBo 0 perfmon counter 0.
727H
MSR_S0_PMON_CTR1
Package
Uncore SBo 0 perfmon counter 1.
728H
MSR_S0_PMON_CTR2
Package
Uncore SBo 0 perfmon counter 2.
729H
MSR_S0_PMON_CTR3
Package
Uncore SBo 0 perfmon counter 3.
72AH
MSR_S1_PMON_BOX_CTL
Package
Uncore SBo 1 perfmon for SBo 1 box-wide control
72BH
MSR_S1_PMON_EVNTSEL0
Package
Uncore SBo 1 perfmon event select for SBo 1 counter 0.
72CH
MSR_S1_PMON_EVNTSEL1
Package
Uncore SBo 1 perfmon event select for SBo 1 counter 1.
72DH
MSR_S1_PMON_EVNTSEL2
Package
Uncore SBo 1 perfmon event select for SBo 1 counter 2.
72EH
MSR_S1_PMON_EVNTSEL3
Package
Uncore SBo 1 perfmon event select for SBo 1 counter 3.
72FH
MSR_S1_PMON_BOX_FILTER
Package
Uncore SBo 1 perfmon box-wide filter.
730H
MSR_S1_PMON_CTR0
Package
Uncore SBo 1 perfmon counter 0.
731H
MSR_S1_PMON_CTR1
Package
Uncore SBo 1 perfmon counter 1.
732H
MSR_S1_PMON_CTR2
Package
Uncore SBo 1 perfmon counter 2.
733H
MSR_S1_PMON_CTR3
Package
Uncore SBo 1 perfmon counter 3.
734H
MSR_S2_PMON_BOX_CTL
Package
Uncore SBo 2 perfmon for SBo 2 box-wide control
735H
MSR_S2_PMON_EVNTSEL0
Package
Uncore SBo 2 perfmon event select for SBo 2 counter 0.
736H
MSR_S2_PMON_EVNTSEL1
Package
Uncore SBo 2 perfmon event select for SBo 2 counter 1.
737H
MSR_S2_PMON_EVNTSEL2
Package
Uncore SBo 2 perfmon event select for SBo 2 counter 2.
738H
MSR_S2_PMON_EVNTSEL3
Package
Uncore SBo 2 perfmon event select for SBo 2 counter 3.
739H
MSR_S2_PMON_BOX_FILTER
Package
Uncore SBo 2 perfmon box-wide filter.
73AH
MSR_S2_PMON_CTR0
Package
Uncore SBo 2 perfmon counter 0.
73BH
MSR_S2_PMON_CTR1
Package
Uncore SBo 2 perfmon counter 1.
73CH
MSR_S2_PMON_CTR2
Package
Uncore SBo 2 perfmon counter 2.
73DH
MSR_S2_PMON_CTR3
Package
Uncore SBo 2 perfmon counter 3.
73EH
MSR_S3_PMON_BOX_CTL
Package
Uncore SBo 3 perfmon for SBo 3 box-wide control
73FH
MSR_S3_PMON_EVNTSEL0
Package
Uncore SBo 3 perfmon event select for SBo 3 counter 0.
740H
MSR_S3_PMON_EVNTSEL1
Package
Uncore SBo 3 perfmon event select for SBo 3 counter 1.
35-216 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
741H
MSR_S3_PMON_EVNTSEL2
Package
Uncore SBo 3 perfmon event select for SBo 3 counter 2.
742H
MSR_S3_PMON_EVNTSEL3
Package
Uncore SBo 3 perfmon event select for SBo 3 counter 3.
743H
MSR_S3_PMON_BOX_FILTER
Package
Uncore SBo 3 perfmon box-wide filter.
744H
MSR_S3_PMON_CTR0
Package
Uncore SBo 3 perfmon counter 0.
745H
MSR_S3_PMON_CTR1
Package
Uncore SBo 3 perfmon counter 1.
746H
MSR_S3_PMON_CTR2
Package
Uncore SBo 3 perfmon counter 2.
747H
MSR_S3_PMON_CTR3
Package
Uncore SBo 3 perfmon counter 3.
E00H
MSR_C0_PMON_BOX_CTL
Package
Uncore C-box 0 perfmon for box-wide control
E01H
MSR_C0_PMON_EVNTSEL0
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 0.
E02H
MSR_C0_PMON_EVNTSEL1
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 1.
E03H
MSR_C0_PMON_EVNTSEL2
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 2.
E04H
MSR_C0_PMON_EVNTSEL3
Package
Uncore C-box 0 perfmon event select for C-box 0 counter 3.
E05H
MSR_C0_PMON_BOX_FILTER0
Package
Uncore C-box 0 perfmon box wide filter 0.
E06H
MSR_C0_PMON_BOX_FILTER1
Package
Uncore C-box 0 perfmon box wide filter 1.
E07H
MSR_C0_PMON_BOX_STATUS
Package
Uncore C-box 0 perfmon box wide status.
E08H
MSR_C0_PMON_CTR0
Package
Uncore C-box 0 perfmon counter 0.
E09H
MSR_C0_PMON_CTR1
Package
Uncore C-box 0 perfmon counter 1.
E0AH
MSR_C0_PMON_CTR2
Package
Uncore C-box 0 perfmon counter 2.
E0BH
MSR_C0_PMON_CTR3
Package
Uncore C-box 0 perfmon counter 3.
E10H
MSR_C1_PMON_BOX_CTL
Package
Uncore C-box 1 perfmon for box-wide control
E11H
MSR_C1_PMON_EVNTSEL0
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 0.
E12H
MSR_C1_PMON_EVNTSEL1
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 1.
E13H
MSR_C1_PMON_EVNTSEL2
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 2.
E14H
MSR_C1_PMON_EVNTSEL3
Package
Uncore C-box 1 perfmon event select for C-box 1 counter 3.
E15H
MSR_C1_PMON_BOX_FILTER0
Package
Uncore C-box 1 perfmon box wide filter 0.
E16H
MSR_C1_PMON_BOX_FILTER1
Package
Uncore C-box 1 perfmon box wide filter1.
E17H
MSR_C1_PMON_BOX_STATUS
Package
Uncore C-box 1 perfmon box wide status.
E18H
MSR_C1_PMON_CTR0
Package
Uncore C-box 1 perfmon counter 0.
E19H
MSR_C1_PMON_CTR1
Package
Uncore C-box 1 perfmon counter 1.
E1AH
MSR_C1_PMON_CTR2
Package
Uncore C-box 1 perfmon counter 2.
E1BH
MSR_C1_PMON_CTR3
Package
Uncore C-box 1 perfmon counter 3.
E20H
MSR_C2_PMON_BOX_CTL
Package
Uncore C-box 2 perfmon for box-wide control
E21H
MSR_C2_PMON_EVNTSEL0
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 0.
E22H
MSR_C2_PMON_EVNTSEL1
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 1.
E23H
MSR_C2_PMON_EVNTSEL2
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 2.
E24H
MSR_C2_PMON_EVNTSEL3
Package
Uncore C-box 2 perfmon event select for C-box 2 counter 3.
E25H
MSR_C2_PMON_BOX_FILTER0
Package
Uncore C-box 2 perfmon box wide filter 0.
Vol. 3C 35-217
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
E26H
MSR_C2_PMON_BOX_FILTER1
Package
Uncore C-box 2 perfmon box wide filter1.
E27H
MSR_C2_PMON_BOX_STATUS
Package
Uncore C-box 2 perfmon box wide status.
E28H
MSR_C2_PMON_CTR0
Package
Uncore C-box 2 perfmon counter 0.
E29H
MSR_C2_PMON_CTR1
Package
Uncore C-box 2 perfmon counter 1.
E2AH
MSR_C2_PMON_CTR2
Package
Uncore C-box 2 perfmon counter 2.
E2BH
MSR_C2_PMON_CTR3
Package
Uncore C-box 2 perfmon counter 3.
E30H
MSR_C3_PMON_BOX_CTL
Package
Uncore C-box 3 perfmon for box-wide control
E31H
MSR_C3_PMON_EVNTSEL0
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 0.
E32H
MSR_C3_PMON_EVNTSEL1
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 1.
E33H
MSR_C3_PMON_EVNTSEL2
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 2.
E34H
MSR_C3_PMON_EVNTSEL3
Package
Uncore C-box 3 perfmon event select for C-box 3 counter 3.
E35H
MSR_C3_PMON_BOX_FILTER0
Package
Uncore C-box 3 perfmon box wide filter 0.
E36H
MSR_C3_PMON_BOX_FILTER1
Package
Uncore C-box 3 perfmon box wide filter1.
E37H
MSR_C3_PMON_BOX_STATUS
Package
Uncore C-box 3 perfmon box wide status.
E38H
MSR_C3_PMON_CTR0
Package
Uncore C-box 3 perfmon counter 0.
E39H
MSR_C3_PMON_CTR1
Package
Uncore C-box 3 perfmon counter 1.
E3AH
MSR_C3_PMON_CTR2
Package
Uncore C-box 3 perfmon counter 2.
E3BH
MSR_C3_PMON_CTR3
Package
Uncore C-box 3 perfmon counter 3.
E40H
MSR_C4_PMON_BOX_CTL
Package
Uncore C-box 4 perfmon for box-wide control
E41H
MSR_C4_PMON_EVNTSEL0
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 0.
E42H
MSR_C4_PMON_EVNTSEL1
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 1.
E43H
MSR_C4_PMON_EVNTSEL2
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 2.
E44H
MSR_C4_PMON_EVNTSEL3
Package
Uncore C-box 4 perfmon event select for C-box 4 counter 3.
E45H
MSR_C4_PMON_BOX_FILTER0
Package
Uncore C-box 4 perfmon box wide filter 0.
E46H
MSR_C4_PMON_BOX_FILTER1
Package
Uncore C-box 4 perfmon box wide filter1.
E47H
MSR_C4_PMON_BOX_STATUS
Package
Uncore C-box 4 perfmon box wide status.
E48H
MSR_C4_PMON_CTR0
Package
Uncore C-box 4 perfmon counter 0.
E49H
MSR_C4_PMON_CTR1
Package
Uncore C-box 4 perfmon counter 1.
E4AH
MSR_C4_PMON_CTR2
Package
Uncore C-box 4 perfmon counter 2.
E4BH
MSR_C4_PMON_CTR3
Package
Uncore C-box 4 perfmon counter 3.
E50H
MSR_C5_PMON_BOX_CTL
Package
Uncore C-box 5 perfmon for box-wide control
E51H
MSR_C5_PMON_EVNTSEL0
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 0.
E52H
MSR_C5_PMON_EVNTSEL1
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 1.
E53H
MSR_C5_PMON_EVNTSEL2
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 2.
E54H
MSR_C5_PMON_EVNTSEL3
Package
Uncore C-box 5 perfmon event select for C-box 5 counter 3.
E55H
MSR_C5_PMON_BOX_FILTER0
Package
Uncore C-box 5 perfmon box wide filter 0.
E56H
MSR_C5_PMON_BOX_FILTER1
Package
Uncore C-box 5 perfmon box wide filter1.
35-218 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
E57H
MSR_C5_PMON_BOX_STATUS
Package
Uncore C-box 5 perfmon box wide status.
E58H
MSR_C5_PMON_CTR0
Package
Uncore C-box 5 perfmon counter 0.
E59H
MSR_C5_PMON_CTR1
Package
Uncore C-box 5 perfmon counter 1.
E5AH
MSR_C5_PMON_CTR2
Package
Uncore C-box 5 perfmon counter 2.
E5BH
MSR_C5_PMON_CTR3
Package
Uncore C-box 5 perfmon counter 3.
E60H
MSR_C6_PMON_BOX_CTL
Package
Uncore C-box 6 perfmon for box-wide control
E61H
MSR_C6_PMON_EVNTSEL0
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 0.
E62H
MSR_C6_PMON_EVNTSEL1
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 1.
E63H
MSR_C6_PMON_EVNTSEL2
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 2.
E64H
MSR_C6_PMON_EVNTSEL3
Package
Uncore C-box 6 perfmon event select for C-box 6 counter 3.
E65H
MSR_C6_PMON_BOX_FILTER0
Package
Uncore C-box 6 perfmon box wide filter 0.
E66H
MSR_C6_PMON_BOX_FILTER1
Package
Uncore C-box 6 perfmon box wide filter1.
E67H
MSR_C6_PMON_BOX_STATUS
Package
Uncore C-box 6 perfmon box wide status.
E68H
MSR_C6_PMON_CTR0
Package
Uncore C-box 6 perfmon counter 0.
E69H
MSR_C6_PMON_CTR1
Package
Uncore C-box 6 perfmon counter 1.
E6AH
MSR_C6_PMON_CTR2
Package
Uncore C-box 6 perfmon counter 2.
E6BH
MSR_C6_PMON_CTR3
Package
Uncore C-box 6 perfmon counter 3.
E70H
MSR_C7_PMON_BOX_CTL
Package
Uncore C-box 7 perfmon for box-wide control.
E71H
MSR_C7_PMON_EVNTSEL0
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 0.
E72H
MSR_C7_PMON_EVNTSEL1
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 1.
E73H
MSR_C7_PMON_EVNTSEL2
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 2.
E74H
MSR_C7_PMON_EVNTSEL3
Package
Uncore C-box 7 perfmon event select for C-box 7 counter 3.
E75H
MSR_C7_PMON_BOX_FILTER0
Package
Uncore C-box 7 perfmon box wide filter 0.
E76H
MSR_C7_PMON_BOX_FILTER1
Package
Uncore C-box 7 perfmon box wide filter1.
E77H
MSR_C7_PMON_BOX_STATUS
Package
Uncore C-box 7 perfmon box wide status.
E78H
MSR_C7_PMON_CTR0
Package
Uncore C-box 7 perfmon counter 0.
E79H
MSR_C7_PMON_CTR1
Package
Uncore C-box 7 perfmon counter 1.
E7AH
MSR_C7_PMON_CTR2
Package
Uncore C-box 7 perfmon counter 2.
E7BH
MSR_C7_PMON_CTR3
Package
Uncore C-box 7 perfmon counter 3.
E80H
MSR_C8_PMON_BOX_CTL
Package
Uncore C-box 8 perfmon local box wide control.
E81H
MSR_C8_PMON_EVNTSEL0
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 0.
E82H
MSR_C8_PMON_EVNTSEL1
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 1.
E83H
MSR_C8_PMON_EVNTSEL2
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 2.
E84H
MSR_C8_PMON_EVNTSEL3
Package
Uncore C-box 8 perfmon event select for C-box 8 counter 3.
E85H
MSR_C8_PMON_BOX_FILTER0
Package
Uncore C-box 8 perfmon box wide filter0.
E86H
MSR_C8_PMON_BOX_FILTER1
Package
Uncore C-box 8 perfmon box wide filter1.
E87H
MSR_C8_PMON_BOX_STATUS
Package
Uncore C-box 8 perfmon box wide status.
Vol. 3C 35-219
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
E88H
MSR_C8_PMON_CTR0
Package
Uncore C-box 8 perfmon counter 0.
E89H
MSR_C8_PMON_CTR1
Package
Uncore C-box 8 perfmon counter 1.
E8AH
MSR_C8_PMON_CTR2
Package
Uncore C-box 8 perfmon counter 2.
E8BH
MSR_C8_PMON_CTR3
Package
Uncore C-box 8 perfmon counter 3.
E90H
MSR_C9_PMON_BOX_CTL
Package
Uncore C-box 9 perfmon local box wide control.
E91H
MSR_C9_PMON_EVNTSEL0
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 0.
E92H
MSR_C9_PMON_EVNTSEL1
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 1.
E93H
MSR_C9_PMON_EVNTSEL2
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 2.
E94H
MSR_C9_PMON_EVNTSEL3
Package
Uncore C-box 9 perfmon event select for C-box 9 counter 3.
E95H
MSR_C9_PMON_BOX_FILTER0
Package
Uncore C-box 9 perfmon box wide filter0.
E96H
MSR_C9_PMON_BOX_FILTER1
Package
Uncore C-box 9 perfmon box wide filter1.
E97H
MSR_C9_PMON_BOX_STATUS
Package
Uncore C-box 9 perfmon box wide status.
E98H
MSR_C9_PMON_CTR0
Package
Uncore C-box 9 perfmon counter 0.
E99H
MSR_C9_PMON_CTR1
Package
Uncore C-box 9 perfmon counter 1.
E9AH
MSR_C9_PMON_CTR2
Package
Uncore C-box 9 perfmon counter 2.
E9BH
MSR_C9_PMON_CTR3
Package
Uncore C-box 9 perfmon counter 3.
EA0H
MSR_C10_PMON_BOX_CTL
Package
Uncore C-box 10 perfmon local box wide control.
EA1H
MSR_C10_PMON_EVNTSEL0
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 0.
EA2H
MSR_C10_PMON_EVNTSEL1
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 1.
EA3H
MSR_C10_PMON_EVNTSEL2
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 2.
EA4H
MSR_C10_PMON_EVNTSEL3
Package
Uncore C-box 10 perfmon event select for C-box 10 counter 3.
EA5H
MSR_C10_PMON_BOX_FILTER0
Package
Uncore C-box 10 perfmon box wide filter0.
EA6H
MSR_C10_PMON_BOX_FILTER1
Package
Uncore C-box 10 perfmon box wide filter1.
EA7H
MSR_C10_PMON_BOX_STATUS
Package
Uncore C-box 10 perfmon box wide status.
EA8H
MSR_C10_PMON_CTR0
Package
Uncore C-box 10 perfmon counter 0.
EA9H
MSR_C10_PMON_CTR1
Package
Uncore C-box 10 perfmon counter 1.
EAAH
MSR_C10_PMON_CTR2
Package
Uncore C-box 10 perfmon counter 2.
EABH
MSR_C10_PMON_CTR3
Package
Uncore C-box 10 perfmon counter 3.
EB0H
MSR_C11_PMON_BOX_CTL
Package
Uncore C-box 11 perfmon local box wide control.
EB1H
MSR_C11_PMON_EVNTSEL0
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 0.
EB2H
MSR_C11_PMON_EVNTSEL1
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 1.
EB3H
MSR_C11_PMON_EVNTSEL2
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 2.
EB4H
MSR_C11_PMON_EVNTSEL3
Package
Uncore C-box 11 perfmon event select for C-box 11 counter 3.
EB5H
MSR_C11_PMON_BOX_FILTER0
Package
Uncore C-box 11 perfmon box wide filter0.
EB6H
MSR_C11_PMON_BOX_FILTER1
Package
Uncore C-box 11 perfmon box wide filter1.
EB7H
MSR_C11_PMON_BOX_STATUS
Package
Uncore C-box 11 perfmon box wide status.
EB8H
MSR_C11_PMON_CTR0
Package
Uncore C-box 11 perfmon counter 0.
35-220 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
EB9H
MSR_C11_PMON_CTR1
Package
Uncore C-box 11 perfmon counter 1.
EBAH
MSR_C11_PMON_CTR2
Package
Uncore C-box 11 perfmon counter 2.
EBBH
MSR_C11_PMON_CTR3
Package
Uncore C-box 11 perfmon counter 3.
EC0H
MSR_C12_PMON_BOX_CTL
Package
Uncore C-box 12 perfmon local box wide control.
EC1H
MSR_C12_PMON_EVNTSEL0
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 0.
EC2H
MSR_C12_PMON_EVNTSEL1
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 1.
EC3H
MSR_C12_PMON_EVNTSEL2
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 2.
EC4H
MSR_C12_PMON_EVNTSEL3
Package
Uncore C-box 12 perfmon event select for C-box 12 counter 3.
EC5H
MSR_C12_PMON_BOX_FILTER0
Package
Uncore C-box 12 perfmon box wide filter0.
EC6H
MSR_C12_PMON_BOX_FILTER1
Package
Uncore C-box 12 perfmon box wide filter1.
EC7H
MSR_C12_PMON_BOX_STATUS
Package
Uncore C-box 12 perfmon box wide status.
EC8H
MSR_C12_PMON_CTR0
Package
Uncore C-box 12 perfmon counter 0.
EC9H
MSR_C12_PMON_CTR1
Package
Uncore C-box 12 perfmon counter 1.
ECAH
MSR_C12_PMON_CTR2
Package
Uncore C-box 12 perfmon counter 2.
ECBH
MSR_C12_PMON_CTR3
Package
Uncore C-box 12 perfmon counter 3.
ED0H
MSR_C13_PMON_BOX_CTL
Package
Uncore C-box 13 perfmon local box wide control.
ED1H
MSR_C13_PMON_EVNTSEL0
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 0.
ED2H
MSR_C13_PMON_EVNTSEL1
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 1.
ED3H
MSR_C13_PMON_EVNTSEL2
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 2.
ED4H
MSR_C13_PMON_EVNTSEL3
Package
Uncore C-box 13 perfmon event select for C-box 13 counter 3.
ED5H
MSR_C13_PMON_BOX_FILTER0
Package
Uncore C-box 13 perfmon box wide filter0.
ED6H
MSR_C13_PMON_BOX_FILTER1
Package
Uncore C-box 13 perfmon box wide filter1.
ED7H
MSR_C13_PMON_BOX_STATUS
Package
Uncore C-box 13 perfmon box wide status.
ED8H
MSR_C13_PMON_CTR0
Package
Uncore C-box 13 perfmon counter 0.
ED9H
MSR_C13_PMON_CTR1
Package
Uncore C-box 13 perfmon counter 1.
EDAH
MSR_C13_PMON_CTR2
Package
Uncore C-box 13 perfmon counter 2.
EDBH
MSR_C13_PMON_CTR3
Package
Uncore C-box 13 perfmon counter 3.
EE0H
MSR_C14_PMON_BOX_CTL
Package
Uncore C-box 14 perfmon local box wide control.
EE1H
MSR_C14_PMON_EVNTSEL0
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 0.
EE2H
MSR_C14_PMON_EVNTSEL1
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 1.
EE3H
MSR_C14_PMON_EVNTSEL2
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 2.
EE4H
MSR_C14_PMON_EVNTSEL3
Package
Uncore C-box 14 perfmon event select for C-box 14 counter 3.
EE5H
MSR_C14_PMON_BOX_FILTER
Package
Uncore C-box 14 perfmon box wide filter0.
EE6H
MSR_C14_PMON_BOX_FILTER1
Package
Uncore C-box 14 perfmon box wide filter1.
EE7H
MSR_C14_PMON_BOX_STATUS
Package
Uncore C-box 14 perfmon box wide status.
EE8H
MSR_C14_PMON_CTR0
Package
Uncore C-box 14 perfmon counter 0.
EE9H
MSR_C14_PMON_CTR1
Package
Uncore C-box 14 perfmon counter 1.
Vol. 3C 35-221
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
EEAH
MSR_C14_PMON_CTR2
Package
Uncore C-box 14 perfmon counter 2.
EEBH
MSR_C14_PMON_CTR3
Package
Uncore C-box 14 perfmon counter 3.
EF0H
MSR_C15_PMON_BOX_CTL
Package
Uncore C-box 15 perfmon local box wide control.
EF1H
MSR_C15_PMON_EVNTSEL0
Package
Uncore C-box 15 perfmon event select for C-box 15 counter 0.
EF2H
MSR_C15_PMON_EVNTSEL1
Package
Uncore C-box 15 perfmon event select for C-box 15 counter 1.
EF3H
MSR_C15_PMON_EVNTSEL2
Package
Uncore C-box 15 perfmon event select for C-box 15 counter 2.
EF4H
MSR_C15_PMON_EVNTSEL3
Package
Uncore C-box 15 perfmon event select for C-box 15 counter 3.
EF5H
MSR_C15_PMON_BOX_FILTER0
Package
Uncore C-box 15 perfmon box wide filter0.
EF6H
MSR_C15_PMON_BOX_FILTER1
Package
Uncore C-box 15 perfmon box wide filter1.
EF7H
MSR_C15_PMON_BOX_STATUS
Package
Uncore C-box 15 perfmon box wide status.
EF8H
MSR_C15_PMON_CTR0
Package
Uncore C-box 15 perfmon counter 0.
EF9H
MSR_C15_PMON_CTR1
Package
Uncore C-box 15 perfmon counter 1.
EFAH
MSR_C15_PMON_CTR2
Package
Uncore C-box 15 perfmon counter 2.
EFBH
MSR_C15_PMON_CTR3
Package
Uncore C-box 15 perfmon counter 3.
F00H
MSR_C16_PMON_BOX_CTL
Package
Uncore C-box 16 perfmon for box-wide control
F01H
MSR_C16_PMON_EVNTSEL0
Package
Uncore C-box 16 perfmon event select for C-box 16 counter 0.
F02H
MSR_C16_PMON_EVNTSEL1
Package
Uncore C-box 16 perfmon event select for C-box 16 counter 1.
F03H
MSR_C16_PMON_EVNTSEL2
Package
Uncore C-box 16 perfmon event select for C-box 16 counter 2.
F04H
MSR_C16_PMON_EVNTSEL3
Package
Uncore C-box 16 perfmon event select for C-box 16 counter 3.
F05H
MSR_C16_PMON_BOX_FILTER0
Package
Uncore C-box 16 perfmon box wide filter 0.
F06H
MSR_C16_PMON_BOX_FILTER1
Package
Uncore C-box 16 perfmon box wide filter 1.
F07H
MSR_C16_PMON_BOX_STATUS
Package
Uncore C-box 16 perfmon box wide status.
F08H
MSR_C16_PMON_CTR0
Package
Uncore C-box 16 perfmon counter 0.
F09H
MSR_C16_PMON_CTR1
Package
Uncore C-box 16 perfmon counter 1.
F0AH
MSR_C16_PMON_CTR2
Package
Uncore C-box 16 perfmon counter 2.
E0BH
MSR_C16_PMON_CTR3
Package
Uncore C-box 16 perfmon counter 3.
F10H
MSR_C17_PMON_BOX_CTL
Package
Uncore C-box 17 perfmon for box-wide control
F11H
MSR_C17_PMON_EVNTSEL0
Package
Uncore C-box 17 perfmon event select for C-box 17 counter 0.
F12H
MSR_C17_PMON_EVNTSEL1
Package
Uncore C-box 17 perfmon event select for C-box 17 counter 1.
F13H
MSR_C17_PMON_EVNTSEL2
Package
Uncore C-box 17 perfmon event select for C-box 17 counter 2.
F14H
MSR_C17_PMON_EVNTSEL3
Package
Uncore C-box 17 perfmon event select for C-box 17 counter 3.
F15H
MSR_C17_PMON_BOX_FILTER0
Package
Uncore C-box 17 perfmon box wide filter 0.
F16H
MSR_C17_PMON_BOX_FILTER1
Package
Uncore C-box 17 perfmon box wide filter1.
F17H
MSR_C17_PMON_BOX_STATUS
Package
Uncore C-box 17 perfmon box wide status.
F18H
MSR_C17_PMON_CTR0
Package
Uncore C-box 17 perfmon counter 0.
F19H
MSR_C17_PMON_CTR1
Package
Uncore C-box 17 perfmon counter 1.
F1AH
MSR_C17_PMON_CTR2
Package
Uncore C-box 17 perfmon counter 2.
35-222 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-31. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address
Hex
Bit Description
Dec
F1BH
35.13
Scope
Register Name
MSR_C17_PMON_CTR3
Package
Uncore C-box 17 perfmon counter 3.
MSRS IN INTEL® CORE™ M PROCESSORS AND 5TH GENERATION INTEL
CORE PROCESSORS
The Intel® Core™ M-5xxx processors and 5th generation Intel® Core™ Processors, and Intel® Xeon® Processor
E3-1200 v4 family are based on the Broadwell microarchitecture. The Intel® Core™ M-5xxx processors and 5th
generation Intel® Core™ Processors have CPUID DisplayFamily_DisplayModel signature 06_3DH. Intel® Xeon®
Processor E3-1200 v4 family and the 5th generation Intel® Core™ Processors have CPUID
DisplayFamily_DisplayModel signature 06_47H. Processors with signatures 06_3DH and 06_47H support the MSR
interfaces listed in Table 35-18, Table 35-19, Table 35-20, Table 35-23, Table 35-27, Table 35-28, Table 35-32, and
Table 35-33. For an MSR listed in Table 35-33 that also appears in the model-specific tables of prior generations,
Table 35-33 supercede prior generation tables.
Table 35-32 lists MSRs that are common to processors based on the Broadwell microarchitectures (including CPUID
signatures 06_3DH, 06_47H, 06_4FH, and 06_56H).
Table 35-32. Additional MSRs Common to Processors Based the Broadwell Microarchitectures
Register
Address
Hex
Dec
38EH
910
390H
912
Register Name
IA32_PERF_GLOBAL_
STATUS
Scope
Thread
Bit Description
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
0
Ovf_PMC0
1
Ovf_PMC1
2
Ovf_PMC2
3
Ovf_PMC3
31:4
Reserved.
32
Ovf_FixedCtr0
33
Ovf_FixedCtr1
34
Ovf_FixedCtr2
54:35
Reserved.
55
Trace_ToPA_PMI. See Section 36.2.6.2, “Table of Physical
Addresses (ToPA).”
60:56
Reserved.
61
Ovf_Uncore
62
Ovf_BufDSSAVE
63
CondChgd
IA32_PERF_GLOBAL_OVF_
CTRL
Thread
See Table 35-2. See Section 18.4.2, “Global Counter Control
Facilities.”
0
Set 1 to clear Ovf_PMC0
1
Set 1 to clear Ovf_PMC1
Vol. 3C 35-223
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-32. Additional MSRs Common to Processors Based the Broadwell Microarchitectures
Register
Address
Hex
560H
561H
570H
571H
Register Name
Scope
Bit Description
Dec
1376
1377
1392
1393
35-224 Vol. 3C
2
Set 1 to clear Ovf_PMC2
3
Set 1 to clear Ovf_PMC3
31:4
Reserved.
32
Set 1 to clear Ovf_FixedCtr0
33
Set 1 to clear Ovf_FixedCtr1
34
Set 1 to clear Ovf_FixedCtr2
54:35
Reserved.
55
Set 1 to clear Trace_ToPA_PMI. See Section 36.2.6.2, “Table of
Physical Addresses (ToPA).”
60:56
Reserved.
61
Set 1 to clear Ovf_Uncore
62
Set 1 to clear Ovf_BufDSSAVE
63
Set 1 to clear CondChgd
IA32_RTIT_OUTPUT_BASE
THREAD
Trace Output Base Register (R/W)
6:0
Reserved.
MAXPHYADDR1-1:7
Base physical address.
63:MAXPHYADDR
Reserved.
IA32_RTIT_OUTPUT_MASK
_PTRS
THREAD
Trace Output Mask Pointers Register (R/W)
6:0
Reserved.
31:7
MaskOrTableOffset
63:32
Output Offset.
IA32_RTIT_CTL
Thread
Trace Control Register (R/W)
0
TraceEn
1
Reserved, MBZ.
2
OS
3
User
6:4
Reserved, MBZ
7
CR3 filter
8
ToPA; writing 0 will #GP if also setting TraceEn
9
Reserved, MBZ
10
TSCEn
11
DisRETC
12
Reserved, MBZ
13
Reserved; writing 0 will #GP if also setting TraceEn
63:14
Reserved, MBZ.
IA32_RTIT_STATUS
Thread
Tracing Status Register (R/W)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-32. Additional MSRs Common to Processors Based the Broadwell Microarchitectures
Register
Address
Hex
572H
Register Name
Scope
Bit Description
Dec
1394
0
Reserved, writes ignored.
1
ContexEn, writes ignored.
2
TriggerEn, writes ignored.
3
Reserved
4
Error (R/W)
5
Stopped
63:6
Reserved, MBZ.
IA32_RTIT_CR3_MATCH
THREAD
Trace Filter CR3 Match Register (R/W)
4:0
Reserved
63:5
CR3[63:5] value to match
NOTES:
1. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
Table 35-33 lists MSRs that are specific to Intel Core M processors and 5th Generation Intel Core Processors.
Table 35-33. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register
Address
Hex
Dec
E2H
226
Register Name
MSR_PKG_CST_CONFIG_
CONTROL
Scope
Core
Bit Description
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-states.
See http://biosbits.org.
3:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
9:4
Reserved
10
I/O MWAIT Redirection Enable (R/W)
Vol. 3C 35-225
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-33. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register
Address
Hex
1ADH
Register Name
Scope
Bit Description
Dec
429
14:11
Reserved
15
CFG Lock (R/WO)
24:16
Reserved
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Enable Package C-State Auto-demotion (R/W)
30
Enable Package C-State Undemotion (R/W)
63:31
Reserved
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5core active.
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6core active.
639H
1593
63:48
Reserved.
MSR_PP0_ENERGY_STATUS Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
See Table 35-18, Table 35-19, Table 35-20, Table 35-23, Table 35-27, Table 35-28, Table 35-32 for other MSR definitions applicable
to processors with CPUID signature 06_3DH.
35.14
MSRS IN INTEL® XEON® PROCESSORS E5 V4 FAMILY
The MSRs listed in Table 35-34 are available and common to Intel® Xeon® Processor D product Family (CPUID
DisplayFamily_DisplayModel = 06_56H) and to Intel Xeon processors E5 v4, E7 v4 families (CPUID
DisplayFamily_DisplayModel = 06_4FH). They are based on the Broadwell microarchitecture.
See Section 35.14.1 for lists of tables of MSRs that are supported by Intel® Xeon® Processor D Family.
35-226 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Dec
4EH
78
Register Name
MSR_PPIN_CTL
Scope
Package
0
Bit Description
Protected Processor Inventory Number Enable Control (R/W)
LockOut (R/WO)
See Table 35-24.
1
Enable_PPIN (R/W)
See Table 35-24.
63:2
4FH
79
MSR_PPIN
Reserved.
Package
63:0
Protected Processor Inventory Number (R/O)
Protected Processor Inventory Number (R/O)
See Table 35-24.
CEH
206
MSR_PLATFORM_INFO
Package
7:0
15:8
See http://biosbits.org.
Reserved.
Package
Maximum Non-Turbo Ratio (R/O)
See Table 35-24.
22:16
23
Reserved.
Package
PPIN_CAP (R/O)
See Table 35-24.
27:24
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
See Table 35-24.
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
See Table 35-24.
30
Package
Programmable TJ OFFSET (R/O)
See Table 35-24.
39:31
47:40
Reserved.
Package
Maximum Efficiency Ratio (R/O)
See Table 35-24.
63:48
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
Reserved.
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-states.
See http://biosbits.org.
Vol. 3C 35-227
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package. The default is set as
factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the
processor are available.
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved
15
CFG Lock (R/WO)
16
Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6)
24:17
Reserved
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Package C State Demotion Enable (R/W)
30
Package C State UnDemotion Enable (R/W)
63:31
179H
377
35-228 Vol. 3C
IA32_MCG_CAP
Reserved
Thread
Global Machine Check Capability (R/O)
7:0
Count
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved.
23:16
MCG_EXT_CNT
24
MCG_SER_P
25
MCG_EM_P
26
MCG_ELOG_P
63:27
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Dec
17DH
390
Register Name
MSR_SMM_MCA_CAP
Scope
THREAD
Bit Description
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in
SMM.
57:0
Reserved
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is
supported and a host-space interface available to SMM handler.
59
Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported
and a host-space interface available to SMM handler.
63:60
19CH
412
IA32_THERM_STATUS
Reserved
Core
Thermal Monitor Status (R/W)
See Table 35-2.
0
Thermal status (RO)
See Table 35-2.
1
Thermal status log (R/WC0)
See Table 35-2.
2
PROTCHOT # or FORCEPR# status (RO)
See Table 35-2.
3
PROTCHOT # or FORCEPR# log (R/WC0)
See Table 35-2.
4
Critical Temperature status (RO)
See Table 35-2.
5
Critical Temperature status log (R/WC0)
See Table 35-2.
6
Thermal threshold #1 status (RO)
See Table 35-2.
7
Thermal threshold #1 log (R/WC0)
See Table 35-2.
8
Thermal threshold #2 status (RO)
See Table 35-2.
9
Thermal threshold #2 log (R/WC0)
See Table 35-2.
10
Power Limitation status (RO)
See Table 35-2.
11
Power Limitation log (R/WC0)
See Table 35-2.
12
Current Limit status (RO)
See Table 35-2.
Vol. 3C 35-229
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
13
Current Limit log (R/WC0)
See Table 35-2.
14
Cross Domain Limit status (RO)
See Table 35-2.
15
Cross Domain Limit log (R/WC0)
See Table 35-2.
22:16
Digital Readout (RO)
See Table 35-2.
26:23
Reserved.
30:27
Resolution in degrees Celsius (RO)
See Table 35-2.
31
Reading Valid (RO)
See Table 35-2.
63:32
1A2H
418
MSR_
TEMPERATURE_TARGET
Reserved.
Package
15:0
Reserved.
23:16
Temperature Target (RO)
See Table 35-24.
27:24
TCC Activation Offset (R/W)
See Table 35-24.
63:28
1ADH
429
MSR_TURBO_RATIO_LIMIT
Reserved.
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
1AEH
430
7:0
Package
Maximum Ratio Limit for 1C
15:8
Package
Maximum Ratio Limit for 2C
23:16
Package
Maximum Ratio Limit for 3C
31:24
Package
Maximum Ratio Limit for 4C
39:32
Package
Maximum Ratio Limit for 5C
47:40
Package
Maximum Ratio Limit for 6C
55:48
Package
Maximum Ratio Limit for 7C
63:56
Package
Maximum Ratio Limit for 8C
MSR_TURBO_RATIO_LIMIT1 Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
35-230 Vol. 3C
7:0
Package
Maximum Ratio Limit for 9C
15:8
Package
Maximum Ratio Limit for 10C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
606H
Register Name
Scope
Bit Description
Dec
1542
23:16
Package
Maximum Ratio Limit for 11C
31:24
Package
Maximum Ratio Limit for 12C
39:32
Package
Maximum Ratio Limit for 13C
47:40
Package
Maximum Ratio Limit for 14C
55:48
Package
Maximum Ratio Limit for 15C
63:56
Package
Maximum Ratio Limit for 16C
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
3:0
Package
Power Units
See Section 14.9.1, “RAPL Interfaces.”
7:4
Package
Reserved
12:8
Package
Energy Status Units
Energy related information (in Joules) is based on the multiplier,
1/2^ESU; where ESU is an unsigned integer represented by bits
12:8. Default value is 0EH (or 61 micro-joules)
15:13
Package
Reserved
19:16
Package
Time Units
See Section 14.9.1, “RAPL Interfaces.”
63:20
618H
1560
MSR_DRAM_POWER_LIMIT
Reserved
Package
DRAM RAPL Power Limit Control (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_
STATUS
Package
DRAM Energy Status (R/O)
Energy consumed by DRAM devices
31:0
Energy in 15.3 micro-joules. Requires BIOS configuration to enable
DRAM RAPL mode 0 (Direct VR).
63:32
Reserved
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O) See Section 14.9.5,
“DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
639H
1593
MSR_PP0_ENERGY_STATUS Package
Reserved (R/O)
Reads return 0
690H
1680
MSR_CORE_PERF_LIMIT_RE Package
ASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
0
PROCHOT Status (R0)
(frequency refers to processor core frequency)
When set, processor core frequency is reduced below the operating
system request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
Vol. 3C 35-231
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
2
Power Budget Management Status (R0)
When set, frequency is reduced below the operating system
request due to PBM limit
3
Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating system
request due to PCS limit
4
5
Reserved.
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system
request because the processor has detected that utilization is low
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g. maximum
electrical current consumption).
9
Reserved.
10
Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system
request due to Multi-Core Turbo limits
12:11
Reserved.
13
Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1
14
Core Max n-core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency
15
Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system
request.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
35-232 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
18
Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19
Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20
Reserved.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28:27
Reserved.
29
Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30
Core Max n-core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
31
Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:32
Reserved.
Vol. 3C 35-233
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
770H
1904
IA32_PM_ENABLE
Package
See Section 14.4.2, “Enabling HWP”
771H
1905
IA32_HWP_CAPABILITIES
Thread
See Section 14.4.3, “HWP Performance Range and Dynamic
Capabilities”
774H
1908
IA32_HWP_REQUEST
Thread
See Section 14.4.4, “Managing HWP”
777H
C8DH
1911
3213
7:0
Minimum Performance (R/W)
15:8
Maximum Performance (R/W)
23:16
Desired Performance (R/W)
63:24
Reserved.
IA32_HWP_STATUS
Thread
See Section 14.4.5, “HWP Feedback”
1:0
Reserved.
2
Excursion to Minimum (RO)
63:3
Reserved.
IA32_QM_EVTSEL
THREAD
Monitoring Event Select Register (R/W)
if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1
7:0
EventID (RW)
Event encoding:
0x00: no monitoring
0x01: L3 occupancy monitoring
0x02: Total memory bandwidth monitoring
0x03: Local memory bandwidth monitoring
All other encoding reserved
C8FH
C90H
3215
3216
31:8
Reserved.
41:32
RMID (RW)
63:42
Reserved.
IA32_PQR_ASSOC
THREAD
Resource Association Register (R/W)
9:0
RMID
31:10
Reserved
51:32
COS (R/W).
63: 52
Reserved
IA32_L3_QOS_MASK_0
Package
L3 Class Of Service Mask - COS 0 (R/W)
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0
C91H
3217
0:19
CBM: Bit vector of available L3 ways for COS 0 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_1
Package
L3 Class Of Service Mask - COS 1 (R/W)
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1
35-234 Vol. 3C
0:19
CBM: Bit vector of available L3 ways for COS 1 enforcement
63:20
Reserved
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Dec
C92H
3218
Register Name
IA32_L3_QOS_MASK_2
Scope
Package
Bit Description
L3 Class Of Service Mask - COS 2 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2
C93H
3219
0:19
CBM: Bit vector of available L3 ways for COS 2 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_3
Package
L3 Class Of Service Mask - COS 3 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3
C94H
3220
0:19
CBM: Bit vector of available L3 ways for COS 3 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_4
Package
L3 Class Of Service Mask - COS 4 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4
C95H
3221
0:19
CBM: Bit vector of available L3 ways for COS 4 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_5
Package
L3 Class Of Service Mask - COS 5 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5
C96H
3222
0:19
CBM: Bit vector of available L3 ways for COS 5 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_6
Package
L3 Class Of Service Mask - COS 6 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6
C97H
3223
0:19
CBM: Bit vector of available L3 ways for COS 6 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_7
Package
L3 Class Of Service Mask - COS 7 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7
C98H
3224
0:19
CBM: Bit vector of available L3 ways for COS 7 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_8
Package
L3 Class Of Service Mask - COS 8 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8
C99H
3225
0:19
CBM: Bit vector of available L3 ways for COS 8 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_9
Package
L3 Class Of Service Mask - COS 9 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9
C9AH
3226
0:19
CBM: Bit vector of available L3 ways for COS 9 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_10
Package
L3 Class Of Service Mask - COS 10 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=10
0:19
CBM: Bit vector of available L3 ways for COS 10 enforcement
63:20
Reserved
Vol. 3C 35-235
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based
on the Broadwell Microarchitecture
Register
Address
Hex
Dec
C9BH
3227
Register Name
IA32_L3_QOS_MASK_11
Scope
Package
Bit Description
L3 Class Of Service Mask - COS 11 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=11
C9CH
3228
0:19
CBM: Bit vector of available L3 ways for COS 11 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_12
Package
L3 Class Of Service Mask - COS 12 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=12
C9DH
3229
0:19
CBM: Bit vector of available L3 ways for COS 12 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_13
Package
L3 Class Of Service Mask - COS 13 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=13
C9EH
3230
0:19
CBM: Bit vector of available L3 ways for COS 13 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_14
Package
L3 Class Of Service Mask - COS 14 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=14
C9FH
3231
0:19
CBM: Bit vector of available L3 ways for COS 14 enforcement
63:20
Reserved
IA32_L3_QOS_MASK_15
Package
L3 Class Of Service Mask - COS 15 (R/W).
if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=15
0:19
CBM: Bit vector of available L3 ways for COS 15 enforcement
63:20
Reserved
35.14.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family
The MSRs listed in Table 35-35 are available to Intel® Xeon® Processor D Product Family (CPUID
DisplayFamily_DisplayModel = 06_56H). The Intel® Xeon® processor D product family is based on the Broadwell
microarchitecture and supports the MSR interfaces listed in Table 35-18, Table 35-27, Table 35-32, Table 35-34,
and Table 35-35.
Table 35-35. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H
Register
Address
Hex
Dec
1ACH
428
Register Name
Scope
MSR_TURBO_RATIO_LIMIT3 Package
Bit Description
Config Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
62:0
35-236 Vol. 3C
Package
Reserved
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-35. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
63
Package
Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).
286H
646
IA32_MC6_CTL2
Package
See Table 35-2.
287H
647
IA32_MC7_CTL2
Package
See Table 35-2.
289H
649
IA32_MC9_CTL2
Package
See Table 35-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 35-2.
291H
657
IA32_MC17_CTL2
Package
See Table 35-2.
292H
658
IA32_MC18_CTL2
Package
See Table 35-2.
293H
659
IA32_MC19_CTL2
Package
See Table 35-2.
418H
1048
IA32_MC6_CTL
Package
419H
1049
IA32_MC6_STATUS
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
41AH
1050
IA32_MC6_ADDR
Package
41BH
1051
IA32_MC6_MISC
Package
41CH
1052
IA32_MC7_CTL
Package
41DH
1053
IA32_MC7_STATUS
Package
41EH
1054
IA32_MC7_ADDR
Package
41FH
1055
IA32_MC7_MISC
Package
424H
1060
IA32_MC9_CTL
Package
425H
1061
IA32_MC9_STATUS
Package
426H
1062
IA32_MC9_ADDR
Package
427H
1063
IA32_MC9_MISC
Package
428H
1064
IA32_MC10_CTL
Package
429H
1065
IA32_MC10_STATUS
Package
42AH
1066
IA32_MC10_ADDR
Package
42BH
1067
IA32_MC10_MISC
Package
444H
1092
IA32_MC17_CTL
Package
445H
1093
IA32_MC17_STATUS
Package
446H
1094
IA32_MC17_ADDR
Package
447H
1095
IA32_MC17_MISC
Package
448H
1096
IA32_MC18_CTL
Package
449H
1097
IA32_MC18_STATUS
Package
44AH
1098
IA32_MC18_ADDR
Package
44BH
1099
IA32_MC18_MISC
Package
Bank MC6 reports MC error from the integrated I/O module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC7 reports MC error from the home agent HA 0.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 10 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 10 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC17 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12,
CBo15.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC18 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13,
CBo16.
Vol. 3C 35-237
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-35. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H
Register
Address
Register Name
Scope
Hex
Dec
44CH
1100
IA32_MC19_CTL
Package
44DH
1101
IA32_MC19_STATUS
Package
44EH
1102
IA32_MC19_ADDR
Package
44FH
1103
IA32_MC19_MISC
Package
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC19 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14,
CBo17.
See Table 35-18, Table 35-27, Table 35-32, and Table 35-34 for other MSR definitions applicable to processors with CPUID signature
06_56H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the factory-set configuration is dependent on features specific to the processor and the platform.
35.14.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families
The MSRs listed in Table 35-35 are available to Intel® Xeon® Processor E5 v4 and E7 v4 Families (CPUID
DisplayFamily_DisplayModel = 06_4FH). The Intel® Xeon® processor E5 v4 family is based on the Broadwell microarchitecture and supports the MSR interfaces listed in Table 35-18, Table 35-19, Table 35-27, Table 35-32, Table
35-34, and Table 35-36.
Table 35-36. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH
Register
Address
Hex
Dec
1ACH
428
Register Name
Scope
MSR_TURBO_RATIO_LIMIT3 Package
Bit Description
Config Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
62:0
Package
Reserved
63
Package
Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration (Default).
285H
645
IA32_MC5_CTL2
Package
See Table 35-2.
286H
646
IA32_MC6_CTL2
Package
See Table 35-2.
287H
647
IA32_MC7_CTL2
Package
See Table 35-2.
288H
648
IA32_MC8_CTL2
Package
See Table 35-2.
289H
649
IA32_MC9_CTL2
Package
See Table 35-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 35-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 35-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 35-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 35-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 35-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 35-2.
35-238 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-36. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
290H
656
IA32_MC16_CTL2
Package
See Table 35-2.
291H
657
IA32_MC17_CTL2
Package
See Table 35-2.
292H
658
IA32_MC18_CTL2
Package
See Table 35-2.
293H
659
IA32_MC19_CTL2
Package
See Table 35-2.
294H
660
IA32_MC20_CTL2
Package
See Table 35-2.
295H
661
IA32_MC21_CTL2
Package
See Table 35-2.
414H
1044
IA32_MC5_CTL
Package
415H
1045
IA32_MC5_STATUS
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
416H
1046
IA32_MC5_ADDR
Package
417H
1047
IA32_MC5_MISC
Package
418H
1048
IA32_MC6_CTL
Package
419H
1049
IA32_MC6_STATUS
Package
41AH
1050
IA32_MC6_ADDR
Package
41BH
1051
IA32_MC6_MISC
Package
41CH
1052
IA32_MC7_CTL
Package
41DH
1053
IA32_MC7_STATUS
Package
41EH
1054
IA32_MC7_ADDR
Package
41FH
1055
IA32_MC7_MISC
Package
420H
1056
IA32_MC8_CTL
Package
421H
1057
IA32_MC8_STATUS
Package
422H
1058
IA32_MC8_ADDR
Package
423H
1059
IA32_MC8_MISC
Package
424H
1060
IA32_MC9_CTL
Package
425H
1061
IA32_MC9_STATUS
Package
426H
1062
IA32_MC9_ADDR
Package
427H
1063
IA32_MC9_MISC
Package
428H
1064
IA32_MC10_CTL
Package
429H
1065
IA32_MC10_STATUS
Package
42AH
1066
IA32_MC10_ADDR
Package
42BH
1067
IA32_MC10_MISC
Package
42CH
1068
IA32_MC11_CTL
Package
42DH
1069
IA32_MC11_STATUS
Package
42EH
1070
IA32_MC11_ADDR
Package
42FH
1071
IA32_MC11_MISC
Package
Bank MC5 reports MC error from the Intel QPI 0 module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC6 reports MC error from the integrated I/O module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC7 reports MC error from the home agent HA 0.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC8 reports MC error from the home agent HA 1.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
Vol. 3C 35-239
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-36. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH
Register
Address
Register Name
Scope
Hex
Dec
430H
1072
IA32_MC12_CTL
Package
431H
1073
IA32_MC12_STATUS
Package
432H
1074
IA32_MC12_ADDR
Package
433H
1075
IA32_MC12_MISC
Package
434H
1076
IA32_MC13_CTL
Package
435H
1077
IA32_MC13_STATUS
Package
436H
1078
IA32_MC13_ADDR
Package
437H
1079
IA32_MC13_MISC
Package
438H
1080
IA32_MC14_CTL
Package
439H
1081
IA32_MC14_STATUS
Package
43AH
1082
IA32_MC14_ADDR
Package
43BH
1083
IA32_MC14_MISC
Package
43CH
1084
IA32_MC15_CTL
Package
43DH
1085
IA32_MC15_STATUS
Package
43EH
1086
IA32_MC15_ADDR
Package
43FH
1087
IA32_MC15_MISC
Package
440H
1088
IA32_MC16_CTL
Package
441H
1089
IA32_MC16_STATUS
Package
442H
1090
IA32_MC16_ADDR
Package
443H
1091
IA32_MC16_MISC
Package
444H
1092
IA32_MC17_CTL
Package
445H
1093
IA32_MC17_STATUS
Package
446H
1094
IA32_MC17_ADDR
Package
447H
1095
IA32_MC17_MISC
Package
448H
1096
IA32_MC18_CTL
Package
449H
1097
IA32_MC18_STATUS
Package
44AH
1098
IA32_MC18_ADDR
Package
44BH
1099
IA32_MC18_MISC
Package
44CH
1100
IA32_MC19_CTL
Package
44DH
1101
IA32_MC19_STATUS
Package
44EH
1102
IA32_MC19_ADDR
Package
44FH
1103
IA32_MC19_MISC
Package
450H
1104
IA32_MC20_CTL
Package
451H
1105
IA32_MC20_STATUS
Package
452H
1106
IA32_MC20_ADDR
Package
453H
1107
IA32_MC20_MISC
Package
35-240 Vol. 3C
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 through MC 16 report MC error from each channel of
the integrated memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC17 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12,
CBo15.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC18 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13,
CBo16.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC19 reports MC error from the following pair of CBo/L3
Slices (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14,
CBo17.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC20 reports MC error from the Intel QPI 1 module.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-36. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH
Register
Address
Register Name
Scope
Hex
Dec
454H
1108
IA32_MC21_CTL
Package
455H
1109
IA32_MC21_STATUS
Package
456H
1110
IA32_MC21_ADDR
Package
457H
1111
IA32_MC21_MISC
Package
C81H
3201
IA32_L3_QOS_CFG
Package
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC21 reports MC error from the Intel QPI 2 module.
Cache Allocation Technology Configuration (R/W)
0
CAT Enable. Set 1 to enable Cache Allocation Technology
63:1
Reserved.
See Table 35-18, Table 35-19, Table 35-27, and Table 35-28 for other MSR definitions applicable to processors with CPUID signature
06_45H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the factory-set configuration is dependent on features specific to the processor and the platform.
35.15
MSRS IN THE 6TH GENERATION INTEL® CORE™ PROCESSORS
The 6th generation Intel® Core™ processor family is based on the Skylake microarchitecture. They have CPUID
DisplayFamily_DisplayModel signatures of 06_4EH and 06_5EH, supports the MSR interfaces listed in Table 35-18,
Table 35-19, Table 35-23, Table 35-27, Table 35-33, Table 35-37, and Table 35-38. For an MSR listed in Table 35-37
that also appears in the model-specific tables of prior generations, Table 35-37 supercede prior generation tables.
The notation of “Platform” in the Scope column (with respect to MSR_PLATFORM_ENERGY_COUNTER and
MSR_PLATFORM_POWER_LIMIT) is limited to the power-delivery domain and the specifics of the power delivery
integration may vary by platform vendor’s implementation.
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Dec
3AH
58
Register Name
IA32_FEATURE_CONTROL
Scope
Thread
Bit Description
Control Features in Intel 64 Processor (R/W)
See Table 35-2.
FEH
254
0
Lock (R/WL)
1
Enable VMX inside SMX operation (R/WL)
2
Enable VMX outside SMX operation (R/WL)
14:8
SENTER local functions enables (R/WL)
15
SENTER global functions enable (R/WL)
18
SGX global functions enable (R/WL)
20
LMCE_ON (R/WL)
63:21
Reserved.
IA32_MTRRCAP
Thread
MTRR Capality (RO, Architectural). See Table 35-2
Vol. 3C 35-241
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Dec
19CH
412
Register Name
IA32_THERM_STATUS
Scope
Core
Bit Description
Thermal Monitor Status (R/W)
See Table 35-2.
0
Thermal status (RO)
See Table 35-2.
1
Thermal status log (R/WC0)
See Table 35-2.
2
PROTCHOT # or FORCEPR# status (RO)
See Table 35-2.
3
PROTCHOT # or FORCEPR# log (R/WC0)
See Table 35-2.
4
Critical Temperature status (RO)
See Table 35-2.
5
Critical Temperature status log (R/WC0)
See Table 35-2.
6
Thermal threshold #1 status (RO)
See Table 35-2.
7
Thermal threshold #1 log (R/WC0)
See Table 35-2.
8
Thermal threshold #2 status (RO)
See Table 35-2.
9
Thermal threshold #2 log (R/WC0)
See Table 35-2.
10
Power Limitation status (RO)
See Table 35-2.
11
Power Limitation log (R/WC0)
See Table 35-2.
12
Current Limit status (RO)
See Table 35-2.
13
Current Limit log (R/WC0)
See Table 35-2.
14
Cross Domain Limit status (RO)
See Table 35-2.
15
Cross Domain Limit log (R/WC0)
See Table 35-2.
22:16
Digital Readout (RO)
See Table 35-2.
26:23
35-242 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
30:27
Resolution in degrees Celsius (RO)
See Table 35-2.
31
Reading Valid (RO)
See Table 35-2.
63:32
1ADH
429
MSR_TURBO_RATIO_LIMIT
Reserved.
Package
Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32
1C9H
457
MSR_LASTBRANCH_TOS
Reserved.
Thread
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-4) that points to the MSR containing the
most recent branch record.
300H
768
MSR_SGXOWNER0
Package
63:0
301H
38EH
768
910
MSR_SGXOWNER1
Lower 64 Bit OwnerEpoch Component of SGX Key (RO).
Low 64 bits of an 128-bit external entropy value for key
derivation of an enclave.
Package
Upper 64 Bit OwnerEpoch Component of SGX Key (RO).
63:0
Upper 64 bits of an 128-bit external entropy value for key
derivation of an enclave.
IA32_PERF_GLOBAL_
STATUS
See Table 35-2. See Section 18.2.4, “Architectural Performance
Monitoring Version 4.”
0
Thread
Ovf_PMC0
1
Thread
Ovf_PMC1
2
Thread
Ovf_PMC2
3
Thread
Ovf_PMC3
4
Thread
Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
5
Thread
Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6
Thread
Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
7
Thread
Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
31:8
32
Reserved.
Thread
Ovf_FixedCtr0
Vol. 3C 35-243
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Dec
33
Thread
Ovf_FixedCtr1
34
Thread
Ovf_FixedCtr2
54:35
55
Reserved.
Thread
57:56
390H
912
58
Thread
LBR_Frz.
59
Thread
CTR_Frz.
60
Thread
ASCI.
61
Thread
Ovf_Uncore
62
Thread
Ovf_BufDSSAVE
63
Thread
CondChgd
IA32_PERF_GLOBAL_STAT
US_RESET
See Table 35-2. See Section 18.2.4, “Architectural Performance
Monitoring Version 4.”
0
Thread
Set 1 to clear Ovf_PMC0
1
Thread
Set 1 to clear Ovf_PMC1
2
Thread
Set 1 to clear Ovf_PMC2
3
Thread
Set 1 to clear Ovf_PMC3
4
Thread
Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
5
Thread
Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6
Thread
Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
7
Thread
Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
Reserved.
32
Thread
Set 1 to clear Ovf_FixedCtr0
33
Thread
Set 1 to clear Ovf_FixedCtr1
34
Thread
Set 1 to clear Ovf_FixedCtr2
54:35
55
Reserved.
Thread
57:56
913
Set 1 to clear Trace_ToPA_PMI.
Reserved.
58
Thread
Set 1 to clear LBR_Frz.
59
Thread
Set 1 to clear CTR_Frz.
60
Thread
Set 1 to clear ASCI.
61
Thread
Set 1 to clear Ovf_Uncore
62
Thread
Set 1 to clear Ovf_BufDSSAVE
63
Thread
Set 1 to clear CondChgd
IA32_PERF_GLOBAL_STAT
US_SET
0
35-244 Vol. 3C
Trace_ToPA_PMI.
Reserved.
31:8
391H
Bit Description
See Table 35-2. See Section 18.2.4, “Architectural Performance
Monitoring Version 4.”
Thread
Set 1 to cause Ovf_PMC0 = 1
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Dec
1
Thread
Set 1 to cause Ovf_PMC1 = 1
2
Thread
Set 1 to cause Ovf_PMC2 = 1
3
Thread
Set 1 to cause Ovf_PMC3 = 1
4
Thread
Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4)
5
Thread
Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5)
6
Thread
Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6)
7
Thread
Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7)
31:8
Reserved.
32
Thread
Set 1 to cause Ovf_FixedCtr0 = 1
33
Thread
Set 1 to cause Ovf_FixedCtr1 = 1
34
Thread
Set 1 to cause Ovf_FixedCtr2 = 1
54:35
55
Reserved.
Thread
57:56
Set 1 to cause LBR_Frz = 1
59
Thread
Set 1 to cause CTR_Frz = 1
60
Thread
Set 1 to cause ASCI = 1
61
Thread
Set 1 to cause Ovf_Uncore
62
Thread
Set 1 to cause Ovf_BufDSSAVE
63
Reserved.
See Table 35-2.
IA32_PERF_GLOBAL_INUSE
3F7H
1015
MSR_PEBS_FRONTEND
560H
1376
Reserved.
Thread
913
1280
Set 1 to cause Trace_ToPA_PMI = 1
58
392H
500H
Bit Description
Thread
FrontEnd Precise Event Condition Select (R/W)
2:0
Event Code Select
3
Reserved.
4
Event Code Select High
7:5
Reserved.
19:8
IDQ_Bubble_Length Specifier
22:20
IDQ_Bubble_Width Specifier
63:23
Reserved
IA32_SGX_SVN_STATUS
Thread
Status and SVN Threshold of SGX Support for ACM (RO).
0
Lock. See Section 42.11.3, “Interactions with Authenticated Code
Modules (ACMs)”
15:1
Reserved.
23:16
SGX_SVN_SINIT. See Section 42.11.3, “Interactions with
Authenticated Code Modules (ACMs)”
63:24
Reserved.
IA32_RTIT_OUTPUT_BASE
Thread
Trace Output Base Register (R/W). See Table 35-2.
Vol. 3C 35-245
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
561H
1377
IA32_RTIT_OUTPUT_MASK
_PTRS
Thread
Trace Output Mask Pointers Register (R/W). See Table 35-2.
570H
1392
IA32_RTIT_CTL
Thread
Trace Control Register (R/W)
571H
572H
1393
1394
0
TraceEn
1
CYCEn
2
OS
3
User
6:4
Reserved, MBZ
7
CR3 filter
8
ToPA; writing 0 will #GP if also setting TraceEn
9
MTCEn
10
TSCEn
11
DisRETC
12
Reserved, MBZ
13
BranchEn
17:14
MTCFreq
18
Reserved, MBZ
22:19
CYCThresh
23
Reserved, MBZ
27:24
PSBFreq
31:28
Reserved, MBZ
35:32
ADDR0_CFG
39:36
ADDR1_CFG
63:40
Reserved, MBZ.
IA32_RTIT_STATUS
Tracing Status Register (R/W)
0
FilterEn, writes ignored.
1
ContexEn, writes ignored.
2
TriggerEn, writes ignored.
3
Reserved
4
Error (R/W)
5
Stopped
31:6
Reserved. MBZ
48:32
PacketByteCnt
63:49
Reserved, MBZ.
IA32_RTIT_CR3_MATCH
4:0
35-246 Vol. 3C
Thread
Thread
Trace Filter CR3 Match Register (R/W)
Reserved
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Dec
63:5
580H
1408
IA32_RTIT_ADDR0_A
CR3[63:5] value to match
Thread
63:0
581H
1409
IA32_RTIT_ADDR0_B
1410
IA32_RTIT_ADDR1_A
Thread
639H
1411
1593
IA32_RTIT_ADDR1_B
Region 0 End Address (R/W)
See Table 35-2.
Thread
63:0
583H
Region 0 Start Address (R/W)
See Table 35-2.
63:0
582H
Bit Description
Region 1 Start Address (R/W)
See Table 35-2.
Thread
Region 1 End Address (R/W)
63:0
See Table 35-2.
MSR_PP0_ENERGY_STATUS Package
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
64DH
1613
MSR_PLATFORM_ENERGY_
COUNTER
Platform*
Platform Energy Counter. (R/O).
This MSR is valid only if both platform vendor hardware
implementation and BIOS enablement support it. This MSR will read
0 if not valid.
31:0
Total energy consumed by all devices in the platform that receive
power from integrated power delivery mechanism, Included
platform devices are processor cores, SOC, memory, add-on or
peripheral devices that get powered directly from the platform
power delivery means. The energy units are specified in the
MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
63:32
Reserved.
64EH
1614
MSR_PPERF
Thread
Productive Performance Count. (R/O).
63:0
Hardware’s view of workload scalability. See Section 14.4.5.1
64FH
1615
MSR_CORE_PERF_LIMIT_RE Package
ASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
0
PROCHOT Status (R0)
(frequency refers to processor core frequency)
When set, frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
3:2
Reserved.
4
Residency State Regulation Status (R0)
When set, frequency is reduced below the operating system
request due to residency state regulation limit.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced below the operating system
request due to Running Average Thermal Limit (RATL).
Vol. 3C 35-247
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from a processor Voltage Regulator
(VR).
7
VR Therm Design Current Status (R0)
When set, frequency is reduced below the operating system
request due to VR thermal design current limit.
8
Other Status (R0)
When set, frequency is reduced below the operating system
request due to electrical or other constraints.
9
Reserved
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package/platform-level power limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package/platform-level power limiting PL2/PL3.
12
Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system
request due to multi-core turbo limits.
13
Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system
request due to Turbo transition attenuation. This prevents
performance degradation due to frequent operating ratio changes.
15:14
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18
Reserved.
20
Residency State Regulation Log
When set, indicates that the Residency State Regulation Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
35-248 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
VR Thermal Design Current Log
When set, indicates that the VR TDC Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24
Other Log
When set, indicates that the Other Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package or Platform Level PL1 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package or Platform Level PL2/PL3
Power Limiting Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software writing 0.
28
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30
652H
1618
MSR_PKG_HDC_CONFIG
Reserved.
Package
2:0
HDC Configuration (R/W).
PKG_Cx_Monitor.
Configures Package Cx state threshold for
MSR_PKG_HDC_DEEP_RESIDENCY
63: 3
653H
1619
MSR_CORE_HDC_
Reserved
Core
Core HDC Idle Residency. (R/O).
RESIDENCY
63:0
Core_Cx_Duty_Cycle_Cnt.
Vol. 3C 35-249
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Dec
655H
1621
Register Name
MSR_PKG_HDC_SHALLOW_
RESIDENCY
Scope
Package
63:0
656H
1622
MSR_PKG_HDC_DEEP_
Bit Description
Accumulate the cycles the package was in C2 state and at least one
logical processor was in forced idle. (R/O).
Pkg_C2_Duty_Cycle_Cnt.
Package
Package Cx HDC Idle Residency. (R/O).
Package
Core-count Weighted C0 Residency. (R/O).
RESIDENCY
63:0
658H
1624
MSR_WEIGHTED_CORE_C0
Pkg_Cx_Duty_Cycle_Cnt.
63:0
659H
1625
MSR_ANY_CORE_C0
Increment at the same rate as the TSC. The increment each cycle is
weighted by the number of processor cores in the package that
reside in C0. If N cores are simultaneously in C0, then each cycle the
counter increments by N.
Package
63:0
65AH
1626
MSR_ANY_GFXE_C0
Increment at the same rate as the TSC. The increment each cycle is
one if any processor core in the package is in C0.
Package
63:0
65BH
1627
MSR_CORE_GFXE_OVERLA
P_C0
1628
MSR_PLATFORM_POWER_L
IMIT
Any Graphics Engine C0 Residency. (R/O)
Increment at the same rate as the TSC. The increment each cycle is
one if any processor graphic device’s compute engines are in C0.
Package
63:0
65CH
Any Core C0 Residency. (R/O)
Core and Graphics Engine Overlapped C0 Residency. (R/O)
Increment at the same rate as the TSC. The increment each cycle is
one if at least one compute engine of the processor graphics is in
C0 and at least one processor core in the package is also in C0.
Platform*
Platform Power Limit Control (R/W-L)
Allows platform BIOS to limit power consumption of the platform
devices to the specified values. The Long Duration power
consumption is specified via Platform_Power_Limit_1 and
Platform_Power_Limit_1_Time. The Short Duration power
consumption limit is specified via the Platform_Power_Limit_2 with
duration chosen by the processor.
The processor implements an exponential-weighted algorithm in
the placement of the time windows.
14:0
Platform Power Limit #1.
Average Power limit value which the platform must not exceed
over a time window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies
with product skus. The unit is specified in MSR_RAPLPOWER_UNIT.
15
Enable Platform Power Limit #1.
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit #1 over
the time window specified by Power Limit #1 Time Window.
35-250 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
16
Platform Clamping Limitation #1.
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit #1 value.
This bit is writeable only when CPUID (EAX=6):EAX[4] is set.
23:17
Time Window for Platform Power Limit #1.
Specifies the duration of the time window over which Platform
Power Limit 1 value should be maintained for sustained long
duration. This field is made up of two numbers from the following
equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17].
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, The unit is specified in
MSR_RAPLPOWER_UNIT[Time Unit].
31:24
Reserved
46:32
Platform Power Limit #2.
Average Power limit value which the platform must not exceed
over the Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration
Power Limit (i.e. Platform Power Limit # 1)
47
Enable Platform Power Limit #2.
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit #2 over
the Short Duration time window.
48
Platform Clamping Limitation #2.
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit #2 value.
690H
1680
62:49
Reserved
63
Lock. Setting this bit will lock all other bits of this MSR until system
RESET.
MSR_
Thread
LASTBRANCH_16_FROM_IP
Last Branch Record 16 From IP (R/W)
One of 32 triplets of last branch record registers on the last branch
record stack. This part of the stack contains pointers to the source
instruction. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.10
691H
1681
MSR_
Thread
LASTBRANCH_17_FROM_IP
Last Branch Record 17 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Vol. 3C 35-251
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Dec
692H
1682
693H
694H
695H
696H
697H
698H
699H
69AH
69BH
69CH
69DH
69EH
69FH
6B0H
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1712
Register Name
Scope
Bit Description
MSR_
Thread
LASTBRANCH_18_FROM_IP
Last Branch Record 18 From IP (R/W)
Thread
MSR_
LASTBRANCH_19_FROM_IP
Last Branch Record 19From IP (R/W)
MSR_
Thread
LASTBRANCH_20_FROM_IP
Last Branch Record 20 From IP (R/W)
MSR_
Thread
LASTBRANCH_21_FROM_IP
Last Branch Record 21 From IP (R/W)
MSR_
Thread
LASTBRANCH_22_FROM_IP
Last Branch Record 22 From IP (R/W)
MSR_
Thread
LASTBRANCH_23_FROM_IP
Last Branch Record 23 From IP (R/W)
MSR_
Thread
LASTBRANCH_24_FROM_IP
Last Branch Record 24 From IP (R/W)
MSR_
Thread
LASTBRANCH_25_FROM_IP
Last Branch Record 25 From IP (R/W)
MSR_
Thread
LASTBRANCH_26_FROM_IP
Last Branch Record 26 From IP (R/W)
MSR_
Thread
LASTBRANCH_27_FROM_IP
Last Branch Record 27 From IP (R/W)
MSR_
Thread
LASTBRANCH_28_FROM_IP
Last Branch Record 28 From IP (R/W)
MSR_
Thread
LASTBRANCH_29_FROM_IP
Last Branch Record 29 From IP (R/W)
MSR_
Thread
LASTBRANCH_30_FROM_IP
Last Branch Record 30 From IP (R/W)
MSR_
Thread
LASTBRANCH_31_FROM_IP
Last Branch Record 31 From IP (R/W)
MSR_GRAPHICS_PERF_LIMI
T_REASONS
Indicator of Frequency Clipping in the Processor Graphics (R/W)
0
Package
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
See description of MSR_LASTBRANCH_0_FROM_IP.
(frequency refers to processor graphics frequency)
PROCHOT Status (R0)
When set, frequency is reduced due to assertion of external
PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2
Reserved.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average thermal
limit.
35-252 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
6
VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert from a
processor Voltage Regulator.
7
VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8
Other Status (R0)
When set, frequency is reduced due to electrical or other
constraints.
9
Reserved
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/platform-level
power limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced due to package/platform-level
power limiting PL2/PL3.
12
Inefficient Operation Status (R0)
When set, processor graphics frequency is operating below target
frequency.
15:13
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20:18
Reserved.
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Vol. 3C 35-253
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
24
Other Log
When set, indicates that the OTHER Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level PL1 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level PL2 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Inefficient Operation Log
When set, indicates that the Inefficient Operation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:29
6B1H
1713
MSR_RING_PERF_LIMIT_RE
ASONS
0
Reserved.
Package
Indicator of Frequency Clipping in the Ring Interconnect (R/W)
(frequency refers to ring interconnect in the uncore)
PROCHOT Status (R0)
When set, frequency is reduced due to assertion of external
PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2
Reserved.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average thermal
limit.
6
VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert from a
processor Voltage Regulator.
7
VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8
Other Status (R0)
When set, frequency is reduced due to electrical or other
constraints.
9
Reserved.
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/Platform-level
power limiting PL1.
35-254 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Register Name
Scope
Bit Description
Dec
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced due to package/Platform-level
power limiting PL2/PL3.
15:12
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20:18
Reserved.
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24
Other Log
When set, indicates that the OTHER Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level PL1 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level PL2 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:28
Reserved.
Vol. 3C 35-255
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Dec
6D0H
1744
Register Name
MSR_
LASTBRANCH_16_TO_IP
Scope
Thread
Bit Description
Last Branch Record 16 To IP (R/W)
One of 32 triplets of last branch record registers on the last branch
record stack. This part of the stack contains pointers to the
destination instruction. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.10
6D1H
6D2H
6D3H
6D4H
6D5H
6D6H
6D7H
6D8H
6D9H
6DAH
6DBH
6DCH
6DDH
6DEH
6DFH
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
MSR_
LASTBRANCH_17_TO_IP
Thread
MSR_
LASTBRANCH_18_TO_IP
Thread
MSR_
LASTBRANCH_19_TO_IP
Thread
MSR_
LASTBRANCH_20_TO_IP
Thread
MSR_
LASTBRANCH_21_TO_IP
Thread
MSR_
LASTBRANCH_22_TO_IP
Thread
MSR_
LASTBRANCH_23_TO_IP
Thread
MSR_
LASTBRANCH_24_TO_IP
Thread
MSR_
LASTBRANCH_25_TO_IP
Thread
MSR_
LASTBRANCH_26_TO_IP
Thread
MSR_
LASTBRANCH_27_TO_IP
Thread
MSR_
LASTBRANCH_28_TO_IP
Thread
MSR_
LASTBRANCH_29_TO_IP
Thread
MSR_
LASTBRANCH_30_TO_IP
Thread
MSR_
LASTBRANCH_31_TO_IP
Thread
Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 25 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 26 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 27 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 28 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 29 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 30 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 31 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
770H
1904
IA32_PM_ENABLE
Package
See Section 14.4.2, “Enabling HWP”
771H
1905
IA32_HWP_CAPABILITIES
Thread
See Section 14.4.3, “HWP Performance Range and Dynamic
Capabilities”
35-256 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
772H
1906
IA32_HWP_REQUEST_PKG
Package
See Section 14.4.4, “Managing HWP”
773H
1907
IA32_HWP_INTERRUPT
Thread
See Section 14.4.6, “HWP Notifications”
774H
1908
IA32_HWP_REQUEST
Thread
See Section 14.4.4, “Managing HWP”
7:0
Minimum Performance (R/W).
15:8
Maximum Performance (R/W).
23:16
Desired Performance (R/W).
31:24
Energy/Performance Preference (R/W).
41:32
Activity Window (R/W).
42
Package Control (R/W).
63:43
Reserved.
777H
1911
IA32_HWP_STATUS
Thread
See Section 14.4.5, “HWP Feedback”
D90H
3472
IA32_BNDCFGS
Thread
See Table 35-2.
DA0H
3488
IA32_XSS
Thread
See Table 35-2.
DB0H
3504
IA32_PKG_HDC_CTL
Package
See Section 14.5.2, “Package level Enabling HDC”
DB1H
3505
IA32_PM_CTL1
Thread
See Section 14.5.3, “Logical-Processor Level HDC Control”
DB2H
3506
IA32_THREAD_STALL
Thread
See Section 14.5.4.1, “IA32_THREAD_STALL”
DC0H
3520
MSR_LBR_INFO_0
Thread
Last Branch Record 0 Additional Information (R/W)
One of 32 triplet of last branch record registers on the last branch
record stack. This part of the stack contains flag, TSX-related and
elapsed cycle information. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.7.1, “LBR Stack.”
DC1H
3521
MSR_LBR_INFO_1
Thread
Last Branch Record 1 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC2H
3522
MSR_LBR_INFO_2
Thread
Last Branch Record 2 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC3H
3523
MSR_LBR_INFO_3
Thread
Last Branch Record 3 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC4H
3524
MSR_LBR_INFO_4
Thread
Last Branch Record 4 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC5H
3525
MSR_LBR_INFO_5
Thread
Last Branch Record 5 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC6H
3526
MSR_LBR_INFO_6
Thread
Last Branch Record 6 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC7H
3527
MSR_LBR_INFO_7
Thread
Last Branch Record 7 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC8H
3528
MSR_LBR_INFO_8
Thread
Last Branch Record 8 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Vol. 3C 35-257
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Dec
DC9H
3529
Register Name
MSR_LBR_INFO_9
Scope
Thread
Bit Description
Last Branch Record 9 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCAH
3530
MSR_LBR_INFO_10
Thread
Last Branch Record 10 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCBH
3531
MSR_LBR_INFO_11
Thread
Last Branch Record 11 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCCH
3532
MSR_LBR_INFO_12
Thread
Last Branch Record 12 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCDH
3533
MSR_LBR_INFO_13
Thread
Last Branch Record 13 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCEH
3534
MSR_LBR_INFO_14
Thread
Last Branch Record 14 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCFH
3535
MSR_LBR_INFO_15
Thread
Last Branch Record 15 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD0H
3536
MSR_LBR_INFO_16
Thread
Last Branch Record 16 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD1H
3537
MSR_LBR_INFO_17
Thread
Last Branch Record 17 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD2H
3538
MSR_LBR_INFO_18
Thread
Last Branch Record 18 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD3H
3539
MSR_LBR_INFO_19
Thread
Last Branch Record 19 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD4H
3520
MSR_LBR_INFO_20
Thread
Last Branch Record 20 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD5H
3521
MSR_LBR_INFO_21
Thread
Last Branch Record 21 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD6H
3522
MSR_LBR_INFO_22
Thread
Last Branch Record 22 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD7H
3523
MSR_LBR_INFO_23
Thread
Last Branch Record 23 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD8H
3524
MSR_LBR_INFO_24
Thread
Last Branch Record 24 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD9H
3525
MSR_LBR_INFO_25
Thread
Last Branch Record 25 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDAH
3526
MSR_LBR_INFO_26
Thread
Last Branch Record 26 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDBH
3527
MSR_LBR_INFO_27
Thread
Last Branch Record 27 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
35-258 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Hex
Dec
DDCH
3528
Register Name
MSR_LBR_INFO_28
Scope
Thread
Bit Description
Last Branch Record 28 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDDH
3529
MSR_LBR_INFO_29
Thread
Last Branch Record 29 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDEH
3530
MSR_LBR_INFO_30
Thread
Last Branch Record 30 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDFH
3531
MSR_LBR_INFO_31
Thread
Last Branch Record 31 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Table 35-38 lists the MSRs of uncore PMU for Intel processors with CPUID DisplayFamily_DisplayModel signatures of
06_4EH and 06_5EH.
Table 35-38. Uncore PMU MSRs Supported by 6th Generation Intel® Core™ Processors
Register
Address
Hex
Dec
394H
916
395H
396H
917
918
Register Name
MSR_UNC_PERF_FIXED_
CTRL
Scope
Package
Bit Description
Uncore fixed counter control (R/W)
19:0
Reserved
20
Enable overflow propagation
21
Reserved
22
Enable counting
63:23
Reserved.
MSR_UNC_PERF_FIXED_
CTR
Package
Uncore fixed counter
43:0
Current count
63:44
Reserved.
MSR_UNC_CBO_CONFIG
Package
Uncore C-Box configuration information (R/O)
3:0
Specifies the number of C-Box units with programmable
counters (including processor cores and processor graphics),
63:4
Reserved.
3B0H
946
MSR_UNC_ARB_PERFCTR0
Package
Uncore Arb unit, performance counter 0
3B1H
947
MSR_UNC_ARB_PERFCTR1
Package
Uncore Arb unit, performance counter 1
3B2H
944
MSR_UNC_ARB_
PERFEVTSEL0
Package
Uncore Arb unit, counter 0 event select MSR
3B3H
945
MSR_UNC_ARB_
PERFEVTSEL1
Package
Uncore Arb unit, counter 1 event select MSR
Vol. 3C 35-259
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-38. Uncore PMU MSRs Supported by 6th Generation Intel® Core™ Processors
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
700H
1792
MSR_UNC_CBO_0_
PERFEVTSEL0
Package
Uncore C-Box 0, counter 0 event select MSR
701H
1793
MSR_UNC_CBO_0_
PERFEVTSEL1
Package
Uncore C-Box 0, counter 1 event select MSR
706H
1798
MSR_UNC_CBO_0_PERFCTR0
Package
Uncore C-Box 0, performance counter 0
707H
1799
MSR_UNC_CBO_0_PERFCTR1
Package
Uncore C-Box 0, performance counter 1
710H
1808
MSR_UNC_CBO_1_
PERFEVTSEL0
Package
Uncore C-Box 1, counter 0 event select MSR
711H
1809
MSR_UNC_CBO_1_
PERFEVTSEL1
Package
Uncore C-Box 1, counter 1 event select MSR
716H
1814
MSR_UNC_CBO_1_PERFCTR0
Package
Uncore C-Box 1, performance counter 0
717H
1815
MSR_UNC_CBO_1_PERFCTR1
Package
Uncore C-Box 1, performance counter 1
720H
1824
MSR_UNC_CBO_2_
PERFEVTSEL0
Package
Uncore C-Box 2, counter 0 event select MSR
721H
1825
MSR_UNC_CBO_2_
PERFEVTSEL1
Package
Uncore C-Box 2, counter 1 event select MSR
726H
1830
MSR_UNC_CBO_2_PERFCTR0
Package
Uncore C-Box 2, performance counter 0
727H
1831
MSR_UNC_CBO_2_PERFCTR1
Package
Uncore C-Box 2, performance counter 1
730H
1840
MSR_UNC_CBO_3_
PERFEVTSEL0
Package
Uncore C-Box 3, counter 0 event select MSR
731H
1841
MSR_UNC_CBO_3_
PERFEVTSEL1
Package
Uncore C-Box 3, counter 1 event select MSR.
736H
1846
MSR_UNC_CBO_3_PERFCTR0
Package
Uncore C-Box 3, performance counter 0.
737H
1847
MSR_UNC_CBO_3_PERFCTR1
Package
Uncore C-Box 3, performance counter 1.
E01H
3585
MSR_UNC_PERF_GLOBAL_
CTRL
Package
Uncore PMU global control
E02H
3586
35-260 Vol. 3C
0
Slice 0 select
1
Slice 1 select
2
Slice 2 select
3
Slice 3 select
4
Slice 4select
18:5
Reserved.
29
Enable all uncore counters
30
Enable wake on PMI
31
Enable Freezing counter when overflow
63:32
Reserved.
MSR_UNC_PERF_GLOBAL_
STATUS
Package
Uncore PMU main status
0
Fixed counter overflowed
1
An ARB counter overflowed
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-38. Uncore PMU MSRs Supported by 6th Generation Intel® Core™ Processors
Register
Address
Hex
35.16
Scope
Register Name
Bit Description
Dec
2
Reserved
3
A CBox counter overflowed (on any slice)
63:4
Reserved.
MSRS IN FUTURE INTEL® XEON® PROCESSORS
Future Intel® Xeon® Processors (CPUID DisplayFamily_DisplayModel = 06_55H) support the machine check bank
registers listed in Table 35-40.
Table 35-39. Machine Check MSRs Supported by Future Intel® Xeon® Processors with DisplayFamily_DisplayModel
06_55H
Register
Address
Register Name
Scope
Bit Description
Hex
Dec
280H
640
IA32_MC0_CTL2
Core
See Table 35-2.
281H
641
IA32_MC1_CTL2
Core
See Table 35-2.
282H
642
IA32_MC2_CTL2
Core
See Table 35-2.
283H
643
IA32_MC3_CTL2
Core
See Table 35-2.
284H
644
IA32_MC4_CTL2
Package
See Table 35-2.
285H
645
IA32_MC5_CTL2
Package
See Table 35-2.
286H
646
IA32_MC6_CTL2
Package
See Table 35-2.
287H
647
IA32_MC7_CTL2
Package
See Table 35-2.
288H
648
IA32_MC8_CTL2
Package
See Table 35-2.
289H
649
IA32_MC9_CTL2
Package
See Table 35-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 35-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 35-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 35-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 35-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 35-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 35-2.
290H
656
IA32_MC16_CTL2
Package
See Table 35-2.
291H
657
IA32_MC17_CTL2
Package
See Table 35-2.
292H
658
IA32_MC18_CTL2
Package
See Table 35-2.
293H
659
IA32_MC19_CTL2
Package
See Table 35-2.
400H
1024
IA32_MC0_CTL
Core
401H
1025
IA32_MC0_STATUS
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
402H
1026
IA32_MC0_ADDR
Core
403H
1027
IA32_MC0_MISC
Core
Bank MC0 reports MC error from the IFU module.
Vol. 3C 35-261
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-39. Machine Check MSRs Supported by Future Intel® Xeon® Processors with DisplayFamily_DisplayModel
06_55H
Register
Address
Register Name
Scope
Hex
Dec
404H
1028
IA32_MC1_CTL
Core
405H
1029
IA32_MC1_STATUS
Core
406H
1030
IA32_MC1_ADDR
Core
407H
1031
IA32_MC1_MISC
Core
408H
1032
IA32_MC2_CTL
Core
409H
1033
IA32_MC2_STATUS
Core
40AH
1034
IA32_MC2_ADDR
Core
40BH
1035
IA32_MC2_MISC
Core
40CH
1036
IA32_MC3_CTL
Core
40DH
1037
IA32_MC3_STATUS
Core
40EH
1038
IA32_MC3_ADDR
Core
40FH
1039
IA32_MC3_MISC
Core
410H
1040
IA32_MC4_CTL
Package
411H
1041
IA32_MC4_STATUS
Package
412H
1042
IA32_MC4_ADDR
Package
413H
1043
IA32_MC4_MISC
Package
414H
1044
IA32_MC5_CTL
Package
415H
1045
IA32_MC5_STATUS
Package
416H
1046
IA32_MC5_ADDR
Package
417H
1047
IA32_MC5_MISC
Package
418H
1048
IA32_MC6_CTL
Package
419H
1049
IA32_MC6_STATUS
Package
41AH
1050
IA32_MC6_ADDR
Package
41BH
1051
IA32_MC6_MISC
Package
41CH
1052
IA32_MC7_CTL
Package
41DH
1053
IA32_MC7_STATUS
Package
41EH
1054
IA32_MC7_ADDR
Package
41FH
1055
IA32_MC7_MISC
Package
420H
1056
IA32_MC8_CTL
Package
421H
1057
IA32_MC8_STATUS
Package
422H
1058
IA32_MC8_ADDR
Package
423H
1059
IA32_MC8_MISC
Package
424H
1060
IA32_MC9_CTL
Package
425H
1061
IA32_MC9_STATUS
Package
426H
1062
IA32_MC9_ADDR
Package
427H
1063
IA32_MC9_MISC
Package
35-262 Vol. 3C
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC1 reports MC error from the DCU module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC2 reports MC error from the DTLB module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC3 reports MC error from the MLC module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC4 reports MC error from the PCU module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC5 reports MC error from a link interconnect module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC6 reports MC error from the integrated I/O module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC7 reports MC error from the M2M 0.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC8 reports MC error from the M2M 1.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 - MC11 report MC error from the CHA
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-39. Machine Check MSRs Supported by Future Intel® Xeon® Processors with DisplayFamily_DisplayModel
06_55H
Register
Address
Register Name
Scope
Hex
Dec
428H
1064
IA32_MC10_CTL
Package
429H
1065
IA32_MC10_STATUS
Package
42AH
1066
IA32_MC10_ADDR
Package
42BH
1067
IA32_MC10_MISC
Package
42CH
1068
IA32_MC11_CTL
Package
42DH
1069
IA32_MC11_STATUS
Package
42EH
1070
IA32_MC11_ADDR
Package
42FH
1071
IA32_MC11_MISC
Package
430H
1072
IA32_MC12_CTL
Package
431H
1073
IA32_MC12_STATUS
Package
432H
1074
IA32_MC12_ADDR
Package
433H
1075
IA32_MC12_MISC
Package
434H
1076
IA32_MC13_CTL
Package
435H
1077
IA32_MC13_STATUS
Package
436H
1078
IA32_MC13_ADDR
Package
437H
1079
IA32_MC13_MISC
Package
438H
1080
IA32_MC14_CTL
Package
439H
1081
IA32_MC14_STATUS
Package
43AH
1082
IA32_MC14_ADDR
Package
43BH
1083
IA32_MC14_MISC
Package
43CH
1084
IA32_MC15_CTL
Package
43DH
1085
IA32_MC15_STATUS
Package
43EH
1086
IA32_MC15_ADDR
Package
43FH
1087
IA32_MC15_MISC
Package
440H
1088
IA32_MC16_CTL
Package
441H
1089
IA32_MC16_STATUS
Package
442H
1090
IA32_MC16_ADDR
Package
443H
1091
IA32_MC16_MISC
Package
444H
1092
IA32_MC17_CTL
Package
445H
1093
IA32_MC17_STATUS
Package
446H
1094
IA32_MC17_ADDR
Package
447H
1095
IA32_MC17_MISC
Package
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 - MC11 report MC error from the CHA.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC9 - MC11 report MC error from the CHA.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC12 report MC error from each channel of a link
interconnect module.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC13 through MC 18 report MC error from the integrated
memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC13 through MC 18 report MC error from the integrated
memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC13 through MC 18 report MC error from the integrated
memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC13 through MC 18 report MC error from the integrated
memory controllers
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC13 through MC 18 report MC error from the integrated
memory controllers.
Vol. 3C 35-263
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-39. Machine Check MSRs Supported by Future Intel® Xeon® Processors with DisplayFamily_DisplayModel
06_55H
Register
Address
Register Name
Scope
Hex
Dec
448H
1096
IA32_MC18_CTL
Package
449H
1097
IA32_MC18_STATUS
Package
44AH
1098
IA32_MC18_ADDR
Package
44BH
1099
IA32_MC18_MISC
Package
44CH
1100
IA32_MC19_CTL
Package
44DH
1101
IA32_MC19_STATUS
Package
44EH
1102
IA32_MC19_ADDR
Package
44FH
1103
IA32_MC19_MISC
Package
35.17
Bit Description
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Banks MC13 through MC 18 report MC error from the integrated
memory controllers.
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” through Section
15.3.2.4, “IA32_MCi_MISC MSRs.”.
Bank MC19 reports MC error from a link interconnect module.
MSRS IN INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES
Intel® Xeon Phi™ processor 3200, 5200, 7200 series, with CPUID DisplayFamily_DisplayModel signature 06_57H,
supports the MSR interfaces listed in Table 35-40. These processors are based on the Knights Landing microarchitecture. Some MSRs are shared between a pair of processor cores, the scope is marked as module.
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Register Name
Scope
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Module
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Module
See Section 35.22, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_
SIZE
Thread
See Section 8.10.5, “Monitor/Mwait Address Range Determination.”
andTable 35-2
10H
16
IA32_TIME_STAMP_
COUNTER
Thread
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
17H
23
IA32_PLATFORM_ID
Package
Platform ID (R)
See Table 35-2.
1BH
27
IA32_APIC_BASE
Thread
See Section 10.4.4, “Local APIC Status and Location,” and
Table 35-2.
34H
52
MSR_SMI_COUNT
Thread
SMI Counter (R/O)
3AH
58
31:0
SMI Count (R/O)
63:32
Reserved.
IA32_FEATURE_CONTROL
Thread
Control Features in Intel 64Processor (R/W)
See Table 35-2.
0
Lock (R/WL)
1
Reserved
2
3BH
59
IA32_TSC_ADJUST
Enable VMX outside SMX operation (R/WL)
THREAD
Per-Logical-Processor TSC ADJUST (R/W)
See Table 35-2.
35-264 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Dec
79H
121
Register Name
IA32_BIOS_UPDT_TRIG
Scope
Core
Bit Description
BIOS Update Trigger Register (W)
See Table 35-2.
8BH
139
IA32_BIOS_SIGN_ID
THREAD
BIOS Update Signature ID (RO)
See Table 35-2.
C1H
193
IA32_PMC0
THREAD
Performance counter register
See Table 35-2.
C2H
194
IA32_PMC1
THREAD
Performance Counter Register
See Table 35-2.
CEH
206
MSR_PLATFORM_INFO
Package
See http://biosbits.org.
Package
Maximum Non-Turbo Ratio (R/O)
7:0
15:8
Reserved.
The is the ratio of the frequency that invariant TSC runs at.
Frequency = ratio * 100 MHz.
27:16
28
Reserved.
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limits for Turbo
mode is enabled, and when set to 0, indicates Programmable Ratio
Limits for Turbo mode is disabled.
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limits for Turbo mode are
programmable, and when set to 0, indicates TDP Limit for Turbo
mode is not programmable.
39:30
47:40
Reserved.
Package
Maximum Efficiency Ratio (R/O)
The is the minimum ratio (maximum efficiency) that the processor
can operates, in units of 100MHz.
63:48
E2H
226
MSR_PKG_CST_CONFIG_
CONTROL
2:0
Reserved.
Module
C-State Configuration Control (R/W)
Package C-State Limit (R/W)
The following C-state code name encodings are supported:
000b: C0/C1
001b: C2
010b: C6 No Retention
011b: C6 Retention
111b: No limit
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved.
15
CFG Lock (R/WO)
63:16
Reserved.
Vol. 3C 35-265
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Dec
E4H
228
Register Name
MSR_PMG_IO_CAPTURE_
BASE
Scope
Module
Bit Description
Power Management IO Redirection in C-state (R/W)
15:0
LVL_2 Base Address (R/W)
18:16
C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name to
be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
100b - C4 is the max C-State to include
110b - C6 is the max C-State to include
63:19
E7H
231
IA32_MPERF
Reserved.
Thread
Maximum Performance Frequency Clock Count (RW)
See Table 35-2.
E8H
232
IA32_APERF
Thread
Actual Performance Frequency Clock Count (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Core
Memory Type Range Register (R)
See Table 35-2.
13CH
52
MSR_FEATURE_CONFIG
Core
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle
unsuccessful read of this MSR.
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instruction can be mis-configured
if a privileged agent unintentionally writes 11b.
63:2
Reserved.
174H
372
IA32_SYSENTER_CS
Thread
See Table 35-2.
175H
373
IA32_SYSENTER_ESP
Thread
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Thread
See Table 35-2.
179H
377
IA32_MCG_CAP
Thread
See Table 35-2.
17AH
378
IA32_MCG_STATUS
Thread
See Table 35-2.
17DH
390
MSR_SMM_MCA_CAP
THREAD
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in
SMM.
57:0
Reserved
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is
supported and a host-space interface available to SMM handler.
35-266 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Register Name
Dec
Scope
59
Bit Description
Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported
and a host-space interface available to SMM handler.
63:60
186H
390
IA32_PERFEVTSEL0
Reserved
Thread
Performance Monitoring Event Select Register (R/W)
See Table 35-2.
7:0
Event Select
15:8
UMask
16
USR
17
OS
18
Edge
19
PC
20
INT
21
AnyThread
22
EN
23
INV
31:24
CMASK
63:32
Reserved.
187H
391
IA32_PERFEVTSEL1
Thread
See Table 35-2.
198H
408
IA32_PERF_STATUS
Package
See Table 35-2.
199H
409
IA32_PERF_CTL
Thread
See Table 35-2.
19AH
410
IA32_CLOCK_MODULATION
Thread
Clock Modulation (R/W)
See Table 35-2.
19BH
411
IA32_THERM_INTERRUPT
Module
Thermal Interrupt Control (R/W)
See Table 35-2.
19CH
412
IA32_THERM_STATUS
Module
Thermal Monitor Status (R/W)
See Table 35-2.
0
Thermal status (RO)
1
Thermal status log (R/WC0)
2
PROTCHOT # or FORCEPR# status (RO)
3
PROTCHOT # or FORCEPR# log (R/WC0)
4
Critical Temperature status (RO)
5
Critical Temperature status log (R/WC0)
6
Thermal threshold #1 status (RO)
7
Thermal threshold #1 log (R/WC0)
8
Thermal threshold #2 status (RO)
9
Thermal threshold #2 log (R/WC0)
10
Power Limitation status (RO)
Vol. 3C 35-267
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Register Name
Dec
Scope
11
Power Limitation log (R/WC0)
15:12
Reserved.
22:16
Digital Readout (RO)
26:23
Reserved.
30:27
Resolution in degrees Celsius (RO)
31
Reading Valid (RO)
63:32
1A0H
416
Bit Description
IA32_MISC_ENABLE
Reserved.
Thread
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
1A2H
1A4H
418
420
35-268 Vol. 3C
0
Fast-Strings Enable
2:1
Reserved.
3
Automatic Thermal Control Circuit Enable (R/W) Default value is
1.
6:4
Reserved.
7
Performance Monitoring Available (R)
10:8
Reserved.
11
Branch Trace Storage Unavailable (RO)
12
Processor Event Based Sampling Unavailable (RO)
15:13
Reserved.
16
Enhanced Intel SpeedStep Technology Enable (R/W)
18
ENABLE MONITOR FSM (R/W)
21:19
Reserved.
22
Limit CPUID Maxval (R/W)
23
xTPR Message Disable (R/W)
33:24
Reserved.
34
XD Bit Disable (R/W)
37:35
Reserved.
38
Turbo Mode Disable (R/W)
63:39
Reserved.
MSR_
TEMPERATURE_TARGET
Package
15:0
Reserved.
23:16
Temperature Target (R)
29:24
Target Offset (R/W)
63:30
Reserved.
MSR_MISC_FEATURE_
CONTROL
Miscellaneous Feature Control (R/W)
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Register Name
Dec
0
Scope
Core
Bit Description
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher.
1
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher.
63:2
Reserved.
1A6H
422
MSR_OFFCORE_RSP_0
Shared
Offcore Response Event Select Register (R/W)
1A7H
423
MSR_OFFCORE_RSP_1
Shared
Offcore Response Event Select Register (R/W)
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW)
0
7:1
Reserved
Package
Maximum Number of Cores in Group 0
Number active processor cores which operates under the maximum
ratio limit for group 0.
15:8
Package
Maximum Ratio Limit for Group 0
Maximum turbo ratio limit when the number of active cores are not
more than the group 0 maximum core count.
20:16
Package
Number of Incremental Cores Added to Group 1
Group 1, which includes the specified number of additional cores
plus the cores in group 0, operates under the group 1 turbo max
ratio limit = “group 0 Max ratio limit” - “group ratio delta for group
1”.
23:21
Package
Group Ratio Delta for Group 1
An unsigned integer specifying the ratio decrement relative to the
Max ratio limit to Group 0.
28:24
Package
Number of Incremental Cores Added to Group 2
Group 2, which includes the specified number of additional cores
plus all the cores in group 1, operates under the group 2 turbo max
ratio limit = “group 1 Max ratio limit” - “group ratio delta for group
2”.
31:29
Package
Group Ratio Delta for Group 2
An unsigned integer specifying the ratio decrement relative to the
Max ratio limit for Group 1.
36:32
Package
Number of Incremental Cores Added to Group 3
Group 3, which includes the specified number of additional cores
plus all the cores in group 2, operates under the group 3 turbo max
ratio limit = “group 2 Max ratio limit” - “group ratio delta for group
3”.
39:37
Package
Group Ratio Delta for Group 3
An unsigned integer specifying the ratio decrement relative to the
Max ratio limit for Group 2.
Vol. 3C 35-269
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Register Name
Dec
44:40
Scope
Package
Bit Description
Number of Incremental Cores Added to Group 4
Group 4, which includes the specified number of additional cores
plus all the cores in group 3, operates under the group 4 turbo max
ratio limit = “group 3 Max ratio limit” - “group ratio delta for group
4”.
47:45
Package
Group Ratio Delta for Group 4
An unsigned integer specifying the ratio decrement relative to the
Max ratio limit for Group 3.
52:48
Package
Number of Incremental Cores Added to Group 5
Group 5, which includes the specified number of additional cores
plus all the cores in group 4, operates under the group 5 turbo max
ratio limit = “group 4 Max ratio limit” - “group ratio delta for group
5”.
55:53
Package
Group Ratio Delta for Group 5
An unsigned integer specifying the ratio decrement relative to the
Max ratio limit for Group 4.
60:56
Package
Number of Incremental Cores Added to Group 6
Group 6, which includes the specified number of additional cores
plus all the cores in group 5, operates under the group 6 turbo max
ratio limit = “group 5 Max ratio limit” - “group ratio delta for group
6”.
63:61
Package
Group Ratio Delta for Group 6
An unsigned integer specifying the ratio decrement relative to the
Max ratio limit for Group 5.
1B0H
432
IA32_ENERGY_PERF_BIAS
Thread
See Table 35-2.
1B1H
433
IA32_PACKAGE_THERM_
STATUS
Package
See Table 35-2.
1B2H
434
IA32_PACKAGE_THERM_
INTERRUPT
Package
See Table 35-2.
1C8H
456
MSR_LBR_SELECT
Thread
Last Branch Record Filtering Select Register (R/W)
1C9H
457
MSR_LASTBRANCH_TOS
Thread
Last Branch Record Stack TOS (R/W)
1D9H
473
IA32_DEBUGCTL
Thread
Debug Control (R/W)
See Table 35-2.
1DDH
477
MSR_LER_FROM_LIP
Thread
Last Exception Record From Linear IP (R)
1DEH
478
1F2H
498
MSR_LER_TO_LIP
Thread
Last Exception Record To Linear IP (R)
IA32_SMRR_PHYSBASE
Core
See Table 35-2.
1F3H
499
IA32_SMRR_PHYSMASK
Core
See Table 35-2.
200H
512
IA32_MTRR_PHYSBASE0
Core
See Table 35-2.
201H
513
IA32_MTRR_PHYSMASK0
Core
See Table 35-2.
202H
514
IA32_MTRR_PHYSBASE1
Core
See Table 35-2.
203H
515
IA32_MTRR_PHYSMASK1
Core
See Table 35-2.
204H
516
IA32_MTRR_PHYSBASE2
Core
See Table 35-2.
35-270 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Dec
Register Name
Scope
Bit Description
205H
517
IA32_MTRR_PHYSMASK2
Core
See Table 35-2.
206H
518
IA32_MTRR_PHYSBASE3
Core
See Table 35-2.
207H
519
IA32_MTRR_PHYSMASK3
Core
See Table 35-2.
208H
520
IA32_MTRR_PHYSBASE4
Core
See Table 35-2.
209H
521
IA32_MTRR_PHYSMASK4
Core
See Table 35-2.
20AH
522
IA32_MTRR_PHYSBASE5
Core
See Table 35-2.
20BH
523
IA32_MTRR_PHYSMASK5
Core
See Table 35-2.
20CH
524
IA32_MTRR_PHYSBASE6
Core
See Table 35-2.
20DH
525
IA32_MTRR_PHYSMASK6
Core
See Table 35-2.
20EH
526
IA32_MTRR_PHYSBASE7
Core
See Table 35-2.
20FH
527
IA32_MTRR_PHYSMASK7
Core
See Table 35-2.
250H
592
IA32_MTRR_FIX64K_00000 Core
See Table 35-2.
258H
600
IA32_MTRR_FIX16K_80000 Core
See Table 35-2.
259H
601
IA32_MTRR_FIX16K_A000
0
Core
See Table 35-2.
268H
616
IA32_MTRR_FIX4K_C0000
Core
See Table 35-2.
269H
617
IA32_MTRR_FIX4K_C8000
Core
See Table 35-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Core
See Table 35-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Core
See Table 35-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Core
See Table 35-2.
26DH
621
IA32_MTRR_FIX4K_E8000
Core
See Table 35-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Core
See Table 35-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Core
See Table 35-2.
277H
631
IA32_PAT
Core
See Table 35-2.
2FFH
767
IA32_MTRR_DEF_TYPE
Core
Default Memory Types (R/W)
See Table 35-2.
309H
777
IA32_FIXED_CTR0
Thread
Fixed-Function Performance Counter Register 0 (R/W)
See Table 35-2.
30AH
778
IA32_FIXED_CTR1
Thread
Fixed-Function Performance Counter Register 1 (R/W)
See Table 35-2.
30BH
779
IA32_FIXED_CTR2
Thread
Fixed-Function Performance Counter Register 2 (R/W)
See Table 35-2.
345H
837
IA32_PERF_CAPABILITIES
Package
See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”
38DH
909
IA32_FIXED_CTR_CTRL
Thread
Fixed-Function-Counter Control Register (R/W)
See Table 35-2.
38EH
910
IA32_PERF_GLOBAL_STATU
S
Thread
See Table 35-2.
38FH
911
IA32_PERF_GLOBAL_CTRL
Thread
See Table 35-2.
Vol. 3C 35-271
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Register Name
Scope
Bit Description
Hex
Dec
390H
912
IA32_PERF_GLOBAL_OVF_
CTRL
Thread
See Table 35-2.
3F1H
1009
MSR_PEBS_ENABLE
Thread
See Table 35-2.
3F8H
1016
MSR_PKG_C3_RESIDENCY
Package
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
63:0
3F9H
1017
MSR_PKG_C6_RESIDENCY
Package C3 Residency Counter. (R/O)
Package
63:0
3FAH
1018
MSR_PKG_C7_RESIDENCY
Package C6 Residency Counter. (R/O)
Package
63:0
3FCH
1020
MSR_MC0_RESIDENCY
Package C7 Residency Counter. (R/O)
Module
63:0
3FDH
1021
MSR_MC6_RESIDENCY
Module C0 Residency Counter. (R/O)
Module
63:0
3FFH
1023
MSR_CORE_C6_RESIDENCY
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
Module C6 Residency Counter. (R/O)
Core
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
CORE C6 Residency Counter. (R/O)
400H
1024
IA32_MC0_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
404H
1028
IA32_MC1_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
408H
1032
IA32_MC2_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
40CH
1036
IA32_MC3_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC3_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
410H
1040
IA32_MC4_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC4_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
IA32_MC4_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
414H
1044
IA32_MC5_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
415H
1045
IA32_MC5_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
35-272 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Register Name
Scope
Bit Description
Hex
Dec
416H
1046
IA32_MC5_ADDR
Package
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
480H
1152
IA32_VMX_BASIC
Core
Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
481H
1153
IA32_VMX_PINBASED_
CTLS
Core
Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Table 35-2.
482H
1154
IA32_VMX_PROCBASED_
CTLS
Core
Capability Reporting Register of Primary Processor-based
VM-execution Controls (R/O)
483H
1155
IA32_VMX_EXIT_CTLS
Core
Capability Reporting Register of VM-exit Controls (R/O)
See Table 35-2.
484H
1156
IA32_VMX_ENTRY_CTLS
Core
Capability Reporting Register of VM-entry Controls (R/O)
See Table 35-2.
485H
1157
IA32_VMX_MISC
Core
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 35-2.
486H
1158
IA32_VMX_CR0_FIXED0
Core
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 35-2.
487H
1159
IA32_VMX_CR0_FIXED1
Core
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 35-2.
488H
1160
IA32_VMX_CR4_FIXED0
Core
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 35-2.
489H
1161
IA32_VMX_CR4_FIXED1
Core
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 35-2.
48AH
1162
IA32_VMX_VMCS_ENUM
Core
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 35-2.
48BH
1163
IA32_VMX_PROCBASED_
CTLS2
Core
Capability Reporting Register of Secondary Processor-based
VM-execution Controls (R/O)
See Table 35-2
48CH
48DH
1164
1165
IA32_VMX_EPT_VPID_ENU
M
Core
IA32_VMX_TRUE_PINBASE
D_CTLS
Core
Capability Reporting Register of EPT and VPID (R/O)
See Table 35-2
Capability Reporting Register of Pin-based VM-execution Flex
Controls (R/O)
See Table 35-2
48EH
1166
IA32_VMX_TRUE_PROCBAS
ED_CTLS
Core
Capability Reporting Register of Primary Processor-based
VM-execution Flex Controls (R/O)
See Table 35-2
48FH
490H
1167
1168
IA32_VMX_TRUE_EXIT_CTL
S
Core
IA32_VMX_TRUE_ENTRY_C
TLS
Core
Capability Reporting Register of VM-exit Flex Controls (R/O)
See Table 35-2
Capability Reporting Register of VM-entry Flex Controls (R/O)
See Table 35-2
Vol. 3C 35-273
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Dec
491H
1169
Register Name
IA32_VMX_FMFUNC
Scope
Core
Bit Description
Capability Reporting Register of VM-function Controls (R/O)
See Table 35-2
4C1H
1217
IA32_A_PMC0
Thread
See Table 35-2.
4C2H
1218
IA32_A_PMC1
Thread
See Table 35-2.
600H
1536
IA32_DS_AREA
Thread
DS Save Area (R/W)
See Table 35-2.
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
3:0
Package
Power Units
See Section 14.9.1, “RAPL Interfaces.”
7:4
Package
Reserved
12:8
Package
Energy Status Units
Energy related information (in Joules) is based on the multiplier,
1/2^ESU; where ESU is an unsigned integer represented by bits
12:8. Default value is 0EH (or 61 micro-joules)
15:13
Package
Reserved
19:16
Package
Time Units
See Section 14.9.1, “RAPL Interfaces.”
63:20
60DH
1549
MSR_PKG_C2_RESIDENCY
Reserved
Package
63:0
610H
1552
MSR_PKG_POWER_LIMIT
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States.
Package C2 Residency Counter. (R/O)
Package
PKG RAPL Power Limit Control (R/W)
See Section 14.9.3, “Package RAPL Domain.”
611H
1553
MSR_PKG_ENERGY_STATUS
Package
PKG Energy Status (R/O)
See Section 14.9.3, “Package RAPL Domain.”
613H
1555
MSR_PKG_PERF_STATUS
Package
PKG Perf Status (R/O)
See Section 14.9.3, “Package RAPL Domain.”
614H
1556
MSR_PKG_POWER_INFO
Package
PKG RAPL Parameters (R/W) See Section 14.9.3, “Package RAPL
Domain.”
618H
1560
MSR_DRAM_POWER_LIMIT
Package
DRAM RAPL Power Limit Control (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_
STATUS
Package
DRAM Energy Status (R/O)
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O) See Section 14.9.5,
“DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 14.9.5, “DRAM RAPL Domain.”
See Section 14.9.5, “DRAM RAPL Domain.”
638H
1592
MSR_PP0_POWER_LIMIT
Package
PP0 RAPL Power Limit Control (R/W)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
35-274 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Dec
639H
1593
Register Name
MSR_PP0_ENERGY_STATUS
Scope
Package
Bit Description
PP0 Energy Status (R/O)
See Section 14.9.4, “PP0/PP1 RAPL Domains.”
648H
1608
MSR_CONFIG_TDP_
NOMINAL
Package
Base TDP Ratio (R/O)
See Table 35-23
649H
1609
MSR_CONFIG_TDP_LEVEL1
Package
ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23
64AH
1610
MSR_CONFIG_TDP_LEVEL2
Package
ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23
64BH
1611
MSR_CONFIG_TDP_
CONTROL
Package
ConfigTDP Control (R/W)
See Table 35-23
64CH
1612
MSR_TURBO_ACTIVATION_
RATIO
Package
690H
1680
MSR_CORE_PERF_LIMIT_RE
ASONS
Package
6E0H
1760
ConfigTDP Control (R/W)
See Table 35-23
Indicator of Frequency Clipping in Processor Cores (R/W)
(frequency refers to processor core frequency)
0
PROCHOT Status (R0)
1
Thermal Status (R0)
5:2
Reserved.
6
VR Therm Alert Status (R0)
7
Reserved.
8
Electrical Design Point Status (R0)
63:9
Reserved.
IA32_TSC_DEADLINE
Core
TSC Target of Local APIC’s TSC Deadline Mode (R/W)
See Table 35-2
802H
2050
IA32_X2APIC_APICID
Thread
x2APIC ID register (R/O) See x2APIC Specification.
803H
2051
IA32_X2APIC_VERSION
Thread
x2APIC Version register (R/O)
808H
2056
IA32_X2APIC_TPR
Thread
x2APIC Task Priority register (R/W)
80AH
2058
IA32_X2APIC_PPR
Thread
x2APIC Processor Priority register (R/O)
80BH
2059
IA32_X2APIC_EOI
Thread
x2APIC EOI register (W/O)
80DH
2061
IA32_X2APIC_LDR
Thread
x2APIC Logical Destination register (R/O)
80FH
2063
IA32_X2APIC_SIVR
Thread
x2APIC Spurious Interrupt Vector register (R/W)
810H
2064
IA32_X2APIC_ISR0
Thread
x2APIC In-Service register bits [31:0] (R/O)
811H
2065
IA32_X2APIC_ISR1
Thread
x2APIC In-Service register bits [63:32] (R/O)
812H
2066
IA32_X2APIC_ISR2
Thread
x2APIC In-Service register bits [95:64] (R/O)
813H
2067
IA32_X2APIC_ISR3
Thread
x2APIC In-Service register bits [127:96] (R/O)
814H
2068
IA32_X2APIC_ISR4
Thread
x2APIC In-Service register bits [159:128] (R/O)
815H
2069
IA32_X2APIC_ISR5
Thread
x2APIC In-Service register bits [191:160] (R/O)
816H
2070
IA32_X2APIC_ISR6
Thread
x2APIC In-Service register bits [223:192] (R/O)
817H
2071
IA32_X2APIC_ISR7
Thread
x2APIC In-Service register bits [255:224] (R/O)
818H
2072
IA32_X2APIC_TMR0
Thread
x2APIC Trigger Mode register bits [31:0] (R/O)
Vol. 3C 35-275
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Dec
Register Name
Scope
Bit Description
819H
2073
IA32_X2APIC_TMR1
Thread
x2APIC Trigger Mode register bits [63:32] (R/O)
81AH
2074
IA32_X2APIC_TMR2
Thread
x2APIC Trigger Mode register bits [95:64] (R/O)
81BH
2075
IA32_X2APIC_TMR3
Thread
x2APIC Trigger Mode register bits [127:96] (R/O)
81CH
2076
IA32_X2APIC_TMR4
Thread
x2APIC Trigger Mode register bits [159:128] (R/O)
81DH
2077
IA32_X2APIC_TMR5
Thread
x2APIC Trigger Mode register bits [191:160] (R/O)
81EH
2078
IA32_X2APIC_TMR6
Thread
x2APIC Trigger Mode register bits [223:192] (R/O)
81FH
2079
IA32_X2APIC_TMR7
Thread
x2APIC Trigger Mode register bits [255:224] (R/O)
820H
2080
IA32_X2APIC_IRR0
Thread
x2APIC Interrupt Request register bits [31:0] (R/O)
821H
2081
IA32_X2APIC_IRR1
Thread
x2APIC Interrupt Request register bits [63:32] (R/O)
822H
2082
IA32_X2APIC_IRR2
Thread
x2APIC Interrupt Request register bits [95:64] (R/O)
823H
2083
IA32_X2APIC_IRR3
Thread
x2APIC Interrupt Request register bits [127:96] (R/O)
824H
2084
IA32_X2APIC_IRR4
Thread
x2APIC Interrupt Request register bits [159:128] (R/O)
825H
2085
IA32_X2APIC_IRR5
Thread
x2APIC Interrupt Request register bits [191:160] (R/O)
826H
2086
IA32_X2APIC_IRR6
Thread
x2APIC Interrupt Request register bits [223:192] (R/O)
827H
2087
IA32_X2APIC_IRR7
Thread
x2APIC Interrupt Request register bits [255:224] (R/O)
828H
2088
IA32_X2APIC_ESR
Thread
x2APIC Error Status register (R/W)
82FH
2095
IA32_X2APIC_LVT_CMCI
Thread
x2APIC LVT Corrected Machine Check Interrupt register (R/W)
830H
2096
IA32_X2APIC_ICR
Thread
x2APIC Interrupt Command register (R/W)
832H
2098
IA32_X2APIC_LVT_TIMER
Thread
x2APIC LVT Timer Interrupt register (R/W)
833H
2099
IA32_X2APIC_LVT_THERMA Thread
L
x2APIC LVT Thermal Sensor Interrupt register (R/W)
834H
2100
IA32_X2APIC_LVT_PMI
Thread
x2APIC LVT Performance Monitor register (R/W)
835H
2101
IA32_X2APIC_LVT_LINT0
Thread
x2APIC LVT LINT0 register (R/W)
836H
2102
IA32_X2APIC_LVT_LINT1
Thread
x2APIC LVT LINT1 register (R/W)
837H
2103
IA32_X2APIC_LVT_ERROR
Thread
x2APIC LVT Error register (R/W)
838H
2104
IA32_X2APIC_INIT_COUNT
Thread
x2APIC Initial Count register (R/W)
839H
2105
IA32_X2APIC_CUR_COUNT
Thread
x2APIC Current Count register (R/O)
83EH
2110
IA32_X2APIC_DIV_CONF
Thread
x2APIC Divide Configuration register (R/W)
83FH
2111
IA32_X2APIC_SELF_IPI
Thread
x2APIC Self IPI register (W/O)
C000_
0080H
IA32_EFER
Thread
Extended Feature Enables
C000_
0081H
IA32_STAR
C000_
0082H
IA32_LSTAR
C000_
0084H
IA32_FMASK
35-276 Vol. 3C
See Table 35-2.
Thread
System Call Target Address (R/W)
See Table 35-2.
Thread
IA-32e Mode System Call Target Address (R/W)
See Table 35-2.
Thread
System Call Flag Mask (R/W)
See Table 35-2.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-40. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H
Address
Hex
Dec
Register Name
Scope
Thread
Bit Description
C000_
0100H
IA32_FS_BASE
Map of BASE Address of FS (R/W)
C000_
0101H
IA32_GS_BASE
C000_
0102H
IA32_KERNEL_GS_BASE
Thread
Swap Target of BASE Address of GS (R/W) See Table 35-2.
C000_
0103H
IA32_TSC_AUX
Thread
AUXILIARY TSC Signature. (R/W) See Table 35-2
See Table 35-2.
Thread
Map of BASE Address of GS (R/W)
See Table 35-2.
35.18
MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS
Table 35-41 lists MSRs (architectural and model-specific) that are defined across processor generations based on
Intel NetBurst microarchitecture. The processor can be identified by its CPUID signatures of DisplayFamily
encoding of 0FH, see Table 35-1.
•
MSRs with an “IA32_” prefix are designated as “architectural.” This means that the functions of these MSRs and
their addresses remain the same for succeeding families of IA-32 processors.
•
MSRs with an “MSR_” prefix are model specific with respect to address functionalities. The column “Model
Availability” lists the model encoding value(s) within the Pentium 4 and Intel Xeon processor family at the
specified register address. The model encoding value of a processor can be queried using CPUID. See
“CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A.
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors
Register
Address
Register Name
Fields and Flags
Model
Availability
Shared/
Unique1
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
0, 1, 2, 3,
4, 6
Shared
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
0, 1, 2, 3,
4, 6
Shared
See Section 35.22, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_LINE_
SIZE
3, 4, 6
Shared
See Section 8.10.5, “Monitor/Mwait Address
Range Determination.”
10H
16
IA32_TIME_STAMP_COUNTER
0, 1, 2, 3,
4, 6
Unique
Time Stamp Counter
See Table 35-2.
On earlier processors, only the lower 32 bits are
writable. On any write to the lower 32 bits, the
upper 32 bits are cleared. For processor family
0FH, models 3 and 4: all 64 bits are writable.
17H
23
IA32_PLATFORM_ID
0, 1, 2, 3,
4, 6
Shared
Platform ID (R)
See Table 35-2.
The operating system can use this MSR to
determine “slot” information for the processor and
the proper microcode update to load.
Vol. 3C 35-277
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
1BH
27
2AH
42
Register Name
Fields and Flags
IA32_APIC_BASE
MSR_EBC_HARD_POWERON
Model
Availability
Shared/
Unique1
0, 1, 2, 3,
4, 6
Unique
0, 1, 2, 3,
4, 6
Shared
Bit Description
APIC Location and Status (R/W)
See Table 35-2. See Section 10.4.4, “Local APIC
Status and Location.”
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features;
(R) indicates current processor configuration.
0
Output Tri-state Enabled (R)
Indicates whether tri-state output is enabled (1)
or disabled (0) as set by the strapping of SMI#.
The value in this bit is written on the deassertion
of RESET#; the bit is set to 1 when the address
bus signal is asserted.
1
Execute BIST (R)
Indicates whether the execution of the BIST is
enabled (1) or disabled (0) as set by the strapping
of INIT#. The value in this bit is written on the
deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
2
In Order Queue Depth (R)
Indicates whether the in order queue depth for
the system bus is 1 (1) or up to 12 (0) as set by
the strapping of A7#. The value in this bit is
written on the deassertion of RESET#; the bit is
set to 1 when the address bus signal is asserted.
3
MCERR# Observation Disabled (R)
Indicates whether MCERR# observation is enabled
(0) or disabled (1) as determined by the strapping
of A9#. The value in this bit is written on the
deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
4
BINIT# Observation Enabled (R)
Indicates whether BINIT# observation is enabled
(0) or disabled (1) as determined by the strapping
of A10#. The value in this bit is written on the
deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
6:5
APIC Cluster ID (R)
Contains the logical APIC cluster ID value as set by
the strapping of A12# and A11#. The logical
cluster ID value is written into the field on the
deassertion of RESET#; the field is set to 1 when
the address bus signal is asserted.
35-278 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Dec
Model
Availability
Shared/
Unique1
7
Bit Description
Bus Park Disable (R)
Indicates whether bus park is enabled (0) or
disabled (1) as set by the strapping of A15#. The
value in this bit is written on the deassertion of
RESET#; the bit is set to 1 when the address bus
signal is asserted.
11:8
Reserved.
13:12
Agent ID (R)
Contains the logical agent ID value as set by the
strapping of BR[3:0]. The logical ID value is
written into the field on the deassertion of
RESET#; the field is set to 1 when the address bus
signal is asserted.
63:14
2BH
43
MSR_EBC_SOFT_POWERON
0
Reserved.
0, 1, 2, 3,
4, 6
Shared
Processor Soft Power-On Configuration (R/W)
Enables and disables processor features.
RCNT/SCNT On Request Encoding Enable (R/W)
Controls the driving of RCNT/SCNT on the request
encoding. Set to enable (1); clear to disabled (0,
default).
1
Data Error Checking Disable (R/W)
Set to disable system data bus parity checking;
clear to enable parity checking.
2
Response Error Checking Disable (R/W)
Set to disable (default); clear to enable.
3
Address/Request Error Checking Disable (R/W)
Set to disable (default); clear to enable.
4
Initiator MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator bus
requests (default); clear to enable.
5
Internal MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator internal
errors (default); clear to enable.
6
BINIT# Driver Disable (R/W)
Set to disable BINIT# driver (default); clear to
enable driver.
63:7
Reserved.
Vol. 3C 35-279
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
2CH
44
Register Name
Fields and Flags
MSR_EBC_FREQUENCY_ID
Model
Availability
2,3, 4, 6
Shared/
Unique1
Shared
Bit Description
Processor Frequency Configuration
The bit field layout of this MSR varies according to
the MODEL value in the CPUID version
information. The following bit field layout applies
to Pentium 4 and Xeon Processors with MODEL
encoding equal or greater than 2.
(R) The field Indicates the current processor
frequency configuration.
15:0
Reserved.
18:16
Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
Encoding Scalable Bus Speed
000B
100 MHz (Model 2)
000B
266 MHz (Model 3 or 4)
001B
133 MHz
010B
200 MHz
011B
166 MHz
100B
333 MHz (Model 6)
133.33 MHz should be utilized if performing
calculation with System Bus Speed when encoding
is 001B.
166.67 MHz should be utilized if performing
calculation with System Bus Speed when encoding
is 011B.
266.67 MHz should be utilized if performing
calculation with System Bus Speed when encoding
is 000B and model encoding = 3 or 4.
333.33 MHz should be utilized if performing
calculation with System Bus Speed when encoding
is 100B and model encoding = 6.
All other values are reserved.
23:19
Reserved.
31:24
Core Clock Frequency to System Bus
Frequency Ratio (R)
The processor core clock frequency to system bus
frequency ratio observed at the de-assertion of
the reset pin.
63:25
2CH
44
MSR_EBC_FREQUENCY_ID
Reserved.
0, 1
Shared
Processor Frequency Configuration (R)
The bit field layout of this MSR varies according to
the MODEL value of the CPUID version
information. This bit field layout applies to
Pentium 4 and Xeon Processors with MODEL
encoding less than 2.
Indicates current processor frequency
configuration.
35-280 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Dec
Model
Availability
Shared/
Unique1
Bit Description
20:0
Reserved.
23:21
Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
Encoding Scalable Bus Speed
000B
100 MHz
All others values reserved.
63:24
3AH
58
IA32_FEATURE_CONTROL
Reserved.
3, 4, 6
Unique
Control Features in IA-32 Processor (R/W)
See Table 35-2
(If CPUID.01H:ECX.[bit 5])
79H
8BH
9BH
121
139
155
IA32_BIOS_UPDT_TRIG
0, 1, 2, 3,
4, 6
Shared
IA32_BIOS_SIGN_ID
0, 1, 2, 3,
4, 6
Unique
IA32_SMM_MONITOR_CTL
3, 4, 6
Unique
BIOS Update Trigger Register (W)
See Table 35-2.
BIOS Update Signature ID (R/W)
See Table 35-2.
SMM Monitor Configuration (R/W)
See Table 35-2.
FEH
174H
254
372
IA32_MTRRCAP
IA32_SYSENTER_CS
0, 1, 2, 3,
4, 6
Unique
0, 1, 2, 3,
4, 6
Unique
MTRR Information
See Section 11.11.1, “MTRR Feature
Identification.”.
CS register target for CPL 0 code (R/W)
See Table 35-2.
See Section 5.8.7, “Performing Fast Calls to
System Procedures with the SYSENTER and
SYSEXIT Instructions.”
175H
373
IA32_SYSENTER_ESP
0, 1, 2, 3,
4, 6
Unique
Stack pointer for CPL 0 stack (R/W)
See Table 35-2.
See Section 5.8.7, “Performing Fast Calls to
System Procedures with the SYSENTER and
SYSEXIT Instructions.”
176H
179H
17AH
17BH
374
377
378
379
IA32_SYSENTER_EIP
IA32_MCG_CAP
IA32_MCG_STATUS
IA32_MCG_CTL
0, 1, 2, 3,
4, 6
Unique
0, 1, 2, 3,
4, 6
Unique
0, 1, 2, 3,
4, 6
Unique
CPL 0 code entry point (R/W)
See Table 35-2. See Section 5.8.7, “Performing
Fast Calls to System Procedures with the
SYSENTER and SYSEXIT Instructions.”
Machine Check Capabilities (R)
See Table 35-2. See Section 15.3.1.1,
“IA32_MCG_CAP MSR.”
Machine Check Status. (R)
See Table 35-2. See Section 15.3.1.2,
“IA32_MCG_STATUS MSR.”
Machine Check Feature Enable (R/W)
See Table 35-2.
See Section 15.3.1.3, “IA32_MCG_CTL MSR.”
Vol. 3C 35-281
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
180H
384
Register Name
Fields and Flags
MSR_MCG_RAX
Model
Availability
0, 1, 2, 3,
4, 6
Shared/
Unique1
Unique
385
MSR_MCG_RBX
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
386
MSR_MCG_RCX
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
387
MSR_MCG_RDX
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
388
MSR_MCG_RSI
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
389
MSR_MCG_RDI
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
390
MSR_MCG_RBP
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
391
35-282 Vol. 3C
MSR_MCG_RSP
Machine Check EBP/RBP Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
187H
Machine Check EDI/RDI Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
186H
Machine Check ESI/RSI Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
185H
Machine Check EDX/RDX Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
184H
Machine Check ECX/RCX Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
183H
Machine Check EBX/RBX Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
182H
Machine Check EAX/RAX Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
181H
Bit Description
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
Machine Check ESP/RSP Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Dec
Model
Availability
Shared/
Unique1
63:0
188H
392
MSR_MCG_RFLAGS
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
393
MSR_MCG_RIP
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
394
MSR_MCG_MISC
Machine Check EIP/RIP Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
18AH
Machine Check EFLAGS/RFLAG Save State
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
189H
Bit Description
Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
0, 1, 2, 3,
4, 6
Unique
Machine Check Miscellaneous
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
0
DS
When set, the bit indicates that a page assist or
page fault occurred during DS normal operation.
The processors response is to shut down.
The bit is used as an aid for debugging DS
handling code. It is the responsibility of the user
(BIOS or operating system) to clear this bit for
normal operation.
63:1
18BH 18FH
395
MSR_MCG_RESERVED1 MSR_MCG_RESERVED5
190H
400
MSR_MCG_R8
Reserved.
Reserved.
0, 1, 2, 3,
4, 6
Unique
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
191H
401
MSR_MCG_R9
63:0
Machine Check R8
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
0, 1, 2, 3,
4, 6
Unique
Machine Check R9D/R9
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
Vol. 3C 35-283
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
192H
402
Register Name
Fields and Flags
MSR_MCG_R10
Model
Availability
0, 1, 2, 3,
4, 6
Shared/
Unique1
Unique
403
MSR_MCG_R11
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
0, 1, 2, 3,
4, 6
Unique
404
MSR_MCG_R12
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
0, 1, 2, 3,
4, 6
Unique
405
MSR_MCG_R13
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
0, 1, 2, 3,
4, 6
Unique
406
MSR_MCG_R14
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
0, 1, 2, 3,
4, 6
Unique
407
35-284 Vol. 3C
MSR_MCG_R15
Machine Check R14
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
197H
Machine Check R13
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
196H
Machine Check R12
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
195H
Machine Check R11
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
194H
Machine Check R10
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0
193H
Bit Description
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
0, 1, 2, 3,
4, 6
Unique
Machine Check R15
See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Model
Availability
Dec
Shared/
Unique1
63:0
Bit Description
Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when the
processor is operating in 64-bit mode at the time
of the error.
198H
408
IA32_PERF_STATUS
3, 4, 6
Unique
See Table 35-2. See Section 14.1, “Enhanced Intel
Speedstep® Technology.”
199H
409
IA32_PERF_CTL
3, 4, 6
Unique
See Table 35-2. See Section 14.1, “Enhanced Intel
Speedstep® Technology.”
19AH
410
IA32_CLOCK_MODULATION
0, 1, 2, 3,
4, 6
Unique
Thermal Monitor Control (R/W)
See Table 35-2.
See Section 14.7.3, “Software Controlled Clock
Modulation.”
19BH
19CH
19DH
1A0H
411
412
413
416
IA32_THERM_INTERRUPT
IA32_THERM_STATUS
0, 1, 2, 3,
4, 6
Unique
0, 1, 2, 3,
4, 6
Shared
See Section 14.7.2, “Thermal Monitor,” and see
Table 35-2.
Thermal Monitor Status (R/W)
See Section 14.7.2, “Thermal Monitor,” and see
Table 35-2.
MSR_THERM2_CTL
IA32_MISC_ENABLE
Thermal Interrupt Control (R/W)
Thermal Monitor 2 Control.
3,
Shared
For Family F, Model 3 processors: When read,
specifies the value of the target TM2 transition
last written. When set, it sets the next target
value for TM2 transition.
4, 6
Shared
For Family F, Model 4 and Model 6 processors:
When read, specifies the value of the target TM2
transition last written. Writes may cause #GP
exceptions.
0, 1, 2, 3,
4, 6
Shared
Enable Miscellaneous Processor Features (R/W)
0
Fast-Strings Enable. See Table 35-2.
1
Reserved.
2
x87 FPU Fopcode Compatibility Mode Enable
3
Thermal Monitor 1 Enable
See Section 14.7.2, “Thermal Monitor,” and see
Table 35-2.
4
Split-Lock Disable
When set, the bit causes an #AC exception to be
issued instead of a split-lock cycle. Operating
systems that set this bit must align system
structures to avoid split-lock scenarios.
When the bit is clear (default), normal split-locks
are issued to the bus.
Vol. 3C 35-285
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Dec
Model
Availability
Shared/
Unique1
Bit Description
This debug feature is specific to the Pentium 4
processor.
5
Reserved.
6
Third-Level Cache Disable (R/W)
When set, the third-level cache is disabled; when
clear (default) the third-level cache is enabled.
This flag is reserved for processors that do not
have a third-level cache.
Note that the bit controls only the third-level
cache; and only if overall caching is enabled
through the CD flag of control register CR0, the
page-level cache controls, and/or the MTRRs.
See Section 11.5.4, “Disabling and Enabling the L3
Cache.”
7
Performance Monitoring Available (R)
See Table 35-2.
8
Suppress Lock Enable
When set, assertion of LOCK on the bus is
suppressed during a Split Lock access. When clear
(default), LOCK is not suppressed.
9
Prefetch Queue Disable
When set, disables the prefetch queue. When clear
(default), enables the prefetch queue.
10
FERR# Interrupt Reporting Enable (R/W)
When set, interrupt reporting through the FERR#
pin is enabled; when clear, this interrupt reporting
function is disabled.
When this flag is set and the processor is in the
stop-clock state (STPCLK# is asserted), asserting
the FERR# pin signals to the processor that an
interrupt (such as, INIT#, BINIT#, INTR, NMI, SMI#,
or RESET#) is pending and that the processor
should return to normal operation to handle the
interrupt.
This flag does not affect the normal operation of
the FERR# pin (to indicate an unmasked floatingpoint error) when the STPCLK# pin is not
asserted.
11
Branch Trace Storage Unavailable
(BTS_UNAVILABLE) (R)
See Table 35-2.
When set, the processor does not support branch
trace storage (BTS); when clear, BTS is supported.
35-286 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Model
Availability
Dec
Shared/
Unique1
12
Bit Description
PEBS_UNAVILABLE: Processor Event Based
Sampling Unavailable (R)
See Table 35-2.
When set, the processor does not support
processor event-based sampling (PEBS); when
clear, PEBS is supported.
13
3
TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor
indicates that the die temperature is at the predetermined threshold, the Thermal Monitor 2
mechanism is engaged. TM2 will reduce the bus to
core ratio and voltage according to the value last
written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor
does not change the VID signals or the bus to core
ratio when the processor enters a thermal
managed state.
If the TM2 feature flag (ECX[8]) is not set to 1
after executing CPUID with EAX = 1, then this
feature is not supported and BIOS must not alter
the contents of this bit location. The processor is
operating out of spec if both this bit and the TM1
bit are set to disabled states.
17:14
18
Reserved.
3, 4, 6
ENABLE MONITOR FSM (R/W)
See Table 35-2.
19
Adjacent Cache Line Prefetch Disable (R/W)
When set to 1, the processor fetches the cache
line of the 128-byte sector containing currently
required data. When set to 0, the processor
fetches both cache lines in the sector.
Single processor platforms should not set this bit.
Server platforms should set or clear this bit based
on platform performance observed in validation
and testing.
BIOS may contain a setup option that controls the
setting of this bit.
21:20
22
Reserved.
3, 4, 6
Limit CPUID MAXVAL (R/W)
See Table 35-2.
Setting this can cause unexpected behavior to
software that depends on the availability of CPUID
leaves greater than 3.
23
Shared
xTPR Message Disable (R/W)
See Table 35-2.
Vol. 3C 35-287
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Dec
Model
Availability
Shared/
Unique1
24
Bit Description
L1 Data Cache Context Mode (R/W)
When set, the L1 data cache is placed in shared
mode; when clear (default), the cache is placed in
adaptive mode. This bit is only enabled for IA-32
processors that support Intel Hyper-Threading
Technology. See Section 11.5.6, “L1 Data Cache
Context Mode.”
When L1 is running in adaptive mode and CR3s
are identical, data in L1 is shared across logical
processors. Otherwise, L1 is not shared and cache
use is competitive.
If the Context ID feature flag (ECX[10]) is set to 0
after executing CPUID with EAX = 1, the ability to
switch modes is not supported. BIOS must not
alter the contents of IA32_MISC_ENABLE[24].
33:25
Reserved.
34
Unique
XD Bit Disable (R/W)
See Table 35-2.
63:35
1A1H
417
MSR_PLATFORM_BRV
Reserved.
3, 4, 6
Shared
Platform Feature Requirements (R)
17:0
Reserved.
18
PLATFORM Requirements
When set to 1, indicates the processor has specific
platform requirements. The details of the platform
requirements are listed in the respective data
sheets of the processor.
63:19
1D7H
471
MSR_LER_FROM_LIP
Reserved.
0, 1, 2, 3,
4, 6
Unique
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction
that the processor executed prior to the last
exception that was generated or the last interrupt
that was handled.
See Section 17.11.3, “Last Exception Records.”
31:0
From Linear IP
Linear address of the last branch instruction.
63:32
1D7H
471
Reserved.
63:0
Unique
From Linear IP
Linear address of the last branch instruction (If IA32e mode is active).
1D8H
472
MSR_LER_TO_LIP
0, 1, 2, 3,
4, 6
Unique
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the
last branch instruction that the processor
executed prior to the last exception that was
generated or the last interrupt that was handled.
See Section 17.11.3, “Last Exception Records.”
35-288 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Register Name
Fields and Flags
Dec
Model
Availability
Shared/
Unique1
31:0
Bit Description
From Linear IP
Linear address of the target of the last branch
instruction.
63:32
1D8H
472
Reserved.
63:0
Unique
From Linear IP
Linear address of the target of the last branch
instruction (If IA-32e mode is active).
1D9H
473
MSR_DEBUGCTLA
0, 1, 2, 3,
4, 6
Unique
Debug Control (R/W)
Controls how several debug features are used. Bit
definitions are discussed in the referenced
section.
See Section 17.11.1, “MSR_DEBUGCTLA MSR.”
1DAH
474
MSR_LASTBRANCH
_TOS
0, 1, 2, 3,
4, 6
Unique
Last Branch Record Stack TOS (R/W)
Contains an index (0-3 or 0-15) that points to the
top of the last branch record stack (that is, that
points the index of the MSR containing the most
recent branch record).
See Section 17.11.2, “LBR Stack for Processors
Based on Intel NetBurst® Microarchitecture”; and
addresses 1DBH-1DEH and 680H-68FH.
1DBH
475
MSR_LASTBRANCH_0
0, 1, 2
Unique
Last Branch Record 0 (R/W)
One of four last branch record registers on the last
branch record stack. It contains pointers to the
source and destination instruction for one of the
last four branches, exceptions, or interrupts that
the processor took.
MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_3 at 1DBH-1DEH are
available only on family 0FH, models 0H-02H.
They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH.
See Section 17.10, “Last Branch, Call Stack,
Interrupt, and Exception Recording for Processors
based on Skylake Microarchitecture.”
1DDH
477
MSR_LASTBRANCH_2
0, 1, 2
Unique
Last Branch Record 2
See description of the MSR_LASTBRANCH_0 MSR
at 1DBH.
1DEH
478
MSR_LASTBRANCH_3
0, 1, 2
Unique
Last Branch Record 3
See description of the MSR_LASTBRANCH_0 MSR
at 1DBH.
200H
201H
512
513
IA32_MTRR_PHYSBASE0
IA32_MTRR_PHYSMASK0
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
Variable Range Base MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Vol. 3C 35-289
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
202H
514
203H
204H
205H
206H
207H
208H
209H
20AH
20BH
20CH
20DH
20EH
20FH
250H
258H
259H
268H
269H
515
516
517
518
519
520
521
522
523
524
525
526
527
592
600
601
616
617
35-290 Vol. 3C
Register Name
Fields and Flags
Model
Availability
IA32_MTRR_PHYSBASE1
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
IA32_MTRR_PHYSMASK1
IA32_MTRR_PHYSBASE2
IA32_MTRR_PHYSMASK2
IA32_MTRR_PHYSBASE3
IA32_MTRR_PHYSMASK3
IA32_MTRR_PHYSBASE4
IA32_MTRR_PHYSMASK4
IA32_MTRR_PHYSBASE5
IA32_MTRR_PHYSMASK5
IA32_MTRR_PHYSBASE6
IA32_MTRR_PHYSMASK6
IA32_MTRR_PHYSBASE7
IA32_MTRR_PHYSMASK7
IA32_MTRR_FIX64K_00000
IA32_MTRR_FIX16K_80000
IA32_MTRR_FIX16K_A0000
IA32_MTRR_FIX4K_C0000
IA32_MTRR_FIX4K_C8000
Shared/
Unique1
Bit Description
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs”.
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Variable Range Mask MTRR
See Section 11.11.2.3, “Variable Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs”.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
26AH
618
26BH
26CH
26DH
26EH
26FH
277H
2FFH
619
620
621
622
623
631
767
Register Name
Fields and Flags
IA32_MTRR_FIX4K_D0000
IA32_MTRR_FIX4K_D8000
IA32_MTRR_FIX4K_E0000
IA32_MTRR_FIX4K_E8000
IA32_MTRR_FIX4K_F0000
IA32_MTRR_FIX4K_F8000
IA32_PAT
IA32_MTRR_DEF_TYPE
Model
Availability
Shared/
Unique1
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Shared
0, 1, 2, 3,
4, 6
Unique
0, 1, 2, 3,
4, 6
Shared
Bit Description
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs”.
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Fixed Range MTRR
See Section 11.11.2.2, “Fixed Range MTRRs.”
Page Attribute Table
See Section 11.11.2.2, “Fixed Range MTRRs.”
Default Memory Types (R/W)
See Table 35-2.
See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE
MSR.”
300H
768
MSR_BPU_COUNTER0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
301H
769
MSR_BPU_COUNTER1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
302H
770
MSR_BPU_COUNTER2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
303H
771
MSR_BPU_COUNTER3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
304H
772
MSR_MS_COUNTER0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
305H
773
MSR_MS_COUNTER1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
306H
774
MSR_MS_COUNTER2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
307H
775
MSR_MS_COUNTER3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
308H
776
MSR_FLAME_COUNTER0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
309H
777
MSR_FLAME_COUNTER1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
30AH
778
MSR_FLAME_COUNTER2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
30BH
779
MSR_FLAME_COUNTER3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
Vol. 3C 35-291
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Availability
Shared/
Unique1
Bit Description
Hex
Dec
30CH
780
MSR_IQ_COUNTER0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
30DH
781
MSR_IQ_COUNTER1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
30EH
782
MSR_IQ_COUNTER2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
30FH
783
MSR_IQ_COUNTER3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
310H
784
MSR_IQ_COUNTER4
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
311H
785
MSR_IQ_COUNTER5
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.2, “Performance Counters.”
360H
864
MSR_BPU_CCCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
361H
865
MSR_BPU_CCCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
362H
866
MSR_BPU_CCCR2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
363H
867
MSR_BPU_CCCR3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
364H
868
MSR_MS_CCCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
365H
869
MSR_MS_CCCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
366H
870
MSR_MS_CCCR2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
367H
871
MSR_MS_CCCR3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
368H
872
MSR_FLAME_CCCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
369H
873
MSR_FLAME_CCCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
36AH
874
MSR_FLAME_CCCR2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
36BH
875
MSR_FLAME_CCCR3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
36CH
876
MSR_IQ_CCCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
36DH
877
MSR_IQ_CCCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
36EH
878
MSR_IQ_CCCR2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
36FH
879
MSR_IQ_CCCR3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
35-292 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Availability
Shared/
Unique1
Bit Description
Hex
Dec
370H
880
MSR_IQ_CCCR4
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
371H
881
MSR_IQ_CCCR5
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.3, “CCCR MSRs.”
3A0H
928
MSR_BSU_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A1H
929
MSR_BSU_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A2H
930
MSR_FSB_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A3H
931
MSR_FSB_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A4H
932
MSR_FIRM_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A5H
933
MSR_FIRM_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A6H
934
MSR_FLAME_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A7H
935
MSR_FLAME_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A8H
936
MSR_DAC_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3A9H
937
MSR_DAC_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3AAH
938
MSR_MOB_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3ABH
939
MSR_MOB_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3ACH
940
MSR_PMH_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3ADH
941
MSR_PMH_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3AEH
942
MSR_SAAT_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3AFH
943
MSR_SAAT_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B0H
944
MSR_U2L_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B1H
945
MSR_U2L_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B2H
946
MSR_BPU_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B3H
947
MSR_BPU_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
Vol. 3C 35-293
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Availability
Shared/
Unique1
Bit Description
Hex
Dec
3B4H
948
MSR_IS_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B5H
949
MSR_IS_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B6H
950
MSR_ITLB_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B7H
951
MSR_ITLB_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B8H
952
MSR_CRU_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3B9H
953
MSR_CRU_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3BAH
954
MSR_IQ_ESCR0
0, 1, 2
Shared
See Section 18.15.1, “ESCR MSRs.”
This MSR is not available on later processors. It is
only available on processor family 0FH, models
01H-02H.
3BBH
955
MSR_IQ_ESCR1
0, 1, 2
Shared
See Section 18.15.1, “ESCR MSRs.”
This MSR is not available on later processors. It is
only available on processor family 0FH, models
01H-02H.
3BCH
956
MSR_RAT_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3BDH
957
MSR_RAT_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3BEH
958
MSR_SSU_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C0H
960
MSR_MS_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C1H
961
MSR_MS_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C2H
962
MSR_TBPU_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C3H
963
MSR_TBPU_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C4H
964
MSR_TC_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C5H
965
MSR_TC_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C8H
968
MSR_IX_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3C9H
969
MSR_IX_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3CAH
970
MSR_ALF_ESCR0
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
35-294 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Availability
Shared/
Unique1
Bit Description
Hex
Dec
3CBH
971
MSR_ALF_ESCR1
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3CCH
972
MSR_CRU_ESCR2
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3CDH
973
MSR_CRU_ESCR3
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3E0H
992
MSR_CRU_ESCR4
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3E1H
993
MSR_CRU_ESCR5
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3F0H
1008
MSR_TC_PRECISE_EVENT
0, 1, 2, 3,
4, 6
Shared
See Section 18.15.1, “ESCR MSRs.”
3F1H
1009
MSR_PEBS_ENABLE
0, 1, 2, 3,
4, 6
Shared
Processor Event Based Sampling (PEBS) (R/W)
Controls the enabling of processor event sampling
and replay tagging.
12:0
See Table 19-33.
23:13
Reserved.
24
UOP Tag
Enables replay tagging when set.
25
ENABLE_PEBS_MY_THR (R/W)
Enables PEBS for the target logical processor
when set; disables PEBS when clear (default).
See Section 18.16.3, “IA32_PEBS_ENABLE MSR,”
for an explanation of the target logical processor.
This bit is called ENABLE_PEBS in IA-32
processors that do not support Intel HyperThreading Technology.
26
ENABLE_PEBS_OTH_THR (R/W)
Enables PEBS for the target logical processor
when set; disables PEBS when clear (default).
See Section 18.16.3, “IA32_PEBS_ENABLE MSR,”
for an explanation of the target logical processor.
This bit is reserved for IA-32 processors that do
not support Intel Hyper-Threading Technology.
63:27
Reserved.
3F2H
1010
MSR_PEBS_MATRIX_VERT
0, 1, 2, 3,
4, 6
Shared
See Table 19-33.
400H
1024
IA32_MC0_CTL
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
Vol. 3C 35-295
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
402H
1026
Register Name
Fields and Flags
IA32_MC0_ADDR
Model
Availability
0, 1, 2, 3,
4, 6
Shared/
Unique1
Shared
Bit Description
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not
implemented or contains no address if the ADDRV
flag in the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
403H
1027
IA32_MC0_MISC
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC0_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
404H
1028
IA32_MC1_CTL
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not
implemented or contains no address if the ADDRV
flag in the IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
407H
1031
IA32_MC1_MISC
Shared
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC1_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
408H
1032
IA32_MC2_CTL
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the ADDRV
flag in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
35-296 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
40BH
1035
Register Name
Fields and Flags
Model
Availability
Shared/
Unique1
Bit Description
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
IA32_MC2_MISC
The IA32_MC2_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
40CH
1036
IA32_MC3_CTL
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC3_ADDR
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC3_ADDR register is either not
implemented or contains no address if the ADDRV
flag in the IA32_MC3_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
40FH
1039
IA32_MC3_MISC
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC3_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC3_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
410H
1040
IA32_MC4_CTL
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC4_STATUS
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
IA32_MC4_ADDR
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the ADDRV
flag in the IA32_MC4_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
413H
1043
IA32_MC4_MISC
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC2_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC4_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a generalprotection exception.
Vol. 3C 35-297
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
480H
1152
Register Name
Fields and Flags
IA32_VMX_BASIC
Model
Availability
3, 4, 6
Shared/
Unique1
Unique
Bit Description
Reporting Register of Basic VMX Capabilities
(R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_CTLS
3, 4, 6
Unique
Capability Reporting Register of Pin-based
VM-execution Controls (R/O)
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_CTLS
3, 4, 6
Unique
Capability Reporting Register of Primary
Processor-based VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls,” and
see Table 35-2.
483H
1155
IA32_VMX_EXIT_CTLS
3, 4, 6
Unique
Capability Reporting Register of VM-exit
Controls (R/O)
See Appendix A.4, “VM-Exit Controls,” and see
Table 35-2.
484H
1156
IA32_VMX_ENTRY_CTLS
3, 4, 6
Unique
Capability Reporting Register of VM-entry
Controls (R/O)
See Appendix A.5, “VM-Entry Controls,” and see
Table 35-2.
485H
1157
IA32_VMX_MISC
3, 4, 6
Unique
Reporting Register of Miscellaneous VMX
Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data,” and see
Table 35-2.
486H
1158
IA32_VMX_CR0_FIXED0
3, 4, 6
Unique
Capability Reporting Register of CR0 Bits Fixed
to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0,” and
see Table 35-2.
487H
1159
IA32_VMX_CR0_FIXED1
3, 4, 6
Unique
Capability Reporting Register of CR0 Bits Fixed
to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0,” and
see Table 35-2.
488H
1160
IA32_VMX_CR4_FIXED0
3, 4, 6
Unique
Capability Reporting Register of CR4 Bits Fixed
to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4,” and
see Table 35-2.
489H
1161
IA32_VMX_CR4_FIXED1
3, 4, 6
Unique
Capability Reporting Register of CR4 Bits Fixed
to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4,” and
see Table 35-2.
48AH
1162
IA32_VMX_VMCS_ENUM
3, 4, 6
Unique
Capability Reporting Register of VMCS Field
Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration,” and see
Table 35-2.
35-298 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
48BH
1163
Register Name
Fields and Flags
IA32_VMX_PROCBASED_CTLS2
Model
Availability
3, 4, 6
Shared/
Unique1
Unique
Bit Description
Capability Reporting Register of Secondary
Processor-based VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls,” and
see Table 35-2.
600H
1536
IA32_DS_AREA
0, 1, 2, 3,
4, 6
Unique
DS Save Area (R/W)
See Table 35-2.
See Section 18.15.4, “Debug Store (DS)
Mechanism.”
680H
1664
MSR_LASTBRANCH_0_FROM_IP
3, 4, 6
Unique
Last Branch Record 0 (R/W)
One of 16 pairs of last branch record registers on
the last branch record stack (680H-68FH). This
part of the stack contains pointers to the source
instruction for one of the last 16 branches,
exceptions, or interrupts taken by the processor.
The MSRs at 680H-68FH, 6C0H-6CfH are not
available in processor releases before family 0FH,
model 03H. These MSRs replace MSRs previously
located at 1DBH-1DEH.which performed the same
function for early releases.
See Section 17.10, “Last Branch, Call Stack,
Interrupt, and Exception Recording for Processors
based on Skylake Microarchitecture.”
681H
1665
MSR_LASTBRANCH_1_FROM_IP
3, 4, 6
Unique
682H
1666
MSR_LASTBRANCH_2_FROM_IP
3, 4, 6
Unique
Last Branch Record 1
See description of MSR_LASTBRANCH_0 at 680H.
Last Branch Record 2
See description of MSR_LASTBRANCH_0 at 680H.
683H
1667
MSR_LASTBRANCH_3_FROM_IP
3, 4, 6
Unique
684H
1668
MSR_LASTBRANCH_4_FROM_IP
3, 4, 6
Unique
Last Branch Record 3
See description of MSR_LASTBRANCH_0 at 680H.
Last Branch Record 4
See description of MSR_LASTBRANCH_0 at 680H.
685H
1669
MSR_LASTBRANCH_5_FROM_IP
3, 4, 6
Unique
686H
1670
MSR_LASTBRANCH_6_FROM_IP
3, 4, 6
Unique
Last Branch Record 5
See description of MSR_LASTBRANCH_0 at 680H.
Last Branch Record 6
See description of MSR_LASTBRANCH_0 at 680H.
687H
1671
MSR_LASTBRANCH_7_FROM_IP
3, 4, 6
Unique
688H
1672
MSR_LASTBRANCH_8_FROM_IP
3, 4, 6
Unique
Last Branch Record 7
See description of MSR_LASTBRANCH_0 at 680H.
Last Branch Record 8
See description of MSR_LASTBRANCH_0 at 680H.
689H
1673
MSR_LASTBRANCH_9_FROM_IP
3, 4, 6
Unique
68AH
1674
MSR_LASTBRANCH_10_FROM_IP 3, 4, 6
Unique
Last Branch Record 9
See description of MSR_LASTBRANCH_0 at 680H.
Last Branch Record 10
See description of MSR_LASTBRANCH_0 at 680H.
Vol. 3C 35-299
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
68BH
1675
Register Name
Fields and Flags
Model
Availability
MSR_LASTBRANCH_11_FROM_IP 3, 4, 6
Shared/
Unique1
Unique
Bit Description
Last Branch Record 11
See description of MSR_LASTBRANCH_0 at 680H.
68CH
1676
MSR_LASTBRANCH_12_FROM_IP 3, 4, 6
Unique
Last Branch Record 12
See description of MSR_LASTBRANCH_0 at 680H.
68DH
1677
MSR_LASTBRANCH_13_FROM_IP 3, 4, 6
Unique
Last Branch Record 13
See description of MSR_LASTBRANCH_0 at 680H.
68EH
1678
MSR_LASTBRANCH_14_FROM_IP 3, 4, 6
Unique
Last Branch Record 14
See description of MSR_LASTBRANCH_0 at 680H.
68FH
1679
MSR_LASTBRANCH_15_FROM_IP 3, 4, 6
Unique
Last Branch Record 15
See description of MSR_LASTBRANCH_0 at 680H.
6C0H
1728
MSR_LASTBRANCH_0_TO_IP
3, 4, 6
Unique
Last Branch Record 0 (R/W)
One of 16 pairs of last branch record registers on
the last branch record stack (6C0H-6CFH). This
part of the stack contains pointers to the
destination instruction for one of the last 16
branches, exceptions, or interrupts that the
processor took.
See Section 17.10, “Last Branch, Call Stack,
Interrupt, and Exception Recording for Processors
based on Skylake Microarchitecture.”
6C1H
1729
MSR_LASTBRANCH_1_TO_IP
3, 4, 6
Unique
Last Branch Record 1
See description of MSR_LASTBRANCH_0 at 6C0H.
6C2H
1730
MSR_LASTBRANCH_2_TO_IP
3, 4, 6
Unique
Last Branch Record 2
See description of MSR_LASTBRANCH_0 at 6C0H.
6C3H
1731
MSR_LASTBRANCH_3_TO_IP
3, 4, 6
Unique
Last Branch Record 3
See description of MSR_LASTBRANCH_0 at 6C0H.
6C4H
1732
MSR_LASTBRANCH_4_TO_IP
3, 4, 6
Unique
Last Branch Record 4
See description of MSR_LASTBRANCH_0 at 6C0H.
6C5H
1733
MSR_LASTBRANCH_5_TO_IP
3, 4, 6
Unique
Last Branch Record 5
See description of MSR_LASTBRANCH_0 at 6C0H.
6C6H
1734
MSR_LASTBRANCH_6_TO_IP
3, 4, 6
Unique
Last Branch Record 6
See description of MSR_LASTBRANCH_0 at 6C0H.
6C7H
1735
MSR_LASTBRANCH_7_TO_IP
3, 4, 6
Unique
Last Branch Record 7
See description of MSR_LASTBRANCH_0 at 6C0H.
6C8H
1736
MSR_LASTBRANCH_8_TO_IP
3, 4, 6
Unique
Last Branch Record 8
See description of MSR_LASTBRANCH_0 at 6C0H.
6C9H
1737
MSR_LASTBRANCH_9_TO_IP
3, 4, 6
Unique
Last Branch Record 9
See description of MSR_LASTBRANCH_0 at 6C0H.
6CAH
1738
MSR_LASTBRANCH_10_TO_IP
3, 4, 6
Unique
Last Branch Record 10
See description of MSR_LASTBRANCH_0 at 6C0H.
35-300 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Hex
Dec
6CBH
1739
Register Name
Fields and Flags
MSR_LASTBRANCH_11_TO_IP
Model
Availability
3, 4, 6
Shared/
Unique1
Unique
Bit Description
Last Branch Record 11
See description of MSR_LASTBRANCH_0 at 6C0H.
6CCH
1740
MSR_LASTBRANCH_12_TO_IP
3, 4, 6
Unique
Last Branch Record 12
See description of MSR_LASTBRANCH_0 at 6C0H.
6CDH
1741
MSR_LASTBRANCH_13_TO_IP
3, 4, 6
Unique
Last Branch Record 13
See description of MSR_LASTBRANCH_0 at 6C0H.
6CEH
1742
MSR_LASTBRANCH_14_TO_IP
3, 4, 6
Unique
Last Branch Record 14
See description of MSR_LASTBRANCH_0 at 6C0H.
6CFH
1743
MSR_LASTBRANCH_15_TO_IP
3, 4, 6
Unique
Last Branch Record 15
See description of MSR_LASTBRANCH_0 at 6C0H.
C000_
0080H
IA32_EFER
C000_
0081H
IA32_STAR
C000_
0082H
IA32_LSTAR
C000_
0084H
IA32_FMASK
C000_
0100H
IA32_FS_BASE
C000_
0101H
IA32_GS_BASE
C000_
0102H
IA32_KERNEL_GS_BASE
3, 4, 6
Unique
Extended Feature Enables
See Table 35-2.
3, 4, 6
Unique
System Call Target Address (R/W)
See Table 35-2.
3, 4, 6
Unique
IA-32e Mode System Call Target Address (R/W)
See Table 35-2.
3, 4, 6
Unique
System Call Flag Mask (R/W)
See Table 35-2.
3, 4, 6
Unique
Map of BASE Address of FS (R/W)
See Table 35-2.
3, 4, 6
Unique
Map of BASE Address of GS (R/W)
See Table 35-2.
3, 4, 6
Unique
Swap Target of BASE Address of GS (R/W)
See Table 35-2.
NOTES
1. For HT-enabled processors, there may be more than one logical processors per physical unit. If an MSR is Shared, this means that
one MSR is shared between logical processors. If an MSR is unique, this means that each logical processor has its own MSR.
35.18.1 MSRs Unique to Intel® Xeon® Processor MP with L3 Cache
The MSRs listed in Table 35-42 apply to Intel® Xeon® Processor MP with up to 8MB level three cache. These
processors can be detected by enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX
= 4 as input) to detect the presence of the third level cache, and with CPUID reporting family encoding 0FH, model
encoding 3 or 4 (see CPUID instruction for more details).
Vol. 3C 35-301
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-42. MSRs Unique to 64-bit Intel® Xeon® Processor MP with
Up to an 8 MB L3 Cache
Register Address
107CCH
Register Name
Fields and Flags
MSR_IFSB_BUSQ0
Model Availability
3, 4
Shared/
Unique
Shared
Bit Description
IFSB BUSQ Event Control and Counter
Register (R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache.”
107CDH
MSR_IFSB_BUSQ1
3, 4
Shared
IFSB BUSQ Event Control and Counter
Register (R/W)
107CEH
MSR_IFSB_SNPQ0
3, 4
Shared
IFSB SNPQ Event Control and Counter
Register (R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache.”
107CFH
MSR_IFSB_SNPQ1
3, 4
Shared
IFSB SNPQ Event Control and Counter
Register (R/W)
107D0H
MSR_EFSB_DRDY0
3, 4
Shared
EFSB DRDY Event Control and Counter
Register (R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache” for
details.
107D1H
MSR_EFSB_DRDY1
3, 4
Shared
EFSB DRDY Event Control and Counter
Register (R/W)
107D2H
MSR_IFSB_CTL6
3, 4
Shared
IFSB Latency Event Control Register
(R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache” for
details.
107D3H
MSR_IFSB_CNTR7
3, 4
Shared
IFSB Latency Event Counter Register
(R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache.”
The MSRs listed in Table 35-43 apply to Intel® Xeon® Processor 7100 series. These processors can be detected by
enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the
presence of the third level cache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID
instruction for more details.). The performance monitoring MSRs listed in Table 35-43 are shared between logical
processors in the same core, but are replicated for each core.
35-302 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-43. MSRs Unique to Intel® Xeon® Processor 7100 Series
Register Address
107CCH
Register Name
Fields and Flags
Model Availability
MSR_EMON_L3_CTR_CTL0
6
Shared/
Unique
Shared
Bit Description
GBUSQ Event Control and Counter
Register (R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache.”
107CDH
MSR_EMON_L3_CTR_CTL1
6
Shared
GBUSQ Event Control and Counter
Register (R/W)
107CEH
MSR_EMON_L3_CTR_CTL2
6
Shared
GSNPQ Event Control and Counter
Register (R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache.”
107CFH
MSR_EMON_L3_CTR_CTL3
6
Shared
GSNPQ Event Control and Counter
Register (R/W)
107D0H
MSR_EMON_L3_CTR_CTL4
6
Shared
FSB Event Control and Counter Register
(R/W)
See Section 18.21, “Performance
Monitoring on 64-bit Intel Xeon Processor
MP with Up to 8-MByte L3 Cache” for
details.
107D1H
MSR_EMON_L3_CTR_CTL5
6
Shared
FSB Event Control and Counter Register
(R/W)
107D2H
MSR_EMON_L3_CTR_CTL6
6
Shared
FSB Event Control and Counter Register
(R/W)
107D3H
MSR_EMON_L3_CTR_CTL7
6
Shared
FSB Event Control and Counter Register
(R/W)
35.19
MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS
Model-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, and Dual-core Intel Xeon processor
LV are listed in Table 35-44. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means
each processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared”
means the MSR or the bit field in an MSR address governs the operation of both processor cores.
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec
0H
0
P5_MC_ADDR
Unique
See Section 35.22, “MSRs in Pentium Processors,” and see
Table 35-2.
1H
1
P5_MC_TYPE
Unique
See Section 35.22, “MSRs in Pentium Processors,” and see
Table 35-2.
6H
6
IA32_MONITOR_FILTER_
SIZE
Unique
See Section 8.10.5, “Monitor/Mwait Address Range Determination,”
and see Table 35-2.
Vol. 3C 35-303
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec
10H
16
IA32_TIME_STAMP_
COUNTER
Unique
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
17H
23
IA32_PLATFORM_ID
Shared
Platform ID (R)
See Table 35-2.
The operating system can use this MSR to determine “slot”
information for the processor and the proper microcode update to
load.
1BH
27
IA32_APIC_BASE
Unique
See Section 10.4.4, “Local APIC Status and Location,” and see
Table 35-2.
2AH
42
MSR_EBL_CR_POWERON
Shared
Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current
processor configuration.
0
Reserved.
1
Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
2
Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
3
MCERR# Drive Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
4
Address Parity Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
6: 5
Reserved
7
BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
8
Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled
9
Execute BIST (R/O)
1 = Enabled; 0 = Disabled
10
MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
11
Reserved
12
BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
13
Reserved
14
1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes
35-304 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
15
Reserved
17:16
APIC Cluster ID (R/O)
18
System Bus Frequency (R/O)
0 = 100 MHz
1 = Reserved
19
Reserved.
21: 20
Symmetric Arbitration ID (R/O)
26:22
Clock Frequency Ratio (R/O)
3AH
58
IA32_FEATURE_CONTROL
Unique
40H
64
MSR_LASTBRANCH_0
Unique
Control Features in IA-32 Processor (R/W)
See Table 35-2.
Last Branch Record 0 (R/W)
One of 8 last branch record registers on the last branch record
stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold the ‘to’
address. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.13, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).”
41H
65
MSR_LASTBRANCH_1
Unique
Last Branch Record 1 (R/W)
See description of MSR_LASTBRANCH_0.
42H
66
MSR_LASTBRANCH_2
Unique
Last Branch Record 2 (R/W)
See description of MSR_LASTBRANCH_0.
43H
67
MSR_LASTBRANCH_3
Unique
Last Branch Record 3 (R/W)
See description of MSR_LASTBRANCH_0.
44H
68
MSR_LASTBRANCH_4
Unique
Last Branch Record 4 (R/W)
See description of MSR_LASTBRANCH_0.
45H
69
MSR_LASTBRANCH_5
Unique
Last Branch Record 5 (R/W)
See description of MSR_LASTBRANCH_0.
46H
70
MSR_LASTBRANCH_6
Unique
Last Branch Record 6 (R/W)
See description of MSR_LASTBRANCH_0.
47H
71
MSR_LASTBRANCH_7
Unique
Last Branch Record 7 (R/W)
See description of MSR_LASTBRANCH_0.
79H
121
IA32_BIOS_UPDT_TRIG
Unique
BIOS Update Trigger Register (W)
See Table 35-2.
8BH
139
IA32_BIOS_SIGN_ID
Unique
BIOS Update Signature ID (RO)
See Table 35-2.
C1H
193
IA32_PMC0
Unique
Performance counter register
See Table 35-2.
C2H
194
IA32_PMC1
Unique
Performance counter register
See Table 35-2.
Vol. 3C 35-305
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Hex
Dec
CDH
205
Register Name
MSR_FSB_FREQ
Shared/
Unique
Shared
Bit Description
Scaleable Bus Speed (RO)
This field indicates the scaleable bus clock speed:
2:0
• 101B: 100 MHz (FSB 400)
• 001B: 133 MHz (FSB 533)
• 011B: 167 MHz (FSB 667)
133.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 101B.
166.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 001B.
63:3
E7H
231
IA32_MPERF
Reserved.
Unique
Maximum Performance Frequency Clock Count. (RW)
See Table 35-2.
E8H
232
IA32_APERF
Unique
Actual Performance Frequency Clock Count. (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Unique
11EH
281
MSR_BBL_CR_CTL3
Shared
0
See Table 35-2.
L2 Hardware Enabled (RO)
1 = If the L2 is hardware-enabled
0 = Indicates if the L2 is hardware-disabled
7:1
Reserved.
8
L2 Enabled (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the WBINVD
instruction or the assertion of the FLUSH# input.
22:9
Reserved.
23
L2 Not Present (RO)
0 = L2 Present
1 = L2 Not Present
63:24
Reserved.
174H
372
IA32_SYSENTER_CS
Unique
See Table 35-2.
175H
373
IA32_SYSENTER_ESP
Unique
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Unique
See Table 35-2.
179H
377
IA32_MCG_CAP
Unique
See Table 35-2.
17AH
378
IA32_MCG_STATUS
Unique
35-306 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
0
RIPV
When set, this bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If this bit is
cleared, the program cannot be reliably restarted.
1
EIPV
When set, this bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, this bit indicates that a machine check has been
generated. If a second machine check is detected while this bit is
still set, the processor enters a shutdown state. Software should
write this bit to 0 after processing a machine check exception.
63:3
Reserved.
186H
390
IA32_PERFEVTSEL0
Unique
See Table 35-2.
187H
391
IA32_PERFEVTSEL1
Unique
See Table 35-2.
198H
408
IA32_PERF_STATUS
Shared
See Table 35-2.
199H
409
IA32_PERF_CTL
Unique
See Table 35-2.
19AH
410
IA32_CLOCK_
MODULATION
Unique
Clock Modulation (R/W)
IA32_THERM_
INTERRUPT
Unique
19BH
411
See Table 35-2.
Thermal Interrupt Control (R/W)
See Table 35-2.
See Section 14.7.2, “Thermal Monitor.”
19CH
412
IA32_THERM_STATUS
Unique
Thermal Monitor Status (R/W)
See Table 35-2.
See Section 14.7.2, “Thermal Monitor”.
19DH
413
MSR_THERM2_CTL
Unique
15:0
Reserved.
16
TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of
the stop-clock duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT
has no effect. Neither TM1 nor TM2 will be enabled.
1A0H
416
63:16
Reserved.
IA32_MISC_ENABLE
Enable Miscellaneous Processor Features
(R/W)
Allows a variety of processor functions to be enabled and disabled.
2:0
Reserved.
Vol. 3C 35-307
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Hex
Register Name
Shared/
Unique
Bit Description
Dec
3
Unique
Automatic Thermal Control Circuit Enable (R/W)
See Table 35-2.
6:4
7
Reserved.
Shared
Performance Monitoring Available (R)
See Table 35-2.
9:8
10
Reserved.
Shared
FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break
event within the processor
0 = Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model usage.
11
Shared
Branch Trace Storage Unavailable (RO)
See Table 35-2.
12
13
Reserved.
Shared
TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that the
die temperature is at the pre-determined threshold, the Thermal
Monitor 2 mechanism is engaged. TM2 will reduce the bus to core
ratio and voltage according to the value last written to
MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change
the VID signals or the bus to core ratio when the processor enters
a thermal managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing
CPUID with EAX = 1, then this feature is not supported and BIOS
must not alter the contents of this bit location. The processor is
operating out of spec if both this bit and the TM1 bit are set to
disabled states.
15:14
16
Reserved.
Shared
Enhanced Intel SpeedStep Technology Enable (R/W)
1=
18
Shared
Enhanced Intel SpeedStep Technology enabled
ENABLE MONITOR FSM (R/W)
See Table 35-2.
19
22
Reserved.
Shared
Limit CPUID Maxval (R/W)
See Table 35-2.
Setting this bit may cause behavior in software that depends on
the availability of CPUID leaves greater than 2.
33:23
34
Reserved.
Shared
XD Bit Disable (R/W)
See Table 35-2.
63:35
35-308 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Hex
Dec
1C9H
457
Register Name
MSR_LASTBRANCH_TOS
Shared/
Unique
Unique
Bit Description
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the
most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
1D9H
473
IA32_DEBUGCTL
Unique
Debug Control (R/W)
Controls how several debug features are used. Bit definitions are
discussed in the referenced section.
1DDH
477
MSR_LER_FROM_LIP
Unique
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
1DEH
478
MSR_LER_TO_LIP
Unique
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled.
1E0H
480
ROB_CR_
BKUPTMPDR6
Unique
1:0
Reserved.
2
Fast String Enable bit. (Default, enabled)
200H
512
MTRRphysBase0
Unique
201H
513
MTRRphysMask0
Unique
202H
514
MTRRphysBase1
Unique
203H
515
MTRRphysMask1
Unique
204H
516
MTRRphysBase2
Unique
205H
517
MTRRphysMask2
Unique
206H
518
MTRRphysBase3
Unique
207H
519
MTRRphysMask3
Unique
208H
520
MTRRphysBase4
Unique
209H
521
MTRRphysMask4
Unique
20AH
522
MTRRphysBase5
Unique
20BH
523
MTRRphysMask5
Unique
20CH
524
MTRRphysBase6
Unique
20DH
525
MTRRphysMask6
Unique
20EH
526
MTRRphysBase7
Unique
20FH
527
MTRRphysMask7
Unique
250H
592
MTRRfix64K_00000
Unique
258H
600
MTRRfix16K_80000
Unique
259H
601
MTRRfix16K_A0000
Unique
268H
616
MTRRfix4K_C0000
Unique
Vol. 3C 35-309
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Register Name
Shared/
Unique
Hex
Dec
269H
617
MTRRfix4K_C8000
Unique
26AH
618
MTRRfix4K_D0000
Unique
26BH
619
MTRRfix4K_D8000
Unique
26CH
620
MTRRfix4K_E0000
Unique
26DH
621
MTRRfix4K_E8000
Unique
26EH
622
MTRRfix4K_F0000
Unique
26FH
623
MTRRfix4K_F8000
Unique
2FFH
767
IA32_MTRR_DEF_TYPE
Unique
Bit Description
Default Memory Types (R/W)
See Table 35-2.
See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
400H
1024
IA32_MC0_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC0_STATUS
register is clear. When not implemented in the processor, all reads
and writes to this MSR will cause a general-protection exception.
404H
1028
IA32_MC1_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC1_STATUS
register is clear. When not implemented in the processor, all reads
and writes to this MSR will cause a general-protection exception.
408H
1032
IA32_MC2_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC2_STATUS
register is clear. When not implemented in the processor, all reads
and writes to this MSR will cause a general-protection exception.
40CH
1036
MSR_MC4_CTL
Unique
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
MSR_MC4_STATUS
Unique
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
MSR_MC4_ADDR
Unique
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear. When not implemented in the processor, all reads
and writes to this MSR will cause a general-protection exception.
410H
1040
IA32_MC3_CTL
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC3_STATUS
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
35-310 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Hex
Dec
412H
1042
Register Name
MSR_MC3_ADDR
Shared/
Unique
Unique
Bit Description
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC3_STATUS
register is clear. When not implemented in the processor, all reads
and writes to this MSR will cause a general-protection exception.
413H
1043
MSR_MC3_MISC
Unique
414H
1044
MSR_MC5_CTL
Unique
415H
1045
MSR_MC5_STATUS
Unique
416H
1046
MSR_MC5_ADDR
Unique
417H
1047
MSR_MC5_MISC
Unique
480H
1152
IA32_VMX_BASIC
Unique
Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information”
(If CPUID.01H:ECX.[bit 9])
481H
1153
IA32_VMX_PINBASED_
CTLS
Unique
Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Appendix A.3, “VM-Execution Controls”
(If CPUID.01H:ECX.[bit 9])
482H
1154
IA32_VMX_PROCBASED_
CTLS
Unique
Capability Reporting Register of Primary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls”
(If CPUID.01H:ECX.[bit 9])
483H
1155
IA32_VMX_EXIT_CTLS
Unique
Capability Reporting Register of VM-exit Controls (R/O)
See Appendix A.4, “VM-Exit Controls”
(If CPUID.01H:ECX.[bit 9])
484H
1156
IA32_VMX_ENTRY_CTLS
Unique
Capability Reporting Register of VM-entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls”
(If CPUID.01H:ECX.[bit 9])
485H
1157
IA32_VMX_MISC
Unique
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data”
(If CPUID.01H:ECX.[bit 9])
486H
1158
IA32_VMX_CR0_FIXED0
Unique
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0”
(If CPUID.01H:ECX.[bit 9])
487H
1159
IA32_VMX_CR0_FIXED1
Unique
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0”
(If CPUID.01H:ECX.[bit 9])
488H
1160
IA32_VMX_CR4_FIXED0
Unique
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4”
(If CPUID.01H:ECX.[bit 9])
Vol. 3C 35-311
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-44. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Address
Hex
Dec
489H
1161
Register Name
IA32_VMX_CR4_FIXED1
Shared/
Unique
Unique
Bit Description
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4”
(If CPUID.01H:ECX.[bit 9])
48AH
1162
IA32_VMX_VMCS_ENUM
Unique
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration”
(If CPUID.01H:ECX.[bit 9])
48BH
1163
IA32_VMX_PROCBASED_
CTLS2
Unique
Capability Reporting Register of Secondary Processor-based
VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls”
(If CPUID.01H:ECX.[bit 9] and
IA32_VMX_PROCBASED_CTLS[bit 63])
600H
1536
IA32_DS_AREA
Unique
DS Save Area (R/W)
See Table 35-2.
See Section 18.15.4, “Debug Store (DS) Mechanism.”
31:0
DS Buffer Management Area
Linear address of the first byte of the DS buffer management area.
63:32
C000_
0080H
35.20
Reserved.
IA32_EFER
Unique
See Table 35-2.
10:0
Reserved.
11
Execute Disable Bit Enable
63:12
Reserved.
MSRS IN THE PENTIUM M PROCESSOR
Model-specific registers (MSRs) for the Pentium M processor are similar to those described in Section 35.21 for P6
family processors. The following table describes new MSRs and MSRs whose behavior has changed on the Pentium
M processor.
Table 35-45. MSRs in Pentium M Processors
Register
Address
Register Name
Bit Description
Hex
Dec
0H
0
P5_MC_ADDR
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
P5_MC_TYPE
See Section 35.22, “MSRs in Pentium Processors.”
10H
16
IA32_TIME_STAMP_COUNTER
See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.
17H
23
IA32_PLATFORM_ID
Platform ID (R)
See Table 35-2.
The operating system can use this MSR to determine “slot” information
for the processor and the proper microcode update to load.
35-312 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-45. MSRs in Pentium M Processors (Contd.)
Register
Address
Hex
Dec
2AH
42
Register Name
MSR_EBL_CR_POWERON
Bit Description
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features.
(R) Indicates current processor configuration.
0
Reserved.
1
Data Error Checking Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
2
Response Error Checking Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
3
MCERR# Drive Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
4
Address Parity Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
6:5
Reserved.
7
BINIT# Driver Enable (R)
1 = Enabled; 0 = Disabled
Always 0 on the Pentium M processor.
8
Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled
9
Execute BIST (R/O)
1 = Enabled; 0 = Disabled
10
MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
Always 0 on the Pentium M processor.
11
Reserved.
12
BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
Always 0 on the Pentium M processor.
13
Reserved.
14
1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes
Always 0 on the Pentium M processor.
15
Reserved.
17:16
APIC Cluster ID (R/O)
Always 00B on the Pentium M processor.
Vol. 3C 35-313
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-45. MSRs in Pentium M Processors (Contd.)
Register
Address
Hex
Register Name
Bit Description
Dec
18
System Bus Frequency (R/O)
0 = 100 MHz
1 = Reserved
Always 0 on the Pentium M processor.
19
Reserved.
21: 20
Symmetric Arbitration ID (R/O)
Always 00B on the Pentium M processor.
40H
64
26:22
Clock Frequency Ratio (R/O)
MSR_LASTBRANCH_0
Last Branch Record 0 (R/W)
One of 8 last branch record registers on the last branch record stack: bits
31-0 hold the ‘from’ address and bits 63-32 hold the to address.
See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.13, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)”
41H
65
MSR_LASTBRANCH_1
42H
66
MSR_LASTBRANCH_2
Last Branch Record 1 (R/W)
See description of MSR_LASTBRANCH_0.
Last Branch Record 2 (R/W)
See description of MSR_LASTBRANCH_0.
43H
67
MSR_LASTBRANCH_3
44H
68
MSR_LASTBRANCH_4
Last Branch Record 3 (R/W)
See description of MSR_LASTBRANCH_0.
Last Branch Record 4 (R/W)
See description of MSR_LASTBRANCH_0.
45H
69
MSR_LASTBRANCH_5
46H
70
MSR_LASTBRANCH_6
Last Branch Record 5 (R/W)
See description of MSR_LASTBRANCH_0.
Last Branch Record 6 (R/W)
See description of MSR_LASTBRANCH_0.
47H
71
MSR_LASTBRANCH_7
119H
281
MSR_BBL_CR_CTL
Last Branch Record 7 (R/W)
See description of MSR_LASTBRANCH_0.
63:0
11EH
281
Reserved.
MSR_BBL_CR_CTL3
0
L2 Hardware Enabled (RO)
1 = If the L2 is hardware-enabled
0 = Indicates if the L2 is hardware-disabled
4:1
35-314 Vol. 3C
Reserved.
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-45. MSRs in Pentium M Processors (Contd.)
Register
Address
Hex
Register Name
Bit Description
Dec
5
ECC Check Enable (RO)
This bit enables ECC checking on the cache data bus. ECC is always
generated on write cycles.
0 = Disabled (default)
1 = Enabled
For the Pentium M processor, ECC checking on the cache data bus is
always enabled.
7:6
Reserved.
8
L2 Enabled (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the WBINVD
instruction or the assertion of the FLUSH# input.
22:9
Reserved.
23
L2 Not Present (RO)
0 = L2 Present
1 = L2 Not Present
63:24
179H
377
Reserved.
IA32_MCG_CAP
7:0
Count (RO)
Indicates the number of hardware unit error reporting banks available in
the processor.
8
IA32_MCG_CTL Present (RO)
1 = Indicates that the processor implements the MSR_MCG_CTL
register found at MSR 17BH.
0 = Not supported.
63:9
17AH
378
Reserved.
IA32_MCG_STATUS
0
RIPV
When set, this bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check was
generated) can be used to restart the program. If this bit is cleared, the
program cannot be reliably restarted.
1
EIPV
When set, this bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check was
generated) is directly associated with the error.
2
MCIP
When set, this bit indicates that a machine check has been generated. If a
second machine check is detected while this bit is still set, the processor
enters a shutdown state. Software should write this bit to 0 after
processing a machine check exception.
63:3
Reserved.
Vol. 3C 35-315
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-45. MSRs in Pentium M Processors (Contd.)
Register
Address
Register Name
Bit Description
Hex
Dec
198H
408
IA32_PERF_STATUS
See Table 35-2.
199H
409
IA32_PERF_CTL
See Table 35-2.
19AH
410
IA32_CLOCK_MODULATION
Clock Modulation (R/W).
See Table 35-2.
See Section 14.7.3, “Software Controlled Clock Modulation.”
19BH
411
IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 35-2.
See Section 14.7.2, “Thermal Monitor.”
19CH
412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 35-2.
See Section 14.7.2, “Thermal Monitor.”
19DH
413
MSR_THERM2_CTL
15:0
Reserved.
16
TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the
stop-clock duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no
effect. Neither TM1 nor TM2 will be enabled.
1A0H
416
63:16
Reserved.
IA32_MISC_ENABLE
Enable Miscellaneous Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
2:0
Reserved.
3
Automatic Thermal Control Circuit Enable (R/W)
1 = Setting this bit enables the thermal control circuit (TCC) portion of
the Intel Thermal Monitor feature. This allows processor clocks to
be automatically modulated based on the processor's thermal
sensor operation.
0 = Disabled (default).
The automatic thermal control circuit enable bit determines if the
thermal control circuit (TCC) will be activated when the processor's
internal thermal sensor determines the processor is about to exceed its
maximum operating temperature.
When the TCC is activated and TM1 is enabled, the processors clocks will
be forced to a 50% duty cycle. BIOS must enable this feature.
The bit should not be confused with the on-demand thermal control
circuit enable bit.
6:4
Reserved.
7
Performance Monitoring Available (R)
1=
0=
35-316 Vol. 3C
Performance monitoring enabled
Performance monitoring disabled
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-45. MSRs in Pentium M Processors (Contd.)
Register
Address
Hex
Register Name
Bit Description
Dec
9:8
Reserved.
10
FERR# Multiplexing Enable (R/W)
1=
FERR# asserted by the processor to indicate a pending break
event within the processor
0 = Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model usage.
Branch Trace Storage Unavailable (RO)
1 = Processor doesn’t support branch trace storage (BTS)
0 = BTS is supported
12
Processor Event Based Sampling Unavailable (RO)
1=
Processor does not support processor event based sampling
(PEBS);
0 = PEBS is supported.
The Pentium M processor does not support PEBS.
15:13
Reserved.
16
Enhanced Intel SpeedStep Technology Enable (R/W)
1 = Enhanced Intel SpeedStep Technology enabled.
On the Pentium M processor, this bit may be configured to be read-only.
22:17
Reserved.
23
xTPR Message Disable (R/W)
When set to 1, xTPR messages are disabled. xTPR messages are optional
messages that allow the processor to inform the chipset of its priority.
The default is processor specific.
1C9H
457
63:24
Reserved.
MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the most
recent branch record. See also:
• MSR_LASTBRANCH_0_FROM_IP (at 40H)
• Section 17.13, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)”
1D9H
473
MSR_DEBUGCTLB
Debug Control (R/W)
Controls how several debug features are used. Bit definitions are
discussed in the referenced section.
See Section 17.13, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).”
1DDH
477
MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch instruction
that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
See Section 17.13, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)” and Section 17.14.2, “Last Branch and Last
Exception MSRs.”
Vol. 3C 35-317
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-45. MSRs in Pentium M Processors (Contd.)
Register
Address
Hex
Dec
1DEH
478
Register Name
MSR_LER_FROM_LIP
Bit Description
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
See Section 17.13, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)” and Section 17.14.2, “Last Branch and Last
Exception MSRs.”
2FFH
767
IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
Sets the memory type for the regions of physical memory that are not
mapped by the MTRRs.
See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
400H
1024
IA32_MC0_CTL
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”.
The IA32_MC0_ADDR register is either not implemented or contains no
address if the ADDRV flag in the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
404H
1028
IA32_MC1_CTL
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or contains no
address if the ADDRV flag in the IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
408H
1032
IA32_MC2_CTL
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
See Chapter 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no
address if the ADDRV flag in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
40CH
1036
MSR_MC4_CTL
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
MSR_MC4_STATUS
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
MSR_MC4_ADDR
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no
address if the ADDRV flag in the MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
410H
1040
MSR_MC3_CTL
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
MSR_MC3_STATUS
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
35-318 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-45. MSRs in Pentium M Processors (Contd.)
Register
Address
Hex
Dec
412H
1042
Register Name
MSR_MC3_ADDR
Bit Description
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no
address if the ADDRV flag in the MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
600H
1536
IA32_DS_AREA
DS Save Area (R/W)
See Table 35-2.
Points to the DS buffer management area, which is used to manage the
BTS and PEBS buffers. See Section 18.15.4, “Debug Store (DS)
Mechanism.”
31:0
DS Buffer Management Area
Linear address of the first byte of the DS buffer management area.
63:32
35.21
Reserved.
MSRS IN THE P6 FAMILY PROCESSORS
The following MSRs are defined for the P6 family processors. The MSRs in this table that are shaded are available
only in the Pentium II and Pentium III processors. Beginning with the Pentium 4 processor, some of the MSRs in this
list have been designated as “architectural” and have had their names changed. See Table 35-2 for a list of the
architectural MSRs.
Table 35-46. MSRs in the P6 Family Processors
Register
Address
Register Name
Bit Description
Hex
Dec
0H
0
P5_MC_ADDR
See Section 35.22, “MSRs in Pentium Processors.”
1H
1
P5_MC_TYPE
See Section 35.22, “MSRs in Pentium Processors.”
10H
16
TSC
See Section 17.15, “Time-Stamp Counter.”
17H
23
IA32_PLATFORM_ID
Platform ID (R)
The operating system can use this MSR to determine “slot” information for
the processor and the proper microcode update to load.
49:0
Reserved.
52:50
Platform Id (R)
Contains information concerning the intended platform for the processor.
52
0
0
0
0
1
1
1
1
51
0
0
1
1
0
0
1
1
50
0
1
0
1
0
1
0
1
Processor Flag 0
Processor Flag 1
Processor Flag 2
Processor Flag 3
Processor Flag 4
Processor Flag 5
Processor Flag 6
Processor Flag 7
56:53
L2 Cache Latency Read.
59:57
Reserved.
Vol. 3C 35-319
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Hex
1BH
Register Name
Bit Description
Dec
27
60
Clock Frequency Ratio Read.
63:61
Reserved.
APIC_BASE
Section 10.4.4, “Local APIC Status and Location.”
7:0
Reserved.
8
Boot Strap Processor indicator Bit
1 = BSP
10:9
Reserved.
11
APIC Global Enable Bit - Permanent till reset
1 = Enabled
0 = Disabled
2AH
42
31:12
APIC Base Address.
63:32
Reserved.
EBL_CR_POWERON
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features;
0
(R) indicates current processor configuration.
Reserved.1
1
Data Error Checking Enable (R/W)
1 = Enabled
0 = Disabled
2
Response Error Checking Enable FRCERR Observation Enable (R/W)
1 = Enabled
0 = Disabled
3
AERR# Drive Enable (R/W)
1 = Enabled
0 = Disabled
4
BERR# Enable for Initiator Bus Requests (R/W)
1 = Enabled
0 = Disabled
5
Reserved.
6
BERR# Driver Enable for Initiator Internal Errors (R/W)
1 = Enabled
0 = Disabled
7
BINIT# Driver Enable (R/W)
1 = Enabled
0 = Disabled
8
Output Tri-state Enabled (R)
1 = Enabled
0 = Disabled
35-320 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Hex
Register Name
Bit Description
Dec
9
Execute BIST (R)
1 = Enabled
0 = Disabled
10
AERR# Observation Enabled (R)
1 = Enabled
0 = Disabled
11
Reserved.
12
BINIT# Observation Enabled (R)
1 = Enabled
0 = Disabled
13
In Order Queue Depth (R)
1=1
0=8
14
1-MByte Power on Reset Vector (R)
1 = 1MByte
0 = 4GBytes
15
FRC Mode Enable (R)
1 = Enabled
0 = Disabled
17:16
APIC Cluster ID (R)
19:18
System Bus Frequency (R)
00 = 66MHz
10 = 100Mhz
01 = 133MHz
11 = Reserved
33H
51
21: 20
Symmetric Arbitration ID (R)
25:22
Clock Frequency Ratio (R)
26
Low Power Mode Enable (R/W)
27
Clock Frequency Ratio
63:28
Reserved.1
TEST_CTL
Test Control Register
29:0
Reserved.
30
Streaming Buffer Disable
31
Disable LOCK#
Assertion for split locked access.
79H
121
BIOS_UPDT_TRIG
BIOS Update Trigger Register.
88H
136
BBL_CR_D0[63:0]
Chunk 0 data register D[63:0]: used to write to and read from the L2
89H
137
BBL_CR_D1[63:0]
Chunk 1 data register D[63:0]: used to write to and read from the L2
8AH
138
BBL_CR_D2[63:0]
Chunk 2 data register D[63:0]: used to write to and read from the L2
Vol. 3C 35-321
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Hex
Dec
8BH
139
Register Name
BIOS_SIGN/BBL_CR_D3[63:0]
Bit Description
BIOS Update Signature Register or Chunk 3 data register D[63:0]
Used to write to and read from the L2 depending on the usage model.
C1H
193
PerfCtr0 (PERFCTR0)
C2H
194
PerfCtr1 (PERFCTR1)
FEH
254
MTRRcap
116H 278
BBL_CR_ADDR [63:0]
Address register: used to send specified address (A31-A3) to L2 during
cache initialization accesses.
BBL_CR_ADDR [63:32]
Reserved,
BBL_CR_ADDR [31:3]
Address bits [35:3]
BBL_CR_ADDR [2:0]
Reserved Set to 0.
118H
280
BBL_CR_DECC[63:0]
Data ECC register D[7:0]: used to write ECC and read ECC to/from L2
119H
281
BBL_CR_CTL
Control register: used to program L2 commands to be issued via cache
configuration accesses mechanism. Also receives L2 lookup response
BL_CR_CTL[63:22]
BBL_CR_CTL[21]
Reserved
Processor number2
Disable = 1
Enable = 0
Reserved
BBL_CR_CTL[20:19]
User supplied ECC
BBL_CR_CTL[18]
Reserved
BBL_CR_CTL[17]
L2 Hit
BBL_CR_CTL[16]
Reserved
BBL_CR_CTL[15:14]
State from L2
BBL_CR_CTL[13:12]
Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00
BBL_CR_CTL[11:10]
BBL_CR_CTL[9:8]
BBL_CR_CTL[7]
BBL_CR_CTL[6:5]
BBL_CR_CTL[4:0]
01100
01110
01111
00010
00011
010 + MESI encode
111 + MESI encode
100 + MESI encode
Way from L2
Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11
Way to L2
Reserved
State to L2
L2 Command
Data Read w/ LRU update (RLU)
Tag Read w/ Data Read (TRR)
Tag Inquire (TI)
L2 Control Register Read (CR)
L2 Control Register Write (CW)
Tag Write w/ Data Read (TWR)
Tag Write w/ Data Write (TWW)
Tag Write (TW)
11AH
282
BBL_CR_TRIG
Trigger register: used to initiate a cache configuration accesses access,
Write only with Data = 0.
11BH
283
BBL_CR_BUSY
Busy register: indicates when a cache configuration accesses L2 command
is in progress. D[0] = 1 = BUSY
35-322 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Hex
11EH
Register Name
Bit Description
Dec
286
BBL_CR_CTL3
Control register 3: used to configure the L2 Cache
BBL_CR_CTL3[63:26]
Reserved
BBL_CR_CTL3[25]
Cache bus fraction (read only)
BBL_CR_CTL3[24]
Reserved
BBL_CR_CTL3[23]
L2 Hardware Disable (read only)
BBL_CR_CTL3[22:20]
L2 Physical Address Range support
111
110
101
100
011
010
001
000
64GBytes
32GBytes
16GBytes
8GBytes
4GBytes
2GBytes
1GBytes
512MBytes
BBL_CR_CTL3[19]
Reserved
BBL_CR_CTL3[18]
Cache State error checking enable (read/write)
BBL_CR_CTL3[17:13
Cache size per bank (read/write)
00001
00010
00100
01000
10000
256KBytes
512KBytes
1MByte
2MByte
4MBytes
BBL_CR_CTL3[12:11]
Number of L2 banks (read only)
BBL_CR_CTL3[10:9]
L2 Associativity (read only)
00
01
10
11
Direct Mapped
2 Way
4 Way
Reserved
BBL_CR_CTL3[8]
L2 Enabled (read/write)
BBL_CR_CTL3[7]
CRTN Parity Check Enable (read/write)
BBL_CR_CTL3[6]
Address Parity Check Enable (read/write)
BBL_CR_CTL3[5]
ECC Check Enable (read/write)
BBL_CR_CTL3[4:1]
L2 Cache Latency (read/write)
BBL_CR_CTL3[0]
L2 Configured (read/write
)
174H
372
SYSENTER_CS_MSR
CS register target for CPL 0 code
175H
373
SYSENTER_ESP_MSR
Stack pointer for CPL 0 stack
176H
374
SYSENTER_EIP_MSR
CPL 0 code entry point
179H
377
MCG_CAP
17AH
378
MCG_STATUS
Vol. 3C 35-323
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name
Hex
Dec
17BH
379
MCG_CTL
186H
390
PerfEvtSel0 (EVNTSEL0)
7:0
Bit Description
Event Select
Refer to Performance Counter section for a list of event encodings.
15:8
UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.
16
USER
Controls the counting of events at Privilege levels of 1, 2, and 3.
17
OS
Controls the counting of events at Privilege level of 0.
18
E
Occurrence/Duration Mode Select
1 = Occurrence
0 = Duration
19
PC
Enabled the signaling of performance counter overflow via BP0 pin
20
INT
Enables the signaling of counter overflow via input to APIC
1 = Enable
0 = Disable
22
ENABLE
Enables the counting of performance events in both counters
1 = Enable
0 = Disable
23
INV
Inverts the result of the CMASK condition
1 = Inverted
0 = Non-Inverted
31:24
187H
391
CMASK (Counter Mask).
PerfEvtSel1 (EVNTSEL1)
7:0
Event Select
Refer to Performance Counter section for a list of event encodings.
15:8
UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.
35-324 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Hex
Register Name
Bit Description
Dec
16
USER
Controls the counting of events at Privilege levels of 1, 2, and 3.
17
OS
Controls the counting of events at Privilege level of 0
18
E
Occurrence/Duration Mode Select
1 = Occurrence
0 = Duration
19
PC
Enabled the signaling of performance counter overflow via BP0 pin.
20
INT
Enables the signaling of counter overflow via input to APIC
1 = Enable
0 = Disable
23
INV
Inverts the result of the CMASK condition
1 = Inverted
0 = Non-Inverted
31:24
1D9H
473
CMASK (Counter Mask)
DEBUGCTLMSR
0
Enable/Disable Last Branch Records
1
Branch Trap Flag
2
Performance Monitoring/Break Point Pins
3
Performance Monitoring/Break Point Pins
4
Performance Monitoring/Break Point Pins
5
Performance Monitoring/Break Point Pins
6
Enable/Disable Execution Trace Messages
31:7
Reserved
1DBH
475
LASTBRANCHFROMIP
1DCH
476
LASTBRANCHTOIP
1DDH
477
LASTINTFROMIP
1DEH
478
LASTINTTOIP
1E0H
480
ROB_CR_BKUPTMPDR6
1:0
Reserved
2
Fast String Enable bit. Default is enabled
200H
512
MTRRphysBase0
201H
513
MTRRphysMask0
202H
514
MTRRphysBase1
Vol. 3C 35-325
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name
Hex
Dec
203H
515
MTRRphysMask1
204H
516
MTRRphysBase2
205H
517
MTRRphysMask2
206H
518
MTRRphysBase3
207H
519
MTRRphysMask3
208H
520
MTRRphysBase4
209H
521
MTRRphysMask4
20AH
522
MTRRphysBase5
20BH
523
MTRRphysMask5
20CH
524
MTRRphysBase6
20DH
525
MTRRphysMask6
20EH
526
MTRRphysBase7
20FH
527
MTRRphysMask7
250H
592
MTRRfix64K_00000
258H
600
MTRRfix16K_80000
259H
601
MTRRfix16K_A0000
268H
616
MTRRfix4K_C0000
269H
617
MTRRfix4K_C8000
26AH
618
MTRRfix4K_D0000
26BH
619
MTRRfix4K_D8000
26CH
620
MTRRfix4K_E0000
26DH
621
MTRRfix4K_E8000
26EH
622
MTRRfix4K_F0000
26FH
623
MTRRfix4K_F8000
2FFH
767
MTRRdefType
2:0
Default memory type
10
Fixed MTRR enable
11
MTRR Enable
400H
1024
MC0_CTL
401H
1025
MC0_STATUS
35-326 Vol. 3C
Bit Description
15:0
MC_STATUS_MCACOD
31:16
MC_STATUS_MSCOD
57
MC_STATUS_DAM
58
MC_STATUS_ADDRV
59
MC_STATUS_MISCV
60
MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is hardcoded to 1.)
61
MC_STATUS_UC
MODEL-SPECIFIC REGISTERS (MSRS)
Table 35-46. MSRs in the P6 Family Processors (Contd.)
Register
Address
Hex
Register Name
Bit Description
Dec
62
MC_STATUS_O
63
MC_STATUS_V
402H
1026
MC0_ADDR
403H
1027
MC0_MISC
404H
1028
MC1_CTL
405H
1029
MC1_STATUS
406H
1030
MC1_ADDR
407H
1031
MC1_MISC
408H
1032
MC2_CTL
409H
1033
MC2_STATUS
40AH
1034
MC2_ADDR
40BH
1035
MC2_MISC
40CH
1036
MC4_CTL
40DH
1037
MC4_STATUS
Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are
hardcoded to 1.
40EH
1038
MC4_ADDR
Defined in MCA architecture but not implemented in P6 Family processors.
40FH
1039
MC4_MISC
Defined in MCA architecture but not implemented in the P6 family
processors.
410H
1040
MC3_CTL
411H
1041
MC3_STATUS
412H
1042
MC3_ADDR
413H
1043
MC3_MISC
Defined in MCA architecture but not implemented in the P6 family
processors.
Bit definitions same as MC0_STATUS.
Defined in MCA architecture but not implemented in the P6 family
processors.
Bit definitions same as MC0_STATUS.
Defined in MCA architecture but not implemented in the P6 family
processors.
Bit definitions same as MC0_STATUS.
Defined in MCA architecture but not implemented in the P6 family
processors.
NOTES
1. Bit 0 of this register has been redefined several times, and is no longer used in P6 family processors.
2. The processor number feature may be disabled by setting bit 21 of the BBL_CR_CTL MSR (model-specific register address 119h) to
“1”. Once set, bit 21 of the BBL_CR_CTL may not be cleared. This bit is write-once. The processor number feature will be disabled
until the processor is reset.
3. The Pentium III processor will prevent FSB frequency overclocking with a new shutdown mechanism. If the FSB frequency selected
is greater than the internal FSB frequency the processor will shutdown. If the FSB selected is less than the internal FSB frequency
the BIOS may choose to use bit 11 to implement its own shutdown policy.
35.22
MSRS IN PENTIUM PROCESSORS
The following MSRs are defined for the Pentium processors. The P5_MC_ADDR, P5_MC_TYPE, and TSC MSRs
(named IA32_P5_MC_ADDR, IA32_P5_MC_TYPE, and IA32_TIME_STAMP_COUNTER in the Pentium 4 processor)
are architectural; that is, code that accesses these registers will run on Pentium 4 and P6 family processors without
generating exceptions (see Section 35.1, “Architectural MSRs”). The CESR, CTR0, and CTR1 MSRs are unique to
Vol. 3C 35-327
MODEL-SPECIFIC REGISTERS (MSRS)
Pentium processors; code that accesses these registers will generate exceptions on Pentium 4 and P6 family
processors.
Table 35-47. MSRs in the Pentium Processor
Register
Address
Hex
Dec
0H
0
P5_MC_ADDR
See Section 15.10.2, “Pentium Processor Machine-Check Exception Handling.”
1H
1
P5_MC_TYPE
See Section 15.10.2, “Pentium Processor Machine-Check Exception Handling.”
10H
16
TSC
See Section 17.15, “Time-Stamp Counter.”
11H
17
CESR
See Section 18.24.1, “Control and Event Select Register (CESR).”
12H
18
CTR0
Section 18.24.3, “Events Counted.”
13H
19
CTR1
Section 18.24.3, “Events Counted.”
35.23
Register Name
Bit Description
MSR INDEX
MSRs of recent processors are indexed here for convenience. IA32 MSRs are excluded from this index.
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_ALF_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_ALF_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_ANY_CORE_C0
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_ANY_GFXE_C0
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_B0_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-328 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_B0_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_MASK
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B0_PMON_MATCH
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_MASK
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_B1_PMON_MATCH
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_BBL_CR_CTL
06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_BBL_CR_CTL3
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
Vol. 3C 35-329
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_BPU_CCCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_CCCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_CCCR2
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_CCCR3
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_COUNTER0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_COUNTER1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_COUNTER2
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_COUNTER3
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BPU_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BSU_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_BSU_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_C0_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C0_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C0_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
35-330 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C0_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C0_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C0_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
Vol. 3C 35-331
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C0_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C0_PMON_EVNT_SEL5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C1_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C1_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C1_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C1_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-332 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C1_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C1_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C1_PMON_EVNT_SEL5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C10_PMON_BOX_FILTER
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
MSR_C10_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C10_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C11_PMON_BOX_FILTER
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
MSR_C11_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C11_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C12_PMON_BOX_FILTER
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
MSR_C12_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C12_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C13_PMON_BOX_FILTER
Vol. 3C 35-333
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
MSR_C13_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C13_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C14_PMON_BOX_FILTER
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
MSR_C14_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C14_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_BOX_CTL
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_BOX_FILTER1
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_BOX_STATUS
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_CTR0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_CTR1
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_CTR2
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_CTR3
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_EVNTSEL0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_EVNTSEL1
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_EVNTSEL2
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C15_PMON_EVNTSEL3
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_BOX_CTL
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_BOX_FILTER1
35-334 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_BOX_STATUS
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_CTR0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_CTR3
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_CTR2
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_CTR3
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_EVNTSEL0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_EVNTSEL1
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_EVNTSEL2
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C16_PMON_EVNTSEL3
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_BOX_CTL
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_BOX_FILTER1
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_BOX_STATUS
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_CTR0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_CTR1
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_CTR2
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_CTR3
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_EVNTSEL0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_EVNTSEL1
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_EVNTSEL2
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C17_PMON_EVNTSEL3
Vol. 3C 35-335
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C2_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C2_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C2_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C2_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_EVNT_SEL1
35-336 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C2_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C2_PMON_EVNT_SEL5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C3_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C3_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C3_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
Vol. 3C 35-337
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C3_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C3_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C3_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C3_PMON_EVNT_SEL5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C4_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C4_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-338 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C4_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C4_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C4_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C4_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C4_PMON_EVNT_SEL5
Vol. 3C 35-339
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C5_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C5_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C5_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C5_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C5_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_EVNT_SEL1
35-340 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C5_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C5_PMON_EVNT_SEL5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C6_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C6_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C6_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
Vol. 3C 35-341
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C6_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C6_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C6_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C6_PMON_EVNT_SEL5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C7_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_BOX_FILTER
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
MSR_C7_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-342 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C7_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_CTR4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C7_PMON_CTR5
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C7_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C7_PMON_EVNT_SEL4
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C7_PMON_EVNT_SEL5
Vol. 3C 35-343
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_C8_PMON_BOX_CTRL
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_BOX_FILTER
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
MSR_C8_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_BOX_OVF_CTRL
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C8_PMON_BOX_STATUS
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_CTR0
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_CTR1
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_CTR2
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_CTR3
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_CTR4
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C8_PMON_CTR5
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C8_PMON_EVNT_SEL0
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_EVNT_SEL1
35-344 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_EVNT_SEL2
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_EVNT_SEL3
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C8_PMON_EVNT_SEL4
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C8_PMON_EVNT_SEL5
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C9_PMON_BOX_CTRL
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_BOX_FILTER
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
MSR_C9_PMON_BOX_FILTER0
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_BOX_FILTER1
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_BOX_OVF_CTRL
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C9_PMON_BOX_STATUS
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_CTR0
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_CTR1
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_CTR2
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
Vol. 3C 35-345
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_CTR3
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_CTR4
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C9_PMON_CTR5
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C9_PMON_EVNT_SEL0
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_EVNT_SEL1
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_EVNT_SEL2
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_EVNT_SEL3
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_C9_PMON_EVNT_SEL4
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_C9_PMON_EVNT_SEL5
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
MSR_CC6_DEMOTION_POLICY_CONFIG
06_37H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-9
MSR_CONFIG_TDP_CONTROL
06_3AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_CONFIG_TDP_LEVEL1
06_3AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_CONFIG_TDP_LEVEL2
06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
35-346 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_CONFIG_TDP_NOMINAL
06_3AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_CORE_C1_RESIDENCY
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
MSR_CORE_C3_RESIDENCY
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_CORE_C6_RESIDENCY
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_CORE_C7_RESIDENCY
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_CORE_GFXE_OVERLAP_C0
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_CORE_HDC_RESIDENCY
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_CORE_PERF_LIMIT_REASONS
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_CORE_THREAD_COUNT
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
MSR_CRU_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_CRU_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_CRU_ESCR2
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_CRU_ESCR3
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_CRU_ESCR4
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_CRU_ESCR5
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
Vol. 3C 35-347
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_DAC_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_DAC_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_DRAM_ENERGY_ STATUS
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_DRAM_PERF_STATUS
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_DRAM_POWER_INFO
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_DRAM_POWER_LIMIT
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_EBC_FREQUENCY_ID
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_EBC_HARD_POWERON
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_EBC_SOFT_POWERON
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_EBL_CR_POWERON
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
35-348 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_EFSB_DRDY0
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
MSR_EFSB_DRDY1
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
MSR_EMON_L3_CTR_CTL0
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_CTR_CTL1
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_CTR_CTL2
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_CTR_CTL3
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_CTR_CTL4
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_CTR_CTL5
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_CTR_CTL6
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_CTR_CTL7
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-43
MSR_EMON_L3_GL_CTL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_ERROR_CONTROL
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
MSR_FEATURE_CONFIG
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_25H, 06_2CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-16
06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
Vol. 3C 35-349
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_FIRM_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FIRM_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_CCCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_CCCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_CCCR2
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_CCCR3
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_COUNTER0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_COUNTER1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_COUNTER2
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_COUNTER3
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FLAME_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FSB_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FSB_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_FSB_FREQ
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_4CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-11
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
MSR_GQ_SNOOP_MESF
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_GRAPHICS_PERF_LIMIT_REASONS
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
MSR_IFSB_BUSQ0
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
35-350 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_IFSB_BUSQ1
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
MSR_IFSB_CNTR7
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
MSR_IFSB_CTL6
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
MSR_IFSB_SNPQ0
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
MSR_IFSB_SNPQ1
0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-42
MSR_IQ_CCCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_CCCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_CCCR2
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_CCCR3
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_CCCR4
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_CCCR5
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_COUNTER0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_COUNTER1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_COUNTER2
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_COUNTER3
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_COUNTER4
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_COUNTER5
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IQ_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IS_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IS_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
Vol. 3C 35-351
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_ITLB_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_ITLB_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IX_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_IX_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LASTBRANCH_0_FROM_IP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_0_TO_IP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_1_FROM_IP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_1_TO_IP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
35-352 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_10_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_10_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_11_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_11_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_12_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_12_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_13_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_13_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
Vol. 3C 35-353
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_LASTBRANCH_14_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_14_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_15_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_15_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_16_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_16_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_17_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_17_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_18_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_18_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_19_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_19_TO_IP
35-354 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_2
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LASTBRANCH_2_FROM_IP
06_0FH, 06_17H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_2_TO_IP
06_0FH, 06_17H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_20_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_20_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_21_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_21_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_22_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_22_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_23_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
Vol. 3C 35-355
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_23_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_24_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_24_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_25_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_25_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_26_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_26_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_27_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_27_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_28_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_28_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_29_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_29_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_3
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
35-356 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LASTBRANCH_3_FROM_IP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_3_TO_IP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_30_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_30_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_31_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_31_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LASTBRANCH_4
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LASTBRANCH_4_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_4_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
Vol. 3C 35-357
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_5
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LASTBRANCH_5_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_5_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_6
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LASTBRANCH_6_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_6_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_7
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
35-358 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_LASTBRANCH_7_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_7_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_8_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_8_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_9_FROM_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_9_TO_IP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_LASTBRANCH_TOS
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
Vol. 3C 35-359
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LBR_INFO_1
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_10
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_11
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_13
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_14
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_15
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_16
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_17
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_18
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_19
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_2
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_20
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_21
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_22
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_23
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_24
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_25
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_26
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_27
35-360 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_29
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_3
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_30
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_31
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_4
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_5
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_6
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_7
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_8
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_INFO_9
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_LBR_SELECT
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_LER_FROM_LIP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_LER_TO_LIP
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
Vol. 3C 35-361
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_M0_PMON_ADDR_MASK
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_ADDR_MATCH
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_BOX_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_BOX_OVF_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_BOX_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_CTR0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_CTR1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_CTR2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_CTR3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_CTR4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_CTR5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_DSP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_EVNT_SEL0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_EVNT_SEL1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_EVNT_SEL2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_EVNT_SEL3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_EVNT_SEL4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-362 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_M0_PMON_EVNT_SEL5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_ISS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_MAP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_MM_CONFIG
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_MSC_THR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_PGT
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_PLD
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_TIMESTAMP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M0_PMON_ZDP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_ADDR_MASK
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_ADDR_MATCH
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_BOX_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_BOX_OVF_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_BOX_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_CTR0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_CTR1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_CTR2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_CTR3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_CTR4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_CTR5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_DSP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
Vol. 3C 35-363
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_M1_PMON_EVNT_SEL0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_EVNT_SEL1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_EVNT_SEL2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_EVNT_SEL3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_EVNT_SEL4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_EVNT_SEL5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_ISS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_MAP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_MM_CONFIG
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_MSC_THR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_PGT
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_PLD
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_TIMESTAMP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_M1_PMON_ZDP
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
IA32_MC0_MISC / MSR_MC0_MISC
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
MSR_MC0_RESIDENCY
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
IA32_MC1_MISC / MSR_MC1_MISC
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
IA32_MC10_ADDR / MSR_MC10_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC10_CTL / MSR_MC10_CTL
35-364 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC10_MISC / MSR_MC10_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC10_STATUS / MSR_MC10_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC11_ADDR / MSR_MC11_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC11_CTL / MSR_MC11_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC11_MISC / MSR_MC11_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC11_STATUS / MSR_MC11_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
Vol. 3C 35-365
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC12_ADDR / MSR_MC12_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC12_CTL / MSR_MC12_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC12_MISC / MSR_MC12_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC12_STATUS / MSR_MC12_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC13_ADDR / MSR_MC13_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC13_CTL / MSR_MC13_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC13_MISC / MSR_MC13_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
35-366 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC13_STATUS / MSR_MC13_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC14_ADDR / MSR_MC14_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC14_CTL / MSR_MC14_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC14_MISC / MSR_MC14_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC14_STATUS / MSR_MC14_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC15_ADDR / MSR_MC15_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC15_CTL / MSR_MC15_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
Vol. 3C 35-367
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC15_MISC / MSR_MC15_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC15_STATUS / MSR_MC15_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC16_ADDR / MSR_MC16_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC16_CTL / MSR_MC16_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC16_MISC / MSR_MC16_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC16_STATUS / MSR_MC16_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC17_ADDR / MSR_MC17_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
35-368 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC17_CTL / MSR_MC17_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC17_MISC / MSR_MC17_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC17_STATUS / MSR_MC17_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC18_ADDR / MSR_MC18_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC18_CTL / MSR_MC18_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC18_MISC / MSR_MC18_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
Vol. 3C 35-369
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC18_STATUS / MSR_MC18_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC19_ADDR / MSR_MC19_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC19_CTL / MSR_MC19_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC19_MISC / MSR_MC19_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC19_STATUS / MSR_MC19_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC2_MISC / MSR_MC2_MISC
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
IA32_MC20_ADDR / MSR_MC20_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-370 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC20_CTL / MSR_MC20_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC20_MISC / MSR_MC20_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC20_STATUS / MSR_MC20_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC21_ADDR / MSR_MC21_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC21_CTL / MSR_MC21_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC21_MISC / MSR_MC21_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC21_STATUS / MSR_MC21_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC22_ADDR / MSR_MC22_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC22_CTL / MSR_MC22_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
Vol. 3C 35-371
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
IA32_MC22_MISC / MSR_MC22_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC22_STATUS / MSR_MC22_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC23_ADDR / MSR_MC23_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC23_CTL / MSR_MC23_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC23_MISC / MSR_MC23_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC23_STATUS / MSR_MC23_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC24_ADDR / MSR_MC24_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC24_CTL / MSR_MC24_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC24_MISC / MSR_MC24_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC24_STATUS / MSR_MC24_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC25_ADDR / MSR_MC25_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC25_CTL / MSR_MC25_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC25_MISC / MSR_MC25_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC25_STATUS / MSR_MC25_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC26_ADDR / MSR_MC26_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC26_CTL / MSR_MC26_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC26_MISC / MSR_MC26_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC26_STATUS / MSR_MC26_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC27_ADDR / MSR_MC27_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC27_CTL / MSR_MC27_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC27_MISC / MSR_MC27_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
35-372 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
IA32_MC27_STATUS / MSR_MC27_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC28_ADDR / MSR_MC28_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC28_CTL / MSR_MC28_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC28_MISC / MSR_MC28_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC28_STATUS / MSR_MC28_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
IA32_MC29_ADDR / MSR_MC29_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC29_CTL / MSR_MC29_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC29_MISC / MSR_MC29_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC29_STATUS / MSR_MC29_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC3_ADDR / MSR_MC3_ADDR
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
IA32_MC3_CTL / MSR_MC3_CTL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
IA32_MC3_MISC / MSR_MC3_MISC
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
IA32_MC3_STATUS / MSR_MC3_STATUS
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
Vol. 3C 35-373
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
IA32_MC30_ADDR / MSR_MC30_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC30_CTL / MSR_MC30_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC30_MISC / MSR_MC30_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC30_STATUS / MSR_MC30_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC31_ADDR / MSR_MC31_ADDR
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC31_CTL / MSR_MC31_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC31_MISC / MSR_MC31_MISC
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC31_STATUS / MSR_MC31_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
IA32_MC4_ADDR / MSR_MC4_ADDR
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
IA32_MC4_CTL / MSR_MC4_CTL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
IA32_MC4_CTL2 / MSR_MC4_CTL2
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
IA32_MC4_STATUS / MSR_MC4_STATUS
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
35-374 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_MC5_ADDR / MSR_MC5_ADDR
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
IA32_MC5_CTL / MSR_MC5_CTL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
IA32_MC5_MISC / MSR_MC5_MISC
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
IA32_MC5_STATUS / MSR_MC5_STATUS
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
Vol. 3C 35-375
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
IA32_MC6_ADDR / MSR_MC6_ADDR
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC6_CTL / MSR_MC6_CTL
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
MSR_MC6_DEMOTION_POLICY_CONFIG
06_37H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-9
IA32_MC6_MISC / MSR_MC6_MISC
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
MSR_MC6_RESIDENCY_COUNTER
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_37H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-9
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
IA32_MC6_STATUS / MSR_MC6_STATUS
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC7_ADDR / MSR_MC7_ADDR
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
35-376 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
IA32_MC7_CTL / MSR_MC7_CTL
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC7_MISC / MSR_MC7_MISC
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC7_STATUS / MSR_MC7_STATUS
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC8_ADDR / MSR_MC8_ADDR
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC8_CTL / MSR_MC8_CTL
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC8_MISC / MSR_MC8_MISC
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC8_STATUS / MSR_MC8_STATUS
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
Vol. 3C 35-377
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC9_ADDR / MSR_MC9_ADDR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC9_CTL / MSR_MC9_CTL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC9_MISC / MSR_MC9_MISC
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
IA32_MC9_STATUS / MSR_MC9_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
MSR_MCG_MISC
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R10
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R11
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R12
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R13
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R14
35-378 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R15
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R8
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_R9
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RAX
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RBP
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RBX
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RCX
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RDI
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RDX
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RESERVED1 - MSR_MCG_RESERVED5
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RFLAGS
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RIP
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RSI
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MCG_RSP
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MISC_FEATURE_CONTROL
06_5CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_MISC_PWR_MGMT
06_5CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_MOB_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MOB_ESCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_CCCR0
Vol. 3C 35-379
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_CCCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_CCCR2
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_CCCR3
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_COUNTER0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_COUNTER1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_COUNTER2
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_COUNTER3
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MS_ESCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_MTRRCAP
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_OFFCORE_RSP_0
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_OFFCORE_RSP_1
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-16
06_2FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PCIE_PLL_RATIO
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
MSR_PCU_PMON_BOX_CTL
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_BOX_FILTER
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_BOX_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
35-380 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_CTR0
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_CTR1
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_CTR2
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_CTR3
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_EVNTSEL0
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_EVNTSEL1
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_EVNTSEL2
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PCU_PMON_EVNTSEL3
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PEBS_ENABLE
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-25
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_PEBS_FRONTEND
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-37
MSR_PEBS_LD_LAT
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_PEBS_MATRIX_VERT
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
Vol. 3C 35-381
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_PEBS_NUM_ALT
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
MSR_PERF_CAPABILITIES
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_PERF_FIXED_CTR_CTRL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_PERF_FIXED_CTR0
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_PERF_FIXED_CTR1
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_PERF_FIXED_CTR2
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_PERF_GLOBAL_CTRL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_PERF_GLOBAL_OVF_CTRL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
MSR_PERF_GLOBAL_STATUS
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
MSR_PERF_STATUS
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_PKG_C10_RESIDENCY
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28 and
Table 35-29
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
MSR_PKG_C2_RESIDENCY
06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-5
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKG_C3_RESIDENCY
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKG_C4_RESIDENCY
06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-5
MSR_PKG_C6_RESIDENCY
35-382 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-5
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKG_C7_RESIDENCY
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKG_C8_RESIDENCY
06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-29
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
MSR_PKG_C9_RESIDENCY
06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-29
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
MSR_PKG_CST_CONFIG_CONTROL
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_4CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-11
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-29
06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_3DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-33
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKG_ENERGY_STATUS
06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-8
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_PKG_HDC_CONFIG
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_PKG_HDC_DEEP_RESIDENCY
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_PKG_HDC_SHALLOW_RESIDENCY
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_PKG_PERF_STATUS
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
Vol. 3C 35-383
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKG_POWER_INFO
06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-10
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKG_POWER_LIMIT
06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-8
06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-10
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PKGC_IRTL1
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3CH, 06_45H, 06_46H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
MSR_PKGC_IRTL2
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3CH, 06_45H, 06_46H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
MSR_PKGC3_IRTL
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_PKGC6_IRTL
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_PKGC7_IRTL
06_2AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-19
MSR_PLATFORM_BRV
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_PLATFORM_ENERGY_COUNTER
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_PLATFORM_ID
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-7
06_5CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
MSR_PLATFORM_INFO
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
35-384 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27 and
Table 35-28
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PLATFORM_POWER_LIMIT
06_4EH, 06_5EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_PMG_IO_CAPTURE_BASE
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_4CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-11
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PMH_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_PMH_ESCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_PMON_GLOBAL_CONFIG
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PMON_GLOBAL_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_PMON_GLOBAL_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_POWER_CTL
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
MSR_PP0_ENERGY_STATUS
06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-8
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PP0_POLICY
06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-19
MSR_PP0_POWER_LIMIT
06_4CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-11
Vol. 3C 35-385
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_PP1_ENERGY_STATUS
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-19
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
MSR_PP1_POLICY
06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-19
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
MSR_PP1_POWER_LIMIT
06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-19
06_3CH, 06_45H, 06_46H
See Table 35-28
MSR_PPERF
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_PPIN
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
MSR_PPIN_CTL
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
MSR_R0_PMON_BOX_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_BOX_OVF_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_BOX_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR6
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_CTR7
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-386 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_R0_PMON_EVNT_SEL0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_EVNT_SEL1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_EVNT_SEL2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_EVNT_SEL3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_EVNT_SEL4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_EVNT_SEL5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_EVNT_SEL6
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_EVNT_SEL7
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P6
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_IPERF0_P7
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_QLX_P0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_QLX_P1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_QLX_P2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R0_PMON_QLX_P3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_BOX_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
Vol. 3C 35-387
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_R1_PMON_BOX_OVF_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_BOX_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR10
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR11
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR12
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR13
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR14
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR15
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR8
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_CTR9
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL10
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL11
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL12
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL13
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL14
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL15
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL8
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_EVNT_SEL9
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_IPERF1_P10
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_IPERF1_P11
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_IPERF1_P12
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-388 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_R1_PMON_IPERF1_P13
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_IPERF1_P14
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_IPERF1_P15
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_IPERF1_P8
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_IPERF1_P9
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_QLX_P4
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_QLX_P5
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_QLX_P6
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_R1_PMON_QLX_P7
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_RAPL_POWER_UNIT
06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-8
06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-10
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_RAT_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_RAT_ESCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_RING_PERF_LIMIT_REASONS
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
MSR_S0_PMON_BOX_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_BOX_FILTER
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_BOX_OVF_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S0_PMON_BOX_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S0_PMON_CTR0
Vol. 3C 35-389
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_CTR1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_CTR2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_CTR3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_EVNT_SEL0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_EVNT_SEL1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_EVNT_SEL2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_EVNT_SEL3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S0_PMON_MASK
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S0_PMON_MATCH
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S1_PMON_BOX_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_BOX_FILTER
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_BOX_OVF_CTRL
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S1_PMON_BOX_STATUS
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S1_PMON_CTR0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_CTR1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
35-390 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_S1_PMON_CTR2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_CTR3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_EVNT_SEL0
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_EVNT_SEL1
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_EVNT_SEL2
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_EVNT_SEL3
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S1_PMON_MASK
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S1_PMON_MATCH
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_S2_PMON_BOX_CTL
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_BOX_FILTER
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_CTR0
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_CTR1
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_CTR2
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_CTR3
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_EVNTSEL0
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_EVNTSEL1
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_EVNTSEL2
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S2_PMON_EVNTSEL3
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
Vol. 3C 35-391
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_S3_PMON_BOX_CTL
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_BOX_FILTER
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_CTR0
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_CTR1
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_CTR2
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_CTR3
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_EVNTSEL0
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_EVNTSEL1
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_EVNTSEL2
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_S3_PMON_EVNTSEL3
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_SAAT_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_SAAT_ESCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_SGXOWNER0
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_SGXOWNER1
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_SMI_COUNT
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_SMM_BLOCKED
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
MSR_SMM_DELAYED
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
MSR_SMM_FEATURE_CONTROL
35-392 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
MSR_SMM_MCA_CAP
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_SMRR_PHYSBASE
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_SMRR_PHYSMASK
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
MSR_SSU_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_TBPU_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_TBPU_ESCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_TC_ESCR0
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_TC_ESCR1
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_TC_PRECISE_EVENT
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
MSR_TEMPERATURE_TARGET
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-18
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24
06_56H, 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_THERM2_CTL
06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-4
0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-41
06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-45
MSR_THREAD_ID_INFO
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
MSR_TURBO_ACTIVATION_RATIO
06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-23
Vol. 3C 35-393
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-27
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_TURBO_GROUP_CORECNT
06_5CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
MSR_TURBO_POWER_CURRENT_LIMIT
06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
MSR_TURBO_RATIO_LIMIT
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-6
06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-10
06_5CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-12
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-13
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-16
06_2FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-17
06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-19
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-21
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24 and
Table 35-25
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_3DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-33
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-40
MSR_TURBO_RATIO_LIMIT1
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-24 and
Table 35-25
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-34
MSR_TURBO_RATIO_LIMIT2
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-30
MSR_TURBO_RATIO_LIMIT3
06_56H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-35
06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-36
MSR_U_PMON_BOX_STATUS
06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-26
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_U_PMON_CTR
06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_U_PMON_CTR0
06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
35-394 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_U_PMON_CTR1
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_U_PMON_EVNT_SEL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_U_PMON_EVNTSEL0
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_U_PMON_EVNTSEL1
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_U_PMON_GLOBAL_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_U_PMON_GLOBAL_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_U_PMON_GLOBAL_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_U_PMON_UCLK_FIXED_CTL
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_U_PMON_UCLK_FIXED_CTR
06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-22
06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-31
MSR_U2L_ESCR0
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-41
MSR_U2L_ESCR1
0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Table 35-41
MSR_UNC_ARB_PERFCTR0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_ARB_PERFCTR1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_ARB_PERFEVTSEL0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_ARB_PERFEVTSEL1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
Vol. 3C 35-395
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_0_PERFCTR0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_0_PERFCTR1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_0_PERFCTR2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_0_PERFCTR3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_0_PERFEVTSEL0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H
See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_0_PERFEVTSEL1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_0_PERFEVTSEL2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_0_PERFEVTSEL3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_0_UNIT_STATUS
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_1_PERFCTR0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_1_PERFCTR1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_1_PERFCTR2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_1_PERFCTR3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_1_PERFEVTSEL0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
35-396 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_1_PERFEVTSEL1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_1_PERFEVTSEL2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_1_PERFEVTSEL3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_1_UNIT_STATUS
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_2_PERFCTR0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_2_PERFCTR1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_2_PERFCTR2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_2_PERFCTR3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_2_PERFEVTSEL0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_2_PERFEVTSEL1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_2_PERFEVTSEL2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_2_PERFEVTSEL3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_2_UNIT_STATUS
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_3_PERFCTR0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_3_PERFCTR1
Vol. 3C 35-397
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_3_PERFCTR2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_3_PERFCTR3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_3_PERFEVTSEL0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_3_PERFEVTSEL1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_CBO_3_PERFEVTSEL2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_3_PERFEVTSEL3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_3_UNIT_STATUS
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFCTR0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFCTR1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFCTR2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFCTR3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFEVTSEL0
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFEVTSEL1
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFEVTSEL2
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_PERFEVTSEL3
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_4_UNIT_STATUS
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
MSR_UNC_CBO_CONFIG
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
35-398 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_PERF_FIXED_CTR
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_PERF_FIXED_CTRL
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_PERF_GLOBAL_CTRL
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNC_PERF_GLOBAL_STATUS
06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-20
06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-28
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-38
MSR_UNCORE_ADDR_OPCODE_MATCH
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_FIXED_CTR_CTRL
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_FIXED_CTR0
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERF_GLOBAL_CTRL
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERF_GLOBAL_OVF_CTRL
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERF_GLOBAL_STATUS
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL0
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL1
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL2
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL3
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL4
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL5
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL6
Vol. 3C 35-399
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PERFEVTSEL7
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PMC0
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PMC1
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PMC2
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PMC3
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PMC4
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PMC5
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_UNCORE_PMC6
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PMC7
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-14
MSR_UNCORE_PRMRR_BASE
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_UNCORE_PRMRR_MASK
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MSR_W_PMON_BOX_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_BOX_OVF_CTRL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_BOX_STATUS
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_CTR0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_CTR1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_CTR2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_CTR3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_EVNT_SEL0
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_EVNT_SEL1
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
35-400 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_W_PMON_EVNT_SEL2
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_EVNT_SEL3
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_FIXED_CTR
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_W_PMON_FIXED_CTR_CTL
06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-15
MSR_WEIGHTED_CORE_C0
06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-37
MTRRfix16K_80000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix16K_A0000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_C0000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_C8000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_D0000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_D8000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_E0000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_E8000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_F0000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix4K_F8000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRfix64K_00000
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
Vol. 3C 35-401
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase0
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase1
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase2
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase3
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase4
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase5
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase6
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysBase7
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask0
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask1
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask2
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask3
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask4
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask5
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
35-402 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask6
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
MTRRphysMask7
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
ROB_CR_BKUPTMPDR6
06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-44
P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 35-46
Vol. 3C 35-403
MODEL-SPECIFIC REGISTERS (MSRS)
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INTEL® PROCESSOR TRACE
CHAPTER 36
INTEL® PROCESSOR TRACE
36.1
OVERVIEW
®
Intel Processor Trace (Intel PT) is an extension of Intel® Architecture that captures information about software
execution using dedicated hardware facilities that cause only minimal performance perturbation to the software
being traced. This information is collected in data packets. The initial implementations of Intel PT offer control
flow tracing, which generates a variety of packets to be processed by a software decoder. The packets include
timing, program flow information (e.g. branch targets, branch taken/not taken indications) and program-induced
mode related information (e.g. Intel TSX state transitions, CR3 changes). These packets may be buffered internally
before being sent to the memory subsystem or other output mechanism available in the platform. Debug software
can process the trace data and reconstruct the program flow.
Later generations include additional trace sources, including software trace instrumentation using PTWRITE, and
Power Event tracing.
36.1.1
Features and Capabilities
Intel PT’s control flow trace generates a variety of packets that, when combined with the binaries of a program by
a post-processing tool, can be used to produce an exact execution trace. The packets record flow information such
as instruction pointers (IP), indirect branch targets, and directions of conditional branches within contiguous code
regions (basic blocks).
Intel PT can also be configured to log software-generated packets using PTWRITE, and packets describing
processor power management events.
In addition, the packets record other contextual, timing, and bookkeeping information that enables both functional
and performance debugging of applications. Intel PT has several control and filtering capabilities available to
customize the tracing information collected and to append other processor state and timing information to enable
debugging. For example, there are modes that allow packets to be filtered based on the current privilege level
(CPL) or the value of CR3.
Configuration of the packet generation and filtering capabilities are programmed via a set of MSRs. The MSRs
generally follow the naming convention of IA32_RTIT_*. The capability provided by these configuration MSRs are
enumerated by CPUID, see Section 36.3. Details of the MSRs for configuring Intel PT are described in Section
36.2.7.
36.1.1.1
Packet Summary
After a tracing tool has enabled and configured the appropriate MSRs, the processor will collect and generate trace
information in the following categories of packets (for more details on the packets, see Section 36.4):
•
Packets about basic information on program execution: These include:
— Packet Stream Boundary (PSB) packets: PSB packets act as ‘heartbeats’ that are generated at regular
intervals (e.g., every 4K trace packet bytes). These packets allow the packet decoder to find the packet
boundaries within the output data stream; a PSB packet should be the first packet that a decoder looks for
when beginning to decode a trace.
— Paging Information Packet (PIP): PIPs record modifications made to the CR3 register. This information,
along with information from the operating system on the CR3 value of each process, allows the debugger
to attribute linear addresses to their correct application source.
— Time-Stamp Counter (TSC) packets: TSC packets aid in tracking wall-clock time, and contain some portion
of the software-visible time-stamp counter.
— Core Bus Ratio (CBR) packets: CBR packets contain the core:bus clock ratio.
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INTEL® PROCESSOR TRACE
— Overflow (OVF) packets: OVF packets are sent when the processor experiences an internal buffer overflow,
resulting in packets being dropped. This packet notifies the decoder of the loss and can help the decoder to
respond to this situation.
•
Packets about control flow information:
— Taken Not-Taken (TNT) packets: TNT packets track the “direction” of direct conditional branches (taken or
not taken).
— Target IP (TIP) packets: TIP packets record the target IP of indirect branches, exceptions, interrupts, and
other branches or events. These packets can contain the IP, although that IP value may be compressed by
eliminating upper bytes that match the last IP. There are various types of TIP packets; they are covered in
more detail in Section 36.4.2.2.
— Flow Update Packets (FUP): FUPs provide the source IP addresses for asynchronous events (interrupt and
exceptions), as well as other cases where the source address cannot be determined from the binary.
— MODE packets: These packets provide the decoder with important processor execution information so that
it can properly interpret the dis-assembled binary and trace log. MODE packets have a variety of formats
that indicate details such as the execution mode (16-bit, 32-bit, or 64-bit).
•
Packets inserted by software:
— PTWRITE (PTW) packets: includes the value of the operand passed to the PTWRITE instruction (see
“PTWRITE - Write Data to a Processor Trace Packet” in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B).
•
Packets about processor power management events:
— MWAIT packets: Indicate successful completion of an MWAIT operation to a C-state deeper than C0.0.
— Power State Entry (PWRE) packets: Indicate entry to a C-state deeper than C0.0.
— Power State Exit (PWRX) packets: Indicate exit from a C-state deeper than C0.0, returning to C0.
— Execution Stopped (EXSTOP) packets: Indicate that software execution has stopped, due to events such as
P-state change, C-state change, or thermal throttling.
36.2
INTEL® PROCESSOR TRACE OPERATIONAL MODEL
This section describes the overall Intel Processor Trace mechanism and the essential concepts relevant to how it
operates.
36.2.1
Change of Flow Instruction (COFI) Tracing
A basic program block is a section of code where no jumps or branches occur. The instruction pointers (IPs) in this
block of code need not be traced, as the processor will execute them from start to end without redirecting code
flow. Instructions such as branches, and events such as exceptions or interrupts, can change the program flow.
These instructions and events that change program flow are called Change of Flow Instructions (COFI). There are
three categories of COFI:
•
•
•
Direct transfer COFI.
Indirect transfer COFI.
Far transfer COFI.
The following subsections describe the COFI events that result in trace packet generation. Table 36-1 lists branch
instruction by COFI types. For detailed description of specific instructions, see Intel® 64 and IA-32 Architectures
Software Developer’s Manual.
Table 36-1. COFI Type for Branch Instructions
COFI Type
Conditional Branch
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Instructions
JA, JAE, JB, JBE, JC, JCXZ< JECXZ, JRCXZ, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE,
JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ, LOOP, LOOPE, LOOPNE, LOOPNZ, LOOPZ
INTEL® PROCESSOR TRACE
Table 36-1. COFI Type for Branch Instructions
COFI Type
Unconditional Direct Branch
Instructions
JMP (E9 xx, EB xx), CALL (E8 xx)
Indirect Branch
JMP (FF /4), CALL (FF /2)
Near Ret
RET (C3, C2 xx)
Far Transfers
INT3, INTn, INTO, IRET, IRETD, IRETQ, JMP (EA xx, FF /5), CALL (9A xx, FF /3), RET (CB, CA xx), SYSCALL, SYSRET, SYSENTER, SYSEXIT, VMLAUNCH, VMRESUME
36.2.1.1
Direct Transfer COFI
Direct Transfer COFI are relative branches. This means that their target is an IP whose offset from the current IP is
embedded in the instruction bytes. It is not necessary to indicate target of these instructions in the trace output
since it can be obtained through the source disassembly. Conditional branches need to indicate only whether the
branch is taken or not. Unconditional branches do not need any recording in the trace output. There are two subcategories:
•
Conditional Branch (Jcc, J*CXZ) and LOOP
To track this type of instruction, the processor encodes a single bit (taken or not taken — TNT) to indicate the
program flow after the instruction.
Jcc, J*CXZ, and LOOP can be traced with TNT bits. To improve the trace packet output efficiency, the processor
will compact several TNT bits into a single packet.
•
Unconditional Direct Jumps
There is no trace output required for direct unconditional jumps (like JMP near relative or CALL near relative)
since they can be directly inferred from the application assembly. Direct unconditional jumps do not generate a
TNT bit or a Target IP packet, though TIP.PGD and TIP.PGE packets can be generated by unconditional direct
jumps that toggle Intel PT enables (see Section 36.2.5).
36.2.1.2
Indirect Transfer COFI
Indirect transfer instructions involve updating the IP from a register or memory location. Since the register or
memory contents can vary at any time during execution, there is no way to know the target of the indirect transfer
until the register or memory contents are read. As a result, the disassembled code is not sufficient to determine the
target of this type of COFI. Therefore, tracing hardware must send out the destination IP in the trace packet for
debug software to determine the target address of the COFI. Note that this IP may be a linear or effective address
(see Section 36.3.1.1).
An indirect transfer instruction generates a Target IP Packet (TIP) that contains the target address of the branch.
There are two sub-categories:
•
Near JMP Indirect and Near Call Indirect
As previously mentioned, the target of an indirect COFI resides in the contents of either a register or memory
location. Therefore, the processor must generate a packet that includes this target address to allow the
decoder to determine the program flow.
•
Near RET
When a CALL instruction executes, it pushes onto the stack the address of the next instruction following the
CALL. Upon completion of the call procedure, the RET instruction is often used to pop the return address off of
the call stack and redirect code flow back to the instruction following the CALL.
A RET instruction simply transfers program flow to the address it popped off the stack. Because a called
procedure may change the return address on the stack before executing the RET instruction, debug software
can be misled if it assumes that code flow will return to the instruction following the last CALL. Therefore,
even for near RET, a Target IP Packet may be sent.
— RET Compression
A special case is applied if the target of the RET is consistent with what would be expected from tracking the
CALL stack. If it is assured that the decoder has seen the corresponding CALL (with “corresponding” defined
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INTEL® PROCESSOR TRACE
as the CALL with matching stack depth), and the RET target is the instruction after that CALL, the RET
target may be “compressed”. In this case, only a single TNT bit of “taken” is generated instead of a Target
IP Packet. To ensure that the decoder will not be confused in cases of RET compression, only RETs that
correspond to CALLs which have been seen since the last PSB packet may be compressed in a given logical
processor. For details, see “Indirect Transfer Compression for Returns (RET)” in Section 36.4.2.2.
36.2.1.3
Far Transfer COFI
All operations that change the instruction pointer and are not near jumps are “far transfers”. This includes exceptions, interrupts, traps, TSX aborts, and instructions that do far transfers.
All far transfers will produce a Target IP (TIP) packet, which provides the destination IP address. For those far
transfers that cannot be inferred from the binary source (e.g., asynchronous events such as exceptions and interrupts), the TIP will be preceded by a Flow Update packet (FUP), which provides the source IP address at which the
event was taken. Table 36-23 indicates exactly which IP will be included in the FUP generated by a far transfer.
36.2.2
Software Trace Instrumentation with PTWRITE
PTWRITE provides a mechanism by which software can instrument the Intel PT trace. PTWRITE is a ring3-accessible instruction that can be passed a register or memory variable, see “PTWRITE - Write Data to a Processor Trace
Packet” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B for details. The contents of
that variable will be used as the payload for the PTW packet (see Table 36-40 “PTW Packet Definition”), inserted at
the time of PTWRITE retirement, assuming PTWRITE is enabled and all other filtering conditions are met. Decode
and analysis software will then be able to determine the meaning of the PTWRITE packet based on the IP of the
associated PTWRITE instruction.
PTWRITE is enabled via IA32_RTIT_CTL.PTWEn[12] (see Table 36-6). Optionally, the user can use
IA32_RTIT_CTL.FUPonPTW[5] to enable PTW packets to be followed by FUP packets containing the IP of the associated PTWRITE instruction.
36.2.3
Power Event Tracing
Power Event Trace is a capability that exposes core- and thread-level sleep state and power down transition information. When this capability is enabled, the trace will expose information about:
— Scenarios where software execution stops.
•
•
Due to sleep state entry, frequency change, or other powerdown.
Includes the IP, when in the tracing context.
— The requested and resolved hardware thread C-state.
•
Including indication of hardware autonomous C-state entry.
— The last and deepest core C-state achieved during a sleep session.
— The reason for C-state wake.
This information is in addition to the bus ratio (CBR) information provided by default after any powerdown, and the
timing information (TSC, TMA, MTC, CYC) provided during or after a powerdown state.
Power Event Trace is enabled via IA32_RTIT_CTL.PwrEvtEn[4].
36.2.4
Trace Filtering
Intel Processor Trace provides filtering capabilities, by which the debug/profile tool can control what code is traced.
36.2.4.1
Filtering by Current Privilege Level (CPL)
Intel PT provides the ability to configure a logical processor to generate trace packets only when CPL = 0, when
CPL > 0, or regardless of CPL.
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INTEL® PROCESSOR TRACE
CPL filtering ensures that no IPs or other architectural state information associated with the filtered CPL can be
seen in the log. For example, if the processor is configured to trace only when CPL > 0, and software executes
SYSCALL (changing the CPL to 0), the destination IP of the SYSCALL will be suppressed from the generated packet
(see the discussion of TIP.PGD in Section 36.4.2.5).
It should be noted that CPL is always 0 in real-address mode and that CPL is always 3 in virtual-8086 mode. To
trace code in these modes, filtering should be configured accordingly.
When software is executing in a non-enabled CPL, ContextEn is cleared. See Section 36.2.5.1 for details.
36.2.4.2
Filtering by CR3
Intel PT supports a CR3-filtering mechanism by which the generation of packets containing architectural states can
be enabled or disabled based on the value of CR3. A debugger can use CR3 filtering to trace only a single application without context switching the state of the RTIT MSRs. For the reconstruction of traces from software with
multiple threads, debug software may wish to context-switch for the state of the RTIT MSRs (if the operating
system does not provide context-switch support) to separate the output for the different threads (see Section
36.3.5, “Context Switch Consideration”).
To trace for only a single CR3 value, software can write that value to the IA32_RTIT_CR3_MATCH MSR, and set
IA32_RTIT_CTL.CR3Filter. When CR3 value does not match IA32_RTIT_CR3_MATCH and IA32_RTIT_CTL.CR3Filter
is 1, ContextEn is forced to 0, and packets containing architectural states will not be generated. Some other
packets can be generated when ContextEn is 0; see Section 36.2.5.3 for details. When CR3 does match
IA32_RTIT_CR3_MATCH (or when IA32_RTIT_CTL.CR3Filter is 0), CR3 filtering does not force ContextEn to 0
(although it could be 0 due to other filters or modes).
CR3 matches IA32_RTIT_CR3_MATCH if the two registers are identical for bits 63:12, or 63:5 when in PAE paging
mode; the lower 5 bits of CR3 and IA32_RTIT_CR3_MATCH are ignored. CR3 filtering is independent of the value
of CR0.PG.
When CR3 filtering is in use, PIP packets may still be seen in the log if the processor is configured to trace when
CPL = 0 (IA32_RTIT_CTL.OS = 1). If not, no PIP packets will be seen.
36.2.4.3
Filtering by IP
Trace packet generation with configurable filtering by IP is supported if CPUID.(EAX=14H, ECX=0):EBX[bit 2] = 1.
Intel PT can be configured to enable the generation of packets containing architectural states only when the
processor is executing code within certain IP ranges. If the IP is outside of these ranges, generation of some
packets is blocked.
IP filtering is enabled using the ADDRn_CFG fields in the IA32_RTIT_CTL MSR (Section 36.2.7.2), where the digit
'n' is a zero-based number that selects which address range is being configured. Each ADDRn_CFG field configures
the use of the register pair IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B (Section 36.2.7.5).
IA32_RTIT_ADDRn_A defines the base and IA32_RTIT_ADDRn_B specifies the limit of the range in which tracing is
enabled. Thus each range, referred to as the ADDRn range, is defined by [IA32_RTIT_ADDRn_A.
IA32_RTIT_ADDRn_B]. There can be multiple such ranges, software can query CPUID (Section 36.3.1) for the
number of ranges supported on a processor.
Default behavior (ADDRn_CFG=0) defines no IP filter range, meaning FilterEn is always set. In this case code at
any IP can be traced, though other filters, such as CR3 or CPL, could limit tracing. When ADDRn_CFG is set to
enable IP filtering (see Section 36.3.1), tracing will commence when a taken branch or event is seen whose target
address is in the ADDRn range.
While inside a tracing region and with FilterEn is set, leaving the tracing region may only be detected once a taken
branch or event with a target outside the range is retired. If an ADDRn range is entered or exited by executing the
next sequential instruction, rather than by a control flow transfer, FilterEn may not toggle immediately. See Section
36.2.5.5 for more details on FilterEn.
Note that these address range base and limit values are inclusive, such that the range includes the first and last
instruction whose first instruction byte is in the ADDRn range.
Depending upon processor implementation, IP filtering may be based on linear or effective address. This can cause
different behavior between implementations if CSbase is not equal to zero or in real mode. See Section 36.3.1.1
for details. Software can query CPUID to determine filters are based on linear or effective address (Section 36.3.1).
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INTEL® PROCESSOR TRACE
Note that some packets, such as MTC (Section 36.3.7) and other timing packets, do not depend on FilterEn. For
details on which packets depend on FilterEn, and hence are impacted by IP filtering, see Section 36.4.1.
TraceStop
The ADDRn ranges can also be configured to cause tracing to be disabled upon entry to the specified region. This is
intended for cases where unexpected code is executed, and the user wishes to immediately stop generating
packets in order to avoid overwriting previously written packets.
The TraceStop mechanism works much the same way that IP filtering does, and uses the same address comparison
logic. The TraceStop region base and limit values are programmed into one or more ADDRn ranges, but
IA32_RTIT_CTL.ADDRn_CFG is configured with the TraceStop encoding. Like FilterEn, TraceStop is detected when
a taken branch or event lands in a TraceStop region.
Further, TraceStop requires that TriggerEn=1 at the beginning of the branch/event, and ContextEn=1 upon
completion of the branch/event. When this happens, the CPU will set IA32_RTIT_STATUS.Stopped, thereby
clearing TriggerEn and hence disabling packet generation. This may generate a TIP.PGD packet with the target IP
of the branch or event that entered the TraceStop region. Finally, a TraceStop packet will be inserted, to indicate
that the condition was hit.
If a TraceStop condition is encountered during buffer overflow (Section 36.3.8), it will not be dropped, but will
instead be signaled once the overflow has resolved.
Note that a TraceStop event does not guarantee that all internally buffered packets are flushed out of internal
buffers. To ensure that this has occurred, the user should clear TraceEn.
To resume tracing after a TraceStop event, the user must first disable Intel PT by clearing IA32_RTIT_CTL.TraceEn
before the IA32_RTIT_STATUS.Stopped bit can be cleared. At this point Intel PT can be reconfigured, and tracing
resumed.
Note that the IA32_RTIT_STATUS.Stopped bit can also be set using the ToPA STOP bit. See Section 36.2.6.2.
IP Filtering Example
The following table gives an example of IP filtering behavior. Assume that IA32_RTIT_ADDRn_A = the IP of RangeBase, and that IA32_RTIT_ADDRn_B = the IP of RangeLimit, while IA32_RTIT_CTL.ADDRn_CFG = 0x1 (enable
ADDRn range as a FilterEn range).
Table 36-2. IP Filtering Packet Example
Code Flow
Bar:
jmp RangeBase // jump into filter range
RangeBase:
jcc Foo // not taken
add eax, 1
Foo:
jmp RangeLimit+1 // jump out of filter range
RangeLimit:
nop
jcc Bar
Packets
TIP.PGE(RangeBase)
TNT(0)
TIP.PGD(RangeLimit+1)
IP Filtering and TraceStop
It is possible for the user to configure IP filter range(s) and TraceStop range(s) that overlap. In this case, code
executing in the non-overlapping portion of either range will behave as would be expected from that range. Code
executing in the overlapping range will get TraceStop behavior.
36.2.5
Packet Generation Enable Controls
Intel Processor Trace includes a variety of controls that determine whether a packet is generated. In general, most
packets are sent only if Packet Enable (PacketEn) is set. PacketEn is an internal state maintained in hardware in
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INTEL® PROCESSOR TRACE
response to software configurable enable controls, PacketEn is not visible to software directly. The relationship of
PacketEn to the software-visible controls in the configuration MSRs is described in this section.
36.2.5.1
Packet Enable (PacketEn)
When PacketEn is set, the processor is in the mode that Intel PT is monitoring and all packets can be generated to
log what is being executed. PacketEn is composed of other states according to this relationship:
PacketEn TriggerEn AND ContextEn AND FilterEn AND BranchEn
These constituent controls are detailed in the following subsections.
PacketEn ultimately determines when the processor is tracing. When PacketEn is set, all control flow packets are
enabled. When PacketEn is clear, no control flow packets are generated, though other packets (timing and bookkeeping packets) may still be sent. See Section 36.2.6 for details of PacketEn and packet generation.
Note that, on processors that do not support IP filtering (i.e., CPUID.(EAX=14H,
ECX=0):EBX.IPFILT_WRSTPRSV[bit 2] = 0), FilterEn is treated as always set.
36.2.5.2
Trigger Enable (TriggerEn)
Trigger Enable (TriggerEn) is the primary indicator that trace packet generation is active. TriggerEn is set when
IA32_RTIT_CTL.TraceEn is set, and cleared by any of the following conditions:
•
•
•
TraceEn is cleared by software.
A TraceStop condition is encountered and IA32_RTIT_STATUS.Stopped is set.
IA32_RTIT_STATUS.Error is set due to an operational error (see Section 36.3.9).
Software can discover the current TriggerEn value by reading the IA32_RTIT_STATUS.TriggerEn bit. When TriggerEn is clear, tracing is inactive and no packets are generated.
36.2.5.3
Context Enable (ContextEn)
Context Enable (ContextEn) indicates whether the processor is in the state or mode that software configured
hardware to trace. For example, if execution with CPL = 0 code is not being traced (IA32_RTIT_CTL.OS = 0), then
ContextEn will be 0 when the processor is in CPL0.
Software can discover the current ContextEn value by reading the IA32_RTIT_STATUS.ContextEn bit. ContextEn is
defined as follows:
ContextEn = !((IA32_RTIT_CTL.OS = 0 AND CPL = 0) OR
(IA32_RTIT_CTL.USER = 0 AND CPL > 0) OR (IS_IN_A_PRODUCTION_ENCLAVE1) OR
(IA32_RTIT_CTL.CR3Filter = 1 AND IA32_RTIT_CR3_MATCH does not match CR3)
If the clearing of ContextEn causes PacketEn to be cleared, a Packet Generation Disable (TIP.PGD) packet is generated, but its IP payload is suppressed. If the setting of ContextEn causes PacketEn to be set, a Packet Generation
Enable (TIP.PGE) packet is generated.
When ContextEn is 0, control flow packets (TNT, FUP, TIP.*, MODE.*) are not generated, and no Linear Instruction
Pointers (LIPs) are exposed. However, some packets, such as MTC and PSB (see Section 36.4.2.16 and Section
36.4.2.17), may still be generated while ContextEn is 0. For details of which packets are generated only when
ContextEn is set, see Section 36.4.1.
The processor does not update ContextEn when TriggerEn = 0.
The value of ContextEn will toggle only when TriggerEn = 1.
36.2.5.4
Branch Enable (BranchEn)
This value is based purely on the IA32_RTIT_CTL.BranchEn value. If BranchEn is not set, then relevant COFI
packets (TNT, TIP*, FUP, MODE.*) are suppressed. Other packets related to timing (TSC, TMA, MTC, CYC), as well
1. Trace packets generation is disabled in a production enclave, see Section 36.2.8.3. See Intel® Software Guard
Extensions Programming Reference about differences between a production enclave and a debug enclave.
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INTEL® PROCESSOR TRACE
as PSB, will be generated normally regardless. Further, PIP and VMCS continue to be generated, as indicators of
what software is running.
36.2.5.5
Filter Enable (FilterEn)
Filter Enable indicates that the Instruction Pointer (IP) is within the range of IPs that Intel PT is configured to watch.
Software can get the state of Filter Enable by a RDMSR of IA32_RTIT_STATUS.FilterEn. For details on configuration
and use of IP filtering, see Section 36.2.4.3.
On clearing of FilterEn that also clears PacketEn, a Packet Generation Disable (TIP.PGD) will be generated, but
unlike the ContextEn case, the IP payload may not be suppressed. For direct, unconditional branches, as well as for
indirect branches (including RETs), the PGD generated by leaving the tracing region and clearing FilterEn will
contain the target IP. This means that IPs from outside the configured range can be exposed in the trace, as long
as they are within context.
When FilterEn is 0, control flow packets are not generated (e.g., TNT, TIP). However, some packets, such as PIP,
MTC, and PSB, may still be generated while FilterEn is clear. For details on packet enable dependencies, see Section
36.4.1.
After TraceEn is set, FilterEn is set to 1 at all times if there is no IP filter range configured by software
(IA32_RTIT_CTL.ADDRn_CFG != 1, for all n), or if the processor does not support IP filtering (i.e.,
CPUID.(EAX=14H, ECX=0):EBX.IPFILT_WRSTPRSV[bit 2] = 0). FilterEn will toggle only when TraceEn=1 and
ContextEn=1, and when at least one range is configured for IP filtering.
36.2.6
Trace Output
Intel PT output should be viewed independently from trace content and filtering mechanisms. The options available
for trace output can vary across processor generations and platforms.
Trace output is written out using one of the following output schemes, as configured by the ToPA and FabricEn bit
fields of IA32_RTIT_CTL (see Section 36.2.7.2):
•
•
A single, contiguous region of physical address space.
•
A platform-specific trace transport subsystem.
A collection of variable-sized regions of physical memory. These regions are linked together by tables of
pointers to those regions, referred to as Table of Physical Addresses (ToPA). The trace output stores bypass
the caches and the TLBs, but are not serializing. This is intended to minimize the performance impact of the
output.
Regardless of the output scheme chosen, Intel PT stores bypass the processor caches by default. This ensures that
they don't consume precious cache space, but they do not have the serializing aspects associated with un-cacheable (UC) stores. Software should avoid using MTRRs to mark any portion of the Intel PT output region as UC, as
this may override the behavior described above and force Intel PT stores to UC, thereby incurring severe performance impact.
There is no guarantee that a packet will be written to memory or other trace endpoint after some fixed number of
cycles after a packet-producing instruction executes. The only way to assure that all packets generated have
reached their endpoint is to clear TraceEn and follow that with a store, fence, or serializing instruction; doing so
ensures that all buffered packets are flushed out of the processor.
36.2.6.1
Single Range Output
When IA32_RTIT_CTL.ToPA and IA32_RTIT_CTL.FabricEn bits are clear, trace packet output is sent to a single,
contiguous memory (or MMIO if DRAM is not available) range defined by a base address in
IA32_RTIT_OUTPUT_BASE (Section 36.2.7.7) and mask value in IA32_RTIT_OUTPUT_MASK_PTRS (Section
36.2.7.8). The current write pointer in this range is also stored in IA32_RTIT_OUTPUT_MASK_PTRS. This output
range is circular, meaning that when the writes wrap around the end of the buffer they begin again at the base
address.
This output method is best suited for cases where Intel PT output is either:
•
Configured to be directed to a sufficiently large contiguous region of DRAM.
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INTEL® PROCESSOR TRACE
•
Configured to go to an MMIO debug port, in order to route Intel PT output to a platform-specific trace endpoint
(e.g., JTAG). In this scenario, a specific range of addresses is written in a circular manner, and SoC will
intercept these writes and direct them to the proper device. Repeated writes to the same address do not
overwrite each other, but are accumulated by the debugger, and hence no data is lost by the circular nature of
the buffer.
The processor will determine the address to which to write the next trace packet output byte as follows:
OutputBase[63:0] IA32_RTIT_OUTPUT_BASE[63:0]
OutputMask[63:0] ZeroExtend64(IA32_RTIT_OUTPUT_MASK_PTRS[31:0])
OutputOffset[63:0] ZeroExtend64(IA32_RTIT_OUTPUT_MASK_PTRS[63:32])
trace_store_phys_addr (OutputBase & ~OutputMask) + (OutputOffset & OutputMask)
Single-Range Output Errors
If the output base and mask are not properly configured by software, an operational error (see Section 36.3.9) will
be signaled, and tracing disabled. Error scenarios with single-range output are:
•
Mask value is non-contiguous.
IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTablePointer value has a 0 in a less significant bit position than the
most significant bit containing a 1.
•
Base address and Mask are mis-aligned, and have overlapping bits set.
IA32_RTIT_OUTPUT_BASE && IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset > 0.
•
Illegal Output Offset
IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset
is
(IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset).
greater
than
the
mask
value
Also note that errors can be signaled due to trace packet output overlapping with restricted memory, see Section
36.2.6.4.
36.2.6.2
Table of Physical Addresses (ToPA)
When IA32_RTIT_CTL.ToPA is set and IA32_RTIT_CTL.FabricEn is clear, the ToPA output mechanism is utilized. The
ToPA mechanism uses a linked list of tables; see Figure 36-1 for an illustrative example. Each entry in the table
contains some attribute bits, a pointer to an output region, and the size of the region. The last entry in the table
may hold a pointer to the next table. This pointer can either point to the top of the current table (for circular array)
or to the base of another table. The table size is not fixed, since the link to the next table can exist at any entry.
The processor treats the various output regions referenced by the ToPA table(s) as a unified buffer. This means that
a single packet may span the boundary between one output region and the next.
The ToPA mechanism is controlled by three values maintained by the processor:
•
proc_trace_table_base.
This is the physical address of the base of the current ToPA table. When tracing is enabled, the processor loads
this value from the IA32_RTIT_OUTPUT_BASE MSR. While tracing is enabled, the processor updates the
IA32_RTIT_OUTPUT_BASE MSR with changes to proc_trace_table_base, but these updates may not be
synchronous to software execution. When tracing is disabled, the processor ensures that the MSR contains the
latest value of proc_trace_table_base.
•
proc_trace_table_offset.
This indicates the entry of the current table that is currently in use. (This entry contains the address of the
current output region.) When tracing is enabled, the processor loads this value from bits 31:7 (MaskOrTableOffset) of the IA32_RTIT_OUTPUT_MASK_PTRS. While tracing is enabled, the processor updates
IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset with changes to proc_trace_table_offset, but these
updates may not be synchronous to software execution. When tracing is disabled, the processor ensures that
the MSR contains the latest value of proc_trace_table_offset.
•
proc_trace_output_offset.
This a pointer into the current output region and indicates the location of the next write. When tracing is
enabled, the processor loads this value from bits 63:32 (OutputOffset) of the
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INTEL® PROCESSOR TRACE
IA32_RTIT_OUTPUT_MASK_PTRS. While tracing is enabled, the processor updates
IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset with changes to proc_trace_output_offset, but these updates
may not be synchronous to software execution. When tracing is disabled, the processor ensures that the MSR
contains the latest value of proc_trace_output_offset.
Figure 36-1 provides an illustration (not to scale) of the table and associated pointers.
0FF_FFFF _FFFFH
Physical Memory
proc_trace_output_offset: IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset
OutputRegionX
END=1
4K
TableBaseB
OutputBaseY
64K
OutputBaseX
proc_trace_table_offset: IA32_RTIT_OUTPUT_MASK_PTRS.TableOffset
ToPA Table A
proc_trace_table_base: IA32_RTIT_OUTPUT_BASE
OutputRegionY
STOP=1
ToPA Table B
0
Figure 36-1. ToPA Memory Illustration
With the ToPA mechanism, the processor writes packets to the current output region (identified by
proc_trace_table_base and the proc_trace_table_offset). The offset within that region to which the next byte will
be written is identified by proc_trace_output_offset. When that region is filled with packet output (thus
proc_trace_output_offset = RegionSize–1), proc_trace_table_offset is moved to the next ToPA entry,
proc_trace_output_offset is set to 0, and packet writes begin filling the new output region specified by
proc_trace_table_offset.
As packets are written out, each store derives its physical address as follows:
trace_store_phys_addr Base address from current ToPA table entry +
proc_trace_output_offset
Eventually, the regions represented by all entries in the table may become full, and the final entry of the table is
reached. An entry can be identified as the final entry because it has either the END or STOP attribute. The END
attribute indicates that the address in the entry does not point to another output region, but rather to another ToPA
table. The STOP attribute indicates that tracing will be disabled once the corresponding region is filled. See Section
36.2.6.2 for details on STOP.
When an END entry is reached, the processor loads proc_trace_table_base with the base address held in this END
entry, thereby moving the current table pointer to this new table. The proc_trace_table_offset is reset to 0, as is
the proc_trace_output_offset, and packet writes will resume at the base address indicated in the first entry.
If the table has no STOP or END entry, and trace-packet generation remains enabled, eventually the maximum
table size will be reached (proc_trace_table_offset = FFFFFFFFH). In this case, the proc_trace_table_offset and
proc_trace_output_offset are reset to 0 (wrapping back to the beginning of the current table) once the last output
region is filled.
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It is important to note that processor updates to the IA32_RTIT_OUTPUT_BASE and
IA32_RTIT_OUTPUT_MASK_PTRS MSRs are asynchronous to instruction execution. Thus, reads of these MSRs
while Intel PT is enabled may return stale values. Like all IA32_RTIT_* MSRs, the values of these MSRs should not
be trusted or saved unless trace packet generation is first disabled by clearing IA32_RTIT_CTL.TraceEn. This
ensures that he output MSR values account for all packets generated to that point, after which the output MSR
values will be frozen until tracing resumes. 1
The processor may cache internally any number of entries from the current table or from tables that it references
(directly or indirectly). If tracing is enabled, the processor may ignore or delay detection of modifications to these
tables. To ensure that table changes are detected by the processor in a predictable manner, software should clear
TraceEn before modifying the current table (or tables that it references) and only then re-enable packet generation.
Single Output Region ToPA Implementation
The first processor generation to implement Intel PT supports only ToPA configurations with a single ToPA entry
followed by an END entry that points back to the first entry (creating one circular output buffer). Such processors
enumerate CPUID.(EAX=14H,ECX=0):ECX.MENTRY[bit 1] = 0 and CPUID.(EAX=14H,ECX=0):ECX.TOPAOUT[bit
0] = 1.
If CPUID.(EAX=14H,ECX=0):ECX.MENTRY[bit 1] = 0, ToPA tables can hold only one output entry, which must be
followed by an END=1 entry which points back to the base of the table. Hence only one contiguous block can be
used as output.
The lone output entry can have INT or STOP set, but nonetheless must be followed by an END entry as described
above. Note that, if INT=1, the PMI will actually be delivered before the region is filled.
ToPA Table Entry Format
The format of ToPA table entries is shown in Figure 36-2. The size of the address field is determined by the
processor’s physical-address width (MAXPHYADDR) in bits, as reported in CPUID.80000008H:EAX[7:0].
63
12 11 10 9
MAXPHYADDR–1
6 5
4
3
2 1 0
Output Region Base Physical Address
9:6 Size
4 : STOP
2 : INT
0 : END
Reserved
Figure 36-2. Layout of ToPA Table Entry
Table 36-3 describes the details of the ToPA table entry fields. If reserved bits are set to 1, an error is signaled.
Table 36-3. ToPA Table Entry Fields
ToPA Entry Field
Output Region
Base Physical
Address
Description
If END=0, this is the base physical address of the output region specified by this entry. Note that all regions
must be aligned based on their size. Thus a 2M region must have bits 20:12 clear. If the region is not properly
aligned, an operational error will be signaled when the entry is reached.
If END=1, this is the 4K-aligned base physical address of the next ToPA table (which may be the base of the current table, or the first table in the linked list if a circular buffer is desired). If the processor supports only a single
ToPA output region (see above), this address must be the value currently in the IA32_RTIT_OUTPUT_BASE
MSR.
1. Although WRMSR is a serializing instruction, the execution of WRMSR that forces packet writes by clearing TraceEn does not itself
cause these writes to be globally observed.
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INTEL® PROCESSOR TRACE
Table 36-3. ToPA Table Entry Fields (Contd.)
ToPA Entry Field
Description
Size
Indicates the size of the associated output region. Encodings are:
0: 4K, 1: 8K,
2: 16K,
3: 32K,
4: 64K,
5: 128K,
6: 256K,
8: 1M, 9: 2M,
10: 4M,
11: 8M,
12: 16M, 13: 32M, 14: 64M,
This field is ignored if END=1.
STOP
When the output region indicated by this entry is filled, software should disable packet generation. This will be
accomplished by setting IA32_RTIT_STATUS.Stopped, which clears TriggerEn. This bit must be 0 if END=1; otherwise it is treated as reserved bit violation (see ToPA Errors).
INT
When the output region indicated by this entry is filled, signal Perfmon LVT interrupt.
Note that if both INT and STOP are set in the same entry, the STOP will happen before the INT. Thus the interrupt handler should expect that the IA32_RTIT_STATUS.Stopped bit will be set, and will need to be reset before
tracing can be resumed.
This bit must be 0 if END=1; otherwise it is treated as reserved bit violation (see ToPA Errors).
END
If set, indicates that this is an END entry, and thus the address field points to a table base rather than an output
region base.
If END=1, INT and STOP must be set to 0; otherwise it is treated as reserved bit violation (see ToPA Errors). The
Size field is ignored in this case.
If the processor supports only a single ToPA output region (see above), END must be set in the second table
entry.
7: 512K,
15: 128M
ToPA STOP
Each ToPA entry has a STOP bit. If this bit is set, the processor will set the IA32_RTIT_STATUS.Stopped bit when
the corresponding trace output region is filled. This will clear TriggerEn and thereby cease packet generation. See
Section 36.2.7.4 for details on IA32_RTIT_STATUS.Stopped. This sequence is known as “ToPA Stop”.
No TIP.PGD packet will be seen in the output when the ToPA stop occurs, since the disable happens only when the
region is already full. When this occurs, output ceases after the last byte of the region is filled, which may mean
that a packet is cut off in the middle. Any packets remaining in internal buffers are lost and cannot be recovered.
When ToPA stop occurs, the IA32_RTIT_OUTPUT_BASE MSR will hold the base address of the table whose entry
had STOP=1. IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset will hold the index value for that entry, and the
IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset should be set to the size of the region.
Note that this means the offset pointer is pointing to the next byte after the end of the region, a configuration that
would produce an operational error if the configuration remained when tracing is re-enabled with
IA32_RTIT_STATUS.Stopped cleared.
ToPA PMI
Each ToPA entry has an INT bit. If this bit is set, the processor will signal a performance-monitoring interrupt (PMI)
when the corresponding trace output region is filled. This interrupt is not precise, and it is thus likely that writes to
the next region will occur by the time the interrupt is taken.
The following steps should be taken to configure this interrupt:
1. Enable PMI via the LVT Performance Monitor register (at MMIO offset 340H in xAPIC mode; via MSR 834H in
x2APIC mode). See Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B for more
details on this register. For ToPA PMI, set all fields to 0, save for the interrupt vector, which can be selected by
software.
2. Set up an interrupt handler to service the interrupt vector that a ToPA PMI can raise.
3. Set the interrupt flag by executing STI.
4. Set the INT bit in the ToPA entry of interest and enable packet generation, using the ToPA output option. Thus,
TraceEn=ToPA=1 in the IA32_RTIT_CTL MSR.
Once the INT region has been filled with packet output data, the interrupt will be signaled. This PMI can be distinguished from others by checking bit 55 (Trace_ToPA_PMI) of the IA32_PERF_GLOBAL_STATUS MSR (MSR 38EH).
Once the ToPA PMI handler has serviced the relevant buffer, writing 1 to bit 55 of the MSR at 390H
(IA32_GLOBAL_STATUS_RESET) clears IA32_PERF_GLOBAL_STATUS.Trace_ToPA_PMI.
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INTEL® PROCESSOR TRACE
Intel PT is not frozen on PMI, and thus the interrupt handler will be traced (though filtering can prevent this). The
Freeze_Perfmon_on_PMI and Freeze_LBRs_on_PMI settings in IA32_DEBUGCTL will be applied on ToPA PMI just as
on other PMIs, and hence Perfmon counters are frozen.
Assuming the PMI handler wishes to read any buffered packets for persistent output, or wishes to modify any Intel
PT MSRs, software should first disable packet generation by clearing TraceEn. This ensures that all buffered packets
are written to memory and avoids tracing of the PMI handler. The configuration MSRs can then be used to determine where tracing has stopped. If packet generation is disabled by the handler, it should then be manually reenabled before the IRET if continued tracing is desired.
In rare cases, it may be possible to trigger a second ToPA PMI before the first is handled. This can happen if another
ToPA region with INT=1 is filled before, or shortly after, the first PMI is taken, perhaps due to EFLAGS.IF being
cleared for an extended period of time. This can manifest in two ways: either the second PMI is triggered before the
first is taken, and hence only one PMI is taken, or the second is triggered after the first is taken, and thus will be
taken when the handler for the first completes. Software can minimize the likelihood of the second case by clearing
TraceEn at the beginning of the PMI handler. Further, it can detect such cases by then checking the Interrupt
Request Register (IRR) for PMI pending, and checking the ToPA table base and off-set pointers (in
IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS) to see if multiple entries with INT=1 have been
filled.
ToPA PMI and Single Output Region ToPA Implementation
A processor that supports only a single ToPA output region implementation (such that only one output region is
supported; see above) will attempt to signal a ToPA PMI interrupt before the output wraps and overwrites the top
of the buffer. To support this functionality, the PMI handler should disable packet generation as soon as possible.
Due to PMI skid, it is possible that, in rare cases, the wrap will have occurred before the PMI is delivered. Software
can avoid this by setting the STOP bit in the ToPA entry (see Table 36-3); this will disable tracing once the region is
filled, and no wrap will occur. This approach has the downside of disabling packet generation so that some of the
instructions that led up to the PMI will not be traced. If the PMI skid is significant enough to cause the region to fill
and tracing to be disabled, the PMI handler will need to clear the IA32_RTIT_STATUS.Stopped indication before
tracing can resume.
ToPA PMI and XSAVES/XRSTORS State Handling
In some cases the ToPA PMI may be taken after completion of an XSAVES instruction that switches Intel PT state,
and in such cases any modification of Intel PT MSRs within the PMI handler will not persist when the saved Intel PT
context is later restored with XRSTORS. To account for such a scenario, it is recommended that the Intel PT output
configuration be modified by altering the ToPA tables themselves, rather than the Intel PT output MSRs.
Table 36-4 depicts a recommended PMI handler algorithm for managing multi-region ToPA output and handling
ToPA PMIs that may arrive between XSAVES and XRSTORS. This algorithm is flexible to allow software to choose
between adding entries to the current ToPA table, adding a new ToPA table, or using the current ToPA table as a
circular buffer. It assumes that the ToPA entry that triggers the PMI is not the last entry in the table, which is the
recommended treatment.
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Table 36-4. Algorithm to Manage Intel PT ToPA PMI and XSAVES/XRSTORS
Pseudo Code Flow
IF (IA32_PERF_GLOBAL_STATUS.ToPA)
Save IA32_RTIT_CTL value;
IF ( IA32_RTIT_CTL.TraceEN )
Disable Intel PT by clearing TraceEn;
FI;
IF ( there is space available to grow the current ToPA table )
Add one or more ToPA entries after the last entry in the ToPA table;
Point new ToPA entry address field(s) to new output region base(s);
ELSE
Modify an upcoming ToPA entry in the current table to have END=1;
IF (output should transition to a new ToPA table )
Point the address of the “END=1” entry of the current table to the new table base;
ELSE
/* Continue to use the current ToPA table, make a circular. */
Point the address of the “END=1”l entry to the base of the current table;
Modify the ToPA entry address fields for filled output regions to point to new, unused output regions;
/* Filled regions are those with index in the range of 0 to (IA32_RTIT_MASK_PTRS.MaskOrTableOffset -1). */
FI;
FI;
Restore saved IA32_RTIT_CTL.value;
FI;
ToPA Errors
When a malformed ToPA entry is found, an operation error results (see Section 36.3.9). A malformed entry can
be any of the following:
1. ToPA entry reserved bit violation.
This describes cases where a bit marked as reserved in Section 36.2.6.2 above is set to 1.
2. ToPA alignment violation.
This includes cases where illegal ToPA entry base address bits are set to 1:
a. ToPA table base address is not 4KB-aligned. The table base can be from a WRMSR to
IA32_RTIT_OUTPUT_BASE, or from a ToPA entry with END=1.
b. ToPA entry base address is not aligned to the ToPA entry size (e.g., a 2MB region with base address[20:12]
not equal to 0).
c.
ToPA entry base address sets upper physical address bits not supported by the processor.
3. Illegal ToPA Output Offset (if IA32_RTIT_STATUS.Stopped=0).
IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset is greater than or equal to the size of the current ToPA output
region size.
4. ToPA rules violations.
These are similar to ToPA entry reserved bit violations; they are cases when a ToPA entry is encountered with
illegal field combinations. They include the following:
a. Setting the STOP or INT bit on an entry with END=1.
b. Setting the END bit in entry 0 of a ToPA table.
c.
On processors that support only a single ToPA entry (see above), two additional illegal settings apply:
i)
ToPA table entry 1 with END=0.
ii) ToPA table entry 1 with base address not matching the table base.
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In all cases, the error will be logged by setting IA32_RTIT_STATUS.Error, thereby disabling tracing when the problematic ToPA entry is reached (when proc_trace_table_offset points to the entry containing the error). Any packet
bytes that are internally buffered when the error is detected may be lost.
Note that operational errors may also be signaled due to attempts to access restricted memory. See Section
36.2.6.4 for details.
A tracing software have a range of flexibility using ToPA to manage the interaction of Intel PT with application
buffers, see Section 36.5.
36.2.6.3
Trace Transport Subsystem
When IA32_RTIT_CTL.FabricEn is set, the IA32_RTIT_CTL.ToPA bit is ignored, and trace output is written to the
trace transport subsystem. The endpoints of this transport are platform-specific, and details of configuration
options should refer to the specific platform documentation. The FabricEn bit is available to be set if
CPUID(EAX=14H,ECX=0):EBX[bit 3] = 1.
36.2.6.4
Restricted Memory Access
Packet output cannot be directed to any regions of memory that are restricted by the platform. In particular, all
memory accesses on behalf of packet output are checked against the SMRR regions. If there is any overlap with
these regions, trace data collection will not function properly. Exact processor behavior is implementation-dependent; Table 36-5 summarizes several scenarios.
Table 36-5. Behavior on Restricted Memory Access
Scenario
Description
ToPA output region
overlaps with
SMRR
Stores to the restricted memory region will be dropped, and that packet data will be lost. Any attempt to read
from that restricted region will return all 1s. The processor also may signal an error (Section 36.3.9) and disable
tracing when the output pointer reaches the restricted region. If packet generation remains enabled, then
packet output may continue once stores are no longer directed to restricted memory (on wrap, or if the output
region is larger than the restricted memory region).
ToPA table overlaps
with SMRR
The processor will signal an error (Section 36.3.9) and disable tracing when the ToPA read pointer
(IA32_RTIT_OUTPUT_BASE + (proc_trace_table_offset « 3)) enters the restricted region.
It should also be noted that packet output should not be routed to the 4KB APIC MMIO region, as defined by the
IA32_APIC_BASE MSR. For details about the APIC, refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. No error is signaled for this case.
Modifications to Restricted Memory Regions
It is recommended that software disable packet generation before modifying the SMRRs to change the scope of the
SMRR regions. This is because the processor reserves the right to cache any number of ToPA table entries internally, after checking them against restricted memory ranges. Once cached, the entries will not be checked again,
meaning one could potentially route packet output to a newly restricted region. Software can ensure that any
cached entries are written to memory by clearing IA32_RTIT_CTL.TraceEn.
36.2.7
Enabling and Configuration MSRs
36.2.7.1
General Considerations
Trace packet generation is enabled and configured by a collection of model-specific registers (MSRs), which are
detailed below. Some notes on the configuration MSR behavior:
•
If Intel Processor Trace is not supported by the processor (see Section 36.3.1), RDMSR or WRMSR of the
IA32_RTIT_* MSRs will cause #GP.
•
A WRMSR to any of these configuration MSRs that begins and ends with IA32_RTIT_CTL.TraceEn set will #GP
fault. Packet generation must be disabled before the configuration MSRs can be changed.
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Note: Software may write the same value back to IA32_RTIT_CTL without #GP, even if TraceEn=1.
•
•
All configuration MSRs for Intel PT are duplicated per logical processor
•
All configuration MSRs for Intel PT are cleared on a cold RESET.
For each configuration MSR, any MSR write that attempts to change bits marked reserved, or utilize encodings
marked reserved, will cause a #GP fault.
— If CPUID.(EAX=14H, ECX=0):EBX.IPFILT_WRSTPRSV[bit 2] = 1, only the TraceEn bit is cleared on warm
RESET; though this may have the impact of clearing other bits in IA32_RTIT_STATUS. Other MSR values of
the trace configuration MSRs are preserved on warm RESET.
•
The semantics of MSR writes to trace configuration MSRs in this chapter generally apply to explicit WRMSR to
these registers, using VM-exit or VM-entry MSR load list to these MSRs, XRSTORS with requested feature bit
map including XSAVE map component of state_8 (corresponding to IA32_XSS[bit 8]), and the write to
IA32_RTIT_CTL.TraceEn by XSAVES (Section 36.3.5.2).
36.2.7.2
IA32_RTIT_CTL MSR
IA32_RTIT_CTL, at address 570H, is the primary enable and control MSR for trace packet generation. Bit positions
are listed in Table 36-6.
Table 36-6. IA32_RTIT_CTL MSR
Position
0
Bit Name
TraceEn
At Reset
0
Bit Description
If 1, enables tracing; else tracing is disabled if 0.
When this bit transitions from 1 to 0, all buffered packets are flushed out of internal buffers.
A further store, fence, or architecturally serializing instruction may be required to ensure that
packet data can be observed at the trace endpoint. See Section 36.2.7.3 for details of
enabling and disabling packet generation.
Note that the processor will clear this bit on #SMI (Section ) and warm reset. Other MSR bits
of IA32_RTIT_CTL (and other trace configuration MSRs) are not impacted by these events.
1
CYCEn
0
0: Disables CYC Packet (see Section 36.4.2.14).
1: Enables CYC Packet.
This bit is reserved if CPUID.(EAX=14H, ECX=0):EBX.CPSB_CAM[bit 1] = 0.
2
OS
0
0: Packet generation is disabled when CPL = 0.
1: Packet generation may be enabled when CPL = 0.
3
User
0
0: Packet generation is disabled when CPL > 0.
1: Packet generation may be enabled when CPL > 0.
4
PwrEvtEn
0
0: Power Event Trace packets are disabled.
1: Power Event Trace packets are enabled (see Section 36.2.3, “Power Event Tracing”).
5
FUPonPTW
0
0: PTW packets are not followed by FUPs.
1: PTW packets are followed by FUPs.
6
FabricEn
0
0: Trace output is directed to the memory subsystem, mechanism depends on
IA32_RTIT_CTL.ToPA.
1: Trace output is directed to the trace transport subsystem, IA32_RTIT_CTL.ToPA is ignored.
This bit is reserved if CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0.
7
CR3Filter
0
0: Disables CR3 filtering.
1: Enables CR3 filtering.
36-16 Vol. 3C
INTEL® PROCESSOR TRACE
Table 36-6. IA32_RTIT_CTL MSR (Contd.)
Position
8
Bit Name
ToPA
At Reset
0
Bit Description
0: Single-range output scheme enabled if CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2]
= 1 and IA32_RTIT_CTL.FabricEn=0.
1: ToPA output scheme enabled (see Section 36.2.6.2) if CPUID.(EAX=14H,
ECX=0):ECX.TOPA[bit 0] = 1, and IA32_RTIT_CTL.FabricEn=0.
Note: WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit and FabricEn would
cause #GP, if CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0.
WRMSR to IA32_RTIT_CTL that sets this bit causes #GP, if CPUID.(EAX=14H,
ECX=0):ECX.TOPA[bit 0] = 0.
9
MTCEn
0
0: Disables MTC Packet (see Section 36.4.2.16).
1: Enables MTC Packet.
This bit is reserved if CPUID.(EAX=14H, ECX=0):EBX.MTC[bit 3] = 0.
10
TSCEn
0
0: Disable TSC packets.
1: Enable TSC packets (see Section 36.4.2.11).
11
DisRETC
0
0: Enable RET compression.
1: Disable RET compression (see Section 36.2.1.2).
12
PTWEn
0
0: PTWRITE packet generation disabled.
1: PTWRITE packet generation enabled (see Table 36-40 “PTW Packet Definition”).
13
BranchEn
0
0: Disable COFI-based packets.
1: Enable COFI-based packets: FUP, TIP, TIP.PGE, TIP.PGD, TNT, MODE.Exec, MODE.TSX.
see Section 36.2.6 for details on BranchEn.
17:14
MTCFreq
0
Defines MTC packet Frequency, which is based on the core crystal clock, or Always Running
Timer (ART). MTC will be sent each time the selected ART bit toggles. The following Encodings
are defined:
0: ART(0), 1: ART(1), 2: ART(2), 3: ART(3), 4: ART(4), 5: ART(5), 6: ART(6), 7: ART(7),
8: ART(8), 9: ART(9), 10: ART(10), 11: ART(11), 12: ART(12), 13: ART(13), 14: ART(14), 15:
ART(15)
Software must use CPUID to query the supported encodings in the processor, see Section
36.3.1. Use of unsupported encodings will result in a #GP fault. This field is reserved if
CPUID.(EAX=14H, ECX=0):EBX.MTC[bit 3] = 0.
18
Reserved
0
Must be 0.
22:19
CycThresh
0
CYC packet threshold, see Section 36.3.6 for details. CYC packets will be sent with the first
eligible packet after N cycles have passed since the last CYC packet. If CycThresh is 0 then
N=0, otherwise N is defined as 2(CycThresh-1). The following Encodings are defined:
0: 0, 1: 1,
2: 2,
3: 4,
4: 8,
5: 16,
6: 32,
7: 64,
8: 128, 9: 256, 10: 512,
11: 1024, 12: 2048, 13: 4096, 14: 8192, 15: 16384
Software must use CPUID to query the supported encodings in the processor, see Section
36.3.1. Use of unsupported encodings will result in a #GP fault. This field is reserved if
CPUID.(EAX=14H, ECX=0):EBX.CPSB_CAM[bit 1] = 0.
23
Reserved
0
Must be 0.
Vol. 3C 36-17
INTEL® PROCESSOR TRACE
Table 36-6. IA32_RTIT_CTL MSR (Contd.)
Position
27:24
Bit Name
PSBFreq
At Reset
0
Bit Description
Indicates the frequency of PSB packets. PSB packet frequency is based on the number of Intel
PT packet bytes output, so this field allows the user to determine the increment of
IA32_IA32_RTIT_STATUS.PacketByteCnt that should cause a PSB to be generated. Note that
PSB insertion is not precise, but the average output bytes per PSB should approximate the
SW selected period. The following Encodings are defined:
0: 2K, 1: 4K,
2: 8K,
3: 16K,
4: 32K,
5: 64K,
6: 128K,
7: 256K,
8: 512K, 9: 1M, 10: 2M,
11: 4M,
12: 8M,
13: 16M, 14: 32M, 15: 64M
Software must use CPUID to query the supported encodings in the processor, see Section
36.3.1. Use of unsupported encodings will result in a #GP fault. This field is reserved if
CPUID.(EAX=14H, ECX=0):EBX.CPSB_CAM[bit 1] = 0.
31:28
Reserved
0
Must be 0.
35:32
ADDR0_CFG
0
Configures the base/limit register pair IA32_RTIT_ADDR0_A/B based on the following
encodings:
0: ADDR0 range unused.
1: The [IA32_RTIT_ADDR0_A..IA32_RTIT_ADDR0_B] range defines a FilterEn range. FilterEn
will only be set when the IP is within this range, though other FilterEn ranges can additionally
be used. See Section 36.2.4.3 for details on IP filtering.
2: The [IA32_RTIT_ADDR0_A..IA32_RTIT_ADDR0_B] range defines a TraceStop range.
TraceStop will be asserted if code branches into this range. See 4.2.8 for details on TraceStop.
3..15: Reserved (#GP).
This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] >= 0.
39:36
ADDR1_CFG
0
Configures the base/limit register pair IA32_RTIT_ADDR1_A/B based on the following
encodings:
0: ADDR1 range unused.
1: The [IA32_RTIT_ADDR1_A..IA32_RTIT_ADDR1_B] range defines a FilterEn range. FilterEn
will only be set when the IP is within this range, though other FilterEn ranges can additionally
be used. See Section 36.2.4.3 for details on IP filtering.
2: The [IA32_RTIT_ADDR1_A..IA32_RTIT_ADDR1_B] range defines a TraceStop range.
TraceStop will be asserted if code branches into this range. See Section 36.4.2.10 for details
on TraceStop.
3..15: Reserved (#GP).
This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] < 2.
43:40
ADDR2_CFG
0
Configures the base/limit register pair IA32_RTIT_ADDR2_A/B based on the following
encodings:
0: ADDR2 range unused.
1: The [IA32_RTIT_ADDR2_A..IA32_RTIT_ADDR2_B] range defines a FilterEn range. FilterEn
will only be set when the IP is within this range, though other FilterEn ranges can additionally
be used. See Section 36.2.4.3 for details on IP filtering.
2: The [IA32_RTIT_ADDR2_A..IA32_RTIT_ADDR2_B] range defines a TraceStop range.
TraceStop will be asserted if code branches into this range. See Section 36.4.2.10 for details
on TraceStop.
3..15: Reserved (#GP).
This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] < 3.
36-18 Vol. 3C
INTEL® PROCESSOR TRACE
Table 36-6. IA32_RTIT_CTL MSR (Contd.)
Position
47:44
Bit Name
ADDR3_CFG
At Reset
0
Bit Description
Configures the base/limit register pair IA32_RTIT_ADDR3_A/B based on the following
encodings:
0: ADDR3 range unused.
1: The [IA32_RTIT_ADDR3_A..IA32_RTIT_ADDR3_B] range defines a FilterEn range. FilterEn
will only be set when the IP is within this range, though other FilterEn ranges can additionally
be used. See Section 36.2.4.3 for details on IP filtering.
2: The [IA32_RTIT_ADDR3_A..IA32_RTIT_ADDR3_B] range defines a TraceStop range.
TraceStop will be asserted if code branches into this range. See Section 36.4.2.10 for details
on TraceStop.
3..15: Reserved (#GP).
This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] < 4.
59:48
Reserved
0
Reserved only for future trace content enables, or address filtering configuration enables.
Must be 0.
63:60
Reserved
0
Must be 0.
36.2.7.3
Enabling and Disabling Packet Generation with TraceEn
When TraceEn transitions from 0 to 1, Intel Processor Trace is enabled, and a series of packets may be generated.
These packets help ensure that the decoder is aware of the state of the processor when the trace begins, and that
it can keep track of any timing or state changes that may have occurred while packet generation was disabled. A
full PSB+ (see Section 36.4.2.17) will be generated if IA32_RTIT_STATUS.PacketByteCnt=0, and may be generated in other cases as well. Otherwise, timing packets will be generated, including TSC, TMA, and CBR (see Section
36.4.2).
In addition to the packets discussed above, if and when PacketEn (Section 36.2.5.1) transitions from 0 to 1 (which
may happen immediately, depending on filtering settings), a TIP.PGE packet (Section 36.4.2.3) will be generated.
When TraceEn is set, the processor may read ToPA entries from memory and cache them internally. For this reason,
software should disable packet generation before making modifications to the ToPA tables (or changing the configuration of restricted memory regions). See Section 36.7 for more details of packets that may be generated with
modifications to TraceEn.
Disabling Packet Generation
Clearing TraceEn causes any packet data buffered within the logical processor to be flushed out, after which the
output MSRs (IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS) will have stable values. When
output is directed to memory, a store, fence, or architecturally serializing instruction may be required to ensure
that the packet data is globally observed. No special packets are generated by disabling packet generation, though
a TIP.PGD may result if PacketEn=1 at the time of disable.
Other Writes to IA32_RTIT_CTL
Any attempt to modify IA32_RTIT_CTL while TraceEn is set will result in a general-protection fault (#GP) unless the
same write also clears TraceEn. However, writes to IA32_RTIT_CTL that do not modify any bits will not cause a
#GP, even if TraceEn remains set.
36.2.7.4
IA32_RTIT_STATUS MSR
The IA32_RTIT_STATUS MSR is readable and writable by software, but some bits (ContextEn, TriggerEn) are readonly and cannot be directly modified. The WRMSR instruction ignores these bits in the source operand (attempts to
modify these bits are ignored and do not cause WRMSR to fault).
This MSR can only be written when IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection
fault (#GP). The processor does not modify the value of this MSR while TraceEn is 0 (software can modify it with
WRMSR).
Vol. 3C 36-19
INTEL® PROCESSOR TRACE
Table 36-7. IA32_RTIT_STATUS MSR
Position
Bit Name
At Reset
Bit Description
0
FilterEn
0
This bit is written by the processor, and indicates that tracing is allowed for the current IP,
see Section 36.2.5.5. Writes are ignored.
1
ContextEn
0
The processor sets this bit to indicate that tracing is allowed for the current context. See
Section 36.2.5.3. Writes are ignored.
2
TriggerEn
0
The processor sets this bit to indicate that tracing is enabled. See Section 36.2.5.2. Writes are
ignored.
3
Reserved
0
Must be 0.
4
Error
0
The processor sets this bit to indicate that an operational error has been encountered. When
this bit is set, TriggerEn is cleared to 0 and packet generation is disabled. For details, see
“ToPA Errors” in Section 36.2.6.2.
When TraceEn is cleared, software can write this bit. Once it is set, only software can clear it.
It is not recommended that software ever set this bit, except in cases where it is restoring a
prior saved state.
5
Stopped
0
The processor sets this bit to indicate that a ToPA Stop condition has been encountered.
When this bit is set, TriggerEn is cleared to 0 and packet generation is disabled. For details,
see “ToPA STOP” in Section 36.2.6.2.
When TraceEn is cleared, software can write this bit. Once it is set, only software can clear it.
It is not recommended that software ever set this bit, except in cases where it is restoring a
prior saved state.
31:6
Reserved
0
48:32
PacketByteCnt 0
Must be 0.
This field is written by the processor, and holds a count of packet bytes that have been sent
out. The processor also uses this field to determine when the next PSB packet should be
inserted. Note that the processor may clear or modify this field at any time while
IA32_RTIT_CTL.TraceEn=1. It will have a stable value when IA32_RTIT_CTL.TraceEn=0.
See Section 36.4.2.17 for details.
63:49
Reserved
36.2.7.5
0
Must be 0.
IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B MSRs
The role of the IA32_RTIT_ADDRn_A/B register pairs, for each n, is determined by the corresponding ADDRn_CFG
fields in IA32_RTIT_CTL (see Section 36.2.7.2). The number of these register pairs is enumerated by
CPUID.(EAX=14H, ECX=1):EAX.RANGECNT[2:0].
•
Processors that enumerate support for 1 range support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
36-20 Vol. 3C
INTEL® PROCESSOR TRACE
•
Processors that enumerate support for 2 ranges support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
•
IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
Processors that enumerate support for 3 ranges support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
•
IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B
Processors that enumerate support for 4 ranges support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B
IA32_RTIT_ADDR3_A, IA32_RTIT_ADDR3_B
Each register has a single 64-bit field that holds a linear address value. Writes must ensure that the address is
properly sign-extended, otherwise a #GP fault will result.
36.2.7.6
IA32_RTIT_CR3_MATCH MSR
The IA32_RTIT_CR3_MATCH register is compared against CR3 when IA32_RTIT_CTL.CR3Filter is 1. Bits 63:5 hold
the CR3 address value to match, bits 4:0 are reserved to 0. For more details on CR3 filtering and the treatment of
this register, see Section 36.2.4.2.
This MSR can be written only when IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection
fault (#GP). IA32_RTIT_CR3_MATCH[4:0] are reserved and must be 0; an attempt to set those bits using WRMSR
causes a #GP.
36.2.7.7
IA32_RTIT_OUTPUT_BASE MSR
This MSR is used to configure the trace output destination, when output is directed to memory
(IA32_RTIT_CTL.FabricEn = 0). The size of the address field is determined by the maximum physical address width
(MAXPHYADDR), as reported by CPUID.80000008H:EAX[7:0].
When the ToPA output scheme is used, the processor may update this MSR when packet generation is enabled, and
those updates are asynchronous to instruction execution. Therefore, the values in this MSR should be considered
unreliable unless packet generation is disabled (IA32_RTIT_CTL.TraceEn = 0).
Accesses to this MSR are supported only if Intel PT output to memory is supported, hence when either
CPUID.(EAX=14H, ECX=0):ECX[bit 0] or CPUID.(EAX=14H, ECX=0):ECX[bit 2] are set. Otherwise WRMSR or
RDMSR cause a general-protection fault (#GP). If supported, this MSR can be written only when
IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection fault (#GP).
Vol. 3C 36-21
INTEL® PROCESSOR TRACE
Table 36-8. IA32_RTIT_OUTPUT_BASE MSR
Position
6:0
Bit Name
At Reset
Reserved
MAXPHYADDR-1:7
0
BasePhysAddr 0
Bit Description
Must be 0.
The base physical address. How this address is used depends on the value of
IA32_RTIT_CTL.ToPA:
0: This is the base physical address of a single, contiguous physical output region.
This could be mapped to DRAM or to MMIO, depending on the value.
The base address should be aligned with the size of the region, such that none of
the 1s in the mask value(Section 36.2.7.8) overlap with 1s in the base address. If
the base is not aligned, an operational error will result (see Section 36.3.9).
1: The base physical address of the current ToPA table. The address must be 4K
aligned. Writing an address in which bits 11:7 are non-zero will not cause a #GP, but
an operational error will be signaled once TraceEn is set. See “ToPA Errors” in
Section 36.2.6.2 as well as Section 36.3.9.
63:MAXPHYADDR
36.2.7.8
Reserved
0
Must be 0.
IA32_RTIT_OUTPUT_MASK_PTRS MSR
This MSR holds any mask or pointer values needed to indicate where the next byte of trace output should be
written. The meaning of the values held in this MSR depend on whether the ToPA output mechanism is in use. See
Section 36.2.6.2 for details.
The processor updates this MSR while when packet generation is enabled, and those updates are asynchronous to
instruction execution. Therefore, the values in this MSR should be considered unreliable unless packet generation
is disabled (IA32_RTIT_CTL.TraceEn = 0).
Accesses to this MSR are supported only if Intel PT output to memory is supported, hence when either
CPUID.(EAX=14H, ECX=0):ECX[bit 0] or CPUID.(EAX=14H, ECX=0):ECX[bit 2] are set. Otherwise WRMSR or
RDMSR cause a general-protection fault (#GP). If supported, this MSR can be written only when
IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection fault (#GP).
Table 36-9. IA32_RTIT_OUTPUT_MASK_PTRS MSR
Position
Bit Name
At Reset
Bit Description
6:0
LowerMask
7FH
Forced to 1, writes are ignored.
31:7
MaskOrTableO
ffset
0
The use of this field depends on the value of IA32_RTIT_CTL.ToPA:
0: This field holds bits 31:7 of the mask value for the single, contiguous physical output
region. The size of this field indicates that regions can be of size 128B up to 4GB. This value
(combined with the lower 7 bits, which are reserved to 1) will be ANDed with the
OutputOffset field to determine the next write address. All 1s in this field should be
consecutive and starting at bit 7, otherwise the region will not be contiguous, and an
operational error (Section 36.3.9) will be signaled when TraceEn is set.
1: This field holds bits 27:3 of the offset pointer into the current ToPA table. This value can
be added to the IA32_RTIT_OUTPUT_BASE value to produce a pointer to the current ToPA
table entry, which itself is a pointer to the current output region. In this scenario, the lower 7
reserved bits are ignored. This field supports tables up to 256 MBytes in size.
36-22 Vol. 3C
INTEL® PROCESSOR TRACE
Table 36-9. IA32_RTIT_OUTPUT_MASK_PTRS MSR (Contd.)
Position
Bit Name
63:32
OutputOffset
At Reset
0
Bit Description
The use of this field depends on the value of IA32_RTIT_CTL.ToPA:
0: This is bits 31:0 of the offset pointer into the single, contiguous physical output region.
This value will be added to the IA32_RTIT_OUTPUT_BASE value to form the physical address
at which the next byte of packet output data will be written. This value must be less than or
equal to the MaskOrTableOffset field, otherwise an operational error (Section 36.3.9) will be
signaled when TraceEn is set.
1: This field holds bits 31:0 of the offset pointer into the current ToPA output region. This
value will be added to the output region base field, found in the current ToPA table entry, to
form the physical address at which the next byte of trace output data will be written.
This value must be less than the ToPA entry size, otherwise an operational error (Section
36.3.9) will be signaled when TraceEn is set.
36.2.8
Interaction of Intel® Processor Trace and Other Processor Features
36.2.8.1
Intel® Transactional Synchronization Extensions (Intel® TSX)
The operation of Intel TSX is described in Chapter 14 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. For tracing purpose, packet generation does not distinguish between hardware lock
elision (HLE) and restricted transactional memory (RTM), but speculative execution does have impacts on the trace
output. Specifically, packets are generated as instructions complete, even for instructions in a transactional region
that is later aborted. For this reason, debugging software will need indication of the beginning and end of a transactional region; this will allow software to understand when instructions are part of a transactional region and
whether that region has been committed.
To enable this, TSX information is included in a MODE packet leaf. The mode bits in the leaf are:
•
•
InTX: Set to 1 on an TSX transaction begin, and cleared on transaction commit or abort.
TXAbort: Set to 1 only when InTX transitions from 1 to 0 on an abort. Cleared otherwise.
If BranchEn=1, this MODE packet will be sent each time the transaction status changes. See Table 36-10 for
details.
Table 36-10. TSX Packet Scenarios
TSX Event
Transaction Begin
Transaction
Commit
Transaction Abort
Other
Instruction
Packets
Either XBEGIN or XACQUIRE lock (the latter if executed
transactionally)
MODE(TXAbort=0, InTX=1), FUP(CurrentIP)
Either XEND or XRELEASE lock, if transactional execution
ends. This happens only on the outermost commit
MODE(TXAbort=0, InTX=0), FUP(CurrentIP)
XABORT or other transactional abort
MODE(TXAbort=1, InTX=0), FUP(CurrentIP),
TIP(TargetIP)
One of the following:
• Nested XBEGIN or XACQUIRE lock
• An outer XACQUIRE lock that doesn’t begin a transaction
(InTX not set)
• Non-outermost XEND or XRELEASE lock
None. No change to TSX mode bits for these
cases.
The CurrentIP listed above is the IP of the associated instruction. The TargetIP is the IP of the next instruction to
be executed; for HLE, this is the XACQUIRE lock; for RTM, this is the fallback handler.
Intel PT stores are non-transactional, and thus packet writes are not rolled back on TSX abort.
Vol. 3C 36-23
INTEL® PROCESSOR TRACE
TSX and IP Filtering
A complication with tracking transactions is handling transactions that start or end outside of the tracing region.
Transactions can’t span across a change in ContextEn, because CPL changes and CR3 changes each cause aborts.
But a transaction can start within the IP filter region and end outside it.
To assist the decoder handling this situation, MODE.TSX packets can be sent even if FilterEn=0, though there will
be no FUP attached. Instead, they will merely serve to indicate to the decoder when transactions are active and
when they are not. When tracing resumes (due to PacketEn=1), the last MODE.TSX preceding the TIP.PGE will indicate the current transaction status.
System Management Mode (SMM)
SMM code has special privileges that non-SMM code does not have. Intel Processor Trace can be used to trace SMM
code, but special care is taken to ensure that SMM handler context is not exposed in any non-SMM trace collection.
Additionally, packet output from tracing non-SMM code cannot be written into memory space that is either
protected by SMRR or used by the SMM handler.
SMM is entered via a system management interrupt (SMI). SMI delivery saves the value of IA32_RTIT_CTL.TraceEn
into SMRAM and then clears it, thereby disabling packet generation.
The saving and clearing of IA32_RTIT_CTL.TraceEn ensures two things:
1. All internally buffered packet data is flushed before entering SMM (see Section 36.2.7.2).
2. Packet generation ceases before entering SMM, so any tracing that was configured outside SMM does not
continue into SMM. No SMM instruction pointers or other state will be exposed in the non-SMM trace.
When the RSM instruction is executed to return from SMM, the TraceEn value that was saved by SMI delivery is
restored, allowing tracing to be resumed. As is done any time packet generation is enabled, ContextEn is re-evaluated, based on the values of CPL, CR3, etc., established by RSM.
Like other interrupts, delivery of an SMI produces a FUP containing the IP of the next instruction to execute. By
toggling TraceEn, SMI and RSM can produce TIP.PGD and TIP.PGE packets, respectively, indicating that tracing was
disabled or re-enabled. See Table 36.7 for more information about packets entering and leaving SMM.
Although #SMI and RSM change CR3, PIP packets are not generated in these cases. With #SMI tracing is disabled
before the CR3 change; with RSM TraceEn is restored after CR3 is written.
TraceEn must be cleared before executing RSM, otherwise it will cause a shutdown. Further, on processors that
restrict use of Intel PT with LBRs (see Section 36.3.1.2), any RSM that results in enabling of both will cause a shutdown.
Intel PT can support tracing of System Transfer Monitor operating in SMM, see Section 36.6.
36.2.8.2
Virtual-Machine Extensions (VMX)
Initial implementations of Intel Processor Trace do not support tracing in VMX operation. Such processors indicate
this by returning 0 for IA32_VMX_MISC[bit 14]. On these processors, execution of the VMXON instruction clears
IA32_RTIT_CTL.TraceEn and any attempt to set that bit in VMX operation using WRMSR causes a general-protection exception (#GP).
Processors that support Intel Processor Trace in VMX operation return 1 for IA32_VMX_MISC[bit 14]. Details of
tracing in VMX operation are described in Section 36.5.
36.2.8.3
Intel Software Guard Extensions (SGX)
SGX provides an application with ability to instantiate a protective container (an enclave) with confidentiality and
integrity (see Intel® Software Guard Extensions Programming Reference). On a processor with both Intel PT and
SGX enabled, when executing code within a production enclave, no control flow packets are produced by Intel PT.
Enclave entry will clear ContextEn, thereby blocking control flow packet generation. A TIP.PGD packet will be
generated if PacketEn=1 at the time of the entry.
Upon enclave exit, ContextEn will no longer be forced to 0. If other enables are set at the time, a TIP.PGE may be
generated to indicate that tracing is resumed.
36-24 Vol. 3C
INTEL® PROCESSOR TRACE
During the enclave execution, Intel PT remains enabled, and periodic or timing packets such as PSB, TSC, MTC, or
CBR can still be generated. No IPs or other architectural state will be exposed.
For packet generation examples on enclave entry or exit, see Section 36.7.
Debug Enclaves
SGX allows an enclave to be configured with relaxed protection of confidentiality for debug purposes, see Intel®
Software Guard Extensions Programming Reference. In a debug enclave, Intel PT continues to function normally.
Specifically, ContextEn is not impacted by enclave entry or exit. Hence the generation of ContextEn-dependent
packets within a debug enclave is allowed.
36.2.8.4
SENTER/ENTERACCS and ACM
GETSEC[SENTER] and GETSEC[ENTERACCS] instructions clear TraceEn, and it is not restored when those instruction complete. SENTER also causes TraceEn to be cleared on other logical processors when they rendezvous and
enter the SENTER sleep state. In these two cases, the disabling of packet generation is not guaranteed to flush
internally buffered packets. Some packets may be dropped.
When executing an authenticated code module (ACM), packet generation is silently disabled during ACRAM setup.
TraceEn will be cleared, but no TIP.PGD packet is generated. After completion of the module, the TraceEn value will
be restored. There will be no TIP.PGE packet, but timing packets, like TSC and CBR, may be produced.
36.2.8.5
Intel® Memory Protection Extensions (Intel® MPX)
Bounds exceptions (#BR) caused by Intel MPX are treated like other exceptions, producing FUP and TIP packets
that indicate the source and destination IPs.
36.3
CONFIGURATION AND PROGRAMMING GUIDELINE
36.3.1
Detection of Intel Processor Trace and Capability Enumeration
Processor support for Intel Processor Trace is indicated by CPUID.(EAX=07H,ECX=0H):EBX[bit 25] = 1. CPUID
function 14H is dedicated to enumerate the resource and capability of processors that report
CPUID.(EAX=07H,ECX=0H):EBX[bit 25] = 1. Different processor generations may have architecturally-defined
variation in capabilities. Table 36-11 describes details of the enumerable capabilities that software must use across
generations of processors that support Intel Processor Trace.
Vol. 3C 36-25
INTEL® PROCESSOR TRACE
Table 36-11. CPUID Leaf 14H Enumeration of Intel Processor Trace Capabilities
CPUID.(EAX=14H,ECX=0)
Register
EAX
Name
Description Behavior
Bits
31:0
Maximum valid sub-leaf Index
Specifies the index of the maximum valid sub-leaf for this CPUID leaf
0
CR3 Filtering Support
1: Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that
IA32_RTIT_CR3_MATCH MSR can be accessed. See Section 36.2.7.
EBX
0: Indicates that writes that set IA32_RTIT_CTL.CR3Filter to 1, or any
access to IA32_RTIT_CR3_MATCH, will #GP fault.
1
Configurable PSB and CycleAccurate Mode Supported
1: (a) IA32_RTIT_CTL.PSBFreq can be set to a non-zero value, in order to
select the preferred PSB frequency (see below for allowed values). (b)
IA32_RTIT_STATUS.PacketByteCnt can be set to a non-zero value, and
will be incremented by the processor when tracing to indicate progress
towards the next PSB. If trace packet generation is enabled by setting
TraceEn, a PSB will only be generated if PacketByteCnt=0. (c)
IA32_RTIT_CTL.CYCEn can be set to 1 to enable Cycle-Accurate Mode.
See Section 36.2.7.
0: (a) Any attempt to set IA32_RTIT_CTL.PSBFreq, to set
IA32_RTIT_CTL.CYCEn, or write a non-zero value to
IA32_RTIT_STATUS.PacketByteCnt any access to
IA32_RTIT_CR3_MATCH, will #GP fault. (b) If trace packet generation is
enabled by setting TraceEn, a PSB is always generated. (c) Any attempt
to set IA32_RTIT_CTL.CYCEn will #GP fault.
2
IP Filtering and TraceStop
supported, and Preserve Intel
PT MSRs across warm reset
1: (a) IA32_RTIT_CTL provides at one or more ADDRn_CFG field to
configure the corresponding address range MSRs for IP Filtering or IP
TraceStop. Each ADDRn_CFG field accepts a value in the range of 0:2
inclusive. The number of ADDRn_CFG fields is reported by
CPUID.(EAX=14H, ECX=1):EAX.RANGECNT[2:0]. (b) At least one register
pair IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B are provided to
configure address ranges for IP filtering or IP TraceStop. (c) On warm
reset, all Intel PT MSRs will retain their pre-reset values, though
IA32_RTIT_CTL.TraceEn will be cleared. The Intel PT MSRs are listed in
Section 36.2.7.
0: (a) An Attempt to write IA32_RTIT_CTL.ADDRn_CFG with non-zero
encoding values will cause #GP. (b) Any access to IA32_RTIT_ADDRn_A
and IA32_RTIT_ADDRn_B, will #GP fault. (c) On warm reset, all Intel PT
MSRs will be cleared.
3
MTC Supported
1: IA32_RTIT_CTL.MTCEn can be set to 1, and MTC packets will be
generated. See Section 36.2.7.
0: An attempt to set IA32_RTIT_CTL.MTCEn or IA32_RTIT_CTL.MTCFreq
to a non-zero value will #GP fault.
4
PTWRITE Supported
1: Writes can set IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5]
(FUPonPTW), and PTWRITE can generate packets.
0: Writes that set IA32_RTIT_CTL[12] or IA32_RTIT_CTL[5] will #GP,
and PTWRITE will #UD fault.
5
Power Event Trace Supported 1: Writes can set IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event
Trace packet generation.
0: Writes that set IA32_RTIT_CTL[4] will #GP.
31:6
36-26 Vol. 3C
Reserved
INTEL® PROCESSOR TRACE
Table 36-11. CPUID Leaf 14H Enumeration of Intel Processor Trace Capabilities (Contd.)
CPUID.(EAX=14H,ECX=0)
Register
Name
Description Behavior
Bits
0
ToPA Output Supported
ECX
1: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing
the ToPA output scheme (Section 36.2.6.2) IA32_RTIT_OUTPUT_BASE
and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
0: Unless CPUID.(EAX=14H, ECX=0):ECX.SNGLRNGOUT[bit 2] = 1. writes
to IA32_RTIT_OUTPUT_BASE or IA32_RTIT_OUTPUT_MASK_PTRS.
MSRs will #GP fault.
1
ToPA Tables Allow Multiple
Output Entries
1: ToPA tables can hold any number of output entries, up to the
maximum allowed by the MaskOrTableOffset field of
IA32_RTIT_OUTPUT_MASK_PTRS.
0: ToPA tables can hold only one output entry, which must be followed
by an END=1 entry which points back to the base of the table.
Further, ToPA PMIs will be delivered before the region is filled. See ToPA
PMI in Section 36.2.6.2.
If there is more than one output entry before the END entry, or if the
END entry has the wrong base address, an operational error will be
signaled (see “ToPA Errors” in Section 36.2.6.2).
2
Single-Range Output
Supported
1: Enabling tracing (TraceEn=1) with IA32_RTIT_CTL.ToPA=0 is
supported.
0: Unless CPUID.(EAX=14H, ECX=0):ECX.TOPAOUT[bit 0] = 1. writes to
IA32_RTIT_OUTPUT_BASE or IA32_RTIT_OUTPUT_MASK_PTRS. MSRs
will #GP fault.
3
Output to Trace Transport
Subsystem Supported
30:4
Reserved
31
IP Payloads are LIP
1: Setting IA32_RTIT_CTL.FabricEn to 1 is supported.
0: IA32_RTIT_CTL.FabricEn is reserved. Write 1 to
IA32_RTIT_CTL.FabricEn will #GP fault.
1: Generated packets which contain IP payloads have LIP values, which
include the CS base component.
0: Generated packets which contain IP payloads have RIP values, which
are the offset from CS base.
EDX
31:0
Reserved
If CPUID.(EAX=14H, ECX=0):EAX reports a non-zero value, additional capabilities of Intel Processor Trace are
described in the sub-leaves of CPUID leaf 14H.
Vol. 3C 36-27
INTEL® PROCESSOR TRACE
Table 36-12. CPUID Leaf 14H, sub-leaf 1H Enumeration of Intel Processor Trace Capabilities
CPUID.(EAX=14H,ECX=1)
Register
EAX
Name
Description Behavior
Bits
2:0
Number of Address Ranges
A non-zero value specifies the number ADDRn_CFG field supported in
IA32_RTIT_CTL and the number of register pair
IA32_RTIT_ADDRn_A/IA32_RTIT_ADDRn_B supported for IP filtering
and IP TraceStop.
NOTE: Currently, no processors support more than 4 address ranges.
15:3
Reserved
31:16
Bitmap of supported MTC
Period Encodings
The non-zero bit positions indicate the map of supported encoding
values for the IA32_RTIT_CTL.MTCFreq field. This applies only if
CPUID.(EAX=14H, ECX=0):EBX.MTC[bit 3] = 1 (MTC Packet generation is
supported), otherwise the MTCFreq field is reserved to 0.
Each bit position in this field represents 1 encoding value in the 4-bit
MTCFreq field (ie, bit 0 is associated with encoding value 0). For each
bit:
1: MTCFreq can be assigned the associated encoding value.
0: MTCFreq cannot be assigned to the associated encoding value. A
write to IA32_RTIT_CTLMTCFreq with unsupported encoding will cause
#GP fault.
EBX
15:0
Bitmap of supported Cycle
Threshold values
The non-zero bit positions indicate the map of supported encoding for
the IA32_RTIT_CTL.CycThresh field. This applies only if
CPUID.(EAX=14H, ECX=0):EBX.CPSB_CAM[bit 1] = 1 (Cycle-Accurate
Mode is Supported), otherwise the CycThresh field is reserved to 0. See
Section 36.2.7.
Each bit position in this field represents 1 encoding value in the 4-bit
CycThresh field (ie, bit 0 is associated with encoding value 0). For each
bit:
1: CycThresh can be assigned the associated encoding value.
0: CycThresh cannot be assigned to the associated encoding value. A
write to CycThresh with unsupported encoding will cause #GP fault.
31:16
Bitmap of supported
Configurable PSB Frequency
encoding
The non-zero bit positions indicate the map of supported encoding for
the IA32_RTIT_CTL.PSBFreq field. This applies only if
CPUID.(EAX=14H, ECX=0):EBX.CPSB_CAM[bit 1] = 1 (Configurable PSB
is supported), otherwise the PSBFreq field is reserved to 0. See
Section 36.2.7.
Each bit position in this field represents 1 encoding value in the 4-bit
PSBFreq field (ie, bit 0 is associated with encoding value 0). For each
bit:
1: PSBFreq can be assigned the associated encoding value.
0: PSBFreq cannot be assigned to the associated encoding value. A
write to PSBFreq with unsupported encoding will cause #GP fault.
ECX
31:0
Reserved
EDX
31:0
Reserved
36-28 Vol. 3C
INTEL® PROCESSOR TRACE
36.3.1.1
Packet Decoding of RIP versus LIP
FUP, TIP, TIP.PGE, and TIP.PGE packets can contain an instruction pointer (IP) payload. On some processor generations, this payload will be an effective address (RIP), while on others this will be a linear address (LIP). In the
former case, the payload is the offset from the current CS base address, while in the latter it is the sum of the offset
and the CS base address (Note that in real mode, the CS base address is the value of CS<<4, while in protected
mode the CS base address is the base linear address of the segment indicated by the CS register.). Which IP type
is in use is indicated by enumeration (see CPUID.(EAX=14H, ECX=0):ECX.LIP[bit 31] in Table 36-11).
For software that executes while the CS base address is 0 (including all software executing in 64-bit mode), the
difference is indistinguishable. A trace decoder must account for cases where the CS base address is not 0 and the
resolved LIP will not be evident in a trace generated on a CPU that enumerates use of RIP. This is likely to cause
problems when attempting to link the trace with the associated binaries.
Note that IP comparison logic, for IP filtering and TraceStop range calculation, is based on the same IP type as
these IP packets. For processors that output RIP, the IP comparison mechanism is also based on RIP, and hence on
those processors RIP values should be written to IA32_RTIT_ADDRn_[AB] MSRs. This can produce differing
behavior if the same trace configuration setting is run on processors reporting different IP types, i.e.
CPUID.(EAX=14H, ECX=0):ECX.LIP[bit 31]. Care should be taken to check CPUID when configuring IP filters.
36.3.1.2
Model Specific Capability Restrictions
Some processor generations impose restrictions that prevent use of LBRs/BTS/BTM/LERs when software has
enabled tracing with Intel Processor Trace. On these processors, when TraceEn is set, updates of LBR, BTS, BTM,
LERs are suspended but the states of the corresponding IA32_DEBUGCTL control fields remained unchanged as if
it were still enabled. When TraceEn is cleared, the LBR array is reset, and LBR/BTS/BTM/LERs updates will resume.
Further, reads of these registers will return 0, and writes will be dropped.
The list of MSRs whose updates/accesses are restricted follows.
•
•
•
MSR_LASTBRANCH_x_TO_IP, MSR_LASTBRANCH_x_FROM_IP, MSR_LBR_INFO_x, MSR_LASTBRANCH_TOS
MSR_LER_FROM_IP, MSR_LER_TO_IP
MSR_LBR_SELECT
For processor with CPUID DisplayFamily_DisplayModel signature of 06_3DH, 06_47H, 06_4EH, 06_4FH, 06_56H
and 06_5EH, the use of Intel PT and LBRs are mutually exclusive.
36.3.2
Enabling and Configuration of Trace Packet Generation
To configure trace packets, enable packet generation, and capture packets, software starts with using CPUID
instruction to detect its feature flag, CPUID.(EAX=07H,ECX=0H):EBX[bit 25] = 1; followed by enumerating the
capabilities described in Section 36.3.1.
Based on the capability queried from Section 36.3.1, software must configure a number of model-specific registers. This section describes programming considerations related to those MSRs.
36.3.2.1
Enabling Packet Generation
When configuring and enabling packet generation, the IA32_RTIT_CTL MSR should be written after any other Intel
PT MSRs have been written, since writes to the other configuration MSRs cause a general-protection fault (#GP) if
TraceEn = 1. If a prior trace collection context is not being restored, then software should first clear
IA32_RTIT_STATUS. This is important since the Stopped, and Error fields are writable; clearing the MSR clears any
values that may have persisted from prior trace packet collection contexts. See Section 36.2.7.2 for details of
packets generated by setting TraceEn to 1.
If setting TraceEn to 1 causes an operational error (see Section 36.3.9), there may be a delay after the WRMSR
completes before the error is signaled in the IA32_RTIT_STATUS MSR.
While packet generation is enabled, the values of some configuration MSRs (e.g., IA32_RTIT_STATUS and
IA32_RTIT_OUTPUT_*) are transient, and reads may return values that are out of date. Only after packet generation is disabled (by clearing TraceEn) do reads of these MSRs return reliable values.
Vol. 3C 36-29
INTEL® PROCESSOR TRACE
36.3.2.2
Disabling Packet Generation
After disabling packet generation by clearing IA32_RTIT_CTL, it is advisable to read the IA32_RTIT_STATUS MSR
(Section 36.2.7.4):
•
If the Error bit is set, an operational error was encountered, and the trace is most likely compromised. Software
should check the source of the error (by examining the output MSR values), correct the source of the problem,
and then attempt to gather the trace again. For details on operational errors, see Section 36.3.9. Software
should clear IA32_RTIT_STATUS.Error before re-enabling packet generation.
•
If the Stopped bit is set, software execution encountered an IP TraceStop (see Section 36.2.4.3) or the ToPA
Stop condition (see “ToPA STOP” in Section 36.2.6.2) before packet generation was disabled.
36.3.3
Flushing Trace Output
Packets are first buffered internally and then written out asynchronously. To collect packet output for postprocessing, a collector needs first to ensure that all packet data has been flushed from internal buffers. Software
can ensure this by stopping packet generation by clearing IA32_RTIT_CTL.TraceEn (see “Disabling Packet Generation” in Section 36.2.7.2).
When software clears IA32_RTIT_CTL.TraceEn to flush out internally buffered packets, the logical processor issues
an SFENCE operation which ensures that WC trace output stores will be ordered with respect to the next store, or
serializing operation. A subsequent read from the same logical processor will see the flushed trace data, while a
read from another logical processor should be preceded by a store, fence, or architecturally serializing operation on
the tracing logical processor.
When the flush operations complete, the IA32_RTIT_OUTPUT_* MSR values indicate where the trace ended. While
TraceEn is set, these MSRs may hold stale values.
36.3.4
Warm Reset
The MSRs software uses to program Intel Processor Trace are cleared after a power-on RESET (or cold RESET). On
a warm RESET, the contents of those MSRs can retain their values from before the warm RESET with the exception
that IA32_RTIT_CTL.TraceEn will be cleared (which may have the side effect of clearing some bits in
IA32_RTIT_STATUS).
36.3.5
Context Switch Consideration
To facilitate construction of instruction execution traces at the granularity of a software process or thread context,
software can save and restore the states of the trace configuration MSRs across the process or thread context
switch boundary. The principle is the same as saving and restoring the typical architectural processor states across
context switches.
36.3.5.1
Manual Trace Configuration Context Switch
The configuration can be saved and restored through a sequence of instructions of RDMSR, management of MSR
content and WRMSR. To stop tracing and to ensure that all configuration MSRs contain stable values, software must
clear IA32_RTIT_CTL.TraceEn before reading any other trace configuration MSRs. The recommended method for
saving trace configuration context manually follows:
1. RDMSR IA32_RTIT_CTL, save value to memory
2. WRMSR IA32_RTIT_CTL with saved value from RDMSR above and TraceEn cleared
3. RDMSR all other configuration MSRs whose values had changed from previous saved value, save changed
values to memory
36-30 Vol. 3C
INTEL® PROCESSOR TRACE
When restoring the trace configuration context, IA32_RTIT_CTL should be restored last:
1. Read saved configuration MSR values, aside from IA32_RTIT_CTL, from memory, and restore them with
WRMSR
2. Read saved IA32_RTIT_CTL value from memory, and restore with WRMSR.
36.3.5.2
Trace Configuration Context Switch Using XSAVES/XRSTORS
On processors whose XSAVE feature set supports XSAVES and XRSTORS, the Trace configuration state can be
saved using XSAVES and restored by XRSTORS, in conjunction with the bit field associated with supervisory state
component in IA32_XSS. See Chapter 13, “Managing State Using the XSAVE Feature Set” of Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1.
The layout of the trace configuration component state in the XSAVE area is shown in Table 36-13.1
Table 36-13. Memory Layout of the Trace Configuration State Component
Offset within
Component Area
Field
Offset within
Component Area
Field
0H
IA32_RTIT_CTL
08H
IA32_RTIT_OUTPUT_BASE
10H
IA32_RTIT_OUTPUT_MASK_PTRS
18H
IA32_RTIT_STATUS
20H
IA32_RTIT_CR3_MATCH
28H
IA32_RTIT_ADDR0_A
30H
IA32_RTIT_ADDR0_B
38H
IA32_RTIT_ADDR1_A
40H
IA32_RTIT_ADDR1_B
48H–End
Reserved
The IA32_XSS MSR is zero coming out of RESET. Once IA32_XSS[bit 8] is set, system software operating at CPL=
0 can use XSAVES/XRSTORS with the appropriate requested-feature bitmap (RFBM) to manage supervisor state
components in the XSAVE map. See Chapter 13, “Managing State Using the XSAVE Feature Set” of Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1.
36.3.6
Cycle-Accurate Mode
Intel PT can be run in a cycle-accurate mode which enables CYC packets (see Section 36.4.2.14) that provide lowlevel information in the processor core clock domain. This cycle counter data in CYC packets can be used to
compute IPC (Instructions Per Cycle), or to track wall-clock time on a fine-grain level.
To enable cycle-accurate mode packet generation, software should set IA32_RTIT_CTL.CYCEn=1. It is recommended that software also set TSCEn=1 anytime cycle-accurate mode is in use. With this, all CYC-eligible packets
will be preceded by a CYC packet, the payload of which indicates the number of core clock cycles since the last CYC
packet. In cases where multiple CYC-eligible packets are generated in a single cycle, only a single CYC will be
generated before the CYC-eligible packets, otherwise each CYC-eligible packet will be preceded by its own CYC. The
CYC-eligible packets are:
•
TNT, TIP, TIP.PGE, TIP.PGD, MODE.EXEC, MODE.TSX, PIP, VMCS, OVF, MTC, TSC, PTWRITE, EXSTOP
TSC packets are generated when there is insufficient information to reconstruct wall-clock time, due to tracing
being disabled (TriggerEn=0), or power down scenarios like a transition to a deep-sleep MWAIT C-state. In this
case, the CYC that is generated along with the TSC will indicate the number of cycles actively tracing (those
powered up, with TriggerEn=1) executed between the last CYC packet and the TSC packet. And hence the amount
of time spent while tracing is inactive can be inferred from the difference in time between that expected based on
the CYC value, and the actual time indicated by the TSC.
Additional CYC packets may be sent stand-alone, so that the processor can ensure that the decoder is aware of the
number of cycles that have passed before the internal hardware counter wraps, or is reset due to other microarchitectural condition. There is no guarantee at what intervals these standalone CYC packets will be sent, except
that they will be sent before the wrap occurs. An illustration is given below.
1. Table 36-13 documents support for the MSRs defining address ranges 0 and 1. Processors that provide XSAVE support for Intel Processor
Trace support only those address ranges.
Vol. 3C 36-31
INTEL® PROCESSOR TRACE
Example 36-1. An Illustrative CYC Packet Example
Time (cycles)
Instruction Snapshot
Generated Packets
Comment
x
call %eax
CYC(?), TIP
?Elapsed cycles from the previous CYC unknown
x+2
call %ebx
CYC(2), TIP
1 byte CYC packet; 2 cycles elapsed from the previous CYC
x+8
jnz Foo (not taken)
CYC(6)
1 byte CYC packet
x+9
ret (compressed)
x + 12
jnz Bar (taken)
x + 16
ret (uncompressed)
TNT, CYC(8), TIP
1 byte CYC packet
x + 4111
CYC(4095)
2 byte CYC packet
x + 12305
CYC(8194)
3 byte CYC packet
CYC(4027), PIP
2 byte CYC packet
x + 16332
36.3.6.1
mov cr3, %ebx
Cycle Counter
The cycle counter is implemented in hardware (independent of the time stamp counter or performance monitoring
counters), and is a simple incrementing counter that does not saturate, but rather wraps. The size of the counter is
implementation specific.
The cycle counter is reset to zero any time that TriggerEn is cleared, and when a CYC packet is sent. The cycle
counter will continue to count when ContextEn or FilterEn are cleared, and cycle packets will still be generated. It
will not count during sleep states that result in Intel PT logic being powered-down, but will count up to the point
where clocks are disabled, and resume counting once they are re-enabled.
36.3.6.2
Cycle Packet Semantics
Cycle-accurate mode adheres to the following protocol:
•
•
All packets that precede a CYC packet represent instructions or events that took place before the CYC time.
•
The CYC-eligible packet that immediately follows a CYC packet represents an instruction or event that took
place at the same time as the CYC time.
All packets that follow a CYC packet represent instructions or events that took place at the same time as, or
after, the CYC time.
These items above give the decoder a means to apply CYC packets to a specific instruction in the assembly stream.
Most packets represent a single instruction or event, and hence the CYC packet that precedes each of those packets
represents the retirement time of that instruction or event. In the case of TNT packets, up to 6 conditional branches
and/or compressed RETs may be contained in the packet. In this case, the preceding CYC packet provides the
retirement time of the first branch in the packet. It is possible that multiple branches retired in the same cycle as
that first branch in the TNT, but the protocol will not make that obvious. Also note that a MTC packet could be
generated in the same cycle as the first JCC in the TNT packet. In this case, the CYC would precede both the MTC
and the TNT, and apply to both.
Note that there are times when the cycle counter will stop counting, though cycle-accurate mode is enabled. After
any such scenario, a CYC packet followed by TSC packet will be sent. See Section 36.8.3.2 to understand how to
interpret the payload values
Multi-packet Instructions or Events
Some operations, such as interrupts or task switches, generate multiple packets. In these cases, multiple CYC
packets may be sent for the operation, preceding each CYC-eligible packet in the operation. An example, using a
task switch on a software interrupt, is shown below.
36-32 Vol. 3C
INTEL® PROCESSOR TRACE
Example 36-2. An Example of CYC in the Presence of Multi-Packet Operations
Time (cycles)
Instruction Snapshot
Generated Packets
x
jnz Foo (not taken)
x+2
ret (compressed)
x+8
jnz Bar (taken)
x+9
jmp %eax
TNT, CYC(9), TIP
x + 12
jnz Bar (not taken)
CYC(3)
x + 32
int3 (task gate)
TNT, FUP, CYC(10), PIP, CYC(20), MODE.Exec, TIP
36.3.6.3
CYC(?),
Cycle Thresholds
Software can opt to reduce the frequency of cycle packets, a trade-off to save bandwidth and intrusion at the
expense of precision. This is done by utilizing a cycle threshold (see Section 36.2.7.2).
IA32_RTIT_CTL.CycThresh indicates to the processor the minimum number of cycles that must pass before the
next CYC packet should be sent. If this value is 0, no threshold is used, and CYC packets can be sent every cycle in
which a CYC-eligible packet is generated. If this value is greater than 0, the hardware will wait until the associated
number of cycles have passed since the last CYC packet before sending another. CPUID provides the threshold
options for CycThresh, see Section 36.3.1.
Note that the cycle threshold does not dictate how frequently a CYC packet will be posted, it merely assigns the
maximum frequency. If the cycle threshold is 16, a CYC packet can be posted no more frequently than every 16
cycles. However, once that threshold of 16 cycles has passed, it still requires a new CYC-eligible packet to be generated before a CYC will be inserted. Table 36-14 illustrates the threshold behavior.
Table 36-14. An Illustrative CYC Packet Example
Time (cycles)
Instruction Snapshot
Threshold
0
16
32
64
x
jmp %eax
CYC, TIP
CYC, TIP
CYC, TIP
CYC, TIP
x+9
call %ebx
CYC, TIP
TIP
TIP
TIP
x + 15
call %ecx
CYC, TIP
TIP
TIP
TIP
x + 30
jmp %edx
CYC, TIP
CYC, TIP
TIP
TIP
x + 38
mov cr3, %eax
CYC, PIP
PIP
CYC, PIP
PIP
x + 46
jmp [%eax]
CYC, TIP
CYC, TIP
TIP
TIP
x + 64
call %edx
CYC, TIP
CYC, TIP
TIP
CYC,TIP
x + 71
jmp %edx
CYC, TIP
TIP
CYC,TIP
TIP
36.3.7
Decoder Synchronization (PSB+)
The PSB packet (Section 36.4.2.17) serves as a synchronization point for a trace-packet decoder. It is a pattern in
the trace log for which the decoder can quickly scan to align packet boundaries. No legal packet combination can
result in such a byte sequence. As such, it serves as the starting point for packet decode. To decode a trace log
properly, the decoder needs more than simply to be aligned: it needs to know some state and potentially some
timing information as well. The decoder should never need to retain any information (e.g., LastIP, call stack,
compound packet event) across a PSB; all compound packet events will be completed before a PSB, and any
compression state will be reset.
When a PSB packet is generated, it is followed by a PSBEND packet (Section 36.4.2.18). One or more packets may
be generated in between those two packets, and these inform the decoder of the current state of the processor.
These packets, known collectively as PSB+, should be interpreted as “status only”, since they do not imply any
change of state at the time of the PSB, nor are they associated directly with any instruction or event. Thus, the
Vol. 3C 36-33
INTEL® PROCESSOR TRACE
normal binding and ordering rules that apply to these packets outside of PSB+ can be ignored when these packets
are between a PSB and PSBEND. They inform the decoder of the state of the processor at the time of the PSB.
PSB+ can include:
•
•
•
Timestamp (TSC), if IA32_RTIT_CTL.TSCEn=1.
•
VMCS packet, if either the logical is in VMX root operation or the logical processor is in VMX non-root operation
and the “conceal VMX non-root operation from Intel PT” VM-execution control is 0.
•
•
•
•
Core Bus Ratio (CBR).
Timestamp-MTC Align (TMA), if IA32_RTIT_CTL.TSCEn=1 && IA32_RTIT_CTL.MTCEn=1.
Paging Info Packet (PIP), if ContextEn=1 and IA32_RTIT_CTL.OS=1. The non-root bit (NR) is set if the logical
processor is in VMX non-root operation and the “conceal VMX non-root operation from Intel PT”. VM-execution
control is 0.
MODE.TSX, if ContextEn=1 and BranchEn = 1.
MODE.Exec, if PacketEn=1.
Flow Update Packet (FUP), if PacketEn=1.
PSB is generated only when TriggerEn=1; hence PSB+ has the same dependencies. The ordering of packets within
PSB+ is not fixed. Timing packets such as CYC and MTC may be generated between PSB and PSBEND, and their
meanings are the same as outside PSB+.
Note that an overflow can occur during PSB+, and this could cause the PSBEND packet to be lost. For this reason,
the OVF packet should also be viewed as terminating PSB+.
36.3.8
Internal Buffer Overflow
In the rare circumstances when new packets need to be generated but the processor’s dedicated internal buffers
are all full, an “internal buffer overflow” occurs. On such an overflow packet generation ceases (as packets would
need to enter the processor’s internal buffer) until the overflow resolves. Once resolved, packet generation
resumes.
When the buffer overflow is cleared, an OVF packet (Section 36.4.2.16) is generated, and the processor ensures
that packets which follow the OVF are not compressed (IP compression or RET compression) against packets that
were lost.
If IA32_RTIT_CTL.BranchEn = 1, the OVF packet will be followed by a FUP if the overflow resolves while PacketEn=1. If the overflow resolves while PacketEn = 0 no packet is generated, but a TIP.PGE will naturally be generated later, once PacketEn = 1. The payload of the FUP or TIP.PGE will be the Current IP of the first instruction upon
which tracing resumes after the overflow is cleared. Between the OVF and following FUP or TIP.PGE, there may be
packets that do not depend on PacketEn, such as timing packets. If the overflow resolves while PacketEn=0, other
packets that are not dependent on PacketEn may come before the TIP.PGE.
36.3.8.1
Overflow Impact on Enables
The address comparisons to ADDRn ranges, for IP filtering and TraceStop (Section 36.2.4.3), continue during a
buffer overflow, and TriggerEn, ContextEn, and FilterEn may change during a buffer overflow. Like other packets,
however, any TIP.PGE or TIP.PGD packets that would have been generated will be lost. Further,
IA32_RTIT_STATUS.PacketByteCnt will not increment, since it is only incremented when packets are generated.
If a TraceStop event occurs during the buffer overflow, IA32_RTIT_STATUS.Stopped will still be set, tracing will
cease as a result. However, the TraceStop packet, and any TIP.PGD that result from the TraceStop, may be
dropped.
36.3.8.2
Overflow Impact on Timing Packets
Any timing packets that are generated during a buffer overflow will be dropped. If only a few MTC packets are
dropped, a decoder should be able to detect this by noticing that the time value in the first MTC packet after the
buffer overflow incremented by more than one. If the buffer overflow lasted long enough that 256 MTC packets are
lost (and thus the MTC packet ‘wraps’ its 8-bit CTC value), then the decoder may be unable to properly understand
36-34 Vol. 3C
INTEL® PROCESSOR TRACE
the trace. This is not an expected scenario. No CYC packets are generated during overflow, even if the cycle
counter wraps.
Note that, if cycle-accurate mode is enabled, the OVF packet will generate a CYC packet. Because the cycle counter
counts during overflows, this CYC packet can provide the duration of the overflow. However, there is a risk that the
cycle counter wrapped during the overflow, which could render this CYC misleading.
36.3.9
Operational Errors
Errors are detected as a result of packet output configuration problems, which can include output alignment issues,
ToPA reserved bit violations, or overlapping packet output with restricted memory. See “ToPA Errors” in Section
36.2.6.2 for details on ToPA errors, and Section 36.2.6.4 for details on restricted memory errors. Operational
errors are only detected and signaled when TraceEn=1.
When an operational error is detected, tracing is disabled and the error is logged. Specifically,
IA32_RTIT_STATUS.Error is set, which will cause IA32_RTIT_STATUS.TriggerEn to be 0. This will disable generation of all packets. Some causes of operational errors may lead to packet bytes being dropped.
It should be noted that the timing of error detection may not be predictable. Errors are signaled when the
processor encounters the problematic configuration. This could be as soon as packet generation is enabled but
could also be later when the problematic entry or field needs to be used.
Once an error is signaled, software should disable packet generation by clearing TraceEn, diagnose and fix the error
condition, and clear IA32_RTIT_STATUS.Error. At this point, packet generation can be re-enabled.
36.4
TRACE PACKETS AND DATA TYPES
This section details the data packets generated by Intel Processor Trace. It is useful for developers writing the
interpretation code that will decode the data packets and apply it to the traced source code.
36.4.1
Packet Relationships and Ordering
This section introduces the concept of packet “binding”, which involves determining the IP in a binary disassembly
at which the change indicated by a given packet applies. Some packets have the associated IP as the payload (FUP,
TIP), while for others the decoder need only search for the next instance of a particular instruction (or instructions)
to bind the packet (TNT). However, in many cases, the decoder will need to consider the relationship between
packets, and to use this packet context to determine how to bind the packet.
Section 36.4.2 below provides detailed descriptions of the packets, including how packets bind to IPs in the disassembly, to other packets, or to nothing at all. Many packets listed are simple to bind, because they are generated
in only a few scenarios. Those that require more consideration are typically part of “compound packet events”, such
as interrupts, exceptions, and some instructions, where multiple packets are generated by a single operation
(instruction or event). These compound packet events frequently begin with a FUP to indicate the source address
(if it is not clear from the disassembly), and are concluded by a TIP or TIP.PGD packet that indicates the destination
address (if one is provided). In this scenario, the FUP is said to be “coupled” with the TIP packet.
Other packets could be in between the coupled FUP and TIP packet. Timing packets, such as TSC, MTC, CYC, or
CBR, could arrive at any time, and hence could intercede in a compound packet event. If an operation changes CR3
or the processor’s mode of execution, a state update packet (i.e., PIP or MODE) is generated. The state changes
indicated by these intermediate packets should be applied at the IP of the TIP* packet. A summary of compound
packet events is provided in Table 36-15; see Section 36.4.2 for more per-packet details and Section 36.7 for more
detailed packet generation examples.
Vol. 3C 36-35
INTEL® PROCESSOR TRACE
Table 36-15. Compound Packet Event Summary
Event Type
Beginning
Middle
Unconditional FUP or none
,
uncompresse
d control-flow
transfer
TSX Update
Overflow
36.4.2
End
Comment
Any combination
of PIP, VMCS,
MODE.Exec, or
none
TIP or TIP.PGD
FUP only for asynchronous events. Order of middle packets
may vary.
MODE.TSX, and
(FUP or none)
None
TIP, TIP.PGD, or
none
FUP
OVF
PSB, PSBEND, or
none
FUP or TIP.PGE
FUP if overflow resolves while ContextEn=1, else TIP.PGE.
PIP/VMCS/MODE only if the operation modifies the state
tracked by these respective packets
TIP/TIP.PGD only for TSX abort cases
Packet Definitions
The following description of packet definitions are in tabular format. Figure 36-3 explains how to interpret them.
Packet bits listed as “RSVD” are not guaranteed to be 0.
Byte Number
Name
Header bits
in Green
Bit Number
Payload in White
Packet name
Packet Format
7
6
5
4
3
2
1
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
0
1
1
0
2
0
1
0
0
0
1
1
0
Description of fields
Dependencies
Depends on packet generation configuration enable controls or other
bits (Section 36.2.5).
Generation Scenario
Which instructions, events, or other
scenarios can cause this packet to be
generated.
Description
Description of the packet, including the purpose it serves, meaning of the information or payload, etc
Application
How a decoder should apply this packet. It may bind to a specific instruction from the binary, or to
another packet in the stream, or have other implications on decode
Figure 36-3. Interpreting Tabular Definition of Packet Format
36.4.2.1
Taken/Not-taken (TNT) Packet
Table 36-16. TNT Packet Definition
Name
Taken/Not-taken (TNT) Packet
Packet Format
0
36-36 Vol. 3C
7
6
5
4
3
2
1
0
1
B1
B2
B3
B4
B5
B6
0
Short TNT
INTEL® PROCESSOR TRACE
Table 36-16. TNT Packet Definition (Contd.)
B1…BN represent the last N conditional branch or compressed RET (Section 36.4.2.2) results, such that B1 is oldest
and BN is youngest. The short TNT packet can contain from 1 to 6 TNT bits. The long TNT packet can contain up
from 1 to 47 TNT bits.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
1
2
B40
B41
B42
B43
B44
B45
B46
B47
3
B32
B33
B34
B35
B36
B37
B38
B39
4
B24
B25
B26
B27
B28
B29
B30
B31
5
B16
B17
B18
B19
B20
B21
B22
B23
6
B8
B9
B10
B11
B12
B13
B14
B15
7
1
B1
B2
B3
B4
B5
B6
B7
Long TNT
Irrespective of how many TNT bits is in a packet, the last valid TNT bit is followed by a trailing 1, or Stop bit, as
shown above. If the TNT packet is not full (fewer than 6 TNT bits for the Short TNT, or fewer than 47 TNT bits for
the Long TNT), the Stop bit moves up, and the trailing bits of the packet are filled with 0s. Examples of these
“partial TNTs” are shown below.
0
7
6
5
4
3
2
1
0
0
0
1
B1
B2
B3
B4
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
1
2
B24
B25
B26
B27
B28
B29
B30
B31
3
B16
B17
B18
B19
B20
B21
B22
B23
4
B8
B9
B10
B11
B12
B13
B14
B15
5
1
B1
B2
B3
B4
B5
B6
B7
6
0
0
0
0
0
0
0
0
7
0
0
0
0
0
0
0
0
Generation
Scenario
Short TNT
Long TNT
Dependencies
PacketEn
On a conditional branch or compressed RET, if it fills the TNT.
Also, partial TNTs may be generated at any time, as a result of
other packets being generated,
or certain micro-architectural conditions occurring, before the
TNT is full.
Description
Provides the taken/not-taken results for the last 1–N conditional branches (Jcc, J*CXZ, or LOOP) or compressed RETs
(Section 36.4.2.2). The TNT payload bits should be interpreted as follows:
• 1 indicates a taken conditional branch, or a compressed RET
• 0 indicates a not-taken conditional branch
Application
Each valid payload bit (that is, bits between the header bits and the trailing Stop bit) applies to an upcoming conditional branch or RET instruction. Once a decoder consumes a TNT packet with N valid payload bits, these bits should
be applied to (and hence provide the destination for) the next N conditional branches or RETs
Vol. 3C 36-37
INTEL® PROCESSOR TRACE
36.4.2.2
Target IP (TIP) Packet
Table 36-17. IP Packet Definition
Name
Target IP (TIP) Packet
Packet Format
7
6
0
IPBytes
1
TargetIP[7:0]
2
TargetIP[15:8]
3
TargetIP[23:16]
4
TargetIP[31:24]
5
TargetIP[39:32]
6
TargetIP[47:40]
7
TargetIP[55:48]
8
TargetIP[63:56]
5
Generation Scenario
4
3
2
1
0
0
1
1
0
1
Dependencies
PacketEn
Indirect branch (including un-compressed RET), far branch, interrupt,
exception, INIT, SIPI, (VM exit, VM entry,)1 TSX abort, (EENTER, EEXIT,
ERESUME, AEX)2.
Description
Provides the target for some control flow transfers
Application
Anytime a TIP is encountered, it indicates that control was transferred to the IP provided in the payload.
The source of this control flow change, and hence the IP or instruction to which it binds, depends on the packets
that precede the TIP. If a TIP is encountered and all preceding packets have already been bound, then the TIP will
apply to the upcoming indirect branch, far branch, or VMRESUME. However, if there was a preceding FUP that
remains unbound, it will bind to the TIP. Here, the TIP provides the target of an asynchronous event or TSX abort
that occurred at the IP given in the FUP payload. Note that there may be other packets, in addition to the FUP, which
will bind to the TIP packet. See the packet application descriptions for other packets for details.
NOTES:
1. If IA32_VMX_MISC[bit 14] reports 1.
2. In a debug enclave.
IP Compression
The IP payload in a TIP. FUP, TIP.PGE, or TIP.PGD packet can vary in size, based on the mode of execution, and the
use of IP compression. IP compression is an optional compression technique the processor may choose to employ
to reduce bandwidth. With IP compression, the IP to be represented in the payload is compared with the last IP
sent out, via any of FUP, TIP, TIP.PGE, or TIP.PGD. If that previous IP had the same upper (most significant) address
bytes, those matching bytes may be suppressed in the current packet. The processor maintains an internal state of
the “Last IP” that was encoded in trace packets, thus the decoder will need to keep track of the “Last IP” state in
software, to match fidelity with packets generated by hardware. “Last IP” is initialized to zero, hence if the first IP
in the trace may be compressed if the upper bytes are zeroes.
The “IPBytes” field of the IP packets (FUP, TIP, TIP.PGE, TIP.PGD) serves to indicate how many bytes of payload are
provided, and how the decoder should fill in any suppressed bytes. The algorithm for reconstructing the IP for a
TIP/FUP packet is shown in the table below.
36-38 Vol. 3C
INTEL® PROCESSOR TRACE
Table 36-18. FUP/TIP IP Reconstruction
IPBytes
Uncompressed IP Value
63:56
55:48
000b
None, IP is out of context
001b
Last IP[63:16]
010b
Last IP[63:32]
47:40
39:32
31:24
23:16
15:8
7:0
IP Payload[15:0]
IP Payload[31:0]
011b
IP Payload[47] extended
IP Payload[47:0]
100b
Last IP [63:48]
IP Payload[47:0]
101b
Reserved
110b
IP Payload[63:0]
111b
Reserved
The processor-internal Last IP state is guaranteed to be reset to zero when a PSB is sent out. This means that the
IP that follows the PSB with either be un-compressed (011b or 110b, see Table 36-18), or compressed against
zero.
At times, “IPbytes” will have a value of 0. As shown above, this does not mean that the IP payload matches the full
address of the last IP, but rather that the IP for this packet was suppressed. This is used for cases where the IP that
applies to the packet is out of context. An example is the TIP.PGD sent on a SYSCALL, when tracing only USR code.
In that case, no TargetIP will be included in the packet, since that would expose an instruction point at CPL = 0.
When the IP payload is suppressed in this manner, Last IP is not cleared, and instead refers to the last IP packet
with a non-zero IPBytes field.
On processors that support a maximum linear address size of 32 bits, IP payloads may never exceed 32 bits
(IPBytes <= 010b).
Indirect Transfer Compression for Returns (RET)
In addition to IP compression, TIP packets for near return (RET) instructions can also be compressed. If the RET
target matches the next IP of the corresponding CALL, then the TIP packet is unneeded, since the decoder can
deduce the target IP by maintaining a CALL/RET stack of its own.
A CALL/RET stack can be maintained by the decoder by doing the following:
1. Allocate space to store 64 RET targets.
2. For near CALLs, push the Next IP onto the stack. Once the stack is full, new CALLs will force the oldest entry off
the end of the stack, such that only the youngest 64 entries are stored. Note that this excludes zero-length
CALLs, which are direct near CALLs with displacement zero (to the next IP). These CALLs typically don’t have
matching RETs.
3. For near RETs, pop the top (youngest) entry off the stack. This will be the target of the RET.
In cases where the RET is compressed, the target is guaranteed to match the value produced in 2) above. If the
target is not compressed, a TIP packet will be generated with the RET target, which may differ from 2).
The hardware ensure that packets read by the decoder will always have seen the CALL that corresponds to any
compressed RET. The processor will never compress a RET across a PSB, a buffer overflow, or scenario where PacketEn=0. This means that a RET whose corresponding CALL executed while PacketEn=0, or before the last PSB, etc.,
will not be compressed.
If the CALL/RET stack is manipulated or corrupted by software, and thereby causes a RET to transfer control to a
target that is inconsistent with the CALL/RET stack, then the RET will not be compressed, and will produce a TIP
packet. This can happen, for example, if software executes a PUSH instruction to push a target onto the stack, and
a later RET uses this target.
When a RET is compressed, a Taken indication is added to the TNT buffer. Because it sends no TIP packet, it also
does not update the internal Last IP value, and thus the decoder should treat it the same way. If the RET is not
compressed, it will generate a TIP packet (just like when RET compression is disabled, via
IA32_RTIT_CTL.DisRETC). For processors that employ deferred TIPs (Section 36.4.2.3), an uncompressed RET will
not be deferred, and hence will force out any accumulated TNTs or TIPs. This serves to avoid ambiguity, and make
Vol. 3C 36-39
INTEL® PROCESSOR TRACE
clear to the decoder whether the near RET was compressed, and hence a bit in the in-progress TNT should be
consumed, or uncompressed, in which case there will be no in-progress TNT and thus a TIP should be consumed.
Note that in the unlikely case that a RET executes in a different execution mode than the associated CALL, the
decoder will need to model the same behavior with its CALL stack. For instance, if a CALL executes in 64-bit mode,
a 64-bit IP value will be pushed onto the software stack. If the corresponding RET executes in 32-bit mode, then
only the lower 32 target bits will be popped off of the stack, which may mean that the RET does not go to the CALL’s
Next IP. This is architecturally correct behavior, and this RET could be compressed, thus the decoder should match
this behavior
36.4.2.3
Deferred TIPs
The processor may opt to defer sending out the TNT when TIPs are generated. Thus, rather than sending a partial
TNT followed by a TIP, both packets will be deferred while the TNT accumulates more Jcc/RET results. Any number
of TIP packets may be accumulated this way, such that only once the TNT is filled, or once another packet (e.g.,
FUP) is generated, the TNT will be sent, followed by all the deferred TIP packets, and finally terminated by the other
packet(s) that forced out the TNT and TIP packets. Generation of many other packets (see list below) will force out
the TNT and any accumulated TIP packets. This is an optional optimization in hardware to reduce the bandwidth
consumption, and hence the performance impact, incurred by tracing.
Table 36-19. TNT Examples with Deferred TIPs
Code Flow
Packets, Non-Deferred TIPS
Packets, Deferred TIPS
0x1000 cmp %rcx, 0
0x1004 jnz Foo // not-taken
0x1008 jmp %rdx
TNT(0b0), TIP(0x1308)
0x1308 cmp %rcx, 1
0x130c jnz Bar // not-taken
0x1310 cmp %rcx, 2
0x1314 jnz Baz // taken
0x1500 cmp %eax, 7
0x1504 jg Exit // not-taken
TNT(0b010), TIP(0x1100)
0x1508 jmp %r15
0x1100 cmp %rbx, 1
0x1104 jg Start // not-taken
0x1108 add %rcx, %eax
0x110c … // an asynchronous Interrupt arrives
INThandler:
0xcc00 pop %rdx
36-40 Vol. 3C
TNT(0b0), FUP(0x110c),
TIP(0xcc00)
TNT(0b00100), TIP(0x1308),
TIP(0x1100), FUP(0x110c),
TIP(0xcc00)
INTEL® PROCESSOR TRACE
36.4.2.4
Packet Generation Enable (TIP.PGE)
Table 36-20. TIP.PGE Packet Definition
Name
Target IP - Packet Generation Enable (TIP.PGE)
Packet Format
7
6
0
IPBytes
1
TargetIP[7:0]
2
TargetIP[15:8]
3
TargetIP[23:16]
4
TargetIP[31:24]
5
TargetIP[39:32]
6
TargetIP[47:40]
7
TargetIP[55:48]
8
TargetIP[63:56]
5
4
3
2
1
0
1
0
0
0
1
Dependencies
PacketEn transitions to 1
Generation
Scenario
Any branch instruction, control flow transfer, or MOV
CR3 that sets PacketEn, a WRMSR that enables
packet generation and sets PacketEn
Description
Indicates that PacketEn has transitioned to 1. It provides the IP at which the tracing begins.
This can occur due to any of the enables that comprise PacketEn transitioning from 0 to 1, as long as all the others
are asserted. Examples:
• TriggerEn: This is set on software write to set IA32_RTIT_CTL.TraceEn as long as the Stopped and Error bits in
IA32_RTIT_STATUS are clear. The IP payload will be the Next IP of the WRMSR.
• FilterEn: This is set when software jumps into the tracing region. This region is defined by enabling IP filtering in
IA32_RTIT_CTL.ADDRn_CFG, and defining the range in IA32_RTIT_ADDRn_[AB], see. Section 36.2.4.3. The
IP payload will be the target of the branch.
• ContextEn: This is set on a CPL change, a CR3 write or any other means of changing ContextEn. The IP payload
will be the Next IP of the instruction that changes context if it is not a branch, otherwise it will be the target of
the branch.
Application
TIP.PGE packets bind to the instruction at the IP given in the payload.
Vol. 3C 36-41
INTEL® PROCESSOR TRACE
36.4.2.5
Packet Generation Disable (TIP.PGD)
Table 36-21. TIP.PGD Packet Definition
Name
Target IP - Packet Generation Disable (TIP.PGD)
Packet Format
7
6
5
0
IPBytes
1
TargetIP[7:0]
2
TargetIP[15:8]
3
TargetIP[23:16]
4
TargetIP[31:24]
5
TargetIP[39:32]
6
TargetIP[47:40]
7
TargetIP[55:48]
8
TargetIP[63:56]
3
2
1
0
0
0
0
0
1
Dependencies
PacketEn transitions to
0
Description
Indicates that PacketEn has transitioned to 0. It will include the IP at which the tracing ends, unless ContextEn= 0 or
TraceEn=0 at the conclusion of the instruction or event that cleared PacketEn.
PacketEn can be cleared due to any of the enables that comprise PacketEn transitioning from 1 to 0. Examples:
• TriggerEn: This is cleared on software write to clear IA32_RTIT_CTL.TraceEn, or when
IA32_RTIT_STATUS.Stopped is set, or on operational error. The IP payload will be suppressed in this case, and the
“IPBytes” field will have the value 0.
• FilterEn: This is set when software jumps out of the tracing region. This region is defined by enabling IP filtering
in IA32_RTIT_CTL.ADDRn_CFG, and defining the range in IA32_RTIT_ADDRn_[AB], see. Section 36.2.4.3.
The IP payload will depend on the type of the branch. For conditional branches, the payload is
suppressed (IPBytes = 0), and in this case the destination can be inferred from the disassembly. For any other
type of branch, the IP payload will be the target of the branch.
• ContextEn: This can happen on a CPL change, a CR3 write or any other means of changing ContextEn. See
Section 36.2.4.3 for details. In this case, when ContextEn is cleared, there will be no IP payload. The “IPBytes”
field will have value 0.
Note that, in cases where a branch that would normally produce a TIP packet (i.e., far transfer, indirect branch, interrupt, etc) or TNT update (conditional branch or compressed RT) causes PacketEn to transition from 1 to 0, the TIP or
TNI bit will be replaced with TIP.PGD. The payload of the TIP.PGD will be the target of the branch, unless the result
of the instruction causes TraceEn or ContextEn to be cleared (ie, SYSCALL when IA32_RTIT_CTL.OS=0, In the case
where a conditional branch clears FilterEn and hence PacketEn, there will be no TNT bit for this branch, replaced
instead by the TIP.PGD.
Application
TIP.PGD can be produced by any branch instructions, as well as some non-branch instructions, that clear PacketEn.
When produced by a branch, it replaces any TIP or TNT update that the branch would normally produce.
In cases where there is an unbound FUP preceding the TIP.PGD, then the TIP.PGD is part of compound operation (i.e.,
asynchronous event or TSX abort) which cleared PacketEn. For most such cases, the TIP.PGD is simply replacing a
TIP, and should be treated the same way. The TIP.PGD may or may not have an IP payload, depending on whether
the operation cleared ContextEn.
If there is not an associated FUP, the binding will depend on whether there is an IP payload. If there is an IP payload,
then the TIP.PGD should be applied to either the next direct branch whose target matches the TIP.PGD payload, or
the next branch that would normally generate a TIP or TNT packet. If there is no IP payload, then the TIP.PGD should
apply to the next branch or MOV CR3 instruction.
36-42 Vol. 3C
Generation
Scenario
4
Any branch instruction, control flow transfer, or MOV CR3 that clears
PacketEn, a WRMSR that disables packet generation and clears PacketEn
INTEL® PROCESSOR TRACE
36.4.2.6
Flow Update (FUP) Packet
Table 36-22. FUP Packet Definition
Name
Flow Update (FUP) Packet
Packet Format
7
0
IPBytes
1
IP[7:0]
2
IP[15:8]
3
IP[23:16]
4
IP[31:24]
5
IP[39:32]
6
IP[47:40]
7
IP[55:48]
8
IP[63:56]
6
5
Generation
Scenario
4
3
2
1
0
1
1
1
0
1
Dependencies
TriggerEn & ContextEn.
(Typically depends on
BranchEn and FilterEn as well,
see Section 36.2.4 for details.)
Asynchronous Events (interrupts, exceptions, INIT, SIPI, SMI, VM
exit1, #MC), XBEGIN, XEND, XABORT, XACQUIRE, XRELEASE, (EENTRY, EEXIT, ERESUME, EEE, AEX,)2, INT 0, INT 3, INT n, a WRMSR that
disables packet generation.
Description
Provides the source address for asynchronous events, and some other instructions. Is never sent alone, always sent
with an associated TIP or MODE packet, and potentially others.
Application
FUP packets provide the IP to which they bind. However, they are never standalone, but are coupled with other
packets.
In TSX cases, the FUP is immediately preceded by a MODE.TSX, which binds to the same IP. A TIP will follow only in
the case of TSX aborts, see Section 36.4.2.8 for details.
Otherwise, FUPs are part of compound packet events (see Section 36.4.1). In these compound cases, the FUP provides the source IP for an instruction or event, while a following TIP (or TIP.PGD) uop will provide any destination IP.
Other packets may be included in the compound event between the FUP and TIP.
NOTES:
1. If IA32_VMX_MISC[bit 14] reports 1.
2. If Intel Software Guard Extensions is supported.
Vol. 3C 36-43
INTEL® PROCESSOR TRACE
FUP IP Payload
Flow Update Packet gives the source address of an instruction when it is needed. In general, branch instructions do
not need a FUP, because the source address is clear from the disassembly. For asynchronous events, however, the
source address cannot be inferred from the source, and hence a FUP will be sent. Table 36-23 illustrates cases
where FUPs are sent, and which IP can be expected in those cases.
Table 36-23. FUP Cases and IP Payload
Event
Flow Update IP
Comment
External Interrupt, NMI/SMI, Traps,
Machine Check (trap-like), INIT/SIPI
Address of next instruction (Next IP) that
would have been executed
Functionally, this matches the LBR FROM field
value and also the EIP value which is saved onto
the stack.
Exceptions/Faults, Machine check
(fault-like)
Address of the instruction which took the
This matches the similar functionality of LBR
FROM field value and also the EIP value which is
saved onto the stack.
Software Interrupt
Address of the software interrupt instruction
(Current IP)
This matches the similar functionality of LBR
FROM field value, but does not match the EIP
value which is saved onto the stack (Next
Linear Instruction Pointer - NLIP).
EENTER, EEXIT, ERESUME, Enclave
Exiting Event (EEE), AEX1
Current IP of the instruction
This matches the LBR FROM field value and also
the EIP value which is saved onto the stack.
XACQUIRE
Address of the X* instruction
XRELEASE, XBEGIN, XEND,
XABORT, other transactional abort
Current IP
#SMI
IP that is saved into SMRAM
WRMSR that clears TraceEn
Current IP
exception/fault (Current IP)
NOTES:
1. Information on EENTER, EEXIT, ERESUME, EEE, Asynchronous Enclave eXit (AEX) can be found in Intel® Software Guard Extensions Programming Reference.
On a canonical fault due to sequentially fetching an instruction in non-canonical space (as opposed to jumping to
non-canonical space), the IP of the fault (and thus the payload of the FUP) will be a non-canonical address. This is
consistent with what is pushed on the stack for such faulting cases.
If there are post-commit task switch faults, the IP value of the FUP will be the original IP when the task switch
started. This is the same value as would be seen in the LBR_FROM field. But it is a different value as is saved on the
stack or VMCS.
36-44 Vol. 3C
INTEL® PROCESSOR TRACE
36.4.2.7
Paging Information (PIP) Packet
Table 36-24. PIP Packet Definition
Name
Paging Information (PIP) Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
2
CR3[11:5] or 0
3
CR3[19:12]
4
CR3[27:20]
5
CR3[35:28]
6
CR3[43:36]
7
CR3[51:44]
0
1
RSVD/NR
Dependencies
TriggerEn && ContextEn &&
IA32_RTIT_CTL.OS
Generation
Scenario
MOV CR3, Task switch, INIT, SIPI, PSB+;
If IA32_VMX_MISC[bit 14] reports 1: VM exit, VM entry
Description
The CR3 payload shown includes only the address portion of the CR3 value. For PAE paging, CR3[11:5] are thus
included. For other page modes (32-bit and IA-32e paging), these bits are 0.
This packet holds the CR3 address value. It will be generated on operations that modify CR3:
• MOV CR3 operation
• Task Switch
• INIT and SIPI
• VM exit and VM entry, if appropriate controls in the VMCS are clear (see Section 36.5.1)
PIPs are not generated, despite changes to CR3, on SMI and RSM. This is due to the special behavior on these operations, see Section for details. Note that, for some cases of task switch where CR3 is not modified, no PIP will be
produced.
The purpose of the PIP is to indicate to the decoder which application is running, so that it can apply the proper
binaries to the linear addresses that are being traced.
The PIP packet contains the new CR3 value when CR3 is written.
PIPs generated by VM entries set the NR bit. PIPs generated in VMX non-root operation set the NR bit if the “conceal VMX non-root operation from Intel PT” VM-execution control is 0. All other PIPs clear the NR bit.
Application
The purpose of the PIP packet is to help the decoder uniquely identify what software is running at any given time.
When a PIP is encountered, a decoder should do the following:
1) If there was a prior unbound FUP (that is, a FUP not preceded by a packet such as MODE.TSX that consumes it,
and it hence pairs with a TIP that has not yet been seen), then this PIP is part of a compound packet event (Section
36.4.1). Find the ending TIP and apply the new CR3/NR values to the TIP payload IP.
2) Otherwise, look for the next MOV CR3, far branch, or VMRESUME/VMLAUNCH in the disassembly, and apply the
new CR3 to the next (or target) IP.
For examples of the packets generated by these flows, see Section 36.7.
Vol. 3C 36-45
INTEL® PROCESSOR TRACE
36.4.2.8
MODE Packets
MODE packets keep the decoder informed of various processor modes about which it needs to know in order to
properly manage the packet output, or to properly disassemble the associated binaries. MODE packets include a
header and a mode byte, as shown below.
Table 36-25. General Form of MODE Packets
7
6
5
4
3
2
1
0
0
1
0
0
1
1
0
0
1
1
Leaf ID
Mode
The MODE Leaf ID indicates which set of mode bits are held in the lower bits.
MODE.Exec Packet
Table 36-26. MODE.Exec Packet Definition
Name
MODE.Exec Packet
Packet Format
7
6
5
4
3
2
1
0
0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
CS.D
(CS.L & LMA)
Dependencies
PacketEn
Generation
Scenario
Description
Indicates whether software is in 16, 32, or 64-bit mode, by providing the CS.D and (CS.L & IA32_EFER.LMA) values.
Essential for the decoder to properly disassemble the associated binary.
Far branch, interrupt, exception, (VM exit, VM entry,)1 if the mode changes.
PSB+, and any scenario that can generate a TIP.PGE, such that the mode may have
changed since the last MODE.Exec.
CS.D
(CS.L & IA32_EFER.LMA)
Addressing Mode
1
1
N/A
0
1
64-bit mode
1
0
32-bit mode
0
0
16-bit mode
MODE.Exec is sent at the time of a mode change, if PacketEn=1 at the time, or when tracing resumes, if necessary.
In the former case, the MODE.Exec packet is generated along with other packets that result from the far transfer
operation that changes the mode. In cases where the mode changes while PacketEn=0, the processor will send out
a MODE.Exec along with the TIP.PGE when tracing resumes. The processor may opt to suppress the MODE.Exec
when tracing resumes if the mode matches that from the last MODE.Exec packet, if there was no PSB in between.
Application
MODE.Exec always immediately precedes a TIP or TIP.PGE. The mode change applies to the IP address in the payload
of the next TIP or TIP.PGE.
NOTES:
1. If IA32_VMX_MISC[bit 14] reports 1.
36-46 Vol. 3C
INTEL® PROCESSOR TRACE
MODE.TSX Packet
Table 36-27. MODE.TSX Packet Definition
Name
MODE.TSX Packet
Packet Format
7
6
5
4
3
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
1
0
TXAbort
InTX
Dependencies
TriggerEn and ContextEn
Description
Indicates when a TSX transaction (either HLE or RTM) begins, commits, or aborts. Instructions executed transactionally will be “rolled back” if the transaction is aborted.
TXAbort
Application
InTX
Generation
Scenario
2
XBEGIN, XEND, XABORT, XACQUIRE, XRELEASE, if INTX
changes, Asynchronous TSX Abort, PSB+
Implication
1
1
N/A
0
1
Transaction begins, or executing transactionally
1
0
Transaction aborted
0
0
Transaction committed, or not executing transactionally
If PacketEn=1, MODE.TSX always immediately precedes a FUP. If the TXAbort bit is zero, then the mode change
applies to the IP address in the payload of the FUP. If TXAbort=1, then the FUP will be followed by a TIP, and the
mode change will apply to the IP address in the payload of the TIP.
MODE.TSX packets may be generated when PacketEn=0, due to FilterEn=0. In this case, only the last MODE.TSX
generated before TIP.PGE need be applied.
Vol. 3C 36-47
INTEL® PROCESSOR TRACE
36.4.2.9
TraceStop Packet
Table 36-28. TraceStop Packet Definition
Name
TraceStop Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
Dependencies
TriggerEn && ContextEn
Generation
Scenario
Taken branch with target in TraceStop IP region, MOV CR3 in TraceStop IP region, or WRMSR that sets TraceEn in TraceStop IP region.
Description
Indicates when software has entered a user-configured TraceStop region.
When the IP matches a TraceStop range while ContextEn and TriggerEn are set, a TraceStop action occurs. This disables tracing by setting IA32_RTIT_STATUS.Stopped, thereby clearing TriggerEn, and causes a TraceStop
packet to be generated.
The TraceStop action also forces FilterEn to 0. Note that TraceStop may not force a flush of internally buffered
packets, and thus trace packet generation should still be manually disabled by clearing IA32_RTIT_CTL.TraceEn
before examining output. See Section 36.2.4.3 for more details.
Application
.If TraceStop follows a TIP.PGD (before the next TIP.PGE), then it was triggered either by the instruction that cleared
PacketEn, or it was triggered by some later instruction that executed while FilterEn=0. In either case, the TraceStop
can be applied at the IP of the TIP.PGD (if any).
If TraceStop follows a TIP.PGE (before the next TIP.PGD), it should be applied at the last known IP.
36.4.2.10 Core:Bus Ratio (CBR) Packet
Table 36-29. CBR Packet Definition
Name
Core:Bus Ratio (CBR) Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
2
Core:Bus Ratio
3
Reserved
Dependencies
TriggerEn
Description
Indicates the core:bus ratio of the processor core. Useful for correlating wall-clock time and cycle time.
Application
All packets following the CBR represent instructions that executed with the new core:bus ratio, while all preceding
packets (aside from timing packets) represent instructions that executed with the prior ratio. There is not a precise
IP provided, to which to bind the CBR packet.
36-48 Vol. 3C
Generation
Scenario
After any frequency change, on C-state wake up, PSB+, and after
enabling trace packet generation.
INTEL® PROCESSOR TRACE
36.4.2.11 Timestamp Counter (TSC) Packet
Table 36-30. TSC Packet Definition
Name
Timestamp Counter (TSC) Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
1
1
SW TSC[7:0]
2
SW TSC[15:8]
3
SW TSC[23:16]
4
SW TSC[31:24]
5
SW TSC[39:32]
6
SW TSC[47:40]
7
SW TSC[55:48]
Dependencies
IA32_RTIT_CTL.TSCEn &&
TriggerEn
Generation
Scenario
Sent after any event that causes the processor clocks or Intel PT timing
packets (such as MTC or CYC) to stop, This may include P-state changes,
wake from C-state, or clock modulation. Also on transition of TraceEn
from 0 to 1.
Description
When enabled by software, a TSC packet provides the lower 7 bytes of the current TSC value, as returned by the
RDTSC instruction. This may be useful for tracking wall-clock time, and synchronizing the packets in the log with
other timestamped logs.
Application
TSC packet provides a wall-clock proxy of the event which generated it (packet generation enable, sleep state wake,
etc). In all cases, TSC does not precisely indicate the time of any control flow packets; however, all preceding packets
represent instructions that executed before the indicated TSC time, and all subsequent packets represent instructions that executed after it. There is not a precise IP to which to bind the TSC packet.
Vol. 3C 36-49
INTEL® PROCESSOR TRACE
36.4.2.12 Mini Time Counter (MTC) Packet
Table 36-31. MTC Packet Definition
Name
Mini time Counter (MTC) Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
1
0
1
1
0
0
1
1
CTC[N+7:N]
Dependencies
IA32_RTIT_CTL.MTCEn &&
TriggerEn
Description
When enabled by software, an MTC packet provides a periodic indication of wall-clock time. The 8-bit CTC (Common
Timestamp Copy) payload value is set to (ART >> N) & 0xFF. The frequency of the ART is related to the Maximum
Non-Turbo frequency, and the ratio can be determined from CPUID leaf 15H, as described in Section 36.8.3.
Software can select the threshold N, which determines the MTC frequency by setting the IA32_RTIT_CTL.MTCFreq
field (see Section 36.2.7.2) to a supported value using the lookup enumerated by CPUID (see Section 36.3.1).
See Section 36.8.3 for details on how to use the MTC payload to track TSC time.
MTC provides 8 bits from the ART, starting with the bit selected by MTCFreq to dictate the frequency of the packet.
Whenever that 8-bit range being watched changes, an MTC packet will be sent out with the new value of that 8-bit
range. This allows the decoder to keep track of how much wall-clock time has elapsed since the last TSC packet was
sent, by keeping track of how many MTC packets were sent and what their value was. The decoder can infer the
truncated bits, CTC[N-1:0], are 0 at the time of the MTC packet.
There are cases in which MTC packet can be dropped, due to overflow or other micro-architectural conditions. The
decoder should be able to recover from such cases by checking the 8-bit payload of the next MTC packet, to determine how many MTC packets were dropped. It is not expected that >256 consecutive MTC packets should ever be
dropped.
Application
MTC does not precisely indicate the time of any other packet, nor does it bind to any IP. However, all preceding packets represent instructions or events that executed before the indicated ART time, and all subsequent packets represent instructions that executed after, or at the same time as, the ART time.
36-50 Vol. 3C
Generation
Scenario
Periodic, based on the core crystal clock, or Always Running Timer
(ART).
INTEL® PROCESSOR TRACE
36.4.2.13 TSC/MTC Alignment (TMA) Packet
Table 36-32. TMA Packet Definition
Name
TSC/MTC Alignment (TMA) Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
0
1
1
2
CTC[7:0]
3
CTC[15:8]
4
Reserved
5
FastCounter[7:0]
6
Reserved
0
FC[8]
Dependencies
IA32_RTIT_CTL.MTCEn &&
IA32_RTIT_CTL.TSCEn && TriggerEn
Generation Scenario
Sent with any TSC packet.
Description
The TMA packet serves to provide the information needed to allow the decoder to correlate MTC packets with TSC
packets. With this packet, when a MTC packet is encountered, the decoder can determine how many timestamp
counter ticks have passed since the last TSC or MTC packet. See Section 36.8.3.2 for details on how to make this calculation.
Application
TMA is always sent immediately following a TSC packet, and the payload values are consistent with the TSC payload
value. Thus the application of TMA matches that of TSC.
Vol. 3C 36-51
INTEL® PROCESSOR TRACE
36.4.2.14 Cycle Count Packet (CYC) Packet
Table 36-33. Cycle Count Packet Definition
Name
Cycle Count (CYC) Packet
Packet Format
7
6
5
4
3
2
1
0
Exp
1
1
0
Cycle Counter[4:0]
1
Cycle Counter[11:5]
Exp
2
Cycle Counter[18:12]
Exp
...
... (if Exp = 1 in the previous byte)
Dependencies
IA32_RTIT_CTL.CYCEn &&
TriggerEn
Description
The Cycle Counter field increments at the same rate as the processor core clock ticks, but with a variable length format (using a trailing EXP bit field) and a range-capped byte length.
If the CYC value is less than 32, a 1-byte CYC will be generated, with Exp=0. If the CYC value is between 32 and
4095 inclusive, a 2-byte CYC will be generated, with byte 0 Exp=1 and byte 1 Exp=0. And so on.
CYC provides the number of core clocks that have passed since the last CYC packet. CYC can be configured to be
sent in every cycle in which an eligible packet is generated, or software can opt to use a threshold to limit the number of CYC packets, at the expense of some precision. These settings are configured using the
IA32_RTIT_CTL.CycThresh field (see Section 36.2.7.2). For details on Cycle-Accurate Mode, IPC calculation, etc, see
Section 36.3.6.
When CycThresh=0, and hence no threshold is in use, then a CYC packet will be generated in any cycle in which any
CYC-eligible packet is generated. The CYC packet will precede the other packets generated in the cycle, and provides
the precise cycle time of the packets that follow.
In addition to these CYC packets generated with other packets, CYC packets can be sent stand-alone. These packets
serve simply to update the decoder with the number of cycles passed, and are used to ensure that a wrap of the
processor’s internal cycle counter doesn’t cause cycle information to be lost. These stand-alone CYC packets do not
indicate the cycle time of any other packet or operation, and will be followed by another CYC packet before any
other CYC-eligible packet is seen.
When CycThresh>0, CYC packets are generated only after a minimum number of cycles have passed since the last
CYC packet. Once this threshold has passed, the behavior above resumes, where CYC will either be sent in the next
cycle that produces other CYC-eligible packets, or could be sent stand-alone.
When using CYC thresholds, only the cycle time of the operation (instruction or event) that generates the CYC
packet is truly known. Other operations simply have their execution time bounded: they completed at or after the
last CYC time, and before the next CYC time.
Application
CYC provides the offset cycle time (since the last CYC packet) for the CYC-eligible packet that follows. If another CYC
is encountered before the next CYC-eligible packet, the cycle values should be accumulated and applied to the next
CYC-eligible packet.
If a CYC packet is generated by a TNT, note that the cycle time provided by the CYC packet applies to the first
branch in the TNT packet.
36-52 Vol. 3C
Generation Sce- Can be sent at any time, though a maximum of one CYC packet is
nario
sent per core clock cycle. See Section 36.3.6 for CYC-eligible packets.
INTEL® PROCESSOR TRACE
36.4.2.15 VMCS Packet
Table 36-34. VMCS Packet Definition
Name
VMCS Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
0
2
VMCS Base Address [19:12]
3
VMCS Base Address [27:20]
4
VMCS Base Address [35:28]
5
VMCS Base Address [43:36]
6
VMCS Base Address [51:44]
Dependencies
TriggerEn && ContextEn;
Also in VMX operation.
Generation Scenario
Generated on successful VMPTRLD, and optionally on SMM VM
exits and VM entries that return from SMM (see Section 36.5).
Description
The VMCS packet provides an address related to a VMCS pointer for a decoder to determine the transition of code
contexts:
•
On a successful VMPTRLD (i.e., a VMPTRLD that doesn’t fault, fail, or VM exit), the VMCS packet contains the
address of the current working VMCS pointer of the logical processor that will execute a VM guest context.
•
On SMM VM exits, the VMCS packet provides the STM VMCS base address (SMM Transfer VMCS pointer), if VMCSbased controls are clear (see Section 36.5.1). See Section 36.6 on tracing inside and outside STM.
•
On VM entries that return from SMM, the VMCS packet provides the current working VMCS pointer of the guest
VM (see Section 36.6), if VMCS-based controls are clear (see Section 36.5.1). Root versus Non-Root operation can
be distinguished from the PIP.NR bit.
If a VMCS packet is generated before a VMCS has been loaded, or after it has been cleared, the base address value
will be all 1s.
VMCS packets will not be seen on processors with IA32_VMX_MISC[bit 14]=0, as these processors do not allow
TraceEn to be set in VMX operation.
Application
The purpose of the VMCS packet is to help the decoder uniquely identify changes in the executing software context
in situations that CR3 may not be unique.
When a VMCS is encountered, a decoder should do the following:
• If there was a prior unbound FUP (that is, a FUP not preceded by a packet such as MODE.TSX that consumes it, and
it hence pairs with a TIP that has not yet been seen), then this VMCS is part of a compound packet event (Section
36.4.1). Find the ending TIP and apply the new VMCS base pointer value to the TIP payload IP.
• Otherwise, look for the next VMPTRLD, VMRESUME, or VMLAUNCH in the disassembly, and apply the new VMCS
base pointer on the next VM entry.
For examples of the packets generated by these flows, see Section 36.7.
Vol. 3C 36-53
INTEL® PROCESSOR TRACE
36.4.2.16 Overflow (OVF) Packet
Table 36-35. OVF Packet Definition
Name
Overflow (OVF) Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
Dependencies
TriggerEn
Generation
Scenario
On resolution of internal buffer overflow
Description
OVF simply indicates to the decoder that an internal buffer overflow occurred, and packets were likely lost. If
BranchEN= 1, OVF is followed by a FUP or TIP.PGE which will provide the IP at which packet generation resumes. See
Section 36.3.8.
Application
When an OVF packet is encountered, the decoder should skip to the IP given in the subsequent FUP or TIP.PGE. The
cycle counter for the CYC packet will be reset at the time the OVF packet is sent.
Software should reset its call stack depth on overflow, since no RET compression is allowed across an overflow. Similarly, any IP compression that follows the OVF is guaranteed to use as a reference LastIP the IP payload of an IP
packet that preceded the overflow.
36.4.2.17 Packet Stream Boundary (PSB) Packet
Table 36-36. PSB Packet Definition
Name
Packet Stream Boundary (PSB) Packet
Packet Format
36-54 Vol. 3C
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
0
3
1
0
0
0
0
0
1
0
4
0
0
0
0
0
0
1
0
5
1
0
0
0
0
0
1
0
6
0
0
0
0
0
0
1
0
7
1
0
0
0
0
0
1
0
8
0
0
0
0
0
0
1
0
9
1
0
0
0
0
0
1
0
10
0
0
0
0
0
0
1
0
11
1
0
0
0
0
0
1
0
12
0
0
0
0
0
0
1
0
13
1
0
0
0
0
0
1
0
14
0
0
0
0
0
0
1
0
15
1
0
0
0
0
0
1
0
INTEL® PROCESSOR TRACE
Table 36-36. PSB Packet Definition (Contd.)
Dependencies
TriggerEn
Generation
Scenario
Periodic, based on the number of output bytes generated while tracing. PSB is sent
when IA32_RTIT_STATUS.PacketByteCnt=0, and each time it crosses the software
selected threshold after that. May be sent for other micro-architectural conditions
as well.
Description
PSB is a unique pattern in the packet output log, and hence serves as a sync point for the decoder. It is a pattern
that the decoder can search for in order to get aligned on packet boundaries. This packet is periodic, based on the
number of output bytes, as indicated by IA32_RTIT_STATUS.PacketByteCnt. The period is chosen by software, via
IA32_RTIT_CTL.PSBFreq (see Section 36.2.7.2). Note, however, that the PSB period is not precise, it simply reflects
the average number of output bytes that should pass between PSBs. The processor will make a best effort to
insert PSB as quickly after the selected threshold is reached as possible. The processor also may send extra
PSB packets for some micro-architectural conditions.
PSB also serves as the leading packet for a set of “status-only” packets collectively known as PSB+ (Section 36.3.7).
Application
When a PSB is seen, the decoder should interpret all following packets as “status only”, until either a PSBEND or
OVF packet is encountered. “Status only” implies that the binding and ordering rules to which these packets normally adhere are ignored, and the state they carry can instead be applied to the IP payload in the FUP packet that is
included.
36.4.2.18 PSBEND Packet
Table 36-37. PSBEND Packet Definition
Name
PSBEND Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
1
Dependencies
TriggerEn
Generation
Scenario
Always follows PSB packet, separated by PSB+ packets
Description
PSBEND is simply a terminator for the series of “status only” (PSB+) packets that follow PSB (Section 36.3.7).
Application
When a PSBEND packet is seen, the decoder should cease to treat packets as “status only”.
Vol. 3C 36-55
INTEL® PROCESSOR TRACE
36.4.2.19 Maintenance (MNT) Packet
Table 36-38. MNT Packet Definition
Name
Maintenance (MNT) Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
1
1
2
1
0
0
0
1
0
0
0
3
Payload[7:0]
4
Payload[15:8]
5
Payload[23:16]
6
Payload[31:24]
7
Payload[39:32]
8
Payload[47:40]
9
Payload[55:48]
10
Payload[63:56]
Dependencies
TriggerEn
Generation Scenario
Implementation specific.
Description
This packet is generated by hardware, the payload meaning is model-specific.
Application
Unless a decoder has been extended for a particular family/model/stepping to interpret MNT packet payloads, this
packet should simply be ignored. It does not bind to any IP.
36.4.2.20 PAD Packet
Table 36-39. PAD Packet Definition
Name
PAD Packet
Packet Format
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Dependencies
TriggerEn
Description
PAD is simply a NOP packet. Processor implementations may choose to add pad packets to improve packet alignment or for implementation-specific reasons.
Application
Ignore PAD packets.
36-56 Vol. 3C
Generation
Scenario
Implementation specific
INTEL® PROCESSOR TRACE
36.4.2.21 PTWRITE Packet
Table 36-40. PTW Packet Definition
Name
PTW Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
IP
PayloadBytes
1
0
0
1
0
2
Payload[7:0]
3
Payload[15:8]
4
Payload[23:16]
5
Payload[31:24]
6
Payload[39:32]
7
Payload[47:40]
8
Payload[55:48]
9
Payload[63:56]
The PayloadBytes field indicates the number of bytes of payload that follow the header bytes. Encodings are as follows:
PayloadBytes
Bytes of Payload
‘00
4
‘01
8
‘10
Reserved
‘11
Reserved
IP bit indicates if a FUP, whose payload will be the IP of the PTWRITE instruction, will follow.
Dependencies
TriggerEn & ContextEn & FilterEn
& PTWEn
Generation
Scenario
PTWRITE Instruction
Description
Contains the value held in the PTWRITE operand.
This packet is CYC-eligible, and hence will generate a CYC packet if IA32_RTIT_CTL.CYCEn=1 and any CYC Threshold
has been reached.
Application
Binds to the associated PTWRITE instruction. The IP of the PTWRITE will be provided by a following FUP, when
PTW.IP=1.
Vol. 3C 36-57
INTEL® PROCESSOR TRACE
36.4.2.22 Execution Stop (EXSTOP) Packet
Table 36-41. EXSTOP Packet Definition
Name
EXSTOP Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
IP
1
1
0
0
0
1
0
IP bit indicates if a FUP will follow.
Dependencies
TriggerEn & PwrEvtEn
Description
This packet indicates that software execution has stopped due to processor clock powerdown. Later packets will
indicate when execution resumes.
If EXSTOP is generated while ContextEn is set, the IP bit will be set, and EXSTOP will be followed by a FUP packet
containing the IP at which execution stopped. More precisely, this will be the IP of the oldest instruction that has
not yet completed.
This packet is CYC-eligible, and hence will generate a CYC packet if IA32_RTIT_CTL.CYCEn=1 and any CYC Threshold
has been reached.
Application
If a FUP follows EXSTOP (hence IP bit set), the EXSTOP can be bound to the FUP IP. Otherwise the IP is not known.
Time of powerdown can be inferred from the preceding CYC, if CYCEn=1. Combined with the TSC at the time of
wake (if TSCEn=1), this can be used to determine the duration of the powerdown.
36-58 Vol. 3C
Generation
Scenario
C-state entry, P-state change, or other processor clock powerdown. Includes :
• Entry to C-state deeper than C0.0
• TM1/2
• STPCLK#
• Frequency change due to IA32_CLOCK_MODULATION, Turbo
INTEL® PROCESSOR TRACE
36.4.2.23 MWAIT Packet
Table 36-42. MWAIT Packet Definition
Name
MWAIT Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
2
MWAIT Hints[7:0]
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
Reserved
9
Reserved
EXT[1:0]
Dependencies
TriggerEn & PwrEvtEn & ContextEn
Generation
Scenario
MWAIT instruction, or I/O redirection to MWAIT, that complete
without fault or VMexit.
Description
Indicates that an MWAIT operation to C-state deeper than C0.0 completed. The MWAIT hints and extensions passed
in by software are exposed in the payload.
This packet is CYC-eligible, and hence will generate a CYC packet if IA32_RTIT_CTL.CYCEn=1 and any CYC Threshold
has been reached.
Application
The MWAIT packet should bind to the IP of the next FUP, which will be the IP of the instruction that caused the
MWAIT. This FUP will be shared with EXSTOP.
Vol. 3C 36-59
INTEL® PROCESSOR TRACE
36.4.2.24 Power Entry (PWRE) Packet
Table 36-43. PWRE Packet Definition
Name
PWRE Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
2
HW
Reserved
3
Resolved Thread C-State
Dependencies
TriggerEn & PwrEvtEn
Description
Indicates processor entry to the resolved thread C-state and sub C-state indicated. The processor will remain in this
C-state until either another PWRE indicates the processor has moved to a C-state deeper than C0.0, or a PWRX
packet indicates a return to C0.
Note that some CPUs may allow MWAIT to request a deeper C-state than is supported by the core. These deeper Cstates may have platform-level implications that differentiate them. However, the PWRE packet will provide only
the resolved thread C-state, which will not exceed that supported by the core.
If the C-state entry was initiated by hardware, rather than a direct software request (such as MWAIT, HLT, or shutdown), the HW bit will be set to indicate this. Hardware Duty Cycling (see Section 14.5, “Hardware Duty Cycling
(HDC)” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B) is an example of such a
case.
Application
When transitioning from C0.0 to a deeper C-state, the PWRE packet will be followed by an EXSTOP. If that EXSTOP
packet has the IP bit set, then the following FUP will provide the IP at which the C-state entry occurred. Subsequent
PWRE packets generated before the next PWRX should bind to the same IP.
36-60 Vol. 3C
Generation
Scenario
Resolved Thread Sub C-State
Transition to a C-state deeper than C0.0.
INTEL® PROCESSOR TRACE
36.4.2.25 Power Exit (PWRX) Packet
Table 36-44. PWRX Packet Definition
Name
PWRX Packet
Packet Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
2
Last Core C-State
Deepest Core C-State
3
Reserved
Wake Reason
4
Reserved
5
Reserved
6
Reserved
Dependencies
TriggerEn & PwrEvtEn
Description
Indicates processor return to thread C0 from a C-state deeper than C0.0.
The Last Core C-State field provides the MWAIT encoding for the core C-state at the time of the wake. The Deepest
Core C-State provides the MWAIT encoding for the deepest core C-state achieved during the sleep session, or since
leaving thread C0. MWAIT encodings for C-states can be found in Table 4-11 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B. Note that these values reflect only the core C-state, and hence will
not exceed the maximum supported core C-state, even if deeper C-states can be requested.
The Wake Reason field is one-hot, encoded as follows:
Application
36.5
Generation
Scenario
Transition from a C-state deeper than C0.0 to C0.
Bit
Field
Meaning
0
Interrupt
Wake due to external interrupt received.
1
Reserved
2
Store to Monitored Address
Wake due to store to monitored address.
3
HW Wake
Wake due to hardware autonomous condition,
such as HDC.
PWRX will always apply to the same IP as the PWRE. The time of wake can be discerned from (optional) timing packets that precede PWRX.
TRACING IN VMX OPERATION
On processors that IA32_VMX_MISC[bit 14] reports 1, TraceEn can be set in VMX operation. A series of mechanisms exist to allow the VMM to configure tracing based on the desired trace domain, and on the consumer of the
trace output. The VMM can configure specific VM-execution controls to control what virtualization-specific data are
included within the trace packets (see Section 36.5.1 for details). MSR save and load lists can be employed by the
VMM to restrict tracing to the desired context (see Section 36.5.2 for details). These configuration options are
summarized in Table 36-45. Table 36-45 covers common Intel PT usages while SMIs are handled by the default
SMM treatment. Tracing with SMM Transfer Monitor is described in Section 36.6.
Vol. 3C 36-61
INTEL® PROCESSOR TRACE
Table 36-45. Common Usages of Intel PT and VMX
Target Domain
Output
Consumer
Virtualize
Output
Configure VMCS
Controls
TraceEN Configuration
Save/Restore MSR states
of Trace Configuration
System-Wide
(VMM + VMs)
Host
NA
Default Setting
(no suppression)
WRMSR or XRSTORS by Host
NA
VMM Only
Intel PT Aware
VMM
NA
Enable
suppression
MSR load list to disable tracing in
VM, enable tracing on VM exits
NA
VM Only
Intel PT Aware
VMM
NA
Enable
suppression
MSR load list to enable tracing in
VM, disable tracing on VM exits
NA
Intel PT Aware
Guest(s)
Per Guest
VMM adds
trace output
virtualization
Enable
suppression
MSR load list to enable tracing in
VM, disable tracing on VM exits
VMM Update guest state
on XRSTORS-exiting VM
exits
36.5.1
VMX-Specific Packets and VMCS Controls
In all of the usages of VMX and Intel PT, the decoder in the host or VMM context can identify the occurrences of VMX
transitions with the aid of VMX-specific packets. Packets relevant to VMX fall into the follow two kinds:
•
VMCS Packet: The VMX transitions of individual VM can be distinguished by a decoder using the base address
field in a VMCS packet. The base address field stores the VMCS pointer address of a successful VMPTRLD. A
VMCS packet is sent on a successful execution of VMPTRLD. See Section 36.4.2.15 for details.
•
NonRoot (NR) bit field in PIP packet: PIP packets are generated with each VM entry/exit. The NR bit in a PIP
packet is set when in VMX non-Root operation. Thus a transition of the NR bit from 0 to 1 indicates the
occurrence of a VM entry, and a transition of 1 to 0 indicates the occurrence of a VM exit.
Processors with IA32_VMX_MISC[bit 14]= 1 also provides VMCS controls that a VMM can configure to prevent
VMX-specific information from leaking across virtualization boundaries.
Table 36-46. VMCS Controls For Intel Processor Trace
Name
Conceal VMX
non-root
operation from
Intel PT
Type
VM-execution
control
Bit
Position
19
Value
0
Behavior
PIPs generated in VM non-root operation will set the PIP.NR bit.
PSB+ in VMX non-root operation will include the VMCS packet, to ensure
that the decoder knows which guest is currently in use.
1
PIPs generated in VMX non-root operation will not set the PIP.NR bit.
PSB+ in VMX non-root operation will not include the VMCS packet.
Conceal VM
exits from Intel
PT
VM-exit control
Conceal VM
entries from
Intel PT
VM-entry control
24
0
PIPs are generated on VM exit, with NonRoot=0.
On VM exit to SMM, VMCS packets are additionally generated.
17
1
No PIP is generated on VM exit, and no VMCS packet is generated on
VM exit to SMM.
0
PIPs are generated on VM entry, with NonRoot=1 if the destination of
the VM entry is VMX non-root operation.
On VM entry to SMM, VMCS packets are additionally generated.
1
No PIP is generated on VM entry, and no VMCS packet is generated on
VM entry to SMM.
The default setting for the VMCS controls that interacts with Intel PT is to enable all VMX-specific packet information. The scenarios that would use the default setting also do not require the VMM to use MSR load list to manage
the configuration of turning-on/off of trace packet generation across VM exits.
If IA32_VMX_MISC[bit 14] reports 0, any attempt to set the VMCS control bits in Table 36-46 will result in a failure
on guest entry.
36-62 Vol. 3C
INTEL® PROCESSOR TRACE
36.5.2
Managing Trace Packet Generation Across VMX Transitions
In tracing scenarios that collect packets for both VMX root operation and VMX non-root operation, a host executive
can manage the MSRs associated with trace packet generation directly. The states of these MSRs need not be
modified using MSR load list or MSR save list across VMX transitions.
For tracing scenarios that collect only packets within either VMX root operation or VMX non-root operation, the
VMM can use the MSR load list and/or MSR save list to toggle IA32_RTIT_CTL.TraceEn.
36.5.2.1
System-Wide Tracing
When a host or VMM configures Intel PT to collect trace packets of the entire system, it can leave the VMCS controls
clear to allow VMX-specific packets to provide information across VMX transitions. MSR load list is not used across
VM exits or VM entries, nor is VM-exit MSR save list.
The decoder will desire to identify the occurrence of VMX transitions. The packets of interests to a decoder are
shown in Table 36-47.
Table 36-47. Packets on VMX Transitions (System-Wide Tracing)
Event
VM exit
Packets
Description
FUP(GuestIP)
The FUP indicates at which point in the guest flow the VM exit occurred. This is important,
since VM exit can be an asynchronous event. The IP will match that written into the VMCS.
PIP(HostCR3, NR=0)
The PIP packet provides the new host CR3 value, as well as indication that the logical processor
is entering VMX root operation. This allows the decoder to identify the change of executing
context from guest to host and load the appropriate set of binaries to continue decode.
TIP(HostIP)
The TIP indicates the destination IP, the IP of the first instruction to be executed in VMX root
operation.
Note, this packet could be preceded by a MODE.Exec packet (Section 36.4.2.8). This is
generated only in cases where CS.D or (CS.L & EFER.LMA) change during the transition.
VM entry
PIP(GuestCR3, NR=1)
The PIP packet provides the new guest CR3 value, as well as indication that the logical
processor is entering VMX non-root operation. This allows the decoder to identify the change
of executing context from host to guest and load the appropriate set of binaries to continue
decode.
TIP(GuestIP)
The TIP indicates the destination IP, the IP of the first instruction to be executed in VMX nonroot operation. This should match the IP value read out from the VMCS.
Note, this packet could be preceded by a MODE.Exec packet (Section 36.4.2.8). This is
generated only in cases where CS.D or (CS.L & EFER.LMA) change during the transition.
Since the packet suppression controls are cleared, the VMCS packet will be included in all PSB+ for this usage
scenario. Thus the decoder can distinguish the execution context of different VMs. Additionally, it will be generated
on VMPTRLD. Thus the decoder can distinguish the execution context of different VMs.
When the host VMM configures a system to collect trace packets in this scenario, it should emulate CPUID to report
CPUID.(EAX=07H, ECX=0):EBX[bit 26] with 0 to guests, indicating to guests that Intel PT is not available.
VMX TSC Manipulation
The TSC packets generated while in VMX non-root operation will include any changes resulting from the use of a
VMM’s use of the TSC offsetting or TSC scaling VMCS control (see Chapter 25, “VMX Non-Root Operation”). In this
system-wide usage model, the decoder may need to account for the effect of per-VM adjustments in the TSC
packets generated in VMX non-root operation and the absence of TSC adjustments in TSC packets generated in
VMX root operation. The VMM can supply this information to the decoder.
36.5.2.2
Host-Only Tracing
When trace packets in VMX non-root operation are not desired, the VMM can use VM-entry MSR load list with
IA32_RTIT_CTL.TraceEn=0 to disable trace packet generation in guests, set IA32_RTIT_CTL.TraceEn=1 via VMexit MSR load list.
Vol. 3C 36-63
INTEL® PROCESSOR TRACE
When tracing only the host, the decoder does not need information about the guests, the VMCS controls for
suppressing VMX-specific packets can be set to reduce the packets generated. VMCS packets will still be generated
on successful VMPTRLD and in PSB+ generated in the Host, but these will be unused by the decoder.
The packets of interests to a decoder when trace packets are collected for host-only tracing are shown in Table 3648.
Table 36-48. Packets on VMX Transitions (Host-Only Tracing)
Event
VM exit
Packets
TIP.PGE(HostIP)
Description
The TIP.PGE indicates that trace packet generation is enabled and gives the IP of the first
instruction to be executed in VMX root operation.
Note, this packet could be preceded by a MODE.Exec packet (Section 36.4.2.8). This is
generated only in cases where CS.D or (CS.L & EFER.LMA) change during the transition.
VM entry
36.5.2.3
TIP.PGD()
The TIP indicates that trace packet generation was disabled. This ensure that all buffered
packets are flushed out.
Guest-Only Tracing
A VMM can configure trace packet generation while in non-root operation for guests executing normally. This is
accomplished by utilizing the MSR load lists across VM exit and VM entry to confine trace packet generation to
stay within the guest environment.
For this usage, the VM-entry MSR load list is programmed to turn on trace packet generation. The VM-exit MSR
load list is used to clear TraceEn=0 to disable trace packet generation in the host. Further, if it is preferred that
the guest packet stream contain no indication that execution was in VMX non-root operation, the VMM should set
the VMCS controls described in Table 36-46.
36.5.2.4
Virtualization of Guest Output Packet Streams
Each Intel PT aware guest OS can produce one or more output packet streams to destination addresses specified
as guest physical address (GPA) using context-switched IA32_RTIT_OUTPUT_BASE within the guest. The processor
generates trace packets to the platform physical address specified in IA32_RTIT_OUTPUT_BASE, and those specified in the ToPA tables. Thus, a VMM that supports Intel PT aware guest OS may wish to virtualize the output configurations of IA32_RTIT_OUTPUT_BASE and ToPA for each trace configuration state of all the guests.
36.5.2.5
Emulation of Intel PT Traced State
If a VMM emulates an element of processor state by taking a VM exit on reads and/or writes to that piece of state,
and the state element impacts Intel PT packet generation or values, it may be incumbent upon the VMM to insert
or modify the output trace data.
If a VM exit is taken on a guest write to CR3 (including “MOV CR3” as well as task switches), the PIP packet
normally generated on the CR3 write will be missing.
To avoid decoder confusion when the guest trace is decoded, the VMM should emulate the missing PIP by writing it
into the guest output buffer. If the guest CR3 value is manipulated, the VMM may also need to manipulate the
IA32_RTIT_CR3_MATCH value, in order to ensure the trace behavior matches the guest's expectation.
Similarly, if a VMM emulates the TSC value by taking a VM exit on RDTSC, the TSC packets generated in the trace
may mismatch the TSC values returned by the VMM on RDTSC. To ensure that the trace can be properly aligned
with software logs based on RDTSC, the VMM should either make corresponding modifications to the TSC packet
values in the guest trace, or use mechanisms such as TSC offsetting or TSC scaling in place of exiting.
36.5.2.6
TSC Scaling
When TSC scaling is enabled for a guest using Intel PT, the VMM should ensure that the value of Maximum NonTurbo Ratio[15:8] in MSR_PLATFORM_INFO (MSR 0CEH) and the TSC/”core crystal clock” ratio (EBX/EAX) in CPUID
leaf 15H are set in a manner consistent with the resulting TSC rate that will be visible to the VM. This will allow the
decoder to properly apply TSC packets, MTC packets (based on the core crystal clock or ART, whose frequency is
indicated by CPUID leaf 15H), and CBR packets (which indicate the ratio of the processor frequency to the Max
36-64 Vol. 3C
INTEL® PROCESSOR TRACE
Non-Turbo frequency). Absent this, or separate indication of the scaling factor, the decoder will be unable to properly track time in the trace. See Section 36.8.3 for details on tracking time within an Intel PT trace.
36.5.2.7
Failed VM Entry
The packets generated by a failed VM entry depend both on the VMCS configuration, as well as on the type of
failure. The results to expect are summarized in the table below. Note that packets in italics may or may not be
generated, depending on implementation choice, and the point of failure.
Table 36-49. Packets on a Failed VM Entry
Usage Model
Entry Configuration
Early Failure (fall
through to Next IP)
Late Failure (VM exit)
System-Wide
No MSR load list
TIP (NextIP)
PIP(Guest CR3, NR=1), TraceEn 0->1 Packets (See Section
36.2.7.3), PIP(HostCR3, NR=0), TIP(HostIP)
VMM Only
MSR load list
disables TraceEn
TIP (NextIP)
TraceEn 0->1 Packets (See Section 36.2.7.3), TIP(HostIP)
VM Only
MSR load list
Enables TraceEn
None
None
36.5.2.8
VMX Abort
VMX abort conditions take the processor into a shutdown state. On a VM exit that leads to VMX abort, some packets
(FUP, PIP) may be generated, but any expected TIP, TIP.PGE, or TIP.PGD may be dropped.
36.6
TRACING AND SMM TRANSFER MONITOR (STM)
SMM Transfer Monitor is a VMM that operates inside SMM while in VMX root operation. An STM operates in conjunction with an executive monitor. The latter operates outside SMM and in VMX root operation. Transitions from the
executive monitor or its VMs to the STM are called SMM VM exits. The STM returns from SMM via a VM entry to the
VM in VMX non-root operation or the executive monitor in VMX root operation.
Intel PT supports tracing in an STM similar to tracing support for VMX operation as described above in Section 36.7.
As a result, on a SMM VM exit resulting from #SMI, TraceEn is not saved and then cleared. Software can save the
state of the trace configuration MSRs and clear TraceEn using the MSR load/save lists.
36.7
PACKET GENERATION SCENARIOS
Table 36-50 and Table 36-52 illustrate the packets generated in various scenarios. In the heading row, PacketEn is
abbreviated as PktEn, ContextEn as CntxEn. Note that this assumes that TraceEn=1 in IA32_RTIT_CTL, while TriggerEn=1 and Error=0 in IA32_RTIT_STATUS, unless otherwise specified. Entries that do not matter in packet
generation are marked “D.C.” Packets followed by a “?” imply that these packets depend on additional factors,
which are listed in the “Other Dependencies” column.
In Table 36-50, PktEn is evaluated based on TiggerEn & ContextEn & FilterEn & BranchEn.
Table 36-50. Packet Generation under Different Enable Conditions
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
1a
Normal non-jump operation
0
0
D.C.
None
1b
Normal non-jump operation
1
1
1
None
2a
WRMSR/XRSTORS/RSM that changes
0
TraceEn 0 -> 1, with PacketByteCnt >0
0
D.C.
*TSC if TSCEn=1;
*TMA if TSCEn=MTCEn=1
TSC?, TMA?, CBR
Vol. 3C 36-65
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
2b
WRMSR/XRSTORS/RSM that changes
0
TraceEn 0 -> 1, with PacketByteCnt =0
0
D.C.
*TSC if TSCEn=1;
*TMA if TSCEn=MTCEn=1
PSB, PSBEND (see Section 36.4.2.17)
2d
WRMSR/XRSTORS/RSM that changes
0
TraceEn 0 -> 1, with PacketByteCnt >0
1
1
TSC if TSCEn=1;
TMA if TSCEn=MTCEn=1
TSC?, TMA?, CBR,
MODE.Exec, TIP.PGE(NLIP)
2e
WRMSR/XRSTORS/RSM that changes
0
TraceEn 0 -> 1, with PacketByteCnt =0
1
1
MODE.Exec,
TIP.PGE(NLIP), PSB,
PSBEND (see Section
36.4.2.8, 36.4.2.7,
36.4.2.13,36.4.2.15,
36.4.2.17)
3a
WRMSR that changes TraceEn 1 -> 0
0
0
D.C.
None
3b
WRMSR that changes TraceEn 1 -> 0
1
0
D.C.
FUP(CLIP), TIP.PGD()
5a
MOV to CR3
0
0
0
None
5f
MOV to CR3
0
0
1
TraceStop if executed in a
TraceStop region
PIP(NewCR3,NR?), TraceStop?
5b
MOV to CR3
0
1
1
*PIP.NR=1 if not in root
operation, and “Conceal
VMX non-root operation
from Intel PT” execution
control = 0
*MODE.Exec if the mode has
changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
PIP(NewCR3, NR?),
MODE.Exec?,
TIP.PGE(NLIP)
5c
MOV to CR3
1
0
0
5e
MOV to CR3
1
0
1
*PIP.NR=1 if not in root
operation, and “Conceal
VMX non-root operation
from Intel PT” execution
control = 0
*TraceStop if executed in a
TraceStop region
PIP(NewCR3, NR?),
TIP.PGE(NLIP), TraceStop?
5d
MOV to CR3
1
1
1
*PIP.NR=1 if not in root
operation, and “Conceal
VMX non-root operation
from Intel PT” execution
control = 0
PIP(NewCR3, NR?)
6a
Unconditional direct near jump
0
0
D.C.
6b
Unconditional direct near jump
1
0
1
TraceStop if BLIP is in a
TraceStop region
TIP.PGD(BLIP), TraceStop?
6c
Unconditional direct near jump
0
1
1
MODE.Exec if the mode has
changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
MODE.Exec?,
TIP.PGE(BLIP)
6d
Unconditional direct near jump
1
1
1
None
7a
Conditional taken jump or compressed
RET that does not fill up the internal
TNT buffer
0
0
D.C.
None
36-66 Vol. 3C
TIP.PGD()
None
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
7b
Conditional taken jump or compressed
RET
0
1
1
MODE.Exec if the mode has
changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
MODE.Exec?,
TIP.PGE(BLIP)
7e
Conditional taken jump or compressed
RET, with empty TNT buffer
1
0
1
TraceStop if BLIP is in a
TraceStop region
TIP.PGD(), TraceStop?
7f
Conditional taken jump or compressed
RET, with non-empty TNT buffer
1
0
1
TraceStop if BLIP is in a
TraceStop region
TNT, TIP.PGD(), TraceStop?
7d
Conditional taken jump or compressed
RET that fills up the internal TNT buffer
1
1
1
TNT
8a
Conditional non-taken jump
0
0
D.C.
None
8d
Conditional not-taken jump that fills up
the internal TNT buffer
1
1
1
TNT
9a
Near indirect jump (JMP, CALL, or
uncompressed RET)
0
0
D.C.
None
9b
Near indirect jump (JMP, CALL, or
uncompressed RET)
0
1
1
MODE.Exec if the mode has
changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
MODE.Exec?,
TIP.PGE(BLIP)
9c
Near indirect jump (JMP, CALL, or
uncompressed RET)
1
0
1
TraceStop if BLIP is in a
TraceStop region
TIP.PGD(BLIP), TraceStop?
9d
Near indirect jump (JMP, CALL, or
uncompressed RET)
1
1
1
TIP(BLIP)
10a
Far Branch (CALL/JMP/RET)
0
0
0
None
10f
Far Branch (CALL/JMP/RET)
0
0
1
*PIP if CR3 is updated (i.e.,
task switch), and OS=1;
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
PIP(new CR3, NR?), TraceStop?
10b
Far Branch (CALL/JMP/RET)
0
1
1
*PIP if CR3 is updated (i.e.,
task switch), and OS=1;
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*MODE.Exec if the mode has
changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
PIP(new CR3, NR?),
MODE.Exec?,
TIP.PGE(BLIP)
10c
Far Branch (CALL/JMP/RET)
1
0
0
TIP.PGD()
Vol. 3C 36-67
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
10d
Far Branch (CALL/JMP/RET)
1
0
1
*PIP if CR3 is updated (i.e.,
task switch), and OS=1;
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
PIP(new CR3, NR?),
TIP.PGD(BLIP), TraceStop?
10e
Far Branch (CALL/JMP/RET)
1
1
1
*PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
* MODE.Exec if the operation changes CS.L/D or
IA32_EFER.LMA
PIP(NewCR3, NR?)?,
MODE.Exec?, TIP(BLIP)
11a
HW Interrupt
0
0
0
11f
HW Interrupt
0
0
1
*PIP if CR3 is updated (i.e.,
task switch), and OS=1;
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
PIP(new CR3, NR?), TraceStop?
11b
HW Interrupt
0
1
1
*PIP if CR3 is updated (i.e.,
task switch), and OS=1;
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
* MODE.Exec if the mode
has changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
PIP(new CR3, NR?),
MODE.Exec?,
TIP.PGE(BLIP)
11c
HW Interrupt
1
0
0
11d
HW Interrupt
1
0
1
36-68 Vol. 3C
None
FUP(NLIP), TIP.PGD()
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
FUP(NLIP), PIP(NewCR3,
NR?)?, TIP.PGD(BLIP),
TraceStop
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
* MODE.Exec if the operation changes CS.L/D or
IA32_EFER.LMA
Packets Output
11e
HW Interrupt
1
1
1
12a
SW Interrupt
0
0
0
12f
SW Interrupt
0
0
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
PIP(NewCR3, NR?)?,
TraceStop?
12b
SW Interrupt
0
1
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*MODE.Exec if the mode has
changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
PIP(NewCR3, NR?)?,
MODE.Exec?,
TIP.PGE(BLIP)
12c
SW Interrupt
1
0
0
12d
SW Interrupt
1
0
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
FUP(CLIP), PIP(NewCR3,
NR?)?, TIP.PGD(BLIP),
TraceStop?
12e
SW Interrupt
1
1
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
* MODE.Exec if the operation changes CS.L/D or
IA32_EFER.LMA
FUP(CLIP), PIP(NewCR3,
NR?)?, FUP(NLIP),
MODE.Exec?, TIP(BLIP)
13a
Exception/Fault
0
0
0
FUP(NLIP), PIP(NewCR3,
NR?)?, MODE.Exec?,
TIP(BLIP)
None
FUP(CLIP), TIP.PGD()
None
Vol. 3C 36-69
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
13f
Exception/Fault
0
0
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
PIP(NewCR3, NR?)?,
TraceStop?
13b
Exception/Fault
0
1
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*MODE.Exec if the mode has
changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
PIP(NewCR3, NR?)?,
MODE.Exec?,
TIP.PGE(BLIP)
13c
Exception/Fault
1
0
0
13d
Exception/Fault
1
0
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
*TraceStop if BLIP is in a
TraceStop region
FUP(CLIP), PIP(NewCR3,
NR?)?, TIP.PGD(BLIP),
TraceStop?
13e
Exception/Fault
1
1
1
* PIP if CR3 is updated (i.e.,
task switch), and OS=1
*PIP.NR=1 if destination is
not root operation, and
“Conceal VMX non-root
operation from Intel PT”
execution control = 0;
* MODE.Exec if the operation changes CS.L/D or
IA32_EFER.LMA
FUP(CLIP), PIP(NewCR3,
NR?)?, MODE.Exec?,
TIP(BLIP)
14a
SMI (TraceEn cleared)
0
0
D.C.
None
14b
SMI (TraceEn cleared)
1
0
0
FUP(SMRAM,LIP),
TIP.PGD()
14f
SMI (TraceEn cleared)
1
0
1
NA
14c
SMI (TraceEn cleared)
1
1
1
NA
15a
RSM, TraceEn restored to 0
0
0
0
None
15b
RSM, TraceEn restored to 1
0
0
D.C.
See WRMSR cases for
packets on enable
36-70 Vol. 3C
FUP(CLIP), TIP.PGD()
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
15c
RSM, TraceEn restored to 1
0
1
1
See WRMSR cases for
packets on enable.
FUP/TIP.PGE IP is
SMRAM.LIP
15e
RSM (TraceEn=1, goes to shutdown)
1
0
0
None
15f
RSM (TraceEn=1, goes to shutdown)
1
0
1
None
15d
RSM (TraceEn=1, goes to shutdown)
1
1
1
None
16i
Vmext
0
0
0
None
16a
Vmext
0
0
1
16b
VM exit, MSR list sets TraceEn=1
0
0
0
See WRMSR cases for
packets on enable. FUP IP
is VMCSh.LIP
16c
VM exit, MSR list sets TraceEn=1
0
1
1
See WRMSR cases for
packets on enable.
FUP/TIP.PGE IP is
VMCSh.LIP
16e
VM exit
0
1
1
*PIP if OF=1, and “Conceal
PIP(HostCR3, NR=0)?,
VM exits from Intel PT” exe- MODE.Exec?,
cution control = 0;
TIP.PGE(VMCSh.LIP)
*MODE.Exec if the value is
different, since last TIP.PGD
16f
VM exit, MSR list clears TraceEn=0
1
0
0
*PIP if OF=1, and “Conceal
FUP(VMCSg.LIP),
VM exits from Intel PT” exe- PIP(HostCR3, NR=0)?,
cution control = 0;
TIP.PGD
16j
VM exit, ContextEN 1->0
1
0
0
16g
VM exit
1
0
1
*PIP if OF=1, and “Conceal
VM exits from Intel PT” execution control = 0;
*TraceStop if VMCSh.LIP is
in a TraceStop region
FUP(VMCSg.LIP),
PIP(HostCR3, NR=0)?,
TIP.PGD(VMCSh.LIP),
TraceStop?
16h
VM exit
1
1
1
*PIP if OF=1, and “Conceal
VM exits from Intel PT” execution control = 0;
*MODE.Exec if the value is
different, since last TIP.PGD
FUP(VMCSg.LIP),
PIP(HostCR3, NR=0)?,
MODE.Exec,
TIP(VMCSh.LIP)
17a
VM entry
0
0
0
17b
VM entry
0
0
1
17c
VM entry, MSR load list sets TraceEn=1 0
0
1
*PIP if OF=1, and “Conceal
PIP(HostCR3, NR=0)?,
VM exits from Intel PT” exe- TraceStop?
cution control = 0;
*TraceStop if VMCSh.LIP is
in a TraceStop region
FUP(VMCSg.LIP), TIP.PGD
None
*PIP if OF=1, and “Conceal
VM entries from Intel PT”
execution control = 0;
*TraceStop if VMCSg.LIP is
in a TraceStop region
PIP(GuestCR3, NR=1)?,
TraceStop?
See WRMSR cases for
packets on enable. FUP IP
is VMCSg.LIP
Vol. 3C 36-71
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
17d
VM entry, MSR load list sets TraceEn=1 0
1
1
17f
VM entry, FilterEN 0->1
0
1
1
*PIP if OF=1, and “Conceal
VM entries from Intel PT”
execution control = 0;
*MODE.Exec if the value is
different, since last TIP.PGD
PIP(GuestCR3, NR=1)?,
MODE.Exec?,
TIP.PGE(VMCSg.LIP)
17j
VM entry, ContextEN 0->1
0
1
1
*MODE.Exec if the value is
different, since last TIP.PGD
MODE.Exec,
TIP.PGE(VMCSg.LIP)
17g
VM entry, MSR list clears TraceEn=0
1
0
0
*PIP if OF=1, and “Conceal
VM entries from Intel PT”
execution control = 0;
PIP(GuestCR3, NR=1)?,
TIP.PGD
17h
VM entry
1
0
1
*PIP if OF=1, and “Conceal
VM entries from Intel PT”
execution control = 0;
*TraceStop if VMCSg.LIP is
in a TraceStop region
PIP(GuestCR3, NR=1)?,
TIP.PGD(VMCSg.LIP),
TraceStop?
17i
VM entry
1
1
1
*PIP if OF=1, and “Conceal
VM entries from Intel PT”
execution control = 0;
*MODE.Exec if the value is
different, since last TIP.PGD
PIP(GuestCR3, NR=1)?,
MODE.Exec,
TIP(VMCSg.LIP)
20a
EENTER/ERESUME to non-debug
enclave
0
0
0
None
20c
EENTER/ERESUME to non-debug
enclave
1
0
0
FUP(CLIP), TIP.PGD()
21a
EEXIT from non-debug enclave
0
0
D.C.
None
21b
EEXIT from non-debug enclave
0
1
1
22a
AEX/EEE from non-debug enclave
0
0
D.C.
22b
AEX/EEE from non-debug enclave
0
1
1
23a
EENTER/ERESUME to debug enclave
0
0
D.C.
23b
EENTER/ERESUME to debug enclave
0
1
1
23c
EENTER/ERESUME to debug enclave
1
0
0
23d
EENTER/ERESUME to debug enclave
0
0
1
23e
EENTER/ERESUME to debug enclave
1
1
1
FUP(CLIP), TIP(BLIP)
24f
EEXIT from debug enclave
0
0
D.C.
None
24b
EEXIT from debug enclave
0
1
1
*MODE.Exec if the value is
different, since last TIP.PGD
MODE.Exec?,
TIP.PGE(BLIP)
24d
EEXIT from debug enclave
1
0
1
*TraceStop if BLIP is in a
TraceStop region
FUP(CLIP), TIP.PGD(BLIP),
TraceStop?
36-72 Vol. 3C
See WRMSR cases for
packets on enable.
FUP/TIP.PGE IP is
VMCSg.LIP
*MODE.Exec if the value is
different, since last TIP.PGD
MODE.Exec?,
TIP.PGE(BLIP)
None
*MODE.Exec if the value is
different, since last TIP.PGD
MODE.Exec?,
TIP.PGE(AEP.LIP)
None
*MODE.Exec if the value is
different, since last TIP.PGD
MODE.Exec?,
TIP.PGE(BLIP)
FUP(CLIP), TIP.PGD()
*TraceStop if BLIP is in a
TraceStop region
FUP(CLIP), TIP.PGD(BLIP),
TraceStop?
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
24e
EEXIT from debug enclave
1
1
1
FUP(CLIP), TIP(BLIP)
25a
AEX/EEE from debug enclave
0
0
D.C.
None
25b
AEX/EEE from debug enclave
0
1
1
*MODE.Exec if the value is
different, since last TIP.PGD
MODE.Exec?,
TIP.PGE(AEP.LIP)
25d
AEX/EEE from debug enclave
1
0
1
*For AEX, FUP IP could be
NLIP, for trap-like events
FUP(CLIP),
TIP.PGD(AEP.LIP)
25e
AEX/EEE from debug enclave
1
1
1
*MODE.Exec if the value is
different, since last TIP.PGD
*For AEX, FUP IP could be
NLIP, for trap-like events
FUP(CLIP), MODE.Exec?,
TIP(AEP.LIP)
26a
XBEGIN/XACQUIRE
0
0
D.C.
None
26d
XBEGIN/XACQUIRE that does not set
InTX
1
1
1
None
26e
XBEGIN/XACQUIRE that sets InTX
1
1
1
MODE(InTX=1,
TXAbort=0), FUP(CLIP)
27a
XEND/XRELEASE
0
0
D.C.
None
27d
XEND/XRELEASE that does not clear
InTX
1
1
1
None
27e
XEND/XRELEASE that clears InTX
1
1
1
MODE(InTX=0,
TXAbort=0), FUP(CLIP)
28a
XABORT(Async XAbort, or other)
0
0
0
None
28e
XABORT(Async XAbort, or other)
0
0
1
28b
XABORT(Async XAbort, or other)
0
1
1
28c
XABORT(Async XAbort, or other)
1
0
1
28d
XABORT(Async XAbort, or other)
1
1
1
MODE(InTX=0,
TXAbort=1), FUP(CLIP),
TIP(BLIP)
30a
INIT (BSP)
0
0
0
None
30b
INIT (BSP)
0
0
1
*TraceStop if RESET.LIP is in
a TraceStop region
BIP(0), TraceStop?
30c
INIT (BSP)
0
1
1
* MODE.Exec if the value is
different, since last TIP.PGD
MODE.Exec?, PIP(0),
TIP.PGE(ResetLIP)
30d
INIT (BSP)
1
0
0
30e
INIT (BSP)
1
0
1
*TraceStop if BLIP is in a
TraceStop region
MODE(InTX=0,
TXAbort=1), TraceStop?
MODE(InTX=0,
TXAbort=1),
TIP.PGE(BLIP)
*TraceStop if BLIP is in a
TraceStop region
MODE(InTX=0,
TXAbort=1), TIP.PGD
(BLIP), TraceStop?
FUP(NLIP), TIP.PGD()
* PIP if OS=1
*TraceStop if RESET.LIP is in
a TraceStop region
FUP(NLIP), PIP(0),
TIP.PGD, TraceStop?
Vol. 3C 36-73
INTEL® PROCESSOR TRACE
Table 36-50. Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
* MODE.Exec if the mode
has changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
* PIP if OS=1
Packets Output
30f
INIT (BSP)
1
1
1
31a
INIT (AP, goes to wait-for-SIPI)
0
D.C.
D.C.
31b
INIT (AP, goes to wait-for-SIPI)
1
D.C.
D.C.
32a
SIPI
0
0
0
32c
SIPI
0
1
1
32d
SIPI
1
0
0
32e
SIPI
1
0
1
*TraceStop if SIPI LIP is in a
TraceStop region
TIP.PGD(SIPILIP); TraceStop?
32f
SIPI
1
1
1
* MODE.Exec if the mode
has changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
MODE.Exec?, TIP(SIPILIP)
33a
MWAIT (to C0)
D.C.
D.C.
D.C.
33b
MWAIT (to higher-numbered C-State,
packet sent on wake)
D.C.
D.C.
D.C.
FUP(NLIP), PIP(0)?,
MODE.Exec?,
TIP(ResetLIP)
None
* PIP if OS=1
FUP(NLIP), PIP(0)
None
* MODE.Exec if the mode
has changed since the last
MODE.Exec, or if no
MODE.Exec since last PSB
MODE.Exec?, TIP.PGE(SIPILIP)
TIP.PGD
None
*TSC if TSCEn=1
*TMA if TSCEn=MTCEn=1
TSC?, TMA?, CBR
In Table 36-52, PktEn is evaluated based on (TiggerEn & ContextEn & FilterEn & BranchEn & PwrEvtEn).
Table 36-51. PwrEvtEn and PTWEn Packet Generation under Different Enable Conditions
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
16.1
MWAIT or I/O redir to MWAIT, gets
#UD or #GP fault
dc
dc
dc
None
16.2
MWAIT or I/O redir to MWAIT, VM
exits
dc
dc
dc
See VM exit examples
(16[a-z] in Table 36-50)
for BranchEn packets.
16.3
MWAIT or I/O redir to MWAIT,
requests C0, or monitor not armed,
or VMX virtual-interrupt delivery
dc
dc
dc
None
16.4a
MWAIT(X) or I/O redir to MWAIT,
goes to C-state Y (Y>0)
dc
0
0
PWRE(Cx), EXSTOP
16.4b
MWAIT(X) or I/O redir to MWAIT,
goes to C-state Y (Y>0)
dc
dc
1
MWAIT(Cy), PWRE(Cx),
EXSTOP(IP), FUP(CLIP)
16.5a
MWAIT(X) or I/O redir to MWAIT,
Pending event after resolving to go
to C-state Y (Y>0)
dc
0
0
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
PWRE(Cx), EXSTOP, TSC?,
TMA?, CBR, PWRX(LCC,
DCC, 0)
16.5b
MWAIT(X) or I/O redir to MWAIT,
Pending event after resolving to go
to C-state Y (Y>0)
dc
dc
1
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
PWRE(Cx), EXSTOP(IP),
FUP(CLIP), TSC?, TMA?,
CBR, PWRX(LCC, DCC, 0)
36-74 Vol. 3C
INTEL® PROCESSOR TRACE
Table 36-51. PwrEvtEn and PTWEn Packet Generation under Different Enable Conditions (Contd.)
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
16.6a
MWAIT(5) or I/O redir to MWAIT,
other thread(s) in core in C0/C1
dc
0
0
PWRE(C1), EXSTOP
16.6b
MWAIT(5) or I/O redir to MWAIT,
other thread(s) in core in C0/C1
dc
dc
1
MWAIT(5), PWRE(C1),
EXSTOP(IP), FUP(CLIP)
16.9a
HLT, Triple-fault shutdown, #MC
with CR4.MCE=0, RSM to Cx (x>0)
dc
0
0
PWRE(C1), EXSTOP
16.9b
HLT, Triple-fault shutdown, #MC
with CR4.MCE=1, RSM to Cx (x>0)
dc
dc
16.10a
VMX abort
dc
0
PWRE(C1), EXSTOP(IP),
FUP(CLIP)
0
See “VMX Abort” (cases
16* and 18* in Table 3650) for BranchEn packets
that precede
PWRE(C1), EXSTOP
16.10b
VMX abort
dc
dc
1
See “VMX Abort” (cases
16* and 18* in Table 3650) for BranchEn packets
that precede
PWRE(C1), EXSTOP(IP),
FUP(CLIP)
16.11a
RSM to Shutdown
dc
0
0
See “RSM to Shutdown”
(cases 15[def] in Table
36-50) for BranchEn
packets that precede
PWRE(C1), EXSTOP
16.11b
RSM to Shutdown
dc
dc
1
See “RSM to Shutdown”
(cases 15[def] in Table
36-50) for BranchEn
packets that precede
PWRE(C1), EXSTOP(IP),
FUP(CLIP)
16.12a
INIT (BSP)
dc
0
0
See “INIT (BSP)” (cases
30[a-z] in Table 36-50)
for packets that BranchEn
precede
PWRE(C1), EXSTOP
16.12b
INIT (BSP)
dc
dc
1
See “INIT (BSP)” (cases
30[a-z] in Table 36-50)
for packets that BranchEn
precede
PWRE(C1), EXSTOP(IP),
FUP(NLIP)
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INTEL® PROCESSOR TRACE
Table 36-51. PwrEvtEn and PTWEn Packet Generation under Different Enable Conditions (Contd.)
Case
16.13a
Operation
INIT (AP, goes to Wait-for-SIPI)
PktEn
Before
PktEn CntxEn
After
After
dc
0
Other Dependencies
0
Packets Output
See “INIT (AP, goes to
Wait-for-SIPI)” (cases
31[a-z] in Table 36-50)
for BranchEn packets that
precede
PWRE(C1), EXSTOP
16.13b
INIT (AP, goes to Wait-for-SIPI)
dc
dc
1
See “INIT (AP, goes to
Wait-for-SIPI)” (cases
31[a-z] in Table 36-50)
for BranchEn packets that
precede
PWRE(C1), EXSTOP(IP),
FUP(NLIP)
16.14a
Hardware Duty Cycling (HDC)
dc
0
0
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
PWRE(HW, C6), EXSTOP,
TSC?, TMA?, CBR,
PWRX(CC6, CC6, 0x8)
16.14b
Hardware Duty Cycling (HDC)
dc
dc
1
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
PWRE(HW, C6), EXSTOP(IP), FUP(NLIP), TSC?,
TMA?, CBR, PWRX(CC6,
CC6, 0x8)
16.15a
VM entry to HLT or Shutdown
dc
0
0
See “VM entry” (cases
17[a-z] in Table 36-50)
for BranchEn packets that
precede.
PWRE(C1), EXSTOP
16.15b
VM entry to HLT or Shutdown
dc
dc
1
See “VM entry” (cases
17[a-z] in Table 36-50)
for BranchEn packets that
precede.
PWRE(C1), EXSTOP(IP),
FUP(CLIP)
16.16a
EIST in C0, S1/TM1/TM2, or STPCLK#
dc
0
0
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
EXSTOP, TSC?, TMA?, CBR
16.16b
EIST in C0, S1/TM1/TM2, or STPCLK#
dc
dc
1
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
EXSTOP(IP), FUP(NLIP),
TSC?, TMA?, CBR
16.17
EIST in Cx (x>0)
dc
dc
dc
16.18
INTR during Cx (x>0)
dc
dc
dc
None
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
TSC?, TMA?, CBR,
PWRX(LCC, DCC, 0x1)
See “HW Interrupt” (cases
11[a-z] in Table 36-50)
for BranchEn packets that
follow.
36-76 Vol. 3C
INTEL® PROCESSOR TRACE
Table 36-51. PwrEvtEn and PTWEn Packet Generation under Different Enable Conditions (Contd.)
Case
16.18
Operation
SMI during Cx (x>0)
PktEn
Before
PktEn CntxEn
After
After
dc
dc
dc
Other Dependencies
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
Packets Output
TSC?, TMA?, CBR,
PWRX(LCC, DCC, 0)
See “HW Interrupt” (cases
14[a-z] in Table 36-50)
for BranchEn packets that
follow.
16.19
NMI during Cx (x>0)
dc
dc
dc
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
TSC?, TMA?, CBR,
PWRX(LCC, DCC, 0)
See “HW Interrupt” (cases
11[a-z] in Table 36-50)
for BranchEn packets that
follow.
16.2
Store to monitored address during
Cx (x>0)
dc
dc
dc
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
TSC?, TMA?, CBR,
PWRX(LCC, DCC, 0x4)
16.22
#MC, IERR, TSC deadline timer
expiration, or APIC counter underflow during Cx (x>0)
dc
dc
dc
* TSC if TSCEn=1
* TMA if TSCEn=MTCEn=1
TSC?, TMA?, CBR,
PWRX(LCC, DCC, 0)
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INTEL® PROCESSOR TRACE
In Table 36-52, PktEn is evaluated based on (TiggerEn & ContextEn & FilterEn & BranchEn & PTWEn).
Table 36-52. PwrEvtEn and PTWEn Packet Generation under Different Enable Conditions
Case
Operation
PktEn
Before
PktEn CntxEn
After
After
Other Dependencies
Packets Output
16.24a
PTWRITE rm32/64, no fault
dc
dc
dc
None
16.24b
PTWRITE rm32/64, no fault
dc
0
0
None
16.24d
PTWRITE rm32, no fault
dc
1
1
* FUP, IP=1 if FUPonPTW=1
PTW(IP=1?, 4B,
rm32_value), FUP(CLIP)?
16.24e
PTWRITE rm64, no fault
dc
1
1
* FUP, IP=1 if FUPonPTW=1
PTW(IP=1?, 8B,
rm64_value), FUP(CLIP)?
16.25a
PTWRITE mem32/64, fault
dc
dc
dc
36.8
SOFTWARE CONSIDERATIONS
36.8.1
Tracing SMM Code
See “Exception/fault”
(cases 13[a-z] in Table
36-50) for BranchEn
packets.
Nothing prevents an SMM handler from configuring and enabling packet generation for its own use. As described in
Section , SMI will always clear TraceEn, so the SMM handler would have to set TraceEn in order to enable tracing.
There are some unique aspects and guidelines involved with tracing SMM code, which follows:
1. SMM should save away the existing values of any configuration MSRs that SMM intends to modify for tracing.
This will allow the non-SMM tracing context to be restored before RSM.
2. It is recommended that SMM wait until it sets CSbase to 0 before enabling packet generation, to avoid possible
LIP vs RIP confusion.
3. Packet output cannot be directed to SMRR memory, even while tracing in SMM.
4. Before performing RSM, SMM should take care to restore modified configuration MSRs to the values they had
immediately after #SMI. This involves first disabling packet generation by clearing TraceEn, then restoring any
other configuration MSRs that were modified.
5. RSM
— Software must ensure that TraceEn=0 at the time of RSM. Tracing RSM is not a supported usage model, and
the packets generated by RSM are undefined.
— For processors on which Intel PT and LBR use are mutually exclusive (see Section 36.3.1.2), any RSM
during which TraceEn is restored to 1 will suspend any LBR or BTS logging.
36.8.2
Cooperative Transition of Multiple Trace Collection Agents
A third-party trace-collection tool should take into consideration the fact that it may be deployed on a processor
that supports Intel PT but may run under any operating system.
In such a deployment scenario, Intel recommends that tool agents follow similar principles of cooperative transition
of single-use hardware resources, similar to how performance monitoring tools handle performance monitoring
hardware:
•
Respect the “in-use” ownership of an agent who already configured the trace configuration MSRs, see architectural MSRs with the prefix “IA32_RTIT_” in Chapter 35, “Model-Specific Registers (MSRs)”, where “in-use” can
be determined by reading the “enable bits” in the configuration MSRs.
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INTEL® PROCESSOR TRACE
•
Relinquish ownership of the trace configuration MSRs by clearing the “enabled bits” of those configuration
MSRs.
36.8.3
Tracking Time
This section describes the relationships of several clock counters whose update frequencies reside in different
domains that feed into the timing packets. To track time, the decoder also needs to know the regularity or irregularity of the occurrences of various timing packets that store those clock counters.
Intel PT provides time information for three different but related domains:
•
Processor timestamp counter
•
This counter increments at the max non-turbo or P1 frequency, and its value is returned on a RDTSC. Its
frequency is fixed. The TSC packet holds the lower 7 bytes of the timestamp counter value. The TSC packet
occurs occasionally and are much less frequent than the frequency of the time stamp counter. The timestamp
counter will continue to increment when the processor is in deep C-States, with the exception of processors
reporting CPUID.80000007H:EDX.InvariantTSC[bit 8] =0.
Core crystal clock
The ratio of the core crystal clock to timestamp counter frequency is known as P, and can calculating
CPUID.15H:EBX[31:0] / CPUID.15H:EAX[31:0]. The frequency of the core crystal clock is fixed and lower than
that of the timestamp counter. The periodic MTC packet is generated based on software-selected multiples of
the crystal clock frequency. The MTC packet is expected to occur more frequently than the TSC packet.
•
Processor core clock
The processor core clock frequency can vary due to P-state and thermal conditions. The CYC packet provides
elapsed time as measured in processor core clock cycles relative to the last CYC packet.
A decoder can use all or some combination of these packets to track time at different resolutions throughout the
trace packets.
36.8.3.1
Time Domain Relationships
The three domains are related by the following formula:
TimeStampValue = (CoreCrystalClockValue * P) + AdjustedProcessorCycles + Software_Offset;
The CoreCrystalClockValue can provide the coarse-grained component of the TSC value. P, or the TSC/”core crystal
clock” ratio, can be derived from CPUID leaf 15H, as described in Section 36.8.3.
The AdjustedProcessorCycles component provides the fine-grained distance from the rising edge of the last core
crystal clock. Specifically, it is a cycle count in the same frequency as the timestamp counter from the last crystal
clock rising edge. The value is adjusted based on the ratio of the processor core clock frequency to the Maximum
Non-Turbo (or P1) frequency.
The Software_Offsets component includes software offsets that are factored into the timestamp value, such as
IA32_TSC_ADJUST.
36.8.3.2
Estimating TSC within Intel PT
For many usages, it may be useful to have an estimated timestamp value for all points in the trace. The formula
provided in Section 36.8.3.1 above provides the framework for how such an estimate can be calculated from the
various timing packets present in the trace.
The TSC packet provides the precise timestamp value at the time it is generated; however, TSC packets are infrequent, and estimates of the current timestamp value based purely on TSC packets are likely to be very inaccurate
for this reason. In order to get more precise timing information between TSC packets, CYC packets and/or MTC
packets should be enabled.
MTC packets provide incremental updates of the CoreCrystalClockValue. On processors that support CPUID leaf
15H, the frequency of the timestamp counter and the core crystal clock is fixed, thus MTC packets provide a means
to update the running timestamp estimate. Between two MTC packets A and B, the number of crystal clock cycles
passed is calculated from the 8-bit payloads of respective MTC packets:
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INTEL® PROCESSOR TRACE
(CTCB - CTCA), where CTCi = MTCi[15:8] << IA32_RTIT_CTL.MTCFreq and i = A, B.
The time from a TSC packet to the subsequent MTC packet can be calculated using the TMA packet that follows the
TSC packet. The TMA packet provides both the crystal clock value (lower 16 bits, in the CTC field) and the AdjustedProcessorCycles value (in the FastCounter field) that can be used in the calculation of the corresponding core
crystal clock value of the TSC packet.
When the next MTC after a pair of TSC/TMA is seen, the number of crystal clocks passed since the TSC packet can
be calculated by subtracting the TMA.CTC value from the time indicated by the MTCNext packet by
CTCDelta[15:0] = (CTCNext[15:0] - TMA.CTC[15:0]), where CTCNext = MTCPayload << IA32_RTIT_CTL.MTCFreq.
The TMA.FastCounter field provides the fractional component of the TSC packet into the next crystal clock cycle.
CYC packets can provide further precision of an estimated timestamp value to many non-timing packets, by
providing an indication of the time passed between other timing packets (MTCs or TSCs).
When enabled, CYC packets are sent preceding each CYC-eligible packet, and provide the number of processor core
clock cycles that have passed since the last CYC packet. Thus between MTCs and TSCs, the accumulated CYC
values can be used to estimate the adjusted_processor_cycles component of the timestamp value. The accumulated CPU cycles will have to be adjusted to account for the difference in frequency between the processor core
clock and the P1 frequency. The necessary adjustment can be estimated using the core:bus ratio value given in the
CBR packet, by multiplying the accumulated cycle count value by P1/CBRpayload.
A greater level of precision may be achieved by calculating the CPU clock frequency, see Section 36.8.3.4 below for
a method to do so using Intel PT packets.
CYCs can be used to estimate time between TSCs even without MTCs, though this will likely result in a reduction in
estimated TSC precision.
36.8.3.3
VMX TSC Manipulation
When software executes in non-Root operation, additional offset and scaling factors may be applied to the TSC
value. These are optional, but may be enabled via VMCS controls on a per-VM basis. See Chapter 25, “VMX NonRoot Operation” for details on VMX TSC offsetting and TSC scaling.
Like the value returned by RDTSC, TSC packets will include these adjustments, but other timing packets (such as
MTC, CYC, and CBR) are not impacted. In order to use the algorithm above to estimate the TSC value when TSC
scaling is in use, it will be necessary for software to account for the scaling factor. See Section 36.5.2.6 for details.
36.8.3.4
Calculating Frequency with Intel PT
Because Intel PT can provide both wall-clock time and processor clock cycle time, it can be used to measure the
processor core clock frequency. Either TSC or MTC packets can be used to track the wall-clock time. By using CYC
packets to count the number of processor core cycles that pass in between a pair of wall-clock time packets, the
ratio between processor core clock frequency and TSC frequency can be derived. If the P1 frequency is known, it
can be applied to determine the CPU frequency. See Section 36.8.3.1 above for details on the relationship between
TSC, MTC, and CYC.
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INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
CHAPTER 37
INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
37.1
OVERVIEW
®
Intel Software Guard Extensions (Intel® SGX) is a set of instructions and mechanisms for memory accesses
added to Intel® Architecture processors. Intel SGX can encompass two collections of instruction extensions,
referred to as SGX1 and SGX2, see Table 37-4. The SGX1 extensions allow an application to instantiate a protected
container, referred to as an enclave. An enclave is a protected area in the application’s address space (see
Figure 37-1), which provides confidentiality and integrity even in the presence of privileged malware. Accesses to
the enclave memory area from any software not resident in the enclave are prevented. The SGX2 extensions allow
additional flexibility in runtime management of enclave resources and thread execution within an enclave.
Chapter 38 covers main concepts, objects and data structure formats that interact within the Intel SGX architecture. Chapter 39 covers operational aspects ranging from preparing an enclave, transferring control to enclave
code, and programming considerations for the enclave code and system software providing support for enclave
execution. Chapter 40 describes the behavior of Asynchronous Enclave Exit (AEX) caused by events while
executing enclave code. Chapter 41 covers the syntax and operational details of the instruction and associated leaf
functions available in Intel SGX. Chapter 42 describes interaction of various aspects of IA32 and Intel® 64 architectures with Intel SGX. Chapter 43 covers Intel SGX support for application debug, profiling and performance
monitoring.
OS
Enclave
Entry Table
Enclave Heap
App Code
Enclave Stack
Enclave Code
App Code
Figure 37-1. An Enclave Within the Application’s Virtual Address Space
37.2
ENCLAVE INTERACTION AND PROTECTION
Intel SGX allows the protected portion of an application to be distributed in the clear. Before the enclave is built, the
enclave code and data are free for inspection and analysis. The protected portion is loaded into an enclave where
its code and data is measured. Once the application’s protected portion of the code and data are loaded into an
enclave, it is protected against external software access. An enclave can prove its identity to a remote party and
provide the necessary building-blocks for secure provisioning of keys and credentials. The application can also
request an enclave-specific and platform-specific key that it can use to protect keys and data that it wishes to store
outside the enclave.1
1. For additional information, see white papers on Intel SGX at http://software.intel.com/en-us/intel-isa-extensions.
Vol. 3D 37-1
INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
Intel SGX introduces two significant capabilities to the Intel Architecture. First is the change in enclave memory
access semantics. The second is protection of the address mappings of the application.
37.3
ENCLAVE LIFE CYCLE
Enclave memory management is divided into two parts: address space allocation and memory commitment.
Address space allocation is the specification of the range of logical addresses that the enclave may use. This range
is called the ELRANGE. No actual resources are committed to this region. Memory commitment is the assignment
of actual memory resources (as pages) within the allocated address space. This two-phase technique allows flexibility for enclaves to control their memory usage and to adjust dynamically without overusing memory resources
when enclave needs are low. Commitment adds physical pages to the enclave. An operating system may support
separate allocate and commit operations.
During enclave creation, code and data for an enclave are loaded from a clear-text source, i.e. from non-enclave
memory.
Untrusted application code starts using an initialized enclave typically by using the EENTER leaf function provided
by Intel SGX to transfer control to the enclave code residing in the protected Enclave Page Cache (EPC). The
enclave code returns to the caller via the EEXIT leaf function. Upon enclave entry, control is transferred by hardware to software inside the enclave. The software inside the enclave switches the stack pointer to one inside the
enclave. When returning back from the enclave, the software swaps back the stack pointer then executes the
EEXIT leaf function.
On processors that supports the SGX2 extensions, an enclave writer may add memory to an enclave using the
SGX2 instruction set, after the enclave is built and running. These instructions allow adding additional memory
resources to the enclave for use in such areas as the heap. In addition, SGX2 instructions allow the enclave to add
new threads to the enclave. The SGX2 features provide additional capabilities to the software model without
changing the security properties of the Intel SGX architecture.
Calling an external procedure from an enclave could be done using the EEXIT leaf function. Software would use
EEXIT and a software convention between the trusted section and the untrusted section.
An active enclave consumes resource from the Enclave Page Cache (EPC, see Section 37.5). Intel SGX provides the
EREMOVE instruction that an EPC manager can use to reclaim EPC pages committed to an enclave. The EPC
manager uses EREMOVE on every enclave page when the enclave is torn down. After successful execution of
EREMOVE the EPC page is available for allocation to another enclave.
37.4
DATA STRUCTURES AND ENCLAVE OPERATION
There are 2 main data structures associated with operating an enclave, the SGX Enclave Control Structure (SECS,
see Section 38.7) and the Thread Control Structure (TCS, see Section 38.8).
There is one SECS for each enclave. The SECS contains meta-data about the enclave which is used by the hardware
and cannot be directly accessed by software. Included in the SECS is a field that stores the enclave build measurement value. This field, MRENCLAVE, is initialized by the ECREATE instruction and updated by every EADD and
EEXTEND. It is locked by EINIT.
Every enclave contains one or more TCS structures. The TCS contains meta-data used by the hardware to save and
restore thread specific information when entering/exiting the enclave. There is one field, FLAGS, that may be
accessed by software. This field can only be accessed by debug enclaves. The flag bit, DBGOPTIN, allows to single
step into the thread associated with the TCS. (see Section 38.8.1)
The SECS is created when ECREATE (see Table 37-1) is executed. The TCS can be created using the EADD instruction or the SGX2 instructions (see Table 37-2).
37.5
ENCLAVE PAGE CACHE
The Enclave Page Cache (EPC) is the secure storage used to store enclave pages when they are a part of an
executing enclave. For an EPC page, hardware performs additional access control checks to restrict access to the
page. After the current page access checks and translations are performed, the hardware checks that the EPC page
37-2 Vol. 3D
INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
is accessible to the program currently executing. Generally an EPC page is only accessed by the owner of the
executing enclave or an instruction which is setting up an EPC page
The EPC is divided into EPC pages. An EPC page is 4KB in size and always aligned on a 4KB boundary.
Pages in the EPC can either be valid or invalid. Every valid page in the EPC belongs to one enclave instance. Each
enclave instance has an EPC page that holds its SECS. The security metadata for each EPC page is held in an
internal micro-architectural structure called Enclave Page Cache Map (EPCM, see Section 37.5.1).
The EPC is managed by privileged software. Intel SGX provides a set of instructions for adding and removing
content to and from the EPC. The EPC may be configured by BIOS at boot time. On implementations in which EPC
memory is part of system DRAM, the contents of the EPC are protected by an encryption engine.
37.5.1
Enclave Page Cache Map (EPCM)
The EPCM is a secure structure used by the processor to track the contents of the EPC. The EPCM holds one entry
for each page in the EPC. The format of the EPCM is micro-architectural, and consequently is implementation
dependent. However, the EPCM contains the following architectural information:
•
•
•
•
•
The status of EPC page with respect to validity and accessibility.
An SECS identifier (see Section 38.19) of the enclave to which the page belongs.
The type of page: regular, SECS, TCS or VA.
The linear address through which the enclave is allowed to access the page.
The specified read/write/execute permissions on that page.
The EPCM structure is used by the CPU in the address-translation flow to enforce access-control on the EPC pages.
The EPCM structure is described in Table 38-27, and the conceptual access-control flow is described in Section
38.5.
The EPCM entries are managed by the processor as part of various instruction flows.
37.6
ENCLAVE INSTRUCTIONS AND INTEL® SGX
The enclave instructions available with Intel SGX are organized as leaf functions under two instruction mnemonics:
ENCLS (ring 0) and ENCLU (ring 3). Each leaf function uses EAX to specify the leaf function index, and may require
additional implicit input registers as parameters. The use of EAX is implied implicitly by the ENCLS and ENCLU
instructions, ModR/M byte encoding is not used with ENCLS and ENCLU. The use of additional registers does not
use ModR/M encoding and is implied implicitly by the respective leaf function index.
Each leaf function index is also associated with a unique, leaf-specific mnemonic. A long-form expression of Intel
SGX instruction takes the form of ENCLx[LEAF_MNEMONIC], where ‘x’ is either ‘S’ or ‘U’. The long-form expression
provides clear association of the privilege-level requirement of a given “leaf mnemonic”. For simplicity, the unique
“Leaf_Mnemonic” name is used (omitting the ENCLx for convenience) throughout in this document.
Details of Individual SGX leaf functions are described in Chapter 41. Table 37-1 provides a summary of the instruction leaves that are available in the initial implementation of Intel SGX, which is introduced in the 6th generation
Intel Core processors. Table 37-1 summarizes enhancement of Intel SGX for future Intel processors.
Table 37-1. Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1
Supervisor Instruction
Description
User Instruction
Description
ENCLS[EADD]
Add an EPC page to an enclave.
ENCLU[EENTER]
Enter an enclave.
ENCLS[EBLOCK]
Block an EPC page.
ENCLU[EEXIT]
Exit an enclave.
ENCLS[ECREATE]
Create an enclave.
ENCLU[EGETKEY]
Create a cryptographic key.
ENCLS[EDBGRD]
Read data from a debug enclave by debug- ENCLU[EREPORT]
ger.
Create a cryptographic report.
ENCLS[EDBGWR]
Write data into a debug enclave by debug- ENCLU[ERESUME]
ger.
Re-enter an enclave.
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INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
Table 37-1. Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1
Supervisor Instruction
Description
ENCLS[EEXTEND]
Extend EPC page measurement.
ENCLS[EINIT]
Initialize an enclave.
ENCLS[ELDB]
Load an EPC page in blocked state.
ENCLS[ELDU]
Load an EPC page in unblocked state.
ENCLS[EPA]
Add an EPC page to create a version array.
ENCLS[EREMOVE]
Remove an EPC page from an enclave.
ENCLS[ETRACK]
Activate EBLOCK checks.
ENCLS[EWB]
Write back/invalidate an EPC page.
User Instruction
Description
Table 37-2. Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX2
Supervisor Instruction
Description
User Instruction
Description
ENCLS[EAUG]
Allocate EPC page to an existing enclave.
ENCLU[EACCEPT]
Accept EPC page into the enclave.
ENCLS[EMODPR]
Restrict page permissions.
ENCLU[EMODPE]
Enhance page permissions.
ENCLS[EMODT]
Modify EPC page type.
ENCLU[EACCEPTCOPY] Copy contents to an augmented EPC
page and accept the EPC page into
the enclave.
37.7
DISCOVERING SUPPORT FOR INTEL® SGX AND ENABLING ENCLAVE
INSTRUCTIONS
Detection of support of Intel SGX and enumeration of available and enabled Intel SGX resources are queried using
the CPUID instruction. The enumeration interface comprises the following:
•
Processor support of Intel SGX is enumerated by a feature flag in CPUID leaf 07H: CPUID.(EAX=07H,
ECX=0H):EBX.SGX[bit 2]. If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support for Intel
SGX, and requires opt-in enabling by BIOS via IA32_FEATURE_CONTROL MSR.
If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, CPUID will report via the available sub-leaves of
CPUID.(EAX=12H) on available and/or configured Intel SGX resources.
The available and configured Intel SGX resources enumerated by the sub-leaves of CPUID.(EAX=12H) depend
on the state of BIOS configuration.
•
37.7.1
Intel® SGX Opt-In Configuration
On processors that support Intel SGX, IA32_FEATURE_CONTROL provides the SGX_ENABLE field (bit 18). Before
system software can configure and enable Intel SGX resources, BIOS is required to set
IA32_FEATURE_CONTROL.SGX_ENABLE = 1 to opt-in the use of Intel SGX by system software.
The semantics of setting SGX_ENABLE follows the rules of IA32_FEATURE_CONTROL.LOCK (bit 0). Software is
considered to have opted into Intel SGX if and only if IA32_FEATURE_CONTROL.SGX_ENABLE and
IA32_FEATURE_CONTROL.LOCK are set to 1. The setting of IA32_FEATURE_CONTROL.SGX_ENABLE (bit 18) is not
reflected by CPUID.
Table 37-3. Intel® SGX Opt-in and Enabling Behavior
CPUID.(07H,0H):EBX.
SGX
CPUID.(12H)
FEATURE_CONTROL. FEATURE_CONTROL.
LOCK
SGX_ENABLE
Enclave Instruction
0
Invalid
X
X
#UD
1
Valid*
X
X
#UD**
37-4 Vol. 3D
INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
Table 37-3. Intel® SGX Opt-in and Enabling Behavior
CPUID.(07H,0H):EBX.
SGX
CPUID.(12H)
FEATURE_CONTROL. FEATURE_CONTROL.
LOCK
SGX_ENABLE
Enclave Instruction
1
Valid*
0
X
#GP
1
Valid*
1
0
#GP
1
Valid*
1
1
Available (see Table 37-4 for details
of SGX1 and SGX2).
* Leaf 12H enumeration results are dependent on enablement.
** See list of conditions in the #UD section of the reference pages of ENCLS and ENCLU
37.7.2
Intel® SGX Resource Enumeration Leaves
If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying CPUID with EAX=12H on Intel
SGX resource capability and configuration. The number of available sub-leaves in leaf 12H depends on the Opt-in
and system software configuration. Information returned by CPUID.12H is thread specific; software should not
assume that if Intel SGX instructions are supported on one hardware thread, they are also supported elsewhere.
A properly configured processor exposes Intel SGX functionality with CPUID.EAX=12H reporting valid information
(non-zero content) in three or more sub-leaves, see Table 37-4.
•
•
CPUID.(EAX=12H, ECX=0H) enumerates Intel SGX capability, including enclave instruction opcode support.
•
CPUID.(EAX=12H, ECX >1) enumerates available EPC resources.
CPUID.(EAX=12H, ECX=1H) enumerates Intel SGX capability of processor state configuration and enclave
configuration in the SECS structure (see Table 38-3).
Table 37-4. CPUID Leaf 12H, Sub-Leaf 0 Enumeration of Intel® SGX Capabilities
CPUID.(EAX=12H,ECX=0)
Register
EAX
EBX
ECX
EDX
Description Behavior
Bits
0
SGX1: If 1, indicates leaf functions of SGX1 instruction listed in Table 37-1 are supported.
1
SGX2: If 1, indicates leaf functions of SGX2 instruction listed in Table 37-2 are supported.
31:2
Reserved (0)
31:0
MISCSELECT: Reports the bit vector of supported extended features that can be written to the MISC
region of the SSA.
31:0
Reserved (0).
7:0
MaxEnclaveSize_Not64: the maximum supported enclave size is 2^(EDX[7:0]) bytes when not in 64-bit
mode.
15:8
MaxEnclaveSize_64: the maximum supported enclave size is 2^(EDX[15:8]) bytes when operating in 64bit mode.
31:16
Reserved (0).
Table 37-5. CPUID Leaf 12H, Sub-Leaf 1 Enumeration of Intel® SGX Capabilities
CPUID.(EAX=12H,ECX=1)
Register
Description Behavior
Bits
EAX
31:0
Report the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE.
SECS.ATTRIBUTES[n] can be set to 1 using ECREATE only if EAX[n] is 1, where n < 32.
EBX
31:0
Report the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE.
SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE only if EBX[n] is 1, where n < 32.
Vol. 3D 37-5
INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
Table 37-5. CPUID Leaf 12H, Sub-Leaf 1 Enumeration of Intel® SGX Capabilities
CPUID.(EAX=12H,ECX=1)
Register
Description Behavior
Bits
ECX
31:0
Report the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.
SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE only if ECX[n] is 1, where n < 32.
EDX
31:0
Report the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.
SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE only if EDX[n] is 1, where n < 32.
On processors that support Intel SGX1 and SGX2, CPUID leaf 12H sub-leaf 2 report physical memory resources
available for use with Intel SGX. These physical memory sections are typically allocated by BIOS as Processor
Reserved Memory, and available to the OS to manage as EPC.
To enumerate how many EPC sections are available to the EPC manager, software can enumerate CPUID leaf 12H
with sub-leaf index starting from 2, and decode the sub-leaf-type encoding (returned in EAX[3:0]) until the subleaf type is invalid. All invalid sub-leaves of CPUID leaf 12H return EAX/EBX/ECX/EDX with 0.
Table 37-6. CPUID Leaf 12H, Sub-Leaf Index 2 or Higher Enumeration of Intel® SGX Resources
CPUID.(EAX=12H,ECX > 1)
Register
EAX
Description Behavior
Bits
3:0
0000b: This sub-leaf is invalid; EDX:ECX:EBX:EAX return 0.
0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the
Enclave Page Cache (EPC) section.
All other encoding are reserved.
EBX
11:4
Reserved (enumerate 0).
31:12
If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of the base of the EPC section.
19:0
If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of the base of the EPC section.
31:20
Reserved.
3: 0
If EAX[3:0] 0000b, then all bits of the EDX:ECX pair are enumerated as 0.
If EAX[3:0] 0001b, then this section has confidentiality and integrity protection.
ECX
EDX
37-6 Vol. 3D
All other encoding are reserved.
11:4
Reserved (enumerate 0).
31:12
If EAX[3:0] = 0001b, these are bits 31:12 of the size of the corresponding EPC section within the
Processor Reserved Memory.
19: 0
If EAX[3:0] = 0001b, these are bits 51:32 of the size of the corresponding EPC section within the
Processor Reserved Memory.
31:20
Reserved.
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
CHAPTER 38
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.1
OVERVIEW OF ENCLAVE EXECUTION ENVIRONMENT
When an enclave is created, it has a range of linear addresses that the processor applies enhanced access control.
This ranged is called the ELRANGE (see Section 37.3). When an enclave generates a memory access, the existing
IA32 segmentation and paging architecture are applied. Additionally, linear addresses inside the ELRANGE must
map to an EPC page otherwise when an enclave attempts to access that linear address a fault is generated.
The EPC pages need not be physically contiguous. System software allocates EPC pages to various enclaves.
Enclaves must abide by OS/VMM imposed segmentation and paging policies. OS/VMM-managed page tables and
extended page tables provide address translation for the enclave pages. Hardware requires that these pages are
properly mapped to EPC (any failure generates an exception).
Enclave entry must happen through specific enclave instructions:
•
ENCLU[EENTER], ENCLU[ERESUME].
Enclave exit must happen through specific enclave instructions or events:
•
ENCLU[EEXIT], Asynchronous Enclave Exit (AEX).
Attempts to execute, read, or write to linear addresses mapped to EPC pages when not inside an enclave will result
in the processor altering the access to preserve the confidentiality and integrity of the enclave. The exact behavior
may be different between implementations. As an example a read of an enclave page may result in the return of all
one's or return of cyphertext of the cache line. Writing to an enclave page may result in a dropped write or a
machine check at a later time. The processor will provide the protections as described in Section 38.4 and Section
38.5 on such accesses.
38.2
TERMINOLOGY
A memory access to the ELRANGE and initiated by an instruction executed by an enclave is called a Direct Enclave
Access (Direct EA).
Memory accesses initiated by certain Intel® SGX instruction leaf functions such as ECREATE, EADD, EDBGRD,
EDBGWR, ELDU/ELDB, EWB, EREMOVE, EENTER, and ERESUME to EPC pages are called Indirect Enclave Accesses
(Indirect EA). Table 38-1 lists additional details of the indirect EA of SGX1 and SGX2 extensions.
Direct EAs and Indirect EAs together are called Enclave Accesses (EAs).
Any memory access that is not an Enclave Access is called a non-enclave access.
38.3
ACCESS-CONTROL REQUIREMENTS
Enclave accesses have the following access-control attributes:
•
•
•
All memory accesses must conform to segmentation and paging protection mechanisms.
•
EPC pages of page types PT_REG, PT_TCS and PT_TRIM must be mapped to ELRANGE at the linear address
specified when the EPC page was allocated to the enclave using ENCLS[EADD] or ENCLS[EAUG] leaf functions.
Enclave accesses through other linear address result in a #PF with the PFEC.SGX bit set.
•
Direct EAs to any EPC pages must conform to the currently defined security attributes for that EPC page in the
EPCM. These attributes may be defined at enclave creation time (EADD) or when the enclave sets them using
SGX2 instructions. The failure of these checks results in a #PF with the PFEC.SGX bit set.
Code fetches from inside an enclave to a linear address outside that enclave result in a #GP(0) exception.
Non-enclave accesses to EPC memory result in undefined behavior. EPC memory is protected as described in
Section 38.4 and Section 38.5 on such accesses.
Vol. 3D 38-1
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
— Target page must belong to the currently executing enclave.
— Data may be written to an EPC page if the EPCM allow write access.
— Data may be read from an EPC page if the EPCM allow read access.
— Instruction fetches from an EPC page are allowed if the EPCM allows execute access.
— Target page must not have a restricted page type1 (PT_SECS, PT_TCS, PT_VA, or PT_TRIM).
— The EPC page must not be BLOCKED.
— The EPC page must not be PENDING.
— The EPC page must not be MODIFIED.
38.4
SEGMENT-BASED ACCESS CONTROL
Intel SGX architecture does not modify the segment checks performed by a logical processor. All memory accesses
arising from a logical processor in protected mode (including enclave access) are subject to segmentation checks
with the applicable segment register.
To ensure that outside entities do not modify the enclave's logical-to-linear address translation in an unexpected
fashion, ENCLU[EENTER] and ENCLU[ERESUME] check that CS, DS, ES, and SS, if usable (i.e., not null), have
segment base value of zero. A non-zero segment base value for these registers results in a #GP(0).
On enclave entry either via EENTER or ERESUME, the processor saves the contents of the external FS and GS registers, and loads these registers with values stored in the TCS at build time to enable the enclave’s use of these registers for accessing the thread-local storage inside the enclave. On EEXIT and AEX, the contents at time of entry are
restored. On AEX, the values of FS and GS are saved in the SSA frame. On ERESUME, FS and GS are restored from
the SSA frame. The details of these operations can be found in the descriptions of EENTER, ERESUME, EEXIT, and
AEX flows.
38.5
PAGE-BASED ACCESS CONTROL
38.5.1
Access-control for Accesses that Originate from non-SGX Instructions
Intel SGX builds on the processor's paging mechanism to provide page-granular access-control for enclave pages.
Enclave pages are only accessible from inside the currently executing enclave if they belong to that enclave. In
addition, enclave accesses must conform to the access control requirements described in Section 38.3. or through
certain Intel SGX instructions. Attempts to execute, read, or write to linear addresses mapped to EPC pages when
not inside an enclave will result in the processor altering the access to preserve the confidentiality and integrity of
the enclave. The exact behavior may be different between implementations.
38.5.2
Memory Accesses that Split across ELRANGE
Memory data accesses are allowed to split across ELRANGE (i.e., a part of the access is inside ELRANGE and a part
of the access is outside ELRANGE) while the processor is inside an enclave. If an access splits across ELRANGE, the
processor splits the access into two sub-accesses (one inside ELRANGE and the other outside ELRANGE), and each
access is evaluated. A code-fetch access that splits across ELRANGE results in a #GP due to the portion that lies
outside of the ELRANGE.
38.5.3
Implicit vs. Explicit Accesses
Memory accesses originating from Intel SGX instruction leaf functions are categorized as either explicit accesses or
implicit accesses. Table 38-1 lists the implicit and explicit memory accesses made by Intel SGX leaf functions.
1. EPCM may allow write, read or execute access only for pages with page type PT_REG.
38-2 Vol. 3D
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.5.3.1
Explicit Accesses
Accesses to memory locations provided as explicit operands to Intel SGX instruction leaf functions, or their linked
data structures are called explicit accesses.
Explicit accesses are always made using logical addresses. These accesses are subject to segmentation, paging,
extended paging, and APIC-virtualization checks, and trigger any faults/exit associated with these checks when the
access is made.
The interaction of explicit memory accesses with data breakpoints is leaf-function-specific, and is documented in
Section 43.3.4.
38.5.3.2
Implicit Accesses
Accesses to data structures whose physical addresses are cached by the processor are called implicit accesses.
These addresses are not passed as operands of the instruction but are implied by use of the instruction.
These accesses do not trigger any access-control faults/exits or data breakpoints. Table 38-1 lists memory objects
that Intel SGX instruction leaf functions access either by explicit access or implicit access. The addresses of explicit
access objects are passed via register operands with the second through fourth column of Table 38-1 matching
implicitly encoded registers RBX, RCX, RDX.
Physical addresses used in different implicit accesses are cached via different instructions and for different durations. The physical address of SECS associated with each EPC page is cached at the time the page is added to the
enclave via ENCLS[EADD] or ENCLS[EAUG], or when the page is loaded to EPC via ENCLS[ELDB] or ENCLS[ELDU].
This binding is severed when the corresponding page is removed from the EPC via ENCLS[EREMOVE] or
ENCLS[EWB]. Physical addresses of TCS and SSA pages are cached at the time of most-recent enclave entry. Exit
from an enclave (ENCLU[EEXIT] or AEX) flushes this caching. Details of Asynchronous Enclave Exit is described in
Chapter 40.
The physical addresses that are cached for use by implicit accesses are derived from logical (or linear) addresses
after checks such as segmentation, paging, EPT, and APIC virtualization checks. These checks may trigger exceptions or VM exits. Note, however, that such exception or VM exits may not occur after a physical address is cached
and used for an implicit access.
Table 38-1. List of Implicit and Explicit Memory Access by Intel® SGX Enclave Instructions
Instr. Leaf
Enum.
Explicit 1
Explicit 2
EACCEPT
SGX2
SECINFO
EPCPAGE
EACCEPTCOPY
SGX2
SECINFO
EPCPAGE (Src)
EADD
SGX1
PAGEINFO and linked structures
EPCPAGE
EPCPAGE
Explicit 3
Implicit
SECS
EPCPAGE (Dst)
EAUG
SGX2
PAGEINFO and linked structures
EBLOCK
SGX1
EPCPAGE
SECS
ECREATE
SGX1
PAGEINFO and linked structures
EPCPAGE
EDBGRD
SGX1
EPCADDR
Destination
EDBGWR
SGX1
EPCADDR
Source
EENTER
SGX1
TCS and linked SSA
EEXIT
SGX1
EEXTEND
SGX1
SECS
EPCPAGE
EGETKEY
SGX1
KEYREQUEST
KEY
EINIT
SGX1
SIGSTRUCT
SECS
EINITTOKEN
ELDB/ELDU
SGX1
PAGEINFO and linked structures, PCMD
EPCPAGE
VAPAGE
EMODPE
SGX2
SECINFO
EPCPAGE
EMODPR
SGX2
SECINFO
EPCPAGE
SECS
EMODT
SGX2
SECINFO
EPCPAGE
SECS
SECS
SECS
SECS
SECS
SECS, TCS
SECS
Vol. 3D 38-3
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Table 38-1. List of Implicit and Explicit Memory Access by Intel® SGX Enclave Instructions (Contd.)
Instr. Leaf
Enum.
EPA
SGX1
Explicit 1
Explicit 2
Explicit 3
REPORTDATA
OUTPUTDATA
Implicit
EPCADDR
EREMOVE
SGX1
EPCPAGE
EREPORT
SGX1
TARGETINFO
SECS
ERESUME
SGX1
TCS and linked SSA
ETRACK
SGX1
EPCPAGE
EWB
SGX1
PAGEINFO and linked structures, PCMD
SECS
SECS
EPCPAGE
VAPAGE
Asynchronous Enclave Exit*
SECS
SECS, TCS,
SSA
*Details of Asynchronous Enclave Exit (AEX) is described in Section 40.4
38.6
INTEL® SGX DATA STRUCTURES OVERVIEW
Enclave operation is managed via a collection of data structures. Many of the top-level data structures contain substructures. The top-level data structures relate to parameters that may be used in enclave setup/maintenance, by
Intel SGX instructions, or AEX event. The top-level data structures are:
•
•
•
•
•
•
•
•
•
•
•
•
•
SGX Enclave Control Structure (SECS)
Thread Control Structure (TCS)
State Save Area (SSA)
Page Information (PAGEINFO)
Security Information (SECINFO)
Paging Crypto MetaData (PCMD)
Enclave Signature Structure (SIGSTRUCT)
EINIT Token Structure (EINITTOKEN)
Report Structure (REPORT)
Report Target Info (TARGETINFO)
Key Request (KEYREQUEST)
Version Array (VA)
Enclave Page Cache Map (EPCM)
Details of the top-level data structures and associated sub-structures are listed in Section 38.7 through Section
38.19.
38.7
SGX ENCLAVE CONTROL STRUCTURE (SECS)
The SECS data structure requires 4K-Bytes alignment.
Table 38-2. Layout of SGX Enclave Control Structure (SECS)
Field
OFFSET (Bytes)
Size (Bytes)
Description
SIZE
0
8
Size of enclave in bytes; must be power of 2.
BASEADDR
8
8
Enclave Base Linear Address must be naturally aligned to size.
SSAFRAMESIZE
16
4
Size of one SSA frame in pages, including XSAVE, pad, GPR, and MISC (if
CPUID.(EAX=12H, ECX=0):.EBX != 0).
MISCSELECT
20
4
Bit vector specifying which extended features are saved to the MISC region
(see Section 38.7.2) of the SSA frame when an AEX occurs.
38-4 Vol. 3D
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Table 38-2. Layout of SGX Enclave Control Structure (SECS) (Contd.)
Field
OFFSET (Bytes)
Size (Bytes)
Description
RESERVED
24
24
ATTRIBUTES
48
16
Attributes of the Enclave, see Table 38-3.
MRENCLAVE
64
32
Measurement Register of enclave build process. See SIGSTRUCT for format.
RESERVED
96
32
MRSIGNER
128
32
RESERVED
160
96
ISVPRODID
256
2
Measurement Register extended with the public key that verified the
enclave. See SIGSTRUCT for format.
Product ID of enclave.
ISVSVN
258
2
Security version number (SVN) of the enclave.
RESERVED
260
3836
The RESERVED field consists of the following:
• EID: An 8 byte Enclave Identifier. Its location is implementation specific.
• PAD: A 352 bytes padding pattern from the Signature (used for key
derivation strings). It’s location is implementation specific.
• The remaining 3476 bytes are reserved area.
The entire 3836 byte field must be cleared prior to executing ECREATE or
EREPORT.
38.7.1
ATTRIBUTES
The ATTRIBUTES data structure is comprised of bit-granular fields that are used in the SECS, the REPORT and the
KEYREQUEST structures. CPUID.(EAX=12H, ECX=1) enumerates a bitmap of permitted 1-setting of bits in ATTRIBUTES.
Table 38-3. Layout of ATTRIBUTES Structure
Field
Bit Position
INIT
0
Description
This bit indicates if the enclave has been initialized by EINIT. It must be cleared when loaded as
part of ECREATE. For EREPORT instruction, TARGET_INFO.ATTRIBUTES[ENIT] must always be 1 to
match the state after EINIT has initialized the enclave.
DEBUG
1
If 1, the enclave permit debugger to read and write enclave data using EDBGRD and EDBGWR.
MODE64BIT
2
Enclave runs in 64-bit mode.
RESERVED
3
Must be Zero.
PROVISIONKEY
4
Provisioning Key is available from EGETKEY.
EINITTOKENKEY
5
EINIT token key is available from EGETKEY.
RESERVED
63:6
XFRM
127:64
38.7.2
XSAVE Feature Request Mask. See Section 42.7.
SECS.MISCSELECT Field
CPUID.(EAX=12H, ECX=0):EBX[31:0] enumerates which extended information that the processor can save into
the MISC region of SSA when an AEX occurs. An enclave writer can specify via SIGSTRUCT how to set the
SECS.MISCSELECT field. The bit vector of MISCSELECT selects which extended information is to be saved in the
MISC region of the SSA frame when an AEX is generated. The bit vector definition of extended information is listed
in Table 38-4.
If CPUID.(EAX=12H, ECX=0):EBX[31:0] = 0, SECS.MISCSELECT field must be all zeros.
The SECS.MISCSELECT field determines the size of MISC region of the SSA frame, see Section 38.9.2.
Vol. 3D 38-5
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Table 38-4. Bit Vector Layout of MISCSELECT Field of Extended Information
Field
Bit Position
Description
EXINFO
0
Report information about page fault and general protection exception that occurred inside an
enclave.
Reserved
31:1
Reserved (0).
38.8
THREAD CONTROL STRUCTURE (TCS)
Each executing thread in the enclave is associated with a Thread Control Structure. It requires 4K-Bytes alignment.
Table 38-5. Layout of Thread Control Structure (TCS)
Field
STAGE
OFFSET (Bytes)
0
Size (Bytes)
8
Description
Enclave execution state of the thread controlled by this TCS. A value of 0 indicates that this TCS is available for enclave entry. A value of 1 indicates that a
processer is currently executing an enclave in the context of this TCS.
FLAGS
8
8
The thread’s execution flags (see Section 38.8.1).
OSSA
16
8
Offset of the base of the State Save Area stack, relative to the enclave base.
Must be page aligned.
CSSA
24
4
Current slot index of an SSA frame, cleared by EADD and EACCEPT.
NSSA
28
4
Number of available slots for SSA frames.
OENTRY
32
8
Offset in enclave to which control is transferred on EENTER relative to the
base of the enclave.
AEP
40
8
The value of the Asynchronous Exit Pointer that was saved at EENTER time.
OFSBASGX
48
8
Offset to add to the base address of the enclave for producing the base
address of FS segment inside the enclave. Must be page aligned.
OGSBASGX
56
8
Offset to add to the base address of the enclave for producing the base
address of GS segment inside the enclave. Must be page aligned.
FSLIMIT
64
4
Size to become the new FS limit in 32-bit mode.
GSLIMIT
68
4
Size to become the new GS limit in 32-bit mode.
RESERVED
72
4024
Must be zero.
38.8.1
TCS.FLAGS
Table 38-6. Layout of TCS.FLAGS Field
Field
Bit Position
DBGOPTIN
0
RESERVED
63:1
38.8.2
Description
If set, allows debugging features (single-stepping, breakpoints, etc.) to be enabled and active while
executing in the enclave on this TCS. Hardware clears this bit on EADD. A debugger may later modify it if the enclave’s ATTRIBUTES.DEBUG is set.
State Save Area Offset (OSSA)
The OSSA points to a stack of State Save Area (SSA) frames (see Section 38.9) used to save the processor state
when an interrupt or exception occurs while executing in the enclave.
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ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.8.3
Current State Save Area Frame (CSSA)
CSSA is the index of the current SSA frame that will be used by the processor to determine where to save the
processor state on an interrupt or exception that occurs while executing in the enclave. It is an index into the array
of frames addressed by OSSA. CSSA is incremented on an AEX and decremented on an ERESUME.
38.8.4
Number of State Save Area Frames (NSSA)
NSSA specifies the number of SSA frames available for this TCS. There must be at least one available SSA frame
when EENTER-ing the enclave or the EENTER will fail.
38.9
STATE SAVE AREA (SSA) FRAME
When an AEX occurs while running in an enclave, the architectural state is saved in the thread’s current SSA frame,
which is pointed to by TCS.CSSA. An SSA frame must be page aligned, and contains the following regions:
•
The XSAVE region starts at the base of the SSA frame, this region contains extended feature register state in
an XSAVE/FXSAVE-compatible non-compacted format.
•
A Pad region: software may choose to maintain a pad region separating the XSAVE region and the MISC region.
Software choose the size of the pad region according to the sizes of the MISC and GPRSGX regions.
•
The GPRSGX region. The GPRSGX region is the last region of an SSA frame (see Table 38-7). This is used to
hold the processor general purpose registers (RAX … R15), the RIP, the outside RSP and RBP, RFLAGS and the
AEX information.
•
The MISC region (If CPUIDEAX=12H, ECX=0):EBX[31:0] != 0). The MISC region is adjacent to the GRPSGX
region, and may contain zero or more components of extended information that would be saved when an AEX
occurs. If the MISC region is absent, the region between the GPRSGX and XSAVE regions is the pad region that
software can use. If the MISC region is present, the region between the MISC and XSAVE regions is the pad
region that software can use. See additional details in Section 38.9.2.
Table 38-7. Top-to-Bottom Layout of an SSA Frame
Region
Offset (Byte)
Size (Bytes)
Description
XSAVE
0
Calculate using CPUID The size of XSAVE region in SSA is derived from the enclave’s support of the colleaf 0DH information lection of processor extended states that would be managed by XSAVE. The
enablement of those processor extended state components in conjunction with
CPUID leaf 0DH information determines the XSAVE region size in SSA.
Pad
End of XSAVE
region
Chosen by enclave
writer
MISC
base of GPRSGX Calculate from high– sizeof(MISC)
est set bit of
SECS.MISCSELECT
See Section 38.9.2.
GPRSGX
SSAFRAMESIZE 176
– 176
See Table 38-8 for layout of the GPRSGX region.
Ensure the end of GPRSGX region is aligned to the end of a 4KB page.
Vol. 3D 38-7
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.9.1
GPRSGX Region
The layout of the GPRSGX region is shown in Table 38-8.
Table 38-8. Layout of GPRSGX Portion of the State Save Area
Field
OFFSET (Bytes)
Size (Bytes)
Description
RAX
0
8
RCX
8
8
RDX
16
8
RBX
24
8
RSP
32
8
RBP
40
8
RSI
48
8
RDI
56
8
R8
64
8
R9
72
8
R10
80
8
R11
88
8
R12
96
8
R13
104
8
R14
112
8
R15
120
8
RFLAGS
128
8
Flag register.
RIP
136
8
Instruction pointer.
URSP
144
8
Non-Enclave (outside) stack pointer. Saved by EENTER, restored on AEX.
URBP
152
8
Non-Enclave (outside) RBP pointer. Saved by EENTER, restored on AEX.
EXITINFO
160
4
Contains information about exceptions that cause AEXs, which might be
needed by enclave software (see Section 38.9.1.1).
RESERVED
164
4
FSBASE
168
8
FS BASE.
GSBASE
176
8
GS BASE.
38.9.1.1
EXITINFO
EXITINFO contains the information used to report exit reasons to software inside the enclave. It is a 4 byte field laid
out as in Table 38-9. The VALID bit is set only for the exceptions conditions which are reported inside an enclave.
See Table 38-10 for which exceptions are reported inside the enclave. If the exception condition is not one reported
inside the enclave then VECTOR and EXIT_TYPE are cleared.
38-8 Vol. 3D
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Table 38-9. Layout of EXITINFO Field
Field
Bit Position
Description
VECTOR
7:0
Exception number of exceptions reported inside enclave.
EXIT_TYPE
10:8
011b: Hardware exceptions.
110b: Software exceptions.
Other values: Reserved.
RESERVED
30:11
Reserved as zero.
VALID
31
0: unsupported exceptions.
1: Supported exceptions. Includes two categories:
•
•
Unconditionally supported exceptions: #DE, #DB, #BP, #BR, #UD, #MF, #AC, #XM.
Conditionally supported exception:
—
38.9.1.2
#PF, #GP if SECS.MISCSELECT.EXINFO = 1.
VECTOR Field Definition
Table 38-10 contains the VECTOR field. This field contains information about some exceptions which occur inside
the enclave. These vector values are the same as the values that would be used when vectoring into regular exception handlers. All values not shown are not reported inside an enclave.
Table 38-10. Exception Vectors
Name
Vector #
Description
#DE
0
Divider exception.
#DB
1
Debug exception.
#BP
3
Breakpoint exception.
#BR
5
Bound range exceeded exception.
#UD
6
Invalid opcode exception.
#GP
13
General protection exception. Only reported if SECS.MISCSELECT.EXINFO = 1.
#PF
14
Page fault exception. Only reported if SECS.MISCSELECT.EXINFO = 1.
#MF
16
x87 FPU floating-point error.
#AC
17
Alignment check exceptions.
#XM
19
SIMD floating-point exceptions.
38.9.2
MISC Region
The layout of the MISC region is shown in Table 38-11. The number of components that the processor supports in
the MISC region corresponds to the set bits of CPUID.(EAX=12H, ECX=0):EBX[31:0] set to 1. Each set bit in
CPUID.(EAX=12H, ECX=0):EBX[31:0] has a defined size for the corresponding component, as shown in Table
38-11. Enclave writers needs to do the following:
•
•
•
Decide which MISC region components will be supported for the enclave.
Allocate an SSA frame large enough to hold the components chosen above.
Instruct each enclave builder software to set the appropriate bits in SECS.MISCSELECT.
The first component, EXINFO, starts next to the GPRSGX region. Additional components in the MISC region grow
in ascending order within the MISC region towards the XSAVE region.
The size of the MISC region is calculated as follows:
•
•
If CPUID.(EAX=12H, ECX=0):EBX[31:0] = 0, MISC region is not supported.
If CPUID.(EAX=12H, ECX=0):EBX[31:0] != 0, the size of MISC region is derived from sum of the highest bit set
in SECS.MISCSELECT and the size of the MISC component corresponding to that bit. Offset and size
Vol. 3D 38-9
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
information of currently defined MISC components are listed in Table 38-11. For example, if the highest bit set
in SECS.MISCSELECT is bit 0, the MISC region offset is OFFSET(GPRSGX)-16 and size is 16 bytes.
•
The processor saves a MISC component i in the MISC region if and only if SECS.MISCSELECT[i] is 1.
Table 38-11. Layout of MISC region of the State Save Area
MISC Components
OFFSET (Bytes)
Size (Bytes)
Description
EXINFO
Offset(GPRSGX) –16 16
if CPUID.(EAX=12H, ECX=0):EBX[0] = 1, exception information on #GP or
#PF that occurred inside an enclave can be written to the EXINFO structure
if specified by SECS.MISCSELECT[0] = 1.
Future Extension
Below EXINFO
Reserved. (Zero size if CPUID.(EAX=12H, ECX=0):EBX[31:1] =0).
38.9.2.1
TBD
EXINFO Structure
Table 38-12 contains the layout of the EXINFO structure that provides additional information.
Table 38-12. Layout of EXINFO Structure
Field
OFFSET (Bytes)
Size (Bytes)
Description
MADDR
0
8
If #PF: contains the page fault linear address that caused a page fault.
If #GP: the field is cleared.
ERRCD
8
4
Exception error code for either #GP or #PF.
RESERVED
12
4
38.9.2.2
Page Fault Error Codes
Table 38-13 contains page fault error code that may be reported in EXINFO.ERRCD.
Table 38-13. Page Fault Error Codes
Name
P
Bit Position
Description
0
Same as non-SGX page fault exception P flag.
W/R
1
Same as non-SGX page fault exception W/R flag.
1
2
Always set to 1 (user mode reference).
RSVD
3
Same as non-SGX page fault exception RSVD flag.
I/D
4
Same as non-SGX page fault exception I/D flag.
PK
5
Protection Key induced fault.
RSVD
14:6
Reserved.
SGX
15
EPCM induced fault.
RSVD
31:5
Reserved.
U/S
NOTES:
1. Page faults incident to enclave mode that report U/S=0 are not reported in EXINFO
38.10
PAGE INFORMATION (PAGEINFO)
PAGEINFO is an architectural data structure that is used as a parameter to the EPC-management instructions. It
requires 32-Byte alignment.
38-10 Vol. 3D
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Table 38-14. Layout of PAGEINFO Data Structure
Field
OFFSET (Bytes)
LINADDR
0
Size (Bytes)
8
Description
Enclave linear address.
SRCPGE
8
8
Effective address of the page where contents are located.
SECINFO/PCMD
16
8
Effective address of the SECINFO or PCMD (for ELDU, ELDB, EWB) structure for
the page.
SECS
24
8
Effective address of EPC slot that currently contains the SECS.
38.11
SECURITY INFORMATION (SECINFO)
The SECINFO data structure holds meta-data about an enclave page.
Table 38-15. Layout of SECINFO Data Structure
Field
OFFSET (Bytes)
Size (Bytes)
Description
FLAGS
0
8
Flags describing the state of the enclave page.
RESERVED
8
56
Must be zero.
38.11.1 SECINFO.FLAGS
The SECINFO.FLAGS are a set of fields describing the properties of an enclave page.
Table 38-16. Layout of SECINFO.FLAGS Field
Field
Bit Position
Description
R
0
If 1 indicates that the page can be read from inside the enclave; otherwise the page cannot be read
from inside the enclave.
W
1
If 1 indicates that the page can be written from inside the enclave; otherwise the page cannot be written from inside the enclave.
X
2
If 1 indicates that the page can be executed from inside the enclave; otherwise the page cannot be
executed from inside the enclave.
PENDING
3
If 1 indicates that the page is in the PENDING state; otherwise the page is not in the PENDING state.
MODIFIED
4
If 1 indicates that the page is in the MODIFIED state; otherwise the page is not in the MODIFIED state.
PR
5
If 1 indicates that a permission restriction operation on the page is in progress, otherwise a permission
restriction operation is not in progress.
RESERVED
7:6
Must be zero.
PAGE_TYPE
15:8
The type of page that the SECINFO is associated with.
RESERVED
63:16
Must be zero.
Vol. 3D 38-11
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.11.2 PAGE_TYPE Field Definition
The SECINFO flags and EPC flags contain bits indicating the type of page.
Table 38-17. Supported PAGE_TYPE
TYPE
Value
Description
PT_SECS
0
Page is an SECS.
PT_TCS
1
Page is a TCS.
PT_REG
2
Page is a regular page.
PT_VA
3
Page is a Version Array.
PT_TRIM
4
Page is in trimmed state.
All other
Reserved.
38.12
PAGING CRYPTO METADATA (PCMD)
The PCMD structure is used to keep track of crypto meta-data associated with a paged-out page. Combined with
PAGEINFO, it provides enough information for the processor to verify, decrypt, and reload a paged-out EPC page.
The size of the PCMD structure (128 bytes) is architectural.
EWB calculates the Message Authentication Code (MAC) value and writes out the PCMD. ELDB/U reads the fields
and checks the MAC.
The format of PCMD is as follows:
Table 38-18. Layout of PCMD Data Structure
Field
OFFSET (Bytes)
Size (Bytes)
Description
SECINFO
0
64
Flags describing the state of the enclave page; R/W by software.
ENCLAVEID
64
8
Enclave Identifier used to establish a cryptographic binding between paged-out
page and the enclave.
RESERVED
72
40
Must be zero.
MAC
112
16
Message Authentication Code for the page, page meta-data and reserved
field.
38.13
ENCLAVE SIGNATURE STRUCTURE (SIGSTRUCT)
SIGSTRUCT is a structure created and signed by the enclave developer that contains information about the
enclave. SIGSTRUCT is processed by the EINIT leaf function to verify that the enclave was properly built.
SIGSTRUCT includes ENCLAVEHASH as SHA256 digest, as defined in FIPS PUB 180-4. The digests are byte strings
of length 32. Each of the 8 HASH dwords is stored in little-endian order.
SIGSTRUCT includes four 3072-bit integers (MODULUS, SIGNATURE, Q1, Q2). Each such integer is represented as
a byte strings of length 384, with the most significant byte at the position “offset + 383”, and the least significant
byte at position “offset”.
The (3072-bit integer) SIGNATURE should be an RSA signature, where: a) the RSA modulus (MODULUS) is a 3072bit integer; b) the public exponent is set to 3; c) the signing procedure uses the EMSA-PKCS1-v1.5 format with DER
encoding of the “DigestInfo” value as specified in of PKCS#1 v2.1/RFC 3447.
The 3072-bit integers Q1 and Q2 are defined by:
q1 = floor(Signature^2 / Modulus);
q2 = floor((Signature^3 - q1 * Signature * Modulus) / Modulus);
SIGSTRUCT must be page aligned
38-12 Vol. 3D
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
In column 5 of Table 38-19, ‘Y’ indicates that this field should be included in the signature generated by the developer.
Table 38-19. Layout of Enclave Signature Structure (SIGSTRUCT)
Field
OFFSET (Bytes)
Size (Bytes)
Description
Signed
HEADER
0
16
Must be byte stream
06000000E10000000000010000000000H
Y
VENDOR
16
4
Intel Enclave: 00008086H
Non-Intel Enclave: 00000000H
Y
DATE
20
4
Build date is yyyymmdd in hex:
yyyy=4 digit year, mm=1-12, dd=1-31
Y
HEADER2
24
16
Must be byte stream
01010000600000006000000001000000H
Y
SWDEFINED
40
4
Available for software use.
Y
RESERVED
44
84
Must be zero.
Y
MODULUS
128
384
Module Public Key (keylength=3072 bits).
N
EXPONENT
512
4
RSA Exponent = 3.
N
SIGNATURE
516
384
Signature over Header and Body.
N
MISCSELECT*
900
4
Bit vector specifying Extended SSA frame feature set to be
used.
Y
MISCMASK*
904
4
Bit vector mask of MISCSELECT to enforce.
Y
RESERVED
908
20
Must be zero.
Y
ATTRIBUTES
928
16
Enclave Attributes that must be set.
Y
ATTRIBUTEMASK
944
16
Mask of Attributes to enforce.
Y
ENCLAVEHASH
960
32
MRENCLAVE of enclave this structure applies to.
Y
RESERVED
992
32
Must be zero.
Y
ISVPRODID
1024
2
ISV assigned Product ID.
Y
ISVSVN
1026
2
ISV assigned SVN (security version number).
Y
RESERVED
1028
12
Must be zero.
N
Q1
1040
384
Q1 value for RSA Signature Verification.
N
Q2
1424
384
Q2 value for RSA Signature Verification.
N
* If CPUID.(EAX=12H, ECX=0):EBX[31:0] = 0, MISCSELECT must be 0.
If CPUID.(EAX=12H, ECX=0):EBX[31:0] !=0, enclave writers must specify MISCSELECT such that each cleared
bit in MISCMASK must also specify the corresponding bit as 0 in MISCSELECT.
38.14
EINIT TOKEN STRUCTURE (EINITTOKEN)
The EINIT token is used by EINIT to verify that the enclave is permitted to launch. EINIT token is generated by an
enclave in possession of the EINITTOKEN key (the Launch Enclave).
EINIT token must be 512-Byte aligned.
Vol. 3D 38-13
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Table 38-20. Layout of EINIT Token (EINITTOKEN)
Field
OFFSET (Bytes)
Size (Bytes) MACed
Description
Valid
0
4
Y
Bit 0: 1: Valid; 0: Invalid.
All other bits reserved.
RESERVED
4
44
Y
Must be zero.
ATTRIBUTES
48
16
Y
ATTRIBUTES of the Enclave.
MRENCLAVE
64
32
Y
MRENCLAVE of the Enclave.
RESERVED
96
32
Y
Reserved.
MRSIGNER
128
32
Y
MRSIGNER of the Enclave.
RESERVED
160
32
Y
Reserved.
CPUSVNLE
192
16
N
Launch Enclave’s CPUSVN.
ISVPRODIDLE
208
02
N
Launch Enclave’s ISVPRODID.
ISVSVNLE
210
02
N
Launch Enclave’s ISVSVN.
RESERVED
212
24
N
Reserved.
MASKEDMISCSEL
ECTLE
236
4
Launch Enclave’s MASKEDMISCSELECT: set by the LE to the resolved
MISCSELECT value, used by EGETKEY (after applying KEYREQUEST’s
masking).
MASKEDATTRIBU 240
TESLE
16
N
Launch Enclave’s MASKEDATTRIBUTES: This should be set to the LE’s
ATTRIBUTES masked with ATTRIBUTEMASK of the LE’s KEYREQUEST.
KEYID
256
32
N
Value for key wear-out protection.
MAC
288
16
N
Message Authentication Code on EINITTOKEN using EINITOKENKEY.
38.15
REPORT (REPORT)
The REPORT structure is the output of the EREPORT instruction, and must be 512-Byte aligned.
Table 38-21. Layout of REPORT
Field
OFFSET (Bytes) Size (Bytes)
Description
CPUSVN
0
16
The security version number of the processor.
MISCSELECT
16
4
Bit vector specifying which extended features are saved to the MISC region of the
SSA frame when an AEX occurs.
RESERVED
20
28
Must be zero.
ATTRIBUTES
48
16
ATTRIBUTES of the Enclave. See Section 38.7.1.
MRENCLAVE
64
32
The value of SECS.MRENCLAVE.
RESERVED
96
32
Reserved.
MRSIGNER
128
32
The value of SECS.MRSIGNER.
RESERVED
160
96
Zero.
ISVPRODID
256
02
Product ID of enclave.
ISVSVN
258
02
Security version number (SVN) of the enclave.
RESERVED
260
60
Zero.
REPORTDATA
320
64
Data provided by the user and protected by the REPORT's MAC, see Section
38.15.1.
KEYID
384
32
Value for key wear-out protection.
MAC
416
16
Message Authentication Code on the report using report key.
38-14 Vol. 3D
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.15.1 REPORTDATA
REPORTDATA is a 64-Byte data structure that is provided by the enclave and included in the REPORT. It can be used
to securely pass information from the enclave to the target enclave.
38.16
REPORT TARGET INFO (TARGETINFO)
This structure is an input parameter to the EREPORT leaf function. The address of TARGETINFO is specified as an
effective address in RBX. It is used to identify the target enclave which will be able to cryptographically verify the
REPORT structure returned by EREPORT. TARGETINFO must be 512-Byte aligned.
Table 38-22. Layout of TARGETINFO Data Structure
Field
OFFSET (Bytes)
Size (Bytes)
Description
MEASUREMENT
0
32
The MRENCLAVE of the target enclave.
ATTRIBUTES
32
16
The ATTRIBUTES field of the target enclave.
RESERVED
48
4
MISCSELECT
52
4
RESERVED
56
456
38.17
The MISCSELECT of the target enclave.
KEY REQUEST (KEYREQUEST)
This structure is an input parameter to the EGETKEY leaf function. It is passed in as an effective address in RBX and
must be 512-Byte aligned. It is used for selecting the appropriate key and any additional parameters required in
the derivation of that key.
Table 38-23. Layout of KEYREQUEST Data Structure
Field
OFFSET (Bytes)
Size (Bytes)
Description
KEYNAME
0
02
Identifies the Key Required.
KEYPOLICY
02
02
Identifies which inputs are required to be used in the key derivation.
ISVSVN
04
02
The ISV security version number that will be used in the key derivation.
RESERVED
06
02
Must be zero.
CPUSVN
08
16
The security version number of the processor used in the key derivation.
ATTRIBUTEMASK 24
16
A mask defining which ATTRIBUTES bits will be included in key derivation.
KEYID
40
32
Value for key wear-out protection.
MISCMASK
72
4
A mask defining which MISCSELECT bits will be included in key derivation.
RESERVED
76
436
Vol. 3D 38-15
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38.17.1
KEY REQUEST KeyNames
Table 38-24. Supported KEYName Values
Key Name
Value
Description
EINITOKEN_KEY
0
EINIT_TOKEN key
PROVISION_KEY
1
Provisioning Key
PROVISION_SEAL_KEY
2
Provisioning Seal Key
REPORT_KEY
3
Report Key
SEAL_KEY
4
Seal Key
All other
Reserved
38.17.2
Key Request Policy Structure
Table 38-25. Layout of KEYPOLICY Field
Field
MRENCLAVE
Bit Position
0
Description
If 1, derive key using the enclave's MRENCLAVE measurement register.
MRSIGNER
1
If 1, derive key using the enclave's MRSIGNER measurement register.
RESERVED
15:2
Must be zero.
38.18
VERSION ARRAY (VA)
In order to securely store the versions of evicted EPC pages, Intel SGX defines a special EPC page type called a
Version Array (VA). Each VA page contains 512 slots, each of which can contain an 8-byte version number for a
page evicted from the EPC. When an EPC page is evicted, software chooses an empty slot in a VA page; this slot
receives the unique version number of the page being evicted. When the EPC page is reloaded, there must be a VA
slot that must hold the version of the page. If the page is successfully reloaded, the version in the VA slot is cleared.
VA pages can be evicted, just like any other EPC page. When evicting a VA page, a version slot in some other VA
page must be used to hold the version for the VA being evicted. A Version Array Page must be 4K-Bytes aligned.
Table 38-26. Layout of Version Array Data Structure
Field
OFFSET (Bytes)
Size (Bytes)
Description
Slot 0
0
08
Version Slot 0
Slot 1
8
08
Version Slot 1
4088
08
Version Slot 511
...
Slot 511
38.19
ENCLAVE PAGE CACHE MAP (EPCM)
EPCM is a secure structure used by the processor to track the contents of the EPC. The EPCM holds exactly one
entry for each page that is currently loaded into the EPC. EPCM is not accessible by software, and the layout of
EPCM fields is implementation specific.
38-16 Vol. 3D
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Table 38-27. Content of an Enclave Page Cache Map Entry
Field
Description
VALID
Indicates whether the EPCM entry is valid.
R
Read access; indicates whether enclave accesses for reads are allowed from the EPC page referenced by this
entry.
W
Write access; indicates whether enclave accesses for writes are allowed to the EPC page referenced by this
entry.
X
Execute access; indicates whether enclave accesses for instruction fetches are allowed from the EPC page
referenced by this entry.
PT
EPCM page type (PT_SECS, PT_TCS, PT_REG, PT_VA, PT_TRIM).
ENCLAVESECS
SECS identifier of the enclave to which the EPC page belongs.
ENCLAVEADDRESS
Linear enclave address of the EPC page.
BLOCKED
Indicates whether the EPC page is in the blocked state.
PENDING
Indicates whether the EPC page is in the pending state.
MODIFIED
Indicates whether the EPC page is in the modified state.
PR
Indicates whether the EPC page is in a permission restriction state.
Vol. 3D 38-17
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
38-18 Vol. 3D
ENCLAVE OPERATION
CHAPTER 39
ENCLAVE OPERATION
The following aspects of enclave operation are described in this chapter:
•
Enclave creation: Includes loading code and data from outside of enclave into the EPC and establishing the
enclave entity.
•
•
Adding pages and measuring the enclave.
•
Enclave entry and exiting including:
Initialization of an enclave: Finalizes the cryptographic log and establishes the enclave identity and sealing
identity.
— Controlled entry and exit.
— Asynchronous Enclave Exit (AEX) and resuming execution after an AEX.
39.1
CONSTRUCTING AN ENCLAVE
Figure 39-1 illustrates a typical Enclave memory layout.
SECS
Base + Size
Replicated once
per thread
OS Context
Enclave Memory
Thread Data
TCS
Application Context
Global Data
Code
Base
Enclave {Base, Size}
Figure 39-1. Enclave Memory Layout
The enclave creation, commitment of memory resources, and finalizing the enclave’s identity with measurement
comprises multiple phases. This process can be illustrated by the following exemplary steps:
1. The application hands over the enclave content along with additional information required by the enclave
creation API to the enclave creation service running at privilege level 0.
2. The enclave creation service running at privilege level 0 uses the ECREATE leaf function to set up the initial
environment, specifying base address and size of the enclave. This address range, the ELRANGE, is part of the
application's address space. This reserves the memory range. The enclave will now reside in this address
Vol. 3D 39-1
ENCLAVE OPERATION
region. ECREATE also allocates an Enclave Page Cache (EPC) page for the SGX Enclave Control Structure
(SECS). Note that this page is not required to be a part of the enclave linear address space and is not required
to be mapped into the process.
3. The enclave creation service uses the EADD leaf function to commit EPC pages to the enclave, and use
EEXTEND to measure the committed memory content of the enclave. For each page to be added to the enclave:
— Use EADD to add the new page to the enclave.
— If the enclave developer requires measurement of the page as a proof for the content, use EEXTEND to add
a measurement for 256 bytes of the page. Repeat this operation until the entire page is measured.
4. The enclave creation service uses the EINIT leaf function to complete the enclave creation process and finalize
the enclave measurement to establish the enclave identity. Until an EINIT is executed, the enclave is not
permitted to execute any enclave code (i.e. entering the enclave by executing EENTER would result in a fault).
39.1.1
ECREATE
The ECREATE leaf function sets up the initial environment for the enclave by reading an SGX Enclave Control Structure (SECS) that contains the enclave's address range (ELRANGE) as defined by BASEADDR and SIZE, the ATTRIBUTES and MISCSELECT bitmaps, and the SSAFRAMESIZE. It then securely stores this information in an Enclave
Page Cache (EPC) page. ELRANGE is part of the application's address space. ECREATE also initializes a cryptographic log of the enclave's build process.
39.1.2
EADD and EEXTEND Interaction
Once the SECS has been created, enclave pages can be added to the enclave via EADD. This involves converting a
free EPC page into either a PT_REG or a PT_TCS page.
When EADD is invoked, the processor will update the EPCM entry with the type of page (PT_REG or PT_TCS), the
linear address used by the enclave to access the page, and the enclave access permissions for the page. It associates the page to the SECS provided as input. The EPCM entry information is used by hardware to manage access
control to the page. EADD records EPCM information in the cryptographic log stored in the SECS and copies 4
KBytes of data from unprotected memory outside the EPC to the allocated EPC page.
System software is responsible for selecting a free EPC page. System software is also responsible for providing the
type of page to be added, the attributes the page, the contents of the page, and the SECS (enclave) to which the
page is to be added as requested by the application. Incorrect data would lead to a failure of EADD or to an incorrect cryptographic log and a failure at EINIT time.
After a page has been added to an enclave, software can measure a 256 byte region as determined by the developer by invoking EEXTEND. Thus to measure an entire 4KB page, system software must execute EEXTEND 16
times. Each invocation of EEXTEND adds to the cryptographic log information about which region is being
measured and the measurement of the section.
Entries in the cryptographic log define the measurement of the enclave and are critical in gaining assurance that
the enclave was correctly constructed by the untrusted system software.
39.1.3
EINIT Interaction
Once system software has completed the process of adding and measuring pages, the enclave needs to be initialized by the EINIT leaf function. After an enclave is initialized, EADD and EEXTEND are disabled for that enclave (An
attempt to execute EADD/EEXTEND to enclave after enclave initialization will result in a fault). The initialization
process finalizes the cryptographic log and establishes the enclave identity and sealing identity used by
EGETKEY and EREPORT.
A cryptographic hash of the log is stored as the enclave identity. Correct construction of the enclave results in the
cryptographic hash matching the one built by the enclave owner and included as the ENCLAVEHASH field of
SIGSTRUCT. The enclave identity provided by the EREPORT leaf function can be verified by a remote party.
39-2 Vol. 3D
ENCLAVE OPERATION
The EINIT leaf function checks the EINIT token to validate that the enclave has been enabled on this platform. If
the enclave is not correctly constructed, or the EINIT token is not valid for the platform, or SIGSTRUCT isn't properly signed, then EINIT will fail. See the EINIT leaf function for details on the error reporting.
The enclave identity is a cryptographic hash that reflects the enclave attributes and MISCSELECT value, content
of the enclave, the order in which it was built, the addresses it occupies in memory, the security attributes, and
access right permissions of each page. The enclave identity is established by the EINIT leaf function.
The sealing identity is managed by a sealing authority represented by the hash of the public key used to sign the
SIGSTRUCT structure processed by EINIT. The sealing authority assigns a product ID (ISVPRODID) and security
version number (ISVSVN) to a particular enclave identity.
EINIT establishes the sealing identity using the following steps:
1. Verifies that SIGSTRUCT is properly signed using the public key enclosed in the SIGSTRUCT.
2. Checks that the measurement of the enclave matches the measurement of the enclave specified in SIGSTRUCT.
3. Checks that the enclave’s attributes and MISCSELECT values are compatible with those specified in SIGSTRUCT.
4. Finalizes the measurement of the enclave and records the sealing identity (the sealing authority, product id
and security version number) and enclave identity in the SECS.
5. Sets the ATTRIBUTES.INIT bit for the enclave.
39.1.4
Intel® SGX Launch Control Configuration
Intel® SGX Launch Control is a set of controls that govern the creation of enclaves. Before the EINIT leaf function
will successfully initialize an enclave, a designated Launch Enclave must create an EINITTOKEN for that enclave.
Launch Enclaves have SECS.ATTRIBUTES.EINITTOKENKEY = 1, granting them access to the EINITTOKENKEY from
the EGETKEY leaf function. EINITTOKENKEY must be used by the Launch Enclave when computing EINITTOKEN.MAC, the Message Authentication Code of the EINITTOKEN.
The hash of the public key used to sign the SIGSTRUCT of the Launch Enclave must equal the value in the
IA32_SGXLEPUBKEYHASH MSRs. Only Launch Enclaves are allowed to launch without a valid token.
The IA32_SGXLEPUBKEYHASH MSRs are provided to designate the platform’s Launch Enclave.
IA32_SGXLEPUBKEYHASH defaults to digest of Intel’s launch enclave signing key after reset.
IA32_FEATURE_CONTROL bit 17 controls the permissions on the IA32_SGXLEPUBKEYHASH MSRs when
CPUID.(EAX=12H, ECX=00H):EAX[0] = 1. If IA32_FEATURE_CONTROL is locked with bit 17 set,
IA32_SGXLEPUBKEYHASH MSRs are reconfigurable (writeable). If either IA32_FEATURE_CONTROL is not locked or
bit 17 is clear, the MSRs are read only. By leaving these MSRs writable, system SW or a VMM can support a plurality
of Launch Enclaves for hosting multiple execution environments. See Section 42.3.2 for more details.
39.2
ENCLAVE ENTRY AND EXITING
39.2.1
Controlled Entry and Exit
The EENTER leaf function is the method to enter the enclave under program control. To execute EENTER, software
must supply an address of a TCS that is part of the enclave to be entered. The TCS holds the location inside the
enclave to transfer control to and a pointer to the SSA frame inside the enclave that an AEX should store the
register state to.
When a logical processor enters an enclave, the TCS is considered busy until the logical processors exits the
enclave. An attempt to enter an enclave through a busy TCS results in a fault. Intel® SGX allows an enclave builder
to define multiple TCSs, thereby providing support for multithreaded enclaves.
Software must also supply to EENTER the Asynchronous Exit Pointer (AEP) parameter. AEP is an address external
to the enclave which an exception handler will return to using IRET. Typically the location would contain the
ERESUME instruction. ERESUME transfers control back to the enclave, to the address retrieved from the enclave
thread’s saved state.
EENTER performs the following operations:
Vol. 3D 39-3
ENCLAVE OPERATION
1. Check that TCS is not busy and flush all cached linear-to-physical mappings.
2. Change the mode of operation to be in enclave mode.
3. Save the old RSP, RBP for later restore on AEX (Software is responsible for setting up the new RSP, RBP to be
used inside enclave).
4. Save XCR0 and replace it with the XFRM value for the enclave.
5. Check if software wishes to debug (applicable to a debuggable enclave):
— If not debugging, then configure hardware so the enclave appears as a single instruction.
— If debugging, then configure hardware to allow traps, breakpoints, and single steps inside the enclave.
6. Set the TCS as busy.
7. Transfer control from outside enclave to predetermined location inside the enclave specified by the TCS.
The EEXIT leaf function is the method of leaving the enclave under program control. EEXIT receives the target
address outside of the enclave that the enclave wishes to transfer control to. It is the responsibility of enclave software to erase any secret from the registers prior to invoking EEXIT. To allow enclave software to easily perform an
external function call and re-enter the enclave (using EEXIT and EENTER leaf functions), EEXIT returns the value of
the AEP that was used when the enclave was entered.
EEXIT performs the following operations:
1. Clear enclave mode and flush all cached linear-to-physical mappings.
2. Mark TCS as not busy.
3. Transfer control from inside the enclave to a location on the outside specified as parameter to the EEXIT leaf
function.
39.2.2
Asynchronous Enclave Exit (AEX)
Asynchronous and synchronous events, such as exceptions, interrupts, traps, SMIs, and VM exits may occur while
executing inside an enclave. These events are referred to as Enclave Exiting Events (EEE). Upon an EEE, the
processor state is securely saved inside the enclave (in the thread’s current SSA frame) and then replaced by a
synthetic state to prevent leakage of secrets. The process of securely saving state and establishing the synthetic
state is called an Asynchronous Enclave Exit (AEX). Details of AEX is described in Chapter 40, “Enclave Exiting
Events”.
As part of most EEEs, the AEP is pushed onto the stack as the location of the eventing address. This is the location
where control will return to after executing the IRET. The ERESUME leaf function can be executed from that point
to reenter the enclave and resume execution from the interrupted point.
After AEX has completed, the logical processor is no longer in enclave mode and the exiting event is processed
normally. Any new events that occur after the AEX has completed are treated as having occurred outside the
enclave (e.g. a #PF in dispatching to an interrupt handler).
39.2.3
Resuming Execution after AEX
After system software has serviced the event that caused the logical processor to exit an enclave, the logical
processor can continue enclave execution using ERESUME. ERESUME restores processor state and returns control
to where execution was interrupted.
If the cause of the exit was an exception or a fault and was not resolved, the event will be triggered again if the
enclave is re-entered using ERESUME. For example, if an enclave performs a divide by 0 operation, executing
ERESUME will cause the enclave to attempt to re-execute the faulting instruction and result in another divide by 0
exception. Intel® SGX provides the means for an enclave developer to handle enclave exceptions from within the
enclave. Software can enter the enclave at a different location and invoke the exception handler within the enclave
by executing the EENTER leaf function. The exception handler within the enclave can read the fault information
from the SSA frame and attempt to resolve the faulting condition or simply return and indicate to software that the
enclave should be terminated (e.g. using EEXIT).
39-4 Vol. 3D
ENCLAVE OPERATION
39.2.3.1
ERESUME Interaction
ERESUME restores registers depending on the mode of the enclave (32 or 64 bit).
•
In 32-bit mode (IA32_EFER.LMA = 0 || CS.L = 0), the low 32-bits of the legacy registers (EAX, EBX, ECX, EDX,
ESP, EBP, ESI, EDI, EIP and EFLAGS) are restored from the thread’s GPR area of the current SSA frame. Neither
the upper 32 bits of the legacy registers nor the 64-bit registers (R8 … R15) are loaded.
•
In 64-bit mode (IA32_EFER.LMA = 1 && CS.L = 1), all 64 bits of the general processor registers (RAX, RBX,
RCX, RDX, RSP, RBP, RSI, RDI, R8 … R15, RIP and RFLAGS) are loaded.
Extended features specified by SECS.ATTRIBUTES.XFRM are restored from the XSAVE area of the current SSA
frame. The layout of the x87 area depends on the current values of IA32_EFER.LMA and CS.L:
•
IA32_EFER.LMA = 0 || CS.L = 0
— 32-bit load in the same format that XSAVE/FXSAVE uses with these values.
•
IA32_EFER.LMA = 1 && CS.L = 1
— 64-bit load in the same format that XSAVE/FXSAVE uses with these values as if REX.W = 1.
39.3
CALLING ENCLAVE PROCEDURES
39.3.1
Calling Convention
In standard call conventions subroutine parameters are generally pushed onto the stack. The called routine, being
aware of its own stack layout, knows how to find parameters based on compile-time-computable offsets from the
SP or BP register (depending on runtime conventions used by the compiler).
Because of the stack switch when calling an enclave, stack-located parameters cannot be found in this manner.
Entering the enclave requires a modified parameter passing convention.
For example, the caller might push parameters onto the untrusted stack and then pass a pointer to those parameters in RAX to the enclave software. The exact choice of calling conventions is up to the writer of the edge routines;
be those routines hand-coded or compiler generated.
39.3.2
Register Preservation
As with most systems, it is the responsibility of the callee to preserve all registers except that used for returning a
value. This is consistent with conventional usage and tends to optimize the number of register save/restore operations that need be performed. It has the additional security result that it ensures that data is scrubbed from any
registers that were used by enclave to temporarily contain secrets.
39.3.3
Returning to Caller
No registers are modified during EEXIT. It is the responsibility of software to remove secrets in registers before
executing EEXIT.
39.4
INTEL® SGX KEY AND ATTESTATION
39.4.1
Enclave Measurement
During the enclave build process, two “measurements” are taken of each enclave and are stored in two 256-bit
Measurement Registers (MR): MRENCLAVE and MRSIGNER. MRENCLAVE represents the enclave's contents and
build process. MRSIGNER represents the entity that signed the enclave's SIGSTRUCT.
Vol. 3D 39-5
ENCLAVE OPERATION
The values of the Measurement Registers are included in attestations to identify the enclave to remote parties. The
MRs are also included in most keys, binding keys to enclaves with specific MRs.
39.4.1.1
MRENCLAVE
MRENCLAVE is a unique 256 bit value that identifies the code and data that was loaded into the enclave during the
initial launch. It is computed as a SHA256 hash that is initialized by the ECREATE leaf function. EADD and EEXTEND
leaf functions record information about each page and the content of those pages. The EINIT leaf function finalizes
the hash, which is stored in SECS.MRENCLAVE. Any tampering with the build process, contents of a page, page
permissions, etc will result in a different MRENCLAVE value.
Figure 39-2 illustrates a simplified flow of changes to the MRENCLAVE register when building an enclave:
•
•
•
•
Enclave creation with ECREATE.
Copying a non-enclave source page into the EPC of an un-initialized enclave with EADD.
Updating twice of the MRENCLAVE after modifying the enclave’s page content, i.e. EEXTEND twice.
Finalizing the enclave build with EINIT.
Details on specific values inserted in the hash are available in the individual instruction definitions.
Page
Metadata
Data
Chunk 1
Chunk 1
Metadata
Data
Chunk 2
Chunk 2
Metadata
SHA_INIT
SHA_UPDATE
SHA_UPDATE
SHA_UPDATE
SHA_FINAL
MRENCLAVE
MRENCLAVE
MRENCLAVE
MRENCLAVE
MRENCLAVE
ECREATE
EADD
EEXTEND
EEXTEND
EINIT
Figure 39-2. Measurement Flow of Enclave Build Process
39.4.1.2
MRSIGNER
Each enclave is signed using a 3072 bit RSA key. The signature is stored in the SIGSTRUCT. In the SIGSTRUCT, the
enclave's signer also assigns a product ID (ISVPRODID) and a security version (ISVSVN) to the enclave.
MRSIGNER is the SHA-256 hash of the signer's public key.
In attestation, MRSIGNER can be used to allow software to approve of an enclave based on the author rather than
maintaining a list of MRENCLAVEs. It is used in key derivation to allow software to create a lineage of an application. By signing multiple enclaves with the same key, the enclaves will share the same keys and data. Combined
with security version numbering, the author can release multiple versions of an application which can access keys
for previous versions, but not future versions of that application.
39-6 Vol. 3D
ENCLAVE OPERATION
39.4.2
Security Version Numbers (SVN)
Intel® SGX supports a versioning system that allows the signer to identify different versions of the same software
released by an author. The security version is independent of the functional version an author uses and is intended
to specify security equivalence. Multiple releases with functional enhancements may all share the same SVN if they
all have the same security properties or posture. Each enclave has an SVN and the underlying hardware has an
SVN.
The SVNs are attested to in EREPORT and are included in the derivation of most keys, thus providing separation
between data for older/newer versions.
39.4.2.1
Enclave Security Version
In the SIGSTRUCT, the MRSIGNER is associated with a 16-bit Product ID (ISVPRODID) and a 16 bit integer SVN
(ISVSVN). Together they define a specific group of versions of a specific product. Most keys, including the Seal Key,
can be bound to this pair.
To support upgrading from one release to another, EGETKEY will return keys corresponding to any value less than
or equal to the software's ISVSVN.
39.4.2.2
Hardware Security Version
CPUSVN is a 128 bit value that reflects the microcode update version and authenticated code modules supported
by the processor. Unlike ISVSVN, CPUSVN is not an integer and cannot be compared mathematically. Not all values
are valid CPUSVNs.
Software must ensure that the CPUSVN provided to EGETKEY is valid. EREPORT will return the CPUSVN of the
current environment. Software can execute EREPORT with TARGETINFO set to zeros to retrieve a CPUSVN from
REPORTDATA. Software can access keys for a CPUSVN recorded previously, provided that each of the elements
reflected in CPUSVN are the same or have been upgraded.
39.4.3
Keys
Intel® SGX provides software with access to keys unique to each processor and rooted in HW keys inserted into
the processor during manufacturing.
Each enclave requests keys using the EGETKEY leaf function. The key is based on enclave parameters such as
measurement, the enclave signing key, security attributes of the enclave, and the Hardware Security version of the
processor itself. A full list of parameter options is specified in the KEYREQUEST structure, see details in Section
38.17.
By deriving keys using enclave properties, SGX guarantees that if two enclaves call EGETKEY, they will receive a
unique key only accessible by the respective enclave. It also guarantees that the enclave will receive the same key
on every future execution of EGETKEY. Some parameters are optional or configurable by software. For example, a
Seal key can be based on the signer of the enclave, resulting in a key available to multiple enclaves signed by the
same party.
The EGETKEY leaf function provides several key types. Each key is specific to the processor, CPUSVN, and the
enclave that executed EGETKEY. The EGETKEY instruction definition details how each of these keys is derived, see
Table 41-56. Additionally,
•
SEAL Key: The Seal key is a general purpose key for the enclave to use to protect secrets. Typical uses of the
Seal key are encrypting and calculating MAC of secrets on disk. There are 2 types of Seal Key described in
Section 39.4.3.1.
•
REPORT Key: This key is used to compute the MAC on the REPORT structure. The EREPORT leaf function is used
to compute this MAC, and destination enclave uses the Report key to verify the MAC. The software usage flow
is detailed in Section 39.4.3.2.
•
EINITOKENKEY: This key is used by Launch Enclaves to compute the MAC on EINITTOKENs. These tokens are
then verified in the EINIT leaf function. The key is only available to enclaves with ATTRIBUTE.EINITTOKENKEY set
to 1.
Vol. 3D 39-7
ENCLAVE OPERATION
•
PROVISIONING Key and PROVISIONING SEAL Key: These keys are used by attestation key provisioning
software to prove to remote parties that the processor is genuine and identify the currently executing TCB.
These keys are only available to enclaves with ATTRIBUTE.PROVISIONKEY set to 1.
39.4.3.1
Sealing Enclave Data
Enclaves can protect persistent data using Seal keys to provide encryption and/or integrity protection. EGETKEY
provides two types of Seal keys specified in KEYREQUEST.KEYPOLICY field: MRENCLAVE-based key and
MRSIGNER-based key.
The MRENCLAVE-based keys are available only to enclave instances sharing the same MRENCLAVE. If a new
version of the enclave is released, the Seal keys will be different. Retrieving previous data requires additional software support.
The MRSIGNER-based keys are bound to the 3 tuple (MRSIGNER, ISVPRODID, ISVSVN). These keys are available
to any enclave with the same MRSIGNER and ISVPRODID and an ISVSVN equal to or greater than the key in questions. This is valuable for allowing new versions of the same software to retrieve keys created before an upgrade.
39.4.3.2
Using REPORTs for Local Attestation
SGX provides a means for enclaves to securely identify one another, this is referred to as “Local Attestation”. SGX
provides a hardware assertion, REPORT that contains calling enclaves Attributes, Measurements and User supplied
data (described in detail in Section 38.15). Figure 39-3 shows the basic flow of information.
1. The source enclave determines the identity of the target enclave to populate TARGETINFO.
2. The source enclave calls EREPORT instruction to generate a REPORT structure. The EREPORT instruction
conducts the following:
— Populates the REPORT with identify information about the calling enclave.
— Derives the Report Key that is returned when the target enclave executes the EGETKEY. TARGETINFO
provides information about the target.
— Computes a MAC over the REPORT using derived target enclave Report Key.
3. Non-enclave software copies the REPORT from source to destination.
4. The target enclave executes the EGETKEY instruction to request its REPORT key, which is the same key used by
EREPORT at the source.
5. The target enclave verifies the MAC and can then inspect the REPORT to identify the source.
Source Enclave
TARGETINFO
Destination Enclave
EREPORT
(Symmetric Key)
REPORT
Legend:
Hardware
EGETKEY
REPORT KEY
Verify REPORT
(Symmetric Key)
Software
Figure 39-3. SGX Local Attestation
39-8 Vol. 3D
ENCLAVE OPERATION
39.5
EPC AND MANAGEMENT OF EPC PAGES
EPC layout is implementation specific, and is enumerated through CPUID (see Table 37-6 for EPC layout). EPC is
typically configured by BIOS at system boot time.
The exact amount, size, and layout of EPC are model-specific, and depend on BIOS settings.
39.5.1
EPC Implementation
EPC must be properly protected against attacks. One example of EPC implementation could use a Memory Encryption Engine (MEE). An MEE provides a cost-effective mechanism of creating cryptographically protected volatile
storage using platform DRAM. These units provide integrity, replay, and confidentiality protection. Details are
implementation specific.
39.5.2
OS Management of EPC Pages
The EPC is a finite resource. SGX1 (i.e. CPUID.(EAX=12H, ECX=0):EAX.SGX1 = 1 but CPUID.(EAX=12H,
ECX=0):EAX.SGX2 = 0) provides the EPC manager with leaf functions to manage this resource and properly swap
pages out of and into the EPC. For that, the EPC manager would need to keep track of all EPC entries, type and
state, context affiliation, and SECS affiliation.
Enclave pages that are candidates for eviction should be moved to BLOCKED state using EBLOCK instruction that
ensures no new cached virtual to physical address mappings can be created by attempts to reference a BLOCKED
page.
Before evicting blocked pages, EPC manager should execute ETRACK leaf function on that enclave and ensure that
there are no stale cached virtual to physical address mappings for the blocked pages remain on any thread on the
platform.
After removing all stale translations from blocked pages, system software should use the EWB leaf function for
securely evicting pages out of the EPC. EWB encrypts a page in the EPC, writes it to unprotected memory, and
invalidates the copy in EPC. In addition, EWB also creates a cryptographic MAC (PCMD.MAC) of the page and stores
it in unprotected memory. A page can be reloaded back to the processor only if the data and MAC match. To ensure
that the only latest version of the evicted page can be loaded back, the version of the evicted page is stored
securely in a Version Array (VA) in EPC.
SGX1 includes two instructions for reloading pages that have been evicted by system software: ELDU and ELDB.
The difference between the two instructions is the value of the paging state at the end of the instruction. ELDU
results in a page being reloaded and set to an UNBLOCKED state, while ELDB results in a page loaded to a
BLOCKED state.
ELDB is intended for use by a Virtual Machine Monitor (VMM). When a VMM reloads an evicted page, it needs to
restore it to the correct state of the page (BLOCKED vs. UNBLOCKED) as it existed at the time the page was
evicted. Based on the state of the page at eviction, the VMM chooses either ELDB or ELDU.
39.5.2.1
Enhancement to Managing EPC Pages
On processors supporting SGX2 (i.e. CPUID.(EAX=12H, ECX=0):EAX.SGX2 = 1), the EPC manager can manage
EPC resources (while enclave is running) with more flexibility provided by the SGX2 leaf functions. The additional
flexibility is described in Section 39.5.7 through Section 39.5.11.
39.5.3
Eviction of Enclave Pages
Intel SGX paging is optimized to allow the Operating System (OS) to evict multiple pages out of the EPC under a
single synchronization.
The suggested flow for evicting a list of pages from the EPC is:
1. For each page to be evicted from the EPC:
a. Select an empty slot in a Version Array (VA) page.
Vol. 3D 39-9
ENCLAVE OPERATION
•
If no empty VA page slots exist, create a new VA page using the EPA leaf function.
b. Remove linear-address to physical-address mapping from the enclave contexts’s mapping tables (page
table and EPT tables).
c.
Execute the EBLOCK leaf function for the target page. This sets the target page state to BLOCKED. At this
point no new mappings of the page will be created. So any access which does not have the mapping cached
in the TLB will generate a #PF.
2. For each enclave containing pages selected in step 1:
— Execute an ETRACK leaf function pointing to that enclave’s SECS. This initiates the tracking process that
ensures that all caching of linear-address to physical-address translations for the blocked pages is cleared.
3. For all logical processors executing in processes (OS) or guests (VMM) that contain the enclaves selected in
step 1:
— Issue an IPI (inter-processor interrupt) to those threads. This causes those logical processors to asynchronously exit any enclaves they might be in, and as a result flush cached linear-address to physical-address
translations that might hold stale translations to blocked pages. There is no need for additional measures
such as performing a “TLB shootdown”.
4. After enclaves exit, allow logical processors can resume normal operation, including enclave re-entry as the
tracking logic keeps track of the activity.
5. For each page to be evicted:
— Evict the page using the EWB leaf function with parameters include the effective-address pointer to the EPC
page, the VA slot, a 4K byte buffer to hold the encrypted page contents, and a 128 byte buffer to hold page
metadata. The last three elements are tied together cryptographically and must be used to later reload the
page.
At this point, system software has the only copy of each page data encrypted with its page metadata in main
memory.
39.5.4
Loading an Enclave Page
To reload a previously evicted page, system software needs four elements: the VA slot used when the page was
evicted, a buffer containing the encrypted page contents, a buffer containing the page metadata, and the parent
SECS to associate this page with. If the VA page or the parent SECS are not already in the EPC, they must be
reloaded first.
1. Execute ELDB/ELDU (depending on the desired BLOCKED state for the page), passing as parameters: the EPC
page linear address, the VA slot, the encrypted page, and the page metadata.
2. Create a mapping in the enclave context’s mapping tables (page tables and EPT tables) to allow the application
to access that page (OS: system page table; VMM: EPT).
The ELDB/ELDU instruction marks the VA slot empty so that the page cannot be replayed at a later date.
39.5.5
Eviction of an SECS Page
The eviction of an SECS page is similar to the eviction of an enclave page. The only difference is that an SECS page
cannot be evicted until all other pages belonging to the enclave have been evicted. Since all other pages have been
evicted, there will be no threads executing inside the enclave and tracking with ETRACK isn’t necessary. When
reloading an enclave, the SECS page must be reloaded before all other constituent pages.
1. Ensure all pages are evicted from enclave.
2. Select an empty slot in a Version Array page.
— If no VA page exists with an empty slot, create a new one using the EPA function leaf.
3. Evict the page using the EWB leaf function with parameters include the effective-address pointer to the EPC
page, the VA slot, a 4K byte buffer to hold the encrypted page contents and a 128 byte buffer to hold page
metadata. The last three elements are tied together cryptographically and must be used to later reload the
page.
39-10 Vol. 3D
ENCLAVE OPERATION
39.5.6
Eviction of a Version Array Page
VA pages do not belong to any enclave and tracking with ETRACK isn’t necessary. When evicting the VA page, a slot
in a different VA page must be specified in order to provide versioning of the evicted VA page.
1. Select a slot in a Version Array page other than the page being evicted.
— If no VA page exists with an empty slot, create a new one using the EPA leaf function.
2. Evict the page using the EWB leaf function with parameters include the effective-address pointer to the EPC
page, the VA slot, a 4K byte buffer to hold the encrypted page contents, and a 128 byte buffer to hold page
metadata. The last three elements are tied together cryptographically and must be used to later reload the
page.
39.5.7
Allocating a Regular Page
On processors that support SGX2, allocating a new page to an already initialized enclave is accomplished by
invoking the EAUG leaf function. Typically, the enclave requests that the OS allocate a new page at a particular
location within the enclave’s address space. Once allocated, the page remains in a pending state until the enclave
executes the corresponding EACCEPT leaf function to accept the new page into the enclave. Page allocation operations may be batched to improve efficiency.
The typical process for allocating a regular page is as follows:
1. Enclave requests additional memory from OS when the current allocation becomes insufficient.
2. The OS invokes the EAUG leaf function to add a new memory page to the enclave.
a. EAUG may only be called on a free EPC page.
b. Successful completion of the EAUG instruction places the target page in the VALID and PENDING state.
c.
All dynamically created pages have the type PT_REG and content of all zeros.
3. The OS maps the page in the enclave context's mapping tables.
4. The enclave issues an EACCEPT instruction, which verifies the page’s attributes and clears the PENDING state.
At that point the page becomes accessible for normal enclave use.
39.5.8
Allocating a TCS Page
On processors that support SGX2, allocating a new TCS page to an already initialized enclave is a two-step process.
First the OS allocates a regular page with a call to EAUG. This page must then be accepted and initialized by the
enclave to which it belongs. Once the page has been initialized with appropriate values for a TCS page, the enclave
requests the OS to change the page’s type to PT_TCS. This change must also be accepted. As with allocating a
regular page, TCS allocation operations may be batched.
A typical process for allocating a TCS page is as follows:
1. Enclave requests an additional page from the OS.
2. The OS invokes EAUG to add a new regular memory page to the enclave.
a. EAUG may only be called on a free EPC page.
b. Successful completion of the EAUG instruction places the target page in the VALID and PENDING state.
3. The OS maps the page in the enclave context's mapping tables.
4. The enclave issues an EACCEPT instruction, at which point the page becomes accessible for normal enclave
use.
5. The enclave initializes the contents of the new page.
6. The enclave requests that the OS convert the page from type PT_REG to PT_TCS.
7. OS issues an EMODT instruction on the page.
a. The parameters to EMODT indicate that the regular page should be converted into a TCS.
Vol. 3D 39-11
ENCLAVE OPERATION
b. EMODT forces all access rights to a page to be removed because TCS pages may not be accessed by enclave
code.
8. The enclave issues an EACCEPT instruction to confirm the requested modification.
39.5.9
Trimming a Page
On processors that support SGX2, Intel SGX supports the trimming of an enclave page as a special case of EMODT.
Trimming allows an enclave to actively participate in the process of removing a page from the enclave (deallocation) by splitting the process into first removing it from the enclave's access and then removing it from the EPC
using the EREMOVE leaf function. The page type PT_TRIM indicates that a page has been trimmed from the
enclave’s address space and that the page is no longer accessible to enclave software. Modifications to a page in
the PT_TRIM state are not permitted; the page must be removed and then reallocated by the OS before the enclave
may use the page again. Page deallocation operations may be batched to improve efficiency.
The typical process for trimming a page from an enclave is as follows:
1. Enclave signals OS that a particular page is no longer in use.
2. OS invokes the EMODT leaf function on the page, requesting that the page’s type be changed to PT_TRIM.
a. SECS and VA pages cannot be trimmed in this way, so the initial type of the page must be PT_REG or
PT_TCS.
b. EMODT may only be called on valid enclave pages.
3. OS invokes the ETRACK leaf function on the enclave containing the page to track removal the TLB addresses
from all the processors.
4. Issue an IPI (inter-processor interrupt) to flush the stale linear-address to physical-address translations for all
logical processors executing in processes that contain the enclave.
5. Enclave issues an EACCEPT leaf function.
6. The OS may now permanently remove the page from the EPC (by issuing EREMOVE).
39.5.10 Restricting the EPCM Permissions of a Page
On processors that support SGX2, restricting the EPCM permissions associated with an enclave page is accomplished using the EMODPR leaf function. This operation requires the cooperation of the OS to flush stale entries to
the page and to update the page-table permissions of the page to match. Permissions restriction operations may
be batched.
The typical process for restricting the permissions of an enclave page is as follows:
1. Enclave requests that the OS to restrict the permissions of an EPC page.
2. OS performs permission restriction, flushing cached linear-address to physical-address translations, and pagetable modifications.
a. Invokes the EMODPR leaf function to restrict permissions (EMODPR may only be called on VALID pages).
b. Invokes the ETRACK leaf function on the enclave containing the page to track removal of the TLB addresses
from all the processor.
c.
Issue an IPI (inter-processor interrupt) to flush the stale linear-address to physical-address translations for
all logical processors executing in processes that contain the enclave.
d. Sends IPIs to trigger enclave thread exit and TLB shootdown.
e. OS informs the Enclave that all logical processors should now see the new restricted permissions.
3. Enclave invokes the EACCEPT leaf function.
a. Enclave may access the page throughout the entire process.
b. Successful call to EACCEPT guarantees that no stale cached linear-address to physical-address translations
are present.
39-12 Vol. 3D
ENCLAVE OPERATION
39.5.11 Extending the EPCM Permissions of a Page
On processors that support SGX2, extending the EPCM permissions associated with an enclave page is accomplished directly be the enclave using the EMODPE leaf function. After performing the EPCM permission extension,
the enclave requests the OS to update the page table permissions to match the extended permission. Security
wise, permission extension does not require enclave threads to leave the enclave as TLBs with stale references to
the more restrictive permissions will be flushed on demand, but to allow forward progress, an OS needs to be
aware that an application might signal a page fault.
The typical process for extending the permissions of an enclave page is as follows:
1. Enclave invokes EMODPE to extend the EPCM permissions associated with an EPC page (EMODPE may only be
called on VALID pages).
2. Enclave requests that OS update the page tables to match the new EPCM permissions.
3. Enclave code resumes.
a. If cached linear-address to physical-address translations are present to the more restrictive permissions,
the enclave thread will page fault. The SGX2-aware OS will see that the page tables permit the access and
resume the thread, which can now successfully access the page because exiting cleared the TLB.
b. If cached linear-address to physical-address translations are not present, access to the page with the new
permissions will succeed without an enclave exit.
39.6
CHANGES TO INSTRUCTION BEHAVIOR INSIDE AN ENCLAVE
This section covers instructions whose behavior changes when executed in enclave mode.
39.6.1
Illegal Instructions
The instructions listed in Table 39-1 are ring 3 instructions which become illegal when executed inside an enclave.
Executing these instructions inside an enclave will generate an exception.
The first row of Table 39-1 enumerates instructions that may cause a VM exit for VMM emulation. Since a VMM
cannot emulate enclave execution, execution of any these instructions inside an enclave results in an invalidopcode exception (#UD) and no VM exit.
The second row of Table 39-1 enumerates I/O instructions that may cause a fault or a VM exit for emulation. Again,
enclave execution cannot be emulated, so execution of any these instructions inside an enclave results in #UD.
The third row of Table 39-1 enumerates instructions that load descriptors from the GDT or the LDT or that change
privilege level. The former class is disallowed because enclave software should not depend on the contents of the
descriptor tables and the latter because enclave execution must be entirely with CPL = 3. Again, execution of any
these instructions inside an enclave results in #UD.
The fourth row of Table 39-1 enumerates instructions that provide access to kernel information from user mode
and can be used to aid kernel exploits from within enclave. Execution of any these instructions inside an enclave
results in #UD
Table 39-1. Illegal Instructions Inside an Enclave
Instructions
Result
CPUID, GETSEC, RDPMC, SGDT, SIDT, SLDT, STR, VMCALL, VMFUNC #UD
IN, INS/INSB/INSW/INSD, OUT, OUTS/OUTSB/OUTSW/OUTSD
#UD
Comment
Might cause VM exit.
I/O fault may not safely recover. May require emulation.
Far call, Far jump, Far Ret, INT n/INTO, IRET, LDS/LES/LFS/LGS/LSS, #UD
MOV to DS/ES/SS/FS/GS, POP DS/ES/SS/FS/GS, SYSCALL,
SYSENTER
Access segment register could change privilege level.
SMSW
#UD
Might provide access to kernel information.
ENCLU[EENTER], ENCLU[ERESUME]
#GP
Cannot enter an enclave from within an enclave.
Vol. 3D 39-13
ENCLAVE OPERATION
RDTSC and RDTSCP are legal inside an enclave for processors that support SGX2 (subject to the value of CR4.TSD).
For processors which support SGX1 but not SGX2, RDTSC and RDTSCP will cause #UD.
RDTSC and RDTSCP instructions may cause a VM exit when inside an enclave.
Software developers must take into account that the RDTSC/RDTSCP results are not immune to influences by other
software, e.g. the TSC can be manipulated by software outside the enclave.
39.6.2
RDRAND and RDSEED Instructions
These instructions may cause a VM exit if the “RDRAND exiting” VM-execution control is 1. Unlike other instructions
that can cause VM exits, these instructions are legal inside an enclave. As noted in Section 6.5.5, any VM exit originating on an instruction boundary inside an enclave sets bit 27 of the exit-reason field of the VMCS. If a VMM
receives a VM exit due to an attempt to execute either of these instructions determines (by that bit) that the execution was inside an enclave, it can do either of two things. It can clear the “RDRAND exiting” VM-execution control
and execute VMRESUME; this will result in the enclave executing RDRAND or RDSEED again, and this time a VM
exit will not occur. Alternatively, the VMM might choose to discontinue execution of this virtual machine.
NOTE
It is expected that VMMs that virtualize Intel SGX will not set “RDRAND exiting” to 1.
39.6.3
PAUSE Instruction
The PAUSE instruction may cause a VM exit if either of the “PAUSE exiting” and “PAUSE-loop exiting” VM-execution
controls is 1. Unlike other instructions that can cause VM exits, the PAUSE instruction is legal inside an enclave.
If a VMM receives a VM exit due to the 1-setting of “PAUSE-loop exiting”, it may take action to prevent recurrence
of the PAUSE loop (e.g., by scheduling another virtual CPU of this virtual machine) and then execute VMRESUME;
this will result in the enclave executing PAUSE again, but this time the PAUSE loop (and resulting VM exit) will not
occur.
If a VMM receives a VM exit due to the 1-setting of “PAUSE exiting”, it can do either of two things. It can clear the
“PAUSE exiting” VM-execution control and execute VMRESUME; this will result in the enclave executing PAUSE
again, but this time a VM exit will not occur. Alternatively, the VMM might choose to discontinue execution of this
virtual machine.
NOTE
It is expected that VMMs that virtualize Intel SGX will not set “PAUSE exiting” to 1.
39.6.4
INT 3 Behavior Inside an Enclave
INT3 is legal inside an enclave, however, the behavior inside an enclave is different from its behavior outside an
enclave. See Section 43.4.1 for details.
39.6.5
INVD Handling when Enclaves Are Enabled
Once processor reserved memory protections are activated (see Section 39.5), any execution of INVD will result in
a #GP(0).
39-14 Vol. 3D
ENCLAVE EXITING EVENTS
CHAPTER 40
ENCLAVE EXITING EVENTS
Certain events, such as exceptions and interrupts, incident to (but asynchronous with) enclave execution may
cause control to transition outside of enclave mode. (Most of these also cause a change of privilege level.) To
protect the integrity and security of the enclave, the processor will exit the enclave (and enclave mode) before
invoking the handler for such an event. For that reason, such events are called an enclave-exiting events (EEE);
EEEs include external interrupts, non-maskable interrupts, system-management interrupts, exceptions, and VM
exits.
The process of leaving an enclave in response to an EEE is called an asynchronous enclave exit (AEX). To protect
the secrecy of the enclave, an AEX saves the state of certain registers within enclave memory and then loads those
registers with fixed values called synthetic state.
40.1
COMPATIBLE SWITCH TO THE EXITING STACK OF AEX
AEXs load registers with a pre-determined synthetic state. These register may be later pushed onto the appropriate stack in a form as defined by the enclave-exiting event. To allow enclave execution to resume after the
invoking handler has process the enclave exiting event, the asynchronous enclave exit loads the address of trampoline code outside of the enclave into RIP. This trampoline code eventually returns to the enclave by means of an
ENCLU(ERESUME) leaf function. Prior to exiting the enclave the RSP and RBP registers are restored to their values
prior to enclave entry.
The stack to be used is chosen using the same rules as for non-SGX mode:
•
•
•
If there is a privilege level change, the stack will be the one associated with the new ring.
If there is no privilege level change, the current application stack is used.
If the IA-32e IST mechanism is used, the exit stack is chosen using that method.
TCS
Next SSA Frame
CSSA
Current SSA Frame
uRSP
AEP
Per-Thread
Trampoline in uRTS
Exit Stack
uRSP
ENCLU[ERESUME]
SS
RSP
TCS LA
RAX
RBX
RFLAGS
AEP
RCX
CS
ENCLU[ERESUME]
RIP
Error Code (optional)
RSP after pushes
RSP
Figure 40-1. Exit Stack Just After Interrupt with Stack Switch
Vol. 3D 40-1
ENCLAVE EXITING EVENTS
In all cases, the choice of exit stack and the information pushed onto it is consistent with non-SGX operation.
Figure 40-1 shows the Application and Exiting Stacks after an exit with a stack switch. An exit without a stack
switch uses the Application Stack. The ERESUME leaf index value is placed into RAX, the TCS pointer is placed in
RBX and the AEP (see below) is placed into RCX to facilitate resuming the enclave after the exit.
Upon an AEX, the AEP (Asynchronous Exit Pointer) is loaded into the RIP. The AEP points to a trampoline code
sequence which includes the ERESUME instruction that is later used to reenter the enclave.
The following bits of RFLAGS are cleared before RFLAGS is pushed onto the exit stack: CF, PF, AF, ZF, SF, OF, RF. The
remaining bits are left unchanged.
40.2
STATE SAVING BY AEX
The State Save Area holds the processor state at the time of an AEX. To allow handling events within the enclave
and re-entering it after an AEX, the SSA can be a stack of multiple SSA frames as illustrated in Figure 40-2.
SSA Stack
TCS
GRP_N-1
NSSA
MISC_N-1
CSSA
XSAVE_N-1
OSSA
GPR_1
MISC_1
XSAVE_1
SECS.SSAFRAMESIZE
(in pages)
Current
SSA Fram
GRP_0
MISC_0
XAVE_0
Figure 40-2. The SSA Stack
The location of the SSA frames to be used is controlled by the following variables in the TCS and the SECS:
•
Size of a frame in the State Save Area (SECS.SSAFRAMESIZE): This defines the number of 4K Byte pages in a
single frame in the State Save Area. The SSA frame size must be large enough to hold the GPR state, the XSAVE
state, and the MISC state.
•
Base address of the enclave (SECS.BASEADDR): This defines the enclave's base linear address from which the
offset to the base of the SSA stack is calculated.
•
Number of State Save Area Slots (TCS.NSSA): This defines the total number of slots (frames) in the State Save
Area stack.
•
•
Current State Save Area Slot (TCS.CSSA): This defines the slot to use on the next exit.
State Save Area (TCS.OSSA): This defines the offset of the base address of a set of State Save Area slots from
the enclave’s base address.
When an AEX occurs, hardware selects the SSA frame to use by examining TCS.CSSA. Processor state is saved into
the SSA frame (see Section 40.4) and loaded with a synthetic state (as described in Section 40.3.1)to avoid leaking
secrets, RSP and RP are restored to their values prior to enclave entry, and TCS.CSSA is incremented. As will be
described later, if an exception takes the last slot, it will not be possible to reenter the enclave to handle the excep-
40-2 Vol. 3D
ENCLAVE EXITING EVENTS
tion from within the enclave. A subsequent ERESUME restores the processor state from the current SSA frame and
frees the SSA frame.
The format of the XSAVE section of SSA is identical to the format used by the XSAVE/XRSTOR instructions. On
EENTER, CSSA must be less than NSSA, ensuring that there is at least one State Save Area slot available for exits.
If there is no free SSA frame when executing EENTER, the entry will fail.
40.3
SYNTHETIC STATE ON ASYNCHRONOUS ENCLAVE EXIT
40.3.1
Processor Synthetic State on Asynchronous Enclave Exit
Table 40-1 shows the synthetic state loaded on AEX. The values shown are the lower 32 bits when the processor is
in 32 bit mode and 64 bits when the processor is in 64 bit mode.
Table 40-1. GPR, x87 Synthetic States on Asynchronous Enclave Exit
Register
Value
RAX
3 (ENCLU[3] is ERESUME).
RBX
Pointer to TCS of interrupted enclave thread.
RCX
AEP of interrupted enclave thread.
RDX, RSI, RDI
0.
RSP
Restored from SSA.uRSP.
RBP
Restored from SSA.uRBP.
R8-R15
0 in 64-bit mode; unchanged in 32-bit mode.
RIP
AEP of interrupted enclave thread.
RFLAGS
CF, PF, AF, ZF, SF, OF, RF bits are cleared. All other bits are left unchanged.
x87/SSE State
Unless otherwise listed here, all x87 and SSE state are set to the INIT state. The INIT state is the state
that would be loaded by the XRSTOR instruction with bits 1:0 both set in the requested feature bitmask
(RFBM), and both clear in XSTATE_BV the XSAVE header.
FCW
On #MF exception: set to 037EH. On all other exits: set to 037FH.
FSW
On #MF exception: set to 8081H. On all other exits: set to 0H.
MXCSR
On #XM exception: set to 1F01H. On all other exits: set to 1FB0H.
CR2
If the event that caused the AEX is a #PF, and the #PF does not directly cause a VM exit, then the low
12 bits are cleared.
If the #PF leads directly to a VM exit, CR2 is not updated (usual IA behavior).
Note: The low 12 bits are not cleared if a #PF is encountered during the delivery of the EEE that caused
the AEX. This is because the #PF was not the EEE.
FS, GS
Restored to values as of most recent EENTER/ERESUME.
40.3.2
Synthetic State for Extended Features
When CR4.OSXSAVE = 1, extended features (those controlled by XCR0[63:2]) are set to their respective INIT
states when this corresponding bit of SECS.XFRM is set. The INIT state is the state that would be loaded by the
XRSTOR instruction had the instruction mask and the XSTATE_BV field of the XSAVE header each contained the
value XFRM. (When the AEX occurs in 32-bit mode, those features that do not exist in 32-bit mode are unchanged.)
Vol. 3D 40-3
ENCLAVE EXITING EVENTS
40.3.3
Synthetic State for MISC Features
State represented by SECS.MISCSELECT might also be overridden by synthetic state after it has been saved into
the SSA. State represented by MISCSELECT[0] is not overridden but if the exiting event is a page fault then lower
12 bits of CR2 are cleared.
40.4
AEX FLOW
On Enclave Exiting Events (interrupts, exceptions, VM exits or SMIs), the processor state is securely saved inside
the enclave, a synthetic state is loaded and the enclave is exited. The EEE then proceeds in the usual exit-defined
fashion. The following sections describes the details of an AEX:
1. The exact processor state saved into the current SSA frame depends on whether the enclave is a 32-bit or a 64bit enclave. In 32-bit mode (IA32_EFER.LMA = 0 || CS.L = 0), the low 32 bits of the legacy registers (EAX, EBX,
ECX, EDX, ESP, EBP, ESI, EDI, EIP and EFLAGS) are stored. The upper 32 bits of the legacy registers and the
64-bit registers (R8 … R15) are not stored.
In 64-bit mode (IA32_EFER.LMA = 1 && CS.L = 1), all 64 bits of the general processor registers (RAX, RBX,
RCX, RDX, RSP, RBP, RSI, RDI, R8 … R15, RIP and RFLAGS) are stored.
The state of those extended features specified by SECS.ATTRIBUTES.XFRM are stored into the XSAVE area of
the current SSA frame. The layout of the x87 and XMM portions (the 1st 512 bytes) depends on the current
values of IA32_EFER.LMA and CS.L:
If IA32_EFER.LMA = 0 || CS.L = 0, the same format (32-bit) that XSAVE/FXSAVE uses with these values.
If IA32_EFER.LMA = 1 && CS.L = 1, the same format (64-bit) that XSAVE/FXSAVE uses with these values
when REX.W = 1.
The cause of the AEX is saved in the EXITINFO field. See Table 38-9 for details and values of the various
fields.
The state of those miscellaneous features (see Section 38.7.2) specified by SECS.MISCSELECT are stored into
the MISC area of the current SSA frame.
2. Synthetic state is created for a number of processor registers to present an opaque view of the enclave state.
Table 40-1 shows the values for GPRs, x87, SSE, FS, GS, Debug and performance monitoring on AEX. The
synthetic state for other extended features (those controlled by XCR0[62:2]) is set to their respective INIT
states when their corresponding bit of SECS.ATTRIBUTES.XFRM is set. The INIT state is that state as defined by
the behavior of the XRSTOR instruction when HEADER.XSTATE_BV[n] is 0. Synthetic state of those miscellaneous features specified by SECS.MISCSELECT depends on the miscellaneous feature. There is no synthetic
state required for the miscellaneous state controlled by SECS.MISCSELECT[0].
3. Any code and data breakpoints that were suppressed at the time of enclave entry are unsuppressed when
exiting the enclave.
4. RFLAGS.TF is set to the value that it had at the time of the most recent enclave entry (except for the situation
that the entry was opt-in for debug; see Section 43.2). In the SSA, RFLAGS.TF is set to 0.
5. RFLAGS.RF is set to 0 in the synthetic state. In the SSA, the value saved is the same as what would have been
saved on stack in the non-SGX case (architectural value of RF). Thus, AEXs due to interrupts, traps, and code
breakpoints save RF unmodified into SSA, while AEXs due to other faults save RF as 1 in the SSA.
If the event causing AEX happened on intermediate iteration of a REP-prefixed instruction, then RF=1 is
saved on SSA, irrespective of its priority.
6. Any performance monitoring activity (including PEBS) or profiling activity (LBR, Tracing using Intel PT) on the
exiting thread that was suppressed due to the enclave entry on that thread is unsuppressed. Any counting that
had been demoted from AnyThread counting to MyThread counting (on one logical processor) is promoted back
to AnyThread counting.
40-4 Vol. 3D
ENCLAVE EXITING EVENTS
40.4.1
AEX Operational Detail
Temp Variables in AEX Operational Flow
Name
Type
Size (bits)
Description
TMP_RIP
Effective Address
32/64
Address of instruction at which to resume execution on ERESUME.
TMP_MODE64
binary
1
((IA32_EFER.LMA = 1) && (CS.L = 1)).
TMP_BRANCH_RECORD
LBR Record
2x64
From/To address to be pushed onto LBR stack.
The pseudo code in this section describes the internal operations that are executed when an AEX occurs in enclave
mode. These operations occur just before the normal interrupt or exception processing occurs.
(* Save RIP for later use *)
TMP_RIP = Linear Address of Resume RIP
(* Is the processor in 64-bit mode? *)
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
(* Save all registers, When saving EFLAGS, the TF bit is set to 0 and
the RF bit is set to what would have been saved on stack in the non-SGX case *)
IF (TMP_MODE64 = 0)
THEN
Save EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI, EFLAGS, EIP into the current SSA frame using
CR_GPR_PA; (* see Table 41-4 for list of CREGs used to describe internal operation within Intel SGX *)
SSA.RFLAGS.TF 0;
ELSE (* TMP_MODE64 = 1 *)
Save RAX, RBX, RCX, RDX, RSP, RBP, RSI, RDI, R8-R15, RFLAGS, RIP into the current SSA frame using
CR_GPR_PA;
SSA.RFLAGS.TF 0;
FI;
Save FS and GS BASE into SSA using CR_GPR_PA;
(* store XSAVE state into the current SSA frame's XSAVE area using the physical addresses
that were determined and cached at enclave entry time with CR_XSAVE_PAGE_i. *)
For each XSAVE state i defined by (SECS.ATTRIBUTES.XFRM[i] = 1, destination address cached in
CR_XSAVE_PAGE_i)
SSA.XSAVE.i XSAVE_STATE_i;
(* Clear bytes 8 to 23 of XSAVE_HEADER, i.e. the next 16 bytes after XHEADER_BV *)
CR_XSAVE_PAGE_0.XHEADER_BV[191:64] 0;
(* Clear bits in XHEADER_BV[63:0] that are not enabled in ATTRIBUTES.XFRM *)
CR_XSAVE_PAGE_0.XHEADER_BV[63:0]
CR_XSAVE_PAGE_0.XHEADER_BV[63:0] & SECS(CR_ACTIVE_SECS).ATTRIBUTES.XFRM;
Apply synthetic state to GPRs, RFLAGS, extended features, etc.
(* Restore the RSP and RBP from the current SSA frame's GPR area using the physical address
that was determined and cached at enclave entry time with CR_GPR_PA. *)
RSP CR_GPR_PA.URSP;
RBP CR_GPR_PA.URBP;
Vol. 3D 40-5
ENCLAVE EXITING EVENTS
(* Restore the FS and GS *)
FS.selector CR_SAVE_FS.selector;
FS.base CR_SAVE_FS.base;
FS.limit CR_SAVE_FS.limit;
FS.access_rights CR_SAVE_FS.access_rights;
GS.selector CR_SAVE_GS.selector;
GS.base CR_SAVE_GS.base;
GS.limit CR_SAVE_GS.limit;
GS.access_rights CR_SAVE_GS.access_rights;
(* Examine exception code and update enclave internal states*)
exception_code Exception or interrupt vector;
(* Indicate the exit reason in SSA *)
IF (exception_code = (#DE OR #DB OR #BP OR #BR OR #UD OR #MF OR #AC OR #XM ))
THEN
CR_GPR_PA.EXITINFO.VECTOR exception_code;
IF (exception code = #BP)
THEN CR_GPR_PA.EXITINFO.EXIT_TYPE 6;
ELSE CR_GPR_PA.EXITINFO.EXIT_TYPE 3;
FI;
CR_GPR_PA.EXITINFO.VALID 1;
ELSE IF (exception_code is #PF or #GP )
THEN
(* Check SECS.MISCSELECT using CR_ACTIVE_SECS *)
IF (SECS.MISCSELECT[0] is set)
THEN
CR_GPR_PA.EXITINFO.VECTOR exception_code;
CR_GPR_PA.EXITINFO.EXIT_TYPE 3;
IF (exception_code is #PF)
THEN
SSA.MISC.EXINFO. MADDR CR2;
SSA.MISC.EXINFO.ERRCD PFEC;
SSA.MISC.EXINFO.RESERVED 0;
ELSE
SSA.MISC.EXINFO. MADDR 0;
SSA.MISC.EXINFO.ERRCD GPEC;
SSA.MISC.EXINFO.RESERVED 0;
FI;
CR_GPR_PA.EXITINFO.VALID 1;
FI;
ELSE
CR_GPR_PA.EXITINFO.VECTOR 0;
CR_GPR_PA.EXITINFO.EXIT_TYPE 0
CR_GPR_PA.REASON.VALID 0;
FI;
(* Execution will resume at the AEP *)
RIP CR_TCS_PA.AEP;
(* Set EAX to the ERESUME leaf index *)
EAX 3;
40-6 Vol. 3D
ENCLAVE EXITING EVENTS
(* Put the TCS LA into RBX for later use by ERESUME *)
RBX CR_TCS_LA;
(* Put the AEP into RCX for later use by ERESUME *)
RCX CR_TCS_PA.AEP;
(* Increment the SSA frame # *)
CR_TCS_PA.CSSA CR_TCS_PA.CSSA + 1;
(* Restore XCR0 if needed *)
IF (CR4.OSXSAVE = 1)
THEN XCR0 CR_SAVE_XCR0; FI;
Un-suppress all code breakpoints that are outside ELRANGE
(* Update the thread context to show not in enclave mode *)
CR_ENCLAVE_MODE 0;
(* Assure consistent translations. *)
Flush linear context including TLBs and paging-structure caches
IF (CR_DBGOPTIN = 0)
THEN
Un-suppress all breakpoints that overlap ELRANGE
(* Clear suppressed breakpoint matches *)
Restore suppressed breakpoint matches
(* Restore TF *)
RFLAGS.TF CR_SAVE_TF;
Un-suppress monitor trap flag;
Un-suppress branch recording facilities;
Un-suppress all suppressed performance monitoring activity;
Promote any sibling-thread counters that were demoted from AnyThread to MyThread during enclave
entry back to AnyThread;
FI;
IF the “monitor trap flag” VM-execution control is 1
THEN Pend MTF VM Exit at the end of exit; FI;
(* Clear low 12 bits of CR2 on #PF *)
IF (Exception code is #PF)
THEN CR2 CR2 & ~0xFFF; FI;
(* end_of_flow *)
(* Execution continues with normal event processing. *)
Vol. 3D 40-7
ENCLAVE EXITING EVENTS
40-8 Vol. 3D
SGX INSTRUCTION REFERENCES
CHAPTER 41
SGX INSTRUCTION REFERENCES
This chapter describes the supervisor and user level instructions provided by Intel® Software Guard Extensions
(Intel® SGX). In general, a various functionality is encoded as leaf functions within the ENCLS (supervisor) and
ENCLU (user) instruction mnemonics. Different leaf functions are encoded by specifying an input value in the EAX
register of the respective instruction mnemonic.
41.1
INTEL® SGX INSTRUCTION SYNTAX AND OPERATION
ENCLS and ENCLU instruction mnemonics for all leaf functions are covered in this section.
For all instructions, the value of CS.D is ignored; addresses and operands are 64 bits in 64-bit mode and are otherwise 32 bits. Aside from EAX specifying the leaf number as input, each instruction leaf may require all or some
subset of the RBX/RCX/RDX as input parameters. Some leaf functions may return data or status information in one
or more of the general purpose registers.
41.1.1
ENCLS Register Usage Summary
Table 41-1 summarizes the implicit register usage of supervisor mode enclave instructions.
Table 41-1. Register Usage of Privileged Enclave Instruction Leaf Functions
Instr. Leaf
EAX
RBX
RCX
ECREATE
00H (In)
PAGEINFO (In, EA)
EPCPAGE (In, EA)
EADD
01H (In)
PAGEINFO (In, EA)
EPCPAGE (In, EA)
EINIT
02H (In)
SIGSTRUCT (In, EA)
SECS (In, EA)
RDX
EINITTOKEN (In, EA)
EREMOVE
03H (In)
EDBGRD
04H (In)
Result Data (Out)
EPCPAGE (In, EA)
EPCPAGE (In, EA)
EDBGWR
05H (In)
Source Data (In)
EPCPAGE (In, EA)
EEXTEND
06H (In)
SECS (In, EA)
EPCPAGE (In, EA)
ELDB
07H (In)
PAGEINFO (In, EA)
EPCPAGE (In, EA)
VERSION (In, EA)
ELDU
08H (In)
PAGEINFO (In, EA)
EPCPAGE (In, EA)
VERSION (In, EA)
EBLOCK
09H (In)
EPA
0AH (In)
PT_VA (In)
EWB
0BH (In)
PAGEINFO (In, EA)
ETRACK
0CH (In)
EAUG
0DH (In)
PAGEINFO (In, EA)
EPCPAGE (In, EA)
EMODPR
0EH (In)
SECINFO (In, EA)
EPCPAGE (In, EA)
EMODT
0FH (In)
SECINFO (In, EA)
EPCPAGE (In, EA)
EPCPAGE (In, EA)
EPCPAGE (In, EA)
EPCPAGE (In, EA)
VERSION (In, EA)
EPCPAGE (In, EA)
LINADDR
EA: Effective Address
41.1.2
ENCLU Register Usage Summary
Table 41-2 Summarized the implicit register usage of user mode enclave instructions.
Vol. 3D 41-1
SGX INSTRUCTION REFERENCES
Table 41-2. Register Usage of Unprivileged Enclave Instruction Leaf Functions
Instr. Leaf
EAX
RBX
RCX
RDX
EREPORT
00H (In)
TARGETINFO (In, EA)
REPORTDATA (In, EA)
OUTPUTDATA (In, EA)
EGETKEY
01H (In)
KEYREQUEST (In, EA)
KEY (In, EA)
EENTER
02H (In)
TCS (In, EA)
AEP (In, EA)
RBX.CSSA (Out)
Return (Out, EA)
ERESUME
03H (In)
TCS (In, EA)
AEP (In, EA)
EEXIT
04H (In)
Target (In, EA)
Current AEP (Out)
EACCEPT
05H (In)
SECINFO (In, EA)
EPCPAGE (In, EA)
EMODPE
06H (In)
SECINFO (In, EA)
EPCPAGE (In, EA)
EACCEPTCOPY
07H (In)
SECINFO (In, EA)
EPCPAGE (In, EA)
EPCPAGE (In, EA)
EA: Effective Address
41.1.3
Information and Error Codes
Information and error codes are reported by various instruction leaf functions to show an abnormal termination of
the instruction or provide information which may be useful to the developer. Table 41-3 shows the various codes
and the instruction which generated the code. Details of the meaning of the code is provided in the individual
instruction.
Table 41-3. Error or Information Codes for Intel® SGX Instructions
Name
Value
Returned By
No Error
0
SGX_INVALID_SIG_STRUCT
1
EINIT
SGX_INVALID_ATTRIBUTE
2
EINIT, EGETKEY
SGX_BLSTATE
3
EBLOCK
SGX_INVALID_MEASUREMENT
4
EINIT
SGX_NOTBLOCKABLE
5
EBLOCK
SGX_PG_INVLD
6
EBLOCK
SGX_LOCKFAIL
7
EBLOCK, EMODPR, EMODT
SGX_INVALID_SIGNATURE
8
EINIT
SGX_MAC_COMPARE_FAIL
9
ELDB, ELDU
SGX_PAGE_NOT_BLOCKED
10
EWB
SGX_NOT_TRACKED
11
EWB, EACCEPT
SGX_VA_SLOT_OCCUPIED
12
EWB
SGX_CHILD_PRESENT
13
EWB, EREMOVE
SGX_ENCLAVE_ACT
14
EREMOVE
SGX_ENTRYEPOCH_LOCKED
15
EBLOCK
SGX_INVALID_EINIT_TOKEN
16
EINIT
SGX_PREV_TRK_INCMPL
17
ETRACK
SGX_PG_IS_SECS
18
EBLOCK
SGX_PAGE_ATTRIBUTES_MISMATCH
19
EACCEPT, EACCEPTCOPY
SGX_PAGE_NOT_MODIFIABLE
20
EMODPR, EMODT
SGX_PAGE_NOT_DEBUGGABLE
21
EDEGRD, EDBGWR
41-2 Vol. 3D
SGX INSTRUCTION REFERENCES
Table 41-3. Error or Information Codes for Intel® SGX Instructions
Name
Value
Returned By
SGX_INVALID_CPUSVN
32
EINIT, EGETKEY
SGX_INVALID_ISVSVN
64
EGETKEY
SGX_UNMASKED_EVENT
128
EINIT
SGX_INVALID_KEYNAME
256
EGETKEY
41.1.4
Internal CREGs
The CREGs as shown in Table 5-4 are hardware specific registers used in this document to indicate values kept by
the processor. These values are used while executing in enclave mode or while executing an Intel SGX instruction.
These registers are not software visible and are implementation specific. The values in Table 41-4 appear at various
places in the pseudo-code of this document. They are used to enhance understanding of the operations.
Table 41-4. List of Internal CREG
Name
Size (Bits)
Scope
CR_ENCLAVE_MODE
1
LP
CR_DBGOPTIN
1
LP
CR_TCS_LA
64
LP
CR_TCS_PH
64
LP
CR_ACTIVE_SECS
64
LP
CR_ELRANGE
128
LP
CR_SAVE_TF
1
LP
CR_SAVE_FS
64
LP
CR_GPR_PA
64
LP
CR_XSAVE_PAGE_n
64
LP
CR_SAVE_DR7
64
LP
CR_SAVE_PERF_GLOBAL_CTRL
64
LP
CR_SAVE_DEBUGCTL
64
LP
CR_SAVE_PEBS_ENABLE
64
LP
CR_CPUSVN
128
PACKAGE
CSR_SGX_OWNEREPOCH
128
PACKAGE
CR_SAVE_XCR0
64
LP
CR_SGX_ATTRIBUTES_MASK
128
LP
CR_PAGING_VERSION
64
PACKAGE
CR_VERSION_THRESHOLD
64
PACKAGE
CR_NEXT_EID
64
PACKAGE
CR_BASE_PK
128
PACKAGE
CR_SEAL_FUSES
128
PACKAGE
41.1.5
Concurrent Operation Restrictions
To protect the integrity of Intel SGX data structures, under certain conditions, Intel SGX disallows certain leaf functions from operating concurrently. Listed below are some examples of concurrency that are not allowed.
•
For example, Intel SGX disallows the following leafs to concurrently operate on the same EPC page.
Vol. 3D 41-3
SGX INSTRUCTION REFERENCES
— ECREATE, EADD, and EREMOVE are not allowed to operate on the same EPC page concurrently with
themselves.
— EADD, EEXTEND, and EINIT leafs are not allowed to operate on the same SECS concurrently.
•
•
Intel SGX disallows the EREMOVE leaf from removing pages from an enclave that is in use.
Intel SGX disallows entry (EENTER and ERESUME) to an enclave while a page from that enclave is being
removed.
When disallowed operation is detected, a leaf function causes an exception. To prevent such exceptions, software
must serialize leaf functions or prevent these leaf functions from accessing the same resource.
41.1.5.1
Concurrency Tables of Intel® SGX Instructions
Concurrent restriction of an individual leaf function (ENCLS or ENCLU) with another Intel SGX instruction leaf functions is listed under the Concurrency Restriction paragraph of the respective reference pages of the leaf function.
Each cell in the table for a given Intel SGX Instruction leaf details the concurrency restriction when that instruction
references the same EPC page (as an explicit or an implicit parameter) as referenced by a concurrent instruction
leaf executed on another logical processor. The concurrency behavior of the instruction leaf if focus shown in a
given row is denoted by the following:
•
‘N’: The instructions listed in a given row heading may not execute concurrently with the instruction leaf shown
in the respective column. Software should serialize them. For example, multiple ETRACK operations on the
same enclave are not allowed to execute concurrently on the same SECS page.
•
‘Y’: The instruction leaf listed in a given row may execute concurrently with the instruction leaf shown in the
respective column. For instance, multiple ELDB/ELDUs are allowed to execute concurrently as long as the
selected EPC page is not the same page.
•
‘C’: The instruction leaf listed in a given row heading may return an error code when executed concurrently with
the instruction leaf shown in the respective column.
•
‘U’: These two instruction leaves may complete, but the occurrence these two simultaneous flows are
considered a user program error for which the processor does not enforce any restriction.
•
A grey cell indicates the concurrency behavior of the instruction in focus (in the row header) may be different
than that of the concurrent instruction (in the column header). The concurrent instruction's behavior is detailed
in its respective concurrency table. For example, EBLOCK's SECS parameter is implicit, thus it is always shown
as 'Y' in the table. However a concurrent instruction may return an error code when accessing the same page.
For instance, multiple ELDB/ELDUs are allowed to execute as long as the selected EPC page is not the same page.
Multiple ETRACK operations are not allowed to execute concurrently.
41.2
41-4 Vol. 3D
INTEL® SGX INSTRUCTION REFERENCE
SGX INSTRUCTION REFERENCES
ENCLS—Execute an Enclave System Function of Specified Leaf Number
Opcode/
Instruction
Op/En
0F 01 CF
ENCLS
NP
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This instruction is used to execute privileged Intel SGX leaf functions that are used for managing and debugging the enclaves.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Implicit Register Operands
NP
NA
NA
NA
See Section 41.3
Description
The ENCLS instruction invokes the specified privileged Intel SGX leaf function for managing and debugging
enclaves. Software specifies the leaf function by setting the appropriate value in the register EAX as input. The
registers RBX, RCX, and RDX have leaf-specific purpose, and may act as input, as output, or may be unused. In 64bit mode, the instruction ignores upper 32 bits of the RAX register.
The ENCLS instruction produces an invalid-opcode exception (#UD) if CR0.PE = 0 or RFLAGS.VM = 1, or if it is
executed in system-management mode (SMM). Additionally, any attempt to execute the instruction when CPL > 0
results in #UD. The instruction produces a general-protection exception (#GP) if CR0.PG = 0 or if an attempt is
made to invoke an undefined leaf function.
In VMX non-root operation, execution of ENCLS may cause a VM exit if the “enable ENCLS exiting” VM-execution
control is 1. In this case, execution of individual leaf functions of ENCLS is governed by the ENCLS-exiting bitmap
field in the VMCS. Each bit in that field corresponds to the index of an ENCLS leaf function (as provided in EAX).
Software in VMX root operation can thus intercept the invocation of various ENCLS leaf functions in VMX non-root
operation by setting the “enable ENCLS exiting” VM-execution control and setting the corresponding bits in the
ENCLS-exiting bitmap.
Addresses and operands are 32 bits outside 64-bit mode (IA32_EFER.LMA = 0 || CS.L = 0) and are 64 bits in 64bit mode (IA32_EFER.LMA = 1 || CS.L = 1). CS.D value has no impact on address calculation. The DS segment is
used to create linear addresses.
Segment override prefixes and address-size override prefixes are ignored, and is the REX prefix in 64-bit mode.
Operation
IF TSX_ACTIVE
THEN GOTO TSX_ABORT_PROCESSING; FI;
IF CR0.PE = 0 or RFLAGS.VM = 1 or in SMM or CPUID.SGX_LEAF.0:EAX.SE1 = 0
THEN #UD; FI;
IF (CPL > 0)
THEN #UD; FI;
IF in VMX non-root operation and the “enable ENCLS exiting“ VM-execution control is 1
THEN
IF EAX < 63 and ENCLS_exiting_bitmap[EAX] = 1 or EAX> 62 and ENCLS_exiting_bitmap[63] = 1
THEN VM exit;
FI;
FI;
IF IA32_FEATURE_CONTROL.LOCK = 0 or IA32_FEATURE_CONTROL.SGX_ENABLE = 0
THEN #GP(0); FI;
IF EAX is invalid leaf number)
Vol. 3D 41-5
SGX INSTRUCTION REFERENCES
THEN #GP(0); FI;
IF CR0.PG = 0
THEN #GP(0); FI;
(* DS must not be an expanded down segment *)
IF not in 64-bit mode and DS.Type is expand-down data
THEN #GP(0); FI;
Jump to leaf specific flow
Flags Affected
See individual leaf functions
Protected Mode Exceptions
#UD
If any of the LOCK/OSIZE/REP/VEX prefix is used.
If current privilege level is not 0.
If CPUID.(EAX=12H,ECX=0):EAX.SGX1 [bit 0] = 0.
If logical processor is in SMM.
#GP(0)
If IA32_FEATURE_CONTROL.LOCK = 0.
If IA32_FEATURE_CONTROL.SGX_ENABLE = 0.
If input value in EAX encodes an unsupported leaf.
If data segment expand down.
If CR0.PG=0.
Real-Address Mode Exceptions
#UD
ENCLS is not recognized in real mode.
Virtual-8086 Mode Exceptions
#UD
ENCLS is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If any of the LOCK/OSIZE/REP/VEX prefix is used.
If current privilege level is not 0.
If CPUID.(EAX=12H,ECX=0):EAX.SGX1 [bit 0] = 0.
If logical processor is in SMM.
#GP(0)
If IA32_FEATURE_CONTROL.LOCK = 0.
If IA32_FEATURE_CONTROL.SGX_ENABLE = 0.
If input value in EAX encodes an unsupported leaf.
41-6 Vol. 3D
SGX INSTRUCTION REFERENCES
ENCLU—Execute an Enclave User Function of Specified Leaf Number
Opcode/
Instruction
Op/En
0F 01 D7
ENCLU
NP
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This instruction is used to execute non-privileged Intel SGX leaf
functions.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Implicit Register Operands
NP
NA
NA
NA
See Section 41.4
Description
The ENCLU instruction invokes the specified non-privileged Intel SGX leaf functions. Software specifies the leaf
function by setting the appropriate value in the register EAX as input. The registers RBX, RCX, and RDX have leafspecific purpose, and may act as input, as output, or may be unused. In 64-bit mode, the instruction ignores upper
32 bits of the RAX register.
The ENCLU instruction produces an invalid-opcode exception (#UD) if CR0.PE = 0 or RFLAGS.VM = 1, or if it is
executed in system-management mode (SMM). Additionally, any attempt to execute this instruction when CPL < 3
results in #UD. The instruction produces a general-protection exception (#GP) if either CR0.PG or CR0.NE is 0, or
if an attempt is made to invoke an undefined leaf function. The ENCLU instruction produces a device not available
exception (#NM) if CR0.TS = 1.
Addresses and operands are 32 bits outside 64-bit mode (IA32_EFER.LMA = 0 or CS.L = 0) and are 64 bits in 64bit mode (IA32_EFER.LMA = 1 and CS.L = 1). CS.D value has no impact on address calculation. The DS segment
is used to create linear addresses.
Segment override prefixes and address-size override prefixes are ignored, and is the REX prefix in 64-bit mode.
Operation
IN_64BIT_MODE 0;
IF TSX_ACTIVE
THEN GOTO TSX_ABORT_PROCESSING; FI;
IF CR0.PE= 0 or RFLAGS.VM = 1 or in SMM or CPUID.SGX_LEAF.0:EAX.SE1 = 0
THEN #UD; FI;
IF CR0.TS = 1
THEN #NM; FI;
IF CPL < 3
THEN #UD; FI;
IF IA32_FEATURE_CONTROL.LOCK = 0 or IA32_FEATURE_CONTROL.SGX_ENABLE = 0
THEN #GP(0); FI;
IF EAX is invalid leaf number
THEN #GP(0); FI;
IF CR0.PG = 0 or CR0.NE = 0
THEN #GP(0); FI;
IN_64BIT_MODE IA32_EFER.LMA AND CS.L ? 1 : 0;
(* Check not in 16-bit mode and DS is not a 16-bit segment *)
IF not in 64-bit mode and (CS.D = 0 or DS.B = 0)
Vol. 3D 41-7
SGX INSTRUCTION REFERENCES
THEN #GP(0); FI;
IF CR_ENCLAVE_MODE = 1 and (EAX = 2 or EAX = 3) (* EENTER or ERESUME *)
THEN #GP(0); FI;
IF CR_ENCLAVE_MODE = 0 and (EAX = 0 or EAX = 1 or EAX = 4 or EAX = 5 or EAX = 6 or EAX = 7)
(* EREPORT, EGETKEY, EEXIT, EACCEPT, EMODPE, or EACCEPTCOPY *)
THEN #GP(0); FI;
Jump to leaf specific flow
Flags Affected
See individual leaf functions
Protected Mode Exceptions
#UD
If any of the LOCK/OSIZE/REP/VEX prefix is used.
If current privilege level is not 3.
If CPUID.(EAX=12H,ECX=0):EAX.SGX1 [bit 0] = 0.
If logical processor is in SMM.
#GP(0)
If IA32_FEATURE_CONTROL.LOCK = 0.
If IA32_FEATURE_CONTROL.SGX_ENABLE = 0.
If input value in EAX encodes an unsupported leaf.
If input value in EAX encodes EENTER/ERESUME and ENCLAVE_MODE = 1.
If input value in EAX encodes EGETKEY/EREPORT/EEXIT/EACCEPT/EACCEPTCOPY/EMODPE
and ENCLAVE_MODE = 0.
If operating in 16-bit mode.
If data segment is in 16-bit mode.
If CR0.PG = 0 or CR0.NE= 0.
#NM
If CR0.TS = 1.
Real-Address Mode Exceptions
#UD
ENCLS is not recognized in real mode.
Virtual-8086 Mode Exceptions
#UD
ENCLS is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If any of the LOCK/OSIZE/REP/VEX prefix is used.
If current privilege level is not 3.
If CPUID.(EAX=12H,ECX=0):EAX.SGX1 [bit 0] = 0.
If logical processor is in SMM.
#GP(0)
If IA32_FEATURE_CONTROL.LOCK = 0.
If IA32_FEATURE_CONTROL.SGX_ENABLE = 0.
If input value in EAX encodes an unsupported leaf.
If input value in EAX encodes EENTER/ERESUME and ENCLAVE_MODE = 1.
If input value in EAX encodes EGETKEY/EREPORT/EEXIT/EACCEPT/EACCEPTCOPY/EMODPE
and ENCLAVE_MODE = 0.
41-8 Vol. 3D
SGX INSTRUCTION REFERENCES
If CR0.NE= 0.
#NM
If CR0.TS = 1.
Vol. 3D 41-9
SGX INSTRUCTION REFERENCES
41.3
INTEL® SGX SYSTEM LEAF FUNCTION REFERENCE
Leaf functions available with the ENCLS instruction mnemonic are covered in this section. In general, each instruction leaf requires EAX to specify the leaf function index and/or additional implicit registers specifying leaf-specific
input parameters. An instruction operand encoding table provides details of each implicit register usage and associated input/output semantics.
In many cases, an input parameter specifies an effective address associated with a memory object inside or outside
the EPC, the memory addressing semantics of these memory objects are also summarized in a separate table.
41-10 Vol. 3D
SGX INSTRUCTION REFERENCES
EADD—Add a Page to an Uninitialized Enclave
Opcode/
Instruction
Op/En
EAX = 01H
ENCLS[EADD]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function adds a page to an uninitialized enclave.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EADD (In)
Address of a PAGEINFO (In)
Address of the destination EPC page (In)
Description
This leaf function copies a source page from non-enclave memory into the EPC, associates the EPC page with an
SECS page residing in the EPC, and stores the linear address and security attributes in EPCM. As part of the association, the enclave offset and the security attributes are measured and extended into the SECS.MRENCLAVE. This
instruction can only be executed when current privilege level is 0.
RBX contains the effective address of a PAGEINFO structure while RCX contains the effective address of an EPC
page. The table below provides additional information on the memory parameter of EADD leaf function.
EADD Memory Parameter Semantics
PAGEINFO
PAGEINFO.SECS
PAGEINFO.SRCPGE
PAGEINFO.SECINFO
EPCPAGE
Read access permitted
by Non Enclave
Read/Write access permitted by Enclave
Read access permitted
by Non Enclave
Read access permitted
by Non Enclave
Write access permitted
by Enclave
The instruction faults if any of the following:
EADD Faulting Conditions
The operands are not properly aligned.
Unsupported security attributes are set.
Refers to an invalid SECS.
Reference is made to an SECS that is locked by another thread.
The EPC page is locked by another thread.
RCX does not contain an effective address of an EPC page.
The EPC page is already valid.
If security attributes specifies a TCS and the source page specifies unsupported
TCS values or fields.
The SECS has been initialized.
The specified enclave offset is outside of the enclave address space.
Concurrency Restrictions
Table 41-5. Concurrency Restrictions of EADD with Other Intel® SGX Operations 1 of 2
Operation
Param
EADD
EEXIT
TCS SSA
EADD
SECS Targ SECS
N
Targ
SECS
N
N
EBLOCK
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EPA
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
SECS VA
N
N
N
N
N
N
N
N
Y
N
Y
Y
N
Y
N
N
N
N
N
N
Vol. 3D 41-11
SGX INSTRUCTION REFERENCES
Table 41-6. Concurrency Restrictions of EADD with Other Intel® SGX Operations 2 of 2
Operation
EADD
EREMOVE
EREPORT
Param
Targ SECS Para
m
Targ
N
SECS
N
Y
SECS
N
ETRACK
EWB
SECS
SRC
VA
N
N
N
Y
N
EAUG
EMODPE
EMODPR
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Y
N
N
N
N
N
EMODT
Targ SEC
S
EACCEPT
Targ SECI
NFO
EACCEPTCOPY
SECS Targ SR
C
SECI
NFO
N
N
N
N
N
Operation
Temp Variables in EADD Operational Flow
Name
Type
Size (bits)
Description
TMP_SRCPGE
Effective Address
32/64
Effective address of the source page.
TMP_SECS
Effective Address
32/64
Effective address of the SECS destination page.
TMP_SECINFO
Effective Address
32/64
Effective address of an SECINFO structure which contains security
attributes of the page to be added.
SCRATCH_SECINFO
SECINFO
512
Scratch storage for holding the contents of DS:TMP_SECINFO.
TMP_LINADDR
Unsigned Integer
64
Holds the linear address to be stored in the EPCM and used to
calculate TMP_ENCLAVEOFFSET.
TMP_ENCLAVEOFFSET
Enclave Offset
64
The page displacement from the enclave base address.
TMPUPDATEFIELD
SHA256 Buffer
512
Buffer used to hold data being added to TMP_SECS.MRENCLAVE.
IF (DS:RBX is not 32Byte Aligned)
THEN #GP(0); FI;
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
TMP_SRCPGE DS:RBX.SRCPGE;
TMP_SECS DS:RBX.SECS;
TMP_SECINFO DS:RBX.SECINFO;
TMP_LINADDR DS:RBX.LINADDR;
IF (DS:TMP_SRCPGE is not 4KByte aligned or DS:TMP_SECS is not 4KByte aligned or
DS:TMP_SECINFO is not 64Byte aligned or TMP_LINADDR is not 4KByte aligned)
THEN #GP(0); FI;
IF (DS:TMP_SECS does not resolve within an EPC)
THEN #PF(DS:TMP_SECS); FI;
SCRATCH_SECINFO DS:TMP_SECINFO;
(* Check for mis-configured SECINFO flags*)
IF (SCRATCH_SECINFO reserved fields are not zero or
! (SCRATCH_SECINFO.FLAGS.PT is PT_REG or SCRATCH_SECINFO.FLAGS.PT is PT_TCS) )
THEN #GP(0); FI;
41-12 Vol. 3D
SGX INSTRUCTION REFERENCES
(* Check the EPC page for concurrency *)
IF (EPC page in use)
THEN #GP(0); FI;
IF (EPCM(DS:RCX).VALID ≠ 0)
THEN #PF(DS:RCX); FI;
(* Check the SECS for concurrency *)
IF (SECS is not available for EADD)
THEN #GP(0); FI;
IF (EPCM(DS:TMP_SECS).VALID = 0 or EPCM(DS:TMP_SECS).PT ≠ PT_SECS)
THEN #PF(DS:TMP_SECS); FI;
(* Copy 4KBytes from source page to EPC page*)
DS:RCX[32767:0] DS:TMP_SRCPGE[32767:0];
CASE (SCRATCH_SECINFO.FLAGS.PT)
{
PT_TCS:
IF (DS:RCX.RESERVED ≠ 0) #GP(0); FI;
IF ( (DS:TMP_SECS.ATTIBUTES.MODE64BIT = 0) and
((DS:TCS.FSLIMIT & 0FFFH ≠ 0FFFH) or (DS:TCS.GSLIMIT & 0FFFH ≠ 0FFFH) )) #GP(0); FI;
BREAK;
PT_REG:
IF (SCRATCH_SECINFO.FLAGS.W = 1 and SCRATCH_SECINFO.FLAGS.R = 0) #GP(0); FI;
BREAK;
ESAC;
(* Check the enclave offset is within the enclave linear address space *)
IF (TMP_LINADDR < DS:TMP_SECS.BASEADDR or TMP_LINADDR ≥ DS:TMP_SECS.BASEADDR + DS:TMP_SECS.SIZE)
THEN #GP(0); FI;
(* Check concurrency of measurement resource*)
IF (Measurement being updated)
THEN #GP(0); FI;
(* Check if the enclave to which the page will be added is already in Initialized state *)
IF (DS:TMP_SECS already initialized)
THEN #GP(0); FI;
(* For TCS pages, force EPCM.rwx bits to 0 and no debug access *)
IF (SCRATCH_SECINFO.FLAGS.PT = PT_TCS)
THEN
SCRATCH_SECINFO.FLAGS.R 0;
SCRATCH_SECINFO.FLAGS.W 0;
SCRATCH_SECINFO.FLAGS.X 0;
(DS:RCX).FLAGS.DBGOPTIN 0; // force TCS.FLAGS.DBGOPTIN off
DS:RCX.CSSA 0;
DS:RCX.AEP 0;
DS:RCX.STATE 0;
FI;
(* Add enclave offset and security attributes to MRENCLAVE *)
Vol. 3D 41-13
SGX INSTRUCTION REFERENCES
TMP_ENCLAVEOFFSET TMP_LINADDR - DS:TMP_SECS.BASEADDR;
TMPUPDATEFIELD[63:0] 0000000044444145H; // “EADD”
TMPUPDATEFIELD[127:64] TMP_ENCLAVEOFFSET;
TMPUPDATEFIELD[511:128] SCRATCH_SECINFO[375:0]; // 48 bytes
DS:TMP_SECS.MRENCLAVE SHA256UPDATE(DS:TMP_SECS.MRENCLAVE, TMPUPDATEFIELD)
INC enclave’s MRENCLAVE update counter;
(* Add enclave offset and security attributes to MRENCLAVE *)
EPCM(DS:RCX).R SCRATCH_SECINFO.FLAGS.R;
EPCM(DS:RCX).W SCRATCH_SECINFO.FLAGS.W;
EPCM(DS:RCX).X SCRATCH_SECINFO.FLAGS.X;
EPCM(DS:RCX).PT SCRATCH_SECINFO.FLAGS.PT;
EPCM(DS:RCX).ENCLAVEADDRESS TMP_LINADDR;
(* associate the EPCPAGE with the SECS by storing the SECS identifier of DS:TMP_SECS *)
Update EPCM(DS:RCX) SECS identifier to reference DS:TMP_SECS identifier;
(* Set EPCM entry fields *)
EPCM(DS:RCX).BLOCKED 0;
EPCM(DS:RCX).PENDING 0;
EPCM(DS:RCX).MODIFIED 0;
EPCM(DS:RCX).VALID 1;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If an enclave memory operand is outside of the EPC.
If an enclave memory operand is the wrong type.
If a memory operand is locked.
If the enclave is initialized.
If the enclave's MRENCLAVE is locked.
If the TCS page reserved bits are set.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the EPC page is valid.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If an enclave memory operand is outside of the EPC.
If an enclave memory operand is the wrong type.
If a memory operand is locked.
If the enclave is initialized.
If the enclave's MRENCLAVE is locked.
If the TCS page reserved bits are set.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the EPC page is valid.
41-14 Vol. 3D
SGX INSTRUCTION REFERENCES
EAUG—Add a Page to an Initialized Enclave
Opcode/
Instruction
Op/En
EAX = 0DH
ENCLS[EAUG]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX2
Description
This leaf function adds a page to an initialized enclave.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EAUG (In)
Address of a SECINFO (In)
Address of the destination EPC page (In)
Description
This leaf function zeroes a page of EPC memory, associates the EPC page with an SECS page residing in the EPC,
and stores the linear address and security attributes in the EPCM. As part of the association, the security attributes
are configured to prevent access to the EPC page until a corresponding invocation of the EACCEPT leaf or EACCEPTCOPY leaf confirms the addition of the new page into the enclave. This instruction can only be executed when
current privilege level is 0.
RBX contains the effective address of a PAGEINFO structure while RCX contains the effective address of an EPC
page. The table below provides additional information on the memory parameter of the EAUG leaf function.
EAUG Memory Parameter Semantics
PAGEINFO
PAGEINFO.SECS
PAGEINFO.SRCPGE
PAGEINFO.SECINFO
EPCPAGE
Read access permitted by Non Enclave
Read/Write access permitted by Enclave
Must be zero
Read access permitted by
Non Enclave
Write access permitted by
Enclave
The instruction faults if any of the following:
EAUG Faulting Conditions
The operands are not properly aligned.
Unsupported security attributes are set.
Refers to an invalid SECS.
Reference is made to an SECS that is locked by another thread.
The EPC page is locked by another thread.
RCX does not contain an effective address of an EPC page.
The EPC page is already valid.
The specified enclave offset is outside of the enclave address space.
The SECS has been initialized.
Concurrency Restrictions
Table 41-7. Concurrency Restrictions of EAUG with Other Intel® SGX Operations 1 of 2
Operation
Param
EAUG
EEXIT
TCS SSA
SECS
Targ
SECS
Y
EADD
EBLOCK
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EP
A
Targ SECS
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
SECS VA
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
Y
N
Y
N
Y
N
Y
N
Vol. 3D 41-15
SGX INSTRUCTION REFERENCES
Table 41-8. Concurrency Restrictions of EAUG with Other Intel® SGX Operations 2 of 2
Operation
EAUG
EREMOVE
EREPORT
ETRACK
EWB
Param
Targ SECS Param SECS
SECS
SRC
VA
Targ
N
N
N
N
SECS
N
Y
N
Y
Y
EAUG
EMODPE
EMODPR
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Y
N
N
N
Y
N
EMODT
Targ SEC
S
EACCEPT
Targ SECI
NFO
EACCEPTCOPY
SECS Targ SR
C
SECI
NFO
N
Y
N
Y
Y
Operation
Temp Variables in EAUG Operational Flow
Name
Type
Size (bits)
Description
TMP_SECS
Effective Address
32/64
Effective address of the SECS destination page.
TMP_SECINFO
Effective Address
32/64
Effective address of an SECINFO structure which contains security
attributes of the page to be added.
SCRATCH_SECINFO
SECINFO
512
Scratch storage for holding the contents of DS:TMP_SECINFO.
TMP_LINADDR
Unsigned Integer
64
Holds the linear address to be stored in the EPCM and used to
calculate TMP_ENCLAVEOFFSET.
IF (DS:RBX is not 32Byte Aligned)
THEN #GP(0); FI;
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
TMP_SECS DS:RBX.SECS;
TMP_LINADDR DS:RBX.LINADDR;
IF ( DS:TMP_SECS is not 4KByte aligned or TMP_LINADDR is not 4KByte aligned )
THEN #GP(0); FI;
IF ( (DS:RBX.SRCPAGE is not 0) or (DS:RBX:SECINFO is not 0) )
THEN #GP(0); FI;
IF (DS:TMP_SECS does not resolve within an EPC)
THEN #PF(DS:SECS); FI;
(* Check the EPC page for concurrency *)
IF (EPC page in use)
THEN #GP(0); FI;
IF (EPCM(DS:RCX).VALID ≠ 0)
THEN #PF(DS:RCX); FI;
(* Check the SECS for concurrency *)
IF (SECS is not available for EAUG)
THEN #GP(0); FI;
41-16 Vol. 3D
SGX INSTRUCTION REFERENCES
IF (EPCM(DS:TMP_SECS).VALID = 0 or EPCM(DS:TMP_SECS).PT ≠ PT_SECS)
THEN #PF(DS:TMP_SECS); FI;
(* Check if the enclave to which the page will be added is in the Initialized state *)
IF (DS:TMP_SECS is not initialized)
THEN #GP(0); FI;
(* Check the enclave offset is within the enclave linear address space *)
IF ( (TMP_LINADDR < DS:TMP_SECS.BASEADDR) or (TMP_LINADDR ≥ DS:TMP_SECS.BASEADDR + DS:TMP_SECS.SIZE) )
THEN #GP(0); FI;
(* Clear the content of EPC page*)
DS:RCX[32767:0] 0;
(* Set EPCM security attributes *)
EPCM(DS:RCX).R 1;
EPCM(DS:RCX).W 1;
EPCM(DS:RCX).X 0;
EPCM(DS:RCX).PT PT_REG;
EPCM(DS:RCX).ENCLAVEADDRESS TMP_LINADDR;
EPCM(DS:RCX).BLOCKED 0;
EPCM(DS:RCX).PENDING 1;
EPCM(DS:RCX).MODIFIED 0;
EPCM(DS:RCX).PR 0;
(* associate the EPCPAGE with the SECS by storing the SECS identifier of DS:TMP_SECS *)
Update EPCM(DS:RCX) SECS identifier to reference DS:TMP_SECS identifier;
(* Set EPCM valid fields *)
EPCM(DS:RCX).VALID 1;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If a memory operand is locked.
If the enclave is not initialized.
#PF(error code)
If a page fault occurs in accessing memory operands.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If a memory operand is locked.
If the enclave is not initialized.
#PF(error code)
If a page fault occurs in accessing memory operands.
Vol. 3D 41-17
SGX INSTRUCTION REFERENCES
EBLOCK—Mark a page in EPC as Blocked
Opcode/
Instruction
Op/En
EAX = 09H
ENCLS[EBLOCK]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function marks a page in the EPC as blocked.
Instruction Operand Encoding
Op/En
EAX
IR
EBLOCK (In)
RCX
Return error code (Out)
Effective address of the EPC page (In)
Description
This leaf function causes an EPC page to be marked as BLOCKED. This instruction can only be executed when
current privilege level is 0.
The content of RCX is an effective address of an EPC page. The DS segment is used to create linear address.
Segment override is not supported.
An error code is returned in RAX.
The table below provides additional information on the memory parameter of EBLOCK leaf function.
EBLOCK Memory Parameter Semantics
EPCPAGE
Read/Write access permitted by Enclave
The error codes are:
Table 41-9. EBLOCK Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EBLOCK successful
SGX_BLKSTATE
Page already blocked. This value is used to indicate to a VMM that the page was already in
BLOCKED state as a result of EBLOCK and thus will need to be restored to this state when it is
eventually reloaded (using ELDB).
SGX_ENTRYEPOCH_LOCKED
SECS locked for Entry Epoch update. This value indicates that an ETRACK is
currently executing on the SECS. The EBLOCK should be reattempted.
SGX_NOTBLOCKABLE
Page type is not one which can be blocked
SGX_PG_INVLD
Page is not valid and cannot be blocked
SGX_LOCKFAIL
Page is being written by EADD, EAUG, ECREATE, ELDU/B, EMODT, or EWB
Concurrency Restrictions
Table 41-10. Concurrency Restrictions of EBLOCK with Other Intel® SGX Operations 1 of 2
Operation
EBLOCK
EEXIT
EADD
EBLOCK
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EPA
Param
TCS SSA
SECS Targ SECS
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
SECS VA
Targ
Y
Y
N
C
C
C
N
Y
C
Y
Y
C
Y
C
Y
C
Y
N
C
C
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SECS
41-18 Vol. 3D
Y
SGX INSTRUCTION REFERENCES
Table 41-11. Concurrency Restrictions of EBLOCK with Other Intel® SGX Operations 2 of 2
Operation
EBLOCK
EREMOVE
EREPORT
ETRACK
EWB
EAUG
EMODPE
EMODPR
EMODT
EACCEPT
EACCEPTCOPY
Param
Targ SECS Param SECS
SECS
SRC
VA
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Targ SEC
S
Targ SECI
NFO
SECS Targ SR
C
SECI
NFO
Targ
N
C
Y
C
C
N
C
C
N
C
Y
Y
Y
C
N
C
Y
Y
C
Y
Y
Y
SECS
Y
Y
Y
Y
U
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Operation
Temp Variables in EBLOCK Operational Flow
Name
Type
Size (Bits)
Description
TMP_BLKSTATE
Integer
64
Page is already blocked.
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
RFLAGS.ZF,CF,PF,AF,OF,SF 0;
RAX 0;
IF (EPCM(DS:RCX). VALID = 0)
THEN
RFLAGS.ZF 1;
RAX SGX_PG_INVLD;
GOTO DONE;
FI;
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) and (EPCM(DS:RCX).PT ≠ PT_TRIM) )
THEN
RFLAGS.CF 1;
IF (EPCM(DS:RCX).PT = PT_SECS)
THEN RAX SGX_PG_IS_SECS;
ELSE RAX SGX_NOTBLOCKABLE;
FI;
GOTO DONE;
FI;
(* Check if the page is already blocked and report blocked state *)
TMP_BLKSTATE EPCM(DS:RCX).BLOCKED;
(* at this point, the page must be valid and PT_TCS or PT_REG or PT_TRIM*)
IF (TMP_BLKSTATE = 1) )
THEN
RFLAGS.CF 1;
RAX SGX_BLKSTATE;
ELSE
EPCM(DS:RCX).BLOCKED 1
FI;
DONE:
Vol. 3D 41-19
SGX INSTRUCTION REFERENCES
Flags Affected
Sets ZF if SECS is in use or invalid, otherwise cleared. Sets CF if page is BLOCKED or not blockable, otherwise
cleared. Clears PF, AF, OF, SF.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If the specified EPC resource is in use.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If the specified EPC resource is in use.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
41-20 Vol. 3D
SGX INSTRUCTION REFERENCES
ECREATE—Create an SECS page in the Enclave Page Cache
Opcode/
Instruction
Op/En
EAX = 00H
ENCLS[ECREATE]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function begins an enclave build by creating an SECS
page in EPC.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
ECREATE (In)
Address of a PAGEINFO (In)
Address of the destination SECS page (In)
Description
ENCLS[ECREATE] is the first instruction executed in the enclave build process. ECREATE copies an SECS structure
outside the EPC into an SECS page inside the EPC. The internal structure of SECS is not accessible to software.
ECREATE will set up fields in the protected SECS and mark the page as valid inside the EPC. ECREATE initializes or
checks unused fields.
Software sets the following fields in the source structure: SECS:BASEADDR, SECS:SIZE in bytes, and ATTRIBUTES.
SECS:BASEADDR must be naturally aligned on an SECS.SIZE boundary. SECS.SIZE must be at least 2 pages
(8192).
The source operand RBX contains an effective address of a PAGEINFO structure. PAGEINFO contains an effective
address of a source SECS and an effective address of an SECINFO. The SECS field in PAGEINFO is not used.
The RCX register is the effective address of the destination SECS. It is an address of an empty slot in the EPC. The
SECS structure must be page aligned. SECINFO flags must specify the page as an SECS page.
ECREATE Memory Parameter Semantics
PAGEINFO
PAGEINFO.SRCPGE
PAGEINFO.SECINFO
EPCPAGE
Read access permitted by
Non Enclave
Read access permitted by
Non Enclave
Read access permitted by Non
Enclave
Write access permitted by
Enclave
ECREATE will fault if the SECS target page is in use; already valid; outside the EPC. It will also fault if addresses are
not aligned; unused PAGEINFO fields are not zero.
If the amount of space needed to store the SSA frame is greater than the amount specified in SECS.SSAFRAMESIZE, a #GP(0) results. The amount of space needed for an SSA frame is computed based on
DS:TMP_SECS.ATTRIBUTES.XFRM size. Details of computing the size can be found Section 42.7.
Concurrency Restrictions
Table 41-12. Concurrency Restrictions of ECREATE with Other Intel® SGX Operations 1 of 2
Operation
EEXIT
Param
ECREATE
TCS SSA
EADD
SECS Targ SECS
N
SECS
ECRE
ATE
EBLOCK
N
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EPA
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
SECS VA
N
N
N
N
N
N
N
N
N
N
Table 41-13. Concurrency Restrictions of ECREATE with Other Intel® SGX Operations 2 of 2
Operation
ECREATE
EREMOVE
Param
Tar
g
SECS
N
EREPORT
SECS Param SECS
ETRACK
EWB
SECS
SRC
VA
N
N
N
EAUG
EMODPE
SECS Targ SECS Targ SECI
NFO
N
N
EMODPR
EMODT
EACCEPT
EACCEPTCOPY
Targ SECS Targ SECS Targ SECI SECS Targ SR
NFO
C
N
SECI
NFO
N
Vol. 3D 41-21
SGX INSTRUCTION REFERENCES
Operation
Temp Variables in ECREATE Operational Flow
Name
Type
Size (Bits)
Description
TMP_SRCPGE
Effective Address
32/64
Effective address of the SECS source page.
TMP_SECS
Effective Address
32/64
Effective address of the SECS destination page.
TMP_SECINFO
Effective Address
32/64
Effective address of an SECINFO structure which contains security
attributes of the SECS page to be added.
TMP_XSIZE
SSA Size
64
The size calculation of SSA frame.
TMP_MISC_SIZE
MISC Field Size
64
Size of the selected MISC field components.
TMPUPDATEFIELD
SHA256 Buffer
512
Buffer used to hold data being added to TMP_SECS.MRENCLAVE.
IF (DS:RBX is not 32Byte Aligned)
THEN #GP(0); FI;
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
TMP_SRCPGE DS:RBX.SRCPGE;
TMP_SECINFO DS:RBX.SECINFO;
IF (DS:TMP_SRCPGE is not 4KByte aligned or DS:TMP_SECINFO is not 64Byte aligned)
THEN #GP(0); FI;
IF (DS:RBX.LINADDR ! = 0 or DS:RBX.SECS ≠ 0)
THEN #GP(0); FI;
(* Check for misconfigured SECINFO flags*)
IF (DS:TMP_SECINFO reserved fields are not zero or DS:TMP_SECINFO.FLAGS.PT ≠ PT_SECS) )
THEN #GP(0); FI;
TMP_SECS RCX;
IF (EPC entry in use)
THEN #GP(0); FI;
IF (EPCM(DS:RCX).VALID = 1)
THEN #PF(DS:RCX); FI;
(* Copy 4KBytes from source page to EPC page*)
DS:RCX[32767:0] DS:TMP_SRCPGE[32767:0];
(* Check lower 2 bits of XFRM are set *)
IF ( ( DS:TMP_SECS.ATTRIBUTES.XFRM BitwiseAND 03H) ≠ 03H)
THEN #GP(0); FI;
IF (XFRM is illegal)
41-22 Vol. 3D
SGX INSTRUCTION REFERENCES
THEN #GP(0); FI;
(* Make sure that the SECS does not have any unsupported MISCSELECT options*)
IF ( !(CPUID.(EAX=12H, ECX=0):EBX[31:0] & DS:TMP_SECS.MISSELECT[31:0]) )
THEN
EPCM(DS:TMP_SECS).EntryLock.Release();
#GP(0);
FI;
( * Compute size of MISC area *)
TMP_MISC_SIZE compute_misc_region_size();
(* Compute the size required to save state of the enclave on async exit, see Section 42.7.2.2*)
TMP_XSIZE compute_xsave_size(DS:TMP_SECS.ATTRIBUTES.XFRM) + GPR_SIZE + TMP_MISC_SIZE;
(* Ensure that the declared area is large enough to hold XSAVE and GPR stat *)
IF ( ( DS:TMP_SECS.SSAFRAMESIZE*4096 < TMP_XSIZE)
THEN #GP(0); FI;
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1) and (DS:TMP_SECS.BASEADDR is not canonical) )
THEN #GP(0); FI;
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0) and (DS:TMP_SECS.BASEADDR and 0FFFFFFFF00000000H) )
THEN #GP(0); FI;
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0) and (DS:TMP_SECS.SIZE ≥ 2 ^ (CPUID.(EAX=12H, ECX=0):.EDX[7:0]) ) )
THEN #GP(0); FI;
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1) and (DS:TMP_SECS.SIZE ≥ 2 ^ (CPUID.(EAX=12H, ECX=0):.EDX[15:8]) ) )
THEN #GP(0); FI;
(* Enclave size must be at least 8192 bytes and must be power of 2 in bytes*)
IF (DS:TMP_SECS.SIZE < 8192 or popcnt(DS:TMP_SECS.SIZE) > 1)
THEN #GP(0); FI;
(* Ensure base address of an enclave is aligned on size*)
IF ( ( DS:TMP_SECS.BASEADDR and (DS:TMP_SECS.SIZE-1) )
THEN #GP(0); FI;
* Ensure the SECS does not have any unsupported attributes*)
IF ( ( DS:TMP_SECS.ATTRIBUTES and (~CR_SGX_ATTRIBUTES_MASK) )
THEN #GP(0); FI;
IF ( ( DS:TMP_SECS reserved fields are not zero)
THEN #GP(0); FI;
Clear DS:TMP_SECS to Uninitialized;
DS:TMP_SECS.MRENCLAVE SHA256INITIALIZE(DS:TMP_SECS.MRENCLAVE);
DS:TMP_SECS.ISVSVN 0;
DS:TMP_SECS.ISVPRODID 0;
(* Initialize hash updates etc*)
Initialize enclave’s MRENCLAVE update counter;
Vol. 3D 41-23
SGX INSTRUCTION REFERENCES
(* Add “ECREATE” string and SECS fields to MRENCLAVE *)
TMPUPDATEFIELD[63:0] 0045544145524345H; // “ECREATE”
TMPUPDATEFIELD[95:64] DS:TMP_SECS.SSAFRAMESIZE;
TMPUPDATEFIELD[159:96] DS:TMP_SECS.SIZE;
TMPUPDATEFIELD[511:160] 0;
SHA256UPDATE(DS:TMP_SECS.MRENCLAVE, TMPUPDATEFIELD)
INC enclave’s MRENCLAVE update counter;
(* Set EID *)
DS:TMP_SECS.EID LockedXAdd(CR_NEXT_EID, 1);
(* Set the EPCM entry, first create SECS identifier and store the identifier in EPCM *)
EPCM(DS:TMP_SECS).PT PT_SECS;
EPCM(DS:TMP_SECS).ENCLAVEADDRESS 0;
EPCM(DS:TMP_SECS).R 0;
EPCM(DS:TMP_SECS).W 0;
EPCM(DS:TMP_SECS).X 0;
(* Set EPCM entry fields *)
EPCM(DS:RCX).BLOCKED 0;
EPCM(DS:RCX).PENDING 0;
EPCM(DS:RCX).MODIFIED 0;
EPCM(DS:RCX).PR 0;
EPCM(DS:RCX).VALID 1;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If the reserved fields are not zero.
If PAGEINFO.SECS is not zero.
If PAGEINFO.LINADDR is not zero.
If the SECS destination is locked.
If SECS.SSAFRAMESIZE is insufficient.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the SECS destination is outside the EPC.
64-Bit Mode Exceptions
#GP(0)
If a memory address is non-canonical form.
If a memory operand is not properly aligned.
If the reserved fields are not zero.
If PAGEINFO.SECS is not zero.
If PAGEINFO.LINADDR is not zero.
If the SECS destination is locked.
If SECS.SSAFRAMESIZE is insufficient.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the SECS destination is outside the EPC.
41-24 Vol. 3D
SGX INSTRUCTION REFERENCES
EDBGRD—Read From a Debug Enclave
Opcode/
Instruction
Op/En
EAX = 04H
ENCLS[EDBGRD]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function reads a dword/quadword from a debug enclave.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EDBGRD (In)
Data read from a debug enclave (Out)
Address of source memory in the EPC (In)
Description
This leaf function copies a quadword/doubleword from an EPC page belonging to a debug enclave into the RBX
register. Eight bytes are read in 64-bit mode, four bytes are read in non-64-bit modes. The size of data read cannot
be overridden.
The effective address of the source location inside the EPC is provided in the register RCX.
EDBGRD Memory Parameter Semantics
EPCQW
Read access permitted by Enclave
The error codes are:
Table 41-14. EDBGRD Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EDBGRD successful
SGX_PAGE_NOT_DEBUGGABLE
The EPC page cannot be accessed because it is in the PENDING or MODIFIED state
The instruction faults if any of the following:
EDBGRD Faulting Conditions
RCX points into a page that is an SECS.
RCX does not resolve to a naturally aligned linear address.
RCX points to a page that does not belong to an
enclave that is in debug mode.
RCX points to a location inside a TCS that is beyond the architectural size of the
TCS (SGX_TCS_LIMIT).
An operand causing any segment violation.
May page fault.
CPL > 0.
This instruction ignores the EPCM RWX attributes on the enclave page. Consequently, violation of EPCM RWX attributes via EDGBRD does not result in a #GP.
Vol. 3D 41-25
SGX INSTRUCTION REFERENCES
Concurrency Restrictions
Table 41-15. Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 1 of 2
Operation
EDBGRD
EEXIT
Param
TCS SSA
Targ
Y
EADD
EBLOCK
SECS Targ SECS
N
Y
SECS
Y
Y
Y
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
Y
N
Y
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EPA
SECS VA
N
Y
Y
Table 41-16. Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 2 of 2
Operation
EDBGRD
EREMOVE
EREPORT
Param
Targ SECS Param SECS
Targ
N
SECS
Y
Y
Y
Y
Y
ETRACK
EWB
SECS
SRC
VA
N
N
Y
Y
Y
Y
EAUG
EMODPE
EMODPR
SECS Targ SECS Targ SECI Targ SEC
NFO
S
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
EMODT
Targ SEC
S
EACCEPT
Targ SECI
NFO
N
Y
Y
EACCEPTCOPY
SECS Targ SR
C
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Operation
Temp Variables in EDBGRD Operational Flow
Name
Type
Size (Bits)
Description
TMP_MODE64
Binary
1
((IA32_EFER.LMA = 1) && (CS.L = 1))
64
Physical address of SECS of the enclave to which source operand belongs
TMP_SECS
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
IF ( (TMP_MODE64 = 1) and (DS:RCX is not 8Byte Aligned) )
THEN #GP(0); FI;
IF ( (TMP_MODE64 = 0) and (DS:RCX is not 4Byte Aligned) )
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
(* make sure no other Intel SGX instruction is accessing EPCM *)
IF (Other EPCM modifying instructions executing)
THEN #GP(0); FI;
IF (EPCM(DS:RCX). VALID = 0)
THEN #PF(DS:RCX); FI;
(* make sure that DS:RCX (SOURCE) is pointing to a PT_REG or PT_TCS or PT_VA *)
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) and (EPCM(DS:RCX).PT ≠ PT_VA))
THEN #PF(DS:RCX); FI;
(* If source is a TCS, then make sure that the offset into the page is not beyond the TCS size*)
IF ( ( EPCM(DS:RCX). PT = PT_TCS) and ((DS:RCX) & FFFH ≥ SGX_TCS_LIMIT) )
THEN #GP(0); FI;
41-26 Vol. 3D
SECI
NFO
SGX INSTRUCTION REFERENCES
(* make sure the enclave owning the PT_REG or PT_TCS page allow debug *)
IF ( (EPCM(DS:RCX).PT = PT_REG) or (EPCM(DS:RCX).PT = PT_TCS) )
THEN
TMP_SECS GET_SECS_ADDRESS;
IF (TMP_SECS.ATTRIBUTES.DEBUG = 0)
THEN #GP(0); FI;
IF ( (TMP_MODE64 = 1) )
THEN RBX[63:0] (DS:RCX)[63:0];
ELSE EBX[31:0] (DS:RCX)[31:0];
FI;
ELSE
TMP_64BIT_VAL[63:0] (DS:RCX)[63:0] & (~07H); // Read contents from VA slot
IF (TMP_MODE64 = 1)
THEN
IF (TMP_64BIT_VAL ≠ 0H)
THEN RBX[63:0] 0FFFFFFFFFFFFFFFFH;
ELSE RBX[63:0] 0H;
FI;
ELSE
IF (TMP_64BIT_VAL ≠ 0H)
THEN EBX[31:0] 0FFFFFFFFH;
ELSE EBX[31:0] 0H;
FI;
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the address in RCS violates DS limit or access rights.
If DS segment is unusable.
If RCX points to a memory location not 4Byte-aligned.
If the address in RCX points to a page belonging to a non-debug enclave.
If the address in RCX points to a page which is not PT_TCS, PT_REG or PT_VA.
If the address in RCX points to a location inside TCS that is beyond SGX_TCS_LIMIT.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the address in RCX points to a non-EPC page.
If the address in RCX points to an invalid EPC page.
64-Bit Mode Exceptions
#GP(0)
If RCX is non-canonical form.
If RCX points to a memory location not 8Byte-aligned.
If the address in RCX points to a page belonging to a non-debug enclave.
If the address in RCX points to a page which is not PT_TCS, PT_REG or PT_VA.
If the address in RCX points to a location inside TCS that is beyond SGX_TCS_LIMIT.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the address in RCX points to a non-EPC page.
If the address in RCX points to an invalid EPC page.
Vol. 3D 41-27
SGX INSTRUCTION REFERENCES
EDBGWR—Write to a Debug Enclave
Opcode/
Instruction
Op/En
EAX = 05H
ENCLS[EDBGWR]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function writes a dword/quadword to a debug enclave.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EDBGWR (In)
Data to be written to a debug enclave (In)
Address of Target memory in the EPC (In)
Description
This leaf function copies the content in EBX/RBX to an EPC page belonging to a debug enclave. Eight bytes are
written in 64-bit mode, four bytes are written in non-64-bit modes. The size of data cannot be overridden.
The effective address of the source location inside the EPC is provided in the register RCX
EDBGWR Memory Parameter Semantics
EPCQW
Write access permitted by Enclave
The instruction faults if any of the following:
EDBGWR Faulting Conditions
RCX points into a page that is an SECS.
RCX does not resolve to a naturally aligned linear address.
RCX points to a page that does not belong to an
enclave that is in debug mode.
RCX points to a location inside a TCS that is not the FLAGS word.
An operand causing any segment violation.
May page fault.
CPL > 0.
The error codes are:
Table 41-17. EDBGWR Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EDBGWR successful
SGX_PAGE_NOT_DEBUGGABLE
The EPC page cannot be accessed because it is in the PENDING or MODIFIED
state
This instruction ignores the EPCM RWX attributes on the enclave page. Consequently, violation of EPCM RWX attributes via EDGBRD does not result in a #GP.
41-28 Vol. 3D
SGX INSTRUCTION REFERENCES
Concurrency Restrictions
Table 41-18. Concurrency Restrictions of EDBGWR with Other Intel® SGX Operations 1 of 2
Operation
EDBGWR
EEXIT
Param
TCS SSA
Targ
Y
EADD
EBLOCK
SECS Targ SECS
N
Y
SECS
Y
Y
Y
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
Y
N
Y
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EPA
SECS VA
N
Y
Y
Table 41-19. Concurrency Restrictions of EDBGWR with Other Intel® SGX Operations 2 of 2
Operation
EDBGWR
EREMOVE
EREPORT
Param
Targ SECS Param SECS
Targ
N
SECS
Y
Y
Y
Y
Y
ETRACK
EWB
SECS
SRC
VA
N
N
Y
Y
Y
Y
EAUG
EMODPE
EMODPR
SECS Targ SECS Targ SECI Targ SEC
NFO
S
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
EMODT
Targ SEC
S
EACCEPT
Targ SECI
NFO
N
Y
Y
EACCEPTCOPY
SECS Targ SR
C
Y
Y
Y
Y
Y
Y
SECI
NFO
Y
Y
Y
Y
Operation
Temp Variables in EDBGWR Operational Flow
Name
Type
Size (Bits)
Description
TMP_MODE64
Binary
1
((IA32_EFER.LMA = 1) && (CS.L = 1)).
64
Physical address of SECS of the enclave to which source operand belongs.
TMP_SECS
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
IF ( (TMP_MODE64 = 1) and (DS:RCX is not 8Byte Aligned) )
THEN #GP(0); FI;
IF ( (TMP_MODE64 = 0) and (DS:RCX is not 4Byte Aligned) )
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
(* make sure no other Intel SGX instruction is accessing EPCM *)
IF (Other EPCM modifying instructions executing)
THEN #GP(0); FI;
IF (EPCM(DS:RCX). VALID = 0)
THEN #PF(DS:RCX); FI;
(* make sure that DS:RCX (DST) is pointing to a PT_REG or PT_TCS *)
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) )
THEN #PF(DS:RCX); FI;
(* If destination is a TCS, then make sure that the offset into the page can only point to the FLAGS field*)
IF ( ( EPCM(DS:RCX). PT = PT_TCS) and ((DS:RCX) & FF8H ≠ offset_of_FLAGS & 0FF8H) )
THEN #GP(0); FI;
(* Locate the SECS for the enclave to which the DS:RCX page belongs *)
TMP_SECS GET_SECS_PHYS_ADDRESS(EPCM(DS:RCX).ENCLAVESCES);
Vol. 3D 41-29
SGX INSTRUCTION REFERENCES
(* make sure the enclave owning the PT_REG or PT_TCS page allow debug *)
IF (TMP_SECS.ATTRIBUTES.DEBUG = 0)
THEN #GP(0); FI;
IF ( (TMP_MODE64 = 1) )
THEN (DS:RCX)[63:0] RBX[63:0];
ELSE (DS:RCX)[31:0] EBX[31:0];
FI;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the address in RCS violates DS limit or access rights.
If DS segment is unusable.
If RCX points to a memory location not 4Byte-aligned.
If the address in RCX points to a page belonging to a non-debug enclave.
If the address in RCX points to a page which is not PT_TCS or PT_REG.
If the address in RCX points to a location inside TCS that is not the FLAGS word.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the address in RCX points to a non-EPC page.
If the address in RCX points to an invalid EPC page.
64-Bit Mode Exceptions
#GP(0)
If RCX is non-canonical form.
If RCX points to a memory location not 8Byte-aligned.
If the address in RCX points to a page belonging to a non-debug enclave.
If the address in RCX points to a page which is not PT_TCS or PT_REG.
If the address in RCX points to a location inside TCS that is not the FLAGS word.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the address in RCX points to a non-EPC page.
If the address in RCX points to an invalid EPC page.
41-30 Vol. 3D
SGX INSTRUCTION REFERENCES
EEXTEND—Extend Uninitialized Enclave Measurement by 256 Bytes
Opcode/
Instruction
Op/En
EAX = 06H
ENCLS[EEXTEND]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function measures 256 bytes of an uninitialized enclave
page.
Instruction Operand Encoding
Op/En
EAX
EBX
RCX
IR
EEXTEND (In)
Effective address of the SECS of the
data chunk (In)
Effective address of a 256-byte chunk in the EPC (In)
Description
This leaf function updates the MRENCLAVE measurement register of an SECS with the measurement of an EXTEND
string compromising of “EEXTEND” || ENCLAVEOFFSET || PADDING || 256 bytes of the enclave page. This instruction can only be executed when current privilege level is 0 and the enclave is uninitialized.
RBX contains the effective address of the SECS of the region to be measured. The address must be the same as the
one used to add the page into the enclave.
RCX contains the effective address of the 256 byte region of an EPC page to be measured. The DS segment is used
to create linear addresses. Segment override is not supported.
EEXTEND Memory Parameter Semantics
EPC[RCX]
Read access by Enclave
The instruction faults if any of the following:
EEXTEND Faulting Conditions
RBX points to an address not 4KBytes aligned.
RBX does not resolve to an SECS.
RBX does not point to an SECS page.
RBX does not point to the SECS page of the data chunk.
RCX points and address not 256B aligned.
RCX points to an unused page or a SECS.
RCX does not resolve in an EPC page.
If SECS is locked.
If the SECS is already initialized.
May page fault.
CPL > 0.
Concurrency Restrictions
Table 41-20. Concurrency Restrictions of EEXTEND with Other Intel® SGX Operations 1 of 2
Operation
Param
EEXTEND
EEXIT
TCS SSA
Targ
N
N
SECS
Y
Y
EADD
SECS Targ SECS
N
Y
Y
N
EBLOCK
ECRE
ATE
EDBGRD/
WR
Targ SECS
SECS
Targ SECS
Y
N
Y
Y
Y
Y
Y
EENTER/
ERESUME
EEXTEND
EGETKEY
TCS SSA SECS Targ SECS Param SECS
Y
Y
Y
Y
N
Y
N
Y
N
EINIT
ELDB/ELDU
SECS
Targ VA
N
N
N
Y
EPA
SECS VA
N
Y
Y
Y
Vol. 3D 41-31
SGX INSTRUCTION REFERENCES
Table 41-21. Concurrency Restrictions of EEXTEND with Other Intel® SGX Operations 2 of 2
Operation
Param
EEXTEND
EREMOVE
EREPORT
Targ SECS Param SECS
Targ
N
SECS
Y
ETRACK
SECS
EWB
SRC
EAUG
Y
N
Y
Y
EMODPR
VA
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Y
Y
N
Y
EMODPE
N
Y
N
N
Y
Y
Y
EMODT
Targ SEC
S
EACCEPT
EACCEPTCOPY
Targ SECI
NFO
SECS Targ SR
C
SECI
NFO
Y
N
Y
N
N
Y
N
Y
Y
Y
Operation
Temp Variables in EEXTEND Operational Flow
Name
Type
TMP_SECS
Size (Bits)
Description
64
Physical address of SECS of the enclave to which source operand belongs.
TMP_ENCLAVEOFFS
ET
Enclave Offset
64
The page displacement from the enclave base address.
TMPUPDATEFIELD
SHA256 Buffer
512
Buffer used to hold data being added to TMP_SECS.MRENCLAVE.
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
IF (DS:RBX does resolve to an EPC page)
THEN #PF(DS:RBX); FI;
IF (DS:RCX is not 256Byte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
(* make sure no other Intel SGX instruction is accessing EPCM *)
IF (Other instructions accessing EPCM)
THEN #GP(0); FI;
IF (EPCM(DS:RCX). VALID = 0)
THEN #PF(DS:RCX); FI;
(* make sure that DS:RCX (DST) is pointing to a PT_REG or PT_TCS *)
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) )
THEN #PF(DS:RCX); FI;
TMP_SECS Get_SECS_ADDRESS();
IF (DS:RBX does not resolve to TMP_SECS)
THEN #GP(0); FI;
(* make sure no other instruction is accessing MRENCLAVE or ATTRIBUETS.INIT *)
IF ( (Other instruction accessing MRENCLAVE) or (Other instructions checking or updating the initialized state of the SECS))
THEN #GP(0); FI;
(* Calculate enclave offset *)
TMP_ENCLAVEOFFSET EPCM(DS:RCX).ENCLAVEADDRESS - TMP_SECS.BASEADDR;
TMP_ENCLAVEOFFSET TMP_ENCLAVEOFFSET + (DS:RCX & 0FFFH)
41-32 Vol. 3D
SGX INSTRUCTION REFERENCES
(* Add EEXTEND message and offset to MRENCLAVE *)
TMPUPDATEFIELD[63:0] 00444E4554584545H; // “EEXTEND”
TMPUPDATEFIELD[127:64] TMP_ENCLAVEOFFSET;
TMPUPDATEFIELD[511:128] 0; // 48 bytes
TMP_SECS.MRENCLAVE SHA256UPDATE(TMP_SECS.MRENCLAVE, TMPUPDATEFIELD)
INC enclave’s MRENCLAVE update counter;
(*Add 256 bytes to MRENCLAVE, 64 byte at a time *)
TMP_SECS.MRENCLAVE SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[511:0] );
TMP_SECS.MRENCLAVE SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[1023: 512] );
TMP_SECS.MRENCLAVE SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[1535: 1024] );
TMP_SECS.MRENCLAVE SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[2047: 1536] );
INC enclave’s MRENCLAVE update counter by 4;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the address in RBX is outside the DS segment limit.
If RBX points to an SECS page which is not the SECS of the data chunk.
If the address in RCX is outside the DS segment limit.
If RCX points to a memory location not 256Byte-aligned.
If another instruction is accessing MRENCLAVE.
If another instruction is checking or updating the SECS.
If the enclave is already initialized.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the address in RBX points to a non-EPC page.
If the address in RCX points to a page which is not PT_TCS or PT_REG.
If the address in RCX points to a non-EPC page.
If the address in RCX points to an invalid EPC page.
64-Bit Mode Exceptions
#GP(0)
If RBX is non-canonical form.
If RBX points to an SECS page which is not the SECS of the data chunk.
If RCX is non-canonical form.
If RCX points to a memory location not 256 Byte-aligned.
If another instruction is accessing MRENCLAVE.
If another instruction is checking or updating the SECS.
If the enclave is already initialized.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the address in RBX points to a non-EPC page.
If the address in RCX points to a page which is not PT_TCS or PT_REG.
If the address in RCX points to a non-EPC page.
If the address in RCX points to an invalid EPC page.
Vol. 3D 41-33
SGX INSTRUCTION REFERENCES
EINIT—Initialize an Enclave for Execution
Opcode/
Instruction
Op/En
EAX = 02H
ENCLS[EINIT]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function initializes the enclave and makes it ready to
execute enclave code.
Instruction Operand Encoding
Op/En
IR
EAX
EINIT (In)
Error code (Out)
RBX
RCX
RDX
Address of SIGSTRUCT (In)
Address of SECS (In)
Address of EINITTOKEN (In)
Description
This leaf function is the final instruction executed in the enclave build process. After EINIT, the MRENCLAVE
measurement is complete, and the enclave is ready to start user code execution using the EENTER instruction.
EINIT takes the effective address of a SIGSTRUCT and EINITTOKEN. The SIGSTRUCT describes the enclave
including MRENCLAVE, ATTRIBUTES, ISVSVN, a 3072 bit RSA key, and a signature using the included key.
SIGSTRUCT must be populated with two values, q1 and q2. These are calculated using the formulas shown below:
q1 = floor(Signature2 / Modulus);
q2 = floor((Signature3 - q1 * Signature * Modulus) / Modulus);
The EINITTOKEN contains the MRENCLAVE, MRSIGNER, and ATTRIBUTES. These values must match the corresponding values in the SECS. If the EINITTOKEN was created with a debug launch key, the enclave must be in
debug mode as well.
Verify
Signature
Hashed
PubKey
ATTRIBUTES
ATTRIBUTEMASK
MRENCLAVE
Check
MRSIGNER
SIGSTRUCT
DS:RBX
DS:RDX
ATTRIBUTES
MRENCLAVE
If VALID=1, Check
MRSIGNER
If VALID=1,
Check
EINITTOKEN
EINIT
Copy
DS:RCX
SECS
Check
ATTRIBUTES
MRENCLAVE
ENCLAVE
EPC
Figure 41-1. Relationships Between SECS, SIGSTRUCT and EINITTOKEN
41-34 Vol. 3D
SGX INSTRUCTION REFERENCES
EINIT Memory Parameter Semantics
SIGSTRUCT
SECS
EINITTOKEN
Access by non-Enclave
Read/Write access by Enclave
Access by non-Enclave
EINIT performs the following steps, which can be seen in Figure 41-1:
Validates that SIGSTRUCT is signed using the enclosed public key.
Checks that the completed computation of SECS.MRENCLAVE equals SIGSTRUCT.HASHENCLAVE.
Checks that no reserved bits are set to 1 in SIGSTRUCT.ATTRIBUTES and no reserved bits in SIGSTRUCT.ATTRIBUTESMASK are set to 0.
Checks that no controlled ATTRIBUTES bits are set in SIGSTRUCT.ATTRIBUTES unless the SHA256 digest of
SIGSTRUCT.MODULUS equals IA32_SGX_LEPUBKEYHASH.
Checks that SIGSTRUCT.ATTRIBUTES equals the result of logically and-ing SIGSTRUCT.ATTRIBUTEMASK with
SECS.ATTRIBUTES.
If EINITTOKEN.VALID is 0, checks that the SHA256 digest of SIGSTRUCT.MODULUS equals
IA32_SGX_LEPUBKEYHASH.
If EINITTOKEN.VALID is 1, checks the validity of EINITTOKEN.
If EINITTOKEN.VALID is 1, checks that EINITTOKEN.MRENCLAVE equals SECS.MRENCLAVE.
If EINITTOKEN.VALID is 1 and EINITTOKEN.ATTRIBUTES.DEBUG is 1, SECS.ATTRIBUTES.DEBUG must be 1.
Commits SECS.MRENCLAVE, and sets SECS.MRSIGNER, SECS.ISVSVN, and SECS.ISVPRODID based on
SIGSTRUCT.
Update the SECS as Initialized.
Periodically, EINIT polls for certain asynchronous events. If such an event is detected, it completes with failure
code (ZF=1 and RAX = SGX_UNMASKED_EVENT), and RIP is incremented to point to the next instruction. These
events includes external interrupts, non-maskable interrupts, system-management interrupts, machine checks,
INIT signals, and the VMX-preemption timer. EINIT does not fail if the pending event is inhibited (e.g., external
interrupts could be inhibited due to blocking by MOV SS blocking or by STI).
The following bits in RFLAGS are cleared: CF, PF, AF, OF, and SF. When the instruction completes with an error,
RFLAGS.ZF is set to 1, and the corresponding error bit is set in RAX. If no error occurs, RFLAGS.ZF is cleared and
RAX is set to 0.
The error codes are:
Table 41-22. EINIT Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EINIT successful
SGX_INVALID_SIG_STRUCT
If SIGSTRUCT contained an invalid value
SGX_INVALID_ATTRIBUTE
If SIGSTRUCT contains an unauthorized attributes mask
SGX_INVALID_MEASUREMENT
If SIGSTRUCT contains an incorrect measurement
If EINITTOKEN contains an incorrect measurement
SGX_INVALID_SIGNATURE
If signature does not validate with enclosed public key
SGX_INVALID_LICENSE
If license is invalid
SGX_INVALID_CPUSVN
If license SVN is unsupported
SGX_UNMASKED_EVENT
If an unmasked event is received before the instruction completes its
operation
Vol. 3D 41-35
SGX INSTRUCTION REFERENCES
Concurrency Restrictions
Table 41-23. Concurrency Restrictions of EINIT with Other Intel® SGX Operations 1 of 2
Operation
Param
EINIT
EEXIT
TCS SSA
SECS
EADD
EBLOCK
ECRE
ATE
EDBGRD/
WR
SECS Targ SECS
Targ SECS
SECS
Targ SECS
N
Y
N
N
N
N
Y
EENTER/
ERESUME
EEXTEND
EGETKEY
TCS SSA SECS Targ SECS Param SECS
Y
N
N
N
N
EINIT
ELDB/ELDU
EPA
SECS
Targ VA
SECS VA
N
N
Y
N
Table 41-24. Concurrency Restrictions of EINIT with Other Intel® SGX Operations 2 of 2
Operation
EINIT
EREMOVE
EREPORT
Param
Targ SECS Param SECS
SECS
N
N
Y
ETRACK
EWB
SECS
SRC
Y
N
VA
EAUG
EMODPE
SECS Targ SECS Targ SECI
NFO
Y
N
EMODPR
EMODT
EACCEPT
EACCEPTCOPY
Targ SECS Targ SECS Targ SECI SECS Targ SR
NFO
C
N
N
N
N
SECI
NFO
N
Operation
Temp Variables in EINIT Operational Flow
Name
Type
Size
Description
TMP_SIG
SIGSTRUCT
1808Bytes
Temp space for SIGSTRUCT.
TMP_TOKEN
EINITTOKEN
304Bytes
Temp space for EINITTOKEN.
TMP_MRENCLAVE
32Bytes
Temp space for calculating MRENCLAVE.
TMP_MRSIGNER
32Bytes
Temp space for calculating MRSIGNER.
CONTROLLED_ATTRIBU
TES
ATTRIBUTES
16Bytes
Constant mask of all ATTRIBUTE bits that can only be set for authorized
enclaves.
TMP_KEYDEPENDENCIE
S
Buffer
224Bytes
Temp space for key derivation.
16Bytes
Temp space for the derived EINITTOKEN Key.
352Bytes
The value of the top 352 bytes from the computation of Signature3
modulo MRSIGNER.
TMP_EINITTOKENKEY
TMP_SIG_PADDING
PKCS Padding
Buffer
(* make sure SIGSTRUCT and SECS are aligned *)
IF ( (DS:RBX is not 4KByte Aligned) or (DS:RCX is not 4KByte Aligned) )
THEN #GP(0); FI;
(* make sure the EINITTOKEN is aligned *)
IF (DS:RDX is not 512Byte Aligned)
THEN #GP(0); FI;
(* make sure the SECS is inside the EPC *)
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
TMP_SIG[14463:0] DS:RBX[14463:0]; // 1808 bytes
TMP_TOKEN[2423:0] DS:RDX[2423:0]; // 304 bytes
(* Verify SIGSTRUCT Header. *)
IF ( (TMP_SIG.HEADER ≠ 06000000E10000000000010000000000h) or
((TMP_SIG.VENDOR ≠ 0) and (TMP_SIG.VENDOR ≠ 00008086h) ) or
(TMP_SIG HEADER2 ≠ 01010000600000006000000001000000h) or
41-36 Vol. 3D
SGX INSTRUCTION REFERENCES
(TMP_SIG.EXPONENT ≠ 00000003h) or (Reserved space is not 0’s) )
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_SIG_STRUCT;
GOTO EXIT;
FI;
(* Open “Event Window” Check for Interrupts. Verify signature using embedded public key, q1, and q2. Save upper 352 bytes of the
PKCS1.5 encoded message into the TMP_SIG_PADDING*)
IF (interrupt was pending) {
RFLAG.ZF 1;
RAX SGX_UNMASKED_EVENT;
GOTO EXIT;
FI
IF (signature failed to verify) {
RFLAG.ZF 1;
RAX SGX_INVALID_SIGNATURE;
GOTO EXIT;
FI;
(*Close “Event Window” *)
(* make sure no other Intel SGX instruction is modifying SECS*)
IF (Other instructions modifying SECS)
THEN #GP(0); FI;
IF ( (EPCM(DS:RCX). VALID = 0) or (EPCM(DS:RCX).PT ≠ PT_SECS) )
THEN #PF(DS:RCX); FI;
(* make sure no other instruction is accessing MRENCLAVE or ATTRIBUETS.INIT *)
IF ( (Other instruction modifying MRENCLAVE) or (Other instructions modifying the SECS’s Initialized state))
THEN #GP(0); FI;
(* Calculate finalized version of MRENCLAVE *)
(* SHA256 algorithm requires one last update that compresses the length of the hashed message into the output SHA256 digest *)
TMP_ENCLAVE SHA256FINAL( (DS:RCX).MRENCLAVE, enclave’s MRENCLAVE update count *512);
(* Verify MRENCLAVE from SIGSTRUCT *)
IF (TMP_SIG.ENCLAVEHASH ≠ TMP_MRENCLAVE)
RFLAG.ZF 1;
RAX SGX_INVALID_MEASUREMENT;
GOTO EXIT;
FI;
TMP_MRSIGNER SHA256(TMP_SIG.MODULUS)
(* if controlled ATTRIBUTES are set, SIGSTRUCT must be signed using an authorized key *)
CONTROLLED_ATTRIBUTES 0000000000000020H;
IF ( ( (DS:RCX.ATTRIBUTES & CONTROLLED_ATTRIBUTES) ≠ 0) and (TMP_MRSIGNER ≠ IA32_SGXLEPUBKEYHASH) )
RFLAG.ZF 1;
RAX SGX_INVALID_ATTRIBUTE;
GOTO EXIT;
FI;
(* Verify SIGSTRUCT.ATTRIBUTE requirements are met *)
Vol. 3D 41-37
SGX INSTRUCTION REFERENCES
IF ( (DS:RCX.ATTRIBUTES & TMP_SIG.ATTRIBUTEMASK) ≠ (TMP_SIG.ATTRIBUTE & TMP_SIG.ATTRIBUTEMASK) )
RFLAG.ZF 1;
RAX SGX_INVALID_ATTRIBUTE;
GOTO EXIT;
FI;
( *Verify SIGSTRUCT.MISCSELECT requirements are met *)
IF ( (DS:RCX.MISCSELECT & TMP_SIG.MISCMASK) ≠ (TMP_SIG.MISCSELECT & TMP_SIG.MISCMASK) )
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ATTRIBUTE;
GOTO EXIT
FI;
(* if EINITTOKEN.VALID[0] is 0, verify the enclave is signed by an authorized key *)
IF (TMP_TOKEN.VALID[0] = 0)
IF (TMP_MRSIGNER ≠ IA32_SGXLEPUBKEYHASH)
RFLAG.ZF 1;
RAX SGX_INVALID_EINITTOKEN;
GOTO EXIT;
FI;
GOTO COMMIT;
FI;
(* Debug Launch Enclave cannot launch Production Enclaves *)
IF ( (DS:RDX.MASKEDATTRIBUTESLE.DEBUG = 1) and (DS:RCX.ATTRIBUTES.DEBUG = 0) )
RFLAG.ZF 1;
RAX SGX_INVALID_EINITTOKEN;
GOTO EXIT;
FI;
(* Check reserve space in EINIT token includes reserved regions and upper bits in valid field *)
IF (TMP_TOKEN reserved space is not clear)
RFLAG.ZF 1;
RAX SGX_INVALID_EINITTOKEN;
GOTO EXIT;
FI;
(* EINIT token must be ≤ CR_CPUSVN *)
IF (TMP_TOKEN.CPUSVN > CR_CPUSVN)
RFLAG.ZF 1;
RAX SGX_INVALID_CPUSVN;
GOTO EXIT;
FI;
(* Derive Launch key used to calculate EINITTOKEN.MAC *)
HARDCODED_PKCS1_5_PADDING[15:0] 0100H;
HARDCODED_PKCS1_5_PADDING[2655:16] SignExtend330Byte(-1); // 330 bytes of 0FFH
HARDCODED_PKCS1_5_PADDING[2815:2656] 2004000501020403650148866009060D30313000H;
TMP_KEYDEPENDENCIES.KEYNAME EINITTOKEN_KEY;
TMP_KEYDEPENDENCIES.ISVPRODID TMP_TOKEN.ISVPRODIDLE;
TMP_KEYDEPENDENCIES.ISVSVN TMP_TOKEN.ISVSVN;
TMP_KEYDEPENDENCIES.OWNEREPOCH CSR_SGXOWNEREPOCH;
41-38 Vol. 3D
SGX INSTRUCTION REFERENCES
TMP_KEYDEPENDENCIES.ATTRIBUTES TMP_TOKEN.MASKEDATTRIBUTESLE;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK 0;
TMP_KEYDEPENDENCIES.MRENCLAVE 0;
TMP_KEYDEPENDENCIES.MRSIGNER IA32_SGXLEPUBKEYHASH;
TMP_KEYDEPENDENCIES.KEYID TMP_TOKEN.KEYID;
TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES CR_SEAL_FUSES;
TMP_KEYDEPENDENCIES.CPUSVN TMP_TOKEN.CPUSVN;
TMP_KEYDEPENDENCIES.MISCSELECT TMP_TOKEN.MASKEDMISCSELECTLE;
TMP_KEYDEPENDENCIES.MISCMASK 0;
TMP_KEYDEPENDENCIES.PADDING HARDCODED_PKCS1_5_PADDING;
(* Calculate the derived key*)
TMP_EINITTOKENKEY derivekey(TMP_KEYDEPENDENCIES);
(* Verify EINITTOKEN was generated using this CPU's Launch key and that it has not been modified since issuing by the Launch
Enclave. Only 192 bytes of EINITOKEN are CMACed *)
IF (TMP_TOKEN.MAC ≠ CMAC(TMP_EINITTOKENKEY, TMP_TOKEN[1535:0] ) )
RFLAG.ZF 1;
RAX SGX_INVALID_EINIT_TOKEN;
GOTO EXIT;
FI;
(* Verify EINITTOKEN (RDX) is for this enclave *)
IF (TMP_TOKEN.MRENCLAVE ≠ TMP_MRENCLAVE) or (TMP_TOKEN.MRSIGNER ≠ TMP_MRSIGNER) )
RFLAG.ZF 1;
RAX SGX_INVALID_MEASUREMENT;
GOTO EXIT;
FI;
(* Verify ATTRIBUTES in EINITTOKEN are the same as the enclave’s *)
IF (TMP_TOKEN.ATTRIBUTES ≠ DS:RCX.ATTRIBUTES)
RFLAG.ZF 1;
RAX SGX_INVALID_EINIT_ATTRIBUTE;
GOTO EXIT;
FI;
COMMIT:
(* Commit changes to the SECS; Set ISVPRODID, ISVSVN, MRSIGNER, INIT ATTRIBUTE fields in SECS (RCX) *)
DS:RCX.MRENCLAVE TMP_MRENCLAVE;
(* MRSIGNER stores a SHA256 in little endian implemented natively on x86 *)
DS:RCX.MRSIGNER TMP_MRSIGNER;
DS:RCX.ISVPRODID TMP_SIG.ISVPRODID;
DS:RCX.ISVSVN TMP_SIG.ISVSVN;
DS:RCX.PADDING TMP_SIG_PADDING;
(* Mark the SECS as initialized *)
Update DS:RCX to initialized;
(* Set RAX and ZF for success*)
RFLAG.ZF 0;
RAX 0;
EXIT:
RFLAGS.CF,PF,AF,OF,SF 0;
Vol. 3D 41-39
SGX INSTRUCTION REFERENCES
Flags Affected
ZF is cleared if successful, otherwise ZF is set and RAX contains the error code. CF, PF, AF, OF, SF are cleared.
Protected Mode Exceptions
#GP(0)
If a memory operand is not properly aligned.
If another instruction is modifying the SECS.
If the enclave is already initialized.
If the SECS.MRENCLAVE is in use.
#PF(error code)
If a page fault occurs in accessing memory operands.
If RCX does not resolve in an EPC page.
If the memory address is not a valid, uninitialized SECS.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is not properly aligned.
If another instruction is modifying the SECS.
If the enclave is already initialized.
If the SECS.MRENCLAVE is in use.
#PF(error code)
If a page fault occurs in accessing memory operands.
If RCX does not resolve in an EPC page.
If the memory address is not a valid, uninitialized SECS.
41-40 Vol. 3D
SGX INSTRUCTION REFERENCES
ELDB/ELDU—Load an EPC page and Marked its State
Opcode/
Instruction
Op/En
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
EAX = 07H
ENCLS[ELDB]
EAX = 08H
ENCLS[ELDU]
IR
V/V
SGX1
Description
This leaf function loads, verifies an EPC page and marks the page
as blocked.
This leaf function loads, verifies an EPC page and marks the page
as unblocked.
Instruction Operand Encoding
Op/En
EAX
ELDB/ELDU
(In)
IR
Return error
code (Out)
RBX
RCX
RDX
Address of the PAGEINFO
(In)
Address of the EPC page
(In)
Address of the versionarray slot (In)
Description
This leaf function copies a page from regular main memory to the EPC. As part of the copying process, the page is
cryptographically authenticated and decrypted. This instruction can only be executed when current privilege level
is 0.
The ELDB leaf function sets the BLOCK bit in the EPCM entry for the destination page in the EPC after copying. The
ELDU leaf function clears the BLOCK bit in the EPCM entry for the destination page in the EPC after copying.
RBX contains the effective address of a PAGEINFO structure; RCX contains the effective address of the destination
EPC page; RDX holds the effective address of the version array slot that holds the version of the page.
The table below provides additional information on the memory parameter of ELDB/ELDU leaf functions.
EBLDB/ELDBU Memory Parameter Semantics
PAGEINFO
PAGEINFO.SRCPGE
PAGEINFO.PCMD
PAGEINFO.SECS
EPCPAGE
Version-Array Slot
Non-enclave
read access
Non-enclave read
access
Non-enclave read
access
Enclave read/write
access
Read/Write access
permitted by Enclave
Read/Write access permitted by Enclave
The error codes are:
Table 41-25. ELDB/ELDU Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
ELDB/ELDU successful
SGX_MAC_COMPARE_FAIL
If the MAC check fails
Concurrency Restrictions
Table 41-26. Concurrency Restrictions of ELDB/ELDU with Intel® SGX Instructions - 1of 2
Operation
Param
ELDB/E
LDU
EEXIT
Targ VA
EADD
SECS Targ SECS Targ SECS
Targ
N
VA
N
SECS
EBLOCK
Y
N
N
Y
Y
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
N
N
N
N
N
Y
N
Y
N
Y
Y
Y
Y
ELDB/ELDU
EPA
Targ VA
SECS VA
N
N
N
N
Y
N
N
N
Y
Vol. 3D 41-41
SGX INSTRUCTION REFERENCES
Table 41-27. Concurrency Restrictions of ELDB/ELDU with Intel® SGX Instructions - 2 of 2
Operation
ELDB/E
LDU
EREMOVE
ETRA
CK
EREPORT
Param
Targ SECS Param SECS SECS
Targ
N
VA
N
SECS
N
N
Y
Y
Y
EWB
SRC VA
EAUG
EMODPE
SECS Targ SECS
N
N
N
N
Y
N
Y
N
Targ
SECI
NFO
N
EMODPR
Targ
SECS
N
EMODT
Targ
SECS
EACCEPT
Targ SECI
NFO
EACCEPTCOPY
SECS Targ SRC
N
N
Y
Y
Y
Y
Operation
Temp Variables in ELDB/ELDU Operational Flow
Name
Type
Size (Bits)
TMP_SRCPGE
Memory page
4KBytes
TMP_SECS
Memory page
4KBytes
TMP_PCMD
PCMD
128 Bytes
TMP_HEADER
MACHEADER
128 Bytes
TMP_VER
UINT64
64
TMP_MAC
UINT128
128
TMP_PK
UINT128
128
SCRATCH_PCMD
PCMD
128 Bytes
Description
Page encryption/MAC key.
(* Check PAGEINFO and EPCPAGE alignment *)
IF ( (DS:RBX is not 32Byte Aligned) or (DS:RCX is not 4KByte Aligned) )
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
(* Check VASLOT alignment *)
IF (DS:RDX is not 8Byte aligned)
THEN #GP(0); FI;
IF (DS:RDX does not resolve within an EPC)
THEN #PF(DS:RDX); FI;
TMP_SRCPGE DS:RBX.SRCPGE;
TMP_SECS DS:RBX.SECS;
TMP_PCMD DS:RBXPCMD;
(* Check alignment of PAGEINFO (RBX)linked parameters. Note: PCMD pointer is overlaid on top of PAGEINFO.SECINFO field *)
IF ( (DS:TMP_PCMD is not 128Byte aligned) or (DS:TMP_SRCPGE is not 4KByte aligned) )
THEN #GP(0); FI;
(* Check concurrency of EPC and VASLOT by other Intel SGX instructions *)
IF ( (other instructions accessing EPC) or (Other instructions modifying VA slot) )
THEN #GP(0); FI;
(* Verify EPCM attributes of EPC page, VA, and SECS *)
41-42 Vol. 3D
SECI
NFO
SGX INSTRUCTION REFERENCES
IF (EPCM(DS:RCX).VALID = 1)
THEN #PF(DS:RCX); FI;
IF ( (EPCM(DS:RDX & ~0FFFH).VALID = 0) or (EPCM(DS:RDX & ~0FFFH).PT ≠ PT_VA) )
THEN #PF(DS:RDX); FI;
(* Copy PCMD into scratch buffer *)
SCRATCH_PCMD[1023: 0] DS:TMP_PCMD[1023:0];
(* Zero out TMP_HEADER*)
TMP_HEADER[sizeof(TMP_HEADER)-1: 0] 0;
TMP_HEADER.SECINFO SCRATCH_PCMD.SECINFO;
TMP_HEADER.RSVD SCRATCH_PCMD.RSVD;
TMP_HEADER.LINADDR DS:RBX.LINADDR;
(* Verify various attributes of SECS parameter *)
IF ( (TMP_HEADER.SECINFO.FLAGS.PT = PT_REG) or (TMP_HEADER.SECINFO.FLAGS.PT = PT_TCS) or
(TMP_HEADER.SECINFO.FLAGS.PT = PT_TRIM) )
THEN
IF ( DS:TMP_SECS is not 4KByte aligned)
THEN #GP(0) FI;
IF (DS:TMP_SECS does not resolve within an EPC)
THEN #PF(DS:TMP_SECS) FI;
IF ( Other instructions modifying SECS)
THEN #GP(0) FI;
IF ( (EPCM(DS:TMP_SECS).VALID = 0) or (EPCM(DS:TMP_SECS).PT ≠ PT_SECS) )
THEN #PF(DS:TMP_SECS) FI;
ELSIF ( (TMP_HEADER.SECINFO.FLAGS.PT = PT_SECS) or (TMP_HEADER.SECINFO.FLAGS.PT = PT_VA) )
IF ( ( TMP_SECS ≠ 0) )
THEN #GP(0) FI;
ELSE
#GP(0)
FI;
IF ( (TMP_HEADER.SECINFO.FLAGS.PT = PT_REG) or (TMP_HEADER.SECINFO.FLAGS.PT = PT_TCS) or
(TMP_HEADER.SECINFO.FLAGS.PT = PT_TRIM) )
THEN
TMP_HEADER.EID DS:TMP_SECS.EID;
ELSE
(* These pages do not have any parent, and hence no EID binding *)
TMP_HEADER.EID 0;
FI;
(* Copy 4KBytes SRCPGE to secure location *)
DS:RCX[32767: 0] DS:TMP_SRCPGE[32767: 0];
TMP_VER DS:RDX[63:0];
(* Decrypt and MAC page. AES_GCM_DEC has 2 outputs, {plain text, MAC} *)
(* Parameters for AES_GCM_DEC {Key, Counter, ..} *)
{DS:RCX, TMP_MAC} AES_GCM_DEC(CR_BASE_PK, TMP_VER << 32, TMP_HEADER, 128, DS:RCX, 4096);
IF ( (TMP_MAC ≠ DS:TMP_PCMD.MAC) )
THEN
Vol. 3D 41-43
SGX INSTRUCTION REFERENCES
RFLAGS.ZF 1;
RAX SGX_MAC_COMPARE_FAIL;
GOTO ERROR_EXIT;
FI;
(* Check version before committing *)
IF (DS:RDX ≠ 0)
THEN #GP(0);
ELSE
DS:RDX TMP_VER;
FI;
(* Commit EPCM changes *)
EPCM(DS:RCX).PT TMP_HEADER.SECINFO.FLAGS.PT;
EPCM(DS:RCX).RWX TMP_HEADER.SECINFO.FLAGS.RWX;
EPCM(DS:RCX).PENDING TMP_HEADER.SECINFO.FLAGS.PENDING;
EPCM(DS:RCX).MODIFIED TMP_HEADER.SECINFO.FLAGS.MODIFIED;
EPCM(DS:RCX).PR TMP_HEADER.SECINFO.FLAGS.PR;
EPCM(DS:RCX).ENCLAVEADDRESS TMP_HEADER.LINADDR;
IF ( (EAX = 07H) and (TMP_HEADER.SECINFO.FLAGS.PT is NOT PT_SECS or PT_VA))
THEN
EPCM(DS:RCX).BLOCKED 1;
ELSE
EPCM(DS:RCX).BLOCKED 0;
FI;
EPCM(DS:RCX). VALID 1;
RAX 0;
RFLAGS.ZF 0;
ERROR_EXIT:
RFLAGS.CF,PF,AF,OF,SF 0;
Flags Affected
Sets ZF if unsuccessful, otherwise cleared and RAX returns error code. Clears CF, PF, AF, OF, SF.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If the instruction’s EPC resource is in use by others.
If the instruction fails to verify MAC.
If the version-array slot is in use.
If the parameters fail consistency checks.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand expected to be in EPC does not resolve to an EPC page.
If one of the EPC memory operands has incorrect page type.
If the destination EPC page is already valid.
64-Bit Mode Exceptions
#GP(0)
41-44 Vol. 3D
If a memory operand is non-canonical form.
SGX INSTRUCTION REFERENCES
If a memory operand is not properly aligned.
If the instruction’s EPC resource is in use by others.
If the instruction fails to verify MAC.
If the version-array slot is in use.
If the parameters fail consistency checks.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand expected to be in EPC does not resolve to an EPC page.
If one of the EPC memory operands has incorrect page type.
If the destination EPC page is already valid.
Vol. 3D 41-45
SGX INSTRUCTION REFERENCES
EMODPR—Restrict the Permissions of an EPC Page
Opcode/
Instruction
Op/En
EAX = 0EH
ENCLS[EMODPR]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX2
Description
This leaf function restricts the access rights associated with a
EPC page in an initialized enclave.
Instruction Operand Encoding
Op/En
EAX
IR
EMODPR (In)
Return Error Code (Out)
RBX
RCX
Address of a SECINFO (In)
Address of the destination EPC page (In)
Description
This leaf function restricts the access rights associated with an EPC page in an initialized enclave. THE RWX bits of
the SECINFO parameter are treated as a permissions mask; supplying a value that does not restrict the page
permissions will have no effect. This instruction can only be executed when current privilege level is 0.
RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC page.
The table below provides additional information on the memory parameter of the EMODPR leaf function.
EMODPR Memory Parameter Semantics
SECINFO
EPCPAGE
Read access permitted by Non Enclave
Read/Write access permitted by Enclave
The instruction faults if any of the following:
EMODPR Faulting Conditions
The operands are not properly aligned.
If unsupported security attributes are set.
The Enclave is not initialized.
SECS is locked by another thread.
The EPC page is locked by another thread.
RCX does not contain an effective address of an EPC page in the running enclave.
The EPC page is not valid.
The error codes are:
Table 41-28. EMODPR Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EMODPR successful
SGX_PAGE_NOT_MODIFIABLE
The EPC page cannot be modified because it is in the PENDING or MODIFIED
state
SGX_LOCKFAIL
Page is being written by EADD, EAUG, ECREATE, ELDU/B, EMODT, or EWB
Concurrency Restrictions
Table 41-29. Concurrency Restrictions of EMODPR with Other Intel® SGX Operations 1 of 2
Operation
Param
EMODPR
Targ
SECS
41-46 Vol. 3D
EEXIT
TCS SSA
SECS
Y
Y
ECRE
ATE
EDBGRD/
WR
EADD
EBLOCK
Targ SECS
Targ SECS
SECS
Targ SECS
N
Y
N
Y
Y
Y
Y
N
Y
Y
EENTER/
ERESUME
EGETKEY
TCS SSA SECS Targ SECS Param SECS
Y
Y
EEXTEND
Y
Y
N
Y
Y
EINIT
SECS
Y
N
Y
ELDB/ELDU
Targ VA
SECS VA
N
Y
N
Y
EP
A
N
Y
Y
Y
SGX INSTRUCTION REFERENCES
Table 41-30. Concurrency Restrictions of EMODPR with Other Intel® SGX Operations 2 of 2
Operation
EMODP
R
EREMOVE
EREPORT
Param
Targ SECS Param SECS
Targ
N
SECS
Y
Y
ETRACK
SECS
Y
Y
Y
EWB
SRC
EAUG
Y
EMODPR
VA
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Y
Y
N
Y
EMODPE
N
Y
Y
C
Y
C
Y
Y
Y
Y
EMODT
EACCEPT
Targ SEC
S
Targ SECI
NFO
C
C
Y
Y
Y
Y
Y
EACCEPTCOPY
SECS Targ SR
C
Y
SECI
NFO
C
Y
Y
Y
Y
Y
Operation
Temp Variables in EMODPR Operational Flow
Name
Type
Size (bits)
Description
TMP_SECS
Effective Address
32/64
Physical address of SECS to which EPC operand belongs.
SCRATCH_SECINFO
SECINFO
512
Scratch storage for holding the contents of DS:RBX.
IF (DS:RBX is not 64Byte Aligned)
THEN #GP(0); FI;
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
SCRATCH_SECINFO DS:RBX;
(* Check for mis-configured SECINFO flags*)
IF ( (SCRATCH_SECINFO reserved fields are not zero ) or
!(SCRATCH_SECINFO.FLAGS.R is 0 or SCRATCH_SECINFO.FLAGS.W is not 0) )
THEN #GP(0); FI;
(* Check concurrency with SGX1 or SGX2 instructions on the EPC page *)
IF (SGX1 or other SGX2 instructions accessing EPC page)
THEN #GP(0); FI;
IF (EPCM(DS:RCX).VALID is 0 )
THEN #PF(DS:RCX); FI;
(* Check the EPC page for concurrency *)
IF (EPC page in use by another SGX2 instruction)
THEN
RFLAGS 1;
RAX SGX_LOCKFAIL;
GOTO DONE;
FI;
IF ( (EPCM(DS:RCX).PENDING is not 0 or (EPCM(DS:RCX).MODIFIED is not 0) )
THEN
RFLAGS 1;
RAX SGX_PAGE_NOT_MODIFIABLE;
GOTO DONE;
Vol. 3D 41-47
SGX INSTRUCTION REFERENCES
FI;
IF (EPCM(DS:RCX).PT is not PT_REG)
THEN #PF(DS:RCX); FI;
TMP_SECS GET_SECS_ADDRESS
IF (TMP_SECS.ATTRIBUTES.INIT = 0)
THEN #GP(0); FI;
(* Set the PR bit to indicate that permission restriction is in progress *)
EPCM(DS:RCX).PR 1;
(* Update EPCM permissions *)
EPCM(DS:RCX).R EPCM(DS:RCX).R & SCRATCH_SECINFO.FLAGS.R;
EPCM(DS:RCX).W EPCM(DS:RCX).W & SCRATCH_SECINFO.FLAGS.W;
EPCM(DS:RCX).X EPCM(DS:RCX).X & SCRATCH_SECINFO.FLAGS.X;
RFLAGS.ZF 0;
RAX 0;
DONE:
RFLAGS.CF,PF,AF,OF,SF 0;
Flags Affected
Sets ZF if page is not modifiable or if other SGX2 instructions are executing concurrently, otherwise cleared. Clears
CF, PF, AF, OF, SF.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
41-48 Vol. 3D
SGX INSTRUCTION REFERENCES
EMODT—Change the Type of an EPC Page
Opcode/
Instruction
Op/En
EAX = 0FH
ENCLS[EMODT]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX2
Description
This leaf function changes the type of an existing EPC page.
Instruction Operand Encoding
Op/En
EAX
IR
EMODT (In)
Return Error Code (Out)
RBX
RCX
Address of a SECINFO (In)
Address of the destination EPC page (In)
Description
This leaf function modifies the type of an EPC page. The security attributes are configured to prevent access to the
EPC page at its new type until a corresponding invocation of the EACCEPT leaf confirms the modification. This
instruction can only be executed when current privilege level is 0.
RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC
page. The table below provides additional information on the memory parameter of the EMODT leaf function.
EMODT Memory Parameter Semantics
SECINFO
EPCPAGE
Read access permitted by Non Enclave
Read/Write access permitted by Enclave
The instruction faults if any of the following:
EMODT Faulting Conditions
The operands are not properly aligned.
If unsupported security attributes are set.
The Enclave is not initialized.
SECS is locked by another thread.
The EPC page is locked by another thread.
RCX does not contain an effective address of an EPC page in the running enclave.
The EPC page is not valid.
The error codes are:
Table 41-31. EMODT Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EMODT successful
SGX_PAGE_NOT_MODIFIABLE
The EPC page cannot be modified because it is in the PENDING or MODIFIED state
SGX_LOCKFAIL
Page is being written by EADD, EAUG, ECREATE, ELDU/B, EMODPR, or EWB
Concurrency Restrictions
Table 41-32. Concurrency Restrictions of EMODT with Other Intel® SGX Operations 1 of 2
Operation
EMODT
EEXIT
Param
TCS SSA
Targ
Y
SECS
SECS
Y
Y
EADD
EBLOCK
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
Targ SECS
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
C
C
C
C
C
C
Y
N
C
C
Y
N
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
C
Y
Y
Y
N
Y
Y
EP
A
SECS VA
C
Y
Y
Vol. 3D 41-49
SGX INSTRUCTION REFERENCES
Table 41-33. Concurrency Restrictions of EMODT with Other Intel® SGX Operations 2 of 2
Operation
EMODT
EREMOVE
EREPORT
Param
Targ SECS Param SECS
Targ
C
SECS
Y
ETRACK
SECS
Y
Y
Y
Y
Y
EWB
SRC
VA
C
C
Y
Y
EAUG
EMODPE
EMODPR
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Y
C
C
C
Y
C
Y
Y
Y
Y
Y
EMODT
Targ SEC
S
C
Y
EACCEPT
Targ SECI
NFO
Y
C
Y
Y
Y
Y
EACCEPTCOPY
SECS Targ SR
C
Y
C
Y
Y
Y
Y
Y
Operation
Temp Variables in EMODT Operational Flow
Name
Type
Size (bits)
Description
TMP_SECS
Effective Address
32/64
Physical address of SECS to which EPC operand belongs.
SCRATCH_SECINFO
SECINFO
512
Scratch storage for holding the contents of DS:RBX.
IF (DS:RBX is not 64Byte Aligned)
THEN #GP(0); FI;
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
SCRATCH_SECINFO DS:RBX;
(* Check for mis-configured SECINFO flags*)
IF ( (SCRATCH_SECINFO reserved fields are not zero ) or
!(SCRATCH_SECINFO.FLAGS.PT is PT_TCS or SCRATCH_SECINFO.FLAGS.PT is PT_TRIM) )
THEN #GP(0); FI;
(* Check concurrency with SGX1 instructions on the EPC page *)
IF (other SGX1 instructions accessing EPC page)
THEN #GP(0); FI;
IF (EPCM(DS:RCX).VALID is 0 or
!(EPCM(DS:RCX).PT is PT_REG or EPCM(DS:RCX).PT is PT_TCS))
THEN #PF(DS:RCX); FI;
(* Check the EPC page for concurrency *)
IF (EPC page in use by another SGX2 instruction)
THEN #GP(0); FI;
(* Check for mis-configured SECINFO flags*)
IF ( (EPCM(DS:RCX).R = 0) and (SCRATCH_SECINFO.FLAGS.R = 0) and (SCRATCH_SECINFO.FLAGS.W ≠ 0) ))
THEN
RFLAGS 1;
RAX SGX_LOCKFAIL;
GOTO DONE;
FI;
41-50 Vol. 3D
SECI
NFO
SGX INSTRUCTION REFERENCES
IF ( (EPCM(DS:RCX).PENDING is not 0 or (EPCM(DS:RCX).MODIFIED is not 0) )
THEN
RFLAGS 1;
RAX SGX_PAGE_NOT_MODIFIABLE;
GOTO DONE;
FI;
TMP_SECS GET_SECS_ADDRESS
IF (TMP_SECS.ATTRIBUTES.INIT = 0)
THEN #GP(0); FI;
(* Check concurrency with ETRACK *)
IF (ETRACK executed concurrently)
THEN #GP(0); FI;
(* Update EPCM fields *)
EPCM(DS:RCX).PR 0;
EPCM(DS:RCX).MODIFIED 1;
EPCM(DS:RCX).R 0;
EPCM(DS:RCX).W 0;
EPCM(DS:RCX).X 0;
EPCM(DS:RCX).PT SCRATCH_SECINFO.FLAGS.PT;
RFLAGS.ZF 0;
RAX 0;
DONE:
RFLAGS.CF,PF,AF,OF,SF 0;
Flags Affected
Sets ZF if page is not modifiable or if other SGX2 instructions are executing concurrently, otherwise cleared. Clears
CF, PF, AF, OF, SF.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
Vol. 3D 41-51
SGX INSTRUCTION REFERENCES
EPA—Add Version Array
Opcode/
Instruction
Op/En
EAX = 0AH
ENCLS[EPA]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function adds a Version Array to the EPC.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EPA (In)
PT_VA (In, Constant)
Effective address of the EPC page (In)
Description
This leaf function creates an empty version array in the EPC page whose logical address is given by DS:RCX, and
sets up EPCM attributes for that page. At the time of execution of this instruction, the register RBX must be set to
PT_VA.
The table below provides additional information on the memory parameter of EPA leaf function.
EPA Memory Parameter Semantics
EPCPAGE
Write access permitted by Enclave
Concurrency Restrictions
Table 41-34. Concurrency Restrictions of EPA with Other Intel® SGX Operations 1 of 2
Operation
Param
EPA
EEXIT
TCS SSA
EADD
SECS Targ SECS
N
VA
EBLOCK
N
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
N
N
N
N
N
N
N
EPA
SECS VA
N
N
Table 41-35. Concurrency Restrictions of EPA with Other Intel® SGX Operations 2 of 2
Operation
EPA
EREMOVE
EREPORT
ETRACK
EWB
Param
Targ SECS Param SECS
SECS
SRC
VA
VA
N
N
N
N
Operation
IF (RBX ≠ PT_VA or DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
(* Check concurrency with other Intel SGX instructions *)
IF (Other Intel SGX instructions accessing the page)
THEN #GP(0); FI;
41-52 Vol. 3D
EAUG
EMODPE
SECS Targ SECS Targ SECI
NFO
N
N
EMODPR
EMODT
EACCEPT
EACCEPTCOPY
Targ SECS Targ SECS Targ SECI SECS Targ SR
NFO
C
N
N
SECI
NFO
SGX INSTRUCTION REFERENCES
(* Check EPC page must be empty *)
IF (EPCM(DS:RCX). VALID ≠ 0)
THEN #PF(DS:RCX); FI;
(* Clears EPC page *)
DS:RCX[32767:0] 0;
EPCM(DS:RCX).PT PT_VA;
EPCM(DS:RCX).ENCLAVEADDRESS 0;
EPCM(DS:RCX).BLOCKED 0;
EPCM(DS:RCX).PENDING 0;
EPCM(DS:RCX).MODIFIED 0;
EPCM(DS:RCX).PR 0;
EPCM(DS:RCX).RWX 0;
EPCM(DS:RCX).VALID 1;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If another Intel SGX instruction is accessing the EPC page.
If RBX is not set to PT_VA.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If the EPC page is valid.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If another Intel SGX instruction is accessing the EPC page.
If RBX is not set to PT_VA.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If the EPC page is valid.
Vol. 3D 41-53
SGX INSTRUCTION REFERENCES
EREMOVE—Remove a page from the EPC
Opcode/
Instruction
Op/En
EAX = 03H
ENCLS[EREMOVE]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function removes a page from the EPC.
Instruction Operand Encoding
Op/En
EAX
RCX
IR
EREMOVE (In)
Effective address of the EPC page (In)
Description
This leaf function causes an EPC page to be un-associated with its SECS and be marked as unused. This instruction
leaf can only be executed when the current privilege level is 0.
The content of RCX is an effective address of an EPC page. The DS segment is used to create linear address.
Segment override is not supported.
The instruction fails if the operand is not properly aligned or does not refer to an EPC page or the page is in use by
another thread, or other threads are running in the enclave to which the page belongs. In addition the instruction
fails if the operand refers to an SECS with associations.
EREMOVE Memory Parameter Semantics
EPCPAGE
Write access permitted by Enclave
The instruction faults if any of the following:
EREMOVE Faulting Conditions
The memory operand is not properly aligned.
The memory operand does not resolve in an EPC page.
Refers to an invalid SECS.
Refers to an EPC page that is locked by another thread.
Another Intel SGX instruction is accessing the EPC page.
RCX does not contain an effective address of an EPC page.
the EPC page refers to an SECS with associations.
The error codes are:
Table 41-36. EREMOVE Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EREMOVE successful
SGX_CHILD_PRESENT
If the SECS still have enclave pages loaded into EPC
SGX_ENCLAVE_ACT
If there are still logical processors executing inside the enclave
41-54 Vol. 3D
SGX INSTRUCTION REFERENCES
Concurrency Restrictions
Table 41-37. Concurrency Restrictions of EREMOVE with Other Intel® SGX Operations 1 of 2
Operation
EREMOVE
EEXIT
Param
TCS SSA
Targ
C
C
SECS
EADD
EBLOCK
SECS Targ SECS
Targ SECS
ECRE
ATE
SECS
EDBGRD/
WR
Targ SECS
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EPA
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
SECS VA
C
N
N
N
C
N
N
C
N
C
C
N
C
C
C
N
N
N
N
N
C
Y
Y
Y
Y
Y
Y
Y
Y
Y
C
Y
Y
Y
C
Y
Y
Y
Y
Y
Table 41-38. Concurrency Restrictions of EREMOVE with Other Intel® SGX Operations 2 of 2
Operation
EREMOVE
EREMOVE
EREPORT
ETRACK
EWB
EAUG
EMODPE
EMODPR
EMODT
EACCEPT
EACCEPTCOPY
Param
Targ SECS Param SECS
SECS
SRC
VA
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Targ SEC
S
Targ SECI
NFO
SECS Targ SR
C
SECI
NFO
Targ
N
C
C
C
N
N
N
C
N
N
C
C
N
C
N
C
C
C
C
C
C
C
SECS
Y
Y
Y
C
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
C
C
C
Y
Y
Y
Operation
Temp Variables in EREMOVE Operational Flow
Name
Type
Size (Bits)
Description
TMP_SECS
Effective Address
32/64
Effective address of the SECS destination page.
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve to an EPC page)
THEN #PF(DS:RCX); FI;
TMP_SECS Get_SECS_ADDRESS();
(* Check the EPC page for concurrency *)
IF (EPC page being referenced by another Intel SGX instruction)
THEN #GP(0); FI;
(* if DS:RCX is already unused, nothing to do*)
IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PT = PT_TRIM AND EPCM(DS:RCX).MODIFIED = 0))
THEN GOTO DONE;
FI;
IF (EPCM(DS:RCX).PT = PT_VA)
THEN
EPCM(DS:RCX).VALID 0;
GOTO DONE;
FI;
IF (EPCM(DS:RCX).PT = PT_SECS)
THEN
IF (DS:RCX has an EPC page associated with it)
THEN
RFLAGS.ZF 1;
Vol. 3D 41-55
SGX INSTRUCTION REFERENCES
RAX SGX_CHILD_PRESENT;
GOTO ERROR_EXIT;
FI;
EPCM(DS:RCX).VALID 0;
GOTO DONE;
FI;
TEMP_SECS Get_SECS_ADDRESS();
IF (Other threads active using SECS)
THEN
RFLAGS.ZF 1;
RAX SGX_ENCLAVE_ACT;
GOTO ERROR_EXIT;
FI;
DONE:
RAX 0;
RFLAGS.ZF 0;
ERROR_EXIT:
RFLAGS.CF,PF,AF,OF,SF 0;
Flags Affected
Sets ZF if unsuccessful, otherwise cleared and RAX returns error code. Clears CF, PF, AF, OF, SF
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If another Intel SGX instruction is accessing the page.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the memory operand is not an EPC page.
64-Bit Mode Exceptions
#GP(0)
If the memory operand is non-canonical form.
If a memory operand is not properly aligned.
If another Intel SGX instruction is accessing the page.
#PF(error code)
If a page fault occurs in accessing memory operands.
If the memory operand is not an EPC page.
41-56 Vol. 3D
SGX INSTRUCTION REFERENCES
ETRACK—Activates EBLOCK Checks
Opcode/
Instruction
Op/En
EAX = 0CH
ENCLS[ETRACK]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function activates EBLOCK checks.
Instruction Operand Encoding
Op/En
EAX
IR
ETRACK (In)
RCX
Return error code (Out)
Pointer to the SECS of the EPC page (In)
Description
This leaf function provides the mechanism for hardware to track that software has completed the required TLB
address clears successfully. The instruction can only be executed when the current privilege level is 0.
The content of RCX is an effective address of an EPC page.
The table below provides additional information on the memory parameter of EBLOCK leaf function.
ETRACK Memory Parameter Semantics
EPCPAGE
Read/Write access permitted by Enclave
The error codes are:
Table 41-39. ETRACK Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
ETRACK successful
SGX_PREV_TRK_INCMPL
All processors did not complete the previous shoot-down sequence
Concurrency Restrictions
Table 41-40. Concurrency Restrictions of ETRACK with Other Intel® SGX Operations 1 of 2
Operation
Param
ETRACK
EEXIT
TCS SSA
EADD
SECS Targ SECS
Y
SECS
EBLOCK
N
Targ SECS
Y
Y
ECRE
ATE
EDBGRD/
WR
SECS
Targ SECS
N
N
Y
EENTER/
ERESUME
EEXTEND
EGETKEY
TCS SSA SECS Targ SECS Param SECS
Y
Y
Y
EINIT
ELDB/ELDU
EPA
SECS
Targ VA
SECS VA
Y
N
Y
N
Table 41-41. Concurrency Restrictions of ETRACK with Other Intel® SGX Operations 2 of 2
Operation
ETRACK
EREMOVE
EREPORT
Param
Targ SECS Param SECS
SECS
N
Y
Y
ETRACK
EWB
SECS
SRC
N
N
VA
EAUG
EMODPE
SECS Targ SECS Targ SECI
NFO
Y
N
Y
EMODPR
EMODT
EACCEPT
EACCEPTCOPY
Targ SECS Targ SECS Targ SECI SECS Targ SR
NFO
C
Y
Y
SECI
NFO
Y
Operation
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
Vol. 3D 41-57
SGX INSTRUCTION REFERENCES
(* Check concurrency with other Intel SGX instructions *)
IF (Other Intel SGX instructions using tracking facility on this SECS)
THEN #GP(0); FI;
IF (EPCM(DS:RCX). VALID = 0)
THEN #PF(DS:RCX); FI;
IF (EPCM(DS:RCX).PT ≠ PT_SECS)
THEN #PF(DS:RCX); FI;
(* All processors must have completed the previous tracking cycle*)
IF ( (DS:RCX).TRACKING ≠ 0) )
THEN
RFLAGS.ZF 1;
RAX SGX_PREV_TRK_INCMPL;
GOTO DONE;
ELSE
RAX 0;
RFLAGS.ZF 0;
FI;
DONE:
RFLAGS.ZF,CF,PF,AF,OF,SF 0;
Flags Affected
Sets ZF if SECS is in use or invalid, otherwise cleared. Clears CF, PF, AF, OF, SF
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If another thread is concurrently using the tracking facility on this SECS.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If the specified EPC resource is in use.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
Table 41-42. ETRACK Return Value in RAX
Error Code (see Table 41-3)
No Error
SGX_PREV_TRK_INCMPL
41-58 Vol. 3D
Value
0
Description
ETRACK successful
All processors did not complete the previous shoot-down sequence
SGX INSTRUCTION REFERENCES
EWB—Invalidate an EPC Page and Write out to Main Memory
Opcode/
Instruction
Op/En
EAX = 0BH
ENCLS[EWB]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function invalidates an EPC page and writes it out to
main memory.
Instruction Operand Encoding
Op/En
IR
EAX
EWB (In)
Error code (Out)
RBX
RCX
RDX
Address of an PAGEINFO (In)
Address of the EPC page (In)
Address of a VA slot (In)
Description
This leaf function copies a page from the EPC to regular main memory. As part of the copying process, the page is
cryptographically protected. This instruction can only be executed when current privilege level is 0.
The table below provides additional information on the memory parameter of EPA leaf function.
EWB Memory Parameter Semantics
PAGEINFO
PAGEINFO.SRCPGE
PAGEINFO.PCMD
EPCPAGE
VASLOT
Non-EPC R/W access
Non-EPC R/W access
Non-EPC R/W access
EPC R/W access
EPC R/W access
The error codes are:
Table 41-43. EWB Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EWB successful
SGX_PAGE_NOT_BLOCKED
If page is not marked as blocked
SGX_NOT_TRACKED
If EWB is racing with ETRACK instruction
SGX_VA_SLOT_OCCUPIED
Version array slot contained valid entry
SGX_CHILD_PRESENT
Child page present while attempting to page out enclave
Concurrency Restrictions
Table 41-44. Concurrency Restrictions of EWB with Intel® SGX Instructions - 1of 2
Operation
EWB
EEXIT
EADD
ECRE
ATE
EBLOCK
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EPA
Param
Targ VA
SECS Targ SECS Targ SECS
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
Src
C
C
N
N
N
N
N
N
N
N
Y
N
Y
N
Y
Y
Y
Y
C
VA
N
N
N
C
N
Y
SECS
Y
Y
Y
Y
C
Y
C
Y
C
Y
N
Y
C
Y
C
Y
C
Y
Y
Y
SECS VA
Y
Y
Table 41-45. Concurrency Restrictions of EWB with Intel® SGX Instructions - 2 of 2
Operation
Param
EREMOVE
EREPORT
ETRA
CK
Targ SECS Param SECS SECS
EWB
SRC VA
EAUG
SECS Targ SECS
EMODPE
Targ
SECI
NFO
EMODPR
Targ
SECS
EMODT
Targ
SECS
EACCEPT
Targ SECI
NFO
EACCEPTCOPY
SECS Targ SRC
SECI
NFO
Vol. 3D 41-59
SGX INSTRUCTION REFERENCES
Table 41-45. Concurrency Restrictions of EWB with Intel® SGX Instructions - 2 of 2
Operation
EWB
EREMOVE
Src
N
VA
N
SECS
Y
C
Y
EREPORT
C
C
Y
Y
ETRA
CK
N
Y
EWB
N
N
N
Y
Y
Y
EAUG
C
N
EMODPE
N
C
C
EMODPR
N
C
N
Y
Y
N
EACCEPT
EACCEPTCOPY
C
C
C
C
C
C
C
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Operation
Temp Variables in EWB Operational Flow
Name
Type
Size (Bytes)
TMP_SRCPGE
Memory page
4096
TMP_PCMD
PCMD
128
TMP_SECS
SECS
4096
TMP_BPEPOCH
UINT64
8
TMP_BPREFCOUNT
UINT64
8
TMP_HEADER
MAC Header
128
TMP_PCMD_ENCLAVEID
UINT64
8
TMP_VER
UINT64
8
TMP_PK
UINT128
16
Description
IF ( (DS:RBX is not 32Byte Aligned) or (DS:RCX is not 4KByte Aligned) )
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
IF (DS:RDX is not 8Byte Aligned)
THEN #GP(0); FI;
IF (DS:RDX does not resolve within an EPC)
THEN #PF(DS:RDX); FI;
(* EPCPAGE and VASLOT should not resolve to the same EPC page*)
IF (DS:RCX and DS:RDX resolve to the same EPC page)
THEN #GP(0); FI;
TMP_SRCPGE DS:RBX.SRCPGE;
(* Note PAGEINFO.PCMD is overlaid on top of PAGEINFO.SECINFO *)
TMP_PCMD DS:RBX.PCMD;
If (DS:RBX.LINADDR ≠ 0) OR (DS:RBX.SECS ≠ 0)
THEN #GP(0); FI;
IF ( (DS:TMP_PCMD is not 128Byte Aligned) or (DSTMP_SRCPGE is not 4KByte Aligned) )
THEN #GP(0); FI;
(* Check for concurrent Intel SGX instruction access to the page *)
IF (Other Intel SGX instruction is accessing page)
41-60 Vol. 3D
EMODT
Y
SGX INSTRUCTION REFERENCES
THEN #GP(0); FI;
(*Check if the VA Page is being removed or changed*)
IF (VA Page is being modified)
THEN #GP(0); FI;
(* Verify that EPCPAGE and VASLOT page are valid EPC pages and DS:RDX is VA *)
IF (EPCM(DS:RCX).VALID = 0)
THEN #PF(DS:RCX); FI;
IF ( (EPCM(DS:RDX & ~0FFFH).VALID = 0) or (EPCM(DS:RDX & ~FFFH).PT is not PT_VA) )
THEN #PF(DS:RDX); FI;
(* Perform page-type-specific exception checks *)
IF ( (EPCM(DS:RCX).PT is PT_REG) or (EPCM(DS:RCX).PT is PT_TCS) or (EPCM(DS:RCX).PT is PT_TRIM ) )
THEN
TMP_SECS = Obtain SECS through EPCM(DS:RCX)
(* Check that EBLOCK has occurred correctly *)
IF (EBLOCK is not correct)
THEN #GP(0); FI;
FI;
RFLAGS.ZF,CF,PF,AF,OF,SF 0;
RAX 0;
(* Perform page-type-specific checks *)
IF ( (EPCM(DS:RCX).PT is PT_REG) or (EPCM(DS:RCX).PT is PT_TCS) or (EPCM(DS:RCX).PT is PT_TRIM ))
THEN
(* check to see if the page is evictable *)
IF (EPCM(DS:RCX).BLOCKED = 0)
THEN
RAX SGX_PAGE NOT_BLOCKED;
RFLAGS.ZF 1;
GOTO ERROR_EXIT;
FI;
(* Check if tracking done correctly *)
IF (Tracking not correct)
THEN
RAX SGX_NOT_TRACKED;
RFLAGS.ZF 1;
GOTO ERROR_EXIT;
FI;
(* Obtain EID to establish cryptographic binding between the paged-out page and the enclave *)
TMP_HEADER.EID TMP_SECS.EID;
(* Obtain EID as an enclave handle for software *)
TMP_PCMD_ENCLAVEID TMP_SECS.EID;
ELSE IF (EPCM(DS:RCX).PT is PT_SECS)
(*check that there are no child pages inside the enclave *)
IF (DS:RCX has an EPC page associated with it)
THEN
RAX SGX_CHILD_PRESENT;
RFLAGS.ZF 1;
Vol. 3D 41-61
SGX INSTRUCTION REFERENCES
GOTO ERROR_EXIT;
FI:
TMP_HEADER.EID 0;
(* Obtain EID as an enclave handle for software *)
TMP_PCMD_ENCLAVEID (DS:RCX).EID;
ELSE IF (EPCM(DS:RCX).PT is PT_VA)
TMP_HEADER.EID 0; // Zero is not a special value
(* No enclave handle for VA pages*)
TMP_PCMD_ENCLAVEID 0;
FI;
(* Zero out TMP_HEADER*)
TMP_HEADER[ sizeof(TMP_HEADER)-1 : 0] 0;
TMP_HEADER.LINADDR EPCM(DS:RCX).ENCLAVEADDRESS;
TMP_HEADER.SECINFO.FLAGS.PT EPCM(DS:RCX).PT;
TMP_HEADER.SECINFO.FLAGS.RWX EPCM(DS:RCX).RWX;
TMP_HEADER.SECINFO.FLAGS.PENDING EPCM(DS:RCX).PENDING;
TMP_HEADER.SECINFO.FLAGS.MODIFIED EPCM(DS:RCX).MODIFIED;
TMP_HEADER.SECINFO.FLAGS.PR EPCM(DS:RCX).PR;
(* Encrypt the page, DS:RCX could be encrypted in place. AES-GCM produces 2 values, {ciphertext, MAC}. *)
(* AES-GCM input parameters: key, GCM Counter, MAC_HDR, MAC_HDR_SIZE, SRC, SRC_SIZE)*)
{DS:TMP_SRCPGE, DS:TMP_PCMD.MAC} AES_GCM_ENC(CR_BASE_PK), (TMP_VER << 32),
TMP_HEADER, 128, DS:RCX, 4096);
(* Write the output *)
Zero out DS:TMP_PCMD.SECINFO
DS:TMP_PCMD.SECINFO.FLAGS.PT EPCM(DS:RCX).PT;
DS:TMP_PCMD.SECINFO.FLAGS.RWX EPCM(DS:RCX).RWX;
DS:TMP_PCMD.SECINFO.FLAGS.PENDING EPCM(DS:RCX).PENDING;
DS:TMP_PCMD.SECINFO.FLAGS.MODIFIED EPCM(DS:RCX).MODIFIED;
DS:TMP_PCMD.SECINFO.FLAGS.PR EPCM(DS:RCX).PR;
DS:TMP_PCMD.RESERVED 0;
DS:TMP_PCMD.ENCLAVEID TMP_PCMD_ENCLAVEID;
DS:RBX.LINADDR EPCM(DS:RCX).ENCLAVEADDRESS;
(*Check if version array slot was empty *)
IF ([DS.RDX])
THEN
RAX SGX_VA_SLOT_OCCUPIED
RFLAGS.CF 1;
FI;
(* Write version to Version Array slot *)
[DS.RDX] TMP_VER;
(* Free up EPCM Entry *)
EPCM.(DS:RCX).VALID 0;
EXIT:
Flags Affected
ZF is set if page is not blocked, not tracked, or a child is present. Otherwise cleared.
CF is set if VA slot is previously occupied, Otherwise cleared.
41-62 Vol. 3D
SGX INSTRUCTION REFERENCES
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If the EPC page and VASLOT resolve to the same EPC page.
If another Intel SGX instruction is concurrently accessing either the target EPC, VA, or SECS
pages.
If the tracking resource is in use.
If the EPC page or the version array page is invalid.
If the parameters fail consistency checks.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If one of the EPC memory operands has incorrect page type.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If the EPC page and VASLOT resolve to the same EPC page.
If another Intel SGX instruction is concurrently accessing either the target EPC, VA, or SECS
pages.
If the tracking resource is in use.
If the EPC page or the version array page in invalid.
If the parameters fail consistency checks.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If one of the EPC memory operands has incorrect page type.
Vol. 3D 41-63
SGX INSTRUCTION REFERENCES
41.4
INTEL® SGX USER LEAF FUNCTION REFERENCE
41.4.1
Instruction Column in the Instruction Summary Table
Leaf functions available with the ENCLU instruction mnemonic are covered in this section. In general, each instruction leaf requires EAX to specify the leaf function index and/or additional registers specifying leaf-specific input
parameters. An instruction operand encoding table provides details of the implicitly-encoded register usage and
associated input/output semantics.
In many cases, an input parameter specifies an effective address associated with a memory object inside or outside
the EPC, the memory addressing semantics of these memory objects are also summarized in a separate table.
41-64 Vol. 3D
SGX INSTRUCTION REFERENCES
EACCEPT—Accept Changes to an EPC Page
Opcode/
Instruction
Op/En
EAX = 05H
ENCLU[EACCEPT]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX2
Description
This leaf function accepts changes made by system software to
an EPC page in the running enclave.
Instruction Operand Encoding
Op/En
IR
EAX
EACCEPT (In)
Return Error Code (Out)
RBX
RCX
Address of a SECINFO (In)
Address of the destination EPC page (In)
Description
This leaf function accepts changes to a page in the running enclave by verifying that the security attributes specified in the SECINFO match the security attributes of the page in the EPCM. This instruction leaf can only be
executed when inside the enclave.
RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC
page. The table below provides additional information on the memory parameter of the EACCEPT leaf function.
EACCEPT Memory Parameter Semantics
SECINFO
EPCPAGE (Destination)
Read access permitted by Non Enclave
Read access permitted by Enclave
The instruction faults if any of the following:
EACCEPT Faulting Conditions
The operands are not properly aligned.
If security attributes of the SECINFO page make the page inaccessible.
The EPC page is locked by another thread.
RBX does not contain an effective address in an EPC page in the running enclave.
The EPC page is not valid.
RCX does not contain an effective address of an EPC page in the running enclave.
SECINFO contains an invalid request.
Page type is PT_REG and MODIFIED bit is 0.
Page type is PT_TCS or PT_TRIM and PENDING bit is 0 and MODIFIED bit is 1.
The error codes are:
Table 41-46. EACCEPT Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EACCEPT successful
SGX_PAGE_ATTRIBUTES_MISMATCH
The attributes of the target EPC page do not match the expected values
SGX_NOT_TRACKED
The OS did not complete an ETRACK on the target page
Concurrency Restrictions
Table 41-47. Concurrency Restrictions of EACCEPT with Intel® SGX Instructions - 1of 2
Operation
Param
EEXIT
Targ VA
EADD
EBLOCK
SECS Targ SECS Targ SECS
ECRE
ATE
SECS
EDBGRD/
WR
Targ SECS
EENTER/
ERESUME
EEXTEND
EGETKEY
TCS SSA SECS Targ SECS Param SECS
EINIT
SECS
ELDB/ELDU
Targ VA
EPA
SECS VA
Vol. 3D 41-65
SGX INSTRUCTION REFERENCES
Table 41-47. Concurrency Restrictions of EACCEPT with Intel® SGX Instructions - 1of 2
Operation
EEXIT
Targ
EACCE
PT
C
SECINFO
EADD
ECRE
ATE
EBLOCK
EDBGRD/
WR
Y
Y
U
Y
SECS
Y
Y
Y
Y
Y
Y
EENTER/
ERESUME
C
EEXTEND
Y
Y
Y
Y
EINIT
ELDB/ELDU
EPA
Y
U
Y
EGETKEY
U
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Table 41-48. Concurrency Restrictions of EACCEPT with Intel® SGX Instructions - 2 of 2
Operation
Param
EACCE
PT
EREMOVE
ETRA
CK
EREPORT
Targ SECS Param SECS SECS
EWB
SRC VA
EAUG
SECS Targ SECS
EMODPE
Targ
SECI
NFO
Targ
N
Targ
Y
N
Y
SECIN
FO
U
Y
Y
Y
Y
SECS
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EMODPR
Y
SECS
EMODT
Targ
SECS
N
Y
Y
Y
EACCEPT
Targ SECI
NFO
N
Y
Y
Y
Y
Y
EACCEPTCOPY
SECS Targ SRC
N
Y
Y
Operation
Temp Variables in EACCEPT Operational Flow
Name
Type
Size (bits)
Description
TMP_SECS
Effective Address
32/64
Physical address of SECS to which EPC operands belongs.
SCRATCH_SECINFO
SECINFO
512
Scratch storage for holding the contents of DS:RBX.
IF (DS:RBX is not 64Byte Aligned)
THEN #GP(0); FI;
IF (DS:RBX is not within CR_ELRANGE)
THEN #GP(0); FI;
IF (DS:RBX does not resolve within an EPC)
THEN #PF(DS:RBX); FI;
IF ( (EPCM(DS:RBX &~FFFH).VALID = 0) or (EPCM(DS:RBX &~FFFH).R = 0) or (EPCM(DS:RBX &~FFFH).PENDING ≠ 0) or
(EPCM(DS:RBX &~FFFH).MODIFIED ≠ 0) or (EPCM(DS:RBX &~FFFH).BLOCKED ≠ 0) or
(EPCM(DS:RBX &~FFFH).PT ≠ PT_REG) or (EPCM(DS:RBX &~FFFH).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RBX &~FFFH).ENCLAVEADDRESS ≠ (DS:RBX & FFFH)) )
THEN #PF(DS:RBX); FI;
(* Copy 64 bytes of contents *)
SCRATCH_SECINFO DS:RBX;
(* Check for mis-configured SECINFO flags*)
IF (SCRATCH_SECINFO reserved fields are not zero ) )
THEN #GP(0); FI;
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX is not within CR_ELRANGE)
THEN #GP(0); FI;
41-66 Vol. 3D
SECI
NFO
Y
C
U
Y
Y
Y
SGX INSTRUCTION REFERENCES
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
(* Check that the combination of requested PT, PENDING and MODIFIED is legal *)
IF (NOT ( ((SCRATCH_SECINFO.FLAGS.PT is PT_REG) and (SCRATCH_SECINFO.FLAGS.MODIFIED is 0)) or
((SCRATCH_SECINFO.FLAGS.PT is PT_TCS or PT_TRIM) and (SCRATCH_SECINFO.FLAGS.PENDING is 0) and
(SCRATCH_SECINFO.FLAGS.MODIFIED is 1)) ) )
THEN #GP(0); FI
(* Check security attributes of the destination EPC page *)
If ( (EPCM(DS:RCX).VALID is 0) or (EPCM(DS:RCX).BLOCKED is not 0) or
((EPCM(DS:RCX).PT is not PT_REG) and (EPCM(DS:RCX).PT is not PT_TCS) and (EPCM(DS:RCX).PT is not PT_TRIM)) or
(EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS))
THEN #PF((DS:RCX); FI;
(* Check the destination EPC page for concurrency *)
IF ( EPC page in use )
THEN #GP(0); FI;
(* Re-Check security attributes of the destination EPC page *)
IF ( (EPCM(DS:RCX).VALID is 0) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) )
THEN #PF(DS:RCX); FI;
(* Verify that accept request matches current EPC page settings *)
IF ( (EPCM(DS:RCX).ENCLAVEADDRESS ≠ DS:RCX) or (EPCM(DS:RCX).PENDING ≠ SCRATCH_SECINFO.FLAGS.PENDING) or
(EPCM(DS:RCX).MODIFIED ≠ SCRATCH_SECINFO.FLAGS.MODIFIED) or (EPCM(DS:RCX).R ≠ SCRATCH_SECINFO.FLAGS.R) or
(EPCM(DS:RCX).W ≠ SCRATCH_SECINFO.FLAGS.W) or (EPCM(DS:RCX).X ≠ SCRATCH_SECINFO.FLAGS.X) or
(EPCM(DS:RCX).PT ≠ SCRATCH_SECINFO.FLAGS.PT) )
THEN
RFLAGS 1;
RAX SGX_PAGE_ATTRIBUTES_MISMATCH;
GOTO DONE;
FI;
(* Check that all required threads have left enclave *)
IF (Tracking not correct)
THEN
RFLAGS.ZF 1;
RAX SGX_NOT_TRACKED;
GOTO DONE;
FI;
(* Get pointer to the SECS to which the EPC page belongs *)
TMP_SECS = << Obtain physical address of SECS through EPCM(DS:RCX)>>
(* For TCS pages, perform additional checks *)
IF (SCRATCH_SECINFO.FLAGS.PT = PT_TCS)
THEN
IF (DS:RCX.RESERVED ≠ 0) #GP(0); FI;
FI;
(* Check that TCS.FLAGS.DBGOPTIN, TCS stack, and TCS status are correctly initialized *)
IF ( ((DS:RCX).FLAGS.DBGOPTIN is not 0) or ((DS:RCX).CSSA ≥ (DS:RCX).NSSA) or ((DS:RCX).AEP is not 0) or ((DS:RCX).STATE is not 0)
THEN #GP(0); FI;
Vol. 3D 41-67
SGX INSTRUCTION REFERENCES
(* Check consistency of FS & GS Limit *)
IF ( (TMP_SECS.ATTRIBUTES.MODE64BIT is 0) and ((DS:RCX.FSLIMIT & FFFH ≠ FFFH) or (DS:RCX.GSLIMIT & FFFH ≠ FFFH)) )
THEN #GP(0); FI;
(* Clear PENDING/MODIFIED flags to mark accept operation complete *)
EPCM(DS:RCX).PENDING 0;
EPCM(DS:RCX).MODIFIED 0;
EPCM(DS:RCX).PR 0;
(* Clear EAX and ZF to indicate successful completion *)
RFLAGS.ZF 0;
RAX 0;
DONE:
RFLAGS.CF,PF,AF,OF,SF 0;
Flags Affected
Sets ZF if page cannot be accepted, otherwise cleared. Clears CF, PF, AF, OF, SF
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If EPC page has incorrect page type or security attributes.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If EPC page has incorrect page type or security attributes.
41-68 Vol. 3D
SGX INSTRUCTION REFERENCES
EACCEPTCOPY—Initialize a Pending Page
Opcode/
Instruction
Op/En
EAX = 07H
ENCLU[EACCEPTCOPY]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX2
Description
This leaf function initializes a dynamically allocated EPC page
from another page in the EPC.
Instruction Operand Encoding
Op/En
IR
EAX
EACCEPTCOPY (In)
Return Error Code
(Out)
RBX
RCX
RDX
Address of a SECINFO (In)
Address of the destination EPC page (In)
Address of the
source EPC page (In)
Description
This leaf function copies the contents of an existing EPC page into an uninitialized EPC page (created by EAUG).
After initialization, the instruction may also modify the access rights associated with the destination EPC page. This
instruction leaf can only be executed when inside the enclave.
RBX contains the effective address of a SECINFO structure while RCX and RDX each contain the effective address
of an EPC page. The table below provides additional information on the memory parameter of the EACCEPTCOPY
leaf function.
EACCEPTCOPY Memory Parameter Semantics
SECINFO
EPCPAGE (Destination)
EPCPAGE (Source)
Read access permitted by Non Enclave
Read/Write access permitted by Enclave
Read access permitted by Enclave
The instruction faults if any of the following:
EACCEPTCOPY Faulting Conditions
The operands are not properly aligned.
If security attributes of the SECINFO page make the page inaccessible.
The EPC page is locked by another thread.
If security attributes of the source EPC page make the page inaccessible.
The EPC page is not valid.
RBX does not contain an effective address in an EPC page in the running enclave.
SECINFO contains an invalid request.
RCX/RDX does not contain an effective address of an EPC page in the running
enclave.
The error codes are:
Table 41-49. EACCEPTCOPY Return Value in RAX
Error Code (see Table 41-3)
Description
No Error
EACCEPTCOPY successful
SGX_PAGE_ATTRIBUTES_MISMATCH
The attributes of the target EPC page do not match the expected values
Vol. 3D 41-69
SGX INSTRUCTION REFERENCES
Concurrency Restrictions
Table 41-50. Concurrency Restrictions of EACCEPTCOPY with Intel® SGX Instructions - 1of 2
Operation
EEXIT
Param
Targ VA
EADD
ECRE
ATE
EBLOCK
SECS Targ SECS Targ SECS
SECS
EDBGRD/
WR
Targ SECS
EENTER/
ERESUME
EEXTEND
EGETKEY
TCS SSA SECS Targ SECS Param SECS
EINIT
SECS
ELDB/ELDU
Targ VA
EPA
SECS VA
Targ
EACCE
PTCOP
Y
Src
U
Y
U
Y
SECIN
FO
U
Y
U
U
Table 41-51. Concurrency Restrictions of EACCEPTCOPY with Intel® SGX Instructions - 2 of 2
Operation
Param
EREMOVE
EREPORT
ETRA
CK
Targ SECS Param SECS SECS
EWB
SRC VA
EAUG
SECS Targ SECS
EMODPE
Targ
SECI
NFO
Targ
N
Targ
EACCE
PTCOP
Y
EMODPR
SECS
EMODT
Targ
N
SECS
EACCEPT
Targ SECI
NFO
EACCEPTCOPY
SECS Targ SRC
N
SECI
NFO
N
Src
Y
Y
Y
Y
U
Y
Y
SECIN
FO
U
Y
Y
Y
Y
Y
Y
Operation
Temp Variables in EACCEPTCOPY Operational Flow
Name
Type
Size (bits)
Description
SCRATCH_SECINFO
SECINFO
512
Scratch storage for holding the contents of DS:RBX.
IF (DS:RBX is not 64Byte Aligned)
THEN #GP(0); FI;
IF ( (DS:RCX is not 4KByte Aligned) or (DS:RDX is not 4KByte Aligned) )
THEN #GP(0); FI;
IF ((DS:RBX is not within CR_ELRANGE) or (DS:RCX is not within CR_ELRANGE) or (DS:RDX is not within CR_ELRANGE))
THEN #GP(0); FI;
IF (DS:RBX does not resolve within an EPC)
THEN #PF(DS:RBX); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
IF (DS:RDX does not resolve within an EPC)
THEN #PF(DS:RDX); FI;
IF ( (EPCM(DS:RBX &~FFFH).VALID = 0) or (EPCM(DS:RBX &~FFFH).R = 0) or (EPCM(DS:RBX &~FFFH).PENDING ≠ 0) or
(EPCM(DS:RBX &~FFFH).MODIFIED ≠ 0) or (EPCM(DS:RBX &~FFFH).BLOCKED ≠ 0) or (EPCM(DS:RBX &~FFFH).PT ≠ PT_REG) or
(EPCM(DS:RBX &~FFFH).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RBX &~FFFH).ENCLAVEADDRESS ≠ DS:RBX) )
THEN #PF(DS:RBX); FI;
41-70 Vol. 3D
SGX INSTRUCTION REFERENCES
(* Copy 64 bytes of contents *)
SCRATCH_SECINFO DS:RBX;
(* Check for mis-configured SECINFO flags*)
IF ( (SCRATCH_SECINFO reserved fields are not zero ) or ((SCRATCH_SECINFO.FLAGS.R=0) AND(SCRATCH_SECINFO.FLAGS.W≠0 ) or
(SCRATCH_SECINFO.FLAGS.PT is not PT_REG) )
THEN #GP(0); FI;
(* Check security attributes of the source EPC page *)
IF ( (EPCM(DS:RDX).VALID = 0) or (EPCM(DS:RDX).PENDING ≠ 0) or (EPCM(DS:RDX).MODIFIED ≠ 0) or
(EPCM(DS:RDX).BLOCKED ≠ 0) or (EPCM(DS:RDX).PT ≠ PT_REG) or (EPCM(DS:RDX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RDX).ENCLAVEADDRESS ≠ DS:RDX))
THEN #PF(DS:RDX); FI;
(* Check security attributes of the destination EPC page *)
IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PENDING ≠ 1) or (EPCM(DS:RCX).MODIFIED ≠ 0) or
(EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) )
THEN
RFLAGS 1;
RAX SGX_PAGE_ATTRIBUTE_MISMATCH;
GOTO DONE;
FI;
(* Check the destination EPC page for concurrency *)
IF (destination EPC page in use )
THEN #GP(0); FI;
(* Re-Check security attributes of the destination EPC page *)
IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PENDING ≠ 1) or (EPCM(DS:RCX).MODIFIED ≠ 0) or
(EPCM(DS:RCX).R ≠ 1) or (EPCM(DS:RCX).W ≠ 1) or (EPCM(DS:RCX).X ≠ 0) or
(EPCM(DS:RCX).PT ≠ SCRATCH_SECINFO.FLAGS.PT) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RCX).ENCLAVEADDRESS ≠ DS:RCX))
THEN #PF(DS:RCX); FI;
(* Copy 4KBbytes form the source to destination EPC page*)
DS:RCX[32767:0] DS:RDX[32767:0];
(* Update EPCM permissions *)
EPCM(DS:RCX).R EPCM(DS:RCX).R | SCRATCH_SECINFO.FLAGS.R;
EPCM(DS:RCX).W EPCM(DS:RCX).W | SCRATCH_SECINFO.FLAGS.W;
EPCM(DS:RCX).X EPCM(DS:RCX).X | SCRATCH_SECINFO.FLAGS.X;
EPCM(DS:RCX).PENDING 0;
RFLAGS.ZF 0;
RAX 0;
DONE:
RFLAGS.CF,PF,AF,OF,SF 0;
Flags Affected
Sets ZF if page is not modifiable, otherwise cleared. Clears CF, PF, AF, OF, SF
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
Vol. 3D 41-71
SGX INSTRUCTION REFERENCES
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If EPC page has incorrect page type or security attributes.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
If a memory operand is not an EPC page.
If EPC page has incorrect page type or security attributes.
41-72 Vol. 3D
SGX INSTRUCTION REFERENCES
EENTER—Enters an Enclave
Opcode/
Instruction
Op/En
EAX = 02H
ENCLU[EENTER]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function is used to enter an enclave.
Instruction Operand Encoding
Op/En
IR
EAX
EENTER (In)
RBX
Content of RBX.CSSA
(Out)
Address of a TCS (In)
RCX
Address of AEP (In)
Address of IP following
EENTER (Out)
Description
The ENCLU[EENTER] instruction transfers execution to an enclave. At the end of the instruction, the logical
processor is executing in enclave mode at the RIP computed as EnclaveBase + TCS.OENTRY. If the target address
is not within the CS segment (32-bit) or is not canonical (64-bit), a #GP(0) results.
EENTER Memory Parameter Semantics
TCS
Enclave access
EENTER is a serializing instruction. The instruction faults if any of the following occurs:
Address in RBX is not properly aligned.
Any TCS.FLAGS’s must-be-zero bit is not zero.
TCS pointed to by RBX is not valid or available or
locked.
Current 32/64 mode does not match the enclave mode in
SECS.ATTRIBUTES.MODE64.
The SECS is in use.
Either of TCS-specified FS and GS segment is not a subsets of the current DS
segment.
Any one of DS, ES, CS, SS is not zero.
If XSAVE available, CR4.OSXSAVE = 0, but SECS.ATTRIBUTES.XFRM ≠ 3.
CR4.OSFXSR ≠ 1.
If CR4.OSXSAVE = 1, SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
The following operations are performed by EENTER:
•
RSP and RBP are saved in the current SSA frame on EENTER and are automatically restored on EEXIT or
interrupt.
•
The AEP contained in RCX is stored into the TCS for use by AEXs.FS and GS (including hidden portions) are
saved and new values are constructed using TCS.OFSBASE/GSBASE (32 and 64-bit mode) and
TCS.OFSLIMIT/GSLIMIT (32-bit mode only). The resulting segments must be a subset of the DS segment.
•
If CR4.OSXSAVE == 1, XCR0 is saved and replaced by SECS.ATTRIBUTES.XFRM. The effect of RFLAGS.TF
depends on whether the enclave entry is opt-in or opt-out (see Section 43.1.2):
— On opt-out entry, TF is saved and cleared (it is restored on EEXIT or AEX). Any attempt to set TF via a POPF
instruction while inside the enclave clears TF (see Section 43.2.5).
— On opt-in entry, a single-step debug exception is pended on the instruction boundary immediately after
EENTER (see Section 43.2.2).
•
All code breakpoints that do not overlap with ELRANGE are also suppressed. If the entry is an opt-out entry, all
code and data breakpoints that overlap with the ELRANGE are suppressed.
•
On opt-out entry, a number of performance monitoring counters and behaviors are modified or suppressed
(see Section 43.2.3):
Vol. 3D 41-73
SGX INSTRUCTION REFERENCES
— All performance monitoring activity on the current thread is suppressed except for incrementing and firing
of FIXED_CTR1 and FIXED_CTR2.
— PEBS is suppressed.
— AnyThread counting on other threads is demoted to MyThread mode and IA32_PERF_GLOBAL_STATUS[60]
on that thread is set
— If the opt-out entry on a hardware thread results in suppression of any performance monitoring, then the
processor sets IA32_PERF_GLOBAL_STATUS[60] and IA32_PERF_GLOBAL_STATUS[63].
Concurrency Restrictions
Table 41-52. Concurrency Restrictions of EENTER with Intel® SGX Instructions - 1of 2
Operation
EENTE
R
EEXIT
Param
Targ VA
TCS
N
EADD
ECRE
ATE
EBLOCK
SECS Targ SECS Targ SECS
N
SECS
N
U
SSA
SECS
Y
Y
N
Y
Y
Y
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
Targ SECS
TCS SSA SECS Targ SECS Param SECS
Y
N
Y
Y
U
Y
Y
Y
Y
EINIT
SECS
ELDB/ELDU
Targ VA
EPA
SECS VA
N
N
U
Y
Y
N
Y
Y
N
Y
Y
Y
Y
Table 41-53. Concurrency Restrictions of EENTER with Intel® SGX Instructions - 2 of 2
Operation
EENTE
R
EREMOVE
EREPORT
ETRA
CK
EWB
Param
Targ SECS Param SECS SECS
SRC VA
TCS
N
N
SSA
SECS
EAUG
SECS Targ SECS
Y
Y
Y
Y
Y
Targ
SECI
NFO
Y
U
Y
Y
EMODPR
Targ
SECS
N
Y
Y
Y
EMODT
Targ
SECS
EACCEPT
Targ SECI
NFO
EACCEPTCOPY
SECS Targ SRC
SECI
NFO
N
U
Y
EMODPE
Y
Y
Y
Y
Y
Y
U
Y
Y
Y
U
U
Y
Y
Operation
Temp Variables in EENTER Operational Flow
Name
Type
Size (Bits)
Description
TMP_FSBASE
Effective Address
32/64
Proposed base address for FS segment.
TMP_GSBASE
Effective Address
32/64
Proposed base address for FS segment.
TMP_FSLIMIT
Effective Address
32/64
Highest legal address in proposed FS segment.
TMP_GSLIMIT
Effective Address
32/64
Highest legal address in proposed GS segment.
TMP_XSIZE
integer
64
Size of XSAVE area based on SECS.ATTRIBUTES.XFRM.
TMP_SSA_PAGE
Effective Address
32/64
Pointer used to iterate over the SSA pages in the current frame.
TMP_GPR
Effective Address
32/64
Address of the GPR area within the current SSA frame.
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
(* Make sure DS is usable, expand up *)
IF (TMP_MODE64 = 0 and (DS not usable or ( ( DS[S] = 1) and (DS[bit 11] = 0) and DS[bit 10] = 1) ) ) )
THEN #GP(0); FI;
(* Check that CS, SS, DS, ES.base is 0 *)
IF (TMP_MODE64 = 0)
THEN
IF(CS.base ≠ 0 or DS.base ≠ 0) #GP(0); FI;
41-74 Vol. 3D
SGX INSTRUCTION REFERENCES
IF(ES usable and ES.base ≠ 0) #GP(0); FI;
IF(SS usable and SS.base ≠ 0) #GP(0); FI;
IF(SS usable and SS.B = 0) #GP(0); FI;
FI;
IF (DS:RBX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RBX does not resolve within an EPC)
THEN #PF(DS:RBX); FI;
(* Check AEP is canonical*)
IF (TMP_MODE64 = 1 and (DS:RCX is not canonical) )
THEN #GP(0); FI;
(* Check concurrency of TCS operation*)
IF (Other Intel SGX instructions is operating on TCS)
THEN #GP(0); FI;
(* TCS verification *)
IF (EPCM(DS:RBX).VALID = 0)
THEN #PF(DS:RBX); FI;
IF (EPCM(DS:RBX).BLOCKED = 1)
THEN #PF(DS:RBX); FI;
IF ( (EPCM(DS:RBX).ENCLAVEADDRESS ≠ DS:RBX) or (EPCM(DS:RBX).PT ≠ PT_TCS) )
THEN #PF(DS:RBX); FI;
IF ((EPCM(DS:RBX).PENDING = 1) or (EPCM(DS:RBX).MODIFIED = 1))
THEN #PF(DS:RBX); FI;
IF ( (DS:RBX).OSSA is not 4KByte Aligned)
THEN #GP(0); FI;
(* Check proposed FS and GS *)
IF ( ( (DS:RBX).OFSBASE is not 4KByte Aligned) or ( (DS:RBX).OGSBASE is not 4KByte Aligned) )
THEN #GP(0); FI;
(* Get the SECS for the enclave in which the TCS resides *)
TMP_SECS Address of SECS for TCS;
(* Check proposed FS/GS segments fall within DS *)
IF (TMP_MODE64 = 0)
THEN
TMP_FSBASE (DS:RBX).OFSBASE + TMP_SECS.BASEADDR;
TMP_FSLIMIT (DS:RBX).OFSBASE + TMP_SECS.BASEADDR + (DS:RBX).FSLIMIT;
TMP_GSBASE (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;
TMP_GSLIMIT (DS:RBX).OGSBASE + TMP_SECS.BASEADDR + (DS:RBX).GSLIMIT;
(* if FS wrap-around, make sure DS has no holes*)
IF (TMP_FSLIMIT < TMP_FSBASE)
THEN
IF (DS.limit < 4GB) THEN #GP(0); FI;
ELSE
Vol. 3D 41-75
SGX INSTRUCTION REFERENCES
IF (TMP_FSLIMIT > DS.limit) THEN #GP(0); FI;
FI;
(* if GS wrap-around, make sure DS has no holes*)
IF (TMP_GSLIMIT < TMP_GSBASE)
THEN
IF (DS.limit < 4GB) THEN #GP(0); FI;
ELSE
IF (TMP_GSLIMIT > DS.limit) THEN #GP(0); FI;
FI;
ELSE
TMP_FSBASE (DS:RBX).OFSBASE + TMP_SECS.BASEADDR;
TMP_GSBASE (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;
IF ( (TMP_FSBASE is not canonical) or (TMP_GSBASE is not canonical))
THEN #GP(0); FI;
FI;
(* Ensure that the FLAGS field in the TCS does not have any reserved bits set *)
IF ( ( (DS:RBX).FLAGS & & FFFFFFFFFFFFFFFEH) ≠ 0)
THEN #GP(0); FI;
(* SECS must exist and enclave must have previously been EINITted *)
IF (the enclave is not already initialized)
THEN #GP(0); FI;
(* make sure the logical processor’s operating mode matches the enclave *)
IF ( (TMP_MODE64 ≠ TMP_SECS.ATTRIBUTES.MODE64BIT) )
THEN #GP(0); FI;
IF (CR4.OSFXSR = 0)
THEN #GP(0); FI;
(* Check for legal values of SECS.ATTRIBUTES.XFRM *)
IF (CR4.OSXSAVE = 0)
THEN
IF (TMP_SECS.ATTRIBUES.XFRM ≠ 03H) THEN #GP(0); FI;
ELSE
IF ( (TMP_SECS.ATTRIBUES.XFRM & XCR0) ≠ TMP_SECS.ATTRIBUES.XFRM) THEN #GP(0); FI;
FI;
(* Make sure the SSA contains at least one more frame *)
IF ( (DS:RBX).CSSA ≥ (DS:RBX).NSSA)
THEN #GP(0); FI;
(* Compute linear address of SSA frame *)
TMP_SSA (DS:RBX).OSSA + TMP_SECS.BASEADDR + 4096 * TMP_SECS.SSAFRAMESIZE * (DS:RBX).CSSA;
TMP_XSIZE compute_XSAVE_frame_size(TMP_SECS.ATTRIBUTES.XFRM);
FOR EACH TMP_SSA_PAGE = TMP_SSA to TMP_SSA + TMP_XSIZE
(* Check page is read/write accessible *)
Check that DS:TMP_SSA_PAGE is read/write accessible;
If a fault occurs, release locks, abort and deliver that fault;
IF (DS:TMP_SSA_PAGE does not resolve to EPC page)
THEN #PF(DS:TMP_SSA_PAGE); FI;
41-76 Vol. 3D
SGX INSTRUCTION REFERENCES
IF (EPCM(DS:TMP_SSA_PAGE).VALID = 0)
THEN #PF(DS:TMP_SSA_PAGE); FI;
IF (EPCM(DS:TMP_SSA_PAGE).BLOCKED = 1)
THEN #PF(DS:TMP_SSA_PAGE); FI;
IF ((EPCM(DS:TMP_SSA_PAGE).PENDING = 1) or (EPCM(DS:TMP_SSA_PAGE).MODIFIED = 1))
THEN #PF(DS:TMP_SSA_PAGE); FI;
IF ( ( EPCM(DS:TMP_SSA_PAGE).ENCLAVEADDRESS ≠ DS:TMPSSA_PAGE) or (EPCM(DS:TMP_SSA_PAGE).PT ≠ PT_REG) or
(EPCM(DS:TMP_SSA_PAGE).ENCLAVESECS ≠ EPCM(DS:RBX).ENCLAVESECS) or
(EPCM(DS:TMP_SECS).R = 0) or (EPCM(DS:TMP_SECS).W = 0) )
THEN #PF(DS:TMP_SSA_PAGE); FI;
CR_XSAVE_PAGE_n Physical_Address(DS:TMP_SSA_PAGE);
ENDFOR
(* Compute address of GPR area*)
TMP_GPR TMP_SSA + 4096 * DS:TMP_SECS.SSAFRAMESIZE -- sizeof(GPRSGX_AREA);
If a fault occurs; release locks, abort and deliver that fault;
IF (DS:TMP_GPR does not resolve to EPC page)
THEN #PF(DS:TMP_GPR); FI;
IF (EPCM(DS:TMP_GPR).VALID = 0)
THEN #PF(DS:TMP_GPR); FI;
IF (EPCM(DS:TMP_GPR).BLOCKED = 1)
THEN #PF(DS:TMP_GPR); FI;
IF ((EPCM(DS:TMP_GPR).PENDING = 1) or (EPCM(DS:TMP_GPR).MODIFIED = 1))
THEN #PF(DS:TMP_GPR); FI;
IF ( ( EPCM(DS:TMP_GPR).ENCLAVEADDRESS ≠ DS:TMP_GPR) or (EPCM(DS:TMP_GPR).PT ≠ PT_REG) or
(EPCM(DS:TMP_GPR).ENCLAVESECS EPCM(DS:RBX).ENCLAVESECS) or
(EPCM(DS:TMP_GPR).R = 0) or (EPCM(DS:TMP_GPR).W = 0) )
THEN #PF(DS:TMP_GPR); FI;
IF (TMP_MODE64 = 0)
THEN
IF (TMP_GPR + (GPR_SIZE -1) is not in DS segment) THEN #GP(0); FI;
FI;
CR_GPR_PA Physical_Address (DS: TMP_GPR);
(* Validate TCS.OENTRY *)
TMP_TARGET (DS:RBX).OENTRY + TMP_SECS.BASEADDR;
IF (TMP_MODE64 = 1)
THEN
IF (TMP_TARGET is not canonical) THEN #GP(0); FI;
ELSE
IF (TMP_TARGET > CS limit) THEN #GP(0); FI;
FI;
(* Ensure the enclave is not already active and this thread is the only one using the TCS*)
IF (DS:RBX.STATE = ACTIVE))
THEN #GP(0); FI;
CR_ENCALVE_MODE 1;
CR_ACTIVE_SECS TMP_SECS;
CR_ELRANGE (TMPSECS.BASEADDR, TMP_SECS.SIZE);
Vol. 3D 41-77
SGX INSTRUCTION REFERENCES
(* Save state for possible AEXs *)
CR_TCS_PA Physical_Address (DS:RBX);
CR_TCS_LA RBX;
CR_TCS_LA.AEP RCX;
(* Save the hidden portions of FS and GS *)
CR_SAVE_FS_selector FS.selector;
CR_SAVE_FS_base FS.base;
CR_SAVE_FS_limit FS.limit;
CR_SAVE_FS_access_rights FS.access_rights;
CR_SAVE_GS_selector GS.selector;
CR_SAVE_GS_base GS.base;
CR_SAVE_GS_limit GS.limit;
CR_SAVE_GS_access_rights GS.access_rights;
(* If XSAVE is enabled, save XCR0 and replace it with SECS.ATTRIBUTES.XFRM*)
IF (CR4.OSXSAVE = 1)
CR_SAVE_XCR0 XCR0;
XCR0 TMP_SECS.ATTRIBUTES.XFRM;
FI;
(* Set CR_ENCLAVE_ENTRY_IP *)
CR_ENCLAVE_ENTRY_IP CRIP”
RIP NRIP;
RAX (DS:RBX).CSSA;
(* Save the outside RSP and RBP so they can be restored on interrupt or EEXIT *)
DS:TMP_SSA.U_RSP RSP;
DS:TMP_SSA.U_RBP RBP;
(* Do the FS/GS swap *)
FS.base TMP_FSBASE;
FS.limit DS:RBX.FSLIMIT;
FS.type 0001b;
FS.W DS.W;
FS.S 1;
FS.DPL DS.DPL;
FS.G 1;
FS.B 1;
FS.P 1;
FS.AVL DS.AVL;
FS.L DS.L;
FS.unusable 0;
FS.selector 0BH;
GS.base TMP_GSBASE;
GS.limit DS:RBX.GSLIMIT;
GS.type 0001b;
GS.W DS.W;
GS.S 1;
GS.DPL DS.DPL;
GS.G 1;
GS.B 1;
GS.P 1;
GS.AVL DS.AVL;
41-78 Vol. 3D
SGX INSTRUCTION REFERENCES
GS.L DS.L;
GS.unusable 0;
GS.selector 0BH;
CR_DBGOPTIN TSC.FLAGS.DBGOPTIN;
Suppress_all_code_breakpoints_that_are_outside_ELRANGE;
IF (CR_DBGOPTIN = 0)
THEN
Suppress_all_code_breakpoints_that_overlap_with_ELRANGE;
CR_SAVE_TF RFLAGS.TF;
RFLAGS.TF 0;
Suppress_monitor_trap_flag for the source of the execution of the enclave;
Suppress any pending debug exceptions;
Suppress any pending MTF VM exit;
ELSE
IF RFLAGS.TF = 1
THEN pend a single-step #DB at the end of EENTER; FI;
IF the “monitor trap flag” VM-execution control is set
THEN pend an MTF VM exit at the end of EENTER; FI;
FI;
Flush_linear_context;
Allow_front_end_to_begin_fetch_at_new_RIP;
Flags Affected
RFLAGS.TF is cleared on opt-out entry
Protected Mode Exceptions
#GP(0)
If DS:RBX is not page aligned.
If the enclave is not initialized.
If part or all of the FS or GS segment specified by TCS is outside the DS segment or not properly aligned.
If the thread is not in the INACTIVE state.
If CS, DS, ES or SS bases are not all zero.
If executed in enclave mode.
If any reserved field in the TCS FLAG is set.
If the target address is not within the CS segment.
If CR4.OSFXSR = 0.
If CR4.OSXSAVE = 0 and SECS.ATTRIBUTES.XFRM ≠ 3.
If CR4.OSXSAVE = 1and SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
#PF(error code)
If a page fault occurs in accessing memory.
If DS:RBX does not point to a valid TCS.
If one or more pages of the current SSA frame are not readable/writable, or do not resolve to
a valid PT_REG EPC page.
64-Bit Mode Exceptions
#GP(0)
If DS:RBX is not page aligned.
If the enclave is not initialized.
If the thread is not in the INACTIVE state.
If CS, DS, ES or SS bases are not all zero.
Vol. 3D 41-79
SGX INSTRUCTION REFERENCES
If executed in enclave mode.
If part or all of the FS or GS segment specified by TCS is outside the DS segment or not properly aligned.
If the target address is not canonical.
If CR4.OSFXSR = 0.
If CR4.OSXSAVE = 0 and SECS.ATTRIBUTES.XFRM ≠ 3.
If CR4.OSXSAVE = 1and SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
#PF(error code)
If a page fault occurs in accessing memory operands.
If DS:RBX does not point to a valid TCS.
If one or more pages of the current SSA frame are not readable/writable, or do not resolve to
a valid PT_REG EPC page.
41-80 Vol. 3D
SGX INSTRUCTION REFERENCES
EEXIT—Exits an Enclave
Opcode/
Instruction
Op/En
EAX = 04H
ENCLU[EEXIT]
IR
Description
CPUID
Feature
Flag
SGX1
64/32
bit Mode
Support
V/V
This leaf function is used to exit an enclave.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EEXIT (In)
Target address outside the enclave (In)
Address of the current AEP (In)
Description
The ENCLU[EEXIT] instruction exits the currently executing enclave and branches to the location specified in RBX.
RCX receives the current AEP. If RBX is not within the CS (32-bit mode) or is not canonical (64-bit mode) a #GP(0)
results.
EEXIT Memory Parameter Semantics
Target Address
Non-Enclave read and execute access
If RBX specifies an address that is inside the enclave, the instruction will complete normally. The fetch of the next
instruction will occur in non-enclave mode, but will attempt to fetch from inside the enclave. This has the effect of
abort page semantics on the next destination.
If secrets are contained in any registers, it is responsibility of enclave software to clear those registers.
If XCR0 was modified on enclave entry, it is restored to the value it had at the time of the most recent EENTER or
ERESUME.
If the enclave is opt-out, RFLAGS.TF is loaded from the value previously saved on EENTER.
Code and data breakpoints are unsuppressed.
Performance monitoring counters are unsuppressed.
Concurrency Restrictions
Table 41-54. Concurrency Restrictions of EEXIT with Intel® SGX Instructions - 1of 2
Operation
Param
EEXIT
EEXIT
Targ VA
EADD
SECS Targ SECS Targ SECS
TCS
U
SSA
SECS
Y
ECRE
ATE
EBLOCK
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EPA
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
SECS
Targ VA
SECS VA
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
U
Y
Y
U
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Table 41-55. Concurrency Restrictions of EEXIT with Intel® SGX Instructions - 2 of 2
Operation
EEXIT
EREMOVE
EREPORT
ETRA
CK
Para
m
Targ SECS Param SECS SECS
TCS
Y
SSA
Y
SECS
Y
Y
Y
Y
Y
EWB
SRC VA
Y
Y
Y
Y
Y
Y
Y
Y
Y
EAUG
SECS Targ SECS
Y
EMODPE
EMODPR
Targ
SECI
NFO
Targ
Y
Y
Y
Y
Y
Y
Y
Y
U
Y
Y
Y
Y
Y
Y
SECS
EMODT
Targ
SECS
Y
Y
Y
Y
Y
EACCEPT
Targ SECI
NFO
Y
Y
Y
U
Y
Y
EACCEPTCOPY
SECS Targ SRC
Y
SECI
NFO
Y
Y
Y
Y
U
U
Y
Y
Y
Vol. 3D 41-81
SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EEXIT Operational Flow
Name
Type
Size (Bits)
Description
TMP_RIP
Effective Address
32/64
Saved copy of CRIP for use when creating LBR.
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
IF (TMP_MODE64 = 1)
THEN
IF (RBX is not canonical) THEN #GP(0); FI;
ELSE
IF (RBX > CS limit) THEN #GP(0); FI;
FI;
TMP_RIP CRIP;
RIP RBX;
(* Return current AEP in RCX *)
RCX CR_TCS_PA.AEP;
(* Do the FS/GS swap *)
FS.selector CR_SAVE_FS.selector;
FS.base CR_SAVE_FS.base;
FS.limit CR_SAVE_FS.limit;
FS.access_rights CR_SAVE_FS.access_rights;
GS.selector CR_SAVE_GS.selector;
GS.base CR_SAVE_GS.base;
GS.limit CR_SAVE_GS.limit;
GS.access_rights CR_SAVE_GS.access_rights;
(* Restore XCR0 if needed *)
IF (CR4.OSXSAVE = 1)
XCR0 CR_SAVE__XCR0;
FI;
Unsuppress_all_code_breakpoints_that_are_outside_ELRANGE;
IF (CR_DBGOPTIN = 0)
THEN
UnSuppress_all_code_breakpoints_that_overlap_with_ELRANGE;
Restore suppressed breakpoint matches;
RFLAGS.TF CR_SAVE_TF;
UnSuppress_montior_trap_flag;
UnSuppress_LBR_Generation;
UnSuppress_performance monitoring_activity;
Restore performance monitoring counter AnyThread demotion to MyThread in enclave back to AnyThread
FI;
IF RFLAGS.TF = 1
THEN Pend Single-Step #DB at the end of EEXIT;
FI;
41-82 Vol. 3D
SGX INSTRUCTION REFERENCES
IF the “monitor trap flag” VM-execution control is set
THEN pend a MTF VM exit at the end of EEXIT;
FI;
CR_ENCLAVE_MODE 0;
CR_TCS_PA.STATE INACTIVE;
(* Assure consistent translations *)
Flush_linear_context;
Flags Affected
RFLAGS.TF is restored from the value previously saved in EENTER or ERESUME.
Protected Mode Exceptions
#GP(0)
If executed outside an enclave.
If RBX is outside the CS segment.
#PF(error code)
If a page fault occurs in accessing memory.
64-Bit Mode Exceptions
#GP(0)
If executed outside an enclave.
#PF(error code)
If a page fault occurs in accessing memory operands.
If RBX is not canonical.
Vol. 3D 41-83
SGX INSTRUCTION REFERENCES
EGETKEY—Retrieves a Cryptographic Key
Opcode/
Instruction
Op/En
EAX = 04H
ENCLU[EGETKEY]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function retrieves a cryptographic key.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EGETKEY (In)
Address to a KEYREQUEST (In)
Address of the OUTPUTDATA (In)
Description
The ENCLU[EGETKEY] instruction returns a 128-bit secret key from the processor specific key hierarchy. The
register RBX contains the effective address of a KEYREQUEST structure, which the instruction interprets to determine the key being requested. The Requesting Keys section below provides a description of the keys that can be
requested. The RCX register contains the effective address where the key will be returned. Both the addresses in
RBX & RCX should be locations inside the enclave.
EGETKEY derives keys using a processor unique value to create a specific key based on a number of possible inputs.
This instruction leaf can only be executed inside an enclave.
EEGETKEY Memory Parameter Semantics
KEYREQUEST
OUTPUTDATA
Enclave read access
Enclave write access
After validating the operands, the instruction determines which key is to be produced and performs the following
actions:
•
•
•
The instruction assembles the derivation data for the key based on the Table 41-56
Computes derived key using the derivation data and package specific value
Outputs the calculated key to the address in RCX
The instruction fails with #GP(0) if the operands are not properly aligned. Successful completion of the instruction
will clear RFLAGS.{ZF, CF, AF, OF, SF, PF}. The instruction returns an error code if the user tries to request a key
based on an invalid CPUSVN or ISVSVN (when the user request is accepted, see the table below), requests a key
for which it has not been granted the attribute to request, or requests a key that is not supported by the hardware.
These checks may be performed in any order. Thus, an indication by error number of one cause (for example,
invalid attribute) does not imply that there are not also other errors. Different processors may thus give different
error numbers for the same Enclave. The correctness of software should not rely on the order resulting from the
checks documented in this section. In such cases the ZF flag is set and the corresponding error bit
(SGX_INVALID_SVN, SGX_INVALID_ATTRIBUTE, SGX_INVALID_KEYNAME) is set in RAX and the data at the
address specified by RCX is unmodified.
Requesting Keys
The KEYREQUEST structure (see Section 38.17.1) identifies the key to be provided. The Keyrequest.KeyName field
identifies which type of key is requested.
Deriving Keys
Key derivation is based on a combination of the enclave specific values (see Table 41-56) and a processor key.
Depending on the key being requested a field may either be included by definition or the value may be included
from the KeyRequest. A “yes” in Table 41-56 indicates the value for the field is included from its default location,
identified in the source row, and a “request” indicates the values for the field is included from its corresponding
KeyRequest field.
41-84 Vol. 3D
SGX INSTRUCTION REFERENCES
Table 41-56. Key Derivation
Owner
Epoch
Key Name Attributes
CPU SVN
ISV SVN
Key
Y
CSR_SEO Y CPUSVN
Dependent SECS.ATTRIBUTE WNEREP Register;
Constant
S and
OCH
SECS.MISCSELECT;
Source
RAttribMask &
SECS.ATTRIBUTE
S and
SECS.MISCSELECT;
ISV
PRODID MRENCLAVE MRSIGNER RAND
R
SECS.
Req.ISVSVN; ISVID
SECS.
SECS.
Req.
MRENCLAVE MRSIGNER KEYID
R
Req.CPUSVN;
EINITTOKEN Yes
Request
Yes
Request
Request
Yes
No
Yes
Request
Report
Yes
Yes
Yes
Yes
No
No
Yes
No
Request
Seal
Yes
Request
Yes
Request
Request
Yes
Request
Request
Request
Provisioning Yes
Request
No
Request
Request
Yes
No
Yes
Yes
Provisioning Yes
Seal
Request
No
Request
Request
Yes
No
Yes
Yes
Keys that permit the specification of a CPU or ISV's code's SVNs have additional requirements. The caller may not
request a key for an SVN beyond the current CPU or ISV SVN, respectively.
Several keys are access controlled. Access to the Provisioning Key and Provisioning Seal key requires the enclave's
ATTRIBUTES.PROVISIONKEY be set. The EINITTOKEN Key requires ATTRIBUTES.EINITTOKENKEY be set and
SECS.MRSIGNER equal IA32_SGXLEPUBKEYHASH.
Some keys are derived based on a hardcode PKCS padding constant (352 byte string):
HARDCODED_PKCS1_5_PADDING[15:0] 0100H;
HARDCODED_PKCS1_5_PADDING[2655:16] SignExtend330Byte(-1); // 330 bytes of 0FFH
HARDCODED_PKCS1_5_PADDING[2815:2656] 2004000501020403650148866009060D30313000H;
The error codes are:
Table 41-57. EGETKEY Return Value in RAX
Error Code (see Table 41-3)
Value
No Error
0
Description
EGETKEY successful
SGX_INVALID_ATTRIBUTE
The KEYREQUEST contains a KEYNAME for which the enclave is not
authorized
SGX_INVALID_CPUSVN
If KEYREQUEST.CPUSVN is an unsupported platforms CPUSVN value
SGX_INVALID_ISVSVN
If KEYREQUEST.ISVSVN is greater than the enclave's ISV_SVN
SGX_INVALID_KEYNAME
If KEYREQUEST.KEYNAME is an unsupported value
Concurrency Restrictions
Table 41-58. Concurrency Restrictions of EGETKEY with Other Intel® SGX Operations 1 of 2
Operation
Param
EGETKEY
Param
SECS
EEXIT
TCS SSA
EADD
SECS Targ SECS
EBLOCK
Targ SECS
ECRE
ATE
SECS
U
EDBGRD/
WR
Targ SECS
EENTER/
ERESUME
Y
Y
Y
Y
Y
Y
U
Y
EGETKEY
TCS SSA SECS Targ SECS Param SECS
Y
Y
EEXTEND
Y
Y
EINIT
ELDB/ELDU
EPA
SECS
Targ VA
SECS VA
Y
Y
Y
U
Y
Y
Y
Y
Y
Y
Y
Vol. 3D 41-85
SGX INSTRUCTION REFERENCES
Table 41-59. Concurrency Restrictions of EGETKEY with Other Intel® SGX Operations 2 of 2
Operation
Param
EGETKEY
EREMOVE
Targ SECS Param SECS
ETRACK
EWB
EAUG
Y
Y
Y
Y
EMODPE
EMODPR
SECS
SRC
VA
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Y
Y
Y
Y
U
Param
SECS
EREPORT
Y
Y
Y
U
Y
Y
Y
Y
EMODT
Targ SEC
S
Y
Y
EACCEPT
Targ SECI
NFO
Y
U
Y
Y
EACCEPTCOPY
SECS Targ SR
C
Y
Y
Operation
Temp Variables in EGETKEY Operational Flow
Name
Type
Size (Bits)
Description
TMP_CURRENTSECS
Address of the SECS for the currently executing enclave.
TMP_KEYDEPENDENCIES
Temp space for key derivation.
TMP_ATTRIBUTES
128
Temp Space for the calculation of the sealable Attributes.
TMP_OUTPUTKEY
128
Temp Space for the calculation of the key.
(* Make sure KEYREQUEST is properly aligned and inside the current enclave *)
IF ( (DS:RBX is not 128Byte aligned) or (DS:RBX is within CR_ELRANGE) )
THEN #GP(0); FI;
(* Make sure DS:RBX is an EPC address and the EPC page is valid *)
IF ( (DS:RBX does not resolve to an EPC address) or (EPCM(DS:RBX).VALID = 0) )
THEN #PF(DS:RBX); FI;
IF (EPCM(DS:RBX).BLOCKED = 1) )
THEN #PF(DS:RBX); FI;
(* Check page parameters for correctness *)
IF ( (EPCM(DS:RBX).PT ≠ PT_REG) or (EPCM(DS:RBX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or (EPCM(DS:RBX).PENDING = 1) or
(EPCM(DS:RBX).MODIFIED = 1) or (EPCM(DS:RBX).ENCLAVEADDRESS ≠ (DS:RBX & ~0FFFH) ) or (EPCM(DS:RBX).R = 0) )
THEN #PF(DS:RBX);
FI;
(* Make sure OUTPUTDATA is properly aligned and inside the current enclave *)
IF ( (DS:RCX is not 16Byte aligned) or (DS:RCX is within CR_ELRANGE) )
THEN #GP(0); FI;
(* Make sure DS:RCX is an EPC address and the EPC page is valid *)
IF ( (DS:RCX does not resolve to an EPC address) or (EPCM(DS:RCX).VALID = 0) )
THEN #PF(DS:RCX); FI;
IF (EPCM(DS:RCX).BLOCKED = 1) )
THEN #PF(DS:RCX); FI;
(* Check page parameters for correctness *)
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or (EPCM(DS:RCX).PENDING = 1) or
(EPCM(DS:RCX).MODIFIED = 1) or (EPCM(DS:RCX).ENCLAVEADDRESS ≠ (DS:RCX & ~0FFFH) ) or (EPCM(DS:RCX).W = 0) )
THEN #PF(DS:RCX);
FI;
41-86 Vol. 3D
SECI
NFO
Y
U
Y
Y
SGX INSTRUCTION REFERENCES
(* Verify RESERVED spaces in KEYREQUEST are valid *)
IF ( (DS:RBX).RESERVED ≠ 0) or (DS:RBX.KEYPOLICY.RESERVED ≠ 0) )
THEN #GP(0); FI;
TMP_CURRENTSECS CR_ACTIVE_SECS;
(* Determine which enclave attributes that must be included in the key. Attributes that must always be include INIT & DEBUG *)
REQUIRED_SEALING_MASK[127:0] 00000000 00000000 00000000 00000003H;
TMP_ATTRIBUTES (DS:RBX.ATTRIBUTEMASK | REQUIRED_SEALING_MASK) & TMP_CURRENTSECS.ATTRIBUTES;
(* Compute MISCSELECT fields to be included *)
TMP_MISCSELECT DS:RBX.MISCMASK & TMP_CURRENTSECS.MISCSELECT
CASE (DS:RBX.KEYNAME)
SEAL_KEY:
IF (DS:RBX.CPUSVN is beyond current CPU configuration)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_CPUSVN;
GOTO EXIT;
FI;
IF (DS:RBX.ISVSVN > TMP_CURRENTSECS.ISVSVN)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ISVSVN;
GOTO EXIT;
FI;
// Include enclave identity?
TMP_MRENCLAVE 0;
IF (DS:RBX.KEYPOLICY.MRENCLAVE = 1)
THEN TMP_MRENCLAVE TMP_CURRENTSECS.MRENCLAVE;
FI;
// Include enclave author?
TMP_MRSIGNER 0;
IF (DS:RBX.KEYPOLICY.MRSIGNER = 1)
THEN TMP_MRSIGNER TMP_CURRENTSECS.MRSIGNER;
FI;
//Determine values key is based on
TMP_KEYDEPENDENCIES.KEYNAME SEAL_KEY;
TMP_KEYDEPENDENCIES.ISVPRODID TMP_CURRENTSECS.ISVPRODID;
TMP_KEYDEPENDENCIES.ISVSVN DS:RBX.ISVSVN;
TMP_KEYDEPENDENCIES.OWNEREPOCH CSR_SEOWNEREPOCH;
TMP_KEYDEPENDENCIES.ATTRIBUTES TMP_ATTRIBUTES;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK DS:RBX.ATTRIBUTEMASK;
TMP_KEYDEPENDENCIES.MRENCLAVE TMP_MRENCLAVE;
TMP_KEYDEPENDENCIES.MRSIGNER TMP_MRSIGNER;
TMP_KEYDEPENDENCIES.KEYID DS:RBX.KEYID;
TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES CR_SEAL_FUSES;
TMP_KEYDEPENDENCIES.CPUSVN DS:RBX.CPUSVN;
TMP_KEYDEPENDENCIES.PADDING TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT TMP_MISCSELECT;
TMP_KEYDEPENDENCIES.MISCMASK ~DS:RBX.MISCMASK;
BREAK;
REPORT_KEY:
Vol. 3D 41-87
SGX INSTRUCTION REFERENCES
//Determine values key is based on
TMP_KEYDEPENDENCIES.KEYNAME REPORT_KEY;
TMP_KEYDEPENDENCIES.ISVPRODID 0;
TMP_KEYDEPENDENCIES.ISVSVN 0;
TMP_KEYDEPENDENCIES.OWNEREPOCH CSR_SEOWNEREPOCH;
TMP_KEYDEPENDENCIES.ATTRIBUTES TMP_CURRENTSECS.ATTRIBUTES;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK 0;
TMP_KEYDEPENDENCIES.MRENCLAVE TMP_CURRENTSECS.MRENCLAVE;
TMP_KEYDEPENDENCIES.MRSIGNER 0;
TMP_KEYDEPENDENCIES.KEYID DS:RBX.KEYID;
TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES CR_SEAL_FUSES;
TMP_KEYDEPENDENCIES.CPUSVN CR_CPUSVN;
TMP_KEYDEPENDENCIES.PADDING HARDCODED_PKCS1_5_PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT TMP_CURRENTSECS.MISCSELECT;
TMP_KEYDEPENDENCIES.MISCMASK 0;
BREAK;
EINITTOKEN_KEY:
(* Check ENCLAVE has LAUNCH capability *)
IF (TMP_CURRENTSECS.ATTRIBUTES.LAUNCHKEY = 0)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ATTRIBUTE;
GOTO EXIT;
FI;
IF (DS:RBX.CPUSVN is beyond current CPU configuration)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_CPUSVN;
GOTO EXIT;
FI;
IF (DS:RBX.ISVSVN > TMP_CURRENTSECS.ISVSVN)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ISVSVN;
GOTO EXIT;
FI;
(* Determine values key is based on *)
TMP_KEYDEPENDENCIES.KEYNAME EINITTOKEN_KEY;
TMP_KEYDEPENDENCIES.ISVPRODID TMP_CURRENTSECS.ISVPRODID
TMP_KEYDEPENDENCIES.ISVSVN DS:RBX.ISVSVN;
TMP_KEYDEPENDENCIES.OWNEREPOCH CSR_SEOWNEREPOCH;
TMP_KEYDEPENDENCIES.ATTRIBUTES TMP_ATTRIBUTES;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK 0;
TMP_KEYDEPENDENCIES.MRENCLAVE 0;
TMP_KEYDEPENDENCIES.MRSIGNER TMP_CURRENTSECS.MRSIGNER;
TMP_KEYDEPENDENCIES.KEYID DS:RBX.KEYID;
TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES CR_SEAL_FUSES;
TMP_KEYDEPENDENCIES.CPUSVN DS:RBX.CPUSVN;
TMP_KEYDEPENDENCIES.PADDING TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT TMP_MISCSELECT;
TMP_KEYDEPENDENCIES.MISCMASK 0;
BREAK;
PROVISION_KEY:
(* Check ENCLAVE has PROVISIONING capability *)
41-88 Vol. 3D
SGX INSTRUCTION REFERENCES
IF (TMP_CURRENTSECS.ATTRIBUTES.PROVISIONKEY = 0)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ATTRIBUTE;
GOTO EXIT;
FI;
IF (DS:RBX.CPUSVN is beyond current CPU configuration)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_CPUSVN;
GOTO EXIT;
FI;
IF (DS:RBX.ISVSVN > TMP_CURRENTSECS.ISVSVN)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ISVSVN;
GOTO EXIT;
FI;
(* Determine values key is based on *)
TMP_KEYDEPENDENCIES.KEYNAME PROVISION_KEY;
TMP_KEYDEPENDENCIES.ISVPRODID TMP_CURRENTSECS.ISVPRODID;
TMP_KEYDEPENDENCIES.ISVSVN DS:RBX.ISVSVN;
TMP_KEYDEPENDENCIES.OWNEREPOCH 0;
TMP_KEYDEPENDENCIES.ATTRIBUTES TMP_ATTRIBUTES;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK DS:RBX.ATTRIBUTEMASK;
TMP_KEYDEPENDENCIES.MRENCLAVE 0;
TMP_KEYDEPENDENCIES.MRSIGNER TMP_CURRENTSECS.MRSIGNER;
TMP_KEYDEPENDENCIES.KEYID 0;
TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES 0;
TMP_KEYDEPENDENCIES.CPUSVN DS:RBX.CPUSVN;
TMP_KEYDEPENDENCIES.PADDING TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT TMP_MISCSELECT;
TMP_KEYDEPENDENCIES.MISCMASK ~DS:RBX.MISCMASK;
BREAK;
PROVISION_SEAL_KEY:
(* Check ENCLAVE has PROVISIONING capability *)
IF (TMP_CURRENTSECS.ATTRIBUTES.PROVISIONKEY = 0)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ATTRIBUTE;
GOTO EXIT;
FI;
IF (DS:RBX.CPUSVN is beyond current CPU configuration)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_CPUSVN;
GOTO EXIT;
FI;
IF (DS:RBX.ISVSVN > TMP_CURRENTSECS.ISVSVN)
THEN
RFLAGS.ZF 1;
RAX SGX_INVALID_ISVSVN;
GOTO EXIT;
FI;
Vol. 3D 41-89
SGX INSTRUCTION REFERENCES
(* Determine values key is based on *)
TMP_KEYDEPENDENCIES.KEYNAME PROVISION_SEAL_KEY;
TMP_KEYDEPENDENCIES.ISVPRODID TMP_CURRENTSECS.ISVPRODID;
TMP_KEYDEPENDENCIES.ISVSVN DS:RBX.ISVSVN;
TMP_KEYDEPENDENCIES.OWNEREPOCH 0;
TMP_KEYDEPENDENCIES.ATTRIBUTES TMP_ATTRIBUTES;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK DS:RBX.ATTRIBUTEMASK;
TMP_KEYDEPENDENCIES.MRENCLAVE 0;
TMP_KEYDEPENDENCIES.MRSIGNER TMP_CURRENTSECS.MRSIGNER;
TMP_KEYDEPENDENCIES.KEYID 0;
TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES CR_SEAL_FUSES;
TMP_KEYDEPENDENCIES.CPUSVN DS:RBX.CPUSVN;
TMP_KEYDEPENDENCIES.PADDING TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT TMP_MISCSELECT;
TMP_KEYDEPENDENCIES.MISCMASK ~DS:RBX.MISCMASK;
BREAK;
DEFAULT:
(* The value of KEYNAME is invalid *)
RFLAGS.ZF 1;
RAX SGX_INVALID_KEYNAME;
GOTO EXIT:
ESAC;
(* Calculate the final derived key and output to the address in RCX *)
TMP_OUTPUTKEY derivekey(TMP_KEYDEPENDENCIES);
DS:RCX[15:0] TMP_OUTPUTKEY;
RAX 0;
RFLAGS.ZF 0;
EXIT:
RFLAGS.CF 0;
RFLAGS.PF 0;
RFLAGS.AF 0;
RFLAGS.OF 0;
RFLAGS.SF 0;
Flags Affected
ZF is cleared if successful, otherwise ZF is set. CF, PF, AF, OF, SF are cleared.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the current enclave.
If an effective address is not properly aligned.
If an effective address is outside the DS segment limit.
If KEYREQUEST format is invalid.
#PF(error code)
If a page fault occurs in accessing memory.
64-Bit Mode Exceptions
#GP(0)
If a memory operand effective address is outside the current enclave.
If an effective address is not properly aligned.
If an effective address is not canonical.
If KEYREQUEST format is invalid.
#PF(error code)
41-90 Vol. 3D
If a page fault occurs in accessing memory operands.
SGX INSTRUCTION REFERENCES
Vol. 3D 41-91
SGX INSTRUCTION REFERENCES
EMODPE—Extend an EPC Page Permissions
Opcode/
Instruction
Op/En
EAX = 06H
ENCLU[EMODPE]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX2
Description
This leaf function extends the access rights of an existing EPC
page.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
IR
EMODPE (In)
Address of a SECINFO (In)
Address of the destination EPC page (In)
Description
This leaf function extends the access rights associated with an existing EPC page in the running enclave. THE RWX
bits of the SECINFO parameter are treated as a permissions mask; supplying a value that does not extend the page
permissions will have no effect. This instruction leaf can only be executed when inside the enclave.
RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC page.
The table below provides additional information on the memory parameter of the EMODPE leaf function.
EMODPE Memory Parameter Semantics
SECINFO
EPCPAGE
Read access permitted by Non Enclave
Read access permitted by Enclave
The instruction faults if any of the following:
EMODPE Faulting Conditions
The operands are not properly aligned.
If security attributes of the SECINFO page make the page inaccessible.
The EPC page is locked by another thread.
RBX does not contain an effective address in an EPC page in the running enclave.
The EPC page is not valid.
RCX does not contain an effective address of an EPC page in the running enclave.
SECINFO contains an invalid request.
Concurrency Restrictions
Table 41-60. Concurrency Restrictions of EMODPE with Other Intel® SGX Operations 1 of 2
Operation
EEXIT
Param
EMODPE
TCS SSA
SECS
EADD
EBLOCK
Targ SECS
Targ SECS
ECRE
ATE
SECS
EDBGRD/
WR
Targ SECS
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
TCS SSA SECS Targ SECS Param SECS
Targ
Y
Y
Y
Y
SECIN
FO
U
Y
U
U
SECS
EP
A
ELDB/ELDU
Targ VA
SECS VA
Table 41-61. Concurrency Restrictions of EMODPE with Other Intel® SGX Operations 2 of 2
Operation
Param
EMODP
E
EREMOVE
EREPORT
Targ SECS Param SECS
ETRACK
SECS
EWB
SRC
VA
EAUG
EMODPE
Targ
Y
N
Y
SECIN
FO
U
Y
Y
41-92 Vol. 3D
EMODPR
SECS Targ SECS Targ SECI Targ SEC
NFO
S
N
EMODT
EACCEPT
EACCEPTCOPY
Targ SEC
S
Targ SECI
NFO
SECS Targ SR
C
SECI
NFO
N
N
Y
Y
Y
Y
Y
Y
Y
SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EMODPE Operational Flow
Name
Type
Size (bits)
Description
SCRATCH_SECINFO
SECINFO
512
Scratch storage for holding the contents of DS:RBX.
IF (DS:RBX is not 64Byte Aligned)
THEN #GP(0); FI;
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF ((DS:RBX is not within CR_ELRANGE) or (DS:RCX is not within CR_ELRANGE) )
THEN #GP(0); FI;
IF (DS:RBX does not resolve within an EPC)
THEN #PF(DS:RBX); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
IF ( (EPCM(DS:RBX).VALID = 0) or (EPCM(DS:RBX).R = 0) or (EPCM(DS:RBX).PENDING ≠ 0) or (EPCM(DS:RBX).MODIFIED ≠ 0) or
(EPCM(DS:RBX).BLOCKED ≠ 0) or (EPCM(DS:RBX).PT ≠ PT_REG) or (EPCM(DS:RBX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RBX).ENCLAVEADDRESS ≠ DS:RBX) )
THEN #PF(DS:RBX); FI;
SCRATCH_SECINFO DS:RBX;
(* Check for mis-configured SECINFO flags*)
IF (SCRATCH_SECINFO reserved fields are not zero )
THEN #GP(0); FI;
(* Check security attributes of the EPC page *)
IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PENDING ≠ 0) or (EPCM(DS:RCX).MODIFIED ≠ 0) or
(EPCM(DS:RCX).BLOCKED ≠ 0) or (EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) )
THEN #PF(DS:RCX); FI;
(* Check the EPC page for concurrency *)
IF (EPC page in use by another SGX2 instruction)
THEN #GP(0); FI;
(* Re-Check security attributes of the EPC page *)
IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PENDING ≠ 0) or (EPCM(DS:RCX).MODIFIED ≠ 0) or
(EPCM(DS:RCX).BLOCKED ≠ 0) or (EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RCX).ENCLAVEADDRESS ≠ DS:RCX))
THEN #PF(DS:RCX); FI;
(* Check for mis-configured SECINFO flags*)
IF ( (EPCM(DS:RCX).R = 0) and (SCRATCH_SECINFO.FLAGS.R = 0) and (SCRATCH_SECINFO.FLAGS.W ≠ 0) ))
THEN #GP(0); FI;
Vol. 3D 41-93
SGX INSTRUCTION REFERENCES
(* Update EPCM permissions *)
EPCM(DS:RCX).R EPCM(DS:RCX).R | SCRATCH_SECINFO.FLAGS.R;
EPCM(DS:RCX).W EPCM(DS:RCX).W | SCRATCH_SECINFO.FLAGS.W;
EPCM(DS:RCX).X EPCM(DS:RCX).X | SCRATCH_SECINFO.FLAGS.X;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
If a page fault occurs in accessing memory operands.
64-Bit Mode Exceptions
#GP(0)
If a memory operand is non-canonical form.
If a memory operand is not properly aligned.
If a memory operand is locked.
#PF(error code)
41-94 Vol. 3D
If a page fault occurs in accessing memory operands.
SGX INSTRUCTION REFERENCES
EREPORT—Create a Cryptographic Report of the Enclave
Opcode/
Instruction
Op/En
EAX = 00H
ENCLU[EREPORT]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function creates a cryptographic report of the enclave.
Instruction Operand Encoding
Op/En
EAX
RBX
RCX
RDX
IR
EREPORT (In)
Address of TARGETINFO
(In)
Address of REPORTDATA
(In)
Address where the REPORT is
written to in an OUTPUTDATA (In)
Description
This leaf function creates a cryptographic REPORT that describes the contents of the enclave. This instruction leaf
can only be executed when inside the enclave. The cryptographic report can be used by other enclaves to determine that the enclave is running on the same platform.
RBX contains the effective address of the MRENCLAVE value of the enclave that will authenticate the REPORT
output, using the REPORT key delivered by EGETKEY command for that enclave. RCX contains the effective address
of a 64-byte REPORTDATA structure, which allows the caller of the instruction to associate data with the enclave
from which the instruction is called. RDX contains the address where the REPORT will be output by the instruction.
EREPORT Memory Parameter Semantics
TARGETINFO
REPORTDATA
OUTPUTDATA
Read access by Enclave
Read access by Enclave
Read/Write access by Enclave
This instruction leaf perform the following:
1. Validate the 3 operands (RBX, RCX, RDX) are inside the enclave.
2. Compute a report key for the target enclave, as indicated by the value located in RBX(TARGETINFO).
3. Assemble the enclave SECS data to complete the REPORT structure (including the data provided using the RCX
(REPORTDATA) operand).
4. Computes a crytpographic hash over REPORT structure.
5. Add the computed hash to the REPORT structure.
6. Output the completed REPORT structure to the address in RDX (OUTPUTDATA).
The instruction fails if the operands are not properly aligned.
CR_REPORT_KEYID, used to provide key wearout protection, is populated with a statistically unique value on boot
of the platform by a trusted entity within the SGX TCB.
The instruction faults if any of the following:
Vol. 3D 41-95
SGX INSTRUCTION REFERENCES
EREPORT Faulting Conditions
An effective address not properly aligned.
An memory address does not resolve in an EPC page.
If accessing an invalid EPC page.
If the EPC page is blocked.
May page fault.
Concurrency Restrictions
Table 41-62. Concurrency Restrictions of EREPORT with Other Intel® SGX Operations 1 of 2
Operation
EEXIT
Param
EREPORT
TCS SSA
EADD
EBLOCK
ECRE
ATE
SECS Targ SECS
Targ SECS
SECS
Y
Y
Y
Targ SECS
U
Param
SECS
EDBGRD/
WR
EENTER/
ERESUME
Y
Y
U
Y
Y
EGETKEY
TCS SSA SECS Targ SECS Param SECS
Y
Y
EEXTEND
Y
EINIT
ELDB/ELDU
EPA
SECS
Targ VA
SECS VA
Y
Y
Y
U
Y
Y
Y
Y
Y
Y
Y
Y
Table 41-63. Concurrency Restrictions of EREPORT with Other Intel® SGX Operations 2 of 2
Operation
Param
EREPORT
EREMOVE
ETRACK
EWB
EAUG
Y
Y
Y
Y
EMODPE
EMODPR
SECS
SRC
VA
SECS Targ SECS Targ SECI Targ SEC
NFO
S
Y
Y
Y
Y
U
Param
SECS
EREPORT
Targ SECS Param SECS
Y
Y
Y
U
Y
Y
Y
Y
EMODT
Targ SEC
S
Y
Y
EACCEPT
Targ SECI
NFO
Y
U
Y
Y
EACCEPTCOPY
SECS Targ SR
C
Y
Y
Y
U
Y
Y
Operation
Temp Variables in EREPORT Operational Flow
Name
Type
TMP_ATTRIBUTES
Size (bits)
Description
32
Physical address of SECS of the enclave to which source operand belongs.
TMP_CURRENTSECS
Address of the SECS for the currently executing enclave.
TMP_KEYDEPENDENCIES
Temp space for key derivation.
TMP_REPORTKEY
128
TMP_REPORT
3712
REPORTKEY generated by the instruction.
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
(* Address verification for TARGETINFO (RBX) *)
IF ( (DS:RBX is not 128Byte Aligned) or (DS:RBX is not within CR_ELRANGE) )
THEN #GP(0); FI;
IF (DS:RBX does not resolve within an EPC)
THEN #PF(DS:RBX); FI;
IF (EPCM(DS:RBX). VALID = 0)
THEN #PF(DS:RBX); FI;
IF (EPCM(DS:RBX).BLOCKED = 1) )
THEN #PF(DS:RBX); FI;
(* Check page parameters for correctness *)
IF ( (EPCM(DS:RBX).PT ≠ PT_REG) or (EPCM(DS:RBX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or (EPCM(DS:RBX).PENDING = 1) or
(EPCM(DS:RBX).MODIFIED = 1) or (EPCM(DS:RBX).ENCLAVEADDRESS ≠ (DS:RBX & ~0FFFH) ) or (EPCM(DS:RBX).R = 0) )
41-96 Vol. 3D
SECI
NFO
SGX INSTRUCTION REFERENCES
THEN #PF(DS:RBX);
FI;
(* Address verification for REPORTDATA (RCX) *)
IF ( (DS:RCX is not 128Byte Aligned) or (DS:RCX is not within CR_ELRANGE) )
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #P(DS:RCX); FI;
IF (EPCM(DS:RCX). VALID = 0)
THEN #PF(DS:RCX); FI;
IF (EPCM(DS:RCX).BLOCKED = 1) )
THEN #PF(DS:RCX); FI;
(* Check page parameters for correctness *)
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or (EPCM(DS:RCX).PENDING = 1) or
(EPCM(DS:RCX).MODIFIED = 1) or (EPCM(DS:RCX).ENCLAVEADDRESS ≠ (DS:RCX & ~0FFFH) ) or (EPCM(DS:RCX).R = 0) )
THEN #PF(DS:RCX);
FI;
(* Address verification for OUTPUTDATA (RDX) *)
IF ( (DS:RDX is not 512Byte Aligned) or (DS:RDX is not within CR_ELRANGE) )
THEN #GP(0); FI;
IF (DS:RDX does not resolve within an EPC)
THEN #PF(DS:RDX); FI;
IF (EPCM(DS:RDX). VALID = 0)
THEN #PF(DS:RDX); FI;
IF (EPCM(DS:RDX).BLOCKED = 1) )
THEN #PF(DS:RDX); FI;
(* Check page parameters for correctness *)
IF ( (EPCM(DS:RDX).PT ≠ PT_REG) or (EPCM(DS:RDX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RDX).ENCLAVEADDRESS ≠ (DS:RDX & ~0FFFH) ) or (EPCM(DS:RDX).W = 0) )
THEN #PF(DS:RDX);
FI;
(* REPORT MAC needs to be computed over data which cannot be modified *)
TMP_REPORT.CPUSVN CR_CPUSVN;
TMP_REPORT.ISVPRODID TMP_CURRENTSECS.ISVPRODID;
TMP_REPORT.ISVSVN TMP_CURRENTSECS..ISVSVN;
TMP_REPORT.ATTRIBUTES TMP_CURRENTSECS.ATTRIBUTES;
TMP_REPORT.REPORTDATA DS:RCX[511:0];
TMP_REPORT.MRENCLAVE TMP_CURRENTSECS.MRENCLAVE;
TMP_REPORT.MRSIGNER TMP_CURRENTSECS.MRSIGNER;
TMP_REPORT.MRRESERVED 0;
TMP_REPORT.KEYID[255:0] CR_REPORT_KEYID;
TMP_REPORT.MISCSELECT TMP_CURRENTSECS.MISCSELECT;
Vol. 3D 41-97
SGX INSTRUCTION REFERENCES
(* Derive the report key *)
TMP_KEYDEPENDENCIES.KEYNAME REPORT_KEY;
TMP_KEYDEPENDENCIES.ISVPRODID 0;
TMP_KEYDEPENDENCIES.ISVSVN 0;
TMP_KEYDEPENDENCIES.OWNEREPOCH CSR_SGX_OWNEREPOCH;
TMP_KEYDEPENDENCIES.ATTRIBUTES DS:RBX.ATTRIBUTES;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK 0;
TMP_KEYDEPENDENCIES.MRENCLAVE DS:RBX.MEASUREMENT;
TMP_KEYDEPENDENCIES.MRSIGNER 0;
TMP_KEYDEPENDENCIES.KEYID TMP_REPORT.KEYID;
TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES CR_SEAL_FUSES;
TMP_KEYDEPENDENCIES.CPUSVN CR_CPUSVN;
TMP_KEYDEPENDENCIES.PADDING TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT DS:RBX.MISCSELECT;
TMP_KEYDEPENDENCIES.MISCMASK 0;
(* Calculate the derived key*)
TMP_REPORTKEY derive_key(TMP_KEYDEPENDENCIES);
(* call cryptographic CMAC function, CMAC data are not including MAC&KEYID *)
TMP_REPORT.MAC cmac(TMP_REPORTKEY, TMP_REPORT[3071:0] );
DS:RDX[3455: 0] TMP_REPORT;
Flags Affected
None
Protected Mode Exceptions
#GP(0)
If the address in RCS is outside the DS segment limit.
If a memory operand is not properly aligned.
If a memory operand is not in the current enclave.
#PF(error code)
If a page fault occurs in accessing memory operands.
64-Bit Mode Exceptions
#GP(0)
If RCX is non-canonical form.
If a memory operand is not properly aligned.
If a memory operand is not in the current enclave.
#PF(error code)
41-98 Vol. 3D
If a page fault occurs in accessing memory operands.
SGX INSTRUCTION REFERENCES
ERESUME—Re-Enters an Enclave
Opcode/
Instruction
Op/En
EAX = 03H
ENCLU[ERESUME]
IR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SGX1
Description
This leaf function is used to re-enter an enclave after an interrupt.
Instruction Operand Encoding
Op/En
RAX
RBX
RCX
IR
ERESUME (In)
Address of a TCS (In)
Address of AEP (In)
Description
The ENCLU[ERESUME] instruction resumes execution of an enclave that was interrupted due to an exception or
interrupt, using the machine state previously stored in the SSA.
ERESUME Memory Parameter Semantics
TCS
Enclave read/write access
The instruction faults if any of the following:
Address in RBX is not properly aligned.
Any TCS.FLAGS’s must-be-zero bit is not zero.
TCS pointed to by RBX is not valid or available or
locked.
Current 32/64 mode does not match the enclave mode in
SECS.ATTRIBUTES.MODE64.
The SECS is in use by another enclave.
Either of TCS-specified FS and GS segment is not a subset of the current DS
segment.
Any one of DS, ES, CS, SS is not zero.
If XSAVE available, CR4.OSXSAVE = 0, but SECS.ATTRIBUTES.XFRM ≠ 3.
CR4.OSFXSR ≠ 1.
If CR4.OSXSAVE = 1, SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
Offsets 520-535 of the XSAVE area not 0.
The bit vector stored at offset 512 of the XSAVE area must be a subset of
SECS.ATTRIBUTES.XFRM.
The SSA frame is not valid or in use.
The following operations are performed by ERESUME:
•
RSP and RBP are saved in the current SSA frame on EENTER and are automatically restored on EEXIT or an
asynchronous exit due to any Interrupt event.
•
The AEP contained in RCX is stored into the TCS for use by AEXs.FS and GS (including hidden portions) are
saved and new values are constructed using TCS.OFSBASE/GSBASE (32 and 64-bit mode) and
TCS.OFSLIMIT/GSLIMIT (32-bit mode only). The resulting segments must be a subset of the DS segment.
•
If CR4.OSXSAVE == 1, XCR0 is saved and replaced by SECS.ATTRIBUTES.XFRM. The effect of RFLAGS.TF
depends on whether the enclave entry is opt-in or opt-out (see Section 43.1.2):
— On opt-out entry, TF is saved and cleared (it is restored on EEXIT or AEX). Any attempt to set TF via a POPF
instruction while inside the enclave clears TF (see Section 43.2.5).
— On opt-in entry, a single-step debug exception is pended on the instruction boundary immediately after
EENTER (see Section 43.2.3).
•
All code breakpoints that do not overlap with ELRANGE are also suppressed. If the entry is an opt-out entry, all
code and data breakpoints that overlap with the ELRANGE are suppressed.
Vol. 3D 41-99
SGX INSTRUCTION REFERENCES
•
On opt-out entry, a number of performance monitoring counters and behaviors are modified or suppressed (see
Section 43.2.3):
— All performance monitoring activity on the current thread is suppressed except for incrementing and firing
of FIXED_CTR1 and FIXED_CTR2.
— PEBS is suppressed.
— AnyThread counting on other threads is demoted to MyThread mode and IA32_PERF_GLOBAL_STATUS[60]
on that thread is set.
— If the opt-out entry on a hardware thread results in suppression of any performance monitoring, then the
processor sets IA32_PERF_GLOBAL_STATUS[60] and IA32_PERF_GLOBAL_STATUS[63].
Concurrency Restrictions
Table 41-64. Concurrency Restrictions of ERESUME with Intel® SGX Instructions - 1of 2
Operation
ERESU
ME
EEXIT
Param
Targ VA
TCS
N
EADD
ECRE
ATE
EBLOCK
SECS Targ SECS Targ SECS
N
Y
N
Y
Y
EEXTEND
EGETKEY
SECS
Targ SECS
TCS SSA SECS Targ SECS Param SECS
Y
N
Y
Y
EENTER/
ERESUME
N
U
SSA
SECS
EDBGRD/
WR
Y
Y
Y
EINIT
ELDB/ELDU
SECS
Targ VA
SECS VA
N
Y
U
Y
Y
EPA
N
U
Y
Y
N
Y
Y
N
Y
Y
Y
Y
Table 41-65. Concurrency Restrictions of ERESUME with Intel® SGX Instructions - 2 of 2
Operation
ERESU
ME
EREMOVE
EREPORT
ETRA
CK
EWB
Param
Targ SECS Param SECS SECS
SRC VA
TCS
N
N
SSA
SECS
EAUG
SECS Targ SECS
Y
Y
Y
Y
Targ
SECI
NFO
Y
U
EMODPR
Targ
SECS
N
Y
Y
EMODT
Targ
SECS
EACCEPT
Targ SECI
NFO
EACCEPTCOPY
SECS Targ SRC
SECI
NFO
N
U
Y
EMODPE
Y
Y
Y
U
Y
U
U
Y
Operation
Temp Variables in ERESUME Operational Flow
Name
Type
Size
Description
TMP_FSBASE
Effective Address
32/64
Proposed base address for FS segment.
TMP_GSBASE
Effective Address
32/64
Proposed base address for FS segment.
TMP_FSLIMIT
Effective Address
32/64
Highest legal address in proposed FS segment.
TMP_GSLIMIT
Effective Address
32/64
Highest legal address in proposed GS segment.
TMP_TARGET
Effective Address
32/64
Address of first instruction inside enclave at which execution is to resume.
TMP_SECS
Effective Address
32/64
Physical address of SECS for this enclave.
TMP_SSA
Effective Address
32/64
Address of current SSA frame.
TMP_XSIZE
integer
64
Size of XSAVE area based on SECS.ATTRIBUTES.XFRM.
TMP_SSA_PAGE
Effective Address
32/64
Pointer used to iterate over the SSA pages in the current frame.
TMP_GPR
Effective Address
32/64
Address of the GPR area within the current SSA frame.
TMP_BRANCH_RECORD
LBR Record
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
41-100 Vol. 3D
From/to addresses to be pushed onto the LBR stack.
SGX INSTRUCTION REFERENCES
(* Make sure DS is usable, expand up *)
IF (TMP_MODE64 = 0 and (DS not usable or ( ( DS[S] = 1) and (DS[bit 11] = 0) and DS[bit 10] = 1) ) ) )
THEN #GP(0); FI;
(* Check that CS, SS, DS, ES.base is 0 *)
IF (TMP_MODE64 = 0)
THEN
IF(CS.base ≠ 0 or DS.base ≠ 0) #GP(0); FI;
IF(ES usable and ES.base ≠ 0) #GP(0); FI;
IF(SS usable and SS.base ≠ 0) #GP(0); FI;
IF(SS usable and SS.B = 0) #GP(0); FI;
FI;
IF (DS:RBX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RBX does not resolve within an EPC)
THEN #PF(DS:RBX); FI;
(* Check AEP is canonical*)
IF (TMP_MODE64 = 1 and (DS:RCX is not canonical) )
THEN #GP(0); FI;
(* Check concurrency of TCS operation*)
IF (Other Intel SGX instructions is operating on TCS)
THEN #GP(0); FI;
(* TCS verification *)
IF (EPCM(DS:RBX).VALID = 0)
THEN #PF(DS:RBX); FI;
IF (EPCM(DS:RBX).BLOCKED = 1)
THEN #PF(DS:RBX); FI;
IF ((EPCM(DS:RBX).PENDING = 1) or (EPCM(DS:RBX).MODIFIED = 1))
THEN #PF(DS:RBX); FI;
IF ( (EPCM(DS:RBX).ENCLAVEADDRESS ≠ DS:RBX) or (EPCM(DS:RBX).PT ≠ PT_TCS) )
THEN #PF(DS:RBX); FI;
IF ( (DS:RBX).OSSA is not 4KByte Aligned)
THEN #GP(0); FI;
(* Check proposed FS and GS *)
IF ( ( (DS:RBX).OFSBASE is not 4KByte Aligned) or ( (DS:RBX).OGSBASE is not 4KByte Aligned) )
THEN #GP(0); FI;
(* Get the SECS for the enclave in which the TCS resides *)
TMP_SECS Address of SECS for TCS;
(* Make sure that the FLAGS field in the TCS does not have any reserved bits set *)
IF ( ( (DS:RBX).FLAGS & & FFFFFFFFFFFFFFFEH) ≠ 0)
THEN #GP(0); FI;
Vol. 3D 41-101
SGX INSTRUCTION REFERENCES
(* SECS must exist and enclave must have previously been EINITted *)
IF (the enclave is not already initialized)
THEN #GP(0); FI;
(* make sure the logical processor’s operating mode matches the enclave *)
IF ( (TMP_MODE64 ≠ TMP_SECS.ATTRIBUTES.MODE64BIT) )
THEN #GP(0); FI;
IF (CR4.OSFXSR = 0)
THEN #GP(0); FI;
(* Check for legal values of SECS.ATTRIBUTES.XFRM *)
IF (CR4.OSXSAVE = 0)
THEN
IF (TMP_SECS.ATTRIBUES.XFRM ≠ 03H) THEN #GP(0); FI;
ELSE
IF ( (TMP_SECS.ATTRIBUES.XFRM & XCR0) ≠ TMP_SECS.ATTRIBUES.XFRM) THEN #GP(0); FI;
FI;
(* Make sure the SSA contains at least one active frame *)
IF ( (DS:RBX).CSSA = 0)
THEN #GP(0); FI;
(* Compute linear address of SSA frame *)
TMP_SSA (DS:RBX).OSSA + TMP_SECS.BASEADDR + 4096 * TMP_SECS.SSAFRAMESIZE * ( (DS:RBX).CSSA - 1);
TMP_XSIZE compute_XSAVE_frame_size(TMP_SECS.ATTRIBUTES.XFRM);
FOR EACH TMP_SSA_PAGE = TMP_SSA to TMP_SSA + TMP_XSIZE
(* Check page is read/write accessible *)
Check that DS:TMP_SSA_PAGE is read/write accessible;
If a fault occurs, release locks, abort and deliver that fault;
IF (DS:TMP_SSA_PAGE does not resolve to EPC page)
THEN #PF(DS:TMP_SSA_PAGE); FI;
IF (EPCM(DS:TMP_SSA_PAGE).VALID = 0)
THEN #PF(DS:TMP_SSA_PAGE); FI;
IF (EPCM(DS:TMP_SSA_PAGE).BLOCKED = 1)
THEN #PF(DS:TMP_SSA_PAGE); FI;
IF ((EPCM(DS:TMP_SSA_PAGE).PENDING = 1) or (EPCM(DS:TMP_SSA_PAGE_.MODIFIED = 1))
THEN #PF(DS:TMP_SSA_PAGE); FI;
IF ( ( EPCM(DS:TMP_SSA_PAGE).ENCLAVEADDRESS ≠ DS:TMPSSA_PAGE) or (EPCM(DS:TMP_SSA_PAGE).PT ≠ PT_REG) or
(EPCM(DS:TMP_SSA_PAGE).ENCLAVESECS ≠ EPCM(DS:RBX).ENCLAVESECS) or
(EPCM(DS:TMP_SECS).R = 0) or (EPCM(DS:TMP_SECS).W = 0) )
THEN #PF(DS:TMP_SSA_PAGE); FI;
CR_XSAVE_PAGE_n Physical_Address(DS:TMP_SSA_PAGE);
ENDFOR
(* Compute address of GPR area*)
TMP_GPR TMP_SSA + 4096 * DS:TMP_SECS.SSAFRAMESIZE -- sizeof(GPRSGX_AREA);
Check that DS:TMP_SSA_PAGE is read/write accessible;
If a fault occurs, release locks, abort and deliver that fault;
IF (DS:TMP_GPR does not resolve to EPC page)
THEN #PF(DS:TMP_GPR); FI;
IF (EPCM(DS:TMP_GPR).VALID = 0)
THEN #PF(DS:TMP_GPR); FI;
41-102 Vol. 3D
SGX INSTRUCTION REFERENCES
IF (EPCM(DS:TMP_GPR).BLOCKED = 1)
THEN #PF(DS:TMP_GPR); FI;
IF ((EPCM(DS:TMP_GPR).PENDING = 1) or (EPCM(DS:TMP_GPR).MODIFIED = 1))
THEN #PF(DS:TMP_GPR); FI;
IF ( ( EPCM(DS:TMP_GPR).ENCLAVEADDRESS ≠ DS:TMP_GPR) or (EPCM(DS:TMP_GPR).PT ≠ PT_REG) or
(EPCM(DS:TMP_GPR).ENCLAVESECS ≠ EPCM(DS:RBX).ENCLAVESECS) or
(EPCM(DS:TMP_GPR).R = 0) or (EPCM(DS:TMP_GPR).W = 0) )
THEN #PF(DS:TMP_GPR); FI;
IF (TMP_MODE64 = 0)
THEN
IF (TMP_GPR + (GPR_SIZE -1) is not in DS segment) THEN #GP(0); FI;
FI;
CR_GPR_PA Physical_Address (DS: TMP_GPR);
TMP_TARGET (DS:TMP_GPR).RIP;
IF (TMP_MODE64 = 1)
THEN
IF (TMP_TARGET is not canonical) THEN #GP(0); FI;
ELSE
IF (TMP_TARGET > CS limit) THEN #GP(0); FI;
FI;
(* Check proposed FS/GS segments fall within DS *)
IF (TMP_MODE64 = 0)
THEN
TMP_FSBASE (DS:RBX).OFSBASE + TMP_SECS.BASEADDR;
TMP_FSLIMIT (DS:RBX).OFSBASE + TMP_SECS.BASEADDR + (DS:RBX).FSLIMIT;
TMP_GSBASE (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;
TMP_GSLIMIT (DS:RBX).OGSBASE + TMP_SECS.BASEADDR + (DS:RBX).GSLIMIT;
(* if FS wrap-around, make sure DS has no holes*)
IF (TMP_FSLIMIT < TMP_FSBASE)
THEN
IF (DS.limit < 4GB) THEN #GP(0); FI;
ELSE
IF (TMP_FSLIMIT > DS.limit) THEN #GP(0); FI;
FI;
(* if GS wrap-around, make sure DS has no holes*)
IF (TMP_GSLIMIT < TMP_GSBASE)
THEN
IF (DS.limit < 4GB) THEN #GP(0); FI;
ELSE
IF (TMP_GSLIMIT > DS.limit) THEN #GP(0); FI;
FI;
ELSE
TMP_FSBASE (DS:RBX).OFSBASE + TMP_SECS.BASEADDR;
TMP_GSBASE (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;
IF ( (TMP_FSBASE is not canonical) or (TMP_GSBASE is not canonical))
THEN #GP(0); FI;
FI;
(* Ensure the enclave is not already active and this thread is the only one using the TCS*)
IF (DS:RBX.STATE = ACTIVE))
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THEN #GP(0); FI;
(* SECS.ATTRIBUTES.XFRM selects the features to be saved. *)
(* CR_XSAVE_PAGE_n: A list of 1 or more physical address of pages that contain the XSAVE area. *)
XRSTOR(TMP_MODE64, SECS.ATTRIBUTES.XFRM, CR_XSAVE_PAGE_n);
IF (XRSTOR failed with #GP)
THEN
DS:RBX.STATE INACTIVE;
#GP(0);
FI;
CR_ENCALVE_MODE 1;
CR_ACTIVE_SECS TMP_SECS;
CR_ELRANGE (TMP_SECS.BASEADDR, TMP_SECS.SIZE);
(* Save sate for possible AEXs *)
CR_TCS_PA Physical_Address (DS:RBX);
CR_TCS_LA RBX;
CR_TCS_LA.AEP RCX;
(* Save the hidden portions of FS and GS *)
CR_SAVE_FS_selector FS.selector;
CR_SAVE_FS_base FS.base;
CR_SAVE_FS_limit FS.limit;
CR_SAVE_FS_access_rights FS.access_rights;
CR_SAVE_GS_selector GS.selector;
CR_SAVE_GS_base GS.base;
CR_SAVE_GS_limit GS.limit;
CR_SAVE_GS_access_rights GS.access_rights;
(* Set CR_ENCLAVE_ENTRY_IP *)
CR_ENCLAVE_ENTRY_IP CRIP”
RIP TMP_TARGET;
Restore_GPRs from DS:TMP_GPR;
(*Restore the RFLAGS values from SSA*)
RFLAGS.CF DS:TMP_GPR.RFLAGS.CF;
RFLAGS.PF DS:TMP_GPR.RFLAGS.PF;
RFLAGS.AF DS:TMP_GPR.RFLAGS.AF;
RFLAGS.ZF DS:TMP_GPR.RFLAGS.ZF;
RFLAGS.SF DS:TMP_GPR.RFLAGS.SF;
RFLAGS.DF DS:TMP_GPR.RFLAGS.DF;
RFLAGS.OF DS:TMP_GPR.RFLAGS.OF;
RFLAGS.NT DS:TMP_GPR.RFLAGS.NT;
RFLAGS.AC DS:TMP_GPR.RFLAGS.AC;
RFLAGS.ID DS:TMP_GPR.RFLAGS.ID;
RFLAGS.RF DS:TMP_GPR.RFLAGS.RF;
RFLAGS.VM 0;
IF (RFLAGS.IOPL = 3)
THEN RFLAGS.IF = DS:TMP_GPR.IF; FI;
IF (TCS.FLAGS.OPTIN = 0)
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THEN RFLAGS.TF = 0; FI;
(* If XSAVE is enabled, save XCR0 and replace it with SECS.ATTRIBUTES.XFRM*)
IF (CR4.OSXSAVE = 1)
CR_SAVE_XCR0 XCR0;
XCR0 TMP_SECS.ATTRIBUTES.XFRM;
FI;
(* Pop the SSA stack*)
(DS:RBX).CSSA (DS:RBX).CSSA -1;
(* Do the FS/GS swap *)
FS.base TMP_FSBASE;
FS.limit DS:RBX.FSLIMIT;
FS.type 0001b;
FS.W DS.W;
FS.S 1;
FS.DPL DS.DPL;
FS.G 1;
FS.B 1;
FS.P 1;
FS.AVL DS.AVL;
FS.L DS.L;
FS.unusable 0;
FS.selector 0BH;
GS.base TMP_GSBASE;
GS.limit DS:RBX.GSLIMIT;
GS.type 0001b;
GS.W DS.W;
GS.S 1;
GS.DPL DS.DPL;
GS.G 1;
GS.B 1;
GS.P 1;
GS.AVL DS.AVL;
GS.L DS.L;
GS.unusable 0;
GS.selector 0BH;
CR_DBGOPTIN TSC.FLAGS.DBGOPTIN;
Suppress all code breakpoints that are outside ELRANGE;
IF (CR_DBGOPTIN = 0)
THEN
Suppress all code breakpoints that overlap with ELRANGE;
CR_SAVE_TF RFLAGS.TF;
RFLAGS.TF 0;
Suppress any MTF VM exits during execution of the enclave;
Clear all pending debug exceptions;
Clear any pending MTF VM exit;
ELSE
Clear all pending debug exceptions;
Clear pending MTF VM exits;
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FI;
(* Assure consistent translations *)
Flush_linear_context;
Clear_Monitor_FSM;
Allow_front_end_to_begin_fetch_at_new_RIP;
Flags Affected
RFLAGS.TF is cleared on opt-out entry
Protected Mode Exceptions
#GP(0)
If DS:RBX is not page aligned.
If the enclave is not initialized.
If the thread is not in the INACTIVE state.
If CS, DS, ES or SS bases are not all zero.
If executed in enclave mode.
If part or all of the FS or GS segment specified by TCS is outside the DS segment.
If any reserved field in the TCS FLAG is set.
If the target address is not within the CS segment.
If CR4.OSFXSR = 0.
If CR4.OSXSAVE = 0 and SECS.ATTRIBUTES.XFRM ≠ 3.
If CR4.OSXSAVE = 1and SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
#PF(error code)
If a page fault occurs in accessing memory.
If DS:RBX does not point to a valid TCS.
If one or more pages of the current SSA frame are not readable/writable, or do not resolve to
a valid PT_REG EPC page.
64-Bit Mode Exceptions
#GP(0)
If DS:RBX is not page aligned.
If the enclave is not initialized.
If the thread is not in the INACTIVE state.
If CS, DS, ES or SS bases are not all zero.
If executed in enclave mode.
If part or all of the FS or GS segment specified by TCS is outside the DS segment.
If any reserved field in the TCS FLAG is set.
If the target address is not canonical.
If CR4.OSFXSR = 0.
If CR4.OSXSAVE = 0 and SECS.ATTRIBUTES.XFRM ≠ 3.
If CR4.OSXSAVE = 1and SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
#PF(error code)
If a page fault occurs in accessing memory operands.
If DS:RBX does not point to a valid TCS.
If one or more pages of the current SSA frame are not readable/writable, or do not resolve to
a valid PT_REG EPC page.
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INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
CHAPTER 42
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
Intel® SGX provides Intel® Architecture with a collection of enclave instructions for creating protected execution
environments on processors supporting IA32 and Intel® 64 architectures. These Intel SGX instructions are
designed to work with legacy software and the various IA32 and Intel 64 modes of operation.
42.1
INTEL® SGX AVAILABILITY IN VARIOUS PROCESSOR MODES
The Intel SGX extensions (see Table 37-1) are available only when the processor is executing in protected mode of
operation. Additionally, the extensions are not available in System Management Mode (SMM) of operation or in
Virtual 8086 (VM86) mode of operation. Finally, all leaf functions of ENCLU and ENCLS require CR0.PG enabled.
The exact details of exceptions resulting from illegal modes and their priority are listed in the reference pages of
ENCLS and ENCLU.
42.2
IA32_FEATURE_CONTROL
IA32_FEATURE_CONTROL MSR provides two new bits related to two aspects of Intel SGX: using the instruction
extensions and launch control configuration.
42.2.1
Availability of Intel SGX
IA32_FEATURE_CONTROL[bit 18] allows BIOS to control the availability of Intel SGX extensions. For Intel SGX
extensions to be available on a logical processor, bit 18 in the IA32_FEATURE_CONTROL MSR on that logical
processor must be set, and IA32_FEATURE_CONTROL MSR on that logical processor must be locked (bit 0 must be
set). See Section 37.7.1 for additional details. OS is expected to examine the value of bit 18 prior to enabling Intel
SGX on the thread, as the settings of bit 18 is not reflected by CPUID.
42.2.2
Intel SGX Launch Control Configuration
The IA32_SGXLEPUBKEYHASHn MSRs used to configure authorized launch enclaves' MRSIGNER digest value. They
are present on logical processors that support the collection of SGX1 leaf functions (i.e. CPUID.(EAX=12H,
ECX=00H):EAX[0] = 1) and that CPUID.(EAX=07H, ECX=00H):ECX[30] = 1. IA32_FEATURE_CONTROL[bit 17]
allows to BIOS to enable write access to these MSRs. If IA32_FEATURE_CONTROL.LE_WR (bit 17) is set to 1 and
IA32_FEATURE_CONTROL is locked on that logical processor, IA32_SGXLEPUBKEYHASH MSRs on that logical
processor then the IA32_SGXLEPUBKEYHASHn MSR are writeable. If this bit 17 is not set or
IA32_FEATURE_CONTROL is not locked, IA32_SGXLEPUBKEYHASH MSRs are read only. See Section 39.1.4 for
additional details.
42.3
INTERACTIONS WITH SEGMENTATION
42.3.1
Scope of Interaction
Intel SGX extensions are available only when the processor is executing in a protected mode operation (see
Section 42.1 for Intel SGX availability in various processor modes). Enclaves abide by all the segmentation policies
set up by the OS, but they can be more restrictive than the OS.
Intel SGX interacts with segmentation at two levels:
•
The Intel SGX instruction (see the enclave instruction in Table 37-1).
Vol. 3D 42-1
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
•
While executing inside an enclave (legacy instructions and enclave instructions permitted inside an enclave).
42.3.2
Interactions of Intel® SGX Instructions with Segment, Operand, and Addressing
Prefixes
All the memory operands used by the Intel SGX instructions are interpreted as offsets within the data segment
(DS). The segment-override prefix on Intel SGX instructions is ignored.
Operand size is fixed for each enclave instruction. The operand-size prefix is reserved, and results in a #UD exception if used.
All address sizes are determined by the operating mode of the processor. The address-size prefix is ignored. This
implies that while operating in 64-bit mode of operation, the address size is always 64 bits, and while operating in
32-bit mode of operation, the address size is always 32 bits. Additionally, when operating in 16-bit addressing,
memory operands used by enclave instructions use 32 bit addressing; the value of CS.D is ignored.
42.3.3
Interaction of Intel® SGX Instructions with Segmentation
All leaf functions of ENCLU and ENCLS instructions require that the DS segment be usable, and be an expand-up
segment. Failing this check results in generation of a #GP(0) exception.
The Intel SGX leaf functions used for entering the enclave (ENCLU[EENTER] and ENCLU[ERESUME]) operate as
follows:
•
•
•
•
All usable segment registers except for FS and GS have a zero base.
•
The CS segment mode (64-bit, compatible, or 32 bit modes) must be consistent with the segment mode for
which the enclave was created, as indicated by the SECS.ATTRIBUTES.MODE64 bit, and that the CPL of the
logical processor is 3
The contents of the FS/GS segment registers (including the hidden portion) is saved in the processor.
New FS and GS values compatible with enclave security are loaded from the TCS
The linear ranges and access rights available under the newly-loaded FS and GS must abide to OS policies by
ensuring they are subsets of the linear-address range and access rights available for the DS segment.
An exit from the enclave either via ENCLU[EEXIT] or via an AEX restores the saved values of FS/GS segment registers.
42.3.4
Interactions of Enclave Execution with Segmentation
During the course of execution, enclave code abides by all segmentation policies as dictated by IA32 and Intel 64
Architectures, and generates appropriate exceptions on violations.
Additionally, any attempt by software executing inside an enclave to modify the processor's segmentation state
(e.g. via MOV seg register, POP seg register, LDS, far jump, etc; excluding WRFSBASE/WRGSBASE) results in the
generation of a #UD. See Section 39.6.1 for more information.
Upon enclave entry via the EENTER leaf function, FS is loaded from the (TCS.OFSBASE + SECS.BASEADDR) and
TCS.FSLIMIT fields and GS is loaded from the (TCS.OGSBASE + SECS.BASEADDR) and TCS.GSLIMIT fields.
Execution of WRFSBASE and WRGSBASE from inside a 64-bit enclave is allowed. The processor will save the new
values into the current SSA frame on an asynchronous exit (AEX) and restore them back on enclave entry via
ENCLU[ERESUME] instruction.
42.4
INTERACTIONS WITH PAGING
Intel SGX instructions are available only when the processor is executing in a protected mode of operation. Additionally, all Intel SGX leaf functions except for EDBGRD and EDBGWR are available only if paging is enabled. Any
attempt to execute these leaf functions with paging disabled results in an invalid-opcode exception (#UD). As with
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INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
segmentation, enclaves abide by all the paging policies set up by the OS, but they can be more restrictive than the
OS.
All the memory operands passed into Intel SGX instructions are interpreted as offsets within the DS segment, and
the linear addresses generated by combining these offsets with DS segment register are subject to paging-based
access control if paging is enabled at the time of the execution of the leaf function.
Since the ENCLU[EENTER] and ENCLU[ERESUME] can only be executed when paging is enabled, and since paging
cannot be disabled by software running inside an enclave (recall that enclaves always run with CPL = 3), enclave
execution is always subject to paging-based access control. The Intel SGX access control itself is implemented as
an extension to the existing paging modes. See Section 38.5 for details.
Execution of Intel SGX instructions may set accessed and dirty flags on accesses to EPC pages that do not fault
even if the instruction later causes a fault for some other reason.
42.5
INTERACTIONS WITH VMX
Intel SGX functionality (including SGX1 and SGX2) can be made available to software running in either VMX root
operation or VMX non-root operation, as long as the processor is using a legal mode of operation (see Section
42.1).
A VMM has the flexibility to configure a VMCS to permit a guest to use any subset of the ENCLS leaf functions. Availability of the ENCLU leaf functions in VMX non-root operation has the same requirement as ENCLU leaf functions
outside of a virtualized environment.
Details of the VMCS control to allow VMM to configure support of Intel SGX in VMX non-root operation is described
in Section 42.5.1
42.5.1
VMM Controls to Configure Guest Support of Intel® SGX
Intel SGX capabilities are primarily exposed to the software via the CPUID instruction. VMMs can virtualize CPUID
instruction to expose/hide this capability to/from guests.
Some of Intel SGX resources are exposed/controlled via model-specific registers (see Section 37.7). VMMs can
virtualize these MSRs for the guests using the MSR bitmaps referenced by pointers in the VMCS.
The VMM can partition the Enclave Page Cache, and assign various partitions to (a subset of) its guests via the
usual memory-virtualization techniques such as paging or the extended page table mechanism (EPT).
The VMM can set the “enable ENCLS exiting” VM-execution controls to cause a VM exit when the ENCLS instruction
is executed in VMX non-root operation. If the “enable ENCLS exiting” control is 0, all of the ENCLS leaf functions are
permitted in VMX non-root operation. If the “enable ENCLS exiting” control is 1, execution of ENCLS leaf functions
in VMX non-root operation is governed by consulting the bits in a new 64-bit VM-execution control field called the
ENCLS-exiting bitmap (Each bit in the bitmap corresponds to an ENCLS leaf function with an EAX value that is identical to the bit’s position). When bits in the “ENCLS-exiting bitmap” are set, attempts to execute the corresponding
ENCLS leaf functions in VMX non-root operation causes VM exits. The checking for these VM exits occurs immediately after checking that CPL = 0.
42.5.2
Interactions with the Extended Page Table Mechanism (EPT)
Intel SGX instructions are fully compatible with the extended page-table mechanism (EPT; see Section 28.2).
All the memory operands passed into Intel SGX instructions are interpreted as offsets within the DS segment, and
the linear addresses generated by combining these offsets with DS segment register are subject to paging and EPT.
As with paging, enclaves abide by all the policies set up by the VMM.
The Intel SGX access control itself is implemented as an extension to paging and EPT, and may be more restrictive.
See Section 42.4 for details of this extension.
An execution of an Intel SGX instruction may set accessed and dirty flags for EPT (when enabled; see Section
28.2.4) on accesses to EPC pages that do not fault or cause VM exits even if the instruction later causes a fault or
VM exit for some other reason.
Vol. 3D 42-3
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
42.5.3
Interactions with APIC Virtualization
This section applies to Intel SGX in VMX non-root operation when the “virtualize APIC accesses” VM-execution
control is 1.
A memory access by an enclave instruction that implicitly uses a cached physical address is never checked for
overlap with the APIC-access page. Such accesses never cause APIC-access VM exits and are never redirected to
the virtual-APIC page. Implicit memory accesses can only be made to the SECS, the TCS, or the SSA of an enclave
(see Section 38.5.3.2).
An explicit Enclave Access (a linear memory access which is either from within an enclave into its ELRANGE, or an
access by an Intel SGX instruction that is expected to be in the EPC) that overlaps with the APIC-access page
causes a #PF exception (APIC page is expected to be outside of EPC).
Non-Enclave accesses made either by an Intel SGX instruction or by a logical processor inside an enclave to an
address that without SGX would have caused redirection to the virtual-APIC page instead cause an APIC-access
VM exit.
Other than implicit accesses made by Intel SGX instructions, guest-physical and physical accesses are not considered “enclave accesses”; consequently, such accesses result in undefined behavior if these accesses eventually
reach EPC. This applies to any non-enclave physical accesses.
While a logical processor is executing inside an enclave, an attempt to execute an instruction outside of ELRANGE
results in a #GP(0), even if the linear address would translate to a physical address that overlaps the APIC-access
page.
42.6
INTEL® SGX INTERACTIONS WITH ARCHITECTURALLY-VISIBLE EVENTS
All architecturally visible vectored events (IA32 exceptions, interrupts, SMI, NMI, INIT, VM exit) can be detected
while inside an enclave and will cause an asynchronous enclave exit if they are not blocked. Additionally, INT3, and
the SignalTXTMsg[SENTER] (i.e. GETSEC[SENTER]’s rendezvous event message) events also cause asynchronous
enclave exits. Note that SignalTXTMsg[SEXIT] (i.e. GETSEC[SEXIT]’s teardown message) does not cause an AEX.
On an AEX, information about the event causing the AEX is stored in the SSA (see Section 40.4 for details of AEX).
The information stored in the SSA only describes the first event that triggered the AEX. If parsing/delivery of the
first event results in detection of further events (e.g. VM exit, double fault, etc.), then the event information in the
SSA is not updated to reflect these subsequently detected events.
42.7
INTERACTIONS WITH THE PROCESSOR EXTENDED STATE AND
MISCELLANEOUS STATE
42.7.1
Requirements and Architecture Overview
Processor extended states are the ISA features that are enabled by the settings of CR4.OSXSAVE and the XCR0
register. Processor extended states are normally saved/restored by software via XSAVE/XRSTOR instructions.
Details of discovery of processor extended states and management of these states are described in CHAPTER 13 of
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Additionally, the following requirements apply to Intel SGX:
•
On an AEX, the Intel SGX architecture must protect the processor extended state and miscellaneous state by
saving them in the enclave’s state-save area (SSA), and clear the secrets from the processor extended state
that is used by an enclave.
•
Intel SGX architecture must verify that the SSA frame size is large enough to contain all the processor extended
states and miscelaneous state used by the enclave.
•
Intel SGX architecture must ensure that enclaves can only use processor extended state that is enabled by
system software in XCR0.
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INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
•
Enclave software should be able to discover only those processor extended state and miscellaneous state for
which such protection is enabled.
•
The processor extended states that are enabled inside the enclave must be approved by the enclave developer:
— Certain processor extended state (e.g., Memory Protection Extensions, see Chapter 17, “Intel® MPX” of
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1) modify the behavior of the
legacy ISA software. If such features are enabled for enclaves that do not understand those features, then
such a configuration could lead to a compromise of the enclave's security.
•
The processor extended states that are enabled inside the enclave must form an integral part of the enclave's
identity. This requirement has two implications:
— Service providers may decide to assign different trust level to the same enclave depending on the ISA
features the enclave is using.
To meet these requirements, the Intel SGX architecture defines a sub-field called X-Feature Request Mask (XFRM)
in the ATTRIBUTES field of the SECS. On enclave creation (ENCLS[ECREATE] leaf function), the required SSA frame
size is calculated by the processor from the list of enabled extended and miscellaneous states and verified against
the actual SSA frame size defined by SECS.SSAFRAMESIZE.
On enclave entry, after verifying that XFRM is only enabling features that are already enabled in XCR0, the value in
the XCR0 is saved internally by the processor, and is replaced by the XFRM. On enclave exit, the original value of
XCR0 is restored. Consequently, while inside the enclave, the processor extended states enabled in XFRM are in
enabled state, and those that are disabled in XFRM are in disabled state.
The entire ATTRIBUTES field, including the XFRM subfield is integral part of enclave's identity (i.e., its value is
included in reports generated by ENCLU[EREPORT], and select bits from this field can be included in key-derivation
for keys obtained via the ENCLU[EGETKEY] leaf function).
Enclave developers can create their enclave to work with certain features and fallback to another code path in case
those features aren't available (e.g. optimize for AVX and fallback to SSE). For this purpose Intel SGX provides the
following fields in SIGSTRUCT: ATTRIBUTES, ATTRIBUTESMASK, MISCSELECT, and MISCMASK. EINIT ensures that
the final SECS.ATTRIBUTES and SECS.MISCSELECT comply with the enclave developer's requirements as follows:
SIGSTRUCT.ATTRIBUTES & SIGSTRUCT.ATTRIBUTEMASK = SECS.ATTRIBUTES & SIGSTRUCT.ATTRIBUTEMASK
SIGSTRUCT.MISCSELECT & SIGSTRUCT.MISCMASK = SECS.MISCSELECT & SIGSTRUCT.MISCMASK.
On an asynchronous enclave exit, the processor extended states enabled by XFRM are saved in the current SSA
frame, and overwritten by synthetic state (see Section 40.3 for the definition of the synthetic state). When the
interrupted enclave is resumed via the ENCLU[ERESUME] leaf function, the saved state for processor extended
states enabled by XFRM is restored.
42.7.2
Relevant Fields in Various Data Structures
42.7.2.1
SECS.ATTRIBUTES.XFRM
The ATTRIBUTES field of the SECS data structure (see Section 38.7) contains a sub-field called XSAVE-Feature
Request Mask (XFRM). Software populates this field at the time of enclave creation according to the features that
are enabled by the operating system and approved by the enclave developer.
Intel SGX architecture guarantees that during enclave execution, the processor extended state configuration of the
processor is identical to what is required by the XFRM sub-field. All the processor extended states enabled in XFRM
are saved on AEX from the enclave and restored on ERESUME.
The XFRM sub-field has the same layout as XCR0, and has consistency requirements that are similar to those for
XCR0. Specifically, the consistency requirements on XFRM values depend on the processor implementation and the
set of features enabled in CR4.
Legal values for SECS.ATTRIBUTES.XFRM conform to these requirements:
•
•
XFRM[1:0] must be set to 0x3.
•
If the processor does support XSAVE, XFRM must contain a value that would be legal if loaded into XCR0.
If the processor does not support XSAVE, or if the system software has not enabled XSAVE, then XFRM[63:2]
must be zero.
Vol. 3D 42-5
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
The various consistency requirements are enforced at different times in the enclave's life cycle, and the exact
enforcement mechanisms are elaborated in Section 42.7.3 through Section 42.7.6.
On processors not supporting XSAVE, software should initialize XFRM to 0x3. On processors supporting XSAVE,
software should initialize XFRM to be a subset of XCR0 that would be present at the time of enclave execution.
Because bits 0 and 1 of XFRM must always be set, the use of Intel SGX requires that SSE be enabled (CR4.OSFXSR
= 1).
42.7.2.2
SECS.SSAFRAMESIZE
The SSAFRAMESIZE field in the SECS data structure specifies the number of pages which software allocated1 for
each SSA frame, including both the GPRSGX area, MISC area, the XSAVE area (x87 and XMM states are stored in
the latter area), and optionally padding between the MISC and XSAVE area. The GPRSGX area must hold all the
general-purpose registers and additional Intel SGX specific information. The MISC area must hold the Miscellaneous state as specified by SECS.MISCSELECT, the XSAVE area holds the set of processor extended states specified
by SECS.ATTRIBUTES.XFRM (see Section 38.9 for the layout of SSA and Section 42.7.3 for ECREATE's consistency
checks). The SSA is always in non-compacted format.
If the processor does not support XSAVE, the XSAVE area will always be 576 bytes; a copy of XFRM (which will be
set to 0x3) is saved at offset 512 on an AEX.
If the processor does support XSAVE, the length of the XSAVE area depends on SECS.ATTRIBUTES.XFRM. The
length would be equal to what CPUID.(EAX=0DH, ECX= 0):EBX would return if XCR0 were set to XFRM. The
following pseudo code illustrates how software can calculate this length using XFRM as the input parameter without
modifying XCR0:
offset = 576;
size_last_x = 0;
For x=2 to 63
IF (XFRM[x] != 0) Then
tmp_offset = CPUID.(EAX=0DH, ECX= x):EBX[31:0];
IF (tmp_offset >= offset + size_last_x) Then
offset = tmp_offset;
size_last_x = CPUID.(EAX=0DH, ECX= x):EAX[31:0];
FI;
FI;
EndFor
return (offset + size_last_x); (* compute_xsave_size(XFRM), see “ECREATE—Create an SECS page in the Enclave
Page Cache”*)
Where the non-zero bits in XFRM are a subset of non-zero bit fields in XCR0.
The size of the MISC region depends on the setting of SECS.MISCSELECT and can be calculated using the layout
information described in Section 38.9.2
42.7.2.3
XSAVE Area in SSA
The XSAVE area of an SSA frame begins at offset 0 of the frame.
42.7.2.4
MISC Area in SSA
The MISC area of an SSA frame is positioned immediately before the GPRSGX region.
42.7.2.5
SIGSTRUCT Fields
Intel SGX provides the flexibility for an enclave developer to choose the enclave's code path according to the
features that are enabled on the platform (e.g. optimize for AVX and fallback to SSE). See Section 42.7.1 for
details.
1. It is the responsibility of the enclave to actually allocate this memory.
42-6 Vol. 3D
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
SIGSTRUCT includes the following fields:
SIGSTRUCT.ATTRIBUTES, SIGSTRUCT.ATTRIBUTEMASK, SIGSTRUCT.MISCSELECT, SIGSTRUCT.MISCMASK.
42.7.2.6
REPORT.ATTRIBUTES.XFRM and REPORT.MISCSELECT
The processor extended states and miscellaneous states that are enabled inside the enclave form an integral part
of the enclave's identity and are therefore included in the enclave's report, as provided by the ENCLU[EREPORT]
leaf function. The REPORT structure includes the enclave's XFRM and MISCSELECT configurations.
42.7.2.7
KEYREQUEST
An enclave developer can specify which bits out of XFRM and MISCSELECT ENCLU[EGETKEY] should include in the
derivation of the sealing key by specifying ATTRIBUTESMASK and MISCMASK in the KEYREQUEST structure.
42.7.3
Processor Extended States and ENCLS[ECREATE]
The ECREATE leaf function of the ENCLS instruction enforces a number of consistency checks described earlier. The
execution of ENCLS[ECREATE] leaf function results in a #GP(0) in any of the following cases:
•
•
SECS.ATTRIBUTES.XFRM[1:0] is not 3.
The processor does not support XSAVE and any of the following is true:
— SECS.ATTRIBUTES.XFRM[63:2] is not 0.
— SECS.SSAFRAMESIZE is 0.
•
The processor supports XSAVE and any of the following is true:
— XSETBV would fault on an attempt to load XFRM into XCR0.
— XFRM[63]=1.
— The SSAFRAME is too small to hold required, enabled states (see Section 42.7.2.2).
42.7.4
Processor Extended States and ENCLU[EENTER]
42.7.4.1
Fault Checking
The EENTER leaf function of the ENCLU instruction enforces a number of consistency requirements described
earlier. The execution of the ENCLU[EENTER] leaf function results in a #GP(0) in any of the following cases:
•
•
If CR4.OSFXSR=0.
If The processor supports XSAVE and either of the following is true:
— CR4.OSXSAVE=0 and SECS.ATTRIBUTES.XFRM is not 3.
— (SECS.ATTRIBUTES.XFRM & XCR0) != SECS.ATTRIBUTES.XFRM
42.7.4.2
State Loading
If ENCLU[EENTER] is successful, the current value of XCR0 is saved internally by the processor and replaced by
SECS.ATTRIBUTES.XFRM.
Vol. 3D 42-7
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
42.7.5
Processor Extended States and AEX
42.7.5.1
State Saving
On an AEX, processor extended states are saved into the XSAVE area of the SSA frame in a compatible format with
XSAVE that was executed with EDX:EAX = SECS.ATTRIBUTES.XFRM, with the memory operand being the XSAVE
area, and (for 64-bit enclaves) as if REX.W=1. The XSTATE_BV part of the XSAVE header is saved with 0 for every
bit that is 0 in XFRM. Other bits may be saved as 0 if the state saved is initialized.
Note that enclave entry ensures that if CR4.OSXSAVE is set to 0, then SECS.ATTRIBUTES.XFRM is set to 3. It
should also be noted that it is not possible to enter an enclave with FXSAVE disabled.
42.7.5.2
State Synthesis
After saving the extended state, the processor restores XCR0 to the value it held at the time of the most recent
enclave entry.
The state of features corresponding to bits set in XFRM is synthesized. In general, these states are initialized.
Details of state synthesis on AEX are documented in Section 40.3.1.
42.7.6
Processor Extended States and ENCLU[ERESUME]
42.7.6.1
Fault Checking
The ERESUME leaf function of the ENCLU instruction enforces a number of consistency requirements described
earlier. Specifically, the ENCLU[ERESUME] leaf function results in a #GP(0) in any of the following cases:
•
•
CR4.OSFXSR=0.
The processor supports XSAVE and either of the following is true:
— CR4.OSXSAVE=0 and SECS.ATTRIBUTES.XFRM is not 3.
— (SECS.ATTRIBUTES.XFRM & XCR0) != SECS.ATTRIBUTES.XFRM.
A successful execution of ENCLU[ERESUME] loads state from the XSAVE area of the SSA frame in a fashion similar
to that used by the XRSTOR instruction. Data in the XSAVE area that would cause the XRSTOR instruction to fault
will cause the ENCLU[ERESUME] leaf function to fault. Examples include, but are not restricted to the following:
•
•
•
A bit is set in the XSTATE_BV field and clear in XFRM.
The required bytes in the header are not clear.
Loading data would set a reserved bit in MXCSR.
Any of these conditions will cause ERESUME to fault, even if CR4.OSXSAVE=0.
42.7.6.2
State Loading
If ENCLU[ERESUME] is successful, the current value of XCR0 is saved internally by the processor and replaced by
SECS.ATTRIBUTES.XFRM.
State is loaded from the XSAVE area of the SSA frame as if the XRSTOR instruction were executed with
XCR0=XFRM, EDX:EAX = XFRM, with the memory operand being the XSAVE area, and (for 64-bit enclaves) as if
REX.W=1.
ENCLU[ERESUME] ensures that a subsequent execution of XSAVEOPT inside the enclave will operate properly (e.g.,
by marking all state as modified).
42.7.7
Processor Extended States and ENCLU[EEXIT]
The ENCLU[EEXIT] leaf function does not perform any X-feature specific consistency checks, nor performs any
state synthesis. It is the responsibility of enclave software to clear any sensitive data from the registers before
42-8 Vol. 3D
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
executing EEXIT. However, successful execution of the ENCLU[EEXIT] leaf function restores XCR0 to the value it
held at the time of the most recent enclave entry.
42.7.8
Processor Extended States and ENCLU[EREPORT]
The ENCLU[EREPORT] leaf function creates the MAC-protected REPORT structure that reports on the enclave’s
identity. ENCLU[EREPORT] includes in the report the values of SECS.ATTRIBUTES.XFRM and SECS.MISCSELECT.
42.7.9
Processor Extended States and ENCLU[EGETKEY]
The ENCLU[EGETKEY] leaf function returns a cryptographic key based on the information provided by the KEYREQUEST structure. Intel SGX provides the means for isolation between different operating conditions by allowing an
enclave developer to select which bits out of XFRM and MISCSELECT need to be included in the derivation of the
keys.
42.8
INTERACTIONS WITH SMM
42.8.1
Availability of Intel® SGX instructions in SMM
Enclave instructions are not available in SMM, and any attempt to execute ENCLS or ENCLU instructions inside SMM
results in an invalid-opcode exception (#UD).
42.8.2
SMI while Inside an Enclave
If the logical processor executing inside an enclave receives an SMI, the logical processor exits the enclave asynchronously. The response to an SMI received while executing inside an enclave depends on whether the dualmonitor treatment is enabled. For detailed discussion of transfer to SMM, see Chapter 34, “System Management
Mode” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C.
If the logical processor executing inside an enclave receives an SMI when dual-monitor treatment is not enabled,
the logical processor exits the enclave asynchronously, and transfers the control to the SMM handler. In addition to
saving the synthetic architectural state to the SMRAM State Save Map (SSM), the logical processor also sets the
“Enclave Interruption” bit in the SMRAM SSM (bit position 1 in SMRAM field at offset 7EE0H).
If the logical processor executing inside an enclave receives an SMI when dual-monitor treatment is enabled, the
logical processor exits the enclave asynchronously, and transfers the control to the SMM monitor via SMM VM exit.
The SMM VM exit sets the “Enclave Interruption” bit in the Exit Reason (see Table 42-1) and in the Guest Interruptibility State field (see Table 42-2) of the SMM VMCS.
42.8.3
SMRAM Synthetic State of AEX Triggered by SMI
All processor registers saved in the SMRAM have the same synthetic values listed in Section 40.3. Additional
SMRAM fields that are treated specially on SMI are:
Table 42-1. SMRAM Synthetic States on Asynchronous Enclave Exit
Position
SMRAM Offset 07EE0H.Bit 1
Field
Value
ENCLAVE_INTERRUPTION Set to 1 if exit occurred in enclave mode
Writable
No
Vol. 3D 42-9
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
42.9
INTERACTIONS OF INIT, SIPI, AND WAIT-FOR-SIPI WITH INTEL® SGX
INIT received inside an enclave, while the logical processor is not in VMX operation, causes the logical processor to
exit the enclave asynchronously. After the AEX, the processor's architectural state is initialized to “Power-on” state
(Table 9.1 in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). If the logical processor
is BSP, then it proceeds to execute the BIOS initialization code. If the logical processor is an AP, it enters wait-forSIPI state.
INIT received inside an enclave, while the logical processor (LP) is in VMX root operation, follows regular Intel
Architecture behavior and is blocked.
INIT received inside an enclave, while the logical processor is in VMX non-root operation, causes an AEX. Subsequent to the AEX, the INIT causes a VM exit with the Enclave Interruption bit in the exit-reason field in the VMCS.
A processor cannot be inside an enclave in the wait-for-SIPI state. Consequently, a SIPI received while inside an
enclave is lost.
Intel SGX does not change the behavior of the processor in the wait-for-SIPI state.
The SGX-related processor states after INIT-SIPI-SIPI is as follows:
•
•
•
•
•
EPC Settings: Unchanged
EPCM: Unchanged
CPUID.LEAF_12H.*: Unchanged
ENCLAVE_MODE: 0 (LP exits enclave asynchronously)
MEE state: Unchanged
Software should be aware that following INIT-SIPI-SIPI, the EPC might contain valid pages and should take appropriate measures such as initialize the EPC with the EREMOVE leaf function.
42.10
INTERACTIONS WITH DMA
DMA is not allowed to access any Processor Reserved Memory.
42.11
INTERACTIONS WITH TXT
42.11.1 Enclaves Created Prior to Execution of GETSEC
Enclaves which have been created before the GETSEC[SENTER] leaf function are available for execution after the
successful completion of GETSEC[SENTER] and the corresponding SINIT ACM. Actions that a TXT Launched Environment performs in preparation to execute code in the Launched Environment, also applies to enclave code that
would run after GETSEC[SENTER].
42.11.2 Interaction of GETSEC with Intel® SGX
All leaf functions of the GETSEC instruction are illegal inside an enclave, and results in an invalid-opcode exception
(#UD).
Responding Logical Processors (RLP) which are executing inside an enclave at the time a GETSEC[SENTER] event
occurs perform an AEX from the enclave and then enter the Wait-for-SIPI state.
RLP executing inside an enclave at the time of GETSEC[SEXIT], behave as defined for GETSEC[SEXIT]-that is, the
RLPs pause during execution of SEXIT and resume after the completion of SEXIT.
The execution of a TXT launch does not affect Intel SGX configuration or security parameters.
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INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
42.11.3 Interactions with Authenticated Code Modules (ACMs)
Intel SGX only allows launching ACMs with an Intel SGX SVN that is at the same level or higher than the expected
Intel SGX SVN. The expected Intel SGX SVN is specified by BIOS and locked down by the processor on the first
successful execution of an Intel SGX instruction that doesn’t return an error code. Intel SGX provides interfaces for
system software to discover whether a non faulting Intel SGX instruction has been executed, and evaluate the suitability of the Intel SGX SVN value of any ACM that is expected to be launched by the OS or the VMM.
These interfaces are provided through a read-only MSR called the IA32_SGX_SVN_STATUS MSR (MSR address
500h). The IA32_SGX_SVN_STATUS MSR has the format shown in Table 42-2.
Table 42-2. Layout of the IA32_SGX_SVN_STATUS MSR
Bit Position
Name
ACM Module ID
Value
0
Lock
N.A.
• If 1, indicates that a non-faulting Intel SGX instruction has been
executed, consequently, launching a properly signed ACM but with Intel
SGX SVN value less than the BIOS specified Intel SGX SVN threshold
would lead to an TXT shutdown.
• If 0, indicates that the processor will allow a properly signed ACM to
launch irrespective of the Intel SGX SVN value of the ACM.
15:1
RSVD
N.A.
0
23:16
SGX_SVN_SINIT
SINIT ACM
• If CPUID.01H:ECX.SMX =1, this field reflects the expected threshold of
Intel SGX SVN for the SINIT ACM.
• If CPUID.01H:ECX.SMX =0, this field is reserved (0).
63:24
RSVD
N.A.
0
OS/VMM that wishes to launch an architectural ACM such as SINIT is expected to read the IA32_SGX_SVN_STATUS
MSR to determine whether the ACM can be launched or a new ACM is needed:
•
If either the Intel SGX SVN of the ACM is greater than the value reported by IA32_SGX_SVN_STATUS, or the
lock bit in the IA32_SGX_SVN_STATUS is not set, then the OS/VMM can safely launch the ACM.
•
If the Intel SGX SVN value reported in the corresponding component of the IA32_SGX_SVN_STATUS is greater
than the Intel SGX SVN value in the ACM's header, and if bit 0 of IA32_SGX_SVN_STATUS is 1, then the
OS/VMM should not launch that version of the ACM. It should obtain an updated version of the ACM either from
the BIOS or from an external resource.
However, OSVs/VMMs are strongly advised to update their version of the ACM any time they detect that the Intel
SGX SVN of the ACM carried by the OS/VMM is lower than that reported by IA32_SGX_SVN_STATUS MSR, irrespective of the setting of the lock bit.
42.12
INTERACTIONS WITH CACHING OF LINEAR-ADDRESS TRANSLATIONS
Entering and exiting an enclave causes the logical processor to flush all the global linear-address context as well as
the linear-address context associated with the current VPID and PCID. The MONITOR FSM is also cleared.
42.13
INTERACTIONS WITH INTEL® TRANSACTIONAL SYNCHRONIZATION
EXTENSIONS (INTEL® TSX)
1. ENCLU or ENCLS instructions inside an HLE region will cause the flow to be aborted and restarted non-speculatively. ENCLU or ENCLS instructions inside an RTM region will cause the flow to be aborted and transfer control to
the fallback handler.
2. If XBEGIN is executed inside an enclave, the processor does NOT check whether the address of the fallback
handler is within the enclave.
3. If an RTM transaction is executing inside an enclave and there is an attempt to fetch an instruction outside the
enclave, the transaction is aborted and control is transferred to the fallback handler. No #GP is delivered.
Vol. 3D 42-11
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
4. If an RTM transaction is executing inside an enclave and there is a data access to an address within the enclave
that denied due to EPCM content (e.g., to a page belonging to a different enclave), the transaction is aborted and
control is transferred to the fallback handler. No #GP is delivered.
5. If an RTM transaction executing inside an enclave aborts and the address of the fallback handler is outside the
enclave, a #GP is delivered after the abort (EIP reported is that of the fallback handler).
42.13.1 HLE and RTM Debug
RTM debug will be suppressed on opt-out enclave entry. After opt-out entry, the logical processor will behave as if
IA32_DEBUG_CTL[15]=0. Any #DB detected inside an RTM transaction region will just cause an abort with no
exception delivered.
After opt-in entry, if either DR7[11] = 0 OR IA32_DEBUGCTL[15] = 0, any #DB or #BP detected inside an RTM
transaction region will just cause an abort with no exception delivered.
After opt-in entry, if DR7[11] = 1 AND IA32_DEBUGCTL[15] = 1, any #DB or #BP detected inside an RTM translation will
•
•
•
•
terminate speculative execution,
set RIP to the address of the XBEGIN instruction, and
be delivered as #DB (implying an Intel SGX AEX; any #BP is converted to #DB).
DR6[16] will be cleared, indicating RTM debug (if the #DB causes a VM exit, DR6 is not modified but bit 16 of
the pending debug exceptions field in the VMCS will be set).
42.14
INTEL® SGX INTERACTIONS WITH S STATES
Whenever an Intel SGX enabled processor enters S3-S5 state, enclaves are destroyed. This is due to the EPC being
destroyed when power down occurs. It is the application runtime’s responsibility to re-instantiate an enclave after
a power transition for which the enclaves were destroyed.
42.15
INTEL® SGX INTERACTIONS WITH MACHINE CHECK ARCHITECTURE (MCA)
42.15.1 Interactions with MCA Events
All architecturally visible machine check events (#MC and CMCI) that are detected while inside an enclave cause an
asynchronous enclave exit.
Any machine check exception (#MC) that occurs after Intel SGX is first enables causes Intel SGX to be disabled,
(CPUID.SGX_Leaf.0:EAX[SGX1] == 0). It cannot be enabled until after the next reset.
42.15.2 Machine Check Enables (IA32_MCi_CTL)
All supported IA32_MCi_CTL bits for all the machine check banks must be set for Intel SGX to be available
(CPUID.SGX_Leaf.0:EAX[SGX1] == 1). Any act of clearing bits from '1 to '0 in any of the IA32_MCi_CTL register
may disable Intel SGX (set CPUID.SGX_Leaf.0:EAX[SGX1] to 0) until the next reset.
42.15.3 CR4.MCE
CR4.MCE can be set or cleared with no interactions with Intel SGX.
42-12 Vol. 3D
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
42.16
INTEL® SGX INTERACTIONS WITH PROTECTED MODE VIRTUAL
INTERRUPTS
ENCLS[EENTER] modifies neither EFLAGS.VIP nor EFLAGS.VIF.
ENCLS[ERESUME] loads EFLAGS in a manner similar to that of an execution of IRET with CPL = 3. This means that
ERESUME modifies neither EFLAGS.VIP nor EFLAGS.VIF regardless of the value of the EFLAGS image in the SSA
frame.
AEX saves EFLAGS.VIP and EFLAGS.VIF unmodified into the EFLAGS image in the SSA frame. AEX modifies neither
EFLAGS.VIP nor EFLAGS.VIF after saving EFLAGS.
If CR4.PVI = 1, CPL = 3, EFLAGS.VM = 0, IOPL < 3, EFLAGS.VIP = 1, and EFLAGS.VIF = 0, execution of STI causes
a #GP fault. In this case, STI modifies neither EFLAGS.IF nor EFLAGS.VIF. This behavior applies without change
within an enclave (where CPL is always 3). Note that, if IOPL = 3, STI always sets EFLAGS.IF without fault;
CR4.PVI, EFLAGS.VIP, and EFLAGS.VIF are neither consulted nor modified in this case.
42.17
INTEL SGX INTERACTION WITH PROTECTION KEYS
SGX interactions with PKRU are as follows:
•
CPUID.(EAX=12H, ECX=1):ECX.PKRU indicates whether SECS.ATTRIBUTES.XFRM.PKRU can be set. If
SECS.ATTRIBUTES.XFRM.PKRU is set, then PKRU is saved and cleared as part of AEX and is restored as part of
ERESUME. If CR4.PKE is set, an enclave can execute RDPKRU and WRKRU independent of whether
SECS.ATTRIBUTES.XFRM.PKRU is set.
SGX interactions with domain permission checks are as follows:
1) If CR4.PKE is not set, then legacy and SGX permission checks are not effected.
2) If CR4.PKE is set, then domain permission checks are applied to all non-enclave access and
enclave accesses to user pages in addition to legacy and SGX permission checks at a higher
priority than SGX permission checks.
3) Implicit accesses aren't subject to domain permission checks.
Vol. 3D 42-13
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
42-14 Vol. 3D
ENCLAVE CODE DEBUG AND PROFILING
CHAPTER 43
ENCLAVE CODE DEBUG AND PROFILING
Intel® SGX is architected to provide protection for production enclaves and permit enclave code developers to use
an SGX-aware debugger to effectively debug a non-production enclave (debug enclave). Intel SGX also allows a
non-SGX-aware debugger to debug non-enclave portions of the application without getting confused by enclave
instructions.
43.1
CONFIGURATION AND CONTROLS
43.1.1
Debug Enclave vs. Production Enclave
The SECS of each enclave provides a bit, SECS.ATTRIBUTES.DEBUG, indicating whether the enclave is a debug
enclave (if set) or a production enclave (if 0). If this bit is set, software outside the enclave can use
EDBGRD/EDBGWR to access the EPC memory of the enclave. The value of DEBUG is not included in the measurement of the enclave and therefore doesn't require an alternate SIGSTRUCT to be generated to debug the enclave.
The ATTRIBUTES field in the SECS is reported in the enclave's attestation, and is included in the key derivation.
Enclave secrets that were protected by the enclave using Intel SGX keys when it ran as a production enclave will
not be accessible by the debug enclave. A debugger needs to be aware that special debug content might be
required for a debug enclave to run in a meaningful way.
EPC memory belonging to a debug enclave can be accessed via the EDBGRD/EDBGWR leaf functions (see Section
41.4), while that belonging to a non-debug enclave cannot be accessed by these leaf functions.
43.1.2
Tool-Chain Opt-in
The TCS.FLAGS.DBGOPTIN bit controls interactions of certain debug and profiling features with enclaves, including
code/data breakpoints, TF, RF, monitor trap flag, BTF, LBRs, BTM, BTS, Intel Processor Trace, and performance
monitoring. This bit is forced to zero when EPC pages are added via EADD. A debugger can set this bit via EDBGWR
to the TCS of a debug enclave.
An enclave entry through a TCS with the TCS.FLAGS.DBGOPTIN set to 0 is called an opt-out entry. Conversely, an
enclave entry through a TCS with TCS.FLAGS.DBGOPTIN set to 1 is called an opt-in entry.
43.2
SINGLE STEP DEBUG
43.2.1
Single Stepping ENCLS Instruction Leafs
If the RFLAGS.TF bit is set at the beginning of ENCLS, then a single-step debug exception is pending as a trap-class
exception on the instruction boundary immediately after the ENCLS instruction. Additionally, if the instruction is
executed in VMX non-root operation and the “monitor trap flag” VM-execution control is 1, an MTF VM exit is
pending on the instruction boundary immediately after the instruction if the instruction does not fault.
43.2.2
Single Stepping ENCLU Instruction Leafs
The interactions of the unprivileged Intel SGX instruction ENCLU are leaf dependent.
An enclave entry via EENTER/ERESUME leaf functions of the ENCLU, in certain cases, may mask the RFLAGS.TF bit,
and mask the setting of the “monitor trap flag” VM-execution control. In such situations, an exit from the enclave,
either via the EEXIT leaf function or via an AEX unmasks the RFLAGS.TF bit and the “monitor trap flag” VM-execu-
Vol. 3D 43-1
ENCLAVE CODE DEBUG AND PROFILING
tion control. The details of this masking/unmasking and the pending of single stepping events across
EENTER/ERESUME/EEXIT/AEX are covered in detail in Section 43.2.3.
If the EFLAGS.TF bit is set at the beginning of EREPORT or EGETKEY leafs, and if the EFLAGS.TF is not masked by
the preceding enclave entry, then a single-step debug exception is pending on the instruction boundary immediately after the ENCLU instruction. Additionally, if the instruction is executed in VMX non-root operation and the
“monitor trap flag” VM-execution control is 1, and if the monitor trap flag is not masked by the preceding enclave
entry, then an MTF VM exit is pending on the instruction boundary immediately after the instruction.
If the instruction under consideration results in a fault, then the control flow goes to the fault handler, and no
single-step debug exception is asserted. In such a situation, if the instruction is executed in VMX non-root operation and the “monitor trap flag” VM-execution control is 1, an MTF VM exit is pending after the delivery of the fault
(or any nested exception). No MTF VM exit occurs if another VM exit occurs before reaching that boundary on which
an MTF VM exit would be pending.
43.2.3
Single-Stepping Enclave Entry with Opt-out Entry
43.2.3.1
Single Stepping without AEX
Figure 43-1 shows the most common case for single-stepping after an opt-out entry.
EENTER
ERESUME
Inst1
Inst2
Inst3
EEXIT
Inst4
TF/MTF
Handler
RFLAGS.TF
Single-Step #DB Pending
VMCS.MTF
MTF VM Exit Pending
SMI
INIT
#MC
Higher Priority
Handler
Figure 43-1. Single Stepping with Opt-out Entry - No AEX
In this scenario, if the RFLAGS.TF bit is set at the time of the enclave entry, then a single step debug exception is
pending on the instruction boundary after EEXIT. Additionally, if the enclave is executing in VMX non-root operation
and the “monitor trap flag” VM-execution control is 1, an MTF VM exit is pending on the instruction boundary after
EEXIT.
The value of the RFLAGS.TF bit at the end of EEXIT is the same as the value of RFLAGS.TF at the time of the enclave
entry.
43.2.3.2
Single Step Preempted by AEX Due to Non-SMI Event
Figure 43-2 shows the interaction of single stepping with AEX due to a non-SMI event after an opt-out entry.
43-2 Vol. 3D
ENCLAVE CODE DEBUG AND PROFILING
EENTER
ERESUME
Inst1
Inst2
Event Inside Enclave
Inst3
EEXIT
AEX
Inst4
TF/MTF
Handler
RFLAGS.TF
Single-Step #DB Pending
Higher Priority
Handler
VMCS.MTF
MTF VM Exit Pending
AEX
Handler
Figure 43-2. Single Stepping with Opt-out Entry -AEX Due to Non-SMI Event Before Single-Step Boundary
In this scenario, if the enclave is executing in VMX non-root operation and the “monitor trap flag” VM-execution
control is 1, an MTF VM exit is pending on the instruction boundary after the AEX. No MTF VM exit occurs if another
VM exit happens before reaching that instruction boundary.
The value of the RFLAGS.TF bit at the end of AEX is the same as the value of RFLAGS.TF at the time of the enclave
entry.
43.2.4
RFLAGS.TF Treatment on AEX
The value of EFLAGS.TF at the end of AEX from an opt-out enclave is same as the value of EFLAGS.TF at the time
of the enclave entry. The value of EFLAGS.TF at the end of AEX from an opt-in enclave is unmodified. The
EFLAGS.TF saved in GPR portion of the SSA on an AEX is 0. For more detail see EENTER and ERESUME in Chapter 5.
43.2.5
Restriction on Setting of TF after an Opt-Out Entry
Enclave entered through an opt-out entry is not allowed to set EFLAGS.TF. The POPF instruction forces RFLAGS.TF
to 0 if the enclave was entered through opt-out entry.
43.2.6
Trampoline Code Considerations
Any AEX from the enclave which results in the RFLAGS.TF =1 on the reporting stack will result in a single-step #DB
after the first instruction of the trampoline code if the trampoline is entered using the IRET instruction.
43.3
CODE AND DATA BREAKPOINTS
43.3.1
Breakpoint Suppression
Following an opt-out entry:
•
•
•
Instruction breakpoints are suppressed during execution in an enclave.
Data breakpoints are not triggered on accesses to the address range defined by ELRANGE.
Data breakpoints are triggered on accesses to addresses outside the ELRANGE
Vol. 3D 43-3
ENCLAVE CODE DEBUG AND PROFILING
Following an opt-in entry instruction and data breakpoints are not suppressed.
The processor does not report any matches on debug breakpoints that are suppressed on enclave entry. However,
the processor does not clear any bits in DR6 that were already set at the time of the enclave entry.
43.3.2
Reporting of Instruction Breakpoint on Next Instruction on a Debug Trap
A debug exception caused by the single-step execution mode or when a data breakpoint condition was met causes
the processor to perform an AEX. Following such an AEX, the processor reports in the debug status register (DR6)
matches of the new instruction pointer (the AEP address) in a breakpoint address register setup to detect instruction execution.
43.3.3
RF Treatment on AEX
RF flag value saved in SSA is the same as what would have been pushed on stack if the exception or event causing
the AEX occurred when executing outside an enclave (see Section 17.3.1.1). Following an AEX, the RF flag is 0 in
the synthetic state.
43.3.4
Breakpoint Matching in Intel® SGX Instruction Flows
Implicit accesses made by Intel SGX instructions to EPC regions do not trigger data breakpoints. Explicit accesses
made by ENCLS[ECREATE], ENCLS[EADD], ENCLS[EEXTEND], ENCLS[EINIT], ENCLS[EREMOVE],
ENCLS[ETRACK], ENCLS[EBLOCK], ENCLS[EPA], ENCLS[EWB], ENCLS[ELD], ENCLS[EDBGRD], ENCLS[EDBGWR],
ENCLU[EENTER], and ENCLU[ERESUME] to the EPC operands do not trigger data breakpoints.
Explicit accesses made by the Intel SGX instructions (ENCLU[EGETKEY] and ENCLU[EREPORT]) executed by an
enclave following an opt-in entry, trigger data breakpoints on accesses to their EPC operands. All Intel SGX instructions trigger data breakpoints on accesses to their non-EPC operands.
43.4
INT3 CONSIDERATION
43.4.1
Behavior of INT3 Inside an Enclave
Inside an enclave, INT3 delivers a fault-class exception and thus does not require the CPL to be less than DPL in the
IDT gate 3. Following opt-out entry, the instruction delivers #UD. Following opt-in entry, INT3 delivers #BP.
The RIP saved in the SSA on AEX is that of the INT3 instruction. The RIP saved on the stack ( or in the TSS or VMCS)
is that of the AEP.
If execution of INT3 in an enclave causes a VM exit, the event type in the VM-exit interruption information field indicates a hardware exception (type 3; not a software exception with type 6) and the VM-exit instruction length field
is saved as zero.
43.4.2
Debugger Considerations
The INT3 is fault-like inside an enclave and the RIP saved in the SSA on AEX is that of the INT3 instruction. Consequently, the debugger must not decrement SSA.RIP for #BP coming from an enclave to re-execute the instruction
at the RIP of the INT3 instruction on a subsequent enclave entry.
43.4.3
VMM Considerations
As described above, INT3 executed by enclave delivers #BP with “interruption type” of 3. A VMM that re-injects
#BP into the guest can obtain the VM entry interruption information from appropriate VMCS fields (as recommended in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C).
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ENCLAVE CODE DEBUG AND PROFILING
VMMs that create the VM-entry interruption information based on the interruption vector should use event type of
3 (instead of 6) when they detect a VM exit incident to enclave mode that is due to an event with vector 3.
43.5
BRANCH TRACING
43.5.1
BTF Treatment
When software enables single-stepping on branches then:
•
•
Following an opt-in entry using EENTER the processor generates a single step debug exception.
Following an EEXIT the processor generates a single-step debug exception
Enclave entry using ERESUME (opt-in or opt-out) and an AEX from the enclave do not cause generation of the
single-step debug exception.
43.5.2
LBR Treatment
43.5.2.1
LBR Stack on Opt-in Entry
Following an opt-in entry into an enclave, last branch recording facilities if enabled continued to store branch
records in the LBR stack MSRs as follows:
•
On enclave entry using EENTER/ERESUME, the processor push the address of EENTER/ERESUME instruction
into MSR_LASTBRANCH_n_FROM_IP, and the destination address of the EENTER/ERESUME into
MSR_LASTBRANCH_n_TO_IP.
•
On EEXIT, the processor pushes the address of EEXIT instruction into MSR_LASTBRANCH_n_FROM_IP, and the
address of EEXIT destination into MSR_LASTBRANCH_n_TO_IP.
•
On AEX, the processor pushes RIP saved in the SSA into MSR_LASTBRANCH_n_FROM_IP, and the address of
AEP into MSR_LASTBRANCH_n_TO_IP.
•
For every branch inside the enclave, a branch record is pushed on the LBR stack.
Figure 43-3 shows an example of LBR stack manipulation after an opt-in entry. Every arrow in this picture indicates
a branch record pushed on the LBR stack. The “From IP” of the branch record contains the linear address of the
instruction located at the start of the arrow, while the “To IP” of the branch record contains the linear address of the
instruction at the end of the arrow.
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ENCLAVE CODE DEBUG AND PROFILING
EENTER
Inst1
BR2
Inst3
Inst4
Fault
Inst4
AEP
AEP
OS
IRET
AEP
ERESUME
Inst4
BR5
Inst6
EEXIT
Inst7
Figure 43-3. LBR Stack Interaction with Opt-in Entry
43.5.2.2
LBR Stack on Opt-out Entry
An opt-out entry into an enclave suppresses last branch recording facilities, and enclave exit after an opt-out entry
un-suppresses last branch recording facilities.
Opt-out entry into an enclave does not push any record on LBR stack.
If last branch recording facilities were enabled at the time of enclave entry, then EEXIT following such an enclave
entry pushes one record on LBR stack. The MSR_LASTBRANCH_n_FROM_IP of such record holds the linear address
of the instruction (EENTER or ERESUME) that was used to enter the enclave, while the
MSR_LASTBRANCH_n_TO_IP of such record holds linear address of the destination of EEXIT.
Additionally, if last branch recording facilities were enabled at the time of enclave entry, then an AEX after such an
entry pushes one record on LBR stack, before pushing record for the event causing the AEX if the event pushes a
record on LBR stack. The MSR_LASTBRANCH_n_FROM_IP of the new record holds linear address of the instruction
(EENTER or ERESUME) that was used to enter the enclave, while MSR_LASTBRANCH_n_TO_IP of the new record
holds linear address of the AEP. If the event causing AEX pushes a record on LBR stack, then the
MSR_LASTBRANCH_n_FROM_IP for that record holds linear address of the AEP.
Figure 43-4 shows an example of LBR stack manipulation after an opt-out entry. Every arrow in this picture indicates a branch record pushed on the LBR stack. The “From IP” of the branch record contains the linear address of
the instruction located at the start of the arrow, while the “To IP” of the branch record contains the linear address
of the instruction at the end of the arrow.
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ENCLAVE CODE DEBUG AND PROFILING
EENTER
Inst1
BR2
Inst3
Inst4
Fault
AEP
AEP
OS
IRET
AEP
ERESUME
Inst4
BR5
Inst6
EEXIT
Inst7
Figure 43-4. LBR Stack Interaction with Opt-out Entry
43.5.2.3
Mispredict Bit, Record Type, and Filtering
All branch records resulting from Intel SGX instructions/AEXs are reported as predicted branches, and consequently, bit 63 of MSR_LASTBRANCH_n_FROM_IP for such records is set. Branch records due to these Intel SGX
operations are always non-HLE/non-RTM records.
EENTER, ERESUME, EEXIT, and AEX are considered to be far branches. Consequently, bit 8 in MSR_LBR_SELECT
controls filtering of the new records introduced by Intel SGX.
43.6
INTERACTION WITH PERFORMANCE MONITORING
43.6.1
IA32_PERF_GLOBAL_STATUS Enhancement
On processors supporting Intel SGX, the IA32_PERF_GLOBAL_STATUS MSR provides a bit indicator, known as “Anti
Side-channel Interference” (ASCI) at bit position 60. If this bit is 0, the performance monitoring data in various
performance monitoring counters are accumulated normally as defined by relevant architectural/microarchitectural conditions. If the ASCI bit is set, the contents in various performance monitoring counters can be affected by
the direct or indirect consequence of Intel SGX protection of enclave code executing in the processor.
43.6.2
Performance Monitoring with Opt-in Entry
An opt-in enclave entry allow performance monitoring logic to observe the contribution of enclave code executing
in the processor. Thus the contents of performance monitoring counters does not distinguish between contribution
originating from enclave code or otherwise. All counters, events, precise events, etc. continue to work as defined
in the IA32/Intel 64 Software Developer Manual. Consequently, bit 60 of IA32_PERF_GLOBAL_STATUS MSR is not
set.
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ENCLAVE CODE DEBUG AND PROFILING
43.6.3
Performance Monitoring with Opt-out Entry
In general, performance monitoring activities are suppressed when entering an opt-out enclave. This applies to all
thread-specific, configured performance monitoring, except for the cycle-counting fixed counter,
IA32_FIXED_CTR1 and IA32_FIXED_CTR2. Upon entering an opt-out enclave, IA32_FIXED_CTR0, IA32_PMCx will
stop accumulating counts. Additionally, if PEBS is configured to capture PEBS record for this thread, PEBS record
generation will also be suppressed. Consequently, bit 60 of IA32_PERF_GLOBAL_STATUS MSR is set.
Performance monitoring on the sibling thread may also be affected. Any one of IA32_FIXED_CTRx or IA32_PMCx
on the sibling thread configured to monitor thread-specific eventing logic with AnyThread =1 is demoted to count
only MyThread while an opt-out enclave is executing on the other thread.
43.6.4
Enclave Exit and Performance Monitoring
When a logical processor exits an enclave, either via ENCLU[EEXIT] or via AEX, all performance monitoring activity
(including PEBS) on that logical processor that was suppressed is unsuppressed.
Any counters that were demoted from AnyThread to MyThread on the sibling thread are promoted back to
AnyThread.
43.6.5
PEBS Record Generation on Intel® SGX Instructions
All leaf functions of the ENCLS instruction report “Eventing RIP” of the ENCLS instruction if a PEBS record is generated at the end of the instruction execution. Additionally, the EGETKEY and EREPORT leaf functions of the ENCLU
instruction report “Eventing RIP” of the ENCLU instruction if a PEBS record is generated at the end of the instruction
execution.
If the EENTER and ERESUME leaf functions are performing an opt-in entry report “Eventing RIP” of the ENCLU
instruction if a PEBS record is generated at the end of the instruction execution. On the other hand, if these leaf
functions are performing an opt-out entry, then these leaf functions result in PEBS being suppressed, and no PEBS
record is generated at the end of these instructions.
A PEBS record is generated if there is a PEBS event pending at the end of EEXIT (due to a counter overflowing
during enclave execution or during EEXIT execution). This PEBS record contains the architectural state of the
logical processor at the end of EEXIT. If the enclave was entered via an opt-in entry, then this record reports the
“Eventing RIP” as the linear address of the ENCLU[EEXIT] instruction. If the enclave was entered via an opt-out
entry, then the record reports the “Eventing RIP” as the linear address of the ENCLU[EENTER/ERESUME] instruction that performed the last enclave entry.
A PEBS record is generated after the AEX if there is a PEBS event pending at the end of AEX (due to a counter overflowing during enclave execution or during AEX execution). This PEBS record contains the synthetic state of the
logical processor that is established at the end of AEX. For opt-in entry, this record has the EVENTING_RIP set to
the RIP saved in the SSA. For opt-out entry, the record has the EVENTING_RIP set to the linear address of
EENTER/ERESUME used for the last enclave entry.
If the enclave was entered via an opt-in entry, then this record reports the “Eventing RIP” as the linear address in
the SSA of the enclave (a.k.a., the “Eventing LIP” inside the enclave). If the enclave was entered via an opt-out
entry, then the record reports the “Eventing RIP” as the linear address of the ENCLU[EENTER/ERESUME] instruction that performed the last enclave entry.
A second PEBS event may be pended during the Enclave Exiting Event (EEE). If the PEBS event is taken at the end
of delivery of the EEE then the “Eventing RIP” in this second PEBS record is the linear address of the AEP.
43.6.6
Exception-Handling on PEBS/BTS Loads/Stores after AEX
The operating system should allocate sections of the DS save area from a non-paged pool, and mark them as
accessed and dirty. If the loads/stores to any section of the DS save area incur faults then such faults are reported
to the OS/VMM immediately, and generation of the PEBS/BTS record is skipped and may leave the buffers in a state
where they have a partial PEBS or BTS records.
However, any events that are detected during PEBS/BTS record generation at the end of AEX and before delivering
the Enclave Exiting Event (EEE) cannot be reported immediately to the OS/VMM, as an event window is not open at
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ENCLAVE CODE DEBUG AND PROFILING
the end of AEX. Consequently, fault-like events such as page faults, EPT faults, EPT mis-configuration, and
accesses to APIC-access page detected on stores to the PEBS/BTS buffer are not reported, and generation of the
PEBS and/or BTS record at the end of AEX is aborted (this may leave the buffers in a state where they have partial
PEBS or BTS records). Trap-like events detected on stores to the PEBS/BTS buffer (such as debug traps) are
pended until the next instruction boundary, where they are handled according to the architecturally defined
priority. The processor continues the handling of the Enclave Exiting Event (SMI, NMI, interrupt, exception delivery,
VM exit, etc.) after aborting the PEBS/BTS record generation.
43.6.6.1
Other Interactions with Performance Monitoring
For opt-in entry, EENTER, ERESUME, EEXIT, and AEX are all treated as predicted far branches, and any counters
that are counting such branches are incremented by 1 as a part of retirement of these instructions. Retirement of
these instructions is also counted in any counters configured to count instructions retired.
For opt-out entry, execution inside an enclave is treated as a single predicted branch, and all branch-counting
performance monitoring counters are incremented accordingly. Additionally, such execution is also counted as a
single instruction, and all performance monitoring counters counting instructions are incremented accordingly.
Enclave entry does not affect any performance monitoring counters shared between cores.
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ENCLAVE CODE DEBUG AND PROFILING
43-10 Vol. 3D
APPENDIX A
VMX CAPABILITY REPORTING FACILITY
The ability of a processor to support VMX operation and related instructions is indicated by
CPUID.1:ECX.VMX[bit 5] = 1. A value 1 in this bit indicates support for VMX features.
Support for specific features detailed in Chapter 26 and other VMX chapters is determined by reading values from
a set of capability MSRs. These MSRs are indexed starting at MSR address 480H. VMX capability MSRs are readonly; an attempt to write them (with WRMSR) produces a general-protection exception (#GP(0)). They do not exist
on processors that do not support VMX operation; an attempt to read them (with RDMSR) on such processors
produces a general-protection exception (#GP(0)).
A.1
BASIC VMX INFORMATION
The IA32_VMX_BASIC MSR (index 480H) consists of the following fields:
•
Bits 30:0 contain the 31-bit VMCS revision identifier used by the processor. Processors that use the same VMCS
revision identifier use the same size for VMCS regions (see subsequent item on bits 44:32).1
•
•
Bit 31 is always 0.
•
Bit 48 indicates the width of the physical addresses that may be used for the VMXON region, each VMCS, and
data structures referenced by pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX transitions). If the bit is 0, these addresses are limited to the processor’s physical-address width.2 If the bit is 1,
these addresses are limited to 32 bits. This bit is always 0 for processors that support Intel 64 architecture.
•
If bit 49 is read as 1, the logical processor supports the dual-monitor treatment of system-management
interrupts and system-management mode. See Section 34.15 for details of this treatment.
•
Bits 53:50 report the memory type that should be used for the VMCS, for data structures referenced by
pointers in the VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
header. If software needs to access these data structures (e.g., to modify the contents of the MSR bitmaps), it
can configure the paging structures to map them into the linear-address space. If it does so, it should establish
mappings that use the memory type reported bits 53:50 in this MSR.3
Bits 44:32 report the number of bytes that software should allocate for the VMXON region and any VMCS
region. It is a value greater than 0 and at most 4096 (bit 44 is set if and only if bits 43:32 are clear).
As of this writing, all processors that support VMX operation indicate the write-back type. The values used are
given in Table A-1.
Table A-1. Memory Types Recommended for VMCS and Related Data Structures
Value(s)
Field
0
Uncacheable (UC)
1–5
Not used
6
Write Back (WB)
7–15
Not used
1. Earlier versions of this manual specified that the VMCS revision identifier was a 32-bit field in bits 31:0 of this MSR. For all processors produced prior to this change, bit 31 of this MSR was read as 0.
2. On processors that support Intel 64 architecture, the pointer must not set bits beyond the processor's physical address width.
3. Alternatively, software may map any of these regions or structures with the UC memory type. (This may be necessary for the MSEG
header.) Doing so is discouraged unless necessary as it will cause the performance of software accesses to those structures to suffer.
Vol. 3D A-1
VMX CAPABILITY REPORTING FACILITY
If software needs to access these data structures (e.g., to modify the contents of the MSR bitmaps), it can
configure the paging structures to map them into the linear-address space. If it does so, it should establish
mappings that use the memory type reported in this MSR.1
•
If bit 54 is read as 1, the processor reports information in the VM-exit instruction-information field on VM exits
due to execution of the INS and OUTS instructions (see Section 27.2.4). This reporting is done only if this bit is
read as 1.
•
Bit 55 is read as 1 if any VMX controls that default to 1 may be cleared to 0. See Appendix A.2 for details. It also
reports support for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and IA32_VMX_TRUE_ENTRY_CTLS. See
Appendix A.3.1, Appendix A.3.2, Appendix A.4, and Appendix A.5 for details.
•
The values of bits 47:45 and bits 63:56 are reserved and are read as 0.
A.2
RESERVED CONTROLS AND DEFAULT SETTINGS
As noted in Chapter 26, “VM Entries”, certain VMX controls are reserved and must be set to a specific value (0 or 1)
determined by the processor. The specific value to which a reserved control must be set is its default setting.
Software can discover the default setting of a reserved control by consulting the appropriate VMX capability MSR
(see Appendix A.3 through Appendix A.5).
Future processors may define new functionality for one or more reserved controls. Such processors would allow
each newly defined control to be set either to 0 or to 1. Software that does not desire a control’s new functionality
should set the control to its default setting. For that reason, it is useful for software to know the default settings of
the reserved controls.
Default settings partition the various controls into the following classes:
•
•
•
Always-flexible. These have never been reserved.
Default0. These are (or have been) reserved with a default setting of 0.
Default1. They are (or have been) reserved with a default setting of 1.
As noted in Appendix A.1, a logical processor uses bit 55 of the IA32_VMX_BASIC MSR to indicate whether any of
the default1 controls may be 0:
•
If bit 55 of the IA32_VMX_BASIC MSR is read as 0, all the default1 controls are reserved and must be 1.
VM entry will fail if any of these controls are 0 (see Section 26.2.1).
•
If bit 55 of the IA32_VMX_BASIC MSR is read as 1, not all the default1 controls are reserved, and some (but
not necessarily all) may be 0. The CPU supports four (4) new VMX capability MSRs:
IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3 through Appendix A.5 for details. (These MSRs are not
supported if bit 55 of the IA32_VMX_BASIC MSR is read as 0.)
See Section 31.5.1 for recommended software algorithms for proper capability detection of the default1 controls.
A.3
VM-EXECUTION CONTROLS
There are separate capability MSRs for the pin-based VM-execution controls, the primary processor-based VMexecution controls, and the secondary processor-based VM-execution controls. These are described in Appendix
A.3.1, Appendix A.3.2, and Appendix A.3.3, respectively.
1. Alternatively, software may map any of these regions or structures with the UC memory type. (This may be necessary for the MSEG
header.) Doing so is discouraged unless necessary as it will cause the performance of software accesses to those structures to suffer. The processor will continue to use the memory type reported in the VMX capability MSR IA32_VMX_BASIC with the exceptions
noted.
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VMX CAPABILITY REPORTING FACILITY
A.3.1
Pin-Based VM-Execution Controls
The IA32_VMX_PINBASED_CTLS MSR (index 481H) reports on the allowed settings of most of the pin-based
VM-execution controls (see Section 24.6.1):
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the pin-based
VM-execution controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if
control X is 0.
Exceptions are made for the pin-based VM-execution controls in the default1 class (see Appendix A.2). These
are bits 1, 2, and 4; the corresponding bits of the IA32_VMX_PINBASED_CTLS MSR are always read as 1. The
treatment of these controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any pin-based VM-execution control in
the default1 class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PINBASED_CTLS MSR (see
below) reports which of the pin-based VM-execution controls in the default1 class can be 0 on VM entry.
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in
the MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PINBASED_CTLS MSR (index 48DH)
reports on the allowed settings of all of the pin-based VM-execution controls:
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the pinbased VM-execution controls:
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the pin-based
VM-execution controls is contained in the IA32_VMX_PINBASED_CTLS MSR. (The
IA32_VMX_TRUE_PINBASED_CTLS MSR is not supported.)
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the pin-based
VM-execution controls is contained in the IA32_VMX_TRUE_PINBASED_CTLS MSR. Assuming that software
knows that the default1 class of pin-based VM-execution controls contains bits 1, 2, and 4, there is no need for
software to consult the IA32_VMX_PINBASED_CTLS MSR.
A.3.2
Primary Processor-Based VM-Execution Controls
The IA32_VMX_PROCBASED_CTLS MSR (index 482H) reports on the allowed settings of most of the primary
processor-based VM-execution controls (see Section 24.6.2):
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the primary
processor-based VM-execution controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to
1, VM entry fails if control X is 0.
Exceptions are made for the primary processor-based VM-execution controls in the default1 class (see
Appendix A.2). These are bits 1, 4–6, 8, 13–16, and 26; the corresponding bits of the
IA32_VMX_PROCBASED_CTLS MSR are always read as 1. The treatment of these controls by VM entry is
determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any of the primary processor-based VMexecution controls in the default1 class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PROCBASED_CTLS MSR (see
below) reports which of the primary processor-based VM-execution controls in the default1 class can be 0
on VM entry.
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
Vol. 3D A-3
VMX CAPABILITY REPORTING FACILITY
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PROCBASED_CTLS MSR (index 48EH)
reports on the allowed settings of all of the primary processor-based VM-execution controls:
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the
primary processor-based VM-execution controls:
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the primary
processor-based VM-execution controls is contained in the IA32_VMX_PROCBASED_CTLS MSR. (The
IA32_VMX_TRUE_PROCBASED_CTLS MSR is not supported.)
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the processorbased VM-execution controls is contained in the IA32_VMX_TRUE_PROCBASED_CTLS MSR. Assuming that
software knows that the default1 class of processor-based VM-execution controls contains bits 1, 4–6, 8, 13–
16, and 26, there is no need for software to consult the IA32_VMX_PROCBASED_CTLS MSR.
A.3.3
Secondary Processor-Based VM-Execution Controls
The IA32_VMX_PROCBASED_CTLS2 MSR (index 48BH) reports on the allowed settings of the secondary processorbased VM-execution controls (see Section 24.6.2). VM entries perform the following checks:
•
Bits 31:0 indicate the allowed 0-settings of these controls. These bits are always 0. This fact indicates that
VM entry allows each bit of the secondary processor-based VM-execution controls to be 0 (reserved bits must
be 0)
•
Bits 63:32 indicate the allowed 1-settings of these controls; the 1-setting is not allowed for any reserved bit.
VM entry allows control X (bit X of the secondary processor-based VM-execution controls) to be 1 if bit 32+X in
the MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X and the “activate secondary
controls” primary processor-based VM-execution control are both 1.
The IA32_VMX_PROCBASED_CTLS2 MSR exists only on processors that support the 1-setting of the “activate
secondary controls” VM-execution control (only if bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1).
A.4
VM-EXIT CONTROLS
The IA32_VMX_EXIT_CTLS MSR (index 483H) reports on the allowed settings of most of the VM-exit controls (see
Section 24.7.1):
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the VM-exit
controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0.
Exceptions are made for the VM-exit controls in the default1 class (see Appendix A.2). These are bits 0–8, 10,
11, 13, 14, 16, and 17; the corresponding bits of the IA32_VMX_EXIT_CTLS MSR are always read as 1. The
treatment of these controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any VM-exit control in the default1 class
is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_EXIT_CTLS MSR (see below)
reports which of the VM-exit controls in the default1 class can be 0 on VM entry.
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control 32+X to be 1 if bit X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_EXIT_CTLS MSR (index 48FH) reports on
the allowed settings of all of the VM-exit controls:
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.
A-4 Vol. 3D
VMX CAPABILITY REPORTING FACILITY
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the
VM-exit controls:
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the VM-exit
controls is contained in the IA32_VMX_EXIT_CTLS MSR. (The IA32_VMX_TRUE_EXIT_CTLS MSR is not
supported.)
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the VM-exit
controls is contained in the IA32_VMX_TRUE_EXIT_CTLS MSR. Assuming that software knows that the default1
class of VM-exit controls contains bits 0–8, 10, 11, 13, 14, 16, and 17, there is no need for software to consult
the IA32_VMX_EXIT_CTLS MSR.
A.5
VM-ENTRY CONTROLS
The IA32_VMX_ENTRY_CTLS MSR (index 484H) reports on the allowed settings of most of the VM-entry controls
(see Section 24.8.1):
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the VM-entry
controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0.
Exceptions are made for the VM-entry controls in the default1 class (see Appendix A.2). These are bits 0–8 and
12; the corresponding bits of the IA32_VMX_ENTRY_CTLS MSR are always read as 1. The treatment of these
controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any VM-entry control in the default1
class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_ENTRY_CTLS MSR (see below)
reports which of the VM-entry controls in the default1 class can be 0 on VM entry.
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry fails if bit X is 1 in the VM-entry controls
and bit 32+X is 0 in this MSR.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_ENTRY_CTLS MSR (index 490H) reports
on the allowed settings of all of the VM-entry controls:
•
Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.
•
Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control 32+X to be 1 if bit X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the
VM-entry controls:
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the VM-entry
controls is contained in the IA32_VMX_ENTRY_CTLS MSR. (The IA32_VMX_TRUE_ENTRY_CTLS MSR is not
supported.)
•
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the VM-entry
controls is contained in the IA32_VMX_TRUE_ENTRY_CTLS MSR. Assuming that software knows that the
default1 class of VM-entry controls contains bits 0–8 and 12, there is no need for software to consult the
IA32_VMX_ENTRY_CTLS MSR.
A.6
MISCELLANEOUS DATA
The IA32_VMX_MISC MSR (index 485H) consists of the following fields:
•
Bits 4:0 report a value X that specifies the relationship between the rate of the VMX-preemption timer and that
of the timestamp counter (TSC). Specifically, the VMX-preemption timer (if it is active) counts down by 1 every
time bit X in the TSC changes due to a TSC increment.
Vol. 3D A-5
VMX CAPABILITY REPORTING FACILITY
•
If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA into the “IA-32e mode guest” VM-entry control;
see Section 27.2 for more details. This bit is read as 1 on any logical processor that supports the 1-setting of
the “unrestricted guest” VM-execution control.
•
Bits 8:6 report, as a bitmap, the activity states supported by the implementation:
— Bit 6 reports (if set) the support for activity state 1 (HLT).
— Bit 7 reports (if set) the support for activity state 2 (shutdown).
— Bit 8 reports (if set) the support for activity state 3 (wait-for-SIPI).
If an activity state is not supported, the implementation causes a VM entry to fail if it attempts to establish that
activity state. All implementations support VM entry to activity state 0 (active).
•
If bit 14 is read as 1, Intel® Processor Trace (Intel PT) can be used in VMX operation. If the processor supports
Intel PT but does not allow it to be used in VMX operation, execution of VMXON clears IA32_RTIT_CTL.TraceEn
(see “VMXON—Enter VMX Operation” in Chapter 30); any attempt to set that bit while in VMX operation
(including VMX root operation) using the WRMSR instruction causes a general-protection exception.
•
If bit 15 is read as 1, the RDMSR instruction can be used in system-management mode (SMM) to read the
IA32_SMBASE MSR (MSR address 9EH). See Section 34.15.6.3.
•
Bits 24:16 indicate the number of CR3-target values supported by the processor. This number is a value
between 0 and 256, inclusive (bit 24 is set if and only if bits 23:16 are clear).
•
Bits 27:25 is used to compute the recommended maximum number of MSRs that should appear in the VM-exit
MSR-store list, the VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if the value bits 27:25 of
IA32_VMX_MISC is N, then 512 * (N + 1) is the recommended maximum number of MSRs to be included in
each list. If the limit is exceeded, undefined processor behavior may result (including a machine check during
the VMX transition).
•
If bit 28 is read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set to 1. VMXOFF unblocks SMIs unless
IA32_SMM_MONITOR_CTL[bit 2] is 1 (see Section 34.14.4).
•
If bit 29 is read as 1, software can use VMWRITE to write to any supported field in the VMCS; otherwise,
VMWRITE cannot be used to modify VM-exit information fields.
•
If bit 30 is read as 1, VM entry allows injection of a software interrupt, software exception, or privileged
software exception with an instruction length of 0.
•
•
Bits 63:32 report the 32-bit MSEG revision identifier used by the processor.
Bits 13:9 and bit 31 are reserved and are read as 0.
A.7
VMX-FIXED BITS IN CR0
The IA32_VMX_CR0_FIXED0 MSR (index 486H) and IA32_VMX_CR0_FIXED1 MSR (index 487H) indicate how bits
in CR0 may be set in VMX operation. They report on bits in CR0 that are allowed to be 0 and to be 1, respectively,
in VMX operation. If bit X is 1 in IA32_VMX_CR0_FIXED0, then that bit of CR0 is fixed to 1 in VMX operation. Similarly, if bit X is 0 in IA32_VMX_CR0_FIXED1, then that bit of CR0 is fixed to 0 in VMX operation. It is always the case
that, if bit X is 1 in IA32_VMX_CR0_FIXED0, then that bit is also 1 in IA32_VMX_CR0_FIXED1; if bit X is 0 in
IA32_VMX_CR0_FIXED1, then that bit is also 0 in IA32_VMX_CR0_FIXED0. Thus, each bit in CR0 is either fixed to
0 (with value 0 in both MSRs), fixed to 1 (1 in both MSRs), or flexible (0 in IA32_VMX_CR0_FIXED0 and 1 in
IA32_VMX_CR0_FIXED1).
A.8
VMX-FIXED BITS IN CR4
The IA32_VMX_CR4_FIXED0 MSR (index 488H) and IA32_VMX_CR4_FIXED1 MSR (index 489H) indicate how bits
in CR4 may be set in VMX operation. They report on bits in CR4 that are allowed to be 0 and 1, respectively, in VMX
operation. If bit X is 1 in IA32_VMX_CR4_FIXED0, then that bit of CR4 is fixed to 1 in VMX operation. Similarly, if
bit X is 0 in IA32_VMX_CR4_FIXED1, then that bit of CR4 is fixed to 0 in VMX operation. It is always the case that,
if bit X is 1 in IA32_VMX_CR4_FIXED0, then that bit is also 1 in IA32_VMX_CR4_FIXED1; if bit X is 0 in
IA32_VMX_CR4_FIXED1, then that bit is also 0 in IA32_VMX_CR4_FIXED0. Thus, each bit in CR4 is either fixed to
A-6 Vol. 3D
VMX CAPABILITY REPORTING FACILITY
0 (with value 0 in both MSRs), fixed to 1 (1 in both MSRs), or flexible (0 in IA32_VMX_CR4_FIXED0 and 1 in
IA32_VMX_CR4_FIXED1).
A.9
VMCS ENUMERATION
The IA32_VMX_VMCS_ENUM MSR (index 48AH) provides information to assist software in enumerating fields in
the VMCS.
As noted in Section 24.11.2, each field in the VMCS is associated with a 32-bit encoding which is structured as
follows:
•
•
•
•
•
•
Bits 31:15 are reserved (must be 0).
Bits 14:13 indicate the field’s width.
Bit 12 is reserved (must be 0).
Bits 11:10 indicate the field’s type.
Bits 9:1 is an index field that distinguishes different fields with the same width and type.
Bit 0 indicates access type.
IA32_VMX_VMCS_ENUM indicates to software the highest index value used in the encoding of any field supported
by the processor:
•
•
Bits 9:1 contain the highest index value used for any VMCS encoding.
Bit 0 and bits 63:10 are reserved and are read as 0.
A.10
VPID AND EPT CAPABILITIES
The IA32_VMX_EPT_VPID_CAP MSR (index 48CH) reports information about the capabilities of the logical
processor with regard to virtual-processor identifiers (VPIDs, Section 28.1) and extended page tables (EPT, Section
28.2):
•
If bit 0 is read as 1, the processor supports execute-only translations by EPT. This support allows software to
configure EPT paging-structure entries in which bits 1:0 are clear (indicating that data accesses are not
allowed) and bit 2 is set (indicating that instruction fetches are allowed).1
•
•
Bit 6 indicates support for a page-walk length of 4.
•
If bit 14 is read as 1, the logical processor allows software to configure the EPT paging-structure memory type
to be write-back (WB).
•
If bit 16 is read as 1, the logical processor allows software to configure a EPT PDE to map a 2-Mbyte page (by
setting bit 7 in the EPT PDE).
•
If bit 17 is read as 1, the logical processor allows software to configure a EPT PDPTE to map a 1-Gbyte page (by
setting bit 7 in the EPT PDPTE).
•
Support for the INVEPT instruction (see Chapter 30 and Section 28.3.3.1).
If bit 8 is read as 1, the logical processor allows software to configure the EPT paging-structure memory type
to be uncacheable (UC); see Section 24.6.11.
— If bit 20 is read as 1, the INVEPT instruction is supported.
— If bit 25 is read as 1, the single-context INVEPT type is supported.
— If bit 26 is read as 1, the all-context INVEPT type is supported.
•
If bit 21 is read as 1, accessed and dirty flags for EPT are supported (see Section 28.2.4).
1. If the “mode-based execute control for EPT” VM-execution control is 1, setting bit 0 indicates also that software may also configure
EPT paging-structure entries in which bits 1:0 are both clear and in which bit 10 is set (indicating a translation that can be used to
fetch instructions from a supervisor-mode linear address or a user-mode linear address).
Vol. 3D A-7
VMX CAPABILITY REPORTING FACILITY
•
If bit 22 is read as 1, the processor reports advanced VM-exit information for EPT violations (see Section
27.2.1). This reporting is done only if this bit is read as 1.
•
Support for the INVVPID instruction (see Chapter 30 and Section 28.3.3.1).
— If bit 32 is read as 1, the INVVPID instruction is supported.
— If bit 40 is read as 1, the individual-address INVVPID type is supported.
— If bit 41 is read as 1, the single-context INVVPID type is supported.
— If bit 42 is read as 1, the all-context INVVPID type is supported.
— If bit 43 is read as 1, the single-context-retaining-globals INVVPID type is supported.
•
Bits 5:1, bit 7, bits 13:9, bit 15, bits 19:18, bits 24:23, bits 31:27, bits 39:33, and bits 63:44 are reserved
and are read as 0.
The IA32_VMX_EPT_VPID_CAP MSR exists only on processors that support the 1-setting of the “activate secondary
controls” VM-execution control (only if bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1) and that support
either the 1-setting of the “enable EPT” VM-execution control (only if bit 33 of the IA32_VMX_PROCBASED_CTLS2
MSR is 1) or the 1-setting of the “enable VPID” VM-execution control (only if bit 37 of the
IA32_VMX_PROCBASED_CTLS2 MSR is 1).
A.11
VM FUNCTIONS
The IA32_VMX_VMFUNC MSR (index 491H) reports on the allowed settings of the VM-function controls (see
Section 24.6.14). VM entry allows bit X of the VM-function controls to be 1 if bit X in the MSR is set to 1; if bit X in
the MSR is cleared to 0, VM entry fails if bit X of the VM-function controls, the “activate secondary controls” primary
processor-based VM-execution control, and the “enable VM functions” secondary processor-based VM-execution
control are all 1.
The IA32_VMX_VMFUNC MSR exists only on processors that support the 1-setting of the “activate secondary
controls” VM-execution control (only if bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1) and the 1-setting of
the “enable VM functions” secondary processor-based VM-execution control (only if bit 45 of the
IA32_VMX_PROCBASED_CTLS2 MSR is 1).
A-8 Vol. 3D
APPENDIX B
FIELD ENCODING IN VMCS
Every component of the VMCS is encoded by a 32-bit field that can be used by VMREAD and VMWRITE. Section
24.11.2 describes the structure of the encoding space (the meanings of the bits in each 32-bit encoding).
This appendix enumerates all fields in the VMCS and their encodings. Fields are grouped by width (16-bit, 32-bit,
etc.) and type (guest-state, host-state, etc.)
B.1
16-BIT FIELDS
A value of 0 in bits 14:13 of an encoding indicates a 16-bit field. Only guest-state areas and the host-state area
contain 16-bit fields. As noted in Section 24.11.2, each 16-bit field allows only full access, meaning that bit 0 of its
encoding is 0. Each such encoding is thus an even number.
B.1.1
16-Bit Control Fields
A value of 0 in bits 11:10 of an encoding indicates a control field. These fields are distinguished by their index value
in bits 9:1. Table B-1 enumerates the 16-bit control fields.
Table B-1. Encoding for 16-Bit Control Fields (0000_00xx_xxxx_xxx0B)
Field Name
Virtual-processor identifier
(VPID)1
2
Posted-interrupt notification vector
EPTP
index3
Index
Encoding
000000000B
00000000H
000000001B
00000002H
000000010B
00000004H
NOTES:
1. This field exists only on processors that support the 1-setting of the “enable VPID” VM-execution control.
2. This field exists only on processors that support the 1-setting of the “process posted interrupts” VM-execution control.
3. This field exists only on processors that support the 1-setting of the “EPT-violation #VE” VM-execution control.
B.1.2
16-Bit Guest-State Fields
A value of 2 in bits 11:10 of an encoding indicates a field in the guest-state area. These fields are distinguished by
their index value in bits 9:1. Table B-2 enumerates 16-bit guest-state fields.
Table B-2. Encodings for 16-Bit Guest-State Fields (0000_10xx_xxxx_xxx0B)
Field Name
Index
Encoding
Guest ES selector
000000000B
00000800H
Guest CS selector
000000001B
00000802H
Guest SS selector
000000010B
00000804H
Guest DS selector
000000011B
00000806H
Guest FS selector
000000100B
00000808H
Guest GS selector
000000101B
0000080AH
Guest LDTR selector
000000110B
0000080CH
Guest TR selector
000000111B
0000080EH
Vol. 3D B-1
FIELD ENCODING IN VMCS
Table B-2. Encodings for 16-Bit Guest-State Fields (0000_10xx_xxxx_xxx0B) (Contd.)
Field Name
Index
Encoding
Guest interrupt status
000001000B
00000810H
2
000001001B
00000812H
1
PML index
NOTES:
1. This field exists only on processors that support the 1-setting of the “virtual-interrupt delivery” VM-execution control.
2. This field exists only on processors that support the 1-setting of the “enable PML” VM-execution control.
B.1.3
16-Bit Host-State Fields
A value of 3 in bits 11:10 of an encoding indicates a field in the host-state area. These fields are distinguished by
their index value in bits 9:1. Table B-3 enumerates the 16-bit host-state fields.
Table B-3. Encodings for 16-Bit Host-State Fields (0000_11xx_xxxx_xxx0B)
Field Name
Index
Encoding
Host ES selector
000000000B
00000C00H
Host CS selector
000000001B
00000C02H
Host SS selector
000000010B
00000C04H
Host DS selector
000000011B
00000C06H
Host FS selector
000000100B
00000C08H
Host GS selector
000000101B
00000C0AH
Host TR selector
000000110B
00000C0CH
B.2
64-BIT FIELDS
A value of 1 in bits 14:13 of an encoding indicates a 64-bit field. There are 64-bit fields only for controls and for
guest state. As noted in Section 24.11.2, every 64-bit field has two encodings, which differ on bit 0, the access
type. Thus, each such field has an even encoding for full access and an odd encoding for high access.
B.2.1
64-Bit Control Fields
A value of 0 in bits 11:10 of an encoding indicates a control field. These fields are distinguished by their index value
in bits 9:1. Table B-4 enumerates the 64-bit control fields.
Table B-4. Encodings for 64-Bit Control Fields (0010_00xx_xxxx_xxxAb)
Field Name
Index
Address of I/O bitmap A (full)
000000000B
Address of I/O bitmap A (high)
Address of I/O bitmap B (full)
000000001B
Address of I/O bitmap B (high)
Address of MSR bitmaps
(full)1
1
Address of MSR bitmaps (high)
VM-exit MSR-store address (full)
VM-exit MSR-store address (high)
B-2 Vol. 3D
000000010B
000000011B
Encoding
00002000H
00002001H
00002002H
00002003H
00002004H
00002005H
00002006H
00002007H
FIELD ENCODING IN VMCS
Table B-4. Encodings for 64-Bit Control Fields (0010_00xx_xxxx_xxxAb) (Contd.)
Field Name
Index
VM-exit MSR-load address (full)
000000100B
VM-exit MSR-load address (high)
VM-entry MSR-load address (full)
000000101B
VM-entry MSR-load address (high)
Executive-VMCS pointer (full)
000000110B
Executive-VMCS pointer (high)
PML address
(full)2
000000111B
2
PML address (high)
TSC offset (full)
000001000B
TSC offset (high)
Virtual-APIC address
(full)3
000001001B
3
Virtual-APIC address (high)
APIC-access address
(full)4
APIC-access address
(high)4
000001010B
Posted-interrupt descriptor address
(full)5
Posted-interrupt descriptor address
(high)5
VM-function controls
000001011B
(full)6
000001100B
6
VM-function controls (high)
EPT pointer (EPTP;
full)7
EPT pointer (EPTP;
high)7
000001101B
EOI-exit bitmap 0 (EOI_EXIT0;
full)8
EOI-exit bitmap 0 (EOI_EXIT0;
high)8
EOI-exit bitmap 1 (EOI_EXIT1;
full)8
000001110B
000001111B
8
EOI-exit bitmap 1 (EOI_EXIT1; high)
EOI-exit bitmap 2 (EOI_EXIT2;
full)8
EOI-exit bitmap 2 (EOI_EXIT2;
high)8
EOI-exit bitmap 3 (EOI_EXIT3;
full)8
EOI-exit bitmap 3 (EOI_EXIT3;
high)8
EPTP-list address
000010000B
000010001B
(full)9
EPTP-list address (high)
000010010B
9
VMREAD-bitmap address
(full)10
VMREAD-bitmap address
(high)10
VMWRITE-bitmap address
(full)10
VMWRITE-bitmap address
(high)10
Virtualization-exception information address
000010011B
000010100B
(full)11
11
Virtualization-exception information address (high)
XSS-exiting bitmap (full)
XSS-exiting bitmap
000010101B
12
(high)12
000010110B
Encoding
00002008H
00002009H
0000200AH
0000200BH
0000200CH
0000200DH
0000200EH
0000200FH
00002010H
00002011H
00002012H
00002013H
00002014H
00002015H
00002016H
00002017H
00002018H
00002019H
0000201AH
0000201BH
0000201CH
0000201DH
0000201EH
0000201FH
00002020H
00002021H
00002022H
00002023H
00002024H
00002025H
00002026H
00002027H
00002028H
00002029H
0000202AH
0000202BH
0000202CH
0000202DH
Vol. 3D B-3
FIELD ENCODING IN VMCS
Table B-4. Encodings for 64-Bit Control Fields (0010_00xx_xxxx_xxxAb) (Contd.)
Field Name
Index
ENCLS-exiting bitmap
(full)13
ENCLS-exiting bitmap (high)
13
000010111B
14
TSC multiplier (full)
TSC multiplier
000011001B
(high)14
Encoding
0000202EH
0000202FH
00002032H
00002033H
NOTES:
1. This field exists only on processors that support the 1-setting of the “use MSR bitmaps”
VM-execution control.
2. This field exists only on processors that support the 1-setting of the “enable PML” VM-execution control.
3. This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control.
4. This field exists only on processors that support the 1-setting of the “virtualize APIC accesses” VM-execution control.
5. This field exists only on processors that support the 1-setting of the “process posted interrupts” VM-execution control.
6. This field exists only on processors that support the 1-setting of the “enable VM functions” VM-execution control.
7. This field exists only on processors that support the 1-setting of the “enable EPT” VM-execution control.
8. This field exists only on processors that support the 1-setting of the “virtual-interrupt delivery” VM-execution control.
9. This field exists only on processors that support the 1-setting of the “EPTP switching” VM-function control.
10. This field exists only on processors that support the 1-setting of the “VMCS shadowing” VM-execution control.
11. This field exists only on processors that support the 1-setting of the “EPT-violation #VE” VM-execution control.
12. This field exists only on processors that support the 1-setting of the “enable XSAVES/XRSTORS” VM-execution control.
13. This field exists only on processors that support the 1-setting of the “enable ENCLS exiting” VM-execution control.
14. This field exists only on processors that support the 1-setting of the “use TSC scaling” VM-execution control.
B.2.2
64-Bit Read-Only Data Field
A value of 1 in bits 11:10 of an encoding indicates a read-only data field. These fields are distinguished by their
index value in bits 9:1. There is only one such 64-bit field as given in Table B-5.(As with other 64-bit fields, this one
has two encodings.)
Table B-5. Encodings for 64-Bit Read-Only Data Field (0010_01xx_xxxx_xxxAb)
Field Name
Index
Guest-physical address (full)
Guest-physical address
1
(high)1
000000000B
Encoding
00002400H
00002401H
NOTES:
1. This field exists only on processors that support the 1-setting of the "enable EPT” VM-execution control.
B.2.3
64-Bit Guest-State Fields
A value of 2 in bits 11:10 of an encoding indicates a field in the guest-state area. These fields are distinguished by
their index value in bits 9:1. Table B-6 enumerates the 64-bit guest-state fields.
Table B-6. Encodings for 64-Bit Guest-State Fields (0010_10xx_xxxx_xxxAb)
Field Name
VMCS link pointer (full)
VMCS link pointer (high)
Guest IA32_DEBUGCTL (full)
Guest IA32_DEBUGCTL (high)
B-4 Vol. 3D
Index
000000000B
000000001B
Encoding
00002800H
00002801H
00002802H
00002803H
FIELD ENCODING IN VMCS
Table B-6. Encodings for 64-Bit Guest-State Fields (0010_10xx_xxxx_xxxAb) (Contd.)
Field Name
Index
Encoding
1
Guest IA32_PAT (full)
00002804H
000000010B
1
Guest IA32_PAT (high)
00002805H
2
Guest IA32_EFER (full)
Guest IA32_EFER
00002806H
000000011B
(high)2
00002807H
3
Guest IA32_PERF_GLOBAL_CTRL (full)
Guest IA32_PERF_GLOBAL_CTRL
Guest PDPTE0
(high)3
(full)4
00002809H
0000280AH
000000101B
4
Guest PDPTE0 (high)
Guest PDPTE1 (full)
00002808H
000000100B
0000280BH
4
Guest PDPTE1
(high)4
Guest PDPTE2
(full)4
Guest PDPTE2 (high)
Guest PDPTE3
Guest PDPTE3
(high)4
0000280DH
0000280EH
000000111B
4
(full)4
0000280CH
000000110B
0000280FH
00002810H
000001000B
Guest IA32_BNDCFGS
(full)5
Guest IA32_BNDCFGS
(high)5
00002811H
00002812H
000001001B
00002813H
NOTES:
1. This field exists only on processors that support either the 1-setting of the "load IA32_PAT" VM-entry control or that of the "save
IA32_PAT" VM-exit control.
2. This field exists only on processors that support either the 1-setting of the "load IA32_EFER" VM-entry control or that of the "save
IA32_EFER" VM-exit control.
3. This field exists only on processors that support the 1-setting of the "load IA32_PERF_GLOBAL_CTRL" VM-entry control.
4. This field exists only on processors that support the 1-setting of the "enable EPT" VM-execution control.
5. This field exists only on processors that support either the 1-setting of the “load IA32_BNDCFGS” VM-entry control or that of the
“clear IA32_BNDCFGS” VM-exit control.
B.2.4
64-Bit Host-State Fields
A value of 3 in bits 11:10 of an encoding indicates a field in the host-state area. These fields are distinguished by
their index value in bits 9:1. Table B-7 enumerates the 64-bit control fields.
Table B-7. Encodings for 64-Bit Host-State Fields (0010_11xx_xxxx_xxxAb)
Field Name
Host IA32_PAT
Index
(full)1
000000000B
1
Host IA32_PAT (high)
Host IA32_EFER
(full)2
Host IA32_EFER
(high)2
000000001B
Host IA32_PERF_GLOBAL_CTRL
(full)3
Host IA32_PERF_GLOBAL_CTRL
(high)3
000000010B
Encoding
00002C00H
00002C01H
00002C02H
00002C03H
00002C04H
00002C05H
NOTES:
1. This field exists only on processors that support the 1-setting of the "load IA32_PAT" VM-exit control.
2. This field exists only on processors that support the 1-setting of the "load IA32_EFER" VM-exit control.
Vol. 3D B-5
FIELD ENCODING IN VMCS
3. This field exists only on processors that support the 1-setting of the "load IA32_PERF_GLOBAL_CTRL" VM-exit control.
B.3
32-BIT FIELDS
A value of 2 in bits 14:13 of an encoding indicates a 32-bit field. As noted in Section 24.11.2, each 32-bit field
allows only full access, meaning that bit 0 of its encoding is 0. Each such encoding is thus an even number.
B.3.1
32-Bit Control Fields
A value of 0 in bits 11:10 of an encoding indicates a control field. These fields are distinguished by their index value
in bits 9:1. Table B-8 enumerates the 32-bit control fields.
Table B-8. Encodings for 32-Bit Control Fields (0100_00xx_xxxx_xxx0B)
Field Name
Index
Encoding
Pin-based VM-execution controls
000000000B
00004000H
Primary processor-based VM-execution controls
000000001B
00004002H
Exception bitmap
000000010B
00004004H
Page-fault error-code mask
000000011B
00004006H
Page-fault error-code match
000000100B
00004008H
CR3-target count
000000101B
0000400AH
VM-exit controls
000000110B
0000400CH
VM-exit MSR-store count
000000111B
0000400EH
VM-exit MSR-load count
000001000B
00004010H
VM-entry controls
000001001B
00004012H
VM-entry MSR-load count
000001010B
00004014H
VM-entry interruption-information field
000001011B
00004016H
VM-entry exception error code
000001100B
00004018H
VM-entry instruction length
000001101B
0000401AH
000001110B
0000401CH
TPR
threshold1
Secondary processor-based VM-execution
controls2
000001111b
0000401EH
PLE_Gap3
000010000b
00004020H
PLE_Window3
000010001b
00004022H
NOTES:
1. This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control.
2. This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control.
3. This field exists only on processors that support the 1-setting of the “PAUSE-loop exiting” VM-execution control.
B-6 Vol. 3D
FIELD ENCODING IN VMCS
B.3.2
32-Bit Read-Only Data Fields
A value of 1 in bits 11:10 of an encoding indicates a read-only data field. These fields are distinguished by their
index value in bits 9:1. Table B-9 enumerates the 32-bit read-only data fields.
Table B-9. Encodings for 32-Bit Read-Only Data Fields (0100_01xx_xxxx_xxx0B)
Field Name
Index
Encoding
VM-instruction error
000000000B
00004400H
Exit reason
000000001B
00004402H
VM-exit interruption information
000000010B
00004404H
VM-exit interruption error code
000000011B
00004406H
IDT-vectoring information field
000000100B
00004408H
IDT-vectoring error code
000000101B
0000440AH
VM-exit instruction length
000000110B
0000440CH
VM-exit instruction information
000000111B
0000440EH
B.3.3
32-Bit Guest-State Fields
A value of 2 in bits 11:10 of an encoding indicates a field in the guest-state area. These fields are distinguished by
their index value in bits 9:1. Table B-10 enumerates the 32-bit guest-state fields.
Table B-10. Encodings for 32-Bit Guest-State Fields
(0100_10xx_xxxx_xxx0B)
Field Name
Index
Encoding
Guest ES limit
000000000B
00004800H
Guest CS limit
000000001B
00004802H
Guest SS limit
000000010B
00004804H
Guest DS limit
000000011B
00004806H
Guest FS limit
000000100B
00004808H
Guest GS limit
000000101B
0000480AH
Guest LDTR limit
000000110B
0000480CH
Guest TR limit
000000111B
0000480EH
Guest GDTR limit
000001000B
00004810H
Guest IDTR limit
000001001B
00004812H
Guest ES access rights
000001010B
00004814H
Guest CS access rights
000001011B
00004816H
Guest SS access rights
000001100B
00004818H
Guest DS access rights
000001101B
0000481AH
Guest FS access rights
000001110B
0000481CH
Guest GS access rights
000001111B
0000481EH
Guest LDTR access rights
000010000B
00004820H
Guest TR access rights
000010001B
00004822H
Guest interruptibility state
000010010B
00004824H
Guest activity state
000010011B
00004826H
Vol. 3D B-7
FIELD ENCODING IN VMCS
Table B-10. Encodings for 32-Bit Guest-State Fields
(0100_10xx_xxxx_xxx0B) (Contd.)
Field Name
Index
Encoding
Guest SMBASE
000010100B
00004828H
000010101B
0000482AH
000010111B
0000482EH
Guest IA32_SYSENTER_CS
1
VMX-preemption timer value
NOTES:
1. This field exists only on processors that support the 1-setting of the "activate VMX-preemption timer" VM-execution control.
The limit fields for GDTR and IDTR are defined to be 32 bits in width even though these fields are only 16-bits wide
in the Intel 64 and IA-32 architectures. VM entry ensures that the high 16 bits of both these fields are cleared to 0.
B.3.4
32-Bit Host-State Field
A value of 3 in bits 11:10 of an encoding indicates a field in the host-state area. There is only one such 32-bit field
as given in Table B-11.
Table B-11. Encoding for 32-Bit Host-State Field (0100_11xx_xxxx_xxx0B)
Field Name
Index
Encoding
Host IA32_SYSENTER_CS
000000000B
00004C00H
B.4
NATURAL-WIDTH FIELDS
A value of 3 in bits 14:13 of an encoding indicates a natural-width field. As noted in Section 24.11.2, each of these
fields allows only full access, meaning that bit 0 of its encoding is 0. Each such encoding is thus an even number.
B.4.1
Natural-Width Control Fields
A value of 0 in bits 11:10 of an encoding indicates a control field. These fields are distinguished by their index value
in bits 9:1. Table B-12 enumerates the natural-width control fields.
Table B-12. Encodings for Natural-Width Control Fields (0110_00xx_xxxx_xxx0B)
Field Name
Index
Encoding
CR0 guest/host mask
000000000B
00006000H
CR4 guest/host mask
000000001B
00006002H
CR0 read shadow
000000010B
00006004H
CR4 read shadow
000000011B
00006006H
CR3-target value 0
000000100B
00006008H
CR3-target value 1
000000101B
0000600AH
CR3-target value 2
000000110B
0000600CH
000000111B
0000600EH
CR3-target value
31
NOTES:
1. If a future implementation supports more than 4 CR3-target values, they will be encoded consecutively following the 4 encodings
given here.
B-8 Vol. 3D
FIELD ENCODING IN VMCS
B.4.2
Natural-Width Read-Only Data Fields
A value of 1 in bits 11:10 of an encoding indicates a read-only data field. These fields are distinguished by their
index value in bits 9:1. Table B-13 enumerates the natural-width read-only data fields.
Table B-13. Encodings for Natural-Width Read-Only Data Fields (0110_01xx_xxxx_xxx0B)
Field Name
Index
Encoding
Exit qualification
000000000B
00006400H
I/O RCX
000000001B
00006402H
I/O RSI
000000010B
00006404H
I/O RDI
000000011B
00006406H
I/O RIP
000000100B
00006408H
Guest-linear address
000000101B
0000640AH
B.4.3
Natural-Width Guest-State Fields
A value of 2 in bits 11:10 of an encoding indicates a field in the guest-state area. These fields are distinguished by
their index value in bits 9:1. Table B-14 enumerates the natural-width guest-state fields.
Table B-14. Encodings for Natural-Width Guest-State Fields (0110_10xx_xxxx_xxx0B)
Field Name
Index
Encoding
Guest CR0
000000000B
00006800H
Guest CR3
000000001B
00006802H
Guest CR4
000000010B
00006804H
Guest ES base
000000011B
00006806H
Guest CS base
000000100B
00006808H
Guest SS base
000000101B
0000680AH
Guest DS base
000000110B
0000680CH
Guest FS base
000000111B
0000680EH
Guest GS base
000001000B
00006810H
Guest LDTR base
000001001B
00006812H
Guest TR base
000001010B
00006814H
Guest GDTR base
000001011B
00006816H
Guest IDTR base
000001100B
00006818H
Guest DR7
000001101B
0000681AH
Guest RSP
000001110B
0000681CH
Guest RIP
000001111B
0000681EH
Guest RFLAGS
000010000B
00006820H
Guest pending debug exceptions
000010001B
00006822H
Guest IA32_SYSENTER_ESP
000010010B
00006824H
Guest IA32_SYSENTER_EIP
000010011B
00006826H
The base-address fields for ES, CS, SS, and DS in the guest-state area are defined to be natural-width (with 64 bits
on processors supporting Intel 64 architecture) even though these fields are only 32-bits wide in the Intel 64 architecture. VM entry ensures that the high 32 bits of these fields are cleared to 0.
Vol. 3D B-9
FIELD ENCODING IN VMCS
B.4.4
Natural-Width Host-State Fields
A value of 3 in bits 11:10 of an encoding indicates a field in the host-state area. These fields are distinguished by
their index value in bits 9:1. Table B-15 enumerates the natural-width host-state fields.
Table B-15. Encodings for Natural-Width Host-State Fields (0110_11xx_xxxx_xxx0B)
Field Name
Index
Encoding
Host CR0
000000000B
00006C00H
Host CR3
000000001B
00006C02H
Host CR4
000000010B
00006C04H
Host FS base
000000011B
00006C06H
Host GS base
000000100B
00006C08H
Host TR base
000000101B
00006C0AH
Host GDTR base
000000110B
00006C0CH
Host IDTR base
000000111B
00006C0EH
Host IA32_SYSENTER_ESP
000001000B
00006C10H
Host IA32_SYSENTER_EIP
000001001B
00006C12H
Host RSP
000001010B
00006C14H
Host RIP
000001011B
00006C16H
B-10 Vol. 3D
APPENDIX C
VMX BASIC EXIT REASONS
Every VM exit writes a 32-bit exit reason to the VMCS (see Section 24.9.1). Certain VM-entry failures also do this
(see Section 26.7). The low 16 bits of the exit-reason field form the basic exit reason which provides basic information about the cause of the VM exit or VM-entry failure.
Table C-1 lists values for basic exit reasons and explains their meaning. Entries apply to VM exits, unless otherwise
noted.
Table C-1. Basic Exit Reasons
Basic Exit
Reason
Description
0
Exception or non-maskable interrupt (NMI). Either:
1: Guest software caused an exception and the bit in the exception bitmap associated with exception’s vector was 1.
2: An NMI was delivered to the logical processor and the “NMI exiting” VM-execution control was 1. This case includes
executions of BOUND that cause #BR, executions of INT3 (they cause #BP), executions of INTO that cause #OF,
and executions of UD2 (they cause #UD).
1
External interrupt. An external interrupt arrived and the “external-interrupt exiting” VM-execution control was 1.
2
Triple fault. The logical processor encountered an exception while attempting to call the double-fault handler and
that exception did not itself cause a VM exit due to the exception bitmap.
3
INIT signal. An INIT signal arrived
4
Start-up IPI (SIPI). A SIPI arrived while the logical processor was in the “wait-for-SIPI” state.
5
I/O system-management interrupt (SMI). An SMI arrived immediately after retirement of an I/O instruction and
caused an SMM VM exit (see Section 34.15.2).
6
Other SMI. An SMI arrived and caused an SMM VM exit (see Section 34.15.2) but not immediately after retirement of
an I/O instruction.
7
Interrupt window. At the beginning of an instruction, RFLAGS.IF was 1; events were not blocked by STI or by MOV
SS; and the “interrupt-window exiting” VM-execution control was 1.
8
NMI window. At the beginning of an instruction, there was no virtual-NMI blocking; events were not blocked by MOV
SS; and the “NMI-window exiting” VM-execution control was 1.
9
Task switch. Guest software attempted a task switch.
10
CPUID. Guest software attempted to execute CPUID.
11
GETSEC. Guest software attempted to execute GETSEC.
12
HLT. Guest software attempted to execute HLT and the “HLT exiting” VM-execution control was 1.
13
INVD. Guest software attempted to execute INVD.
14
INVLPG. Guest software attempted to execute INVLPG and the “INVLPG exiting” VM-execution control was 1.
15
RDPMC. Guest software attempted to execute RDPMC and the “RDPMC exiting” VM-execution control was 1.
16
RDTSC. Guest software attempted to execute RDTSC and the “RDTSC exiting” VM-execution control was 1.
17
RSM. Guest software attempted to execute RSM in SMM.
18
VMCALL. VMCALL was executed either by guest software (causing an ordinary VM exit) or by the executive monitor
(causing an SMM VM exit; see Section 34.15.2).
19
VMCLEAR. Guest software attempted to execute VMCLEAR.
20
VMLAUNCH. Guest software attempted to execute VMLAUNCH.
21
VMPTRLD. Guest software attempted to execute VMPTRLD.
22
VMPTRST. Guest software attempted to execute VMPTRST.
23
VMREAD. Guest software attempted to execute VMREAD.
Vol. 3D C-1
VMX BASIC EXIT REASONS
Table C-1. Basic Exit Reasons (Contd.)
Basic Exit
Reason
Description
24
VMRESUME. Guest software attempted to execute VMRESUME.
25
VMWRITE. Guest software attempted to execute VMWRITE.
26
VMXOFF. Guest software attempted to execute VMXOFF.
27
VMXON. Guest software attempted to execute VMXON.
28
Control-register accesses. Guest software attempted to access CR0, CR3, CR4, or CR8 using CLTS, LMSW, or
MOV CR and the VM-execution control fields indicate that a VM exit should occur (see Section 25.1 for details). This
basic exit reason is not used for trap-like VM exits following executions of the MOV to CR8 instruction when the “use
TPR shadow” VM-execution control is 1.
29
MOV DR. Guest software attempted a MOV to or from a debug register and the “MOV-DR exiting” VM-execution
control was 1.
30
I/O instruction. Guest software attempted to execute an I/O instruction and either:
1: The “use I/O bitmaps” VM-execution control was 0 and the “unconditional I/O exiting” VM-execution control was 1.
2: The “use I/O bitmaps” VM-execution control was 1 and a bit in the I/O bitmap associated with one of the ports
accessed by the I/O instruction was 1.
31
RDMSR. Guest software attempted to execute RDMSR and either:
1: The “use MSR bitmaps” VM-execution control was 0.
2: The value of RCX is neither in the range 00000000H – 00001FFFH nor in the range C0000000H – C0001FFFH.
3: The value of RCX was in the range 00000000H – 00001FFFH and the nth bit in read bitmap for low MSRs is 1,
where n was the value of RCX.
4: The value of RCX is in the range C0000000H – C0001FFFH and the nth bit in read bitmap for high MSRs is 1, where
n is the value of RCX & 00001FFFH.
32
WRMSR. Guest software attempted to execute WRMSR and either:
1: The “use MSR bitmaps” VM-execution control was 0.
2: The value of RCX is neither in the range 00000000H – 00001FFFH nor in the range C0000000H – C0001FFFH.
3: The value of RCX was in the range 00000000H – 00001FFFH and the nth bit in write bitmap for low MSRs is 1,
where n was the value of RCX.
4: The value of RCX is in the range C0000000H – C0001FFFH and the nth bit in write bitmap for high MSRs is 1,
where n is the value of RCX & 00001FFFH.
33
VM-entry failure due to invalid guest state. A VM entry failed one of the checks identified in Section 26.3.1.
34
VM-entry failure due to MSR loading. A VM entry failed in an attempt to load MSRs. See Section 26.4.
36
MWAIT. Guest software attempted to execute MWAIT and the “MWAIT exiting” VM-execution control was 1.
37
Monitor trap flag. A VM entry occurred due to the 1-setting of the “monitor trap flag” VM-execution control and
injection of an MTF VM exit as part of VM entry. See Section 25.5.2.
39
MONITOR. Guest software attempted to execute MONITOR and the “MONITOR exiting” VM-execution control was 1.
40
PAUSE. Either guest software attempted to execute PAUSE and the “PAUSE exiting” VM-execution control was 1 or
the “PAUSE-loop exiting” VM-execution control was 1 and guest software executed a PAUSE loop with execution
time exceeding PLE_Window (see Section 25.1.3).
41
VM-entry failure due to machine-check event. A machine-check event occurred during VM entry (see Section
26.8).
43
TPR below threshold. The logical processor determined that the value of bits 7:4 of the byte at offset 080H on the
virtual-APIC page was below that of the TPR threshold VM-execution control field while the “use TPR shadow” VMexecution control was 1 either as part of TPR virtualization (Section 29.1.2) or VM entry (Section 26.6.7).
44
APIC access. Guest software attempted to access memory at a physical address on the APIC-access page and the
“virtualize APIC accesses” VM-execution control was 1 (see Section 29.4).
45
Virtualized EOI. EOI virtualization was performed for a virtual interrupt whose vector indexed a bit set in the EOIexit bitmap.
C-2 Vol. 3D
VMX BASIC EXIT REASONS
Table C-1. Basic Exit Reasons (Contd.)
Basic Exit
Reason
Description
46
Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT and the “descriptor-table
exiting” VM-execution control was 1.
47
Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR and the “descriptor-table
exiting” VM-execution control was 1.
48
EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of
the EPT paging structures.
49
EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured
EPT paging-structure entry.
50
INVEPT. Guest software attempted to execute INVEPT.
51
RDTSCP. Guest software attempted to execute RDTSCP and the “enable RDTSCP” and “RDTSC exiting” VM-execution
controls were both 1.
52
VMX-preemption timer expired. The preemption timer counted down to zero.
53
INVVPID. Guest software attempted to execute INVVPID.
54
WBINVD. Guest software attempted to execute WBINVD and the “WBINVD exiting” VM-execution control was 1.
55
XSETBV. Guest software attempted to execute XSETBV.
56
APIC write. Guest software completed a write to the virtual-APIC page that must be virtualized by VMM software
(see Section 29.4.3.3).
57
RDRAND. Guest software attempted to execute RDRAND and the “RDRAND exiting” VM-execution control was 1.
58
INVPCID. Guest software attempted to execute INVPCID and the “enable INVPCID” and “INVLPG exiting”
VM-execution controls were both 1.
59
VMFUNC. Guest software invoked a VM function with the VMFUNC instruction and the VM function either was not
enabled or generated a function-specific condition causing a VM exit.
60
ENCLS. Guest software attempted to execute ENCLS and “enable ENCLS exiting” VM-execution control was 1 and
either (1) EAX < 63 and the corresponding bit in the ENCLS-exiting bitmap is 1; or (2) EAX ≥ 63 and bit 63 in the
ENCLS-exiting bitmap is 1.
61
RDSEED. Guest software attempted to execute RDSEED and the “RDSEED exiting” VM-execution control was 1.
62
Page-modification log full. The processor attempted to create a page-modification log entry and the value of the
PML index was not in the range 0–511.
63
XSAVES. Guest software attempted to execute XSAVES, the “enable XSAVES/XRSTORS” was 1, and a bit was set in
the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the XSS-exiting bitmap.
64
XRSTORS. Guest software attempted to execute XRSTORS, the “enable XSAVES/XRSTORS” was 1, and a bit was set
in the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the XSS-exiting bitmap.
Vol. 3D C-3
VMX BASIC EXIT REASONS
C-4 Vol. 3D
INDEX
Numerics
0000, Vol.1-B-41
128-bit
packed byte integers data type, Vol.1-4-9, Vol.1-11-4
packed double-precision floating-point
data type, Vol.1-4-9, Vol.1-11-4
packed doubleword integers data type, Vol.1-4-9
packed quadword integers data type, Vol.1-4-9
packed SIMD data types, Vol.1-4-8
packed single-precision floating-point
data type, Vol.1-4-9, Vol.1-10-5
packed word integers data type, Vol.1-4-9, Vol.1-11-4
16-bit
address size, Vol.1-3-9
operand size, Vol.1-3-9
16-bit code, mixing with 32-bit code, Vol.3-21-1
286 processor, Vol.1-2-1
32-bit
address size, Vol.1-3-9
operand size, Vol.1-3-9
32-bit code, mixing with 16-bit code, Vol.3-21-1
32-bit physical addressing
overview, Vol.3-3-6
36-bit physical addressing
overview, Vol.3-3-6
64-bit
packed byte integers data type, Vol.1-4-8, Vol.1-9-3
packed doubleword integers data type, Vol.1-4-8
packed doubleword integers data types, Vol.1-9-3
packed word integers data type, Vol.1-4-8, Vol.1-9-3
64-bit mode
sub-mode of IA-32e, Vol.1-3-1
address calculation, Vol.1-3-10
address size, Vol.1-3-19
address space, Vol.1-3-5
BOUND instruction, Vol.1-7-18
branch behavior, Vol.1-6-9
byte register limitation, Vol.1-3-13
call gates, Vol.3-5-14
CALL instruction, Vol.1-6-9, Vol.1-7-17
canonical address, Vol.1-3-10
CMPS instruction, Vol.1-7-20
CMPXCHG16B instruction, Vol.1-7-5
code segment descriptors, Vol.3-5-3, Vol.3-9-12
control and debug registers, Vol.2-2-12
control registers, Vol.3-2-13
CR8 register, Vol.3-2-13
D flag, Vol.3-5-4
data types, Vol.1-7-2
debug registers, Vol.3-2-7
DEC instruction, Vol.1-7-8
decimal arithmetic instructions, Vol.1-7-10
default operand and address sizes, Vol.1-3-2
default operand size, Vol.2-2-12
descriptors, Vol.3-5-3, Vol.3-5-5
direct memory-offset MOVs, Vol.2-2-11
DPL field, Vol.3-5-4
exception handling, Vol.3-6-16
exceptions, Vol.1-6-14
external interrupts, Vol.3-10-31
far pointer, Vol.1-4-7
fast system calls, Vol.3-5-22
feature list, Vol.1-2-21
GDTR register, Vol.1-3-6, Vol.3-2-12, Vol.3-2-13
general purpose encodings, Vol.1-B-18
GP faults, causes of, Vol.3-6-38
IDTR register, Vol.1-3-6, Vol.3-2-12
immediates, Vol.2-2-11
INC instruction, Vol.1-7-8
initialization process, Vol.3-2-8, Vol.3-9-11
instruction pointer, Vol.1-3-10, Vol.1-3-18
instructions introduced, Vol.1-5-33
interrupt and trap gates, Vol.3-6-16
interrupt controller, Vol.3-10-31
interrupt descriptors, Vol.3-2-5
interrupt handling, Vol.3-6-16
interrupt stack table, Vol.3-6-19
interrupts, Vol.1-6-14
introduction, Vol.1-2-21, Vol.1-3-1, Vol.1-7-1, Vol.2-2-7
IRET instruction, Vol.1-7-18, Vol.3-6-18
I/O instructions, Vol.1-7-20
JCC instruction, Vol.1-6-9, Vol.1-7-17
JCXZ instruction, Vol.1-6-9, Vol.1-7-17
JMP instruction, Vol.1-6-9, Vol.1-7-17
L flag, Vol.3-3-12, Vol.3-5-4
LAHF instruction, Vol.1-7-22
LDTR register, Vol.1-3-6
legacy modes, Vol.1-2-21
LODS instruction, Vol.1-7-20
logical address translation, Vol.3-3-7
LOOP instruction, Vol.1-6-9, Vol.1-7-17
machine instructions, Vol.1-B-1
memory models, Vol.1-3-9
memory operands, Vol.1-3-21
MMX technology, Vol.1-9-2
MOV CRn, Vol.3-2-13, Vol.3-10-31
MOVS instruction, Vol.1-7-20
MOVSXD instruction, Vol.1-7-8
near pointer, Vol.1-4-7
null segment checking, Vol.3-5-6
operand addressing, Vol.1-3-24
operand size, Vol.1-3-19
operands, Vol.1-3-21
paging, Vol.3-2-6
POPF instruction, Vol.1-7-22
promoted instructions, Vol.1-3-2
PUSHA, PUSHAD, POPA, POPAD, Vol.1-7-7
PUSHF instruction, Vol.1-7-22
PUSHFD instruction, Vol.1-7-22
reading counters, Vol.3-2-25
reading & writing MSRs, Vol.3-2-25
real address mode, Vol.1-3-9
reg (reg) field, Vol.1-B-4
register operands, Vol.1-3-21
registers and mode changes, Vol.3-9-12
REP prefix, Vol.1-7-20
RET instruction, Vol.1-6-9, Vol.1-7-17
REX prefix, Vol.1-3-2, Vol.1-3-12, Vol.1-3-19
REX prefixes, Vol.2-2-8, Vol.1-B-2
RFLAGS register, Vol.1-7-22, Vol.3-2-11
RIP register, Vol.1-3-10
RIP-relative addressing, Vol.1-3-18, Vol.1-3-24, Vol.2-2-12
SAHF instruction, Vol.1-7-22
SCAS instruction, Vol.1-7-20
segment descriptor tables, Vol.3-3-16, Vol.3-5-3
segment loading instructions, Vol.3-3-9
segment registers, Vol.1-3-15
segmentation, Vol.1-3-9, Vol.1-3-22
segments, Vol.3-3-5
SIMD encodings, Vol.1-B-37
special instruction encodings, Vol.1-B-64
SSE extensions, Vol.1-10-3
SSE2 extensions, Vol.1-11-3
SSE3 extensions, Vol.1-12-1
SSSE3 extensions, Vol.1-12-1
stack behavior, Vol.1-6-4
stack switching, Vol.3-5-19, Vol.3-6-18
STOS instruction, Vol.1-7-20
summary table notation, Vol.2-3-8
SYSCALL and SYSRET, Vol.3-2-7, Vol.3-5-22
SYSENTER and SYSEXIT, Vol.3-5-21
system registers, Vol.3-2-7
task gate, Vol.3-7-16
task priority, Vol.3-2-18, Vol.3-10-31
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -1
INDEX
task register, Vol.3-2-13
TR register, Vol.1-3-6
TSS
stack pointers, Vol.3-7-17
x87 FPU, Vol.1-8-1
See also: IA-32e mode, compatibility mode
8086
emulation, support for, Vol.3-20-1
processor, exceptions and interrupts, Vol.3-20-6
8086 processor, Vol.1-2-1
8086/8088 processor, Vol.3-22-6
8087 math coprocessor, Vol.3-22-7
8088 processor, Vol.1-2-1
82489DX, Vol.3-22-26, Vol.3-22-27
Local APIC and I/O APICs, Vol.3-10-4
A
A20M# signal, Vol.3-20-2, Vol.3-22-33, Vol.3-23-4
AAA instruction, Vol.1-7-9, Vol.2-3-18, Vol.2-3-20
AAD instruction, Vol.1-7-10, Vol.2-3-20
AAM instruction, Vol.1-7-10, Vol.2-3-22
AAS instruction, Vol.1-7-10, Vol.2-3-24
Aborts
description of, Vol.3-6-5
restarting a program or task after, Vol.3-6-5
AC (alignment check) flag, EFLAGS register, Vol.1-3-17, Vol.3-2-11,
Vol.3-6-45, Vol.3-22-6
Access rights
checking, Vol.3-2-22
checking caller privileges, Vol.3-5-26
description of, Vol.3-5-24
invalid values, Vol.3-22-18
Access rights, segment descriptor, Vol.1-6-7, Vol.1-6-10
ADC instruction, Vol.1-7-8, Vol.2-3-26, Vol.2-3-537, Vol.3-8-3
ADD instruction, Vol.1-7-8, Vol.2-3-18, Vol.2-3-31, Vol.2-3-279,
Vol.2-3-537, Vol.3-8-3
ADDPD instruction, Vol.1-11-6, Vol.2-3-33
ADDPS- Add Packed Single-Precision Floating-Point Values, Vol.2-3-36
ADDPS instruction, Vol.1-10-8
Address
size prefix, Vol.3-21-1
space, of task, Vol.3-7-14
Address size attribute
code segment, Vol.1-3-18
description of, Vol.1-3-18
of stack, Vol.1-6-3
Address sizes, Vol.1-3-9
Address space
64-bit mode, Vol.1-3-1, Vol.1-3-5
compatibility mode, Vol.1-3-1
overview of, Vol.1-3-2
physical, Vol.1-3-6
Address translation
in real-address mode, Vol.3-20-2
logical to linear, Vol.3-3-7
overview, Vol.3-3-6
Addressing methods
RIP-relative, Vol.2-2-12
Addressing modes
assembler, Vol.1-3-24
base, Vol.1-3-22, Vol.1-3-23, Vol.1-3-24
base plus displacement, Vol.1-3-23
base plus index plus displacement, Vol.1-3-23
base plus index time scale plus displacement, Vol.1-3-23, Vol.1-3-24
canonical address, Vol.1-3-10
displacement, Vol.1-3-22, Vol.1-3-23, Vol.1-3-24
effective address, Vol.1-3-23
immediate operands, Vol.1-3-20
index, Vol.1-3-22, Vol.1-3-24
index times scale plus displacement, Vol.1-3-23
memory operands, Vol.1-3-21
Index-2 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
register operands, Vol.1-3-20, Vol.1-3-21
RIP-relative addressing, Vol.1-3-18, Vol.1-3-24
scale factor, Vol.1-3-22, Vol.1-3-24
specifying a segment selector, Vol.1-3-21
specifying an offset, Vol.1-3-22
specifying offsets in 64-bit mode, Vol.1-3-24
Addressing, segments, Vol.2-1-6, Vol.3-1-7
ADDSD- Add Scalar Double-Precision Floating-Point Values, Vol.2-3-39
ADDSD instruction, Vol.1-11-6, Vol.2-3-39
ADDSS- Add Scalar Single-Precision Floating-Point Values, Vol.2-3-41
ADDSS instruction, Vol.1-10-8
ADDSUBPD instruction, Vol.1-5-21, Vol.1-12-4, Vol.2-3-43
ADDSUBPS instruction, Vol.1-5-21, Vol.1-12-4, Vol.2-3-45
Advanced media boost, Vol.1-2-11
Advanced power management
C-state and Sub C-state, Vol.3-14-18
MWAIT extensions, Vol.3-14-18
See also: thermal monitoring
Advanced programmable interrupt controller (see I/O APIC or Local APIC)
advanced smart cache, Vol.1-2-11
AESDEC/AESDECLAST- Perform One Round of an AES Decryption Flow,
Vol.2-3-56
AESIMC- Perform the AES InvMixColumn Transformation, Vol.2-3-52
AESKEYGENASSIST - AES Round Key Generation Assist, Vol.2-3-59
AF (adjust) flag, EFLAGS register, Vol.1-3-16, Vol.1-A-1
AH register, Vol.1-3-12
AL register, Vol.1-3-12
Alignment
check exception, Vol.3-2-11, Vol.3-6-45, Vol.3-22-11, Vol.3-22-20
checking, Vol.3-5-27
words, doublewords, quadwords, Vol.1-4-2
AM (alignment mask) flag
CR0 control register, Vol.3-2-14, Vol.3-22-17
AND instruction, Vol.1-7-10, Vol.2-3-61, Vol.2-3-537, Vol.3-8-3
ANDNPD instruction, Vol.1-11-7
ANDNPS- Bitwise Logical AND NOT of Packed Single Precision
Floating-Point Values, Vol.2-3-73
ANDNPS instruction, Vol.1-10-9
ANDPD- Bitwise Logical AND of Packed Double Precision Floating-Point
Values, Vol.2-3-64
ANDPD instruction, Vol.1-11-7, Vol.2-3-63
ANDPS- Bitwise Logical AND of Packed Single Precision Floating-Point
Values, Vol.2-3-67
ANDPS instruction, Vol.1-10-9
APIC, Vol.3-10-39, Vol.3-10-40, Vol.3-10-41
APIC bus
arbitration mechanism and protocol, Vol.3-10-25, Vol.3-10-32
bus message format, Vol.3-10-33, Vol.3-10-47
diagram of, Vol.3-10-2, Vol.3-10-3
EOI message format, Vol.3-10-14, Vol.3-10-47
nonfocused lowest priority message, Vol.3-10-49
short message format, Vol.3-10-48
SMI message, Vol.3-34-2
status cycles, Vol.3-10-50
structure of, Vol.3-10-4
See also
local APIC
APIC flag, CPUID instruction, Vol.3-10-7
APIC ID, Vol.3-10-40, Vol.3-10-44, Vol.3-10-46
APIC (see I/O APIC or Local APIC)
Arctangent, x87 FPU operation, Vol.1-8-21, Vol.2-3-365
Arithmetic instructions, x87 FPU, Vol.1-8-25
ARPL instruction, Vol.2-3-76, Vol.3-2-22, Vol.3-5-27
not supported in 64-bit mode, Vol.3-2-22
Assembler, addressing modes, Vol.1-3-24
Asymmetric processing model, Vol.1-12-1
Atomic operations
automatic bus locking, Vol.3-8-3
effects of a locked operation on internal processor caches, Vol.3-8-5
guaranteed, description of, Vol.3-8-2
overview of, Vol.3-8-1, Vol.3-8-3
software-controlled bus locking, Vol.3-8-3
INDEX
At-retirement
counting, Vol.3-18-21, Vol.3-18-96
events, Vol.3-18-21, Vol.3-18-85, Vol.3-18-86, Vol.3-18-96,
Vol.3-18-101
authenticated code execution mode, Vol.1-6-3
Auto HALT restart
field, SMM, Vol.3-34-14
SMM, Vol.3-34-13
Automatic bus locking, Vol.3-8-3
Automatic thermal monitoring mechanism, Vol.3-14-19
AX register, Vol.1-3-12
B
B (busy) flag
TSS descriptor, Vol.3-7-5, Vol.3-7-10, Vol.3-7-13, Vol.3-8-3
B (default size) flag, segment descriptor, Vol.1-3-18
B (default stack size) flag
segment descriptor, Vol.3-21-1, Vol.3-22-32
B0-B3 (BP condition detected) flags
DR6 register, Vol.3-17-3
Backlink (see Previous task link)
Base address fields, segment descriptor, Vol.3-3-10
Base (operand addressing), Vol.1-3-22, Vol.1-3-23, Vol.1-3-24, Vol.2-2-3
Basic execution environment, Vol.1-3-2
Basic programming environment, Vol.1-7-1
B-bit, x87 FPU status word, Vol.1-8-5
BCD integers
packed, Vol.1-4-10, Vol.2-3-279, Vol.2-3-281, Vol.2-3-315,
Vol.2-3-317
relationship to status flags, Vol.1-3-17
unpacked, Vol.1-4-9, Vol.1-7-9, Vol.2-3-18, Vol.2-3-20, Vol.2-3-22,
Vol.2-3-24
x87 FPU encoding, Vol.1-4-10
BD (debug register access detected) flag, DR6 register, Vol.3-17-3,
Vol.3-17-9
BEXTR - Bit Field Extract, Vol.2-3-80
BH register, Vol.1-3-12
Bias value
numeric overflow, Vol.1-8-30
numeric underflow, Vol.1-8-30
Biased exponent, Vol.1-4-13
Biasing constant, for floating-point numbers, Vol.1-4-6
Binary numbers, Vol.1-1-6, Vol.2-1-5, Vol.3-1-7
Binary-coded decimal (see BCD)
BINIT# signal, Vol.3-2-24
BIOS role in microcode updates, Vol.3-9-38
Bit field, Vol.1-4-7
Bit order, Vol.1-1-5, Vol.2-1-4, Vol.3-1-6
BL register, Vol.1-3-12
BLSMSK - Get Mask Up to Lowest Set Bit, Vol.2-3-89
bootstrap processor, Vol.1-6-16, Vol.1-6-21, Vol.1-6-29, Vol.1-6-30
BOUND instruction, Vol.1-6-13, Vol.1-7-18, Vol.1-7-23, Vol.2-3-106,
Vol.3-2-5, Vol.3-6-4, Vol.3-6-25
BOUND range exceeded exception (#BR), Vol.1-6-13, Vol.2-3-106,
Vol.3-6-25
BP register, Vol.1-3-12
BP0#, BP1#, BP2#, and BP3# pins, Vol.3-17-37, Vol.3-17-39
Branch
control transfer instructions, Vol.1-7-14
hints, Vol.1-11-13
on EFLAGS register status flags, Vol.1-7-15, Vol.1-8-6
on x87 FPU condition codes, Vol.1-8-6, Vol.1-8-20
prediction, Vol.1-2-8
Branch hints, Vol.2-2-2
Branch record
branch trace message, Vol.3-17-13
IA-32e mode, Vol.3-17-21
saving, Vol.3-17-15, Vol.3-17-25, Vol.3-17-26, Vol.3-17-34
saving as a branch trace message, Vol.3-17-13
structure, Vol.3-17-34
structure of in BTS buffer, Vol.3-17-19
Branch trace message (see BTM)
Branch trace store (see BTS)
Brand information, Vol.2-3-216
processor brand index, Vol.2-3-219
processor brand string, Vol.2-3-216
Breakpoint exception (#BP), Vol.3-6-4, Vol.3-6-23, Vol.3-17-10
Breakpoints
data breakpoint, Vol.3-17-5
data breakpoint exception conditions, Vol.3-17-9
description of, Vol.3-17-1
DR0-DR3 debug registers, Vol.3-17-3
example, Vol.3-17-5
exception, Vol.3-6-23
field recognition, Vol.3-17-5, Vol.3-17-6
general-detect exception condition, Vol.3-17-9
instruction breakpoint, Vol.3-17-5
instruction breakpoint exception condition, Vol.3-17-8
I/O breakpoint exception conditions, Vol.3-17-9
LEN0 - LEN3 (Length) fields
DR7 register, Vol.3-17-5
R/W0-R/W3 (read/write) fields
DR7 register, Vol.3-17-4
single-step exception condition, Vol.3-17-9
task-switch exception condition, Vol.3-17-10
BS (single step) flag, DR6 register, Vol.3-17-3
BSF instruction, Vol.1-7-14, Vol.2-3-108
BSP flag, IA32_APIC_BASE MSR, Vol.3-10-8
BSR instruction, Vol.1-7-14, Vol.2-3-110
BSWAP instruction, Vol.1-7-4, Vol.2-3-112, Vol.3-22-4
BT instruction, Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-113
BT (task switch) flag, DR6 register, Vol.3-17-3, Vol.3-17-10
BTC instruction, Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-115,
Vol.2-3-537, Vol.3-8-3
BTF (single-step on branches) flag
DEBUGCTLMSR MSR, Vol.3-17-39
BTMs (branch trace messages)
description of, Vol.3-17-13
enabling, Vol.3-17-11, Vol.3-17-23, Vol.3-17-24, Vol.3-17-33,
Vol.3-17-36, Vol.3-17-37
TR (trace message enable) flag
MSR_DEBUGCTLA MSR, Vol.3-17-33
MSR_DEBUGCTLB MSR, Vol.3-17-11, Vol.3-17-36, Vol.3-17-37
BTR instruction, Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-117,
Vol.2-3-537, Vol.3-8-3
BTS buffer
description of, Vol.3-17-18
introduction to, Vol.3-17-11, Vol.3-17-13
records in, Vol.3-17-19
setting up, Vol.3-17-23
structure of, Vol.3-17-19, Vol.3-17-21, Vol.3-18-39
BTS instruction, Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-119,
Vol.2-3-537, Vol.3-8-3
BTS (branch trace store) facilities
availability of, Vol.3-17-32
BTS_UNAVAILABLE flag,
IA32_MISC_ENABLE MSR, Vol.3-17-18, Vol.1-35-286
introduction to, Vol.3-17-11
setting up BTS buffer, Vol.3-17-23
writing an interrupt service routine for, Vol.3-17-24
BTS_UNAVAILABLE, Vol.3-17-18
Built-in self-test (BIST)
description of, Vol.3-9-1
performing, Vol.3-9-5
Bus
errors detected with MCA, Vol.3-15-26
hold, Vol.3-22-34
locking, Vol.3-8-3, Vol.3-22-34
BX register, Vol.1-3-12
Byte, Vol.1-4-1
Byte order, Vol.1-1-5, Vol.2-1-4, Vol.3-1-6
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -3
INDEX
C
C (conforming) flag, segment descriptor, Vol.3-5-11
C1 flag, x87 FPU status word, Vol.1-8-4, Vol.1-8-27, Vol.1-8-30,
Vol.1-8-31, Vol.3-22-7, Vol.3-22-14
C2 flag, x87 FPU status word, Vol.1-8-5, Vol.3-22-7
Cache and TLB information, Vol.2-3-210
Cache control, Vol.3-11-20
adaptive mode, L1 Data Cache, Vol.3-11-18
cache management instructions, Vol.3-11-17, Vol.3-11-18
cache mechanisms in IA-32 processors, Vol.3-22-29
caching terminology, Vol.3-11-5
CD flag, CR0 control register, Vol.3-11-10, Vol.3-22-18
choosing a memory type, Vol.3-11-8
CPUID feature flag, Vol.3-11-18
flags and fields, Vol.3-11-10
flushing TLBs, Vol.3-11-19
G (global) flag
page-directory entries, Vol.3-11-13
page-table entries, Vol.3-11-13
internal caches, Vol.3-11-1
MemTypeGet() function, Vol.3-11-29
MemTypeSet() function, Vol.3-11-31
MESI protocol, Vol.3-11-5, Vol.3-11-9
methods of caching available, Vol.3-11-6
MTRR initialization, Vol.3-11-29
MTRR precedences, Vol.3-11-28
MTRRs, description of, Vol.3-11-20
multiple-processor considerations, Vol.3-11-32
NW flag, CR0 control register, Vol.3-11-13, Vol.3-22-18
operating modes, Vol.3-11-12
overview of, Vol.3-11-1
page attribute table (PAT), Vol.3-11-33
PCD flag
CR3 control register, Vol.3-11-13
page-directory entries, Vol.3-11-13, Vol.3-11-33
page-table entries, Vol.3-11-13, Vol.3-11-33
PGE (page global enable) flag, CR4 control register, Vol.3-11-13
precedence of controls, Vol.3-11-13
preventing caching, Vol.3-11-16
protocol, Vol.3-11-9
PWT flag
CR3 control register, Vol.3-11-13
page-directory entries, Vol.3-11-33
page-table entries, Vol.3-11-33
remapping memory types, Vol.3-11-29
setting up memory ranges with MTRRs, Vol.3-11-22
shared mode, L1 Data Cache, Vol.3-11-18
variable-range MTRRs, Vol.3-11-23, Vol.3-11-25
Cache Inclusiveness, Vol.2-3-192
Caches, Vol.3-2-7
cache hit, Vol.3-11-5
cache line, Vol.3-11-5
cache line fill, Vol.3-11-5
cache write hit, Vol.3-11-5
description of, Vol.3-11-1
effects of a locked operation on internal processor caches, Vol.3-8-5
enabling, Vol.3-9-7
management, instructions, Vol.3-2-23, Vol.3-11-17
Caches, invalidating (flushing), Vol.2-3-469, Vol.2-5-568
cache, smart, Vol.1-2-4
Caching
cache control protocol, Vol.3-11-9
cache line, Vol.3-11-5
cache management instructions, Vol.3-11-17
cache mechanisms in IA-32 processors, Vol.3-22-29
caching terminology, Vol.3-11-5
choosing a memory type, Vol.3-11-8
flushing TLBs, Vol.3-11-19
implicit caching, Vol.3-11-19
internal caches, Vol.3-11-1
L1 (level 1) cache, Vol.3-11-4
L2 (level 2) cache, Vol.3-11-4
Index-4 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
L3 (level 3) cache, Vol.3-11-4
methods of caching available, Vol.3-11-6
MTRRs, description of, Vol.3-11-20
operating modes, Vol.3-11-12
overview of, Vol.3-11-1
self-modifying code, effect on, Vol.3-11-18, Vol.3-22-29
snooping, Vol.3-11-6
store buffer, Vol.3-11-20
TLBs, Vol.3-11-5
UC (strong uncacheable) memory type, Vol.3-11-6
UC- (uncacheable) memory type, Vol.3-11-6
WB (write back) memory type, Vol.3-11-7
WC (write combining) memory type, Vol.3-11-7
WP (write protected) memory type, Vol.3-11-7
write-back caching, Vol.3-11-6
WT (write through) memory type, Vol.3-11-7
Call gate, Vol.1-6-7
Call gates
16-bit, interlevel return from, Vol.3-22-32
accessing a code segment through, Vol.3-5-15
description of, Vol.3-5-13
for 16-bit and 32-bit code modules, Vol.3-21-1
IA-32e mode, Vol.3-5-14
introduction to, Vol.3-2-4
mechanism, Vol.3-5-15
privilege level checking rules, Vol.3-5-16
CALL instruction, Vol.1-3-18, Vol.1-6-3, Vol.1-6-4, Vol.1-6-7, Vol.1-7-15,
Vol.1-7-22, Vol.2-3-122, Vol.3-2-5, Vol.3-3-9, Vol.3-5-10,
Vol.3-5-15, Vol.3-5-20, Vol.3-7-2, Vol.3-7-9, Vol.3-7-10,
Vol.3-21-5
Caller access privileges, checking, Vol.3-5-26
Calls
16 and 32-bit code segments, Vol.3-21-3
controlling operand-size attribute, Vol.3-21-5
returning from, Vol.3-5-20
Calls (see Procedure calls)
Canonical address, Vol.1-3-10
GETSEC, Vol.1-6-2
Capability MSRs
See VMX capability MSRs
Catastrophic shutdown detector
Thermal monitoring
catastrophic shutdown detector, Vol.3-14-20
catastrophic shutdown detector, Vol.3-14-19
CBW instruction, Vol.1-7-7, Vol.2-3-135
CC0 and CC1 (counter control) fields, CESR MSR (Pentium processor),
Vol.3-18-121
CD (cache disable) flag, CR0 control register, Vol.3-2-14, Vol.3-9-7,
Vol.3-11-10, Vol.3-11-12, Vol.3-11-13, Vol.3-11-16,
Vol.3-11-32, Vol.3-22-17, Vol.3-22-18, Vol.3-22-29
CDQ instruction, Vol.1-7-7, Vol.2-3-278
CDQE instruction, Vol.2-3-135
Celeron processor
description of, Vol.1-2-3
CESR (control and event select) MSR (Pentium processor), Vol.3-18-120,
Vol.3-18-121
CF (carry) flag, EFLAGS register, Vol.1-3-16, Vol.1-A-1, Vol.2-3-31,
Vol.2-3-113, Vol.2-3-115, Vol.2-3-117, Vol.2-3-119,
Vol.2-3-137, Vol.2-3-148, Vol.2-3-283, Vol.2-3-444,
Vol.2-3-449, Vol.2-4-144, Vol.2-4-523, Vol.2-4-590,
Vol.2-4-611, Vol.2-4-614, Vol.2-4-655
CH register, Vol.1-3-12
CL register, Vol.1-3-12
CLC instruction, Vol.1-3-16, Vol.1-7-21, Vol.2-3-137
CLD instruction, Vol.1-3-17, Vol.1-7-21, Vol.2-3-138
CLFLSH feature flag, CPUID instruction, Vol.3-9-8
CLFLUSH instruction, Vol.1-11-12, Vol.2-3-139, Vol.2-3-141, Vol.3-2-15,
Vol.3-9-8, Vol.3-11-17
CPUID flag, Vol.2-3-209
CLI instruction, Vol.1-18-3, Vol.2-3-143, Vol.3-6-7
Clocks
counting processor clocks, Vol.3-18-105
INDEX
Hyper-Threading Technology, Vol.3-18-105
nominal CPI, Vol.3-18-105
non-halted clockticks, Vol.3-18-105
non-halted CPI, Vol.3-18-105
non-sleep Clockticks, Vol.3-18-105
time stamp counter, Vol.3-18-105
CLTS instruction, Vol.2-3-145, Vol.3-2-22, Vol.3-5-24, Vol.3-25-2,
Vol.3-25-6
Cluster model, local APIC, Vol.3-10-24
CMC instruction, Vol.1-3-16, Vol.1-7-21, Vol.2-3-148
CMOVcc flag, Vol.2-3-209
CMOVcc instructions, Vol.1-7-3, Vol.1-7-4, Vol.2-3-149, Vol.3-22-4
CPUID flag, Vol.2-3-209
CMP instruction, Vol.1-7-8, Vol.2-3-153
CMPPD- Compare Packed Double-Precision Floating-Point Values,
Vol.2-3-155
CMPPD instruction, Vol.1-11-7
CMPPS- Compare Packed Single-Precision Floating-Point Values,
Vol.2-3-162
CMPPS instruction, Vol.1-10-9
CMPS instruction, Vol.1-3-17, Vol.1-7-18, Vol.2-3-169, Vol.2-4-550
CMPSB instruction, Vol.2-3-169
CMPSD- Compare Scalar Double-Precision Floating-Point Values,
Vol.2-3-173
CMPSD instruction, Vol.1-11-7, Vol.2-3-169
CMPSQ instruction, Vol.2-3-169
CMPSS- Compare Scalar Single-Precision Floating-Point Values,
Vol.2-3-177
CMPSS instruction, Vol.1-10-9
CMPSW instruction, Vol.2-3-169
CMPXCHG instruction, Vol.1-7-4, Vol.2-3-181, Vol.2-3-537, Vol.3-8-3,
Vol.3-22-4
CMPXCHG16B instruction, Vol.1-7-5, Vol.2-3-183
CPUID bit, Vol.2-3-207
CMPXCHG8B instruction, Vol.1-7-4, Vol.2-3-183, Vol.3-8-3, Vol.3-22-4
CPUID flag, Vol.2-3-209
Code modules
16 bit vs. 32 bit, Vol.3-21-1
mixing 16-bit and 32-bit code, Vol.3-21-1
sharing data, mixed-size code segs, Vol.3-21-3
transferring control, mixed-size code segs, Vol.3-21-3
Code segment, Vol.1-3-14
Code segments
accessing data in, Vol.3-5-9
accessing through a call gate, Vol.3-5-15
description of, Vol.3-3-12
descriptor format, Vol.3-5-2
descriptor layout, Vol.3-5-2
direct calls or jumps to, Vol.3-5-10
paging of, Vol.3-2-6
pointer size, Vol.3-21-4
privilege level checks
transferring control between code segs, Vol.3-5-10
COMISD- Compare Scalar Ordered Double-Precision Floating-Point Values
and Set EFLAGS, Vol.2-3-186
COMISD instruction, Vol.1-11-7
COMISS- Compare Scalar Ordered Single-Precision Floating-Point Values
and Set EFLAGS, Vol.2-3-188
COMISS instruction, Vol.1-10-9
Compare
compare and exchange, Vol.1-7-4
integers, Vol.1-7-8
real numbers, x87 FPU, Vol.1-8-20
strings, Vol.1-7-18
Compatibility
IA-32 architecture, Vol.3-22-1
software, Vol.3-1-6
Compatibility mode
address space, Vol.1-3-1
branch functions, Vol.1-6-9
call gate descriptors, Vol.1-6-9
code segment descriptor, Vol.3-5-3
code segment descriptors, Vol.3-9-12
control registers, Vol.3-2-13
CS.L and CS.D, Vol.3-9-12
debug registers, Vol.3-2-23
EFLAGS register, Vol.3-2-11
exception handling, Vol.3-2-5
gates, Vol.3-2-4
GDTR register, Vol.3-2-12, Vol.3-2-13
global and local descriptor tables, Vol.3-2-4
IDTR register, Vol.3-2-12
interrupt handling, Vol.3-2-5
introduction, Vol.1-2-21, Vol.1-3-1, Vol.2-2-7
L flag, Vol.3-3-12, Vol.3-5-4
memory management, Vol.3-2-6
memory models, Vol.1-3-9
MMX technology, Vol.1-9-2
operation, Vol.3-9-12
see 64-bit mode
segment loading instructions, Vol.3-3-9
segmentation, Vol.1-3-22
segments, Vol.3-3-5
SSE extensions, Vol.1-10-3
SSE2 extensions, Vol.1-11-3
SSE3 extensions, Vol.1-12-1
SSSE3 extensions, Vol.1-12-1
summary table notation, Vol.2-3-9
switching to, Vol.3-9-12
SYSCALL and SYSRET, Vol.3-5-22
SYSENTER and SYSEXIT, Vol.3-5-21
system flags, Vol.3-2-11
system registers, Vol.3-2-7
task register, Vol.3-2-13
x87 FPU, Vol.1-8-1
See also: 64-bit mode, IA-32e mode
See also: IA-32e mode, 64-bit mode
Compatibility, software, Vol.1-1-5, Vol.2-1-5
Condition code flags, EFLAGS register, Vol.2-3-149
Condition code flags, x87 FPU status word
branching on, Vol.1-8-6
compatibility information, Vol.3-22-7
conditional moves on, Vol.1-8-6
description of, Vol.1-8-4
flags affected by instructions, Vol.2-3-14
interpretation of, Vol.1-8-5
setting, Vol.2-3-401, Vol.2-3-403, Vol.2-3-406
use of, Vol.1-8-19
Conditional jump, Vol.2-3-483
Conditional moves, x87 FPU condition codes, Vol.1-8-6
Conforming code segment, Vol.2-3-515
Conforming code segments
accessing, Vol.3-5-12
C (conforming) flag, Vol.3-5-11
description of, Vol.3-3-13
Constants (floating point), Vol.1-8-18
Constants (floating point), loading, Vol.2-3-355
Context, task (see Task state)
Control registers
64-bit mode, Vol.1-3-5, Vol.3-2-13
CR0, Vol.3-2-13
CR1 (reserved), Vol.3-2-13
CR2, Vol.3-2-13
CR3 (PDBR), Vol.3-2-6, Vol.3-2-13
CR4, Vol.3-2-13
description of, Vol.3-2-13
introduction to, Vol.3-2-6
overview of, Vol.1-3-4
VMX operation, Vol.3-31-17
Control registers, moving values to and from, Vol.2-4-40
Coprocessor segment
overrun exception, Vol.3-6-30, Vol.3-22-11
Core microarchitecture, Vol.1-2-11, Vol.1-2-13, Vol.1-2-14
core microarchitecture, Vol.1-2-11, Vol.1-2-13
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -5
INDEX
Core Solo and Core Duo, Vol.1-2-4
Cosine, x87 FPU operation, Vol.1-8-21, Vol.2-3-331, Vol.2-3-383
Counter mask field
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors), Vol.3-18-4,
Vol.3-18-119
CPL, Vol.2-3-143, Vol.2-5-93
description of, Vol.3-5-7
field, CS segment selector, Vol.3-5-2
CPUID instruction, Vol.2-3-190, Vol.2-3-209
36-bit page size extension, Vol.2-3-209
APIC on-chip, Vol.2-3-209
availability, Vol.3-22-4
basic CPUID information, Vol.2-3-191
cache and TLB characteristics, Vol.2-3-191
CLFLUSH flag, Vol.1-11-12, Vol.2-3-209
CLFLUSH instruction cache line size, Vol.2-3-205
CMOVcc feature flag, Vol.1-7-3
CMPXCHG16B flag, Vol.2-3-207
CMPXCHG8B flag, Vol.2-3-209
control register flags, Vol.3-2-19
CPL qualified debug store, Vol.2-3-206
debug extensions, CR4.DE, Vol.2-3-209
debug store supported, Vol.2-3-210
detecting features, Vol.3-22-2
determine support for, Vol.1-3-17
deterministic cache parameters leaf, Vol.2-3-191, Vol.2-3-194,
Vol.2-3-195, Vol.2-3-196, Vol.2-3-197, Vol.2-3-198, Vol.2-3-199,
Vol.2-3-200
earlier processors, Vol.1-19-1
extended function information, Vol.2-3-202
feature information, Vol.2-3-208
FPU on-chip, Vol.2-3-209
FSAVE flag, Vol.2-3-210
FXRSTOR flag, Vol.2-3-210
FXSAVE-FXRSTOR flag, Vol.1-10-14
IA-32e mode available, Vol.2-3-202
input limits for EAX, Vol.2-3-203
L1 Context ID, Vol.2-3-207
local APIC physical ID, Vol.2-3-205
machine check architecture, Vol.2-3-209
machine check exception, Vol.2-3-209
memory type range registers, Vol.2-3-209
MMX feature flag, Vol.1-9-8
MONITOR feature information, Vol.2-3-214
MONITOR/MWAIT flag, Vol.2-3-206
MONITOR/MWAIT leaf, Vol.2-3-192, Vol.2-3-193, Vol.2-3-195,
Vol.2-3-201
MWAIT feature information, Vol.2-3-214
page attribute table, Vol.2-3-209
page size extension, Vol.2-3-209
performance monitoring features, Vol.2-3-215
physical address bits, Vol.2-3-203
physical address extension, Vol.2-3-209
power management, Vol.2-3-214, Vol.2-3-215, Vol.2-3-216
processor brand index, Vol.2-3-205, Vol.2-3-216
processor brand string, Vol.2-3-202, Vol.2-3-216
processor identification, Vol.1-19-1
processor serial number, Vol.2-3-191, Vol.2-3-209
processor type field, Vol.2-3-205
RDMSR flag, Vol.2-3-209
returned in EBX, Vol.2-3-205
returned in ECX & EDX, Vol.2-3-205
self snoop, Vol.2-3-210
serializing instructions, Vol.3-8-17
serializing use, Vol.1-18-5
SpeedStep technology, Vol.2-3-206
SS2 extensions flag, Vol.2-3-210
SSE extensions flag, Vol.2-3-210
SSE feature flag, Vol.1-10-1, Vol.1-10-6
SSE2 feature flag, Vol.1-11-1, Vol.1-12-5
SSE3 extensions flag, Vol.2-3-206
SSE3 feature flag, Vol.1-12-5
Index-6 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
SSSE2 feature flag, Vol.1-12-9, Vol.1-12-19, Vol.1-12-25
SSSE3 extensions flag, Vol.2-3-206
summary of, Vol.1-7-23
syntax for data, Vol.3-1-8
SYSENTER flag, Vol.2-3-209
SYSEXIT flag, Vol.2-3-209
thermal management, Vol.2-3-214, Vol.2-3-215, Vol.2-3-216
thermal monitor, Vol.2-3-206, Vol.2-3-210
time stamp counter, Vol.2-3-209
using CPUID, Vol.2-3-190
vendor ID string, Vol.2-3-204
version information, Vol.2-3-191, Vol.2-3-214
virtual 8086 Mode flag, Vol.2-3-209
virtual address bits, Vol.2-3-203
WRMSR flag, Vol.2-3-209
CQO instruction, Vol.2-3-278
CR0 control register, Vol.2-4-630, Vol.3-22-7
description of, Vol.3-2-13
introduction to, Vol.3-2-6
state following processor reset, Vol.3-9-2
CR1 control register (reserved), Vol.3-2-13
CR2 control register
description of, Vol.3-2-13
introduction to, Vol.3-2-6
CR3 control register (PDBR)
associated with a task, Vol.3-7-1, Vol.3-7-3
description of, Vol.3-2-13
in TSS, Vol.3-7-4, Vol.3-7-14
introduction to, Vol.3-2-6
loading during initialization, Vol.3-9-10
memory management, Vol.3-2-6
page directory base address, Vol.3-2-6
page table base address, Vol.3-2-5
CR4 control register
description of, Vol.3-2-13
enabling control functions, Vol.3-22-2
inclusion in IA-32 architecture, Vol.3-22-17
introduction to, Vol.3-2-6
VMX usage of, Vol.3-23-3
CR8 register, Vol.3-2-7
64-bit mode, Vol.3-2-13
compatibility mode, Vol.3-2-13
description of, Vol.3-2-13
task priority level bits, Vol.3-2-18
when available, Vol.3-2-13
CS register, Vol.1-3-13, Vol.1-3-14, Vol.2-3-123, Vol.2-3-457,
Vol.2-3-476, Vol.2-3-489, Vol.2-4-36, Vol.2-4-386,
Vol.3-22-10
state following initialization, Vol.3-9-5
C-state, Vol.3-14-18
CTI instruction, Vol.1-7-22
CTR0 and CTR1 (performance counters) MSRs (Pentium processor),
Vol.3-18-120, Vol.3-18-122
Current privilege level (see CPL)
Current stack, Vol.1-6-1, Vol.1-6-3
CVTDQ2PD- Convert Packed Doubleword Integers to Packed
Double-Precision Floating-Point Values, Vol.2-3-228,
Vol.2-5-25, Vol.2-5-31, Vol.2-5-50, Vol.2-5-52, Vol.2-5-57,
Vol.2-5-62, Vol.2-5-77, Vol.2-5-79
CVTDQ2PD instruction, Vol.1-11-10, Vol.2-3-225
CVTDQ2PS- Convert Packed Doubleword Integers to Packed
Single-Precision Floating-Point Values, Vol.2-3-232
CVTDQ2PS instruction, Vol.1-11-10
CVTPD2DQ- Convert Packed Double-Precision Floating-Point Values to
Packed Doubleword Integers, Vol.2-3-235
CVTPD2DQ instruction, Vol.1-11-10
CVTPD2PI instruction, Vol.1-11-10, Vol.2-3-239
CVTPD2PS- Convert Packed Double-Precision Floating-Point Values to
Packed Single-Precision Floating-Point Values, Vol.2-3-240
CVTPD2PS instruction, Vol.1-11-9
CVTPI2PD instruction, Vol.1-11-10, Vol.2-3-244
CVTPI2PS instruction, Vol.1-10-11, Vol.2-3-245
INDEX
CVTPS2DQ- Convert Packed Single Precision Floating-Point Values to
Packed Signed Doubleword Integer Values, Vol.2-3-246
CVTPS2DQ- Convert Packed Single Precision Floating-Point Values to
Packed Singed Doubleword Integer Values, Vol.2-5-47,
Vol.2-5-66, Vol.2-5-68
CVTPS2DQ instruction, Vol.1-11-10
CVTPS2PD instruction, Vol.1-11-9
CVTPS2PI instruction, Vol.1-10-11, Vol.2-3-252
CVTSD2SI- Convert Scalar Double Precision Floating-Point Value to
Doubleword Integer, Vol.2-3-253
CVTSD2SI instruction, Vol.1-11-10
CVTSD2SS instruction, Vol.1-11-9
CVTSI2SD- Convert Doubleword Integer to Scalar Double-Precision
Floating-Point Value, Vol.2-5-25, Vol.2-5-52, Vol.2-5-57,
Vol.2-5-62, Vol.2-5-79
CVTSI2SD instruction, Vol.1-11-10
CVTSI2SS- Convert Doubleword Integer to Scalar Single-Precision
Floating-Point Value, Vol.2-3-259
CVTSI2SS instruction, Vol.1-10-11
CVTSS2SD- Convert Scalar Single-Precision Floating-Point Value to Scalar
Double-Precision Floating-Point Value, Vol.2-3-261
CVTSS2SD instruction, Vol.1-11-9
CVTSS2SI- Convert Scalar Single-Precision Floating-Point Value to
Doubleword Integer, Vol.2-3-263
CVTSS2SI instruction, Vol.1-10-11
CVTTPD2DQ- Convert with Truncation Packed Double-Precision
Floating-Point Values to Packed Doubleword Integers,
Vol.2-3-265
CVTTPD2DQ instruction, Vol.1-11-10
CVTTPD2PI instruction, Vol.1-11-10, Vol.2-3-269
CVTTPS2DQ- Convert with Truncation Packed Single-Precision
Floating-Point Values to Packed Signed Doubleword Integer
Values, Vol.2-3-270
CVTTPS2DQ instruction, Vol.1-11-10
CVTTPS2PI instruction, Vol.1-10-11, Vol.2-3-273
CVTTSD2SI- Convert with Truncation Scalar Double-Precision
Floating-Point Value to Signed Integer, Vol.2-3-274
CVTTSD2SI instruction, Vol.1-11-10
CVTTSS2SI- Convert with Truncation Scalar Single-Precision Floating-Point
Value to Integer, Vol.2-3-276
CVTTSS2SI instruction, Vol.1-10-11
CWD instruction, Vol.1-7-7, Vol.2-3-278
CWDE instruction, Vol.1-7-7, Vol.2-3-135
CX register, Vol.1-3-12
C/C++ compiler intrinsics
compiler functional equivalents, Vol.1-C-1
composite, Vol.1-C-14
description of, Vol.2-3-12
lists of, Vol.1-C-1
simple, Vol.1-C-2
D
D (default operation size) flag
segment descriptor, Vol.3-21-1, Vol.3-22-32
D (default operation size) flag, segment descriptor, Vol.2-4-390
D (default size) flag, segment descriptor, Vol.1-6-2, Vol.1-6-3
DAA instruction, Vol.1-7-9, Vol.2-3-279
DAS instruction, Vol.1-7-9, Vol.2-3-281
Data breakpoint exception conditions, Vol.3-17-9
Data movement instructions, Vol.1-7-2
Data pointer, x87 FPU, Vol.1-8-9
Data registers, x87 FPU, Vol.1-8-1
Data segment, Vol.1-3-14
Data segments
description of, Vol.3-3-12
descriptor layout, Vol.3-5-2
expand-down type, Vol.3-3-11
paging of, Vol.3-2-6
privilege level checking when accessing, Vol.3-5-8
Data types
128-bit packed SIMD, Vol.1-4-8
64-bit mode, Vol.1-7-2
64-bit packed SIMD, Vol.1-4-8
alignment, Vol.1-4-2
BCD integers, Vol.1-4-9, Vol.1-7-9
bit field, Vol.1-4-7
byte, Vol.1-4-1
doubleword, Vol.1-4-1
floating-point, Vol.1-4-4
fundamental, Vol.1-4-1
integers, Vol.1-4-3
numeric, Vol.1-4-2
operated on by GP instructions, Vol.1-7-1, Vol.1-7-2
operated on by MMX technology, Vol.1-9-3
operated on by SSE extensions, Vol.1-10-5
operated on by SSE2 extensions, Vol.1-11-3
operated on by x87 FPU, Vol.1-8-13
operated on in 64-bit mode, Vol.1-4-7
packed bytes, Vol.1-9-3
packed doublewords, Vol.1-9-3
packed SIMD, Vol.1-4-8
packed words, Vol.1-9-3
pointers, Vol.1-4-6
quadword, Vol.1-4-1, Vol.1-9-3
signed integers, Vol.1-4-4
strings, Vol.1-4-8
unsigned integers, Vol.1-4-3
word, Vol.1-4-1
DAZ (denormals-are-zeros) flag
MXCSR register, Vol.1-10-5
DE (debugging extensions) flag, CR4 control register, Vol.3-2-17,
Vol.3-22-17, Vol.3-22-19
DE (denormal operand exception) flag
MXCSR register, Vol.1-11-15
x87 FPU status word, Vol.1-8-5, Vol.1-8-29
Debug exception (#DB), Vol.3-6-7, Vol.3-6-21, Vol.3-7-5, Vol.3-17-7,
Vol.3-17-12, Vol.3-17-40
Debug registers
64-bit mode, Vol.1-3-5
legacy modes, Vol.1-3-4
Debug registers, moving value to and from, Vol.2-4-43
Debug store (see DS)
DEBUGCTLMSR MSR, Vol.3-17-38, Vol.3-17-39, Vol.1-35-325
Debugging facilities
breakpoint exception (#BP), Vol.3-17-1
debug exception (#DB), Vol.3-17-1
DR6 debug status register, Vol.3-17-1
DR7 debug control register, Vol.3-17-1
exceptions, Vol.3-17-6
INT3 instruction, Vol.3-17-1
last branch, interrupt, and exception recording, Vol.3-17-1,
Vol.3-17-11
masking debug exceptions, Vol.3-6-7
overview of, Vol.3-17-1
performance-monitoring counters, Vol.3-18-1
registers
description of, Vol.3-17-2
introduction to, Vol.3-2-6
loading, Vol.3-2-23
RF (resume) flag, EFLAGS, Vol.3-17-1
see DS (debug store) mechanism
T (debug trap) flag, TSS, Vol.3-17-1
TF (trap) flag, EFLAGS, Vol.3-17-1
virtualization, Vol.3-32-1
VMX operation, Vol.3-32-1
DEC instruction, Vol.1-7-8, Vol.2-3-283, Vol.2-3-537, Vol.3-8-3
Decimal integers, x87 FPU, Vol.1-4-10
Deeper sleep, Vol.1-2-4
Denormal number (see Denormalized finite number)
Denormal operand exception (#D), Vol.3-22-9
overview of, Vol.1-4-20
SSE and SSE2 extensions, Vol.1-11-15
x87 FPU, Vol.1-8-28
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -7
INDEX
Denormalization process, Vol.1-4-15
Denormalized finite number, Vol.1-4-5, Vol.1-4-14, Vol.2-3-406
Denormalized operand, Vol.3-22-12
Denormals-are-zero
DAZ flag, MXCSR register, Vol.1-10-5, Vol.1-11-2, Vol.1-11-3,
Vol.1-11-20
mode, Vol.1-10-5, Vol.1-11-20
Detecting and Enabling SMX
level 2, Vol.1-6-1
Device-not-available exception (#NM), Vol.3-2-15, Vol.3-2-22,
Vol.3-6-27, Vol.3-9-7, Vol.3-22-10, Vol.3-22-11
DF (direction) flag, EFLAGS register, Vol.1-3-17, Vol.1-A-1, Vol.2-3-138,
Vol.2-3-170, Vol.2-3-451, Vol.2-3-539, Vol.2-4-107,
Vol.2-4-176, Vol.2-4-592, Vol.2-4-644
DFR
Destination Format Register, Vol.3-10-37, Vol.3-10-41, Vol.3-10-46
DH register, Vol.1-3-12
DI register, Vol.1-3-12
Digital media boost, Vol.1-2-4
Digital readout bits, Vol.3-14-26, Vol.3-14-29
Displacement (operand addressing), Vol.1-3-22, Vol.1-3-23, Vol.1-3-24,
Vol.2-2-3
DIV instruction, Vol.1-7-9, Vol.2-3-285, Vol.3-6-20
Divide, Vol.1-4-20
Divide by zero exception (#Z)
SSE and SSE2 extensions, Vol.1-11-15
x87 FPU, Vol.1-8-29
Divide configuration register, local APIC, Vol.3-10-16
Divide error exception (#DE), Vol.2-3-285
Divide-error exception (#DE), Vol.3-6-20, Vol.3-22-20
DIVPD- Divide Packed Double-Precision Floating-Point Values,
Vol.2-3-288, Vol.2-5-323
DIVPD instruction, Vol.1-11-6
DIVPS- Divide Packed Single-Precision Floating-Point Values, Vol.2-3-291
DIVPS instruction, Vol.1-10-8
DIVSD- Divide Scalar Double-Precision Floating-Point Values, Vol.2-3-294
DIVSD instruction, Vol.1-11-6
DIVSS- Divide Scalar Single-Precision Floating-Point Values, Vol.2-3-296
DIVSS instruction, Vol.1-10-8
DL register, Vol.1-3-12
DM (denormal operand exception) mask bit
MXCSR register, Vol.1-11-15
x87 FPU, Vol.1-8-29
x87 FPU control word, Vol.1-8-7
Double-extended-precision FP format, Vol.1-4-4
Double-fault exception (#DF), Vol.3-6-28, Vol.3-22-26
Double-precision floating-point format, Vol.1-4-4
Doubleword, Vol.1-4-1
DPL (descriptor privilege level) field, segment descriptor, Vol.3-3-11,
Vol.3-5-2, Vol.3-5-4, Vol.3-5-7
DR0-DR3 breakpoint-address registers, Vol.3-17-1, Vol.3-17-3,
Vol.3-17-37, Vol.3-17-39, Vol.3-17-40
DR4-DR5 debug registers, Vol.3-17-3, Vol.3-22-19
DR6 debug status register, Vol.3-17-3
B0-B3 (BP detected) flags, Vol.3-17-3
BD (debug register access detected) flag, Vol.3-17-3
BS (single step) flag, Vol.3-17-3
BT (task switch) flag, Vol.3-17-3
debug exception (#DB), Vol.3-6-21
reserved bits, Vol.3-22-19
DR7 debug control register, Vol.3-17-4
G0-G3 (global breakpoint enable) flags, Vol.3-17-4
GD (general detect enable) flag, Vol.3-17-4
GE (global exact breakpoint enable) flag, Vol.3-17-4
L0-L3 (local breakpoint enable) flags, Vol.3-17-4
LE local exact breakpoint enable) flag, Vol.3-17-4
LEN0-LEN3 (Length) fields, Vol.3-17-4
R/W0-R/W3 (read/write) fields, Vol.3-17-4, Vol.3-22-19
DS feature flag, CPUID instruction, Vol.3-17-17, Vol.3-17-32,
Vol.3-17-36, Vol.3-17-37
DS register, Vol.1-3-13, Vol.1-3-14, Vol.2-3-169, Vol.2-3-521,
Vol.2-3-539, Vol.2-4-107, Vol.2-4-176
Index-8 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
DS save area, Vol.3-17-19, Vol.3-17-20, Vol.3-17-21
DS (debug store) mechanism
availability of, Vol.3-18-90
description of, Vol.3-18-90
DS feature flag, CPUID instruction, Vol.3-18-90
DS save area, Vol.3-17-17, Vol.3-17-20
IA-32e mode, Vol.3-17-20
interrupt service routine (DS ISR), Vol.3-17-24
setting up, Vol.3-17-22
Dual-core technology
architecture, Vol.3-8-31
introduction, Vol.1-2-19
logical processors supported, Vol.3-8-24
MTRR memory map, Vol.3-8-32
multi-threading feature flag, Vol.3-8-24
performance monitoring, Vol.3-18-108
specific features, Vol.3-22-4
Dual-monitor treatment, Vol.3-34-19
DX register, Vol.1-3-12
Dynamic data flow analysis, Vol.1-2-8
Dynamic execution, Vol.1-2-8, Vol.1-2-11, Vol.1-2-13, Vol.1-2-14
D/B (default operation size/default stack pointer size and/or upper bound)
flag, segment descriptor, Vol.3-3-11, Vol.3-5-4
E
E (edge detect) flag
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family), Vol.3-18-4
E (edge detect) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family
processors), Vol.3-18-118
E (expansion direction) flag
segment descriptor, Vol.3-5-2, Vol.3-5-4
E (MTRRs enabled) flag
IA32_MTRR_DEF_TYPE MSR, Vol.3-11-23
EAX register, Vol.1-3-11, Vol.1-3-12
EBP register, Vol.1-3-11, Vol.1-3-12, Vol.1-6-3, Vol.1-6-5
EBX register, Vol.1-3-11, Vol.1-3-12
ECX register, Vol.1-3-11, Vol.1-3-12
EDI register, Vol.1-3-11, Vol.1-3-12, Vol.2-4-592, Vol.2-4-644,
Vol.2-4-648
EDX register, Vol.1-3-11, Vol.1-3-12
Effective address, Vol.1-3-23, Vol.2-3-525
EFLAGS register
64-bit mode, Vol.1-7-2
condition codes, Vol.1-B-1, Vol.2-3-151, Vol.2-3-323, Vol.2-3-328
cross-reference with instructions, Vol.1-A-1
description of, Vol.1-3-15
flags affected by instructions, Vol.2-3-14
identifying 32-bit processors, Vol.3-22-6
instructions that operate on, Vol.1-7-21
introduction to, Vol.3-2-6
new flags, Vol.3-22-5
overview, Vol.1-3-11
part of basic programming environment, Vol.1-7-1
popping, Vol.2-4-394
popping on return from interrupt, Vol.2-3-476
pushing, Vol.2-4-516
pushing on interrupts, Vol.2-3-457
restoring from stack, Vol.1-6-6
saved in TSS, Vol.3-7-4
saving, Vol.2-4-580
saving on a procedure call, Vol.1-6-6
status flags, Vol.1-8-6, Vol.1-8-7, Vol.1-8-20, Vol.2-3-153,
Vol.2-3-486, Vol.2-4-597, Vol.2-4-679
system flags, Vol.3-2-9
use with CMOVcc instructions, Vol.1-7-3
VMX operation, Vol.3-31-2
EIP register, Vol.2-3-123, Vol.2-3-457, Vol.2-3-476, Vol.2-3-489,
Vol.3-22-10
description of, Vol.1-3-18
overview, Vol.1-3-11
part of basic programming environment, Vol.1-7-1
INDEX
relationship to CS register, Vol.1-3-14
saved in TSS, Vol.3-7-4
state following initialization, Vol.3-9-5
EM (emulation) flag
CR0 control register, Vol.3-2-15, Vol.3-2-16, Vol.3-6-27, Vol.3-9-6,
Vol.3-9-7, Vol.3-12-1, Vol.3-13-3
EMMS instruction, Vol.1-9-8, Vol.1-9-9, Vol.2-3-303, Vol.3-12-3
Encodings
See machine instructions, opcodes
Enhanced Intel Deeper Sleep, Vol.1-2-4
Enhanced Intel SpeedStep Technology
ACPI 3.0 specification, Vol.3-14-1
IA32_APERF MSR, Vol.3-14-2
IA32_MPERF MSR, Vol.3-14-2
IA32_PERF_CTL MSR, Vol.3-14-1
IA32_PERF_STATUS MSR, Vol.3-14-1
introduction, Vol.3-14-1
multiple processor cores, Vol.3-14-1
performance transitions, Vol.3-14-1
P-state coordination, Vol.3-14-1
See also: thermal monitoring
ENTER instruction, Vol.1-6-14, Vol.1-7-21, Vol.2-3-304
GETSEC, Vol.1-6-3, Vol.1-6-10, Vol.1-5-34
EOI
End Of Interrupt register, Vol.3-10-38
Error code, Vol.3-16-3, Vol.3-16-7, Vol.3-16-10, Vol.3-16-13,
Vol.3-16-15
architectural MCA, Vol.3-16-1, Vol.3-16-3, Vol.3-16-7, Vol.3-16-10,
Vol.3-16-13, Vol.3-16-15
decoding IA32_MCi_STATUS, Vol.3-16-1, Vol.3-16-3, Vol.3-16-7,
Vol.3-16-10, Vol.3-16-13, Vol.3-16-15
exception, description of, Vol.3-6-14
external bus, Vol.3-16-1, Vol.3-16-3, Vol.3-16-7, Vol.3-16-10,
Vol.3-16-13, Vol.3-16-15
memory hierarchy, Vol.3-16-3, Vol.3-16-7, Vol.3-16-10, Vol.3-16-13,
Vol.3-16-15
pushing on stack, Vol.3-22-31
watchdog timer, Vol.3-16-1, Vol.3-16-3, Vol.3-16-7, Vol.3-16-10,
Vol.3-16-13, Vol.3-16-15
Error numbers
VM-instruction error field, Vol.3-30-29
Error signals, Vol.3-22-10
Error-reporting bank registers, Vol.3-15-2
ERROR#
input, Vol.3-22-15
output, Vol.3-22-15
ES register, Vol.1-3-13, Vol.1-3-14, Vol.2-3-521, Vol.2-4-176,
Vol.2-4-592, Vol.2-4-648
ES (exception summary) flag
x87 FPU status word, Vol.1-8-31
ES0 and ES1 (event select) fields, CESR MSR (Pentium processor),
Vol.3-18-121
ESC instructions, x87 FPU, Vol.1-8-15
ESI register, Vol.1-3-11, Vol.1-3-12, Vol.2-3-169, Vol.2-3-539,
Vol.2-4-107, Vol.2-4-176, Vol.2-4-644
ESP register, Vol.1-3-12, Vol.2-3-123, Vol.2-4-386
ESP register (stack pointer), Vol.1-3-11, Vol.1-6-3
ESR
Error Status Register, Vol.3-10-39
ET (extension type) flag, CR0 control register, Vol.3-2-15, Vol.3-22-7
Event select field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family
processors), Vol.3-18-3, Vol.3-18-18, Vol.3-18-118
Events
at-retirement, Vol.3-18-96
at-retirement (Pentium 4 processor), Vol.3-18-85
non-retirement (Pentium 4 processor), Vol.3-18-85, Vol.3-19-173
P6 family processors, Vol.3-19-204
Pentium processor, Vol.3-19-213
EVEX.R, Vol.2-3-5
Exception flags, x87 FPU status word, Vol.1-8-5
Exception handler
calling, Vol.3-6-11
defined, Vol.3-6-1
flag usage by handler procedure, Vol.3-6-14
machine-check exception handler, Vol.3-15-27
machine-check exceptions (#MC), Vol.3-15-27
machine-error logging utility, Vol.3-15-27
procedures, Vol.3-6-11
protection of handler procedures, Vol.3-6-13
task, Vol.3-6-14, Vol.3-7-2
Exception handlers
overview of, Vol.1-6-10
SIMD floating-point exceptions, Vol.1-E-1
SSE and SSE2 extensions, Vol.1-11-17, Vol.1-11-18
typical actions of a FP exception handler, Vol.1-4-23
x87 FPU, Vol.1-8-32
Exception priority, floating-point exceptions, Vol.1-4-23
Exception-flag masks, x87 FPU control word, Vol.1-8-7
Exceptions
64-bit mode, Vol.1-6-14
alignment check, Vol.3-22-11
BOUND range exceeded (#BR), Vol.2-3-106
classifications, Vol.3-6-4
compound error codes, Vol.3-15-20
conditions checked during a task switch, Vol.3-7-11
coprocessor segment overrun, Vol.3-22-11
description of, Vol.1-6-9, Vol.3-2-5, Vol.3-6-1
device not available, Vol.3-22-11
double fault, Vol.3-6-28
error code, Vol.3-6-14
exception bitmap, Vol.3-32-1
execute-disable bit, Vol.3-5-32
floating-point error, Vol.3-22-11
general protection, Vol.3-22-11
handler, Vol.1-6-10
handler mechanism, Vol.3-6-11
handler procedures, Vol.3-6-11
handling, Vol.3-6-11
handling in real-address mode, Vol.3-20-4
handling in SMM, Vol.3-34-10
handling in virtual-8086 mode, Vol.3-20-11
handling through a task gate in virtual-8086 mode, Vol.3-20-14
handling through a trap or interrupt gate in virtual-8086 mode,
Vol.3-20-12
IA-32e mode, Vol.3-2-5
IDT, Vol.3-6-9
implicit call to handler, Vol.1-6-1
in real-address mode, Vol.1-6-13
initializing for protected-mode operation, Vol.3-9-10
invalid-opcode, Vol.3-22-5
masking debug exceptions, Vol.3-6-7
masking when switching stack segments, Vol.3-6-7
MCA error codes, Vol.3-15-20
MMX instructions, Vol.3-12-1
notation, Vol.1-1-7, Vol.2-1-6, Vol.3-1-9
overflow exception (#OF), Vol.2-3-457
overview of, Vol.3-6-1
priorities among simultaneous exceptions and interrupts, Vol.3-6-8
priority of, Vol.3-22-21
priority of, x87 FPU exceptions, Vol.3-22-10
reference information on all exceptions, Vol.3-6-19
reference information, 64-bit mode, Vol.3-6-16
restarting a task or program, Vol.3-6-5
returning from, Vol.2-3-476
segment not present, Vol.3-22-11
simple error codes, Vol.3-15-20
sources of, Vol.3-6-4
summary of, Vol.3-6-2
vectors, Vol.3-6-1
Executable, Vol.3-3-11
Execute-disable bit capability
conditions for, Vol.3-5-30
CPUID flag, Vol.3-5-30
detecting and enabling, Vol.3-5-30
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -9
INDEX
exception handling, Vol.3-5-32
page-fault exceptions, Vol.3-6-40
protection matrix for IA-32e mode, Vol.3-5-31
protection matrix for legacy modes, Vol.3-5-31
reserved bit checking, Vol.3-5-31
Execution events, Vol.3-19-196
GETSEC, Vol.1-6-3, Vol.1-6-5
Exit-reason numbers
VM entries & exits, Vol.1-C-1
Expand-down data segment type, Vol.3-3-11
Exponent, extracting from floating-point number, Vol.2-3-421
Exponent, floating-point number, Vol.1-4-11
Extended signature table, Vol.3-9-31
extended signature table, Vol.3-9-31
External bus errors, detected with machine-check architecture,
Vol.3-15-26
Extract exponent and significand, x87 FPU operation, Vol.2-3-421
EXTRACTPS- Extract packed floating-point values, Vol.2-3-307
F
F2XM1 instruction, Vol.1-8-22, Vol.2-3-309, Vol.2-3-421, Vol.3-22-13
FABS instruction, Vol.1-8-18, Vol.2-3-311
FADD instruction, Vol.1-8-18, Vol.2-3-312
FADDP instruction, Vol.1-8-18, Vol.2-3-312
Family 06H, Vol.3-16-1
Family 0FH, Vol.3-16-1
microcode update facilities, Vol.3-9-28
Far call
description of, Vol.1-6-4
operation, Vol.1-6-4
Far pointer
16-bit addressing, Vol.1-3-9
32-bit addressing, Vol.1-3-9
64-bit mode, Vol.1-4-7
description of, Vol.1-3-7, Vol.1-4-6
legacy modes, Vol.1-4-6
Far pointer, loading, Vol.2-3-521
Far return operation, Vol.1-6-4
Far return, RET instruction, Vol.2-4-553
Faults
description of, Vol.3-6-5
restarting a program or task after, Vol.3-6-5
FBLD instruction, Vol.1-8-16, Vol.2-3-315
FBSTP instruction, Vol.1-8-17, Vol.2-3-317
FCHS instruction, Vol.1-8-18, Vol.2-3-319
FCLEX instruction, Vol.2-3-321
FCLEX/FNCLEX instructions, Vol.1-8-5
FCMOVcc instructions, Vol.1-8-7, Vol.1-8-17, Vol.2-3-323, Vol.3-22-4
FCOM instruction, Vol.1-8-6, Vol.1-8-19, Vol.2-3-325
FCOMI instruction, Vol.1-8-7, Vol.1-8-19, Vol.2-3-328, Vol.3-22-4
FCOMIP instruction, Vol.1-8-7, Vol.1-8-19, Vol.2-3-328, Vol.3-22-4
FCOMP instruction, Vol.1-8-6, Vol.1-8-19, Vol.2-3-325
FCOMPP instruction, Vol.1-8-6, Vol.1-8-19, Vol.2-3-325
FCOS instruction, Vol.1-8-5, Vol.1-8-21, Vol.2-3-331, Vol.3-22-12
FDECSTP instruction, Vol.2-3-333
FDISI instruction (obsolete), Vol.3-22-14
FDIV instruction, Vol.1-8-18, Vol.2-3-334, Vol.3-22-11, Vol.3-22-12
FDIVP instruction, Vol.1-8-18, Vol.2-3-334
FDIVR instruction, Vol.1-8-18, Vol.2-3-337
FDIVRP instruction, Vol.1-8-18, Vol.2-3-337
FE (fixed MTRRs enabled) flag, IA32_MTRR_DEF_TYPE MSR, Vol.3-11-23
Feature
determination, of processor, Vol.3-22-2
information, processor, Vol.3-22-2
Feature determination, of processor, Vol.1-19-1
Feature information, processor, Vol.2-3-190
FENI instruction (obsolete), Vol.3-22-14
FFREE instruction, Vol.2-3-340
FIADD instruction, Vol.1-8-18, Vol.2-3-312
FICOM instruction, Vol.1-8-6, Vol.1-8-19, Vol.2-3-341
FICOMP instruction, Vol.1-8-6, Vol.1-8-19, Vol.2-3-341
Index-10 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
FIDIV instruction, Vol.1-8-18, Vol.2-3-334
FIDIVR instruction, Vol.1-8-18, Vol.2-3-337
FILD instruction, Vol.1-8-16, Vol.2-3-343
FIMUL instruction, Vol.1-8-18, Vol.2-3-361
FINCSTP instruction, Vol.2-3-345
FINIT instruction, Vol.2-3-346
FINIT/FNINIT instructions, Vol.1-8-5, Vol.1-8-7, Vol.1-8-8, Vol.1-8-24,
Vol.2-3-376, Vol.3-22-7, Vol.3-22-15
FIST instruction, Vol.1-8-17, Vol.2-3-348
FISTP instruction, Vol.1-8-17, Vol.2-3-348
FISTTP instruction, Vol.1-5-20, Vol.1-12-3, Vol.2-3-351
FISUB instruction, Vol.1-8-18, Vol.2-3-395
FISUBR instruction, Vol.1-8-18, Vol.2-3-398
FIX (fixed range registers supported) flag, IA32_MTRRCAPMSR,
Vol.3-11-22
Fixed-range MTRRs
description of, Vol.3-11-23
Flags
cross-reference with instructions, Vol.1-A-1
Flat memory model, Vol.1-3-7, Vol.1-3-13
Flat segmentation model, Vol.3-3-3
FLD instruction, Vol.1-8-16, Vol.2-3-353, Vol.3-22-13
FLD1 instruction, Vol.1-8-18, Vol.2-3-355
FLDCW instruction, Vol.1-8-7, Vol.1-8-24, Vol.2-3-357
FLDENV instruction, Vol.1-8-5, Vol.1-8-9, Vol.1-8-11, Vol.1-8-24,
Vol.2-3-359, Vol.3-22-11
FLDL2E instruction, Vol.1-8-18, Vol.2-3-355, Vol.3-22-13
FLDL2T instruction, Vol.1-8-18, Vol.2-3-355, Vol.3-22-13
FLDLG2 instruction, Vol.1-8-18, Vol.2-3-355, Vol.3-22-13
FLDLN2 instruction, Vol.1-8-18, Vol.2-3-355, Vol.3-22-13
FLDPI instruction, Vol.1-8-18, Vol.2-3-355, Vol.3-22-13
FLDSW instruction, Vol.1-8-24
FLDZ instruction, Vol.1-8-18, Vol.2-3-355
Floating point instructions
machine encodings, Vol.1-B-64
Floating-point data types
biasing constant, Vol.1-4-6
denormalized finite number, Vol.1-4-5
description of, Vol.1-4-4
double extended precision format, Vol.1-4-4, Vol.1-4-5
double precision format, Vol.1-4-4, Vol.1-4-5
infinites, Vol.1-4-5
normalized finite number, Vol.1-4-5
single precision format, Vol.1-4-4, Vol.1-4-5
SSE extensions, Vol.1-10-5
SSE2 extensions, Vol.1-11-3
storing in memory, Vol.1-4-6
x87 FPU, Vol.1-8-13
zeros, Vol.1-4-5
Floating-point error exception (#MF), Vol.3-22-11
Floating-point exception handlers
SSE and SSE2 extensions, Vol.1-11-17, Vol.1-11-18
typical actions, Vol.1-4-23
x87 FPU, Vol.1-8-32
Floating-point exceptions
denormal operand exception (#D), Vol.1-4-20, Vol.1-8-28,
Vol.1-11-15, Vol.1-C-1, Vol.3-22-9
divide by zero exception (#Z), Vol.1-4-20, Vol.1-8-29, Vol.1-11-15,
Vol.1-C-1
exception conditions, Vol.1-4-19
exception priority, Vol.1-4-23
inexact result (precision) exception (#P), Vol.1-4-22, Vol.1-8-31,
Vol.1-11-16, Vol.1-C-1
invalid operation exception (#I), Vol.1-4-20, Vol.1-8-27, Vol.1-11-14
invalid operation (#I), Vol.3-22-13
invalid-operation exception (#IA), Vol.1-C-1
invalid-operation exception (#IS), Vol.1-C-1
invalid-operation exception (#I), Vol.1-C-1
numeric overflow exception (#O), Vol.1-4-20, Vol.1-8-29,
Vol.1-11-15, Vol.1-C-1
numeric overflow (#O), Vol.3-22-9
INDEX
numeric underflow exception (#U), Vol.1-4-21, Vol.1-8-30,
Vol.1-11-16, Vol.1-C-1
numeric underflow (#U), Vol.3-22-10
saved CS and EIP values, Vol.3-22-10
SSE and SSE2 SIMD, Vol.2-3-16
summary of, Vol.1-4-18, Vol.1-C-1
typical handler actions, Vol.1-4-23
x87 FPU, Vol.2-3-16
Floating-point format
biased exponent, Vol.1-4-13
description of, Vol.1-8-13
exponent, Vol.1-4-11
fraction, Vol.1-4-11
indefinite, Vol.1-4-5
QNaN floating-point indefinite, Vol.1-4-17
real number system, Vol.1-4-11
sign, Vol.1-4-11
significand, Vol.1-4-11
Floating-point numbers
defined, Vol.1-4-11
encoding, Vol.1-4-5
Flushing
caches, Vol.2-3-469, Vol.2-5-568
TLB entry, Vol.2-3-471
Flush-to-zero
FZ flag, MXCSR register, Vol.1-10-4, Vol.1-11-2
mode, Vol.1-10-4
FLUSH# pin, Vol.3-6-3
FMA operation, Vol.1-14-22, Vol.1-14-23
FMUL instruction, Vol.1-8-18, Vol.2-3-361
FMULP instruction, Vol.1-8-18, Vol.2-3-361
FNCLEX instruction, Vol.2-3-321
FNINIT instruction, Vol.2-3-346
FNOP instruction, Vol.1-8-24, Vol.2-3-364
FNSAVE instruction, Vol.2-3-376, Vol.3-12-4
FNSTCW instruction, Vol.2-3-389
FNSTENV instruction, Vol.2-3-359, Vol.2-3-391
FNSTSW instruction, Vol.2-3-393
Focus processor, local APIC, Vol.3-10-25
Fopcode compatibility mode, Vol.1-8-10
FORCEPR# log, Vol.3-14-25, Vol.3-14-29
FORCPR# interrupt enable bit, Vol.3-14-27
FPATAN instruction, Vol.1-8-21, Vol.2-3-365, Vol.3-22-13
FPREM instruction, Vol.1-8-5, Vol.1-8-18, Vol.1-8-21, Vol.2-3-367,
Vol.3-22-7, Vol.3-22-11, Vol.3-22-12
FPREM1 instruction, Vol.1-8-5, Vol.1-8-18, Vol.1-8-21, Vol.2-3-369,
Vol.3-22-7, Vol.3-22-12
FPTAN instruction, Vol.1-8-5, Vol.2-3-371, Vol.3-22-7, Vol.3-22-12
Fraction, floating-point number, Vol.1-4-11
FRNDINT instruction, Vol.1-8-18, Vol.2-3-373
Front_end events, Vol.3-19-196
FRSTOR instruction, Vol.1-8-5, Vol.1-8-9, Vol.1-8-11, Vol.1-8-24,
Vol.2-3-374, Vol.3-12-4, Vol.3-22-11
FS register, Vol.1-3-13, Vol.1-3-14, Vol.2-3-521
FSAVE instruction, Vol.2-3-376, Vol.3-12-3, Vol.3-12-4
FSAVE/FNSAVE instructions, Vol.1-8-4, Vol.1-8-5, Vol.1-8-9, Vol.1-8-11,
Vol.1-8-24, Vol.2-3-374, Vol.3-22-11, Vol.3-22-14
FSCALE instruction, Vol.1-8-22, Vol.2-3-379, Vol.3-22-12
FSIN instruction, Vol.1-8-5, Vol.1-8-21, Vol.2-3-381, Vol.3-22-12
FSINCOS instruction, Vol.1-8-5, Vol.1-8-21, Vol.2-3-383, Vol.3-22-12
FSQRT instruction, Vol.1-8-18, Vol.2-3-385, Vol.3-22-11, Vol.3-22-12
FST instruction, Vol.1-8-17, Vol.2-3-387
FSTCW instruction, Vol.2-3-389
FSTCW/FNSTCW instructions, Vol.1-8-7, Vol.1-8-24
FSTENV instruction, Vol.2-3-391, Vol.3-12-3
FSTENV/FNSTENV instructions, Vol.1-8-4, Vol.1-8-9, Vol.1-8-11,
Vol.1-8-24, Vol.3-22-14
FSTP instruction, Vol.1-8-17, Vol.2-3-387
FSTSW instruction, Vol.2-3-393
FSTSW/FNSTSW instructions, Vol.1-8-4, Vol.1-8-24
FSUB instruction, Vol.1-8-18, Vol.2-3-395
FSUBP instruction, Vol.1-8-18, Vol.2-3-395
FSUBR instruction, Vol.1-8-18, Vol.2-3-398
FSUBRP instruction, Vol.1-8-18, Vol.2-3-398
FTAN instruction, Vol.3-22-7
FTST instruction, Vol.1-8-6, Vol.1-8-19, Vol.2-3-401
FUCOM instruction, Vol.1-8-19, Vol.2-3-403, Vol.3-22-12
FUCOMI instruction, Vol.1-8-7, Vol.1-8-19, Vol.2-3-328, Vol.3-22-4
FUCOMIP instruction, Vol.1-8-7, Vol.1-8-19, Vol.2-3-328, Vol.3-22-4
FUCOMP instruction, Vol.1-8-19, Vol.2-3-403, Vol.3-22-12
FUCOMPP instruction, Vol.1-8-6, Vol.1-8-19, Vol.2-3-403, Vol.3-22-12
FWAIT instruction, Vol.3-6-27
FXAM instruction, Vol.1-8-4, Vol.1-8-19, Vol.2-3-406, Vol.3-22-13,
Vol.3-22-14
FXCH instruction, Vol.1-8-17, Vol.2-3-408
FXRSTOR instruction, Vol.1-5-12, Vol.1-8-12, Vol.1-10-14, Vol.1-11-23,
Vol.2-3-410, Vol.3-2-17, Vol.3-2-18, Vol.3-9-8, Vol.3-12-3,
Vol.3-12-4, Vol.3-13-2, Vol.3-13-6
CPUID flag, Vol.2-3-210
FXSAVE instruction, Vol.1-5-12, Vol.1-8-12, Vol.1-10-14, Vol.1-11-23,
Vol.2-3-413, Vol.2-5-563, Vol.2-5-565, Vol.2-5-590,
Vol.2-5-602, Vol.2-5-606, Vol.2-5-610, Vol.2-5-613,
Vol.2-5-616, Vol.2-5-619, Vol.2-5-622, Vol.3-2-17,
Vol.3-2-18, Vol.3-9-8, Vol.3-12-3, Vol.3-12-4, Vol.3-13-2,
Vol.3-13-6
CPUID flag, Vol.2-3-210
FXSR feature flag, CPUID instruction, Vol.3-9-8
FXTRACT instruction, Vol.1-8-18, Vol.2-3-379, Vol.2-3-421, Vol.3-22-9,
Vol.3-22-13
FYL2X instruction, Vol.1-8-22, Vol.2-3-423
FYL2XP1 instruction, Vol.1-8-22, Vol.2-3-425
G
G (global) flag
page-directory entries, Vol.3-11-13
page-table entries, Vol.3-11-13
G (granularity) flag
segment descriptor, Vol.3-3-10, Vol.3-3-11, Vol.3-5-2, Vol.3-5-4
G0-G3 (global breakpoint enable) flags
DR7 register, Vol.3-17-4
Gate descriptors
call gates, Vol.3-5-13
description of, Vol.3-5-13
IA-32e mode, Vol.3-5-14
Gates, Vol.3-2-4
IA-32e mode, Vol.3-2-4
GD (general detect enable) flag
DR7 register, Vol.3-17-4, Vol.3-17-9
GDT
description of, Vol.3-2-3, Vol.3-3-15
IA-32e mode, Vol.3-2-4
index field of segment selector, Vol.3-3-7
initializing, Vol.3-9-10
paging of, Vol.3-2-6
pointers to exception/interrupt handlers, Vol.3-6-11
segment descriptors in, Vol.3-3-9
selecting with TI flag of segment selector, Vol.3-3-7
task switching, Vol.3-7-9
task-gate descriptor, Vol.3-7-8
TSS descriptors, Vol.3-7-5
use in address translation, Vol.3-3-6
GDT (global descriptor table), Vol.2-3-530, Vol.2-3-533
GDTR register, Vol.1-3-4, Vol.1-3-6
description of, Vol.3-2-3, Vol.3-2-6, Vol.3-2-12, Vol.3-3-15
IA-32e mode, Vol.3-2-4, Vol.3-2-12
limit, Vol.3-5-5
loading during initialization, Vol.3-9-10
storing, Vol.3-3-15
GDTR (global descriptor table register), Vol.2-3-530, Vol.2-4-600
GE (global exact breakpoint enable) flag
DR7 register, Vol.3-17-4, Vol.3-17-9
General purpose registers
64-bit mode, Vol.1-3-5, Vol.1-3-13
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -11
INDEX
description of, Vol.1-3-11
overview of, Vol.1-3-2, Vol.1-3-5
parameter passing, Vol.1-6-5
part of basic programming environment, Vol.1-7-1
using REX prefix, Vol.1-3-13
General-detect exception condition, Vol.3-17-9
General-protection exception (#GP), Vol.3-3-12, Vol.3-5-6, Vol.3-5-7,
Vol.3-5-11, Vol.3-5-12, Vol.3-6-9, Vol.3-6-13, Vol.3-6-37,
Vol.3-7-5, Vol.3-17-3, Vol.3-22-11, Vol.3-22-20, Vol.3-22-33,
Vol.3-22-34
General-purpose instructions
64-bit encodings, Vol.1-B-18
64-bit mode, Vol.1-7-1
basic programming environment, Vol.1-7-1
data types operated on, Vol.1-7-1, Vol.1-7-2
description of, Vol.1-7-1
non-64-bit encodings, Vol.1-B-7
origin of, Vol.1-7-1
programming with, Vol.1-7-1
summary of, Vol.1-5-3, Vol.1-7-2
General-purpose registers
moving value to and from, Vol.2-4-36
popping all, Vol.2-4-390
pushing all, Vol.2-4-514
General-purpose registers, saved in TSS, Vol.3-7-4
GETSEC, Vol.1-6-1, Vol.1-6-2, Vol.1-6-5
Global control MSRs, Vol.3-15-2
Global descriptor table register (see GDTR)
Global descriptor table (see GDT)
GS register, Vol.1-3-13, Vol.1-3-14, Vol.2-3-521
H
HADDPD instruction, Vol.1-5-21, Vol.1-12-4, Vol.2-3-427, Vol.2-3-428
HADDPS instruction, Vol.1-5-21, Vol.1-12-4, Vol.2-3-430
HALT state
relationship to SMI interrupt, Vol.3-34-3, Vol.3-34-13
Hardware Lock Elision (HLE), Vol.1-16-2
Hardware reset
description of, Vol.3-9-1
processor state after reset, Vol.3-9-2
state of MTRRs following, Vol.3-11-20
value of SMBASE following, Vol.3-34-4
Hexadecimal numbers, Vol.1-1-6, Vol.2-1-5, Vol.3-1-7
high-temperature interrupt enable bit, Vol.3-14-27, Vol.3-14-30
HITM# line, Vol.3-11-6
HLT instruction, Vol.2-3-433, Vol.3-2-24, Vol.3-5-24, Vol.3-6-29,
Vol.3-25-2, Vol.3-34-13, Vol.3-34-14
Horizontal processing model, Vol.1-12-1
HSUBPD instruction, Vol.1-5-21, Vol.1-12-5, Vol.2-3-434
HSUBPS instruction, Vol.1-5-21, Vol.1-12-4, Vol.2-3-437
HT Technology
first processor, Vol.1-2-3
implementing, Vol.1-2-18
introduction, Vol.1-2-17
Hyper-Threading Technology
architectural state of a logical processor, Vol.3-8-32
architecture description, Vol.3-8-26
caches, Vol.3-8-30
debug registers, Vol.3-8-29
description of, Vol.3-8-24, Vol.3-22-3, Vol.3-22-4
detecting, Vol.3-8-35, Vol.3-8-39, Vol.3-8-40
executing multiple threads, Vol.3-8-26
execution-based timing loops, Vol.3-8-52
external signal compatibility, Vol.3-8-31
halting logical processors, Vol.3-8-50
handling interrupts, Vol.3-8-26
HLT instruction, Vol.3-8-46
IA32_MISC_ENABLE MSR, Vol.3-8-29, Vol.3-8-32
initializing IA-32 processors with, Vol.3-8-25
introduction of into the IA-32 architecture, Vol.3-22-3, Vol.3-22-4
local a, Vol.3-8-27
Index-12 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
local APIC
functionality in logical processor, Vol.3-8-28
logical processors, identifying, Vol.3-8-35
machine check architecture, Vol.3-8-28
managing idle and blocked conditions, Vol.3-8-46
mapping resources, Vol.3-8-33
memory ordering, Vol.3-8-29
microcode update resources, Vol.3-8-29, Vol.3-8-32, Vol.3-9-35
MP systems, Vol.3-8-26
MTRRs, Vol.3-8-28, Vol.3-8-32
multi-threading feature flag, Vol.3-8-24
multi-threading support, Vol.3-8-24
PAT, Vol.3-8-28
PAUSE instruction, Vol.3-8-46, Vol.3-8-47
performance monitoring, Vol.3-18-100, Vol.3-18-108
performance monitoring counters, Vol.3-8-29, Vol.3-8-32
placement of locks and semaphores, Vol.3-8-52
required operating system support, Vol.3-8-48
scheduling multiple threads, Vol.3-8-51
self modifying code, Vol.3-8-30
serializing instructions, Vol.3-8-29
spin-wait loops
PAUSE instructions in, Vol.3-8-49, Vol.3-8-51
thermal monitor, Vol.3-8-31
TLBs, Vol.3-8-30
I
IA-32 architecture
history of, Vol.1-2-1
introduction to, Vol.1-2-1
IA-32 Intel architecture
compatibility, Vol.3-22-1
processors, Vol.3-22-1
IA32e mode
registers and mode changes, Vol.3-9-12
IA-32e mode
call gates, Vol.3-5-14
code segment descriptor, Vol.3-5-3
CPUID flag, Vol.2-3-202
D flag, Vol.3-5-4
data structures and initialization, Vol.3-9-11
debug registers, Vol.3-2-7
debug store area
descriptors, Vol.3-2-4
DPL field, Vol.3-5-4
exceptions during initialization, Vol.3-9-12
feature-enable register, Vol.3-2-7
gates, Vol.3-2-4
global and local descriptor tables, Vol.3-2-4
IA32_EFER MSR, Vol.3-2-7, Vol.3-5-30
initialization process, Vol.3-9-11
interrupt stack table, Vol.3-6-19
interrupts and exceptions, Vol.3-2-5
introduction, Vol.1-2-21, Vol.2-2-7, Vol.2-2-13, Vol.2-2-35
IRET instruction, Vol.3-6-18
L flag, Vol.3-3-12, Vol.3-5-4
logical address, Vol.3-3-7
MOV CRn, Vol.3-9-11
MTRR calculations, Vol.3-11-27
NXE bit, Vol.3-5-30
page level protection, Vol.3-5-30
paging, Vol.3-2-6
PDE tables, Vol.3-5-31
PDP tables, Vol.3-5-31
PML4 tables, Vol.3-5-31
PTE tables, Vol.3-5-31
registers and data structures, Vol.3-2-1
see 64-bit mode
see compatibility mode
segment descriptor tables, Vol.3-3-16, Vol.3-5-3
segment descriptors, Vol.3-3-9
INDEX
segment loading instructions, Vol.3-3-9
segmentation, Vol.1-3-22, Vol.3-3-5
stack switching, Vol.3-5-19, Vol.3-6-18
SYSCALL and SYSRET, Vol.3-5-22
SYSENTER and SYSEXIT, Vol.3-5-21
system descriptors, Vol.3-3-14
system registers, Vol.3-2-7
task switching, Vol.3-7-16
task-state segments, Vol.3-2-5
terminating mode operation, Vol.3-9-12
See also: 64-bit mode, compatibility mode
IA32_APERF MSR, Vol.3-14-2
IA32_APIC_BASE MSR, Vol.3-8-18, Vol.3-8-19, Vol.3-10-6, Vol.3-10-8,
Vol.1-35-278
IA32_BIOS_SIGN_ID MSR, Vol.1-35-281
IA32_BIOS_UPDT_TRIG MSR, Vol.3-32-9, Vol.1-35-281
IA32_BISO_SIGN_ID MSR, Vol.3-32-9
IA32_CLOCK_MODULATION MSR, Vol.3-8-31, Vol.3-14-7, Vol.3-14-10,
Vol.3-14-11, Vol.3-14-14, Vol.3-14-15, Vol.3-14-16,
Vol.3-14-17, Vol.3-14-23, Vol.3-14-24, Vol.3-14-26,
Vol.3-14-34, Vol.3-14-35, Vol.3-14-36, Vol.3-14-37,
Vol.3-14-38, Vol.1-35-48, Vol.1-35-61, Vol.1-35-70,
Vol.1-35-111, Vol.1-35-147, Vol.1-35-267, Vol.1-35-285,
Vol.1-35-307, Vol.1-35-316
IA32_CTL MSR, Vol.1-35-281
IA32_DEBUGCTL MSR, Vol.3-27-26, Vol.1-35-289
IA32_DS_AREA MSR, Vol.3-17-17, Vol.3-17-18, Vol.3-17-22,
Vol.3-18-83, Vol.3-18-99, Vol.1-35-299
IA32_EFER MSR, Vol.3-2-7, Vol.3-2-8, Vol.3-5-30, Vol.3-27-26,
Vol.3-31-16
IA32_FEATURE_CONTROL MSR, Vol.3-23-3
IA32_KernelGSbase MSR, Vol.3-2-7
IA32_LSTAR MSR, Vol.3-2-7, Vol.3-5-22
IA32_MCG_CAP MSR, Vol.3-15-2, Vol.3-15-27, Vol.1-35-281
IA32_MCG_CTL MSR, Vol.3-15-2, Vol.3-15-4
IA32_MCG_EAX MSR, Vol.3-15-11
IA32_MCG_EBP MSR, Vol.3-15-11
IA32_MCG_EBX MSR, Vol.3-15-11
IA32_MCG_ECX MSR, Vol.3-15-11
IA32_MCG_EDI MSR, Vol.3-15-11
IA32_MCG_EDX MSR, Vol.3-15-11
IA32_MCG_EFLAGS MSR, Vol.3-15-11
IA32_MCG_EIP MSR, Vol.3-15-11
IA32_MCG_ESI MSR, Vol.3-15-11
IA32_MCG_ESP MSR, Vol.3-15-11
IA32_MCG_MISC MSR, Vol.3-15-11, Vol.3-15-12, Vol.1-35-283
IA32_MCG_R10 MSR, Vol.3-15-12, Vol.1-35-284
IA32_MCG_R11 MSR, Vol.3-15-12, Vol.1-35-284
IA32_MCG_R12 MSR, Vol.3-15-12
IA32_MCG_R13 MSR, Vol.3-15-12
IA32_MCG_R14 MSR, Vol.3-15-12
IA32_MCG_R15 MSR, Vol.3-15-12, Vol.1-35-284
IA32_MCG_R8 MSR, Vol.3-15-12
IA32_MCG_R9 MSR, Vol.3-15-12
IA32_MCG_RAX MSR, Vol.3-15-11, Vol.1-35-282
IA32_MCG_RBP MSR, Vol.3-15-12
IA32_MCG_RBX MSR, Vol.3-15-11, Vol.1-35-282
IA32_MCG_RCX MSR, Vol.3-15-12
IA32_MCG_RDI MSR, Vol.3-15-12
IA32_MCG_RDX MSR, Vol.3-15-12
IA32_MCG_RESERVEDn, Vol.1-35-283, Vol.1-35-379
IA32_MCG_RESERVEDn MSR, Vol.3-15-11
IA32_MCG_RFLAGS MSR, Vol.3-15-12, Vol.1-35-283, Vol.1-35-379
IA32_MCG_RIP MSR, Vol.3-15-12, Vol.1-35-283, Vol.1-35-379
IA32_MCG_RSI MSR, Vol.3-15-12
IA32_MCG_RSP MSR, Vol.3-15-12
IA32_MCG_STATUS MSR, Vol.3-15-2, Vol.3-15-4, Vol.3-15-27,
Vol.3-15-29, Vol.3-27-3
IA32_MCi_ADDR MSR, Vol.3-15-9, Vol.3-15-29, Vol.1-35-296
IA32_MCi_CTL, Vol.3-15-5
IA32_MCi_CTL MSR, Vol.3-15-5, Vol.1-35-295
IA32_MCi_MISC MSR, Vol.3-15-9, Vol.3-15-10, Vol.3-15-11, Vol.3-15-29,
Vol.1-35-296
IA32_MCi_STATUS MSR, Vol.3-15-6, Vol.3-15-27, Vol.3-15-29,
Vol.1-35-295
decoding for Family 06H, Vol.3-16-1
decoding for Family 0FH, Vol.3-16-1, Vol.3-16-3, Vol.3-16-7,
Vol.3-16-10, Vol.3-16-13, Vol.3-16-15
IA32_MISC_ENABLE MSR, Vol.1-8-10, Vol.3-14-1, Vol.3-14-20,
Vol.3-17-18, Vol.3-17-32, Vol.3-18-83, Vol.1-35-285
IA32_MPERF MSR, Vol.3-14-1, Vol.3-14-2
IA32_MTRRCAP MSR, Vol.3-11-21, Vol.3-11-22, Vol.1-35-281
IA32_MTRR_DEF_TYPE MSR, Vol.3-11-22
IA32_MTRR_FIXn, fixed ranger MTRRs, Vol.3-11-23
IA32_MTRR_PHYS BASEn MTRR, Vol.1-35-289
IA32_MTRR_PHYSBASEn MTRR, Vol.1-35-290
IA32_MTRR_PHYSMASKn MTRR, Vol.1-35-289
IA32_P5_MC_ADDR MSR, Vol.1-35-277
IA32_P5_MC_TYPE MSR, Vol.1-35-277
IA32_PAT_CR MSR, Vol.3-11-34
IA32_PEBS_ENABLE MSR, Vol.3-18-22, Vol.3-18-83, Vol.3-18-99,
Vol.3-19-196, Vol.1-35-295
IA32_PERF_CTL MSR, Vol.3-14-1
IA32_PERF_STATUS MSR, Vol.3-14-1
IA32_PLATFORM_ID, Vol.1-35-43, Vol.1-35-57, Vol.1-35-107,
Vol.1-35-143, Vol.1-35-264, Vol.1-35-277, Vol.1-35-304,
Vol.1-35-312, Vol.1-35-319
IA32_STAR MSR, Vol.3-5-22
IA32_STAR_CS MSR, Vol.3-2-7
IA32_STATUS MSR, Vol.1-35-281
IA32_SYSCALL_FLAG_MASK MSR, Vol.3-2-7
IA32_SYSENTER_CS MSR, Vol.3-5-21, Vol.3-5-22, Vol.3-27-21,
Vol.1-35-281
IA32_SYSENTER_EIP MSR, Vol.3-5-21, Vol.3-27-26, Vol.1-35-281
IA32_SYSENTER_ESP MSR, Vol.3-5-21, Vol.3-27-26, Vol.1-35-281
IA32_TERM_CONTROL MSR, Vol.1-35-48, Vol.1-35-61, Vol.1-35-70,
Vol.1-35-111, Vol.1-35-147
IA32_THERM_INTERRUPT MSR, Vol.3-14-22, Vol.3-14-24, Vol.3-14-25,
Vol.3-14-27, Vol.1-35-285
FORCPR# interrupt enable bit, Vol.3-14-27
high-temperature interrupt enable bit, Vol.3-14-27, Vol.3-14-30
low-temperature interrupt enable bit, Vol.3-14-27, Vol.3-14-30
overheat interrupt enable bit, Vol.3-14-27, Vol.3-14-30
THERMTRIP# interrupt enable bit, Vol.3-14-27, Vol.3-14-30
threshold #1 interrupt enable bit, Vol.3-14-27, Vol.3-14-30
threshold #1 value, Vol.3-14-27, Vol.3-14-30
threshold #2 interrupt enable, Vol.3-14-27, Vol.3-14-30
threshold #2 value, Vol.3-14-27, Vol.3-14-30
IA32_THERM_STATUS MSR, Vol.3-14-24, Vol.3-14-25, Vol.1-35-285
digital readout bits, Vol.3-14-26, Vol.3-14-29
out-of-spec status bit, Vol.3-14-25, Vol.3-14-29
out-of-spec status log, Vol.3-14-26, Vol.3-14-29
PROCHOT# or FORCEPR# event bit, Vol.3-14-25, Vol.3-14-29
PROCHOT# or FORCEPR# log, Vol.3-14-25, Vol.3-14-29
resolution in degrees, Vol.3-14-26
thermal status bit, Vol.3-14-25, Vol.3-14-28
thermal status log, Vol.3-14-25, Vol.3-14-29
thermal threshold #1 log, Vol.3-14-26, Vol.3-14-29
thermal threshold #1 status, Vol.3-14-26, Vol.3-14-29
thermal threshold #2 log, Vol.3-14-26, Vol.3-14-29
thermal threshold #2 status, Vol.3-14-26, Vol.3-14-29
validation bit, Vol.3-14-26
IA32_TIME_STAMP_COUNTER MSR, Vol.1-35-277
IA32_VMX_BASIC MSR, Vol.3-24-3, Vol.3-31-2, Vol.3-31-5, Vol.3-31-6,
Vol.3-31-11, Vol.1-35-55, Vol.1-35-66, Vol.1-35-74,
Vol.1-35-119, Vol.1-35-156, Vol.1-35-273, Vol.1-35-298,
Vol.1-35-311, Vol.1-A-1, Vol.1-A-2
IA32_VMX_CR0_FIXED0 MSR, Vol.3-31-4, Vol.1-35-55, Vol.1-35-66,
Vol.1-35-74, Vol.1-35-120, Vol.1-35-156, Vol.1-35-273,
Vol.1-35-298, Vol.1-35-311, Vol.1-A-6
IA32_VMX_CR0_FIXED1 MSR, Vol.3-31-4, Vol.1-35-55, Vol.1-35-66,
Vol.1-35-74, Vol.1-35-120, Vol.1-35-156, Vol.1-35-273,
Vol.1-35-298, Vol.1-35-311, Vol.1-A-6
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -13
INDEX
IA32_VMX_CR4_FIXED0 MSR, Vol.3-31-4, Vol.1-35-55, Vol.1-35-66,
Vol.1-35-74, Vol.1-35-120, Vol.1-35-156, Vol.1-35-273,
Vol.1-35-298, Vol.1-35-311, Vol.1-A-6
IA32_VMX_CR4_FIXED1 MSR, Vol.3-31-4, Vol.1-35-55, Vol.1-35-66,
Vol.1-35-74, Vol.1-35-75, Vol.1-35-120, Vol.1-35-157,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-312, Vol.1-A-6
IA32_VMX_ENTRY_CTLS MSR, Vol.3-31-5, Vol.3-31-6, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-119, Vol.1-35-156,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-311, Vol.1-A-2,
Vol.1-A-5
IA32_VMX_EXIT_CTLS MSR, Vol.3-31-5, Vol.3-31-6, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-119, Vol.1-35-156,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-311, Vol.1-A-2,
Vol.1-A-4, Vol.1-A-5
IA32_VMX_MISC MSR, Vol.3-24-6, Vol.3-26-3, Vol.3-26-12, Vol.3-34-26,
Vol.1-35-55, Vol.1-35-66, Vol.1-35-74, Vol.1-35-119,
Vol.1-35-156, Vol.1-35-273, Vol.1-35-298, Vol.1-35-311,
Vol.1-A-5
IA32_VMX_PINBASED_CTLS MSR, Vol.3-31-5, Vol.3-31-6, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-119, Vol.1-35-156,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-311, Vol.1-A-2,
Vol.1-A-3
IA32_VMX_PROCBASED_CTLS MSR, Vol.3-24-9, Vol.3-31-5, Vol.3-31-6,
Vol.1-35-55, Vol.1-35-66, Vol.1-35-67, Vol.1-35-74,
Vol.1-35-75, Vol.1-35-119, Vol.1-35-120, Vol.1-35-156,
Vol.1-35-157, Vol.1-35-191, Vol.1-35-273, Vol.1-35-274,
Vol.1-35-298, Vol.1-35-311, Vol.1-35-312, Vol.1-A-2,
Vol.1-A-3, Vol.1-A-4, Vol.1-A-8
IA32_VMX_VMCS_ENUM MSR, Vol.1-35-298, Vol.1-A-7
ICR
Interrupt Command Register, Vol.3-10-38, Vol.3-10-41, Vol.3-10-47
ID (identification) flag
EFLAGS register, Vol.3-2-11, Vol.3-22-6
ID (identification) flag, EFLAGS register, Vol.1-3-17
IDIV instruction, Vol.1-7-9, Vol.2-3-440, Vol.3-6-20, Vol.3-22-20
IDT
64-bit mode, Vol.3-6-16
call interrupt & exception-handlers from, Vol.3-6-11
change base & limit in real-address mode, Vol.3-20-5
description of, Vol.3-6-9
handling NMIs during initialization, Vol.3-9-9
initializing protected-mode operation, Vol.3-9-10
initializing real-address mode operation, Vol.3-9-8
introduction to, Vol.3-2-5
limit, Vol.3-22-26
paging of, Vol.3-2-6
structure in real-address mode, Vol.3-20-5
task switching, Vol.3-7-10
task-gate descriptor, Vol.3-7-8
types of descriptors allowed, Vol.3-6-10
use in real-address mode, Vol.3-20-4
IDT (interrupt descriptor table), Vol.2-3-457, Vol.2-3-530
IDTR register, Vol.1-3-4, Vol.1-3-6
description of, Vol.3-2-12, Vol.3-6-9
IA-32e mode, Vol.3-2-12
introduction to, Vol.3-2-5
limit, Vol.3-5-5
loading in real-address mode, Vol.3-20-5
storing, Vol.3-3-16
IDTR (interrupt descriptor table register), Vol.2-3-530, Vol.2-4-626
IE (invalid operation exception) flag
MXCSR register, Vol.1-11-14
x87 FPU status word, Vol.1-8-5, Vol.1-8-27, Vol.3-22-8
IEEE Standard 754, Vol.1-4-4, Vol.1-4-11, Vol.1-8-1
IEEE Standard 754 for Binary Floating-Point Arithmetic, Vol.3-22-8,
Vol.3-22-9, Vol.3-22-12, Vol.3-22-13
IF (interrupt enable) flag
EFLAGS register, Vol.1-3-17, Vol.1-6-10, Vol.1-18-4, Vol.1-A-1,
Vol.3-2-10, Vol.3-2-11, Vol.3-6-6, Vol.3-6-10, Vol.3-6-14,
Vol.3-20-4, Vol.3-20-19, Vol.3-34-11
IF (interrupt enable) flag, EFLAGS register, Vol.2-3-143, Vol.2-4-645
IM (invalid operation exception) mask bit
Index-14 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
MXCSR register, Vol.1-11-14
x87 FPU control word, Vol.1-8-7
Immediate operands, Vol.1-3-20, Vol.2-2-3
IMUL instruction, Vol.1-7-9, Vol.2-3-443
IN instruction, Vol.1-5-7, Vol.1-7-20, Vol.1-18-3, Vol.2-3-447,
Vol.3-8-15, Vol.3-22-34, Vol.3-25-2
INC instruction, Vol.1-7-8, Vol.2-3-449, Vol.2-3-537, Vol.3-8-3
Indefinite
description of, Vol.1-4-17, Vol.1-14-18
floating-point format, Vol.1-4-5, Vol.1-4-13
integer, Vol.1-4-4, Vol.1-8-14
packed BCD integer, Vol.1-4-11
QNaN floating-point, Vol.1-4-17
Index field, segment selector, Vol.3-3-7
Index (operand addressing), Vol.1-3-22, Vol.1-3-23, Vol.1-3-24,
Vol.2-2-3
Inexact result (precision)
exception (#P), overview, Vol.1-4-22
exception (#P), SSE-SSE2 extensions, Vol.1-11-16
exception (#P), x87 FPU, Vol.1-8-31
on floating-point operations, Vol.1-4-18
Infinity control flag, x87 FPU control word, Vol.1-8-8
Infinity, floating-point format, Vol.1-4-5, Vol.1-4-15
INIT interrupt, Vol.3-10-3
INIT pin, Vol.1-3-15
Initial-count register, local APIC, Vol.3-10-16
Initialization
built-in self-test (BIST), Vol.3-9-1, Vol.3-9-5
CS register state following, Vol.3-9-5
EIP register state following, Vol.3-9-5
example, Vol.3-9-14
first instruction executed, Vol.3-9-5
hardware reset, Vol.3-9-1
IA-32e mode, Vol.3-9-11
IDT, protected mode, Vol.3-9-10
IDT, real-address mode, Vol.3-9-8
Intel486 SX processor and Intel 487 SX math coprocessor,
Vol.3-22-15
location of software-initialization code, Vol.3-9-5
machine-check initialization, Vol.3-15-18
model and stepping information, Vol.3-9-5
multitasking environment, Vol.3-9-10, Vol.3-9-11
overview, Vol.3-9-1
paging, Vol.3-9-10
processor state after reset, Vol.3-9-2
protected mode, Vol.3-9-9
real-address mode, Vol.3-9-8
RESET# pin, Vol.3-9-1
setting up exception- and interrupt-handling facilities, Vol.3-9-10
x87 FPU, Vol.3-9-5
Initialization x87 FPU, Vol.2-3-346
initiating logical processor, Vol.1-6-3, Vol.1-6-4, Vol.1-6-5, Vol.1-6-10,
Vol.1-6-21
INIT# pin, Vol.3-6-3, Vol.3-9-1
INIT# signal, Vol.3-2-24, Vol.3-23-4
Input/output (see I/O)
INS instruction, Vol.1-5-7, Vol.1-7-20, Vol.1-18-3, Vol.2-3-451,
Vol.2-4-550, Vol.3-17-9
INSB instruction, Vol.2-3-451
INSD instruction, Vol.2-3-451
INSERTPS- Insert Scalar Single-Precision Floating-Point Value, Vol.2-3-454
instruction encodings, Vol.1-B-60, Vol.1-B-66, Vol.1-B-73
Instruction format
base field, Vol.2-2-3
description of reference information, Vol.2-3-1
displacement, Vol.2-2-3
immediate, Vol.2-2-3
index field, Vol.2-2-3
Mod field, Vol.2-2-3
ModR/M byte, Vol.2-2-3
opcode, Vol.2-2-3
operands, Vol.2-1-5
INDEX
prefixes, Vol.2-2-1
reg/opcode field, Vol.2-2-3
r/m field, Vol.2-2-3
scale field, Vol.2-2-3
SIB byte, Vol.2-2-3
See also: machine instructions, opcodes
Instruction operands, Vol.1-1-6, Vol.3-1-7
Instruction pointer
64-bit mode, Vol.1-7-2
EIP register, Vol.1-3-11, Vol.1-3-18
RIP register, Vol.1-3-18
RIP, EIP, IP compared, Vol.1-3-10
x87 FPU, Vol.1-8-9
Instruction prefixes
effect on SSE and SSE2 instructions, Vol.1-11-25
REX prefix, Vol.1-3-2, Vol.1-3-12
Instruction reference, nomenclature, Vol.2-3-1
Instruction set
binary arithmetic instructions, Vol.1-7-8
bit scan instructions, Vol.1-7-14
bit test and modify instructions, Vol.1-7-14
byte-set-on-condition instructions, Vol.1-7-14
cacheability control instructions, Vol.1-5-16, Vol.1-5-20
comparison and sign change instruction, Vol.1-7-8
control transfer instructions, Vol.1-7-14
data movement instructions, Vol.1-7-2
decimal arithmetic instructions, Vol.1-7-9
EFLAGS cross-reference, Vol.1-A-1
EFLAGS instructions, Vol.1-7-21
exchange instructions, Vol.1-7-4
FXSAVE and FXRSTOR instructions, Vol.1-5-12
general-purpose instructions, Vol.1-5-3
grouped by processor, Vol.1-5-1, Vol.1-5-2
increment and decrement instructions, Vol.1-7-8
instruction ordering instructions, Vol.1-5-16, Vol.1-5-20
I/O instructions, Vol.1-5-7, Vol.1-7-20
logical instructions, Vol.1-7-10
MMX instructions, Vol.1-5-12, Vol.1-9-5
multiply and divide instructions, Vol.1-7-9
processor identification instruction, Vol.1-7-23
repeating string operations, Vol.1-7-19
rotate instructions, Vol.1-7-13
segment register instructions, Vol.1-7-22
shift instructions, Vol.1-7-10
SIMD instructions, introduction to, Vol.1-2-15
software interrupt instructions, Vol.1-7-17
SSE instructions, Vol.1-5-14
SSE2 instructions, Vol.1-5-17
stack manipulation instructions, Vol.1-7-5
string operation instructions, Vol.1-7-18
summary, Vol.1-5-1
system instructions, Vol.1-5-28, Vol.1-5-32
test instruction, Vol.1-7-14
type conversion instructions, Vol.1-7-7
x87 FPU and SIMD state management instructions, Vol.1-5-12
x87 FPU instructions, Vol.1-5-9
Instruction set, reference, Vol.2-3-1
Instruction-breakpoint exception condition, Vol.3-17-8
Instructions
new instructions, Vol.3-22-4
obsolete instructions, Vol.3-22-5
privileged, Vol.3-5-23
serializing, Vol.3-8-17, Vol.3-8-29, Vol.3-22-15
supported in real-address mode, Vol.3-20-3
system, Vol.3-2-7, Vol.3-2-20
INSW instruction, Vol.2-3-451
INS/INSB/INSW/INSD instruction, Vol.3-25-2
INT 3 instruction, Vol.2-3-457, Vol.3-2-5, Vol.3-6-23
INT instruction, Vol.1-6-13, Vol.1-7-23, Vol.3-2-5, Vol.3-5-10
INT n instruction, Vol.3-3-9, Vol.3-6-1, Vol.3-6-4, Vol.3-17-10
INT (APIC interrupt enable) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6
family processors), Vol.3-18-4, Vol.3-18-119
INT15 and microcode updates, Vol.3-9-42
INT3 instruction, Vol.3-3-9, Vol.3-6-4
Integers
description of, Vol.1-4-3
indefinite, Vol.1-4-4, Vol.1-8-14
signed integer encodings, Vol.1-4-4
signed, description of, Vol.1-4-4
unsigned integer encodings, Vol.1-4-3
unsigned, description of, Vol.1-4-3
Integer, storing, x87 FPU data type, Vol.2-3-348
Intel 287 math coprocessor, Vol.3-22-7
Intel 387 math coprocessor system, Vol.3-22-7
Intel 487 SX math coprocessor, Vol.3-22-6, Vol.3-22-15
Intel 64 architecture
64-bit mode, Vol.1-3-1
64-bit mode instructions, Vol.1-5-33
address space, Vol.1-3-6
compatibility mode, Vol.1-3-1
data types, Vol.1-4-1
definition of, Vol.1-1-3, Vol.2-1-3, Vol.3-1-3
executing calls, Vol.1-6-1
general purpose instructions, Vol.1-7-1
generations, Vol.1-2-21
history of, Vol.1-2-1
IA32e mode, Vol.1-3-1
instruction format, Vol.2-2-1
introduction, Vol.1-2-21
memory organization, Vol.1-3-6, Vol.1-3-8
relation to IA-32, Vol.1-1-3, Vol.2-1-3, Vol.3-1-3
See also: IA-32e mode
Intel 8086 processor, Vol.3-22-7
Intel Advanced Digital Media Boost, Vol.1-2-4, Vol.1-2-11
Intel Advanced Smart Cache, Vol.1-2-11
Intel Advanced Thermal Manager, Vol.1-2-4
Intel Core 2 Extreme processor family, Vol.1-2-4, Vol.1-2-5, Vol.1-2-19
Intel Core Duo processor, Vol.1-2-4, Vol.1-2-19
Intel Core microarchitecture, Vol.1-2-4, Vol.1-2-5, Vol.1-2-11,
Vol.1-2-13, Vol.1-2-14, Vol.1-2-19
Intel Core Solo and Duo processors
model-specific registers, Vol.1-35-303
Intel Core Solo and Intel Core Duo processors
event mask (Umask), Vol.3-18-16, Vol.3-18-17
last branch, interrupt, exception recording, Vol.3-17-35
notes on P-state transitions, Vol.3-14-1
performance monitoring, Vol.3-18-16, Vol.3-18-17
performance monitoring events, Vol.3-19-21, Vol.3-19-34,
Vol.3-19-43, Vol.3-19-57, Vol.3-19-117, Vol.3-19-118,
Vol.3-19-143, Vol.3-19-149, Vol.3-19-154
sub-fields layouts, Vol.3-18-16, Vol.3-18-17
time stamp counters, Vol.3-17-40
Intel Core Solo processor, Vol.1-2-4
Intel Dynamic Power Coordination, Vol.1-2-4
Intel NetBurst microarchitecture, Vol.1-1-2, Vol.2-1-2, Vol.3-1-2
description of, Vol.1-2-8
introduction, Vol.1-2-8
Intel Pentium D processor, Vol.1-2-19
Intel Pentium processor Extreme Edition, Vol.1-2-19
Intel Smart Cache, Vol.1-2-4
Intel Smart Memory Access, Vol.1-2-4, Vol.1-2-11
Intel software network link, Vol.1-1-8, Vol.2-1-8, Vol.3-1-10
Intel SpeedStep Technology
See: Enhanced Intel SpeedStep Technology
Intel Transactional Synchronization, Vol.1-15-3, Vol.1-16-1
Intel VTune Performance Analyzer
related information, Vol.1-1-8, Vol.2-1-8, Vol.3-1-9
Intel Wide Dynamic Execution, Vol.1-2-4, Vol.1-2-11, Vol.1-2-13,
Vol.1-2-14
Intel Xeon processor, Vol.1-1-1, Vol.2-1-1, Vol.3-1-1
description of, Vol.1-2-3
last branch, interrupt, and exception recording, Vol.3-17-32
time-stamp counter, Vol.3-17-40
Intel Xeon processor 5100 series, Vol.1-2-4, Vol.1-2-5, Vol.1-2-19
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -15
INDEX
Intel Xeon processor MP
with 8MB L3 cache, Vol.3-18-109, Vol.3-18-111
Intel286 processor, Vol.3-22-7
Intel386 DX processor, Vol.3-22-7
Intel386 processor, Vol.1-2-1
Intel386 SL processor, Vol.3-2-7
Intel486 DX processor, Vol.3-22-6
Intel486 processor
history of, Vol.1-2-2
Intel486 SX processor, Vol.3-22-6, Vol.3-22-15
Intel® Trusted Execution Technology, Vol.1-6-3
Inter-privilege level
call, CALL instruction, Vol.2-3-122
return, RET instruction, Vol.2-4-553
Inter-privilege level call
description of, Vol.1-6-6
operation, Vol.1-6-7
Interprivilege level calls
call mechanism, Vol.3-5-15
stack switching, Vol.3-5-17
Inter-privilege level return
description of, Vol.1-6-6
operation, Vol.1-6-7
Interprocessor interrupt (IPIs), Vol.3-10-1
Interprocessor interrupt (IPI)
in MP systems, Vol.3-10-1
interrupt, Vol.3-6-12
Interrupt Command Register, Vol.3-10-37
Interrupt command register (ICR), local APIC, Vol.3-10-18
Interrupt gate, Vol.1-6-10
Interrupt gates
16-bit, interlevel return from, Vol.3-22-32
clearing IF flag, Vol.3-6-7, Vol.3-6-14
difference between interrupt and trap gates, Vol.3-6-14
for 16-bit and 32-bit code modules, Vol.3-21-1
handling a virtual-8086 mode interrupt or exception through,
Vol.3-20-12
in IDT, Vol.3-6-10
introduction to, Vol.3-2-4, Vol.3-2-5
layout of, Vol.3-6-10
Interrupt handler, Vol.1-6-10
calling, Vol.3-6-11
defined, Vol.3-6-1
flag usage by handler procedure, Vol.3-6-14
procedures, Vol.3-6-11
protection of handler procedures, Vol.3-6-13
task, Vol.3-6-14, Vol.3-7-2
Interrupts
64-bit mode, Vol.1-6-14
automatic bus locking, Vol.3-22-34
control transfers between 16- and 32-bit code modules, Vol.3-21-6
description of, Vol.1-6-9, Vol.3-2-5, Vol.3-6-1
destination, Vol.3-10-26
distribution mechanism, local APIC, Vol.3-10-24
enabling and disabling, Vol.3-6-6
handler, Vol.1-6-10
handling, Vol.3-6-11
handling in real-address mode, Vol.3-20-4
handling in SMM, Vol.3-34-10
handling in virtual-8086 mode, Vol.3-20-11
handling multiple NMIs, Vol.3-6-6
handling through a task gate in virtual-8086 mode, Vol.3-20-14
handling through a trap or interrupt gate in virtual-8086 mode,
Vol.3-20-12
IA-32e mode, Vol.3-2-5, Vol.3-2-12
IDT, Vol.3-6-9
IDTR, Vol.3-2-12
implicit call to an interrupt handler
procedure, Vol.1-6-10
implicit call to an interrupt handler task, Vol.1-6-13
implicit call to interrupt handler procedure, Vol.1-6-10
implicit call to interrupt handler task, Vol.1-6-13
Index-16 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
in real-address mode, Vol.1-6-13
initializing for protected-mode operation, Vol.3-9-10
interrupt descriptor table register (see IDTR)
interrupt descriptor table (see IDT)
list of, Vol.3-6-2, Vol.3-20-6
local APIC, Vol.3-10-1
maskable, Vol.1-6-10
maskable hardware interrupts, Vol.3-2-10
masking maskable hardware interrupts, Vol.3-6-6
masking when switching stack segments, Vol.3-6-7
message signalled interrupts, Vol.3-10-34
on-die sensors for, Vol.3-14-19
overview of, Vol.3-6-1
priorities among simultaneous exceptions and interrupts, Vol.3-6-8
priority, Vol.3-10-28
propagation delay, Vol.3-22-26
real-address mode, Vol.3-20-6
restarting a task or program, Vol.3-6-5
returning from, Vol.2-3-476
software, Vol.2-3-457, Vol.3-6-51
sources of, Vol.3-10-1
summary of, Vol.3-6-2
thermal monitoring, Vol.3-14-19
user defined, Vol.3-6-1, Vol.3-6-51
valid APIC interrupts, Vol.3-10-14
vectors, Vol.3-6-1
virtual-8086 mode, Vol.3-20-6
INTn instruction, Vol.1-7-17, Vol.2-3-457
INTO instruction, Vol.1-6-13, Vol.1-7-18, Vol.1-7-23, Vol.2-3-457,
Vol.3-2-5, Vol.3-3-9, Vol.3-6-4, Vol.3-6-24, Vol.3-17-10
Intrinsics
compiler functional equivalents, Vol.1-C-1
composite, Vol.1-C-14
description of, Vol.2-3-12
list of, Vol.1-C-1
simple, Vol.1-C-2
INTR# pin, Vol.3-6-2, Vol.3-6-6
Invalid arithmetic operand exception (#IA)
description of, Vol.1-8-27
masked response to, Vol.1-8-28
Invalid opcode exception (#UD), Vol.3-2-16, Vol.3-6-26, Vol.3-6-48,
Vol.3-12-1, Vol.3-17-3, Vol.3-22-5, Vol.3-22-10, Vol.3-22-19,
Vol.3-22-20, Vol.3-34-3
Invalid operation exception (#I)
overview, Vol.1-4-20
SSE and SSE2 extensions, Vol.1-11-14
x87 FPU, Vol.1-8-27
Invalid TSS exception (#TS), Vol.3-6-31, Vol.3-7-6
Invalid-operation exception, x87 FPU, Vol.3-22-11, Vol.3-22-13
INVD instruction, Vol.2-3-469, Vol.3-2-23, Vol.3-5-24, Vol.3-11-17,
Vol.3-22-4
INVLPG instruction, Vol.2-3-471, Vol.3-2-23, Vol.3-5-24, Vol.3-22-4,
Vol.3-25-2, Vol.3-32-3, Vol.3-32-4
IOPL (I/O privilege level) field
EFLAGS register, Vol.1-3-17, Vol.1-18-3
IOPL (I/O privilege level) field, EFLAGS register, Vol.2-3-143, Vol.2-4-516,
Vol.2-4-645
description of, Vol.3-2-10
on return from exception, interrupt handler, Vol.3-6-13
sensitive instructions in virtual-8086 mode, Vol.3-20-10
virtual interrupt, Vol.3-2-11
IPI (see interprocessor interrupt)
IRET instruction, Vol.1-3-18, Vol.1-6-12, Vol.1-6-13, Vol.1-7-15,
Vol.1-7-23, Vol.1-18-4, Vol.2-3-476, Vol.3-3-9, Vol.3-6-7,
Vol.3-6-13, Vol.3-6-14, Vol.3-6-18, Vol.3-7-10, Vol.3-8-17,
Vol.3-20-5, Vol.3-20-19, Vol.3-25-7
IRETD instruction, Vol.2-3-476, Vol.3-2-10, Vol.3-8-17
IRR
Interrupt Request Register, Vol.3-10-39, Vol.3-10-41, Vol.3-10-47
IRR (interrupt request register), local APIC, Vol.3-10-29
ISR
In Service Register, Vol.3-10-38, Vol.3-10-41, Vol.3-10-47
INDEX
I/O
address space, Vol.1-18-1
breakpoint exception conditions, Vol.3-17-9
in virtual-8086 mode, Vol.3-20-10
instruction restart flag
SMM revision identifier field, Vol.3-34-15
instruction restart flag, SMM revision identifier field, Vol.3-34-15
instruction serialization, Vol.1-18-5
instructions, Vol.1-5-7, Vol.1-7-20, Vol.1-18-3
IO_SMI bit, Vol.3-34-12
I/O permission bit map, TSS, Vol.3-7-5
I/O privilege level (see IOPL)
map base, Vol.1-18-4
map base address field, TSS, Vol.3-7-5
permission bit map, Vol.1-18-4
ports, Vol.1-3-4, Vol.1-18-1, Vol.1-18-2, Vol.1-18-3, Vol.1-18-5
restarting following SMI interrupt, Vol.3-34-15
saving I/O state, Vol.3-34-12
sensitive instructions, Vol.1-18-3
SMM state save map, Vol.3-34-12
I/O APIC, Vol.3-10-26
bus arbitration, Vol.3-10-25
description of, Vol.3-10-1
external interrupts, Vol.3-6-3
information about, Vol.3-10-1
interrupt sources, Vol.3-10-2
local APIC and I/O APIC, Vol.3-10-2, Vol.3-10-3
overview of, Vol.3-10-1
valid interrupts, Vol.3-10-14
See also: local APIC
J
J-bit, Vol.1-4-11
Jcc instructions, Vol.1-3-17, Vol.1-3-18, Vol.1-7-15, Vol.2-3-483
JMP instruction, Vol.1-3-18, Vol.1-7-15, Vol.1-7-22, Vol.2-3-488,
Vol.3-2-5, Vol.3-3-9, Vol.3-5-10, Vol.3-5-15, Vol.3-7-2,
Vol.3-7-9, Vol.3-7-10
Jump operation, Vol.2-3-488
K
KEN# pin, Vol.3-11-13, Vol.3-22-35
L
L0-L3 (local breakpoint enable) flags
DR7 register, Vol.3-17-4
L1 Context ID, Vol.2-3-207
L1 (level 1) cache, Vol.1-2-8, Vol.1-2-10
caching methods, Vol.3-11-6
CPUID feature flag, Vol.3-11-18
description of, Vol.3-11-4
effect of using write-through memory, Vol.3-11-8
introduction of, Vol.3-22-29
invalidating and flushing, Vol.3-11-17
MESI cache protocol, Vol.3-11-9
shared and adaptive mode, Vol.3-11-18
L2 (level 2) cache, Vol.1-2-8, Vol.1-2-10
caching methods, Vol.3-11-6
description of, Vol.3-11-4
disabling, Vol.3-11-17
effect of using write-through memory, Vol.3-11-8
introduction of, Vol.3-22-29
invalidating and flushing, Vol.3-11-17
MESI cache protocol, Vol.3-11-9
L3 (level 3) cache
caching methods, Vol.3-11-6
description of, Vol.3-11-4
disabling and enabling, Vol.3-11-13, Vol.3-11-17
effect of using write-through memory, Vol.3-11-8
introduction of, Vol.3-22-30
invalidating and flushing, Vol.3-11-17
MESI cache protocol, Vol.3-11-9
LAHF instruction, Vol.1-3-15, Vol.1-7-21, Vol.2-3-514
LAR instruction, Vol.2-3-515, Vol.3-2-23, Vol.3-5-24
Larger page sizes
introduction of, Vol.3-22-30
support for, Vol.3-22-18
Last branch
interrupt & exception recording
description of, Vol.2-4-565, Vol.3-17-11, Vol.3-17-25,
Vol.3-17-27, Vol.3-17-29, Vol.3-17-31, Vol.3-17-33,
Vol.3-17-35, Vol.3-17-37, Vol.3-17-38
record stack, Vol.3-17-16, Vol.3-17-17, Vol.3-17-25, Vol.3-17-26,
Vol.3-17-32, Vol.3-17-34, Vol.3-17-36, Vol.3-17-38,
Vol.1-35-289, Vol.1-35-299
record top-of-stack pointer, Vol.3-17-16, Vol.3-17-26, Vol.3-17-32,
Vol.3-17-36, Vol.3-17-38
Last instruction opcode, x87 FPU, Vol.1-8-10
LastBranchFromIP MSR, Vol.3-17-39
LastBranchToIP MSR, Vol.3-17-39
LastExceptionFromIP MSR, Vol.3-17-35, Vol.3-17-36, Vol.3-17-39
LastExceptionToIP MSR, Vol.3-17-35, Vol.3-17-36, Vol.3-17-39
LBR (last branch/interrupt/exception) flag, DEBUGCTLMSR MSR,
Vol.3-17-12, Vol.3-17-33, Vol.3-17-38, Vol.3-17-39
LDDQU instruction, Vol.1-5-20, Vol.1-12-3, Vol.2-3-518
LDMXCSR instruction, Vol.1-10-12, Vol.1-11-24, Vol.2-3-520,
Vol.2-4-530, Vol.2-5-570
LDR
Logical Destination Register, Vol.3-10-41, Vol.3-10-45, Vol.3-10-46
LDS instruction, Vol.1-7-23, Vol.2-3-521, Vol.3-3-8, Vol.3-5-8
LDT
associated with a task, Vol.3-7-3
description of, Vol.3-2-3, Vol.3-2-5, Vol.3-3-15
index into with index field of segment selector, Vol.3-3-7
pointer to in TSS, Vol.3-7-4
pointers to exception and interrupt handlers, Vol.3-6-11
segment descriptors in, Vol.3-3-9
segment selector field, TSS, Vol.3-7-14
selecting with TI (table indicator) flag of segment selector, Vol.3-3-7
setting up during initialization, Vol.3-9-10
task switching, Vol.3-7-9
task-gate descriptor, Vol.3-7-8
use in address translation, Vol.3-3-6
LDT (local descriptor table), Vol.2-3-533
LDTR register, Vol.1-3-4, Vol.1-3-6
description of, Vol.3-2-3, Vol.3-2-5, Vol.3-2-6, Vol.3-2-12, Vol.3-3-15
IA-32e mode, Vol.3-2-12
limit, Vol.3-5-5
storing, Vol.3-3-16
LDTR (local descriptor table register), Vol.2-3-533, Vol.2-4-628
LE (local exact breakpoint enable) flag, DR7 register, Vol.3-17-4,
Vol.3-17-9
LEA instruction, Vol.1-7-23, Vol.2-3-525
LEAVE instruction, Vol.1-6-14, Vol.1-6-19, Vol.1-7-21, Vol.2-3-527
LEN0-LEN3 (Length) fields, DR7 register, Vol.3-17-4, Vol.3-17-5
LES instruction, Vol.1-7-23, Vol.2-3-521, Vol.3-3-8, Vol.3-5-8,
Vol.3-6-26
LFENCE instruction, Vol.1-11-12, Vol.2-3-529, Vol.3-2-15, Vol.3-8-6,
Vol.3-8-15, Vol.3-8-16, Vol.3-8-17
LFS instruction, Vol.2-3-521, Vol.3-3-8, Vol.3-5-8
LGDT instruction, Vol.2-3-530, Vol.3-2-22, Vol.3-5-23, Vol.3-8-17,
Vol.3-9-10, Vol.3-22-19
LGS instruction, Vol.1-7-23, Vol.2-3-521, Vol.3-3-8, Vol.3-5-8
LIDT instruction, Vol.2-3-530, Vol.3-2-22, Vol.3-5-24, Vol.3-6-9,
Vol.3-8-17, Vol.3-9-9, Vol.3-20-5, Vol.3-22-26
Limit checking
description of, Vol.3-5-4
pointer offsets are within limits, Vol.3-5-25
Limit field, segment descriptor, Vol.3-5-2, Vol.3-5-4
Linear address, Vol.1-3-7
description of, Vol.3-3-6
IA-32e mode, Vol.3-3-7
introduction to, Vol.3-2-6
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -17
INDEX
Linear address space, Vol.3-3-6
defined, Vol.1-3-7, Vol.3-3-1
maximum size, Vol.1-3-7
of task, Vol.3-7-14
Link (to previous task) field, TSS, Vol.3-6-14
Linking tasks
mechanism, Vol.3-7-12
modifying task linkages, Vol.3-7-13
LINT pins
function of, Vol.3-6-2
LLDT instruction, Vol.2-3-533, Vol.3-2-22, Vol.3-5-23, Vol.3-8-17
LMSW instruction, Vol.2-3-535, Vol.3-2-22, Vol.3-5-24, Vol.3-25-3,
Vol.3-25-7
Load effective address operation, Vol.2-3-525
Local APIC, Vol.3-10-38
64-bit mode, Vol.3-10-31
APIC_ID value, Vol.3-8-33
arbitration over the APIC bus, Vol.3-10-26
arbitration over the system bus, Vol.3-10-25
block diagram, Vol.3-10-4
cluster model, Vol.3-10-24
CR8 usage, Vol.3-10-31
current-count register, Vol.3-10-16
description of, Vol.3-10-1
detecting with CPUID, Vol.3-10-7
DFR (destination format register), Vol.3-10-23
divide configuration register, Vol.3-10-16
enabling and disabling, Vol.3-10-8
external interrupts, Vol.3-6-2
features
Pentium 4 and Intel Xeon, Vol.3-22-27
Pentium and P6, Vol.3-22-27
focus processor, Vol.3-10-25
global enable flag, Vol.3-10-8
IA32_APIC_BASE MSR, Vol.3-10-8
initial-count register, Vol.3-10-16
internal error interrupts, Vol.3-10-2
interrupt command register (ICR), Vol.3-10-18
interrupt destination, Vol.3-10-26
interrupt distribution mechanism, Vol.3-10-24
interrupt sources, Vol.3-10-2
IRR (interrupt request register), Vol.3-10-29
I/O APIC, Vol.3-10-1
local APIC and 82489DX, Vol.3-22-27
local APIC and I/O APIC, Vol.3-10-2, Vol.3-10-3
local vector table (LVT), Vol.3-10-12
logical destination mode, Vol.3-10-23
LVT (local-APIC version register), Vol.3-10-11
mapping of resources, Vol.3-8-33
MDA (message destination address), Vol.3-10-23
overview of, Vol.3-10-1
performance-monitoring counter, Vol.3-18-120
physical destination mode, Vol.3-10-22
receiving external interrupts, Vol.3-6-2
register address map, Vol.3-10-6, Vol.3-10-38
shared resources, Vol.3-8-33
SMI interrupt, Vol.3-34-2
spurious interrupt, Vol.3-10-32
spurious-interrupt vector register, Vol.3-10-8
state after a software (INIT) reset, Vol.3-10-10
state after INIT-deassert message, Vol.3-10-11
state after power-up reset, Vol.3-10-10
state of, Vol.3-10-32
SVR (spurious-interrupt vector register), Vol.3-10-8
timer, Vol.3-10-16
timer generated interrupts, Vol.3-10-1
TMR (trigger mode register), Vol.3-10-29
valid interrupts, Vol.3-10-14
version register, Vol.3-10-11
Local descriptor table register (see LDTR)
Local descriptor table (see LDT)
Local vector table (LVT)
Index-18 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
description of, Vol.3-10-12
thermal entry, Vol.3-14-22
Local x2APIC, Vol.3-10-31, Vol.3-10-41, Vol.3-10-46
Local xAPIC ID, Vol.3-10-41
LOCK prefix, Vol.2-3-27, Vol.2-3-32, Vol.2-3-61, Vol.2-3-115,
Vol.2-3-117, Vol.2-3-119, Vol.2-3-181, Vol.2-3-283,
Vol.2-3-449, Vol.2-3-537, Vol.2-4-161, Vol.2-4-164,
Vol.2-4-166, Vol.2-4-590, Vol.2-4-655, Vol.2-5-581,
Vol.2-5-586, Vol.2-5-594, Vol.3-2-24, Vol.3-6-26, Vol.3-8-1,
Vol.3-8-3, Vol.3-8-15, Vol.3-22-34
LOCK signal, Vol.1-7-4
Locked (atomic) operations
automatic bus locking, Vol.3-8-3
bus locking, Vol.3-8-3
effects on caches, Vol.3-8-5
loading a segment descriptor, Vol.3-22-19
on IA-32 processors, Vol.3-22-34
overview of, Vol.3-8-1
software-controlled bus locking, Vol.3-8-3
Locking operation, Vol.2-3-537
LOCK# signal, Vol.3-2-24, Vol.3-8-1, Vol.3-8-3, Vol.3-8-4, Vol.3-8-5
LODS instruction, Vol.1-3-17, Vol.1-7-18, Vol.2-3-539, Vol.2-4-550
LODSB instruction, Vol.2-3-539
LODSD instruction, Vol.2-3-539
LODSQ instruction, Vol.2-3-539
LODSW instruction, Vol.2-3-539
Log epsilon, x87 FPU operation, Vol.1-8-22, Vol.2-3-423
Log (base 2), x87 FPU operation, Vol.2-3-425
Logical address, Vol.1-3-7
description of, Vol.3-3-6
IA-32e mode, Vol.3-3-7
Logical address space, of task, Vol.3-7-15
Logical destination mode, local APIC, Vol.3-10-23
Logical processors
per physical package, Vol.3-8-24
Logical x2APIC ID, Vol.3-10-46
LOOP instructions, Vol.1-7-16, Vol.2-3-542
LOOPcc instructions, Vol.1-3-17, Vol.1-7-16, Vol.2-3-542
low-temperature interrupt enable bit, Vol.3-14-27, Vol.3-14-30
LSL instruction, Vol.2-3-544, Vol.3-2-23, Vol.3-5-25
LSS instruction, Vol.1-7-23, Vol.2-3-521, Vol.3-3-8, Vol.3-5-8
LTR instruction, Vol.2-3-547, Vol.3-2-22, Vol.3-5-24, Vol.3-7-7,
Vol.3-8-17, Vol.3-9-11
LVT (see Local vector table)
LZCNT - Count the Number of Leading Zero Bits, Vol.2-3-549
M
Machine check architecture
CPUID flag, Vol.2-3-209
description, Vol.2-3-209
VMX considerations, Vol.3-33-11
Machine check registers, Vol.1-3-4
Machine instructions
64-bit mode, Vol.1-B-1
condition test (tttn) field, Vol.1-B-6
direction bit (d) field, Vol.1-B-6
floating-point instruction encodings, Vol.1-B-64
general description, Vol.1-B-1
general-purpose encodings, Vol.1-B-7–Vol.1-B-37
legacy prefixes, Vol.1-B-1
MMX encodings, Vol.1-B-38–Vol.1-B-41
opcode fields, Vol.1-B-2
operand size (w) bit, Vol.1-B-4
P6 family encodings, Vol.1-B-41
Pentium processor family encodings, Vol.1-B-37
reg (reg) field, Vol.1-B-3, Vol.1-B-4
REX prefixes, Vol.1-B-2
segment register (sreg) field, Vol.1-B-5
sign-extend (s) bit, Vol.1-B-5
SIMD 64-bit encodings, Vol.1-B-37
special 64-bit encodings, Vol.1-B-64
INDEX
special fields, Vol.1-B-2
special-purpose register (eee) field, Vol.1-B-5
SSE encodings, Vol.1-B-42–Vol.1-B-48
SSE2 encodings, Vol.1-B-48–Vol.1-B-58
SSE3 encodings, Vol.1-B-59–Vol.1-B-60
SSSE3 encodings, Vol.1-B-60–Vol.1-B-63
VMX encodings, Vol.1-B-117, Vol.1-B-118
See also: opcodes
Machine specific registers (see MSRs)
Machine status word, CR0 register, Vol.2-3-535, Vol.2-4-630
Machine-check architecture
availability of MCA and exception, Vol.3-15-18
compatibility with Pentium processor, Vol.3-15-1
compound error codes, Vol.3-15-20
CPUID flags, Vol.3-15-18
error codes, Vol.3-15-20
error-reporting bank registers, Vol.3-15-2
error-reporting MSRs, Vol.3-15-5
extended machine check state MSRs, Vol.3-15-11
external bus errors, Vol.3-15-26
first introduced, Vol.3-22-21
global MSRs, Vol.3-15-2
initialization of, Vol.3-15-18
introduction of in IA-32 processors, Vol.3-22-35
logging correctable errors, Vol.3-15-28, Vol.3-15-30, Vol.3-15-34
machine-check exception handler, Vol.3-15-27
machine-check exception (#MC), Vol.3-15-1
MSRs, Vol.3-15-2
overview of MCA, Vol.3-15-1
Pentium processor exception handling, Vol.3-15-28
Pentium processor style error reporting, Vol.3-15-12
simple error codes, Vol.3-15-20
VMX considerations, Vol.3-33-8, Vol.3-33-9
writing machine-check software, Vol.3-15-26
Machine-check exception (#MC), Vol.3-6-47, Vol.3-15-1, Vol.3-15-18,
Vol.3-15-27, Vol.3-22-20, Vol.3-22-35
Mapping of shared resources, Vol.3-8-33
Maskable hardware interrupts
description of, Vol.3-6-3
handling with virtual interrupt mechanism, Vol.3-20-15
masking, Vol.3-2-10, Vol.3-6-6
Maskable interrupts, Vol.1-6-10
Masked responses
denormal operand exception (#D), Vol.1-4-20, Vol.1-8-29
divide by zero exception (#Z), Vol.1-4-20, Vol.1-8-29
inexact result (precision) exception (#P), Vol.1-4-22, Vol.1-8-31
invalid arithmetic operation (#IA), Vol.1-8-28
invalid operation exception (#I), Vol.1-4-20
numeric overflow exception (#O), Vol.1-4-21, Vol.1-8-29
numeric underflow exception (#U), Vol.1-4-22, Vol.1-8-30
stack overflow or underflow
exception (#IS), Vol.1-8-27
MASKMOVDQU instruction, Vol.1-11-12, Vol.1-11-25, Vol.2-4-43
MASKMOVQ instruction, Vol.1-10-12, Vol.1-11-25, Vol.2-5-318
Masks, exception-flags
MXCSR register, Vol.1-10-4
x87 FPU control word, Vol.1-8-7
MAXPD instruction, Vol.1-11-6
MAXPD- Maximum of Packed Double-Precision Floating-Point Values,
Vol.2-4-12
MAXPS instruction, Vol.1-10-8
MAXPS- Maximum of Packed Single-Precision Floating-Point Values,
Vol.2-4-15
MAXSD instruction, Vol.1-11-6
MAXSD- Return Maximum Scalar Double-Precision Floating-Point Value,
Vol.1-15-3, Vol.2-4-18
MAXSS instruction, Vol.1-10-9
MAXSS- Return Maximum Scalar Single-Precision Floating-Point Value,
Vol.2-4-20
MCA flag, CPUID instruction, Vol.3-15-18
MCE flag, CPUID instruction, Vol.3-15-18
MCE (machine-check enable) flag
CR4 control register, Vol.3-2-17, Vol.3-22-17
MDA (message destination address)
local APIC, Vol.3-10-23
measured environment, Vol.1-6-1
Measured Launched Environment, Vol.1-6-1, Vol.1-6-25
Memory, Vol.3-11-1
flat memory model, Vol.1-3-7
management registers, Vol.1-3-4
memory type range registers (MTRRs), Vol.1-3-4
modes of operation, Vol.1-3-9
organization, Vol.1-3-6, Vol.1-3-7
physical, Vol.1-3-6
real address mode memory model, Vol.1-3-7, Vol.1-3-8
segmented memory model, Vol.1-3-7
virtual-8086 mode memory model, Vol.1-3-7, Vol.1-3-8
Memory management
introduction to, Vol.3-2-6
overview, Vol.3-3-1
paging, Vol.3-3-1, Vol.3-3-2
registers, Vol.3-2-11
segments, Vol.3-3-1, Vol.3-3-2, Vol.3-3-7
virtualization of, Vol.3-32-2
Memory operands
64-bit mode, Vol.1-3-21
legacy modes, Vol.1-3-21
Memory ordering
in IA-32 processors, Vol.3-22-33
overview, Vol.3-8-5
processor ordering, Vol.3-8-5
strengthening or weakening, Vol.3-8-15
write ordering, Vol.3-8-5
Memory type range registers (see MTRRs)
Memory types
caching methods, defined, Vol.3-11-6
choosing, Vol.3-11-8
MTRR types, Vol.3-11-21
selecting for Pentium III and Pentium 4 processors, Vol.3-11-15
selecting for Pentium Pro and Pentium II processors, Vol.3-11-14
UC (strong uncacheable), Vol.3-11-6
UC- (uncacheable), Vol.3-11-6
WB (write back), Vol.3-11-7
WC (write combining), Vol.3-11-7
WP (write protected), Vol.3-11-7
writing values across pages with different memory types, Vol.3-11-16
WT (write through), Vol.3-11-7
Memory-mapped I/O, Vol.1-18-2
MemTypeGet() function, Vol.3-11-29
MemTypeSet() function, Vol.3-11-31
MESI cache protocol, Vol.3-11-5, Vol.3-11-9
Message address register, Vol.3-10-34
Message data register format, Vol.3-10-35
Message signalled interrupts
message address register, Vol.3-10-34
message data register format, Vol.3-10-34
MFENCE instruction, Vol.1-11-12, Vol.1-11-25, Vol.2-4-22, Vol.3-2-15,
Vol.3-8-6, Vol.3-8-15, Vol.3-8-16, Vol.3-8-17
Microarchitecture
(see Intel NetBurst microarchitecture)
(see P6 family microarchitecture)
Microcode update facilities
authenticating an update, Vol.3-9-37
BIOS responsibilities, Vol.3-9-38
calling program responsibilities, Vol.3-9-39
checksum, Vol.3-9-33
extended signature table, Vol.3-9-31
family 0FH processors, Vol.3-9-28
field definitions, Vol.3-9-28
format of update, Vol.3-9-28
function 00H presence test, Vol.3-9-42
function 01H write microcode update data, Vol.3-9-43
function 02H microcode update control, Vol.3-9-46
function 03H read microcode update data, Vol.3-9-47
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -19
INDEX
general description, Vol.3-9-28
HT Technology, Vol.3-9-35
INT 15H-based interface, Vol.3-9-42
overview, Vol.3-9-27
process description, Vol.3-9-28
processor identification, Vol.3-9-32
processor signature, Vol.3-9-32
return codes, Vol.3-9-48
update loader, Vol.3-9-34
update signature and verification, Vol.3-9-36
update specifications, Vol.3-9-37
VMX non-root operation, Vol.3-25-9, Vol.3-32-8
VMX support
early loading, Vol.3-32-8
late loading, Vol.3-32-8
virtualization issues, Vol.3-32-8
MINPD instruction, Vol.1-11-6
MINPD- Minimum of Packed Double-Precision Floating-Point Values,
Vol.2-4-23
MINPS instruction, Vol.1-10-9
MINPS- Minimum of Packed Single-Precision Floating-Point Values,
Vol.2-4-26
MINSD instruction, Vol.1-11-7
MINSD- Return Minimum Scalar Double-Precision Floating-Point Value,
Vol.2-4-29
MINSS instruction, Vol.1-10-9
MINSS- Return Minimum Scalar Single-Precision Floating-Point Value,
Vol.2-4-31
Mixing 16-bit and 32-bit code
in IA-32 processors, Vol.3-22-32
overview, Vol.3-21-1
MLE, Vol.1-6-1
MMX instruction set
arithmetic instructions, Vol.1-9-6
comparison instructions, Vol.1-9-7
conversion instructions, Vol.1-9-7
data transfer instructions, Vol.1-9-6
EMMS instruction, Vol.1-9-8
logical instructions, Vol.1-9-7
overview, Vol.1-9-5
shift instructions, Vol.1-9-8
MMX instructions
CPUID flag for technology, Vol.2-3-210
encodings, Vol.1-B-38
MMX registers
description of, Vol.1-9-2
overview of, Vol.1-3-2
MMX technology
64-bit mode, Vol.1-9-2
64-bit packed SIMD data types, Vol.1-4-8
compatibility mode, Vol.1-9-2
compatibility with FPU architecture, Vol.1-9-8
data types, Vol.1-9-3
debugging MMX code, Vol.3-12-5
detecting MMX technology with CPUID instruction, Vol.1-9-8
effect of instruction prefixes on MMX instructions, Vol.1-9-11
effect of MMX instructions on pending x87 floating-point exceptions,
Vol.3-12-5
emulation of the MMX instruction set, Vol.3-12-1
exception handling in MMX code, Vol.1-9-11
exceptions that can occur when executing MMX instructions,
Vol.3-12-1
IA-32e mode, Vol.1-9-2
instruction set, Vol.1-5-12, Vol.1-9-5
interfacing with MMX code, Vol.1-9-10
introduction of into the IA-32 architecture, Vol.3-22-2
introduction to, Vol.1-9-1
memory data formats, Vol.1-9-3
mixing MMX and floating-point instructions, Vol.1-9-10
MMX registers, Vol.1-9-2
programming environment (overview), Vol.1-9-1
register aliasing, Vol.3-12-1
Index-20 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
register mapping, Vol.1-9-11
saturation arithmetic, Vol.1-9-4
SIMD execution environment, Vol.1-9-4
state, Vol.3-12-1
state, saving and restoring, Vol.3-12-3
system programming, Vol.3-12-1
task or context switches, Vol.3-12-4
transitions between x87 FPU - MMX code, Vol.1-9-9
updating MMX technology routines using 128-bit SIMD integer
instructions, Vol.1-11-24
using MMX code in a multitasking operating system environment,
Vol.1-9-10
using the EMMS instruction, Vol.1-9-9
using TS flag to control saving of MMX state, Vol.3-13-7
wraparound mode, Vol.1-9-4
Mod field, instruction format, Vol.2-2-3
Mode switching
example, Vol.3-9-14
real-address and protected mode, Vol.3-9-13
to SMM, Vol.3-34-2
Model and stepping information, following processor initialization or reset
, Vol.3-9-5
Model & family information, Vol.2-3-214
Model-specific registers (see MSRs)
Modes of operation
64-bit mode, Vol.1-3-1
compatibility mode, Vol.1-3-1
memory models used with, Vol.1-3-9
overview, Vol.1-3-1, Vol.1-3-5
protected mode, Vol.1-3-1
real address mode, Vol.1-3-1
system management mode (SMM), Vol.1-3-1
Modes of operation (see Operating modes)
ModR/M byte, Vol.2-2-3
16-bit addressing forms, Vol.2-2-5
32-bit addressing forms of, Vol.2-2-6
description of, Vol.2-2-3
MONITOR instruction, Vol.1-5-21, Vol.1-12-5, Vol.2-4-33, Vol.3-25-3
CPUID flag, Vol.2-3-206
feature data, Vol.2-3-214
Moore’s law, Vol.1-2-21
MOV instruction, Vol.1-7-3, Vol.1-7-22, Vol.2-4-35, Vol.3-3-8, Vol.3-5-8
MOV instruction (control registers), Vol.2-4-40
MOV instruction (debug registers), Vol.2-4-43, Vol.2-4-53
MOV (control registers) instructions, Vol.3-2-22, Vol.3-5-24, Vol.3-8-17,
Vol.3-9-13
MOV (debug registers) instructions, Vol.3-2-23, Vol.3-5-24, Vol.3-8-17,
Vol.3-17-9
MOVAPD instruction, Vol.1-11-5, Vol.1-11-23
MOVAPD- Move Aligned Packed Double-Precision Floating-Point Values,
Vol.2-4-45
MOVAPS instruction, Vol.1-10-7, Vol.1-11-23
MOVAPS- Move Aligned Packed Single-Precision Floating-Point Values,
Vol.2-4-49
MOVD instruction, Vol.1-9-6, Vol.2-4-53
MOVDDUP instruction, Vol.1-5-21, Vol.1-12-3
MOVDDUP- Replicate Double FP Values, Vol.2-4-59
MOVDQ2Q instruction, Vol.1-11-11, Vol.2-4-75
MOVDQA instruction, Vol.1-11-11, Vol.1-11-23
MOVDQA- Move Aligned Packed Integer Values, Vol.2-4-62
MOVDQU instruction, Vol.1-11-11, Vol.1-11-23
MOVDQU- Move Unaligned Packed Integer Values, Vol.2-4-67
MOVHLPS - Move Packed Single-Precision Floating-Point Values High to
Low, Vol.2-4-76
MOVHLPS instruction, Vol.1-10-8
MOVHPD instruction, Vol.1-11-6
MOVHPD- Move High Packed Double-Precision Floating-Point Values,
Vol.2-4-78
MOVHPS instruction, Vol.1-10-8
MOVHPS- Move High Packed Single-Precision Floating-Point Values,
Vol.2-4-80
MOVLHPS instruction, Vol.1-10-8
INDEX
MOVLPD instruction, Vol.1-11-6
MOVLPD- Move Low Packed Double-Precision Floating-Point Values,
Vol.2-4-84
MOVLPS instruction, Vol.1-10-7
MOVLPS- Move Low Packed Single-Precision Floating-Point Values,
Vol.2-4-86
MOVMSKPD instruction, Vol.1-11-6, Vol.2-4-88
MOVMSKPS instruction, Vol.1-10-8, Vol.2-4-90
MOVNTDQ instruction, Vol.1-11-12, Vol.1-11-25, Vol.2-4-106, Vol.3-8-6,
Vol.3-11-17
MOVNTDQ- Store Packed Integers Using Non-Temporal Hint, Vol.2-4-94
MOVNTI instruction, Vol.1-11-12, Vol.1-11-25, Vol.2-4-106, Vol.3-2-15,
Vol.3-8-6, Vol.3-11-17
MOVNTPD instruction, Vol.1-11-12, Vol.1-11-25, Vol.3-8-6, Vol.3-11-17
MOVNTPD- Store Packed Double-Precision Floating-Point Values Using
Non-Temporal Hint, Vol.2-4-98
MOVNTPS instruction, Vol.1-10-12, Vol.1-11-25, Vol.3-8-6, Vol.3-11-17
MOVNTPS- Store Packed Single-Precision Floating-Point Values Using
Non-Temporal Hint, Vol.2-4-100
MOVNTQ instruction, Vol.1-10-12, Vol.1-11-25, Vol.2-4-102, Vol.3-8-6,
Vol.3-11-17
MOVQ instruction, Vol.1-9-6, Vol.2-4-53, Vol.2-4-103
MOVQ2DQ instruction, Vol.1-11-11, Vol.2-4-106
MOVS instruction, Vol.1-3-17, Vol.1-7-18, Vol.2-4-107, Vol.2-4-550
MOVSB instruction, Vol.2-4-107
MOVSD instruction, Vol.1-11-6, Vol.1-11-23, Vol.2-4-107
MOVSD- Move or Merge Scalar Double-Precision Floating-Point Value,
Vol.2-4-111
MOVSHDUP instruction, Vol.1-5-21, Vol.1-12-3
MOVSHDUP- Replicate Single FP Values, Vol.2-4-114
MOVSLDUP instruction, Vol.1-5-21, Vol.1-12-3
MOVSLDUP- Replicate Single FP Values, Vol.2-4-117
MOVSQ instruction, Vol.2-4-107
MOVSS instruction, Vol.1-10-7, Vol.1-11-23
MOVSS- Move or Merge Scalar Single-Precision Floating-Point Value,
Vol.2-4-120
MOVSW instruction, Vol.2-4-107
MOVSX instruction, Vol.1-7-8, Vol.2-4-124
MOVSXD instruction, Vol.1-7-8, Vol.2-4-124
MOVUPD instruction, Vol.1-11-6, Vol.1-11-23
MOVUPD- Move Unaligned Packed Double-Precision Floating-Point Values,
Vol.2-4-126
MOVUPS instruction, Vol.1-10-6, Vol.1-10-7, Vol.1-11-23
MOVUPS- Move Unaligned Packed Single-Precision Floating-Point Values,
Vol.2-4-130
MOVZX instruction, Vol.1-7-8, Vol.2-4-134
MP (monitor coprocessor) flag
CR0 control register, Vol.3-2-15, Vol.3-2-16, Vol.3-6-27, Vol.3-9-6,
Vol.3-9-7, Vol.3-12-1, Vol.3-22-7
MS-DOS compatibility mode, Vol.1-8-33, Vol.1-D-1
MSR
Model Specific Register, Vol.3-10-36, Vol.3-10-37
MSRs, Vol.1-3-4
architectural, Vol.1-35-2
description of, Vol.3-9-7
introduction of in IA-32 processors, Vol.3-22-35
introduction to, Vol.3-2-6
list of, Vol.1-35-1
machine-check architecture, Vol.3-15-2
P6 family processors, Vol.1-35-319
Pentium 4 processor, Vol.1-35-43, Vol.1-35-57, Vol.1-35-172,
Vol.1-35-188, Vol.1-35-204, Vol.1-35-277, Vol.1-35-301
Pentium processors, Vol.1-35-327, Vol.1-35-403
reading and writing, Vol.3-2-19, Vol.3-2-20, Vol.3-2-25
reading & writing in 64-bit mode, Vol.3-2-25
virtualization support, Vol.3-31-14
VMX support, Vol.3-31-14
MSRs (model specific registers)
reading, Vol.2-4-532
MSR_ TC_PRECISE_EVENT MSR, Vol.3-19-196
MSR_DEBUBCTLB MSR, Vol.3-17-12, Vol.3-17-27, Vol.3-17-36,
Vol.3-17-37
MSR_DEBUGCTLA MSR, Vol.3-17-11, Vol.3-17-17, Vol.3-17-23,
Vol.3-17-24, Vol.3-17-32, Vol.3-17-33, Vol.3-18-4,
Vol.3-18-8, Vol.3-18-21, Vol.3-18-25, Vol.3-18-31,
Vol.3-18-56, Vol.3-18-67, Vol.1-35-289
MSR_DEBUGCTLB MSR, Vol.3-17-11, Vol.3-17-35, Vol.3-17-37,
Vol.1-35-51, Vol.1-35-63, Vol.1-35-71, Vol.1-35-114,
Vol.1-35-150, Vol.1-35-190, Vol.1-35-270, Vol.1-35-309,
Vol.1-35-317
MSR_EBC_FREQUENCY_ID MSR, Vol.1-35-280
MSR_EBC_HARD_POWERON MSR, Vol.1-35-278
MSR_EBC_SOFT_POWERON MSR, Vol.1-35-279, Vol.1-35-348
MSR_IFSB_CNTR7 MSR, Vol.3-18-111
MSR_IFSB_CTRL6 MSR, Vol.3-18-111
MSR_IFSB_DRDY0 MSR, Vol.3-18-110
MSR_IFSB_DRDY1 MSR, Vol.3-18-110
MSR_IFSB_IBUSQ0 MSR, Vol.3-18-109
MSR_IFSB_IBUSQ1 MSR, Vol.3-18-109
MSR_IFSB_ISNPQ0 MSR, Vol.3-18-110
MSR_IFSB_ISNPQ1 MSR, Vol.3-18-110
MSR_LASTBRANCH _TOS, Vol.1-35-289
MSR_LASTBRANCH_0_TO_IP, Vol.1-35-300
MSR_LASTBRANCH_n MSR, Vol.3-17-17, Vol.3-17-34, Vol.1-35-289,
Vol.1-35-352
MSR_LASTBRANCH_n_FROM_IP MSR, Vol.3-17-16, Vol.3-17-17,
Vol.3-17-34, Vol.3-17-35, Vol.1-35-299
MSR_LASTBRANCH_n_TO_IP MSR, Vol.3-17-16, Vol.3-17-17,
Vol.3-17-34, Vol.3-17-35
MSR_LASTBRANCH_n_TO_LIP MSR, Vol.1-35-300
MSR_LASTBRANCH_TOS MSR, Vol.3-17-34
MSR_LER_FROM_LIP MSR, Vol.3-17-35, Vol.3-17-36, Vol.1-35-288
MSR_LER_TO_LIP MSR, Vol.3-17-35, Vol.3-17-36, Vol.1-35-288
MSR_PEBS_ MATRIX_VERT MSR, Vol.3-19-196
MSR_PEBS_MATRIX_VERT MSR, Vol.1-35-295, Vol.1-35-381
MSR_PLATFORM_BRV, Vol.1-35-288, Vol.1-35-384
MTRR feature flag, CPUID instruction, Vol.3-11-21
MTRRcap MSR, Vol.3-11-21
MTRRfix MSR, Vol.3-11-23
MTRRs, Vol.1-3-4, Vol.3-8-15
base & mask calculations, Vol.3-11-26, Vol.3-11-27
cache control, Vol.3-11-13
description of, Vol.3-9-8, Vol.3-11-20
dual-core processors, Vol.3-8-32
enabling caching, Vol.3-9-7
feature identification, Vol.3-11-21
fixed-range registers, Vol.3-11-23
IA32_MTRRCAP MSR, Vol.3-11-21
IA32_MTRR_DEF_TYPE MSR, Vol.3-11-22
initialization of, Vol.3-11-29
introduction of in IA-32 processors, Vol.3-22-35
introduction to, Vol.3-2-6
large page size considerations, Vol.3-11-33
logical processors, Vol.3-8-32
mapping physical memory with, Vol.3-11-21
memory types and their properties, Vol.3-11-21
MemTypeGet() function, Vol.3-11-29
MemTypeSet() function, Vol.3-11-31
multiple-processor considerations, Vol.3-11-32
precedence of cache controls, Vol.3-11-13
precedences, Vol.3-11-28
programming interface, Vol.3-11-29
remapping memory types, Vol.3-11-29
state of following a hardware reset, Vol.3-11-20
variable-range registers, Vol.3-11-23, Vol.3-11-25
MUL instruction, Vol.1-7-9, Vol.2-3-22, Vol.2-4-144
MULPD instruction, Vol.1-11-6
MULPD- Multiply Packed Double-Precision Floating-Point Values,
Vol.2-4-146
MULPS instruction, Vol.1-10-8
MULPS- Multiply Packed Single-Precision Floating-Point Values,
Vol.2-4-149
MULSD instruction, Vol.1-11-6
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -21
INDEX
MULSD- Multiply Scalar Double-Precision Floating-Point Values,
Vol.2-4-152
MULSS instruction, Vol.1-10-8
MULSS- Multiply Scalar Single-Precision Floating-Point Values, Vol.2-4-154
Multi-byte no operation, Vol.2-4-161, Vol.2-4-163, Vol.1-B-13
Multi-core technology, Vol.1-2-19
See multi-threading support
Multiple-processor management
bus locking, Vol.3-8-3
guaranteed atomic operations, Vol.3-8-2
initialization
MP protocol, Vol.3-8-18
procedure, Vol.3-8-53
local APIC, Vol.3-10-1
memory ordering, Vol.3-8-5
MP protocol, Vol.3-8-18
overview of, Vol.3-8-1
SMM considerations, Vol.3-34-16
VMM design, Vol.3-31-10
asymmetric, Vol.3-31-10
CPUID emulation, Vol.3-31-12
external data structures, Vol.3-31-11
index-data registers, Vol.3-31-11
initialization, Vol.3-31-11
moving between processors, Vol.3-31-11
symmetric, Vol.3-31-10
Multiple-processor system
local APIC and I/O APICs, Pentium 4, Vol.3-10-3
local APIC and I/O APIC, P6 family, Vol.3-10-3
Multisegment model, Vol.3-3-4
Multitasking
initialization for, Vol.3-9-10, Vol.3-9-11
initializing IA-32e mode, Vol.3-9-11
linking tasks, Vol.3-7-12
mechanism, description of, Vol.3-7-2
overview, Vol.3-7-1
setting up TSS, Vol.3-9-10
setting up TSS descriptor, Vol.3-9-10
Multi-threading capability, Vol.1-2-19
Multi-threading support
executing multiple threads, Vol.3-8-26
handling interrupts, Vol.3-8-26
logical processors per package, Vol.3-8-24
mapping resources, Vol.3-8-33
microcode updates, Vol.3-8-32
performance monitoring counters, Vol.3-8-32
programming considerations, Vol.3-8-33
See also: Hyper-Threading Technology and dual-core technology
MULX - Unsigned Multiply Without Affecting Flags, Vol.2-4-156
MVMM, Vol.1-6-1, Vol.1-6-4, Vol.1-6-5, Vol.1-6-37
MWAIT instruction, Vol.1-5-21, Vol.1-12-5, Vol.2-4-158, Vol.3-25-3
CPUID flag, Vol.2-3-206
feature data, Vol.2-3-214
power management extensions, Vol.3-14-18
MXCSR register, Vol.1-11-16, Vol.3-6-48, Vol.3-9-8, Vol.3-13-6
denormals-are-zero (DAZ) flag, Vol.1-10-5, Vol.1-11-2, Vol.1-11-3
description, Vol.1-10-3
flush-to-zero flag (FZ), Vol.1-10-4
FXSAVE and FXRSTOR instructions, Vol.1-11-23
LDMXCSR instruction, Vol.1-11-24
load and store instructions, Vol.1-10-12
RC field, Vol.1-4-18
saving on a procedure or function call, Vol.1-11-23
SIMD floating-point mask and flag bits, Vol.1-10-4
SIMD floating-point rounding control field, Vol.1-10-4
state management instructions, Vol.1-5-16, Vol.1-10-12
STMXCSR instruction, Vol.1-11-24
writing to while preventing general-protection exceptions (#GP),
Vol.1-11-21
Index-22 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
N
NaNs
description of, Vol.1-4-13, Vol.1-4-15
encoding of, Vol.1-4-5, Vol.1-4-14
SNaNs vs. QNaNs, Vol.1-4-15
NaN, compatibility, IA-32 processors, Vol.3-22-8
NaN. testing for, Vol.2-3-401
NE (numeric error) flag
CR0 control register, Vol.3-2-15, Vol.3-6-43, Vol.3-9-6, Vol.3-9-7,
Vol.3-22-7, Vol.3-22-17
Near
return, RET instruction, Vol.2-4-553
Near call
description of, Vol.1-6-4
operation, Vol.1-6-4
Near pointer
64-bit mode, Vol.1-4-7
legacy modes, Vol.1-4-6
Near return operation, Vol.1-6-4
NEG instruction, Vol.1-7-8, Vol.2-3-537, Vol.2-4-161, Vol.3-8-3
NetBurst microarchitecture (see Intel NetBurst microarchitecture)
NMI interrupt, Vol.3-2-24, Vol.3-10-3
description of, Vol.3-6-2
handling during initialization, Vol.3-9-9
handling in SMM, Vol.3-34-11
handling multiple NMIs, Vol.3-6-6
masking, Vol.3-22-26
receiving when processor is shutdown, Vol.3-6-29
reference information, Vol.3-6-22
vector, Vol.3-6-2
NMI# pin, Vol.3-6-2, Vol.3-6-22
No operation, Vol.2-4-161, Vol.2-4-163, Vol.1-B-12
Nomenclature, used in instruction reference pages, Vol.2-3-1
Nominal CPI method, Vol.3-18-106
Non-arithmetic instructions, x87 FPU, Vol.1-8-25
Nonconforming code segments
accessing, Vol.3-5-11
C (conforming) flag, Vol.3-5-11
description of, Vol.3-3-13
Non-halted clockticks, Vol.3-18-105
setting up counters, Vol.3-18-106
Non-Halted CPI method, Vol.3-18-106
Nonmaskable interrupt (see NMI)
Non-number encodings, floating-point format, Vol.1-4-13
Non-precise event-based sampling
defined, Vol.3-18-86
used for at-retirement counting, Vol.3-18-97
writing an interrupt service routine for, Vol.3-17-24
Non-retirement events, Vol.3-18-85, Vol.3-19-173
Non-sleep clockticks, Vol.3-18-105
Non-temporal data
caching of, Vol.1-10-12
description, Vol.1-10-12
temporal vs. non-temporal data, Vol.1-10-12
Non-waiting instructions, x87 FPU, Vol.1-8-24, Vol.1-8-32
NOP instruction, Vol.1-7-23, Vol.2-4-163
Normalized finite number, Vol.1-4-5, Vol.1-4-13, Vol.1-4-14
NOT instruction, Vol.1-7-10, Vol.2-3-537, Vol.2-4-164, Vol.3-8-3
Notation
bit and byte order, Vol.1-1-5, Vol.2-1-4, Vol.3-1-6
conventions, Vol.3-1-6
exceptions, Vol.1-1-7, Vol.2-1-6, Vol.3-1-9
hexadecimal and binary numbers, Vol.1-1-6, Vol.2-1-5, Vol.3-1-7
instruction operands, Vol.1-1-6, Vol.2-1-5
Instructions
operands, Vol.3-1-7
notational conventions, Vol.1-1-5
reserved bits, Vol.1-1-5, Vol.2-1-5, Vol.3-1-6
segmented addressing, Vol.1-1-6, Vol.2-1-6, Vol.3-1-7
Notational conventions, Vol.2-1-4
NT (nested task) flag
EFLAGS register, Vol.3-2-10, Vol.3-7-10, Vol.3-7-12
INDEX
NT (nested task) flag, EFLAGS register, Vol.1-3-17, Vol.1-A-1,
Vol.2-3-476
Null segment selector, checking for, Vol.3-5-6
Numeric overflow exception (#O), Vol.3-22-9
overview, Vol.1-4-20
SSE and SSE2 extensions, Vol.1-11-15
x87 FPU, Vol.1-8-4, Vol.1-8-29
Numeric underflow exception (#U), Vol.3-22-10
overview, Vol.1-4-21
SSE and SSE2 extensions, Vol.1-11-16
x87 FPU, Vol.1-8-4, Vol.1-8-30
NV (invert) flag, PerfEvtSel0 MSR
(P6 family processors), Vol.3-18-4, Vol.3-18-119
NW (not write-through) flag
CR0 control register, Vol.3-2-14, Vol.3-9-7, Vol.3-11-12, Vol.3-11-13,
Vol.3-11-16, Vol.3-11-32, Vol.3-22-17, Vol.3-22-18, Vol.3-22-29
NXE bit, Vol.3-5-30
O
Obsolete instructions, Vol.3-22-5, Vol.3-22-14
OE (numeric overflow exception) flag
MXCSR register, Vol.1-11-15
x87 FPU status word, Vol.1-8-5, Vol.1-8-29
OF flag, EFLAGS register, Vol.3-6-24
OF (carry) flag, EFLAGS register, Vol.2-3-444
OF (overflow) flag
EFLAGS register, Vol.1-3-16, Vol.1-6-13
OF (overflow) flag, EFLAGS register, Vol.1-A-1, Vol.2-3-31, Vol.2-3-457,
Vol.2-4-144, Vol.2-4-590, Vol.2-4-611, Vol.2-4-614,
Vol.2-4-655
Offset (operand addressing, 64-bit mode), Vol.1-3-24
Offset (operand addressing), Vol.1-3-22
OM (numeric overflow exception) mask bit
MXCSR register, Vol.1-11-15
x87 FPU control word, Vol.1-8-7, Vol.1-8-29
On die digital thermal sensor, Vol.3-14-25
relevant MSRs, Vol.3-14-25
sensor enumeration, Vol.3-14-25
On-Demand
clock modulation enable bits, Vol.3-14-23
On-demand
clock modulation duty cycle bits, Vol.3-14-23
On-die sensors, Vol.3-14-19
Opcode format, Vol.2-2-3
Opcodes
addressing method codes for, Vol.1-A-1
extensions, Vol.1-A-17
extensions tables, Vol.1-A-18
group numbers, Vol.1-A-17
integers
one-byte opcodes, Vol.1-A-7
two-byte opcodes, Vol.1-A-7
key to abbreviations, Vol.1-A-1
look-up examples, Vol.1-A-3, Vol.1-A-17, Vol.1-A-20
ModR/M byte, Vol.1-A-17
one-byte opcodes, Vol.1-A-3, Vol.1-A-7
opcode maps, Vol.1-A-1
operand type codes for, Vol.1-A-2
register codes for, Vol.1-A-3
superscripts in tables, Vol.1-A-6
two-byte opcodes, Vol.1-A-4, Vol.1-A-5, Vol.1-A-7
undefined, Vol.3-22-5
VMX instructions, Vol.1-B-117, Vol.1-B-118
x87 ESC instruction opcodes, Vol.1-A-20
Operand
addressing, modes, Vol.1-3-19
instruction, Vol.1-1-6
size attribute, Vol.1-3-18
sizes, Vol.1-3-9, Vol.1-3-19
x87 FPU instructions, Vol.1-8-15
Operands, Vol.2-1-5
instruction, Vol.3-1-7
operand-size prefix, Vol.3-21-1
Operating modes
64-bit mode, Vol.3-2-7
compatibility mode, Vol.3-2-7
IA-32e mode, Vol.3-2-7, Vol.3-2-8
introduction to, Vol.3-2-7
protected mode, Vol.3-2-7
SMM (system management mode), Vol.3-2-7
transitions between, Vol.3-2-8
virtual-8086 mode, Vol.3-2-7
VMX operation
enabling and entering, Vol.3-23-3
guest environments, Vol.3-31-1
OR instruction, Vol.1-7-10, Vol.2-3-537, Vol.2-4-166, Vol.3-8-3
Ordering I/O, Vol.1-18-5
ORPD instruction, Vol.1-11-7
ORPS- Bitwise Logical OR of Packed Single Precision Floating-Point Values
, Vol.2-4-171
ORPS instruction, Vol.1-10-9
OS (operating system mode) flag
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 only), Vol.3-18-4,
Vol.3-18-118
OSFXSR (FXSAVE/FXRSTOR support) flag
CR4 control register, Vol.3-2-17, Vol.3-9-8, Vol.3-13-2
OSXMMEXCPT flag
control register CR4, Vol.1-11-18
OSXMMEXCPT (SIMD floating-point exception support) flag, CR4 control
register, Vol.3-2-18, Vol.3-6-48, Vol.3-9-8, Vol.3-13-3
OUT instruction, Vol.1-5-7, Vol.1-7-20, Vol.1-18-3, Vol.2-4-174,
Vol.3-8-15, Vol.3-25-2
Out-of-spec status bit, Vol.3-14-25, Vol.3-14-29
Out-of-spec status log, Vol.3-14-26, Vol.3-14-29
OUTS instruction, Vol.1-5-7, Vol.1-7-20, Vol.1-18-3, Vol.2-4-176,
Vol.2-4-550
OUTSB instruction, Vol.2-4-176
OUTSD instruction, Vol.2-4-176
OUTSW instruction, Vol.2-4-176
OUTS/OUTSB/OUTSW/OUTSD instruction, Vol.3-17-9, Vol.3-25-2
Overflow exception (#OF), Vol.1-6-13, Vol.2-3-457, Vol.3-6-24
Overflow, x87 FPU stack, Vol.1-8-27
Overheat interrupt enable bit, Vol.3-14-27, Vol.3-14-30
P
P (present) flag
page-directory entry, Vol.3-6-40
page-table entry, Vol.3-6-40
segment descriptor, Vol.3-3-11
P5_MC_ADDR MSR, Vol.3-15-12, Vol.3-15-28, Vol.1-35-43, Vol.1-35-57,
Vol.1-35-68, Vol.1-35-107, Vol.1-35-143, Vol.1-35-264,
Vol.1-35-303, Vol.1-35-312, Vol.1-35-319, Vol.1-35-328
P5_MC_TYPE MSR, Vol.3-15-12, Vol.3-15-28, Vol.1-35-43, Vol.1-35-57,
Vol.1-35-68, Vol.1-35-107, Vol.1-35-143, Vol.1-35-264,
Vol.1-35-303, Vol.1-35-312, Vol.1-35-319, Vol.1-35-328
P6 family microarchitecture
description of, Vol.1-2-7
history of, Vol.1-2-2
P6 family processors
compatibility with FP software, Vol.3-22-6
description of, Vol.1-1-1, Vol.2-1-1, Vol.3-1-1
history of, Vol.1-2-2
last branch, interrupt, and exception recording, Vol.3-17-38
list of performance-monitoring events, Vol.3-19-204
machine encodings, Vol.1-B-41
MSR supported by, Vol.1-35-319
P6 family microarchitecture, Vol.1-2-7
PABSB instruction, Vol.1-5-22, Vol.1-12-7, Vol.2-4-180, Vol.2-4-194,
Vol.2-5-85, Vol.2-5-400, Vol.2-5-403, Vol.2-5-426
PABSD instruction, Vol.1-12-8, Vol.2-4-180, Vol.2-4-194, Vol.2-5-85,
Vol.2-5-400, Vol.2-5-403, Vol.2-5-426
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -23
INDEX
PABSW instruction, Vol.1-5-22, Vol.1-12-8, Vol.2-4-180, Vol.2-4-194,
Vol.2-5-85, Vol.2-5-400, Vol.2-5-403, Vol.2-5-426
Packed
BCD integer indefinite, Vol.1-4-11
BCD integers, Vol.1-4-10
bytes, Vol.1-9-3
doublewords, Vol.1-9-3
SIMD data types, Vol.1-4-8
SIMD floating-point values, Vol.1-4-8
SIMD integers, Vol.1-4-8
words, Vol.1-9-3
PACKSSDW instruction, Vol.2-4-186
PACKSSWB instruction, Vol.1-9-7, Vol.2-4-186
PACKUSWB instruction, Vol.1-9-7, Vol.2-4-199
PADDB instruction, Vol.1-9-6
PADDB/PADDW/PADDD/PADDQ - Add Packed Integers, Vol.2-4-204
PADDD instruction, Vol.1-9-6
PADDQ instruction, Vol.1-11-11
PADDSB instruction, Vol.1-9-7, Vol.2-4-211
PADDSW instruction, Vol.1-9-7, Vol.2-4-211
PADDUSB instruction, Vol.1-9-7, Vol.2-4-215
PADDUSW instruction, Vol.1-9-7, Vol.2-4-215
PADDW instruction, Vol.1-9-6
PAE paging
feature flag, CR4 register, Vol.3-2-17
flag, CR4 control register, Vol.3-3-6, Vol.3-22-17, Vol.3-22-18
Page attribute table (PAT)
compatibility with earlier IA-32 processors, Vol.3-11-36
detecting support for, Vol.3-11-34
IA32_PAT MSR, Vol.3-11-34
introduction to, Vol.3-11-33
memory types that can be encoded with, Vol.3-11-34
MSR, Vol.3-11-13
precedence of cache controls, Vol.3-11-14
programming, Vol.3-11-35
selecting a memory type with, Vol.3-11-35
Page directories, Vol.3-2-6
Page directory
base address (PDBR), Vol.3-7-5
introduction to, Vol.3-2-6
overview, Vol.3-3-2
setting up during initialization, Vol.3-9-10
Page directory pointers, Vol.3-2-6
Page frame (see Page)
Page tables, Vol.3-2-6
introduction to, Vol.3-2-6
overview, Vol.3-3-2
setting up during initialization, Vol.3-9-10
Page-directory entries, Vol.3-8-3, Vol.3-11-5
Page-fault exception (#PF), Vol.3-4-47, Vol.3-6-40, Vol.3-22-20
Pages
disabling protection of, Vol.3-5-1
enabling protection of, Vol.3-5-1
introduction to, Vol.3-2-6
overview, Vol.3-3-2
PG flag, CR0 control register, Vol.3-5-1
split, Vol.3-22-14
Page-table entries, Vol.3-8-3, Vol.3-11-5, Vol.3-11-19
Paging
combining segment and page-level protection, Vol.3-5-29
combining with segmentation, Vol.3-3-5
defined, Vol.3-3-1
IA-32e mode, Vol.3-2-6
initializing, Vol.3-9-10
introduction to, Vol.3-2-6
large page size MTRR considerations, Vol.3-11-33
mapping segments to pages, Vol.3-4-47
page boundaries regarding TSS, Vol.3-7-5
page-fault exception, Vol.3-6-40, Vol.3-6-50
page-level protection, Vol.3-5-2, Vol.3-5-3, Vol.3-5-27
page-level protection flags, Vol.3-5-28
virtual-8086 tasks, Vol.3-20-7
Index-24 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
PALIGNR instruction, Vol.1-5-23, Vol.1-12-8, Vol.2-4-219
PAND instruction, Vol.1-9-7, Vol.2-4-223
PANDN instruction, Vol.1-9-7, Vol.2-4-226
Parameter
passing, between 16- and 32-bit call gates, Vol.3-21-6
translation, between 16- and 32-bit code segments, Vol.3-21-6
Parameter passing
argument list, Vol.1-6-6
on stack, Vol.1-6-5
on the stack, Vol.1-6-5
through general-purpose registers, Vol.1-6-5
x87 FPU register stack, Vol.1-8-3
XMM registers, Vol.1-11-23
GETSEC, Vol.1-6-4
PAUSE instruction, Vol.1-11-12, Vol.2-4-229, Vol.3-2-15, Vol.3-25-3
PAVGB instruction, Vol.1-10-11, Vol.2-4-230
PAVGW instruction, Vol.2-4-230
PBi (performance monitoring/breakpoint pins) flags, DEBUGCTLMSR MSR,
Vol.3-17-37, Vol.3-17-39
PC (pin control) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family
processors), Vol.3-18-4, Vol.3-18-119
PC (precision) field, x87 FPU control word, Vol.1-8-7
PC0 and PC1 (pin control) fields, CESR MSR (Pentium processor),
Vol.3-18-121
PCD pin (Pentium processor), Vol.3-11-13
PCD (page-level cache disable) flag
CR3 control register, Vol.3-2-16, Vol.3-11-13, Vol.3-22-17,
Vol.3-22-29
page-directory entries, Vol.3-9-7, Vol.3-11-13, Vol.3-11-33
page-table entries, Vol.3-9-7, Vol.3-11-13, Vol.3-11-33, Vol.3-22-30
PCE flag, CR4 register, Vol.2-4-538
PCE (performance monitoring counter enable) flag, CR4 control register,
Vol.3-2-17, Vol.3-5-24, Vol.3-18-88, Vol.3-18-119
PCE (performance-monitoring counter enable) flag, CR4 control register,
Vol.3-22-17
PCLMULQDQ - Carry-Less Multiplication Quadword, Vol.2-5-339,
Vol.2-5-348
PCMPEQB instruction, Vol.1-9-7, Vol.2-4-244
PCMPEQD instruction, Vol.1-9-7, Vol.2-4-244
PCMPEQW instruction, Vol.1-9-7, Vol.2-4-244
PCMPGTB instruction, Vol.1-9-7, Vol.2-4-257
PCMPGTD instruction, Vol.1-9-7, Vol.2-4-257
PCMPGTW instruction, Vol.1-9-7, Vol.2-4-257
PDBR (see CR3 control register)
PDEP - Parallel Bits Deposit, Vol.2-4-270
PE (inexact result exception) flag, Vol.1-11-16
MXCSR register, Vol.1-4-18
x87 FPU status word, Vol.1-4-18, Vol.1-8-4, Vol.1-8-5, Vol.1-8-31
PE (protection enable) flag, CR0 control register, Vol.3-2-16, Vol.3-5-1,
Vol.3-9-10, Vol.3-9-13, Vol.3-34-9
PE (protection enable) flag, CR0 register, Vol.2-3-535
PEBS records, Vol.3-17-21
PEBS (precise event-based sampling) facilities
availability of, Vol.3-18-99
description of, Vol.3-18-86, Vol.3-18-99
DS save area, Vol.3-17-17
IA-32e mode, Vol.3-17-21
PEBS buffer, Vol.3-17-18, Vol.3-18-99
PEBS records, Vol.3-17-17, Vol.3-17-20
writing a PEBS interrupt service routine, Vol.3-18-99
writing interrupt service routine, Vol.3-17-24
PEBS_UNAVAILABLE flag
IA32_MISC_ENABLE MSR, Vol.3-17-18, Vol.1-35-287
Pending break enable, Vol.2-3-210
Pentium 4 processor, Vol.1-1-1, Vol.2-1-1, Vol.3-1-1
compatibility with FP software, Vol.3-22-6
description of, Vol.1-2-3, Vol.1-2-4
last branch, interrupt, and exception recording, Vol.3-17-32
list of performance-monitoring events, Vol.3-19-2, Vol.3-19-173
MSRs supported, Vol.1-35-43, Vol.1-35-57, Vol.1-35-68,
Vol.1-35-83, Vol.1-35-85, Vol.1-35-277, Vol.1-35-301
time-stamp counter, Vol.3-17-40
INDEX
Pentium 4 processor supporting Hyper-Threading Technology
description of, Vol.1-2-3, Vol.1-2-4
Pentium II processor, Vol.1-1-2, Vol.2-1-2, Vol.3-1-2
description of, Vol.1-2-2
P6 family microarchitecture, Vol.1-2-7
Pentium II Xeon processor
description of, Vol.1-2-2
Pentium III processor, Vol.1-1-2, Vol.2-1-2, Vol.3-1-2
description of, Vol.1-2-3
P6 family microarchitecture, Vol.1-2-7
Pentium III Xeon processor
description of, Vol.1-2-3
Pentium M processor
description of, Vol.1-2-3
instructions supported, Vol.1-2-3
last branch, interrupt, and exception recording, Vol.3-17-37
MSRs supported by, Vol.1-35-312
time-stamp counter, Vol.3-17-40
Pentium Pro processor, Vol.1-1-2, Vol.2-1-2, Vol.3-1-2
description of, Vol.1-2-2
P6 family microarchitecture, Vol.1-2-7
Pentium processor, Vol.1-1-1, Vol.2-1-1, Vol.3-1-1, Vol.3-22-6
compatibility with MCA, Vol.3-15-1
history of, Vol.1-2-2
list of performance-monitoring events, Vol.3-19-213
MSR supported by, Vol.1-35-327
performance-monitoring counters, Vol.3-18-120
Pentium processor Extreme Edition
introduction, Vol.1-2-4
Pentium processor family processors
machine encodings, Vol.1-B-37
Pentium processor with MMX technology, Vol.1-2-2
PerfCtr0 and PerfCtr1 MSRs
(P6 family processors), Vol.3-18-118, Vol.3-18-119
PerfEvtSel0 and PerfEvtSel1 MSRs
(P6 family processors), Vol.3-18-118
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors), Vol.3-18-118
Performance events
architectural, Vol.3-18-1
Intel Core Solo and Intel Core Duo processors, Vol.3-18-1
non-architectural, Vol.3-18-1
non-retirement events (Pentium 4 processor), Vol.3-19-173
P6 family processors, Vol.3-19-204
Pentium 4 and Intel Xeon processors, Vol.3-17-32
Pentium M processors, Vol.3-17-37
Pentium processor, Vol.3-19-213
Performance monitoring counters, Vol.1-3-4
Performance state, Vol.3-14-1
Performance-monitoring counters
counted events (P6 family processors), Vol.3-19-204
counted events (Pentium 4 processor), Vol.3-19-2, Vol.3-19-173
counted events (Pentium processors), Vol.3-18-122
CPUID inquiry for, Vol.2-3-215
description of, Vol.3-18-1, Vol.3-18-2
events that can be counted (Pentium processors), Vol.3-19-213
interrupt, Vol.3-10-1
introduction of in IA-32 processors, Vol.3-22-36
monitoring counter overflow (P6 family processors), Vol.3-18-120
overflow, monitoring (P6 family processors), Vol.3-18-120
overview of, Vol.3-2-7
P6 family processors, Vol.3-18-117
Pentium II processor, Vol.3-18-117
Pentium Pro processor, Vol.3-18-117
Pentium processor, Vol.3-18-120
reading, Vol.3-2-24, Vol.3-18-119
setting up (P6 family processors), Vol.3-18-118
software drivers for, Vol.3-18-120
starting and stopping, Vol.3-18-119
PEXT - Parallel Bits Extract, Vol.2-4-272
PEXTRW instruction, Vol.1-10-11, Vol.2-4-277
PF (parity) flag, EFLAGS register, Vol.1-3-16, Vol.1-A-1
PG (paging) flag
CR0 control register, Vol.3-2-14, Vol.3-5-1
PG (paging) flag, CR0 control register, Vol.3-9-10, Vol.3-9-13,
Vol.3-22-31, Vol.3-34-9
PGE (page global enable) flag, CR4 control register, Vol.3-2-17,
Vol.3-11-13, Vol.3-22-17, Vol.3-22-18
PHADDD instruction, Vol.1-5-22, Vol.1-12-7, Vol.2-4-280
PHADDSW instruction, Vol.1-5-22, Vol.1-12-7, Vol.2-4-284
PHADDW instruction, Vol.1-5-22, Vol.1-12-7, Vol.2-4-280
PHSUBD instruction, Vol.1-5-22, Vol.1-12-7, Vol.2-4-288
PHSUBSW instruction, Vol.1-5-22, Vol.1-12-7, Vol.2-4-291
PHSUBW instruction, Vol.1-5-22, Vol.1-12-7, Vol.2-4-288
PhysBase field, IA32_MTRR_PHYSBASEn MTRR, Vol.3-11-24,
Vol.3-11-26
Physical
address space, Vol.1-3-6
memory, Vol.1-3-6
Physical address extension
introduction to, Vol.3-3-6
Physical address space
4 GBytes, Vol.3-3-6
64 GBytes, Vol.3-3-6
addressing, Vol.3-2-6
defined, Vol.3-3-1
description of, Vol.3-3-6
guest and host spaces, Vol.3-32-2
IA-32e mode, Vol.3-3-6
mapped to a task, Vol.3-7-14
mapping with variable-range MTRRs, Vol.3-11-23, Vol.3-11-25
memory virtualization, Vol.3-32-2
See also: VMM, VMX
Physical destination mode, local APIC, Vol.3-10-22
PhysMask
IA32_MTRR_PHYSMASKn MTRR, Vol.3-11-24, Vol.3-11-26
Pi, Vol.2-3-355
PINSRW instruction, Vol.1-10-11, Vol.2-4-296, Vol.2-4-427
Pi, x87 FPU constant, Vol.1-8-21
PM (inexact result exception) mask bit
MXCSR register, Vol.1-11-16
x87 FPU control word, Vol.1-8-7, Vol.1-8-31
PM0/BP0 and PM1/BP1 (performance-monitor) pins (Pentium processor),
Vol.3-18-121, Vol.3-18-122
PMADDUBSW instruction, Vol.1-5-22, Vol.1-12-8, Vol.2-4-298
PMADDUDSW instruction, Vol.2-4-298
PMADDWD instruction, Vol.1-9-7, Vol.2-4-301
PMAXSW instruction, Vol.1-10-11
PMAXUB instruction, Vol.1-10-11
PMINSW instruction, Vol.1-10-11
PMINUB instruction, Vol.1-10-11
PML4 tables, Vol.3-2-6
PMOVMSKB instruction, Vol.1-10-11
PMULHRSW instruction, Vol.1-5-22, Vol.1-12-8, Vol.2-4-362
PMULHUW instruction, Vol.1-10-12, Vol.2-4-366
PMULHW instruction, Vol.2-4-370
PMULLW instruction, Vol.2-4-378
PMULUDQ instruction, Vol.1-11-11, Vol.2-4-382
Pointer data types, Vol.1-4-6, Vol.1-4-7
Pointers
64-bit mode, Vol.1-4-7
code-segment pointer size, Vol.3-21-4
far pointer, Vol.1-4-6
limit checking, Vol.3-5-25
near pointer, Vol.1-4-6
validation, Vol.3-5-24
POP instruction, Vol.1-6-1, Vol.1-6-2, Vol.1-7-6, Vol.1-7-22,
Vol.2-4-385, Vol.3-3-8
POPA instruction, Vol.1-6-6, Vol.1-7-6, Vol.2-4-390
POPAD instruction, Vol.2-4-390
POPF instruction, Vol.1-3-15, Vol.1-6-6, Vol.1-7-21, Vol.1-18-4,
Vol.2-4-394, Vol.3-6-7, Vol.3-17-9
POPFD instruction, Vol.1-3-15, Vol.1-6-6, Vol.1-7-21, Vol.2-4-394
POPFQ instruction, Vol.2-4-394
POR instruction, Vol.1-9-7, Vol.2-4-399
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -25
INDEX
Power consumption
software controlled clock, Vol.3-14-19, Vol.3-14-23
Power coordination, Vol.1-2-4
Precise event-based sampling (see PEBS)
PREFETCHh instruction, Vol.2-4-402, Vol.3-2-15, Vol.3-11-17
PREFETCHh instructions, Vol.1-10-13, Vol.1-11-25
PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write
and T1 Hint, Vol.2-4-406
Prefixes
Address-size override prefix, Vol.2-2-2
Branch hints, Vol.2-2-2
branch hints, Vol.2-2-2
instruction, description of, Vol.2-2-1
legacy prefix encodings, Vol.1-B-1
LOCK, Vol.2-2-1, Vol.2-3-537
Operand-size override prefix, Vol.2-2-2
REP or REPE/REPZ, Vol.2-2-1
REPNE/REPNZ, Vol.2-2-1
REP/REPE/REPZ/REPNE/REPNZ, Vol.2-4-549
REX prefix encodings, Vol.1-B-2
Segment override prefixes, Vol.2-2-2
Previous task link field, TSS, Vol.3-7-4, Vol.3-7-12, Vol.3-7-13
Privilege levels
checking when accessing data segments, Vol.3-5-8
checking, for call gates, Vol.3-5-15
checking, when transferring program control between code segments,
Vol.3-5-10
description of, Vol.1-6-6, Vol.3-5-6
inter-privilege level calls, Vol.1-6-6
protection rings, Vol.1-6-6, Vol.3-5-8
stack switching, Vol.1-6-11
Privileged instructions, Vol.3-5-23
Procedure calls
description of, Vol.1-6-4
far call, Vol.1-6-4
for block-structured languages, Vol.1-6-14
inter-privilege level call, Vol.1-6-7
linking, Vol.1-6-3
near call, Vol.1-6-4
overview, Vol.1-6-1
return instruction pointer (EIP register), Vol.1-6-3
saving procedure state information, Vol.1-6-6
stack, Vol.1-6-1
stack switching, Vol.1-6-7
to exception handler procedure, Vol.1-6-10
to exception task, Vol.1-6-13
to interrupt handler procedure, Vol.1-6-10
to interrupt task, Vol.1-6-13
to other privilege levels, Vol.1-6-6
types of, Vol.1-6-1
Processor families
06H, Vol.3-16-1
0FH, Vol.3-16-1
Processor identification
earlier Intel architecture processors, Vol.1-19-1
early processors, Vol.1-19-1
notes on where to start, Vol.1-19-1
using CPUID, Vol.1-19-1
using CPUID instruction, Vol.1-19-1
Processor management
initialization, Vol.3-9-1
local APIC, Vol.3-10-1
microcode update facilities, Vol.3-9-27
overview of, Vol.3-8-1
See also: multiple-processor management
Processor ordering, description of, Vol.3-8-5
Processor state information, saving, Vol.1-6-6
PROCHOT# log, Vol.3-14-25, Vol.3-14-29
PROCHOT# or FORCEPR# event bit, Vol.3-14-25, Vol.3-14-29
Protected mode
IDT initialization, Vol.3-9-10
initialization for, Vol.3-9-9
Index-26 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
I/O, Vol.1-18-3
memory models used, Vol.1-3-9
mixing 16-bit and 32-bit code modules, Vol.3-21-1
mode switching, Vol.3-9-13
overview, Vol.1-3-1
PE flag, CR0 register, Vol.3-5-1
switching to, Vol.3-5-1, Vol.3-9-13
system data structures required during initialization, Vol.3-9-9
Protection
combining segment & page-level, Vol.3-5-29
disabling, Vol.3-5-1
enabling, Vol.3-5-1
flags used for page-level protection, Vol.3-5-2, Vol.3-5-3
flags used for segment-level protection, Vol.3-5-2
IA-32e mode, Vol.3-5-3
of exception, interrupt-handler procedures, Vol.3-6-13
overview of, Vol.3-5-1
page level, Vol.3-5-1, Vol.3-5-27, Vol.3-5-28, Vol.3-5-30
page level, overriding, Vol.3-5-29
page-level protection flags, Vol.3-5-28
read/write, page level, Vol.3-5-28
segment level, Vol.3-5-1
user/supervisor type, Vol.3-5-28
Protection rings, Vol.1-6-6, Vol.3-5-8
PSADBW instruction, Vol.1-10-12, Vol.2-4-408
PSE (page size extension) flag
CR4 control register, Vol.3-2-17, Vol.3-11-20, Vol.3-22-17,
Vol.3-22-18
PSE-36 page size extension, Vol.3-3-6
Pseudo-functions
VMfail, Vol.3-30-2
VMfailInvalid, Vol.3-30-2
VMfailValid, Vol.3-30-2
VMsucceed, Vol.3-30-2
Pseudo-infinity, Vol.3-22-9
Pseudo-NaN, Vol.3-22-9
Pseudo-zero, Vol.3-22-9
PSHUFB instruction, Vol.1-5-23, Vol.1-12-8, Vol.2-4-412
PSHUFD instruction, Vol.1-11-11, Vol.2-4-416
PSHUFHW instruction, Vol.1-11-11, Vol.2-4-420
PSHUFLW instruction, Vol.1-11-11, Vol.2-4-423
PSHUFW instruction, Vol.1-10-12, Vol.1-11-11, Vol.2-4-426
PSIGNB instruction, Vol.2-4-427
PSIGNB/W/D instruction, Vol.1-5-23, Vol.1-12-8
PSIGND instruction, Vol.2-4-427
PSIGNW instruction, Vol.2-4-427
PSLLD instruction, Vol.1-9-8, Vol.2-4-433
PSLLDQ instruction, Vol.1-11-11, Vol.2-4-431
PSLLQ instruction, Vol.1-9-8, Vol.2-4-433
PSLLW instruction, Vol.1-9-8, Vol.2-4-433
PSRAD instruction, Vol.2-4-445
PSRAW instruction, Vol.2-4-445
PSRLD instruction, Vol.2-4-457
PSRLDQ instruction, Vol.1-11-11, Vol.2-4-455
PSRLQ instruction, Vol.2-4-457
PSRLW instruction, Vol.2-4-457
P-state, Vol.3-14-1
PSUBB instruction, Vol.1-9-6, Vol.2-4-469
PSUBD instruction, Vol.1-9-6, Vol.2-4-469
PSUBQ instruction, Vol.1-11-11, Vol.2-4-476
PSUBSB instruction, Vol.1-9-7, Vol.2-4-479
PSUBSW instruction, Vol.1-9-7, Vol.2-4-479
PSUBUSB instruction, Vol.1-9-7, Vol.2-4-483
PSUBUSW instruction, Vol.1-9-7, Vol.2-4-483
PSUBW instruction, Vol.1-9-6, Vol.2-4-469
PTEST- Packed Bit Test, Vol.2-3-509
PUNPCKHBW instruction, Vol.1-9-7, Vol.2-4-491
PUNPCKHDQ instruction, Vol.1-9-7, Vol.2-4-491
PUNPCKHQDQ instruction, Vol.1-11-11, Vol.2-4-491
PUNPCKHWD instruction, Vol.1-9-7, Vol.2-4-491
PUNPCKLBW instruction, Vol.1-9-7, Vol.2-4-501
PUNPCKLDQ instruction, Vol.1-9-7, Vol.2-4-501
INDEX
PUNPCKLQDQ instruction, Vol.1-11-11, Vol.2-4-501
PUNPCKLWD instruction, Vol.1-9-7, Vol.2-4-501
PUSH instruction, Vol.1-6-1, Vol.1-6-2, Vol.1-7-5, Vol.1-7-22,
Vol.2-4-511, Vol.3-22-6
PUSHA instruction, Vol.1-6-6, Vol.1-7-5, Vol.2-4-514
PUSHAD instruction, Vol.2-4-514
PUSHF instruction, Vol.1-3-15, Vol.1-6-6, Vol.1-7-21, Vol.2-4-516,
Vol.3-6-7, Vol.3-22-6
PUSHFD instruction, Vol.1-3-15, Vol.1-6-6, Vol.1-7-21, Vol.2-4-516
PVI (protected-mode virtual interrupts) flag
CR4 control register, Vol.3-2-11, Vol.3-2-17, Vol.3-22-17
PWT pin (Pentium processor), Vol.3-11-13
PWT (page-level write-through) flag
CR3 control register, Vol.3-2-16, Vol.3-11-13, Vol.3-22-17,
Vol.3-22-29
page-directory entries, Vol.3-9-7, Vol.3-11-13, Vol.3-11-33
page-table entries, Vol.3-9-7, Vol.3-11-33, Vol.3-22-30
PXOR instruction, Vol.1-9-7, Vol.2-4-518
Q
QNaN floating-point indefinite, Vol.1-4-5, Vol.1-4-17, Vol.1-8-14
QNaNs
description of, Vol.1-4-15
effect on COMISD and UCOMISD, Vol.1-11-7
encodings, Vol.1-4-5
operating on, Vol.1-4-16
rules for generating, Vol.1-4-16
using in applications, Vol.1-4-16
QNaN, compatibility, IA-32 processors, Vol.3-22-8
Quadword, Vol.1-4-1, Vol.1-9-3
Quiet NaN (see QNaN)
R
R8D-R15D registers, Vol.1-3-12
R8-R15 registers, Vol.1-3-12
RAX register, Vol.1-3-12
RBP register, Vol.1-3-12, Vol.1-6-4
RBX register, Vol.1-3-12
RC (rounding control) field
MXCSR register, Vol.1-4-18, Vol.1-10-4
x87 FPU control word, Vol.1-4-18, Vol.1-8-8
RC (rounding control) field, x87 FPU control word, Vol.2-3-348,
Vol.2-3-355, Vol.2-3-387
RCL instruction, Vol.1-7-13, Vol.2-4-521
RCPPS instruction, Vol.1-10-8, Vol.2-4-526
RCPSS instruction, Vol.1-10-8, Vol.2-4-528
RCR instruction, Vol.1-7-13, Vol.2-4-521
RCX register, Vol.1-3-12
RDI register, Vol.1-3-12
RDMSR instruction, Vol.2-4-532, Vol.2-4-538, Vol.2-4-545, Vol.3-2-19,
Vol.3-2-20, Vol.3-2-25, Vol.3-5-24, Vol.3-17-34, Vol.3-17-39,
Vol.3-17-41, Vol.3-18-88, Vol.3-18-118, Vol.3-18-119,
Vol.3-18-120, Vol.3-22-4, Vol.3-22-35, Vol.3-25-4,
Vol.3-25-8
CPUID flag, Vol.2-3-209
RDPMC instruction, Vol.2-4-535, Vol.2-4-537, Vol.2-5-574, Vol.3-2-24,
Vol.3-5-24, Vol.3-18-87, Vol.3-18-118, Vol.3-18-119,
Vol.3-22-4, Vol.3-22-17, Vol.3-22-36, Vol.3-25-4
in 64-bit mode, Vol.3-2-25
RDRAND, Vol.1-7-24
RDTSC instruction, Vol.2-4-541, Vol.2-4-545, Vol.2-4-547, Vol.3-2-24,
Vol.3-5-24, Vol.3-17-41, Vol.3-22-4, Vol.3-25-4, Vol.3-25-9
in 64-bit mode, Vol.3-2-25
RDX register, Vol.1-3-12
reading sensors, Vol.3-14-25
Read/write
protection, page level, Vol.3-5-28
rights, checking, Vol.3-5-25
Real address mode
handling exceptions in, Vol.1-6-13
handling interrupts in, Vol.1-6-13
memory model, Vol.1-3-7, Vol.1-3-8
memory model used, Vol.1-3-9
not in 64-bit mode, Vol.1-3-9
overview, Vol.1-3-1
Real numbers
continuum, Vol.1-4-11
encoding, Vol.1-4-13, Vol.1-4-14
notation, Vol.1-4-12, Vol.1-14-18
system, Vol.1-4-11
Real-address mode
8086 emulation, Vol.3-20-1
address translation in, Vol.3-20-2
description of, Vol.3-20-1
exceptions and interrupts, Vol.3-20-6
IDT initialization, Vol.3-9-8
IDT, changing base and limit of, Vol.3-20-5
IDT, structure of, Vol.3-20-5
IDT, use of, Vol.3-20-4
initialization, Vol.3-9-8
instructions supported, Vol.3-20-3
interrupt and exception handling, Vol.3-20-4
interrupts, Vol.3-20-6
introduction to, Vol.3-2-7
mode switching, Vol.3-9-13
native 16-bit mode, Vol.3-21-1
overview of, Vol.3-20-1
registers supported, Vol.3-20-3
switching to, Vol.3-9-14
Recursive task switching, Vol.3-7-13
Register operands
64-bit mode, Vol.1-3-21
legacy modes, Vol.1-3-20
Register stack, x87 FPU, Vol.1-8-1
Registers
64-bit mode, Vol.1-3-12, Vol.1-3-15
control registers, Vol.1-3-4
CR in 64-bit mode, Vol.1-3-5
debug registers, Vol.1-3-4
EFLAGS register, Vol.1-3-11, Vol.1-3-15
EIP register, Vol.1-3-11, Vol.1-3-18
general purpose registers, Vol.1-3-11
instruction pointer, Vol.1-3-11
machine check registers, Vol.1-3-4
memory management registers, Vol.1-3-4
MMX registers, Vol.1-3-2, Vol.1-9-2
MSRs, Vol.1-3-4
MTRRs, Vol.1-3-4
MXCSR register, Vol.1-10-4
performance monitoring counters, Vol.1-3-4
REX prefix, Vol.1-3-12
segment registers, Vol.1-3-11, Vol.1-3-13
x87 FPU registers, Vol.1-8-1
XMM registers, Vol.1-3-2, Vol.1-10-3
Reg/opcode field, instruction format, Vol.2-2-3
Related literature, Vol.1-1-8, Vol.2-1-7, Vol.3-1-9
Remainder, x87 FPU operation, Vol.2-3-369
Replay events, Vol.3-19-196
REP/REPE/REPZ/REPNE/REPNZ
prefixes, Vol.1-7-19, Vol.1-18-3
REP/REPE/REPZ/REPNE/REPNZ prefixes, Vol.2-3-170, Vol.2-3-452,
Vol.2-4-177, Vol.2-4-549
Requested privilege level (see RPL)
Reserved
use of reserved bits, Vol.2-1-5
Reserved bits, Vol.1-1-5, Vol.3-1-6, Vol.3-22-2
RESET pin, Vol.1-3-15
RESET# pin, Vol.3-6-3, Vol.3-22-15
RESET# signal, Vol.3-2-24
Resolution in degrees, Vol.3-14-26
Responding logical processor, Vol.1-6-4
responding logical processor, Vol.1-6-4, Vol.1-6-5
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -27
INDEX
Restarting program or task, following an exception or interrupt, Vol.3-6-5
Restricting addressable domain, Vol.3-5-28
RET instruction, Vol.1-3-18, Vol.1-6-3, Vol.1-6-4, Vol.1-7-15, Vol.1-7-22,
Vol.2-4-553, Vol.3-5-10, Vol.3-5-20, Vol.3-21-6
Return instruction pointer, Vol.1-6-3
Returning
from a called procedure, Vol.3-5-20
from an interrupt or exception handler, Vol.3-6-13
Returns, from procedure calls
exception handler, return from, Vol.1-6-10
far return, Vol.1-6-4
inter-privilege level return, Vol.1-6-7
interrupt handler, return from, Vol.1-6-10
near return, Vol.1-6-4
REX prefixes, Vol.1-3-2, Vol.1-3-12, Vol.1-3-19
addressing modes, Vol.2-2-9
and INC/DEC, Vol.2-2-8
encodings, Vol.2-2-8, Vol.1-B-2
field names, Vol.2-2-9
ModR/M byte, Vol.2-2-8
overview, Vol.2-2-8
REX.B, Vol.2-2-8
REX.R, Vol.2-2-8
REX.W, Vol.2-2-8
special encodings, Vol.2-2-11
RF (resume) flag
EFLAGS register, Vol.3-2-10, Vol.3-6-7
RF (resume) flag, EFLAGS register, Vol.1-3-17, Vol.1-A-1
RFLAGS, Vol.1-3-18
RFLAGS register, Vol.1-7-22
See EFLAGS register
RIP register, Vol.1-6-4
64-bit mode, Vol.1-7-2
description of, Vol.1-3-18
relation to EIP, Vol.1-7-2
RIP-relative addressing, Vol.2-2-12
ROL instruction, Vol.1-7-13, Vol.2-4-521
ROR instruction, Vol.1-7-13, Vol.2-4-521
RORX - Rotate Right Logical Without Affecting Flags, Vol.2-4-563
Rounding
modes, floating-point operations, Vol.1-4-18, Vol.2-4-565
modes, x87 FPU, Vol.1-8-8
toward zero (truncation), Vol.1-4-18
Rounding control (RC) field
MXCSR register, Vol.1-4-18, Vol.1-10-4, Vol.2-4-565
x87 FPU control word, Vol.1-4-18, Vol.1-8-8, Vol.2-4-565
Rounding, round to integer, x87 FPU operation, Vol.2-3-373
ROUNDPD- Round Packed Double-Precision Floating-Point Values,
Vol.2-4-656
RPL
description of, Vol.3-3-8, Vol.3-5-8
field, segment selector, Vol.3-5-2
RPL field, Vol.2-3-76
RSI register, Vol.1-3-12
RSM instruction, Vol.2-4-574, Vol.3-2-24, Vol.3-8-17, Vol.3-22-5,
Vol.3-25-4, Vol.3-34-1, Vol.3-34-2, Vol.3-34-3, Vol.3-34-13,
Vol.3-34-15, Vol.3-34-18
RSP register, Vol.1-3-12, Vol.1-6-4
RSQRTPS instruction, Vol.1-10-8, Vol.2-4-576
RSQRTSS instruction, Vol.1-10-8, Vol.2-4-578
RsvdZ, Vol.3-10-39
R/m field, instruction format, Vol.2-2-3
R/S# pin, Vol.3-6-3
R/W (read/write) flag
page-directory entry, Vol.3-5-1, Vol.3-5-2, Vol.3-5-28
page-table entry, Vol.3-5-1, Vol.3-5-2, Vol.3-5-28
R/W0-R/W3 (read/write) fields
DR7 register, Vol.3-17-4, Vol.3-22-19
S
S (descriptor type) flag
Index-28 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
segment descriptor, Vol.3-3-11, Vol.3-3-12, Vol.3-5-2, Vol.3-5-5
Safer Mode Extensions, Vol.1-6-1
SAHF instruction, Vol.1-3-15, Vol.1-7-21, Vol.2-4-580
SAL instruction, Vol.1-7-10, Vol.2-4-582
SAR instruction, Vol.1-7-11, Vol.2-4-582
Saturation arithmetic (MMX instructions), Vol.1-9-4
SBB instruction, Vol.1-7-8, Vol.2-3-537, Vol.2-4-589, Vol.3-8-3
Scalar operations
defined, Vol.1-10-7, Vol.1-11-5
scalar double-precision FP operands, Vol.1-11-5
scalar single-precision FP operands, Vol.1-10-7
Scale (operand addressing), Vol.1-3-22, Vol.1-3-23, Vol.1-3-24, Vol.2-2-3
Scale, x87 FPU operation, Vol.1-8-22, Vol.2-3-379
Scaling bias value, Vol.1-8-30
Scan string instructions, Vol.2-4-592
SCAS instruction, Vol.1-3-17, Vol.1-7-18, Vol.2-4-550, Vol.2-4-592
SCASB instruction, Vol.2-4-592
SCASD instruction, Vol.2-4-592
SCASW instruction, Vol.2-4-592
Segment
defined, Vol.1-3-7
descriptor, segment limit, Vol.2-3-544
limit, Vol.2-3-544
maximum number, Vol.1-3-7
registers, moving values to and from, Vol.2-4-36
selector, RPL field, Vol.2-3-76
Segment descriptors
access rights, Vol.3-5-24
access rights, invalid values, Vol.3-22-18
automatic bus locking while updating, Vol.3-8-3
base address fields, Vol.3-3-10
code type, Vol.3-5-2
data type, Vol.3-5-2
description of, Vol.3-2-4, Vol.3-3-9
DPL (descriptor privilege level) field, Vol.3-3-11, Vol.3-5-2
D/B (default operation size/default stack pointer size and/or upper
bound) flag, Vol.3-3-11, Vol.3-5-4
E (expansion direction) flag, Vol.3-5-2, Vol.3-5-4
G (granularity) flag, Vol.3-3-11, Vol.3-5-2, Vol.3-5-4
limit field, Vol.3-5-2, Vol.3-5-4
loading, Vol.3-22-19
P (segment-present) flag, Vol.3-3-11
S (descriptor type) flag, Vol.3-3-11, Vol.3-3-12, Vol.3-5-2, Vol.3-5-5
segment limit field, Vol.3-3-10
system type, Vol.3-5-2
tables, Vol.3-3-14
TSS descriptor, Vol.3-7-5, Vol.3-7-6
type field, Vol.3-3-10, Vol.3-3-12, Vol.3-5-2, Vol.3-5-5
type field, encoding, Vol.3-3-14
when P (segment-present) flag is clear, Vol.3-3-11
Segment limit
checking, Vol.3-2-22
field, segment descriptor, Vol.3-3-10
Segment not present exception (#NP), Vol.3-3-11
Segment override prefixes, Vol.1-3-21
Segment registers
64-bit mode, Vol.1-3-15, Vol.1-3-22, Vol.1-7-2
default usage rules, Vol.1-3-21
description of, Vol.1-3-11, Vol.1-3-13, Vol.3-3-8
IA-32e mode, Vol.3-3-9
part of basic programming environment, Vol.1-7-1
saved in TSS, Vol.3-7-4
Segment selector
description of, Vol.1-3-7, Vol.1-3-13
segment override prefixes, Vol.1-3-21
specifying, Vol.1-3-21
Segment selectors
description of, Vol.3-3-7
index field, Vol.3-3-7
null, Vol.3-5-6
null in 64-bit mode, Vol.3-5-6
RPL field, Vol.3-3-8, Vol.3-5-2
INDEX
TI (table indicator) flag, Vol.3-3-7
Segmented addressing, Vol.2-1-6, Vol.3-1-7
Segmented memory model, Vol.1-1-6, Vol.1-3-7, Vol.1-3-13
Segment-not-present exception (#NP), Vol.3-6-34
Segments
64-bit mode, Vol.3-3-5
basic flat model, Vol.3-3-3
code type, Vol.3-3-12
combining segment, page-level protection, Vol.3-5-29
combining with paging, Vol.3-3-5
compatibility mode, Vol.3-3-5
data type, Vol.3-3-12
defined, Vol.3-3-1
disabling protection of, Vol.3-5-1
enabling protection of, Vol.3-5-1
mapping to pages, Vol.3-4-47
multisegment usage model, Vol.3-3-4
protected flat model, Vol.3-3-3
segment-level protection, Vol.3-5-2, Vol.3-5-3
segment-not-present exception, Vol.3-6-34
system, Vol.3-2-4
types, checking access rights, Vol.3-5-24
typing, Vol.3-5-5
using, Vol.3-3-2
wraparound, Vol.3-22-33
SELF IPI register, Vol.3-10-38
Self Snoop, Vol.2-3-210
Self-modifying code, effect on caches, Vol.3-11-18
GETSEC, Vol.1-6-2, Vol.1-6-3, Vol.1-6-5
SENTER sleep state, Vol.1-6-10
Serialization of I/O instructions, Vol.1-18-5
Serializing, Vol.3-8-17
Serializing instructions, Vol.1-18-5
CPUID, Vol.3-8-17
HT technology, Vol.3-8-29
non-privileged, Vol.3-8-17
privileged, Vol.3-8-17
SETcc instructions, Vol.1-3-17, Vol.1-7-14, Vol.2-4-596
GETSEC, Vol.1-6-4
SF (sign) flag, EFLAGS register, Vol.1-3-16, Vol.1-A-1, Vol.2-3-31
SF (stack fault) flag, x87 FPU status word, Vol.1-8-6, Vol.1-8-27,
Vol.3-22-8
SFENCE instruction, Vol.1-10-14, Vol.1-11-12, Vol.1-11-25, Vol.2-4-599,
Vol.3-2-15, Vol.3-8-6, Vol.3-8-15, Vol.3-8-16, Vol.3-8-17
SGDT instruction, Vol.2-4-600, Vol.3-2-22, Vol.3-3-15
SHAF instruction, Vol.2-4-580
Shared resources
mapping of, Vol.3-8-33
Shift instructions, Vol.2-4-582
SHL instruction, Vol.1-7-10, Vol.2-4-582
SHLD instruction, Vol.1-7-12, Vol.2-4-611
SHR instruction, Vol.1-7-11, Vol.2-4-582
SHRD instruction, Vol.1-7-12, Vol.2-4-614
Shuffle instructions
SSE extensions, Vol.1-10-9
SSE2 extensions, Vol.1-11-7
SHUFPD - Shuffle Packed Double Precision Floating-Point Values,
Vol.2-4-617, Vol.2-4-656
SHUFPD instruction, Vol.1-11-7
SHUFPS - Shuffle Packed Single Precision Floating-Point Values,
Vol.2-4-622
Shutdown
resulting from double fault, Vol.3-6-29
resulting from out of IDT limit condition, Vol.3-6-29
SI register, Vol.1-3-12
SIB byte, Vol.2-2-3
32-bit addressing forms of, Vol.2-2-7, Vol.2-2-20
description of, Vol.2-2-3
SIDT instruction, Vol.2-4-600, Vol.2-4-626, Vol.3-2-22, Vol.3-3-16,
Vol.3-6-9
Signaling NaN (see SNaN)
Signed
infinity, Vol.1-4-15
integers, description of, Vol.1-4-4
integers, encodings, Vol.1-4-4
zero, Vol.1-4-14
Significand, extracting from floating-point number, Vol.2-3-421
Significand, of floating-point number, Vol.1-4-11
Sign, floating-point number, Vol.1-4-11
SIMD floating-point exception (#XM), Vol.1-11-18, Vol.3-2-18,
Vol.3-6-48, Vol.3-9-8
SIMD floating-point exceptions
denormal operand exception (#D), Vol.1-11-15
description of, Vol.3-6-48, Vol.3-13-5
divide-by-zero (#Z), Vol.1-11-15
exception conditions, Vol.1-11-14
exception handlers, Vol.1-E-1
handler, Vol.3-13-3
inexact result exception (#P), Vol.1-11-16
invalid operation exception (#I), Vol.1-11-14
list of, Vol.1-11-13
numeric overflow exception (#O), Vol.1-11-15
numeric underflow exception (#U), Vol.1-11-16
precision exception (#P), Vol.1-11-16
software handling, Vol.1-11-18
summary of, Vol.1-C-1
support for, Vol.3-2-18
writing exception handlers for, Vol.1-E-1
SIMD floating-point exceptions, unmasking, effects of, Vol.2-3-520,
Vol.2-4-530, Vol.2-5-570
SIMD floating-point flag bits, Vol.1-10-4
SIMD floating-point mask bits, Vol.1-10-4
SIMD floating-point rounding control field, Vol.1-10-4
SIMD (single-instruction, multiple-data)
execution model, Vol.1-2-2, Vol.1-2-3, Vol.1-9-4
instructions, Vol.1-2-15, Vol.1-5-17, Vol.1-10-7
MMX instructions, Vol.1-5-12
operations, on packed double-precision floating-point operands,
Vol.1-11-4
operations, on packed single-precision floating-point operands,
Vol.1-10-6
packed data types, Vol.1-4-8
SSE instructions, Vol.1-5-14
SSE2 instructions, Vol.1-11-4, Vol.1-12-2, Vol.1-12-6
Sine, x87 FPU operation, Vol.1-8-21, Vol.2-3-381, Vol.2-3-383
Single-precision floating-point format, Vol.1-4-4
Single-stepping
breakpoint exception condition, Vol.3-17-9
on branches, Vol.3-17-13
on exceptions, Vol.3-17-13
on interrupts, Vol.3-17-13
TF (trap) flag, EFLAGS register, Vol.3-17-9
SINIT, Vol.1-6-4
SLDT instruction, Vol.2-4-628, Vol.3-2-22
Sleep, Vol.1-2-4
SLTR instruction, Vol.3-3-16
Smart cache, Vol.1-2-4
Smart memory access, Vol.1-2-11
smart memory access, Vol.1-2-4
SMBASE
default value, Vol.3-34-4
relocation of, Vol.3-34-14
GETSEC, Vol.1-6-4
SMI handler
description of, Vol.3-34-1
execution environment for, Vol.3-34-9
exiting from, Vol.3-34-3
VMX treatment of, Vol.3-34-16
SMI interrupt, Vol.3-2-24, Vol.3-10-3
description of, Vol.3-34-1, Vol.3-34-2
IO_SMI bit, Vol.3-34-11
priority, Vol.3-34-3
switching to SMM, Vol.3-34-2
synchronous and asynchronous, Vol.3-34-11
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -29
INDEX
VMX treatment of, Vol.3-34-16
SMI# pin, Vol.3-6-3, Vol.3-34-2, Vol.3-34-15
SMM
asynchronous SMI, Vol.3-34-11
auto halt restart, Vol.3-34-13
executing the HLT instruction in, Vol.3-34-14
exiting from, Vol.3-34-3
handling exceptions and interrupts, Vol.3-34-10
introduction to, Vol.3-2-7
I/O instruction restart, Vol.3-34-15
I/O state implementation, Vol.3-34-12
memory model used, Vol.1-3-9
native 16-bit mode, Vol.3-21-1
overview, Vol.1-3-1
overview of, Vol.3-34-1
revision identifier, Vol.3-34-13
revision identifier field, Vol.3-34-13
switching to, Vol.3-34-2
switching to from other operating modes, Vol.3-34-2
synchronous SMI, Vol.3-34-11
VMX operation
default RSM treatment, Vol.3-34-17
default SMI delivery, Vol.3-34-16
dual-monitor treatment, Vol.3-34-19
overview, Vol.3-34-1
protecting CR4.VMXE, Vol.3-34-18
RSM instruction, Vol.3-34-18
SMM monitor, Vol.3-34-1
SMM VM exits, Vol.3-27-1, Vol.3-34-19
SMM-transfer VMCS, Vol.3-34-19
SMM-transfer VMCS pointer, Vol.3-34-19
VMCS pointer preservation, Vol.3-34-17
VMX-critical state, Vol.3-34-17
SMRAM
caching, Vol.3-34-8
state save map, Vol.3-34-4
structure of, Vol.3-34-3
SMSW instruction, Vol.2-4-630, Vol.3-2-22, Vol.3-25-9
SNaNs
description of, Vol.1-4-15
effect on COMISD and UCOMISD, Vol.1-11-7
encodings, Vol.1-4-5
operating on, Vol.1-4-16
typical uses of, Vol.1-4-15
using in applications, Vol.1-4-16
SNaN, compatibility, IA-32 processors, Vol.3-22-8, Vol.3-22-13
Snooping mechanism, Vol.3-11-6
Software compatibility, Vol.1-1-5
Software controlled clock
modulation control bits, Vol.3-14-23
power consumption, Vol.3-14-19, Vol.3-14-23
Software interrupts, Vol.3-6-4
Software-controlled bus locking, Vol.3-8-3
SP register, Vol.1-3-12
Speculative execution, Vol.1-2-8, Vol.1-2-10
SpeedStep technology, Vol.2-3-206
Spin-wait loops
programming with PAUSE instruction, Vol.1-11-12
Split pages, Vol.3-22-14
Spurious interrupt, local APIC, Vol.3-10-32
SQRTPD instruction, Vol.1-11-6
SQRTPD- Square Root of Double-Precision Floating-Point Values,
Vol.2-4-656
SQRTPD—Square Root of Double-Precision Floating-Point Values,
Vol.2-4-632
SQRTPS instruction, Vol.1-10-8
SQRTPS- Square Root of Single-Precision Floating-Point Values,
Vol.2-4-635
SQRTSD - Compute Square Root of Scalar Double-Precision Floating-Point
Value, Vol.2-4-638, Vol.2-4-656
SQRTSD instruction, Vol.1-11-6
Index-30 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
SQRTSS - Compute Square Root of Scalar Single-Precision Floating-Point
Value, Vol.2-4-640
SQRTSS instruction, Vol.1-10-8
Square root, Fx87 PU operation, Vol.2-3-385
SS register, Vol.1-3-13, Vol.1-3-14, Vol.1-6-1, Vol.2-3-521, Vol.2-4-36,
Vol.2-4-386
SSE extensions
128-bit packed single-precision data type, Vol.1-10-5
64-bit mode, Vol.1-10-3
64-bit SIMD integer instructions, Vol.1-10-11
branching on arithmetic operations, Vol.1-11-24
cacheability control instructions, Vol.1-10-12
cacheability hint instructions, Vol.1-11-25
cacheability instruction encodings, Vol.1-B-48
caller-save requirement for procedure and function calls, Vol.1-11-24
checking for SSE and SSE2 support, Vol.1-11-19
checking for with CPUID, Vol.3-13-2
checking support for FXSAVE/FXRSTOR, Vol.3-13-2
comparison instructions, Vol.1-10-9
compatibility mode, Vol.1-10-3
compatibility of SIMD and x87 FPU floating-point data types,
Vol.1-11-22
conversion instructions, Vol.1-10-11
CPUID feature flag, Vol.3-9-8
CPUID flag, Vol.2-3-210
data movement instructions, Vol.1-10-7
data types, Vol.1-10-5, Vol.1-12-1
denormal operand exception (#D), Vol.1-11-15
denormals-are-zeros mode, Vol.1-10-5
divide by zero exception (#Z), Vol.1-11-15
EM flag, Vol.3-2-16
emulation of, Vol.3-13-6
exceptions, Vol.1-11-13
facilities for automatic saving of state, Vol.3-13-6, Vol.3-13-7
floating-point encodings, Vol.1-B-42
floating-point format, Vol.1-4-11
flush-to-zero mode, Vol.1-10-4
generating SIMD FP exceptions, Vol.1-11-16
guidelines for using, Vol.1-11-19
handling combinations of masked and unmasked exceptions,
Vol.1-11-18
handling masked exceptions, Vol.1-11-16
handling SIMD floating-point exceptions in software, Vol.1-11-18
handling unmasked exceptions, Vol.1-11-17, Vol.1-11-18
inexact result exception (#P), Vol.1-11-16
initialization, Vol.3-9-8
instruction encodings, Vol.1-B-42
instruction prefixes, effect on SSE and SSE2 instructions, Vol.1-11-25
instruction set, Vol.1-5-14, Vol.1-10-6
integer instruction encodings, Vol.1-B-46
interaction of SIMD and x87 FPU floating-point exceptions,
Vol.1-11-18
interaction of SSE and SSE2 instructions with x87 FPU and MMX
instructions, Vol.1-11-21
interfacing with SSE and SSE2 procedures and functions, Vol.1-11-23
intermixing packed and scalar floating-point
and 128-bit SIMD integer instructions
and data ....................., Vol.1-11-22
introduction, Vol.1-2-3
introduction of into the IA-32 architecture, Vol.3-22-3
invalid operation exception (#I), Vol.1-11-14
logical instructions, Vol.1-10-9
masked responses to invalid arithmetic operations, Vol.1-11-14
memory ordering encodings, Vol.1-B-48
memory ordering instruction, Vol.1-10-14
MMX technology compatibility, Vol.1-10-5
MXCSR register, Vol.1-10-3
MXCSR state management instructions, Vol.1-10-12
non-temporal data, operating on, Vol.1-10-12
numeric overflow exception (#O), Vol.1-11-15
numeric underflow exception (#U), Vol.1-11-16
overview, Vol.1-10-1
INDEX
packed 128-Bit SIMD data types, Vol.1-4-8
packed and scalar floating-point instructions, Vol.1-10-6
programming environment, Vol.1-10-2
providing exception handlers for, Vol.3-13-4, Vol.3-13-5
providing operating system support for, Vol.3-13-1
QNaN floating-point indefinite, Vol.1-4-17
restoring SSE and SSE2 state, Vol.1-11-20
REX prefixes, Vol.1-10-3
saving and restoring state, Vol.3-13-6
saving SSE and SSE2 state, Vol.1-11-20
saving state on task, context switches, Vol.3-13-6
saving XMM register state on a procedure or function call, Vol.1-11-23
shuffle instructions, Vol.1-10-9
SIMD floating-point exception conditions, Vol.1-11-14
SIMD floating-point exception cross reference, Vol.1-C-3
SIMD Floating-point exception (#XM), Vol.3-6-48
SIMD floating-point exception (#XM), Vol.1-11-17, Vol.1-11-18
SIMD floating-point exceptions, Vol.1-11-13
SIMD floating-point mask and flag bits, Vol.1-10-4
SIMD floating-point rounding control field, Vol.1-10-4
SSE and SSE2 conversion instruction chart, Vol.1-11-9
SSE feature flag, CPUID instruction, Vol.1-11-19
SSE2 compatibility, Vol.1-10-5
system programming, Vol.1-13-18
unpack instructions, Vol.1-10-9
updating MMX technology routines
using128-bit SIMD integer instructions, Vol.1-11-24
using TS flag to control saving of state, Vol.3-13-7
x87 FPU compatibility, Vol.1-10-5
XMM registers, Vol.1-10-3
SSE feature flag
CPUID instruction, Vol.3-13-2
SSE feature flag, CPUID instruction, Vol.1-11-19, Vol.1-12-5
SSE instructions
descriptions of, Vol.1-10-6
SIMD floating-point exception cross-reference, Vol.1-C-3
summary of, Vol.1-5-14
SSE2 extensions
128-bit packed single-precision
data type, Vol.1-11-3
128-bit packed single-precision data type, Vol.1-12-1
128-bit SIMD integer instruction
extensions, Vol.1-11-11
64-bit and 128-bit SIMD integer instructions, Vol.1-11-10
64-bit mode, Vol.1-11-3
arithmetic instructions, Vol.1-11-6
branch hints, Vol.1-11-13
branching on arithmetic operations, Vol.1-11-24
cacheability control instructions, Vol.1-11-12
cacheability hint instructions, Vol.1-11-25
cacheability instruction encodings, Vol.1-B-58
caller-save requirement for procedure and function calls, Vol.1-11-24
checking for SSE and SSE2 support, Vol.1-11-19
checking for with CPUID, Vol.3-13-2
checking support for FXSAVE/FXRSTOR, Vol.3-13-2
comparison instructions, Vol.1-11-7
compatibility mode, Vol.1-11-3
compatibility of SIMD and x87 FPU floating-point data types,
Vol.1-11-22
conversion instructions, Vol.1-11-9
CPUID feature flag, Vol.3-9-8
CPUID flag, Vol.2-3-210
data movement instructions, Vol.1-11-5
data types, Vol.1-11-3, Vol.1-12-1
denormal operand exception (#D), Vol.1-11-15
denormals-are-zero mode, Vol.1-11-3
divide by zero exception (#Z), Vol.1-11-15
EM flag, Vol.3-2-16
emulation of, Vol.3-13-6
exceptions, Vol.1-11-13
facilities for automatic saving of state, Vol.3-13-6, Vol.3-13-7
floating-point encodings, Vol.1-B-49
floating-point format, Vol.1-4-11
generating SIMD floating-point exceptions, Vol.1-11-16
guidelines for using, Vol.1-11-19
handling combinations of masked and unmasked exceptions,
Vol.1-11-18
handling masked exceptions, Vol.1-11-16
handling SIMD floating-point exceptions in software, Vol.1-11-18
handling unmasked exceptions, Vol.1-11-17, Vol.1-11-18
inexact result exception (#P), Vol.1-11-16
initialization, Vol.3-9-8
initialization of, Vol.1-11-20
instruction prefixes, effect on SSE and SSE2 instructions, Vol.1-11-25
instruction set, Vol.1-5-17
instructions, Vol.1-11-4, Vol.1-12-2, Vol.1-12-6
integer instruction encodings, Vol.1-B-54
interaction of SIMD and x87 FPU floating-point exceptions,
Vol.1-11-18
interaction of SSE and SSE2 instructions with x87 FPU and MMX
instructions, Vol.1-11-21
interfacing with SSE and SSE2 procedures and functions, Vol.1-11-23
intermixing packed and scalar floating-point and 128-bit SIMD integer
instructions and data, Vol.1-11-22
introduction of into the IA-32 architecture, Vol.3-22-3
invalid operation exception (#I), Vol.1-11-14
logical instructions, Vol.1-11-7
masked responses to invalid arithmetic operations, Vol.1-11-14
memory ordering instructions, Vol.1-11-12
MMX technology compatibility, Vol.1-11-3
numeric overflow exception (#O), Vol.1-11-15
numeric underflow exception (#U), Vol.1-11-16
overview of, Vol.1-11-1
packed 128-Bit SIMD data types, Vol.1-4-8
packed and scalar floating-point instructions, Vol.1-11-4
programming environment, Vol.1-11-2
providing exception handlers for, Vol.3-13-4, Vol.3-13-5
providing operating system support for, Vol.3-13-1
QNaN floating-point indefinite, Vol.1-4-17
restoring SSE and SSE2 state, Vol.1-11-20
REX prefixes, Vol.1-11-3
saving and restoring state, Vol.3-13-6
saving SSE and SSE2 state, Vol.1-11-20
saving state on task, context switches, Vol.3-13-6
saving XMM register state on a procedure or function call, Vol.1-11-23
shuffle instructions, Vol.1-11-7
SIMD floating-point exception conditions, Vol.1-11-14
SIMD floating-point exception cross reference, Vol.1-C-5
SIMD Floating-point exception (#XM), Vol.3-6-48
SIMD floating-point exception (#XM), Vol.1-11-17, Vol.1-11-18
SIMD floating-point exceptions, Vol.1-11-13
SSE and SSE2 conversion instruction chart, Vol.1-11-9
SSE compatibility, Vol.1-11-3
SSE2 feature flag, CPUID instruction, Vol.1-11-19
system programming, Vol.1-13-18
unpack instructions, Vol.1-11-7
updating MMX technology routines using 128-bit SIMD integer
instructions, Vol.1-11-24
using TS flag to control saving state, Vol.3-13-7
writing applications with, Vol.1-11-19
x87 FPU compatibility, Vol.1-11-3
SSE2 feature flag
CPUID instruction, Vol.3-13-2
SSE2 feature flag, CPUID instruction, Vol.1-11-19, Vol.1-12-5
SSE2 instructions
descriptions of, Vol.1-11-4, Vol.1-12-2, Vol.1-12-6
SIMD floating-point exception cross-reference, Vol.1-C-5
summary of, Vol.1-5-17
SSE3
CPUID flag, Vol.2-3-206
SSE3 extensions
64-bit mode, Vol.1-12-1
asymmetric processing, Vol.1-12-1
checking for with CPUID, Vol.3-13-2
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -31
INDEX
compatibility mode, Vol.1-12-1
CPUID feature flag, Vol.3-9-8
CPUID flag, Vol.2-3-206
DNA exceptions, Vol.1-12-9
EM flag, Vol.3-2-16
emulation, Vol.1-12-10
emulation of, Vol.3-13-6
enabling support in a system executive, Vol.1-12-5, Vol.1-12-18
event mgmt instruction encodings, Vol.1-B-59
example verifying SS3 support, Vol.3-8-43, Vol.3-8-47, Vol.3-14-2
exceptions, Vol.1-12-9
facilities for automatic saving of state, Vol.3-13-6, Vol.3-13-7
floating-point instruction encodings, Vol.1-B-59
guideline for packed addition/subtraction instructions, Vol.1-12-6
horizontal addition/subtraction instructions, Vol.1-12-4
horizontal processing, Vol.1-12-1
initialization, Vol.3-9-8
instruction that addresses cache line splits, Vol.1-5-20
instruction that improves X87-FP integer conversion, Vol.1-5-20
instructions for horizontal addition/subtraction, Vol.1-5-21
instructions for packed addition/subtraction, Vol.1-5-21
instructions that enhance LOAD/MOVE/DUPLICATE, Vol.1-5-21
instructions that improve synchronization between agents, Vol.1-5-21
integer instruction encodings, Vol.1-B-60
introduction of into the IA-32 architecture, Vol.3-22-3
LOAD/MOVE/DUPLICATE enhancement instructions, Vol.1-12-3
MMX technology compatibility, Vol.1-12-1
numeric error flag and IGNNE#, Vol.1-12-9
packed addition/subtraction instructions, Vol.1-12-4
programming environment, Vol.1-12-1
providing exception handlers for, Vol.3-13-4, Vol.3-13-5
providing operating system support for, Vol.3-13-1
REX prefixes, Vol.1-12-1
saving and restoring state, Vol.3-13-6
saving state on task, context switches, Vol.3-13-6
SIMD floating-point exception cross reference, Vol.1-C-7, Vol.1-C-8
specialized 120-bit load instruction, Vol.1-12-3
SSE compatibility, Vol.1-12-1
SSE2 compatibility, Vol.1-12-1
system programming, Vol.1-13-18
using TS flag to control saving of state, Vol.3-13-7
x87 FPU compatibility, Vol.1-12-1
SSE3 feature flag
CPUID instruction, Vol.3-13-2
SSE3 instructions
descriptions of, Vol.1-12-2
SIMD floating-point exception
cross-reference, Vol.1-C-7, Vol.1-C-8
summary of, Vol.1-5-20
SSSE3 extensions, Vol.1-B-60, Vol.1-B-66, Vol.1-B-73
64-bit mode, Vol.1-12-1
asymmetric processing, Vol.1-12-1
checking for support, Vol.1-12-9
compatibility, Vol.1-12-1
compatibility mode, Vol.1-12-1
CPUID flag, Vol.2-3-206
data types, Vol.1-12-1
DNA exceptions, Vol.1-12-9
emulation, Vol.1-12-10
enabling support in a system executive, Vol.1-12-9
exceptions, Vol.1-12-9
horizontal add/subtract instructions, Vol.1-12-7
horizontal processing, Vol.1-12-1
MMX technology compatibility, Vol.1-12-1
multiply and add packed instructions, Vol.1-12-8
numeric error flag and IGNNE#, Vol.1-12-9
packed absolute value instructions, Vol.1-12-7
packed align instruction, Vol.1-12-8
packed multiply high instructions, Vol.1-12-8
packed shuffle instruction, Vol.1-12-8
programming environment, Vol.1-12-1
SSSE2 compatibility, Vol.1-12-1
Index-32 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
x87 FPU compatibility, Vol.1-12-1
SSSE3 instructions
descriptions of, Vol.1-12-6
summary of, Vol.1-5-21
Stack
64-bit mode, Vol.1-3-5, Vol.1-6-4
64-bit mode behavior, Vol.1-6-14
address-size attribute, Vol.1-6-3
alignment, Vol.1-6-2
alignment of stack pointer, Vol.1-6-2
current stack, Vol.1-6-1, Vol.1-6-3
description of, Vol.1-6-1
EIP register (return instruction pointer), Vol.1-6-3
maximum size, Vol.1-6-1
number allowed, Vol.1-6-1
overview of, Vol.1-3-4
passing parameters on, Vol.1-6-5
popping values from, Vol.1-6-1
procedure linking information, Vol.1-6-3
pushing values on, Vol.1-6-1
return instruction pointer, Vol.1-6-3
SS register, Vol.1-6-1
stack segment, Vol.1-3-14, Vol.1-6-1
stack-frame base pointer, EBP register, Vol.1-6-3
switching
on calls to interrupt and exception handlers, Vol.1-6-11
on inter-privilege level calls, Vol.1-6-8, Vol.1-6-12
privilege levels, Vol.1-6-7
width, Vol.1-6-2
Stack fault exception (#SS), Vol.3-6-36
Stack fault, x87 FPU, Vol.3-22-8, Vol.3-22-12
Stack pointers
privilege level 0, 1, and 2 stacks, Vol.3-7-5
size of, Vol.3-3-11
Stack segments
paging of, Vol.3-2-6
privilege level check when loading SS register, Vol.3-5-10
size of stack pointer, Vol.3-3-11
Stack switching
exceptions/interrupts when switching stacks, Vol.3-6-7
IA-32e mode, Vol.3-6-18
inter-privilege level calls, Vol.3-5-17
Stack-fault exception (#SS), Vol.3-22-33
Stacks
error code pushes, Vol.3-22-31
faults, Vol.3-6-36
for privilege levels 0, 1, and 2, Vol.3-5-17
interlevel RET/IRET
from a 16-bit interrupt or call gate, Vol.3-22-32
interrupt stack table, 64-bit mode, Vol.3-6-19
management of control transfers for
16- and 32-bit procedure calls, Vol.3-21-4
operation on pushes and pops, Vol.3-22-31
pointers to in TSS, Vol.3-7-5
stack switching, Vol.3-5-17, Vol.3-6-18
usage on call to exception
or interrupt handler, Vol.3-22-32
Stack, pushing values on, Vol.2-4-511
Stack, x87 FPU
stack fault, Vol.1-8-6
stack overflow and underflow exception (#IS), Vol.1-8-4, Vol.1-8-27
Status flags
EFLAGS register, Vol.1-3-16, Vol.1-8-6, Vol.1-8-7, Vol.1-8-20
Status flags, EFLAGS register, Vol.2-3-151, Vol.2-3-153, Vol.2-3-323,
Vol.2-3-328, Vol.2-3-486, Vol.2-4-597, Vol.2-4-679
STC instruction, Vol.1-3-16, Vol.1-7-21, Vol.2-4-643
STD instruction, Vol.1-3-17, Vol.1-7-21, Vol.2-4-644
Stepping information, Vol.2-3-214
Stepping information, following processor initialization or reset, Vol.3-9-5
STI instruction, Vol.1-7-22, Vol.1-18-3, Vol.2-4-645, Vol.3-6-7
Sticky bits, Vol.1-8-5
STMXCSR instruction, Vol.1-10-12, Vol.1-11-24, Vol.2-4-647
INDEX
Store buffer
caching terminology, Vol.3-11-5
characteristics of, Vol.3-11-4
description of, Vol.3-11-5, Vol.3-11-20
in IA-32 processors, Vol.3-22-33
location of, Vol.3-11-1
operation of, Vol.3-11-20
STOS instruction, Vol.1-3-17, Vol.1-7-19, Vol.2-4-550, Vol.2-4-648
STOSB instruction, Vol.2-4-648
STOSD instruction, Vol.2-4-648
STOSQ instruction, Vol.2-4-648
STOSW instruction, Vol.2-4-648
STPCLK# pin, Vol.3-6-3
STR instruction, Vol.2-4-652, Vol.3-2-22, Vol.3-3-16, Vol.3-7-7
Streaming SIMD extensions 2 (see SSE2 extensions)
Streaming SIMD extensions (see SSE extensions)
String data type, Vol.1-4-8
String instructions, Vol.2-3-169, Vol.2-3-451, Vol.2-3-539, Vol.2-4-107,
Vol.2-4-176, Vol.2-4-592, Vol.2-4-648
Strong uncached (UC) memory type
description of, Vol.3-11-6
effect on memory ordering, Vol.3-8-16
use of, Vol.3-9-8, Vol.3-11-8
ST(0), top-of-stack register, Vol.1-8-3
Sub C-state, Vol.3-14-18
SUB instruction, Vol.1-7-8, Vol.2-3-24, Vol.2-3-281, Vol.2-3-537,
Vol.2-4-654, Vol.3-8-3
SUBPD- Subtract Packed Double Precision Floating-Point Values,
Vol.2-4-656
SUBPD- Subtract Packed Double-Precision Floating-Point Values,
Vol.2-4-656
SUBPS- Subtract Packed Single-Precision Floating-Point Values,
Vol.2-4-659
SUBSD- Subtract Scalar Double-Precision Floating-Point Values,
Vol.2-4-662
SUBSS- Subtract Scalar Single-Precision Floating-Point Values,
Vol.2-4-664
Superscalar microarchitecture
P6 family microarchitecture, Vol.1-2-2
P6 family processors, Vol.1-2-7
Pentium 4 processor, Vol.1-2-9
Pentium Pro processor, Vol.1-2-2
Pentium processor, Vol.1-2-2
Supervisor mode
description of, Vol.3-5-28
U/S (user/supervisor) flag, Vol.3-5-28
SVR (spurious-interrupt vector register), local APIC, Vol.3-10-8,
Vol.3-22-27
SWAPGS instruction, Vol.2-4-666, Vol.3-2-7, Vol.3-31-15
SYSCALL instruction, Vol.2-4-668, Vol.3-2-7, Vol.3-5-22, Vol.3-31-15
SYSENTER instruction, Vol.2-4-670, Vol.3-3-9, Vol.3-5-10, Vol.3-5-20,
Vol.3-5-21, Vol.3-31-15, Vol.3-31-16
CPUID flag, Vol.2-3-209
SYSENTER_CS_MSR, Vol.3-5-21
SYSENTER_EIP_MSR, Vol.3-5-21
SYSENTER_ESP_MSR, Vol.3-5-21
SYSEXIT instruction, Vol.2-4-673, Vol.3-3-9, Vol.3-5-10, Vol.3-5-20,
Vol.3-5-21, Vol.3-31-15, Vol.3-31-16
CPUID flag, Vol.2-3-209
SYSRET instruction, Vol.2-4-676, Vol.3-2-7, Vol.3-5-22, Vol.3-31-15
System
architecture, Vol.3-2-1, Vol.3-2-2
data structures, Vol.3-2-2
instructions, Vol.3-2-7, Vol.3-2-20
registers in IA-32e mode, Vol.3-2-7
registers, introduction to, Vol.3-2-6
segment descriptor, layout of, Vol.3-5-2
segments, paging of, Vol.3-2-6
System management mode (see SMM)
System programming
MMX technology, Vol.3-12-1
SSE/SSE2/SSE3 extensions, Vol.1-13-18
virtualization of resources, Vol.3-32-1
System-management mode (see SMM)
T
T (debug trap) flag, TSS, Vol.3-7-5
Tangent, x87 FPU operation, Vol.1-8-21, Vol.2-3-371
Task gate, Vol.1-6-13
Task gates
descriptor, Vol.3-7-8
executing a task, Vol.3-7-2
handling a virtual-8086 mode interrupt or exception through,
Vol.3-20-14
IA-32e mode, Vol.3-2-5
in IDT, Vol.3-6-10
introduction for IA-32e, Vol.3-2-4
introduction to, Vol.3-2-4, Vol.3-2-5
layout of, Vol.3-6-10
referencing of TSS descriptor, Vol.3-6-14
Task management, Vol.3-7-1
data structures, Vol.3-7-3
mechanism, description of, Vol.3-7-2
Task register, Vol.1-3-4, Vol.3-3-16
description of, Vol.3-2-13, Vol.3-7-1, Vol.3-7-7
IA-32e mode, Vol.3-2-13
initializing, Vol.3-9-11
introduction to, Vol.3-2-6
loading, Vol.2-3-547
storing, Vol.2-4-652
Task state segment (see TSS)
Task switch
CALL instruction, Vol.2-3-122
return from nested task, IRET instruction, Vol.2-3-476
Task switching
description of, Vol.3-7-3
exception condition, Vol.3-17-10
operation, Vol.3-7-10
preventing recursive task switching, Vol.3-7-13
saving MMX state on, Vol.3-12-4
saving SSE/SSE2/SSE3 state
on task or context switches, Vol.3-13-6
T (debug trap) flag, Vol.3-7-5
Tasks
address space, Vol.3-7-14
description of, Vol.3-7-1
exception handler, Vol.1-6-13
exception-handler task, Vol.3-6-11
executing, Vol.3-7-2
Intel 286 processor tasks, Vol.3-22-36
interrupt handler, Vol.1-6-13
interrupt-handler task, Vol.3-6-11
interrupts and exceptions, Vol.3-6-14
linking, Vol.3-7-12
logical address space, Vol.3-7-15
management, Vol.3-7-1
mapping linear and physical address space, Vol.3-7-14
restart following an exception or interrupt, Vol.3-6-5
state (context), Vol.3-7-2, Vol.3-7-3
structure, Vol.3-7-1
switching, Vol.3-7-3
task management data structures, Vol.3-7-3
Temporal data, Vol.1-10-12
TEST instruction, Vol.1-7-14, Vol.2-4-679, Vol.2-5-560
TF (trap) flag, EFLAGS register, Vol.1-3-17, Vol.1-A-1, Vol.3-2-9,
Vol.3-6-14, Vol.3-17-9, Vol.3-17-11, Vol.3-17-33,
Vol.3-17-35, Vol.3-17-37, Vol.3-17-39, Vol.3-20-4,
Vol.3-20-19, Vol.3-34-11
Thermal Monitor, Vol.1-2-4
CPUID flag, Vol.2-3-210
Thermal Monitor 2, Vol.2-3-206
CPUID flag, Vol.2-3-206
Thermal monitoring
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -33
INDEX
advanced power management, Vol.3-14-18
automatic, Vol.3-14-20
automatic thermal monitoring, Vol.3-14-19
catastrophic shutdown detector, Vol.3-14-19, Vol.3-14-20
clock-modulation bits, Vol.3-14-23
C-state, Vol.3-14-18
detection of facilities, Vol.3-14-24
Enhanced Intel SpeedStep Technology, Vol.3-14-1
IA32_APERF MSR, Vol.3-14-2
IA32_MPERF MSR, Vol.3-14-1
IA32_THERM_INTERRUPT MSR, Vol.3-14-25
IA32_THERM_STATUS MSR, Vol.3-14-25
interrupt enable/disable flags, Vol.3-14-22
interrupt mechanisms, Vol.3-14-19
MWAIT extensions for, Vol.3-14-18
on die sensors, Vol.3-14-19, Vol.3-14-24
overview of, Vol.3-14-1, Vol.3-14-19
performance state transitions, Vol.3-14-21
sensor interrupt, Vol.3-10-1
setting thermal thresholds, Vol.3-14-25
software controlled clock modulation, Vol.3-14-19, Vol.3-14-23
status flags, Vol.3-14-21
status information, Vol.3-14-21, Vol.3-14-22
stop clock mechanism, Vol.3-14-19
thermal monitor 1 (TM1), Vol.3-14-20
thermal monitor 2 (TM2), Vol.3-14-20
TM flag, CPUID instruction, Vol.3-14-24
Thermal status bit, Vol.3-14-25, Vol.3-14-28
Thermal status log bit, Vol.3-14-25, Vol.3-14-29
Thermal threshold #1 log, Vol.3-14-26, Vol.3-14-29
Thermal threshold #1 status, Vol.3-14-26, Vol.3-14-29
Thermal threshold #2 log, Vol.3-14-26, Vol.3-14-29
Thermal threshold #2 status, Vol.3-14-26, Vol.3-14-29
THERMTRIP# interrupt enable bit, Vol.3-14-27, Vol.3-14-30
thread timeout indicator, Vol.3-16-3, Vol.3-16-7, Vol.3-16-10,
Vol.3-16-13, Vol.3-16-15
Threshold #1 interrupt enable bit, Vol.3-14-27, Vol.3-14-30
Threshold #1 value, Vol.3-14-27, Vol.3-14-30
Threshold #2 interrupt enable, Vol.3-14-27, Vol.3-14-30
Threshold #2 value, Vol.3-14-27, Vol.3-14-30
TI (table indicator) flag, segment selector, Vol.3-3-7
Time Stamp Counter, Vol.2-3-209
Timer, local APIC, Vol.3-10-16
Time-stamp counter
counting clockticks, Vol.3-18-105
description of, Vol.3-17-40
IA32_TIME_STAMP_COUNTER MSR, Vol.3-17-40
RDTSC instruction, Vol.3-17-40
reading, Vol.3-2-24
software drivers for, Vol.3-18-120
TSC flag, Vol.3-17-40
TSD flag, Vol.3-17-40
Time-stamp counter, reading, Vol.2-4-545, Vol.2-4-547
TLB entry, invalidating (flushing), Vol.2-3-471
TLBs
description of, Vol.3-11-1, Vol.3-11-5
flushing, Vol.3-11-19
invalidating (flushing), Vol.3-2-23
relationship to PGE flag, Vol.3-22-18
relationship to PSE flag, Vol.3-11-20
virtual TLBs, Vol.3-32-3
TM1 and TM2
See: thermal monitoring, Vol.3-14-20
TMR
Trigger Mode Register, Vol.3-10-31, Vol.3-10-38, Vol.3-10-41,
Vol.3-10-47
TMR (Trigger Mode Register), local APIC, Vol.3-10-29
TOP (stack TOP) field
x87 FPU status word, Vol.1-8-2, Vol.1-9-9
TPR
Task Priority Register, Vol.3-10-38, Vol.3-10-41
TR register, Vol.1-3-6
Index-34 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
TR (trace message enable) flag
DEBUGCTLMSR MSR, Vol.3-17-11, Vol.3-17-33, Vol.3-17-36,
Vol.3-17-37, Vol.3-17-39
Trace cache, Vol.1-2-10, Vol.3-11-4, Vol.3-11-5
Transcendental instruction accuracy, Vol.1-8-22, Vol.3-22-7, Vol.3-22-14
Translation lookaside buffer (see TLB)
Trap gate, Vol.1-6-10
Trap gates
difference between interrupt and trap gates, Vol.3-6-14
for 16-bit and 32-bit code modules, Vol.3-21-1
handling a virtual-8086 mode interrupt or exception through,
Vol.3-20-12
in IDT, Vol.3-6-10
introduction for IA-32e, Vol.3-2-4
introduction to, Vol.3-2-4, Vol.3-2-5
layout of, Vol.3-6-10
Traps
description of, Vol.3-6-5
restarting a program or task after, Vol.3-6-5
Truncation
description of, Vol.1-4-18
with SSE-SSE2 conversion instructions, Vol.1-4-18
Trusted Platform Module, Vol.1-6-4, Vol.1-6-5
TS (task switched) flag
CR0 control register, Vol.3-2-15, Vol.3-2-22, Vol.3-6-27, Vol.3-12-1,
Vol.3-13-3, Vol.3-13-7
TS (task switched) flag, CR0 register, Vol.2-3-145
TSD (time-stamp counter disable) flag
CR4 control register, Vol.3-2-17, Vol.3-5-24, Vol.3-17-41,
Vol.3-22-17
TSS
16-bit TSS, structure of, Vol.3-7-15
32-bit TSS, structure of, Vol.3-7-3
64-bit mode, Vol.3-7-16
CR3 control register (PDBR), Vol.3-7-4, Vol.3-7-14
description of, Vol.3-2-4, Vol.3-2-5, Vol.3-7-1, Vol.3-7-3
EFLAGS register, Vol.3-7-4
EFLAGS.NT, Vol.3-7-12
EIP, Vol.3-7-4
executing a task, Vol.3-7-2
floating-point save area, Vol.3-22-11
format in 64-bit mode, Vol.3-7-16
general-purpose registers, Vol.3-7-4
IA-32e mode, Vol.3-2-5
initialization for multitasking, Vol.3-9-10
interrupt stack table, Vol.3-7-17
invalid TSS exception, Vol.3-6-31
IRET instruction, Vol.3-7-12
I/O map base, Vol.1-18-4
I/O map base address field, Vol.3-7-5, Vol.3-22-28
I/O permission bit map, Vol.1-18-4, Vol.3-7-5, Vol.3-7-17
LDT segment selector field, Vol.3-7-4, Vol.3-7-14
link field, Vol.3-6-14
order of reads/writes to, Vol.3-22-28
pointed to by task-gate descriptor, Vol.3-7-8
previous task link field, Vol.3-7-4, Vol.3-7-12, Vol.3-7-13
privilege-level 0, 1, and 2 stacks, Vol.3-5-17
referenced by task gate, Vol.3-6-14
saving state of EFLAGS register, Vol.1-3-15
segment registers, Vol.3-7-4
T (debug trap) flag, Vol.3-7-5
task register, Vol.3-7-7
using 16-bit TSSs in a 32-bit environment, Vol.3-22-28
virtual-mode extensions, Vol.3-22-28
TSS descriptor
B (busy) flag, Vol.3-7-5
busy flag, Vol.3-7-13
initialization for multitasking, Vol.3-9-10
structure of, Vol.3-7-5, Vol.3-7-6
TSS segment selector
field, task-gate descriptor, Vol.3-7-8
writes, Vol.3-22-28
INDEX
TSS, relationship to task register, Vol.2-4-652
Type
checking, Vol.3-5-5
field, IA32_MTRR_DEF_TYPE MSR, Vol.3-11-22
field, IA32_MTRR_PHYSBASEn MTRR, Vol.3-11-24, Vol.3-11-26
field, segment descriptor, Vol.3-3-10, Vol.3-3-12, Vol.3-3-14,
Vol.3-5-2, Vol.3-5-5
of segment, Vol.3-5-5
TZCNT - Count the Number of Trailing Zero Bits, Vol.2-4-681
USR (user mode) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family
processors), Vol.3-18-3, Vol.3-18-7, Vol.3-18-9, Vol.3-18-10,
Vol.3-18-11, Vol.3-18-19, Vol.3-18-20, Vol.3-18-42,
Vol.3-18-44, Vol.3-18-52, Vol.3-18-53, Vol.3-18-71,
Vol.3-18-73, Vol.3-18-74, Vol.3-18-118
U/S (user/supervisor) flag
page-directory entry, Vol.3-5-1, Vol.3-5-2, Vol.3-5-28
page-table entries, Vol.3-20-8
page-table entry, Vol.3-5-1, Vol.3-5-2, Vol.3-5-28
U
V
UC- (uncacheable) memory type, Vol.3-11-6
UCOMISD - Unordered Compare Scalar Double-Precision Floating-Point
Values and Set EFLAGS, Vol.2-4-683
UCOMISD instruction, Vol.1-11-7, Vol.2-4-681
UCOMISS - Unordered Compare Scalar Single-Precision Floating-Point
Values and Set EFLAGS, Vol.2-4-685
UCOMISS instruction, Vol.1-10-9
UD2 instruction, Vol.1-7-24, Vol.2-4-687, Vol.3-22-4
UE (numeric underflow exception) flag
MXCSR register, Vol.1-11-16
x87 FPU status word, Vol.1-8-5, Vol.1-8-30
UM (numeric underflow exception) mask bit
MXCSR register, Vol.1-11-16
x87 FPU control word, Vol.1-8-7, Vol.1-8-30
Uncached (UC-) memory type, Vol.3-11-8
Uncached (UC) memory type (see Strong uncached (UC) memory type)
Undefined opcodes, Vol.3-22-5
Undefined, format opcodes, Vol.2-3-401
Underflow
FPU exception
(see Numeric underflow exception)
numeric, floating-point, Vol.1-4-14
x87 FPU stack, Vol.1-8-27
Underflow, x87 FPU stack, Vol.1-8-27
Unit mask field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors)
, Vol.3-18-3, Vol.3-18-7, Vol.3-18-9, Vol.3-18-10,
Vol.3-18-11, Vol.3-18-13, Vol.3-18-19, Vol.3-18-20,
Vol.3-18-42, Vol.3-18-44, Vol.3-18-52, Vol.3-18-53,
Vol.3-18-71, Vol.3-18-73, Vol.3-18-74, Vol.3-18-118
Un-normal number, Vol.3-22-9
Unordered values, Vol.2-3-325, Vol.2-3-401, Vol.2-3-403
Unpack instructions
SSE extensions, Vol.1-10-9
SSE2 extensions, Vol.1-11-7
UNPCKHPD instruction, Vol.1-11-8
UNPCKHPD- Unpack and Interleave High Packed Double-Precision
Floating-Point Values, Vol.2-4-688
UNPCKHPS instruction, Vol.1-10-10
UNPCKHPS- Unpack and Interleave High Packed Single-Precision
Floating-Point Values, Vol.2-4-692
UNPCKLPD instruction, Vol.1-11-8
UNPCKLPD- Unpack and Interleave Low Packed Double-Precision
Floating-Point Values, Vol.2-4-696
UNPCKLPS instruction, Vol.1-10-10
UNPCKLPS- Unpack and Interleave Low Packed Single-Precision
Floating-Point Values, Vol.2-4-700
Unsigned integers
description of, Vol.1-4-3
range of, Vol.1-4-3
types, Vol.1-4-3
Unsupported, Vol.1-8-14
floating-point formats, x87 FPU, Vol.1-8-14
x87 FPU instructions, Vol.1-8-25
User mode
description of, Vol.3-5-28
U/S (user/supervisor) flag, Vol.3-5-28
User-defined interrupts, Vol.3-6-1, Vol.3-6-51
V (valid) flag
IA32_MTRR_PHYSMASKn MTRR, Vol.3-11-24, Vol.3-11-26
VALIGND/VALIGNQ- Align Doubleword/Quadword Vectors, Vol.2-4-703,
Vol.2-5-5
Variable-range MTRRs, description of, Vol.3-11-23, Vol.3-11-25
VBLENDMPD- Blend Float64 Vectors Using an OpMask Control, Vol.2-5-9
VCNT (variable range registers count) field, IA32_MTRRCAP MSR,
Vol.3-11-22
VCVTPD2UDQ- Convert Packed Double-Precision Floating-Point Values to
Packed Unsigned Doubleword Integers, Vol.2-5-28
VCVTPS2UDQ- Convert Packed Single Precision Floating-Point Values to
Packed Unsigned Doubleword Integer Values, Vol.2-5-41
VCVTSD2USI- Convert Scalar Double Precision Floating-Point Value to
Unsigned Doubleword Integer, Vol.2-5-54
VCVTSS2USI- Convert Scalar Single-Precision Floating-Point Value to
Unsigned Doubleword Integer, Vol.2-5-55
VCVTTPD2UDQ- Convert with Truncation Packed Double-Precision
Floating-Point Values to Packed Unsigned Doubleword Integers
, Vol.2-5-59
VCVTTPS2UDQ- Convert with Truncation Packed Single-Precision
Floating-Point Values to Packed Unsigned Doubleword Integer
Values, Vol.2-5-64
VCVTTSD2USI- Convert with Truncation Scalar Double-Precision
Floating-Point Value to Unsigned Integer, Vol.2-5-70
VCVTTSS2USI- Convert with Truncation Scalar Single-Precision
Floating-Point Value to Unsigned Integer, Vol.2-5-71
VCVTUDQ2PD- Convert Packed Unsigned Doubleword Integers to Packed
Double-Precision Floating-Point Values, Vol.2-4-703,
Vol.2-5-73
VCVTUDQ2PS- Convert Packed Unsigned Doubleword Integers to Packed
Single-Precision Floating-Point Values, Vol.2-5-75
VCVTUSI2SD- Convert Unsigned Integer to Scalar Double-Precision
Floating-Point Value, Vol.2-5-81
VCVTUSI2SS- Convert Unsigned Integer to Scalar Single-Precision
Floating-Point Value, Vol.2-5-83
Vectors
exceptions, Vol.3-6-1
interrupts, Vol.3-6-1
VERR instruction, Vol.2-5-93, Vol.3-2-23, Vol.3-5-25
Version information, processor, Vol.2-3-190
VERW instruction, Vol.2-5-93, Vol.3-2-23, Vol.3-5-25
VEX, Vol.2-3-3
VEXP2PD—Approximation to the Exponential 2^x of Packed
Double-Precision Floating-Point Values with Less Than 2^-23
Relative Error, Vol.2-5-95
VEXP2PS—Approximation to the Exponential 2^x of Packed
Single-Precision Floating-Point Values with Less Than 2^-23
Relative Error, Vol.2-5-97
VEXTRACTF128- Extract Packed Floating-Point Values, Vol.2-5-99
VEX.B, Vol.2-3-3
VEX.L, Vol.2-3-3, Vol.2-3-4
VEX.mmmmm, Vol.2-3-3
VEX.pp, Vol.2-3-4
VEX.R, Vol.2-3-4
VEX.vvvv, Vol.2-3-3
VEX.W, Vol.2-3-3
VEX.X, Vol.2-3-3
VFMADD132SS/VFMADD213SS/VFMADD231SS - Fused Multiply-Add of
Scalar Single-Precision Floating-Point Values, Vol.2-5-143
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -35
INDEX
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD - Fused
Multiply-Alternating Add/Subtract of Packed Double-Precision
Floating-Point Values, Vol.2-5-146
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS - Fused
Multiply-Alternating Add/Subtract of Packed Single-Precision
Floating-Point Values, Vol.2-5-156
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS - Fused Multiply-Subtract
of Packed Single-Precision Floating-Point Values, Vol.2-5-192
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD - Fused Multiply-Subtract
of Scalar Double-Precision Floating-Point Values, Vol.2-5-199
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS - Fused Multiply-Subtract
of Scalar Single-Precision Floating-Point Values, Vol.2-5-202
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD - Fused
Multiply-Alternating Subtract/Add of Packed Double-Precision
Floating-Point Values, Vol.2-5-165
VFNMADD132PD/VFMADD213PD/VFMADD231PD - Fused Negative
Multiply-Add of Packed Double-Precision Floating-Point Values,
Vol.2-5-205
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS - Fused Negative
Multiply-Add of Packed Single-Precision Floating-Point Values,
Vol.2-5-212
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD - Fused Negative
Multiply-Add of Scalar Double-Precision Floating-Point Values,
Vol.2-5-218
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD - Fused Negative
Multiply-Subtract of Scalar Double-Precision Floating-Point
Values, Vol.2-5-236
VGATHERDPS/VGATHERDPD - Gather Packed Single, Packed Double with
Signed Dword, Vol.2-5-261
VGATHERDPS/VGATHERQPS - Gather Packed SP FP values Using Signed
Dword/Qword Indices, Vol.2-5-256
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QP
D - Sparse Prefetch Packed SP/DP Data Values with Signed
Dword, Signed Qword Indices Using T0 Hint, Vol.2-5-264
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QP
D - Sparse Prefetch Packed SP/DP Data Values with Signed
Dword, Signed Qword Indices Using T1 Hint, Vol.2-5-267
VGATHERQPS/VGATHERQPD -Gather Packed Single, Packed Double with
Signed Qword Indices, Vol.2-5-270
VIF (virtual interrupt) flag
EFLAGS register, Vol.3-2-11, Vol.3-22-5, Vol.3-22-6
VIF (virtual interrupt) flag, EFLAGS register, Vol.1-3-17
VINSERTF128/VINSERTF32x4/VINSERTF64x4- Insert Packed
Floating-Point Values, Vol.2-5-310
VINSERTI128/VINSERTI32x4/VINSERTI64x4- Insert Packed Integer
Values, Vol.2-5-314
VIP (virtual interrupt pending) flag
EFLAGS register, Vol.1-3-17, Vol.3-2-11, Vol.3-22-5, Vol.3-22-6
Virtual 8086 mode
description of, Vol.1-3-17
memory model, Vol.1-3-7, Vol.1-3-8
Virtual Machine Monitor, Vol.1-6-1
Virtual memory, Vol.3-2-6, Vol.3-3-1, Vol.3-3-2
Virtual-8086 mode
8086 emulation, Vol.3-20-1
description of, Vol.3-20-5
emulating 8086 operating system calls, Vol.3-20-18
enabling, Vol.3-20-6
entering, Vol.3-20-8
exception and interrupt handling overview, Vol.3-20-11
exceptions and interrupts, handling through a task gate, Vol.3-20-14
exceptions and interrupts, handling through a trap or interrupt gate,
Vol.3-20-12
handling exceptions and interrupts through a task gate, Vol.3-20-14
interrupts, Vol.3-20-6
introduction to, Vol.3-2-7
IOPL sensitive instructions, Vol.3-20-10
I/O-port-mapped I/O, Vol.3-20-11
leaving, Vol.3-20-9
memory mapped I/O, Vol.3-20-11
native 16-bit mode, Vol.3-21-1
overview of, Vol.3-20-1
Index-36 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
paging of virtual-8086 tasks, Vol.3-20-7
protection within a virtual-8086 task, Vol.3-20-8
special I/O buffers, Vol.3-20-11
structure of a virtual-8086 task, Vol.3-20-7
virtual I/O, Vol.3-20-10
VM flag, EFLAGS register, Vol.3-2-10
Virtual-8086 tasks
paging of, Vol.3-20-7
protection within, Vol.3-20-8
structure of, Vol.3-20-7
Virtualization
debugging facilities, Vol.3-32-1
interrupt vector space, Vol.3-33-3
memory, Vol.3-32-2
microcode update facilities, Vol.3-32-8
operating modes, Vol.3-32-2
page faults, Vol.3-32-5
system resources, Vol.3-32-1
TLBs, Vol.3-32-3
VM
OSs and application software, Vol.3-31-1
programming considerations, Vol.3-31-1
VM entries
basic VM-entry checks, Vol.3-26-2
checking guest state
control registers, Vol.3-26-8
debug registers, Vol.3-26-8
descriptor-table registers, Vol.3-26-11
MSRs, Vol.3-26-8
non-register state, Vol.3-26-12
RIP and RFLAGS, Vol.3-26-11
segment registers, Vol.3-26-9
checks on controls, host-state area, Vol.3-26-2
registers and MSRs, Vol.3-26-6
segment and descriptor-table registers, Vol.3-26-7
VMX control checks, Vol.3-26-2
exit-reason numbers, Vol.1-C-1
loading guest state, Vol.3-26-14
control and debug registers, MSRs, Vol.3-26-15
RIP, RSP, RFLAGS, Vol.3-26-16
segment & descriptor-table registers, Vol.3-26-16
loading MSRs, Vol.3-26-17
failure cases, Vol.3-26-17
VM-entry MSR-load area, Vol.3-26-17
overview of failure conditions, Vol.3-26-1
overview of steps, Vol.3-26-1
VMLAUNCH and VMRESUME, Vol.3-26-1
See also: VMCS, VMM, VM exits
VM exits
architectural state
existing before exit, Vol.3-27-1
updating state before exit, Vol.3-27-1
basic VM-exit information fields, Vol.3-27-4
basic exit reasons, Vol.3-27-4
exit qualification, Vol.3-27-4
exception bitmap, Vol.3-27-1
exceptions (faults, traps, and aborts), Vol.3-25-5
exit-reason numbers, Vol.1-C-1
external interrupts, Vol.3-25-5
handling of exits due to exceptions, Vol.3-31-8
IA-32 faults and VM exits, Vol.3-25-1
INITs, Vol.3-25-5
instructions that cause:
conditional exits, Vol.3-25-2
unconditional exits, Vol.3-25-2
interrupt-window exiting, Vol.3-25-6
non-maskable interrupts (NMIs), Vol.3-25-5
page faults, Vol.3-25-5
reflecting exceptions to guest, Vol.3-31-8
resuming guest after exception handling, Vol.3-31-9
start-up IPIs (SIPIs), Vol.3-25-5
task switches, Vol.3-25-5
INDEX
See also: VMCS, VMM, VM entries
VM (virtual 8086 mode) flag, EFLAGS register, Vol.1-3-17, Vol.2-3-476
VM (virtual-8086 mode) flag
EFLAGS register, Vol.3-2-8, Vol.3-2-10
VMCALL instruction, Vol.1-5-34, Vol.3-30-1
VMCLEAR instruction, Vol.1-5-34, Vol.3-30-1, Vol.3-31-7
VMCS
error numbers, Vol.3-30-29
field encodings, Vol.3-1-6, Vol.1-B-1
16-bit guest-state fields, Vol.1-B-1
16-bit host-state fields, Vol.1-B-2
32-bit control fields, Vol.1-B-1, Vol.1-B-6
32-bit guest-state fields, Vol.1-B-7
32-bit read-only data fields, Vol.1-B-7
64-bit control fields, Vol.1-B-2
64-bit guest-state fields, Vol.1-B-4, Vol.1-B-5
natural-width control fields, Vol.1-B-8
natural-width guest-state fields, Vol.1-B-9
natural-width host-state fields, Vol.1-B-10
natural-width read-only data fields, Vol.1-B-9
format of VMCS region, Vol.3-24-2
guest-state area, Vol.3-24-3, Vol.3-24-4
guest non-register state, Vol.3-24-5
guest register state, Vol.3-24-4
host-state area, Vol.3-24-3, Vol.3-24-8
introduction, Vol.3-24-1
migrating between processors, Vol.3-24-24
software access to, Vol.3-24-24
VMCS data, Vol.3-24-2, Vol.3-25-16
VMCS pointer, Vol.3-24-1, Vol.3-31-2
VMCS region, Vol.3-24-1, Vol.3-31-2
VMCS revision identifier, Vol.3-24-2, Vol.3-25-16
VM-entry control fields, Vol.3-24-3, Vol.3-24-18
entry controls, Vol.3-24-19
entry controls for event injection, Vol.3-24-20
entry controls for MSRs, Vol.3-24-19
VM-execution control fields, Vol.3-24-3, Vol.3-24-8
controls for CR8 accesses, Vol.3-24-13
CR3-target controls, Vol.3-24-13
exception bitmap, Vol.3-24-12
I/O bitmaps, Vol.3-24-12
masks & read shadows CR0 & CR4, Vol.3-24-12
pin-based controls, Vol.3-24-8
processor-based controls, Vol.3-24-9
time-stamp counter offset, Vol.3-24-12
VM-exit control fields, Vol.3-24-3, Vol.3-24-17
exit controls, Vol.3-24-17
exit controls for MSRs, Vol.3-24-18
VM-exit information fields, Vol.3-24-3, Vol.3-24-21
basic exit information, Vol.3-24-21, Vol.1-C-1
basic VM-exit information, Vol.3-24-21
exits due to instruction execution, Vol.3-24-23
exits due to vectored events, Vol.3-24-22
exits occurring during event delivery, Vol.3-24-22
VM-instruction error field, Vol.3-24-23
VM-instruction error field, Vol.3-26-1, Vol.3-30-29
VMREAD instruction, Vol.3-31-2
field encodings, Vol.3-1-6, Vol.1-B-1
VMWRITE instruction, Vol.3-31-2
field encodings, Vol.3-1-6, Vol.1-B-1
VMX-abort indicator, Vol.3-24-2, Vol.3-25-16
See also: VM entries, VM exits, VMM, VMX
VME (virtual-8086 mode extensions) flag, CR4 control register,
Vol.3-2-11, Vol.3-2-16, Vol.3-22-17
VMLAUNCH instruction, Vol.1-5-34, Vol.3-30-1, Vol.3-31-7
VMM, Vol.1-6-1
asymmetric design, Vol.3-31-10
control registers, Vol.3-31-17
CPUID instruction emulation, Vol.3-31-12
debug exceptions, Vol.3-32-1
debugging facilities, Vol.3-32-1
entering VMX root operation, Vol.3-31-4
error handling, Vol.3-31-2
exception bitmap, Vol.3-32-1
external interrupts, Vol.3-33-1
fast instruction set emulator, Vol.3-31-1
index data pairs, usage of, Vol.3-31-11
interrupt handling, Vol.3-33-1
interrupt vectors, Vol.3-33-3
leaving VMX operation, Vol.3-31-4
machine checks, Vol.3-33-8, Vol.3-33-9, Vol.3-33-11
memory virtualization, Vol.3-32-2
microcode update facilities, Vol.3-32-8
multi-processor considerations, Vol.3-31-10
operating modes, Vol.3-31-12
programming considerations, Vol.3-31-1
response to page faults, Vol.3-32-5
root VMCS, Vol.3-31-2
SMI transfer monitor, Vol.3-31-4
steps for launching VMs, Vol.3-31-6
SWAPGS instruction, Vol.3-31-15
symmetric design, Vol.3-31-10
SYSCALL/SYSRET instructions, Vol.3-31-15
SYSENTER/SYSEXIT instructions, Vol.3-31-15
triple faults, Vol.3-33-1
virtual TLBs, Vol.3-32-3
virtual-8086 container, Vol.3-31-1
virtualization of system resources, Vol.3-32-1
VM exits, Vol.3-27-1
VM exits, handling of, Vol.3-31-7
VMCLEAR instruction, Vol.3-31-7
VMCS field width, Vol.3-31-12
VMCS pointer, Vol.3-31-2
VMCS region, Vol.3-31-2
VMCS revision identifier, Vol.3-31-2
VMCS, writing/reading fields, Vol.3-31-2
VM-exit failures, Vol.3-33-8
VMLAUNCH instruction, Vol.3-31-7
VMREAD instruction, Vol.3-31-2
VMRESUME instruction, Vol.3-31-7
VMWRITE instruction, Vol.3-31-2, Vol.3-31-7
VMXOFF instruction, Vol.3-31-4
See also: VMCS, VM entries, VM exits, VMX
VMM software interrupts, Vol.3-33-1
VMPTRLD instruction, Vol.1-5-34, Vol.3-30-1
VMPTRST instruction, Vol.1-5-34, Vol.3-30-1
VMREAD instruction, Vol.1-5-34, Vol.3-30-1, Vol.3-31-2
field encodings, Vol.1-B-1
VMRESUME instruction, Vol.1-5-34, Vol.3-30-1, Vol.3-31-7
VMWRITE instruction, Vol.1-5-34, Vol.3-30-1, Vol.3-31-2, Vol.3-31-7
field encodings, Vol.1-B-1
VMX
A20M# signal, Vol.3-23-4
capability MSRs
overview, Vol.3-23-2, Vol.1-A-1
IA32_VMX_BASIC MSR, Vol.3-24-3, Vol.3-31-2, Vol.3-31-5,
Vol.3-31-6, Vol.3-31-11, Vol.1-35-55, Vol.1-35-66,
Vol.1-35-74, Vol.1-35-119, Vol.1-35-156, Vol.1-35-273,
Vol.1-35-298, Vol.1-35-311, Vol.1-A-1, Vol.1-A-2
IA32_VMX_CR0_FIXED0 MSR, Vol.3-31-4, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-120, Vol.1-35-156,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-311, Vol.1-A-6
IA32_VMX_CR0_FIXED1 MSR, Vol.3-31-4, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-120, Vol.1-35-156,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-311, Vol.1-A-6
IA32_VMX_CR4_FIXED0 MSR, Vol.3-31-4, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-120, Vol.1-35-156,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-311
IA32_VMX_CR4_FIXED1 MSR, Vol.3-31-4, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-75, Vol.1-35-120,
Vol.1-35-157, Vol.1-35-273, Vol.1-35-298, Vol.1-35-312
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -37
INDEX
IA32_VMX_ENTRY_CTLS MSR, Vol.3-31-5, Vol.3-31-6,
Vol.1-35-55, Vol.1-35-66, Vol.1-35-74, Vol.1-35-119,
Vol.1-35-156, Vol.1-35-273, Vol.1-35-298, Vol.1-35-311,
Vol.1-A-2, Vol.1-A-5
IA32_VMX_EXIT_CTLS MSR, Vol.3-31-5, Vol.3-31-6, Vol.1-35-55,
Vol.1-35-66, Vol.1-35-74, Vol.1-35-119, Vol.1-35-156,
Vol.1-35-273, Vol.1-35-298, Vol.1-35-311, Vol.1-A-2,
Vol.1-A-4, Vol.1-A-5
IA32_VMX_MISC MSR, Vol.3-24-6, Vol.3-26-3, Vol.3-26-12,
Vol.3-34-26, Vol.1-35-55, Vol.1-35-66, Vol.1-35-74,
Vol.1-35-119, Vol.1-35-156, Vol.1-35-273, Vol.1-35-298,
Vol.1-35-311, Vol.1-A-5
IA32_VMX_PINBASED_CTLS MSR, Vol.3-31-5, Vol.3-31-6,
Vol.1-35-55, Vol.1-35-66, Vol.1-35-74, Vol.1-35-119,
Vol.1-35-156, Vol.1-35-273, Vol.1-35-298, Vol.1-35-311,
Vol.1-A-2, Vol.1-A-3
IA32_VMX_PROCBASED_CTLS MSR, Vol.3-24-9, Vol.3-31-5,
Vol.3-31-6, Vol.1-35-55, Vol.1-35-66, Vol.1-35-67,
Vol.1-35-74, Vol.1-35-75, Vol.1-35-119, Vol.1-35-120,
Vol.1-35-156, Vol.1-35-157, Vol.1-35-191, Vol.1-35-273,
Vol.1-35-274, Vol.1-35-298, Vol.1-35-311, Vol.1-35-312,
Vol.1-A-2, Vol.1-A-3, Vol.1-A-4, Vol.1-A-8
IA32_VMX_VMCS_ENUM MSR, Vol.1-35-298
CPUID instruction, Vol.3-23-2, Vol.1-A-1
CR4 control register, Vol.3-23-3
CR4 fixed bits, Vol.1-A-6
debugging facilities, Vol.3-32-1
EFLAGS, Vol.3-31-2
entering operation, Vol.3-23-3
entering root operation, Vol.3-31-4
error handling, Vol.3-31-2
guest software, Vol.3-23-1
IA32_FEATURE_CONTROL MSR, Vol.3-23-3
INIT# signal, Vol.3-23-4
instruction set, Vol.1-5-34, Vol.3-23-2
introduction, Vol.1-2-21, Vol.3-23-1
memory virtualization, Vol.3-32-2
microcode update facilities, Vol.3-25-9, Vol.3-32-8
non-root operation, Vol.3-23-1
event blocking, Vol.3-25-10
instruction changes, Vol.3-25-6
overview, Vol.3-25-1
task switches not allowed, Vol.3-25-10
see VM exits
operation restrictions, Vol.3-23-3
root operation, Vol.3-23-1
SMM
CR4.VMXE reserved, Vol.3-34-18
overview, Vol.3-34-1
RSM instruction, Vol.3-34-18
VMCS pointer, Vol.3-34-17
VMX-critical state, Vol.3-34-17
testing for support, Vol.3-23-2
Virtual machine monitor (VMM), Vol.1-2-21
virtual TLBs, Vol.3-32-3
virtualization, Vol.1-2-21
virtual-machine control structure (VMCS), Vol.3-23-2
virtual-machine monitor (VMM), Vol.3-23-1
vitualization of system resources, Vol.3-32-1
VM entries and exits, Vol.3-23-1
VM exits, Vol.3-27-1
VMCS pointer, Vol.3-23-2
VMM life cycle, Vol.3-23-2
VMXOFF instruction, Vol.3-23-3
VMXON instruction, Vol.3-23-3
VMXON pointer, Vol.3-23-3
VMXON region, Vol.3-23-3
See also:VMM, VMCS, VM entries, VM exits
VMXOFF instruction, Vol.1-5-34, Vol.3-23-3, Vol.3-30-1
VMXON instruction, Vol.1-5-34, Vol.3-23-3, Vol.3-30-1
VPBLENDMD- Blend Int32 Vectors Using an OpMask Control, Vol.2-5-325
VPBROADCASTM—Broadcast Mask to Vector Register, Vol.2-5-19
Index-38 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
VPCMPD/VPCMPUD - Compare Packed Integer Values into Mask,
Vol.2-5-342
VPCMPQ/VPCMPUQ - Compare Packed Integer Values into Mask,
Vol.2-5-345
VPCONFLICTD/Q - Detect Conflicts Within a Vector of Packed Dword,
Packed Qword Values into Dense Memory/Register, Vol.2-5-95
VPERM2I128 - Permute Integer Values, Vol.2-5-360
VPERMILPD- Permute Double-Precision Floating-Point Values,
Vol.2-5-371
VPERMILPS- Permute Single-Precision Floating-Point Values, Vol.2-5-376
VPERMPD - Permute Double-Precision Floating-Point Elements,
Vol.2-5-360
VPGATHERDD/VPGATHERDQ- Gather Packed Dword, Packed Qword with
Signed Dword Indices, Vol.2-5-277
VPGATHERDQ/VPGATHERQQ - Gather Packed Qword values Using Signed
Dword/Qword Indices, Vol.2-5-280
VPGATHERQD/VPGATHERQQ- Gather Packed Dword, Packed Qword with
Signed Qword Indices, Vol.2-5-285
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword,
Packed Qword Values, Vol.2-5-394
VPMOVDB/VPMOVSDB/VPMOVUSDB - Down Convert DWord to Byte,
Vol.2-5-418
VPMOVDW/VPMOVSDW/VPMOVUSDW - Down Convert DWord to Word,
Vol.2-5-422
VPMOVQB/VPMOVSQB/VPMOVUSQB - Down Convert QWord to Byte,
Vol.2-5-406
VPMOVQD/VPMOVSQD/VPMOVUSQD - Down Convert QWord to DWord,
Vol.2-5-414
VPMOVQW/VPMOVSQW/VPMOVUSQW - Down Convert QWord to Word,
Vol.2-5-410
VPTERNLOGD/VPTERNLOGQ - Bitwise Ternary Logic, Vol.2-5-460
VPTESTMD/VPTESTMQ - Logical AND and Set Mask, Vol.2-5-463
VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision
Floating-Point Values with Less Than 2^-28 Relative Error,
Vol.2-5-493
VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision
Floating-Point Values with Less Than 2^-28 Relative Error,
Vol.2-5-497
VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision
Floating-Point Value with Less Than 2^-28 Relative Error,
Vol.2-5-495
VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision
Floating-Point Value with Less Than 2^-28 Relative Error,
Vol.2-5-499
VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed
Double-Precision Floating-Point Values with Less Than 2^-28
Relative Error, Vol.2-5-529
VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed
Single-Precision Floating-Point Values with Less Than 2^-28
Relative Error, Vol.2-5-533
VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar
Double-Precision Floating-Point Value with Less Than 2^-28
Relative Error, Vol.2-5-531
VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar
Single-Precision Floating-Point Value with Less Than 2^-28
Relative Error, Vol.2-5-535
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF
0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
Dword, Signed Qword Indices Using T0 Hint with Intent to Write
, Vol.2-5-551
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF
1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed
Dword, Signed Qword Indices Using T1 Hint with Intent to Write
, Vol.2-5-553
W
Waiting instructions, x87 FPU, Vol.1-8-24
WAIT/FWAIT instructions, Vol.1-8-24, Vol.1-8-31, Vol.2-5-567,
Vol.3-6-27, Vol.3-22-7, Vol.3-22-14, Vol.3-22-15
GETSEC, Vol.1-6-4
WB (write back) memory type, Vol.3-8-16, Vol.3-11-7, Vol.3-11-8
INDEX
WB (write-back) pin (Pentium processor), Vol.3-11-13
WBINVD instruction, Vol.2-5-568, Vol.3-2-23, Vol.3-5-24, Vol.3-11-16,
Vol.3-11-17, Vol.3-22-4
WBINVD/INVD bit, Vol.2-3-192
WB/WT# pins, Vol.3-11-13
WC buffer (see Write combining (WC) buffer)
WC memory type, Vol.1-10-12
WC (write combining)
flag, IA32_MTRRCAP MSR, Vol.3-11-22
memory type, Vol.3-11-7, Vol.3-11-8
wide dynamic execution, Vol.1-2-4
Word, Vol.1-4-1
WP (write protected) memory type, Vol.3-11-7
WP (write protect) flag
CR0 control register, Vol.3-2-15, Vol.3-5-28, Vol.3-22-17
Wraparound mode (MMX instructions), Vol.1-9-4
Write
hit, Vol.3-11-5
Write combining (WC) buffer, Vol.3-11-4, Vol.3-11-7
Write-back and invalidate caches, Vol.2-5-568
Write-back caching, Vol.3-11-6
WRMSR instruction, Vol.2-5-572, Vol.3-2-19, Vol.3-2-20, Vol.3-2-25,
Vol.3-5-24, Vol.3-8-17, Vol.3-17-33, Vol.3-17-38,
Vol.3-17-41, Vol.3-18-88, Vol.3-18-118, Vol.3-18-119,
Vol.3-18-120, Vol.3-22-4, Vol.3-22-35, Vol.3-25-9
CPUID flag, Vol.2-3-209
WT (write through) memory type, Vol.3-11-7, Vol.3-11-8
WT# (write-through) pin (Pentium processor), Vol.3-11-13
X
x2APIC ID, Vol.3-10-40, Vol.3-10-41, Vol.3-10-44, Vol.3-10-46
x2APIC Mode, Vol.3-10-31, Vol.3-10-37, Vol.3-10-39, Vol.3-10-40,
Vol.3-10-41, Vol.3-10-44, Vol.3-10-45, Vol.3-10-46
x87 FPU
64-bit mode, Vol.1-8-1
checking for pending x87 FPU exceptions, Vol.2-5-567
compatibility mode, Vol.1-8-1
compatibility with IA-32 x87 FPUs and math coprocessors, Vol.3-22-6
configuring the x87 FPU environment, Vol.3-9-6
constants, Vol.2-3-355
control word, Vol.1-8-7
data pointer, Vol.1-8-9
data registers, Vol.1-8-1
device-not-available exception, Vol.3-6-27
effect of MMX instructions on pending x87 floating-point exceptions,
Vol.3-12-5
effects of MMX instructions on x87 FPU state, Vol.3-12-3
effects of MMX, x87 FPU, FXSAVE, and FXRSTOR instructions on x87
FPU tag word, Vol.3-12-3
error signals, Vol.3-22-10
execution environment, Vol.1-8-1
floating-point data types, Vol.1-8-13
floating-point format, Vol.1-4-11
fopcode compatibility mode, Vol.1-8-10
FXSAVE and FXRSTOR instructions, Vol.1-11-23
IEEE Standard 754, Vol.1-8-1
initialization, Vol.2-3-346, Vol.3-9-5
instruction opcodes, Vol.1-A-20
instruction pointer, Vol.1-8-9
instruction set, Vol.1-8-15
instruction synchronization, Vol.3-22-15
last instruction opcode, Vol.1-8-10
overview of registers, Vol.1-3-2
programming, Vol.1-8-1
QNaN floating-point indefinite, Vol.1-4-17
register stack, Vol.1-8-1
register stack, aliasing with MMX registers, Vol.3-12-2
register stack, parameter passing, Vol.1-8-3
registers, Vol.1-8-1
save and restore state instructions, Vol.1-5-12
saving registers, Vol.1-11-23
setting up for software emulation of x87 FPU functions, Vol.3-9-6
state, Vol.1-8-11
state, image, Vol.1-8-11, Vol.1-8-12
state, saving, Vol.1-8-11, Vol.1-8-12
status register, Vol.1-8-4
tag word, Vol.1-8-8
transcendental instruction accuracy, Vol.1-8-22
using TS flag to control saving of x87 FPU state, Vol.3-13-7
x87 floating-point error exception (#MF), Vol.3-6-43
x87 FPU control word
compatibility, IA-32 processors, Vol.3-22-8
description of, Vol.1-8-7
exception-flag mask bits, Vol.1-8-7
infinity control flag, Vol.1-8-8
loading, Vol.2-3-357, Vol.2-3-359
precision control (PC) field, Vol.1-8-7
RC field, Vol.2-3-348, Vol.2-3-355, Vol.2-3-387
restoring, Vol.2-3-374
rounding control (RC) field, Vol.1-4-18, Vol.1-8-8
saving, Vol.2-3-376, Vol.2-3-391
storing, Vol.2-3-389
x87 FPU data pointer, Vol.2-3-359, Vol.2-3-374, Vol.2-3-376,
Vol.2-3-391
x87 FPU exception handling
description of, Vol.1-8-32
floating-point exception summary, Vol.1-C-1
MS-DOS compatibility mode, Vol.1-8-33
native mode, Vol.1-8-32
x87 FPU floating-point error exception (#MF), Vol.3-6-43
x87 FPU floating-point exceptions
denormal operand exception, Vol.1-8-28
division-by-zero, Vol.1-8-29
exception conditions, Vol.1-8-26
exception summary, Vol.1-C-1
guidelines for writing exception handlers, Vol.1-D-1
inexact-result (precision), Vol.1-8-31
interaction of SIMD and x87 FPU floating-point exceptions,
Vol.1-11-18
invalid arithmetic operand, Vol.1-8-27
MS-DOS compatibility mode, Vol.1-D-1
numeric overflow, Vol.1-8-29
numeric underflow, Vol.1-8-30
software handling, Vol.1-8-32
stack overflow, Vol.1-8-4, Vol.1-8-27
stack underflow, Vol.1-8-4, Vol.1-8-27
summary of, Vol.1-8-25
synchronization, Vol.1-8-31
x87 FPU instruction pointer, Vol.2-3-359, Vol.2-3-374, Vol.2-3-376,
Vol.2-3-391
x87 FPU instructions
arithmetic vs. non-arithmetic instructions, Vol.1-8-25
basic arithmetic, Vol.1-8-18
comparison and classification, Vol.1-8-19
control, Vol.1-8-24
data transfer, Vol.1-8-16
exponential, Vol.1-8-22
instruction set, Vol.1-8-15
load constant, Vol.1-8-18
logarithmic, Vol.1-8-22
operands, Vol.1-8-15
overview, Vol.1-8-15
save and restore state, Vol.1-8-24
scale, Vol.1-8-22
transcendental, Vol.1-8-22
transitions between x87 FPU and MMX code, Vol.1-9-9
trigonometric, Vol.1-8-21
unsupported, Vol.1-8-25
x87 FPU last opcode, Vol.2-3-359, Vol.2-3-374, Vol.2-3-376,
Vol.2-3-391
x87 FPU status word
condition code flags, Vol.1-8-4, Vol.2-3-325, Vol.2-3-341,
Vol.2-3-401, Vol.2-3-403, Vol.2-3-406, Vol.3-22-7
Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Index -39
INDEX
DE flag, Vol.1-8-29
description of, Vol.1-8-4
exception flags, Vol.1-8-5
loading, Vol.2-3-359
OE flag, Vol.1-8-29
PE flag, Vol.1-8-4
restoring, Vol.2-3-374
saving, Vol.2-3-376, Vol.2-3-391, Vol.2-3-393
stack fault flag, Vol.1-8-6
TOP field, Vol.1-8-2, Vol.2-3-345
top of stack (TOP) pointer, Vol.1-8-4
x87 FPU flags affected by instructions, Vol.2-3-14
x87 FPU tag word, Vol.1-8-8, Vol.1-9-9, Vol.2-3-359, Vol.2-3-374,
Vol.2-3-376, Vol.2-3-391, Vol.3-22-8
XABORT - Transaction Abort, Vol.2-5-579
XADD instruction, Vol.1-7-4, Vol.2-3-537, Vol.2-5-581, Vol.3-8-3,
Vol.3-22-4
xAPIC, Vol.3-10-37, Vol.3-10-40
determining lowest priority processor, Vol.3-10-24
interrupt control register, Vol.3-10-21
introduction to, Vol.3-10-4
message passing protocol on system bus, Vol.3-10-32
new features, Vol.3-22-27
spurious vector, Vol.3-10-32
using system bus, Vol.3-10-4
xAPIC Mode, Vol.3-10-31, Vol.3-10-37, Vol.3-10-41, Vol.3-10-44,
Vol.3-10-46
XCHG instruction, Vol.1-7-4, Vol.2-3-537, Vol.2-5-586, Vol.3-8-3,
Vol.3-8-16
XCR0, Vol.1-14-15, Vol.2-5-622, Vol.2-5-623, Vol.3-2-18
XEND - Transaction End, Vol.2-5-588
XFEATURE_ENALBED_MASK, Vol.1-15-4
XGETBV, Vol.2-5-590, Vol.2-5-602, Vol.2-5-606, Vol.1-B-41, Vol.3-2-18,
Vol.3-2-21, Vol.3-2-22
XLAB instruction, Vol.2-5-592
XLAT instruction, Vol.2-5-592
XLAT/XLATB instruction, Vol.1-7-23
XMM registers
64-bit mode, Vol.1-3-5
description, Vol.1-10-3
FXSAVE and FXRSTOR instructions, Vol.1-11-23
overview of, Vol.1-3-2
parameters passing in, Vol.1-11-23
saving on a procedure or function call, Vol.1-11-23
XMM registers, saving, Vol.3-13-6
XOR instruction, Vol.1-7-10, Vol.2-3-537, Vol.2-5-594, Vol.3-8-3
XORPD- Bitwise Logical XOR of Packed Double Precision Floating-Point
Values, Vol.2-5-596
XORPD instruction, Vol.1-11-7
XORPS- Bitwise Logical XOR of Packed Single Precision Floating-Point
Values, Vol.2-5-599
XORPS instruction, Vol.1-10-9
XRSTOR, Vol.1-14-15, Vol.1-15-1, Vol.1-15-4, Vol.1-B-41
XSAVE, Vol.1-14-15, Vol.1-14-20, Vol.1-14-25, Vol.1-14-32,
Vol.1-14-33, Vol.1-15-1, Vol.1-15-4, Vol.1-15-8, Vol.2-5-590,
Vol.2-5-604, Vol.2-5-605, Vol.2-5-607, Vol.2-5-608,
Vol.2-5-610, Vol.2-5-611, Vol.2-5-612, Vol.2-5-613,
Vol.2-5-614, Vol.2-5-615, Vol.2-5-616, Vol.2-5-617,
Vol.2-5-618, Vol.2-5-619, Vol.2-5-620, Vol.2-5-621,
Vol.2-5-622, Vol.2-5-623, Vol.1-B-41, Vol.3-2-18, Vol.3-13-7,
Vol.3-13-8, Vol.3-13-9, Vol.3-13-10
XSETBV, Vol.2-5-616, Vol.2-5-622, Vol.1-B-41, Vol.3-2-18, Vol.3-2-19,
Vol.3-2-21, Vol.3-2-25
XTEST - Test If In Transactional Execution, Vol.2-5-624
Z
ZE (divide by zero exception) flag
x87 FPU status word, Vol.1-8-5, Vol.1-8-29
ZE (divide by zero exception) flag bit
MXCSR register, Vol.1-11-15
Zero, floating-point format, Vol.1-4-5, Vol.1-4-14
Index-40 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D
ZF flag, EFLAGS register, Vol.3-5-25
ZF (zero) flag, EFLAGS register, Vol.1-3-16, Vol.1-A-1, Vol.2-3-181,
Vol.2-3-515, Vol.2-3-542, Vol.2-3-544, Vol.2-4-550,
Vol.2-5-93
ZM (divide by zero exception) mask bit
MXCSR register, Vol.1-11-15
x87 FPU control word, Vol.1-8-7, Vol.1-8-29
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Encryption : Standard V4.4 (128-bit) User Access : Print, Copy, Extract, Print high-res Author : Intel Corporation Create Date : 2016:10:02 12:39:20Z Keywords : 64, ia 32 architecture, 325462 Modify Date : 2016:10:11 00:24:32+05:30 XMP Toolkit : Adobe XMP Core 5.6-c015 84.158975, 2016/02/13-02:40:29 Creator Tool : FrameMaker 10.0.2 Metadata Date : 2016:10:11 00:24:32+05:30 Producer : Acrobat Distiller 9.2.0 (Windows) Format : application/pdf Title : Intel® 64 and IA-32 Architectures Software Developer’s Manual, Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D Creator : Intel Corporation Subject : 64, ia 32 architecture, 325462 Document ID : uuid:c7cc4f3c-4b50-48c2-a728-8e51ae829847 Instance ID : uuid:bd881d6c-c8d2-4004-998d-f6eab0ffaf9b Page Mode : UseOutlines Page Count : 4670EXIF Metadata provided by EXIF.tools